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Linux support package (LSP) v2.3 for SPEAr

1. licati TONS User applications space I Sysfs interface Linux drivers __ U E B TITI Linux GPIO framework Kernel space Y PLO61 GPIO driver E L2 Hardware ARM PL061 GPIO The GPIO driver provides a standard interface to the Linux GPIO framework which interfaces to sysfs for user space applications and Linux drivers 208 245 Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Miscellaneous device drivers 9 1 3 Note 9 1 4 GPIO usage in user mode The following GPIO operations are allowed from user space request free set and get direction set and get value Setting a GPIO in interrupt mode is not possible from user space Request User space may ask the kernel to export control of a GPIO pin to user space by writing its number to this file sys class gpio export Example The following line creates a gpio19 node for GPIO 19 if it is not requested by kernel code echo 19 sys class gpio export This node can be used for further communication with the GPIO pin Free User space may ask the kernel to take back control of a GPIO pin from user space by writing its number to this file sys class gpio unexport Example The following line removes the gpio19 node exported using export file echo 19 sys class gpio unexport Set and get direction Once a GPIO pin is requested you can find the following files under sys class gpio gpiopi
2. i Network Device Drivers CAN Controller Hardware 4 9 3 Socket CAN framework in Linux The socket CAN framework is an implementation of CAN protocol controller area network which uses Berkeley socket API Socket CAN implements a new protocol family PF CAN which provides a socket interface to user space applications and builds upon the Linux network layer A device driver for CAN controller hardware registers itself with the Linux network layer as a network device so that CAN frames from the controller can be passed up to the network layer and on to the CAN protocol family module and vice versa Also the protocol family module provides an API for transport protocol modules to register so that any number of transport protocols can be loaded or unloaded dynamically Multiple sockets can be opened at the same time on the same or different protocol modules and they can listen send frames on the same or different CAN IDs Several sockets listening on the same interface for frames with the same CAN ID are all passed the same received matching CAN frames An application wishing to communicate using a specific transport protocol for example ISO TP has just to select this protocol when opening the socket and then it can read and write application data byte streams without having to deal with CAN IDs frames etc The basic CAN frame structure and the sockaddr structures are defined in include linux can h
3. name clock source rating 200 read clocksource read cycles mask OxFFFF 16 bits mult 0 to be computed Shift 20 flags CLOCK SOURCE IS CONTINUOUS s void hrt clocksource init void f Doc ID 16604 Rev 2 29 245 www BDTIC com ST Platform section UM0851 30 245 static struct spear timer gpt u32 tick rate gpt spear timer request specific 2 BUG ON gpt NULL Spear timer set source gpt SPEAR TIMER SRC SYS CLK initialize other fields ot clocksource structure load the counter start timer Spear timer set load start gpt 1 OxFFFF register the clocksource clocksource register amp clocksource gpt Clock event This entity is used by the kernel to program the next tick event Normally this happens every 10 msec CLOCK_EVT_MODE_PERIODIC In tickless and high resolution timers it can be used by the kernel to program the tick at the next suitable interval even if it is longer than than 10 msec For that it uses two callbacks set_mode and set_next_event static struct clock_event_device clockevent_gpt name Clock event features CLOCK EVT FEAT PERIODIC CLOCK EVT FEAT ONESHOT set mode clockevent set mode set next event clockevent next event shift e32 li static void clockevent set mode enum clock event mode mode struct clock event device clk event d
4. CAN Frame struct can_frame canid_t can_id 32 bit CAN_ID EFF RTR ERR flags us can dlc data length code 0 8 u8 data 8 attribute aligned 8 ky Doc ID 16604 Rev 2 107 245 www BDTIC com ST Communication device drivers UM0851 4 9 4 108 245 SockAddr struct sockaddr can sa family t can family int can ifindex union transport protocol class address info struct canid t rx id tx id tp reserved for future can addr hi The struct sockaddr can has an interface index like the PF PACKET socket which also binds to a specific interface SPEAr CAN driver The SPEAr CAN driver uses the socket CAN framework to provide a network driver as an interface for the user land applications The CAN driver exposes itself to the kernel as a platform driver through the struct spr can driver whose members are described below SPEAr CAN driver static struct platform driver spr can driver driver name DRV NAME m probe spr can drv probe remove spr can drv remove ifdef CONFIG PM suspend spr can drv suspend resume spr can drv resume endif CONFIG PM Je The CAN driver inserts a data structure for each newly detected interface into a global list of network devices Each interface is described by a struct net_device item which is defined in linux netdevice h This structure must be allocated dynamically The ker
5. u32 len length of requested data for single transaction it cannot be greater than 16 1024 bfr max channel configured for e g if a given timeslot is configured for 16 channel then length cannot be greater than 1024 bytes u32 actual len Reports bytes transfered to from the buffer Function call when request completes void complete struct spear ts ts struct spear tdm req int status Reports zero or negative error number struct list head list request list used by TDM driver LI Buffer read This API is used to read n bytes of data from the buffer memory spear ts timeslot structure Spear tdm req tdm request structure Spear tdm bfr read struct spear ts spear ts struct spear tdm req req TDM bufferization start This API starts bufferization for a single channel and enables the interrupt line If bufferization for more than one channel is required the API needs to be called again for each channel spear ts timeslot structure pcm synchro Indicate whether the channel used is narrowband wideband dir Direction for the bufferization IN OUT BOTH Note Not used in switching spear tdm bfr start struct spear ts ts u8 pcm synchro int dir TDM bufferization stop This API is used to stop TDM bufferization and disable interrupts It also frees any pending request spear ts timeslot structure Note Not used in switching spear tdm bfr stop struct spear ts
6. routine exported by usbd driver for gadgets to un register int usb gadget unregister driver struct usb gadget driver driver The composite device layer registers to the gadget framework by calling the above APIs and exposes an interface which can be used by different functions gadgets to represent a composite device Composite device interface The composite device is designed in such way that the driver should first register to the composite layer During registration it passes some of the device related details device string descriptor to the composite layer After that the composite device needs to add configuration multiple is also possible and then individual functions can add their interfaces The following figure shows a simple gadget driver zero gadget available with SPEAr LSP This gadget driver is build over a composite layer although it is not a composite device and is mainly used for testing the USB Device controller It provides two configurations in the first one a source sink function generating consuming USB packets and in the second one loop back feature We refer to this example gadget driver in the explanations given throughout this part of the document This driver can be found in inux arivers usb gadget zero c Figure 17 Zero gadget device Zero gadget device f Source Sink Config Loop back Config Function 1 Function 1 Interface O Interface 0 OUT Endpoint IN Endpoint OUT Endpoint IN En
7. 3 1 Platform section This section describes the basic SPEAr platform code and driver It consists of the following directories e arch arm plat spear e arch arm mach spear600 e arch arm mach spear300 The platform code has been split in this way so that common code across SPEAr platforms is kept in the plat spear directory and platform specific code is kept in the respective mach spear600 or mach spear300 directory for all SPEAr3xx The platform code is responsible for e Initializing VIC Initializing the timer clock source and clock event Initializing static memory mapping if required by the system Defining IO ADDRESS and related macros so that the static memory can be used Providing platform specific code for power management clock framework etc and initialization code for some specific controllers like fsmc and gpio Providing system specific header files like those describing irq lines and base addresses of respective devices Additionally there are 3 variants for SPEAr300 platform e SPEAr300 Basic SPEAr300 with IPs for telecom applications e SPEAr310 Basic SPEAr300 with IPs for communication applications e SPEAr320 Basic SPEAr300 with IPs for industrial applications Different architecture specific code for all the above variants SPEAr3xx are kept in mach spear300 as all of these are basically SPEAr300 machines Architecture specific code for SPEAr600 is kept in mach spear600 and has no variant Th
8. Setting the baud rate The cfsetospeed and cfsetispeed functions are provided to set the baud rate in the termios structure regardless of the underlying operating system interface These are user level functions which do not implement any system calls TCGETS and struct termios fill all the current termios parameters like baudrate etc ioctl fd TCGETS amp termios Doc ID 16604 Rev 2 101 245 www BDTIC com ST Communication device drivers UM0851 102 245 Set the baud rate to 115200 baud cfsetispeed amp termios B115200 Set the terminal output baud rate cfsetospeed amp termios B115200 Set the terminal input baud rate TCSETS and the struct termios sets all the current termios parameters ioctl fd TCSETS amp termios Getting the control signals The T OCMGET ioctl gets the current MODEM status bits which consist of all of the RS 232 signal lines except RXD and TXD listed in Table 33 Table 33 Control signal constants Constant Description TIOCM LE DSR data set ready line enable TIOCM DTR DTR data terminal ready TIOCM RTS RTS request to send TIOCM ST Secondary TXD transmit TIOCM SR Secondary RXD receive TIOCM CTS CTS clear to send TIOCM CAR DCD data carrier detect TIOCM CD Synonym for TIOCM CAR TIOCM RNG RNG ring TIOCM RI Synonym for TIOCM RNG TIOCM DSR DSR data set ready To get the status bits
9. TDM controller driver Hardware TDM controller TDM layer interface To use the TDM block you must call a sequence of the APIs provided for switching and bufferization Before using the APIs you need to understand the timeslot structure shown below which contains the parameters for bufferization and switching struct spear ts u8 endianess endianness of the device little big endian int ts index timeslot number for which bufferization switching takes place int bfr index represent channel number for bufferization It can be from 0 15 struct spear ts ts SW void iomem io base act mem tdm action mem base Address int bfr dir Direction for the bufferization IN OUT BOTH ul6 bfr_active field value 1 shows bufferization is start 0 means bufferization is stopped int status struct list_head rx_list List for received request struct list_head tx_list List for transmit request 1G Clock configuration This API is used for configuring the TDM clock The TDM clock structure must be passed as an input argument Spear tdm set clock struct spear tdm confclk clk struct spear tdm confclk u32 divisor used for the divided clock input The output of the divider stage is then the input frequency divided by 2 D 15 0 1 int bypass when bypass 1 the selected input clock is directly used as clock for master mode when bypass 0 the divi
10. Table 24 8 USBD performance results continued i BulkOUT BulkIN BlkSize Data Size eee ums throughput BulkIN time s throughput KB KB Mbps Mbps 160 16000 0 463621 282 7136821 0 588701 222 6461311 320 32000 0 914002 286 8090004 1 165675 224 8860103 400 40000 1 139009 287 6886838 1 454232 225 3285583 800 80000 2 340529 280 0050758 3 002247 218 2898342 1600 160000 4 680984 280 0095023 5 818188 225 2797606 3200 320000 9 356929 280 1602962 11 4153 229 6426524 Figure 18 USB Device performance at buffer length 4096 350 300 250 DF 200 EA Buk Out T 150 F ft Buk in E ner 100 50 0 IS Pr e e e gt PP OT gv a LP Ku KI eS Data Size in KB 4 4 6 Configuration options This section presents the general configuration options affecting the USB Device Kernel configurations You can select the Linux kernel configurations from make menuconfig Their purpose is mentioned in the table below Table 25 Linux kernel configuration Configuration option Comment CONFIG USB GADGET This enables USB gadget support in Linux kernel CONFIG USB ZERO This enables a test gadget driver zero ky Doc ID 16604 Rev 2 77 245 www BDTIC com ST Communication device drivers UM0851 Note 4 4 7 4 5 4 5 1 78 245 Table 25 Linux kernel configuration continued This enables SPEAr USB Device controller support CONFIG USB GADGET SPEAR SYN This enables USB test module f
11. U Boot FFFF0000h C BoM Linux OS High vectors eROM DDR Embedded in SPEAr Part of LSP XLoader XLoader is a small firmware loaded during the second stage of the boot phase by the BootROM The main steps performed by XLoader in LSP v2 3 are e Initializing the DDR and PLLs at 333 MHz e Passing of board information DDR size etc to U Boot e Loading the U Boot from NAND NOR depending on boot type selection and transferring the control to it The XLoader coming with the LSP v2 3 is licensed under GPLv2 and distributed in full source code This distributed XLoader version runs on the SPEAr hardware development kits You have to customize Xloader to run it on a different PCB especially the MPMC Doc ID 16604 Rev 2 13 245 www BDTIC com ST Boot loader overview UM0851 1 2 14 245 settings required for different DDR memory hardware and routing Please refer to one of the following application notes for more information on MPMC configuration e AN3100 Configuring the SPEAr3xx multi port memory controller MPMC for external DDR SDRAM e AN3132 Configuring the SPEAr600 multi port memory controller MPMC for external DDR SDRAM Building XLoader To build XLoader you need to use the STLinux toolchain and run the following commands Build XLoader for SPEAr600 target with DDR 333MHz for size 128MB make SOC SPR600 DDRFREQ 333 DDRSIZE 1
12. UM0851 Accelerator engine device drivers Figure 40 JPGC block diagram pa AHB Master DMAC A A Y Y AHB Slave CODEC CODEC ts Controller Core AHB Slave FIFO Do In 1AHB Slave alaga Internal memories AHB Slave AHB Bus The main features of the JPGC are e Compliance with the baseline JPEG standard ISO IEC 10918 1 e Single clock per pixel encoding decoding e Support for four channel interface Pixel In Compressed Out Compressed In Pixel Out e 8 bit channel pixel depths e Programmable quantization tables up to four e Programmable Huffman tables two AC and two DC e Programmable Minimum Coded Unit MCU e Configurable JPEG headers processing e Support for restart marker insertion e Chunk by chunk processing of data at source and destination side e Useoftwo DMA channels and two 8 x 32 bits FIFOs local to the JPGC for efficient transferring and buffering of encoded decoded data from to the codec core e Output decoded data is in the MCU format It is neither planar nor interleaved 6 1 2 Software overview The JPEG controller driver supports both JPEG encoding and decoding with without header processing enabled It acts as an interface between user level applications and the JPEG codec JPEG driver provides a char device interface to the user application and can be used from user level only JPEG driver accepts for encoding and gives for decoding data in MCU format The overall JPEG codec software system architecture is s
13. spear ts Bufferization channel free If the channel is not in use this API is called to free the unused channel spear ts timeslot structure Note Not used in switching Return channel number on success and negative value on error Spear tdm bfr put struct spear ts ts 204 245 Doc ID 16604 Rev 2 a www BDTIC com ST UM0851 Audio video drivers 8 2 4 Configuration options Table 52 Configuration options Configuration option Comment CONFIG S300 HEND IP PHONE MODE Enable TDM support in RAS CONFIG TDM Enable spear TDM support 8 2 5 References Refer to SPEAr300 user manual for more details 8 3 USB audio device class support SPEAr supports USB speakers and microphones through the USB Audio Device Class Please refer to the for more details ky Doc ID 16604 Rev 2 205 245 www BDTIC com ST Miscellaneous device drivers UM0851 9 9 1 206 245 Miscellaneous device drivers General purpose I O GPIO driver This section describes the the GPIO capabilities of the SPEAr embedded MPU family Hardware overview A General Purpose Input Output GPIO is a flexible software controlled digital signal Each GPIO represents a bit connected to a particular pin or ball on Ball Grid Array BGA packages Each input output can be controlled in two distinct modes e Software mode through an APB interface e Hardware mode through a hardware control interface The GPIO IP use
14. static struct spi board info spi board info __initdata modalias eeprom platform data amp m25 info controller data amp m25 hw max speed hz 21000000 21MHz mode SPI MODE 3 bus num SPEAR SSPO ID chip select 1 The name provided in modalias should be the same as the slave driver name The combination of bus_num and chip_select must be unique The device will be visible in the sysfs directory with the name spi bus num chip select The controller transmits data on the available frequency which must be less than or equal to Max_speed_hz Registering the driver The SPI slave driver must be registered with the SPI framework This is accomplished by calling spi_register_driver amp eeprom_driver where struct slave_driver is a structure which contains information about the SPI slave driver struct spi_driver int probe struct spi_device spi int remove struct spi_device spi void shutdown struct spi device spi int suspend struct spi device spi pm message t mesg int resume struct spi device spi struct device driverdriver You may not need to implement all these functions Like for the EEPROM driver only few fields are given struct spi driver eeprom driver driver name eeprom field must contain the same name which is used while adding the slave device in spi board info structure using modalias name owner THIS_M
15. www BDTIC com ST UM0851 Miscellaneous device drivers 9 3 5 References e SPEAr PWM Driver arch arm mach spear300 spr pwm st c ky Doc ID 16604 Rev 2 219 245 www BDTIC com ST Power management section UM0851 10 10 1 10 1 1 220 245 Power management section Power Management means that parts of your computer are shut off or put into a power conserving mode if they are not being used The techniques of clock frequency are also part of power management Hardware overview The hardware section has been divided into two subsections based on the power management techniques that have been used in the software Each subsection is based on the software architectures that have been followed in the design Power management techniques The System Control State Machine allows you to reduce power consumption by controlling the clock inputs to the CPU It has four states e SLEEP e DOZE reset state e SLOW e NORMAL All transitions between states are software controllable except for SLEEP to DOZE which is activated only by a hardware event Figure 64 System control state machine Consumption IRQ FIQ Dynamic Frequency Scaling Performances The system control state machine is used to select the input frequency applied to the system Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Power management section There are three main selections available e
16. 0x00780000 mask flags 0 hi static struct physmap flash data emi norflash data width 4 parts emi norflash partitions nr parts ARRAY SIZE emi norflash partitions YG static struct resource emi norflash resource start NOR FLASH PHYS end NOR FLASH PHYS SZ 16M 1 flags IORESOURCE MEM Jo static struct platform_device emi_norflash_device name physmap flash id O dev platform data amp emi_norflash_data p num resources da amp emi norflash resource resource hi These settings are based on two M28 W640HC chips as used in the SPEAr310 Evaluation board You have to modify these settings for different chips How to support a new NOR Flash In case of a new NOR Flash chip the following needs to be checked in the global configuration file of U Boot 1 Change CFG MAX FLASH SECT macro definition based on the number of blocks of NOR Flash 2 If you want to change the partition size the following macro definitions also need to be modified CONFIG BOOTCOMMAND CFG MONITOR LEN CFG MONITOR BASE CFG ENV SIZE In case of a new NOR Flash chip the following need to be checked in the resource file of Linux 142 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Non volatile memory device drivers 5 3 5 3 1 1 If you want to change the partition size the emi norflash partitions table should be modifie
17. 300 250 200 150 100 50 1 2 I 3 4 Jumper number SPEAr300 For SPEAr300 the following jumpers were replaced one at a time to measure the current source JP 1 for 1 2 V JP 2 for 3 3 V JP 3 for 2 5 V JP 4 for 1 8 V The current measurements indicate significant power savings The table and figures below present the results for SPEAr300 Table 65 SPEAr300 power consumption measurements Jumper settings Current in resumed Current in suspended Decrease in current state mA state mA consumption JP1 1 2V 198 5 43 78 33 JP2 3 3V 7 2 7 0 2 77 JP3 2 5V 25 8 25 8 0 JP4 1 8V 43 36 16 27 Doc ID 16604 Rev 2 239 245 www BDTIC com ST Power management section UM0851 10 5 10 5 1 10 5 2 240 245 Figure 70 SPEAr300 PM framework results O Current consumption in resume state E Current consumption in suspend state 200 150 100 Current consumed mA 50 Jumper number Configuration options Linux PM framework Table 66 Linux PM framework configuration options Configuration options Comment CONFIG_PM This option is used to enable the power management support This option enables various debugging support in the Power CONFIG_PM_DEBUG Management code This option enables verbose messages from the power management code CONFIG SUSPEND Allows the system to enter a
18. A good number of online documents related to USB can be found at e The official USB website e The USB FAQ e Compaq s OHCI standard e Intel s UHCI standard e Intel s EHCI standard USB host API Linux provides two host control drivers Linux EHCI amp Linux OHCI The architecture driver plugs into the USB host stack and allocates the basic resources for the USB host controller The host side drivers for USB devices talk to the usbcore APIs There are standard details of the API available The details of the USB Host APIs could be found online at the following address http www kernel org doc htmldocs usb html USB host usage A USB device can either use a custom driver or use one already present in the system This is based on the concept of a device class and means that if a device belongs to a certain class then the other devices of the same class can make use of the same device driver Some of these classes are the USB HID human interface devices class which covers input devices like keyboards and mice the USB Mass storage devices class which covers devices like pen drives digital cameras audio players etc and the USB CDC communication devices class which essentially covers USB modems and similar devices Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers USB mass storage class The USB mass storage standard provides an interface to a variety of storage devices like hard
19. CAN driver SP320 Communication device drivers HDLC driver SP310 Non volatile memory device NAND Flash driver All drivers Non volatile memory device EMI interface diver All drivers naa aa Serial NOR Flash driver All drivers Non volatile memory device USB mass storage support All drivers Non volate PAGAN vien 2C and SPI memory device support All drivers Non volatile memory device SD MMC memory support SP300 drivers Accelerator engine device JPEG driver All drivers Doc ID 16604 Rev 2 23 245 www BD TIC com ST Linux OS and device driver general information UM0851 Table 9 LSP v2 3 device drivers continued Section name Driver name SPEAr MPU aa ki General purpose DMA DMAC driver All rivers Human interface device HID YXonb csceas divar All drivers Human interface device HID Keypad driver SP300 drivers Human interface device HID ADC driver All drivers Human interface device HID peque LCD panel support All sapang AROG device FD USB HID Class Support All rivers Audio video drivers LCD controller CLCD driver SP600 SP300 Audio video drivers TDM driver SP300 Miscellaneous device drivers General purpose I O GPIO driver All Miscellaneous device drivers Watchdog WDT driver All Miscellaneous device drivers Pulse width modulator PWM driver SP320 24 245 Doc ID 16604 Rev 2 a www BD TIC com ST UM0851 Platform section 3
20. I create a little endian file system S page size e erase block size These commands create the image which does not contain OOB Hence for 512 byte page NAND Flash the image size must be divisible by 512 512 byte data NAND device driver performance The performance measurement has been performed using e Hardware ARM926EJS 333 MHz STMicroelectronics NAND 512W3A2CZA6 Flash e Test file system on the NAND Flash YAFFS2 and JFFS2 for dev mtdblock7 e Kernel Linux 2 6 27 e Driver DMA was disabled Results for YAFFS2 Mount YAFFS2 fs and write read to a file The sequence is as follows Doc ID 16604 Rev 2 135 245 www BDTIC com ST Non volatile memory device drivers UM0851 1 mount t yaffs2 dev mtdblock7 mnt 2 time dd if dev zero of mnt file bin bs 4K count 8192 Write the file 3 umount mnt 4 mount t yaffs2 dev mtdblock7 mnt 5 time dd if mnt file bin of dev null bs 4K count 8192 Read file back 6 umount mnt 7 mount t yaffs2 dev mtdblock7 mnt 8 rm mni file bin 9 umount mnt 10 Repeat for bs 8 16 32 64K and count 4096 2048 1024 512 Table 37 Results on SPEAr600 Block size in File size in Duration Mega l Duration Mega l Kbvtes MB seconds byte sec in seconds byte sec in y in write write in read read 1 4 32 49 5 21 9 0 64 1 46 2 8 32 49 7 21 9 0 64 1 46 3 16 32 49 6 21 9 0 64 1 46 4 32 32 49 3 21
21. It may be desired or necessary to keep a bad block table in Flash This is mandatory for those chips which have no factory marked bad blocks rather have factory marked good blocks The marker pattern is erased when the block is erased to be reused So in case of power loss before writing the pattern back to the chip this block would be lost and added to the bad blocks Therefore we scan the chips when we detect them the first time for good blocks and store this information in a bad block table before erasing any of the blocks The blocks in which the tables are stored are protected against accidental access by marking them bad in the memory bad block table The bad block table management functions are allowed to circumvent this protection The blocks in which the tables are stored are protected against accidental access by marking them bad in the memory bad block table The bad block table management functions are allowed to circumvent this protection The simplest way to activate the Flash based bad block table support is to set the option NAND USE FLASH BBT in the option field of the NAND chip structure before calling 130 245 Doc ID 16604 Rev 2 ki www BDTIC com ST UM0851 Non volatile memory device drivers nand scan This activates the default Flash based bad block table functionality of the NAND driver The default bad block table options are e Store bad block table per chip Use 2 bits per block Automatic placement
22. Multi functional printers USB Ethernet plus mass storage are such examples These devices are generally known as composite devices The USB Device controller driver in SPEAr LSP supports Linux USB gadget framework This framework provides a flexible and easy interface for adding different USB slave devices It also offers the facility to easily add multi function USB composite devices The following figure explains the USB gadget framework 70 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers Figure 16 USBD software architecture Ethernet usb0 File storage Kernel space USB gadget framework USBD driver USBD device controller Hardware As shomn in the figure above the gadget drivers can access the USB Device driver either directly through the gadget framework or through the composite layer The composite layer provides an interface where multi functional devices like audio and video can be easily supported It is preferable that USB gadget drivers who do not have composite features also interact through the composite layer Note Please note that only one gadget driver at a time can exist in this framework using gadget framework Also remember that composite layer is in itself a gadget drive Therefore according to the figure the printer and the composite layer cannot exist at the same time One possibility is to build the printer gadget over the composite layer T
23. N UM0851 Sf i User manual Linux support package LSP v2 3 for SPEAr May 2010 Introduction SPEAr is a family of highly customizable ARM based embedded MPUS suitable for use in many different kinds of application SPEAr Linux Support Package consists of a collection of all the Linux drivers that control the specific hardware controllers embedded in SPEAr as well as the set of bootloaders for performing the low level hardware configuration and loading of the Linux OS LSPv2 3 handles in a single source tree the following SPEAr devices SPEAr600 SPEAr300 SPEAr310 and SPEAr320 LSPv2 3 is integrated into the STLinux 2 3 distribution which is a full featured distro consisting of more than 500 RPM packages Please refer to http www stlinux com for more details Doc ID 16604 Rev 2 1 245 www st com www BDTIC com ST Contents UM0851 Contents 1 Boot loader overview llleeeeeeeeeee 13 1 1 XLoader ss 13 1 1 1 Building XLoader 0 cee mh 14 1 2 U BOOT x1 avs de i obe a ic e Je dic NAAN AA Paes 14 1 2 1 U Boot overview l llllelseeees s nn 15 1 2 2 Features EC 15 1 2 3 Building U Boot nee 15 1 2 4 U Boot commands 200 ees 16 1 2 5 Booting Linux with U Boot 0 0 00 eee 21 2 Linux OS and device driver general information 23 3 Platform section sscccdeiedveeetiewecacedsee de XE REOR RR ERO ees 25 3 1 General purpose
24. NOR device driver supports various serial NOR Flash chips All NOR devices are listed in arch arm plat spear include plat flash chars h lf a new NOR device is added in the system then its details must be entered here Here is a code snippet of flash chars c Flash Chip Device List Name Device ID code chip shift page shift page size sector size Total size in bytes static struct sflash dev sflash ids ST M25P16 SFLASH DEVID M25P16 21 0x8 0x100 0x10000 0x200000 Y f ST M25P32 SFLASH DEVID M25P32 22 0x8 0x100 0x10000 0x400000 Ye ST M25P64 SFLASH DEVID M25P64 23 0x8 0x100 0x10000 0x800000 Fa A ST M25P05 SFLASH_DEVID_M25P05 16 0x7 0x80 0x8000 0x10000 Doc ID 16604 Rev 2 145 245 www BDTIC com ST Non volatile memory device drivers UM0851 5 3 3 146 245 Serial NOR device driver overview MTD overview The MTD is common to both NAND and NOR Flash an overview is given in MTD overview NOR device driver interface to MTD The NOR device driver allocates and fills the structure struct mtd info so that the MTD layer obtains information about the hardware The code snippet shows some of the important data sent to MTD struct mtd info mtd mtd name SMI NOR Name for the NOR device mtd type MTD NORFLASH Type of MTD device mtd writesize 1 mtd flags MTD_CAP_NORFLASH IL Il sflash ids nor chip size in by
25. clk get rate Kernel clk put space v Middle level clock management Reference count arch arm plat spear clock c Dependency resolving d Low level clock management arch arm mach spearxxx spearxxx clock c Hardware Hardware clock generating unit The interaction with the kernel and the architecture specific code can be subdivided into three parts kernel middle level clock management layer and low level clock management layer see Figure 68 Kernel interaction Whenever the device drivers need some functionality that involves the interaction with the clock framework Linux provides the following APIs defined in the Linux Clock framework struct cl struct cl k clk get lookup and obtain a reference to a clock producer k clk enable inform the system when the clock source should be running struct clk cik disable inform the system when the clock source is no longer required struct clk cik put free the clock source struct clk cik get rate obtain the current clock rate in Hz for a clock source struct clk cik set rate set the clock rate for a clock source Doc ID 16604 Rev 2 229 245 www BDTIC com ST Power management section UM0851 Note 230 245 Middle level clock management layer The middle management clock layer acts as a transition between the lower layer which actuall
26. dmac modes interrupt option after each packet transfer src dest address increment after each access width sized transfer Please see linux spr dmac pl080 h for further information u32 cfg Platform specific value for the CFG register Configuration information include transfer flow controller and src dest request id physical request line between peripheral and DMAC Please see linux spr dmac p1080 h5 for further information enum dma master src master DMA masters for source and destination side Masters are fixed for the board architecture Master information is present in enum dma master info present in mach dma h enum dma master dest master void private data It is for client driver private data purposes It can be extracted from pointer to client structure in dma event callback Generic information about the slave See below struct dma slave struct device dev struct device dma dev dma addr t tx reg dma addr t rx reg enum dma slave widthreg width J This slave structure must be defined by the client driver before requesting DMA channels It must be filled with configuration values before preparing DMA transfer The default DMA driver ctl configuration for memory to memory transfers is DWC_CTL_USER_MODE DWC CTL NON BUFFERABLE DWC CTL NON CACHEABLE DWC CTL DEST BURST BURST 8 DWC CTL SRC BURST BURST 8 DWC CTL DEST WIDTH width DW
27. l l 240 Linux CPUfreq framework configuration options 0 00 e eee 241 List of acronyms used in the document 0 00 cee eee tee 243 Document revision history mh 244 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 ky SPEAr booting stageS 0 0 ett 13 GPT hardware interface 0 0 0 ccc eee 26 GPT software architecture 0 0 00 cece eae 27 VIC block diagram 1 0 0 cc tet mr 33 RTC functional block diagram eee 39 RTC software system architecture 0 0000 c eect eee 40 GMAC block diagram 1 2 20 uaaa 44 GMAC Ethernet software architecture ccc ae 45 Ethernet performance evaluation results Checksum offloading disabled 53 Ethernet performance evaluation results Checksum offloading enabled 53 MACB diagram ex oci m ye ru aba
28. name eeprom mode S IRWXUGO owner THIS MODULE Ts Size EEPROM SIZE read eeprom read Cleaning up When the I2C chip device is removed from the system by unloading either the I2C bus driver or the I2C chip driver the 12C core calls the detach client function specified in the struct i2c driver This is usually a simple function as it can be seen in the example driver s implementation static int eeprom detach client struct i2c client client f int err sysfs remove bin file amp client dev kobj amp xxx attr err i2c detach client client if err return err kfree i2c get clientdata client return 0 While the i2c attach client function is called to register the struct i2c_client with the I2C core the i2c detach client function is used to unregister it If that function succeeds the memory the driver has allocated for the I2C device needs to be freed before returning from the function This example driver does not specifically remove the sysfs files from the sysfs core This step is done automatically in the driver core within the i2c detach client function But if necessary you can remove the file manually using a call to device remove file I2C driver performance The driver performance was evaluated using the following setup e Target device SPEAr600 CPU 332 MHz AHB 166 MHz DDR 333 MHz M24C04 EEPROM size 512 Bytes block size 16 Bytes Doc ID 16604 Rev
29. 4 10 11 122 245 e IP over HDLC The Linux HDLC mid layer wraps HDLC to a network device It is possible to implement IP protocol over an HDLC interface You need two boards to make an IP based test Example On board A setslot hdlcO tx 0 127 setslot hdlcO rx 0 127 sethdlc hdic0 hdlc On board B setslot hdlcO tx 0 127 setslot hdlcO rx 0 127 sethdlc hdic0 hdlc Ping from board A ping 192 168 1 2 Configuration options ifconfig hdlc0 192 168 1 1 netmask 255 255 255 0 ifconfig hdlc0 192 168 1 2 netmask 255 255 255 0 Table 36 Menuconfig options Configuration option Comment SPEAR HDLC SPEAR HDLC support SPEAR TDM HDLC Enables TDM interface SPEAR TDM HDLC CHANNEL NUM Number of TDM sub channel SPEAR E1 DS21554 INIT Enables E1 interface SPEAR RS485 1 HDLC Enables RS485 1 interface SPEAR RS485 1 HDLC CTS ENABLE Enables collision detection for RS485 1 interface SPEAR RS485 2 HDLC Enables RS485 2 interface SPEAR RS485 2 HDLC CTS ENABLE Enables collision detection for RS485 2 interface SPEAr HDLC driver drivers net wan spr hdlc c and drivers net wan spr halc h HDLC Framework documentation Documentation networking generic hdlc txt hdlctest utility http www kernel org pub linux utils net hdlc hdlctest 1 0 tar gz sethdlc utility http www kernel org pub linux utils net hdlc sethdlc 1 18 tar gz References e HDLC framework in linux d
30. Be sure NOT to set delay more than one clock cycle e penalty Only for RS485 port set waiting time before re transmitting the frame when collision occurs Refer to the SPEAR310 User Manual for more details e tx faling edge Tx edge config True for transmit at falling clock edge false for transmit at rising clock edge e rx rising edge Rx edge config True for sample at rising clock edge false for sample at falling clock edge Logical channel parameters e common flag Enables common flag feature Refer to the SPEAR310 User Manual for more details e crc32 enable True for CRC32 false for CRC16 Default is CRC16 e flag enable Transmits flag when idle Refer to the SPEAR310 User Manual for more details e addr recog Address recognition mode Refer to the SPEAR310 User Manual for more details Parameters are defined in the global data array spear hdlc port Assigning timeslots for TDM E1 interface SPEAr HDLC driver uses two loctls to assign timeslots for the TDM E1 interface e SIOCDEVASSIGNSLOT Only for the TDM E1 port assign Tx Rx timeslot for logical HDLC channel e SIOCDEVREMOVESLOT Only for the TDM E1 port remove Tx Rx timeslot for logical HDLC channel Code sample struct ifreq req unsigned int data 2 Sock socket PF INET SOCK DGRAM IPPROTO IP Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers strcpy req ifr name hdlc0 data 0 TX data 1 TIMESLOTO r
31. NULL NULL rbuf 2 NULL NULL unsigned int wsize 4 4096 rsize 4 4096 unsigned int ssize XXX set size of input data here int rfd wfd cur rbuf 1 cur wbuf 1 pid t pid void jpegread int size 0 status while encoding decoding is not over do shuffle buf cur rbuf if status ioctl rfd JPEGIOC GET OUT DATA SIZE amp size 0 return 1 Add code here for manipulating decoded data present in rbuf cur rbuf while size rsize get jpeg info after encoding decoding is over ioctl rfd JPEGIOC GET INFO amp jpeg info unmap buf munmap char rbuf 0 2 rsize close rfd void jpegwrite a 160 245 Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Accelerator engine device drivers uint size 0 count 0 int wfd status open jpeg nodes wfd open dev jpegwrite O_RDWR O_SYNC if wfd 1 return 1 set src image size ioctl wfd JPEGIOC SET SRC IMG SIZE ssize set jpeg info for DWOH struct jpeg_dec_info dec_info ioctl wfd JPEGIOC SET DEC INFO dec info set jpeg info for EWH EWOH struct jpeg enc info enc info ioctl wfd JPEGIOC SET ENC INFO enc info wbuf 0 unsigned char mmap 0 2 wsize PROT READ PROT WRITE MAP SHARED wfd 0 wbuf 1 wbuf 0 wsize while count ssize size ssize count lt wsize ssize count wsize count
32. The IP is provided by Synopsis Hardware overview I2C is a multi master serial computer bus invented by Philips that is used to attach low speed peripherals to a motherboard embedded system or cell phone It is a master slave protocol where communication takes place between a host adapter or host controller and client devices or slaves Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers 4 5 2 I2C uses only two bidirectional lines serial data SDA and serial clock SCL pulled up with resistors Typical voltages used are 5 V or 43 3 V but systems with higher or lower voltages are permitted too The 12C controller serves as an interface between the APB bus and the serial I2C bus It provides master functions and controls all I2C bus specific sequencing protocol arbitration and timing Features supported by I2C are e Two wire I2C serial interface e Three speeds standard mode 100 Kb s fast mode 400 Kb s high speed mode 3 4 Mb s Master or slave I2C operation 7 or 10 bit addressing Slave bulk transfer mode Interrupt or polled mode operation Simple software interface consistent with design ware APB peripherals Digital filter for the received SDA and SCL lines Component parameters for configurable software driver support DMA handshaking interface compatible with the arm PLO80 DMA controller refer to Section 6 2 General purpose DMA DMAC driver Figure 19 12C
33. and include linux spi for Linux 2 6 27 e SPEAr SPI driver drivers spi spr_ssp_pl022 c and drivers spi spr ssp pl022 h e SPI master framework documentation Documentation spi folder Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers 4 7 4 7 1 SDIO driver An SDIO card is a combination of an SD card and an I O device This kind of combination is increasingly found in portable electronics devices SDIO cards define a standard protocol at several layers including mechanical electrical power signaling and software A large number of different SDIO devices can be now found in consumer applications like GPS receivers Wi Fi or Bluetooth adapters modems and Ethernet adapters Flash memories and other mass storage media such as hard drives SPEAr300 and SPEAr320 embed a SDIO controller described in this section Hardware overview SDIO stands for secure digital input output SD MMC is a memory card specifically designed to meet the security capacity performance and environment requirements inherent in newly emerging audio and video consumer electronic devices In addition to the SD memory card there is the SD I O SDIO card The SDIO card specification is defined in a separate specification named SDIO card specification that can be obtained from the SD Association The SDIO specification defines an SD card that may contain interfaces between various I O units and an SD hosts The SDIO ca
34. copy the data from the safe buffer back to the unsafe buffer and free up the safe buffer Packet reception Receiving data from the network is trickier than transmitting it because a struct sk buff must be allocated and handed off to the upper layers within an atomic context The mode of packet reception that has been implemented is interrupt driven There is a common interrupt registered for both reception and transmission When the packet is received a tasklet is scheduled for handing the packet to the upper stacks as the packet has been fetched by DMA into the memory buffers The scheduled tasklet executes not later than the next timer tick This scheduling allows to handle more packets in a more efficient way One important thing to note over here is that since the packet handling to the stack is done through tasklet it keeps the DMA descriptor occupied till the packet is handed over to the stack In case of heavy Ethernet traffic at high speeds the number of DMA descriptors Doc ID 16604 Rev 2 49 245 www BDTIC com ST Communication device drivers UM0851 4 1 5 Note 50 245 configured should be sufficient to handle the excess traffic otherwise there is a possibility of retransmissions or packet losses Packet transmission Whenever the kernel needs to transmit a data packet it calls the driver s hard start xmit method to put the data on an outgoing queue The socket buffer passed to hard start xmit contai
35. dev device directory Major number 4 is associated to the ttyS driver For the UART layer major number is 4 and the minor number ranges between 64 255 DMA support is not present in the driver TTY framework in Linux The TTY driver serves as an intermediary device between hardware device drivers and user applications to provide line buffering of input and management of input and output The driver is purely software oriented and makes no direct communication with physical hardware Instead the TTY driver relies on an underlying device driver to communicate directly with the hardware It has the following system calls Open Open associates a TTY with an underlying char oriented hardware device The device should already be opened and initialized before the TTY is opened When the port is opened for the first time you can do the necessary hardware initialization and memory allocation Since a serial port is a file the open function is used to access it e Open returns a file descriptor which is just an int e Open returns 1 if any error occurs To open a serial port include lt fcntl h gt Ant fd The name argument is the filename dev ttys0 in case of SPEAr300 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers dev ttys0 or dev ttys1 in case of SPEAr 600 The flags argument is an int that specifies how the file is to be opened the main values are O
36. fd return 0 The other functions of the I O ports like the modem control operations can also be controlled by adding some modem control functions to this application Some important TTY commands e Getty getty opens a TTY port prompts for a login name and invokes the bin login command The getty command sets and manages terminals by setting up the speed the terminal flags and the line discipline Example sbin getty 9600 ttyS1 e Stty stty is used to change and print the terminal line settings List the attribute settings for a terminal that has a user logged on it already stty a F dev ttys0 Disable modem control signals stty clocal F dev ttys0 Enable RTS CTS handshaking stty crtscts F dev ttys0 Set the baud rate of current terminal to 9600 baud stty baud 9600 Configuration options Table 34 UART menuconfig kernel options Configuration option Comment CONFIG_SERIAL_CORE This option enables UART tty framework CONFIG_SERIAL_CORE_CONSOLE This option enables UART console framework This option enables SPEAr UART driver support CONFIG_SPEAR_SERIAL_PLO11 for TTY framework This option enables SPEAr UART driver support CONFIG_SPEAR_SERIAL_PL0O11_CONSOLE for console framework a Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Communication device drivers 4 9 4 9 1 Note Note CAN driver CAN is a message based protocol d
37. type So attach is left empty O control channel iocti is used to configure the HDLC channel Most IOCTLs are handled in the Linux network layer and the generic HDLC layer This function just calls hdlc ioctl to hand over these IOCTL requests Besides standard IOCTLs the driver defines some private IOCTLs which change the hardware behavior int channel_ioctl struct net_device dev struct ifreq ifr int cmd switch cmd case SIOCDEVPRIVATE default return hdlc_ioctl dev ifr cmd Driver parameters TDM E1 HDLC and RS485 HDLC share the same driver code The differences between them are specified in different driver parameters There are two kinds of driver parameters one is for a physical port another is for logical channels multiple logical channels may share the same physical port Doc ID 16604 Rev 2 117 245 www BDTIC com ST Communication device drivers UM0851 4 10 5 118 245 Physical port parameters e has tsa True for TDM E1 port false for RS485 port e tsO delay Only for TDM E1 port delay between SYNC signal and beginning of TSO e cts enable Only for RS485 port enable collision detection or not Initial value is set by kernel configuration e cts delay Only for RS485 port set delay when controller start to sample the CTS signal This parameter tells the controller when to sample the CTS signal after transmitting one bit The delay can be calculated by cts delay 2 freq ahb
38. when creating partitions Dynamic parititions are defined in the command line arguments by using this command setenv bootargs console ttyS0 root dev mtdblock3 rootfstype jffs2 mtdparts SMI NORO 4k XLoader 200k uBoot 2M Linux 5M Ramdisk The command line argument creates 4 partitions XLoader Uboot Linux and Ramdisk in the NOR Flash Sizes are also given in the partitions How to support a new NOR Flash In case of a new NOR Flash chip the following needs to be checked in the device driver 1 NOR chip should be listed in arch arm plat spear include plat flash_chars h 2 NOR chip base address should be defined in platform device of arch arm mach spear600 spear600 c or arch arm mach spear300 spear300 c static struct resource nand_resources x Start SPEAR START SFLASH MEM end SPEAR START SFLASH MEM SPEAR SIZE SFLASH MEM 1 flags IORESOURCE MEM 3 NOR chip should be supported by SMI families supported by SMI are listed in SPEAr user manuals NOR Flash file system image creation JFFS2 image creation To create the JFFS2 file system image for NOR Flash use the command 4 mkfs jffs2 n p 1 s 0x200 e 0x10000 r dir name gt o image name gt n don t add a cleanmarker to every eraseblock p add pad bytes to the end of the final erase block I create a little endian filesystem S page size e erase block size Serial NOR device usage The us
39. 0x0 PT CT RESCALER2 0x1 RESCALER4 0x2 RESCALER8 0x3 RESCALER16 0x4 RESCALER32 0x5 RESCALER64 0x6 RESCALER128 0x7 PT CTRL PRESCALER256 0x8 PT CT PT CT PT CT PT CT PT CT PT CT Di 2M a Sk SRM SG SEE oQoooooQoQdnqn aaa oo a un Spear timer set prescaler struct spear timer int prescaler GPT interrupt management Each timer channel of a hardware block of GPT has separate independent interrupt lines You can use the following API to know which interrupt line is associated with the timer Then using Linux calls you can attach an interrupt handler to these irq lines You can use separate APIs to enable and clear the interrupts for a timer This shall return the irq associated with timer int spear timer get irq struct spear timer timer Enable Disable the timer match interrupt void spear timer set match struct spear timer timer int enable a Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Platform section Clear the match interrupt status value must be GPT STATUS MATCH void spear timer write status struct spear timer timer ul6 value GPT operation The following APIs can be used to start stop the GPT timer in single shot or auto reload mode This shall load the timer with load count value and start the timer void spear timer set load start struct spear timer timer int autoreload u16 load These APIs separately load start
40. 1 Hardware overview 2 215 9 3 2 Software overview sse 217 9 3 3 PWM usage in Linux seller I 217 9 3 4 Configuration options 0 00 ee 218 9 3 5 References 0 0 nnn 219 10 Power management section eee eee eee 220 ky Doc ID 16604 Rev 2 7 245 www BDTIC com ST Contents UM0851 10 1 Hardware overview cessas acewxdvee shee sede eee RR Roy pl 220 10 1 1 Power management techniques a 220 10 2 Software overview re 222 10 2 1 Linux power management PM framework 200 000 223 10 2 2 Linux clock framework 000 223 10 2 3 CPU frequency framework elles 225 10 3 Power management API eese 227 10 33 PM framework API en 227 10 3 2 Clock framework API 0 es 228 10 3 8 CPU freq framework API eh 231 10 4 Usage and performance 002 ee 233 10 4 4 Usage Linux PM framework een 233 10 4 Usage clock framework ee 233 10 4 8 Usage CPUfreq user interface 0 ccc eee 235 10 4 4 Performance nn 238 10 5 Configuration options ues sec ve peice EE REX RETRO ERR HA KE 240 10 5 4 Linux PM framework ssssee een 240 10 5 2 Linux clock framework 00 00 cee tee 240 10 5 8 Linux CPU freq framework lisse 241 11 Flashing utility section 25 66 a na vee eee eee sew ee KAREN E x Rn 242 Appendix A AcronymS a AA
41. 2 ky www BDTIC com ST UM0851 Communication device drivers Note 4 5 6 e Test method Build kernel with i2c support as module After booting the SPEAr board insert i2c module with different clock speeds 100 400 KHz insmod spr i2c syn ko clock 100 insmod spr i2c syn ko clock 400 Perform the measurement in this way time dd if dev zero of dev i2c 0 bs 16 count 1 time dd if dev i2c 0 of dev null bs 16 count 1 As per I2C slave device limitation the EEPROM bs must be maximum 16 e Test results Table 26 12C at clock speed 100 Sizein Write Throughput Size in Read Throughput Bytes time in sec kbps Bytes time in sec kbps 16 0 01 12 8 16 0 01 12 8 16 0 01 12 8 64 0 01 51 2 16 0 01 12 8 128 0 02 51 2 16 0 01 12 8 196 0 03 52 26666667 16 0 01 12 8 255 0 03 68 Table 27 12C at clock speed 400 Sizein Write Throughput Size in Read Throughput Bytes time in sec kbps Bytes time in sec kbps 16 0 005 25 6 16 0 005 25 6 16 0 005 25 6 64 0 01 51 2 16 0 005 25 6 128 0 01 102 4 16 0 005 25 6 196 0 01 156 8 16 0 005 25 6 255 0 02 102 Known issues or limitations current driver 10 bit addressing is not supported Data transfer is supported only in interrupt mode DMA mode is not supported by the Doc ID 16604 Rev 2 85 245 www BDTIC com ST Communication device drivers UM0851 4 5 7 4 5 8 4 6 4 6 1
42. 832550681 Figure 35 NAND memory performance jffs2 type 25 2 15 Write to NAND memo ry Mi jffz2 type EF 4 Read from NAND memory 8 jffs2 type a 0 5 0 0 20 40 60 80 Block Size in KB Doc ID 16604 Rev 2 137 245 www BDTIC com ST Non volatile memory device drivers UM0851 5 1 7 Note 138 245 Configuration options Table 39 NAND Flash driver configuration options Configuration option Comment This option is used to enable the NAND Driver CONFIG_MTD_NAND_SPEAR support for SPEAr platform This option provides the generic support for MTD CONFIG_MTD drivers This option enables multiple partitions each of CONFIG MTD PARTITIONS which appears to the user as a separate MTD device This option provides a character device for each CONFIG MTD CHAR MTD device This option provides a block device for each MTD CONFIG MTD BLOCK device This option enables support for accessing all type FROM TDUNAMD of NAND Flash devices CONFIG JFFS2 FS This option includes the JFFS2 file system CONFIG JFFS2 CMODE NONE This option disables the compression for JFFS2 CONFIG YAFFS FS This option includes the YAFFS file system This option ensures that all data transfer to NAND CONFIG SPEAR DMAC PL080 Flash will use DMA References e http www linux mtd infradead org tech mtdnand inde
43. ADC converts the analog voltage present on the analog input pin AIN The A D conversion is done as configured by the ADC driver The converted voltage then is returned as a digital value to the ADC driver The ADC software system architecture is shown in the following figure Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Human interface device HID drivers Figure 50 ADC driver architecture User space User application Linux char device framework Linux drivers Kernel space l ii ADC driver Hardware ADC ST10 IP 7 3 3 ADC usage in Linux ADC can be accessed from two levels in Linux User level User level applications must include include linux spr_adc_st10_usr h file to access data types related to ADC In order to use the ADC at user level you need to create nodes for the ADC The major number is allocated dynamically to the ADC driver To obtain the major number of the ADC run the following command after startup cat proc devices Character devices 1 mem pty ttyp dev vc 0 tty ttys dev tty dev console dev ptmx ves st misc YNuUUNOP RP BP WD RR Wow input fb 12c mtd 128 ptm 136 pts 180 usb 189 usb device 206 osst 250 usb endpoint 251 C3 252 spear adc 254 rtc Oo ON O to lo Doc ID 16604 Rev 2 185 245 www BDTIC com ST Human interface device HID drivers UM0851 186 245 Block devices 1
44. CAN driver For designing a typical user land application that uses the CAN driver the following steps should be followed To open a socket for communicating over a CAN network 1 PassPF CAN as the first argument to the socket system call Currently there are two CAN protocols to choose from the raw socket protocol RAW and the broadcast manager BCM Open a RAW socket S socket PF CAN SOCK RAW CAN RAW Open a BCM socket S socket PF CAN SOCK DGRAM CAN BCM 2 Now bind the socket to a CAN interface using the bind system call An example of binding a raw socket to the CAN interface can0 is given below int s struct sockaddr can addr struct ifreq ifr S socket PF CAN SOCK RAW CAN RAW strcpy ifr ifr name can0 ioctl s SIOCGIFINDEX amp ifr addr can family AF CAN addr can ifindex ifr ifr ifindex bind s struct sockaddr amp addr sizeof addr 3 After binding CAN RAW or connecting CAN BCM the socket you can read and write from to the socket using read and write APIs respectively Read nbytes from a CAN socket nbytes read s amp frame sizeof struct can frame Write nbytes to a CAN socket nbytes write s amp frame sizeof struct can frame You can also use other standard APIs like sena sendto sendmsg and recv to perform the desired operations on the socket Doc ID 16604 Rev 2 109 245 www BDTIC com ST Communication
45. Data structure of framebuffer e The struct fb info defines the current state of the video card struct fb info is only visible from the kernel Inside struct fb info there is a struct fb ops which is a collection of the functions needed to make the driver work struct fb info is the central data structure of framebuffer drivers This structure is defined in include linux fb h as follows struct fb info TP cao 7 struct fb var screeninfo var Variable screen information struct fb fix screeninfo fix Fixed screen information PE xx struct fb cmap cmap Color map JE sax cy struct fb ops fbops Driver operations 4 wee FL char __iomem screen_base Frame buffer s virtual address unsigned long screen_size Frame buffer s size x x From here on everything is device dependent void par Private area Memory for struct fb info is allocated by framebuffer_alloc a library routine provided by the framebuffer core This function also takes the size of a private area as an argument and appends it to the end of the allocated struct fb info This private area can be referenced using the par pointer in the struct fb info e The user application program can use the ioctl system call to perform low level operations on theLCD hardware Methods defined in struct fb ops are used to support these operations The struct fb ops structure contains the addresses of all entry points provided by th
46. Doc ID 16604 Rev 2 27 245 www BDTIC com ST Platform section UM0851 Note 28 245 1 Setting the source clock There are two possible clock sources for each timer block One source can be directly from PLL3 constant 48 MHz and the other can be from PLL1 through synthesizer Either of these source clocks can be selected by the following API The selection of the source clock applies to the whole timer hardware block thus affecting both channels When the PLL1 system clock is selected as the timer clock any change in the system clock for power saving etc has an impact on the frequency of the GPT In such cases you must always get the current clock rate for programming next GPT interrupt Please refer to clock framework chapter for information on clock framework usage The use of 48 MHz PLL3 is discouraged as it leads to unpredictable results in reading counter value Please refer to the GPT application note for details set the appropriate clock src source can be SPEAR TIMER SRC SYS CLK from PLL1 SPEAR TIMER SRC PLL3 CLK from PLL3 void spear timer set source struct spear timer timer int source Programming the prescaler After configuring the appropriate clock source you can program the prescaler The prescaler can be different for each timer channel within a hardware block and can range from 1 to 256 in 8 levels set the appropriate prescaler prescaler can be PT CTRL PRESCALER1
47. HBASE MEM SIZE Huff base memory char hsymb mem HSYMB MEM SIZE Huff symb memory lg On success zero is returned otherwise on error 1 is returned and errno is set appropriately If this ioctl is not called before writing reading data to from JPEG then DWH decoding with header processing is performed by default Mapping memory for read and write The JPEG driver needs to allocate buffers for storing the input and output data To speed up the encoding decoding process the driver uses the mmap Linux system call This system call allocates physically contiguous memory for JPEG driver and returns the virtual address of this memory to the user application Now user can then read and write to these virtual addresses and the same data is reflected in the driver buffers This saves unnecessary data copy time between kernel and user level In order to further increase the performance of the encoding decoding process two buffers are used both for read and write operations By having two buffers for read and write we are actually parallelizing JPEG processing By the time JPEG hardware reads writes data from to read write buffer software has written read data to from other buffer Use the following system call to map physical memory in virtual space void mmap void start size t length int prot int flags int fd off t offset fd file descriptor of jpeg read jpeg write node length is total size of buffers write or r
48. ID 16604 processing it should unmap the memory that s Use the following system call to unmap Rev 2 159 245 www BDTIC com ST Accelerator engine device drivers UM0851 munmap adrs size adrs is address of mapped memory size is size of mapped memory On success zero is returned otherwise 1 is returned on error and errno is set appropriately Close After unmapping memory you must close JPEG nodes Use the following system call to do this close fd Close returns zero on success or 1 if error occurred errno is set appropriately This function must be called both for read and write nodes JPEG codec usage JPEG read and write are not synchronized enough for example one chunk of input data may produce output data varying in size Due to this you need to write and read simultaneously to JPEG driver otherwise JPEG codec may be wasting time sitting idle It is recommended to use two processes or threads to read and write data simultaneously from the JPEG driver This will increase speed of JPEG processing The following example is for encoding decoding a JPEG image Here input data is read by application from a file and is passed to JPEG driver After that it is processed by JPEG codec based no processing type encoding decoding and output data is read by application again include lt sys mman h gt include include linux spr jpeg syn usr h struct jpeg info jpeg info volatile unsigned char wbuf 2
49. MAIN oscillator directly 30 MHz or its ratio 1 2 1 4 1 16 or 1 32 e RTC oscillator if present its frequency is 32 768 kHz e PLL1 Frequency generated from MAIN Oscillator A detailed description is given in the system controller section of the SPEAr datasheet Table 59 Power states for synchronous DRAM systems State ARM ARM clock DRAM POERI COME execution memory SLEEP Hibernate Off Self Refresh None 32 876 kHz DOZE WFI R If Refresh Int SRAM O Run 30 MHz PLL Off Self Refres nternal S Memory SLOW WFI Run 30 MHz PLL Off Self Refresh Internal SRAM Memory Internal SRAM Memory NORMAL WFI Run Upto 333 MHz PLLOn Active amp external DRAM Table 60 Power states for asynchronous DRAM Systems State ARM ARM clock DRAM pose bie code execution memory SLEEP Hibernate Off Eo seien pi Active None 32 876 kHz Self Refresh Internal Memory 2 876 kH i DOZE Running 32 876 kHz Active Internal Mem 4 DRAM 30 MHz PLL Off Self Refresh Internal Memory 30 MHz PLL Off Active Internal Mem amp DRAM Self Refresh Internal Memory SLOW WFI R MHz PLL Off 9 fn Sable on Active Internal Mem amp SRAM Up to 333 MHz PLL Internal SRAM Memory NORMAL WFI Run On Active amp external DRAM e Dynamic frequency scaling DFS This technique is applicable in NORMAL state It uses dynamic selection of the optimal frequency to allow a task to be performed in the required amount of t
50. MANUFACTURER IDX id id device desc iManufacturer id static int sourcesink_bind struct usb_configuration c struct usb_function f f allocate interface ID s id usb interface id c f if id 0 return id source sink intf bInterfaceNumber id Data and control transfer After completing the registering process the gadget driver can handle setup requests through setup callbacks In this way you can configure other required endpoints and initiate a transfer of control or data through Linux gadget framework APIs You can obtain more details on these APIs through references The following table summarizes these APIs and their purpose Table 22 Linux gadget endpoint APIs API Description struct usb ep usb ep autoconfig struct Allocates a suitable free endpoint described by usb gadget struct usb endpoint descriptor struct usb endpoint descriptor Enables the endpoint ep in order to be used for data transfer The endpoint ep is described in struct usb endpoint descriptor intusb ep enable struct usb ep ep const struct usb endpoint descriptor desc struct usb request usb ep alloc request struct usb ep ep gin t gio flags Allocates a request for USB transfer a Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Communication device drivers Table 22 Linux gadget endpoint APIs continued void usb ep free request struct usb ep ep struct usb request re
51. Sleep state Suspend to RAM Standby CONFIG PM VERBOSE Linux clock framework The Clock framework is implicitly present in the Linux kernel and does not require any configuration option except for the System Type Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Power management section 10 5 3 Linux CPU freq framework Table 67 Linux CPUfreq framework configuration options Configuration options Comment This option is used to enable the CPU frequency CONFIG CPU FREQ scaling option This option sets which CPUfreq governor is loaded Detant CPU Freq evemer Choice at startup The default is Performance This CPUfreq governor sets the frequency CONFIG CPU_FREQ_GOV_PERFORMANCE statically to the highest available CPU frequency This CPU freq governor sets the frequency CONFIG_CPU_FREQ_GOV_POWERSAVE statically to the lowest available CPU frequency Enable this CPUfreq governor when you either want to set the CPU frequency manually or when an user space program must be able to set the CPU dynamically CONFIG_CPU_FREQ_GOV_USERSPACE This driver adds a dynamic CPUfreq policy governor The governor does a periodic polling and changes frequency based on the CPU utilization CONFIG_CPU_FREQ_GOV_ONDEMAND This driver is rather similar to the on demand governor both in its source code and its purpose the difference is its optimization for better suitability in a
52. The general HDLC layer for Linux is an interface between low level hardware drivers for synchronous serial HDLC cards and the rest of kernel networking It exposes the HDLC interface as a network device With this design it is very easy to use and test the HDLC interface Lyr Doc ID 16604 Rev 2 113 245 www BDTIC com ST Communication device drivers UM0851 Figure 29 HDLC software system architecture User space Application Socket API Netif I F Kernel space Generic HDLC layer SPEAr HDLC driver Hardware HDLC controller SPEAr HDLC driver talks to the HDLC controller hardware It carries out transmit requests coming from the upper layers In parallel it collects incoming data from hardware and queues them up to the upper layers The generic HDLC layer is between the HDLC driver and Linux network layer It implements several protocols based on HDLC such as Raw HDLC PPP Frame Relay etc It works as a translator or a multiplexer between the physical HDLC driver and Linux network layer The application uses the standard BSD socket API to access the HDLC interfaces Main data structures of the driver The main driver structures include port t channel t hdlc dev net device The relationship between these structures is shown in the following figure 114 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers Figure 30 Data structure layers Network Generic HDLC
53. battery powered environment CONFIG CPU FREQ GOV CONSERVATIVE This driver exports CPU frequency statistics CONFIG CPU FREQ STAT information through sysfs file system Presently not supported in the driver ky Doc ID 16604 Rev 2 241 245 www BDTIC com ST Flashing utility section UM0851 11 Flashing utility section The flashing utility is a PC Host application which connects to a SPEAr target through USB and is capable of uploading files over a TTY over USB communication protocol It is based on a few building blocks such as a board dependent DDR driver used to configure the target memory system and on u boot used for the NAND NOR flashing which is the purpose of this utility Please refer to the flashing utility help available with the flashing package for details on how to use it 242 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Acronyms Appendix A Acronyms Table 68 List of acronyms used in the document Acronym Definition ADC Analog to digital converter ARM Advanced RISC machine BSP Board support package CETK Windows CE test kit FAT File allocation table FTL Flash translation layer HID Human interface device JFFS2 Journaling Flash file system version 2 MTD Memory technology device SPI Serial peripheral interface TDM Time division multiplexing USB Universal serial bus YAFFS Yet another flash file system Lyr Doc ID 16604 Re
54. be 0 2 4 8 or 16 It will return on success and negative value on error Spear tdm bfr max chan u32 max chan Frame size configuration This API configures the number of samples that must be compiled in buffering mode before switching the banks and interrupting the processor frame size specifies number of samples It will return zero on success and negative value on error spear tdm bfr frame size u32 frame size Getting timeslot information This API is used to get timeslot information It returns a pointer to the timeslot structure containing the necessary information for switching bufferization This information is needed to start bufferization or switching It contains the information about endianess of the device timeslot number for which the bufferization or switching takes place It also contains the information about the channel number for bufferization More details on the timeslot structure are given at the beginning of Section 8 2 3 TDM layer interface Index represent the timeslot number for which switching bufferization takes place Return timeslot structure on success and zero if the index is greater than the maximum timeslot value Spear tdm ts get int index Get bufferization channel This API gives the unused channel number for bufferization If the channel is not available it will return an error Return channel number on success and negative value on error Note Not used in switch
55. buf size t len Reading data To read data over the SPI bus you can use the spi read function provided by the SPI framework Spi device from which data will be read buf data buffer len data buffer size static inline int spi read struct spi device spi u8 buf size t len Writing reading data full duplex mode Writing and reading simultaneously can be achieved the with following code static inline int spi write and read struct spi device spi const u8 txbuf u8 rxbuf size t len f create SPI transfer structure and fill all relevant fields struct spi transfer Gom tx buf txbuf rx buf rxbuf len len hi create and initialize spi message structure struct spi messagem Spi message init amp m adding the transfer structure to the tail of the spi message Spi message add tail amp t amp m spi sync function will submit the current message with the spi and will Doc ID 16604 Rev 2 91 245 www BDTIC com ST Communication device drivers UM0851 4 6 4 4 6 5 4 6 6 4 6 7 4 6 8 92 245 return after completion of transfer return spi sync spi amp m Un registering the driver On module exit the SPI slave driver must be un registered with the SPI framework This is accomplished by calling spi_unregister_driver amp eeprom_driver Known issues or limitations There are some known issues with the current controller driver and current slave dr
56. call ioct with a pointer to an integer to hold the bits Getting the MODEM status bits int fd int status ioctl fd TIOCMGET amp status Setting the control signals The TIOCMSET ioctl sets the modem status bits defined above To drop the DTR signal you can use the code listed below Ant fd int status ioctl fd TIOCMGET amp status status amp TIOCM DTR ioctl fd TIOCMSET amp status The bits that can be set depend on the operating system driver and modes in use Writing data to a port When data is to be sent to the hardware the write function is called This function returns the number of characters that are actually written to the device Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers Writing data to the port is easy just use the write system call to send data The write function returns the number of bytes sent or 1 if an error occurred fd file descriptor buf character array n number of bytes to be transferred write int fd char buf int n Reading data from a port is a little trickier When you operate the port in raw data mode each read system call returns the number of characters that are actually available in the serial input buffers If no characters are available the call blocks waits until characters come in an interval timer expires or an error occurs Reading data from the port fd file descriptor buf
57. called whenever a new I2C bus driver is loaded in the system This function is described in more detail below int attach adapter struct i2c adapter called when the i2c client device is to be removed from the system int detach client struct i2c client static struct i2c driver eeprom driver driver name eeprom id I2C DRIVERID eeprom attach adapter eeprom attach adapter detach client eeprom detach client Registering a chip driver To register this I2C chip driver the function i2c add driver should be called with a pointer to the struct i2c driver static int init eeprom init void f return i2c add driver amp eeprom driver Unregistering a chip driver To unregister the 12C chip driver the i2c del driver function should be called with the same pointer to the struct i2c driver I2c del driver is defined in include linux i2c h which will internally call i2c unregister driver defined in drivers i2c i2c core c static void exit eeprom exit void f i2c del driver zeeprom driver Doc ID 16604 Rev 2 81 245 www BDTIC com ST Communication device drivers UM0851 Note 82 245 Attaching an adapter After the registration of the I2C chip driver when an I2C bus driver is loaded the attach adapter function callback is called This function checks if any I2C devices are on the 12C bus to which the client driver wants to attach static
58. can be used to program and configure watchdog timer The following code snippet demonstrates the use of these ioctls int ret 0 int timeleft 0 struct watchdog_info ident int timeout 45 in seconds to find out supported options in watchdog ret ioctl fd WDIOC GETSUPPORT amp ident to set time out ioctl fd WDIOC SETTIMEOUT amp timeout to find out how much time is left before reset ret ioctl fd WDIOC GETTIMEOUT amp timeleft Refresh watchdog timer at every 10 secs to prevent reset while 1 ioctl fd WDIOC KEEPALIVE 0 sleep 10 The following table lists the standard ioctl calls supported by the SPEAr watchdog driver Table 56 Watchdog IOCTLs IOCTLs Purpose The fields returned in the ident structure are identity A string identifying the watchdog driver firmware version the firmware version of the card if available options A flags describing what the device supports WDIOC GETSUPPORT This ioctl does exactly the same thing as a write to the watchdog device NOIGO KEEPALIVE and hence refreshes the timer Set time out in seconds after which reset would be generated if wat is WDIOC SETTIMEOUT not refreshed WDIOC GETTIMEOUT _ Query the current timeout Watchdog deamon The watchdog is a daemon It opens dev watchdog and keeps writing to it often enough to keep the kernel from resetting at least once per minute Each write
59. com ST Contents UM0851 4 6 um a na ABRA NA NAGING KA KA WE ER RAE NOME ROM NAKAALAY AN 86 4 6 1 Hardware overview 0 en 86 4 6 2 Software overview 0 eee eee eens 87 4 6 3 SPI framework in Linux ne 88 4 6 4 Un registering the driver llle 92 4 6 5 Known issues or limitations llle 92 4 6 6 SPI device driver performance 0 0 0 c eee eee 92 4 6 7 Configuration options es 92 4 6 8 References essc dus es ARRA DIN A REG ee Sa ERA NG 92 4 7 SDIO dilVBI vs dur bU BKA AKI ka NAG Saeed UKG ON shee PE DR da 93 4 7 1 Hardware overview sss 93 4 7 2 Software overview er 94 4 7 3 SDIO SD MMC usage in Linux 000 cee ee 95 4 7 4 SDIO host controller driver performance aa 97 4 7 5 Configuration options es 98 4 7 6 Heferences saa yd e ue de E RE uv e Dukha BG aH ds eee NG 98 4 8 UART driver scu e Ee ee Vana Paes ee eae EA ee ae oe ee Ve 98 4 8 1 Hardware overview 0 000 c cece nn 98 4 8 2 Software overview 2 er 99 4 8 3 TTY framework in Linux l i 100 4 8 4 Configuration options eren 104 4 9 CANGINGE 4 352 923 3 5 3874 3 9 39 deco dt fec aea editi e qa die do tuns 105 4 9 1 Hardware overview nes 105 4 9 2 Software overview llle ne 106 4 9 3 Socket CAN framework in Linux 0 00 cece eee eee 107 4 9 4 SPEAr CAN driver 0 eens 108 4 9 5 User land a
60. delays the reboot time another minute After a minute the watchdog hardware generates a reset The watchdog can be stopped without causing a reboot if the device dev watchdog is closed correctly unless your kernel is compiled with the CONFIG_WATCHDOG_NOWAYOUT option enabled a 214 245 Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Miscellaneous device drivers 9 2 5 9 2 6 9 3 9 3 1 The default timeout period can be programmed by passing an argument to the watchdog daemon in following manner watchdog T 60 Configuration options The following kernel configuration options affect the watchdog These configurations can be selected through the make menuconfig interface in Linux Table 57 Linux kernel configurations Configuration option Comment CONFIG WATCHDOG This enables the watchdog support in the Linux kernel Enabling this option means that even on closing watchdog the timer would remain active and would eventually reset the system if not refreshed Hence the wdt cannot be stopped once started CONFIG WATCHDOG NOWAYOUT CONFIG SPEAR SP805 WATCHDOOG This enables SPEAr watchdog support References e linux 2 6 27 Documentation watchdog txt Pulse width modulator PWM driver In some embedded application areas there is the specific need for providing intermediate amounts of power between off and on for example to control the speed of a DC motor to vary the brightness o
61. described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE U
62. device drivers UM0851 4 9 6 4 9 7 110 245 Netlink interface for the CAN driver The CAN network device driver interface provides a generic interface to setup configure and monitor CAN network devices via the netlink interface using the program ip from the IPROUTE2 utility suite The supported netlink message types are defined and briefly described in include linux can netlink h for CAN network device drivers The following section of this document describes briefly how to use this with a CAN interface canO Set Get devices properties using Netlink interface e To set CAN device properties ip link set can0 type can e Todisplay CAN device details and statistics ip details statistics link show can0 e Tosetthe CAN bit timing CAN bit timing parameters can always be defined in a hardware independent format as proposed in the CAN 2 0 specification specifying the arguments tq prop seg phase seg1 phase seg2 and sjw ip link set can0 type can tq 125 prop seg 6 phase segl 7 phase seg2 2 sjw 1 e Tosetthe CAN device bit rate ip link set can0 type can bitrate 125000 Starting and stopping a device using Netlink interface e Tostart a CAN network device ip link set can0 up OR ifconfig can0 up e To stop a CAN network device ip link set can0 down OR ifconfig can0 down Kernel configuration options The following table contains the options that can be enabled in the kernel to support CAN in
63. disk drives and Flash memories Plug in Flash memory into available USB port and then type the following command The device is picked up as a USB 1 1 and allocates an address It also indicated which HCD is used dmesg less usb 1 1 new full speed USB device using spear ehci and address 2 usb 1 1 configuration 1 chosen from 1 choice SCSI emulation automatically kicks in scsi0 SCSI emulation for USB Mass Storage devices usb storage device found at 2 Now the device information including model number is retrieved usb storage waiting for device to settle before scanning Vendor JetFlash Model TS2GJCV30 Type Direct Access ANSI SCSI revision 02 SCSI device sda 4014078 512 byte hdwr sectors 2055 MB The write protect sense is EXPERIMENTAL code in the later kernels Sda Write Protect is off Sda assuming drive cache write through SCSI device sda 4014078 512 byte hdwr sectors 2055 MB sda Write Protect is off Sda assuming drive cache write through sda sdal usb storage Attached SCSI removable disk At this point the device is generally accessible by mounting dev sdal When the device is disconnected the system acknowledges the same usb 1 1 USB disconnect address 2 Once the device is connected and mounted you can access it like a normal hard disk Usual operations like cp mv rm etc work fine You could also create a file system on the USB stick format it mount dev sdal mnt df h File
64. down is detected and it is the same key as in the previous scan a bit is set in the Status register indicating New Key Data The code for the key is written to the keyboard value register Key release is signaled only once The keypad encoder initialization is made once only when the application starts setting the prescaler load value keypad enable scan rate keypad operation mode The software then handles the keypad interrupts The following table shows the assignment of the keypad matrix signals on the SPEAr300 PL GPIO pins Table 47 PL GPIO keypad pins Port Pin PL GPIO Keypad ROWO PL GPIO87 output kbd row O ROW1 PL GPIO86 output kbd row 1 ROW2 PL GPIO85 output kbd row 2 ROW3 PL GPIO84 output kbd row 3 ROW4 PL GPIO83 output kbd row 4 ROW5 PL GPIO82 output kbd row 5 ROW6 PL GPIO81 output kbd row 6 ROW7 PL GPIO56 output kbd row 7 ROW8 PL GPIO55 output kbd row 8 COLUMNO PL GPIO96 Input kbd column O COLUMN 1 PL GPIO95 Input kbd column 1 COLUMN2 PL GPIO94 Input kbd column 2 COLUMN3 PL GPIO93 Input kbd column 3 COLUMNA PL GPIO92 Input kbd column 4 COLUMNS PL GPIO91 Input kbd column 5 COLUMN6 PL GPIO90 Input kbd column 6 COLUMN7 PL GPIO89 Input kbd column 7 COLUMNS PL GPIO88 Input kbd column 8 7 2 2 Software overview The keypad is a 18 pin interface module that is used to detect the pressed key in an 9x9 maximum keypad matrix The size of the input keypad matrix is software programmable The keypad module supports two modes of operation
65. driver to look for command line dynamic partition If not found then driver will go for static partition CONFIG MTD CONCAT Support for concatenating several MTD devices into a single virtual one This allows you to have for example a JFFS2 file system spanning multiple physical Flash chips CONFIG MTD CHAR This provides a character device for each MTD device present in the system allowing the user to read and write directly to the memory chips and also use ioctl to obtain information about the device or to erase parts of it CONFIG MTD BLOCK Although most Flash chips have an erase size too large to be useful as block devices it is possible to use MTD devices which are based on RAM chips in this manner This block device is a user of MTD devices performing that function Doc ID 16604 Rev 2 a www BDTIC com ST UM0851 Non volatile memory device drivers 5 3 8 5 4 5 5 5 6 References http www linux mtd infradead org tech mtdnand index html MTD source code under directory drivers mtal for Linux 2 6 27 SPEAr NOR Flash device driver drivers mtd devices spr_nor_st c http www linux mtd infradead org index html USB mass storage support Non volatile memories such as data flashes or magnetic hard disk can be plugged to SPEAr and accessed using the USB mass storage device class Please refer to Section 4 3 USB Host for more details I2C and SPI memory device su
66. enum spear_sync_delay NODELAY 0 for no delay DELAY1 1 for 1 byte delay DELAY2 2 for 2 byte delay DELAYA 4 for 4byte delay x enum spear sync type SYNCO 0 used in slave mode sampled at slave clock rate ClkSM SYNC1 used in master mode SYNC2 used in master mode SYNC3 used in master mode is Configuring timeslot Configuring timeslot number This API is used to configure the timeslot number register The argument specifies the number of timeslots contained in the frame By programming 2 in the timeslot register indicates that the sync signal will be generated after two timeslots max ts specifies the maximum number of timeslot user wants to configure Maximum timeslot can be configure is 1024 0x400 It will return zero on success and negative value on error Spear tdm ts max u32 max ts Channel configuration This API indicates how many channels are present It also indicates how many valid bits are used to indicate the channel number The API is not used in Switching Doc ID 16604 Rev 2 201 245 www BDTIC com ST Audio video drivers UM0851 202 245 The API is called only once at the start of bufferization The only way to change the channel configuration is by resetting the device Setting the maximum channel as n can be O 2 4 8 16 means dividing the buffer memory into n equal blocks max chan specifies the maximum number of channels It could
67. fck 0 166000000 0 fsmc fck 0 83000000 1 udc ck 0 48000000 1 appl sub gpio fclk 0 83000000 0 basic sub gpio fclk 0 83000000 0 jpeg fclk 0 166000000 0 ssp2 fclk 0 83000000 0 ssp1 fclk 0 83000000 0 ssp0 fclk 0 83000000 0 adc fclk 0 83000000 0 dma fclk 0 166000000 1 clcd fclk 0 48000000 0 mmci fclk 0 33000000 0 wdt fck 0 30000000 0 i2c fck 0 166000000 0 i2c ick 0 83000000 0 uart2 fck 0 48000000 0 uart1 fck 0 48000000 1 rtc fck 0 32000 0 gpt5 fck 0 48000000 0 gpt5 ick 0 83000000 0 gpt4 fck 0 48000000 0 gpt4 ick 0 83000000 0 gpt3 fck 0 48000000 0 gpt3 ick 0 83000000 0 gpt2 fck 0 48000000 0 gpt2 ick 0 83000000 0 gptl fck 0 332000000 2 gptl ick 0 83000000 2 core apb lo sys ck 0 83000000 1 core apb cpu2 sys ck 0 83000000 0 core apb cpul sys ck 0 83000000 1 core apb basic sys ck 0 83000000 0 core apb app sys ck 0 83000000 0 core ahb ck 0 166000000 4 mpu ck 0 332000000 0 core ck 0 332000000 2 pill ck 0 332000000 1 p113 48 ck 0 48000000 2 sys ck O 30000000 2 osc sys ck 0 30000000 1 spear 32k ck 0 32000 0 The command displays all the clocks in the clock dependency tree in the following format Table 63 Clock dependency tree display format example Clock name Clock ID Clock rate Clock usage count gmac fck 0 166000000 0 The above data can be interpreted to obtain the information that the GMAC functional clock has a clock rate of 166 MHz and it s usage count is zero indicates that th
68. flags It can t be called directly call it using chan pointer tx chan device spear prep dma memset chan dest val len flags Check the Start transfer section below for for details on starting the actual transfer Peripheral to peripheral or memory to from peripheral transfer Transfers involving peripherals are peripheral to peripheral and memory to from peripheral transfers The routine is exported from the DMA driver Here synchronization issues are to be handled by client driver In this routine synchronization issues are expected to be handled by the client driver Firstly you need to prepare transfers then assign any callback if required and then start the actual transfer Transfers with peripherals always require you to pass the configuration so the slave pointer in the client structure must be non NULL A transfer is prepared by the following call chan is a pointer to DMA channel allocated to client sgl is a scatter list prepared by the client driver Nodes of this scatter list are configured with the address of memory or address of another peripherals register with which current peripheral wants to do transfer This enables the user to perform scatter gather feature of DMA i e a single DMA transfer can transfer data to from different memory buffers which are not present continuously in memory sg len number of scatterlist nodes in sgl direction if direction is DMA TO DEVICE then data is transferre
69. hardware architecture IC Clock 2C controller Reset Clock DMA interface Software overview The following figure illustrates the Linux I2C subsystem It shows the role of the I2C framework which interfaces the I2C bus driver below to the I2C specific device drivers above Doc ID 16604 Rev 2 79 245 www BDTIC com ST Communication device drivers UM0851 4 5 3 80 245 Figure 20 12C framework architecture User application I2C user mode application 12C client driver I2C dev sys dev I2C core layer 12C controller driver I2C controller User space Kernel space Hardware 12C framework in linux The 12C kernel code is broken up into a number of logical pieces the I2C core I2C bus drivers I2C algorithm drivers and I2C client drivers 12C core The 12C core is a code base consisting of routines and data structures available to host adapter drivers and client drivers The core also provides a level of indirection that renders client drivers independent of the host adapter allowing them to work even if the client device is used on a board that has a different I2C host adapter Device drivers for I2C host adapters They fall in the realm of bus drivers and usually contain an adapter driver The former uses the latter to talk to the I2C bus I2C host adapter code is provided by ST and the path is Refer to Linux 2 6 27 drivers i2c bus spr i2c syn
70. int irq void enable unsigned int irq void disable unsigned int irq Doc ID 16604 Rev 2 35 245 www BDTIC com ST Platform section UM0851 3 2 3 3 2 4 36 245 void ack unsigned int irq void mask unsigned int irq void mask ack unsigned int irq void unmask unsigned int irq void eoi unsigned int irq void end unsigned int irq void set affinity unsigned int irq cpumask t dest int retrigger unsigned int irq int set type unsigned int irq unsigned int flow type int set wake unsigned int irq unsigned int on Currently used only by UML might disappear one day ifdef CONFIG IRQ RELEASE METHOD void release unsigned int irq void dev id endif For compatibility gt typename is copied into gt name Will disappear sconst char typename IT VIC API high level IRQ flow handlers in SPEAR In the SPEAr architecture code the setup for the chip level hardware encapsulation is done at the boot up time The basic primitives provided are ack mask unmask set wake You can see the code at arch arm mach spearxxx irq c For each interrupt triggered these functions provide the interrupt handling at the VIC level and handle the VIC specific settings in the registers for the Acknowledgement Masking Un Masking Setting up the Wake up sources at the VIC level Static struct irq chip vie chip name spear vic ack vic
71. layers and the input output buffers of any socket are lists of struct sk buff The same struct sk buff is used to host network data throughout all the Linux network subsystems but a Socket buffer is just a packet as far as the interface is concerned A pointer to struct sk buff is usually called skb This practice is used both in the sample code and in the text The skb buffers used for the reception or transmission must guarantee cache coherency These buffers are allocated in the cached memory regions and therefore there is a possibility that the memory data is not in synch with cache The driver uses the following calls for cache coherency dma addr t dma map single struct device dev void ptr size t size enum dma data direction dir Depending upon the directions of the data transfer the above function either invalidates or clean the cache contents If the argument dir in the above function is set as DMA FROM DEVICE this argument may do nothing in the above function but invalidates the cache when used in dma unmap single If the argument dir is set to DMA TO DEVICE it cleans the cache Cleaning a cache reestablishes coherence between the cached memory and the main memory void dma unmap single struct device dev dma addr t dma addr size t size enum dma data direction dir The call to the above function is made when the packet has been received to see if a mapped address was really a safe buffer and if so
72. lt gt USB Modem CDC ACM support lt gt USB Printer support lt gt USB Mass Storage support a Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Communication device drivers If you have a USB keyboard mouse joystick or any other input device you need to enable HID support Go back one level to Device drivers and enable HID support as shown Device Drivers gt 4 HID Devices gt lt gt USB Human Interface Device full HID support If you have a USB modem you need to enable USB Modem CDC ACM support as shown above along with the following supports Device Drivers gt Network device support gt USB Network Adapters gt lt gt Multi Purpose USB Networking Framework 4 4 USB Device 4 4 1 Hardware overview SPEAr600 provides a Synopsys s USB 2 0 Device controller which is fully compliant with the universal serial bus specification version 2 0 and offers an interface to the industry standard AHB bus The main features provided by the USB 2 0 Device are listed below e USB plug detect UPD which detects the connection disconnection of a device e UDC AHB supports 480 Mbps high speed HS for USB 2 0 as well as 12 Mbps full speed FS for USB 1 1 e UDC AHB supports 16 physical unidirectional endpoints and proper configurations to achieve logical endpoints e Both DMA mode and slave only mode supported e in DMA mode the UDC AHB supports descriptor based memory structures in applica
73. management Kernel space Governor e CPUfreq core The CPUfreq core offers a standardized interface for the CPUfreq architecture drivers CPUfreq notifiers conform to the standard kernel notifier interface The device drivers have to register themselves into these notifier lists to be informed of the events e CPUfreq driver The architecture driver for the CPUfreq changes the registers into the CPUfreq framework and does the actual work of frequency transition The details about this are covered in the next section Architecture driver e CPUfreq Governors The CPUfreq infrastructure allows for frequency changing policy governors which can change the CPU frequency based on different criteria such as CPU usage Here is a list of the governors which you can select Performance governor keeps the CPU at the highest possible frequency within a user specified range Powersave governor keeps the CPU at the lowest possible frequency within a user specified range Userspace governor exports the available frequency information to the user level through the sysfs and permits user space control of the CPU frequency All user space dynamic CPU frequency governors use this governor as their proxy Doc ID 16604 Rev 2 225 245 www BDTIC com ST Power management section UM0851 Note 226 245 1 Ondemand governor varies the CPU fre
74. ops struct module owner int open struct device void release struct device int ioctl struct device unsigned int unsigned long int read time struct device struct rtc time int set time struct device struct rtc time int read alarm struct device struct rtc wkalrm int set alarm struct device struct rtc wkalrm int proc struct device struct seq file int set mmss struct device unsigned long secs hg rtc rtc device register pdev 5name amp pdev dev a Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Platform section 4 amp spear_rtc_ops THIS MODULE The following system calls are supported by Linux RTC framework Opening the RTC device The open function is used to establish the connection between the RTC device and a file descriptor int fd fd open dev rtc O RDONLY 0 IOCTL operations The ioctl command is used to configure the RTC device int fd struct rtc time rtc tm int ret fd open dev rtc O RDONLY 0 the ioctl command RTC RD TIME is used to read the current timer y ret ioctl rtc fd RTC RD TIME amp rtc tm close fd Table 13 RTC ioctl requests Request Description RTC AIE OFF This ioctl does not need an argument and it can be used to disable the RTC alarm interrupt RTC AIE ON This ioctl does not need an argument and it can be used to enable the R
75. p Y Gee ade a Soa eke Se 56 MACB software layers 0006 tenes 57 USB driver overview 0 0 cette ee 62 USB Host performance at buffer length 4096 0c cece eee 67 USBD interface osi ceu bor er Ram R e ker ta eee eee eee 70 USBD software architecture rn 71 Zero gadget device 2 lehren 72 USB Device performance at buffer length 4096 seres 77 I2C hardware architecture 4 79 I2C framework architecture hn 80 Master slave connectivity e eee 86 SPI driver architecture ct eee 88 SDIO block diagram hh 93 SD SDIO MMC Linux protocol stack lille 95 The interface between UART and RS 232 2 2 esee 99 UART software system architecture llle 100 Block diagram of CAN IP iissssssssesesee hr 106 Socket CAN architecture hn 107 HDLC software system architecture liliis 114 Data structure layers hn 115 Interface between FSMC and NAND Flash 0000 c cece eere 124 NAND software system architecture 2 0 0 2 eee 124 OOB layout for various size NAND Flash 00000 cee eee eee eee 129 NAND memory performance yaffs2 type 0 00 cee ee 136 NAND memory performance jffs2 type lille 137 EMI system software architecture llle 140 The interface between NOR Flash and SMI controller 0 0000000 aes 144 NOR Flash software system archi
76. packets packet size test patten It supports two port tests If only one port is specified the tool both transmits and receives on this port It two ports are specified the tool transmits on the first ports and try to receive on the second port List HDLC channels The HDLC channels are just a network devices in Linux Use ifconfig command to see them Example ifconfig a hd1lcO0 Link encap UNSPEC HWaddr 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 POINTOPOINT NOARP MTU 1500 Metric 1 RX packets 0 errors 0 dropped 0 overruns 0 frame 0 TX packets 0 errors 0 dropped 0 overruns 0 carrier 0 collisions 0 txqueuelen 7 RX bytes 0 0 0 B TX bytes 0 0 0 B a Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Communication device drivers 4 10 9 hdlc1 Link encap UNSPEC HWaddr 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 POINTOPOINT NOARP MTU 1500 Metric 1 RX packets 0 errors 0 dropped 0 overruns 0 frame 0 TX packets 0 errors 0 dropped 0 overruns 0 carrier 0 collisions 0 txqueuelen 7 RX bytes 0 0 0 B TX bytes 0 0 0 B hdic2 Link encap UNSPEC HWaddr 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 POINTOPOINT NOARP MTU 1500 Metric 1 RX packets 0 errors 0 dropped 0 overruns 0 frame 0 TX packets 0 errors 0 dropped 0 overruns 0 carrier 0 collisions 0 txqueuelen 7 RX bytes 0 0 0 B TX bytes 0 0 0 B hdl1c3 Link encap UNSPEC HWaddr 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 POINTOPOINT NOARP MT
77. reg void mdio write struct net device dev int addr int reg int val b In case you are not able to use the generic existing phy interfaces and want to add support for a new phy interface xxx phy def you can add this in the phy table The current table provides support for National ST and a Generic PHY interface static struct mii phy def mii phy table amp st phy def amp national phy def amp genmii phy def amp xxx phy def NULL ka Similarly Define the details of the member function for example static struct mii phy def xxx phy def phy id 0x00000000 phy id mask 0x00000000 name XXX MII Ops amp xxx_phy_ops I Make sure to provide in the proper PHY ID and the Mask as defined in the PHY configuration registers of the Phy to properly identify the Phy Define the Operations to be performed on PHY xxx static struct mii phy ops xxx phy ops Setup aneg xxx mii setup aneg setup forced xxx mii setup forced poll link xxx mii poll link read link xxx mii read link Doc ID 16604 Rev 2 47 245 www BDTIC com ST Communication device drivers UM0851 48 245 State the member functions as provided in the above structure as per your design requirements GMAC interface to kernel The key kernel interfaces that have been set up in the initialization routines are int open struct net device dev This is the function that ope
78. struct clk parent unsigned long rate v32 flags volatile u32 enable reg u8 enable bit 88 usecount void recalc struct clk int set_rate struct clk unsigned long long round_rate struct clk unsigned long void init struct clk int enable struct clk void disable struct clk u32 prcmid u8 fixed div volatile u32 clksel reg u32 cilksel mask const struct clksel clksel const struct dpll data dpll data u8 rate offset u8 src offset is a Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Power management section 10 3 3 CPU freq framework API The architecture specific CPUfreq driver registers into the CPUfreq core via the following structure struct cpufreq driver struct module owner char name CPUFREQ NAME LEN u8 flags int init struct cpufreq policy policy int verify struct cpufreq policy policy int setpolicy struct cpufreq policy policy int target struct cpufreq policy policy unsigned int target freq unsigned int relation should be defined if possible unsigned int get unsigned int cpu optional unsigned int getavg unsigned int cpu int exit struct cpufreq policy policy int suspend struct cpufreq policy policy pm message t pmsg int resume struct cpufreq policy policy struct freq attr attr js Above defined structure provide few call back functions t
79. support device specific commands int fb ioctl struct fb info info unsigned int cmd unsigned long arg LP gue EL i Framebuffer sources dev fbO also allows several IOCTLs on it by which a lot of information about the hardware can be queried and set The color map handling works via IOCTLs too Look into lt linux fb h gt for more information on what IOCTLs exist and on which data structures they work Here s just a brief overview Table 50 Framebuffer information in source code Directory or resource Purpose The frame buffer core layer and low level frame buffer driversreside in this drivers video directory include linux fb h Generic frame buffer structures are defined in this directory include video Chipset specific headers stay inside this directory Creates the dev fbX character devices and is the front end for handling BIS Veo OE frame buffer ioctl commands issued by user applications How to support a new CLCD panel There is a separate application note AN2641 which discusses this in detail However in short for a new CLCD panel at least following needs to be checked in the device driver Step 1 CLCD panel information should be defined in platform amba device of arch Step 2 CLCD panel should be supported by ARM PL110 Controller The types of panels supported by controller are listed in the corresponding SPEAr user manual CLCD driver usage A framebuffer device i
80. the start of the usable area size the length in bytes More than one area can be defined The list is terminated by an 0 0 entry ki The OOB layout for 512 page size NAND Flash over SPEAr platform is as follows static struct nand ecclayout spear nand oobinfo 512 eccbytes 3 eccpos 2 3 4 oobfree 8 8 The total number of OOB bytes for 512 byte data is 16 In OOB bytes 3 bytes at offset 2 3 and 4 are for the ECC 8 bytes from offset 8 to 15 are free and used by file system specific information One byte at offset 5 is used for bad block information OOB layout for 2048 page size NAND Flash in the SPEAr platform is as follows static struct nand ecclayout spear nand oobinfo 2048 eccbytes 12 eccpos 2 3 4 18 19 20 34 35 36 50 51 52 128 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Non volatile memory device drivers oobfree 8 8 24 8 40 8 56 823 hi Figure 33 OOB layout for various size NAND Flash Small Page NAND Flash 0 511 528 1039 1056 512 bytes page 16 byte OOB 2 5 D Bet 2 Ode Er S RO BUE ET 16 byte OOB for x8 NAND Flash x x ec FRx x x x x x x x x x f OOB 5 OxFF block is NOT valid 16 byte OOB for x16 NAND Flash B B Ecc xixixixixixixixix xx if OOB 0 OxFFFF block is NOT valid Large Page NAND
81. the struct fb var screeninfo The command FB ACTIVATE FORCE enables and activates the CLCD The program then goes on to mmap the framebuffer memory and writes color data in each constituent pixel bit Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Audio video drivers fbfd open dev fb0 O_RDWR Open the file for reading and writing ioctl fbfd FBIOGET FSCREENINFO amp finfo Get fixed screen information ioctl fbfd FBIOGET VSCREENINFO amp vinfo Get variable screen information vinfo activate FB ACTIVATE FORCE FB ACTIVATE NOW ioctl fbfd FBIOPUT VSCREENINFO amp vinfo Put variable screen information to Switch ON CLCD Panel Screensize vinfo xres vinfo yres vinfo bits per pixel 8 Figure out the size of the screen in bytes Map the device to memory fbp char mmap 0 screensize PROT READ PROT WRITE MAP SHARED fbfd O Loop will draw 3 color bands blue green and red for location 0 y 0 y vinfo yres yt for x 0 x lt vinfo xres x if y vinfo yres 3 fbp location OxFF show Blue fbp locationt1 0 no Green fbp location 2 0 no Red fbp location 3 0 No Transparency else if y lt 2 vinfo yres 3 fbp location OxFF no Blue fbp location 1 0 show Green fbp location 2 0 no Red fbp location 3 0 No transpar
82. the touchscreen over Xserver then just providing the device name is enough Table 46 Configuration options Configuration option Comment This option make input device events be CONFIG INPUT EVDEV accessible under char device 13 644 dev input eventX in a generic way CONFIG INPUT TOUCHSCREEN This option enables the touchscreen device Doc ID 16604 Rev 2 177 245 www BDTIC com ST Human interface device HID drivers UM0851 Note 7 2 7 2 1 178 245 Table 46 Configuration options continued Configuration option Comment This option enables the SPEAr touchscreen CONFIG_TOUCHSCREEN_SPEAR device This option enables debug prints for the SPEAr CONFIG TOUCHSCREEN SPEAR DEBUG h touchscreen device This option make input device events be CONFIG INPUT EVDEV accessible under char device 13 64 dev input eventX in a generic way Both CONFIG INPUT TOUCHSCREEN and CONFIG TOUCHSCREEN SPEAR must be defined CONFIG TOUCHSCREEN SPEAR is visible only if CONFIG INPUT TOUCHSCREEN is defined CONFIG INPUT TOUCHSCREEN selects the touchscreen CONFIG TOUCHSCREEN SPEAR selects the SPEAr device for touchscreen References e Linux 2 6 27 Documentation input input txt e Linux 2 6 27 Documentation input input programming txt Keypad driver This section describes the keypad controller driver This controller and driver are present on SPEAr300 only Hard
83. they pass acceptance filtering into a receive buffer e Loopback combined with silent mode This mode can be used for a hot self test meaning the CAN IP can be tested without affecting a running CAN system connected to the pins CAN TX and CAN RX e Basic mode In this mode the CAN IP runs without the Message RAM For further details please refer to SPEAr320 user manual Doc ID 16604 Rev 2 105 245 www BDTIC com ST Communication device drivers UM0851 4 9 2 Note 106 245 Figure 27 Block diagram of CAN IP CAN TxCAN Rx CAN Core Message RAM i n Module Interface Clock Reset Interrupt Control Dataln DataOut Address 7 0 Software overview AN controller driver in SPEAr LSP is based on the socket CAN framework Socket CAN uses the Berkeley socket API and the Linux network stack and implements the CAN device drivers as network interfaces As shown in the figure below the socket CAN driver sits on the top of the CAN controller IP and directly interfaces with the socket layer through the standard SOCK RAW and SOCK DGRAM interfaces In the Linux source tree the socket CAN driver for SPEAr is present in drivers net can spr can c Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers Figure 28 Socket CAN architecture Application User Space Socket Layer Protocol family Protocol family kernel CAN Internet Space
84. to pass JPEG header and compression table information to JPEG driver in all above cases except DWH In DWH JPEG codec extracts header and table information from input JPEG image Before proceeding with encoding decoding you will provide header and table information to JPEG driver not required for DWH Use the following system call to set JPEG info for EWH and EWOH ioctl wfd JPEGIOC SET ENC INFO amp enc info wfd file descriptor of jpeg write node JPEGIOC SET ENC INFO ioctl command for setting JPEG encoding information enc info structure containing jpeg encoding information Description of enc info structure struct jpeg enc info struct jpeg hdr hdr jpeg image header int hdr enable header processing enable disable char qnt mem QNT MEM SIZE quantization memory char dht mem DHT MEM SIZE DHT memory char henc mem HENC MEM SIZE Huff enc memory hi Description of jpeg hdr structure struct jpeg hdr u32 num clr cmp number of color components minus 1 u32 clr spc type number of quantization tables in the output stream u32 num cmp for scan hdr number of components for scan header marker segment minus 1 u32 rst mark en restart marker enable disable u32 xsize number of pixels per line u32 ysize number of lines u32 mcu num this value defines the number of minimum coded units to be coded minus 1 u32 mcu num in rst number of mcu s between tw
85. usual bad block marker in the OOB area does not allow us to distinguish between factory bad and worn out bad blocks we need to store this information elsewhere This place is called bad block table BBT and is stored as a bitmap in the last two good blocks at the end of NAND To increase security a backup of those two blocks is kept in the two preceding good blocks as well The BBT location itself is identified by special markers BBTO BBT1 in the OOB area of the first page of the respective erase blocks The BBT consists of two bits per block Both U Boot and Linux implement the same BBT layout and thus interoperate quite well The BBT is created once a BBT implementing U Boot is started for the first time The BBT scanning code assumes that the NAND is completely erased and only contains OxFF as content Any block that contains bytes OxFF in the OOB is marked as factory bad block In order to maintain the BBT created by U Boot the kernel needs to have BBT support enabled In Linux nand scan calls the function nand default bbt nand default bbt selects appropriate default bad block table descriptors depending on the chip information which was retrieved by nand scan The standard policy is scanning the device for bad blocks and build a RAM based bad block table which allows faster access than always checking the bad block information on the Flash chip itself To skip this process NAND SKIP BBTSCAN can be used Flash based tables
86. 0 ls dev mtd Ccrw rw Crw rw Crw rw Crw rw Ccrw rw Ccrw rw Ccrw rw Crw rw brw rw brw rw brw rw brw rw brw rw brw rw brw rw brw rw DQ QD OD OD DD O O QD DQ O O O O O erasesize 00010000 00010000 00010000 00010000 00004000 00004000 00004000 00004000 H name XLoader UBoot Kernel Root File system XLoader Uboot Kernel Root File system DQ QD OD DD DQ OD O O DQ DQ O O O O O 90 90 90 90 90 90 90 90 WWWW WW WwW Raw mode usage from user space oo ND ib N O PRR ANO IAURB WN H O Jan Jan Jan Jan Jan Jan Jan Jan Jan Jan Jan Jan Jan 1 00 1 00 1 00 1 00 1 00 1 00 1 00 1 00 1 00 1 00 1 00 1 00 1 00 1 00 1 00 L 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 dev mtdO0 dev mtd1 dev mtd2 dev mtd3 dev mtd4 dev mtd5 dev mtd6 dev mtd7 dev mtdblock0 dev mtdblock1 dev mtdblock2 dev mtdblock3 dev mtdblock4 dev mtdblock5 dev mtdblock6 dev mtdblock7 Raw mode means accessing NAND via MTD layer without using file systems MTD utils can be used to access NAND Flash directly without file system MTD utils uses nodes such as dev mtdX or dev mtdblockX and operates using IOCTL calls Doc ID 16604 Rev 2 133 245 www BDTIC com ST Non volatile memory device drivers UM0851 The MTD project prov
87. 00 PLL2 So effectively this command DDR frequency changed to 300 changes PLL1 2 frequency This changes the PLL1 frequency to 300 MHz sleep Delay execution for some time 1 2 5 Booting Linux with U Boot This section describes how to configure U Boot in order to achieve different booting schemes For example in some environments it might be required to have a completely standalone board while during development phase it is recommended to boot from network and to mount RootFS through NFS The Linux kernel accepts a command line that can be used to pass arguments to the kernel and to overwrite statically built in values In this way the you can change parameters without the need to rebuild the kernel Please refer to the Linux kernel source tree file Linux Documentation kernel parameters txt for a complete listing of all the supported kernel arguments Das U Boot stores the argument list in the environment variable bootargs The syntax is a sequence of items in the form key value where key is a well known argument defined by the kernel The following list contains the most common arguments e memznn This argument forces the usage of a specific amount of memory This can be the total size of the available memory or just a subset of it Linux will make use of this specific amount leaving the rest to different purposes like a 2nd OS setenv bootargs mem 128M e console Output console device and options setenv bootargs c
88. 00 17 0b 92 10 inet addr 192 168 1 1 Bcast 192 168 1 255 Mask 255 255 255 0 UP BROADCAST RUNNING MULTICAST MTU 4000 Metric 1 RX packets 0 errors 0 dropped 0 overruns 0 frame 0 TX packets 0 errors 0 dropped 0 overruns 0 carrier 0 collisions 0 txqueuelen 32 RX bytes 0 0 0 B TX bytes 0 0 0 B The maximum MTU size for SPEAr600 is 4000 and the for SPEAr300 is 9000 To shutdown the interface and reactivate it a Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Communication device drivers ifconfig eth0 down Ifconfig eth0 up Usage of Ethtool The ethtool utility is used to display or change the Ethernet card settings e Tosetup the auto negotiation ethtool s eth0 autoneg on e Tocheckthe existing network configurations result for SPEAr600 ethtool eth0 Settings for eth0 Supported ports MII Supported link modes 10baseT Half 10baseT Full 100baseT Half 100baseT Full 1000baseT Half 1000baseT Full Supports auto negotiation Yes Advertised link modes 10baseT Half 10baseT Full 100baseT Half 100baseT Full 1000baseT Half 1000baseT Full Advertised auto negotiation Yes Speed 1000Mb s Duplex Full Port MII PHYAD 1 Transceiver external Auto negotiation on Link detected yes e Tosetup the forced speed 100 full duplex mode thtool s eth0 autoneg off speed 100 duplex full setup the forced speed 100 half duplex mode htool s eth0 autoneg off speed 100 duplex half setup the forc
89. 1 Communication device drivers 4 7 3 Figure 24 SD SDIO MMC Linux protocol stack User space User applications Block UART WLAN BT Kernel space SDIO SD MMC core SDIO controller driver Hardware Arasan SDIO controller SDIO SD MMC usage in Linux You can interact with the SDIO SD MMC card inserted in the SDIO slot on SPEAr board from two levels either from the user level using the block device interface exposed by the existing card driver or from the core driver interface creating a new card driver Using the block device interface There are few card drivers present in Linux that expose the block device interface to the user application You can use dev mmcblkp1 dev mmcblkp2 etc nodes provided by this layer for any interaction with the SDIO SD MMC card Once the card is inserted you can mount its file system using the above nodes and access it like a normal mass storage device Usual operations like cp mv rm etc work fine You could also create a new file system structure on the memory card mount dev mmcblkp1 mnt Using the MMC core driver interface The core driver layer provides function calls to use the underlying SDIO hardware This section explains how you can create a new card driver There are few sample drivers present in Linux which use this interface They are present at the drivers mmc card folder The card driver can use functions exposed by the underlying core driver layer It must inc
90. 1 amp clockevent gpt clockevent gpt cpumask cpumask of cpu 0 clockevents register device amp clockevent gpt spear timer irq dev id void clk event tmr setup irq spear timer get irq clk event tmr amp spear timer irq spear timer set match clk event tmr 1 Configuration options As mentioned above the GPT hardware clock can be obtained from two sources the system clock PLL1 and PLL3 The system clock if selected goes through a synthesizer before reaching GPT This synthesizer can be programmed to obtain the desired operating frequency for GPT By default it is divided by 2 For more details please refer to the SPEAr user manual References e Refer to linux 2 6 27 Documentation timers for new time keeping and tick generation architecture of Linux Vector interrupt controller VIC driver This section describes the VIC driver Doc ID 16604 Rev 2 31 245 www BDTIC com ST Platform section UM0851 3 2 1 32 245 Hardware overview Each ARM subsystem of the SPEAR family has a Daisy Chained ARM PrimeCell amp vector interrupt controller PL190 The VIC provides a software interface to the interrupt system In a system with an interrupt controller software must determine the source requesting service and where its service routine is loaded A VIC does both of these in hardware It supplies the starting address or vector address of the service routine corresponding to the h
91. 1 26 0 Spear vic spear ssp 0 27 0 Spear vic spear ssp 1 28 0 Spear vic spear i2c 36 0 spear vic lt NULL gt Sus 0 spear vic spear ssp 2 42 1 Spear vic spear dmac 44 29164 Spear vic spear snor 50 0 spear vic rtc0 5 1 0 spear vic NULL 57 0 Spear vic spear udc 58 3 spear vic ohci hcd usb3 59 102 Spear vic ehci hcd usb1 60 1 spear vic ohci hcd usb4 61 0 spear vic ehci hcd usb2 Err 0 Table 12 Format of interrupt source list IRQ No No of interrupts Interrupt string passed in request irq 44 29164 spear snor 3 3 Real time clock RTC driver 3 3 1 Hardware overview The Real time clocks RTC is used to keep track of days dates and time including century year month hour minutes and seconds It supports the use of a battery switchover circuit enabling it to keep track of time even when power is off Features e Time of day clock in 24 hours mode e Calendar e Alarm capability e Self isolation mode which allows RTC to work even with no power supplied at the rest of the device a 38 245 Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Platform section 3 3 2 Figure 5 RTC functional block diagram CLK C32K P OSCI82B EN TST MODE SCAN TST MODE IDDQ PCDATA 31 0 PSEL RTC ___ INTERRUPT b gt RWRITE EP PADDR 4 2 PWDATA 31 0 Software overview RTC support in the kernel is architected into
92. 100mA I If 0 Alt 0 EPs 1 Cls 03 HID Sub 01 Prot 02 Driver usbhid E Ad 81 1 Atr 03 Int MxPS 4 Ivl 10ms USB keyboard Compile and then boot up the kernel with the options relevant to the USB keyboard enabled The options are covered in the configuration section below Plug in the USB keyboard You can then see print output messages that are similar to the following hub 1 0 1 0 over current change on prot 1 usb 3 1 new full speed USB device using spear ohci and address 4 usb 3 1 configuration 1 chosen from 1 choice input Dell Dell Smart Card Reader Keyboard as class input input3 input USB HID v1 11 Keyboard Dell Dell Smart Card Reader Keyoard on usb spear ohci 0 1 cat proc bus usb devices Bus 03 Lev 01 Prnt 01 Port 00 Cnt 01 Dev 4 Spd 12 MxCh 0 Ver 2 00 Cls 00 gt ifc Sub 00 Prot 00 MxPS 8 Cfgs 1 Vendor 413c ProdID 2101 Rev 1 00 Manufacturer Dell Product Dell Smart Card Reader Keyboard Ifs 2 Cfg 1 Atr a0 MxPwr 100mA If 0 Alt 0 EPs 1 Cls 03 HID Sub 01 Prot 01 Driver usbhid Ad 81 I Atr 03 Int MxPS 8 Ivl 24ms If 1 Alt 0 EPs 3 Cls 0b scard Sub 00 Prot 00 Driver none Ej Ej H EH HO unu td Y H Ad 02 0 Atr 02 Bulk MxPS 64 Ivl 0ms Ad 82 I Atr 02 Bulk MxPS 64 Ivl 0ms Doc ID 16604 Rev 2 65 245 www BDTIC com ST Communication device drivers UM0851 E Ad 83 I Atr 03 Int MxPS 8 Ivl 24ms 4 3 4
93. 212 WDT software architecture lille c ah 213 PWM output with a 1096 b 5096 and c 90 duty cycle 00000 216 Duty and Period AA AA LER ERREUR ee a ERA NER Rue EA EE 217 PWM driver architecture llle rra 217 System control state machine es 220 SPEAr clock tree susc Rx reae a Rana a Rake ad as e 224 CPU freq kernel architectural blocks e 225 Linux PM framework llle Rh e Rn 227 Clock framework architecture RR RR RR nn 229 SPEAr600 current consumption chart ee 239 SPEAr300 PM framework results llllllll RR Re 240 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Boot loader overview 1 1 Boot loader overview The SPEAr boot process is divided into four different stages On power on the BootROM hard coded in the silicon eROM starts first stage Its role is to locate XLoader and transfer the control to it The BootROM is embedded in the silicon and is not part of the LSP The following sections describe the features offered by the components which are not embedded in the silicon XLoader and U Boot because they are usually board dependent and need to be customized by the user These components are part of LSP v2 3 For a detailed description please refer to the corresponding SPEAr datasheet and user manual Figure 1 SPEAr booting stages D2800000h NAND NOR Shadow C BootROM memory eSRAM C X Loader ARM p Reset
94. 28M Build XLoader for SPEAr300 target with DDR 333MHz for size 128MB make SOC SPR300 DDRFREQ 333 DDRSIZE 128M Build XLoader which could be used as a firmware for initializing DDR with USB Flashing utility x make SOC SPR600 DDRFREQ 166 DDRSIZE 128M CONSOLE USB Build XLoader for all platform and all types normal XLoader and Flashing utility firmware KH makeall The XLoader source can be compiled with various options which are listed below e make SOC SPR300 This option generates XLoader for the requested platform Other platform options can be SPR600 SPR310 and SPR320 e make DDRFREQ 333 This option generates XLoader binary image with DDR driver that supports 333 MHz operation To generate XLoader for DDR 166 MHZ pass DDRFREQ 166 This option is available for SPEAr3XX and SPEAr600 e make DDRSIZE 128M This option generates XLoader for DDR size of 128 MB An other possible parameter can be 64 M to generate 64 MB XLoader e make CONSOLE USB This option generates XLoader which is used as a firmware to initialize DDR in USB flashing utility e make DDRFREQ 333 DDRCONF ASYNC This option generates XLoader to configure DDR 333 MHz asynchronoulsy for example the DDR is driven through the clock from PLL2 rather than PLL1 synchronous operation This option only works for DDR 333 MHz This XLoader can be used with some features of Linux Power Management like CPU Freq which currently guarantees o
95. 3 Configuration options hrs 177 PL GPIO keypad pins eR 179 Keypad configuration options A RR Ih 183 Doc ID 16604 Rev 2 9 245 www BDTIC com ST List of tables UM0851 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 10 245 ADC configurations options rn 190 Framebuffer information in source code llis 195 CLCD configuration options nh 197 Configuration options 0 rr 205 GPIO pin mapping in SPEAr3XX 2 nh 207 GPIO pin mapping in SPEAr600 eres 207 GPIO kernel configuration options ese 211 Watchdog IOC TES 224 pna dee NA oe Shae hee Looked e doe nba Segre a es 214 Linux kernel configurations 0 0 0 0 III 215 SDIO menuconfig kernel options tees 218 Power states for synchronous DRAM systems 221 Power states for asynchronous DRAM Systems 2 sees 221 SPEAr600 modules with DCS feature eee 222 SPEAr300 modules with DCS feature 0 0 00 ccc eee 222 Clock dependency tree display format example 0000 cece eee eee 234 SPEAr600 power consumption measurements 000 e eee eee ee 238 SPEAr300 power consumption measurements 000 eects 239 Linux PM framework configuration options
96. 4 1 3 GMAC API The following sections describe the GMA API Device registration The GMAC driver inserts a data structure for each newly detected interface into a global list of network devices Each interface is described by a struct net device item which is defined in linux netdevice h The structure must be allocated dynamically The kernel function provided to perform this allocation is alloc etherdev which has the following prototype struct net device alloc etherdev int sizeof priv Here sizeof priv is the size of the SPEAr MAC driver s private data area Once the net device structure has been initialized the process of registration is complete by passing the structure to register netdev The access to the SPEAr GMAC private data is done via standard call provided by kernel struct spear eth priv priv netdev priv dev The GMAC driver interacts with the kernel via the struct net device data structure The structure fields are initialized to provide the necessary interface The code below is a fairly routine initialization of the struct net device structure it is mostly a matter of storing pointers to the various functions of the driver struct net device dev dev gt open spear eth open dev gt stop spear eth stop dev do ioctl spear eth ioctl dev get stats spear eth get stats dev tx timeout spear eth tx timeout Doc ID 16604 Rev 2 45 245 www BDTIC com ST Communica
97. 4th offset of the OOB area For the 2048 bytes page size NAND Flash number of ECC are 12 bytes at the offset 2 3 4 18 19 20 34 35 36 50 51 and 52th respectively NAND partitioning Partitioning can be done by 2 ways static or dynamic Static partitions need to define a partitioning table in the NAND driver define NUM PARTITIONS 4 static struct mtd partition partition info64M 4096 X 0x00004000 name XLoader offset 0 size 0x00010000 4 X 0x00004000 Y name Uboot offset 0x00010000 Size 0x00050000 20 X 0x00004000 Js name Kernel offset 0x00060000 Size 0x00400000 256 X 0x00004000 name Root File system offset 0x00460000 size 0x03BA0000 3816 X 0x00004000 is Please note that the offset of any partition is in multiple of sector size of the NAND Flash While modifying the static partition table you should take care of this to avoid warning messages when creating partitions Dynamic partitions are defined in the command line arguments by using the command setenv bootargs console ttyS0 root dev mtdblock7 rootfstype yaffs mtdparts spear nand 4k XLoader 200k uBoot 2M Linux 61M Ramdisk The command line argument creates 4 partitions in the NAND Flash NAND device usage The user space application can access the NAND Flash device content using the mtdblock nodes dev mtdblockN and mtdchar nodes dev mtdN either in
98. 600 0 064312 203 8064436 0 057234 229 0107279 32 3200 0 107938 242 8653486 0 10739 244 1046652 40 4000 0 13325 245 9136961 0 132797 246 7525622 80 8000 0 24764 264 6422226 0 24686 265 4784088 160 16000 0 489281 267 8869607 0 4757 275 5350011 66 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers Table 20 USB Host device performance results continued BlkSize Data Size BulkOUT time BUIKOUT BulkiN time BulkIN s throughput s throughput KB KB Mbps Mbps 320 32000 0 959063 273 3334515 0 933094 280 9406126 400 40000 1 160719 282 3077765 1 160719 282 3077765 Figure 14 USB Host performance at buffer length 4096 300 ZA KA e 200 qm 5 I Bulk out amp 150 Bulk in i F 100 50 0 O O O KO SF SF PP s Data Size in KB 4 3 5 Kernel configuration options To ensure proper USB support for your devices you need to enable some of the options in the kernel The following table shows the configuration options Table 24 USB host configurations Configuration option Comment CONFIG_USB_SUPPORT This option adds core support for USB bus Enable this option if your system has the host side bus and you CONFIG_ USB want to use USB devices and also see your USB devices in proc bus usb This is recommended If you enable this option you will get a file proc bus usb devices which lists the devices
99. 8 bits wide Switching means that all the input timeslots of a frame received on the TDM are stored in the memory and at the next frame this data will be sent on the timeslot that is required to be switched Consider an example of switching TS3 is switched with TS1021 It means that during TS3 the TS3 content received on the DIN pin is stored at the 3rd byte of the storage part of the switching memory while TS1021 of the previous frame 1021st byte of the reading part of the switching memory is played on the DOUT pin During TS1021 TS1021 received on the DIN pin is stored at the 1021st byte of the storage part of the switching memory while TS3 of the previous frame 3rd byte of the reading part of the switching memory is played on the TDM output allowing a phone call to be established between the caller connected on TS3 and the one connected on TS1021 Figure 55 TDM waveforms Frame n Frame n 41 4 Pa b Input ITSO ITSx ITS31 frame y gt x Output OTSO OTS31 frame OTSy OTSy Software overview The TDM device driver sits on top of the TDM Controller and provides all necessary functions for switching and bufferization The TDM software system architecture is represented in the Figure 56 Doc ID 16604 Rev 2 199 245 www BDTIC com ST Audio video drivers UM0851 8 2 3 200 245 Figure 56 TDM driver architecture Kernel application Kernel space
100. 86 245 Configuration options Table 28 12C configuration options Configuration option Comment CONFIG l2C Enables I2C support CONFIG_I2C_CHARDEV Enables I2C device interface CONFIG I2C SPEAR Enables SPEAr I2C hardware bus support References e Linux 2 6 27 Documentation i2c e Linux 2 6 27 drivers i2c chips SPI driver This section describes the driver for the SPI controller embedded in SPEAr Hardware overview The serial peripheral interface bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode Devices communicate in master slave mode where the master device initiates the data frame Individual slave select chip select lines allow multiple slave devices SPI is used to connect microcontrollers to sensors memory and peripherals Figure 21 Master slave connectivity Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers 4 6 2 The SPI bus specifies four logic signals e SCLK serial clock output from master e MOSI master output slave input output from master MISO master input slave output output from slave e SS slave select active low output from master SPEAr600 has three SSP ARM PL022 controllers and SPEAr3xx has one SSP ARM PL022 controller SSP controllers are connected through the APB bus and thus they work on the APB clock SSP frequency is configured by dividing A
101. 9 0 65 1 46 5 64 32 49 6 21 9 0 64 1 46 Figure 34 NAND memory performance yaffs2 type 1 6 aq 8 e 98 8 1 4 Q 1 2 g 4 g Write to NAND memroy E as yatfs2 typo i B Read from NAND memory o 06 y affs 2 typ e nil 0 4 0 2 0 4 8 16 32 64 Block Size in KB Results for JFFS2 In JFFS2 compression is on by default This causes the writing of data which is uniform to finish in much less time Therefore compression was disabled from config Mount JFFS2 fs and write read to a file The sequence is as follows 136 245 Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Non volatile memory device drivers 1 mount t jffs2 dev mtdblock7 mnt 2 time dd if dev zero of mnt file bin bs 4K count 8192 Write the 3 file 4 umount mnt 5 mount t jffs2 dev mtdblock7 mnt 6 time dd if mnt file bin of dev null bs 4K count 8192 7 Read file back 8 umount mnt 9 mount t jffs2 dev mtdblock7 mnt 10 rm mnt file bin 11 umount mnt 12 Repeat for bs 8 16 32 64K and count 4096 2048 1024 512 Table 38 Results on SPEAr600 Block size Fils size ene Nawa in os Mega byte sec in InKbyiee TOME in write write in read read 1 4 32 22 311 1 434270091 17 92 1 785714286 2 8 32 22 127 1 446196954 14 984 2 135611319 3 16 32 22 129 1 446066248 17 59 1 819215463 4 32 32 21 933 1 458988738 17 506 1 827944705 5 64 32 22 03 1 452564685 17 462 1
102. AA ee me tn 243 REVISION DISIOFV 433a ane kcdeucacicacacg dade ae ico a OEC EC ewe e 244 8 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 ky Informative U Boot commands 0 c cette nee 17 Memory U Boot commands 0 2 0000 rn 17 Persistent storage U Boot commands I2C NOR NAND 2 220 18 Network U Boot commands hr 19 Image booting U Boot commands 0 00 nen 20 Environment variables U Boot commands cece eee eee 20 Serial i f file loading U Boot commands ees 20 Miscellaneous U Boot commands 2 nes 21 LSP v2 3 device drivers rers 23 GPTs available on SPEAr er 26 Differences between SPEAr600 and SPEAr300 00 eee 32 Format of interrupt source list eee 38 RTC ioctl requests 4 a es rere donauit obi deb ada e doe RUE DAE EE 41 RTC menuconfig kernel options ren 42 SP
103. AHB 166 MHz DDR 333 MHz e Benchmark testusb www linux usb org usbtest testusb c e Test method The target board is connected to the Linux PC via an USB standard A B cable On host side run testusb using following command testusb D proc bus usb bus No dev No t 1 s 4096 c 10 D It used to pass the gadget zero bus id and device id t It used to pass the test type 1 is BulkOUT 2 is BulkIN S block size 4096 8192 16384 32768 65024 c test loop count On target side run gadget zero as a module using make menuconfig to declare it as a module and make modules to build it Then insert the module passing the size of the buffer as a parameter insmod g_zero ko buflen 4096 e Test result The following are the results using following commands Target insmod g zero ko buflen 4096 HOST testusb D proc bus usb bus No dev No t 1 s BlkSize c 10 HOST testusb D proc bus usb bus No dev No t 2 s BlkSize c 10 Table 24 USBD performance results e ES Size dd time maba BulkIN time s ap Mbps Mbps 4 400 0 039872 82 18298555 0 02514 130 3420843 8 800 0 041113 159 4045679 0 043696 149 9816917 16 1600 0 050237 260 9072994 0 062876 208 461098 32 3200 0 100362 261 1984616 0 125675 208 5888204 40 4000 0 125614 260 8626427 0 150206 218 1537355 80 8000 0 238237 275 087413 0 305275 214 6785685 76 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers
104. C CTL SRC WIDTH width DWC CTL DEST ADDR INC The default DMA driver ctl configuration for memset transfers is a 166 245 Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Accelerator engine device drivers DWC CTL USER MODE DWC CTL NON BUFFERABLE DWC CTL NON CACHEABLE DWC CTL DEST BURST BURST 8 DWC CTL SRC BURST BURST 8 DWC CTL DEST WIDTH width DWC CTL SRC WIDTH width DWC CTL DEST ADDR INC DWC CTL SRC ADDR INC The default DMA driver cfg configuration for memset and memory to memory transfers is DWC CFG FLOW CTRL DMA MEMORY TO MEMORY DMA transfer preparation Before requesting a DMA transfer you should increment the usage count of channel per CPU using the following function call static inline void dma chan get struct dma chan chan This is important for multiprocessor systems This function keeps note of the channel used per CPU There are three different types of transfers Memory to memory Memory to memory or memopy transfers can be prepared using two different routines The first routine is exported from the DMA framework It first synchronizes source memory between RAM and cache then prepares the transfer and finally starts the transfer On completion of DMA transfer it does not call any client driver callback It can work with either the default configuration of the DMA driver or a configuration provided by the client if the slave point
105. EAr600 Ethernet evaluation results iles 52 Menuconfig options llli m rh 54 Other optiohs AA 55 Menuconfig options lisse rh rh 60 USB host configuration in SPEAr res 61 USB Host device performance results eres 66 USB host configurations 1 0 0 0 00 ccc rn 67 Linux gadget endpoint APIS 0 00 ee n 74 USB device control APIS hrs 75 USBD performance results rn 76 Linux kernel configuration lies RI III 77 I2C at clock speed 100 0 hr 85 I2C at clock speed 400 0 85 I2C configuration options cts 86 Section of active CSx signal by GPIO7 and GPI06 0a 87 SPI driver configuration options ee 92 SDIO configuration options 0 0 ae 98 IOCTL requests for serial ports llle 101 Control signal constants liliis hes 102 UART menuconfig kernel options llle I 104 CAN menuconfig kernel options llli 110 Menuconfig options 00 hne 122 Results on SPEAr600 rh 136 Results on SPEAr600 sehr 137 NAND Flash driver configuration options lille 138 Supported transactions llle rens 139 Results on SPEAr600 iussulssssessesee ehh 149 Serial NOR menuconfig options llli 150 JPEG driver configuration options eh 162 DMA device performance results c eet eee 172 DMA configuration options 0 0 RII I t 17
106. EEPROM protocol driver SPIDEV protocol driver Kernel space Linux SPI framework SPI controller driver SSP controller ARM Prime cell PL 022 Hardware 4 6 3 SPI framework in Linux The Linux SPI Framework defines two types of SPI drivers in Linux see Figure 22 e Controller drivers these drivers configure SPI controllers Their interface can be used for configuring the controller and transfer data over the SPI bus They may or may not use DMA for data transfer with the slave device The Linux SPI framework uses controller drivers for all its SPI related operations You can find them at drivers spi spr ssp pl022 e Protocol Slave drivers These drivers pass messages through the controller driver to communicate with a slave device on the other side of a SPI link They are present above the SPI kernel framework and they provide interface to the user applications present in the user space Currently two sample protocol drivers are present in the LSP drivers spi folder e EEPROM protocol driver This driver uses the SPI framework to communicate with a M25P40 EEPROM chip present on the SPEAr board You can access it by opening reading and writing the following node sys bus spi drivers eeprom spi3 1 m25 e General char interface driver spidev This driver provides a char dev interface to the SPI controller To access it use the following calls Open Read Write and locti Note For a new interface you have t
107. ER DMA TX FC RX FC VF m PHY MAC VF CSR c SGMII E DMA OMR AHB CSR REGS N SLAVE gt lt m VF an G MII GMAC MTL GMAC DMA GMAC AHB The GMAC UNIV supports any one or a combination of the following PHY interfaces e Gigabit media independent interface GMII media independent interface MII default e Serial GMII SGMII Apart from the above the following hardware features are available and supported by the software e Promiscuous mode e Check Sum offload for received IP and TCP UDP packets e Dualbuffer ring implicit chaining being used for handling DMA descriptors This option allows a maximum of 4 KB of packets to be handled by a single DMA descriptor for SPEAr600 and 16 KB of packets handled by a single DMA descriptor for SPEAr300 e Magic packet detection support for waking up from sleep 4 1 2 Software overview The GMAC Ethernet driver sits on top of the GMAC controller and interfaces with the Linux TCP IP stack through the standard Linux network interface 44 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers Figure 8 GMAC Ethernet software architecture User space ETE Application Socket API TCP IP stack Kernel space Netif I F GMAC Ethernet driver Hardware GMAC controller C7 Eth Phy GMII MII
108. Example To specify the 5th byte of the OOB data associated with the NAND flash page at 0x1000 in the device you would pass address 0x1005 The NAND device driver populates the struct mtd info to MTD layer by calling the following routines ifdef CONFIG MTD PARTITIONS err add mtd partitions amp mtd v mtd parts mtd parts nb a Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Non volatile memory device drivers else err add mtd device amp mtd endif The hardware control function provides access to the control pins ALE CLE of the NAND chip Port address is assigned as per signal type static void spear nand hwcontrol struct mtd info mtd int cmd unsigned int ctrl struct nand chip this mtd gt priv if ctrl amp NAND_CTRL_CHANGE if ctrl amp NAND CLE this gt IO_ADDR_R void iomem SPEAR START NAND FLASH CMD this gt IO_ADDR_W void iomem SPEAR START NAND FLASH CMD else if ctrl amp NAND ALE this gt IO_ADDR_R void iomem SPEAR START NAND FLASH ADDR this gt IO_ADDR_W void iomem SPEAR START NAND FLASH ADDR else this IO ADDR R void _ iomem SPEAR START NAND FLASH ADDR this gt IO_ADDR_W void iomem SPEAR START NAND FLASH ADDR if cmd NAND CMD NONE writeb cmd this IO ADDR W How to support a new NAND Flash In case of anew NAND Flash chip the following needs to be checked in the devi
109. FIG MII Generic media independent interface provided by kernel CONFIG ETH SPEAR SYN This option is used to enable the GMAC driver support CONFIG ETH SPEAR SYN Y Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers Other miscellaneous options Table 17 Other options Configuration option Comment JUMBO frame size Can be configured by setting ifconfig ethO mtu size Checksum offloading is used to relieve the kernel and thus the CPU from the burden of calculating transport CRC OFFLOAD PDU checksums TCP and UDP checksums when the SPEAr MAC hardware can perform these calculations itself Setup the number of DMA descriptors being used in No of receive transmit descriptors reception and transmission The default has been set to 32 for both reception and transmission This option enables the GMAC to strip the PAD FCS on ETH SPEAR CRC STRIP the incoming frames only when the length of the frame is less than or equal to 1500 bytes Ethtool is used for querying the settings of an Ethernet Ethtool a device and changing them 4 2 MACB MAC block driver MACB is a 10M 100M Ethernet controller with an SMII Serial MII interface to an external PHY This section describes the driver for MACB Ethernet controller embedded in SPEAr The IP is provided by Cadence 4 2 1 Hardware overview The MACB module implements a 10 100 Ethernet MAC compatible with the IEEE 802 3
110. Figure 25 The interface between UART and RS 232 DSR UART RS 232 APB Interface APB 4 8 2 Software overview UART drivers service another kernel layer the TTY layer I O system calls start their journey above top level line disciplines and finally ripple down to UART drivers through the TTY layer The data flow between the user space and the serial device driver therefore is mediated by the TTY layer that implements functionalities that are common to all TTY type devices ky Doc ID 16604 Rev 2 99 245 www BDTIC com ST Communication device drivers UM0851 Note 4 8 3 100 245 Figure 26 UART software system architecture User space Application Console driver Linux TTY layer Kernel space UART driver Hardware UART hardware ARM PLO11 There are different types of TTY drivers console amp serial port The console driver is used at two different places in Linux Firstly at boot time it is used before the initialization of the serial TTY framework as it takes some time for the serial TTY framework to initialize during Linux boot up Secondly after Linux boot up the console device sits in the lowest levels of Linux in order to bring critical information out of the system as soon as possible It is not involved in all the complexity of TTY management The serial ports are named ityS0 ttyS1 etc and usually correspond respectively to COM1 COM2 etc For each such serial port there is a special file in the
111. Flash 0 2047 2112 4159 4224 2048 bytes page 64 byte OOB 012 3 4 5 6 789 ABCNE TF oxoo Bf x ecc xIxIx ixIxIxIxIxIxi x x ox10 X X ECC XIXIXIX x x x x xxx 64 byte OOB for x8 NAND Flash o0 x x i X x x x x x xIxixixix if OOB 0 I OxFF block is NOT valid oso X X ECC XIXIXIXIXIXIXIX X x x 012 3 4 5 6 789 ABCNE TF oo BENE Ecc xIxixixixixixixixix x Od0 X X ECC XIXIXIXIXIXIXIXIXIX X 64 byte OOB for x16 NAND Flash ooo Kh BEN x Ix xixixixixixixixix if OOB 0 I OxFFFF block is NOT valid ox30 x x ecc xixixixixixixixix x x Bad block table BBT NAND memory sometimes gets shipped with blocks that are already bad The vendor just marks those blocks as bad thus resulting in higher yield and lower per unit cost Doc ID 16604 Rev 2 129 245 www BDTIC com ST Non volatile memory device drivers UM0851 The Flash contains four kinds of blocks 16 KBytes e Factory default bad blocks Usually NAND vendors mark the 5th OOB byte as non OxFF in the first and or second page in blocks that are bad for the 512 page size NAND Flash e Worn out bad blocks e Good blocks e Thefirst block this block is guaranteed not to require error correction up to 1000 writes This is needed because the initial boot code cannot do ECC NAND Flash also guarantees that a minimum of 9896 of the blocks are good Since the
112. JPEG Codec PLL 2 PLL 3 DMA ADC SPI 1 SPI 2 RTC SPI 3 ARM 1 Ethernet Table 62 SPEAr300 modules with DCS feature Module USB 2 0 host 1 GPIO DMA 12C Ethernet MAC UART 1 ARM 1 SUBSYSTEM TIMER 1 TIMER 2 TIMER 3 Flash NAND FSMC PLL 1 CLCD CTRL IRDA PLL 2 PLL 3 USB2 0 Device Flash Serial SMI SPI 1 ADC Internal ROM JPEG Codec ARM 1 RTC e Combining frequency scaling and clock switching techniques DFS DCS In NORMAL state the best active power saving results are obtained by combining both the previously described power management techniques These techniques can be used to reduce the power consumption of the devices while still allowing fast response to critical tasks that can be always be performed at maximum frequency if needed Software overview The section describes the various Power Management systems already present in the Linux kernel that used in SPEAr applications to manage power in an efficient way Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Power management section 10 2 1 Linux power management PM framework The Power Management framework provides the basic framework for system wide power management The framework in Linux is a BIOS less implementation of the existing Standard APM Advanced Power Management model The framework supports the low power state transitions in Suspend To RAM or Standby modes The details of the modes are as follows e Standby mode This state offers mini
113. MAC ARM PLO080 Memories and peripherals DMA framework in Linux The DMA Framework present in Linux provides a simple interface to client drivers wishing to use DMA Clients just register themselves with the DMA framework request DMA channels transfer data on allocated DMA channels and finally get unregistered from the DMA framework unregistering also frees allocated DMA channels To increase the performance of the DMA driver consistency related issues are handled by client drivers They can synchronize data between cache and RAM if source or destination memory is cached If memories are un cached there is no need for synchronization The following paragraphs describe the steps that client driver needs to perform when transferring data using DMA Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Accelerator engine device drivers Client registration A client can register with the framework by using the following call dma async client register amp dma client1 dma clientl is an instance of struct dma client present in include linux dmaengine h struct dma client dma event callback event callback Function ptr for DMA framework purposes Mandatory dma cap mask t cap mask Capability of the DMA Channel to be requested a value of zero corresponds to any capability Mandatory struct dma slave slave Data for preparing slave transfer Must be non NULL if the DMA SLAVE capab
114. ODE DWC CTL NON BUFFERABLE DWC CTL NON CACHEABLE DWC CTL SRC ADDR INC DWC CTL DEST BURST BURST 8 DWC CTL SRC BURST BURST 8 DWC CTL SRC WIDTH WIDTH WORD struct dma_client dma_client event callback dma_event slave amp dma_slave slave static enum dma_state_client dma_event struct dma_client client struct dma_chan chan enum dma state state void dma xfer void f struct dma async tx descriptor tx u32 dma addr dma cap set DMA SLAVE dma client cap mask Details of this function are not provided here It will create a scatter list of 2 nodes sg len create sg sg src buf 100 dma chan get chan Doc ID 16604 Rev 2 a www BDTIC com ST UM0851 Accelerator engine device drivers dma addr dma map single chan device dev void src buf 100 DMA TO DEVICE tx chan device device prep slave sg chan sg sg len DMA TO DEVICE 0 Af itx dma unmap single chan device dev src buf 100 DMA TO DEVICE return ENOMEM tx gt callback skull_callback tx gt callback_param NULL cookie tx gt tx_submit tx if dma_submit_error cookie printk submit error d with src x size 100 bytes n cookie src buf return EAGAIN return 0 static void skull_callback void param s32 status u32 cpu Details of this function are not provided here It will delete scatter list previ
115. ODULE probe eeprom_probe remove _ devexit p eeprom remove E The kind of interface provided to the user applications is slave driver dependent sysfs proc dev etc The struct spi device is passed to the slave driver when the probe function of the slave is called from the SPI framework after the device registration You must save the structrure in the slave driver and use it for any communication with the SPI framework The definition of this structure is struct spi device struct device dev Doc ID 16604 Rev 2 a www BDTIC com ST UM0851 Communication device drivers struct spi master master u32 max speed hz u8 chip select u8 mode u8 bits per word int itd void controller state void controller data const char modalias NG Configuring the SPI controller settings To configure the SPI controller you can use the spi setup function provided by the SPI framework Slave developers can change the previously saved struct spi device with the new SPI configuration like bits per word max speed hz mode spi is device whose settings are being modified static inline int spi setup struct spi device spi Writing data To send data over the SPI bus you can use the spi write function provided by the SPI framework spi device to which data will be written buf data buffer len data buffer size static inline int spi write struct spi device spi const u8
116. ONFIG amp chan config On success zero is returned otherwise 1 is returned and errno is set appropriately Kernel level spear adc get chan configure dev chan config On success zero is returned otherwise negative standard kernel errors are returned In the function calls chan config is an instance of the previously defined struct adc chan config Close put channel The channel must be freed after you have finished using it to convert data for the moment This is done using the following call User level close fd On success zero is returned otherwise 1 is returned and errno is set appropriately Kernel level spear adc chan put dev ADC CHANNELO On success zero is returned otherwise negative standard kernel errors are returned Doc ID 16604 Rev 2 189 245 www BDTIC com ST Human interface device HID drivers UM0851 7 3 4 7 3 5 7 3 6 7 3 7 7 3 8 7 3 9 190 245 Known issues or limitations There are some known issues with the current hardware or driver e DMA is only available for Channel 0 This is a limitation of ADC Device e In SPEAr300 DMA on ADC channel zero is not working due to a hardware issue ADC device driver performance The performance measurement has been performed using Hardware ARM926EJS 333MHz SPEAr600 and SPEAr300 boards Kernel linux 2 6 27 Configuration options Table 49 ADC configurations options Configuration option Comment CONFIG SPEA
117. OR Flash driver is a application sample based on the EMI driver The parallel NOR Flash driver is a part of the Common Flash Interface driver and provides all necessary functions for a filesystem via the standard Linux MTD interface Figure 36 EMI system software architecture User space Application YAFFS2 JFFS2 Kernel space P Linux MTD layer CFI driver CMO EMI Hardware Pali controller Once U Boot and Linux startup has completed the EMI driver attempts to initialize the bus bandwidth and acknowledge signal functionality of the EMI controller according to the system boot option Its timing is set based on a table in U Boot const struct cust emi para emi timing m28w640hc tap 0x10 tsdp 0x05 tdpw 0x0a Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Non volatile memory device drivers tdpr tdcs Ox0a 0x05 Wo All timing values are expressed in numbers of AHB Cycles For a detailed description please refer to the corresponding SPEAr datasheet and user manual Because the transactions supported by EMI are limited the EMI driver in U Boot also supports functions for handing unalignment When a transaction that EMI can not support occurs it generates an AHB bus error This error causes an external data abort in ARM core and forces the core to enter data abort exception mode It then handles the data abort and parses which instruction are executing and which registers are involved Then i
118. PB frequency with a factor specified in the controller configuration SPEAr support both master and slave sides for the following interfaces e Motorola SPI compatible interface e Texas instruments synchronous serial interface e National Semiconductor Microwire interface In SPEAr3xx although four chip select lines are available only one at a time can be operational The selection of the active one is done using the two GPIO lines 6 and 7 The FSSOUT of SPI controller is multiplexed to the external CSx according to the following table Table 29 Section of active CSx signal by GPIO7 and GPIO6 GPIO 7 GPIO 6 CSx 0 0 CS1 0 1 CS2 1 0 CS3 1 1 CS4 Software overview The SPI framework present in Linux supports only the master side of the Motorola SPI interface User applications can use the interface of the protocol drivers present in Linux Protocol drivers use the standard call provided by the SPI framework present in Linux The SPI controller driver provides interface to the SPI Framework for accessing the SPI controller The SPI controller transfers data through the SPI slave devices memories connected to it according to the configuration provided by the SPI controller driver The following figure presents the SPI software system architecture Doc ID 16604 Rev 2 87 245 www BDTIC com ST Communication device drivers UM0851 Figure 22 SPI driver architecture User space User applications
119. PIO 5 BASIC SUBSYSTEM GPIO 6 BASIC SUBSYSTEM GPIO 7 RAS GPIO 0 RAS GPIO 1 OoOo INI OD oa AJOJN RAS_GPIO_2 RAS GPIO 3 RAS GPIO 4 RAS GPIO 5 RAS GPIO 6 RAS GPIO 7 Table 54 GPIO pin mapping in SPEAr600 BASIC SUBSYSTEM GPIO 0 GPIO pin on SPEAr600 GPIO pin number in Linux BASIC SUBSYSTEM GPIO 1 BASIC_SUBSYSTEM_GPIO_2 BASIC_SUBSYSTEM_GPIO_3 BASIC_SUBSYSTEM_GPIO_4 BASIC_SUBSYSTEM_GPIO_5 BASIC_SUBSYSTEM_GPIO_6 BASIC_SUBSYSTEM_GPIO_7 APPL SUBSYSTEM GPIO 0 APPL SUBSYSTEM GPIO 1 oloo NI OD oa AJOJN APPL_SUBSYSTEM _GPIO_2 o APPL SUBSYSTEM GPIO 3 11 APPL SUBSYSTEM GPIO 4 APPL SUBSYSTEM GPIO 5 APPL SUBSYSTEM GPIO 6 APPL SUBSYSTEM GPIO 7 Doc ID 16604 Rev 2 207 245 www BDTIC com ST Miscellaneous device drivers UM0851 Table 54 GPIO pin mapping in SPEAr600 continued GPIO pin on SPEAr600 GPIO pin number in Linux CPU GPIO 0 16 CPU GPIO 1 17 CPU GPIO 2 18 CPU GPIO 3 19 CPU GPIO 4 20 CPU GPIO 5 21 CPU GPIO 6 22 CPU GPIO 7 23 9 1 2 Software overview GPIO can be accessed from two levels in Linux e From the user level using the sysfs interface e From other kernel Modules The GPIO software system architecture is shown in the following figure Figure 58 GPIO driver architecture
120. Persistent storage commands This section describes the U Boot commands used to access non volatile storage Table 3 Persistent storage U Boot commands I2C NOR NAND Command Behavior Example Oxf8000000 0x10000 erase Erase Flash memory cM erase 1 0 3 flinfo Print Flash memory information i2c md 0x50 0x0 0000 14 15 16 17 18 19 1a 1b 1c i2c I2C subsystem commands pa dedr od mins 43 Ne eR mi iminfo 0xf8000000 Checking Image at 8000000 Image Name XLoader Kamal T ARM Li u Print header information for application Image Type ue iminfo i Kernel Image uncompressed Image Data Size 4472 Bytes 4 4 kB Load Address d2800b00 Entry Point d2800b00 Verifying Checksum OK List all images found in NAND NOR imls Flash d jffs2 0x1 00 0x0 nand NAND command subsystem nand roadeJi fea 011300000 0 0x10000 nboot jffs2 0x1300000 0 0x60000 for the image to boot nboot Boot from NAND device automatically an environment variable autostart is to be set to yes Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Boot loader overview Table 3 Persistent storage U Boot commands I2C NOR NAND continued Command Behavior Example cmp b 0x1300000 0x1600000 cmp Memory compare oz200000 B MenicRE as cp b 0x1300000 0x1600000 P y copy 0x300000 Write MAC address in I2C memory writemac 00 99 88 77 66 55 This command writes 0x55 and OxAA W
121. R ADC ST10 This option enables the ADC driver in Linux This option enables DMA transfers on ADC channel 0 by CONFIG_SPEAR_DMAC_PL080 enabling support for DMA driver CONFIG_SPEAR_ADC_ST10_DEBUG This option enables ADC debug prints References e SPEAr ADC Driver drivers char spr adc st10 c drivers char spr adc st10 h and include linux spr adc st10 usr h LCD panel support SPEAr supports LCD panels of different resolutions Pls refer to Section 8 1 LCD controller CLCD driver for more details USB HID Class Support If needed it is possible to plug to SPEAr USB mice and keyboards which will be accessed through the USB HID class Please refer to the Section 4 3 USB Host for more details Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Audio video drivers 8 8 1 Audio video drivers This section describes all the drivers related to SPEAr audio video devices LCD controller CLCD driver This section describes the driver for the CLCD controller available in SPEAr600 and SPEAr300 Hardware overview SPEAr300 and SPEAr600 have an ARM PrimeCell Color Liquid Crystal Display Controller CLCD that provides all the necessary control signals to interface directly to a variety of color and monochrome LCD panels The CLCD controller fetches the data for display from a framebuffer memory in RAM and transfers it to the CLCD panel using an internal DMA The basic interface of the CLCD co
122. RDONLY open for reading only O WRONLY open for writing only O RDWR open for both reading and writing The perms argument is always zero for the uses of open fd open name flags perms Configure The serial interface is used for changing parameters such as baud rate character size and so on The first thing you need to do is to include the file termios h Here we use the ioclt system calls It takes three arguments IOCTL system call The fd argument specifies the serial port file descriptor The request argument is a constant defined in the lt termios h gt header file and is typically one of the constants listed in Table 4 The 3rd argument depends upon the particular control request but it shall be either an integer or a pointer to a device specific data structure int ioctl int fd int request arg Table 32 IOCTL requests for serial ports Request Description TCGETS Gets the current serial port settings TCSETS Sets the serial port settings immediately TCSETSF Sets the serial port settings after flushing the input and output buffers TCSETSW a after allowing the input and output TCSBRK Sends a break for the given time TCXONC Controls software flow control TCFLSH Flushes the input and or output queue TIOCMGET Returns the state of the MODEM bits TIOCMSET Sets the state of the MODEM bits FIONREAD Returns the number of bytes in the input buffer
123. SED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2010 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky Doc ID 16604 Rev 2 245 245 www BDTIC com ST
124. SPEAr HDLC channel t Driver e port t physical interface abstraction SPEAr HDLC driver specified structure It keeps track of all the HDLC channels running on this interface TDM E1 interfaces may have multiple HDLC channels RS485 interface only has one HDLC channel e channel t logical HDLC channel abstraction SPEAr HDLC driver specified structure Derived from hdlc device structure It contains a pointer to the physical interfaces it belongs to e hdic device common HDLC device defined in the generic HDLC layer derived from net device e net device common network device defined in the Linux network layer 4 10 3 SPEAr HDLC driver interface The SPEAr HDLC driver uses common network device interfaces The generic HDLC layer provides common routines to interact with the Linux network layer The SPEAr HDLC driver calls the generic HDLC layer to register itself and handle any common requests Init HDLC channels When the driver module is loaded spr hdlc add port is called for each physical port to be initialized and registers the corresponding HDLC channels For TDM E1 port multiple HDLC channel is registered The number of HDLC channels is defined in configuration CONFIG SPEAR TDM HDLC CHANNEL NUM For each RS485 port one HDLC channel is registered For every HDLC channel one SPEAr HDLC private structure channel t is created The driver also creates a common HDLC device structure by calling alloc halcdev in Linux generic HDLC layer T
125. Sends an event and changes Remains in same state to IDLE state when touched and sends event again and again The touchscreen driver is probed as input driver during Linux boot up The driver opens the ADC and GPIO channels and starts reading values from the ADC channels by polling in a 100 ms loop The polling interval currently 100 ms of driver is important because it determines the touchscreen response time 50 initial readings are performed to estimate a threshold The touchscreen is considered to be touched or pressed only when the values go above the threshold If the touchscreen is pressed the driver keeps sending coordinates until the touchscreen is untouched or released Touchscreen calibration A CLCD panel touchscreen cannot initially return absolutely correct coordinates it returns values which need to be adjusted according to the CLCD panel dimensions For this reason calibration is required to get the correct coordinates The driver sends the raw un calibrated coordinates The application layer is responsible for performing the calibration which can be done using the tslib standard utility ts calibrate Touchscreen driver interface to input layer In the init function which is called either when the module is loaded or when booting the kernel the touchscreen driver grabs the required resources Then it allocates a new input device structure with input allocate device and sets up input bitfields In
126. TC alarm interrupt This ioctl needs one argument struct rtc time and it can be used to RTG ALM READ get the current RTC alarm parameter This ioctl needs one argument struct rtc time and it can be used to RTC_ALM_SET set the RTC alarm RTC_RD_TIME This ioctl needs one argument struct rtc time and it can be used to get the current RTC time RTC SET TIME This ioctl needs one argument struct rtc time and it can be used to set the current RTC time Read from RTC device This is the standard read function call In the RTC driver the read function is used to wait for the RTC device interrupt When the read function is called the application is locked until an interrupt is generated int fd int ret struct rtc time rtc tm unsigned long data Doc ID 16604 Rev 2 41 245 www BDTIC com ST Platform section UM0851 3 3 3 3 3 4 42 245 fd open dev rtc O RDONLY 0 ret ioctl fd RTC ALM SET amp rtc tm call the read function to wait the Alarm interrupt ret read fd amp data sizeof unsigned long close td s Closing the device The close function is used to disconnect the RTC device with the relevant file descriptor int d fd open dev rtc O RDONLY 0 close fd RTC driver usage e hwclock hwclock is a shell utility for accessing the RTC clock You can use it to display the current time set the hardware clock to a specif
127. U 1500 Metric 1 RX packets 0 errors 0 dropped 0 overruns 0 frame 0 TX packets 0 errors 0 dropped 0 overruns 0 carrier 0 collisions 0 txqueuelen 7 RX bytes 0 0 0 B TX bytes 0 0 0 B If you set SPEAR TDM HDLC channel number to 2 then the first two interfaces hdlcO and hdlc1 are logical HDLC channels on TDM E1 port The other two interfaces hdlc2 and hdlc3 correspond to RS485 HDLC 1 and RS485 HDLC2 Use the correct interface name in the following commands Raw data test To make a raw data test use the hdlctest tool e TDM loopback test loopback TXD and RXD Example setslot hdlc0 tx 0 127 setslot hdlc0 rx 0 127 hdlctest hdlc0 1000 1024 55aa55aa e For E1 application there are only 32 timeslots And TSO in E1 is reserved So only use TS1 to TS31 First remove TSO and TS32 TS32 must have the same assignment as TSO if you use TDM E1 HDLC port as E1 application Example setslot hdic0 tx 0 32 setslot hdic0 rx 0 32 setslot hdlcO tx 1 31 setslot hdic0 rx 1 31 hdlctest hdlcO 1000 1024 55aa55aa dE dk db HH e TDM two port loopback test transmit on hdlcO and receive on hdlc1 Example setslot hdic0 tx 0 63 setslot hdlcO rx 64 127 setslot hdlcl tx 64 127 setslot hdlcl rx 0 63 hdlctest hdlc0O hdlci1 1000 dE db db db Gk e RS485 loopback test Example hdlctest hdlc2 1000 Doc ID 16604 Rev 2 121 245 www BDTIC com ST Communication device drivers UM0851 4 10 10
128. USB Host performance The driver performace was evaluated using the following setup e HostPC Linux Fedora Core11 Processor 1 GHz AMD Athlon 64 bit dual core RAM 1 GB DDR2 RAM 667 MHz Gigabit Ethernet e Target device SPEAr600 CPU 332 MHz AHB 166 MHz DDR 333 MHz e Benchmark testusb www linux usb org usbtest testusb c e Test method The target board is connected to the Linux PC via an USB standard A B cable On host side run testusb using the following command testusb D proc bus usb bus No dev No t 1 s 4096 c 10 D It used to pass the gadget zero bus id and device id t It used to pass the test type 1 is BulkOUT 2 is BulkIN s block size 4096 8192 16384 32768 65024 c test loop count On target side run gadget zero as a module using make menuconfig to declare it as a module and make modules to build it Then insert the module passing the size of the buffer as a parameter insmod g zero ko buflen 4096 e Testresult The following are the results using following commands Target insmod g zero ko buflen 4096 HOST testusb D proc bus usb bus No dev No t 1 s BlkSize c 100 HOST testusb D proc bus usb bus No dev No t 2 s BlkSize c 100 Table 20 USB Host device performance results BlkSize Data Size BulkOUT time BUIKOUT BulkiN time BUIKIN KB KB s aa s throughput ps Mbps 4 400 0 03125 104 8576 0 03125 104 8576 8 800 0 044016 148 8913123 0 034125 192 0468864 16 1
129. X Rx communication e ForTDM applications up to 8 Mbps per Tx Rx channel For E1 applications up to 2 Mbps per Tx Rx channel e ForTDM applications 128 time slots Frame 125us For E1 applications 32 time slots Frame 125us e Supports any time slots banding to any Tx Rx Channel e Data sending sampling time is configurable e Delay between Bit 0 of TSO and SYNC signal is configurable ky Doc ID 16604 Rev 2 111 245 www BDTIC com ST Communication device drivers UM0851 HDLC features e Compliant with ISO IEC13239 e Standard HDLC frame code decode e Tx channel features Automatic Inter Frame Fill IFF generation Ox7E or OxFF Automatic flag generation Selectable CRC generation e Rx channel features Automatic flag detection Programable address recognition Automatic Inter Frame Fill IFF detection 0x7E or OxFF Storing CRC received into external memory is configurable e Exception report RS485 HDLC controller The RS485 HDLC controller supports one signal HDLC channel at a speed up to 3 88 Mbps It has one extra CTS signal for performing collision detection The main features provided by RS485 controller are listed below General IP features e AMBA 2 0 compliant AMBA slave interface for programming the controller AMBA master interface for transferring data between memory and IP e DMA engine included e Support data buffer queue e Support interrupt queue e Miscellaneous interrupt gene
130. _fix_screeninfo These values cannot be altered by the user struct fb fix screeninfo char id 16 Identification string unsigned long smem start Start of frame buffer memory u32 smem len Length of frame buffer memory o gt lg 3 The struct fb cmap specifies the color map which is used to convey the user s definition of colors to the underlying video hardware You can use this structure to define the RGB Red Green and Blue ratio that you desire for different colors Device independent color map information You can get and set the color map using the FBIOGETCMAP and FBIOPUTCMAP ioctls struct fb cmap v32 start First entry u32 len Number of entries 7116 red Red values u16 green Green values 7116 blue Blue values u16 transp Transparency ks Sample User application Using the steps given below you can prepare a simple user application which works over the framebuffer API The program shows three color bands on the screen by operating on dev fbO the framebuffer device node corresponding to the display After opening the framebuffer device node dev fbO the program gets the fixed screen and variable screen information It first deciphers the visible resolutions and the bits per pixel in a hardware independent manner using the framebuffer ioctl FBIOGET VSCREENINFO This interface command obtains the display s variable parameters by operating on
131. a e Static implementation that is the System Suspend To RAM is triggered from user space through sysfs 10 2 2 Linux clock framework The clock framework has been devised to model the hardware clock tree track dependencies maintain usage counts disable clocks when unused by devices propagate changes to the dependents y Doc ID 16604 Rev 2 223 245 www BDTIC com ST Power management section UM0851 Figure 65 SPEAr clock tree p PLL2 CLKPLL2 DDR Aux tp PLI Ly cLKPLLI gt CPU Sys UART BO ma I UCLK12MHZ 30MHz TT OSC H jg gt UCLK30MHZ gt TIMER I UCLK48MHZ qu Mg CLK30MHZ 32 768kHz TI OSC L CLK32KHZ gt RTC The advantages of providing the clock framework in software are as follows Clocks can be managed dynamically at run time Structured approach Hide complexity of internal clock generation amp clock interdependencies Reuse across different SPEAr devices Reuse across different platforms Clock management from multiple cores Using existing OS power management interfaces when possible Clock dependency graph and reference counting 224 245 The clock framework software generates a clock dependency graph internally Dependency links are dynamic and can be reconfigured at run time The clock dependencies are set up by establishing a Parent Child R
132. aengine h for Linux 2 6 27 e SPEAr DMA Driver drivers dma spr dmac pl080 c drivers dma spr dmac pl080 regs h and include linux spr dmac pl080 h ky Doc ID 16604 Rev 2 173 245 www BDTIC com ST Human interface device HID drivers UM0851 7 7 1 174 245 Human interface device HID drivers This section groups all drivers related to SPEAr human interface devices Touchscreen driver Hardware overview There is no dedicated Touchscreen controller in SPEAr Instead a combination of ADC and GPIO functions are used for Touchscreen operation ADC channels 5 and 6 are used to read the X and Y coordinates respectively By pulling GPIO high or low the device driver selects either ADC Channel 5 or 6 Figure 45 Interfacing between CLCD panel and SPEAr ADC channel 5 ADC channel 6 go L SPEAr GPIO pin CLCD panel product specific Software overview The touchscreen device driver reads all the touch related value from the ADC channels and provides all the necessary functions for the application via the standard Linux Input Device Layer Interface The overall touchscreen software system architecture is represented in the Figure 46 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Human interface device HID drivers Figure 46 Touchscreen software architecture User application space X QT GTK Input device la
133. agement 2 eel 59 4 2 5 Cache coherency ens 59 4 2 6 Packet reception 0 0 eren 60 4 2 7 Packet transmission lee 60 4 2 8 MACB driver usage 2 2 ens 60 4 2 9 Kernel configuration options 00 eee eee 60 4 3 USB OD ETSI 61 4 3 1 Hardware overview 0 en 61 4 3 2 USB host API a nee KGG dew eda KN ABR EAE eu Rae gd 62 4 3 3 USB host USAGE 22 scree ui a ced KA yee db xA x Reg RR YANG 62 4 3 4 USB Host performance ees 66 4 3 5 Kernel configuration options A ee 67 4 4 USB Device xa satan aig dees na Sekt Sean p ege Aha aS ceps De 69 4 4 1 Hardware overview sess nn 69 4 4 2 Software overview 1 0 06 re 70 4 4 8 USBD driver interface with Linux gadget layer 71 44 4 Composite device interface else 72 4 4 5 USBD driver performance 2 76 4 4 6 Configuration options rens 77 4 4 7 HeferenCces cus cc eee AA eld fee RS 78 4 5 I2C diet ana na NANG ANNE NAA fede rure ee eee EL 78 4 5 1 Hardware overview 0 78 4 5 2 Software overview er 79 4 5 3 I2C framework inlinux llle II 80 4 5 4 Adding a new I2C client driver 0 0 eee eee 81 4 5 5 l2C driver performance ees 84 4 5 6 Known issues or limitations llle 85 4 5 7 Configuration options rens 86 4 5 8 References rn 86 ky Doc ID 16604 Rev 2 3 245 www BDTIC
134. aits for it to be stopped Finally it calls hdlc close to let the generic HDLC layer finish the device closing int channel_close net_device dev struct channel t ch dev_to_hdlc dev gt priv net_stop_queue dev stop DMA return hdlc_close dev Xmit over HDLC channels channel_xmit is called when there is data ready to be sent out It will append the buffer to the transmit buffer ring And if Tx DMA is not running it will start Tx DMA to transmit the package This function is non blocked It doesn t wait the transmitting to be completed Transmitting status is checked in bottom half of Tx interrupt handler int channel_xmit struct sk_buff skb struct net_device dev struct channel t ch dev to hdlc dev gt priv if Tx buffer ring full return EBUSY Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers Note 4 10 4 append skb to Tx buffer ring if Tx DMA not running START Tx DMA return 0 Attach protocols channel_attach is a function called by the generic HDLC layer when a certain protocol is attached to the HDLC device It requires the device to change the encoding schema and CRC type based on the protocol The function prototype is int channel_xmit struct net_device dev unsigned short encoding unsigned short parity Currently SPEAr HDLC driver does not support changing the encoding schema and CRC
135. and stop the timer void spear timer set load struct spear timer timer int autoreload u16 load void spear timer start struct spear timer timer void spear timer stop struct spear timer timer GPT counter value The 16 bit GPT counter value can be read any time through the following API Please note that in case of an asynchronous operation when the GPT runs on PLL3 and AHB is fed by PLL1 due to different clock domains the value reported by this API may not be valid Please refer to the GPT application note for more details on this This shall return the count value of the timer unsigned int spear timer read counter struct spear timer timer 3 1 3 GPT driver usage q Two of these timers are used by the clock keeping and event generation framework of Linux to maintain Linux time and generation of timer tick They are defined using the GPT APIs to configure program and use the hardware timers For details please refer to arch arm plat spear time c Clock source One of the GPT timers acts as a free running timer used by Linux to maintain the time of day The clock source for Linux is a monotonic increasing timer used by the kernel to get timer value at any time For this it needs to provide a callback to the kernel clocksource read cycles for reading the count value static cycle t clocksource read cycles void return cycle t spear timer read counter clk clksrc tmr struct clocksource clocksource_gpt
136. ardware overview 2 000 cece nes 139 5 2 2 Software overview ne 140 5 3 Serial NOR Flash driver 24 5 245444 eR Re ee a RR RR Ras 143 5 8 1 Hardware overview 0 ees 143 5 3 2 Software overview ene 144 5 3 3 Serial NOR device driver overview aa 146 5 3 4 NOR Flash file system image creation llli 147 5 3 5 Serial NOR device usage eese 147 5 3 6 Serial NOR device driver performance lesus 149 5 3 7 Configuration options eh 150 5 3 8 References nn 151 5 4 USB mass storage support eee 151 5 5 12C and SPI memory device support eee eee eee 151 56 SD MMC memory support 2 2 cise Rr RREERRERPEREET 151 6 Accelerator engine device drivers eee eee 152 6 1 JPEG OVE xs ves p dex uade RAE anea EEEa EA EE ANR RR GREG YS 152 6 1 1 Hardware overview 00 cece nes 152 ky Doc ID 16604 Rev 2 5 245 www BDTIC com ST Contents UM0851 6 1 2 Software overview n 153 6 1 3 JPEG device driver performance a 162 6 1 4 References enn 162 6 2 General purpose DMA DMAC driver a 162 6 2 1 Hardware overview 2 nes 162 6 2 2 Software overview sls 164 6 2 3 DMA device driver performance eee eee 172 6 2 4 Configuration options 0 00 173 6 2 5 References 0 00 nnn 173 7 Huma
137. aseis irq svc The function irq svc saves r0 12 on the SVC mode stack the Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Platform section 3 2 5 kernel stack of the process which was interrupted reads LR and SPSR from a temporary IRQ stack and saves them on the SVC mode stack It increments the preempt count and calls get irqnr and base to find out the IRQ line number The SPEAr architecture provides the get irqnr and base arch arm mach spearxxx include mach entry macro S function to query the interrupt controller to find out which IRQ line raised this interrupt After this irq svc calls asm do IRQY which in turn calls the IRQ handler the interrupt handler that you registered through request irq or a default IRQ handler registered by default during boot time After the completion of these actions the IRQ line for which the interrupt was raised is unmasked and do level irq returns After this interrupt handling is complete irq svc restores the state of the interrupted process So now the IRQ infrastructure is in place and various modules can register their IRQ handlers through request irq When you call request irq the kernel appends your IRQ handler to the list of all the IRQ handlers registered for that particular IRQ line It does not change the exception vector table As described above the Linux implementation for interrupt handling is not a vectored approach hence it does not uti
138. at the end of the chip Use mirrored tables with version numbers e e e e Reserve 4 blocks at the end of the chip User defined tables User defined tables are created by filling out a struct nand bbt descr and storing the pointer in the struct nand chip member bbt td before calling nand scan If a mirror table is necessary a second structure must be created and a pointer to this structure must be stored in bbt md inside the struct nand chip If the bbt md member is set to NULL then only the main table is used and no scan for the mirrored table is performed The struct nand bbt descr is the descriptor for the bad block table marker and the descriptor for the pattern which identifies good and bad blocks The assumption is made that the pattern and the version count are always located in the oob area of the first block struct nand bbt descr int options options for this descriptor int pages the page s where we find the bbt used with option BBT ABSPAGE when bbt is searched then we store the found bbts pages here Its an array and supports up to 8 chips now int offs offset of the pattern in the oob area of the page int veroffs offset of the bbt version counter in the oob are of the page uint8 t version version read from the bbt page during scan int len length of the pattern if 0 no pattern check is performed int maxblocks maximum number of blocks to search for a bbt This number of blocks is reserved at the end of th
139. ata nae as magic number to say that MAC id is present here at offset O and 1 in the chip and stores the MAC address from offset 2 protect Enable or disable Flash write protection protect off 1 0 5 Network commands Table 4 Network U Boot commands Command Behavior Example badi Boot image via network using bootp 0x1600000 uImage P BootP TFTP protocol cdp Perform CDP network configuration Invoke DHCP client to obtain IP boot dhcp parameters Nfs Boot image via network using NFS protocol i Send ICMP echo request to network ping 192 168 1 1 ping host Boot image via network using TFTP tftpboot 0x1300000 uImage tftpboot protocol rbol Boot image via network using P RARP TFTP protocol Write MAC address in I2C memory writemac 00 99 88 77 66 55 This command writes 0x55 and OxAA writemac as magic number to say that MAC id is present here at offset 0 and 1 in the chip and stores the MAC address from offset 2 Doc ID 16604 Rev 2 19 245 www BDTIC com ST Boot loader overview UM0851 Image booting commands Table 5 Image booting U Boot commands Command Behavior Example autoscr 0x1600000 Autoscr Run script from memory Executing script at 01300000 Boot Boot default for example run bootcmd Bootd Boot default for example run bootcmd go 0x1300000 Go Start application at address addr jl Starting application at 0x01300000 Bootm Boo
140. ation YAFFS2 JFFS2 Kernel space Linux MTD layer NAND driver NOR driver Hardware dum FSMC SMI controller Once started the NAND device driver scans for the available NAND chips and if a chip is found and matches to its list of devices the device driver configure it After the initial configuration the NAND Flash information regarding the NAND Flash is exported to the MTD layer and the Flash is ready to be used by the file system 124 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Non volatile memory device drivers The NAND device driver supports various NAND Flash chips All NAND devices are enlisted in drivers mtd nand nand ids c If a new NAND device is added in the system then its details must be entered here Here is a code snippet of nand ids c Chip ID list AA Name ID code pagesize chipsize in MegaByte eraseblock size options struct nand flash dev nand flash ids NAND 1MiB 5V 8 bit 0x6e 256 1 Ox1000 0 NAND 2MiB 5V 8 bit 0x64 256 2 Ox1000 0 NAND 64MiB 1 8V 16 bit 0x46 512 64 0x4000 NAND BUSWIDTH 16 NAND 64MiB 1 8V 8 bit 0xA2 0 64 O LP OPTIONS NAND 64MiB 3 3V 8 bit OxF2 0 64 0 LP OPTIONS NAND 64MiB 1 8V 16 bit 0xB2 0 64 0 LP OPTIONS16 NAND 64MiB 3 3V 16 bit 0xC2 0 64 0 LP_OPTIONS16 NULL 5 1 3 NAND device driver overview 4 This section decribes the Linux MTD framework MTD
141. ave been defined to get the clock rate and clk set rate to set the clock rate Usage CPUfreq user interface The user interface to CPUfreq is through sysfs CPUfreq provides the flexibility to manage CPUs at a per processor level as long as hardware agrees to manage CPUs at that level The interface for each CPU will be under sysfs typically at sys devices system cpu cpuX cpufreq where X ranges from O through N 1 with N being total number of logical CPUs in the system The basic interfaces provided by CPUfreq are cd sys devices system cpu cpu0 cpufreq ls la affected_cpus cpuinfo_cur_freq Current CPU freq cpuinfo_max_freq Max CPU Freq cpuinfo_min_freq Min CPU freq scaling_available_frequencies All available CPU freq scaling_available_governors lists out all the governors supported by the kernel scaling_cur_freq cached value of current frequency from cpufreq subsystem scaling_driver CPU Freq driver used to change the freq scaling governor User assigned governor scaling max freq User Controlled Upper Limit scaling min freq User Controlled Lower Limit To show the available governors you can use Doc ID 16604 Rev 2 235 245 www BDTIC com ST Power management section UM0851 236 245 cat sys devices system cpu cpu0 cpufreg scaling available governors conservative ondemand userspace powersave performance Ondemand governor sampling rate This is measured in microsecond
142. c Device drivers for I2C client devices They are used for reading writing to the slave device 12C client device drivers for EEPROM as an example are provided in the following path Refer to Linux 2 6 27 drivers i2c chips eeprom c I2C dev They allow communication with the user space Usually I2C devices are controlled by a kernel driver But you can also access all devices on an adapter from the user space through the dev interface For this you need to load the module i2c dev Each registered i2c Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers 4 5 4 adapter gets a number counting from 0 You can examine sys class i2c dev to see what number corresponds to which adapter I2C device files are character device files with major device number 89 and a minor device number corresponding to the number assigned as explained above They should be called i2c d i2c 0 i2c 1 i2c 10 All 256 minor device numbers are reserved for i2c Adding a new I2C client driver To add a new client driver you should be familiar with struct i2c driver The struct i2c driver describes an I2C chip driver This structure is defined in the include linux i2c h file Only the following fields are necessary to create a working chip driver set to a descriptive name of the I2C chip driver This value shows up in the sysfs file name created for every I2C chip device char name I2C NAME SIZE
143. ce driver 1 NAND chip should be listed in drivers mtd nand nand ids h 2 NAND chip base address should be defined in platform device of arch arm mach spear600 spear600 c or arch arm mach spear300 spear300 c static struct resource nand_resources 0 Start SPEAR START NAND FLASH MEM end SPEAR START NAND FLASH MEM SPEAR SIZE NAND FLASH MEM 1 flags IORESOURCE MEM 1 Start SPEAR START NAND FLASH CMD end SPEAR START NAND FLASH CMD SPEAR SIZE NAND FLASH CMD 1 flags IORESOURCE MEM 21 Start SPEAR START NAND FLASH ADDR end SPEAR START NAND FLASH ADDR SPEAR SIZE NAND FLASH ADDR 1 flags IORESOURCE MEM 3 NAND chip timings should be correctly programmed in FSMC done in spear nand fsmc setup routine in drivers mtd nand spr nand st c Fills the structure for Timing and other parameter nand ctrl wait on FSMC WAIT ON nand ctrl enable bank FSMC BANK ENABLE nand ctrl mem type FSMC NAND MEM nand ctrl dev width FSMC ACCESS 8 nand ctrl tar 0x04 Address Latch Low to Read Enable Low Doc ID 16604 Rev 2 127 245 www BDTIC com ST Non volatile memory device drivers UM0851 nand ctrl tclr 0x04 Command Latch Low to Read Enable Low Call FSMC API fsmc set nand control bank amp nand ctrl Fills the structure for Timi
144. ce drivers 29 fb 89 i2c 90 mtd 128 ptm 136 pts 180 usb 189 usb device 206 osst 250 usb endpoint 251 C3 252 spear jpeg 254 rtc Block devices 1 ramdisk 31 mtdblock After obtaining the major number of the JPEG device create JPEG nodes using the following commands mknod dev jpegread c major 0 mknod dev jpegwrite c major 1 Here major is major number allocated to JP E Q These user level nodes are used for any further interaction with the JPEG driver The following steps illustrate how to do encoding decoding with JPEG Open JPEG nodes After creating JPEG read and write nodes the application should open them Use the following system call to open JPEG nodes rfd open dev jpegread O_RDWR O SYNC wfd open dev jpegwrite O RDWR O SYNC O_RDWR access permission is used to get read write permissions O_SYNC access permission is used for synchronous I O Any writes on the resulting file descriptor will block the calling process until the data has been physically written to the underlying hardware MMap function used later will give uncached memory if this flag is used otherwise data consistency issues will occur Rfd amp wfd are read and write file descriptors used to further communicate with jpeg nodes JPEG nodes can be opened by only one application at a time thus it can t be shared On success positive file descriptors are returned otherwise on error 1 is re
145. character array n number of bytes to be transferred read int fd char buf int n Closing a serial port Close disassociates a TTY from its underlying device and resets the TTY s device control block When the port is closed for the last time you can do the proper hardware shutdown and free any allocated memory To close the serial port just use the close system call int fd fd file descriptor close fd Application code The test code given below uses the open read iocti and close functions The serial port ttySO is opened and later it receives the data when the read function is called The input and output port baud rate can be also configured in the code by using the cfsetispeed and cfsetospeed functions include lt stdio h gt include lt fcntl h gt include lt termios h gt main int fd char s 10 fd open dev ttys0 O_RDWR 0 Af fd lt 0 return 1 struct termios options Get the current options for the port ioctl fd TCGETS amp options Set the baud rates soar eee eee y cfsetispeed amp options B115200 cfsetospeed amp options B115200 Doc ID 16604 Rev 2 103 245 www BDTIC com ST Communication device drivers UM0851 4 8 4 104 245 Enable the receiver and set local mode options c cflag CLOCAL CREAD Set the new options for the port af ioctl fd TCSETS amp options read fd s 10 close
146. chmark that is used to measure the performance of Ethernet It uses TCP and UDP via BSD sockets It provides tests for both unidirectional throughput and end to end latency The worksheet provides test results for TCP STREAM performance tests At giga speeds Table 15 SPEAr600 Ethernet evaluation results 4000 322 61 235 88 321 35 234 76 382 72 241 383 96 241 76 MTU Checksum offloading disabled Checksum offloading enabled CRC strip off CRC strip on CRC strip off CRC strip on RX RX RX RX speed Tx speed Tx speed Tx speed Tx speed speed speed speed 3500 293 98 228 06 289 91 226 32 352 91 233 95 354 58 232 56 3000 263 75 211 86 260 1 208 12 311 38 217 57 308 92 211 88 2500 223 37 205 03 220 51 203 47 261 86 207 65 257 47 206 32 2000 192 01 174 23 191 38 172 88 225 96 177 46 226 55 175 31 1500 168 3 143 6 170 12 142 41 201 64 146 95 204 48 144 82 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers Table 15 SPEAr600 Ethernet evaluation results Reception baud Throughput for the test case 30 seconds netperf I 30 H 192 168 1 10 at P Linux PC Reception baud Transmission Throughput for the test case run for 30 seconds baud netperf I 30 H 192 168 1 1 at SPEAr Transmission baud Note For the tests conducted above the number of DMA descriptors used for Rx are 64 and for Tx are 128 The speeds shown abo
147. ck and return DMA NAK on the fourth call In addition you must save all the struct dma chan chan parameters passed to event callback chan is a pointer to the DMA channel which is currently allocated to the client During channel removal dma event is called for every DMA channel allocated to the client You must return DMA ACK for the channels you want to free Doc ID 16604 Rev 2 165 245 www BDTIC com ST Accelerator engine device drivers UM0851 DMA transfer configuration There are four types of DMA transfer possible memory set memory to memory peripheral to peripheral and memory to from peripheral The first two can work either with the default configuration of the DMA driver or the configuration provided by client Transfers with peripherals always require the user to pass the configuration Configuration parameters are passed to the DMA driver using the struct dma slave slave pointer present in struct dma client We need to pass address of transmit register in tx reg and receive register in rx reg for DMA SLAVE transfers otherwise this structure must not be filled by user driver Note Address of this slave structure has to be passed to in slave pointer in client structure struct dw dma slave struct dma slave slave Generic information about the slave See below u32 ctl Platform specific value for the CTL register Control information include src dest access width src dest burst size
148. current consumption results that have been obtained for the SPEAr600 and SPEAr300 boards The details of the test setup are as follows OS Linux 2 6 27 running on SPEAr boards Wake up Source Ethernet Magic Packets Test setup The target board was connected to a Host Linux PC which sends in the wake up packets when the system goes into sleep The target was booted up using NFS The current was measured on all the power supplies available on the SPEAr boards a first measurement before moving into suspended state and a second measurement after resuming from suspended state SPEAr600 For the SPEAr600 the following jumpers were replaced one at a time to measure the current source JP 1 for 1 0 V JP 2 for 1 8 V JP 3 for 2 5 V JP 4 for 3 3 V The current measurements indicate significant power savings The table and figures below present the results for SPEAr300 Table 64 SPEAr600 power consumption measurements Jumper settings Current in resumed Current in suspended Decrease in current state mA state mA consumption JP1 1 0 V 288 8 145 49 79 JP2 1 8V 96 2 67 8 29 59 JP3 2 5V 10 5 10 5 0 JP4 3 3 V 16 3 16 3 0 Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Power management section Figure 69 SPEAr600 current consumption chart Current consumed mA Current consumption in resume state Current consumption in suspend state 350
149. currently CONFIG USB DEVICES connected to your USB bus or buses and a file named fproc bus usb xxx yyy for every connected device where xxx is the bus number and yyy the device number Since the USB Host controller supports USB2 0 enable this CONFIG USB EHCI HCD option to configure the Host controller driver EHCI is standard for USB 2 0 high speed host control hardware ky Doc ID 16604 Rev 2 67 245 www BDTIC com ST Communication device drivers UM0851 Note 68 245 Table 24 USB host configurations continued The OHCI is the standard for accessing USB 1 1 Host CONFIG USB OHCI HCD controller hardware Since the USB Host controller hardware for SPEAr follows the OHCI Specification enable this option Enable this option to connect a USB mass storage device to CONFIG USB STORAGE the host USB port The option depends on SCSI support being enabled Enable this option to use a SCSI hard disk a SCSI tape drive a SCSI CD ROM or any other SCSI device under Linux USB CONFIG SOS mass storage devices follow SCSI protocol and hence this option should be enabled over USB mass storage devices This driver supports USB modems and ISDN adapters which CONFIG USB ACM support thecommunication device class abstract control model interface CONFIG NET Required for enabling USB modem support CONFIG USB USBNET Multi purpose USB networking framework This option supports devices conforming to the communicatio
150. d 2 If the bandwidth of the Flash is 8 bits set emi norflash data width to 1 If it is 16 bits set emi norflash data width to 2 If it is 32 bits set emi norflash data width to 4 3 Setemi norflash resource end as NOR FLASH PHYS lt Flash size gt 1 Serial NOR Flash driver The serial NOR Flash is the primary method for booting the system This section describes the controller driver Hardware overview NOR Flash is a non volatile memory which is memory mapped and has a standard memory interface NOR Flash is well suited to use as code storage because of its reliability fast read operations and random access capabilities Because code can be directly executed in place NOR Flash is ideal for storing firmware boot code operating systems and other data that changes infrequently NOR Flash memory has traditionally been used to store relatively small amounts of executable code for embedded computing devices such as PDAs and cell phones The NOR Flash used in SPEAr platform board is a Serial NOR Flash and is driven by a SMI Serial Memory Interface controller Serial Memory Interface SMI acting as an AHB slave interface 32 16 or 8 bit manages the clock data access and status of NOR Flash memory The main features of SMI are e Supports a group of SPI compatible Flash and EEPROM devices e SMI clock signal SMI CLK is generated by SMI using clock provided by the AHB bus e SMI_CLK can be up to 50 MHz in Fast Read mo
151. d ptr size t size enum dma data direction dir The last parameter may be set to DMA FROM DEVICE or DMA TO DEVICE according to whether the cache must be invalidated to read incoming data or flushed to send outcoming data The dma unmap single routine is not present in Linux for ARM Doc ID 16604 Rev 2 59 245 www BDTIC com ST Communication device drivers UM0851 4 2 6 4 2 7 4 2 8 4 2 9 60 245 Packet reception Receiving data from the network is trickier than transmitting it because an sk buff must be allocated and handed off to the upper layers from within an atomic context The mode of packet reception that has been implemented is interrupt driven There is a common interrupt registered for both reception and transmission When the packet is received the interrupt handler queues the packet on to the upper stacks In a heavy traffic environment it may receive thousands of packets per second With that sort of interrupt load the overall performance of the system can suffer As a way of improving the performance the MACB driver uses NAPI functions based on polling When the system has a high speed interface handling heavy traffic there are always more packets to process There is no need to interrupt the processor in such situations If the poll method is able to process all of the available packets within the limits given to it it should re enable receive interrupts call netif rx complete to turn off p
152. d buffer have to be done simultaneously It is recommended to use different threads processes for reading and writing This will speed up encoding decoding process Get JPEG information Once encoding decoding is finished user can read JPEG information JPEG header information and compression tables Use the following system call to get JPEG information ioctl rfd JPEGIOC GET INFO amp jpeg info rfd read node file descriptor JPEGIOC GET INFO jepg info instance of struct jpeg info Ng command to get jpeg information After successful completion of this system call it will contain information of JPEG header and compression tables On success zero is returned otherwise 1 appropriately struct jpeg hdr info is defined below struct jpeg info is returned on error and errno is set struct jpeg hdr hdr jpeg image header char qnt mem QNT MEM SIZE char hmin mem HMIN MEM SIZE char hbase mem HBASE MEM SIZE char hsymb mem HSYMB MEM SIZE char dht mem DHT MEM SIZE char henc mem HENC MEM SIZE P quantization memory Huff min memory Huff base memory Huff symb memory DHT memory Huff enc memory struct jpeg hdr is already defined earlier in section Set JPEG Info This ioctl is mainly useful for DWH decoding with header processing enabled Munmap Once the application is finished with JPEG has been mapped for read and write buffer memory Doc
153. d in the SPEAr family is an ARM PLO61 GPIO SPEAr3xx contains one PL061 instance and SPEAr600 contains four PLO61 instances two local GPIOs in CPU subsystem one GPIO in the application subsystem and one in the basic subsystem The main features of the ARM PLO61 GPIO are e Eight individually programmable input output pins default to input at reset e Programmable interrupt generation capability on any number of pins edge and level interrupts Figure 57 GPIO block diagram AMBA APB interface Register block Mode tol Hardware COMTO control multiplexer interface Enable lines Input gt Ki Kap lt Input output Output EN 1 multiplexer control K Input data Interrupt Interrupt detection control logic The GPIO pin numbers are different in SPEAr3xx and SPEAr600 Refer to Table 53 and Table 54 GPIO pin numbers are different in case of SPEAr3xx and SPEAr600 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Miscellaneous device drivers Table 53 GPIO pin mapping in SPEAr3xx BASIC SUBSYSTEM GPIO 0 GPIO pin on SPEAr3xx GPIO pin number in Linux BASIC SUBSYSTEM GPIO 1 BASIC SUBSYSTEM GPIO 2 BASIC SUBSYSTEM GPIO 3 BASIC SUBSYSTEM GPIO 4 BASIC SUBSYSTEM G
154. d to address present in slave tx reg and if DMA FROM DEVICE then data is transferred to address in sgl flags if you don t want the DMA driver to call dma unmap single for src and dest addresses after completion of transfer then you can pass DMA COMPL SKIP SRC UNMAP or DMA COMPL SKIP DEST UNMAP in flags parameter for both bitwise OR is used dma async tx descriptor It is the descriptor which contains the prepared transfer information It must not be NULL for successful preparation of DMA xfer 168 245 Doc ID 16604 Rev 2 a www BDTIC com ST UM0851 Accelerator engine device drivers struct dma async tx descriptor device prep slave sg struct dma chan chan struct scatterlist sgl unsigned int sg len enum dma data direction direction unsigned long flags It can t be called directly call it using chan pointer tx chan device device prep slave sg chan sgl sg len direction flags Check the Start transfer section below for for details on starting the actual transfer Start transfer Up until this point DMA transfer has been prepared using the previously described routines but actual transfer has not yet started except the framework function call for memcpy Assigning a callback and submitting the dma async tx descriptor for actual transfer can be done as follows tx is struct dma async tx descriptor returned from transfer prepration functions A non negative value of cooki
155. d to interrupt handler upon interrupt void free irq unsigned int irq void dev id Configuration options Table 55 GPIO kernel configuration options Configuration option Comment Selecting this from the architecture code will cause the gpiolib code to always get built in GPIOLIB This enables GPIO support through the generic GPIO library GPIO SYSFS This enables the sysfs interface for GPIOs CONFIG SPEAR GPIO This enables the SPEAr GPIO ARCH REQUIRE GPIOLIB Watchdog WDT driver A Watchdog timer is a hardware device that triggers a system reset if its regularly generated interrupts are not acknowledged The idea behind it is to have an reliable way to bring the system back from the hung state into normal operation Hardware overview SPEAr platform provides a watchdog timer which has a 32 bit down counter with a programmable timeout value On timeout it generates an interrupt and reset signal The Doc ID 16604 Rev 2 211 245 www BDTIC com ST Miscellaneous device drivers UM0851 watchdog is intended to be used to generate a system reset if a software failure or a system hang occurs The main features of the watchdog module are listed below e 32 bit down counter with a programmable timeout interval e Interrupt generation on timeout e Reset signal generation on timeout if the interrupt from the previous timeout remains pending not serviced e Lock register to protect registe
156. de or 20 MHz in Normal mode and it can be controlled by a programmable 7 bits prescaler allowing then 127 different clock frequencies Doc ID 16604 Rev 2 143 245 www BDTIC com ST Non volatile memory device drivers UM0851 5 3 2 144 245 Figure 37 The interface between NOR Flash and SMI controller SMI clock prescaler Data command Bank select Serial NOR SMI data Flash processing and control AMBA AHB Bus Data Status SMI controller Software overview The NOR device driver sits on top of the SMI controller and provides all necessary functions for a file system via the standard Linux MTD interface In the SPEAr platform SMI controller is dedicated to serial NOR Flash only Therefore separate APIs for controlling the SMI are not available The NOR device driver controls the functionality of SMI by directly accessing the SMI registers Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Non volatile memory device drivers q Figure 38 NOR Flash software system architecture User space Application Kernel space Linux MTD layer Hardware controller The NOR device driver scans for the available NOR chips and if a chip is found and matches to its list of device the device driver configures it After initial configuration the information regarding NOR Flash is exported to the MTD layer and the Flash is ready to be used by the file system
157. der output is used for clock in master mode int x Application will fill the x and y value for configuring clock Fout Fout Fin X Y FIN PLL1 Frq 333 Mhz X 1 Y 5 Fout 66 6MHz The value of should be x y 2 and y 256 By getting these values the driver will set clock in miscellaneous register int y see x enum spear tdm clockclock type input clock source selection a Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Audio video drivers input clock source selection enum spear_tdm_clock TDM_CLK_CLKSM 1 slave mode clock coming on CLK pin TDM_CLK_CLKROSC1 It is the internally generated source clock generally 24MHz TDM CLK CLKRSYNT3 Internal clock can be taken from PLL1 or PLL2 TDM_CLK_PLCLK4 External clock source can be taken some external clock source generator i Sync signal generation This API is used to configure the sync signal It specifies the start and end of the signal The first argument is the structure of the sync register and the second argument defines whether the channel used is narrowband or wideband spear_tdm_set_sync struct spear_sync_gen sync u8 pcm_synchro struct spear_sync_gen enum spear sync type sync type used for the generation of sync signal enum spear sync delay delay indicates the sync generation delayed value u8 sync aligned indicates no delay For delay pass sync aligned as 1 1
158. dinfo 1 size 0x08000000 Frequency at which DDR is operating DDR Freq 333 DDR type DDR2 DDRMOBILE DDR Type DDR2 XLoader revision ethaddr 55 66 77 88 99 00 ip addr 192 168 1 10 baudrate 115200 bps XLoader Rev XLoader SPEAr600 help Print online help version Print monitor version Memory commands U Boot offers the possibility to interact with the memory subsystem RAM ROM Flash using a set of basic commands to move data to from memory compare memory locations change memory locations and test memory Table 2 Memory U Boot commands Command Behavior Example baka Print or set address offset for memory base 0x1300000 commands md Memory display md 0x1300000 Mm Memory modify auto incrementing mm 0x1300000 Doc ID 16604 Rev 2 17 245 www BDTIC com ST Boot loader overview UM0851 18 245 Table 2 Memory U Boot commands continued Command Behavior Example mtest Simple RAM test mtest 0x1600000 0x1610000 Oxff Mw Memory write fill mw 1 0x1600000 0x55aa55aa 0x100 nm 0x1600000 01600000 00000000 abcdabcd Nm Memory modify constant address Eco QUUD sbedsbd 2125 sere 01600000 12345678 87654321 Ba M morvcompare cmp b 0x1300000 0x1600000 p y comp 0x200000 cp b 0x1300000 0x1600000 Cp Memory copy R Itest Return true false on integer compare loop Infinite loop on address range loop 0x1300000 0x10000
159. dpoint a Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Communication device drivers Registering to composite device usb composite gadget need to fill following structure static struct usb composite driver zero driver name zero dev amp device desc Strings dev strings bind zero bind callback called on successful registration Following are the APIs for register un register usb composite register amp zero driver usb composite unregister amp zero driver Adding configuration Any composite device can have multiple configurations with multiple interfaces each interface or a group of interface representing a unique function You can use the following API to add a configuration static struct usb configuration sourcesink driver label source sink strings sourcesink strings bind sourcesink bind config callback called during registration to finish other configurations Setup sourcesink setup callback to handle control requests bConfigurationValue 3 bmAttributes USB CONFIG ATT SELFPOWER bMaxPower 1 2 mA minimal I following function registered earlier is called during registration static int init zero bind struct usb composite dev cdev f usb add config cdev amp sourcesink driver Adding function After adding configurations you also need to define functions supported in each configu
160. e Ethernet driver interface has not been made up and is not using the clock There are certain drivers like I2C UART which will only enable the clock while transmitting or receiving the data as they are acting as Master Controllers The other drivers such as 234 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Power management section 10 4 3 Ethernet and USB are asynchronous to data transfers so once the network has been initialized or the USB enumeration is complete the clocks of the respective modules should be on for the modules to function properly The clock framework is mainly used by the drivers in the kernel space This is done to allow the drivers to fetch the clock from the clock dependency tree through the set of kernel interfaces such as clk get clk put clk enable etc To illustrate this a sample from the 12C driver is given below 1 During the initialization probe time the calls are made to the clock framework to get the clock The return value is a handler to manage the clocks related functionality in future dev gt iclk clk get dev dev i2c ick dev gt fclk clk get dev dev i2c fck 2 Prior to the data transfers enable the clock do the transfers and then disable the clock clik enable dev gt iclk cik enable dev fclk DO DATA TRANSFERS clik disable dev fclk clk_disable dev gt iclk Some other kernel interfaces such as clk_get_rate h
161. e Linux source tree the watchdog driver is present in drivers watchdog spr wdt st c Watchdog device driver interface with misc device layer As mentioned the watchdog driver behaves as a character device so you use normal file operations open close ioctl write to access its features For this the driver uses the misc device layer and registers static const struct file operations spear wdt fops owner THIS MODULE write spear wdt write unlocked ioctl spear wdt ioctl open spear wdt open release spear wdt release minor no is standard defined in miscdevice h spear wdt miscdev minor WATCHDOG MINOR spear wdt miscdev name watchdog spear wdt miscdev fops amp spear wdt fops register watchdog driver ret misc register amp spear wdt miscdev Watchdog driver usage The watchdog device driver provides a char device interface dev watchdog to the user You can use standard file operations to open and configure watchdog device The following sections explain how the watchdog device can be used Opening WDT The watchdog timer is enabled as soon as it is opened by the user The usual open call can be used to open the watchdog device char wdt dev dev watchdog int fd Doc ID 16604 Rev 2 213 245 www BDTIC com ST Miscellaneous device drivers UM0851 fd open wdt dev O RDWR if fd 0 printf Error in opening deviceWMn Configuring WDT IOCTL calls
162. e device where the tables are written int reserved block code if non 0 this pattern denotes a reserved rather than bad block in the stored bbt uint8 t pattern pattern to identify bad block table or factory marked good bad blocks can be NULL if len 0 Jay Error correcting code ECC To manage ECC the NAND driver must provide the following functions e enable hwecc this function is called before reading writing to the chip It resets or initializes the hardware ECC generator in this function The function is called with an Doc ID 16604 Rev 2 131 245 www BDTIC com ST Non volatile memory device drivers UM0851 132 245 argument which distinguishes between read and write operations This function must only be provided if hardware ECC is available e calculate ecc this function is called after read write from to the chip It transfers the ECC from the hardware to the buffer e correct data in case of an ECC error this function is called for error detection and correction If the hardware generator matches the default algorithm of the nand ecc software generator then use the correction function provided by nand ecc instead of implementing duplicated code In the SPEAr platform ECC calculation is done by hardware FSMC and ECC correction by software The FSMC hardware in the SPEAr3xx and SPEAr600 platforms generates 3 bytes ECC for 512 bytes page As already stated these 3 bytes are at the 2 3 and
163. e indicates success in starting transfer On error cookie is negative static void dma callback void param f callback function to be called and transfer completion tx gt callback dma_callback tx gt callback_param param cookie tx gt tx_submit tx Transfer completion notification If callback is not assigned before submitting transfer then completion of DMA transfer can be checked by using the following function chan DMA channel cookie transaction identifier to check status of last returns last completed cookie of channel can be passed as NULL used returns last issued cookie of channel can be passed as NULL If transfer is completed then DMA SUCCESS or DMA ERROR is returned else DMA IN PROGRESS is returned static inline enum dma status dma async is tx complete struct dma chan chan dma cookie t cookie dma cookie t last dma cookie t used If callback is assigned then callback is called with the parameter given by the user On completion of transfer you must update the amount of bytes transferred to the framework using the following code cpu get cpu per cpu ptr chan 1local cpu bytes transferred size per cpu ptr chan 10ocal cpu gt memcpy_count put cpu In addition you should decrement the usage count of channel per CPU using the following call static inline void dma chan put struct dma chan chan This lets the framework know the amount of da
164. e low level framebuffer driver The first few methods in struct fb ops are necessary for the functioning of the driver while the remaining are optional ones that provide for graphics acceleration The CLCD device driver fills this structure with all hardware related routines and exports it to framebuffer layer The responsibility of each function is briefly explained within comments struct fb ops struct module owner int fb open struct fb info info int user Driver open int fb release struct fb info info int user Driver close us FF int fb check var struct fb var screeninfo var struct fb info info Sanity check on video parameters int fb set par struct fb info info Configure the video controller registers int fb setcolreg unsigned regno unsigned red unsigned green unsigned blue unsigned transp struct fb info info Create pseudo color palette map int fb blank int blank struct fb info info Blank unblank display st E a FT Accelerated method to fill a rectangle with pixel lines a 194 245 Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Audio video drivers 8 1 4 void fb fillrect struct fb info info const struct fb fillrect rect Accelerated method to copy a rectangular area from one screen region to another void fb copyarea struct fb info info const struct fb copyarea region Ioctl interface to
165. ead to allocate Size should be multiple of page size i e 4096 bytes Maximum size that can be allocated or mapped at once is 4 MB this makes size of each buffer write or read 2 MB Single call to mmap for jpegread jpegwrite node will allocate length amount of memory and will return its base address Now user application should use this memory as two buffers of same size Doc ID 16604 Rev 2 157 245 www BDTIC com ST Accelerator engine device drivers UM0851 On success mmap returns a pointer to the mapped area On error the value MAP FAILED that is void 1 is returned and errno is set appropriately The mmap function asks to map length bytes starting at offset offset from the file specified by the file descriptor fd into memory preferably at address start This start address is a hint only and is usually specified as 0 You can use following parameters to call this function for rfd and wfd mmap 0 size PROT READ PROT WRITE MAP SHARED file desc 0 After completion of one codec operation encoding decoding if you need to encode decode again without closing nodes of jpegread jpegwrite then user is not required to allocate map this memory again Still if user needs to map it again with a different size then you must first unmap any memory that has been already mapped Write source JPEG data After mapping memory for the write buffer you can write input data to write buffers data length le
166. eady in struct mtd info is set to NULL The SPEAr platform can use the device ready functionality by enabling the option CONFIG FSMC WAIT DISABLE in compilation config Obviously this needs hardware connection connection of NAND Flash R B pin to GPIO pin in the SPEAr board as well EMI interface driver Hardware overview The EMI controller provide a simple external memory interface for acessing external NOR Flash memory or FPGA devices using only a few signals This block is designed to perform simple read write operations and does not support burst type operations either on the AHB or on the EMI interface EMI is a generic interface for general data exchange for example with NOR Flash The data exchange flow of the attached device must be broken down into simple operations and should be performed in accordance with the EMI cycles Main features AHB slave interface Multiplexed address and data bus EMI is always master on the EMI bus Performs 32 16 8 bit transfers Can access 6 different peripherals using CS one at a time Supports single transfer with an ACK signal from the external peripheral which is used to terminate the transfer e Supports peripherals which use Byte Lane procedure Prior to any read write operation the Timing and Control registers must be programmed The timing registers are used to time the EMI interface signals with respect to the HCLK cycles There are various registers for extending the EMI in
167. ed speed 10 full duplex mode htool s eth0 autoneg off speed 10 duplex full setup the forced speed 10 half duplex mode htool s eth0 autoneg off speed 10 duplex half e og 8 e sl o e oO ct Doc ID 16604 Rev 2 51 245 www BDTIC com ST Communication device drivers UM0851 4 1 6 52 245 GMAC driver performance The driver performance was evaluated using the following setup Host PC Linux Fedora Core11 Processor 1 GHz AMD Athlon 64 bit dual core RAM 1 GB DDR2 RAM 667 MHz Gigabit Ethernet Target device SPEAr600 CPU 332 MHz AHB 166 MHz DDR 333 MHz Ethernet Traffic Sniffer Ethereal On Linux PC Benchmark netperf netserver http www netperf org netperf Test method The target board is connected to the Linux PC via an Ethernet cross cable A terminal emulator running on the Windows PC connected via the serial port is used to run the Linux image and execute test cases The netserver is run on the Linux test PC and the netperf is run on the target board with the necessary options for different test cases to measure the transmission throughput and vice versa to measure the reception throughput The test method covers the following combination of tests The MTU size varied from 4000 to 1500 bytes and for each set of readings the various combinations for Checksum offloading On Off with CRC stripping on off were tested Test type Netperf is a ben
168. ed with that call The return value of gpio request must be checked On error standard Linux errors are returned else O is returned Free After using a GPIO pin that you previously requested you must free it You can free a GPIO pin by calling the following function Gpio is gpio pin number already requested void gpio free unsigned gpio Passing an invalid GPIO number to gpio_free will fail Set direction After requesting a GPIO pin you must set its direction This can be done using following function Gpio is gpio pin number Value is value to be set 0 or 1 int gpio direction output unsigned gpio int value The return value is zero for success else a negative errno You must check the return value since the get set calls do not return errors and a wrong configuration is possible Setting the direction can fail if the GPIO number is invalid or when that particular GPIO can not be used in that mode Set and get value After the direction of GPIO is set its value can be read or written You can write a value to a GPIO in OUT mode and can read a value from a GPIO in IN mode This can be done using following functions Gpio is gpio pin number Value is value to be set 0 or 1 void gpio set value unsigned gpio int value Gpio is gpio pin number int gpio get value unsigned gpio The values are Boolean zero for low nonzero for high GPIO in interrupt mode GPIO pins can be c
169. efined or architecture specific are assigned to specific interrupts by the architecture either during the boot up or during the device initialization In the SPEAr architecture at boot up time the architecture specific code sets up the handle level irq flow method as the default for all the VIC interrupts This is done in arch arm mach spearxxx irq c Below is a part of the code captured from the SPEAr300 architecture related initialization code for VIC void init spear3xx init irq void f unsigned int i do init irq 1 for i IRQ VIC START i lt IRQ VIC END i set irq chip i amp vic chip set irq handler i handle level irq set irq flags i IRQF VALID IRQF PROBE Chip level hardware encapsulation The chip level hardware descriptor structure structs irq_chip contains all the direct chip relevant functions which can be utilized by the IRQ flow implementations e ack e mask ack optional recommended for performance e mask e unmask e retrigger optional e set type optional e set waker optional These primitives mean exactly what their name says ack means ACK masking means masking of an IRQ line etc It is up to the flow handler s to use these basic units of low level functionality struct irq chip is a hardware interrupt chip descriptor described below struct irq chip const char name unsigned int startup unsigned int irq void shutdown unsigned
170. el to be configured enum adc avg samples avg samples number of average samples unsigned int scan rate rate at which ADC converts data in microseconds int scan rate fixed if 1 configured scan rate should be equal to requested can rate else if 0 configured scan rate can be less than equal to requested scan rate xz The above functions configure an ADC channel if the ADC device is already configured They also initiate the conversion In SINGLE CONVERSION mode the channel must be configured before each conversion In CONTINUOUS CONVERSION mode the ADC channel is configured only once and then multiple read commands may follow The scan rate is common to all ADC channels So changing the scan rate affects all ADC channels In non DMA mode the scan rate is configured to the minimum scan rate requested and already configured by the channel configurations In DMA mode e If DMA is requested and the scan rate of the DMA is lower than the already configured scan rate then the scan rate is configured e Otherwise an error is returned If DMA is already configured and a new non DMA request is made e Ifthe requested scan rate is less than already configured scan rate then an error is returned Otherwise the scan rate is not changed and success is returned This function returns zero on success and 1 on error and errno is set appropriately Read converted data After configuring the ADC channel you can read the c
171. elation between a clock and its derivatives This hierarchy provides makes it easy to track all the clocks that are used in the system Whenever a device needs a clock it sends a request to the clock framework The clock framework iterates through the total clock dependency tree and sees if the parent has been enabled for the clock If not first the parent clock is enabled followed by the child clock Else if the parent clock is already enabled the reference counts for each related clock are incremented The reference count for the clock usage is incremented or decremented depending upon the resource utilization Whenever the clock is enabled the reference count is incremented and it is decremented when the clock is disabled The reference count is tracked recursively in the total tree to capture all the dependencies Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Power management section 10 2 3 CPU frequency framework Clock scaling allows you to change the clock speed of the CPUs on the fly Cpufreq provides a modularized set of interfaces to manage the CPU frequency changes Figure 66 CPU freq kernel architectural blocks User space Power saved CPU speed Governor lt 7 Performance User space Power save OnDemand boi fl CPU FREQ module with proc and sys interfaces SPEAr Arch driver SPEAr architecture arch arm plat spear cpu_spear c Y Clock framework low level clock
172. emory informs about what to do with each timeslot It is a dual port memory connected both to the module and the AHB Switching means that an output timeslot a timeslot played on the DOUT pin contains the data received during the previous frame on an input timeslot a timeslot received in the DIN pin Switching data is stored in a single port Switching Memory without access from AHB Bufferization means that data from DIN pin one to four timeslots is stored in the buffer memory during a programmable number of frames and data from buffer memory is played at the same time The buffer memory is shared between the module and the AHB and split into two banks Up to 16 channels buffers can be stored played from different buffers Using 16 channels of 4 bytes allows 30 ms data storage for each channel as required by VoIP applications The block diagram of the TDM is shown in Figure 54 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Audio video drivers 8 2 2 Figure 54 TDM Cell DIN Switching CLK 4 Switched memory SYNC y data BO DOUT state Switching machine memory c B1 L 53 Ox gt Buffer 5 Lp a Bufferized memory m data BO state uiter interface machine memory q B1 j Action memory 63 The switching feature uses a total of 2048 memory locations each
173. ency else fbp location 0 no Blue fbp location 1 0 no Green fbp location 2 OxFF show Red fbp location 3 0 No transparency H location 1 4 Note The CLCD controller is connected to DDR through port of MPMC DDR controller The priority of the MPMC ports can be tuned by Xloader A low proirity for port of CLCD can cause a slow performance hence resulting in flickering on the CLCD panel Therefore currently Xloader sets the highest priority for the CLCD port 8 1 6 Kernel configuration options Table 51 CLCD configuration options Configuration option Comment This option is used to enable the framebuffer CONFIG FB Driver support This framebuffer device driver is for the ARM PrimeCell PL110 Colour LCD controller CONFIG FB ARMCLCD SAMSUNG LMS700 This option selects the Samsung 7 panel CONFIG FB ARMCLCD SHARP LQO43T1DGO1 This option selects the Sharp 4 3 panel CONFIG FB ARMCLCD This option includes the cfb fillrect function CONFIG FB CFB FILLRECT Ma for generic software rectangle filling Doc ID 16604 Rev 2 197 245 www BDTIC com ST Audio video drivers UM0851 8 2 8 2 1 198 245 Table 51 8 CLCD configuration options continued Configuration option Comment This option includes the cfb copyarea CONFIG FB CFB COPYAREA function for generic software area copying This option
174. entation has the CLCD running on PLL 3 and is not impacted by the change in PLL 1 CPU frequency changes 2 Ethernet DMA transactions to be stopped momentarily when the PLL frequency change is taking place Also the MDIO clock needs to be programmed properly after the frequency change The IP reads the clock rate from the Clock Framework 3 USB Host Device DMA transactions would be suspended and then resumed as done in Ethernet 4 12C Before any transaction takes place I2C driver will fetch the functional clock rate from the clock framework and then program its internal register with the necessary SCL clock values It will also Enable and Disable the i2c clock as per its requirement 5 UART Will always transmit receive post reading the clock rate from the clock framework and hence will not depend directly on the CPU Freq changes It will enable and disable the clocks as per the read write requirements 6 GPT Will setup the events post reading the clock rate from the clock framework and hence will not directly depend on the CPU freq changes The system timer would be running on PLL 3 so as to avoid the changes in PLL affecting the timer interrupts 7 SPI Will run fine as long as minimum clock speed is maintained 8 SMI Will run fine as long as minimum clock speed is maintained 9 FSMC Will run fine as long as minimum clock speed is maintained 10 JPEG No impact 11 WDT No impact 12 DMA Disable the individual channels mo
175. eq ifr data data ioctl sock SIOCDEVASSIGNSLOT amp req close sock Here the first word in data array is direction 1 for TX 0 for Rx The second word is Timeslot number 4 10 6 Application code The application uses standard socket interface to access the HDLC channel The code in Section 4 10 7 Test utilities can be used as a reference Doc ID 16604 Rev 2 119 245 www BDTIC com ST Communication device drivers UM0851 4 10 7 4 10 8 120 245 Test utilities e setslot A utility to assign timeslot for HDLC channel Only useful for TDM E1 port Usage setslot IF DIR SLOT IF hdlcx DIR tx rx for remove SLOT 0 127 Example setslot hdlcO tx 0 TDM E1 ch0 TS 0 gt Chan 0 setslot hdlcl tx 1 2 TDM E1 chl TS 1 gt Chan 1 TDM El ch1 TS 2 gt Chan 1 setslot hdlcO rx 0 2 5 TDM E1 ch0 RS 0 gt Chan 0 TDM E1 ch0 RS 2 gt Chan 0 TDM E1 ch0 RS 3 gt Chan 0 TDM E1 ch0 RS 4 gt Chan 0 TDM E1 ch0 RS 5 gt Chan 0 setslot hdlcl tx 1 2 TDM E1 ch1 Remove Tx TS TDM E1 ch1 Remove Tx TS 2 setslot hdlc0 rx 2 4 TDM E1 ch0 Remove Rx TS 2 TDM E1 ch0 Remove Rx TS 3 TDM E1 ch0 Remove Rx TS 4 e sethdlc A utility to set HDLC mode See sethdlc README for detail information Example sethdlc hdlc0 hale n e h lctest A utility to do HDLC transmitting and receiving test Usage hdlctest hdlcX hdicX hdicY number of
176. er in the client structure is non NULL chan is a pointer to DMA channel allocated to client dest and src are destination and source memory addresses len number of bytes to be copied dma cookie t non negative value of cookie indicates success in preparing and starting transfer On error cookie is negative dma cookie t dma async memcpy buf to buf struct dma chan chan void dest void src size t len For transfer completion notification refer to Transfer completion notification section The second routine is exported from the DMA driver In this routine synchronization issues are expected to be handled by the client driver Firstly you need to prepare transfers then assign any callback if required and then start the actual transfer A transfer is prepared by the following call flags if you don t want the DMA driver to call dma unmap single for src and dest addresses after completion of transfer then you can pass DMA COMPL SKIP SRC UNMAP or DMA COMPL SKIP DEST UNMAP in flags parameter for both bitwise OR is used dma async tx descriptor It is the descriptor which contains the prepared transfer information If must be non NULL for successful prepration of DMA transfer struct dma async tx descriptor device prep dma memcpy struct dma chan chan dma addr t dest dma addr t src size t len unsigned long flags It can t be called directly call it using chan pointer tx chan device d
177. er space application can access the NOR Flash device content using the mtdblock nodes dev mtdblockN and the mtdchar nodes dev midN either in raw mode for example using the dd command or in logical mode by mounting a file system usually JFFS2 and accessing its files through open read write system calls Doc ID 16604 Rev 2 147 245 www BDTIC com ST Non volatile memory device drivers UM0851 Raw mode usage from user space MTD Utils can be used to access NOR Flash via the MTD layer without a file system The MTD project provides a number of helpful tools for handling NOR Flash e flasherase flasheraseall erase and format Flash partitions e flashcp Write filesystem images to NOR Flash NOR Flash does not have bad blocks so normal busy box commands can also be used to access it The random access capability of NOR Flash makes it possible to access any address of NOR Flash from user mode once that address is properly mapped Raw mode usage from kernel space NOR Flash can be directly accessed However MTD calls such as mtd gt read mtd serase and mtd gt write can be used to read erase and write to MTD devices The following code snippet shows an example where 4 bytes are read and written in the same location of the MTD partition number 3 struct mtd info mtd int ret 0 void buffer size_t retlen 0 Get MTD info of 3rd partition mtd get_mtd_device NULL 3 if mtd err Err in get
178. es the events generated in the kernel straight to the program with timestamps The devices are in dev input crw r r 1 root root 13 64 Apr 1 10 49 eventO crw r r 1 root root 13 65 Apr 1 10 50 eventi crw r r 1 root root 13 66 Apr 1 10 50 event2 crw r r 1 root root 13 67 Apr 1 10 50 event3 The device nodes are created in dev input directory with the major number 13 and minor number 64 The device can be opened using the open system call in both blocking and non blocking modes and read using the select system call on the dev input eventX devices which will always get a whole number of input events on a read Their layout is struct input event struct timeval time unsigned short type unsigned short code unsigned int value hi time is the timestamp it returns the time at which the event happened Type is for example EV REL for relative moment REL KEY for a key press or key release More types are defined in include linux input h code is event code for example REL X or KEY BACKSPACE again a complete list is in include linux input h Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Human interface device HID drivers value is the value the event carries Either a relative change for EV REL absolute new value for EV ABS joysticks or O for EV KEY for release 1 for key press and 2 for autorepeat 7 2 5 Configuration options Table 48 Keypad configuration optio
179. es to the kernel via the struct net device data structure The structure fields are initialized to provide the necessary interface The below code is a fairly routine initialization of the struct net device structure it is mostly a matter of storing pointers to our various driver functions struct net device dev dev gt open macb open dev gt stop macb close dev do ioctl macb ioctl dev get stats macb get stats dev hard start xmit macb start xmit dev set multicast list macb set rx mode dev gt dev_addr 0 5 MAC ADDRESS The private data structure use by the driver is struct macb void iomem regs unsigned int rx tail struct dma des rx ring void rx buffers unsigned int tx head tx tail unsigned int lasttx base struct dma desc tx ring struct ring info tx skb spinlock t lock struct platform device pdev struct net device dev struct net device stats stats struct macb stats hw stats dma addr t rx ring dma dma addr t tx ring dma dma addr t rx buffers dma unsigned int rx pending tx pending struct mii bus mii bus struct mii if info mii struct phy device phy dev unsigned int link unsigned int speed unsigned int duplex li PHY framework for SPEAr MACB In the MACB driver there is a top layer drivers net arm macb top c whose function is to scan all the PHY chips and to assign each of them to the corresponding MACB drivers After scanning and ve
180. esigned specifically for automotive applications but now also used in other areas such as industrial automation and medical equipment This section describes the driver for the SPEAr320 CAN controller Hardware overview Available only on SPEAr320 SPEAr320 provides two independent CAN bus interfaces fully compliant to CAN 2 0 protocol specifications both Part A and Part B within its standard customization The main features provided by the CAN IP are listed below Bit rates up to 1 MBit s 32 Message objects Each Message object has its own identifier mask Programmable FIFO mode concatenation of message objects Maskable interrupt Disabled automatic retransmission mode for time triggered CAN applications Programmable loop back mode for self test operation CAN IPs in SPEAr support the following test modes The test mode is entered by setting bit test in the CAN control register to one In test mode the bits Tx1 Tx0 LBack Silent and Basic in the test register are writable e Silent mode nthis mode the IP is able to receive valid data frames and valid remote frames but it sends only recessive bits on the CAN bus and it cannot start a transmission tcan be used to analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits acknowledge bits error frames e Loopback mode In loop back mode the CAN core treats its own transmitted messages as received messages and stores them if
181. ev u32 period spear timer stop clk event tmr clear interrupt spear timer write status clk event tmr GPT STATUS MATCH switch mode case CLOCK EVT MODE PERIODIC calculate period for 10 msec timer program timer for 10 msec tic Enable interrupt spear timer set match clk event tmr 1 Spear timer set load start clk event tmr 1 period break case CLOCK EVT MODE ONESHOT timer to be programmed for one shot the actual programming period to be passed in program next event function break case CLOCK case CLOCK case CLOCK break 3 r MODE UNUSED VT MODE SHUTDOWN IM MODE RESUME o D DO 3 a Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Platform section 3 2 default printk XXX set mode Error WMn break static int clockevent_next_event unsigned long cycles struct clock_event_device clk_event_dev spear_timer_set_load_start clk_event_tmr 0 ul6 cycles return 0 static void __init hrt_clockevent_init void u32 tick_rate clk_event_tmr spear_timer_request_specific 1 BUG ON clk event tmr NULL program other parameters set clock source program pre scaler yf clockevent gpt mult div sc tick rate NSEC PER SEC clockevent gpt shift clockevent gpt max delta ns clockevent delta2ns 0xffff amp clockevent gpt clockevent gpt min delta ns clockevent delta2ns
182. evice prep dma memcpy chan dest src len flags Check the Start transfer section below for for details on starting the actual transfer Doc ID 16604 Rev 2 167 245 www BDTIC com ST Accelerator engine device drivers UM0851 Memory set Memory set is a important feature that is required a number of times The routine is exported from the DMA driver In this routine synchronization issues are expected to be handled by the client driver Firstly you need to prepare transfers then assign any callback if required and then start the actual transfer The routine can work with either the default configuration of the DMA driver or a configuration provided by the client if the slave pointer in the client structure is non NULL A transfer is prepared by the following call chan is a pointer to DMA channel allocated to client dest is destination memory address value is value to be set at dest len number of bytes to be copied flags if you don t want the DMA driver to call dma unmap single for dest address after completion of memset then you can pass DMA COMPL SKIP DEST UNMAP in flags parameter for both bitwise OR is used dma async tx descriptor It is the descriptor which contains the prepared transfer information If must be non NULL for successful prepration of DMA transfer struct dma async tx descriptor spear prep dma memset struct dma chan chan dma addr t dest int value size t len unsigned long
183. ey are distinguished with the help of the following macros e MACH SPEAR600 or ARCH SPEAR600 for SPEAr600 e MACH SPEAR300 or ARCH SPEAR300 for all SPEAr300 platforms including variants BOARD SPEAR300 specific for telecom version of SPEAr300 BOARD SPEAR310 specific for communication version of SPEAr300 BOARD SPEAR320 specific for industrial version of SPEAr300 General purpose timer GPT driver This section describes the driver of the general purpose timer embedded in SPEAr devices A digital general purpose timer is a programmable device with a counter that increments or decrements at a fixed frequency and generates interrupts after a specified time An embedded system makes wide use of timers for different purpose like for generating the system tick which is the basic temporization mechanism of any RTOS or for other fine granularity time measurement mechanisms Doc ID 16604 Rev 2 25 245 www BDTIC com ST Platform section UM0851 3 1 1 Hardware overview SPEAr provides several GPTs acting as APB slaves Each GPT consists of 2 independent channels each one made of a programmable 16 bit counter and a dedicated 8 bit timer clock prescaler The programmable 8 bit prescaler performs a clock division from 1 to 256 Different input frequencies can be defined using SPEAr configuration registers The main features of the GPT module are listed below e Eachtimer module provides two independent channels with separate contr
184. f light in a lamp or just to reduce the power consumption in any type of device connected to the system Pulse Width Modulation is a very efficient technique that is often used for this kind of purpose since it does not waste power for heating resistors like when using a rheostat Instead PWM is a technique based on the modulation of the power duty cycle SPEAr320 contains one PWM hardware block Hardware overview Pulse width modulation PWM is a powerful technique for controlling analog circuits with a microprocessor s digital outputs PWM is a way of digitally encoding analog signal levels Through the use of high resolution counters the duty cycle of a square wave is modulated to encode a specific analog signal level The PWM signal is still digital because at any given instant of time the full DC supply is either fully on or fully off The voltage or current source is supplied to the analog load by means of a repeating series of on and off pulses The on time is the time during which the DC supply is applied to the load and the off time is the period during which supply is switched off Given a sufficient bandwidth any analog value can be encoded with PWM The term duty cycle describes the proportion of on time to the regular interval or period of time a low duty cycle corresponds to low power because the power is off for most of the time Duty cycle is expressed in percent 10096 being fully on Doc ID 16604 Rev 2 215 245 ww
185. family GMAC is hard configured to support only fast Ethernet This section describes the GMAC Ethernet driver Hardware overview Within its high speed HS connection subsystem SPEAr provides a Synopsys s DWC Ether MAC 10 1000 1000 Univ able to transmit and receive data over Ethernet in compliance with the IEEE 802 3 2002 standard The GMAC controller is equipped with a AHB master interface DMA for transferring Ethernet frames to from the system memory and a AHB 32 bit slave interface to access the GMAC subsystem s control amp status registers It supports the following modes e MII media independent interface for 10 100 Mbps operation e GMII interface for gigabit 1000Mbps operation only in SPEAr600 The transmit FIFO TxFIFO buffers the data read from the system memory by the DMA before their transmission by the GMAC core Similarly the receive FIFO RxFIFO stores the Ethernet frames received from the line until they are transferred to the system memory by the DMA These are asynchronous FIFOs as they also transfer data between the application clock and the GMAC line clocks Both FIFOs are implemented in 35 bit wide dual ported RAM TxFIFO is 2 Kbytes deep while RxFIFO is 4 Kbytes deep Doc ID 16604 Rev 2 43 245 www BDTIC com ST Communication device drivers UM0851 Figure 7 GMAC block diagram TX FIFO RX FIFO MEM MEM ZN ZN vn m AHB fw qu 3 MAST
186. ferent from the previous one Input allocate device input report key and input register device are part of the Linux input framework Customizing the keypad driver The keypad controller driver needs some platform data to work correctly This information is present in arch arm mach spear300 spear300 c It includes information about the keymap table which represent the value associated with each of the rows column pair and its size It also says whether repeat key is supported or not The structure for the platform specific data is given below Doc ID 16604 Rev 2 181 245 www BDTIC com ST Human interface device HID drivers UM0851 7 2 4 182 245 static struct spear kp platform data spear kbd data keymap spear keymap keymapsize ARRAY SIZE spear keymap rep z1 li e keymap Pointer to the Keymap table e keymapsize Array size of the Keymap table usually rows x cols e ep Repeat key support 1 if supported Below is the example for the Keymap table static int spear keymap KEY 0 0 KEY ESC KEY O 1 KEY 1 KEY 1 3 KEY 3 KEY 1 4 KEY A KEY 8 8 KEY EQUAL The keymap table is fully customizable and can support a keypad with a generic NxM matrix 9x9 is the maximum matrix size The format is like KEY row col val Keypad usage The keypad driver provides an event interface to the input layer Evdev is the generic input event interface It pass
187. first In first out memory buffers FIFOs to reduce CPU interrupts e Programmable baud rate generator This enables division of the reference clock by 1x16 to 65535 x16 and generates an internal x16 clock The divisor can be a Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers fractional number enabling you to use any clock with a frequency 53 6864 MHz as the reference clock e Standard asynchronous communication bits start stop and parity These are added prior to transmission and removed on reception e Support for direct memory access DMA e Support of the modem control functions CTS DCD DSR RTS DTR and RI e Programmable hardware flow control e Fully programmable serial interface characteristics Data can be 5 6 7 or 8 bits Even odd stick or no parity bit generation and detection 1or2 stop bit generation Baud rate generation dc up to UARTCLK max freq 16 The most common use of the UART is to communicate to a PC serial port using the RS 232 recommended standard 232 protocol RS 232 is a standard electrical interface for serial communications RS 232 actually comes in 3 different flavors A B and C with each one defining a different voltage range for the on and off levels The most commonly used variety is RS 232C which defines a mark on bit as a voltage between 3V and 12V and a space off bit as a voltage between 3V and 12V
188. ftware overview The MACB Ethernet driver sits on top of the MACB controller and interfaces to the Linux TCP IP stack through the standard Linux Network interface The figure below shows the framework of the MACB Ethernet software Figure 12 MACB software layers User space Application Socket API TCP IP stack Kernel space Netif I F MACB Ethernet driver Hardware MACB controller p Eth Phy SMII The related Linux files are e drivers net arm macb top c e drivers net arm spear macb c MACB driver interface Device registration The MACB driver inserts a data structure for each newly detected interface into a global list of network devices Each interface is described by a struct net device item which is defined in linux netdevice h The structure must be allocated dynamically The kernel function provided to perform this allocation is alloc etherdev which has the following prototype struct net device alloc etherdev int sizeof priv Here sizeof priv is the size of the SPEAr MACB driver s private data area Once the net device structure has been initialized the process of registration is complete by passing the structure to register netdev The access to the SPEAr MACB private data is done via standard call provided by kernel Doc ID 16604 Rev 2 57 245 www BDTIC com ST Communication device drivers UM0851 struct macb bp netdev priv dev The MACB driver interfac
189. gine support in menuconfig 2 Compile modules with make modules 3 After linux boot up insmod dmatest ko will start dma memopy transfers on multiple threads 4 Doing rmmod dmatest ko stops all dma mempy transfers and shows its result as pass or fail Note The dmatest ko is a standard module that does not provide any performance evaluation features but only testing capabilites The module has been slightly modified in order to provide performance results Table 44 DMA device performance results Burst Size ME ut um Takan es 1 16 938511 17 88 4 16 205907 81 48 8 16 125076 134 14 16 16 89077 188 35 32 16 89118 188 26 64 16 89075 188 35 128 16 89077 188 35 256 16 89080 188 34 172 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Accelerator engine device drivers Figure 44 DMA speed at different burst size 200 00 180 00 160 00 140 00 120 00 100 00 80 00 60 00 40 00 20 00 0 00 D MA Speed at diff sent bust size Speed in MB ps 1 4 8 16 32 amp 128 25 Burst Size in Bytes 6 2 4 Configuration options Table 45 DMA configuration options Configuration option Comment CONFIG DMA ENGINE This option enables the DMA Engine framework in Linux CONFIG SPEAR DMAC PL080 This option enables the SPEAr DMAC PL080 driver CONFIG DMA DEBUG This option enables DMA debug prints 6 2 5 References e DMA Engine framework in linux drivers dma dmaengine c and include linux dm
190. hat have to be added in the SPEAr architecture code to provide the transitions into the new frequency for the CPU as requested by the CPUfreq framework e init Per CPU Initialization Whenever a new CPU is registered with the device model or after the CPUfreq driver registers itself the per CPU initialization function cpufreq driver init is called The driver provides in the Policy related information to the CPUfreq core This includes the CPU operating min max frequency and information related to the governor that the core should use for switching the frequency The policy related information is captured in the following data structure by the kernel struct cpufreq policy cpumask t cpus CPUs requiring sw coordination cpumask t related cpus CPUs with any coordination unsigned int shared type ANY or ALL affected CPUs should set cpufreq unsigned int cpu cpu nr of registered CPU struct cpufreq_cpuinfo cpuinfo see above unsigned int min in kHz unsigned int max in kHz unsigned int cur in kHz only needed if cpufreq governors are used unsigned int policy see above struct cpufreq governor governor struct work struct update if update policy needs to be called but you re in IRQ context struct cpufreq real policy user policy struct kobject kobj struct completion kobj unregister e Verify When the user decides that a new policy consisting of polic
191. he remaining part of this document describes the composite layer interface For detailed documentation on the gadget framework please refer to http www linux usb org gadget In the Linux source tree the USBD controller driver is present in drivers usb gadget spr udc syn c 4 4 3 USBD driver interface with Linux gadget layer As mentioned above the USB Device controller driver supports Linux gadget framework For this it exports certain device and endpoint specific routines and exports two functions for registering and un registering to the framework device specific operations exported by usbd driver static const struct usb gadget ops spear udc dev ops get frame spear dev get frame wakeup spear dev wakeup set selfpowered spear set selfpowered ky Doc ID 16604 Rev 2 71 245 www BDTIC com ST Communication device drivers UM0851 4 4 4 72 245 ioctl spear ioctl hi endpoint specific operations exported by usbd driver static struct usb ep ops spear udc ep ops enable spear ep enable disable spear ep disable alloc request spear ep alloc request free request spear ep free request queue spear ep queue dequeue spear ep dequeue Set halt spear ep set halt fifo status spear ep fifo status fifo flush spear ep fifo flush hi routine exported by usbd driver for gadgets to register int usb gadget register driver struct usb gadget driver driver
192. hen it associates it with the channel t structure The prototype of alloc hdlcdev is struct net device alloc hdlcdev void priv Driver passes the SPEAR HDLC priavte structure channel t to the priv argument It returns a standard net device structure pointer The access to hdlcdev structure is done via macros struct hdlc dev hdev dev to hdlc dev The access to the SPEAR HDLC private structure is done via casting the priv member of hdlc dev struct channel t ch dev to hdlc dev priv Doc ID 16604 Rev 2 115 245 www BDTIC com ST Communication device drivers UM0851 116 245 Once the net_device structure has been initialized the registration process is completed by passing the structure to register hdlcdev Open HDLC channels channel open is called if the application opens the HDLC channel It resets the DMA buffer ring and starts the DMA engine to begin receiving HDLC frames Then it calls net start queue to enable transmitting packages Finally it calls hdlc open to let Generic HDLC Layer finish the device opening int channel open net device dev f struct channel t ch dev to hdlce dev 5priv reset ring ch start DMA net start queue dev return hdlc open dev Close HDLC channels channel_close is called if the application closes the HDLC channel It first calls net_stop_queue to stop the transmit queue Then it writes the STOP command to the DMA engine and w
193. hold This is same as the up threshold found in the ondemand governor but for the opposite direction For example when set to its default value of 20 it means Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Power management section that if the CPU usage needs to be below 20 between samples to have the frequency decreased For example to set the down threshold to 3096 you would do the following echo 30 5 sys devices system cpu cpu0 cpufreq conservative down threshold sampling rate same as ondemand sampling rate minlmax same as ondemand up threshold same as ondemand ignore nice load same as ondemand Performance governor The CPU runs at maximum frequency regardless of the load echo performance gt sys devices system cpu cpu0 cpufreg scaling governor Powersave governor The CPU runs at a minimum frequency regardless of the load echo powersave gt sys devices system cpu cpu0 cpufreq scaling governor CPUfreq stats about your CPU The CPUfreq module lists stats about your CPU These will help you find out things like the current frequency of your processor or what available frequencies your CPU can scale to e cpuinfo cur freq Show the current frequency of your CPU s You can also find this out by doing a cat proc cpuinfo cat sys devices system cpu cpu0 cpufreq cpuinfo cur freq e cpuinfo max freq Show the maximum frequency your CPU s can scale to cat sys devices system cpu cpu0 cpufreq cpui
194. hown in Figure 41 below ky Doc ID 16604 Rev 2 153 245 www BDTIC com ST Accelerator engine device drivers UM0851 Figure 41 JPEG driver framework User U licati space ser application Linux Char device framework PI SS JPEG controller driver JPEG controller JPEG Codec The JPEG driver exposes two device nodes to the user application jpegread and jpegwrite You can write input data to the jpegwrite node and get output data from the jpegread node You can write read data to from jpeg chunk by chunk This means that you do not need very big buffers for input and output data You can take buffers of small size and write read data to from JPEG again and again The following sections describe usage of JPEG driver in detail Note that the sections are in the sequence in which JPEG driver is required to be programmed Kernel space Hardware DMA controller Using the JPEG codec in Linux To access the JPEG driver specific data types in user applications include linux spr jpeg syn usr h The JPEG device is allocated major number dynamically To obtain the major number of the JPEG device run the following command after board boot up cat proc devices Character devices 1 mem pty ttyp dev vc 0 tty ttys dev tty dev console dev ptmx ves st misc WO ON LU UN ll ib BP BP WD RoR input Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Accelerator engine devi
195. ice s driver is asked to resume e The suspend and resume operations always go together and both are multi phase operations e The SPEAr architecture driver arch arm mach spearxxx pm c registers into the kernel PM framework using the suspend set ops call The arch code provides the function pointers to a set of suspend resume operations to be performed by the SPEAr specific code The data structure used for the this is struct platform suspend ops int valid suspend state t state int begin suspend state t state int prepare void int enter suspend state t state void finish void void end void Below is a section of the code demonstrating the registration into the PM framework from the architecture specific driver static int init spear pm init void suspend pm ops amp spear pm ops The device driver which need to act as wakeup source should set up the wakeup event via following system calls int set irq wake irq state int disable irq wake unsigned int irq refer drivers net arm spr eth syn c for details Clock framework API The Linux 2 6 kernel provides a clock framework to be used by the drivers in the kernel space Doc ID 16604 Rev 2 ky www BDTIC com ST Power management section Figure 68 Clock framework architecture User space User application Kernel device driver clk enable clk disable clk get
196. ides a number of helpful tools to handle NAND Flash e flasherase flasheraseall erase and format FLASH partitions e nandwrite write file system images to NAND FLASH e nanddump dump the contents of a NAND FLASH partitions These tools are aware of the NAND restrictions Please use those tools and avoid unnecessary trouble with errors caused by non NAND aware access methods like copy or cat commands Raw mode usage from kernel space Calls such as mtd gt read mtd gt erase and mtd gt write can be used to read erase and write into MTD devices The following code snippet shows an example where 512 bytes are read and write in the same location of the MTD partition number 4 struct mtd info mtd int ret 0 void buffer size_t retlen 0 Get MTD info of 4th partition mtd get_mtd_device NULL 4 if mtd err Err in get mtd n return Read 512 bytes from partition 4 and store in buffer ret mtd gt read mtd 0 512 amp retlen buffer if ret 0 err Err MTD read d n ret return Write 512 bytes into the partition 4 from the buffer ret mtd gt write mtd 0 512 amp retlen buffer if ret lt 0 err Err MTD write d n ret return Logical mode usage from user space An MTD partition can be mounted using a file system such as JFFS2 or YAFFS and then that partition can be used Commands like cp and rm can be used to write erase in the NAND F
197. ied time set the hardware clock to the system time and set the system time from the hardware clock You can also run hwclock periodically to insert or remove time from the hardware clock in order to compensate for systematic drift where the clock consistently gains or loses time at a certain rate if left to run Example hwclock set date 9 22 96 16 45 05 e rtcwake rtcwakeup is a shell utility which can be used to program RTC for the next alarm interrupt It accepts an argument in seconds which is the programmed alarm time Example rtcwake s 10 Configuration options Table 14 RTC menuconfig kernel options Configuration option Comment CONFIG RTC This option enables the RTC driver References e Refer linux 2 6 27 Documentation timers for the time keeping and tick generation architecture of Linux Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers 4 4 1 Communication device drivers All the devices in the SPEAr embedded MPU family provide a rich set connectivity functions and have embedded controllers for various low speed and high speed standard buses This section describes all the communication oriented SPEAr drivers GMAC Ethernet driver Ethernet is a family of standard technologies widely used in local area networks LAN All SPEAr devices have an embedded GMAC Ethernet controller While SPEAr600 supports gigabit Ethernet operations the SPEAr3xx
198. ighest priority requesting interrupt source The following table shows the differences between the hardware features for SPEAr600 and SPEAr300 Table 11 Differences between SPEAr600 and SPEAr300 SPEAr600 SPEAr300 Two daisy chained ARM PrimeCells One ARM PrimeCell A total of 64 interrupt lines are available for A total of 32 interrupt lines are available for the each CPU from its two daisy chained ICs CPU from the ARM PrimeCell The main features of the VIC are listed below e Generation of both fast interrupt request FIQ and interrupt request IRQ according to ARM system operation IRQ is used for general interrupts whereas FIQ is intended for fast low latency interrupt handling In particular using a single FIQ source at a time provides interrupt latency reduction because the ISR can be directly executed without determining the source of the interrupt e Support for 16 vectored interrupts IRQ only Each vectored interrupt block receives the IRQ from the interrupt request logic block and generates a vectored interrupt Each vectored interrupt is associated with the 32 bit address of the interrupt service routine to be executed e Hardware interrupt priority where FIQ interrupt has the highest priority followed by vectored IRQs from vector O to vector 15 and then non vectored IRQs with the lowest priority e Interrupt masking e Interrupt request status and raw interrupt status prior to ma
199. ility is requested Optional struct list head global node list head for global dma client list Not for user driver hi CAP can be one of DMA MEMCPY memory to memory DMA MEMSET memory to memory DMA SLAVE peripheral to peripheral or memory to from peripheral Prototype of this event callback Static enum dma state client dma event struct dma client client struct dma chan chan enum dma state state cap mask can be set using following function dma cap set CAP dma client1 cap mask After registering the client you must request the DMA channels for transferring data This can be done using following call dma async client chan request amp dma client1 The DMA framework calls the dma event function twice once for channel allocation and once for channel removal The value of enum dma state state is e DMA RESOURCE AVAILABLE during channel allocation and e DMA RESOURCE REMOVED during channel removal You have to check the value of the state variable in dma event to determine the cause of the function call During channel allocation dma event is called for every free DMA channel available that satisfies the capability requested by the client This callback is called until you return DMA NAK from the dma event function Suppose there are 8 DMA channels available and you need only three of them then you must return DMA ACK on the first three calls to event callba
200. ime The technique requires a change in the CPU frequency which is done by changing the PLL 1 values programmed in the PLL1 FRQ register Offset OxOC in the Misc register space e Dynamic clock switching DCS Dynamic Clock switching is a power management technique for reducing the active power consumption of a device Unlike DFS which changes the frequency of all Doc ID 16604 Rev 2 221 245 www BDTIC com ST Power management section UM0851 10 2 222 245 modules driven by the CLK PLL1 signal DCS can completely switch OFF the clock of an unused module and quickly switch it ON again when it is required With this technique the processor or system can run at maximum frequency and achieve its maximum performance For complete flexibility DCS is fully software controllable via the PERIP1 CLK ENB register in the Miscellaneous register address space DCS is useful when a real time application is waiting for an event The system can switch OFF the clock to modules that are not used and enable them with a low latency when needed Modules that support this feature are shown in the tables below Table 61 SPEAr600 modules with DCS feature Module USB 2 0 host 1 GPIO 3 GPIO 4 12C aa 2 For luARTA4 UART 2 TIMER 1 TIMER 2 TIMER 3 TIMER 4 TIMER 5 CLCD CTRL IRDA ARM 1 SUBSYSTEM ARM 2 SUBSYTEM USB2 0 Device Flash Serial SMI Flash NAND FSMC PLL 1 Internal ROM
201. includes the cfb imageblit GONFISCEBCDFB IMAGEBLIT function for generic software image blitting References e linux 2 6 27 Documentation fb framebuffer txt e linux 2 6 27 Documentation fb internals txt TDM driver This driver controls the TDM hardware block which is present in SPEAr300 only Hardware overview Time division multiplexing TDM is a type of digital or rarely analog multiplexing in which two or more signals or bit streams are transferred apparently simultaneously as sub channels in one communication channel but are physically taking turns on the channel The time domain is divided into several recurrent timeslots of fixed length one for each sub channel A sample byte or data block of sub channel 1 is transmitted during timeslot 1 sub channel 2 during timeslot 2 etc One TDM frame consists of one timeslot per sub channel After the last sub channel the cycle starts all over again with a new frame starting with the second sample byte or data block from sub channel 1 etc The TDM block includes the switching and bufferization functions of the Telecom IP The external TDM port supports synchronous data transfer Each frame has a programmable length and can support up to 1024 timeslots in full duplex Data is synchronized by the bit clock and a frame synchronization delimits frames that contain a programmable number of timeslots Each timeslot 8 bit data can be used for switching or bufferization Action m
202. ing Spear tdm bfr get struct spear ts ts struct spear ts u8 endianess endianness of the device little ending big endian int ts index timeslot number for which bufferization switching takes place int bfr index represents channel number for bufferization Valid values are from 0 15 struct spear ts ts sw void _ iomem tio base act mem action memory base address tdm base address action memory base address int bfr dir Direction for the bufferization IN OUT BOTH ul6 bfr_active field value 1 shows bufferization is start 0 means bufferization is stopped int status Doc ID 16604 Rev 2 a www BDTIC com ST UM0851 Audio video drivers struct list head rx list List for received request struct list head tx list List for transmit request li TDM switching start This API is used to activate TDM switching spear ts timeslot structure as explained above pcm synchro indicate whether the channel used is narrowband wideband Inside buffer bank memory pointer increases differently for each frame according to the kind of frame Frame types are TDM NARROWBAND COMPANDED Companded 8 bit samples the pointer will progress by 1 byte at each frame TDM NARRORBAND LINEAR Linear 16 bits samples the pointer will progress by 2 bytes at each frame The two bytes will be in consecutive timeslots TDM WIDEBAND COMPANDED the poi
203. ing User Space processes elapsed 0 00 seconds done Freezing remaining freezable tasks elapsed 0 00 seconds done Suspending Console s use no console suspend to debug The system comes out of sleep mode either through the Ethernet Wake or RTC alarm or through GPIO This has been tested using the following setups Wake up through Ethernet Connect the SPEAR board on the network to Linux PC via a cross cable Setup the system IP address for SPEAR ifconfig eth0 192 168 1 11 Put the system in sleep using the suspend command Now from a distant PC send across the wakeup command ether wake MAC Address of SPEAR The SPEAR board comes out of sleep and gives the following debug messages Restarting Tasks Done Wake up through RTC Set Up the RTC alarm as the wakeup event from the application space The command below sets the wakeup event after 10 seconds rtc wake s 10 Now Put the system in sleep mode and the system wakes up in 10 seconds The debug prints are same as the ones obtained for the Ethernet The SPEAR board comes out of sleep and gives the following debug messages Restarting Tasks Done 10 4 2 Usage clock framework The clock dependency tree can be viewed from user space by typing in the following command Doc ID 16604 Rev 2 233 245 www BDTIC com ST Power management section UM0851 S cat proc spear clocks irda fck 0 166000000 0 gmac fck 0 166000000 1 smi
204. int eeprom attach adapter struct i2c adapter adapter t return i2c probe adapter amp addr data eeprom detect The i2c probe function probes the I2C adapter looking for the different addresses specified in the struct addr data If a device is found the eeprom detect function is called The addr data macro is defined in the include linux i2c h file It sets up a static variable called addr data based on the number of different types of chips that this driver supports and the addresses at which these chips typically are present It then provides the ability to override these values by using module parameters static struct i2c client address data addr data normal i2c normal i2c probe probe ignore ignore forces forces normal i2c An I2C chip driver provide the variables normal i2c It is an array of addresses all terminated by special value I2C CLIENT END Usually a specific type of I2C chip shows up in only a limited range of addresses The eeprom c driver defines these variables as static unsigned short normal i2c 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 I2C CLIENT END The normal i2c range variable specifies that we can find this chip device at any I2C address Probe A list of pairs The first value is a bus number adapter id the second is the I2C address These addresses are also probed as if they were in the normal list The i2c probe function will call the eeprom detec
205. int mvolt This is reference voltage applied to ADC It will be useful in calculating output voltage in millivolts Provide mvolt in millivolt enum adc scan ref scan ref reference of scan rate can be internal or external ifdef CONFIG MACH SPEAR300 enum adc resolution resolution resolution of output data can be normal 10 bit or high 17 bit only for SPEAR300 endif unsigned int req clk ADC clock requested in Hz unsigned int avail clk closest clock less than equal to req clk possible in Hz The default configuration done at initialization is struct adc config adc config mode CONTINUOUS CONVERSION volt ref EXTERNAL VOLT mvolt 2500 scan ref INTERNAL SCAN ifdef CONFIG MACH SPEAR300 resolution NORMAL RESOLUTION endif req clk 14000000 ADC channel configuration Channel configuration can be done using the following calls User level ioctl fd ADCIOC CHAN CONFIG amp chan config On success a zero is returned otherwise 1 is returned and errno is set appropriately Doc ID 16604 Rev 2 187 245 www BDTIC com ST Human interface device HID drivers UM0851 Kernel level spear adc chan configure dev amp chan config On success zero is returned otherwise negative standard kernel errors are returned In the function calls chan config is an instance of struct adc chan config struct adc chan config enum adc chan id chan id chann
206. interface thus allows applications to be independent of the specific characteristics of the underlying graphics hardware Applications can run unchanged over diverse types of video hardware if they and the display drivers conform to the framebuffer interface If standard GUIs Graphic User Interface such as MiniGUI MicroWindows are used LCD device drivers must be implemented as Linux framebuffer device drivers in addition to those low level operations which only deal with commands provided by LCD controllers The device is accessed through special device nodes usually located in the dev directory and have names such as dev fbO or dev fb O dev fb1 etc The framebuffer devices are also normal memory devices this means one can read and write their contents You can for example even make a screen snapshot by cat dev fbO gt myfile Application software that uses the frame buffer device e g the X server uses dev fbO by default An alternative frame buffer device can be specified by setting the environment variable FRAMEBUFFER to the path name of a frame buffer device for example export FRAMEBUFFER dev fb1 for sh bash users setenv FRAMEBUFFER dev fb1 for csh users After this the X server will use the second frame buffer export FRAMEBUFFER dev fbl1 for sh bash users ky Doc ID 16604 Rev 2 193 245 www BDTIC com ST Audio video drivers UM0851 setenv FRAMEBUFFER dev fbl for csh users
207. ions for a graphic application via the standard Linux framebuffer interface The CLCD software system architecture is shown in Figure 52 Figure 52 CLCD software architecture User space X GTK QT Framebuffer layer CLCD driver CLCD controller Hardware gt CLCD panel The CLCD device driver for linux is drivers video amba clcd c CLCD device driver interface with framebuffer layer The framebuffer layer is a part of the Linux kernel and should not be confused with the CLCD Panel Data Framebuffer register in the CLCD Controller which is also referred to as frame buffer memory The framebuffer device provides a general abstraction of the graphics hardware and allows the application software to access the graphics hardware through a well defined programming interface so the application software does not need to know anything about the low level part hardware registers Figure 53 briefly illustrates the advantage of the framebuffer layer Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Audio video drivers Figure 53 Framebuffer layer of Linux GUls consoles movie players etc Common Framebuffer API Framebuffer Framebuffer driver 1 driver N Video cards using different graphics controllers Video card 1 Video card N The kernel s frame buffer
208. is option enables MMC block device driver support CONFIG MMC TEST This option enables the MMC test driver It is a development driver that performs a series of reads and writes to a memory card in order to expose certain well known bugs in host controllers CONFIG SPEAR SDIO ARASAN This option enables SPEAr ARASAN SDIO host controller support CONFIG MMC DEBUG This option enables MMC debugging prints 4 7 6 4 8 4 8 1 98 245 References e MMC framework in Linux drivers mmc and include linux mmc for Linux 2 6 27 e SPEAr Arasan SDIO controller driver drivers mmc host spr arasan sdio c and drivers mmc host spr arasan sdio h UART driver Hardware overview The UART universal asynchronous receiver transmitter ARM PLO11 is an advanced microcontroller bus architecture AMBA compliant system on ship SoC peripheral that is developed tested and licensed by ARM It is commonly used to implement serial communication The UART is an AMBA slave module that connects to the advanced peripheral bus APB UART is one of the most commonly used serial interface peripherals It is intended to perform e Serial to parallel conversion on data received from a peripheral device e Parallel to serial conversion on data transmitted to the peripheral device UART PLO11 provides the following features e Programmable use of UART or IrDA SIR input output e Separate 16x8 transmit and 16x12 receive
209. is option is available for SPEAr3xx and SPEAr600 e make FLASH PNOR This option generates an image that supports parallel NOR in place of serial NOR Flash drivers It is applicable only for SPEAr310 1 2 4 U Boot commands You can display the complete list of U Boot commands using the help command spear600 gt help jg alias for help autoscr run script from memory base print or set address offset bdinfo print Board Info structure boot boot default for example run bootcmd bootd boot default for example run bootcmd bootm boot application image from memory bootp boot image via network using BootP TFTP protocol cdp Perform CDP network configuration cmp memory compare coninfo print console devices and information cp memory copy erc32 checksum calculation dhcp invoke DHCP client to obtain IP boot params echo echo args to console erase erase FLASH memory flinfo print FLASH memory information go start application at address addr help print online help i2c I2C sub system iminfo print header information for application image imls list all images found in flash itest return true false on integer compare loadb load binary file over serial line kermit mode loads load S Record file over serial line loady load binary file over serial line ymodem mode loop infinite loop on address range md memory display mm memory modify auto incrementing mtest simple RAM test m
210. isable header processing If disabled only the ECS data are generated decoded Support for restart markers is also provided the codec core recognizes them in the encoded stream when decoding and can optionally insert them when encoding JPEG encoded data streams decoded by the codec core must be compliant with the interchange format syntax specified in ISO IEC 10918 1 JFIF images the de facto standard used to encoded JPEG images are also supported The codec core receives its input data from the FIFO IN buffer This data can be either e Asequence of minimum coded units MCU if the JPGC is used as an encoder from YUV to JPEG The MCU is the minimum number of block that can be encoded or decoded e Astream of entropy coded segments ECS if the JPGC is used as a decoder from JPEG to YUV Conversely output data from the codec core are sent to the FIFO Out buffer as e AnECS stream whenever the JPGC is working as an encoder An MCU sequence whenever the JPGC is working as a decoder The codec controller manages the data flow between the codec core and the FIFO buffers and between the FIFO buffers and the external RAM In order to accomplish the latter task it uses the DMAC to perform fast data transfers The overall JPEG codec block diagram is shown in Figure 40 below Doc ID 16604 Rev 2 ky www BDTIC com ST
211. ith a nice value will not count and thus be ignored in the overall usage calculation This is useful if you are running a CPU intensive calculation that you do not care how long it takes to complete You can nice it and prevent it from taking part in the deciding process of whether to increase your CPU frequency To turn this on do the following echo 1 sys devices system cpu cpu0 cpufreq ondemand ignore nice load Conservative governor Conservative governor CPU frequency is scaled based on the current load of the system It is similar to ondemand The difference is that it gracefully increases and decreases the CPU speed rather than jumping to max speed the moment there is any load on the CPU This would be best used in a battery powered environment Conservative governor configuration options freq step This describes what percentage steps the CPU freq should be increased and decreased smoothly by By default the CPU frequency is increased in 596 chunks of your maximum CPU frequency You can change this value to anywhere between 0 and 100 where 0 effectively locks your CPU at a speed regardless of its load whilst 100 in theory makes it behave identically to the ondemand governor For example to have it step up and down in increments of 1096 you would do the following echo conservative sys devices system cpu cpu0 cpufreq scaling governor echo 10 gt sys devices system cpu cpu0 cpufreq conservative freq step down thres
212. ivers e The SPI controller supports data transfer with EEPROM chip up to 1 MHz in interrupt mode Actually the depth of the Tx FIFO is 8 bytes half words Transmit interrupt comes at half FIFO empty condition Therefore if the speed is 2 MHz then it will take only 16 us to transmit 4 bytes of data However interrupt latency in Linux is around 16 us Therefore by the time the interrupt handler passes more data to the FIFO the older data is completely transmitted The timeout for the EEPROM chip is one clock cycle So the data transfer is terminated at that point e The SPI controller supports data transfer with EEPROM chip up to 21 MHz in DMA mode SPI device driver performance The performance measurement has been performed using e Hardware ARM926EJS 333MHz SPEAr600 and SPEAr300 boards e Kernel linux 2 6 27 Configuration options Table 30 SPI driver configuration options Configuration option Comment CONFIG SPI MASTER This option enables the SPI Master framework in Linux CONFIG SPEAR SSP MASTER PL022 This option enables the SPEAr SPI PLO22 driver CONFIG SPI EEPROM This option enables the EEPROM driver CONFIG SPI SPIDEV This option enables the PIDEV driver This option enables the SPI transfers in DMA CONFIG SPEAR DMAC PL080 mode by enabling support for SPEAr DMAC PLO80 driver CONFIG_SPI_DEBUG This option enables SPI debug prints References e SPI master framework in linux drivers spi
213. lash mount t jffs2 dev mtdblock7 mnt cp tmp song mp3 mnt 1s mnt Song mp3 Before mounting JFFS2 make sure that valid JFFS2 image is already present in the partition to avoid getting a lot of error messages For YAFFS if YAFFS image is present then it is fine otherwise YAFFS can initialize an empty partition structure a 134 245 Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Non volatile memory device drivers 5 1 5 NAND Flash file system image creation YAFFS2 image creation To create the YAFFS2 file system image for 512 byte page NAND Flash use the command 4 mkyaffsimage layout no dir name image name gt To create the YAFFS2 file system image for 2048 byte page NAND Flash use the command mkyaffs2image layout no dir name gt image name gt These commands create the image which contains OOB Hence for a 512 byte page NAND Flash the image size must be divisible by 528 512 byte data 16 byte OOB JFFS2 image creation To create the JFFS2 file system image for a 512 byte page NAND Flash use the command 4 mkfs jffs2 n p 1 s 0x200 e 0x4000 r dir name gt o image name gt To create the JFFS2 file system image for a 2048 byte page NAND Flash use the command mkfs jffs2 n p 1 s 0x800 e 0x20000 r dir name gt o image name gt n don t add a cleanmarker to every eraseblock p add pad bytes to the end of the final erase block
214. lient new client struct eeprom data data int err 0 if data kzalloc sizeof struct eeprom data GFP KERNEL err ENOMEM goto exit new_client amp data gt client memset data gt data Oxff EEPROM SIZE 12c set clientdata new client data new client addr address new client adapter adapter new client driver amp eeprom driver new client flags 0 strlcpy new client name eeprom I2C NAME SIZE First the struct i2c client and a separate local data structure called struct eeprom data are created After the memory is allocated successfully some fields in the struct i2c client are set to point to this specific device and this specific driver Notably the addr adapter and driver variables must be initialized The name of the struct i2c client also must be set in order to be displayed properly in the sysfs tree for this I2C device After the struct i2c client is initialized it must be registered with the I2C core This is done with a call to the i2c attach client function Tell the I2C layer a new client has arrived if err i2c attach client new client goto exit kfree When this function returns with no errors reported the I2C chip device is set up properly in the kernel For creating sysfs tree structure sysfs create bin file amp new client dev kobj amp eeprom attr In the Linux 2 6 kernel all 12C chip devices and adapte
215. lize the vector interrupt capabilities provided by the VIC hardware VIC usage The current implementation in Linux does not allow the exploitation of the complete capabilities of the VIC Within the current capabilities that have been added in the Linux you can use the VIC in the following ways If a driver needs to register a specific interrupt handler the following call is provided by Linux The following functions declared in linux interrupt h implement the interrupt registration interface and is use to register the interrupt handler int request irq unsigned int irq irgreturn t handler unsigned long flags const char dev name void dev id The details of the above fields are as follow irq interrupt number being requested handler pointer to the handler being installed in driver flags Options related to interrupt management dev name string passed here is used in proc interrupts to show the owner of interrupts dev id Pointer used for shared interrupt lines The function below is use to unregister the interrupt handler void free irq unsigned int irq void dev id To check for the interrupt sources being used in the system type in the following command Scat proc interrupts CPUO 16 3903 spear vic gp timer 18 0 spear vic lt NULL gt 20 0 Spear vic spear jpeg Doc ID 16604 Rev 2 37 245 www BDTIC com ST Platform section UM0851 24 244 spear vic uart p101
216. lude the following files to access the internal structures of the MMC framework include linux mmc core h include linux mmc card h include linux mmc host h include linux mmc mmc h e Driver registration The card driver must register itself with the MMC core layer in order to use the core driver layer interface This can be done using the following function drv MMC media driver int mmc register driver struct mmc driver drv struct mmc driver struct device driver drv int probe struct mmc card void remove struct mmc card Doc ID 16604 Rev 2 95 245 www BDTIC com ST Communication device drivers UM0851 int suspend struct mmc card pm message t int resume struct mmc card li During registration the probe function of the card driver will be called and a pointer to card structure will be passed You must use this pointer for any further communication with host driver e Claim host The card driver must claim host in order to do any transfers with the card using the host controller This can be done using the following function call host MMC host to claim It can be found in card structure card gt host void mmc claim host struct mmc host host e Send command This function starts a new MMC command for a host and waits for the command to complete This will not exchange any data with the card Only configuration related commands are sent here It returns any error tha
217. mal though real power savings while providing a very low latency transition back to a working system Devices are suspended and their clocks are gated system and device state are saved in memory but no operating state is lost the CPU Devices retains power so the system easily starts up again where it left off The memory is placed in self refresh mode e Suspend to RAM STR This state offers significant power savings as everything in the system is put into a low power state except for memory which is placed in self refresh mode to retain its contents System and device state is saved and kept in memory All devices are suspended In many cases all peripheral buses lose power when entering STR so devices must be able to handle the transition back to the On state STR requires some minimal boot strapping code to resume the system from STR Note In the current software release LSPv2 3 both Suspend to RAM and Standby modes are treated in an identical way The system goes into sleep mode everything except the wake up sources is suspended Features of the framework e Support for System Sleep model The drivers can enter low power states as part of entering system wide low power states like Suspend To RAM e Role of device drivers The Device Bus and Class drivers collaborate by implementing various role specific suspend and resume methods to cleanly power down hardware and software subsystems then reactivate them without loss of dat
218. mask iraq mask vic mask iraq unmask vic unmask iraq Set wake vic set wake The internals of interrupt handling in ARM The function start kernel is the first C function in Linux executed when the kernel boots up It initializes various subsystems of the kernel including the IRQ system The initialization of IRQ requires that a valid vector table and first level interrupt handlers are in place both of these are architecture specific start kernel calls a function called trap init to setup the exception vector table at location Oxffff0000 The vector table and vector stub code for ARM resides in the arch arm kernel entry armv S file The trap init function copies the vector table at location Oxffff0000 and the exception handlers at OxffffO200 Keep in mind that the addresses mentioned here are virtual After setting up the vector tables start kernel calls init IRQ to set up the kernel IRQ handling infrastructure The function init irq calls init arch irq here the architecture specific code of SPEAR does the basic initializations for the VIC at kernel level The spearxxx init irq function is defined in arch arm mach spearxxx irq c When a IRQ is raised ARM stops what it is processing assuming it is not processing a FIQ disables further IRQs puts CPSR in SPSR puts current PC to LR and switches to IRQ mode Then it refers to the vector table and jumps to the exception handler which in ourc
219. mentarily when the PLL frequency change over takes place and then resume them as soon as PLL is locked Make sure that the data present in FIFO s have been flushed The user manual provides the details for handling the same 13 ADC Driver would reprogram its internal registers based on the new clock rate every time by calling into clk get rate 14 DDR If the DDR is running on PLL 2 then there is no impact of the PLL 1 frequency change but if the DDR is running on PLL 1 then the DDR should be put in Self Refresh Mode and then the PLL 1 frequency would be changed and then the DDR would be moved to normal mode In the current implementation DDR should be running on PLL 2 only Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Power management section 10 4 Usage and performance 10 4 1 Usage Linux PM framework The status of the devices which have been setup as the wake up events is available through the sysfs interface Below is the status of the devices that have the capability to wake up SPEAr from sleep mode Wake up source status If any of the sources has been enabled to provide wake up from sleep its status can be captured by the following command cat sys devices platform spear eth power wakeup enabled cat sys devices platform spear rtc power wakeup enabled To put the system into sleep mode execute the following command echo mem sys power state PM Syncing FileSystems done Freez
220. mework in Linux The input subsystem is the part of the Linux kernel that manages the various input devices such as keyboards mice joysticks tablets and a wide range of other devices that a user uses to interact with the kernel command line and graphical user interface This subsystem is included in the kernel because these devices usually are accessed through special hardware interfaces such as serial ports PS 2 ports Apple Desktop Bus and the Universal Serial Bus which are protected and managed by the kernel The kernel then exposes the user input in a consistent device independent way to user space through a range of defined APIs 180 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Human interface device HID drivers Note 7 2 3 The three elements of the input subsystem are the input core drivers and event handlers The relationship between them is shown in Figure 48 Note that while the normal path is from low level hardware to drivers drivers to input core input core to handler and handler to user space there usually is a return path as well The interaction between various elements is through events which are implemented as structures The first field time is a simple timestamp The type field shows the generic type of event being reported for example a key press or button press The code field tells which of the various buttons are being manipulated while the value field tells you what the state o
221. mtd n return Read 4 bytes from partition 3 and store in buffer ret mtd gt read mtd 0 4 amp retlen buffer if ret lt 0 err Err MTD read d n ret return Write 4 bytes into the partition 3 from the buffer ret mtd gt write mtd 0 4 amp retlen buffer if ret lt 0 err Err MTD write d n ret return Logical mode usage from user space The MTD partition can be mounted using a file system and then can be used The NOR Flash partition is supported by JFFS2 only so make sure that a valid JFFS2 image is already present in the partition to avoid getting a lot of JFFS2 errror messages mount t jffs2 dev mtdblock3 mnt cp tmp song mp3 mnt 1s mnt Song mp3 a 148 245 Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Non volatile memory device drivers 5 3 6 Note Serial NOR device driver performance e Hardware ARM926EJS 333 MHz STMicroelectronics 8 MB M25P64 Serial NOR Flash e Test Filesystem on the NAND Flash JFFS2 for dev mtdblock3 e Kernel Linux 2 6 27 Results for JFFS2 Compression is on by default in JFFS2 This causes the writing of data which is uniform to finish in much less time Therefore compression was disabled from config Mount JFFS2 fs and write read to a file Sequence is as follows mount t jffs2 dev mtdblock3 mnt time dd if dev zero of mnt file bin bs 128K count 8 Write the file umount mnt m
222. must configure the ADC There are two types of configurations possible for the ADC e Common configuration This configuration is common to all ADC channels It does not have to be done every time you want to use the ADC It must be configured keeping in mind that it affects all ADC channels During ADC module initialization common configuration is configured with the default configuration passed from the platform data present in arch arm mach spear spear c This common configuration may not need to be changed e Channel configuration this configuration is for a particular ADC channel ADC device configuration Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Human interface device HID drivers Common configuration of all ADC channels can be done using the following calls User level ioctl fd ADCIOC CONFIG amp config On success zero is returned otherwise 1 is returned and errno is set appropriately Kernel level spear adc configure dev ADC CHANNELO amp config On success zero is returned otherwise negative standard kernel errors are returned The above functions will be successful if the ADC is not being used by another user In the function calls config is an instance of struct adc config struct adc config enum adc conv mode mode mode to be configured can be single or continuous enum adc volt ref volt ref reference of voltage can be internal or external unsigned
223. n CONFIG USB_NET_CDCETHER device class CDC Ethernet control model CONFIG_HID_SUPPORT Options for various computer human interface device drivers This option compiles into kernel the generic HID layer code CONFIG_HID parser usages etc which can then be used by transport specific HID implementation like USB or Bluetooth Examples in this document show configuration options for basic USB support as well as the commonly needed options for example a USB mass storage device most cameras and USB pen drives make menuconfig options Device Drivers gt SCSI device support gt Although SCSI will be enabled automatically when selecting USB Mass Storage we need to enable disk support SCSI support type disk tape CD ROM lt gt SCSI disk support Then Move a Level Back and Go into USB Support USB support gt This is the root hub and is required for USB support If you d like to compile this as a module it will be called usbcore lt gt Support for Host side USB Enable this option if your system has the host side bus and wants to use USB devices and also to see your USB devices in proc bus usb This is recommended USB device filesystem Select at least one of the HCDs If you are unsure picking all is fine USB Host Controller Drivers lt gt EHCI HCD USB 2 0 support lt gt OHCI HCD support Moving a little further down we come to CDC and mass storage
224. n folder direction and value The direction of the GPIO can be set to OUT or IN by writing out or in on direction file Here gpiopin is a file formed after exporting a GPIO pin for example gpio9 gpio42 Example setting direction in OUT mode echo out sys class gpio gpio42 direction The direction of GPIO can be read by reading the above file Set and get value The value of the GPIO can be configured if GPIO is configured in OUT mode and its value can be read if the GPIO is configured in IN mode The value can be set by writing 1 or O in the sys class gpio gpionr value file Example setting gpio pin 42 echo 1 sys class gpio gpio42 value Similarly the value can be read by reading the same file Here gpiopin is a file formed after exporting a GPIO pin for example gpio9 gpio42 GPIO usage in kernel mode The following GPIO operations are allowed from kernel space Request set and get direction and value and configure GPIO for interrupt Doc ID 16604 Rev 2 209 245 www BDTIC com ST Miscellaneous device drivers UM0851 9 1 5 210 245 Request You can request a GPIO pin by calling following function Gpio is gpio pin number to be requested Label is a string passed by user as a unique identification of user int gpio request unsigned gpio const char label Passing invalid GPIO numbers to gpio request will fail as will requesting GPIOs that have already been claim
225. n interface device HID drivers 174 7 1 Touchscreen driver 0 0 0 0 cc cece eet tees 174 7 1 1 Hardware overview 2 000 cece eee 174 7 1 2 Software overview 0 eee teens 174 7 1 3 Touchscreen driver overview llli 175 7 1 4 Touchscreen usage eres 177 7 1 5 References nnn 178 7 2 Keypad driver maawa co BAGA AANGAL tomes ROSES the E aaa PAK 178 7 2 1 Hardware overview 0 nes 178 7 2 2 Software overview eee 179 7 2 3 Customizing the keypad driver 000 c eee 181 7 2 4 Keypad usage rn 182 7 2 5 Configuration options eh 183 g ADCONYE isis o X DR IL OR see NAMRG NAG KAMAG KKK NG KA d 183 7 3 1 Hardware overview 00 cece eee 183 7 3 2 Software overview teens 184 7 3 3 ADC usage in Linux e 185 7 3 4 Known issues or limitations llli 190 7 3 5 ADC device driver performance leen 190 7 3 6 Configuration options eren 190 7 3 7 ALAGA AA PA 190 7 3 8 LCD panel support eI Ih 190 7 3 9 USB HID Class Support 0 0 00 e eee 190 8 Audio video drivers eee 191 8 1 LCD controller CLCD driver 00 0 eee 191 8 1 1 Hardware overview 0 nes 191 6 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Contents 8 1 2 Software overview n 192 8 1 3 CLCD device driver interface with frameb
226. ndled count spinlock t lock ifdef CONFIG SMP cpumask t affinity unsigned int cpu endif if defined CONFIG GENERIC PENDING IRQ defined CONFIG IRQBALANCE cpumask t pending mask endif ifdef CONFIG PROC FS struct proc dir entry dir endif const char name High level driver API The high level driver API normally used in device drivers consists of the following functions e request irq e free irq e disable irq e enable irq e disable irg nosync SMP only e synchronize irq SMP only e set irq type e set irq wake e set irq data e set irq chip e set irq chip data The details of some of the most important APIs described above are covered in Section 3 2 5 VIC usage a Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Platform section High level IRQ flow handlers The generic layer provides a set of pre defined IRQ flow methods e handle level irq provides a generic implementation for level triggered interrupts e handle edge irq provides a generic implementation for edge triggered interrupts e handle simple irq provides a generic implementation for simple interrupts The simple flow handler does not call any handler chip primitives e handle percpu irq provides a generic implementation for per CPU interrupts Per CPU interrupts are only available on SMP and the handler provides a simplified version without locking The interrupt flow handlers either pred
227. nect bp dev bp 5phy dev dev bus id amp macb handle link change 0 General kernel interface Please refer to the corresponding chapter of the GMAC section GMAC interface to kernel 4 2 4 Socket buffer management Please refer to the corresponding chapter of the GMAC section Section 4 1 4 Concept of socket buffers 4 2 5 Cache coherency Working with the CPU cache results in increased performance but introduces cache memory coherence problems as external DMAs can only access the external memory There are two cache strategies in the MACB driver e FIFO descriptor memory is allocated as an uncached memory block It uses the void dma alloc coherent struct device size t dma addr t gfp t function to allocate the uncached memory which uses the pgprot noncached macro to set the page table Since there is never a cached copy of this buffer CPU access is slower but there are no such coherency problems e Thereal data buffer whose address is stored in the FIFO descriptor is allocated as a cached memory block The driver allocates the RX buffers directly using kmalloc while the TX buffers are allocated by network stack upper layers In both cases the skb data field is populated with a data buffer pointer Since these RX TX buffers are cached the driver must explicitly guarantee the coherence between memory and cache For this purpose the Linux kernel provides the function dma adar t dma map single struct device dev voi
228. nel function provided to perform this allocation is alloc ccandev which has the following prototype sizeof priv is the size of SPEAr320 CAN driver s private data area struct net device alloc ccandev int sizeof priv Once the net device structure has been initialized the process of registration is completed by passing the same to register ccandev The access to the SPEAr CAN driver private data is done via the standard call provided by Linux kernel struct ccan priv priv netdev priv dev The private data structure used by the CAN driver is described below struct ccan priv struct can priv can struct net device dev int tx object int last status struct delayed work work u16 read reg struct net device dev enum c regs reg a Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Communication device drivers 4 9 5 void write reg struct net device dev enum c regs reg ul6 val ifdef CCAN DEBUG unsigned int bufstat MAX OBJECT 1 endif hi To write and read the CAN IP registers the APIs spr can write reg and spr can read reg are used respectively static u16 spr can read reg struct net device dev enum c regs reg static void spr can write reg struct net device dev enum c regs reg u16 val User land applications over the CAN driver This section describes how to design a simple application that accesses the services provided by the
229. nfo max freq e cpuinfo min freq Show the minimum frequency your CPU s can scale to cat sys devices system cpu cpu0 cpufreq cpuinfo min freq e scaling cur freq Show the available frequency your CPU s are currently scaled to cat sys devices system cpu cpu0 cpufreq scaling cur freq e scaling driver Show the cpufreq driver the CPU s are using cat sys devices system cpu cpu0 cpufreq scaling driver e scaling max freq Set the maximum frequency your CPU s are allowed to scale to Look at the output from scaling available frequencies above Then you can pick one of those numbers frequencies to set to be the maximum frequency the CPU s are allowed to scale to In SPEAr the range of scaling available frequencies is 166 MHz 266 MHz 333 MHz So you might set this to 166000 So when the CPU frequency scales it only goes to a max of 166000 and not 333000 An example on how to set this would be the following echo 166000 gt sys devices system cpu cpu0 cpufreqg scaling max freq e scaling min freq Same as scaling max freq but setting a lower frequency limit that the CPU s are not allowed to go below For example echo 266000 gt sys devices system cpu cpu0 cpufreqg scaling min freq This does not allow the CPU to go below the frequency of 266 MHz Doc ID 16604 Rev 2 237 245 www BDTIC com ST Power management section UM0851 10 4 4 238 245 Performance e Power management framework Below are some of the
230. ng 4 parallel data lines sd4 bit mode Upto 416 Mbits per second data rate using 8 bit parallel data lines sd8 bit mode Cyclic redundancy check CRC7 for command and CRC16 for data integrity Error correction code ECC support for MMC4 2 cards Software overview The SDIO host controller provides interface between the core driver layer of Linux MMC stack and the underlying SDIO host controller The SDIO host controller driver is present at the drivers mmc host spr sdio arasan c file The SDIO core driver layer is present in the drivers mmc core folder in Linux This layer provides an interface to card or function drivers which can use it to communicate with the SD MMC SDIO card Card drivers are present in the drivers mmc card folder in Linux This layer can provide its own interface to the user for example the MMC card driver implemented in Linux provides a block driver interface to the user After inserting the card on the slot you can access the MMC device nodes dev mmcblkp1 dev mmcblkp2 etc The following examples demonstrate how a card driver can access the functionalities provided by the core driver layer The device nodes dev mmcblkp1 and dev mmcblkp2 are created because the disk has partitions If you use a generic disk or a disk without partitions then the generic dev node dev mmcbIk 0 1 2 are created The driver does not support ADMA feature of SDIO host controller Doc ID 16604 Rev 2 ky www BDTIC com ST UM085
231. ng parameter nand timing data bus hiz phase 0x1 timing from start of cycle and enable data out bus only for write mode nand timing addr hold phase 0x4 Time from enable off and end of cycle Both for read and write cycle nand timing wait phase 0x6 Time from enable on to enable off for all signals Both for read and write cycle nand timing addr setup phase 0x0 Time from address valid to enable off activation Both for read and write cycle Call FSMC API fsmc set nand timing bank FSMC PC NAND COMMON MEM SPACE amp nand timing Out of band OOB data A NAND page consists of a number of data bytes 512 or 2048 plus a number of out of band OOB bytes 16 or 64 respectively Only the data bytes are used for application data The OOB bytes are used for e Marking an erase block as bad first or second page of erase block e Storing ECC error correction codes e Storing file system specific information JFFS2 or YAFFS OOB placement schemes are defined by a struct nand ecclayout struct nand ecclayout int eccbytes The eccbytes member defines the number of ecc bytes per page int eccpos 24 The eccpos array holds the byte offsets in the spare area where the ecc codes are placed int oobfree 8 2 The oobfree array defines the areas in the spare area which can be used for automatic placement The information is given in the format offset size offset defines
232. nly the system stability with asynchronous DDR operation U Boot Das U Boot is an open source boot monitor available for a wide range of embedded processors architectures A boot monitor is a small piece of software that executes after powering up an embedded system It can be used to achieve the following objectives e Monitor the system for develop debug purpose e Bootan OS Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Boot loader overview Note 1 2 1 1 2 2 1 2 3 Das U Boot starts from the second sector of Serial NOR Flash from where it is loaded in RAM by XLoader In case of NAND it starts from the fifth sector Das U Boot coming with the LSP v2 3 is licensed under GPLv2 and it is distributed in full Source code This distributed U Boot version runs on the SPEAr hardware development kits U Boot overview The U Boot bootloader is based on U Boot 1 3 1 release This U Boot source supports the complete SPEAr embedded MPU family SPEAr600 SPEAr300 SPEAr310 and SPEAr320 The U Boot is loaded into DDR2 from NOR parallel serial or NAND memory device and executed from DDR2 It initializes the following IPs or has the drivers for the following IPs e UART 12C Ethernet Serial NOR through SMI NAND device through FSMC Parallel NOR only in SPEAr310 USB Device Features U Boot for SPEAr devices supports the following features e Provides a first level debug environment for on board testing Supp
233. ns Configuration option Comment CONFIG INPUT This option enables input device mouse keyboard Touchscreen joystick etc connected to the system CONFIG INPUT EVDEV This option make input device events be accessible under char device 13 64 dev input eventX in a generic way CONFIG INPUT KEYBOARD Enables KEYBOARD devices CONFIG_ KEYBOARD_SPEAR Enables spear keypad support References e Linux 2 6 27 Documentation input input txt e Linux 2 6 27 Documentation input input programming txt 7 3 ADC driver This section describes the ADC controller driver 7 3 1 Hardware overview An analog to digital converter or simply ADC is a semiconductor device that converts an analog signal to digital codes that consist of 1 s and 0 s In the real world most of the signals sensed and processed by humans are analog signals Analog to digital conversion is the primary means by which analog signals are converted into digital data that can be processed by computers for various purposes ky Doc ID 16604 Rev 2 183 245 www BDTIC com ST Human interface device HID drivers UM0851 7 3 2 184 245 Figure 49 ADC block diagram A ADC lt L Configuration registers 8 Conversion data 8 analog inputs v APB bus When you scan a picture with a scanner what the scanner is doing is an analog to digital conversion it is taking the analog information provided by the picture ligh
234. ns the interface The interface is opened whenever ifconfig activates it The open method registers any system resource it needs I O ports IRQ DMA and sets up the MAC hardware as well as the PHY in auto negotiation mode The open method also starts the interface transmit queue The kernel provides a function to start the queue void netif start queue struct net device dev int stop struct net device dev This function stops the interface and powers down the PHY This function should reverse operations performed at open time The close method also stops the interface s transmit queue The kernel provides a function to stop the queue void netif stop queue struct net device dev int hard start xmit struct sk buff skb struct net device dev Method called to initiate the transmission of a packet The full packet protocol headers and all is contained in a socket buffer struct sk buff structure The function basically makes use of the chained DMA descriptors to transmit the packet sent by stack void tx timeout struct net device dev Method called by the networking code when a packet transmission fails to complete within a reasonable period on the assumption that an interrupt has been missed or the interface has locked up It should handle the problem and resume packet transmission The current driver reinitializes the total DMA MAC related hardware int do ioctl struct net device dev struct if
235. ns the physical packet as it should appear on the media complete with the transmission level headers The interface does not need to modify the data being transmitted skb gt data points to the packet being transmitted and skb gt en is its length in octets The transmission function in the SPEAr driver initializes DMA Descriptors to point to the relevant socket buffer to be transmitted As soon as the transmission is complete the TX completed interrupt is received where a transmission tasklet is scheduled for freeing up the Socket buffers being used for transfers and reinitializing some of the parameters of the DMA descriptors GMAC driver usage Usage of ifconfig command The ifconfig command allows the operating system to setup the network interfaces and the user to view information about the configured interfaces e To configure the network IP address ifconfig eth0 192 168 1 1 netmask 255 255 255 0 ifconfig ethO eth0 Link encap Ethernet HWaddr 08 00 17 0b 92 10 inet addr 192 168 1 1 Bcast 192 168 1 255 Mask 255 255 255 0 UP BROADCAST RUNNING MULTICAST MTU 1500 Metric 1 RX packets 0 errors 0 dropped 0 overruns 0 frame 0 TX packets 0 errors 0 dropped 0 overruns 0 carrier 0 collisions 0 txqueuelen 32 RX bytes 0 0 0 B TX bytes 0 0 0 B e Toconfigure the MTU size ifconfig eth0 mtu size If the user sets the mtu size as 4000 and then gives following command ifconfig ethO etho Link encap Ethernet HWaddr 08
236. nter will also progress by 2 bytes at each frame The first sample will be in the first half of the frame and the second sample in the second half TDM WIDEBAND LINEAR For wideband linear samples the pointer will progress by 4 bytes at each frame Two bytes are located in the first half of the frame two other in the second half dir Direction for the switching IN OUT BOTH Note Not used in bufferization Spear tdm sw start struct spear ts ts1 struct spear ts ts2 u8 pcm synchro int dir TDM switching stop This API is used to deactivate TDM switching spear ts timeslot structure as explained above The api will stop switching operation for the given timeslot Note Not used in bufferization Spear tdm sw stop struct spear ts ts Buffer write This API is used to write data to the buffer memory The information concerning the data data pointer data length are in the struct spear tdm request spear ts timeslot structure as explained above Spear tdm req transmit request Every request is added in tx list On reception of interrupt req will be extracted from the tx list and served spear tdm req structure describe one i o request Note Not used in switching spear tdm bfr write struct spear ts spear ts struct spear tdm req req struct spear tdm req u8 buf Buffer used for data storage Doc ID 16604 Rev 2 203 245 www BDTIC com ST Audio video drivers UM0851
237. ntroller is shown in Figure 51 The AMBA AHB slave interface connects the CLCD to the AMBA AHB bus and provides CPU accesses to the registers The AMBA AHB master interface transfers display data from a selected slave memory to the PrimeCell CLCD DMA FIFOs The output of the panel clock generator block is the panel clock This is a divided down version of the CLCD reference clock A free running reference clock must be provided to CLCD Panel Clock Generator can be programmed to match the bit per pixel data rate of the CLCD panel The primary function of the timing controller block is to generate the horizontal and vertical timing panel signals It also provides panel bias enable signals These timings are all register programmable through the AMBA AHB slave interface Figure 51 Block diagram of CLCD controller EN Panel gt clock LCD panel clock AHB slave Control controller interface and status E register Timing LCD panel control D gt controller I lt lt E 2 AHB master interface DMA FIFO and gt E data formatter CLCD panel LCD panel data Zs CLCD controller lt Doc ID 16604 Rev 2 191 245 www BDTIC com ST Audio video drivers UM0851 8 1 2 192 245 Software overview The CLCD device driver sits on top of the CLCD Controller and provides all necessary funct
238. o restart markers minus 1 struct mcu composition mcu comp MAX MCU COMP represents MCU composition Description of mcu composition structure struct mcu composition a 156 245 Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Accelerator engine device drivers u32 hdc hdc bit selects the Huffman table for the encoding of the DC coefficient in the data units belonging to the color component u32 hac hac bit selects the Huffman table for the encoding of the AC coefficients in the data units belonging to the color component u32 qt QT indicates the quantization table to be used for the color component oy u32 nblock nblock value is the number of data units 8 x 8 blocks of data of the color component contained in the MCU u32 h Horizontal Sampling factor for component u32 v Vertical Sampling factor for component hi Use the following system call to set JPEG info for DWOH ioctl wfd JPEGIOC SET DEC INFO amp dec info wfd file descriptor of jpeg write node JPEGIOC SET DEC INFO ioctl command for setting JPEG decoding information dec info structure containing jpeg decoding information Description of dec info structure struct jpeg dec info struct jpeg hdr hdr jpeg image header int hdr enable header processing enable disable char qnt mem QNT MEM SIZE quantization memory char hmin mem HMIN MEM SIZE Huff min memory char hbase mem
239. o write a new protocol driver For information on using the SPI framework please see eeprom c and spidev c files in drivers spi folder 88 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers SPI shows up in sysfs in several locations e sys devices CTLR physical node for a given SPI controller e sys devices CTLR spiB C spi device on bus B chipselect C accessed through CTLR e sys bus spi devices spiB C symlink to that physical CTLR spiB C device e sys devices CTLR spiB C modalias identifies the driver that should be used with this device for hot plug cold plug e sys bus spi drivers D driver for one or more spi devices e sys class spi master spiB symlink or actual device node to a logical node which could hold class related state for the controller managing bus B All spiB devices share one physical SPI bus segment with SCLK MOSI and MISO Linux SPI framework provides some functions that are used for registering and un registering SPI slave drivers It also provides some functions for transferring data over the SPI bus We will examine these functions one by one with examples from the EEPROM driver Adding a new slave device The SPI controller driver and slave driver need some board specific data to work correctly This data is present in arch arm mach spear300 spear300 c or arch arm mach spear600 spear600 c There are t
240. of known or generic PHY interfaces maintained in the PHY table structure struct mii phy def Below is a set of data structures used in the interface struct mii phy def u32 phy id Concatenated ID1 16 ID2 u32 phy id mask Significant bits u32 features Ethtool SUPPORTED defines or 0 for autodetect int magic aneg Autoneg does all speed test for us const char name const struct mii phy ops ops struct mii phy ops 46 245 int init struct mii phy phy Doc ID 16604 Rev 2 a www BDTIC com ST UM0851 Communication device drivers int suspend struct mii phy phy int wol options int setup aneg struct mii phy phy u32 advertise int setup forced struct mii phy phy int speed int fd int poll link struct mii phy phy int read link struct mii phy phy hi struct mii phy struct mii phy def def u32 advertising Ethtool ADVERTISED defines u32 features Copied from mii phy def features or determined automatically u8 address PHY address int mode PHY mode 1 autoneg enabled 0 disabled int autoneg forced speed amp duplex no autoneg partner speed amp duplex amp pause autoneg int speed int duplex int pause int asym pause Provided by host chip struct net device dev struct device pdev int mdio read struct net device dev int addr int
241. ointer to a callback function which will be called by the driver module when the erase has completed int read struct mtd info mtd loff t from size t len u char buf int write struct mtd info mtd loff t to size t len const u char buf Read and write functions for the memory device These may sleep and should not be called from IRQ context or with locks held The buf argument is assumed to be in kernel space If you need to copy to userspace either use a kiobuf to lock down the pages first or use a bounce buffer int read ecc struct mtd info mtd loff t from size t len u char buf u char eccbuf int write ecc struct mtd info mtd loff t to size t len const u char buf u char eccbuf For devices which support automatic ECC generation or checking these routines behave just the same at the read write functions above but with the addition that the write ecc function places the generated ECC data into eccbuf and the read ecc function verifies the ECC data and attempts to correct any errors which it detects int read oob struct mtd info mtd loff t from size t len u char buf int write oob struct mtd info mtd loff t to size t len const u char buf For devices which have out of band data these functions provide access to it The from to address is the address of the start of the real page of memory with which the OOB data is associated added to the offset within the OOB block
242. ol count clock prescaler and interrupt registers e Eachchannel has 16 bit counter with a programmable timer interval e Provides auto reload or single shot mode feature The following table shows GPTs available on different SPEAr platforms Table 10 GPTs available on SPEAr SPEAr600 SPEAr3xx 1 GPT in each CPU subsystem 2 in application subsystem 1 in basic subsystem 1 GPT in CPU subsystem 2 in basic subsystem The following figure describes the GPT hardware interface Figure 2 GPT hardware interface PLL1 synthesizer Match IntO PLL3 APB interface Match Intt 48 MHz The TIMER CLK can be selected between a fixed 48 MHz source and PLL1 which is also the source for the rest of the system The PLL1 output also goes through a synthesizer which can be programmed to derive the actual required operating GPT clock 3 1 2 Software overview SPEAr LSP provides proprietary software routines to allocate program and use the general purpose timer This set of routines abstract the GPT hardware block and provide easy kernel APIs to manage and control these timers This layer does not provide any interface to the user space The following figure explains the GPT framework as used by the kernel time keeping and tick management subsystem The GPT routines can also be directly used by user modules applications 26 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Platform secti
243. olling and return O Later when new data comes the interrupt calls the netif rx schedule to turn on the poll again Packet transmission Whenever the kernel needs to transmit a data packet it calls the driver s hard start xmit method to put the data on an outgoing queue The socket buffer passed to hard start xmit contains the physical packet as it should appear on the media complete with the transmission level headers The interface does not need to modify the data being transmitted skb gt data points to the packet being transmitted and skb gt len is its length in octets The transmission function in the MACB driver initializes DMA descriptors to point to the relevant socket buffer to be transmitted flushes the cache and then starts transmitting DMA As soon as the transmission is complete the TX completed interrupt is received which frees up the socket buffers being used for transfers reinitializing some of the parameters of the DMA descriptors MACB driver usage Please refer to the corresponding chapter of GMAC section Section 4 1 5 GMAC driver usage Kernel configuration options Below is a list of kernel configuration options being supported by the SPEAr MACB driver Table 18 Menuconfig options Configuration option Comment CONFIG NETDEVICES y Kernel Network Device Support CONFIG NET ETHERNET y Kernel Ethernet Support CONFIG MII y Generic Media Independent Interface provided by ke
244. on 4 Figure 3 GPT software architecture User space Date sleep User applications Time management Time of day keeping Kernel space Clock event User modules GPT routines Hardware General purpose timer In the Linux source tree the GPT layer is present in arch arm plat spear gpt c GPT layer interface The GPT layer represents the timer as a structure with the following fields struct spear_timer unsigned long phys_base int irq struct clk iclk interface clk struct clk fclk functional clk void __iomem io_base unsigned reserved 1 unsigned enabled 1 Pi The SPEAr LSP defines an array of struct spear timer for the available timers on each respective platform The GPT layer provides a set of APIs which operate on this structure to manage the set of available timers Allocating a timer There are two ways of allocating a GPT You can either ask for a free timer in this case an available timer on the list will be allocated to you or ask for a specific timer so if it is available it will be allocated to you Both the APIs return one of the available timers or NULL which you can subsequently use to program and control the timer request for a free timer struct spear timer spear timer request void request for a specific timer greater than or equal to 1 struct spear timer spear timer request specific int timer
245. onfigured in interrupt mode They support rising falling or both edge triggered interrupts and high or low level triggered interrupts Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Miscellaneous device drivers 9 1 6 9 2 9 2 1 You can get an interrupt line number for the GPIO pin to be used in interrupt mode You can also get the GPIO pin number from the interrupt line number for GPIOs used in interrupt mode This can be done using following function This function returns irq no for gpio pin int gpio to irq unsigned gpio This function returns gpio pin for irq no int irq to gpio unsigned irq To request a GPIO in interrupt mode you should use the standard linux request irq function Here irq is irq no value returned from gpio to irq handler irq handler with standard prototype Irqflags flags passed for configuring type of interrupt it can be one of following IRQ TYPE EDGE RISING IRQ TYPE EDGE FALLING IRQ TYPE EDGE BOTH IRQ TYPE LEVEL HIGH IRQ TYPE LEVEL LOW Devname name of device requesting interrupt Dev id pointer passed to interrupt handler upon interrupt int request irq unsigned int irq irq handler t handler unsigned long irqflags const char devname void dev id After use the GPIO interrupt can be freed using the following function call irq is irq no value returned from gpio to irq Dev id pointer passe
246. onsole ttySO0 e initrd This argument specifies the location of the initial ramdisk if a ramdisk is used Doc ID 16604 Rev 2 21 245 www BDTIC com ST Boot loader overview UM0851 setenv bootargs initrd 0x00800040 7M e init This argument runs a specified binary ex bin sh instead of sbin init as init process setenv bootargs init bin sh root rootdelay rootfstype e e e e n sroot These arguments provide information about how the root file system must be mounted NFS mount setenv bootargs root dev nfs nfsroot 192 168 1 1 home spear600 rootfs MTD mount NAND NOR flash root dev mtdblock3 rootfstype jffs2 RAMDisk mount setenv bootargs root dev ram0 initrd 0x00800040 7M USB flash mount setenv bootargs root dev sdal rootdelay 5 e ip lt client ip gt lt server ip gt lt gw ip gt lt netmask gt lt hostname gt lt device gt lt autoconf gt This argument shows how the IP address is determined setenv bootargs ip 192 168 1 13 192 168 1 1 192 168 1 1 255 255 255 0 spear600 eth0 off e mtdparts This argument overwrites the default MTD Flash partitioning mtdparts lt mtddef gt lt mtddef lt mtddef gt lt mtd id gt lt partdef gt lt partdef gt spartdef5 lt size gt offset lt name gt ro 1k mtd id unique name used in mapping driver device mtd name gize standa
247. onverted voltage on the ADC channel The output data is in millivolts The converted data can be read using the following calls User level read fd amp data count On success it returns the number of bytes copied otherwise 1 is returned and errno is set appropriately Kernel level Spear adc get data dev ADC CHANNELO amp data count Data is variable in which converted voltage in millivolts will a 188 245 Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Human interface device HID drivers be stored Type of data is unsigned int Count can be greater than one only for channel zero where dma transfers are possible For all other channels it must be equal to one otherwise error is returned On success zero is returned otherwise negative standard kernel errors are returned Get ADC configuration Use the following calls to get the configuration of the ADC device User level ioctl fd ADCIOC GET CONFIG amp config On success zero is returned otherwise 1 is returned and errno is set appropriately Kernel level Spear adc get configure dev ADC CHANNELO config On success zero is returned otherwise negative standard kernel errors are returned In the function calls config is instance of the previously defined struct adc config Get ADC channel configuration Use the following calls to get the configuration of any ADC channel User level ioctl fd ADCIOC GET CHAN C
248. or testing zero gadget on host side This enables dual FULL and HIGH speed support CONFIG USB TEST CONFIG USB GADGET DUALSPEED There are certainly other configurations related to the USB Device which may be required for an individual application One of these is FIFO related configurations The RxFIFO on SPEAr USBD can be configured for each endpoint Keep in mind that total combined RxFIFO usage for all out endpoints should not exceed 2 KB Similarly total combined TxFIFO usage for all IN endpoints should be limited to 2 KB To change this FIFO configuration you can edit the corresponding macro in drivers usb gadget spr udc syn h Default Endpoint FIFO sizes in words define EP1 IN FIFO SIZE 512 4 define EP2 OUT FIFO SIZE 512 4 Buffer length configuration The gadget drivers allocate a USB request and then submit it to the framework for transfer The length of such transfer requests will determine the performance of the driver Allocating a large buffer and hence a bigger buffer length will make CPU more free USB DMA would try to complete the transfer for the asked length and then interrupt CPU notifying the completion of the transfer The maximum buffer length is limited to 65535 bytes on SPEAr USB Device References e http www linux usb org gadgets e http www linux usb org usbtest e http www usb org 12C driver This section describes the driver for the I2C controller embedded in SPEAr
249. orts erasing writing to NAND NOR memory devices Supports uploading binary images through Ethernet or Serial port Supports booting the OS Linux VxWorks etc Acts as a firmware for flashing utilities It supports USB TTY driver Building U Boot To build U Boot for both serial NOR and NAND Flash you need to use the STLinux toolchain and run the following commands Build U Boot for SPEAr600 target make spear600 config Generating include autoconf mk Configuring for spear600 board make Build U Boot for SPEAr300 target make spear300 config Generating include autoconf mk Configuring for spear300 board make Build U Boot for SPEAr310 target make spear310 config Generating include autoconf mk Configuring for spear310 board Doc ID 16604 Rev 2 15 245 www BDTIC com ST Boot loader overview UM0851 make Build U Boot for SPEAr320 target make spear320 config Generating include autoconf mk Configuring for spear320 board make The U Boot source can be compiled with various options which are listed below e make CONSOLE USB This option generates firmware binary image containing TTY over USB driver to be downloaded for the operation of the Flashing Utility refer to the Section 11 Flashing utility section This option is available for SPEAr3xx and SPEAr600 e make ENV NAND This option generates U Boot firmware image which saves environment variables in NAND device Th
250. ount t jffs2 dev mtdblock3 mnt time dd if mnt file bin of dev null bs 128K count 8 Read file back umount mnt mount t jffs2 dev mtdblock3 mnt rm mnt file bin umount mnt 0 Repeat for bs 128K 256K 512K 1024K and count 8 4 2 1 3 POND O RA DN Please be sure that JFFS2 compression is disabled To disable it use the following Linux configuration parameter CONFIG JFFS2 CMODE NONE Table 41 Results on SPEAr600 Block size in Filesize seconds byte sec in seconds im Mega byte sec in write write read 1 4 1 2 28 0 438596491 0 12 8 333333333 2 8 1 2 85 0 350877193 0 12 8 333333333 3 16 1 2 27 0 440528634 0 12 8 333333333 4 32 1 2 27 0 440528634 0 12 8 333333333 5 64 1 2 27 0 440528634 0 12 8 333333333 Doc ID 16604 Rev 2 149 245 www BDTIC com ST Non volatile memory device drivers UM0851 5 3 7 150 245 Figure 39 NOR memory performance 9 W AHAHAHA 8 7 H 6 s5 4 Write to NOR i 4 fl Readfro mN OR z3 2 1 Ka Gn 0 1 1 1 1 1 Block Size in MB Configuration options Table 42 Serial NOR menuconfig options Configuration option Comment CONFIG MTD NOR SPEAR This option is used to enable the NOR driver support CONFIG MTD PARTITIONS This option enables multiple partitions each of which appears to the user as a separate MTD device CONFIG MTD CMDLINE PARTS This option will make the
251. ously created delete sg sg sg len dma chan put chan dma unmap single chan device dev src buf 100 DMA TO DEVICE status chan device device is tx complete chan cookie NULL NULL if status DMA SUCCESS printk dma xfer fail n return EAGAIN else cpu get_cpu per_cpu_ptr chan gt local cpu bytes transferred size per_cpu_ptr chan gt local cpu gt memcpy_count put cpu printk dma xfer pass n dma async client unregister sdma client static enum dma_state_client dma_event struct dma_client client struct dma_chan gchan enum dma_state state unsigned long flags enum dma_state_clientack DMA_NAK switch state case DMA RESOURCE AVAILABLE if chan chan gchan ack DMA_ACK break case DMA_RESOURCE_REMOVED if chan gchan chan NULL ack DMA_ACK break return ack Doc ID 16604 Rev 2 171 245 www BDTIC com ST Accelerator engine device drivers UM0851 6 2 3 DMA device driver performance The driver performance was evaluated using the following setup e Target device SPEAr600 CPU 332 MHz AHB 166 MHz DDR 333 MHz e Test method Use of DMA memory to memory DDR to DDR transfers with a single master for both source and destination transfers To test the driver performance 1 Select CONFIG DMATEST as Module under device drivers DMA En
252. overview MTD is a generic subsystem for handling memory technology devices under Linux MTD provides a generic interface between the device drivers and the upper layers of the system Device drivers do not need to know about the storage formats used such as FTL FFS2 etc They only need to provide simple routines for read write and erase The presentation of the device s contents to the user in an appropriate form will be handled by the upper layers of the system The MTD system is divided into two types of module users and drivers Drivers are the modules which provide raw read write erase access to physical memory devices Users are like YAFFS or JFFS as shown in figure above they are the modules which use MTD drivers and provide a higher level interface to the user space JFFS is a file system which runs directly on the Flash and MTDBLOCK performs no translation just provides a block device interface directly to the underlying MTD driver NAND device driver interface to MTD The NAND device driver allocates a struct mtd info with information about the NAND Flash device and pointers to access routines at the time of initialization Some important fields of the struct mtd info are described below struct mtd info char name 32 Name of the device Rarely used but presented to the user via the proc mtd interface u char type Type of memory technology used in this device Choose from u long flags Device capabilities Bi
253. pplications over the CAN driver aa 109 4 9 6 Netlink interface for the CAN driver 0 00 ene eee 110 4 9 7 Kernel configuration options AA 110 4 9 8 Heferences isses ke edu ia a ewe ead dar Pa edd re 111 4 10 HDLC driver 111 4 10 1 Hardware overview llle en 111 4 10 2 Software overview e 113 4 40 3 SPEAr HDLC driver interface llle 115 4 10 4 Driver parameters re 117 4 10 5 Assigning timeslots for TDM E1 interface lusus 118 4 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Contents 4 10 6 Application code B 119 440 7 Testutlities is 24 seek I eR ERI E Rar CER EE x 120 4 10 8 List HDLC channels 0 22 res 120 410 9 Raw datatest een 121 4 10 10 Configuration options ele 122 4 10 11 References enn 122 5 Non volatile memory device drivers 123 5 1 NAND Flash driver ee 123 5 1 1 Hardware overview nes 123 5 1 2 Software overview 0 ne 124 5 1 3 NAND device driver overview ccc eee eens 125 5 1 4 NAND device usage 00 eet nh 132 5 1 5 NAND Flash file system image creation 135 5 1 6 NAND device driver performance sels 135 5 1 7 Configuration options ren 138 5 1 8 References lille nnn 138 5 2 EMI interface driver llli 139 5 2 1 H
254. pport Sometimes small size and cheap non volatile memories are a proper solution for an embedded application Please refer to Section 4 5 I2C driver and Section 4 6 SPI driver SD MMC memory support SPEAr300 supports SD MMC memory cards accessible through an SD SDIO MMC stack Please refer to Section 4 7 SDIO driver for more information Doc ID 16604 Rev 2 151 245 www BDTIC com ST Accelerator engine device drivers UM0851 6 6 1 6 1 1 152 245 Accelerator engine device drivers SPEAr family devices have several embedded engines for processing specific tasks directly in hardware These engines accelerate system throughput and off load the CPU at the same time This section describes the drivers for the following SPEAr accelerator engines e JPEG codec e DMA JPEG driver This section describes the JPEG encoder decoder driver Hardware overview The JPEG codec is connected to the AHB bus It is able to decode and encode image data contained in memory from the JPEG or YUV format to the YUV or JPEG format with or without header processing The codec core implements all the required steps for encoding and decoding image data according to the JPEG baseline algorithm as specified in ISO IEC 10918 1 It is specifically designed to accelerate entropy coded segment ECS encoding and decoding because this forms the most computing intensive part of the baseline JPEG algorithm The codec core can enable d
255. press release press mode and press hold mode Press release press mode identifies a press release press sequence of a key as two consecutive presses of the same key Press hold mode checks the input key s state at periodic intervals to determine the number of times the same key has been pressed ky Doc ID 16604 Rev 2 179 245 www BDTIC com ST Human interface device HID drivers UM0851 The main features of the keypad are as follows e Programmable input keypad matrix size e Press release press and press hold mode supported e Interrupt on any key pressed The keypad software system architecture is shown in Figure 48 Figure 48 Keypad driver architecture overview i t tX Userspace dev input eventX Input event handler A v Input device layer Kernel space A v SPEAr keypad controller driver Hardware SPEAr keypad controller Keypad operation A keypad device consists of a matrix with two sets of wires one set that runs horizontally rows and another that runs vertically columns with a push button switch at each intersection The row and column wires do not touch but run over each other When the push button is pressed a contact is established at the intersection of a given row and column serving as a switch The number of switches for a given matrix depends on the number of rows and columns For example a 4x4 matrix can support up to 16 switches Input fra
256. q Frees the allocated request intusb ep disable struct usb ep ep Disables the endpoint ep so that it is not usable int usb ep queue struct usb ep ep Submist a transfer request on this endpoint e struct usb request req gfp t gfp flags 3 P ep int usb_ep_set_halt struct usb_ep ep Halts a particular endpoint ep USBD control You can use the following APIs to configure and program the USB Device Table 23 USB device control APIs API Description int usb gadget frame number struct usb gadget gadget Returns the current Start of Frame number int usb gadget wakeup struct usb gadget Enables the remote wakeup feature of USB gadget Device int usb gadget set selfpowered struct usb gadget gadget USB Device is self powered int usb gadget clear selfpowered struct usb gadget gadget USB Device is not self powered but bus powered Configures USB device on configuration change This API is SPEAr specific and is mandatory to int usb gadget ioctl struct usb gadget call on SET CONFIGURATION as it programs the gaage gac dad controller accordingly param points to the unsigned code unsigned long param function descriptors Please refer hardware User Manual USB_CSR of USBD register for details USBD driver usage As explained above there can be various user defined functions over the Linux gadget framework Each of the functions gadgets exposes it
257. q dynamically This governor was introduced in Linux kernel 2 6 9 to keep the performance loss due to reduced frequency to a minimum A Conservative governor is a fork of the ondemand governor with a slightly different algorithm to decide on the target frequency Architecture driver The SPEAR architecture driver provides in the following set of frequencies to the CPUfreq governor to iterate through and determine the best possible system configuration e 33000000 Hz highest configurable frequency e 266000000 Hz e 166000000 Hz lowest configurable frequency CPUfreq is operational and allows the CPU frequency to be changed only when the system is running on PLL 1 and the DDR is running on PLL 2 In other cases the architecture code will not allow the transitions Support for the following statistics is currently not supported in driver time in state total trans trans table Details on this are available at Linux Documentation in the kernel tree cpu freq cpufreq stats txt The architecture driver handles the CPU frequency changes at two levels e The first level of the architecture code interacts with the kernel This level is covered in Section 10 3 Power management API e The second level of the architecture code gets the request from the top level to check for the CPU frequency that can be configured closest to the requested frequency This code maintains a pseudo control structure for the CPU frequency control in the clock
258. r motion is For example if the type is a key or button code tells you which key or button it is and value tells you if the button has been pressed or released struct input event struct timeval time v16 type v16 code 832 value Initialization and registration In the spear kp init driver function which is called either when the module is loaded or when booting the kernel the keypad driver grabs the required resources it should also check for the presence of the device Then it allocates a new input device structure using input allocate device and sets up input bitfields In this way the device driver tells the other parts of the input systems what it is and what events can be generated or accepted by this input device The driver registers the input device structure by calling input register device This adds the struct input dev to the linked lists of the input driver and calls the device handler modules connect functions to tell them a new input device has appeared Input register device may sleep and therefore must not be called from an interrupt or with a spinlock held struct input dev input input register device input Upon any press or release of key the driver reports it via the input report key call to the input system The value is interpreted as a truth value any nonzero value means key pressed zero value means key released The input code generates events only in case the value is dif
259. r USB FS and the 1 5 Mbps low speed LS for USB 1 1 through one integrated OHCI host controller 1 1 through two integrated OHCI Host controllers The main features provided by each USB 2 0 Host are listed below e PHY interface implementing a USB 2 0 transceiver macro cell interface UTMI fully compliant with UTMI specification revision 1 05 to execute serialization and de serialization of transmissions over the USB line e 30 MHz clock for 16 bit interface supported by the UTMI PHY interface e USB 2 0 Host controller UHC connected to the AHB bus that generates the commands for the UTMI PHY e The UHC complies with both the enhanced host controller interface EHCI specification version 1 0 and the open host controller interface OHCI specification version 1 0a e All clock synchronization is handled within the UHC e An AHB slave for each controller EHCI and OHCI acting as a programming interface for access to control and status registers e An AHB master for each controller EHCI and OHCI for data transfer to system memory supporting 8 16 and 32 bit wide data transactions on the AHB bus ky Doc ID 16604 Rev 2 61 245 www BDTIC com ST Communication device drivers UM0851 4 3 2 4 3 3 62 245 Figure 13 USB driver overview User space Application Other USB Mass storage class drivers Kernel space USB core UHC driver Other controller drivers Hardware UHCI EHCI
260. ramdisk 31 mtdblock After obtaining the major number of the ADC create ADC nodes using the following commands mknod dev adcx c major x Above command must be executed for x 0 5 7 These user level nodes may then be used for any further interaction with the ADC driver hardware Kernel level Kernel modules must include drivers char spr adc st10 h file to access data types related to the ADC All kernel level calls expect the first argument to be a pointer unique to the calling module This pointer is kept in the ADC driver to track the owner of an ADC channel In the following examples ADC channel 0 is used as the configuring channel Open get channel To access any of the avaialble ADC features you must acquire get an ADC channel The channel can be opened using the open call User level fd open dev adc0 O_RDWR On success a positive file descriptor number is returned otherwise 1 is returned and errno is set appropriately This file descriptor is used for any further communication with the ADC device Kernel level dev pointer unique to the calling module Spear adc chan get dev ADC CHANNELO On success zero is returned otherwise negative standard kernel errors are returned The above functions will be successful if the requested ADC channel is free and the ADC device is not already being used in SINGLE CONVERSION mode Configure ADC Before converting data on an ADC channel you
261. ration RS485 features e Five interface signals TXCLK RXCLK TXD RXD CTS e Supports duplex TX Rx communication e Maximum Tx Rx data rate up to 3 88 Mbps e Data sending sampling time is configurable e Noconstraints on clock duty cycle 112 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers HDLC controller features e Compliant with ISO IEC13239 e Standard HDLC frame code decode e Txchannel features Automatic Inter Frame Fill IFF generation Ox7E or OxFF Automatic flag generation Selectable CRC generation Automatic contention resolution RS485 which sends bit 0 first occupies the bus RS485 which loses the bus will restart the frame transmitting automatically as Soon as the bus becomes idle Delay between Tx data and echo data is configurable Priority class penalty configurable e Rx channel feature Automatic flag detection Programmable address recognition Automatic inter frame fill IFF detection Ox7E or OxFF Storing CRC received into external memory is configurable e Exception report 4 10 2 Software overview From the software view the programming models for the TDM E1 HDLC and RS485 HDLC controllers are very similar in several aspects Both of them use similar DMA descriptor structure similar interrupt queue and so on So TDM E1 HDLC and RS485 HDLC share the same driver code in Linux There is a generic HDLC layer in the Linux kernel
262. ration We can add several functions as per our composite device design You can use the following mechanism to add functions to configurations Following function registered earlier is called during registration static int sourcesink_bind_config struct usb_configuration c struct f_sourcesink ss int status ss kzalloc sizeof ss GFP_KERNEL if ss return ENOMEM ss gt function name source sink ss gt function descriptors fs_source_sink_descs ss gt function bind sourcesink_bind ss gt function unbind sourcesink_unbind ss gt function set_alt sourcesink_set_alt Doc ID 16604 Rev 2 73 245 www BDTIC com ST Communication device drivers UM0851 ss gt function disable sourcesink disable ss gt function suspend sourcesink suspend ss gt function resume sourcesink resume status usb add function c amp ss function if status kfree ss return status Initializing USB descriptors There are some fields in standard USB descriptors that require inputs from the composite layer for initialization In almost all descriptors some of these fields are indexed to string tables and to an interface number for the interface descriptors For this there are some helper routines which are described below static int zero_bind struct usb_composite_dev cdev get next available string index id usb string id cdev if id 0 return id strings dev STRING
263. raw mode for example using the dd command or in logical mode mounting a file system usually YAFFS2 or JFFS2 and accessing its files through open read write system calls Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Non volatile memory device drivers MTD device nodes MTD is neither a block nor a char device There are translations Flash translation layers or FTLs to use them as if they were Instead the MTD device e Consists of eraseblocks e Maintains 3 main operations read from eraseblock write to eraseblock and erase eraseblock e Baderaseblocks are not hidden and should be dealt with in software Two popular user modules that enable access to Flash are character device nodes and block device nodes Character device nodes provide raw character access to the Flash while block device nodes project the Flash as a normal block device on which a file system can be created The devices associated with character device nodes are dev mtaO mtd1 mtd2 etc while the devices associated with block device nodes are dev mtablockO mtablock 1 etc Since block device nodes provide block device like emulation it is often preferable to use file systems like YAFFS JFFS2 over this emulation You can find the list of MTD device nodes below cat dev mtdo mtd1 mtd2 mtd3 mtd4 mtd5 mtd6 mtd proc mtd size 00010000 00040000 002c0000 004 0000 00010000 00050000 00400000 03ba000
264. rd linux memsize OR to denote all remaining space name NAME ej setenv bootargs mtdparts SMI NOR0 2M PARTITION 1 3M PARTITION 2 22 245 Doc ID 16604 Rev 2 a www BDTIC com ST UM0851 Linux OS and device driver general information 2 q Linux OS and device driver general information Linux coming with the LSP v2 3 which is based on kernel version 2 6 27 is licensed under GPLv2 and distributed in full source code LSP v2 3 supports the following features of Linux e Patch for YAFFS file system support over NAND e Support for high resolution timer e Alldrivers integrated into standard Linux device model LSP v2 3 incorporates the following SPEAr specific set of drivers Table 9 LSP v2 3 device drivers Section name Driver name SPEAr MPU Platform section General purpose timer GPT driver All Platform section Vector interrupt controller VIC driver All Platform section Real time clock RTC driver All Communication device drivers GMAC Ethernet driver All Communication device drivers MACB MAC block driver SP310 SP320 Communication device drivers USB Host All Communication device drivers USB Device All Communication device drivers 12C driver All Communication device drivers SPI driver AI Communication device drivers SDIO driver SP300 SP320 Communication device drivers UART driver All Communication device drivers
265. rd may contain memory storage capability as well as I O functionality The Arasan SDIO host controller included in the SPEAr300 and SPEAr320 customization has an AMBA compatible interface and conforms to the SD host controller standard specification version 2 0 It handles SDIO SD protocol at transmission level packing data adding cyclic redundancy check CRC setting of start end bit and checking for transaction format correctness The host controller provides programmed I O and DMA data transfer method Figure 23 SDIO block diagram r zl Power Management E Bus Monitor DIO2 0 SD2 0 Me SD Protocol Uni MMC 3 31 4 2 Control Unit AHB Interface SD Registers Control Unit Clock Control L Synchronizer Storage Device Doc ID 16604 Rev 2 93 245 www BDTIC com ST Communication device drivers UM0851 4 7 2 Note 94 245 1 Features of the SD host controller e Compliant to SD host controller SDIO card and SD memory card standard specification version 2 0 Compliant to SD memory card security specification version 1 01 Compliant to MMC specification version 3 31 and 4 2 Supports both DMA SDMA amp ADMA and Non DMA mode of operation Supports MMC Plus and MMC Mobile Host clock rate variable between O and 52 MHz Supports 1 bit 4 bit and 8 bit SD modes and SPI mode Up to 100 Mbits per second data rate usi
266. req ifr int cmd Function that performs interface specific ioctl commands the implementation of these commands is described in the Custom ioctl commands section The corresponding field in struct net device can be left as NULL if the interface does not need any interface specific commands The SPEAr driver routes the ioctls to the standard MII interface provided by the kernel The commands are as follows SIOCGMIIPHY get address of MII PHY in use SIOCGMIIREG read MII PHY register The usage of the above ioctls can be explored by using the mii tool provided in the user space int change mtu struct net device dev int new mtu Function that takes action if there is a change in the maximum transfer unit MTU for the interface Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers Note The maximum MTU size for SPEAr600 is 4000 and for SPEAr300 is 9000 e void set multicast list struct net device dev Method called when the multicast list for the device changes and when the flags change 4 1 4 Concept of socket buffers Each packet handled by the kernel is contained in a socket buffer structure struct sk buff whose definition is found in lt inux skbuff h gt The structure gets its name from the Unix abstraction used to represent a network connection the socket Even if the interface has nothing to do with sockets each network packet belongs to a socket in the higher network
267. returns pointer to struct pwm device structure if the PWM channel is free otherwise errno is returned Configure The user driver must configure the PWM channel with required duty and period in nanoseconds This is done using the following function call pwm is pointer to channel previously allocated duty ns is duty in nanoseconds period ns is period in nanoseconds int pwm config struct pwm device pwm int duty ns int period ns It returns zero on success otherwise errno is returned 12 936 sec period ns 12 nsec period ns gt duty ns gt 12 nsec Enable After configuring the PWM channel it must be enabled This is done using the following function call pwm is pointer to channel previously allocated int pwm enable struct pwm device pwm It returns zero on success otherwise errno is returned Disable After using the PWM channel it must be disabled This is done using the following function call pwm is pointer to channel previously allocated void pwm disable struct pwm device pwm Free The PWM channel must be freed once it is used This can be done using the following function call Pwm is pointer to channel previously allocated void pwm free struct pwm device pwm Configuration options Table 58 SDIO menuconfig kernel options Configuration option Comment CONFIG SPEAR PWM This option enables SPEAr PWM driver a Doc ID 16604 Rev 2
268. rface The transmit block takes data from the DMA interface adds preamble and if necessary pad and FCS and transmits data according to the CSMA CD carrier sense multiple access with collision detect protocol The start of transmission is deferred if CRS carrier sense is active If COL collision becomes active during transmission a jam sequence is asserted and the transmission is retried after a random back off CRS and COL have no effect in full duplex mode The DMA block connects to external memory through its AMBA AHB or ASB bus interface It contains receive and transmit FIFOs for buffering frame data It loads the transmit FIFO and empties the receive FIFO using AHB or ASB bus master operations Receive data is not sent to memory until the address checking logic has determined that the frame should be copied Receive or transmit frames are stored in one or more buffers Receive buffers have a fixed length of 128 bytes Transmit buffers range in length between 0 and 2047 bytes and up to 128 buffers are permitted per frame The DMA block manages transmit and receive frame buffer queues These queues can hold multiple frames Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers 4 2 2 4 2 3 In system applications where no DMA is required the DMA interface can be replaced with a FIFO interface using a compile option In this configuration the MACB may be used with a larger external FIFO So
269. rifying all the PHY chips the top layer driver creates four or a different number of platform devices which matches the MACB platform drivers The platform contains the struct phy device and its corresponding MACB base register address The code below is in the top layer driver driver net arm macb top c register MDIO bus of MACB bp mii bus name MACB mii bus bp mii bus read amp macb mdio read bp mii bus write amp macb mdio write bp mii bus reset amp macb mdio reset bp mii bus id bp gt pdev gt id 58 245 Doc ID 16604 Rev 2 a www BDTIC com ST UM0851 Communication device drivers this function will register the mdio bus basic operation and scan all PHYs in this bus mdiobus register amp bp mii bus after this function if there s a valid PHY at address addr bp 5mii bus phy map phy addr will point to a phy device structure otherwise it is NULL Through platform device driver the MACB drivers will get the phy device structure and the MAC base register address from the top layer The following code is in MACB driver drivers net arm spear macb c to start the PHY phy start bp phy dev in the run time the network environment may change So the state of PHY link on off 100M 10M may also change At the same time it is necessary to change the MAC setting in software This can be done through a callback function macb handle link change phydev phy con
270. ripheral to memory and peripheral to peripheral transfers Scatter or gather DMA support through the use of linked lists Hardware DMA channel priority Each DMA channel has a specific hardware priority DMA channel 0 has the highest priority and channel 7 has the lowest priority If Doc ID 16604 Rev 2 163 245 www BDTIC com ST Accelerator engine device drivers UM0851 6 2 2 164 245 requests from two channels become active at the same time the channel with the highest priority is serviced first e Two AHB bus masters for transferring data Use these interfaces to transfer data when a DMA request goes active e Incrementing or non incrementing addressing for source and destination e Programmable DMA burst size You can program the DMA burst size to transfer data more efficiently The burst size is usually set to half the size of the FIFO in the peripheral e Supports eight 16 and 32 bit wide transactions e Big endian and little endian support The DMAC defaults to little endian mode on reset Software overview The DMAC driver is the software between the Linux DMA Engine framework and the ARM PLO80 DMA controller It configures the hardware with the help of instructions passed from the DMA framework or user driver The overall DMA software system architecture is represented in the figure below Figure 43 DMA software architecture Linux drivers Kernel space DMA engine framework DMAC driver TT D
271. rivers net wan for Linux 2 6 27 e e e http www kernel org pub linux utils net hdlc e e e setslot utility Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Non volatile memory device drivers 5 5 1 5 1 1 Non volatile memory device drivers Non volatile memory can retain stored information even when not powered and it is a fundamental feature of an embedded system The following section groups the drivers related to the non volatile memory controllers embedded in SPEAr NAND Flash driver Hardware overview NAND Flash is a non volatile memory with a data access width of 8 or 16 bits The read and write operations are done in pages typically 512 or 2048 bytes while the erase operation is done in erase blocks block size is typically 16 K or 64 K NAND Flash is I O mapped and requires a relatively complicated driver for any operation Nowadays the NAND technology allows bigger size parts at lower cost but with a lower reliability The main issues the NAND technology has to face are bit flipping and bad blocks To correct bit flipping NAND controller and driver uses error detection correction code EDC ECC The second issue requires the use of some bad block management techniques Higher density lower cost faster write erase times and a longer re write life expectancy make NAND Flash especially well suited for consumer media applications such as USB Flash drives digital cameras and MP3 players in
272. rnel CONFIG PHYLIB y the PHY management library provided by kernel CONFIG ETH SPEAR MACB y SPEAr MACB driver Support Doc ID 16604 Rev 2 Ty www BDTIC com ST UM0851 Communication device drivers 4 3 USB Host 4 3 1 Hardware overview Within its high speed HS connection subsystem SPEAr provides Synopsys s USB 2 0 Host fully compliant with the universal serial bus specification version 2 0 and offering an interface to the industry standard AHB bus The high speed connection subsystem in SPEAr provides in the following numbers features of USB host controllers for SPEAr 600 300 Table 19 USB host configuration in SPEAr SPEAr600 SPEAr300 Two USB hosts compatible with USB 2 0 high speed specification They can work One USB host controller compatible with USB 2 0 simultaneously either in full speed or in high high speed specification managing two ports speed mode The peripherals have dedicated channels to the The peripheral has dedicated channel to the multi port memory controller and four slave ports multi port memory controller and two slave ports for CPU programming for CPU programming The UHC supports the 480 Mbps high speed The UHC supports the 480 Mbps high speed HS for USB 2 0 through an embedded EHCI HS for USB 2 0 through an embedded EHCI host controller as well as the 12 Mbps full speed host controller as well as the 12 Mbps full speed FS and the 1 5 Mbps low speed LS fo
273. rs from being altered by runaway software Figure 59 WDT interface Watchdog timer WDT clock _ Control Load register register APB 32 bit down counter p WDT interrupt interface Interrupt and reset generation WDT reset The down counter is driven by the WDT clock which is the oscillator clock 30 MHz in SPEAr600 and 24 MHz in SPEAr3xx 9 2 2 Software overview The watchdog driver for SPEAr in the Linux support package is part of standard Linux watchdog framework Watchdog drivers in Linux are based on character device using misc device layer and provide a standard set of ioctls to the user Through this interface you can configure program and refresh the watchdog timer You can use the standard Linux watchdog daemon to configure and periodically pat refresh the driver in order to avoid System reset A software crash or hang would thus prevent this pat from happening and hence cause a system reset after timeout The following figure describes the watchdog framework 212 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Miscellaneous device drivers 9 2 3 9 2 4 4 Figure 60 WDT software architecture User space NG Ki Watchdog daemon application dev watchdog Kernel space misc dev layer Watchdog driver Hardware Watchdog timer In th
274. rs show up in the sysfs filesystem I2C chip devices can be found at sys bus i2c devices listed by their adapter address and chip address For example the eeprom driver loaded on a machine might produce the following sysfs tree structure tree sys bus i2c Sys bus i2c devices 0 0050 devices platform spear i2c 6 i2c 0 0 0050 0 0051 devices platform spear i2c 6 i2c 0 0 0051 0 0052 gt devices platform spear i2c 6 i2c 0 0 0052 0 0053 gt devices platform spear i2c 6 i2c 0 0 0053 drivers i2c adapter eeprom 0 0050 devices platform spear i2c 6 i2c 0 0 0050 0 0051 devices platform spear i2c 6 i2c 0 0 0051 0 0052 devices platform spear i2c 6 i2c 0 0 0052 0 0053 gt devices platform spear i2c 6 i2c 0 0 0053 Doc ID 16604 Rev 2 83 245 www BDTIC com ST Communication device drivers UM0851 4 5 5 84 245 This shows four different I2C chip devices all controlled by the same EEPROM driver To locate the controlling driver you can look in the sys bus i2c drivers directory or in the directory of the chip device itself and read the name file cat sys devices platform spear i2c 6 i2c 0 0 0050 name eeprom Read and write To read and write from the user space you need binary attribute The structure used for this is static struct bin attribute eeprom attr attr
275. s one millionth of a second This is how often you want the kernel to look at the CPU usage and to make decisions on what to do about the frequency If you wanted to set the sampling rate to 1 second you would set it to 1000000 like in the following example echo ondemand gt sys devices system cpu cpu0 cpufreq scaling governor echo 1000000 gt sys devices system cpu cpu0 cpufreq ondemand sampling rate show sampling rate minlmax These are the available minimum and maximum sampling rates that you may set sampling rate to To see both just do the following cat sys devices system cpu cpu0 cpufreq ondemand sampling rate min 125000 cat sys devices system cpu cpu0 cpufreq ondemand sampling rate max 125000000 up threshold This defines what the average CPU usage between the samplings of sampling rate needs to be for the kernel to make a decision on whether or not it should increase the frequency For example when it is set to its default value of 80 it means that between the checking intervals the CPU needs to be on average more than 80 in use to then decide that the CPU frequency needs to be increased To set this to something lower like 20 you would do the following echo 20 sys devices system cpu cpu0 cpufreq ondemand up threshold ignore nice load This parameter takes a value of O or 1 When set to 0 its default all processes are counted towards the cpu utilization value When set to 1 the processes that are run w
276. s a memory device like dev mem and it has the same features You can read it write it seek to some location in it and mmap it the main usage The difference is just that the memory that appears in the special file is not the whole memory but the frame buffer of the video hardware Data structures for using Framebuffer The following three structures must be understood because they are needed for any user application that uses framebuffer 1 Variable information pertaining to the video card is held in struct fb var screeninfo This structure contains fields such as the X resolution Y resolution bits required to Doc ID 16604 Rev 2 195 245 www BDTIC com ST Audio video drivers UM0851 196 245 hold a pixel pixclock HSYNC duration VSYNC duration and margin lengths These values are user programmable struct fb var screeninfo u32 xres Visible resolution in the X axis u32 yres Visible resolution in the Y axis KE uaa I u32 bits per pixel Number of bits required to hold a pixel PE auus u32 pixclock Pixel clock in picoseconds u32 left margin Time from sync to picture u32 right margin Time from picture to sync E u32 hsync len Length of horizontal sync u32 vsync len Length of vertical sync JE wew EL F 2 Fixed information about the video hardware such as the start address and size of frame buffer memory is held in struct fb
277. s device drivers UM0851 Figure 62 Duty and Period Counter clock after prescaler I Duty Period 9 3 2 Software overview The PWM driver provides a direct interface to other Linux drivers The PWM driver can be found at arch arm mach spear300 spr pwm st c Based upon input from user drivers the PWM is programmed by the PWM driver Figure 63 PWM driver architecture User drivers Kernel space Y PWM driver z mn p SHE Sas a EL Ng Hardware ST PWM 9 3 3 PWM usage in Linux The PWM can be used from the kernel level only User drivers must include include linux pwm h file to access functions exported from the PWM driver There are four channels in the PWM hardware There numbers are O 1 2 amp 3 To use the PWM channels follow the steps described below Request The user driver must request the PWM channel it wants to use This is done using the following function call Pwm id is pwm channel id can be 0 1 2 or 3 y Doc ID 16604 Rev 2 217 245 www BDTIC com ST Miscellaneous device drivers UM0851 9 3 4 218 245 Label is a string passed by user as a unique identification of user struct pwm device is local to pwm driver Its internals are not for user driver Only pointer to this must be saved for any future communication with PWM driver struct pwm device pwm request int pwm id const char label This function
278. s in the clock framework before making any transactions or plugging into the notifier lists of the CPUfreq framework The concept of notifier list has been covered later in Section 10 3 Power management API 10 3 Power management API This section describes the PM interfaces 10 3 1 PM framework API Figure 67 Linux PM framework Linux PM framework kernel power pm c Valid Prepare Enter Finish Architecture code provides states arch arm mach spearxxx pm c y Doc ID 16604 Rev 2 227 245 www BDTIC com ST Power management section UM0851 10 3 2 228 245 The architecture specific code puts the system into low power mode The architecture specific code uses the following algorithm e Register SPEAr Architecture Specific driver PM framework The Architecture layer provides the functions for entering suspend to RAM state and then waking up from sleep e Each device s driver is asked to suspend the device by putting it into a state compatible with the target system state e The DDR is put into self refresh mode The system enters a low power state depending on the mode e Wake up enabled devices usually stay partly functional in order to wake the system e The wake up is normally triggered by a GPIO Ethernet RTC interrupt This trigger generates the interrupt to wake up the system The DDR is then moved back from Self Refresh mode and the system is put back into Normal mode e When the system leaves this low power state the dev
279. s own interface For example the USB Ethernet function exposes a netdev interface the USB serial gadget exposes a tty interface and so on This makes the usage of the USB gadgets very easy You can use standard tools for standard interfaces provided by these gadgets You can find such example usage in e linux Documentation gadget printer txt for usb printer device e linux Documentation gadget serial txt for usb serial device SPEAr LSP provides a test gadget driver zero gadget to test the USB Device controller This gadget does not have any user interface It just provides two configurations source amp sink and loop back to support several test cases which can be executed from the USB Host side On USB Host corresponding to the zero gadget we have a usbtest driver which supports several test cases to validate USB through ioctls A standard application testusb is ky Doc ID 16604 Rev 2 75 245 www BDTIC com ST Communication device drivers UM0851 available on host side to execute desired test cases Please refer to the following link for details on this test setup http www linux usb org usbtest 4 4 5 USBD driver performance The driver performance was evaluated using the following setup e Host PC Linux Fedora Core11 Processor 1 GHz AMD Athlon 64 bit dual core RAM 1 GB DDR2 RAM 667 MHz Gigabit Ethernet e Target device SPEAr600 CPU 332 MHz
280. size shuffle buf cur wbuf Add code here to copy size amount of data on wbuf cur wbuf if status ioctl wfd JPEGIOC START rd 0 return 1 munmap char wbuf 0 2 wsize close wfd int main void open jpeg nodes rfd open dev jpegread O RDWR O SYNC if rfd 1 return 1 rbuf 0 unsigned char mmap 0 2 rsize PROT READ PROT WRITE MAP SHARED rfd 0 if rbuf 0 NULL return 1 rbuf 1 rbuf 0 rsize pid fork if pid 0 child jpegwrite exit 0 4 Doc ID 16604 Rev 2 161 245 www BDTIC com ST Accelerator engine device drivers UM0851 6 1 3 JPEG device driver performance The JPEG driver performance has been measured in the following environment e Hardware ARM926EJS 333 MHz SPEAr600 SPEAr300 SPEar310 and SPEAr320 evaluation boards e Kernel linux 2 6 27 Configuration options Table 43 JPEG driver configuration options Configuration option Comment CONFIG SPEAR JPEG SYN This option enables the SPEAr JPEG driver CONFIG SPEAR JPEG SYN DEBUG Hi enables debug prints in the JPEG This option must be selected for JPEG CONFIG_SPEAR_DMAC_PL080 operations This will enable the DMA driver 6 1 4 References e SPEAr JPEG Driver drivers char spr jpeg syn c drivers char spr jpeg syn h and include linux spr jpeg syn usr h 6 2 General purpose DMA DMAC driver All SPEAr MPUs are equipped with a general purpose DMA Controller which provides se
281. sking The interrupt inputs must be level sensitive active high and held asserted until the interrupt service routine clears the interrupt Edge triggered interrupts are not compatible Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Platform section Figure 4 VIC block diagram FIQSTATUS 31 0 Non vectored FIQ nVICFIQ interrupt logic Non vectored IRQ IRQSTATUS 31 0 interrupt logic Interrupt mmm VICINTSOURCE 31 0 request IRQO 9 logic ectored interrupt 0 VectAddr0 gt IRQn VectAddrn IRQ vector IRQ15 address and ectored interrupt 15 VectAddr15 priority logic nVICIRQIN VICVECTADDRIN amp VICVECTADDROUT nVICFIQIN ectAddrOut IRHQ VectAddrin HCLK HSELVIC HTRANS HRESETn HADDR 11 2 HWRITE AHB slave interface HRDATA 31 0 gt HREADYIN HWDATA 31 0 4 amp HREADYOUT HSIZE 2 0 lt lt HRESP 1 0 HPROT Control logic 3 2 2 Software overview Linux provides the generic interrupt handling layer which contributes to the complete abstraction of interrupt handling for device drivers It is able to handle all the different types of interrupt controller hardware Device drivers use generic API functions to request enable disable and free interrupts The drivers do not have to know anything about interrupt hardware details so they can be used on different platforms without code changes At Linu
282. ss than equal to size of one write buffer This can be done by writing or copying data directly to the mapped virtual memory addresses of write buffers Start encoding or decoding Once input data is written to write buffer encoding decoding can be started resumed Use the following system call to start and resume JPEG encoding decoding with new input data ioctl wfd JPEGIOC START size wfd file descriptor of write node JPEGIOC START command to start resume jpeg encoding decoding Size amount of data written on jpeg write node memory mapped for each jpeg write buffer This is a blocking system call which unblocks or returns only when encoding decoding with data supplied from current write buffer is started or an error has occurred On success zero is returned otherwise 1 is returned on error and errno is set appropriately For example total size of input data is 15 K size of each write buffer is 4 K then you need to follow these steps to pass data to JPEG 1 Set current write buffer to write bufferO 2 Write 4K data in current write buffer 3 Call JPEGIOC START ioctl with size equal to 4 K 4 Toggle current write buffer to buffer1 if current buffer is bufferO else to bufferO if current buffer is buffer1 5 Follow steps 2 3 4 two more times with size 4 K and one time with size 3 K Get encoded decoded data Once encoding decoding is started then output data must be copied from read buffer Use the following s
283. standard using an address checker statistics and control registers as well as receive and transmit blocks and a DMA interface The address checker recognizes four specific 48 bit addresses and contains a 64 bit hash register for matching multicast and unicast addresses It can recognize the broadcast address of all ones copy all frames and act on an external address match signal ky Doc ID 16604 Rev 2 55 245 www BDTIC com ST Communication device drivers UM0851 56 245 Figure 11 MACB diagram Status amp statistic registers Register APB as interface L MDIO Control registers MAC transmitter AHB DMA AHB or ASB cy interface A SMII MAC receiver External FIFO FIFO interface interface Frame filtering The statistics register block contains registers for counting various types of event associated with transmit and receive operations These registers along with the status words stored in the receive buffer list enable software to generate network management statistics compatible with IEEE 802 3 Clause 30 The control registers drive the MDIO interface setup up DMA activity start frame transmission and select modes of operation such as full or half duplex The register interface is compatible with the AMBA APB bus standard The receive block checks for valid preamble FCS alignment and length and presents received frames to the address checking block and DMA inte
284. system Size Used Avail Use Mounted on dev root 4 9M 2 5M 2 5M 503 dev 61 8M 0 61 8M 03 dev tmpfs 1 9GM 453 0M 1 5G 23 mnt tmpfs 2 0M OM 2 0M 0 tmp dev sdal 1 9GM 453 0M 1 5G 23 mnt Digital cameras can be accessed the same way as memory sticks USB communication device class CDC The USB CDC class supports a lot of communication devices including Ethernet Compile and then boot up the kernel with the options relevant to the USB Ethernet adapters enabled The options are covered in the configuration section below Plug in the USB Ethernet adapter you can then see console messages that are similar to the following Shub 1 0 1 0 over current change on prot 1 usb 1 1 new high speed USB device using spear ehci and address 2 usb 1 1 configuration 1 chosen from 1 choice eth0 register asix at usb SPEAr EHCI 1 ASIX AX88772 USB2 0 Ethernet 00 89 c8 3a 4c 0b Type in the following command and check if the device has been recognized cat proc bus usb devices Doc ID 16604 Rev 2 63 245 www BDTIC com ST Communication device drivers UM0851 64 245 Bus 01 Lev 01 Prnt 01 Port 00 Cnt 01 Dev 2 Spd 480 MxCh 0 Ver 2 00 Cls ff vendor Sub ff Prot 00 MxPS 64 Cfgs 1 Vendor 2001 ProdID 3c05 Rev 0 01 Manufacturer D Link Corporation Product DUB E100 Serial Number 000001 Ifs 1 Cfg 1 Atr 80 MxPwr 250mA If 0 Alt 0 EPs 3 Cls ff vendor specific Sub ff Prot 00 Driver asix Ad 82 I A
285. t and converting into digital When you record your voice or use a VolP solution on your computer you are using an analog to digital converter to convert your voice which is analog into digital information Digital information is not only restricted to computers When you talk on the phone for example your voice is converted into digital at the central office switch if you use an analog line or at you home if you use a digital line like ISDN or DSL since your voice is analog and the communication between the phone switches is done digitally SPEAr includes an Analog to Digital Converter ADC which is connected to the APB bus It is a successive approximation ADC and its main features are e 10 bit resolution e 8 analog input AIN channels ranging from O to 2 5 V e For each input the number of samples to be collected for average calculation can be one no average or up to 128 as 2 s power 2 4 8 e Normal or enhanced mode In normal mode a single conversion is perfomed on one channel In enhanced mode the ADC converts the selected channels continuously inserting a selectable amount of time between two conversions e Positive and negative reference voltages can be supplied by dedicated pins to select different conversion range Default O 2 5V Software overview The ADC can be accessed from two levels in Linux e From the user level by operating on nodes created for ADC channels e From other kernel modules The
286. t application image from memory bootm 0x1600000 Environment variable commands Table 6 Environment variables U Boot commands Command Behavior Example echo abcd abcd echo Echo args to console uns amp bootdelay 1 printenv Print environment variables ho bootcmd Run commands in an environment uS run commands Mam environne bootm 0xf8050000 variable run bootcmd Save environment variables to saveenv persistent storage setenv Set environment variables Serial i f commands Table 7 Serial i f file loading U Boot commands Command Behavior Example coninfo Print console devices ad information Coninfo loads Load S record file over serial line loads 0x1300000 Load binary file over serial line loady 0x1300000 loady ymodem mode Load binary file over serial line Kermit 1oadb 0x1300000 loadb mode saves Save S Record file over serial line Doc ID 16604 Rev 2 a www BDTIC com ST UM0851 Boot loader overview Miscellaneous commands Table 8 Miscellaneous U Boot commands Command Behavior Example reset Resets the CPU crc32 Crc32 checksum calculation crc32 0x1300000 0x10000 echo abcd abcd echo Echo args to console echo bootdeiay 1 setfreq cpu 300 Change ddr cpu frequency CPU frequency changed to 300 This command actually assumes that S rhe PELI freguengy setfreq CPU is running on PLL1 and DDR on setfreg ddr 3
287. t function only for those i2c addresses and the adapter id that actually have a device on them unless a force parameter was used Ignore List of adapter address pairs not to scan These addresses are Never probed Forces Contains list of valid address along with there adapter id The first value is a bus number adapter id the second is the I2C address A device is blindly assumed to be on the given address no probing is done Chip detection In the chip driver when an I2C chip device is found the function chip detect is called by the 12C core This function is declared with the following parameters static int eeprom detect struct i2c adapter adapter int address int kind The adapter variable is the I2C adapter structure on which this chip is located The address variable contains the address where the chip was found and the kind variable indicates what kind of chip was found The kind variable usually is ignored but some I2C chip drivers support different kinds of I2C chips so this variable can be used to determine the type of chip present Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers This function is responsible for creating a struct i2c client structure that will be registered with the I2C core The I2C core uses that structure as an individual I2C chip device To create this structure the eeprom detect function is used struct i2c c
288. t occurred while the command was executing without attempting to parse the response This function is used to configure the SDIO host controller Please use the struct mmc command in the include linux mmc core h file to see all the configuration options host MMC host to start command cmd MMC command to start retries maximum number of retries int mmc wait for cmd struct mmc host host struct mmc command cmd int retries e Send request This function starts a new MMC custom command request for a host and waits for the command to be completed It sends data using data commands It does not attempt to parse the response You can use it for any kind of data transfer with the SDIO SD MMC card using the SDIO host controller host MMC host to start command mrq MMC request to start void mmc wait for req struct mmc host host struct mmc request mrq struct mmc request struct mmc command cmd struct mmc data data struct mmc command stop void done data completion data void done struct mmc request completion function e Settimeout for data command This function sets the timeout for a data command It computes the data timeout parameters according to the correct algorithm related to the card type data data phase for command card MMC card associated with the data transfer void mmc set data timeout struct mmc data data const struct mmc card card e Set clock This function se
289. t splits 32 bit or 16 bit EMI accesses to 8 bit EMI accesses Finally it returns to SVC mode reloading the SVC registers This part of the driver is ported from the Linux kernel In U Boot the common Flash Interface driver can support the AMD Intel and ST NOR Flash command sets It tries to automatically detect the bandwidth of the controller and the external device and the number of external devices installed by polling from 8 bits x 8 bits single to 64 bits x 64 bits single In the Linux kernel the current MTD partition table and resource table for parallel NOR Flash are static struct mtd partition emi norflash partitions name xloader offset 0 size 0x00020000 mask flags 0 3 name u boot offset 0x00020000 size 0x00060000 mask_flags 0 rs name kernel offset 0x00080000 size 0x00300000 mask flags 0 Xs name rootfs static struct mtd partition emi norflash partitions name xloader offset 0 size 0x00020000 mask flags 0 3 name u boot offset 0x00020000 size 0x00060000 mask flags 0 ty name kernel offset 0x00080000 size 0x00300000 q Doc ID 16604 Rev 2 141 245 www BDTIC com ST Non volatile memory device drivers UM0851 mask flags 0 j name rootfs offset 0x00380000 size 0x00500000 mask_flags p name userspace offset 0x00880000 size
290. ta copied by the DMA driver and how many channels each CPU is using Doc ID 16604 Rev 2 169 245 www BDTIC com ST Accelerator engine device drivers UM0851 170 245 Terminate DMA transfer In some cases DMA transfer has to be stopped due to some error condition occurring in the client driver This can be done using the following function It can t be called directly call it using chan pointer chan device device terminate all chan void device terminate all struct dma chan chan Client un registration After all the transfers are over the client must free the channels so that they can be used by some other user For this client must un registered itself This can be done by the following call dma async client unregister amp dma client1 This will call dma event with status parameter set as DMA RESOURCE REMOVED DMA usage example The following example transfers 100 bytes from memory to the tx register of the skull driver include linux spr dmac p1080 h struct dma chan chan static int src buf 100 struct scatterlist sg u32 sg len dma cookie t cookie struct dw dma slave dma slave Src master DMA MASTER MEMORY dest master DMA MASTER SKULL Slave tx reg dma addr t skull tx reg Slave rx reg dma addr t skull rx reg Slave reg width DMA SLAVE WIDTH 32BIT cfg DWC CFG FLOW CTRL DMA MEMORY TO PERIPHERAL DWC CFG DEST RQID DMA REQ SKULL TX ctl DWC CTL USER M
291. tecture liliis elei 145 NOR memory performance rrr 150 JPGC block diagram hr 153 JPEG driver framework 154 DMAC block diagram rre 163 DMA software architecture nh 164 DMA speed at different burst size unanunua ee 173 Interfacing between CLCD panel and SPEAr cee eee 174 Touchscreen software architecture ree 175 State machine of touchscreen driver eee 176 Keypad driver architecture overview llle 180 Doc ID 16604 Rev 2 11 245 www BDTIC com ST List of figures UM0851 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 12 245 ADC block diagram hr 184 ADC driver architecture RR RR RR eee eens 185 Block diagram of CLCD controller 0 0 0 191 CLCD software architecture RR RR RR R nn 192 Framebuffer layer of Linux hr 193 T DM Gell te geprinte a dew eur AAP 199 TDM Waveltoltms aseae ace E EROR X RUE 4 AC POE CR GR A Ee GU RGOR GU WO ea 3 GO por FOROR EC 199 TDM driver architecture e rns 200 GPIO block diagram RR mh 206 GPIO driver architecture llle RR RR RR RR Ren 208 WDT interface usa uc wu che DE Gu paa Edw e EN wee ea wee RU COXUC E Ge Y E Re
292. terface signals to a specified number of HCLK cycles The Control register provides information about the peripheral connected When a write operation to the peripheral is requested then an AHB write operation is initiated Similarly for a read operation an AHB read is done The EMI supports 8 bit 16 bit and 32 bit peripherals The following table lists the transactions supported by EMI Table 40 Supported transactions Peripheral connected AHB access Support 32 bit 32 bit Yes 32 bit 16 bit Yes 32 bit 8 bit Yes 16 bit 32 bit No AHB Error Interrupt 16 bit 16 bit Yes 16 bit 8 bit Yes Doc ID 16604 Rev 2 139 245 www BDTIC com ST Non volatile memory device drivers UM0851 5 2 2 140 245 Table 40 Supported transactions Peripheral connected AHB access Support 8 bit 32 bit No AHB Error Interrupt 8 bit 16 bit No AHB Error Interrupt 8 bit 8 bit Yes For transactions that are not supported an AHB Error is generated on the bus and an interrupt is raised The interrupt flag can be checked in the IRQ register The data phase the data bus along with the control signals is extended until the EMI ACK is asserted low by the external peripheral If this feature is not used depending on the configuration in the Ack reg this signal is ignored Software overview The EMI driver handles the initialization and timing settings for the EMI controller The parallel N
293. tes sflash ids nor chip l sectorsize spear snor erase spear snor read Spear snor write mtd size mtd erasesize mtd erase mtd read mtd write Read Write and Erase operations on serial NOR Flash are simple and are controlled using the SMI The SMI clock is enabled just before starting any of these operations and disabled just after completion The NOR Flash device driver populates the struct mtd info to MTD layer by calling these routines err add mtd partitions amp mtd mtd partition table total num of mtd partitions else err add mtd device amp mtd Standard serial NOR partitioning Partitioning can be done by two ways static or dynamic To divide the device into static partitions define a partitioning scheme in the NOR driver like a table drivers mtd devices spr_nor_st h define NUM_PARTITIONS 4 static struct mtd_partition stwsf_par_info_primary name XLoader offset 0x00000000 size 0x00010000 Js name UBoot offset 0x00010000 size 0x00040000 name Kernel offset 0x0050000 size 0x002c0000 Js name Root File system offset 0x00310000 Size 0x004F0000 a Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Non volatile memory device drivers 5 3 4 5 3 5 The offset of any partition is in multiples of the sector size of NOR Flash While modifying the static partition table you should take care of this to avoid getting warning messages
294. the SPEAr LSP Table 35 CAN menuconfig kernel options Configuration option Comment CONFIG CAN CCAN Bosch C CAN device CONFIG CAN SPEAR SPEAr CAN device driver CONFIG CAN CAN support in linux kernel CONFIG CAN RAW Raw CAN Protocol raw access with CAN ID filtering CONFIG CAN BCM Broadcast Manager CAN Protocol with content filtering Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers Table 35 CAN menuconfig kernel options continued CAN DEV Enables the common framework for platform CAN drivers with B Netlink support This is the standard library for CAN drivers CAN VCAN Virtual Local CAN interface 4 9 8 References Socket CAN project http developer berlios de projects socketcan 4 10 HDLC driver 4 10 1 Hardware overview SPEAr310 has one TDM E1 HDLC controller and two RS485 HDLC controllers TDM E1 HDLC controller The TDM E1 HDLC controller supports up to 128 HDLC channels multiplexed on one single TDM interface The main features provided by the TDM E1 HDLC controller are listed below General IP features e AMBA 2 0 compliant AMBA slave interface for programming the controller AMBA master interface for transferring data between memory and IP e DMA engine included e Support data buffer queue e Support interrupt queue e Miscellaneous interrupt generation TDM E1 features e Six signals interface TXCLK RXCLK TXD RXD TSYNC RSYNC e Supports duplex T
295. this way the device driver tells the other parts of the input systems what it is and what events can be generated or accepted by this input device The touchscreen driver enables the Touch and X Y coordinate information to send to the user application via the input device input dev evbit 0 BIT MASK EV KEY BIT MASK EV ABS input dev keybit BIT WORD BTN TOUCH BIT MASK BTN TOUCH Then the driver registers the input device structure by calling input register device struct input dev input input register device input Registration of the device adds the input structure to the linked lists of the input driver and calls the modules connect functions in the device handler to tell them that a new input Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Human interface device HID drivers device has appeared Input register device may sleep and therefore must not be called from an interrupt or with a spinlock held When a press occurs on the panel screen the driver reports it via the input report key call to the input system The value is interpreted as a truth value any nonzero value means key pressed zero value means key released The input code generates events only if the value is different from the previous one Coordinates are reported using the input report abs call The input sync call can be used to tell those who receive the events that we ve sent a complete report This ma
296. timer GPT driver a 25 3 1 1 Hardware overview 00000 cece en 26 3 1 2 Software overview 0 er 26 3 1 3 GPT driver usage 1 n 29 3 2 Vector interrupt controller VIC driver a 31 3 2 1 Hardware overview 0 en 32 3 2 2 Software overview er 33 3 2 3 VIC API high level IRQ flow handlers in SPEAR 36 3 2 4 The internals of interrupt handling in ARM Less 36 3 2 5 VIC USAGE svo serbe daadaa sai gei peg heehee a seed hee beg 37 3 3 Real time clock RTC driver 0 000 cece eee 38 3 3 1 Hardware overview cece en 38 3 3 2 Software overview ere 39 3 3 3 RTC driver usage llleselseesee ln 42 3 3 4 References rn 42 4 Communication device drivers luee s 43 4 1 GMAC Ethernet driver llle 43 4 1 1 Hardware overview eee 43 4 1 2 Software overview ee eee eens 44 4 1 3 GMAC API uid aoo e x RR LAGING E ER NT RS els Re a 45 2 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Contents 4 1 4 Concept of socket buffers ses 49 4 1 5 GMAC driver usage 2 ees 50 4 1 6 GMAC driver performance ees 52 4 2 MACB MAG block diver z uuu GANA KIA HAD sah GI KAL A KARA 55 4 2 1 Hardware overview 0 nn 55 4 2 2 Software overview 0 er 57 4 2 3 MACB driver interface ree 57 4 2 4 Socket buffer man
297. tion device drivers UM0851 dev hard start xmit spear eth start xmit dev set multicast list spear eth set multicast list dev 5change mtu amp spear eth change mtu dev gt dev_addr 0 5 MAC ADDRESS The private data structure use by the driver is struct spear eth priv li struct dma mac descr txd table struct dma mac descr rxd table dma addr t dma tx descrp dama addr t dma rx descrp volatile unsigned int rx curr descr num volatile unsigned int tx curr descr num volatile unsigned int tx prev descr num volatile signed int tx mac win size int tx ring count int rx ring count spinlock t eth lock struct tasklet struct rx tasklet struct tasklet struct tx tasklet struct timer list tmr hotplug MII interface info struct mii if info mii OS defined structs struct net device dev struct platform device pdev struct net device stats stats uint32 t gotcl RX uint64 t hw csum err uint64 t hw csum good uint32 t gorcl struct spear hw stats hw stats struct mii phy phy u8 spr dma rx abnorm struct clk spear eth clk int rx skb size int rx sync size struct resource res PHY framework for SPEAr The PHY abstraction layer in SPEAr provides a generic interface to support different PHYs The interface is defined as spear mii phy probe struct mii phy phy u8 address It is used to probe for the PHY addresses from 0 31 across the set
298. tion memory e Multiple RxFIFO controllers supported for each OUT endpoint This gives flexibility in configuring different FIFO sizes for each endpoint Doc ID 16604 Rev 2 69 245 www BDTIC com ST Communication device drivers UM0851 Figure 15 USBD interface External RAM IN Endpoints t NEN READ Port WRITE Port A EPFIFO EPFIFO EP FIFO gt CNTRLI CNTRL2 CNTRUV AHB aye TAK x Slave Only m Memory SOF i x Interface E ULPI Tracker I z gt Or 8 BP UDC20 la USB 2 0 UTMI UTLI t i UDcvci Hp EE USB 11 Control amp Status m PA Winstel Trans 4 Registers Th ARM ceiver Interrupt F Manager CSR Slave ii Access Receive FIFO Controller s Io Interrupt WRITE Port READ Port External RAM OUT Endpoints SL 4 4 2 Software overview There is wide variety of USB Devices available in the market General examples of these devices are USB Ethernet adapters USB audio devices USB mass storage devices USB printers etc In the Linux USB world these functions are called gadgets You can use SPEAr USBD to build any of these functions You can also build a device with multiple functions
299. tmask Choose from Such as Direct IO is possible eXecute In Place possible Out of band data NAND flash and Device capable of automatic ECC loff t size Total size in bytes Doc ID 16604 Rev 2 125 245 www BDTIC com ST Non volatile memory device drivers UM0851 126 245 li u long erasesize Size in bytes of the erase block of this memory device the smallest area which can be erased in a single erase command u long oobblock u long oobsize Some memory technologies support out of band data for example NAND flash has 16 extra bytes per 512 byte page for error correction or metadata oobsize and oobblock hold the size of each out of band area and the number of bytes of real memory with which each is associated respectively As an example NAND flash would have oobblock 512 and oobsize 16 to show that it has 16 bytes of OOB data per 512 bytes of flash u long ecctype Some hardware not only allows access to flash or similar devices u long eccsize but also has ECC error correction capabilities built in to the interface The eccsize holds the size of the blocks on which the hardware can perform automatic ECC int erase struct mtd info mtd struct erase info instr This routine adds a struct erase info to the erase queue for the device This routine may sleep until the erase had finished or it may simply queue the request and return immediately The struct erase info contains a p
300. tr 03 Int MxPS 8 Ivl 128ms Ad 81 I Atr 02 Bulk MxPS 512 Ivl 0ms Ad 03 O Atr 02 Bulk MxPS 512 Ivl 0ms Ej Ej Ej k9s0ounuu t ud The functionality could be checked by assigning the IP and then test a simple ping operation ifconfig eth0 192 168 1 11 eth0 link up 100Mbps full duplex lpa 0xcdel eth0 linkup 100Mbps full duplex lpa 0xcdel a Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Communication device drivers USB human interface device HID class The USB HID class describes human interface devices such as keyboard and mice q USB mouse Compile and then boot up the kernel with the options relevant to the USB mouse enabled The options are covered in the configuration section below Plug in the USB mouse You can then see print output messages that are similar to the following hub 1 0 1 0 over current change on prot 1 usb 3 1 new low speed USB device using spear ohci and address 3 usb 3 1 configuration 1 chosen from 1 choice input USB Optical Mouse as class input input2 input USB HID v1 11 Mouse USB Optical Mouse on usb spear ohci 0 1 Type in the following command to check if device has been recognized cat proc bus usb devices T Bus 03 Lev 01 Prnt 01 Port 00 Cnt 01 Dev 3 Spd 1 5 MxCh 0 D Ver 2 00 Cls 00 gt ifc Sub 00 Prot 00 MxPS 8 Cfgs 1 P Vendor 0461 ProdID 4d15 Rev 2 00 S Product USB Optical Mouse C Ifs 1 Cfg 1 Atr a0 MxPwr
301. tree The pseudo control structure can be used to override the CPU frequency values that have been configured at the boot time This structure is used by the Middle Management Layer to register into the clock framework and use the interfaces provided by the clock framework to change the CPU frequency struct clk virt mpu pm ck name virt mpu pm ck parent amp mpu ck flags CLOCK IN SPEAR ALWAYS ENABLED VIRTUAL CLOCK RATE PROPAGATES recalc amp spear mpu clk table recalc round rate amp spear round to table rate set rate amp spear select table rate Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Power management section The call back functions defined in the structure above are spear round to table rate This function looks for the rate equal to or less than the target requested rate and returns the rate to the middle management layer e spear select table rate This function configures the rate based on the target requested rate The clock rate is strictly monitored to be in the range of frequencies that have been defined in the arch code i e 166 MHz 266 MHz 333 MHz After the checks the PLL 1 is reconfigured for the desired frequency value The new frequency is then iterated through the clock dependency tree and all the drivers get to know the information either by voluntarily calling the clk get rate function
302. ts the host clock to the highest possible frequency that is below hz 96 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Communication device drivers 4 7 4 host MMC host to start command hz requested frequency void mmc set clock struct mmc host host unsigned int hz e Setdata bus width This function sets the data bus width of a host host MMC host to start command width requested bus width it can be one of MMC BUS WIDTH 1 or MMC BUS WIDTH 4 void mmc set bus width struct mmc host host unsigned int width e Free host After the card has finished working with the host controller it should free the host This can be done using following the call host MMC host to free void mmc release host struct mmc host host e Driver un registration The card driver must un register itself after its usage is over This can be done using the following function Drv MMC media driver int mmc unregister driver struct mmc driver drv SDIO host controller driver performance The performance measurement has been performed using e Hardware ARM926EJS 333MHz SPEAr300 boards e Kernel linux 2 6 27 Doc ID 16604 Rev 2 97 245 www BDTIC com ST Communication device drivers UM0851 4 7 5 Configuration options Table 31 SDIO configuration options Configuration option Comment CONFIG MMC This option enables MMC framework support in Linux CONFIG MMC BLOCK Th
303. turned and errno is set appropriately These file descriptors can be used for any further communication with the JPEG device Set source image size The JPEG driver must be told in advance the size of the input data required by hardware Use the following system call to set the input data size ioctl wfd JPEGIOC SET SRC IMG SIZE size wfd file descriptor of jpeg write node JPEGIOC SET SRC IMG SIZE ioctl command for setting input data size Size size of source image in bytes Doc ID 16604 Rev 2 155 245 www BDTIC com ST Accelerator engine device drivers UM0851 On success zero is returned otherwise on error 1 is returned and errno is set appropriately After completion of processing if user needs to encode decode another image then user don t have to close JPEG nodes de allocate buffer memory and open the nodes again User can simply call this function again with size of new input data This resets complete JPEG system software and hardware Set JPEG Info JPEG can perform four types of operations They are e Encoding with header processing EWH Output JPEG image will have header as part of image e Encoding without header processing EWOH Output JPEG image will not have header as part of image e Decoding with header processing DWH Input JPEG image will have header as part of image e Decoding without header processing DWOH Input JPEG image will not have header as part of image You need
304. two layers a hardware independent top layer char driver that implements the kernel RTC API and a hardware dependent bottom layer driver that communicates with the underlying bus The SPEAr RTC driver is located in linux drivers rtc spr rtc st c Doc ID 16604 Rev 2 39 245 www BDTIC com ST Platform section UM0851 Note 40 245 Figure 6 RTC software system architecture dev rtc Kernel space Linux RTC Class RTC driver Hardware RTC hardware To get access to the real time clock you need to create a character special file dev rtc with major number 10 and minor number 135 An RTC Class framework is defined to support several different RTCs It offers three different user space interfaces e dev tcN much the same as the older dev rtc interface e sys class rtc rtcN sysfs attributes support read only access to some RTC attributes e proc driver rtc the first RTC rtcO may expose itself using a proc fs interface The kernel has a dedicated RTC subsystem providing the top layer char driver and a core infrastructure that bottom layer RTC drivers can use to tie in with the top layer The main components of this infrastructure are the rtc class ops structure and the registration functions rtc device registerlunregister Bottom layer RTC drivers scattered under different bus specific directories are unified with this subsystem under drivers rtc Linux RTC class interface struct rtc class
305. uffer layer 192 8 1 4 How to support a new CLCD panel 2 0c eae nee 195 8 1 5 CLCD driver usage 2 ren 195 8 1 6 Kernel configuration options a 197 8 1 7 Referentes cesset onc d A ER WG PENA KAMANG E SR AER 198 8 2 NOMINEE crc seeded ureters ue hoes Kets eae eee see 198 8 2 1 Hardware overview 000 cece 198 8 2 2 Software overview ssas asaurar ene eens 199 8 2 3 TDM layer interface 0 0 eee 200 8 2 4 Configuration options 0000 ee 205 8 2 5 References ipad PA nana iBA to tat Raa dees a eee 205 8 3 USB audio device class support a 205 9 Miscellaneous device drivers cece ee eee eee 206 9 1 General purpose I O GPIO driver a 206 9 1 1 Hardware overview 2 nes 206 9 1 2 Software overview n 208 9 1 3 GPIO usage in user mode 2 0 209 9 1 4 GPIO usage in kernel mode lees 209 9 1 5 GPIO in interrupt mode 2 210 9 1 6 Configuration options eh 211 9 2 Watchdog WDT driver 00 c eee ee 211 9 2 1 Hardware overview 00 cece 211 9 2 2 Software overview 0 eee eee eens 212 9 2 3 Watchdog device driver interface with misc device layer 213 9 2 4 Watchdog driver usage eee 213 9 2 5 Configuration options eren 215 9 2 6 References nnn 215 9 3 Pulse width modulator PWM driver 00000 215 9 3
306. ut for SPEAr300 the maximum MTU size is kept at 9000 The advantage of using bigger MTU size can be estimated from the fact that smaller frames usually mean more CPU interrupts and more processing overhead for a given data transfer size Often the per packet processing overhead sets the limit of TCP performance in the LAN environment The experiments results obtained above prove that the jumbo frames provided 5096 more throughput with 5096 less CPU load than 1500 byte frames Checksum offloading during reception Checksum offloading is used to relieve the kernel and thus the CPU from the burden of calculating transport PDU checksums TCP and UDP checksums when the SPEAr MAC hardware can perform these calculations itself As it can be seen in the results above when the checksum offloading is enabled the reception performance has increased by almost 60 Mbps CRC stripping This option enables GMAC to strip the PAD FC S on the incoming frames only when the length of the frame is less than or equal to 1500 bytes The results show that enabling this particular option does not impact the performance significantly as the execution time for the same option in the software is also on the lower side Kernel configuration options Below is a list of the kernel configuration options supported by the driver using make menuconfig Table 16 8 Menuconfig options CONFIG NET ETHERNET Kernel networking support Configuration options Comment CON
307. v 2 243 245 www BDTIC com ST Revision history UM0851 Revision history 244 245 Table 69 Document revision history Date 08 Jan 2010 Revision 1 Changes Initial release 21 May 2010 Replaced LSPv2 2 by LSPv2 3 Updated Section 8 1 3 CLCD device driver interface with framebuffer layer Corrected first row of Table 51 CLCD configuration options Corrected link in Section 5 4 USB mass storage support Removed occurences of the 12S feature when applicable Updated Section 6 1 JPEG driver Updated Section 6 2 3 DMA device driver performance Section 5 1 6 NAND device driver performance Section 5 3 6 Serial NOR device driver performance Added Section 4 1 6 GMAC driver performance Section 4 3 4 USB Host performance Section 4 4 5 USBD driver performance Section 4 5 5 I2C driver performance Minor format changes a Doc ID 16604 Rev 2 www BDTIC com ST UM0851 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services
308. ve are in Mbps Figure 9 Ethernet performance evaluation results Checksum offloading disabled 4500 4000 3500 RX ChkSumOff Disabled CRC Strip 3000 Disabled o TX ChkSumOff a as Disabled CRC Strip E 2000 Disabled z te RX ChkSumOff 1500 Disabled CRC Sirip Enabled 1000 TX ChkSumOff 500 Disabled CRC Strip Enabled Performance in Mbps Figure 10 Ethernet performance evaluation results Checksum offloading enabled 4500 4000 3500 RX ChkSumOff Enabled CRC Strip N 3000 Disabled o 8 TX ChkSumOff E o Enabled CRC Strip 2000 Disabled A RX ChkSumOff 1500 Enabled CRC Strip Enabled 1000 TX ChkSumOff Enabled CRC Strip 500 Enabled 0 0 200 400 600 Performance in Mbps 4 Doc ID 16604 Rev 2 53 245 www BDTIC com ST Communication device drivers UM0851 54 245 The data shown above is a result of the following configuration features supported by the driver Jumbo frames Since its creation around 1980 Ethernet has used 1500 byte frame sizes To maintain backward compatibility 100 Mbps Ethernet used the same size and today standard gigabit Ethernet also uses 1500 byte frames This is so a packet to from any combination of 10 100 1000 Mbps Ethernet devices can be handled without any layer two fragmentation or reassembly Jumbo frames extends Ethernet to 9000 bytes For SPEAr600 the maximum MTU size has been limited to 4000 b
309. veral DMA channels that can be used to off load the CPU from some of the memory copying tasks This section describes the details of the DMAC driver 6 2 1 Hardware overview Direct memory access DMA allows certain subsystems within the SPEAr MPU to access system memory for reading and or writing independently of the CPU and to transfer data without subjecting the CPU to a heavy overhead 162 245 Doc ID 16604 Rev 2 KY else if pid 0 parent f jpegread wait 0 else failed to fork printf Cant create child n exit 1 www BDTIC com ST UM0851 Accelerator engine device drivers Figure 42 DMAC block diagram DMACCLR 15 0 AHB Master 1 DMACTC 15 0 Channelo DMA request and response DMACSREQ 15 0 block DMACBREQ 15 0 DMACLSREQ 15 0 DMACLBREQ 15 0 im ad Channel1 AHB bus AHB slave interface Bi Channel7 Internal arbiter AHB Master 2 Internal arbiter The SPEAr family uses the ARM PL080 DMA controller which is connected to the AHB bus Its main features are Eight DMA channels Each channel can support a unidirectional transfer 16 DMA requests The DMAC provides 16 peripheral DMA request lines Single DMA and burst DMA request signals Each peripheral connected to the DMAC can assert either a burst DMA request or a single DMA request You set the DMA burst size by programming the DMAC Memory to memory memory to peripheral pe
310. w memory write fill nand NAND sub system nboot boot from NAND device nfs boot image via network using NFS protocol nm memory modify constant address 16 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Boot loader overview ping send ICMP ECHO REQUEST to network host printenv print environment variables protect enable or disable FLASH write protection rarpboot boot image via network using RARP TFTP protocol reset Perform RESET of the CPU run run commands in an environment variable saveenv save environment variables to persistent storage saves save S Record file over serial line setenv set environment variables setfreq change ddr cpu frequency Sleep delay execution for some time tftpboot boot image via network using TFTP protocol version print monitor version writemac write mac address in I2C memory Commands can be grouped into the following categories according to their function Informative commands This group of commands is used to get runtime information concerning the system itself For example using the bdinfo command you can retrieve the XLoader image revision Table 1 Informative U Boot commands Command Behavior Example spear600 bdinfo arch number 0x000008BC env t 0x00000000 Print board info structure boot params 0x00000100 Along with other things this structure DRAM bank 0x00000000 also contains gt start 0x00000000 b
311. w BDTIC com ST Miscellaneous device drivers UM0851 Figure 61 below shows three different PWM signals Figure 61 a shows a PWM output ata 10 duty cycle That is the signal is on for 10 of the period and off the other 90 Figure 61 b and c show PWM outputs at 5096 and 9096 duty cycles respectively These three PWM outputs encode three different analog signal values at 1096 5096 and 9096 of the full strength If for example the supply is 9 V and the duty cycle is 10 a 0 9 V analog signal results Figure 61 PWM output with a 10 b 5096 and c 90 duty cycle On high level Off low level 10 a 50 b 90 c SPEAr320 contains a PWM IP with four independent channels PWM1 PWM2 and PWM3 PWMA All four channels are functionally identical Using a 16 bit counter each PWM channel generates a rectangular output pulse with programmable duty factor O to 10096 and frequency Features of SPEAr320 PWM Four independent PWM channels Prescaler to define the input clock frequency to each timer Programmable duty factor from O to 10096 Programmable pulse frequency or period APB clock PCLK 83 MHz as the source clock for prescaler The relationship of duty to period is described in the following figure 216 245 Doc ID 16604 Rev 2 ky www BDTIC com ST Miscellaneou
312. ware overview SPEAr300 has a GPIO keypad block which is a two mode input and output port In summary it provides e 18 bit general purpose parallel port with input or output single pin programmability e 81 key keypad 9x9 matrix The selection between the two modes is a programmable bit The mode control bits in the mode control register must be set to 00 to enable the keypad mode When the keypad mode is selected it is possible to read the value of the externally connected keyboard scanned at programmed rate The keypad may contain up to 81 keys Eighteen 18 port pins provide a 9x9 scanning matrix Nine 9 of the pins are strobes and nine 9 of the pins are inputs The circuitry scans the keys at a rate of 10 20 40 or 80 ms controlled by the software Two successive cycles are needed to validate a key Only one key is allowed to be down in a scan cycle Each valid key condition causes the value of the key to be written to a register and an interrupt to be set The key value is coded on eight bits The lower nibble refers to the column number 0 1 2 8 while the higher nibble gives the row number 0 1 2 8 of the pressed key Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Human interface device HID drivers Control Register bits b3 and b2 determine the keypad scanning rate Each time the timer count expires the keypad is scanned If only one key
313. which large files of sequential data need to be loaded into memory quickly and replaced with new files repeatedly The FSMC flexible static memory controller controls the NAND Flash in the SPEAr platform The main features of the FSMC are e t provides programmable timings to support a wide range of devices It supports programmable wait states bus turn around cycles as well as output enable and write enable delays e Itprovides an interface between the AHB system bus and Nand Flash memory devices It can do the ECC calculation for the NAND Flash e When using the FSMC wait feature the controller waits for the NAND Flash to indicate that it is ready For this the ready busy pin of the NAND Flash should be connected to the FSMC wait pin and then the wait bit should be enabled in the control register Doc ID 16604 Rev 2 123 245 www BDTIC com ST Non volatile memory device drivers UM0851 Figure 31 Interface between FSMC and NAND Flash EN Chip Select E FSMC A NAND Flash AHB Data Interface Address Control Bus NG FSMC Wait Ready Busy AHB 5 1 2 Software overview The NAND device driver sits on top of the FSMC and provides all the necessary functions for a file system via the standard Linux MTD interface NAND device driver controls the functionality of FSMC by using the API of FSMC driver Figure 32 NAND software system architecture User space Applic
314. wo types of platform information e Controller data this is required by the SPI controller driver This structure is controller driver specific and for adding a new slave device it must be supplied to be implemented if chip select is configurable Currently it is automatically given static void spidev chip select u32 command f struct spear spi chip is present in drivers spi spr ssp pl1022 h static struct spear spi chip m25 hw Interface MOTOROLA SPI framework supports only MOTOROLA SPI cs control m25 chip select Slave driver provides cs control function and this function must enable or disable chip select of the slave chip dma burst size BURST SIZE 1 framework Dma burst size supported by SPI slave chip supports e Platform data this is defined and required by the slave driver The driver can keep important data here for programming the slave device static struct spi eeprom m25 info byte len 1024 1024 name m25 page size 256 sector size 0x10000 flags EE ADDR3 i These two structures are added to struct spi board info which is registered with the kernel struct spi board info is declared by the Linux SPI framework You must create an instance of this structure for every device which will use the SPI framework Doc ID 16604 Rev 2 89 245 www BDTIC com ST Communication device drivers UM0851 Note 90 245 struct spi board info can be initialized as
315. x html e MTD source code under directory drivers mtd nand for Linux 2 6 27 e SPEAr NAND Flash device driver drivers mtd nand spr nand st c e http www linux mtd infradead org index html By default the FSMC s wait feature is enabled When the wait feature is enabled the FSMC Controller does not acknowledge any AHB read write transaction until the NAND ready busy signal indicates that the device is ready So if a particular software program is accessing in either read or write the NAND device the system becomes completely unresponsive to external interrupt events both IRQ and FIQ for a few tens of microseconds the ARM core is in a frozen state waiting for the completion of a r w LDR instruction For specific applications that require hard real time interrupt latency this behavior must be avoided In such cases it is desirable to disable the wait feature of the FSMC controller and connect the NAND ready busy signal directly to a SPEAr GPIO pin which needs to be monitored by implementing the Device Ready function in the NAND device driver The function has no arguments and should return O if the NAND device is busy R B pin is low and 1 if the NAND device is ready R B pin is high If the hardware interface does not Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Non volatile memory device drivers 5 2 5 2 1 give access to the Ready Busy pin then the function must not be defined and the function pointer dev r
316. x level there are three main levels of abstraction in the interrupt code e High level driver API e High level IRQ flow handlers e Chiplevel hardware encapsulation Interrupt control flow Each interrupt is described by an interrupt descriptor struct irg desc The interrupt is referenced by an unsigned int numeric value which selects the corresponding interrupt 4 Doc ID 16604 Rev 2 33 245 www BDTIC com ST Platform section UM0851 34 245 description structure in the descriptor structures array The descriptor structure contains status information and pointers to the interrupt flow method and the interrupt chip structure which are assigned to this interrupt Whenever an interrupt triggers the low level arch code calls into the generic interrupt code by calling desc 5hanale irq This high level IRQ handling function only uses desc gt chip primitives referenced by the assigned chip descriptor structure The details of these primitives are covered in later sections struct irq desc irq flow handler t handle irq struct irq chip chip struct msi desc msi desc void handler data void chip data struct irqaction action IRQ action list unsigned int status IRQ status unsigned int depth nested irq disables unsigned int wake depth nested wak nables unsigned int irq count For detecting broken IRQs unsigned int irgs unhandled unsigned long last unhandled Aging timer for unha
317. y governor min max shall be set this policy must be validated so that incompatible values can be corrected e Target The target call has three arguments struct cpufreq policy policy unsigned int target frequency unsigned int relation The CPUfreq driver sets the new frequency when called here Apart from the change in frequency the driver must also notify into Doc ID 16604 Rev 2 231 245 www BDTIC com ST Power management section UM0851 232 245 the Transition Notifier in the CPUfreq core so that the drivers listed in the CPUfreq transition notifier lists are informed of the change The kernel also provides a notification list in the CPUfreq framework that the device drivers can register into This notification list is called as Transition Notifier being used in Ethernet driver for reference The drivers impacted on CPUfreq change are notified twice when the CPUfreq driver switches the CPU core frequency and this change has any external implications on the drivers The calls are made before and after the frequency change to allow the drivers to judge the impact of the change Device driver perspective The architecture supports devices which have their clocks either functional or interface clocks running on the same system clock PLL 1 as the CPU Below is a list of devices which could be impacted by a change of frequency and any required actions that are handled by the drivers 1 CLCD The current implem
318. y interacts with the hardware and the kernel The drivers calling into the kernel for the clock requirements need to ensure that if the clock source is shared between multiple drivers clk enable calls must be balanced by the same number of clk disable calls for the clock source to be disabled Each clk enable call increments the reference count of the clock and its dependencies as described in Section 10 2 2 above The Middle Management layer tracks the reference counts and resolves the dependencies in the clock dependency tree Lower level clock management layer The lower level clock management layer actually interacts with the hardware to ensure that the proper settings are being done in the respective registers required for the proper functioning of the clock tree At the time when the kernel is being booted the clock tree initialization takes place based upon a static clock tree that has been defined in arc arm mach spearxxx include arm spearxxx clock h This tree provides in the exhaustive clock dependencies that have been maintained for the SPEAr system The clocks in the RAS hardware area are not covered in the software management of the clocks as yet One of the most important data structures that has been used in the clock framework is the struct clk struct clk struct res handle res struct list head node struct list head cik got struct list head cik enabled struct module owner const char name int id
319. y not seem important in the one button case but is quite important for example for mouse movement where you do not want the X and Y values to be interpreted separately because that would result in a different movement Touchscreen usage The touchscreen driver provides an event interface to the input layer Evdev is the generic input event interface It passes the events generated in the kernel straight to the program with timestamps The devices are in dev input normally up to event 31 crw r r 1 root root 13 64 Apr 1 10 49 event0 Ccrw r r 1 root root 13 65 Apr 1 10 50 event1 crw r r 1 root root 13 66 Apr 1 10 50 event2 Crw r r 1 root root 13 67 Apr 1 10 50 event3 For the touchscreen the device name is dev input eventO or dev input ts with major 13 and minor 64 The device can be opened using using the open system call in both blocking and non blocking modes It can be read using the select system call on the dev input eventX devices which will always get a whole number of input events on a read Their layout is struct input event struct timeval time unsigned short type unsigned short code unsigned int value time is the timestamp it returns the time at which the event happened type is for example EV REL for relative moment or REL KEY for a keypress or release code is the event code for example REL X or KEY BACKSPACE value is the value carried by the event If you are using
320. yer Kernel space Touchscreen driver ADC GPIO gt CLOD panel Hardware 7 1 3 Touchscreen driver overview Input device layer The kernel s input subsystem layer unifies the interface to different drivers that handle diverse classes of data input devices such as keyboards mice and touchscreens The kernel s input subsystem layer provides a uniform way of handling of functionally similar input devices even when they are physically different For example all mice such as PS 2 USB or Bluetooth are treated alike It has an easy to use event interface for dispatching input reports to user applications The driver does not have to create or manage dev nodes and related access methods Instead it can simply invoke input APIs to send mouse movements key presses or touch events upstream to user land Applications such as X Windows work seamlessly over the event interfaces exported by the input subsystem layer Touchscreen driver basics The touchscreen driver has a state machine which gets called every 100 ms and reads both ADC channels The state machine has 3 states as shown in Figure 47 ky Doc ID 16604 Rev 2 175 245 www BDTIC com ST Human interface device HID drivers UM0851 176 245 Figure 47 State machine of touchscreen driver Initial default state Returns to IDLE state from RELEASE state after finger is removed ae a is entered RELEASE state is entered when when panel is finger is removed from panel touched PRESS
321. ystem call used to get the output data ioctl rfd JPEGIOC GET OUT DATA SIZE amp size rfd read node file descriptor JPEGIOC GET OUT DATA SIZE command to get output data 158 245 Doc ID 16604 Rev 2 ky www BDTIC com ST UM0851 Accelerator engine device drivers Size variable which will store size of equal to size of individual read buffer output data in bytes This must always be If it is less than size of individual read buffer end of encoding decoding is indicated This is a blocking system call which unblocks or returns only when the output data size less than equal to the size of the individual read buffer is written to current read buffer after encoding decoding On success zero is re turned otherwise 1 is returned on error and errno is set appropriately For example total size of output data is 15 K size of each write buffer is 4 K then user needs to do following steps to read data from JPEG 1 Set current read buffer to read bufferO 2 Call JPEGIOC GET OUT DATA SIZE ioctl 3 Check value of parameter size if it is less than 4 K end of encoding decoding is indicated 4 Read data from current read buffer 5 Toggle current read buffer to buffer1 if buffer is buffer1 current buffer is bufferO else to bufferO if current 6 Follow steps 2 3 4 5 till the time step 3 doesn t indicate end of encoding decoding Writing input data to write buffer and reading output data from rea

Linux support package (LSP) v2.3 for SPEAr

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