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LPC2114/2124/2212/2214 USER MANUAL

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1. nVICIRQIN VICVECTADDRIN 31 0 Figure 19 Block Diagram of the Vectored Interrupt Controller Vectored Interrupt Controller VIC 87 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 SPURIOUS INTERRUPTS Spurious interrupts are possible to occur in the ARM7TDMI based microcontroller such as the LPC2114 2124 2212 2214 due to the asynchronous interrupt handling The asynchronous character of the interrupt processing has its roots in the interaction of the core and the VIC If the VIC state is changed between the moments when the core detects an interrupt and the core actually processes an interrupt problems may be generated Real life application may experience following scenario 1 VIC decides there is an IRQ interrupt and sends the IRQ signal to the core 2 Core latches the IRQ state 3 Processing continues for a few cycles due to pipelining 4 Core loads IRQ address from VIC Furthermore It is possible that the VIC state has changed during the step 3 For example VIC was modified so that the interrupt that triggered the sequence starting with step 1 is no longer pending interrupt got disabled in the executed code In this case the VIC will not be able to clearly identify the interrupt that generated the interrupt request and as a result the VIC will return the default interrupt VicDefVectAddr OxFFFF F034 This poten
2. Figure 26 Format in the master transmitter mode Master Receiver Mode In the master receiver mode data is received from a slave transmitter The transfer is initiated in the same way as in the master transmitter mode When the START condition has been transmitted the interrupt service routine must load the slave address and the data direction bit to 12C Data Register I2DAT and then clear the SI bit When the slave address and data direction bit have been transmitted and an acknowledge bit has been received the SI bit is set and the Status Register will show the status code For master mode the possible status codes are 40H 48H or 38H For slave mode the possible status codes are 68H 78H or BOH Refer to Table 4 in 80C51 Family Derivatives 8XC552 562 Overview datasheet available on line at http www semiconductors philips com acrobat various 8XC552 5620VERVIEW 2 pdf for details Slave Address R DATA A M A P 0 Write A Data Transferred A 1 Read n Bytes Acknowledge A Acknowledge SDA low From Master to Slave A Not Acknowledge SDA high From Slave to Master S START condition P STOP Condition Figure 27 Format of master receiver mode After a repeated START condition C may switch to the master transmitter mode 12C Interface 149 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller L
3. m ems me 2 3 4 0 5 0 5 00 100 0 200 0 300 0 20 00 00 m 12C Interface 156 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 111 I2C Clock Rate Selections for VPB Clock Divider 2 I2SCLL Bit Frequency kHz At fcc k MHz amp VPB Clock Divider 2 I2SCLH 8 A E TA m qme qms p EC 8 me ms ms Table 112 12C Clock Rate Selections for VPB Clock Divider 4 I2SCLL Bit Frequency kHz At fcc x MHz amp VPB Clock Divider 4 I2SCLH 16 8 500 0 9 ms E E m ws me me 12C Interface 157 May 03 2004 Philips Semiconductors ARM based Microcontroller ARCHITECTURE Input Filter Output Stage Input Filter Output Stage Status Bus Status Decoder 12C Interface I2ZCONSET I2ZCONCLR I2SCLH I2SCLL Preliminary User Manual LPC2114 2124 2212 2214 Address Register al Shift Register 4 I2DAT Bit Counter Arbitration amp Sync Logic Timing amp Control Logic VPB BUS Serial Clock Generator Control Register amp SCL Duty Cycle Registers Status Register I2STAT Figure 32 I2C Architecture 158 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2
4. 0005 57 Table 19 MEMMAP Register llle RR I y ru 59 Table 20 Memory Mapping Control Register MEMMAP 0xE01FC040 oooooooocooocoo o 59 T ble 21 PLL Registers s lp AA A A A Date Sl RE REM PEU aS 60 Table 22 PLL Control Register PLLCON OXEO1FC080 ooooccococococo ees 62 Table 23 PLL Configuration Register PLLCFG OXEO1FC084 0 0 2c eee esee 62 Table 24 PLL Status Register PLLSTAT OXEO1FC088 0 0 eee 63 Table 25 PLL Control Bit Combinations o ooooooooooro e 63 Table 26 PLL Feed Register PLLFEED O0xE01FC08C o ooocccccccoccococn eee 64 Table 27 PLL Divider Values 0 00 000 cee eee 65 Table 28 PLE Multiplier Valles s 5 22 cee ees RE eee eee ee eR ee Rohr e Roe din 65 Table 29 Power Control Registers oooooococcccccoco eet 66 Table 30 Power Control Register PCON OxEQ1FCOCO 0000s 66 Table 31 Power Control for Peripherals Register for LPC2114 2124 PCONP OXEO1FCOCA4 67 Table 32 Power Control for Peripherals Register for LPC2212 2214 PCONP OXEO1FCOCA 67 Table 33 VPBDIV Register Map oooooccoocorc y re 70 Table 34 VPB Divider Register VPBDIV OxE01FC100 0 00 eee cette 70 Table 35 MAM Responses to Program Accesses of Various TypeS 0 00 ce eee eee eee ee 75 Table 36 MAM Responses to Data and DMA Accesses of Various TypeS 0 0 eee ee 75 Table 37 S
5. mem Ne This command must be executed before executing Copy RAM to Flash or Erase Sector s command Successful execution of the Copy RAM to Flash or Erase Sector s command causes relevant sectors to be protected again The boot sector can not be prepared by this command To prepare a single sector use the same Start and End sector numbers Description Flash Memory System and Programming 236 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Copy RAM to Flash Table 181 IAP Copy RAM to Flash command description Command Copy RAM to Flash Command code 51 ParamO DST Destination Flash address where data bytes are to be written The destination address should be a 512 byte boundary Input Param1 SRO Source RAM address from which data bytes are to be read This address should be on word boundary Param2 Number of bytes to be written Should be 512 1024 4096 8192 Param3 System Clock Frequency CCLK in KHz CMD SUCCESS SRC ADDR ERROR Address not on word boundary DST ADDR ERROR Address not on correct boundary Status Code SRC ADDR NOT MAPPED DST ADDR NOT MAPPED COUNT ERROR Byte count is not 512 1024 4096 8192 SECTOR NOT PREPARED FOR WRITE OPERATION BUSY A AN This command is used to program the flash memory The affected sectors should be prepared first by calling Prepare Sector for Write Operation
6. sseseeeeeee hm mr 76 Register Description s sess eI Rex e AO ALE EE eat AUR E ROS 76 MAM Usage Notes rre Rem CENE EE Mes arm boe WEM ERE Bug 77 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Vectored Interrupt Controller VIC 0 00 eee eee eee 79 Features ii uec Wess pas Soporte FACE a ara cl y cheated cy R ED DE Sonata aac fo ge RSEN ee IER 79 Description mm 79 Register Description usu een ge a RR A pal E EXE CREE 80 MIC Registers tra repe pene DEEP P LEBRM tae 82 Interrupt Sources ved ERE RR S ade ap RCROGRTR ta ACER RU CR 86 Spurious Interrupts 2 42 acetone kee ee OMA diete teo duit A rte Et ds 88 VIC Usage Notes cuero ee 9 RE RR RR ER PER Ros Aog RR i E ed 91 Pin Configuration oo oocoococcno n nh hm hh hh 93 LPC2114 2124 PinQUt iiec et aes BE EEA ide te 93 Pin Description for LPC2114 2124 liiis hn 94 LPC2212 2214 PIDOUE ziii cvs re mee eal ee ene E eels DA Oe INE Ue SR Rin en 98 Pin Description for LPC2212 2214 2 eene 99 Pin Connect Block 24s oe I eR Siete Pee EEER rures 109 Features Sni enr OR EERAR acne sl note ie deca ORARE IURE OR RC E eae act 109 Applications sui Te byReg4 A A Edad Neden A GU PER KE AN 109 Description ssis i ee R id ERG o RE LEEREN RE E RH RR att 109 Register Description llcisilleseeeee Rl m ne 109 Boot Control on 144 pin Package 0 cece cette tenes 114 GPIO is oes A R
7. Real Time Clock 204 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Consolidated Time Register 2 CTIME2 0xE002401C The Consolidate Time Register 2 contains just the Day of Year value Table 150 Consolidated Time Register 2 Bits CTIME2 0xE002401C CTIME2 Function Description 11 0 Day of Year Day of year value in the range of 1 to 365 366 for leap years Reserved user software should not write ones to reserved bits The value read from a reserved 31 12 Reserved ND A bit is not defined Real Time Clock 205 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 TIME COUNTER GROUP The time value consists of the eight counters shown in Tables 151 and 152 These counters can be read or written at the locations shown in Table 152 Table 151 Time Counter Relationships and Values Counter Enabled by Maximum value m uu Clk1 see Figure 40 e 59 we e sew o 9 mw 5 w 2 Lowswe 3 mw 9 s A ara js ws 7 Table 152 Time Counter registers Address Name Description Access 0xE0024020 SEC Seconds value in the range of 0 to 59 R W 0xE0024024 MIN EN Minutes value in the range of 0 to 59 R W 0xE0024028 HOUR Hours value in the range of 0 to 23 R W OxE002402C DOM 5 Day of month value in the range of 1 to 28 29 30 or 31 depending
8. RRR RRR KK A A A A A A A I Ck I kk I Ck Ck Ck Ck kk Ck CK kk kCk Ck ok KKKA I OK Setup Vectored Interrupt controller DCC Rx and Tx interrupts generate Non Vectored IRQ request rm init entry is aware of the VIC and it enables the DBGCommRX and DBGCommTx interrupts Default vector address register is programmed with the address of Vectored IRQs or FIQs here AA VICBaseAddr EQU OxFFFFFOO00 VIC Base address VICDefVectAddrOffset EQU 0x34 LDR r0 VICBaseAddr LDR rl app irqDispatch STR rl r0 4VICDefVectAddrOffset BL rm init entry Initialize RealMonitor enable FIQ and IRQ in ARM Processor MRS rl CPSE get the CPSR BIC rl rl 0xCO enable IRQs and FIQs MSR CPSR_c rl update the CPSR RRR RR KR A A RARA RARA A A RRA RAR RR I kk A A A I 0 e Get the address of the User entry point FR A A A RARA A A A A RARA RR I I I A A A ke ke ke I x x f LDR lr User_Entry MOV pc lr RRR KR KK A A A A A A kk I kk kk I kk Ck Ck KC kCk Ck ok I kk Non vectored irq handler app irqDispatch Fe A A A A A A A A A A kk kk I I A A A kk kk ko I I x x f AREA app_irqDispatch CODE VICVectAddrOffset EQU 0x30 app irgDispatch enable interrupt nesting STMFD sp r12 r14 MRS r12 spsr Save SPSR in to r12 MSR cpsr_c 0x1F Re enable IRQ go to system mode User should insert code here if non vectored Interrupt sharing is required Each non vectored shared irq handler must
9. This command makes flash write erase operation a two step process Table 170 ISP Prepare sector s for write operation command description Command P input Start Sector Number P End Sector Number Should be greater than or equal to start sector number CMD SUCCESS BUSY Return Code INVALID_SECTOR PARAM_ERROR This command must be executed before executing Copy RAM to Flash or Erase Sector s Description command Successful execution of the Copy RAM to Flash or Erase Sector s command causes relevant sectors to be protected again The boot sector can not be prepared by this command To prepare a single sector use the same Start and End sector numbers Example P 0 0 lt CR gt lt LF gt prepares the flash sector 0 Copy RAM to Flash lt Flash address gt lt RAM address gt lt number of bytes gt Table 171 ISP Copy RAM to Flash command description Command C Flash Address DST Destination Flash address where data bytes are to be written The destination Input address should be a 512 byte boundary p RAM Address SRC Source RAM address from where data bytes are to be read Number of Bytes Number of bytes to be written Should be 512 1024 4096 8192 CMD_SUCCESS SRC_ADDR_ERROR Address not on word boundary DST_ADDR_ERROR Address not on correct boundary SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED Return Code COUNT_ERROR Byte count is not 512 1024 4096 8192 SECTOR NOT PREPA
10. 26 24 Day of Week Day of week value in the range of 0 to 6 Reserved user software should not write ones to reserved bits The value read from a reserved 23 21 Reserved bit is not defined 20 16 Hours value in the range of 0 to 23 Reserved user software should not write ones to reserved bits The value read from a reserved 15 14 Reserved bit is not defined Minutes value in the range of 0 to 59 Reserved user software should not write ones to reserved bits The value read from a reserved 7 6 Reserved E bit is not defined Seconds value in the range of 0 to 59 Consolidated Time Register 1 CTIME1 0xE0024018 The Consolidate Time Register 1 contains the Day of Month Month and Year values Table 149 Consolidated Time Register 1 Bits CTIME1 0xE0024018 CTIME1 Function Description Reserved user software should not write ones to reserved bits The value read from a reserved 31 28 Reserved bit is not defined 27 16 Year value in the range of 0 to 4095 Reserved user software should not write ones to reserved bits The value read from a reserved 15 12 Reserved D bit is not defined Month value in the range of 1 to 12 1 8 Reserved user software should not write ones to reserved bits The value read from a reserved 7 5 Reserved au bit is not defined 4 0 Day of Month Day of month value in the range of 1 to 28 29 30 or 31 depending on the month and whether itis a leap year
11. LPC2114 2124 2212 2214 MEMORY RE MAPPING AND BOOT BLOCK Memory Map Concepts and Operating Modes The basic concept on the LPC2114 2124 2212 2214 is that each memory area has a natural location in the memory map This is the address range for which code residing in that area is written The bulk of each memory space remains permanently fixed in the same location eliminating the need to have portions of the code designed to run in different address ranges Because of the location of the interrupt vectors on the ARM7 processor at addresses 0x0000 0000 through 0x0000 001C as shown in Table 3 below a small portion of the Boot Block and SRAM spaces need to be re mapped in order to allow alternative uses of interrupts in the different operating modes described in Table 4 Re mapping of the interrupts is accomplished via the Memory Mapping Control feature described in the System Control Block section Table 3 ARM Exception Vector Locations Address Exception Prefetch Abort instruction fetch memory fault Data Abort data access memory fault wwwwis m dentified as reserved in ARM documentation this location is used by the Boot Loader as the Valid User Program key This is descibed in detail in Flash Memory System and Programming on page 217 Table 4 LPC2114 2124 2212 2214 Memory Mapping Modes Mode Activation Usage The Boot Loader always executes after any reset The Boot Block interrupt vectors are mapped to the
12. LPC2114 2124 has two 32 bit General Purpose l O ports Total of 30 out of 32 pins are available on PORTO PORT1 has up to 16 pins available for GPIO functions PORTO and PORT are controlled via two groups of 4 registers as shown in Table 68 LPC2212 2214 has two 32 bit additional ports PORT2 and PORTS and they are configured to be used either as external memory data address and data bus or as GPIOs sharing pins with a handful of digital and analog functions Details on PORT2 and PORTS usage can be found in Pin Configuration and Pin Connect Block chapters GPIO 115 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 68 GPIO Register Map Reset PORTO PORT1 PORT2 PORT3 Description Access Address amp Address amp Address amp Address amp Value Name Name Name Name GPIO Port Pin value register The current state of the GPIO configured port pins can always be read from this register regardless of pin direction NA 0xE0028000 0xE0028010 0xE0028020 0xE0028030 and mode IOOPIN IO1PIN IO2PIN IO3PIN Activity on non GPIO configured pins will not be reflected in this register GPIO Port Output set register This register controls the state of output 0x0000 pins in conjunction with the IOCLR Read 0000 0xE0028004 0xE0028014 0xE0028024 0xE0028034 register Writing ones produces highs Write IOOSET IO1SET 102SET IO3SET atthe corresponding port pins W
13. SPI Interface 164 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 SPI Status Register SOSPSR 0xE0020004 S1SPSR 0xE0030004 The SPSR register controls the operation of the SPI as per the configuration bits setting Table 117 SPI Status Register SOSPSR 0xE0020004 S1SPSR 0xE0030004 Function Description Reserved user software should not write ones to reserved bits The value read from Reserved a reserved bit is not defined Slave abort When 1 this bit indicates that a slave abort has occurred This bit is cleared by reading this register Mode fault when 1 this bit indicates that a Mode fault error has occurred This bit is cleared by reading this register then writing the SPI control register Read overrun When 1 this bit indicates that a read overrun has occurred This bit is cleared by reading this register Write collision When 1 this bit indicates that a write collision has occurred This bit is cleared by reading this register then accessing the SPI data register SPI transfer complete flag When 1 this bit indicates when a SPI data transfer is complete When a master this bit is set at the end of the last cycle of the transfer When a slave this bit is set on the last data sampling edge of the SCK This bit is cleared by first reading this register then accessing the SPI data register Note this is not the SPI interrupt flag
14. This field controls the length of read accesses except for subsequent reads from a 9 5 WST1 burst ROM The length of such read accesses in CCLK cycles is the value in this field 11111 plus 3 This bit should be 0 for banks composed of byte wide or non byte partitioned devices 10 RBLE so that the EMC drives the BLS3 0 lines High during read accesses This bit should be 1 for banks composed of 16 bit and 32 bit wide devices that include byte select inputs so that the EMC drives the BLS3 0 lines Low during read accesses For SRAM banks this field controls the length of write accesses which consist of one CCLK cycle of address setup with CS BLS and WE high this value plus 1 CCLK cycles with address valid and CS BLS and WE low and 15 11 WST2 one CCLK cycle with address valid CS low BLS and WE high 11111 For burst ROM banks this field controls the length of subsequent accesses which are this value plus 1 CCLK cycles long Reserved user software should not write ones to reserved bits The value read from a 16 23 Reserved zs i N reserved bit is not defined 24 BUSERR The only known case in which this bit is set is if the EMC detects an AMBA request for more than 32 bits of data The ARM7TDMI S will not make such a request 25 WPERR This bit is set if software attempts to write to a bank that has the WP bit 1 Write a 1 to this bit to clear it A 1 in this bit write protects the bank A 1 in this bit identifies a burst
15. 1 Match 32 bit data R W Register 1 oxEo008020 Tt MR2 Match 32 bit data R W Register 2 oxE0008024 T1MR3 1 Match 32 bit data R W Register 3 Int on 4 reserved bits Cpt 3 T1 Capture falling 0xE0008028 T1CCR Control Register Int on Int on Int on Int on Int on Int on Cpt 2 Cpt 2 Cpt 1 Cpt 1 Cpt 0 Cpt 0 falling rising falling rising falling rising 0xE000802C Ticro 11 Capture 32 bit data Register 0 oxE0008030 T1CR1 T1 Capture 32 bit data Register 1 0xE0008034 T1CR2 T Capture 32 bit data Register 2 Introduction 22 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 2 LPC2114 2124 2212 2214 Registers Address a Reset Offset Description LSB Access Value oxE0008038 T1CR3 1 Capture 32 bit data Register 3 4 reserved bits External Match External Match T1 External Control 3 Control 2 0xE000803C T1EMR Match Register External Match External Match Ext Ext Ext Ext Control 1 Control 0 Mtch 3 Mtch2 Mtch 1 Mtch 0 UARTO UO Transmit DLAB 0 Register UODLL UO Divisor UO Interrupt Enable En Rx UOIER Enable THRE Data DLAB 0 OxE000C004 Register dd UO Divisor Latch MSB 8 bit data uoi UO Interrupt Eos Enabled IRS HR2 IIR1 0x01 ID Register 0xE000C008 UO FIFO UOFCR Control Rx Trigger FIFO WO Register Enable UO Line Even OxEO00COOC UOLCR Cont
16. Figure 12 Oscillator modes and models a slave mode of operation b oscillation mode of operation c external crystal model used for Cxy x2 evaluation Table 13 Recommended values for Cxyyx2 in oscillation mode crystal and external components parameters Fundamental Oscillation Crystal Load Max Crystal Series External Load Frequency Fc Capacitance C Resistence Rs Capacitors Cy4 Cx 10 pF n a n a System Control Block 52 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 13 Recommended values for Cxyyx2 in oscillation mode crystal and external components parameters Fundamental Oscillation Crystal Load Max Crystal Series External Load Frequency Fc Capacitance C Resistence Rs Capacitors Cy4 Cxo 10 pF lt 300 Q 18 pF 18 pF C fosc Selection Y on chip PLL used in application y False ISP used for initial code download y False external crystal oscillator used i Y y False min fosc 10 MHz min fosc 1 MHz min fosc 1 MHz max fosc 25 MHz max fosc 50 MHz max fosc 30 MHz Figure 12 mode a and or b Figure 12 mode a Figure 12 mode b Figure 13 Fosc selection algorithm System Control Block 53 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 EXTERNAL INTERRUPT INPUTS The LPC
17. Figure 42 Watchdog Block Diagram Watchdog 216 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 19 FLASH MEMORY SYSTEM AND PROGRAMMING This chapter describes the Flash Memory System and the Boot Loader It also includes In System Programming ISP and In Application Programming IAP interfaces FLASH MEMORY SYSTEM The Flash Memory System contains 16 sectors for 128 kB part and 17 sectors for 256 kB part Flash memory begins at address 0 and continues upward Details may be found in the LPC2114 2124 2212 2214 Memory Addressing chapter On chip Flash memory is capable of withstanding at least 10 000 erase and write cycles over the whole temperature range FLASH BOOT LOADER The Boot Loader controls initial operation after reset and also provides the means to accomplish programming of the Flash memory This could be initial programming of a blank device erasure and re programming of a previously programmed device or programming of the Flash memory by the application program in a running system FEATURES In System Programming In System programming ISP is programming as well as reprogramming the on chip flash memory using the boot loader software and a serial port while the part may reside in the end user system In Application Programming In Application IAP programming is performing erase and write operation on the on chip flash memory as directed by the
18. INTEGRATED CIRCUITS USER MANUAL LPC2114 2124 2212 2214 USER MANUAL Preliminary 2004 May 03 Supersedes data of 2004 Feb 03 Philips PHILIPS Semiconductors El l LI PS Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 2 May 03 2004 Philips Semiconductors ARM based Microcontroller Table of Contents Preliminary User Manual LPC2114 2124 2212 2214 Listot Figures ac ocn A AA ee AA A ceci aee pee vg 7 List of Tables 4 occ eed Nees tdi 9 Document Revision History 0 0 eee ene 13 Introduction i lum eI RS de ee Gee SE dee ed eed 15 General Description os e meu e EE RR dr LEER CURRERE eee RS 15 RII E 5 ORO 15 Applications iuuenem a A RA A a ate nes 16 Device Information vele A A AA AA AA 2 ee Pe 16 Architectural Overview o ooooococcoco mme 17 ARM7TDMIES Processor ucraniana eub AAA A dw aid CR RT eee ds 17 On Chip Flash Memory System oococccocccoc el rm 17 on Chip Static RAM eer ees miei eR Oed xD REN OE Ere ge ee Repas 18 Block Diagram 22 ded tm RE eee T hoe VAR p ur o Ga IMP FR 19 LPC2114 2124 2212 2214 Registers 0 cect nen 20 LPC2114 2124 2212 2214 Memory Addressing lesser 33 Memory Maps terca ed Ere RR acie Po E Ae e e Roma oar Ek e eg a 33 LPC2114 2124 2212 2214 Memory Re mapping and Boot Block o oooocooo oo o
19. OXFFFFF000 Read Only This register reads out the state of those interrupt requests that are enabled and classified as IRQ It does not differentiate between vectored and non vectored IRQs Table 47 IRQ Status Register VICIRQStatus OXFFFFF000 Read Only VICIRQStatus Function Reset Value 31 0 1 the interrupt request with this bit number is enabled classified as IRQ and asserted 0 Vectored Interrupt Controller VIC 83 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 FIQ Status Register VICFIQStatus OXFFFFF004 Read Only This register reads out the state of those interrupt requests that are enabled and classified as FIQ If more than one request is classified as FIQ the FIQ service routine can read this register to see which request s is are active Table 48 IRQ Status Register VICFIQStatus OXFFFFF004 Read Only VICFIQStatus Function Reset Value 31 0 1 the interrupt request with this bit number is enabled classified as FIQ and asserted 0 Vector Control Registers 0 15 VICVectCntl0 15 OxFFFFF200 23C Read Write Each of these registers controls one of the 16 vectored IRQ slots Slot 0 has the highest priority and slot 15 the lowest Note that disabling a vectored IRQ slot in one of the VICVectCnil registers does not disable the interrupt itself the interrupt is simply changed to the non vectored form Table 49 Vector Control
20. OxXE001C000 0 ee 154 Table 101 12C Control Clear Register I2CONCLR OxE001C018 0 0 ee 154 Table 102 l2C Status Register IASTAT OXE001C004 o oococcocccccoo eh 155 Table 103 l2C Data Register I2DAT OXE001C008 o oococccccccocc eh 155 Table 104 l2C Slave Address Register IBADR OXE001C00C oooccccoccccc ee 155 Table 105 I2C SCL High Duty Cycle Register IPSCLH OXE001C010 o oocooocococcoo 00 ee 156 Table 106 l2C SCL Low Duty Cycle Register I2SCLL 0OXE001C014 lslseseseels esee 156 Table 107 12C Clock Rate Selections for VPB Clock Divider 1 0 000 c cece eee eee ee eee 156 10 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 108 12C Clock Rate Selections for VPB Clock Divider 2 o0oooccccoccccccocooo o 157 Table 109 12C Clock Rate Selections for VPB Clock Divider 4 lees eese eene 157 Table 110 SPI Data To Clock Phase Relationship 0 0 0 0 cee cette ee 160 fable 113 zSPI Pin Description acido ext Rhe RR EUR RO RUE ee Rin 163 Table 112 SPI Register Map oooococcccc hh mme 164 Table 113 SPI Control Register SOSPCR 0xE0020000 S1SPCR OxE0030000 164 Table 114 SPI Status Register SOSPSR 0xE0020004 S1SPSR 0xE0030004 165 Table 115 SPI Data Register SOSPDR 0xE0020008 S1SPDR 0xE0030008 1
21. Reserved IRQ App IRQHandler Figure 51 Exception Handlers RealMonitor 254 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 RMTarget initialization While the processor is in a privileged mode and IRQs are disabled user must include a line of code within the start up sequence of application to call rm_init_entry RealMonitor 255 May 03 2004 Philips Semiconductors ARM based Microcontroller Code Example The following example shows how to setup stack VIC vectored interrupts IMPORT rm_init_entry IMPORT rm prefetchabort handler IMPORT rm dataabort handler IMPORT rm irghandler2 IMPORT rm undef handler IMPORT User Entry Entry point of user application CODE32 ENTRY Define exception table Instruct linker to place code at address 0x0000 0000 Preliminary User Manual LPC2114 2124 2212 2214 initialize RealMonitor and share non AREA exception table CODE LDR pc Reset Address LDR pc Undefined Address LDR pc SWI Address LDR pc Prefetch Address LDR pc Abort Address OP Insert User code valid signature here LDR pc pc OxFFO Load IRQ vector from VIC LDR PC FIQ Address Reset Address DCD init Reset Entry point Undefined Address DCD rm undef handler Provided by RealMonitor SWI Address DCD 0 User can put addres
22. SPI Interface 167 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 SPI Interface 168 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 14 TIMERO AND TIMER1 TimerO and Timer1 are functionally identical except for the peripheral base address FEATURES A 32 bit Timer Counter with a programmable 32 bit Prescaler Up to four 32 bit capture channels per timer that can take a snapshot of the timer value when an input signal transitions A capture event may also optionally generate an interrupt Four 32 bit match registers that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Up to four external outputs corresponding to match registers with the following capabilities Setlow on match Sethigh on match Toggle on match Do nothing on match APPLICATIONS Interval Timer for counting internal events Pulse Width Demodulator via Capture inputs Free running timer TimerO and Timer1 169 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 DESCRIPTION The Timer is designed to count cycles of the peripheral clock pclk and optionally generate interrupts or perform other actions a
23. The routine exploits this restriction to determine how it was called by examining the I bit of the SPSR and returns using the appropriate instruction If the routine is entered due to an IRQ being received during execution of the MSR instruction which disables IRQs then the bit in the SPSR will be set The routine would therefore assume that it could not have been entered via an IRQ Problem 2 FIQs and IRQs are both disabled by the same write to the CPSR In this case if an IRQ is received during the CPSR write FIQs will be disabled for the execution time of the IRQ handler This may not be acceptable in a system where FIQs must not be disabled for more than a few cycles Workaround There are 3 suggested workarounds Which of these is most applicable will depend upon the requirements of the particular system Solution 1 Add code similar to the following at the start of the interrupt routine SUB lr lr 4 Adjust LR to point to return STMFD Spi Toug dE Get some fr regs MRS lr SPSR See if we got an interrupt while TST lr I Bit interrupts were disabled LDMNEFD sp pc If so just return immediately The interrupt will remain pending since we haven t acknowledged it and will be reissued when interrupts are next enabled Rest of interrupt routine This code will test for the situation where the IRQ was received during a write to disable IRQs If this is the case the code returns immedi
24. command The affected sectors are automatically protected again once the copy command is successfully executed The boot sector can not be written by this command Description Erase Sector s Table 182 IAP Erase Sector s command description Command Erase Sector s Command code 52 in t Paramo Start Sector Number p Param1 End Sector Number Should be greater than or equal to start sector number Param2 System Clock Frequency CCLK in KHz CMD SUCCESS BUSY SECTOR NOT PREPARED FOR WRITE OPERATION INVALID SECTOR Status Code This command is used to erase a sector or multiple sectors of on chip Flash memory The boot Description sector can not be erased by this command To erase a single sector use the same Start and End sector numbers Flash Memory System and Programming 237 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Blank check sector s Table 183 IAP Blank check sector s command description Command Blank check sector s Command code 53 Input Paramo Start Sector Number Param1 End Sector Number Should be greater than or equal to start sector number CMD SUCCESS BUSY SECTOR NOT BLANK INVALID SECTOR Result0 Offset of the first non blank word location if the Status Code is SECTOR NOT BLANK Result1 Contents of non blank word location ar This command is used to blank check a sector or multiple sector
25. is given by Foco cclk M Fosc or cclk 2 P The CCO frequency can be computed as Foco CCIK 2 P or Feco Fos M 2 P The PLL inputs and settings must meet the following e Fog is in the range of 10 MHz to 25 MHz e cclk is in the range of 10 MHz to Fmax the maximum allowed frequency for the LPC2114 2124 2212 2214 Foco is in the range of 156 MHz to 320 MHz System Control Block 64 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Procedure for Determining PLL Settings If a particular application uses the PLL its configuration may be determined as follows 1 Choose the desired processor operating frequency cclk This may be based on processor throughput requirements need to support a specific set of UART baud rates etc Bear in mind that peripheral devices may be running from a lower clock than the processor see the VPB Divider description in this chapter 2 Choose an oscillator frequency Fosc cclk must be the whole non fractional multiple of Fosc 3 Calculate the value of M to configure the MSEL bits M cclk Fose M must be in the range of 1 to 32 The value written to the MSEL bits in PLLCFG is M 1 see Table 28 4 Find a value for P to configure the PSEL bits such that Feco is within its defined frequency limits Foc is calculated using the equation given above P must have one of the values 1 2 4 or 8 The value written to t
26. or transistors that drive low while RESET is low to these pins to select among the following options Table 66 Boot Control on BOOT1 0 BOOT1 BOOTO latched from P2 27 D27 on latched from P2 26 D26 on Boot from Reset pin rising edge only Reset pin rising edge only 8 bit memory on CSO 16 bit memory on CSO 32 bit memory on CSO Internal Flash Memory Note that if an application enables the Watchdog Timer to Reset the part if it s not serviced transistors driven by RESET should not be used Pin Connect Block 114 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 9 GPIO FEATURES Direction control of individual bits Separate control of output set and clear All I O default to inputs after reset APPLICATIONS General purpose l O Driving LEDs or other indicators Controlling off chip devices Sensing digital inputs PIN DESCRIPTION Table 67 GPIO Pin Description Pin Name Description P0 0 P0 31 General purpose input output The number of GPIOs actually available depends on the use of P1 16 P1 31 alternate functions External bus data address lines shared with GPIO digital and analog functions The number of P2 0 P2 31 Input GPIOs digital and analog functions actually available depends on the selected bus structure P3 0 P3 31 Output PORT2 and PORTS are available in LPC2212 2214 only REGISTER DESCRIPTION
27. sectors and specify sector numbers The following table indicates the correspondence between sector numbers and memory addresses for LPC2114 2124 2212 2214 device s IAP ISP and RealMonitor routines are located in the Boot Sector The boot sector is present in all devices ISP and IAP commands do not allow write erase go operation on the boot sector In a device having 128K of Flash only 120 kB is available for the user program Devices with the total of 256 kB of Flash allow user code of up to 248 kB Table 162 Sectors in a device with 128K bytes of Flash Memory Addresses and Sector Sizes 128 kB part Sector size kB 256 kB part Sector size kB 0x0000 0000 1FFF 8 0x0000 0000 1FFF 8 3 ME s sweme w owmsm sr s owmem sr s MEE s ME s Mc s wemsm srt 3 Ma s A s ME s A s Ma s E s MEET s owmwom mr 9 Lem amer s a 9 Mc s wemsom wrt s MEET s NC CN MEE s MU s Ma s ML 5 wwe omar coor s owes s 55e sewer s O 8 16 0x10 0x0003 C000 DFFF mE Al 17 0x11 0x0003 E000 FFFF o ae Boot Block always resides on the top of the on chip available Flash memory In case of 128 kB Flash it is the 16 sector sector with logical number 15 and in case of 256 kB Flash it is the 18 sector sector with logical number 17 Fla
28. 000 c eee ren 239 Table 185 EmbeddedICE Pin Description lilieeeleeseee RII 242 Table 186 EmbeddedICE Logic Registers llle eh 243 Table 187 ETM Contiguration vita A unc qe Re PERO ERU E EROR 245 Table 188 ETM Pin Description o o oooooooooorroor RR RR A RH II etn 246 Table 189 ETM Registers ns iiias saan din a a e m m mm 9c 247 Table 190 RealMonitor stack requirement lisse 253 12 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 DOCUMENT REVISION HISTORY 2003 Dec 03 Prototype LPC2114 2124 2212 2214 User Manual created from the design specification 2003 Dec 09 External Memory Controller and Pin Connect Block chapters updated 2003 Dec 15 16 System Control Block chapter updated 2003 Dec 18 A D Converter Block chapter updated 2004 Jan 07 PLL related material updated 2004 Jan 26 System Control Block Crystal Oscillator section new frequencies added updated 2004 Feb 03 Introduction chapter register list updated 2004 May 03 P0 16 description in Pin Connect Block chapter corrected from Reserved to Capture 0 2 TIMERO LPC2212 Flash size corrected in Introduction chapter corrected from 256 to 128 kB Interrupt source 17 in Vectored Interrupt Controller VIC corrected from EINT2 to EINT3 Parallel ports 2 and 3 related registers added to Introduction and
29. 01 Even parity Can select 10 Forced 1 stick parity 11 Forced 0 stick parity 0 Disable break transmission Break Control 1 Enable break transmission Output pin UART1 TxD is forced to logic O when U1LCR6 is active high 7 Divisor Latch 0 Disable access to Divisor Latches Access Bit 1 Enable access to Divisor Latches UART1 140 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 UART1 Modem Control Register U1MCR 0xE0010010 The U1MCR enables the modem loopback mode and controls the modem output signals Table 97 UART1 Modem Control Register Bit Descriptions U1MCR 0xE0010010 Function Description neset Value DTR Control Source for modem output pin DTR This bit reads as 0 when modem loopback mode is 0 active RTS Control Source for modem output pin RTS This bit reads as 0 when modem loopback mode is active Reserved user software should not write ones to reserved bits The value read from a Reserved i reserved bit is not defined Reserved user software should not write ones to reserved bits The value read from a 3 Reserved In reserved bit is not defined 0 Disable modem loopback mode 1 Enable modem loopback mode The modem loopback mode provides a mechanism to perform diagnostic loopback testing Serial data from the transmitter is connected internally to serial input of the receiver Input pin RxD1 has no effect on loopback an
30. 2 2 lt Vectored Interrupt Controller VIC 80 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 40 VIC Register Map Description Address VICVectAddr10 Vector address 10 register OxFFFF F128 vein Vector control 0 register Vector Control Registers 0 15 each control one Perera VICVectCntl0 of the 16 vectored IRQ slots Slot 0 has the highest priority and slot 15 OxFFFF F200 the lowest s Reset Value refers to the data stored in used bits only It does not include reserved bits content Vectored Interrupt Controller VIC 81 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 VIC REGISTERS This section describes the VIC registers in the order in which they are used in the VIC logic from those closest to the interrupt request inputs to those most abstracted for use by software For most people this is also the best order to read about the registers when learning the VIC Software Interrupt Register VICSoftInt OXFFFFF018 Read Write The contents of this register are ORed with the 32 interrupt requests from the various peripherals before any other logic is applied Table 41 Software Interrupt Register VICSoftlnt OXFFFFF018 Read Write VICSoftInt Function Reset Value 1 force the interrupt request with this bit number 31 0 0 do not force the interrupt request wi
31. 37 Prefetch Abort and Data Abort Exceptions o oooocooocococcrr eh 40 External Memory Controller EMC 200 e eee ee eee eee 41 Features ocv cR ERE RV a Wap dine Rei phd ee E Rass aw aN eS are Su tae 41 IDi T refoji el e IET 41 Pini Description v eeseekPEPebeseeMReRn ERREUR A RE ROG RE LAE alk 42 Register Description arepo uaga e a a a e m e mmn 42 External Memory Interface oooooooooco ttt 44 Typical Bus Sequences isses eee kee ee Reale ee del ee e s See KORR Pos aoe Rice dia 46 External Memory Selection asnan cece rn 47 System Control Block 5 en 49 Summary of System Control Block Functions 0 0c cece eee 49 Pin Description i si iere ta Lb ber Pere e paeem rr EAR S E RIA eem Eus 49 Register Description isr estu pec iiw a us nose CUR GI ao PU Rcx ASI 51 Grystal Oscillatot e A are s bte un tee 52 External Interrupt Inputs hau E Aes a E RE IRE ia REUS 54 Memory Mapping Control oooccccccococ RR m 59 PLL Phase Locked Loop am RE eR UE RE Ro oe SR RO ke ROS 60 Power Controls xz ete stre A xe et OF ed PR 66 Power Control Usage Notes 0 cece eee hme 68 Reset c r 69 MPB Divider 2 tte ea a woes pode Hie ded pa p Du ee ee 70 Wakeup Timer 0 A aie whale on ROME EM eek ge 72 Memory Accelerator Module MAM o ooocoooooocon eee 73 IntrodUctlon ii A eM O 73 Memory Accelerator Module Operating Modes 002 0 e cece eee eee eens 75 MAM Configuration
32. 64 0xE002C014 Pin Connect Block 109 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Pin Function Select Register 0 PINSELO 0xE002C000 The PINSELO register controls the functions of the pins as per the settings listed in Table 65 The direction control bit in the IOODIR register is effective only when the GPIO function is selected for a pin For other functions direction is controlled automatically Table 58 Pin Function Select Register 0 for LPC2114 2124 2212 2214 PINSELO 0xE002C000 m Sa c o8 PINSELO Pee Function when 00 Function when 01 Function when 10 Function when 11 PO 0 e o 1 0 GPIO Port 0 0 TxD UARTO PWM1 Reserved 3 2 al ES N o wore OO AE EE mew wre ros cromos wawan Pin Function Select Register 1 PINSEL1 0xE002C004 The PINSEL1 register controls the functions of the pins as per the settings listed in following tables The direction control bit in the IOODIR register is effective only when the GPIO function is selected for a pin For other functions direction is controlled automatically Table 60 Pin Function Select Register 1 for LPC2114 2124 2212 2214 PINSEL1 0xE002C004 PINSEL1 d Function when 00 Function when 01 Function when 10 Function when 11 1 0 P0 16 GPIO Port 0 16 EINTO Match 0 2 TIMERO Capture 0 2 TIMERO P0 17 GPIO Port 0 17 Capture 1 2 TIMER1 SCK SPI1 Match 1 2
33. Bit 31 in IOODIR controls P0 31 0 GPIO USAGE NOTES If for the specified output pin corresponding bit is set both in GPIO Output Set Register IOnSET and in GPIO Output Clear Register IOnCLR observed pin will output level determined by the later write access of IOnSET nad IOnCLR This means that in case of sequence IOOSET 0x0000 0080 IOOCLR 0x0000 0080 pin PO 7 will have low output since access to Clear register came after access to Set register Applications that require instanatneous appearance of zeros and ones on the respected parallel port can use direct access to port s corresponding GPIO Pin Value Register IOPIN Assuming that pins P0 8 to P0 15 are configured as output write to IOOPIN IOOPIN 0x0000 C700 will produce the same output as following sequence of writes IOOSET 0x0000 C700 IOOCLR 0x0000 3800 GPIO 118 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Solution utilizing access to IOOSET and IOOCLR will take more steps compared to a single IOOPIN write access GPIO 119 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 GPIO 120 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 10 UARTO FEATURES 16 byte Receive and Transmit FIFOs Register locations conform to 550 industry standard
34. Contents of non Return Code blank word location INVALID SECTOR PARAM ERROR ius This command is used to blank check a sector or multiple sectors of on chip Flash memory To blank Description check a single sector use the same Start and End sector numbers 2 3 lt CR gt lt LF gt blank checks the flash sectors 2 and 3 Blank check on sector 0 always fails as first 64 bytes are re mapped to flash boot sector Read Part ID Table 175 ISP Read Part ID command description Command J Input None Return Code CMD SUCCESS followed by part identification number in ASCII format This command is used to read the part identification number Read Boot code version Table 176 ISP Read Boot Code version command description Command K Input None CMD SUCCESS followed by 2 bytes of boot code version number in ASCII format It is to be Return Code interpreted as lt byte1 Major gt lt byte0 Minor gt This command is used to read the boot code version number Flash Memory System and Programming 231 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Compare lt address1 gt lt address2 gt number of bytes gt Table 177 ISP Compare command description Command M Address1 DST Starting Flash or RAM address from where data bytes are to be compared This address should be on word boundary Input Address2 SRO Starting Fl
35. Data valid Gala WST2 1 XCLK CS OE WE BLS Addr valid address Data valid data Figure 11 External memory write access WST2 0 and WST2 1 examples Figure 10 and Figure 11 are showing typical read and write accesses to external memory However variations can be noticed in some particular cases For example when the first read access to the memory bank that has just been selected is performed CS and OE lines may become low one XCLK cycle earlier than it is shown in Figure 10 Likewise in a sequence of several consecutive write accesses to SRAM the last write access will look like those shown in Figure 11 On the other hand leading write cycles in that case will have data valid one cycle longer Also isloated write access will be identical to the one in Figure 11 External Memory Controller EMC 46 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 EXTERNAL MEMORY SELECTION Based on the description of the EMC operation and external memory in general appropriate read and write access times taa and twrite respecitely the following table can be constructed and used for external memory selection tcyc is the period of a single XCLK cycle see Figure 10 and Figure 11 fmax is the maximum cclk frequency achievable in the system with selected external memory Table 10 External memory and system
36. LPC2114 2124 2212 2214 Table 147 Alarm Mask Register Bits AMR 0xE0024010 Function Description AMRSEC When one the Second value is not compared for the alarm AMRMIN When one the Minutes value is not compared for the alarm AMRHOUR When one the Hour value is not compared for the alarm AMRDOM When one the Day of Month value is not compared for the alarm aro Wren one e Mont value isror compared orte damn Real Time Clock 203 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 CONSOLIDATED TIME REGISTERS The values of the Time Counters can optionally be read in a consolidated format which allows the programmer to read all time counters with only three read operations The various registers are packed into 32 bit values as shown in Tables 148 149 and 150 The least significant bit of each register is read back at bit 0 8 16 or 24 The Consolidated Time Registers are read only To write new values to the Time Counters the Time Counter addresses should be used Consolidated Time Register 0 CTIMEO 0xE0024014 The Consolidated Time Register O contains the low order time values Seconds Minutes Hours and Day of Week Table 148 Consolidated Time Register 0 Bits CTIMEO 0xE0024014 CTIMEO Function Description Reserved user software should not write ones to reserved bits The value read from a reserved 31 27 Reserved a bit is not defined
37. Microcontroller LPC2114 2124 2212 2214 ON CHIP STATIC RAM The LPC2114 2124 2212 2214 provide a 16 kB static RAM memory that may be used for code and or data storage The SRAM supports 8 bit 16 bit and 32 bit accesses The SRAM controller incorporates a write back buffer in order to prevent CPU stalls during back to back writes The write back buffer always holds the last data sent by software to the SRAM This data is only written to the SRAM when another write is requested by software the data is only written to the SRAM when software does another write If a chip reset occurs actual SRAM contents will not reflect the most recent write request i e after a warm chip reset the SRAM does not reflect the last write operation Any software that checks SRAM contents after reset must take this into account Two identical writes to a location guarantee that the data will be present after a Reset Alternatively a dummy write operation before entering idle or power down mode will similarly guarantee that the last data written will be present in SRAM after a subsequent Reset Introduction 18 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 BLOCK DIAGRAM System Clock Emulation Trace Module Vectored Interrupt Controller AMBA AHB ARM7 Local Bus Advanced High performance Bus Internal SRAM Internal Flash AHB Controller Controller Decoder AHB to VPB VPB R30 O 107
38. Mode Fault MODF SPI Interrupt Flag SPIF Mode Fault MODF PLL PLL Lock PLOCK 12 RTC Counter Increment RTCCIF Alarm RTCALF TIMER1 4 o SPIO SPI1 A Co System Control External Interrupt O EINTO System Control External Interrupt 1 EINT1 System Control External Interrupt 2 EINT2 System Control External Interrupt 3 EINT3 A D A D Converter za sex es ise m s Vectored Interrupt Controller VIC 86 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 nVICFIQIN Interrupt Request Masking and Selection Non vectored FIQ Interrupt Logic SoftlntClear IntEnableClear r 1 1 Ale aS a gt nVICFIQ FIQStatus SoftInt IntEnable 31 0 FIQStatus 31 0 31 0 31 0 VICINT u SOURCE ar Non vectored IRQ Interrupt Logic 31 0 IRQ NonVectIRQ Rawlnterrupt IntSelect S gt 31 0 31 0 i Vector Interrupt 0 Priory Q nterrupt Priority Logic f I VectlRQO Hardware Priority Do nVICIRQ Logic VectorAddr VectAddro 31 0 Address Select for VectorCntl 5 0 31 0 Highest Priority Interrupt Vector Interrupt 1 Priority 1 i VectIRQ1 VectAddr1 31 0 RATE VICVECT ea i Priority 2 31 0 Vector Interrupt 15 Priority 14 i VectIRQ15 Default Es VectAddr15 31 0 VectorAddr i i 31 0 el
39. Pin name Pin direction Pin Description X1 Input Crystal Oscillator Input Input to the oscillator and internal clock generator circuits Output Crystal Oscillator Output Output from the oscillator amplifier External Interrupt Input 0 An active low general purpose interrupt input This pin may be used to wake up the processor from Idle or Power down modes EINTO Input Pins P0 1 and P0 16 can be selected to perform EINTO function LOW level on this pin immediately after reset is considered as an external hardware request to start the ISP command handler More details on ISP and Flash memory can be found in Flash Memory System and Programming chapter External Interrupt Input 1 See the EINTO description above EINT1 Input Pins P0 3 and P0 14 can be selected to perform EINT1 function External Interrupt Input 2 See the EINTO description above EINT2 Input Pins PO 7 and P0 15 can be selected to perform EINT2 function External Interrupt Input 3 See the EINTO description above EINT3 Input Pins P0 9 P0 20 and P0 30 can be selected to perform EINT3 function RESET Input External Reset input A low on this pin resets the chip causing I O ports and peripherals P to take on their default states and the processor to begin execution at address 0 System Control Block 49 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 System Control Block 50 May 03 2004 Philips Semic
40. ROM bank This field controls the width of the data bus for this bank 29 28 00 8 bit 01 16 bit 10 32 bit 11 reserved see tales 31 30 Always write 00 to this field 00 Table 8 Bank Configuration Registers 0 3 BCFGO0 3 OXFFE00000 0C The table below shows the state of BCFGO 29 28 after the Boot Loader has run The hardware reset state of these bits is 10 Bank BOOT 1 0 during Reset BCFG 29 28 Reset value Memory Width 0 LL 00 8 bits mo gt A AE o oe sms AAA Table 9 Default memory widths at Reset External Memory Controller EMC 43 May 03 2004 Preliminary User Manual LPC2114 2124 2212 2214 Philips Semiconductors ARM based Microcontroller EXTERNAL MEMORY INTERFACE External memory interface depends on the bank width 32 16 or 8 bit selected via MW bits in corresponding BCFG register Furthermore choice of the memory chip s will require an adequate setup of RBLE bit in BCFG register too RBLE 0 in case of 8 bit based external memories while memory chips capable of accepting 16 or 32 bit wide data will work with RBLE 1 If a memory bank is configured to be 32 bits wide address lines AO and A1 can be used as non address lines Memory bank configured to 16 bits wide will not require AO while 8 bit wide memory bank will require address lines down to AO Configuring A1 and or AO line s to provide address or non address function is acomplished using bits 23 and 24 in Pin Function Sele
41. Receiver FIFO trigger points at 1 4 8 and 14 bytes Built in baud rate generator PIN DESCRIPTION Table 73 UARTO Pin Description Pin Name Type Description RxDO Input Serial Input Serial receive data Output Serial Output Serial transmit data UARTO 121 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 REGISTER DESCRIPTION Table 74 UARTO Register Map Name Description BIT4 BIT3 Receiver UORBR Buffer READ DATA Register Transmit UOTHR Holding WRITE DATA WO Register Interrupt UOIER Enable Register Interrupt Enable THRE Interrupt Enable Rx Data Available Enable Rx Line A d 0xE000C008 NA BH 0xE000C008 u OxEO00C00C OxE000C014 0x01 IR3 IIR2 IIR 1 voir I lerrupt ID eros Enabled Register FIFO UOFCR Control Rx Trigger Reserved Register UOLCR Line Control Register uosa Ure Sas 9 Error UOSCR Scratch Pad Register Divisor Latch Divisor Latch E Reset Value refers to the data stored in used bits only It does not include reserved bits content WO Tx FIFO Reset Rx FIFO Reset FIFO Enable Word Length Select Break TEMT gt DLAB O Parity DEJEN B LS EI 0xE000C01C tsp gw o 0xE000C000 Ls M M DLAB 1 0xE000C004 DLAB 1 UARTO contains ten 8 bit registers as shown in Table 74 The Divisor Latch Access Bit DLAB is contained in UOLCR7 and enables access to the
42. Registers VICVectCntl0 15 OXFFFFF200 23C Read Write VICVectCntl0 15 Function Reset Value 5 1 this vectored IRQ slot is enabled and can produce a unique ISR address when its 0 assigned interrupt request or software interrupt is enabled classified as IRQ and asserted The number of the interrupt request or software interrupt assigned to this vectored IRQ slot As a matter of good programming practice software should not assign the same interrupt number to more than one enabled vectored IRQ slot But if this does occur the lower numbered slot will be used when the interrupt request or software interrupt is enabled classified as IRQ and asserted Vector Address Registers 0 15 VICVectAddr0 15 OXFFFFF100 13C Read Write These registers hold the addresses of the Interrupt Service routines ISRs for the 16 vectored IRQ slots Table 50 Vector Address Registers VICVectAddr0 15 OXFFFFF100 13C Read Write VICVectAddr0 15 Function Reset Value When one or more interrupt request or software interrupt is are enabled classified as IRQ 31 0 asserted and assigned to an enabled vectored IRQ slot the value from this register for the 0 highest priority such slot will be provided when the IRQ service routine reads the Vector Address register VICVectAddr Default Vector Address Register VICDefVectAddr OxFFFFF034 Read Write This register holds the address of the Interrupt Service routine ISR for non vector
43. Select Register 2 for LPC2114 2124 PINSEL2 0xE002C014 PINSEL2 Description Reset Value 1 0 Reserved 00 When 0 pins P1 36 26 are used as GPIO pins When 1 P1 31 26 are used as a Debug port P1 26 RTCK A P1 20 When 0 pins P1 25 16 are used as GPIO pins When 1 P1 25 16 are used as a Trace port TRACESYNC Reserved Am Note These bits must not be altered at any time Changing them may result in an incorrect code 1 execution Reserved Pin Connect Block 111 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 64 Pin Function Select Register 2 for LPC2212 2214 PINSEL2 0xE002C014 PINSEL2 Description Reset Value Reserved When 0 pins P1 36 26 are used as GPIO pins When 1 P1 31 26 are used as a Debug port P1 26 RTCK 1 When 0 pins P1 25 16 are used as GPIO pins When 1 P1 25 16 are used as a Trace port SE ee en 0 pins are p P1 25 pott TRACESYNC 5 REE Controls the use of the data bus and strobe pins Pins P2 7 0 11 P2 7 0 Ox or 10 Pin P1 0 11 P1 0 Ox or 10 Pin P1 1 11 2 P1 1 Ox or 10 Pin P3 31 11 P3 31 Ox or 10 Pins P2 15 8 00 or 11 P2 15 8 01 or 10 BOOT1 0 Pin P3 30 00 or 11 P3 30 01 or 10 Pins P2 27 16 Oxor11 P2 27 16 10 Pins P2 29 28 Oxor11 P2 29 28 10 Pins P2 31 30 Ox or 11 P2 31 30 or AIN5 4 10 Pins P3 29 28 Ox or 11 P3 29 28 or AIN6 7 10 EE El BET ATM 00 If bits 5 4 are not 10 controls the use of
44. TIMER1 2 Pin Connect Block 110 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 60 Pin Function Select Register 1 for LPC2114 2124 2212 2214 PINSEL1 0xE002C004 PINSEL1 na Function when 00 Function when 01 Function when 10 Function when 11 GPIO Port 0 21 PWM5 Capture 1 3 TIMER1 13 12 P0 22 GPIO Port 0 22 Capture 0 0 TIMERO Match 0 0 TIMERO 23 22 P0 27 GPIO Port 0 27 AINO A D Converter Capture 0 1 TIMERO Match 0 1 TIMERO 071 25 24 P0 28 GPIO Port 0 28 AIN1 A D Converter Capture 0 2 TIMERO Match 0 2 TIMERO 01 27 26 P0 29 GPIO Port 0 29 AIN2 A D Converter Capture 0 3 TIMERO Match 0 3 TIMERO 01 29 28 P0 30 GPIO Port 0 30 AIN3 A D Converter EINT3 Capture 0 0 TIMERO 01 31 30 P0 31 Reserved 00 P0 21 Pin Function Select Register 2 PINSEL2 0xE002C014 The PINSEL2 register controls the functions of the pins as per the settings listed in Table 63 The direction control bit in the IO1DIR register is effective only when the GPIO function is selected for a pin For other functions direction is controlled automatically Warning use read modify write operation when accessing PINSEL2 register Accidental write of 0 to bit 2 and or bit 3 results in loss of debug and or trace functionality Changing of either bit 4 or bit 5 from 1 to 0 may cause an incorrect code execution Table 63 Pin Function
45. This asserts the corresponding interrupt request to the VIC which will cause an intrerrupt if interrupts from the pin are enabled Writing ones to bits EINTO through EINT3 in EXTINT register clears the corresponding bits In level sensitive mode this action is efficacious only when the pin is in its innactive state System Control Block 54 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 15 External Interrupt Flag Register EXTINT OXEO1FC140 EXTINT Function Description In level sensitive mode this bit is set if the EINTO function is selected for its pin and the pin is in its active state In edge sensitive mode this bit is set if the EINTO function is selected for its pin and the selected edge occurs on the pin 0 Up to two pins can be selected to perform EINTO function see P0 1 and P0 16 description in Pin Configuration chapter This bit is cleared by writing a one to it except in level sensitive mode when the pin is in its active state In level sensitive mode this bit is set if the EINT1 function is selected for its pin and the pin is in its active state In edge sensitive mode this bit is set if the EINT1 function is selected for its pin and the selected edge occurs on the pin Up to two pins can be selected to perform EINT1 function see P0 3 and P0 14 description in Pin Configuration chapter This bit is cleared by writing a one to it e
46. added to to Introduction chapter 13 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 TOIR TOCCR TOTCR T1TCR TOEMR and PCONP updated in Introduction chapter EXTMODE and EXTPOLAR registers added in Introduction chapter and updated in System Control Block chapter Power Control Usage Notes for reducing the total power added to System Control Block chapter PINSEL2 register as well as booting procedure updated in Pin Connect Block and Watchdog chapters references to the pclk in External Memory Controller EMC chapter corrected to the cclk LPC2212 2214 PINSEL2 table in Pin Connect Block chapter corrected A D pin description in A D Converter chapter rephrased Information on Spurious Interrupts added into Vectored Interrupt Controller VIC chapter Details on the checksum generation in case of Read Memory and Write to RAM ISP commands added in Flash Memory System and Programming chapter 14 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 1 INTRODUCTION GENERAL DESCRIPTION The LPC2114 2124 2212 2214 are based on a 16 32 bit ARM7TDMI S CPU with real time emulation and embedded trace support together with 128 256 kilobytes kB of embedded high speed flash memory A 128 bit wide internal memory interface and a unique accelerator architecture enable 32 bit code execution a
47. address lines 000 if BOOT1 0 11 at Reset 111 010 A5 2 are address lines 110 A19 2 are address lines otherwise 011 A7 2 are address lines 111 A23 2 are address lines Pin Function Select Register Values 001 A3 2 are address lines 101 2 A15 2 are address lines The PINSEL registers control the functions of device pins as shown below Pairs of bits in these registers correspond to specific device pins Table 65 Pin Function Select Register Bits PinselO and Pinseli Values Function Value after Reset Primary default function typically GPIO Port First alternate function Second alternate function Reserved The direction control bit in the IOODIR IO1DIR register is effective only when the GPIO function is selected for a pin For other functions direction is controlled automatically Each derivative typically has a different pinout and therefore a different set of functions possible for each pin Details for a specific derivative may be found in the appropriate data sheet Pin Connect Block 113 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 BOOT CONTROL ON 144 PIN PACKAGE In the 144 pin package only the state of the BOOT1 0 pins while RESET is low controls booting and initial operation Internal pullups in the receivers ensure high state if a pin is left unconnected Board designers can connect weak pulldown resistors 10 KQ
48. adjusted Fast Interrupt reQuest FIQ requests have the highest priority If more than one request is assigned to FIQ the VIC ORs the requests to produce the FIQ signal to the ARM processor The fastest possible FIQ latency is achieved when only one request is classified as FIQ because then the FIQ service routine can simply start dealing with that device But if more than one request is assigned to the FIQ class the FIQ service routine can read a word from the VIC that identifies which FIQ source s is are requesting an interrupt Vectored IRQs have the middle priority but ony 16 of the 32 requests can be assigned to this category Any of the 32 requests can be assigned to any of the 16 vectored IRQ slots among which slot O has the highest priority and slot 15 has the lowest Non vectored IRQs have the lowest priority The VIC ORs the requests from all the vectored and non vectored IRQs to produce the IRQ signal to the ARM processor The IRQ service routine can start by reading a register from the VIC and jumping there If any of the vectored IRQs are requesting the VIC provides the address of the highest priority requesting IRQs service routine otherwise it provides the address of a default routine that is shared by all the non vectored IRQs The default routine can read another VIC register to see what IRQs are active All registers in the VIC are word registers Byte and halfword reads and write are not supported Additional informatio
49. an error condition in slave mode When STO is 1 in master mode a STOP condition is transmitted on the IC bus When the bus detects the STOP condition STO is cleared automatically In slave mode setting this bit can recover from an error condition In this case no STOP condition is transmitted to the bus The hardware behaves as if a STOP condition has been received and it switches to not addressed slave receiver mode The STO flag is cleared by hardware automatically STA is the START flag Setting this bit causes the I C interface to enter master mode and transmit a START condition or transmit a repeated START condition if it is already in master mode When STA is 1and the IC interface is not already in master mode it enters master mode checks the bus and generates a START condition if the bus is free If the bus is not free it waits for a STOP condition which will free the bus and generates a START condition after a delay of a half clock period of the internal clock generator If the 12C interface is already in master mode and data has been transmitted or received it transmits a repeated START condition STA may be set at any time including when the 12C interface is in an addressed slave mode STA can be cleared by writing 1 to the STAC bit in the IICONCLR register When STA is 0 no START condition or repeated START condition will be generated If STA and STO are both set then a STOP condition is transmitted on the IC bus if it the i
50. bit data R W SELO register 0 PIN Pin function 0xE002C004 select 32 bit data R W SEL1 register 1 Pin function 24 bit 24 bitpin configuration data 144 package case R data AA package case PIN PAREDES SEL2 select Reserved bits 64 Reservedbits 64package case case register 2 AE MN data ADC Introduction 29 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 2 LPC2114 2124 2212 2214 Registers Address T E Reset Offset Description LSB Access Value EDGE START 0xE0034000 ADC Control TESTO PON CLKS register 8 bit data Po Bitar bit data A Oo 0xE0034004 ADDR ADC Data register o EN System Control Block oxEo1FCooo MAM MAM control 2 bit data R W CR register oxE01Fcoo4 MAM j MAM timing sbitaate Ll oor TIM control MEM Memory 0xE01FC040 mapping 2 bit data R W MAP control PLL PLL control PLL PLL 0xE01FC084 CFG configuration 2bit data PSEL 5 bit data MSEL R W register oxeo1rcogg PLL PLL status ee o STAT register 2bit data PSEL 5 bit data MSEL PLL PLL feed 0xE01FC08C FEED register 8 bit data register Power control reserved 19 bits poao hie ES Es 0xE01FCOC4 PCONP for R W 0x3BE peripherals PC PC PC PC oe sae URT1 URTO TIM1 TIMO oxE01Fc100 MPO VPB divider 2 bit data DIV control External OxEO1FC140 interrupt flag EINT3 EINT2 EINT1 EINTO register
51. block Each bit in PCONP controls one of the peripherals The bit numbers correspond to the related peripheral number as shown in the VPB peripheral map in the LPC2114 2124 2212 2214 Memory Addressing section Table 31 Power Control for Peripherals Register for LPC2114 2124 PCONP OxEO1FCOCA PCONP Function Description Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Reserved PCPWMO When 1 PWMO is enabled When 0 PWMO is disabled to conserve power User software should not write ones to reserved bits The value read from a reserved bit is not Reserved defined 7 PCI2C When 1 the IC interface is enabled When 0 the 12C interface is disabled to conserve power PCSPIO When 1 the SPIO interface is enabled When 0 the SPIO is disabled to conserve power PCRTC When 1 the RTC is enabled When 0 the RTC is disabled to conserve power 10 PCSPI1 When 1 the SPI1 interface is enabled When 0 the SPI1 is disabled to conserve power 11 Reserved User software should write O here to reduce power consumption 12 PCAD When 1 the A D converter is enabled When 0 the A D is disabled to conserve power Reserved user software should not write ones to reserved bits The value read from a reserved 31 13 Reserved NA bit is not defined Table 32 Power Control for Peripherals Register for LPC2212 2214 PCONP 0xE01FC0C4 PCONP Function D
52. bottom of memory to allow handling exceptions and using interrupts during the Boot Loading process Boot Loader Hardware activation mode by any Reset Activated by Boot Loader when a valid User Program Signature is recognized in memory and Boot Loader operation is not forced Interrupt vectors are not re mapped and are found in the bottom of the Flash memory User Flash Software activation mode by Boot code User RAM Software activation Activated by a User Program as desired Interrupt vectors are re mapped to the bottom mode by User program of the Static RAM Activated by the Boot Loader when either or both BOOT pins are low at the end of Activated by RESET low Interrupt vectors are re mapped from the bottom of the external memory BOOT1 0 pins not map 11 at Reset User External mode Note This mode is available in LPC2212 2214 only LPC2114 2124 2212 2214 Memory Addressing 37 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Memory Re Mapping In order to allow for compatibility with future derivatives the entire Boot Block is mapped to the top of the on chip memory space In this manner the use of larger or smaller flash modules will not require changing the location of the Boot Block which would require changing the Boot Loader code itself or changing the mapping of the Boot Block interrupt vectors Memory spaces other than the interrupt vectors remain
53. by software if the RTC is enabled Real Time Clock 199 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 RTC INTERRUPTS Interrupt generation is controlled through the Interrupt Location Register ILR Counter Increment Interrupt Register CIIR the alarm registers and the Alarm Mask Register AMR Interrupts are generated only by the transition into the interrupt state The ILR separately enables CIIR and AMR interrupts Each bit in CIIR corresponds to one of the time counters If CIIR is enabled for a particular counter then every time the counter is incremented an interrupt is generated The alarm registers allow the user to specify a date and time for an interrupt to be generated The AMR provides a mechanism to mask alarm compares If all non masked alarm registers match the value in their corresponding time counter then an interrupt is generated Real Time Clock 200 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 MISCELLANEOUS REGISTER GROUP Table 142 summarizes the registers located from 0 to 7 of A 6 2 More detailed descriptions follow Table 142 Miscellaneous Registers Address i Description Access Interrupt Location Reading this location indicates the source of an 0xE0024000 interrupt Writing a one to the appropriate bit at this location clears the RW associated int
54. device informati0N ooooooooooooooro eee ene 16 Table 2 LPC2114 2124 2212 2214 RegisterS oooooocoocococccn ne 20 Table 3 ARM Exception Vector Locations lisse tet 37 Table 4 LPC2114 2124 2212 2214 Memory Mapping Modes 0 00 e cence eee eee 37 Table 5 Address Ranges of External Memory Banks LPC2212 2214 only 0000 eeu 41 Table 6 External Memory Controller Pin Description 0 00000 cece e 42 Table 7 External Memory Controller Register Map oococococcococccnr 42 Table 8 Bank Configuration Registers 0 3 BCFGO 3 OXFFE00000 0C lssssseses 0 eee 43 Table 9 Default memory widths at Reset ooooccooccccooocc tees 43 Table 10 External memory and system requirements 0 0 cee eee 47 Tableti Pin surimary o a A UAE RIP VEG ELE SAEC RE EER CERES 49 Table 12 Summary of System Control Registers o ooooooooooooro eee 51 Table 13 Recommended values for CX1 X2 in oscillation mode crystal and external components parameters oooooccoccocor eee 52 Table 14 External Interrupt Registers III 54 Table 15 External Interrupt Flag Register EXTINT OXEO1FC140 ssseses esee eere 55 Table 16 External Interrupt Wakeup Register EXTWAKE OXEO1FC144 00 0002 56 Table 17 External Interrupt Mode Register EXTMODE OXEO1FC148 0000 e eee eee 56 Table 18 External Interrupt Polarity Register EXTPOLAR OxEO1FC14C
55. edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle when an PWMMRO match occurs Pulse Width Modulator PWM 179 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Three match registers can be used to provide a PWM output with both edges controlled Again the PNMMRO match register controls the PWM cycle rate The other match registers control the two PWM edge positions Additional double edge controlled PWM outputs require only two match registers each since the repetition rate is the same for all PWM outputs With double edge controlled PWM outputs specific match registers control the rising and falling edge of the output This allows both positive going PWM pulses when the rising edge occurs prior to the falling edge and negative going PWM pulses when the falling edge occurs prior to the rising edge Figure 38 shows the block diagram of the PWM The portions that have been added to the standard timer block are on the right hand side and at the top of the diagram Pulse Width Modulator PWM 180 May 03 2004 Philips Semiconductors ARM based Microcontroller Match Register 0 Match Register 1 Match Register 2 Match Register 3 Match Register 4 Match Register 5 Match Register 6 Shadow Register O Load Enable Shadow Register 1 Load Enable Shadow Register 2 Load Enable Shadow Register 3 Load E
56. end user application code APPLICATIONS The flash boot loader provides both In System and In Application programming interfaces for programming the on chip flash memory DESCRIPTION The flash boot loader code is executed every time the part is powered on or reset The loader can execute the ISP command handler or the user application code A LOW level after reset at the P0 14 pin is considered as the external hardware request to start the ISP command handler This pin is sampled in software Asuming that proper signal is present on X1 pin when the rising edge on RST pin is generated it may take up to 3 ms before P0 14 is sampled and the decision on wether to continue with user code or ISP handler is made If P0 14 is sampled low and the watchdog overflow flag is set the external hardware request to start the ISP command handler is ignored If there is no request for the ISP command handler execution P0 14 is sampled HIGH after reset a search is made for a valid user program If a valid user program is found then the execution control is transferred to it If a valid user program is not found the auto baud routine is invoked Pin P0 14 that is used as hardware request for ISP requires special attention Since P0 14 is in high impedance mode after reset it is important that the user provides external hardware a pull up resistor or other device to put the pin in a defined state Otherwise unintended entry into ISP mode may occur Memory map
57. feed values is incorrect or one of the previously mentioned conditions is not met any changes to the PLLCON or PLLCFG register will not become effective Table 26 PLL Feed Register PLLFEED 0xE01FC08C Reset PLLFEED Function Description Value The PLL feed sequence must be written to this register in order for PLL configuration and control register changes to take effect 7 0 PLLFEED undefined PLL and Power Down Mode Power Down mode automatically turns off and disconnects the PLL Wakeup from Power Down mode does not automatically restore the PLL settings this must be done in software Typically a routine to activate the PLL wait for lock and then connect the PLL can be called at the beginning of any interrupt service routine that might be called due to the wakeup It is important not to attempt to restart the PLL by simply feeding it when execution resumes after a wakeup from Power Down mode This would enable and connect the PLL at the same time before PLL lock is established PLL Frequency Calculation The PLL equations use the following parameters Fosc the frequency from the crystal oscillator Foco the frequency of the PLL current controlled oscillator cclk the PLL output frequency also the processor clock frequency M PLL Multiplier value from the MSEL bits in the PLLCFG register P PLL Divider value from the PSEL bits in the PLLCFG register The PLL output frequency when the PLL is both active and connected
58. from any peripheral clock frequency greater than or equal to 65 536 kHz 2 x 32 768 kHz This permits the RTC to always run atthe proper rate regardless of the peripheral clock rate Basically the Prescaler divides the peripheral clock pclk by a value which contains both an integer portion and a fractional portion The result is not a continuous output at a constant frequency some clock periods will be one pclk longer than others However the overall result can always be 32 768 counts per second The reference clock divider consists of a 13 bit integer counter and a 15 bit fractional counter The reasons for these counter sizes are as follows 1 For frequencies that are expected to be supported by the LPC2114 2124 2212 2214 a 13 bit integer counter is required This can be calculated as 160 MHz divided by 32 768 minus 1 2 4881 with a remainder of 26 624 Thirteen bits are needed to hold the value 4881 but actually supports frequencies up to 268 4 MHz 32 768 x 8192 2 The remainder value could be as large as 32 767 which requires 15 bits Table 154 Reference Clock Divider registers Address Name Size Description Access 0xE0024080 PREINT 13 Prescale Value integer portion 0xE0024084 PREFRAC Prescale Value fractional Prescale Value fractional portion Prescaler Integer Register PREINT 0xE0024080 This is the integer portion of the prescale value calculated as PREINT int pclk 32768 1 The value of PREINT mu
59. function is enabled and whether a capture event happens on the rising edge of the associated pin the falling edge or on both edges Capture Control Register CCR TIMERO TOCCR 0xE0004028 TIMER1 T1CCR 0xE0008028 The Capture Control Register is used to control whether one of the four Capture Registers is loaded with the value in the Timer Counter when the capture event occurs and whether an interrupt is generated by the capture event Setting both the rising and falling bits at the same time is a valid configuration resulting in a capture event for both edges In the description below n represents the Timer number 0 or 1 Table 126 Capture Control Register CCR TIMERO TOCCR 0xE0004028 TIMER1 T1CCR 0xE0008028 Reset Function Description Value Capture on CAPn 0 When one a sequence of 0 then 1 on CAPn 0 will cause CRO to be loaded with rising edge the contents of the TC When zero this feature is disabled 1 Capture on CAPn 0 When one a sequence of 1 then 0 on CAPn 0 will cause CRO to be loaded with falling edge the contents of TC When zero this feature is disabled Interrupt on CAPn 0 When one a CRO load due to a CAPn 0 event will generate an interrupt When event zero this feature is disabled Capture on CAPn 1 When one a sequence of 0 then 1 on CAPn 1 will cause CR1 to be loaded with rising edge the contents of the TC When zero this feature is disabled 0 0 Capture on CAPn 1 When one a sequ
60. if the external modem is ready to accept transmitted data via TxD1 from the UART1 In normal operation of the modem interface U1MCR4 0 the complement value of this signal is stored in U1MSR4 State change information is stored in U1MSRO and is a source for a priority level 4 interrupt if enabled U1IER3 1 CTS1 Input Data Carrier Detect Active low signal indicates if the external modem has established a communication link with the UART1 and data may be exchanged In normal operation of the modem interface U1MCR4 0 the complement value of this signal is stored in UT MSR7 State change information is stored in U1 MSR3 and is a source for a priority level 4 interrupt if enabled U1IER3 1 Data Set Ready Active low signal indicates if the external modem is ready to establish a communications link with the UART1 In normal operation of the modem interface Input U1MCR4 0 the complement value of this signal is stored in U1 MSR5 State change information is stored in U1MSR1 and is a source for a priority level 4 interrupt if enabled U1IER3 1 DTR1 Output Data Terminal Ready Active low signal indicates that the UART1 is ready to establish P connection with external modem The complement value of this signal is stored in Uf MCRO Ring Indicator Active low signal indicates that a telephone ringing signal has been detected by the modem In normal operation of the modem interface U1MCR4 0 the complement value of this signal is st
61. in R1 typedef void IAP unsigned int unsigned int IAP iap entry Setting function pointer iap entry IAP IAP LOCATION Whenever you wish to call IAP you could use the following statement iap entry command result The IAP call could be simplified further by using the symbol definition file feature supported by ARM Linker in ADS ARM Developer Suite You could also call the IAP routine using assembly code The following symbol definitions can be used to link IAP routine and user application lt SYMDEFS gt ARM Linker ADS1 2 Build 826 Last Updated Wed May 08 16 12 23 2002 Ox7fffff90 T rm init entry Ox7fffffa0 A rm undef handler Flash Memory System and Programming 234 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Ox7fffffbO rm prefetchabort handler Ox7fffffcO rm dataabort handler Ox 7fffffd0 rm irghandler Dopo mp P Ox7fffffe0 rm_irghandler2 Ox7ffffffO0 T iap entry As per the ARM specification The ARM Thumb Procedure Call Standard SWS ESPC 0002 A 05 up to 4 parameters can be passed in the rO r1 r2 and r3 registers respectively Additional parameters are passed on the stack Up to 4 parameters can be returned in the rO r1 r2 and r3 registers respectively Additional parameters are returned indirectly via memory Some of the IAP calls require more than 4 parameters If the ARM suggested scheme is used for the parameter passing retu
62. in kHz at which the part is running For example if the part is running at 10 MHz a valid response from the host should be 10000 lt CR gt lt LF gt OK lt CR gt lt LF gt string is sent to the host after receiving the crystal frequency If synchronization is not verified then the auto baud routine waits again for a synchronization character For auto baud to work correctly the crystal frequency should be greater than or equal to 10 MHz The on chip PLL is not used by the boot code Once the crystal frequency is received the part is initialized and the ISP command handler is invoked For safety reasons an Unlock command is required before executing commands resulting in flash erase write operations and the Go command The rest of the commands can be executed without the unlock command The Unlock command is required to be executed once per ISP session Unlock command is explained in the ISP Commands section Flash Memory System and Programming 218 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Communication Protocol All ISP commands should be sent as single ASCII strings Strings should be terminated with Carriage Return CR and or Line Feed LF control characters Extra CR and lt LF gt characters are ignored All ISP responses are sent as lt CR gt lt LF gt terminated ASCII strings Data is sent and received in UU encoded format ISP Command Format Comman
63. is CCLK VPB divider rate as determined by the VPBDIV register contents SPI Interrupt Register SOSPINT 0xE002001C S1SPINT 0xE003001C This register contains the interrupt flag for the SPI interface Table 120 SPI Interrupt Register SOSPINT 0xE002001C S1SPINT 0xE003001C Function Description SPI interrupt flag Set by the SPI interface to generate an interrupt Cleared by writing a 1 to this bit SPI Interrupt Note this bit will be set once when SPIE 1 and at least one of SPIF and WCOL bits is 1 However only when SPI Interrupt bit is set and SPI Interrupt is enabled in the VIC SPI based interrupt can be processed by interrupt handling software Reserved user software should not write ones to reserved bits The value read from 7 1 Reserved A NA a reserved bit is not defined SPI Interface 166 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 ARCHITECTURE The block diagram of the SPI solution implemented in SPIO and SPI1 interfaces is shown in the Figure 34 MOSI in MOSI out MISO in MISO out SPI Shift Register gt I SPI Clock Generator amp Detector SPI Interrupt SPI Register Interface Y VPB Bus lt a dE SPI State Control n SCK_out_en MOSI_out_en Output MISO_out_en Enable p Logic Figure 34 SPI Block Diagram
64. last value written to the PWM Match 1 register to be become effective when the timer is next reset by a PWM Match event See the description of the PWM Match Control Register PWMMCR Enable PWM Match 1 Latch Writing a one to this bit allows the last value written to the PWM Match 2 register to be become effective when the timer is next reset by a PWM Match event See the description of the PWM Match Control Register PWMMCR Enable PWM Match 2 Latch Writing a one to this bit allows the last value written to the PWM Match 3 register to be become effective when the timer is next reset by a PWM Match event See the description of the PWM Match Control Register PWMMCR Enable PWM Match 3 Latch Writing a one to this bit allows the last value written to the PWM Match 4 register to be become effective when the timer is next reset by a PWM Match event See the description of the PWM Match Control Register PWMMCR Enable PWM Match 4 Latch Writing a one to this bit allows the last value written to the PWM Match 5 register to be become effective when the timer is next reset by a PWM Match event See the description of the PWM Match Control Register PWMMCR Enable PWM Match 5 Latch Writing a one to this bit allows the last value written to the PWM Match 6 register to be become effective when the timer is next reset by a PWM Match event See the description of the PWM Match Control Register PWMMCR Reserved Reserved user sof
65. m Reset Offset Name Description LSB Access Value 12C Slave 0xE001C00C Address 7 bit data GC R W 0 ADR Register SCL Duty 12 Cycle 0xE001C010 SCLH Register High 16 bit data R W 0x04 Half Word SCL Duty 12 Cycle 0xE001C014 SCLL Register Low 16 bit data R W 0x04 Half Word 12C Control 0xE001C018 n Clear I2ENC STAC SIC AAC WO NA Register oxeoo20000 2 SPIO Control coe LsBF msTR CPOL CPHA R W SPCR Register oxE0020004 S0__ SPIO Status Spie wcoL RovR MODF ABRT SPSR Register SO SPIO Data 0xE0020008 SPDR a bit data SO SPIO Clock 0xE002000C Counter 8 bit data R W SPCCR Register S0 SPIO SPI oxeoo30000 St SPH Control Spie ser msTR CPOL CPHA R W SPCR Register oxeoo30004 S SPH Status lt p woot RoyR Mopr ABRT SPSR Register S1 SPI Data 0xE0030008 png e s4 SPI Clock 0xE003000C Counter 8 bit data R W SPCCR Register si SPI SPI Introduction 26 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 2 LPC2114 2124 2212 2214 Registers Address Reset Offset Name Description LSB Access Value Interrupt RTC RTC 0xE0024000 Location ALF CIF Register ossooza0os oro E Tick 15 bit data EE Clock Control CTC E Counter Increment IM IM IM IM IM IM IM IM 0xE002400C redi Interrupt YEAR MON DOY DOW DOM HOUR MIN SEC Register 0xE0024010 Alarm Mask AMR AMR
66. master or data output from SPI slave MATO 1 Match output for TIMERO channel 1 MOSIO Master Out Slave In for SPIO Data output from SPI master or data input to SPI slave CAPO0 2 Capture input for TIMERO channel 2 SSELO Slave Select for SPIO Selects the SPI interface as a slave PWM2 Pulse Width Modulator output 2 EINT2 External interrupt 2 input TxD1 Transmitter output for UART1 PWMA Pulse Width Modulator output 4 RxD1 Receiver input for UART1 PWM6 Pulse Width Modulator output 6 EINT3 External interrupt 3 input Pin Configuration 94 May 03 2004 Philips Semiconductors ARM based Microcontroller Table 55 Pin description for LPC2114 2124 Preliminary User Manual LPC2114 2124 2212 2214 LQFP64 O GN Important Pin Configuration Request to Send output for UART1 Capture input for TIMER1 channel 0 Clear to Send input for UART1 Capture input for TIMER1 channel 1 Data Set Ready input for UART1 Match output for TIMER1 channel 0 Data Terminal Ready output for UART1 Match output for TIMER1 channel 1 Data Carrier Detect input for UART1 External interrupt 1 input LOW on this pine while RESET is LOW forces on chip boot loader to take over control of the part after reset LOW on pin P0 14 while RESET is LOW forces on chip boot loader to take over control of the part after reset Ring Indicator input for VART1 External interrupt 2 input External interrupt 0 input Match output for T
67. o CR2 Capture Register 2 See CRO description CR3 Capture Register 3 See CRO description EMR External Match Register The EMR controls the external match pins MATO 0 3 MAT1 0 3 Reset Value refers to the data stored in used bits only It does not include reserved bits content TimerO and Timer1 171 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Interrupt Register IR TIMERO TOIR 0xE0004000 TIMER1 T1IR 0xE0008000 The Interrupt Register consists of four bits for the match interrupts and four bits for the capture interrupts If an interrupt is generated then the corresponding bit in the IR will be high Otherwise the bit will be low Writing a logic one to the corresponding IR bit will reset the interrupt Writing a zero has no effect Table 123 Interrupt Register IR TIMERO TOIR 0xE0004000 TIMER1 T1IR 0xE0008000 Reset Function Description Value MRO Interrupt Interrupt flag for match channel 0 0 1 MR1 Interrupt Interrupt flag for match channel 1 eos MR2 Interrupt Interrupt flag for match channel 2 MN E UN A TO DTO merita trance LN Timer Control Register TCR TIMERO TOTCR 0xE0004004 TIMER1 T1TCR 0xE0008004 The Timer Control Register TCR is used to control the operation of the Timer Counter Table 124 Timer Control Register TCR TIMERO TOTCR 0xE0004004 TIMER1 T1TCR 0xE0008004 Reset
68. pin P3 29 0 enables P3 29 1 enables AIN6 1 1 C 1 1 ontrols the use of pin P3 27 0 enables P3 27 1 enables WE 2 3 7 1 1 1 If bits 5 4 are not 10 controls the use of pin P3 28 0 enables P3 28 1 enables AIN7 If bits 25 23 are not 111 controls the use of pin P3 23 A23 XCLK 0 enables P3 23 1 enables ow XCLK Controls the use of pin P3 26 0 enables P3 26 1 enables CS1 15 14 Controls the use of pin P3 25 00 enables P3 25 01 enables CS2 10 and 11 are reserved values 17 16 Controls the use of pin P3 24 00 enables P3 24 01 enables CS3 10 and 11 are reserved values If bits 5 4 are not 10 controls the use of pin P2 29 28 0 enables P2 29 28 1 is reserved If bits 5 4 are not 10 controls the use of pin P2 30 0 enables P2 30 1 enables AIN4 22 If bits 5 4 are not 10 controls the use of pin P2 31 0 enables P2 31 1 enables AIN5 1 if BOOT1 0 00 at RESET 0 0 otherwise Controls whether P3 1 A1 is a port pin 0 or an address line 1 ee 2 2 2 2 Controls whether P3 0 A0 is a port pin 0 or an address line 1 0 4 1 2 3 0 1 2 3 4 Pin Connect Block 112 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 64 Pin Function Select Register 2 for LPC2212 2214 PINSEL2 0xE002C014 Controls the number of pins among P3 23 A23 XCLK and P3 22 2 A2 22 2 that are address lines 000 None 100 A11 2 are
69. reserved bits Cpt 3 TO Capture falling 0xE0004028 TOCCR Control R W Register Int on Int on Int on Int on Int on Int on Cpt 2 Cpt 2 Cpt 1 Cpt 1 Cpt 0 Cpt 0 falling rising falling rising falling rising oxE000402C Tocro 10 Capture 32 bit data Register O 0xE0004030 TocR1 T0 Capture 32 bit data Register 1 0xE0004034 TocR2 T Capture 32 bit data Register 2 Introduction 21 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 2 LPC2114 2124 2212 2214 Registers Address Ert Reset Offset Name Description LSB Access Value 4 reserved bits External Match External Match TO External Control 3 Control 2 0xE000403C TOEMR Match R W 0 xt Register External Match External Match Ext Ext Ext Ext Control 1 Control 0 Mtch3 Mtch2 Mtch 1 Mtch 0 TIMER1 OxEO008000 TIR T1 Interrupt CR3 CR2 CR1 CRO MR3 MR2 MR1 MRO R W Register Int Int Int Int Int Int Int Int T1 Control CTR CTR 0xE0008008 T1TC 32 bit data RW 0 oxEooosooc TiPR I Prescale 32 bit data LIE Register T1 Prescale O aa mer PUES m Counter Stop Reset Stop Int on 4 reserved bits on on MR3 on T1 Match MR3 MR3 MR2 0xE0008014 T1MCR Control R W Register jn Int on en jo Int on id bou Int on MB2 MR2 MR1 MRO MRO oxE0008018 T1MRO 1 Match 32 bit data R W Register O oxEo00801C T1MnR1
70. should compare it with the check sum of the received bytes If the check sum matches then the host should respond with OK lt CR gt lt LF gt to continue further transmission If the check sum does not match then the host should respond with RESEND lt CR gt lt LF gt In response the ISP command handler sends the data again Flash Memory System and Programming 227 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 169 ISP Read Memory command description Command R Start Address Address from where data bytes are to be read This address should be a word Input boundary Number of Bytes Number of bytes to be read Count should be a multiple of 4 CMD SUCCESS followed by actual data UU encoded gt ADDR ERROR Address not on word boundary Return Cede ADDR NOT MAPPED COUNT ERROR Byte count is not multiple of 4 PARAM ERROR CODE READ PROTECTION ENABLED This command is used to read data from RAM or Flash memory As of Bootloader rev 1 61 this command is blocked when code read protection is enabled Example X R 1073741824 4 lt CR gt lt LF gt reads 4 bytes of data from address 0x4000 0000 Description Flash Memory System and Programming 228 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Prepare sector s for write operation start sector number end sector number gt
71. the ARM7TDMI S processor has two instruction sets The standard 32 bit ARM instruction set A 16 bit THUMB instruction set The THUMB set s 16 bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM s performance advantage over a traditional 16 bit processor using 16 bit registers This is possible because THUMB code operates on the same 32 bit register set as ARM code THUMB code is able to provide up to 65 of the code size of ARM and 160 of the performance of an equivalent ARM processor connected to a 16 bit memory system The ARM7TDMI S processor is described in detail in the ARM7TDMI S Datasheet that can be found on official ARM website ON CHIP FLASH MEMORY SYSTEM The LPC2114 2212 incorporate a 128 kB Flash memory system while LPC2124 2214 incorporate a 256 kB Flash memory system This memory may be used for both code and data storage Programming of the Flash memory may be accomplished in several ways over the serial built in JTAG interface using In System Programming ISP and UARTO or by means of In Application Programming IAP capabilities The application program using the In Application Programming IAP functions may also erase and or program the Flash while the application is running allowing a great degree of flexibility for data storage field firmware upgrades etc Introduction 17 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based
72. the Flash memory the MAM holding latches are automatically invalidated at the beginning of any Flash programming or erase operation Any subsequent read from a Flash address will cause a new fetch to be initiated after the Flash operation has completed MEMORY ACCELERATOR MODULE OPERATING MODES Three modes of operation are defined for the MAM trading off performance for ease of predictability 0 MAM off All memory requests result in a Flash read operation see note 2 below There are no instruction prefetches 1 MAM partially enabled Sequential instruction accesses are fulfilled from the holding latches if the data is present Instruction prefetch is enabled Non sequential instruction accesses initiate Flash read operations see note 2 below This means that all branches cause memory fetches All data operations cause a Flash read because buffered data access timing is hard to predict and is very situation dependent 2 MAM fully enabled Any memory request code or data for a value that is contained in one of the corresponding holding latches is fulfilled from the latch Instruction prefetch is enabled Flash read operations are initiated for instruction prefetch and code or data values not available in the corresponding holding latches Table 35 MAM Responses to Program Accesses of Various Types Program Memory Request Type Sequential access data in MAM latches Initiate Fetch Use Latched Data Use Latched Data Sequential
73. the SPI by writing to this register Data received by Write SOSPDR S1SPDR SPI Control Register SOSPCR 0xE0020000 S1SPCR 0xE0030000 The SPCR register controls the operation of the SPI as per the configuration bits setting Table 116 SPI Control Register SOSPCR 0xE0020000 S1SPCR 0xE0030000 Description Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Clock phase control determines the relationship between the data and the clock on SPI transfers and controls when a slave transfer is defined as starting and ending When 1 data is sampled on the second clock edge of the SCK A transfer starts with the first clock edge and ends with the last sampling edge when the SSEL signal is active When 0 data is sampled on the first clock edge of SCK A transfer starts and ends with activation and deactivation of the SSEL signal CPOL Clock polarity control When 1 SCK is active low When 0 SCK is active high Master mode select When 1 the SPI operates in Master mode When 0 the SPI 5 MSTR operates in Slave mode LSB First controls which direction each byte is shifted when transferred When 1 SPI data is transferred LSB bit 0 first When 0 SPI data is transferred MSB bit 7 first Serial peripheral interrupt enable When 1 a hardware interrupt is generated each time the SPIF or MODF bits are activated When 0 SPI interrupts are inhibited
74. the end of a serial transfer The 12C interface will enter master transmitter mode when software sets the STA bit The I C logic will send the START condition as soon as the bus is free After the START condition is transmitted the SI bit is set and the status code in I2STAT should be 08h This status code must be used to vector to an interrupt service routine which should load the slave address and Write bit to I2DAT Data Register and then clear the SI bit SI is cleared by writing a 1 to the SIC bit in the I2CONCLR register 12C Interface 148 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 When the slave address and R W bit have been transmitted and an acknowledgment bit has been received the SI bit is set again and the possible status codes now are 18h 20h or 38h for the master mode or 68h 78h or OBOh if the slave mode was enabled by setting AA 1 The appropriate actions to be taken for each of these status codes are shown in Table 3 to Table 6 in 80C51 Family Derivatives 8XC552 562 Overview datasheet available on line at http www semiconductors philips com acrobat various 8XC552_5620VERVIEW_2 pdf Slave Address R W DATA A M 0 Write A Data Al 1 Read n Bytes Acknowledge A Acknowledge SDA low From Master to Slave A Not Acknowledge SDA high From Slave to Master S START condition P STOP Condition
75. the first mismatch if the Status Code is COMPARE ERROR This command is used to compare the memory contents at two locations Compare result may not Description be correct when source or destination address contains any of the first 64 bytes starting from address zero First 64 bytes can be re mapped to RAM Table 187 IAP Status Codes Summary Status Code Mnemonic Description CMD SUCCESS Command is executed successfully INVALID COMMAND Invalid command SRC ADDR ERROR Source address is not on a word boundary DST ADDR ERROR Destination address is not on a correct boundary Source address is not mapped in the memory map SRC ADDR NOT MAPPED Count value is taken in to consideration where applicable 1 2 3 Destination address is not mapped in the memory DST ADDR NOT MAPPED map Count value is taken in to consideration where applicable COUNT ERROR Qa is not multiple of 4 or is not a permitted INVALID SECTOR Sector number is invalid SECTOR NOT BLANK Sector is not blank SECTOR NOT PREPARED FOR WRITE OPERATION Rd prepare sector for write ODOFS MO ANS COMPARE_ERROR Source and destination data is not same BUSY Flash programming hardware interface is busy 0 RE a cr ME ES a 7 10 11 Flash Memory System and Programming 239 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 JTAG FLASH PROGRAMMING INTERFACE Debug tools can wri
76. the value stored in the Prescale Register the Timer Counter is incremented and the Prescale Counter is reset on the next pclk This causes the TC to increment on every pclk when PR 0 every 2 pclks when PR 1 etc Match Registers MRO MR3 The Match register values are continuously compared to the Timer Counter value When the two values are equal actions can be triggered automatically The action possibilities are to generate an interrupt reset the Timer Counter or stop the timer Actions are controlled by the settings in the MCR register Match Control Register MCR TIMERO TOMCR 0xE0004014 TIMER1 TT MCR 0xE0008014 The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter The function of each of the bits is shown in Table 125 Table 125 Match Control Register MCR TIMERO TOMCR 0xE0004014 TIMER1 TI MCR 0xE0008014 Reset Value O E Function Description When one an interrupt is generated when MRO matches the value in the TC When zero this interrupt is disabled 1 Reset on MRO When one the TC will be reset if MRO matches it When zero this feature is disabled 2 Stop on MRO When one the TC and PC will be stopped and TCR 0 will be set to 0 if MRO matches P the TC When zero this feature is disabled 3 Interrupt on MR1 When one an interrupt is generated when MR1 matches the value in the TC When P zero this interrupt is dis
77. these buses or lines to power it back up software should reprogram the pin function to External Interrupt select the appropriate mode and polarity for the Interrupt and then select power down mode Upon wakeup software should restore the pin mulitplexing to the peripheral function All of the bus or line activity indications in the list above happen to be low active If software wants the device to come out of power down mode in response to actity on more than one pin that share the same EINTi channel it should program low level sensitivity for that channel because only in level mode will the channel logically OR the signals to wake the device The only flaw in this scheme is that the time to restart the oscillator prevents the LPC2114 2124 2212 2214 from capturing the bus or line activity that wakes it up Idle mode is more appropriate than power down mode for devices that must capture and respond to external activity in a timely manner To summarize on the LPC2114 2124 2212 2214 the Wakeup Timer enforces a minimum reset duration based on the crystal oscillator and is activated whenever there is a wakeup from Power Down mode or any type of Reset System Control Block 72 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 5 MEMORY ACCELERATOR MODULE MAM INTRODUCTION Simply put the Memory Accelerator Module MAM attempts to have the next ARM instruction that will be needed
78. time frame where data cannot be written to the SPI data register is from when the transfer starts until after the status register has been read when the SPIF status is active If the SPI data register is written in this time frame the write data will be lost and the write collision WCOL bit in the status register will be activated Mode Fault The SSEL signal must always be inactive when the SPI block is a master If the SSEL signal goes active when the SPI block is a master this indicates another master has selected the device to be a slave This condition is known as a mode fault When a mode fault is detected the mode fault MODF bit in the status register will be activated the SPI signal drivers will be de activated and the SPI mode will be changed to be a slave Slave Abort A slave transfer is considered to be aborted if the SSEL signal goes inactive before the transfer is complete In the event of a slave abort the transmit and receive data for the transfer that was in progress are lost and the slave abort ABRT bit in the status register will be activated SPI Interface 162 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 PIN DESCRIPTION Table 114 SPI Pin Description Pin Name Pin Description Serial Clock The SPI is a clock signal used to synchronize the transfer of data across the SPI interface The SPI is always driven by the master and received by
79. with OK lt CR gt lt LF gt to continue further transmission If the check sum does not match then the ISP command handler responds with RESEND lt CR gt lt LF gt In response the host should retransmit the bytes Table 168 ISP Write to RAM command description Command W Start Address RAM address where data bytes are to be written This address should be a word Input boundary Number of Bytes Number of bytes to be written Count should be a multiple of 4 CMD_SUCCESS ADDR_ERROR Address not a word boundary Ret r Code ADDR NOT MAPPED COUNT ERROR Byte count is not multiple of 4 PARAM ERROR CODE READ PROTECTION ENABLED Deserlatlofi This command is used to download data to RAM The data should be in UU encoded format As of P Bootloader rev 1 61 this command is blocked when code read protection is enabled Example W 1073742336 4 lt CR gt lt LF gt writes 4 bytes of data to address 0x4000 0200 Read Memory lt address gt number of bytes gt The data stream is followed by the command success return code The check sum is sent after transmitting 20 UU encoded lines The checksum is generated by adding raw data before UU encoding bytes and is reset after transmitting 20 UU encoded lines The length of any UU encoded line should not exceed 61 characters bytes i e it can hold 45 data bytes When the data fits in less then 20 UU encoded lines then the check sum is of actual number of bytes sent The host
80. 0 0 ec RII II E a 133 Table 84 UART1 Register Map o ooococcorc e m teens 134 Table 85 UART1 Receiver Buffer Register U1RBR OxE0010000 when DLAB 0 Read Only 135 Table 86 UART1 Transmit Holding Register U1THR 0xE0010000 when DLAB 0 Write Only 135 Table 87 UART1 Divisor Latch LSB Register U1DLL 0xE0010000 when DLAB 1 135 Table 88 UART1 Divisor Latch MSB Register U1DLM 0xE0010004 when DLAB 1 136 Table 89 UART1 Interrupt Enable Register Bit Descriptions U1IER 0xE0010004 when DLAB 0 136 Table 90 UART1 Interrupt Identification Register Bit Descriptions IIR OXE0010008 Read Only 137 Table 91 UART1 Interrupt Handling 0 0 ce RII 138 Table 92 UART1 FCR Bit Descriptions U1FCR OxE0010008 0 0 eee eee ee 139 Table 93 UART1 Line Control Register Bit Descriptions U1LCR OxE001000C 140 Table 94 UART1 Modem Control Register Bit Descriptions U1MCR 0xE0010010 141 Table 95 UART1 Line Status Register Bit Descriptions U1LSR 0xE0010014 Read Only 142 Table 96 UART1 Modem Status Register Bit Descriptions U1MSR 0x0xE0010018 143 Table 97 UART1 Scratchpad Register U1SCR OXE001001C 0 cee lesen 144 Table 98 12C Pin Description i pen oirre enna iee Aee ren 151 Table 99 12C Register Map oooococooccccoc mme 152 Table 100 I2C Control Set Register I2CONSET
81. 0 of the prescaler output clocks will be 306 3054 1 pclks long the rest will be 305 pclks long In a similar manner any pclk rate greater than 65 536 kHz as long as it is an even number of cycles per second may be turned into a 32 kHz reference clock for the RTC The only caveat is that if PREFRAC does not contain a zero then not all of the 32 768 per second clocks are of the same length Some of the clocks are one pclk longer than others While the longer pulses are distributed as evenly as possible among the remaining pulses this jitter could possibly be of concern in an application that wishes to observe the contents of the Clock Tick Counter CTC directly To Clock Tick pclk Counter VPB Clock Clk lt 13 bit Integer Counter 15 bit Fraction Counter Down Counter Underflow Reload Combinatorial Logic Extend Reload 13 bit Reload Integer Register 15 bit Fraction Register PREINT PREFRAC VPB Bus Figure 41 RTC Prescaler block diagram Real Time Clock 209 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Prescaler Operation The Prescaler block labelled Combination Logic in Figure 41 determines when the decrement of the 13 bit PREINT counter is extended by one pclk In order to both insert the correct number of longer cycles and to distribute them evenly the Combinatorial Logic associates each bit in PREFRAC with a combination i
82. 00 eee eee 228 Table 167 ISP Prepare sector s for write operation command descripti0N o o 229 Table 168 ISP Copy RAM to Flash command description 00 ccc eee eee eens 229 Table 169 ISP Go command description ooocococcoococncncn res 230 Table 170 ISP Erase sector command description oooococccoccocccn eese 230 Table 171 ISP Blank check sector s command description oocoooccccocorcorono 231 Table 172 ISP Read Part ID command description lllileseleele eere 231 Table 173 ISP Read Boot Code version command description 00 eee eee eee 231 Table 174 ISP Compare command description 0 0 0 cece teens 232 Table 175 ISP Return Codes SuUMMary oococcocc les 233 Table 176 IAP Command Summary oocccocc eere 235 Table 177 IAP Prepare sector s for write operation command descripti0N oooocooo 236 Table 178 IAP Copy RAM to Flash command description 0000 c eee eee eee eens 237 Table 179 IAP Erase Sector s command description 0 000s 237 Table 180 IAP Blank check sector s command description 000 02 cee eee eee 238 Table 181 IAP Read Part ID command description ooooooooocoorno ee 238 Table 182 IAP Read Boot Code version command description 00 cee ee eee 238 Table 183 IAP Compare command description 0 000 cece es 239 Table 184 IAP Status Codes Summary 1 0 0
83. 0011 ETM Status Holds the pending overflow status bit Read Only 000 0100 System Configuration Holds the configuration information using the SYSOPT bus Read Only 000 0101 Trace Enable Control 3 Holds the trace on off addresses Write Only 000 0110 o mew p 0000 ps m0 ELS ps ESE E 0 LN BEL MEN IO ACI MEA meme p Lew Remi Le Embedded Trace Macrocell 247 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 BLOCK DIAGRAM The block diagram of the ETM debug environment is shown below in Figure 48 PERIPHERAL TRACE TRACE PORT ES ETM ANALYZER TRIGGER PERIPHERAL CONNECTOR pgoooooo0o pgoooooo0o pooooooo HOST RUNNING JTAG DEBUGGER UNIT AE EmbeddedICE ARM CONNECTOR APPLICATION PCB Figure 48 ETM Debug Environment Block Diagram Embedded Trace Macrocell 248 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 22 REALMONITOR RealMonitor is a configurable software module which enables real time debug RealMonitor is developed by ARM Inc Information presented in this chapter is taken from the ARM document RealMonitor Target Integration Guide ARM DUI 0142A It applies to a speci
84. 16 kB 128 256 kB Divider External Memory BLS3 0 SRAM FLASH d Controller E ci VPB VLSI Peripheral Bus External C Serial Interrupts Interface Capture SPI Serial Compare TIMER 0 amp 1 Interfaces 0 amp 1 A D UART O amp 1 DSR1 CTS1 D Converter CDI RH P1 31 16 1 0 General P2310 Purpose I O Watchdog Timer Real Time System Clock Control Shared with GPIO TWhen Test Debug Interface is used GPIO other functions sharing these pins are not available LPC2212 2214 only Figure 1 LPC2114 2124 2212 2214 Block Diagram Introduction 19 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 LPC2114 2124 2212 2214 REGISTERS Accesses to registers in LPC2114 2124 2212 2214 is restricted in the following ways 1 user must NOT attempt to access any register locations not defined 2 Access to any defined register locations must be strictly for the functions for the registers 3 Register bits labeled 0 or 1 can ONLY be written and read as follows MUST be written with 0 but can return any value when read even if it was written with 0 It is a reserved bit and may be used in future derivatives 0 MUST be written with 0 and will return a 0 when read 1 MUST be written with 1 and will return a 1 when read The following table shows all registers available in LPC2114 2124 2212 2214 microcontr
85. 2 2214 LQFP144 EAT Em E P3 23 A23 External memory address line 23 XCLK Clock output CS3 Low active Chip Select 3 signal Bank 3 addresses range 8300 0000 83FF FFFF Low active Chip Select 2 signal Bank 2 addresses range 8200 0000 82FF FFFF Low active Chip Select 1 signal Bank 1 addresses range 8100 0000 81FF FFFF Low active Write enable signal Low active Byte Lane Select signal Bank 3 A D converter input 7 This analog input is always connected to its pin Low active Byte Lane Select signal Bank 2 A D converter input 6 This analog input is always connected to its pin P3 30 BLS1 Low active Byte Lane Select signal Bank 1 P3 31 BLSO Low active Byte Lane Select signal Bank 0 External Reset input A LOW on this pin resets the device causing I O ports and RESET 135 peripherals to take on their default states and processor execution to begin at address 0 TTL with hysteresis 5V tolerant XTAL1 ta i Input to the oscillator circuit and internal clock generator circuits XTAL2 144 poo m o Output from the oscillator amplifier 3 9 26 38 54 67 79 93 103 Ground OV reference 107 111 128 V 139 Analog Ground OV reference This should nominally be the same voltage as Vss but SSA should be isolated to minimize noise and error V 138 PLL Analog Ground OV reference This should nominally be the same voltage as Vss but Ben PEE should be isolated to minimize noise and error
86. 2114 2124 2212 2214 includes four External Interrupt Inputs as selectable pin functions The External Interrupt Inputs can optionally be used to wake up the processor from the Power Down mode Register Description The external interrupt function has four registers associated with it The EXTINT register contains the interrupt flags and the EXTWAKEUP register contains bits that enable individual external interrupts to wake up the LPC2114 2124 2212 2214 from Power Down mode The EXTMODE and EXTPOLAR registers specify the level and edge sensitivity parameters Table 14 External Interrupt Registers Address Name Description Access The External Interrupt Flag Register contains interrupt flags for EINTO EINT1 OREO IEG TO ERUNT and EINT2 See Table 15 did The External Interrupt Wakeup Register contains three enable bits that control 0xE01FC144 EXTWAKE whether each external interrupt will cause the processor to wake up from Power R W Down mode See Table 16 OxEO1FC148 EXTMODE The External Interrupt Mode Register controls whether each pin is edge or level sensitive OxEO1FC14C EXTPOLAR The External Interrupt Polarity Register controls which level or edge on each pin will cause an interrupt External Interrupt Flag Register EXTINT 0xE01FC140 When a pin is selected for its external interrupt function the level or edge on that pin selected by its bits in the EXTPOLAR and EXTMODE registers will set its interrupt flag in this register
87. 212 2214 13 SPI INTERFACE FEATURES Two complete and independent SPI cintrollers Compliant with Serial Peripheral Interface SPI specification Synchronous Serial Full Duplex Communication Combined SPI master and slave Maximum data bit rate of one eighth of the input clock rate DESCRIPTION SPI Overview SPIO and SPI1 are full duplex serial interfaces They can handle multiple masters and slaves being connected to a given bus Only a single master and a single slave can communicate on the interface during a given data transfer During a data transfer the master always sends a byte of data to the slave and the slave always sends a byte of data to the master SPI Data Transfers Figure 33 is a timing diagram that illustrates the four different data transfer formats that are available with the SPI This timing diagram illustrates a single 8 bit data transfer The first thing one should notice in this timing diagram is that it is divided into three horizontal parts The first part describes the SCK and SSEL signals The second part describes the MOSI and MISO signals when the CPHA variable is 0 The third part describes the MOSI and MISO signals when the CPHA variable is 1 In the first part of the timing diagram note two points First the SPI is illustrated wit CPOL set to both 0 and 1 The second point to note is the activation and de activation of the SSEL signal When CPHA 1 the SSEL signal will always go inactive betwe
88. 214 Table 94 UART1 Interrupt Handling Interrupt Interrupt Interrupt U1IIR 3 0 Priority Type Source Reset 0001 none 0110 Highest P ae OE or PE or FE or BI U1LSR Read U1RBR Reador 0100 Second Rx Data Rx data available or trigger level reached in FIFO mode UART1 FIFO Available FCRO 1 drops below trigger level Minimum of one character in the Rx FIFO and no character input or removed during a time period depending on how many Character Time characters are in FIFO and what the trigger level is set at 3 5 1100 Second E to 4 5 character times U1RBR Read out Indication E The exact time will be word length X 7 2 X 8 trigger level number of characters X 8 1 RCLKs U1IIR Read if 0010 Third THRE THRE Source O interrupt or THR write 0000 Modem Status CTS or DSR or RI or DCD MSR Read note values 0011 0101 0111 1000 1001 1010 1011 1101 1110 1111 are reserved The UART1 THRE interrupt U11IR3 12001 is a third level interrupt and is activated when the UART1 THR FIFO is empty provided certain initialization conditions have been met These initialization conditions are intended to give the UART1 THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start up The initialization conditions implement a one character delay minus the stop bit whenever THRE 1 and there have not been at least two charac
89. 2212 2214 Watchdog Feed Register WDFEED 0xE0000008 Writing OxAA followed by 0x55 to this register will reload the Watchdog timer to the WDTC value This operation will also start the Watchdog if it is enabled via the WDMOD register Setting the WDEN bit in the WDMOD register is not sufficient to enable the Watchdog A valid feed sequence must first be completed before the Watchdog is capable of generating an interrupt reset Until then the Watchdog will ignore feed errors Once OxAA is written to the WDFEED register the next operation in the Watchdog register space should be a WRITE 0x55 to the WDFFED register otherwise the Watchdog is triggered The interrupt reset will be generated during the second pclk following an incorrect access to a watchdog timer register during a feed sequence Table 160 Watchdog Feed Register WDFEED 0xE0000008 Reset Value 7 0 Feed Feed value should be OxAA followed by 0x55 undefined WDFEED Function Description Watchdog Timer Value Register WDTV 0xE000000C The WDTV register is used to read the current value of Watchdog timer Table 161 Watchdog Timer Value Register WDTV 0xE000000C Function Description Count Current timer value USAGE NOTES ON WATCHDOG RESET AND EXTERNAL START When LPC2212 2214 is conditioned by components attached to the BOOT1 0 pins to start execution in off chip memory and is programmed to enable the Watchdog Timer to reset the part if itis not
90. 2214 APPLICATIONS Industrial control Medical systems Access control Point of sale Communication gateway Embedded soft modem general purpose applications DEVICE INFORMATION Table 1 LPC2114 2124 2212 2214 device information No of 10 bit Device No of pins On chip RAM AD Channels LPC2114 64 16 kB 4 4 LPC2212 16 kB 128 kB Le 9 with external memory interface LPC2214 16 kB 256 kB eoe with external memory interface Introduction 16 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 ARCHITECTURAL OVERVIEW The LPC2114 2124 2212 2214 consists of an ARM7TDMI S CPU with emulation support the ARM7 Local Bus for interface to on chip memory controllers the AMBA Advanced High performance Bus AHB for interface to the interrupt controller and the VLSI Peripheral Bus VPB a compatible superset of ARM s AMBA Advanced Peripheral Bus for connection to on chip peripheral functions The LPC2114 2124 2212 2214 configures the ARM7TDMI S processor in little endian byte order AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the 4 gigabyte ARM memory space Each AHB peripheral is allocated a 16 kilobyte address space within the AHB address space LPC2114 2124 2212 2214 peripheral functions other than the interrupt controller are connected to the VPB bus The AHB to VPB bridge interfaces the VPB bus to the AHB bus VPB periph
91. 24084 ERAC racional 15 bit data R portion GPIO PORTO oxE0028000 icoPiN GPIO 0 Pin 32 bit data I Value reg oxE0028004 icosET GPIO 0 Out 32 bit data Set register oxE0028008 1oopir F O 0 Dir 32 bit data R W control reg oxE002800C IoocLR GPIO 0 Out 32 bit data WO Clear register GPIO PORT1 oxE0028010 101PINn SPIO 1 Pin 32 bit data ES NA Value reg oxE0028014 1o1seT GPIO 1 Out 32 bit data EN Set register Introduction 28 May 03 2004 BS lt lt I 2 0 co ot NA D z Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 2 LPC2114 2124 2212 2214 Registers Address Offset Name Description LSB Access oxE0028018 101p1R SPIO 1 Dir 32 bit data control reg oxE002801C 101cLR GPO 1 Out 32 bit data WO Clear register GPIO PORT2 oxE0028020 102PINn GPIO 2 Pin 32 bit data Value reg OxE0028024 102sET GPIO 2 Out 32 bit data Set register oxE0028028 io2pin GPIO 2 Dir 32 bit data R W control reg oxE002802C 102cLR GPIO 2 Out 32 bit data w Clear register GPIO PORT3 0xE0028030 ioaPIN GPIO 3 Pin 32 bit data Value reg 53 o eo o8 O 0xE0028034 IOGSET GPIO x Out 32 bit data CE Set register oxE0028038 ioapiR P O 3 Dir 32 bit data LIE control reg 0xE002803C lO3CLR GRIO 3 Que 32 bit data WO Clear register Pin Connet Block PIN Pin function 0xE002C000 select 32
92. 4 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 WAKEUP TIMER The purpose of the wakeup timer is to ensure that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions This is important at power on all types of Reset and whenever any of the aforementioned functions are turned off for any reason Since the oscillator and other functions are turned off during Power Down mode any wakeup of the processor from Power Down mode makes use of the Wakeup Timer The Wakeup Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution When power is applied to the chip or some event caused the chip to exit Power down mode some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic The amount of time depends on many factors including the rate of Vdd ramp in the case of power on the type of crystal and its electrical characteristics if a quartz crystal is used as well as any other external circuitry e g capacitors and the characteristics of the oscillator itself under the existing ambient conditions Once a clock is detected the Wakeup Timer counts 4096 clocks then enables the Flash memory to initialize When the Flash memory initialization is complete the processor is released to execute instructions if the ext
93. 65 Table 116 SPI Clock Counter Register SOSPCCR OxE002000C S1SPCCR OxE003000C 165 Table 117 SPI Interrupt Register SOSPINT 0xE002001C S1SPINT OxE003001C 166 Table 118 Pin Suminaty 5 sr Peste ope weds re ed ae ddp Bae E A pu n 170 Table 119 TIMERO and TIMER1 Register Map oooooocoocco RII Ih 171 Table 120 Interrupt Register IR TIMERO TOIR OxE0004000 TIMER1 T1IR OxE0008000 172 Table 121 Timer Control Register TCR TIMERO TOTCR 0xE0004004 TIMER1 T1TCR OxE0008004 172 Table 122 Match Control Register MCR TIMERO TOMCR 0xE0004014 TIMER1 T1MCR 0xE0008014 173 Table 123 Capture Control Register CCR TIMERO TOCCR 0xE0004028 TIMER1 T1CCR 0xE0008028 174 Table 124 External Match Register EMR TIMERO TOEMR 0xE000403C TIMER1 TTEMR OxE000803C 175 Table 125 External Match Control 0 0 0 cece hr 175 Table 126 Set and Reset inputs for PWM Flip Flops 0 0 0 0 cece tee ee 182 Table 127 Pin SuMMary 5 ss cease ales pis ie Maeve A A A pd Re ele ate 184 Table 128 Pulse Width Modulator Register Map 0 0c eee ete 185 Table 129 PWM Interrupt Register PWMIR OxE0014000 0 eee ee 187 Table 130 PWM Timer Control Register PWMTCR 0xE0014004 0 ee ee 188 Table 131 PWM Match Control Register PWMMCR 0xE0014014 02 cee eee 189 T
94. 9 17 CLKS number of bits of accuracy of the result in the LS bits of ADDR between 11 clocks 10 bits 110 start conversion when the edge selected by bit 27 occurs on MAT1 0 When the BURST bit is 0 these bits control whether and when an A D conversion is started 000 no start this value should be used when clearing PDN to 0 001 start conversion now 010 start conversion when the edge selected by bit 27 occurs on P0 16 EINTO MATO 2 CAPO 2 26 24 START 011 start conversion when the edge selected by bit 27 occurs on P0 22 CAPO0 0 MATO O Note for choices 100 111 the MAT signal need not be pinned out 100 start conversion when the edge selected by bit 27 occurs on MATO 1 101 start conversion when the edge selected by bit 27 occurs on MATO 3 111 start conversion when the edge selected by bit 27 occurs on MAT1 1 EDGE 0 start conversion on a falling edge on the selected CAP MAT signal 1 start conversion on a rising edge on the selected CAP MAT signal n These bits are used in device testing 00 normal operation 01 digital test mode 10 DAC 23 22 TEST1 0 test mode and 11 simple conversion test mode BH This bit is significant only when the START field contains 010 111 In these cases 27 A D Converter 194 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 A D Data Register ADDR 0xE0034004 ADDR Name Description Reset Value This bit is set to 1 w
95. AMR AMR AMR AMR AMR AMR Register YEAR MON DOY DOW DOM HOUR MIN SEC RESI 3 bit Day of Week Consolidated S85tows bit Hours 0xE0024014 CTIMEO Time Register 0 En 6 bit Minutes 6bitSecondss 6 bit 6bitSeconds Consolidated 12 o0 Year Year 0xE0024018 CTIME1 Time Consolidated 0xE002401C CTIME2 Time reserved 20 bits 12 bit Day of Year Register 2 egister Register Register EDEN BoM Register EXEDE TAS ce Register ET sow Register EEE IN n 188 Register Day of Year Register Register 0xE002403C YEAR Year Register reserved 4 bits 12 bit data 0xE0024034 DOY reserved 7 bits 9 bit data Introduction 27 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 SB Access 6 bit data R Table 2 LPC2114 2124 2212 2214 Registers Address Offset Description Alarm value for Seconds AL Alarm value OxE0024064 for Minutes ES 0xE0024060 J A Alarm value 0xE0024070 for Day of 3 bit data Ww Alarm value 0xE0024074 for Day of reserved 7 bits 9 bit data R W AL Alarm value Ww Ww JJ AL Alarm value 0xE0024068 HOUR Alarm value OxE002406C for Day of AL Alarm value reserved c 0xE002407C YEAR for Year 4 bits 12 bit data Prescale PRE reserved 0xE0024080 value integer 3 bits 13 bit data portion Prescale PRE value oxE00
96. C100 VPBDIV Function Description The rate of the VPB clock is as follows 0 0 VPB bus clock is one fourth of the processor clock 0 1 VPB bus clock is the same as the processor clock VPBDIV 1 0 VPB bus clock is one half of the processor clock 1 1 Reserved If this value is written to the VPBDIV register it has no effect the previous setting is retained Reserved user software should not write ones to reserved bits The value read from a Reserved reserved bit is not defined In the LPC2212 2214 parts in 144 packages only these bits control the clock that can be driven onto the A23 XCLK pin They have the same encoding as the VPBDIV bits above A bit in the PINSEL2 register Pin Connect Block on page 109 controls whether XCLKDIV the pin carries A23 or the clock selected by this field Note If this field and VPBDIV have the same value the same clock is used on the VPB and XCLK This might be useful for external logic dealing with the VPB peripherals Reserved user software should not write ones to reserved bits The value read from a 7 6 Reserved ne reserved bit is not defined System Control Block 70 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Crystal Oscillator or Processor Clock External Clock Source cclk Fosc VPB Divider VPB Clock pclk Figure 17 VPB Divider Connections System Control Block 71 May 03 200
97. CK falling edge SCK rising edge The definition of when an 8 bit transfer starts and stops is dependent on whether a device is a master or a slave and the setting of the CPHA variable SPI Interface 160 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 When a device is a master the start of a transfer is indicated by the master having a byte of data that is ready to be transmitted At this point the master can activate the clock and begin the transfer The transfer ends when the last clock cycle of the transfer is complete When a device is a slave and CPHA is set to 0 the transfer starts when the SSEL signal goes active and ends when SSEL goes inactive When a device is a slave and CPHA is set to 1 the transfer starts on the first clock edge when the slave is selected and ends on the last clock edge where data is sampled SPI Peripheral Details General Information There are four registers that control the SPI peripheral They are described in detail in Register Description section The SPI control register contains a number of programmable bits used to control the function of the SPI block The settings for this register must be set up prior to a given data transfer taking place The SPI status register contains read only bits that are used to monitor the status of the SPI interface including normal functions and exception conditions The primary purpose of this reg
98. CK1 MAT1 2 P0 24 P0 16 EINTO MATO 2 CAPO 2 VSS P0 15 RH EINT2 P2 23 D23 P2 0 DO P2 24 D24 P3 30 BLS1 P2 25 D25 P3 31 BLSO P2 26 D26 BOOTO P1 21 PIPESTATO V3A v3 P1 18 TRACEPKT2 VSS P2 27 D27 BOOT1 P0 14 DCD1 EINT1 P2 28 D28 P1 0 CSO P2 29 D29 P1 1 OE P2 30 D30 AIN4 9 P3 0 A0 P2 31 D31 AIN5 0 P3 1 A1 P0 25 P3 2 A2 NC 8 P1 22 PIPESTAT1 P0 27 AINO CAPO 1 MATO 1 P0 13 DTR1 MAT1 1 P1 17 TRACEPKT1 P0 12 DSR1 MAT1 0 P0 28 AIN1 CAP0 2 MATO 2 P0 11 CTS1 CAP1 1 vss P1 23 PIPESTAT2 P3 29 BLS2 AIN6 P3 3 A3 P3 28 BLS3 AIN7 P3 4 A4 P3 27 WE VSS P3 26 CS1 P0 10 RTS1 CAP1 0 v3 V3 P0 29 AIN2 CAPO 3 MATO 3 PO 9 RxD1 PWM6 EINT3 P0 30 AIN3 EINT3 CAP0 0 P0 8 TxD1 PWM4 P1 16 TRACEPKTO P3 5 A5 P3 25 CS2 P3 6 A6 P3 24 CS3 40 42 i 49 52 58 61 S8 v3 P3 23 A23 XCLK P3 22 A22 P0 0 TxDO PWM1 P1 31 TRST P3 21 A21 P3 20 A20 P3 19 A19 P3 18 A18 P3 17 A17 P0 1 RxDO PWM3 EINTO P0 2 SCL CAPO 0 P1 26 RTCK P3 16 A16 P3 15 A15 P3 14 A14 P0 3 SDA MATO 0 EINT1 P0 4 SCKO CAPO 1 P1 25 EXTINO P0 5 MISO0 MATO 1 P3 13 A13 P3 12 A12 P3 11 A11 P3 10 A10 P0 6 MOSIO CAPO 2 P0 7 SSELO PWM2 EINT2 P1 24 TRACECLK Figure 21 LPC2212 2214 144 pin package Pin Configuration 98 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 PIN DESCRIPTION FOR LPC2212 2214 Pin description for LPC2212 2214 and a brief of correspondi
99. Counter Timer Counter Timer Counter Reset Interrupt Figure 35 A timer cycle in which PR 2 MRx 6 and both interrupt and reset on match are enabled pclk Prescale Counter Timer Counter TCR O0 Counter Enable Interrupt Figure 36 A timer cycle in which PR 2 MRx 6 and both interrupt and stop on match are enabled TimerO and Timer1 176 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 ARCHITECTURE The block diagram for TIMERO and TIMER is shown in Figure 37 Match Control Register External Match Register Interrupt Register Control MAT 3 0 Stop on Match Reset on Match Load 3 0 Prescale Counter ENABLE MAXVAL Timer Control Register Prescale Register Note that Capture Register 3 cannot be used on TIMERO Figure 37 Timer block diagram TimerO and Timer 177 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 TimerO and Timer1 178 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 15 PULSE WIDTH MODULATOR PWM LPC2114 2124 2212 2214 Pulse Width Modulator is based on standard Timer 0 1 described in previous chapter Application can choose among PWM and match
100. DCC only RDI messages for the JTAG unit For complete details on debugging a RealMonitor integrated application from the host see the ARM RMHost User Guide ARM DUI 0137A RMTarget This is pre programmed in the on chip Flash memory boot sector and runs on the target hardware It uses the EmbeddedICE logic and communicates with the host using the DCC For more details on RMTarget functionality see the RealMonitor Target Integration Guide ARM DUI 0142A Debugger RDI 1 5 1 RealMonitor dll RMHost h RDI 1 5 1rt Y JTAG unit RealMonitor protocol A DCC transmissions Y over the JTAG link y Target RMTarget Board and n Processor Application Figure 49 RealMonitor components RealMonitor 250 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 How RealMonitor works In general terms the RealMonitor operates as a state machine as shown in Figure 50 RealMonitor switches between running and stopped states in response to packets received by the host or due to asynchronous events on the target RMTarget supports the triggering of only one breakpoint watchpoint stop or semihosting SWI at a time There is no provision to allow nested events to be saved and restored So for example if user application has stopped at one breakpoint and another breakpoint occurs in an IRQ handler R
101. Divisor Latches B zu D D 2 SB SB B UARTO Receiver Buffer Register UORBR 0xE000C000 when DLAB 0 Read Only The UORBR is the top byte of the UARTO Rx FIFO The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface The LSB bit 0 represents the oldest received data bit If the character received is less than 8 bits the unused MSBs are padded with zeroes The Divisor Latch Access Bit DLAB in UOLCR must be zero in order to access the UORBR The UORBR is always Read Only UARTO 122 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 75 UARTO Receiver Buffer Register UORBR OXE000C000 when DLAB 0 Read Only Reset Value Function Description Receiver Buffer The UARTO Receiver Buffer Register contains the oldest received byte in the UARTO Rx un Register FIFO defined UARTO Transmitter Holding Register UOTHR 0xE000C000 when DLAB 0 Write Only The UOTHR is the top byte of the UARTO Tx FIFO The top byte is the newest character in the Tx FIFO and can be written via the bus interface The LSB represents the first bit to transmit The Divisor Latch Access Bit DLAB in UOLCR must be zero in order to access the UOTHR The UOTHR is always Write Only Table 76 UARTO Transmit Holding Register UOTHR OXEO00C000 when DLAB 0 Write Only Function Description Writing to t
102. ED configuration information from the PLLCON and PLLCFG registers into the System Control Block 60 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Clock Synchronization PSEL 1 0 po 0 Phase Frequency Detector msel lt 4 0 gt MSEL 4 0 Figure 15 PLL Block Diagram PLL Control Register PLLCON 0xE01FC080 The PLLCON register contains the bits that enable and connect the PLL Enabling the PLL allows it to attempt to lock to the current settings of the multiplier and divider values Connecting the PLL causes the processor and all chip functions to run from the PLL output clock Changes to the PLLCON register do not take effect until a correct PLL feed sequence has been given see PLL Feed Register PLLFEED 0xE01FC08C description System Control Block 61 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 22 PLL Control Register PLLCON 0xE01FC080 PLLCON Function Description 0 PLLE PLL Enable When one and after a valid PLL feed this bit will activate the PLL and allow it to lock to the requested frequency See PLLSTAT register Table 24 PLL Connect When PLLC and PLLE are both set to one and after a valid PLL feed 1 PLLC connects the PLL as the clock source for the LPC2114 2124 2212 2214 Otherwise the oscil
103. FOs Table 82 UARTO FIFO Control Register Bit Descriptions UOFCR 0xE000C008 Function Description Active high enable for both UARTO Rx and Tx FIFOs and UOFCR7 1 access This bit FIFO Enable must be set for proper UARTO opearation Any transition on this bit will automatically clear the UARTO FIFOs Rx FIFO Reset Writing a logic 1 to UOFCR1 will clear all bytes in UARTO Rx FIFO and reset the pointer logic This bit is self clearing Tx FIFO Reset Writing a logic 1 to UOFCR2 will clear all bytes in UARTO Tx FIFO and reset the pointer logic This bit is self clearing Reserved user software should not write ones to reserved bits The value read from a Reserved E A reserved bit is not defined before an interrupt is activated The four trigger levels are defined by the user at compilation allowing the user to tune the trigger levels to the FIFO depths chosen 0 00 trigger level O default 1 character or 0x01h 01 trigger level 1 default 4 characters or 0x04h 10 trigger level 2 default 8 characters or 0x08h 76 Rx Trigger Level 11 trigger level 3 default 14 characters or OxOeh Select These two bits determine how many receiver UARTO FIFO characters must be written UARTO 126 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 UARTO Line Control Register UOLCR 0xE000C00C The UOLCR determines the format of the data character that is to be tra
104. Function Description Value When one the Timer Counter and Prescale Counter are enabled for counting When Counter Enable 0 zero the counters are disabled 1 Counter Reset When one the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of pclk The counters remain reset until TCR 1 is returned to zero Timer Counter TC TIMERO TOTC 0xE0004008 TIMER1 T1TC 0xE0008008 The 32 bit Timer Counter is incremented when the Prescale Counter reaches its terminal count Unless it is reset before reaching its upper limit the TC will count up through the value OXFFFFFFFF and then wrap back to the value 0x00000000 This event does not cause an interrupt but a Match register can be used to detect an overflow if needed Prescale Register PR TIMERO TOPR 0xE000400C TIMER1 T1PR 0xE000800C The 32 bit Prescale Register specifies the maximum value for the Prescale Counter TimerO and Timer1 172 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Prescale Counter Register PC TIMERO TOPC 0xE0004010 TIMER1 T1PC 0xE0008010 The 32 bit Prescale Counter controls division of pclk by some constant value before it is applied to the Timer Counter This allows control of the relationship of the resolution of the timer versus the maximum time before the timer overflows The Prescale Counter is incremented on every pclk When it reaches
105. GPIO chapters Trigger levels determined by bits 7 and 6 in UOFCR and U1FCR UARTO and UART1 chapters now showed in both decimal and hexadecimal notations References to DBGSEL pin removed from entire document pin does not exist in this family of microcontrollers Pin 20 in figure showing 64 pin package Pin Configuration chapter corrected from 1 3 to 1 31 e Vaga replaced with V3 in A D Converter chapter and V3 description updated in Pin Configuration chapter Warning on analog input levels added to A D Converter chapter On chip upper RAM boundary corrected from 0x4000 1FFF to 0x4000 3FFF in LPC2114 2124 2212 2214 Memory Addressing chapter Port pin tolerance pull up presence and voltage considerations added in Pin Configuration and A D Converter chapter Baudrates in Flash Memory System and Programming corrected 115200 and 230400 instead of 115000 and 230000 Number of the on chip Flash erase and write cycles added into Introduction and Flash Memory System and Programming chapters Pins capable of providing an External Interrupt functionality are acounted and listed in System Control Block chapter Access to ports with respect to GPIO configured pins clarified in GPIO and Pin Connect Block chapters Description of Code Read Protection feature added in Flash Memory System and Programming chapter OPINO and IOPIN1 tyopografic errors corrected in System Control Block chapter PINSEL2
106. IMERO channel 2 Capture input for TIMERO channel 2 Capture input for TIMER1 channel 2 Serial Clock for SPI1 SPI clock output from master or input to slave Match output for TIMER1 channel 2 Capture input for TIMER1 channel 3 Master In Slave Out for SPI1 Data input to SPI master or data output from SPI slave Match output for TIMER1 channel 3 Match output for TIMER1 channel 2 Master Out Slave In for SPI1 Data output from SPI master or data input to SPI slave Capture input for TIMER1 channel 2 Match output for TIMER1 channel 3 Slave Select for SPI1 Selects the SPI interface as a slave External interrupt 3 input Pulse Width Modulator output 5 Capture input for TIMER1 channel 3 Capture input for TIMERO channel 0 Match output for TIMERO channel 0 95 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 55 Pin description for LPC2114 2124 LQFP64 E o S P0 23 General purpose bidirectional digital port only P0 24 General purpose bidirectional digital port only P0 25 General purpose bidirectional digital port only P0 27 AINO A D converter input 0 This analog input is always connected to its pin CAPO 1 Capture input for TIMERO channel 1 MATO 1 Match output for TIMERO channel 1 AIN1 A D converter input 1 This analog input is always connected to its pin CAP0 2 Capture input for TIMERO channel 2 MATO 2 Match outpu
107. Introduction 30 May 03 2004 Philips Semiconductors ARM based Microcontroller Table 2 LPC2114 2124 2212 2214 Registers Address Offset Description Preliminary User Manual LPC2114 2124 2212 2214 Reset Value External interrupt wakeup register External EXT OxEO1FC148 MODE interrupt mode register External EXT interrupt OxEO1FC14C POLAR polarity register External memory Controller EMC oxFFEo0000 BCFGo Cont Reg for mem bank 0 OxEO1FC144 oxFFE00004 BcFG1 Conf Reg for mem bank 1 oxFFEo0008 BCFG2 Conf Reg for mem bank 2 oxFFEo000C BcFas COM Reg for mem bank 3 Vectored Interrupt Controller VIC OxFFFFFO000 VICIRQ IRQ Status Status Register OxFFFFFO04 VICFIQ FIQ Status Status Register Introduction 31 LSB Access EXT EXT EXT EXT WAKE WAKE WAKE WAKE 2 1 0 3 EXT EXT EXT EXT MODE MODE MODE MODE 3 2 1 0 EXT EXT EXT EXT POLAR POLAR POLAR POLAR 3 2 1 0 WP BUS CATA EAE WST1 IDCY 32 bit data TU UJ o m T mu ms mo ET UJ m Er ET UJ m Er May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 2 LPC2114 2124 2212 2214 Registers Address T E Reset Offset Description LSB Access Value Raw Interrupt Rawlntr Status Reg OxFFEEPOOG EIE enteren 32 bit data RW Select Select Reg VICInt Interrupt VICInt Int Enab
108. Manual ARM based Microcontroller LPC2114 2124 2212 2214 0x8000 0000 2 0 GB 8K byte Boot Block Ox7FFF FFFF re mapped from top of Flash memory 2 0 GB 8K Boot Block interrupt vectors Reserved for On Chip Memory 0x4000 4000 0x4000 3FFF 16 kB On Chip SRAM SRAM interrupt vectors 0x4000 0000 Ox3FFF FFFF Reserved for On Chip Memory 0x0002 0000 8k byte Boot Block re Mapped to higher address range 0x0001 FFFF Active interrupt vectors from Flash SRAM or Boot Block 0x0000 0000 Note memory regions are not drawn to scale Figure 6 Map of lower memory is showing re mapped and re mappable areas 128 kB Flash LPC2114 2124 2212 2214 Memory Addressing 39 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 PREFETCH ABORT AND DATA ABORT EXCEPTIONS The LPC2114 2124 2212 2214 generates the appropriate bus cycle abort exception if an access is attempted for an address that is in a reserved or unassigned address region The regions are Areas of the memory map that are not implemented for a specific ARM derivative For the LPC2114 2124 2212 2214 this is Address space between On Chip Non Volatile Memory and On Chip SRAM labelled Reserved for On Chip Memory in Figure 2 and Figure 6 For 128 kB Flash device this is memory address range from 0x0002 0000 to Ox3FFF FFFF while for 256 kB Flash device this range is from 0x0004 0000 to OxSFFF FFFF Add
109. O 7 0 A a m 0 BLS 0 D 7 0 CE OE WE IO 7 0 A a m 0 LPC211 Preliminary User Manual 4 2124 2212 2214 BLS 1 BLS 0 D 15 0 10 15 0 A a m 0 A a b 1 A a b 1 a 16 bit wide memory bank interfaced to 16 bit memory chips a 16 bit wide memory bank interfaced to 8 bit memory chips Figure 8 16 Bit Bank External Memory Interfaces CE OE BLS 0 WE D 7 0 IO 7 0 A a m 0 Ala_b 0 Figure 9 8 Bit Bank External Memory Interface External Memory Controller EMC 45 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 TYPICAL BUS SEQUENCES Following figures show typical external read and write access cycles XCLK is the clock signal avalable on P3 23 While not necessary used by external memory In these examples it is used to provide the time reference XCLK and CCLK were set to have the same frequency 1 wait state WST1 0 XCLK CS OE WE BLS Addr valid address Data change valid data X 2 wait states WST1 1 XCLK Ces OE WE BLS Addr valid address Data change valid data Figure 10 External memory read access WST1 0 and WST1 1 examples XCLK CSU OE WE BLS Addr valid address
110. O is set when the UORBR holds an unread character and is cleared when the UARTO RBR FIFO is empty 0 Overrun error status is inactive 1 Overrun error status is active The overrun error condition is set as soon as it occurs An UOLSR read clears UOLSR1 UOLSR1 is set when UARTO RSR has a new character assembled and the UARTO RBR FIFO is full In this case the UARTO RBR FIFO will not be overwritten and the character in the UARTO RSR will be lost 0 Parity error status is inactive 1 Parity error status is active When the parity bit of a received character is in the wrong state a parity error occurs An UOLSR read clears UOLSR2 Time of parity error detection is dependent on UOFCRO A parity error is associated with the character being read from the UARTO RBR FIFO 0 Framing error status is inactive 1 Framing error status is active When the stop bit of a received character is a logic 0 a framing error occurs An UOLSR read clears UOLSR3 The time of the framing error detection is dependent on UOFCRO A framing error is associated with the character being read from the UARTO RBR FIFO Upon detection of a framing error the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit However it cannot be assumed that the next received byte will be correct even if there is no Framing Error 0 Break interrupt status is inactive 1 Break interrupt status is active When RxDO is he
111. PC2114 2124 2212 2214 ee A DATA A DATA A RS A Data me n Bytes Acknowledge A Acknowledge SDA low A Not Acknowledge SDA high S START condition P STOP Condition From Master to Slave SLA Slave Address From Slave to Master RS Repeat START condition Figure 28 A master receiver switch to master transmitter after sending repeated START Slave Receiver Mode In the slave receiver mode data bytes are received from a master transmitter To initialize the slave receiver mode user should write the Slave Address Register I2ADR and write the 12C Control Set Register I2CONSET as shown in Figure 29 I2ZCONSET Figure 29 Slave Mode Configuration I2EN must be set to 1 to enable the 12C function AA bit must be set to 1 to acknowledge its own slave address or the general call address The STA STO and SI bits are set to 0 After IZADR and I2CONSET are initialized the IC interface waits until it is addressed by its own address or general address followed by the data direction bit If the direction bit is 1 R it enters slave transmitter mode After the address and direction bit have been received the SI bit is set and a valid status code can be read from the Status Register I2STAT Refer to Table 5 in 80C51 Family Derivatives 8XC552 562 Overview datasheet available on line at http www semiconductors
112. PR 2 MRx 6 and both interrupt and stop on match are enabled 176 Figure 37 Timer block diagraM o oooooocoor RR ae 177 Figure 38 PWM block diagram o ose eR RR ee Bese ple ee ERE eter ere eel 181 Figure 39 Sample PWM waveforms llis mme 182 Figure 40 RTC block diagraM oooococccccco eR Rh mcs 198 Figure 41 RTC Prescaler block diagram issssseseleeeee en 209 Figure 42 Watchdog Block DiagraM ooocooocooco e I 216 Figure 43 Map of lower memory after any reset 128 kB Flash part 0 0 20 eee eee eee 218 Figure 44 Boot Process flowchart Bootloader revisions before 1 61 oooooooommoomo 221 Figure 45 Boot Process flowchart Bootloader revisions 1 61 and later o oooo 222 Figure 46 IAP Parameter passing silii tne eae 236 Figure 47 EmbeddedICE Debug Environment Block Diagram lisse eese 244 Figure 48 ETM Debug Environment Block Diagram lslseeeee ee 248 Figure 49 RealMonitor components 0 cece RR e 250 Figure 50 RealMonitor as a state MachiNe o ooocooccccro 251 Figure 51 Exception Handlers 20 0 0 eee ee m e 254 7 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 8 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 List of Tables Table 1 LPC2114 2124 2212 2214
113. Pin Configuration 106 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 56 Pin description for LPC2212 2214 LQFP144 fare Fame mee TE serpin O O 37 110 BUE 1 8V Core Power Supply This is the power supply voltage for internal circuitry Analog 1 8V Core Power Supply This is the power supply voltage for internal circuitry V18A 143 This should be nominally the same voltage as V18 but should be isolated to minimize noise and error 2 31 39 51 57 77 94 104 3 3V Pad Power Supply This is the power supply voltage for the I O ports 112 119 Analog 3 3V Pad Power Supply This should be nominally the same voltage as V3 but L should be isolated to minimize noise and error Pin Configuration 107 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Pin Configuration 108 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 8 PIN CONNECT BLOCK FEATURES Allows individual pin configuration APPLICATIONS The purpose of the Pin Connect Block is to configure the microcontroller pins to the desired functions DESCRIPTION The pin connect block allows selected pins of the microcontroller to have more than one function Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals Peri
114. Pin Connect Block Note All Port 2 pins excluding those that can be used as A D inputs P2 30 and P2 31 are functionally 5V tolerant Port 2 pin configured to perform an input function will use built in pull up resistor to set the default input level to high If the A D converter is not used at all pins associated with A D inputs can be used as 5V tolerant digital lO pins See A D Converter chapter for A D input pin voltage considerations 102 May 03 2004 Philips Semiconductors ARM based Microcontroller Table 56 Pin description for LPC2212 2214 Preliminary User Manual LPC2114 2124 2212 2214 LQFP144 Deme E ee Pin Configuration External memory data line 0 External memory data line 1 External memory data line 2 External memory data line 3 External memory data line 4 External memory data line 5 External memory data line 6 External memory data line 7 External memory data line 8 External memory data line 9 External memory data line 10 External memory data line 11 External memory data line 12 External memory data line 13 External memory data line 14 External memory data line 15 External memory data line 16 External memory data line 17 External memory data line 18 External memory data line 19 External memory data line 20 External memory data line 21 103 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontrol
115. R W on the month and whether it is a leap year 0xE0024030 DOW Day of week value in the range of 0 to 6 R W 0xE0024034 DOY 99 Day of year value in the range of 1 to 365 366 for leap years 1 R W 0xE0024038 MONTH Month value in the range of 1 to 12 R W 0xE002403C YEAR Year value in the range of 0 to 4095 R W Notes 1 These values are simply incremented at the appropriate intervals and reset at the defined overflow point They are not calculated and must be correctly initialized in order to be meaningful Leap Year Calculation The RTC does a simple bit comparison to see if the two lowest order bits of the year counter are zero If true then the RTC considers that year a leap year The RTC considers all years evenly divisible by 4 as leap years This algorithm is accurate from the year 1901 through the year 2099 but fails for the year 2100 which is not a leap year The only effect of leap year on the RTC is to alter the length of the month of February for the month day of month and year counters Real Time Clock 206 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 ALARM REGISTER GROUP The alarm registers are shown in Table 153 The values in these registers are compared with the time counters If all the unmasked See Alarm Mask on page 202 alarm registers match their corresponding time counters then an interrupt is generated The interrupt is cleared when
116. RED FOR WRITE OPERATION BUSY CMD LOCKED PARAM ERROR CODE READ PROTECTION ENABLED This command is used to program the flash memory The affected sectors should be prepared first by calling Prepare Sector for Write Operation command The affected sectors are automatically Description protected again once the copy command is successfully executed The boot sector can not be written by this command As of Bootloader rev 1 61 this command is blocked when code read protection is enabled C 0 1073774592 512 lt CR gt lt LF gt copies 512 bytes from the RAM address 0x4000 8000 to the flash Example address 0 Flash Memory System and Programming 229 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Go address Mode Table 172 ISP Go command description Command G Address Flash or RAM address from which the code execution is to be started This address should Input be on a word boundary Mode T Execute program in Thumb Mode A Execute program in ARM mode CMD SUCCESS ADDR ERROR ADDR NOT MAPPED Return Code CMD LOCKED PARAM ERROR CODE READ PROTECTION ENABLED This command is used to execute call a program residing in RAM or Flash memory It may not be Description possible to return to ISP command handler once this command is successfully executed If executed code has ended with return instruction ISP handler will resume wi
117. Rd 198 REG lriterr pts i ied e eren in peeled ARIS DDR eR ada 200 Miscellaneous Register Group oooococcococ m 201 Consolidated Time Registers oocococcocccncrr rne 204 Time Counter Group cssc e Re RR Er RESP Aa a Rn EXERCERI d 206 Alarm Register Group 2 2 mme 207 RTC Usage Notes vocal ie bwin A cei eee a Ros qu AR 207 Reference Clock Divider Prescaler sssseseeeleee teen eens 208 Watchdog ucc o kirara a er a teeta ed bia cans m deis 211 Feal les x c uu IE erede reuera ue e Estee i reset 211 Applications a esto It SERE REI A REESE RID S a AAA ts 211 Descriptio Dc 211 Register Description ccm LS a ee DS RIS 212 Usage Notes on Watchdog Reset and External Start o oooooooccoococoo een eee 214 Pd cine ary sabe oie anda DU Y ewe Edo as on e ROSA ear Reda tae 215 Block Diagram dresses dna aad D eMe eon eoi salon Eee A Reale acier EN RR d 216 Flash Memory System and Programming sseseee eene 217 Flash Memory System ss eseis centa satoo mere 217 Flash boot toader iei spend greener hag ada UE DU ERETISQONRRR EET EE REIR 217 Feal les xe A A eg A eut occ EN PEU At neem 217 Applications tese A A BRE XE AA RI EM a 217 Description s 3 22 t uerb ia Eu p eter ee daa ive 217 Boot process FlowChart ococccocccoco erm 221 Sector Numbers eee aye RR VIAM MU DU E eed ae ea VERE RE DER 223 Code Read Protection oooococococcoco hh 224 JTAG FLASH Programming interface cece e
118. S eta vais rer rd ake E eA 115 KC c m 115 AppliCatlOns x vtr eset Est wen vu eiue e esie eL e uM LIS pte leute eA are ena 115 Pili Description s s 2v emere ren ROSA SES MD deor token 115 Register Description sco icu eer ke aeree e E Y b Dak n a 115 GPIO Usage Notes iaa nee pps ac da dee heed tr bu a LAORE et A 118 DJ YIIUPRPRUDCC DI ERIT 121 BILCIIMMEREDE CDM 121 Pin Description ge ek be eer hee a GU EUR a Deak win de wate 121 Register Description 00 Sh ee ed ee Pe ee 122 ArChItecture n oi raea E Atak eens ales A RE REG CR ale ace alle EN PRER 130 VAR Toons A a A A ete Us Mel e palates ete eo ea aa 133 Fealures ors EREIGNIS A OU REN NUN PEE ne s 133 Pin Description sce mE A M UAE LAE ER ate tated atk 133 Register Description oooooooocrocoror elm me 134 Architecture v nai a UE a ea CUR ct rs aes ng se Pos a 145 l2C Interface A A meurtre se mE ERE 147 AO este a due ut gor EO ade bp eae A Ee Ga BARRERA 147 AppliGations ux onere tee m ve ei enu rie wr buic Here 147 Description voces egt ere A necu RIA yay pU DRE EE RR EORR 147 Pin Description sui qe sede 2 PI DUE et ee ee P ue den eot eee ER e Rod e ed 151 Register Description lleleeeeeeeeee ee Rh m mh rn 152 Atchitect re vus EVI REN ee A or eR a Vx NE UH Ere i RE 158 SPI Interface 2 coo A REI IEEE A 159 Features ais a A RU ANREDE UR UR CR period 159 DescriptlOrn seo oer A WE DW E VEG AM 159 PIN Description us ah RA RA a IRSE CURE CREER NOE RERERRUR E 163 Reg
119. TO ENABLE REALMONITOR The following steps must be performed to enable RealMonitor A code example which implements all the steps can be found at the end of this section Adding stacks User must ensure that stacks are set up within application for each of the processor modes used by RealMonitor For each mode RealMonitor requires a fixed number of words of stack space User must therefore allow sufficient stack space for both RealMonitor and application RealMonitor has the following stack requirements Table 193 RealMonitor stack requirement Processor Mode RealMonitor Stack Usage Bytes Undef 48 IRQ mode A stack for this mode is always required RealMonitor uses two words on entry to its interrupt handler These are freed before nested interrupts are enabled Undef mode A stack for this mode is always required RealMonitor uses 12 words while processing an undefined instruction exception SVC mode RealMonitor makes no use of this stack Prefetch Abort mode RealMonitor uses four words on entry to its Prefetch abort interrupt handler Data Abort mode RealMonitor uses four words on entry to its data abort interrupt handler User System mode RealMonitor makes no use of this stack FIQ mode RealMonitor makes no use of this stack RealMonitor 253 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Handling exceptions This section descr
120. This analog input is always connected to its pin CAPO 3 Capture input for TIMERO channel 3 MATO 3 Match output for TIMERO channel 3 AIN3 A D converter input 3 This analog input is always connected to its pin EINT3 External interrupt 3 input CAPO 0 Capture input for TIMERO channel 0 Port 1 Port 1 is a 32 bit bi directional I O port with individual direction controls for each bit 91 90 34 24 15 The operation of port 1 pins depends upon the pin function selected via the Pin Connect 7 102 95 86 8 Block Pins 2 through 15 of port 1 are not available 2 70 60 52 144 140 126 113 Note All Port 1 pins are 5V tolerant with built in pull up resistor that sets input level to high 43 when corresponding pin is used as input 91 P1 0 CSO Low active Chip Select 0 signal Bank 0 addresses range 8000 0000 80FF FFFF OE Low active Output Enable signal TRACEPKTOTrace Packet bit 0 Standard I O port with internal pull up TRACEPKT1Trace Packet bit 1 Standard I O port with internal pull up TRACEPKT2Trace Packet bit 2 Standard I O port with internal pull up Pin Configuration 101 May 03 2004 Philips Semiconductors ARM based Microcontroller Table 56 Pin description for LPC2212 2214 LQFP144 EA AS INCNENNI P1 19 TRACEPKT3Trace Packet bit 3 Standard I O port with internal pull up 98 105 106 10 8 109 114 118 120 124 1 25 127 129 134 136 137 1 10 13 16 20 Pin Configuration Preliminary User M
121. This flag is found in the SPINT registrer SPI Data Register SOSPDR 0xE0020008 S1SPDR 0xE0030008 This bi directional data register provides the transmit and receive data for the SPI Transmit data is provided to the SPI by writing to this register Data received by the SPI can be read from this register When a master a write to this register will start a SPI data transfer Writes to this register will be blocked from when a data transfer starts to when the SPIF status bit is set and the status register has not been read Table 118 SPI Data Register SOSPDR 0xE0020008 S1SPDR 0xE0030008 Function Description Data SPI Bi directional data port SPI Clock Counter Register SOSPCCR 0xE002000C S1SPCCR 0xE003000C This register controls the frequency of a master s SCK The register indicates the number of pclk cycles that make up an SPI clock The value of this register must always be an even number As a result bit O must always be 0 The value of the register must also always be greater than or equal to 8 Violations of this can result in unpredictable behavior Table 119 SPI Clock Counter Register SOSPCCR 0xE002000C S1SPCCR 0xE003000C Function Description Counter SPI Clock counter setting SPI Interface 165 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 The SPI rate may be calculated as PCLK rate SPCCR value The pclk rate
122. This option enables or disables support for any target to host packets sent on a non RealMonitor third party channel RM OPT STOPSTART TRUE This option enables or disables support for all stop and start debugging features RM OPT SOFTBREAKPOINT TRUE This option enables or disables support for software breakpoints RM_OPT_HARDBREAKPOINT TRUE Enabled for cores with EmbeddedICE RT This device uses ARM 7TDMI S Rev 4 with EmbeddedICE RT RM_OPT_HARDWATCHPOINT TRUE Enabled for cores with EmbeddedICE RT This device uses ARM 7TDMI S Rev 4 with EmbeddedICE RT RM_OPT_SEMIHOSTING FALSE This option enables or disables support for SWI semi hosting Semi hosting provides code running on an ARM target use of facilities on a host computer that is running an ARM debugger Examples of such facilities include the keyboard input screen output and disk I O RM_OPT_SAVE_FIQ_REGISTERS TRUE This option determines whether the FIQ mode registers are saved into the registers block when RealMonitor stops RM_OPT_READBYTES TRUE RM_OPT_WRITEBYTES TRUE RM_OPT_READHALFWORDS TRUE RM_OPT_WRITEHALFWORDS TRUE RM_OPT_READWORDS TRUE RM_OPT_WRITEWORDS TRUE Enables Disables support for 8 16 32 bit read write RM_OPT_EXECUTECODE FALSE Enables Disables support for executing code from execute code buffer The code must be downloaded first RM_OPT_GETPC TRUE This option enables or disables support for the RealMonitor GetPC packet Useful in code profiling when
123. XTMODE3 Reserved user software should not write ones to reserved bits The value read from Reserved me a reserved bit is not defined Multiple External Interrupt Pins Software can select multiple pins for each of EINT3 0 in the Pin Select registers which are described in chapter Pin Connect Block on page 109 The external interrupt logic for each of EINT3 0 receives the state of all of its associated pins from the pins receivers along with signals that indicate whether each pin is selected for the EINT function The external interrupt logic handles the case when more than one pin is so selected differently according to the state of its Mode and Polarity bits In Low Active Level Sensitive mode the states of all pins selected for EINT functionality are digitally combined using a positive logic AND gate In High Active Level Sensitive mode the states of all pins selected for EINT functionality are digitally combined using a positive logic OR gate n Edge Sensitive mode regardless of polarity the pin with the lowest GPIO port number is used Selecting multiple EINT pins in edge sensitive mode could be considered a programming error The signal derived by this logic is the EINTi signal in the following logic schematic Figure 14 When more than one EINT pin is logically ORed the interrupt service routine can read the states of the pins from GPIO port using IOOPINO and IO1PIN registers to determine which pin s caused th
124. a one is written to bit one of the Interrupt Location Register ILR 1 Table 153 Alarm Registers Address Name Description Access 0xE0024060 ALSEC Alarm value for Seconds R W 0xE0024064 ALMIN REL Alarm value for Minutes R W 0xE0024068 ALHOUR Alarm value for Hours R W 0xE002406C ALDOM Alarm value for Day of Month R W m wes mnov s O HM m y RTC USAGE NOTES Since the RTC operates from the VPB clock pclk any interruption of that clock will cause the time to drift away from the time value it would have provided otherwise The variance could be to actual clock time if the RTC was initialized to that or simply an error in elapsed time since the RTC was activated No provision is made in the LPC2114 2124 2212 2214 to retain RTC status upon power loss or to maintain time incrementation if the clock source is lost interrupted or altered Loss of chip power will result in complete loss of all RTC register contents Entry to Power Down mode will cause a lapse in the time update Altering the RTC timebase during system operation by reconfiguring the PLL the VPB timer or the RTC prescaler will result in some form of accumulated time error Real Time Clock 207 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 REFERENCE CLOCK DIVIDER PRESCALER The reference clock divider hereafter referred to as the Prescaler allows generation of a 32 768 kHz reference clock
125. a read or write of the UOSCR has occurred Table 85 UARTO Scratchpad Register UOSCR 0xE000C01C UOSCR Function Description 7 0 A readable writable byte UARTO 129 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 ARCHITECTURE The architecture of the UARTO is shown below in the block diagram The VPB interface provides a communications link between the CPU or host and the UARTO The UARTO receiver block UORx monitors the serial input line RxDO for valid input The UARTO Rx Shift Register UORSR accepts valid characters via RxDO After a valid character is assembled in the UORSR it is passed to the UARTO Rx Buffer Register FIFO to await access by the CPU or host via the generic host interface The UARTO transmitter block UOTx accepts data written by the CPU or host and buffers the data in the UARTO Tx Holding Register FIFO UOTHR The UARTO Tx Shift Register UOTSR reads the data stored in the UOTHR and assembles the data to transmit via the serial output pin TxDO The UARTO Baud Rate Generator block UOBRG generates the timing enables used by the UARTO Tx block The UOBRG clock input source is the VPB clock pclk The main clock is divided down per the divisor specified in the UODLL and UODLM registers This divided down clock is a 16x oversample clock NBAUDOUT The interrupt interface contains registers UOIER and UOIIR The interrupt interface receiv
126. able 132 PWM Control Register PWMPCR 0xE001404C 2 2 2 0 nananana 190 Table 133 PWM Latch Enable Register PWMLER 0xE0014050 0 0 0 0 cee eee eee 191 Table 134 A D Pin Description 0 00 00 a aei ee eee m hh 193 Table 135 A D Registers else ee eee a ROC HERR eb de BR Ue s 193 Table 136 A D Control Register ADCR 0xE0034000 o oooooococcocr esee 194 Table 137 A D Data Register ADDR 0xE0034004 o ooooocococcco nn 195 Table 138 Real Time Clock Register Map sssseseseeeeee e mn 199 Table 139 Miscellaneous Registers llileleeeee RR I 201 Table 140 Interrupt Location Register Bits ILR OxE0024000 0 0 eee eee ee 201 Table 141 Clock Tick Counter Bits CTC OXE0024004 ssssseeeeeee eee 201 Table 142 Clock Control Register Bits CCR OxE0024008 0 cc eee ete eee 202 Table 143 Counter Increment Interrupt Register Bits CIIR OXE002400C 000 5 202 Table 144 Alarm Mask Register Bits AMR OXE0024010 0 eee eee 203 Table 145 Consolidated Time Register 0 Bits CTIMEO OXE0024014 0 0 eee ee 204 Table 146 Consolidated Time Register 1 Bits CTIME1 OxE0024018 0 00 02 ee ee ee 204 Table 147 Consolidated Time Register 2 Bits CTIME2 OxE002401C 0 00 205 Table 148 Time Counter Relationships and ValueS oocococccccococo 206 Table 149 Time Counter registers 0 0 0
127. abled 4 Reset on MR1 When one the TC will be reset if MR1 matches it When zero this feature is disabled 5 Stop on MR1 When one the TC and PC will be stopped and TCR 0 will be set to 0 if MR1 matches P the TC When zero this feature is disabled When one an interrupt is generated when MR2 matches the value in the TC When Interrupt on MR2 nag ee zero this interrupt is disabled 7 Reset on MR2 When one the TC will be reset if MR2 matches it When zero this feature is disabled Interrupt on MRO 0 When one an interrupt is generated when MR3 matches the value in the TC When Interrupt on MR3 1 zero this interrupt is disabled 10 Reset on MR3 When one the TC will be reset if MR3 matches it When zero this feature is disabled Stop on MR2 When one the TC and PC will be stopped and TCR 0 will be set to 0 if MR2 matches P the TC When zero this feature is disabled 11 Stop on MR3 When one the TC and PC will be stopped and TCR 0 will be set to O if MR3 matches P the TC When zero this feature is disabled EI EEN 2 ES E E ES rw ES TimerO and Timer1 173 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Capture Registers CRO CR3 Each Capture register is associated with a device pin and may be loaded with the Timer Counter value when a specified event occurs on that pin The settings in the Capture Control Register register determine whether the capture
128. access data not in MAM latches Initiate Fetch Initiate Fetch Initiate Fetch Non Sequential access data in MAM latches Initiate Fetch Initiate Fetch Use Latched Data Non Sequential access data not in MAM latches Initiate Fetch Initiate Fetch Initiate Fetch Table 36 MAM Responses to Data and DMA Accesses of Various Types MAM Mode Data Memory Request Type 0 1 2 Sequential access data in MAM latches Initiate Fetch Initiate Fetch Use Latched Data Sequential access data not in MAM latches Initiate Fetch Initiate Fetch Initiate Fetch Non Sequential access data in MAM latches Initiate Fetch Initiate Fetch Use Latched Data Non Sequential access data not in MAM latches Initiate Fetch Initiate Fetch Initiate Fetch Instruction prefetch is enabled in modes 1 and 2 2 The MAM actually uses latched data if it is available but mimics the timing of a Flash read operation This saves power while resulting in the same execution timing The MAM can truly be turned off by setting the fetch timing value in MAMTIM to one clock Memory Accelerator Module MAM 75 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 MAM CONFIGURATION After reset the MAM defaults to the disabled state Software can turn memory access acceleration on or off at any time This allows most of an application to be run at the highest possible performance while certain funct
129. addition a match between MR4 and the TC clears PWMA in either single 0xE0014040 edge mode or double edge mode and sets PWM6 if it is in double edge mode Pulse Width Modulator PWM 185 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 131 Pulse Width Modulator Register Map Description Address PWM Match Register 5 MR5 can be enabled through MCR to reset the TC stop both the TC and PC and or generate an interrupt when it matches the TC In addition a match between MR5 and the TC clears PWM5 in either single edge mode or double edge mode and sets PWM6 if it is in double edge mode PWMMR5 0xE0014044 PWM Match Register 6 MR6 can be enabled through MCR to reset the TC stop both the TC and PC and or generate an interrupt when it matches the TC HIMES In addition a match between MR6 and the TC clears PWM6 in either single 0XE0014048 edge mode or double edge mode 0xE001404C 0xE0014050 Reset Value refers to the data stored in used bits only It does not include reserved bits content Pulse Width Modulator PWM 186 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 PWM Interrupt Register PWMIR 0xE0014000 The PWM Interrupt Register consists of eleven bits Table 132 seven for the match interrupts and four reserved for the future use If an interrupt is generated then the corres
130. after any reset The boot sector is 8 kB in size and resides in the top portion starting from 0x0001 E000 in 128 kB Flash part and from 0x0003 E000 in 256 kb Flash part of the on chip flash memory After any reset the entire boot sector is also mapped to the top Flash Memory System and Programming 217 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 of the on chip memory space i e the boot sector is also visible in the memory region starting from the address Ox7FFF E000 The flash boot loader is designed to run from this memory area but both the ISP and IAP software use parts of the on chip RAM The RAM usage is described later in this chapter The interrupt vectors residing in the boot sector of the on chip flash memory also become active after reset i e the bottom 64 bytes of the boot sector are also visible in the memory region starting from the address 0x0000 0000 The reset vector contains a jump instruction to the entry point of the flash boot loader software 2 0 GB 8k byte Boot Block QXIFEEEFRE re mapped from top of Flash memory 2 0 GB 8kB Boot Block interrupt vectors Ox7FFF E000 0x0001 FFFF 8k byte Boot Block re Mapped to higher address range 0x0001 E000 0 0 GB Active interrupt vectors from the Boot Block 0x0000 0000 Note memory regions are not drawn to scale Figure 43 Map of lower memory after any reset 128 kB Flash part Criterion for valid u
131. al 126 OxFFFF 8000 AHB peripheral 125 OxFFFF 4000 AHB peripheral 124 OxFFFF 0000 OxFFE1 0000 AHB peripheral 3 OxFFEO C000 AHB peripheral 2 OxFFEO 8000 AHB peripheral 1 OxFFEO 4000 AHB peripheral 0 OxFFEO 0000 Figure 4 AHB Peripheral Map LPC2114 2124 2212 2214 Memory Addressing 35 May 03 2004 Philips Semiconductors ARM based Microcontroller System Control Block VPB peripheral 127 VPB peripherals 1 4 126 not used 10 bit A D VPB peripheral 13 SPI1 VPB peripheral 12 Pin Connect Block VPB peripheral 11 GPIO VPB peripheral 10 RTC VPB peripheral 9 SPIO VPB peripheral 8 C VPB peripheral 7 not used VPB peripheral 6 PWMO VPB peripheral 5 UART1 VPB peripheral 4 UARTO VPB peripheral 3 TIMER1 VPB peripheral 2 TIMERO VPB peripheral 1 Watchdog Timer VPB peripheral 0 Figure 5 VPB Peripheral Map LPC2114 2124 2212 2214 Memory Addressing 36 Preliminary User Manual LPC2114 2124 2212 2214 OxEO1F FFFF OxEO1F C000 0xE003 8000 0xE003 4000 0xE003 0000 0xE002 C000 0xE002 8000 0xE002 4000 0xE002 0000 0xE001 C000 0xE001 8000 OxE001 4000 0xE001 0000 0xE000 C000 0xE000 8000 0xE000 4000 0xE000 0000 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214
132. ammable 32 bit timer with internal pre scaler Selectable time period from tpg x 256 x 4 to toc x 29 x 4 in multiples of tpoik x 4 APPLICATIONS The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state When enabled the Watchdog will generate a system reset if the user program fails to feed or reload the Watchdog within a predetermined amount of time For interaction of the on chip watchdog and other peripherals especially the reset and boot up procedures please read Reset and Boot Control on 144 pin Package sections of this document DESCRIPTION The Watchdog consists of a divide by 4 fixed pre scaler and a 32 bit counter The clock is fed to the timer via a pre scaler The timer decrements when clocked The minimum value from which the counter decrements is OxFF Setting a value lower than OxFF causes OxFF to be loaded in the counter Hence the minimum Watchdog interval is tpg x 256 x 4 and the maximum Watchdog interval is toci x 232 x 4 in multiples of tock X 4 The Watchdog should be used in the following manner Set the Watchdog timer constant reload value in WDTC register Setup mode in WDMOD register Start the Watchdog by writing OxAA followed by 0x55 to the WDFEED register Watchdog should be fed again before the Watchdog counter underflows to prevent reset interrupt When the Watchdog counter underflows the program counter will sta
133. anual LPC2114 2124 2212 2214 P1 20 TRACESYNCTrace Synchronization Standard I O port with internal pull up Important PIPESTATO PIPESTAT1 PIPESTAT2 TRACECLK EXTINO RTCK Important TDO TDI TCK TMS TRST LOW on this pin while RESET is LOW enables pins P1 25 16 to operate as a Trace port after reset LOW on pin P1 20 while RESET is LOW enables pins P1 25 16 to operate as a Trace port after reset Pipeline Status bit O Standard I O port with internal pull up Pipeline Status bit 1 Standard I O port with internal pull up Pipeline Status bit 2 Standard I O port with internal pull up Trace Clock Standard I O port with internal pull up External Trigger Input Standard I O with internal pull up Returned Test Clock output Extra signal added to the JTAG port Assists debugger synchronization when processor frequency varies Bi directional pin with internal pullup LOW on this pin while RESET is LOW enables pins P1 31 26 to operate as a Debug port after reset LOW on pin P1 26 while RESET is LOW enables pins P1 31 26 to operate as a Debug port after reset Test Data out for JTAG interface Test Data in for JTAG interface Test Clock for JTAG interface Test Mode Select for JTAG interface Test Reset for JTAG interface Port 2 Port 2 is a 32 bit bi directional I O port with individual direction controls for each bit The operation of port 2 pins depends upon the pin function selected via the
134. applicable Destination address is not mapped in the memory DST ADDR NOT MAPPED map Count value is taken in to consideration where applicable COUNT ERROR Byte count is not multiple of 4 or is not a permitted value INVALID SECTOR Sector number is invalid or end sector number is greater than start sector number SECTOR NOT BLANK Sector is not blank SECTOR NOT PREPARED FOR WRITE OPERATION xii d prepare sector for write Operator was COMPARE_ERROR Source and destination data not equal BUSY Flash programming hardware interface is busy PARAM_ERROR Insufficient number of parameters or invalid parameter ADDR_ERROR Address is not on word boundary ADDR_NOT_MAPPED Address is not mapped in the memory map Count value is taken in to consideration where applicable CMD_LOCKED Command is locked INVALID_CODE Unlock code is invalid INVALID_BAUD_RATE Invalid baud rate setting CODE_READ_PROTECTION_ENABLED Code read protection enabled Available as of Bootloader rev 1 61 0 T DERI ERE RN REN Ed E Em mum BUR BH INVALID STOP BIT Invalid stop bit setting 7 10 11 12 13 14 15 16 17 18 9 1 Flash Memory System and Programming 233 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 IAP Commands For in application programming the IAP routine should be called with a word pointer in register rO pointing to memory RAM containing command code and para
135. apture input for TIMER1 channel 2 Serial Clock for SPI1 SPI clock output from master or input to slave Match output for TIMER1 channel 2 Capture input for TIMER1 channel 3 Master In Slave Out for SPI Data input to SPI master or data output from SPI slave Match output for TIMER1 channel 3 Match output for TIMER1 channel 2 Master Out Slave In for SPI1 Data output from SPI master or data input to SPI slave Capture input for TIMER1 channel 2 Match output for TIMER1 channel 3 Slave Select for SPI1 Selects the SPI interface as a slave External interrupt 3 input Pulse Width Modulator output 5 Capture input for TIMER1 channel 3 100 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 56 Pin description for LPC2212 2214 LQFP144 EOS A CAPO 0 Capture input for TIMERO channel 0 MATO 0 Match output for TIMERO channel 0 General purpose bidirectional digital port only General purpose bidirectional digital port only General purpose bidirectional digital port only AINO A D converter input 0 This analog input is always connected to its pin CAPO 1 Capture input for TIMERO channel 1 MATO 1 Match output for TIMERO channel 1 AIN1 A D converter input 1 This analog input is always connected to its pin CAPO0 2 Capture input for TIMERO channel 2 MATO 2 Match output for TIMERO channel 2 AIN2 A D converter input 2
136. ased Microcontroller LPC2114 2124 2212 2214 12C Control Set Register IZCONSET 0xE001C000 AA is the Assert Acknowledge Flag When set to 1 an acknowledge low level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations The address in the Slave Address Register has been received The general call address has been received while the general call bit GC in I2ADR is set on gt A data byte has been received while the 12C is in the master receiver mode 4 A data byte has been received while the 12C is in the addressed slave receiver mode The AA bit can be cleared by writing 1 to the AAC bit in the IACONCLR register When AA is 0 a not acknowledge high level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 A data byte has been received while the I C is in the master receiver mode 2 A data byte has been received while the C is in the addressed slave receiver mode Sl is the 12C Interrupt Flag This bit is set when one of the 25 possible 12C states is entered Typically the lc interrupt should only be used to indicate a start condition at an idle slave device or a stop condition at an idle master device if it is waiting to use the 12C bus SI is cleared by writing a 1 to the SIC bit in IICONCLR register STO is the STOP flag Setting this bit causes the 12C interface to transmit a STOP condition in master mode or recover from
137. ash or RAM address from where data bytes are to be compared This address should be on word boundary Number of Bytes Number of bytes to be compared Count should be in multiple of 4 CMD SUCCESS Source and destination data is same COMPARE ERROR Followed by the offset of first mismatch COUNT ERROR Byte count is not multiple of 4 Return Code ADDR ERROR ADDR NOT MAPPED PARAM ERROR This command is used to compare the memory contents at two locations M 8192 1073741824 4 lt CR gt lt LF gt compares 4 bytes from the RAM address 0x4000 0000 to the 4 bytes from the flash address 0x2000 Compare result may not be correct when source or destination address contains any of the first 64 bytes starting from address zero First 64 bytes are re mapped to flash boot sector Flash Memory System and Programming 232 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 178 ISP Return Codes Summary Return Code Mnemonic Description Command is executed successfully Sent by ISP CMD SUCCESS handler only when command given by the host has been completely and successfully executed 1 INVALID COMMAND Invalid command 2 SRC ADDR ERROR Source address is not on word boundary 3 DST ADDR ERROR Destination address is not on a correct boundary Source address is not mapped in the memory map SRC ADDR NOT MAPPED Count value is taken in to consideration where
138. ata and comparison address for that bank from the last Instruction miss The other set called the Prefetch Buffer holds the data and comparison address from prefetches undertaken speculatively by the MAM Each Instruction Latch holds 4 words of code 4 ARM instructions or 8 Thumb instructions Similarly there is a 128 bit Data Latch and 13 bit Data Address latch that are used during Data cycles This single set of latches is shared by both Flash banks Each Data access that is not in the Data latch causes a Flash fetch of 4 words of data which are captured in the Data latch This speeds up sequential Data operations but has little or no effect on random accesses Flash Programming Issues Since the Flash memory does not allow accesses during programming and erase operations it is necessary for the MAM to force the CPU to wait if a memory access to a Flash address is requested while the Flash module is busy This is accomplished by asserting the ARM7TDMI S local bus signal CLKEN Under some conditions this delay could result in a Watchdog time out The user will need to be aware of this possibility and take steps to insure that an unwanted Watchdog reset does not cause a system failure while programming or erasing the Flash memory Memory Accelerator Module MAM 74 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 In order to preclude the possibility of stale data being read from
139. ately resulting in the IRQ not being acknowledged cleared and further IRQs being disabled Similar code may also be applied to the FIQ handler in order to resolve the first issue This is the recommended workaround as it overcomes both problems mentioned above However in the case of problem two it does add several cycles to the maximum length of time FIQs will be disabled Vectored Interrupt Controller VIC 89 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Solution 2 Disable IRQs and FIGs using separate writes to the CPSR eg MRS r0 cpsr ORR LOs r0 FL BIC disable IRQs MSR cpsr c roO ORR rO r0 F Bit disable FIQs MSR cpsr c ro This is the best workaround where the maximum time for which FIQs are disabled is critical it does not increase this time at all However it does not solve problem one and requires extra instructions at every point where IRQs and FIQs are disabled together Solution 3 Re enable FIQs at the beginning of the IRQ handler As the required state of all bits in the c field of the CPSR are known this can be most efficiently be achieved by writing an immediate value to CPSR c for example MSR Cpsr c 4I Bit OR irq MODE IRQ should be disabled FIQ enabled ARM state IRQ mode This requires only the IRQ handler to be modified and FIQs may be re enabled more quickly than by using workaround 1 However this should only be
140. baud rate of the UART1 UART1 Interrupt Enable Register U1IER 0xE0010004 when DLAB 0 The U1IER is used to enable the four interrupt sources Table 92 UART1 Interrupt Enable Register Bit Descriptions U1IER 0xE0010004 when DLAB 0 Function Description 0 Disable the RDA interrupt RBR Interrupt 1 Enable the RDA interrupt Enable U1IERO enables the Receive Data Available interrupt for UART1 It also controls the Receive Time out interrupt 0 Disable the THRE interrupt THRE Interrupt 1 Enable the THRE interrupt Enable U1IER1 enables the THRE interrupt for UART1 The status of this interrupt can be read from U1LSR5 0 Disable the Rx line status interrupts Rx Line Status 1 Enable the Rx line status interrupts Interrupt Enable U1IER2 enables the UART1 Rx line status interrupts The status of this interrupt can be read from U1LSR A 1 0 Disable the modem interrupt Modem Status 1 Enable the modem interrupt Interrupt Enable U1IERS enables the modem interrupt The status of this interrupt can be read from U1MSR 3 0 Reserved user software should not write ones to reserved bits The value read from a Reserved n reserved bit is not defined UART1 136 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 UART1 Interrupt Identification Register U1IIR OXE0010008 Read Only The U1IIR provides a status code that den
141. bled 1 0 MAM functions fully enabled 1 1 reserved Reserved user software should not write ones to reserved bits The value read from a 7 2 Reserved SR 3 NA reserved bit is not defined MAM Timing Register MAMTIM 0xE01FC004 MAM mode control The MAM Timing register determines how many cclk cycles are used to access the Flash memory This allows tuning MAM timing to match the processor operating frequency Flash access times from 1 clock to 7 clocks are possible Single clock Flash accesses would essentially remove the MAM from timing calculations In this case the MAM mode may be selected to optimize power usage Table 39 MAM Timing Register MAMTIM 0xE01FC004 MAMTIM Function Description These bits set the duration of MAM Flash fetch operations as follows 00020 Reserved 00121 MAM fetch cycles are 1 processor clock cclk in duration 01022 MAM fetch cycles are 2 processor clocks cclks in duration 01123 MAM fetch cycles are 3 processor clocks cclks in duration 10024 MAM fetch cycles are 4 processor clocks cclks in duration MAM Fetch i l 5 MAM fetch cycles are 5 processor clocks cclks in duration cclks cclks Cycle timing 101 11026 MAM fetch cycles are 6 processor clocks cclks in duration 11127 MAM fetch cycles are 7 processor clocks cclks in duration Warning Improper setting of this value may result in incorrect operation of the device Reserved user software
142. cate to the host that a read or write of the U1SCR has occurred Table 100 UART1 Scratchpad Register U1SCR 0xE001001C U1SCR Function Description 7 0 A readable writable byte UART1 144 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 ARCHITECTURE The architecture of the UART1 is shown below in the block diagram The VPB interface provides a communications link between the CPU or host and the UART1 The UART1 receiver block U1Rx monitors the serial input line RxD1 for valid input The UART1 Rx Shift Register U1RSR accepts valid characters via RxD1 After a valid character is assembled in the U1RSR it is passed to the UART1 Rx Buffer Register FIFO to await access by the CPU or host via the generic host interface The UART1 transmitter block U1Tx accepts data written by the CPU or host and buffers the data in the UART1 Tx Holding Register FIFO U1THR The UART1 Tx Shift Register U1TSR reads the data stored in the U1THR and assembles the data to transmit via the serial output pin TxD1 The UART1 Baud Rate Generator block U1BRG generates the timing enables used by the UART1 Tx block The U1BRG clock input source is the VPB clock pclk The main clock is divided down per the divisor specified in the U1DLL and u1DLM registers This divided down clock is a 16x oversample clock NBAUDOUT The modem interface contains registers Uf MCR and U1MSR This inter
143. cece e 206 Table 150 Alarm Registers ris srie oea ena E A a hh 207 Table 151 Reference Clock Divider regiSterS oooococccoccocrcrr tees 208 Table 152 Prescaler Integer Register PREINT OxE0024080 0 0 eee eee 208 Table 153 Prescaler Fraction Register PREFRAC 0xE0024084 0 000 cc eee eee 208 Table 154 Prescaler cases where the Integer Counter reload value is incremented 210 Table 155 Watchdog Register Map 0 0 cee eee eee 212 Table 156 Watchdog Mode Register WDMOD OxEQO00000 0200 e eee eee 213 Table 157 Watchdog Feed Register WDFEED 0xE0000008 200 0 eee 214 Table 158 Watchdog Timer Value Register WDTV OXEQOO0O00C 20 eese 214 Table 159 Sectors in a device with 128K bytes of Flash 0 cece eee 223 Table 160 ISP Command Summary oococcoccc ehh ren 225 11 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 161 ISP Unlock command description llle eh 225 Table 162 ISP Set Baud Rate command description 0 000 cece eee 226 Table 163 Correlation between possible ISP baudrates and external crystal frequency in MHz 226 Table 164 ISP Echo command description liliis res 226 Table 165 ISP Write to RAM command description llle 227 Table 166 ISP Read Memory command description 0
144. ch 1 Table 128 shows the encoding of Control 1 these bits External Match Determines the functionality of External Match 2 Table 128 shows the encoding of Control 2 these bits 11 10 External Match Determines the functionality of External Match 3 Table 128 shows the encoding of j Control 3 these bits Table 128 External Match Control External Match 1 External Match 2 External Match 3 5 4 7 6 EMR 11 10 EMR 9 8 EMR 7 6 or EMR 5 4 Function Do Nothing Clear corresponding External Match output to 0 LOW if pinned out 00 TimerO and Timer 175 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 EXAMPLE TIMER OPERATION Figure 35 shows a timer configured to reset the count and generate an interrupt on match The prescaler is set to 2 and the match register set to 6 At the end of the timer cycle where the match occurs the timer count is reset This gives a full length cycle to the match value The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value Figure 36 shows a timer configured to stop and generate an interrupt on match The prescaler is again set to 2 and the match register set to 6 In the next clock after the timer reaches the match value the timer enable bit in TCR is cleared and the interrupt indicating that a match occurred is generated pclk Prescale
145. chpoints can be configured such that a range of addresses are enabled for the watchpoints to be active The RANGE function allows the breakpoints to be combined such that a breakpoint is to occur if an access occurs in the bottom 256 bytes of memory but not in the bottom 32 bytes The ARM7TDMI S core has a Debug Communication Channel function in built The debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state The debug communication channel is accessed as a co processor 14 by the program running on the ARM7TDMI S core The debug communication channel allows the JTAG port to be used for sending and receiving data without affecting the normal program flow The debug communication channel data and control registers are mapped in to addresses in the EmbeddedICE logic For more details refer to IEEE Standard 1149 1 1990 Standard Test Access Port and Boundary Scan Architecture EmbeddedICE Logic 241 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 PIN DESCRIPTION Table 188 EmbeddedlCE Pin Description Pin Name Type Description TMS Input Test Mode Select The TMS pin selects the next state in the TAP state machine TCK input Test Clock This allows shifting of the data in on the TMS and TDI pins It is a positive edge P triggered clock with th
146. clear value equals 0 and the other value equals the PWM rate 5 If a match value is out of range i e greater than the PWM rate value no match event occurs and that match channel has no effect on the output This means that the PWM output will remain always in one state allowing always low always high or no change outputs Pulse Width Modulator PWM 183 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 PIN DESCRIPTION Table 130 gives a brief summary of each of PWM related pins Table 130 Pin summary Pin name Pin direction Pin Description PWM1 Output Output from PWM channel 1 PWM2 Output Output from PWM channel 2 PWM3 Output Output from PWM channel 3 PWM4 Output Output from PWM channel 4 PWM5 Output Output from PWM channel 5 Output Output from PWM channel 6 Pulse Width Modulator PWM 184 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 REGISTER DESCRIPTION The PWM function adds new registers and registers bits as shown in Table 131 below Table 131 Pulse Width Modulator Register Map Name Description Address PRI E doom inch of he possible ntemuprsaures ale pend 0xE0014000 PWMPR PWM Prescale Register The TC is incremented every PR 1 cycles of pclk OxE001400C PWM Prescale Counter The 32 bit PC is a counter which is incremented to the PWMPG value stored in PR When t
147. ct Register 2 PINSEL2 register Symbol a b in following figures refers to the highest order address line in the data bus Symbol a m refers to the highest order address line of the memory chip used in the external memory interface OE OE OE OE BLS 3 D 31 24 WE IO 7 0 A a m 0 BLS 2 D 23 16 WE IO 7 0 A a m 0 BLS 1 D 15 8 WE IO 7 0 A a m 0 BLS 0 D 7 0 WE IO 7 0 A a m 0 A a b 2 a 32 bit wide memory bank interfaced to 8 bit memory chips CE OE WE CE OE WE CE OE WE BLS 3 BLS 2 D 31 16 UB LB 10 15 0 A a m 0 BLS 1 BLS 0 D 15 0 UB LB 10 15 0 A a m 0 BLS 3 BLS 2 BLS 1 BLS 0 D 31 0 B3 B2 B1 BO 10 31 0 A a b 2 A a m 0 Ala_b 0 C 32 bit wide memory bank interfaced to 32 bit memory chip b 32 bit wide memory bank interfaced to 16 bit memory chips Figure 7 32 Bit Bank External Memory Interfaces External Memory Controller EMC 44 May 03 2004 Philips Semiconductors ARM based Microcontroller BLS 1 D 15 8 CE OE WE I
148. ction chapter Pin Connect Block on page 109 and enabled in the VICIntEnable register chapter Vectored Interrupt Controller VIC on page 79 can cause interrupts from the External Interrupt function though of course pins selected for other functions may cause interrupts from those functions Note Software should only change a bit in this register when its interrupt is disabled in VICIntEnable and should write the corresponding 1 to EXTINT before re enabling the interrupt to clear the EXTINT bit that could be set by changing the polarity System Control Block 56 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 18 External Interrupt Polarity Register EXTPOLAR 0xE01FC14C EXTPOLAR Function Description When 0 EINTO is low active or falling edge sensitive depending on EXTMODEO When 1 EINTO is high active or rising edge sensitive depending on EXTMODEO EXTPOLAR1 When 0 EINT1 is low active or falling edge sensitive depending on EXTMODE1 When 1 EINT1 is high active or rising edge sensitive depending on EXTMODE1 0 EXTPOLARO 2 EXTPOLAR2 When 0 EINT2 is low active or falling edge sensitive depending on EXTMODE2 When 1 EINT2 is high active or rising edge sensitive depending on EXTMODE2 EXTPOLAR3 When 0 EINT3 is low active or falling edge sensitive depending on EXTMODES When 1 EINT3 is high active or rising edge sensitive depending on E
149. ction Enable Register VICProtection OXFFFFF020 Read Write 85 Table 54 Connection of Interrupt Sources to the Vectored Interrupt Controller 86 9 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 55 Pin description for LPC2114 2424 0 0 0 0 oooooooooco nes 94 Table 56 Pin description for LPC2212 2214 0 nannaa anaana nes 99 Table 57 Pin Connect Block Register Map 00 cece tte 109 Table 58 Pin Function Select Register 0 for LPC2114 2124 2212 2214 PINSELO OxE002C000 110 Table 59 Pin Function Select Register 1 for LPC2114 2124 2212 2214 PINSEL1 OXE002C004 110 Table 60 Pin Function Select Register 2 for LPC2114 2124 PINSEL2 OXE002C014 111 Table 61 Pin Function Select Register 2 for LPC2212 2214 PINSEL2 0xE002C014 112 Table 62 Pin Function Select Register Bits lille nes 113 Table 63 Boot Control on BOOT1 0 oocoococcccococ ee heres 114 Table 64 GPIO Pin Description RR e 115 Table 65 GPIO Register Map isseseeseeeseeee mre 116 Table 66 GPIO Pin Value Register IOOPIN 0xE0028000 IO1PIN 0xE0028010 IO2PIN 0xE0028020 IO3PIN 0xXE0028030 o oococcocccocc eh 117 Table 67 GPIO Output Set Register IOOSET 0xE0028004 IO1SET 0xE0028014 IO2SET 0xE0028024 IOSSET OxE0028034 o oocccoccccccccc ees 117 Table 68 GPIO Outpu
150. d PLL Interrupt The PLOCK bit in the PLLSTAT register is connected to the interrupt controller This allows for software to turn on the PLL and continue with other functions without having to wait for the PLL to achieve lock When the interrupt occurs PLOCK 1 the PLL may be connected and the interrupt disabled PLL Modes The combinations of PLLE and PLLC are shown in Table 25 Table 25 PLL Control Bit Combinations PLLC PLLE PLL Function 0 0 PLL is turned off and disconnected The system runs from the unmodified clock input 1 The PLL is active but not yet connected The PLL can be connected after PLOCK is asserted 1 EE Same as 0 0 combination This prevents the possibility of the PLL being connected without also being enabled 1 The PLL is active and has been connected as the system clock source PLL Feed Register PLLFEED 0xE01FC08C A correct feed sequence must be written to the PLLFEED register in order for changes to the PLLCON and PLLCFG registers to take effect The feed sequence is 1 Write the value OxAA to PLLFEED 2 Write the value 0x55 to PLLFEED System Control Block 63 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 The two writes must be in the correct sequence and must be consecutive VPB bus cycles The latter requirement implies that interrupts must be disabled for the duration of the PLL feed operation If either of the
151. d Parameter 0 Parameter 1 Parameter n CR LF Data Applicable only in case of Write commands ISP Response Format Return_Code lt CR gt lt LF gt Response_0 lt CR gt lt LF gt Response_1 lt CR gt lt LF gt Response n CR LF Data Applicable in case of Read commands ISP Data Format The data stream is in UU encode format The UU encode algorithm converts 3 bytes of binary data in to 4 bytes of printable ASCII character set It is more efficient than Hex format which converts 1 byte of binary data in to 2 bytes of ASCII hex The sender should send the check sum after transmitting 20 UU encoded lines The length of any UU encoded line should not exceed 61 characters bytes i e it can hold 45 data bytes The receiver should compare it with the check sum of the received bytes If the check sum matches then the receiver should respond with OK lt CR gt lt LF gt to continue further transmission If the check sum does not match the receiver should respond with RESEND lt CR gt lt LF gt In response the sender should retransmit the bytes A description of UU encode is available at http www wotsit org ISP Flow control A software XON XOFF flow control scheme is used to prevent data loss due to buffer overrun When the data arrives rapidly the ASCII control character DC3 stop is sent to stop the flow of data Data flow is resumed by sending the ASCII control character DC1 start The host should also support the same flo
152. d mode for the PWM2 output PWMSEL3 When zero selects single edge controlled mode for PWM3 When one selects double edge controlled mode for the PWMS output PWMSEL4 When zero selects single edge controlled mode for PWM4 When one selects double edge controlled mode for the PWM4 output PWMSEL5 When zero selects single edge controlled mode for PWM5 When one selects double edge controlled mode for the PWM5 output PWMSEL6 When zero selects single edge controlled mode for PWM6 When one selects double edge controlled mode for the PWM6 output 0 Reserved 2 3 4 5 7 1 a reserved bit is not defined Reserved user software should not write ones to reserved bits The value read from Reserved E a reserved bit is not defined Pulse Width Modulator PWM 190 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 PWM Latch Enable Register PWMLER 0xE0014050 ThePWM Latch Enable Register is used to control the update of the PWM Match registers when they are used for PWM generation When software writes to the location of a PWM Match register while the Timer is in PWM mode the value is held in a shadow register When a PWM Match 0 event occurs normally also resetting the timer in PWM mode the contents of shadow registers will be transferred to the actual Match registers if the corresponding bit in the Latch Enable Register has been set At that point the new valu
153. d not write ones to reserved bits The value read from 1 Reserved ma a reserved bit is not defined Assert Acknowledge Clear bit Writing a 1 to this bit clears the AA bit in the IICONSET 2 AAC T register Writing O has no effect IC Interrupt Clear Bit Writing a 1 to this bit clears the SI bit in the IICONSET 3 SIC 2 register Writing O has no effect Reserved user software should not write ones to reserved bits The value read from 4 Reserved _ a reserved bit is not defined Start flag clear bit Writing a 1 to this bit clears the STA bit in the I2CONSET register 5 STAC Eh Writing O has no effect 12C interface disable Writing a 1 to this bit clears the I2EN bit in the I2ZCONSET I2ENC f i register Writing O has no effect 7 Besatvati Reserved user software should not write ones to reserved bits The value read from N a reserved bit is not defined zZ gt Z Z NA NA NA N A A 12C Interface 154 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 12C Status Register IDSTAT 0xE001C004 This is a read only register It contains the status code of the 12C interface The least three bits are always 0 There are 26 possible status codes When the code is F8H there is no relevant information available and the SI bit is not set All other 25 status codes correspond to defined 12C states When any of these states entered SI bit w
154. d output pin TxD1 is held in marking state The four modem inputs CTS DSR RI and DCD are disconnected externally Externally the modem outputs RTS DTR are set inactive Internally the four modem outputs are connected to the four modem inputs As a result of these connections the upper four bits of the UTMSR will be driven by the lower four bits of the U1MCR rather than the four modem inputs in normal mode This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of UTMCR Reserved user software should not write ones to reserved bits The value read from a 7 5 Reserved ne NA reserved bit is not defined Loopback Mode Select UART1 141 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 UART1 Line Status Register U1LSR 0xE0010014 Read Only The U1LSR is a read only register that provides status information on the UART1 Tx and Rx blocks Table 98 UART1 Line Status Register Bit Descriptions U1LSR 0xE0010014 Read Only Function Description 0 U1RBR is empty Receiver Data 1 UTRBR contains valid data Ready RDR U1LSRO is set when the U1RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty 0 Overrun error status is inactive 1 Overrun error status is active Overrun Error The overrun error condition is set as soon as it occurs An U1LSR read clears U1LSR1 OE U1LSR1
155. d to denote a Flash read of instructions beyond the current processor fetch address Flash Memory Banks There are two banks of Flash memory in order to allow two parallel accesses and eliminate delays for sequential accesses Memory Accelerator Module MAM 73 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Flash programming operations are not controlled by the Memory Accelerator Module but are handled as a separate function A boot block sector contains Flash programming algorithms that may be called as part of the application program and a loader that may be run to allow serial programming of the Flash memory The Flash memories are wired so that each sector exists in both banks such that a sector erase operation acts on part of both banks simultaneously In effect the existence of two banks is transparent to the programming functions Memory Address Flash Memory Flash Memory Bus Bank 0 Bank 1 ARM Local Bus Interface Bank Selection Memory Data Figure 18 Simplified Block Diagram of the Memory Accelerator Module Instruction Latches and Data Latches Code and Data accesses are treated separately by the Memory Accelerator Module There are two sets of 128 bit Instruction Latches and 12 bit Comparison Address Latches associated with each Flash Bank One of the two sets called the Branch Trail Buffer holds the d
156. data TC Counter Introduction 24 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 2 LPC2114 2124 2212 2214 Registers Address Ur E Reset Offset Name Description LSB Access Value PWM PWM 0xE001400C PR Prescale 32 bit data R W 0 Register PWM eM Prescale 32 bit data R W Counter Reset MR6 PWM Match Reset Control on 1 R W Register nt on Stop on MR1 PWM PWM Match MRO Register 0 32 bit data mw oo PWM PWM Match MR1 Register 1 92 pitqata Rw o PWM PWM Match MR2 Register 2 2bitdata aw o PWM PWM Match MR3 Register 3 32 bit data CEN PWM PWM Match MR4 Register 4 32bit data CE PWM PWM Match MR5 Register 5 32 bit data LIE PWM PWM Match MR6 Register 6 32 bit data pnw oo oxEoo14046 PWM PWM Control EE ENA6 ENA5 ENA4 ENA3 ENA2 ENA1 sal PCR Register SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 PWM Latch 0xE0014050 Enable LER Register 2 Kc 2 0xE001c000 CONS IC Control IPEN STA STO SI AA R W ET Set Register 2 Register 2 Register Introduction 25 May 03 2004 0xE0014010 0xE0014014 0xE0014018 0xE001401C 0xE0014020 0xE0014024 0xE0014040 0xE0014044 0xE0014048 TU oz a sisisasisisisi a ad Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 2 LPC2114 2124 2212 2214 Registers Address
157. ddressing 33 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 TU GB OxFFFF FFFF AHB Peripherals OxFFEO 0000 AS OxFFDF FFFF Notes AHB section is 128 x 16 kB blocks totaling 2 MB Reserved VPB section is 128 x16 kB blocks totaling 2 MB OxF000 0000 OxEFFF FFFF Reserved 0xE020 0000 OxEO1F FFFF 3 5 GB 2 MB VPB Peripherals 3 5 GB 0xE000 0000 Figure 3 Peripheral Memory Map Figures 3 through 5 show different views of the peripheral address space Both the AHB and VPB peripheral areas are 2 megabyte spaces which are divided up into 128 peripherals Each peripheral space is 16 kilobytes in size This allows simplifying the address decoding for each peripheral All peripheral register addresses are word aligned to 32 bit boundaries regardless of their size This eliminates the need for byte lane mapping hardware that would be required to allow byte 8 bit or half word 16 bit accesses to occur at smaller boundaries An implication of this is that word and half word registers must be accessed all at once For example it is not possible to read or write the upper byte of a word register separately LPC2114 2124 2212 2214 Memory Addressing 34 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Vectored Interrupt Controller OxFFFF F000 4G 4K OxFFFF C000 AHB peripher
158. ductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 PIN DESCRIPTION FOR LPC2114 2124 Pin description for LPC2114 2124 and a brief of corresponding functions are shown in the following table Table 55 Pin description for LPC2114 2124 LOFP64 ENEE Port 0 Port 0 is a 32 bit bi directional I O port with individual direction controls for each bit The operation of port 0 pins depends upon the pin function selected via the Pin Connect Block Pins 26 and 31 of port 0 are not available Note All Port 0 pins excluding those that can be used as A D inputs P0 27 P0 28 P0 29 and P0 30 are functionally 5V tolerant If the A D converter is not used at all pins associated with A D inputs can be used as 5V tolerant digital lO pins See A D Converter chapter for A D input pin voltage considerations P0 0 TxDO Transmitter output for UARTO PWM1 Pulse Width Modulator output 1 RxDO Receiver input for UARTO PWM3 Pulse Width Modulator output 3 EINTO External interrupt 0 input SCL 12C clock input output Open drain output for IPC compliance CAPO 0 Capture input for TIMERO channel 0 SDA 12C data input output Open drain output for IPC compliance MATO 0 Match output for TIMERO channel 0 EINT1 External interrupt 1 input SCKO Serial Clock for SPIO SPI clock output from master or input to slave CAPO0 1 Capture input for TIMERO channel 1 MISOO Master In Slave Out for SPIO Data input to SPI
159. e TMS and TCK signals that define the internal state of the device Test Data In This is the serial data input for the shift register Test Data Output This is the serial data output from the shift register Data is shifted out of the TDO Output a device on the negative edge of the TCK signal nTRST Test Reset The nTRST pin can be used to reset the test logic within the EmbeddedICE logic Returned Test Clock Extra signal added to the JTAG port Required for designs based on ARM7TDMI S processor core Multi ICE Development system from ARM uses this signal to RTCK Output nde He maintain synchronization with targets having slow or widely varying clock frequency For details refer to Multi ICE System Design considerations Application Note 72 ARM DAI 0072A RESET STATE OF MULTIPLEXED PINS On the LPC2114 2124 2212 2214 the pins above are multiplexed with P1 31 26 To have them come up as a Debug port connect a weak bias resistor 4 7 kQ between VSS and the P1 26 RTCK pin To have them come up as GPIO pins do not connect a bias resistor and ensure that any external driver connected to P1 26 RTCK is either driving high or is in high impedance state during Reset EmbeddedICE Logic 242 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 REGISTER DESCRIPTION The Embedded ICE logic contains 16 registers as shown in Table 189 below The ARM7TDMI S debu
160. e interrupt System Control Block 57 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Wakeup Enable one bit of EXTWAKE VPB Read of EXTWAKE EINTi to Wakeup Timer Figure 16 VPB Bus Data 2 Glitch Interrupt Flag geou 209 one bit of EXTINT to VIC EXTMODEi VPB Read of EXTINT Figure 14 External Interrupt Logic System Control Block 58 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 MEMORY MAPPING CONTROL The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x00000000 This allows code running in different memory spaces to have control of the interrupts Memory Mapping Control Register MEMMAP 0xE01FC040 Table 19 MEMMAP Register Address Name Description Memory mapping control Selects whether the ARM interrupt vectors are read 0xE01FC040 MEM from the Flash Boot Block User Flash or RAM Table 20 Memory Mapping Control Register MEMMAP 0xE01FC040 MEMMAP Function Description 00 Boot Loader Mode Interrupt vectors are re mapped to Boot Block 01 User Flash Mode Interrupt vectors are not re mapped and reside in Flash 10 User RAM Mode Interrupt vectors are re mapped to Static RAM 11 User External memory Mode Interrupt vectors are re mapped to external memory Thi
161. e processor and peripheral registers have been initialized to predetermined values External and internal Resets have some small differences An external Reset causes the value of certain pins to be latched to configure the part External circuitry cannot determine when an internal Reset occurs in order to allow setting up those special pins so those latches are not reloaded during an internal Reset Pins that are examined during an external Reset for various purposes are P1 20 TRACESYNC P1 26 RTCK BOOT1 and BOOTO see chapters Pin Configuration on page 93 Pin Connect Block on page 109 and External Memory Controller EMC on page 41 Pin P0 14 see Flash Memory System and Programming on page 217 is exemined by on chip bootloader when this code is executed after reset It is possible for a chip Reset to occur during a Flash programming or erase operation The Flash memory will interrupt the ongoing operation and hold off the completion of Reset to the CPU until internal Flash high voltages have settled External Reset O o Reset to kFlash shell Watchdo p Resetto g PCON PD Reset Power Down d Wakeup Timer Start Count 2 VPB Read Oscillator of PDbit Output Fosc in PCON EINT1 Wakeup m EINT2 Wakeup Write 1 EINT3 Wakeup from VPB EINTO Wakeup Reset Figure 16 Reset Block Diagram including Wakeup Timer System Control Block 69 May 03 2004 Philips Semiconductors Pre
162. ealMonitor enters a panic state No debugging can be performed after RealMonitor enters this state MN B Figure 50 RealMonitor as a state machine A debugger such as the ARM eXtended Debugger AXD or other RealMonitor aware debugger that runs on a host computer can connect to the target to send commands and receive data This communication between host and target is illustrated in Figure 49 The target component of RealMonitor RMTarget communicates with the host component RMHost using the Debug Communications Channel DCC which is a reliable link whose data is carried over the JTAG connection While user application is running RMTarget typically uses IRQs generated by the DCC This means that if user application also wants to use IRQs it must pass any DCC generated interrupts to RealMonitor To allow nonstop debugging the EmbeddedICE RT logic in the processor generates a Prefetch Abort exception when a breakpoint is reached or a Data Abort exception when a watchpoint is hit These exceptions are handled by the RealMonitor exception handlers that inform the user by way of the debugger of the event This allows user application to continue running without stopping the processor RealMonitor considers user application to consist of two parts aforeground application running continuously typically in User System or SVC mode a background application containing interrupt and exception handlers that are triggered by certain ev
163. eceives no internal clocks The processor state and registers peripheral registers and internal SRAM values are preserved throughout Power Down mode and the logic levels of chip pins remain static The Power Down mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks Since all dynamic operation of the chip is suspended Power Down mode reduces chip power consumption to nearly zero Entry to Power Down and Idle modes must be coordinated with program execution Wakeup from Power Down or Idle modes via an interrupt resumes program execution in such a way that no instructions are lost incomplete or repeated Wake up from Power Down mode is discussed further in the description of the Wakeup Timer later in this chapter A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application resulting in additional power savings Register Description The Power Control function contains two registers as shown in Table 29 More detailed descriptions follow Table 29 Power Control Registers Address Description Access Power Control Register This register contains control bits that enable the two reduced power operating modes of the LPC21 14 2124 2212 2214 See Table 30 0xE01FCOCO R W Power Control for Peripherals Register This register contains control bits that OxEO1FCOCA enable and disable indi
164. ed IRQs Table 51 Default Vector Address Register VICDefVectAddr OXFFFFF034 Read Write VICDefVectAddr Function Reset Value When an IRQ service routine reads the Vector Address register VICVectAddr and no IRQ slot responds as described above this address is returned 31 0 0 Vectored Interrupt Controller VIC 84 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Vector Address Register VICVectAddr OxFFFFF030 Read Write When an IRQ interrupt occurs the IRQ service routine can read this register and jump to the value read Table 52 Vector Address Register VICVectAddr OXFFFFF030 Read Write VICVectAddr Function Reset Value If any of the interrupt requests or software interrupts that are assigned to a vectored IRQ slot is are enabled classified as IRQ and asserted reading from this register returns the address in the Vector Address Register for the highest priority such slot lowest numbered such slot Otherwise it returns the address in the Default Vector Address Register Writing to this register does not set the value for future reads from it Rather this register should be written near the end of an ISR to update the priority hardware Protection Enable Register VICProtection OXFFFFF020 Read Write This one bit register controls access to the VIC registers by software running in User mode Table 53 Protection Enable Re
165. egister are ORed with R W OxFFFF F018 the 32 interrupt requests from various peripheral functions VICSoftlntClear Software Interrupt Clear Register This register allows software to clear OxFFFF FO1C one or more bits in the Software Interrupt register ae OxFFFF F020 OxFFFF F030 Protection enable register This register allows limiting access to the VIC VIG EFolecton registers by software running in privileged mode Vector Address Register When an IRQ interrupt occurs the IRQ service wIGvecAdat routine can read this register and jump to the value read Default Vector Address Register This register holds the address of the Interrupt Service routine ISR for non vectored IRQs Dero E034 ViCDefVectAddr Vector address 0 register Vector Address Registers 0 15 hold the VICVectAddr0 addresses of the Interrupt Service routines ISRs for the 16 vectored IRQ slots VICVectAddr2 Vector address 2 register VICVectAddr3 Vector address 3 register VICVectAddr4 Vector address 4 register VICVectAddr5 Vector address 5 register OxFFFF F100 B OxFFFF F104 pr OxFFFF F108 0 OxFFFF F10C Em OxFFFF F110 EN OxFFFF F114 EA OxFFFF F118 NES OxFFFF F11C EN OxFFFF F120 uA OxFFFF F124 VICVectAddr6 Vector address 6 register VICVectAddr7 Vector address 7 register VICVectAddr8 Vector address 8 register VICVectAddr9 Vector address 9 register 3 3 3 3 2 DJ BJ DID Y D o z 2 2 2 sz
166. en data transfers This is not guaranteed when CPHA 0 the signal can remain active SPI Interface 159 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 SCK CPOL 0 NO a A A SCK CPOL 1 E A a ae ATA SSEL TX E Mi CPHA 0 Cycle CPHA 0 B iX2X3X lt X5xXo6x7 Xx s M MOSI CPHA 0 sit XBit2 Xits X Bit4 XBit5 XBite Bit Bro QUE MISO CPHA 0 Bit1 XBit2 XBit3 X Bit4 XBits KBite Bir X Bits MB CPHA 1 Cycle CPHA 1 EB NX 2 a 5x6 xo7Xs W MOSI CPHA 1 I Bits XBit2 X Bio X Bits Bits XBite X Bit 7 X bite NBS MISO CPHA 1 MR Bit 1 XBit2 Bits X Bit 4 Bits XBite XBit7 X Bits Figure 33 SPI Data Transfer Format CPHA 0 and CPHA 1 The data and clock phase relationships are summarized in Table 113 This table summarizes the following for each setting of CPOL and CPHA When the first data bit is driven When all other data bits are driven When data is sampled Table 113 SPI Data To Clock Phase Relationship CPOL And CPHA Settings First Data Driven Other Data Driven Data Sampled CPOL 0 CPHA 0 Prior to first SCK rising edge SCK falling edge SCK rising edge CPOL 0 CPHA 1 First SCK rising edge SCK rising edge SCK falling edge CPOL 1 CPHA 0 Prior to first SCK falling edge SCK rising edge SCK falling edge CPOL 1 CPHA 1 First SCK falling edge S
167. ence of 1 then 0 on CAPn 1 will cause CR1 to be loaded with falling edge the contents of TC When zero this feature is disabled Interrupt on CAPn 1 When one a CR1 load due to a CAPn 1 event will generate an interrupt When event zero this feature is disabled Capture on CAPn 2 When one a sequence of 0 then 1 on CAPn 2 will cause CR2 to be loaded with rising edge the contents of the TC When zero this feature is disabled Capture on CAPn 3 When one a sequence of 0 then 1 on CAPn 3 will cause CR3 to be loaded with rising edge the contents of TC When zero this feature is disabled 0 Capture on CAPn 3 When one a sequence of 1 then 0 on CAPn 3 will cause CR3 to be loaded with falling edge the contents of TC When zero this feature is disabled 11 Interrupt on CAPn 3 When one a CR3 load due to a CAPn 3 event will generate an interrupt When event zero this feature is disabled 2 3 4 5 7 1 Capture on CAPn 2 When one a sequence of 1 then 0 on CAPn 2 will cause CR2 to be loaded with falling edge the contents of TC When zero this feature is disabled Interrupt on CAPn 2 When one a CR2 load due to a CAPn 2 event will generate an interrupt When event zero this feature is disabled TimerO and Timer1 174 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 External Match Register EMR TIMERO TOEMR 0xE000403C TIMER1 T1EMR 0xE000803C The External Match Re
168. ental aborts that could be caused by prefetches that occur when code is executed very near a memory boundary LPC2114 2124 2212 2214 Memory Addressing 40 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 3 EXTERNAL MEMORY CONTROLLER EMC This module is available in LPC2212 and LPC2214 only FEATURES Supports static memory mapped devices including RAM ROM flash burst ROM and some external I O devices Asynchronous page mode read operation in non clocked memory subsystems Asynchronous burst mode read access to burst mode ROM devices Independent configuration for up to four banks each up to 16M Bytes Programmable bus turnaround idle cycles 1 to 16 Programmable read and write WAIT states up to 32 for static RAM devices Programmable initial and subsequent burst read WAIT state for burst ROM devices Programmable write protection Programmable burst mode operation Programmable external data width 8 16 or 32 bits Programmable read byte lane enable control DESCRIPTION The external Static Memory Controller is an AMBA AHB slave module which provides an interface between an AMBA AHB system bus and external off chip memory devices It provides support for up to four independently configurable memory banks simultaneously Each memory bank is capable of supporting SRAM ROM Flash EPROM Burst ROM memory or some external I O devices Each mem
169. ented This interrupt remains valid until cleared by writing a one to bit zero of the Interrupt Location Register ILR O Table 146 Counter Increment Interrupt Register Bits CIIR OXE002400C CIIR Function Description 0 IMSEC When one an increment of the Second value generates an interrupt 1 When one an increment of the Minute value generates an interrupt When one an increment of the Hour value generates an interrupt When one an increment of the Day of Month value generates an interrupt When one an increment of the Day of Week value generates an interrupt When one an increment of the Day of Year value generates an interrupt When one an increment of the Month value generates an interrupt 7 When one an increment of the Year value generates an interrupt Alarm Mask The Alarm Mask Register AMR allows the user to mask any of the alarm registers Table 147 shows the relationship between the bits in the AMR and the alarms For the alarm function every non masked alarm register must match the corresponding time counter for an interrupt to be generated The interrupt is generated only when the counter comparison first changes from no match to match The interrupt is removed when a one is written to the appropriate bit of the Interrupt Location Register ILR If all mask bits are set then the alarm is disabled Real Time Clock 202 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller
170. ents in user system including IRQs or FIQs Data and Prefetch aborts caused by user foreground application This indicates an error in the application being debugged In both cases the host is notified and the user application is stopped Undef exception caused by the undefined instructions in user foreground application This indicates an error in the application being debugged RealMonitor stops the user application until a Go packet is received from the host When one of these exceptions occur that is not handled by user application the following happens RealMonitor 251 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 RealMonitor enters a loop polling the DCC If the DCC read buffer is full control is passed to rm ReceiveData RealMonitor internal function If the DCC write buffer is free control is passed to rm TransmitData RealMonitor internal function If there is nothing else to do the function returns to the caller The ordering of the above comparisons gives reads from the DCC a higher priority than writes to the communications link RealMonitor stops the foreground application Both IRQs and FIQs continue to be serviced if they were enabled by the application at the time the foreground application was stopped RealMonitor 252 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 HOW
171. erals are also allocated a 2 megabyte range of addresses beginning at the 3 5 gigabyte address point Each VPB peripheral is allocated a 16 kilobyte address space within the VPB address space The connection of on chip peripherals to device pins is controlled by a Pin Connection Block This must be configured by software to fit specific application requirements for the use of peripheral functions and pins ARM7TDMI S PROCESSOR The ARM7TDMI S is a general purpose 32 bit microprocessor which offers high performance and very low power consumption The ARM architecture is based on Reduced Instruction Set Computer RISC principles and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers This simplicity results in a high instruction throughput and impressive real time interrupt response from a small and cost effective processor core Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously Typically while one instruction is being executed its successor is being decoded and a third instruction is being fetched from memory The ARM7TDMI S processor also employs a unique architectural strategy known as THUMB which makes it ideally suited to high volume applications with memory restrictions or applications where code density is an issue The key idea behind THUMB is that of a super reduced instruction set Essentially
172. erface enables breakpoints and watch points Interrupt service routines can continue to execute whilst the foreground task is debugged with the on chip RealMonitor software Embedded Trace Macrocell enables non intrusive high speed real time tracing of instruction execution Four eight channel 64 144 pin package 10 bit A D converter with conversion time as low as 2 44 ms Two 32 bit timers with 4 capture and 4 compare channels PWM unit 6 outputs Real Time Clock and Watchdog Multiple serial interfaces including two UARTs 16C550 Fast I C 400 kbits s and two SPIs 60 MHz maximum CPU clock available from programmable on chip Phase Locked Loop Vectored Interrupt Controller with configurable priorities and vector addresses Up to forty six 64 pin and hundred twelve 144 pin package 5 V tolerant general purpose I O pins Up to 12 independent external interrupt pins available EIN and CAP functions On chip crystal oscillator with an operating range of 1 MHz to 30 MHz Two low power modes Idle and Power down Processor wake up from Power down mode via external interrupt Individual enable disable of peripheral functions for power optimization Dual power supply CPU operating voltage range of 1 65V to 1 95V 1 8V 8 3 O power supply range of 3 0V to 3 6V 3 3V 10 Introduction 15 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212
173. erial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer The 12C bus may be used for test and diagnostic purposes APPLICATIONS Interfaces to external 12C standard parts such as serial RAMs LCDs tone generators etc DESCRIPTION A typical 12C bus configuration is shown in Figure 24 Depending on the state of the direction bit R W two types of data transfers are possible on the 12C bus Datatransfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave returns an acknowledge bit after each received byte Data transfer from a slave transmitter to a master receiver The first byte the slave address is transmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all received bytes other than the last byte At the end of the last received byte a not acknowledge is returned The master device generates all of the serial clock pulses and the START and STOP conditions A transfer is ended with a STOP condition or with a repeated START condition Since a repeated START condition is also the beginning of the next serial transfer the 12C bus will not be released This device provides a byte oriented I C interface It has four operating modes master transmi
174. ernal Reset has been de asserted In the case where an external clock source is used in the system as opposed to a crystal connected to the oscillator pins the possibility that there could be little or no delay for oscillator start up must be considered The Wakeup Timer design then ensures that any other required chip functions will be operational prior to the beginning of program execution The LPC2114 2124 2212 2214 does not contain any analog function such as comparators that operate without clocks or any independent clock source such as a dedicated Watchdog oscillator The only remaining functions that can operate in the absence of a clock source are the external interrupts EINTO EINT1 EINT2 and EINT3 When an external interrupt is enabled for wakrup and its selected event occurs an oscillator wakeup cycle is started The actual interrupt if any occurs after the wakeup time expires and is handled by the Vectored Interrupt Controller VIC However the pin multiplexing on the LPC2114 2124 2212 2214 see Pin Configuration on page 93 and Pin Connect Block on page 109 was designed to allow other peripherals to in effect bring the device out of power down mode The following pin function pairings allow interrupts from events relating to UARTO or 1 SPI 0 or 1 or the 12C RxDO EINTO SDA EINT1 SSELO EINT2 RxD1 EINT3 DCD1 EINT1 RI1 EINT2 SSEL1 EINT3 To put the device in power down mode and allow activity on one or more of
175. ero this interrupt is disabled Reset on PWMMR3 ies the PWMTC will be reset if PWMMR3 matches it When zero this feature 1 2 3 4 5 7 10 11 12 13 14 5 Pulse Width Modulator PWM 189 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 134 PWM Match Control Register PWMMCR 0xE0014014 PWMMCR Function Description When one the PWMTC and PWMPC will be stopped and PWMTCR O0 will be set to 0 if PWMMR5 matches the PWMTC When zero this feature is disabled When one an interrupt is generated when PWMMR6 matches the value in the eo EWMMRG PWMTC When zero this interrupt is disabled 17 Stop on PWMMR5 i 19 Reset on PWMMR6 When one the PWMTC will be reset if PWMMR6 matches it When zero this feature is disabled Stop on PWMMR6 When one the PWMTC and PWMPC will be stopped and PWMTCR O will be set to p 0 if PWMMR6 matches the PWMTC When zero this feature is disabled PWM Control Register PWMPCR 0xE001404C The PWM Control Register is used to enable and select the type of each PWM channel The function of each of the bits are shown in Table 135 Table 135 PWM Control Register PWMPCR 0xE001404C Function Description Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined PWMSEL2 When zero selects single edge controlled mode for PWM2 When one selects double edge controlle
176. errupt 0xE0024004 Clock Tick Counter Value from the clock divider Clock Control Register Controls the function of the clock divider RW OxE002400C CIR Counter Increment Interrupt Selects which counters will generate an BW interrupt when they are incremented 0xE0024010 AMR 8 Alarm Mask Register Controls which of the alarm registers are masked 0xE0024014 CTIMEO Consolidated Time Register 0 RO 0xE0024018 CTIME1 Consolidated Time Register 1 RO 0xE002401C CTIME2 Consolidated Time Register 2 RO Interrupt Location ILR 0xE0024000 The Interrupt Location Register is a 2 bit register that specifies which blocks are generating an interrupt see Table 143 Writing a one to the appropriate bit clears the corresponding interrupt Writing a zero has no effect This allows the programmer to read this register and write back the same value to clear only the interrupt that is detected by the read Table 143 Interrupt Location Register Bits ILR 0xE0024000 Function Description When one the Counter Increment Interrupt block generated an interrupt Writing a one to this bit location clears the counter increment interrupt When one the alarm registers generated an interrupt Writing a one to this bit location clears the 1 RTCALF alarm interrupt Clock Tick Counter CTC 0xE0024004 The Clock Tick Counter is read only It can be reset to zero through the Clock Control Register CCR The CTC consists of the bi
177. erter is enabled When 0 the A D is disabled to conserve power Reserved user software should not write ones to reserved bits The value read from a reserved 31 13 Reserved NA bit is not defined POWER CONTROL USAGE NOTES After every reset PCONP register contains the value that enables all interfaces and peripherals controlled by the PCONP to be enabled Therefore apart from proper configuring via peripheral dedicated registers user s application has no need to access the PCONP in order to start using any of the on board peripherals ews DH oa E pul Power saving oriented systems should have 1s in the PCONP register only in positions that match peripherals really used in the application All other bits declared to be Reserved or dedicated to the peripherals not used in the current application must be cleared to 0 System Control Block 68 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 RESET Reset has two sources on the LPC2114 2124 2212 2214 the RESET pin and Watchdog Reset The RESET pin is a Schmitt trigger input pin with an additional glitch filter Assertion of chip Reset by any source starts the Wakeup Timer see Wakeup Timer description later in this chapter causing reset to remain asserted until the external Reset is de asserted the oscillator is running a fixed number of clocks have passed and the Flash controller has completed its initial
178. es how one should process a data transfer with the SPI block when it is set up to be the master This process assumes that any prior data transfer has already completed Set the SPI clock counter register to the desired clock rate Set the SPI control register to the desired settings Write the data to transmitted to the SPI data register This write starts the SPI data transfer Wait for the SPIF bit in the SPI status register to be set to 1 The SPIF bit will be set after the last cycle of the SPI data transfer Bom al Read the SPI status register 6 Read the received data from the SPI data register optional 7 Go to step 3 if more data is required to transmit Note that a read or write of the SPI data register is required in order to clear the SPIF status bit Therefore if the optional read of the SPI data register does not take place a write to this register is required in order to clear the SPIF status bit Slave Operation SPI Interface 161 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 The following sequence describes how one should process a data transfer with the SPI block when it is set up to be a slave This process assumes that any prior data transfer has already completed It is required that the system clock driving the SPI logic be at least 8X faster than the SPI 1 Set the SPI control register to the desired settings 2 Write the data t
179. es several one clock wide enables from the UOTx and UORx blocks Status information from the UOTx and UORx is stored in the UOLSR Control information for the UOTx and UORx is stored in the UOLCR UARTO 130 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 NTXRDY NBAUDOUT RCLK INTERRUPT NRXRDY UOIER UOINTR PA 2 0 UOIIR PSEL PSTB PWRITE PD 7 0 VPB Interface AR MR UARTO Figure 22 UARTO Block Diagram 131 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 UARTO 132 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 11 UART1 FEATURES UARTI is identical to UARTO with the addition of a modem interface 16 byte Receive and Transmit FIFOs Register locations conform to 550 industry standard Receiver FIFO trigger points at 1 4 8 and 14 bytes Built in baud rate generator Standard modem interface signals included PIN DESCRIPTION Table 86 UART1 Pin Description Pin Name Type Description RxD1 Input Serial Input Serial receive data Output Serial Output Serial transmit data Clear To Send Active low signal indicates
180. es will take effect and determine the course of the next PWM cycle Once the transfer of new values has taken place all bits of the LER are automatically cleared Until the corresponding bit in the PWMLER is set and a PWM Match 0 event occurs any value written to the PWM Match registers has no effect on PWM operation For example if PWM2 is configured for double edge operation and is currently running a typical sequence of events for changing the timing would be Write a new value to the PWM Match1 register Write a new value to the PWM Match register Write to the PWMLER setting bits 1 and 2 at the same time The altered values will become effective at the next reset of the timer when a PWM Match 0 event occurs The order of writing the two PWM Match registers is not important since neither value will be used until after the write to PWMLER This insures that both values go into effect at the same time if that is required A single value may be altered in the same way if needed The function of each of the bits in the PWMLER is shown in Table 136 Table 136 PWM Latch Enable Register PWMLER 0xE0014050 PWMLER Function Description Writing a one to this bit allows the last value written to the PWM Match 0 register to be become effective when the timer is next reset by a PWM Match event See the description of the PWM Match Control Register PWMMCR Enable PWM Match 0 Latch Writing a one to this bit allows the
181. escription Reserved user software should not write ones to reserved bits The value read from a reserved Reserved bit is not defined 1 PCTIMO When 1 TIMERO is enabled When 0 TIMERO is disabled to conserve power PCTIM1 When 1 TIMER1 is enabled When 0 TIMER1 is disabled to conserve power PCURTO When 1 UARTO is enabled When 0 UARTO is disabled to conserve power PCURT1 When 1 UART1 is enabled When 0 UART1 is disabled to conserve power PCPWMO When 1 PWMO is enabled When 0 PWMO is disabled to conserve power System Control Block 67 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 32 Power Control for Peripherals Register for LPC2212 2214 PCONP 0xE01FC0C4 PCONP Function Description User software should not write ones to reserved bits The value read from a reserved bit is not defined 7 PCI2C When 1 the I C interface is enabled When 0 the I C interface is disabled to conserve power PCSPIO When 1 the SPIO interface is enabled When 0 the SPIO is disabled to conserve power PCRTC When 1 the RTC is enabled When 0 the RTC is disabled to conserve power Reserved 10 PCSPH When 1 the SPI1 interface is enabled When 0 the SPI1 is disabled to conserve power 11 PCEMC When 1 the External Memory Controller is enabled When 0 the EMC is disabled to conserve 1 power 12 PCAD When 1 the A D conv
182. f interrupts can be delayed as a result Angel as a fully functional target based debugger is therefore too heavyweight to perform as a real time monitor Multi ICE is a hardware debug solution that operates using the EmbeddedICE unit that is built into most ARM processors To perform debug tasks such as accessing memory or the processor registers Multi ICE must place the core into a debug state While the processor is in this state which can be millions of cycles normal program execution is suspended and interrupts cannot be serviced RealMonitor combines features and mechanisms from both Angel and Multi ICE to provide the services and functions that are required In particular it contains both the Multi ICE communication mechanisms the DCC using JTAG and Angel like support for processor context saving and restoring RealMonitor is pre programmed in the on chip Flash memory boot sector When enabled It allows user to observe and debug while parts of application continue to run Refer to section How to Enable RealMonitor for details RealMonitor 249 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 RealMonitor Components As shown in Figure 49 RealMonitor is split in to two functional components RMHost This is located between a debugger and a JTAG unit The RMHost controller RealMonitor dll converts generic Hemote Debug Interface RDI requests from the debugger into
183. f test of the A D Converter can be done by driving these pins as port outputs Note if the A D converter is used signal levels on analog input pins must not be above the level of V34 at any time Otherwise A D converter readings will be invalid If the A D converter is not used in an application then the pins associated with A D inputs can be used as 5V tolerant digital IO pins Van V Power Analog Power and Ground These should be nominally the same voltages as V3 and Vgsp SAP SA but should be isolated to minimize noise and error REGISTER DESCRIPTION The base address of the A D Converter is 0xE003 4000 page 36 The A D Converter includes 2 registers as shown in Table 138 Table 138 A D Registers Name Description Access Reset Value Address A D Control Register The ADCR register must be written to Read Write 0x0000 0001 oxE003 4000 ADCR select the operating mode before A D conversion can occur A D Data Register This register contains the ADC s DONE bit ADDR and when DONE is 1 the 10 bit result of the conversion ea o NA 0XE003 4004 A D Converter 193 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 A D Control Register ADCR 0xE0034000 Table 139 A D Control Register ADCR 0xE0034000 ADCR Name Description Selects which of the Ain3 0 LPC2114 2124 or Ain7 0 LPC2212 2214 pins is are to be sampled and converted Only bits 3 0 s
184. face is responsible for handshaking between a modem peripheral and the UART1 The interrupt interface contains registers U1IER and U1IIR The interrupt interface receives several one clock wide enables from the U1Tx U1Rx and modem blocks Status information from the U1Tx and U1Rx is stored in the U1LSR Control information for the U1Tx and U1Rx is stored in the U1LCR UART1 145 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 NTXRDY TxD1 NBAUDOUT RCLK INTERRUPT NRXRDY U1IER U1INTR U1IIR PA 2 0 PSEL PSTB PWRITE VPB PD 7 0 Interface AR MR Figure 23 UART1 Block Diagram UART1 146 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 12 IC INTERFACE FEATURES Standard 12C compliant bus interface Easy to configure as Master Slave or Master Slave Programmable clocks allow versatile rate control Bidirectional data transfer between masters and slaves Multi master bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one s
185. fic configuration of RealMonitor software programmed in the on chip flash memory of this device Refer to the white paper Heal Time Debug for System on Chip available at htip www arm com support White Papers OpenDocument for background information FEATURES Allows user to establish a debug session to a currently running system without halting or resetting the system Allows user time critical interrupt code to continue executing while other user application code is being debugged APPLICATIONS Real time debugging DESCRIPTION RealMonitor is a lightweight debug monitor that allows interrupts to be serviced while user debug their foreground application It communicates with the host using the DCC Debug Communications Channel which is present in the EmbeddedICE logic RealMonitor provides advantages over the traditional methods for debugging applications in ARM systems The traditional methods include Angel a target based debug monitor e Multi ICE or other JTAG unit and EmbeddedICE logic a hardware based debug solution Although both of these methods provide robust debugging environments neither is suitable as a lightweight real time monitor Angel is designed to load and debug independent applications that can run in a variety of modes and communicate with the debug host using a variety of connections such as a serial port or ethernet Angel is required to save and restore full processor context and the occurrence o
186. for memory bank 1 Read Write 0x2000 FBEF OxFFE00004 BCFG2 Configuration register for memory bank 2 Read Write 0x1000 FBEF OxFFE00008 Configuration register for memory bank 3 Read Write 0x0000 FBEF OxFFEO000C Table 7 External Memory Controller Register Map Each register selects the following options for its memory bank The number of idle clock cycles inserted between between read and write accesses in this bank and between an access in another bank and an access in this bank to avoid bus contention between devices 1 to 17 clocks the length of read accesses except for subsequent reads from a burst ROM 3 to 35 clocks the length of write accesses 3 to 19 clocks whether the bank is write protected whether the bank is 8 16 or 32 bits wide External Memory Controller EMC 42 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Bank Configuration Registers 0 3 BCFGO 3 OXFFE00000 0C This field controls the minimum number of idle CCLK cycles that the EMC maintains 3 0 IDCY between read and write accesses in this bank and between an access in another bank 1111 and an access in this bank to avoid bus contention between devices The number of idle CCLK cycles between such accesses is the value in this field plus 1 Reserved user software should not write ones to reserved bits The value read from a 4 Reserved nic NA reserved bit is not defined A
187. functions available FEATURES Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs or a mix of both types The match registers also allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation An external output for each match register with the following capabilities Setlow on match Sethigh on match Toggle on match Do nothing on match Supports single edge controlled and or double edge controlled PWM outputs Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low Double edge controlled PWM outputs can have either edge occur at any position within a cycle This allows for both positive going and negative going pulses Pulse period and width can be any number of timer counts This allows complete flexibility in the trade off between resolution and repetition rate All PWM outputs will occur at the same repetition rate Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses Software must release new match values before they can become effective May be used as a standard timer if the PWM mode is not enabled A 32 bit Timer Co
188. g architecture is described in detail in ARM7TDMI S rev 4 Technical Reference Manual ARM DDI 02344 published by ARM Limited and is available via Internet at http www arm com Table 189 EmbeddedICE Logic Registers Name Description Address Debug Control Force debug state disable interrupts 00000 Debug Status Status of debug 00001 Debug Comms Control Register Debug communication control register 00100 Debug Comms Data Register Debug communication data register 00101 Watchpoint 0 Address Value Holds watchpoint 0 address value 01000 Watchpoint 0 Address Mask Holds watchpoint 0 address mask 01001 Watchpoint 0 Data Value Holds watchpoint 0 data value 01010 Watchpoint 0 Data Mask Holds watchpoint 0 data Mask 01011 Watchpoint 0 Control Value 9 o Holds watchpoint 0 control value 01100 Watchpoint 0 Control Mask ngon Holds watchpoint 0 control mask 01101 Watchpoint 1 Address Value Holds watchpoint 1 address value 10000 Watchpoint 1 Address Mask Holds watchpoint 1 address mask 10001 Watchpoint 1 Data Value Holds watchpoint 1 data value 10010 Watchpoint 1 Data Mask Holds watchpoint 1 data Mask 10011 Watchpoint 1 Control Value mW Holds watchpoint 1 control value 10100 Watchpoint 1 Control Mask 8 Holds watchpoint 1 control mask 10101 EmbeddedICE Logic 243 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 BLOCK DIAGRAM The block diagram of the debug environment is
189. gister VICProtection OXFFFFF020 Read Write VICProtection Function Reset Value 1 the VIC registers can only be accessed in privileged mode 0 0 VIC registers can be accessed in User or privileged mode 0 Vectored Interrupt Controller VIC 85 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 INTERRUPT SOURCES Table 54 lists the interrupt sources for each peripheral function Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller but may have several internal interrupt flags Individual interrupt flags may also represent more than one interrupt source Table 54 Connection of Interrupt Sources to the Vectored Interrupt Controller Flag s VIC Channel Watchdog Interrupt WDINT Reserved for software interrupts only 1 ARM Core Embedded ICE DogCommRx 2 ARM Core Embedded ICE DogCommTx 3 Match 0 3 MRO MR1 MR2 MR3 TMERO Capture 0 3 CRO CR1 CR2 CR3 Match 0 3 MRO MR1 MR2 MR3 Capture 0 3 CRO CR1 CR2 CR3 Rx Line Status RLS Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CTI Rx Line Status RLS Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CTI Modem Status Interrupt MSI PWMO Match 0 6 MRO MR1 MR2 MR3 MR4 MR5 MR6 C SI state change SPI Interrupt Flag SPIF
190. gister provides both control and status of the external match pins M 0 3 Table 127 External Match Register EMR TIMERO TOEMR 0xE000403C TIMER1 T1EMR 0xE000803C Function Description This bit reflects the state of output MATO 0 MAT 1 0 whether or not this output is connected to its pin When a match occurs for MRO this output of the timer can either toggle go low go high or do nothing Bits EMR 4 5 control the functionality of this output External Match O This bit reflects the state of output MATO 1 MAT1 1 whether or not this output is connected to its pin When a match occurs for MR1 this output of the timer can either toggle go low go high or do nothing Bits EMR 6 7 control the functionality of this output This bit reflects the state of output MATO 2 MAT1 2 whether or not this output is connected to its pin When a match occurs for MR2 this output of the timer can either toggle go low go high or do nothing Bits EMR 8 9 control the functionality of this output This bit reflects the state of output MATO 3 MAT1 3 whether or not this output is connected to its pin When a match occurs for MR3 this output of the timer can either toggle go low go high or do nothing Bits EMR 10 11 control the functionality of this output External Match Determines the functionality of External Match 0 Table 128 shows the encoding of Control 0 these bits External Match Determines the functionality of External Mat
191. h 240 Preliminary User Manual LPC2114 2124 2212 2214 5 May 03 2004 Philips Semiconductors ARM based Microcontroller Preliminary User Manual LPC2114 2124 2212 2214 EmbeddedIlCE Logic ce ccce cl I n e I re 241 Features x a A uA na ORDRE GE Maa atte E RR RD 241 Applications cw ver eee A tee AA Nue by deu ua RUPEE unte uen 241 Description aiu buc A a GRO EE EE Sas wed ate 241 Pin Description mie onm ar eRLCOPEeELR HPLC E VIT uber Wie Ere Ree 242 Reset State of Multiplexed Pins 0 000 cece e eh 242 Register Description ous chess Che Rote ARE Le ae ER EI AE MER REC Ra e 243 Block Diagram 235 vun eR REEREER RON RATE ERE a E UE 244 Embedded Trace Macrocell ecele eere 245 Features ooo tr A a tst uaa Ao rete arae poids en o 245 Applications 2 4 I Toe ee ie eee A ee ee a ee RE ee 245 DescriptiOn suce dioe et E uer pner demus dees eed de b dr ORE eae alk pal 245 Pin Description e ome sate a EIE X ee ende ned urbe 246 Reset State of Multiplexed Pins 0 000 cece cette tte eh 246 Register Description 2 2 00 60 lm e 247 Block Diagram su ea fee eget See ee aa eter EROR OA REESE E 248 RealMonitor uec esp a a ds OS ae ee E EAR 249 Feat les ns ose eed RR E ERUPSN il ido Ne IS MERI aM ES 249 Applications 3 2x e a eee sem als Sensis Sash ER Rue onu pind avenue EUR RE 249 Description UEM 249 How to Enable RealMonitor 0 0 cece RR 253 RealMonitor build op
192. hange detected on modem input CTS Delta CTS 1 State change detected on modem input CTS 0 Set upon state change of input CTS Cleared on an U1MSR read 0 No change detected on modem input DSR Delta DSR 1 State change detected on modem input DSR Set upon state change of input DSR Cleared on an U1MSR read 0 No change detected on modem input RI Trailing Edge RI 1 Low to high transition detected on RI Set upon low to high transition of input RI Cleared on an U1MSR read 0 No change detected on modem input DCD 3 Delta DCD 1 State change detected on modem input DCD Set upon state change of input DCD Cleared on an U1MSR read 4 CTS Clear To Send State Complement of input signal CTS This bit is connected to U1MCR 1 in modem loopback mode 5 DSR Data Set Ready State Complement of input signal DSR This bit is connected to U1MCR 0 in modem loopback mode Ring Indicator State Complement of input RI This bit is connected to U1 MCR 2 in modem loopback mode DCD Data Carrier Detect State Complement of input DCD This bit is connected to U1MCR S3 in modem loopback mode 7 UART1 143 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 UART1 Scratch Pad Register U1SCR 0xE001001C The U1SCR has no effect on the UART1 operation This register can be written and or read at user s discretion There is no provision in the interrupt interface that would indi
193. hapter Pin Connect Block on page 109 and enabled via the VICIntEnable register chapter Vectored Interrupt Controller VIC on page 79 can cause interrupts from the External Interrupt function though of course pins selected for other functions may cause interrupts from those functions Note Software should only change a bit in this register when its interrupt is disabled in VICIntEnable and should write the corresponding 1 to EXTINT before re enabling the interrupt to clear the EXTINT bit that could be set by changing the mode Table 17 External Interrupt Mode Register EXTMODE 0xE01FC148 EXTMODE Function Description EXTMODEO When 0 level sensitivity is selected for EINTO When 1 EINTO is edge sensitive EXTMODE1 When 0 level sensitivity is selected for EINT1 When 1 EINT1 is edge sensitive EXTMODES When 0 level sensitivity is selected for EINT3 When 1 EINTS is edge sensitive Reserved user software should not write ones to reserved bits The value read 7 Reserved NA from a reserved bit is not defined 0 EXTMODE2 When 0 level sensitivity is selected for EINT2 When 1 EINT2 is edge sensitive 4 ay i External Interrupt Polarity Register EXTPOLAR 0xE01FC14C In level sensitive mode the bits in this register select whether the corresponding pin is high or low active In edge sensitive mode they select whether the pin is rising or falling edge sensitive Only pins that are selected for the EINT fun
194. he PSEL bits in PLLCFG is 00 for P 1 01 for P 2 10 for P 4 11 for P 8 see Table 27 Table 27 PLL Divider Values PSEL Bits PLLCFG bits 6 5 value cle MSEL Bits PLLCFG bits 4 0 PLL Example System design asks for Fos 10 MHz and requires cclk 60 MHz Based on these specifications M celk Fose 60 MHz 10 MHz 6 Consequenty M 1 5 will be written as PLLCFG 4 0 Value for P can be derived from P Feco celk 2 using condition that Feco must be in range of 156 MHz to 320 MHz Assuming the lowest allowed frequency for Feco 156 MHz P 156 MHz 2 60 MHz 1 3 The highest Foco frequency criteria produces P 2 67 The only solution for P that satisfies both of these requirements and is listed in Table 27 is P 2 Therefore PLLCFG 6 5 1 will be used System Control Block 65 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 POWER CONTROL The LPC2114 2124 2212 2214 supports two reduced power modes Idle mode and Power Down mode In Idle mode execution of instructions is suspended until either a Reset or interrupt occurs Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution Idle mode eliminates power used by the processor itself memory systems and related controllers and internal buses In Power Down mode the oscillator is shut down and the chip r
195. he UARTO Transmit Holding Register causes the data to be stored in the UARTO transmit FIFO The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available Transmit Holding Register UARTO Divisor Latch LSB Register UODLL 0xE000C000 when DLAB 1 UARTO Divisor Latch MSB Register UODLM 0xE000C004 when DLAB 1 The UARTO Divisor Latch is part of the UARTO Baud Rate Generator and holds the value used to divide the VPB clock pclk in order to produce the baud rate clock which must be 16x the desired baud rate The UODLL and UODLM registers together form a 16 bit divisor where UODLL contains the lower 8 bits of the divisor and UODLM contains the higher 8 bits of the divisor A h0000 value is treated like a h0001 value as division by zero is not allowed The Divisor Latch Access Bit DLAB in UOLCR must be one in order to access the UARTO Divisor Latches Table 77 UARTO Divisor Latch LSB Register UODLL 0xE000C000 when DLAB 1 Function Description Divisor Latch The UARTO Divisor Latch LSB Register along with the UODLM register determines the LSB Register baud rate of the UARTO Function Description Divisor Latch The UARTO Divisor Latch MSB Register along with the UODLL register determines the MSB Register baud rate of the UARTO UARTO 123 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 UARTO Interr
196. he value in PR is reached the TC is incremented 0X00 14010 0xE0014014 PWM Match Register 0 MRO can be enabled through MCR to reset the TC stop both the TC and PC and or generate an interrupt when it matches the TC PAYO In addition a match between MRO and the TC sets all PWM outputs that are in 0xE0014018 single edge mode and sets PWM1 if it is in double edge mode PWM Match Register 1 MR1 can be enabled through MCR to reset the TC PWMMR1 stop both the TC and PC and or generate an interrupt when it matches the TC In addition a match between MR1 and the TC clears PWM1 in either single edge mode or double edge mode and sets PWM2 if it is in double edge mode PWM Match Register 2 MR2 can be enabled through MCR to reset the TC stop both the TC and PC and or generate an interrupt when it matches the TC Era In addition a match between MR2 and the TC clears PWMe in either single UXEDUESUAD edge mode or double edge mode and sets PWM3 if it is in double edge mode PWM Match Register 3 MR3 can be enabled through MCR to reset the TC stop both the TC and PC and or generate an interrupt when it matches the TC MNS In addition a match between MR3 and the TC clears PWMS in either single 0xE0914024 edge mode or double edge mode and sets PWM4 if it is in double edge mode PWM Match Register 4 MR4 can be enabled through MCR to reset the TC stop both the TC and PC and or generate an interrupt when it matches the TC TIS In
197. hen an A D conversion completes It is cleared when this register is read 31 DONE and when the ADCR is written If the ADCR is written while a conversion is still in progress 0 this bit is set and a new conversion is started B This bit is 1 in burst mode if the results of one or more conversions was were lost and 30 OVERUN overwritten before the conversion that produced the result in the LS bits In non FIFO operation this bit is cleared by reading this register These bits always read as zeroes They could be used for expansion of the CHN field in 29 27 3 future compatible A D converters that can convert more channels 26 24 These bits contain the channel from which the LS bits were converted 23 16 These bits always read as zeroes They allow accumulation of successive A D values without i AND masking for at least 256 values without overflow into the CHN field When DONE is 1 this field contains a binary fraction representing the voltage on the Ain pin selected by the SEL field divided by the voltage on the VddA pin Zero in the field indicates that the voltage on the Ain pin was less than equal to or close to that on Vssa while OX3FF 15 6 V V3A indicates that the voltage on Ain was close to equal to or greater than that on V34 X For testing data written to this field is captured in a shift register that is clocked by the A D converter clock The MS bit of this register sources the DINSERI input of the A D converter w
198. hich is used only when TEST1 0 are 10 5 0 These bits always read as zeroes They provide compatible expansion room for future higher resolution A D converters Table 140 A D Data Register ADDR 0xE0034004 OPERATION Hardware Triggered Conversion If the BURST bit in the ADCR is 0 and the START field contains 010 111 the A D converter will start a conversion when a transition occurs on a selected pin or Timer Match signal The choices include conversion on a specified edge of any of 4 Match signals or conversion on a specified edge of either of 2 Capture Match pins The pin state from the selected pad or the selected Match signal XORed with ADCR bit 27 is used in the edge detection logic Clock Generation It is highly desirable that the clock divider for the 4 5 MHz conversion clock be held in a Reset state when the A D converter is idle so that the sampling clock can begin immediately when 01 is written to the START field of the ADCR or the selected edge occurs on the selected signal This feature also saves power particularly if the A D converter is used infrequently Interrupts An interrupt request is asserted to the Vectored Interrupt Controller VIC when the DONE bit is 1 Software can use the Interrupt Enable bit for the A D Converter in the VIC to control whether this assertion results in an interrupt DONE is negated when the ADDR is read Accuracy vs Digital Receiver While the A D converter can be used to meas
199. hould be set to 1 in the 48 or 64 pin package In 7 0 SEL software controlled mode only one of these bits should be 1 In hardware scan mode any value containing 1 to 8 ones 1 to 4 ones in the 48 or 64 pin package can be used All zeroes is equivalent to 0x01 The VPB clock PCLK is divided by this value plus one to produce the clock for the A D 15 8 CLKDIV converter which should be less than or equal to 4 5 MHz Typically software should program i the smallest value in this field that yields a clock of 4 5 MHz or slightly less but in certain cases such as a high impedance analog source a slower clock may be desirable If this bit is O conversions are software controlled and require 11 clocks If this bitis 1 the AD converter does repeated conversions at the rate selected by the CLKS field scanning if 16 BURST necessary through the pins selected by 1s in the SEL field The first conversion after the start corresponds to the least significant 1 in the SEL field then higher numbered 1 bits pins if applicable Repeated conversions can be terminated by clearing this bit but the conversion that s in progress when this bit is cleared will be completed and 4 clocks 3 bits 000211 clocks 10 bits 001 210 clocks 9 bits 111 4 clocks 3 bits 21 PDN 1 the A D converter is operational 0 the A D converter is in power down mode This field selects the number of clocks used for each conversion in Burst mode and the 1
200. hrough a narrow trace port An external Trace Port Analyzer captures the trace information under software debugger control Trace port can broadcast the Instruction trace information Instruction trace or PC trace shows the flow of execution of the processor and provides a list of all the instructions that were executed Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis Trace information generation can be controlled by selecting the trigger resource Trigger resources include address comparators counters and sequencers Since trace information is compressed the software debugger requires a static image of the code being executed Self modifying code can not be traced because of this restriction ETM Configuration The following standard configuration is selected for the ETM macrocell Table 190 ETM Configuration Resource number type Small Pairs of address comparators 1 Data Comparators 0 Data tracing is not supported Memory Map Decoders Counters Sequencer Present External Inputs Embedded Trace Macrocell 245 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 190 ETM Configuration Resource number type Small External Outputs 0 FIFOFULL Present Yes Not wired FIFO depth 10 bytes 1 For details refer to ARM documen
201. ibes the importance of sharing exception handlers between RealMonitor and user application RealMonitor exception handling To function properly RealMonitor must be able to intercept certain interrupts and exceptions Figure 51 illustrates how exceptions can be claimed by RealMonitor itself or shared between RealMonitor and application If user application requires the exception sharing they must provide function such as app IRQDispatch Depending on the nature of the exception this handler can either pass control to the RealMonitor processing routine such as rm irghandler2 claim the exception for the application itself such as app_ RQHandler In a simple case where an application has no exception handlers of its own the application can install the RealMonitor low level exception handlers directly into the vector table of the processor Although the irq handler must get the address of the Vectored Interrupt Controller The easiest way to do this is to write a branch instruction adaress into the vector table where the target of the branch is the start address of the relevant RealMonitor exception handler Reset f Real Monitor supplied exception vector handlers Undef rm_undef_handler rm_prefetchabort_handler rm_dataabort_handler SWI rm irghandler Prefetch Abort Sharing irgs between RealMonitor and User IRQ handler Data Abort rm irghandler2 app irqDispatch
202. icator CTI Identification 001 3 THRE Interrupt UOIERS identifies an interrupt corresponding to the UARTO Rx FIFO All other combinations of UOIER3 1 not listed above are reserved 000 100 101 111 Reserved user software should not write ones to reserved bits The value read from a 5 Reserved d i NA reserved bit is not defined 4 7 6 FIFO Enable These bits are equivalent to UOFCRO Interrupts are handled as described in Table 81 Given the status of UOIIR 3 0 an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt Interrupts are handled as described in Table 81 The UOIIR must be read in order to clear the interrupt prior to exitting the Interrupt Service Routine UARTO 124 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 The UARTO RLS interrupt UOIIR3 1 011 is the highest priority interrupt and is set whenever any one of four error conditions occur on the UARTO Rx input overrun error OE parity error PE framing error FE and break interrupt Bl The UARTO Rx error condition that set the interrupt can be observed via UOLSR4 1 The interrupt is cleared upon an UOLSR read The UARTO RDA interrupt UOIIR3 1 010 shares the second level priority with the CTI interrupt UOIIR3 1 110 The RDA is activated when the UARTO Rx FIFO reaches the trigger level defined in UOFCR7 6 and is reset when the UARTO Rx FIFO de
203. ill be set Refer to Table 3 to Table 6 in 80C51 Family Derivatives 8XC552 562 Overview datasheet available on line at http www semiconductors philips com acrobat various 8XC552_5620VERVIEW_2 paf for a complete list of status codes Table 105 I C Status Register I2STAT 0xE001C004 I2STAT Function Description Status These bits are always 0 12C Data Register IZDAT 0xE001C008 This register contains the data to be transmitted or the data just received The CPU can read and write to this register while it is not in the process of shifting a byte This register can be accessed only when SI bit is set Data in I2DAT remains stable as long as the SI bit is set Data in I2DAT is always shifted from right to left the first bit to be transmitted is the MSB bit 7 and after a byte has been received the first bit of received data is located at the MSB of I2DAT Table 106 I C Data Register I2DAT 0xE001C008 Function Description Data Transmit Receive data bits 12C Slave Address Register I2ADR 0xE001C00C This register is readable and writable and is only used when the 12C is set to slave mode In master mode this register has no effect The LSB of I2ADR is the general call bit When this bit is set the general call address 00h is recognized Table 107 12C Slave Address Register I2ADR 0xE001C00C I2ADR Function Description 0 GC General Call bit Slave mode address 12C Interface 155 Ma
204. ime will be word length X 7 2 X 8 trigger level number of characters X 8 1 RCLKs UOIIR Read if 0010 Third THRE THRE SDUICEROE interrupt or THR write note values 0000 0011 0101 0111 1000 1001 1010 1011 1101 1110 1111 are reserved The UARTO THRE interrupt UOIIR3 1 001 is a third level interrupt and is activated when the UARTO THR FIFO is empty provided certain initialization conditions have been met These initialization conditions are intended to give the UARTO THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start up The initialization conditions implement a one character delay minus the stop bit whenever THRE 1 and there have not been at least two characters in the UOTHR at one time since the last THRE 1 event This delay is provided to give the CPU time to write data to UOTHR without a THRE interrupt to decode and service A THRE interrupt is set immediately if the UARTO THR FIFO has held two or more characters at one time and currently the UOTHR is empty The THRE interrupt is reset when a UOTHR write occurs or a read of the UOIIR occurs and the THRE is the highest interrupt UOIIR3 1 001 UARTO 125 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 UARTO FIFO Control Register UOFCR 0xE000C008 The UOFCR controls the operation of the UARTO Rx and Tx FI
205. in fixed locations Figure 6 shows the on chip memory mapping in the modes defined above The portion of memory that is re mapped to allow interrupt processing in different modes includes the interrupt vector area 32 bytes and an additional 32 bytes for a total of 64 bytes The re mapped code locations overlay addresses 0x0000 0000 through 0x0000 003F A typical user program in the Flash memory can place the entire FIQ handler at address 0x0000 001C without any need to consider memory boundaries The vector contained in the SRAM external memory and Boot Block must contain branches to the actual interrupt handlers or to other instructions that accomplish the branch to the interrupt handlers There are three reasons this configuration was chosen 1 To give the FIQ handler in the Flash memory the advantage of not having to take a memory boundary caused by the re mapping into account 2 Minimize the need to for the SRAM and Boot Block vectors to deal with arbitrary boundaries in the middle of code space 3 To provide space to store constants for jumping beyond the range of single word branch instructions Re mapped memory areas including the Boot Block and interrupt vectors continue to appear in their original location in addition to the re mapped address Details on re mapping and examples can be found in System Control Block on page 49 LPC2114 2124 2212 2214 Memory Addressing 38 May 03 2004 Philips Semiconductors Preliminary User
206. in its latches in time to prevent CPU fetch stalls The method used is to split the Flash memory into two banks each capable of independent accesses Each of the two Flash banks has its own Prefetch Buffer and Branch Trail Buffer The Branch Trail Buffers for the two banks capture two 128 bit lines of Flash data when an Instruction Fetch is not satisfied by either the Prefetch buffer nor Branch Trail buffer for its bank and for which a prefetch has not been initiated Each prefetch buffer captures one 128 bit line of instructions from its Flash bank at the conclusion of a prefetch cycle initiated speculatively by the MAM Each 128 bit value includes four 32 bit ARM instructions or eight 16 bit Thumb instructions During sequential code execution typically one Flash bank contains or is fetching the current instruction and the entire Flash line that contains it The other bank contains or is prefetching the next sequential code line After a code line delivers its last instruction the bank that contained it begins to fetch the next line in that bank Timing of Flash read operations is programmable and is described later in this section as well as in the System Control Block section Branches and other program flow changes cause a break in the sequential flow of instruction fetches described above When a backward branch occurs there is a distinct possibility that a loop is being executed In this case the Branch Trail Buffers may already contain the ta
207. ions can be run at a somewhat slower but more predictable rate if more precise timing is required REGISTER DESCRIPTION All registers regardless of size are on word address boundaries Details of the registers appear in the description of each function Table 37 Summary of System Control Registers Description Address Memory Accelerator Module Control Register Determines the MAM MAMCR functional mode that is to what extent the MAM performance R W OxE01FCO000 enhancements are enabled See Table 38 MAMTIM Memory Accelerator Module Timing control Determines the number of R W 0x07 OxEO1FCOO4 clocks used for Flash memory fetches 1 to 7 processor clocks Reset Value refers to the data stored in used bits only It does not include reserved bits content Memory Accelerator Module MAM 76 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 MAM Control Register MAMCR 0xE01FC000 Two configuration bits select the three MAM operating modes as shown in Table 38 Following Reset MAM functions are disabled Changing the MAM operating mode causes the MAM to invalidate all of the holding latches resulting in new reads of Flash information as required Table 38 MAM Control Register MAMCR 0xE01FC000 Function Description These bits determine the operating mode of the MAM as follows 0 0 MAM functions disabled 0 1 MAM functions partially ena
208. is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full In this case the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost 0 Parity error status is inactive 1 Parity error status is active Parity Error PE When the parity bit of a received character is in the wrong state a parity error occurs An U1LSR read clears U1LSR2 Time of parity error detection is dependent on U1FCRO A parity error is associated with the character being read from the UART1 RBR FIFO 0 Framing error status is inactive 1 Framing error status is active When the stop bit of a received character is a logic 0 a framing error occurs An U1LSR read clears this bit The time of the framing error detection is dependent on U1FCRO A framing error is associated with the character being read from the UART1 RBR FIFO Upon detection of a framing error the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit Framing Error FE 0 Break interrupt status is inactive 1 Break interrupt status is active When RxD1 is held in the spacing state all 0 s for one full character transmission start Break Interrupt data parity stop a break interrupt occurs Once the break condition has been detected Bl the receiver goes idle until RxD1 goes to marking state all 1 s An U1LSR read clears this status bit The time of break detection is depe
209. ister Description usnice peronai i lm e 164 Architecture ui nae REX Eee EEE GR NEUE Gp E ea CUR RC RR Rr ae i ERN a 167 4 May 03 2004 Philips Semiconductors ARM based Microcontroller Timer and Timerl 120 2 a lll clk EET eed 169 Features rex A uA GLEE A ade A REGN RR RE 169 Applications zril Osrex E A u ee d eu ua RUPEE Ene AN 169 Description iis tend Ande ER eg Vat a RU EE REN IDE ER MEA 170 Pin Description steep wet kgs Merde ceeds Peed uberi Aie he ERE 170 Register Description i e cia a EUR RR EVE ES 171 Example Timer Operation o oooccoccccccco mh ren 176 Architecture oe ce OPERI E I A Ier Rea dee that ever d eer ede ds 177 Pulse Width Modulator PWM ooooooooocnnoono eee 179 RII LETT 179 Description 4 002 Sela Pra A ecrire pterea P PRESE 179 Pin Description oes vade eek ec ub eg ROS quss dud a e E dak aly 184 Register Description 5 cece rr hb une 185 A D Converter 2 llle A RETI Eee E a erue 193 Feat res uev A A da ARCU RR RR ER gece pect 193 DescriptlOn nodo do er Er MN on SUPE PAN ud rre E VPE V AM 193 Pim Descriptions oci o att tels ont Ge nonce usce iu eee nt 193 Register Description ooooooooorooror e m hne 193 OPERATION zs y dde ERR o ata pagg E 195 Real Time Clock vpn eee neri Rum mung Rx Rr m RE rini 197 aD 2c X 197 Description EE Em 197 Architecture Adee tes tire AS eer A ar dto pta 198 Register Description enlm br ken e re Ra ree ya PY E hte Ron
210. ister is to detect completion of a data transfer This is indicated by the SPIF bit The remaining bits in the register are exception condition indicators These exceptions will be described later in this section The SPI data register is used to provide the transmit and receive data bytes An internal shift register in the SPI block logic is used for the actual transmission and reception of the serial data Data is written to the SPI data register for the transmit case There is no buffer between the data register and the internal shift register A write to the data register goes directly into the internal shift register Therefore data should only be written to this register when a transmit is not currently in progress Read data is buffered When a transfer is complete the receive data is transferred to a single byte data buffer where it is later read A read of the SPI data register returns the value of the read data buffer The SPI clock counter register controls the clock rate when the SPI block is in master mode This needs to be set prior to a transfer taking place when the SPI block is a master This register has no function when the SPI block is a slave The I Os for this implementation of SPI are standard CMOS I Os The open drain SPI option is not implemented in this design When a device is set up to be a slave its I Os are only active when it is selected by the SSEL signal being active Master Operation The following sequence describ
211. ization The relationship between Reset the oscillator and the Wakeup Timer are shown in Figure 16 The Reset glitch filter allows the processor to ignore external reset pulses that are very short and also determines the minimum duration of RESET that must be asserted in order to guarantee a chip reset Once asserted RESET pin can be deasserted only when crystal oscillator is fully running and an adequate signal is present on the X1 pin of the LPC2114 2124 2212 2214 Assuming that an external crystal is used in the crystal oscillator subsystem after power on the RESET pin should be asserted for 10 ms For all subsequent resets when crystal osillator is already running and stable signal is on the X1 pin the RESET pin needs to be asserted for 300 ns only Speaking in general there are no sequence requirements for powering up the supplies V g Va Viga and Vza However for proper reset handling It is absolutely necessary to have valid voltage supply on Vg pins since on chip Reset circuit and oscillator dedicated hardware are powered by them V3 pins enable microcontroller s interface to the environment via its digital pins Consequently not providing V3 power supply will not affect the reset sequence itself but will prevent microcontroller from communicating with external world When the internal Reset is removed the processor begins executing at address 0 which isinitially the Reset vector mapped from the Boot Block At that point all of th
212. lace It is not necessary for the interrupt to be enabled in the Vectored Interrupt Controller for a wakeup to take place This arrangement allows additional capabilities such as having an external interrupt input wake up the processor from Power Down mode without causing an interrupt simply resuming operation or allowing an interrupt to be enabled during Power Down without waking the processor up if it is asserted eliminating the need to disable the interrupt if the wakeup feature is not desirable in the application System Control Block 55 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 16 External Interrupt Wakeup Register EXTWAKE 0xE01FC144 EXTWAKE Function Description EXTWAKEO When one assertion of EINTO will wake up the processor from Power Down mode EXTWAKE1 When one assertion of EINT1 will wake up the processor from Power Down mode 0 cm EXTWAKE2 When one assertion of EINT2 will wake up the processor from Power Down mode EXTWAKES3 When one assertion of EINT3 will wake up the processor from Power Down mode 4 e Reserved user software should not write ones to reserved bits The value read 7 Reserved NA from a reserved bit is not defined External Interrupt Mode Register EXTMODE 0xE01FC148 The bits in this register select whether each EINT pin is level or edge sensitive Only pins that are selected for the EINT function c
213. lator clock is used directly by the LPC2114 2124 2212 2214 See PLLSTAT register Table 24 Reserved user software should not write ones to reserved bits The value read from a 7 2 Reserved ND a NA reserved bit is not defined The PLL must be set up enabled and Lock established before it may be used as a clock source When switching from the oscillator clock to the PLL output or vice versa internal circuitry synchronizes the operation in order to ensure that glitches are not generated Hardware does not insure that the PLL is locked before it is connected or automatically disconnect the PLL if lock is lost during operation In the event of loss of PLL lock it is likely that the oscillator clock has become unstable and disconnecting the PLL will not remedy the situation PLL Configuration Register PLLCFG 0xE01FC084 The PLLCFG register contains the PLL multiplier and divider values Changes to the PLLCFG register do not take effect until a correct PLL feed sequence has been given see PLL Feed Register PLLFEED 0xE01FC08C description Calculations for the PLL frequency and multiplier and divider values are found in the PLL Frequency Calculation section Table 23 PLL Configuration Register PLLCFG 0xE01FC084 PLLCFG Function Description PLL Multiplier value Supplies the value M in the PLL frequency calculations 59 MSEL4 0 Note For details on selecting the right value for MSEL4 0 see section PLL Frequency Calculatio
214. ld in the spacing state all 0 s for one full character transmission start data parity stop a break interrupt occurs Once the break condition has been detected the receiver goes idle until RxDO goes to marking state all 1 s An UOLSR read clears this status bit The time of break detection is dependent on UOFCRO The break interrupt is associated with the character being read from the UARTO RBR FIFO 0 UOTHR contains valid data 1 UOTHR is empty THRE is set immediately upon detection of an empty UARTO THR and is cleared on a UOTHR write 0 UOTHR and or the UOTSR contains valid data 1 UOTHR and the UOTSR are empty TEMT is set when both UOTHR and UOTSR are empty TEMT is cleared when either the UOTSR or the UOTHR contain valid data 0 UORBR contains no UARTO Rx errors or UOFCRO 0 1 UARTO RBR contains at least one UARTO Rx error UOLSR7 is set when a character with a Rx error such as framing error parity error or break interrupt is loaded into the UORBR This bit is cleared when the UOLSR register is read and there are no subsequent errors in the UARTO FIFO 128 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 UARTO Scratch Pad Register UOSCR 0xE000C01C The UOSCR has no effect on the UARTO operation This register can be written and or read at user s discretion There is no provision in the interrupt interface that would indicate to the host that
215. le OxFFFFF014 Clear Reg 32 bit data XEFFEFOIS Voor SofiWare 32 bit data R W Int Interrupt Reg ago e OE oo ew 32 bit data W ntClear Clear Reg VIC Protection y VICVect Vector OxFFFFF008 32 bit data OxFFFFF034 VICDefv Default Vec 32 bit data R W ectAddr Addr Reg VICVect Vector VICVect Vector i VICVect Vector VICVect Vect Control 1 bit VICVect Vect Control 1 bit VICVect Vect Control 1 bit Introduction 32 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 2 LPC2114 2124 2212 2214 MEMORY ADDRESSING MEMORY MAPS The LPC2114 2124 221 2 2214 incorporates several distinct memory regions shown in the following figures Figure 2 shows the overall map of the entire address space from the user program viewpoint following reset The interrupt vector area supports address re mapping which is described later in this section OxFFFF FFFF AHB Peripherals OxF000 0000 VPB Peripherals 0xE000 0000 0xC000 0000 Reserved for External Memory 0x8000 0000 Boot Block re mapped from On Chip Flash memory Reserved for On Chip Memory 0x4000 3FFF 0x4000 0000 16 kB On Chip Static RAM 0x0004 0000 256 kB On Chip Non Volatile Memory POSERER LPC2212 2214 0x0002 0000 128 kB On Chip Non Volatile Memory 0x0001 FFFF LPC2114 2124 0x0000 0000 Figure 2 System Memory Map LPC2114 2124 2212 2214 Memory A
216. ler LPC2114 2124 2212 2214 Table 56 Pin description for LPC2212 2214 LQFP144 Line ree ee ere MN External memory data line 22 External memory data line 23 External memory data line 24 External memory data line 25 External memory data line 26 While RESET is low together with BOOT1 controls booting and internal operation Internal pullup ensures high state if pin is left unconnected External memory data line 27 While RESET is low together with BOOTO controls booting and internal operation Internal pullup ensures high state if pin is left unconnected BOOT1 0 00 selects 8 bit memory on CSO for boot BOOT1 0 01 selects 16 bit memory on CSO for boot BOOT1 0 10 selects 32 bit memory on CSO for boot BOOT1 0 11 selects Internal Flash memory External memory data line 28 External memory data line 29 External memory data line 30 A D converter input 4 This analog input is always connected to its pin External memory data line 31 A D converter input 5 This analog input is always connected to its pin Port 3 Port 3 is a 32 bit bi directional I O port with individual direction controls for each bit The operation of port 3 pins depends upon the pin function selected via the Pin Connect 89 Block 87 81 80 74 P3 0 71 66 lO Note All Port 3 pins excluding those that can be used as A D inputs P3 28 and P3 29 to 62 56 55 53 48 are functionally 5V tolerant Port 3 pin configured to perform an input functi
217. lf clearing Tx FIFO Reset Writing a logic 1 to U1 FCR2 will clear all bytes in UART1 Tx FIFO and reset the pointer logic This bit is self clearing Reserved user software should not write ones to reserved bits The value read from a Reserved ae A reserved bit is not defined before an interrupt is activated The four trigger levels are defined by the user at compilation allowing the user to tune the trigger levels to the FIFO depths chosen 0 00 trigger level O default 1 character or 0x01h 01 trigger level 1 default 4 characters or 0x04h 10 trigger level 2 default 8 characters or 0x08h 76 Rx Trigger Level 11 trigger level 3 default 14 characters or OxOeh Select These two bits determine how many receiver UART1 FIFO characters must be written UART1 139 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 UART1 Line Control Register U1LCR 0xE001000C The U1LCR determines the format of the data character that is to be transmitted or received Table 96 UART1 Line Control Register Bit Descriptions U1LCR 0xE001000C Function Description 00 5 bit character length Word Length 01 6 bit character length 10 7 bit character length 11 8 bit character length 0 1 stop bit Stop Bit Select 4 Stop bits 1 5 if UILCR 1 0 00 0 Disable parity generation and checking PRUDOERGDIS 1 Enable parity generation and checking 00 Odd parity
218. liminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 VPB DIVIDER The VPB Divider determines the relationship between the processor clock cclk and the clock used by peripheral devices pclk The VPB Divider serves two purposes The first is to provides peripherals with desired pclk via VPB bus so that they can operate at the speed chosen for the ARM processor In order to achieve this the VPB bus may be slowed down to one half or one fourth of the processor clock rate Because the VPB bus must work properly at power up and its timing cannot be altered if it does not work since the VPB divider control registers reside on the VPB bus the default condition at reset is for the VPB bus to run at one quarter speed The second purpose of the VPB Divider is to allow power savings when an application does not require any peripherals to run at the full processor rate The connection of the VPB Divider relative to the oscillator and the processor clock is shown in Figure 17 Because the VPB Divider is connected to the PLL output the PLL remains active if it was running during Idle mode VPBDIV Register VPBDIV 0xE01FC100 The VPB Divider register contains two bits allowing three divider values as shown in Table 34 Table 33 VPBDIV Register Map Address Name Description Access OxE01FC100 VPBDIV Controls the rate of the VPB clock in relation to the processor clock R W Table 34 VPB Divider Register VPBDIV 0xE01F
219. lk for purposes of rate equations etc elsewhere in this document Fs and celk are the same value unless the PLL is running and connected Refer to the PLL description in this chapter for details and frequency limitations Onboard oscillator in LPC2114 2124 2212 2214 can operate in one of two modes slave mode and oscillation mode In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF Cc in Figure 12 drawing a with an amplitude of at least 200 mVrms X2 pin in this configuration can be left not connected If slave mode is selected Fog signal of 50 50 duty cycle can range from 1 MHz to 50 MHz External components and models used in oscillation mode are shown in Figure 12 drawings b and c and in Table 13 Since the feedback resistance is integrated on chip only a crystal and the capacitances Cy and Cy need to be connected externally in case of fundamental mode oscillation the fundamental frequency is represented by L C and Rg Capacitance Cp in Figure 12 drawing c represents the parallel package capacitance and should not be larger than 7 pF Parameters Fc CL Rs and Cp are supplied by the crystal manufacturer Choosing an oscillation mode as an on board oscillator mode of operation limits F clock selection to 1 MHz to 30 MHz LPC2114 2124 LPC2114 2124 LPC2212 2214 LPC2212 2214 x1 x2 x1
220. lling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Rightto make changes Philips Semiconductors reserves the right to make changes in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance When the productis in full production status Production relevant changes will be communicated viaa Customer Product Process Change Notification CPCN Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Contact information Koninklijke Philips Electronics N V 2004 For additional information please visit All rights reserved Printed in U S A http www semiconductors philips com Fax 31 40 27 24825 Date of release 5 04 Document order number 9397 750 13261 Lele make things beti ness S PHILIPS For sales offices addresses send e mail to sales addresses www semiconductors philips com
221. meters Result of the IAP command is returned in the result table pointed to by register r1 The user can reuse the command table for result by passing the same pointer in registers rO and r1 The parameter table should be big enough to hold all the results in case if number of results are more than number of parameters Parameter passing is illustrated in the Figure 46 The number of parameters and results vary according to the IAP command The maximum number of parameters is 5 passed to the Copy RAM to FLASH command The maximum number of results is 2 returned by the Blank check sector s command The command handler sends the status code INVALID COMMAND when an undefined command is received The IAP routine resides at OX7FFFFFFO location and it is thumb code The IAP function could be called in the following way using C Define the IAP location entry point Since the Oth bit of the IAP location is set there will be a change to Thumb instruction set when the program counter branches to this address define IAP LOCATION Ox7ffffff1 Define data structure or pointers to pass IAP command table and result table to the IAP function unsigned long command 5 unsigned long result 2 or unsigned long command unsigned long result command unsigned long Ox result unsigned long Ox Define pointer to function type which takes two parameters and returns void Note the IAP returns the result with the base address of the table residing
222. n on page 64 PLL Divider value Supplies the value P in the PLL frequency calculations 6 9 FOELKS Note For details on selecting the right value for PSEL1 0 see section PLL Frequency Calculation on page 64 Reserved user software should not write ones to reserved bits The value read from a 7 Reserved M NA reserved bit is not defined PLL Status Register PLLSTAT 0xE01FC088 The read only PLLSTAT register provides the actual PLL parameters that are in effect at the time it is read as well as the PLL status PLLSTAT may disagree with values found in PLLCON and PLLCFG because changes to those registers do not take effect until a proper PLL feed has occurred see PLL Feed Register PLLFEED 0xE01FC08C description System Control Block 62 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 24 PLL Status Register PLLSTAT 0xE01FC088 Description Read back for the PLL Enable bit When one the PLL is currently activated When zero the PLL is turned off This bit is automatically cleared when Power Down mode is activated Read back for the PLL Connect bit When PLLC and PLLE are both one the PLL is connected as the clock source for the LPC2114 2124 2212 2214 When either PLLC or PLLE is zero the PLL is bypassed and the oscillator clock is used directly by the LPC2114 2124 2212 2214 This bit is automatically cleared when Power Down mode is activate
223. n PWMPR 1 etc PWM Match Registers PWMMRO PWMMR6 ThePWM Match register values are continuously compared to the PWM Timer Counter value When the two values are equal actions can be triggered automatically The action possibilities are to generate an interrupt reset the PWM Timer Counter or stop the timer Actions are controlled by the settings in the PWMMCR register Pulse Width Modulator PWM 188 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 PWM Match Control Register PWMMCR 0xE0014014 The PWM Match Control Register is used to control what operations are performed when one of the PWM Match Registers matches the PWM Timer Counter The function of each of the bits is shown in Table 134 Table 134 PWM Match Control Register PWMMCR 0xE0014014 er Reset PWMMCR Function Description Value When one an interrupt is generated when PWMMRO matches the value in the 0 Interrupt on FW MMRO PWMTC When zero this interrupt is disabled b Reset on PWMMRO When one the PWMTC will be reset if PWMMRO matches it When zero this feature is disabled Stop on PWMMRO When one the PWMTC and PWMPC will be stopped and PWMTCRIO will be set to P 0 if PWMMRO matches the PWMTC When zero this feature is disabled When one an interrupt is generated when PWMMR 1 matches the value in the interrupto PMMA PWMTC When zero this interrupt is disabled Reset on PWMMR1 ce the PWMTC will be re
224. n a number of pins in parallel It is also possible for example to have 2 pins selected at the same time so that they provide MAT1 3 function in parallel MATO 3 0 Output MATO 0 can be selected on up to 2 pins at the same time MAT1 0 0 MATO 1 can be selected on up to 2 pins at the same time MATO 2 can be selected on up to 2 pins at the same time MATO 3 can be selected on 1 pin MAT1 0 can be selected on 1 pin MAT 1 1 can be selected on 1 pin MAT1 2 can be selected on up to 2 pins at the same time MAT 1 3 can be selected on up to 2 pins at the same time TimerO and Timer1 170 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 REGISTER DESCRIPTION Each Timer contains the registers shown in Table 122 More detailed descriptions follow Table 122 TIMERO and TIMER1 Register Map Reset TIMERO TIMER1 Description Access Value Address amp Address amp Name Name Interrupt Register The IR can be written to clear interrupts The IR can be read to identify which of eight possible interrupt sources are R W 0 die reo 0420008000 pending Timer Control Register The TCR is used to control the Timer Counter functions The Timer Counter can be disabled or reset RAN a e ci through the TCR TC Timer Counter The 32 bit TC is incremented every PR 1 cycles of RW 0xE0004008 0xE0008008 pclk The TC is controlled through the TCR TOTC T1TC Prescale Register The TC is incremen
225. n on the Vectored Interrupt Controller is available in the ARM PrimeCell Vectored Interrupt Controller PL190 documentation Vectored Interrupt Controller VIC 79 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 REGISTER DESCRIPTION The VIC implements the registers shown in Table 40 More detailed descriptions follow Table 40 VIC Register Map Reset Name Description Access Value Address IRQ Status Register This register reads out the state of those interrupt Se requests that are enabled and classified as IRQ RO 9 UE Te OH FIQ Status Requests This register reads out the state of those interrupt Meneses requests that are enabled and classified as FIQ DX EFE Un Raw Interrupt Status Register This register reads out the state of the 32 VICRawintr interrupt requests software interrupts regardless of enabling or OxFFFF F008 classification VICIntSelect Interrupt Select Register This register classifies each of the 32 interrupt R W OxFEFF FOOC requests as contributing to FIQ or IRQ Interrupt Enable Register This register controls which of the 32 interrupt VICIntEnable requests and software interrupts are enabled to contribute to FIQ or R W OxFFFF F010 IRQ VICIntEnCIr Interrupt Enable Clear Register This register allows software to clear W OxFFFF F014 one or more bits in the Interrupt Enable register VICSoftlnt Software Interrupt Register The contents of this r
226. n the 15 bit Fraction Counter These associations are shown in For example if PREFRAC bit 14 is a one representing the fraction 1 2 then half of the cycles counted by the 13 bit counter need to be longer When there is a 1 in the LSB of the Fraction Counter the logic causes every alternate count whenever the LSB of the Fraction Counter 1 to be extended by one pclk evenly distributing the pulse widths Similarly a one in PREFRAC bit 13 representing the fraction 1 4 will cause every fourth cycle whenever the two LSBs of the Fraction Counter 10 counted by the 13 bit counter to be longer Table 157 Prescaler cases where the Integer Counter reload value is incremented PREFRAC Bit Fraction Counter 1 0000 000 10 0000 000 200 0000 0000 0000 ES EE Ed E ER o o o e e o o o o o o o o ce o o Oo Oo o o o o o o o o en o e o o 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0000 0 0 0 0 Real Time Clock 210 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 18 WATCHDOG FEATURES Internally resets chip if not periodically reloaded Debug mode Enabled by software but requires a hardware reset or a Watchdog reset interrupt to be disabled Incorrect Incomplete feed sequence causes reset interrupt if enabled Flag to indicate Watchdog reset Progr
227. n the ARM7TDMI S A JTAG style Test Access Port Controller controls the scan chains In addition to the scan chains the debug architecture uses EmbeddedlCE logic which resides on chip with the ARM7TDMI S core The EmbeddedICE has its own scan chain that is used to insert watchpoints and breakpoints for the ARM7TDMI S core The EmbeddedICE logic consists of two real time watchpoint registers together with a control and status register One or both of the watchpoint registers can be programmed to halt the ARM7TDMI S core Execution is halted when a match occurs between the values programmed into the EmbeddedICE logic and the values currently appearing on the address bus databus and some control signals Any bit can be masked so that its value does not affect the comparison Either watchpoint register can be configured as a watchpoint i e on a data access or a break point i e on an instruction fetch The watchpoints and breakpoints can be combined such that The conditions on both watchpoints must be satisfied before the ARM7TDMI core is stopped The CHAIN functionality requires two consecutive conditions to be satisfied before the core is halted An example of this would be to set the first breakpoint to trigger on an access to a peripheral and the second to trigger on the code segment that performs the task switching Therefore when the breakpoints trigger the information regarding which task has switched out will be ready for examination The wat
228. nable Shadow Register 4 Load Enable Shadow Register 5 Load Enable Shadow Register 6 Load Enable Latch Enable Register M 6 0 Interrupt Stop on Match Reset on Match Clea Match Control Register Interrupt Register Preliminary User Manual LPC2114 2124 2212 2214 Match 0 Match 1 S oH pwmt RE PWMENA1 PWMSEL3 mux HS Qr gt PWM3 RE PWMENA3 PWMENA2 PWMSEL4 PWM4 PWMENA4 ENABLE Timer Control Register Prescale Counter MAXVAL Prescale Register PWMSEL5 mux HS perte M E PWMENA5 R PWMSEL6 PWM6 PWMENA6 PWMENA1 6 PWM Control Register PWMSEL2 6 Note this diagram is intended to clarify the function of the PWM rather than to suggest a specific design implementation Pulse Width Modulator PWM Figure 38 PWM block diagram 181 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 A sample of how PWM values relate to waveform outputs is shown in Figure 39 PWM output logic is shown in Figure 38 that allows selection of either single or double edge controlled PWM outputs via the muxes controlled by the PWMSELn bits The match register selections for various PWM outputs is shown in Table 129 This implementation supports up to N 1 single edge PWM outputs
229. ndent on U1FCRO The break interrupt is associated with the character being read from the UART1 RBR FIFO 0 U1THR contains valid data 1 U1THR is empty THRE is set immediately upon detection of an empty U1THR and is cleared on a U1THR write 0 UTTHR and or the U1TSR contains valid data Transmitter 1 U1THR and the U1TSR are empty Empty TEMT TEMT is set when both THR and TSR are empty TEMT is cleared when either the U1TSR or the U1THR contain valid data 0 U1RBR contains no UART1 Rx errors or U1FCRO 0 1 U1RBR contains at least one UART1 Rx error U1LSR7 is set when a character with a Rx error such as framing error parity error or break interrupt is loaded into the U1RBR This bit is cleared when the U1LSR register is read and there are no subsequent errors in the UART1 FIFO Transmitter Holding Register Empty THRE Error in Rx FIFO RXFE 0 UART1 142 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 UART1 Modem Status Register U1MSR 0x0xE0010018 The U1MSR is a read only register that provides status information on the modem input signals Uf MSR3 0 is cleared on UT MSR read Note that modem signals have no direct affect on UART1 operation they facilitate software implementation of modem signal operations Table 99 UART1 Modem Status Register Bit Descriptions U1MSR 0x0xE0010018 Reset Function Description Value 0 No c
230. nductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Vectored Interrupt Controller VIC 92 May 03 2004 Philips Semiconductors ARM based Microcontroller 7 PIN CONFIGURATION LPC2114 2124 PINOUT P0 21 PWM5 CAP1 3 P0 22 CAPO 0 MATO O P0 23 P1 19 TRACEPKT3 P0 24 Vss V3A P1 18 TRACEPKT2 P0 25 NC P0 27 AINO CAPO 1 MATO 1 P1 17 TRACEPKT1 P0 28 AIN1 CAPO 2 MATO 2 P0 29 AIN2 CAPO 3 MATO 3 P0 30 AINS EINTS CAPO 0 P1 16 TRACEPKTO P1 27 TDO P1 28 TDI P1 29 TCK P0 20 MAT1 3 SSEL1 EINT3 P0 19 MAT1 2 MOSI1 CAP1 2 P0 18 CAP1 3 MISO 1 MAT1 3 P1 30 TMS Preliminary User Manual LPC2114 2124 2212 2214 64 19 60 56 26 27 53 52 29 P0 0 TxDO PWM1 P1 31 TRST 20 P0 1 RxDO PWM3 EINTO 21 P0 2 SCL CAPO 0 22 Va 23 P1 26 RTCK 24 Vss 25 P0 3 SDA MATO 0 EINT1 P0 4 SCKO CAPO 1 P1 25 EXTINO 28 P0 5 MISOO MATO 1 P0 6 MOSIO CAPO 2 30 P0 7 SSELO PWM2 EINT2 31 P1 24 TRACECLK 32 P1 20 TRACESYNC P0 17 CAP1 2 SCK1 MAT1 2 P0 16 EINTO MATO 2 CAPO0 2 P0 15 RIH EINT2 P1 21 PIPESTATO V3 Vss P0 14 DCD1 EINT1 P1 22 PIPESTAT1 P0 13 DTR1 MAT1 1 P0 12 DSR1 MAT1 0 P0 11 CTS1 CAP1 1 P1 23 PIPESTAT2 P0 10 RTS1 CAP1 0 P0 9 RxD1 PWM6O EINT3 P0 8 TxD1 PWM4 Figure 20 LPC2114 2124 64 pin package Pin Configuration 93 May 03 2004 Philips Semicon
231. nel 1 MOSIO Master Out Slave In for SPIO Data output from SPI master or data input to SPI slave CAPO0 2 Capture input for TIMERO channel 2 SSELO Slave Select for SPIO Selects the SPI interface as a slave PWM2 Pulse Width Modulator output 2 EINT2 External interrupt 2 input TxD1 Transmitter output for UART1 PWM4 Pulse Width Modulator output 4 RxD1 Receiver input for UART1 PWM6 Pulse Width Modulator output 6 EINT3 External interrupt 3 input Pin Configuration 99 May 03 2004 Philips Semiconductors ARM based Microcontroller Table 56 Pin description for LPC2212 2214 Preliminary User Manual LPC2114 2124 2212 2214 LQFP144 POE ES MMNNNNEK r Important Pin Configuration Request to Send output for UART1 Capture input for TIMER1 channel 0 Clear to Send input for UART1 Capture input for TIMER1 channel 1 Data Set Ready input for UART1 Match output for TIMER1 channel 0 Data Terminal Ready output for UART1 Match output for TIMER1 channel 1 Data Carrier Detect input for UART1 External interrupt 1 input LOW on this pin while RESET is LOW forces on chip boot loader to take over control of the part after reset LOW on pin P0 14 while RESET is LOW forces on chip boot loader to take over control of the part after reset Ring Indicator input for VART1 External interrupt 2 input External interrupt 0 input Match output for TIMERO channel 2 Capture input for TIMERO channel 2 C
232. ng functions are shown in the following table Pin Description Table 56 Pin description for LPC2212 2214 LQFP144 arr a ml Port 0 Port 0 is a 32 bit bi directional I O port with individual direction controls for each bit 42 49 50 58 59 The operation of port 0 pins depends upon the pin function selected via the Pin Connect 61 68 69 75 7 Block Pins 26 and 31 of Port 0 are not available 6 78 83 85 92 99 100 1 Note All Port 0 pins excluding those that can be used as A D inputs P0 27 P0 28 P0 29 01 121 123 4 and P0 30 are functionally 5V tolerant If the A D converter is not used at all pins 6 8 21 23 25 3 associated with A D inputs can be used as 5V tolerant digital IO pins See A D Converter 2 33 chapter for A D input pin voltage considerations 42 P0 0 TxDO Transmitter output for UARTO PWM1 Pulse Width Modulator output 1 RxDO Receiver input for UARTO PWM3 Pulse Width Modulator output 3 EINTO External interrupt O input SCL 12C clock input output Open drain output for IPC compliance CAPO 0 Capture input for TIMERO channel 0 SDA 12C data input output Open drain output for IPC compliance MATO 0 Match output for TIMERO channel 0 EINT1 External interrupt 1 input SCKO Serial Clock for SPIO SPI clock output from master or input to slave CAPO 1 Capture input for TIMERO channel 1 MISOO Master In Slave Out for SPIO Data input to SPI master or data output from SPI slave MATO 1 Match output for TIMERO chan
233. ning 1 0 Debug with the Watchdog interrupt but no WDRESET 1 1 Operate with the Watchdog interrupt and WDRESET Once the WDEN and or WDRESET bits are set they can not be cleared by software Both flags are cleared by an external reset or a Watchdog timer underflow WDTOF The Watchdog time out flag is set when the Watchdog times out This flag is cleared by software WDINT The Watchdog interrupt flag is set when the Watchdog times out This flag is cleared when any reset occurs Table 159 Watchdog Mode Register WDMOD 0xE0000000 WDMOD Function Description Reset Value 0 WDEN Watchdog interrupt enable bit Set only 0 WDRESET _ Watchdog reset enable bit Set Only 00 WDTOF Watchdog time out flag Reset E WDINT Watchdog interrupt flag Read Only npn Reserved user software should not write ones to reserved bits The value read Reserved es q from a reserved bit is not defined Watchdog Timer Constant Register WDTC 0xE0000004 The WDTC register determines the time out value Every time a feed sequence occurs the WDTC content is reloaded in to the Watchdog timer It s a 32 bit register with 8 LSB set to 1 on reset Writing values below OxFF will cause OxFF to be loaded to the WDTC Thus the minimum time out interval is tpoik x 256 x 4 Function Description Count Watchdog time out interval Watchdog 213 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124
234. nsmitted or received Table 83 UARTO Line Control Register Bit Descriptions UOLCR 0xE000C00C Function Description 00 5 bit character length Word Length 01 6 bit character length 10 7 bit character length 11 8 bit character length 0 1 stop bit Stop Bit Select 2 Stop bits 1 5 if UOLCR 1 0 00 0 Disable parity generation and checking PRUDOERGDIS 1 Enable parity generation and checking 00 Odd parity 01 Even parity Can select 10 Forced 1 stick parity 11 Forced 0 stick parity 0 Disable break transmission Break Control 1 Enable break transmission Output pin UARTO TxD is forced to logic O when UOLCRE is active high 7 Divisor Latch 0 Disable access to Divisor Latches Access Bit 1 Enable access to Divisor Latches UARTO Line Status Register UOLSR 0xE000C014 Read Only The UOLSR is a read only register that provides status information on the UARTO Tx and Rx blocks UARTO 127 May 03 2004 Philips Semiconductors ARM based Microcontroller LPC2114 2124 2212 2214 Preliminary User Manual Table 84 UARTO Line Status Register Bit Descriptions UOLSR 0xE000C014 Read Only Function Description UARTO Receiver Data Ready RDR Overrun Error OE Parity Error PE Framing Error FE Break Interrupt BI Transmitter Holding Register Empty THRE Transmitter Empty Error in Rx FIFO 0 UORBR is empty 1 UORBR contains valid data UOLSR
235. nterface is in master mode and transmits a START condition thereafter If the 12C interface is in slave mode an internal STOP condition is generated but is not transmitted on the bus 12C Interface 153 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 I2EN 12C Interface Enable When I2EN is 1 the I C function is enabled I2EN can be cleared by writing 1 to the I2ENC bit in the 12CONCLR register When I2EN is 0 the C function is disabled Table 103 I C Control Set Register IICONSET 0xE001C000 I2CONSET Function Description Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Reserved user software should not write ones to reserved bits The value read from 1 Reserved iie a reserved bit is not defined AA SI STO STA Z gt Reserved OO 7 Assert acknowledge flag E 3n 12C interrupt flag I2EN 12C interface enable Reserved user software should not write ones to reserved bits The value read from 7 Reserved Ht a reserved bit is not defined 12C Control Clear Register IZCONCLR 0xE001C018 STOP flag START flag NA NA Table 104 12C Control Clear Register IICONCLR 0xE001C018 I2CONCLR Function Description Reserved user software should not write ones to reserved bits The value read from 0 Reserved du a reserved bit is not defined Reserved user software shoul
236. nternal pull up Pin Configuration 96 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 55 Pin description for LPC2114 2124 LQFP64 i IN PIPESTAT2 Pipeline Status bit 2 Standard I O port with internal pull up TRACECLK Trace Clock Standard I O port with internal pull up EXTINO External Trigger Input Standard l O with internal pull up RTCK Returned Test Clock output Extra signal added to the JTAG port Assists debugger synchronization when processor frequency varies Bi directional pin with internal pullup LOW on this pin while RESET is LOW enables pins P1 31 26 to operate as a Debug port after reset Important LOW on pin P1 26 while RESET is LOW enables pins P1 31 26 to operate as a Debug port after reset TDO Test Data out for JTAG interface TDI Test Data in for JTAG interface TCK Test Clock for JTAG interface TMS Test Mode Select for JTAG interface TRST Test Reset for JTAG interface AA A External Reset input A LOW on this pin resets the device causing I O ports and peripherals to RESET 57 take on their default states and processor execution to begin at address 0 TTL with hysteresis 5V tolerant XTAL1 ea i Input to the oscillator circuit and internal clock generator circuits XTAL2 e o Output from the oscillator amplifier 6 18 25 N 42 50 ES Ground OV reference V 59 Analog Ground OV reference This should nominally be the
237. nterrupt Enable Register VICINtEnable OXFFFFF010 Read Write VICIntEnable Function Reset Value When this register is read 1s indicate interrupt requests or software interrupts that are enabled to contribute to FIQ or IRQ When this register is written ones enable interrupt requests or software interrupts to contribute to FIQ or IRQ zeroes have no effect See the VICIntEnClear register Table 45 below for how to disable interrupts Interrupt Enable Clear Register VICIntEnClear OXFFFFF014 Write Only This register allows software to clear one or more bits in the Interrupt Enable register without having to first read it Table 45 Software Interrupt Clear Register VICIntEnClear OxFFFFF014 Write Only VICIntEnClear Function Reset Value 1 writing a 1 clears the corresponding bit in the Interrupt Enable register thus disabling 31 0 interrupts for this request 0 writing a O leaves the corresponding bit in VICIntEnable unchanged Interrupt Select Register VICIntSelect OxFFFFFOOC Read Write This register classifies each of the 32 interrupt requests as contributing to FIQ or IRQ Table 46 Interrupt Select Register VICIntSelect OXFFFFFOOC Read Write VICIntSelect Function Reset Value 1 the interrupt request with this bit number is assigned to the FIQ category 0 the interrupt request with this bit number is assigned to the IRQ category 31 0 0 IRQ Status Register VICIRQStatus
238. o operate in connection with the Match registers A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been PWM Enable set followed by the occurrence of a PWM Match 0 event Note that the PWM Match register that determines the PWM rate PWM Match 0 must be set up prior to the PWM Timer Counter PWMTC 0xE0014008 The 32 bit PWM Timer Counter is incremented when the Prescale Counter reaches its terminal count Unless it is reset before reaching its upper limit the PWMTC will count up through the value OXFFFFFFFF and then wrap back to the value 0x00000000 This event does not cause an interrupt but a Match register can be used to detect an overflow if needed PWM Prescale Register PWMPR 0xE001400C The 32 bit PWM Prescale Register specifies the maximum value for the PWM Prescale Counter PWM Prescale Counter Register PWMPC 0xE0014010 The 32 bit PWM Prescale Counter controls division of pclk by some constant value before it is applied to the PWM Timer Counter This allows control of the relationship of the resolution of the timer versus the maximum time before the timer overflows The PWM Prescale Counter is incremented on every pclk When it reaches the value stored in the PWM Prescale Register the PWM Timer Counter is incremented and the PWM Prescale Counter is reset on the next pclk This causes the PWM TC to increment on every pclk when PWMPR 0 every 2 pclks whe
239. o transmitted to the SPI data register optional Note that this can only be done when a slave SPI transfer is not in progress 3 Wait for the SPIF bit in the SPI status register to be set to 1 The SPIF bit will be set after the last sampling clock edge of the SPI data transfer 4 Read the SPI status register 5 Read the received data from the SPI data register optional 6 Go to step 2 if more data is required to transmit Note that a read or write of the SPI data register is required in order to clear the SPIF status bit Therefore at least one of the optional reads or writes of the SPI data register must take place in order to clear the SPIF status bit Exception Conditions Read Overrun A read overrun occurs when the SPI block internal read buffer contains data that has not been read by the processor and a new transfer has completed The read buffer containing valid data is indicated by the SPIF bit in the status register being active When a transfer completes the SPI block needs to move the received data to the read buffer If the SPIF bit is active the read buffer is full the new receive data will be lost and the read overrun ROVR bit in the status register will be activated Write Collision As stated previously there is no write buffer between the SPI block bus interface and the internal shift register As a result data must not be written to the SPI data register when a SPI data transfer is currently in progress The
240. oller sorted according to the address Access to the specific one can be categorized as either read write read only or write only R W RO and WO respectively Reset Value field refers to the data stored in used accessible bits only It does not include reserved bits content Some registers may contain undetermined data upon reset In this case reset value is categorized as undefined Classification as NA is used in case reset value is not applicable Some registers in RTC are not affected by the chip reset Their reset value is marked as and these registers must be initialized by software if the RTC is enabled Registers in LPC2114 2124 2212 2214 are 8 16 or 32 bits wide For 8 bit registers shown in Table 2 bit residing in the MSB The Most Significant Bit column corresponds to the bit 7 of that register while bit in the LSB The Least Significant Bit column corresponds to the bit 0 of the same register If a register is 16 32 bit wide the bit residing in the top left corner of its description is the bit corresponding to the bit 15 31 of the register while the bit in the bottom right corner corresponds to bit O of this register Examples bit ENA6 in PWMPCR register address 0xE001404C represents the bit at position 14 in this register bits 15 8 7 and 0 in the same register are reserved Bit Stop on MR6 in PWMMCR register 0xE0014014 corresponds to the bit at position 20 bits 31 to 21 of the same register are reserved Un
241. on will use built P3 31 in pull up resistor to set the default input level to high If the A D converter is not used at all 44 41 40 36 35 pins associated with A D inputs can be used as 5V tolerant digital lO pins See A D 30 27 97 96 Converter chapter for A D input pin voltage considerations 89 O P3 0 A0 External memory address line 0 Pin Configuration 104 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 56 Pin description for LPC2212 2214 LQFP144 Deme e e EL External memory address line 1 External memory address line 2 External memory address line 3 External memory address line 4 External memory address line 5 External memory address line 6 External memory address line 7 External memory address line 8 External memory address line 9 External memory address line 10 External memory address line 11 External memory address line 12 External memory address line 13 External memory address line 14 External memory address line 15 External memory address line 16 External memory address line 17 External memory address line 18 External memory address line 19 External memory address line 20 External memory address line 21 External memory address line 22 Pin Configuration 105 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 56 Pin description for LPC221
242. onductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 REGISTER DESCRIPTION All registers regardless of size are on word address boundaries Details of the registers appear in the description of each function Table 12 Summary of System Control Registers Description Access Address External Interrupts Gur eersmenntemese o e EIA EME 0 6 IA ELE mW o foero EXE WW RN FOTO WemnyWanmgGi 0000 O Memory Mapping Control MEMMAP Memory Mapping Control RW 0 0xE01FC040 Phase Locked Loop A A A E A 1 v EI A mo _ ovo Power Control POON Power conri AT A VPB Divider VPBDIV VPB Divider Control RW 0 OxEO1FC100 Reset Value refers to the data stored in used bits only It does not include reserved bits content System Control Block 51 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 CRYSTAL OSCILLATOR While an input signal of 50 50 duty cycle within a frequency range from 1 MHz to 50 MHz can be used by LPC2114 2124 2212 2214 if supplied to its input XTAL1 pin this microcontroller s onboard oscillator circuit supports external crystals in the range of 1 MHz to 30 MHz only If on chip PLL system or boot loader is used input clock frequency is limited to exclusive range of 10 MHz to 25 MHz The oscillator output frequency is called Fog and the ARM processor clock frequency is referred to as cc
243. one possibility for VIC setup VICIntSelect 0x0000 0000 SPIO I2C UART1 and UARTO are IRQ gt bit10 bit9 bit7 and bit6 0 VICIntEnable 0x0000 06C0 SPIO 12C UART1 and UARTO are enabled interrupts gt bit10 bit9 bit 7 and bit6 1 VICDefVectAddr 0x holds address at what routine for servicing non vectored IRQs i e UART1 and 12C starts VICVectAddr0 0x holds address where UARTO IRQ service routine starts VICVectAddrl 0x holds address where SPIO IRQ service routine starts VICVectCntlO 0x0000 0026 interrupt source with index 6 UARTO is enabled as the one with priority O the highest VICVectCnt11 0x0000 002A interrupt source with index 10 SPIO is enabled as the one with priority 1 After any of IRQ requests SPIO 12C UARTO or UART1 is made microcontroller will redirect code execution to the address specified at location 0x00000018 For vectored and non vectored IRQ s the following instruction could be placed at 0x18 LDR pc pc OxFF0 This instruction loads PC with the address that is present in VICVectAddr register In case UARTO request has been made VICVectAddr will be identical to VICVectAddrO while in case SPIO request has been made value from VICVectAddr1 will be found here If neither UARTO nor SPIO have generated IRQ request but UART1 and or 12C were the reason content of VICVectAddr will be identical to VICDefVectAdar Vectored Interrupt Controller VIC 91 May 03 2004 Philips Semico
244. or N 1 2 double edge PWM outputs where N is the number of match registers that are implemented PWM types can be mixed if desired The waveforms below show a single PWM cycle and demonstrate PWM outputs under the following conditions The timer is configured for PWM mode The Match register values are as follows Match 0 is configured to reset the timer counter MRO 100 PWM rate when a match event occurs MR1 41 MR2 78 PWM2 output e Control bits PWMSEL2 and PWMSEL4 are set MR3 53 MR4 27 PWM4 output MR5 65 PWM5 output counter is reset Figure 39 Sample PWM waveforms Table 129 Set and Reset inputs for PWM Flip Flops PWM Single Edge PWM PWMSELn 0 Double Edge PWM PWMSELn 1 Channel Set by Reset by Set by Reset by 1 Match 0 Match 1 Match 0 Match 1 Match 0 Match 2 Match 1 Match 2 Match 0 Match 4 Match 3 Match 4 Match 0 Match 5 Match 4 Match 5 Match 0 Match 6 Match 5 Match 6 Match 0 Match 3 Match 2 Match 3 Notes 1 Identical to single edge mode in this case since Match 0 is the neighboring match register Essentially PWM1 cannot be a double edged output 2 It is generally not advantageous to use PWM channels 3 and 5 for double edge PWM outputs because it would reduce the number of double edge PWM outputs that are possible Using PWM 2 PWM4 and PWM6 for double edge PWM outputs provides the most pairings Pulse Width Modulator PWM 182 May 03 2004 Philips Semicond
245. ored in U1MSR6 State change information is stored in Uf MSR2 and is a source for a priority level 4 interrupt if enabled U1IER3 1 RTS1 Output Request To Send Active low signal indicates that the UART1 would like to transmit data to the P external modem The complement value of this signal is stored in U1MCR1 RI Input UART1 133 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 REGISTER DESCRIPTION Table 87 UART1 Register Map Description Receiver Buffer READ DATA Register Transmit Holding WRITE DATA Register Interrupt Enable Register Interrupt ID U1IIR FIFOs Enabled 0x01 0xE0010008 FIFO U1FCR Control Rx Trigger 0xE0010008 Register Enable Modem Status Interrupt Enable Rx Line Status Interrupt Enable THRE Interrupt Available Interrupt Line Control 7 Word Length Register Select 0xE001000C 0xE0010010 Modem Control RTS DTR Register Register Modem ili Delta Delta Delta re mr Ey ern Register Scratch Pad U1SCR MSB LSB R EN 0xE001001C UTDLL Por Latch usa LSB EN 0xE0010000 MSB LSB EN B DLAB 1 Divisor Latch 0xE0010004 MSB U1TDLM DLAB 1 U1MCR U1MSR Reset Value refers to the data stored in used bits only It does not include reserved bits content UART1 contains twelve 8 bit registers as shown in Table 87 The Divisor Latch Access Bit DLAB is contained in U1LCR7 and enables access to the Divi
246. ory bank may be 8 16 or 32 bits wide This module is available in LPC2212 and LPC2214 only Since this 144 pin package pins out address lines A 23 0 the decoding among the four banks uses address bits A 25 24 The native location of the four banks is at the start of the External Memory area identified in Figure 2 on page 33 but Bank 0 can be used for initial booting under control of the state of the BOOT 1 0 pins Bank Address Range Configuration Register 0 8000 0000 80FF FFFF BCFGO 8100 0000 81FF FFFF BCFG1 8200 0000 82FF FFFF BCFG2 8300 0000 83FF FFFF BCFG3 Table 5 Address Ranges of External Memory Banks LPC2212 2214 only External Memory Controller EMC 41 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 PIN DESCRIPTION Pin Name Pin Description D 31 0 External memory data lines A 23 0 Output External memory address lines BLS 3 0 Output Low active Byte Lane Select signals Output Low active Write Enable signal Output Low active Chip Select signals Table 6 External Memory Controller Pin Description Output Low active Output Enable signal E REGISTER DESCRIPTION The external memory controller contains 4 registers as shown in Table 7 Reset Value Name Description Access see Table 9 Address BCFGO Configuration register for memory bank 0 Read Write 0x0000 FBEF OxFFE00000 BCFG1 Configuration register
247. otes the priority and source of a pending interrupt The interrupts are frozen during an U1IIR access If an interrupt occurs during an U1IIR access the interrupt is recorded for the next U1IIR access Table 93 UART1 Interrupt Identification Register Bit Descriptions IIR 0xE0010008 Read Only Function Description 0 At least one interrupt is pending Interrupt 1 No pending interrupts Pending Note that U1IIRO is active low The pending interrupt can be determined by evaluating U1IIR3 1 011 1 Receive Line Status RLS 010 2a Receive Data Available RDA 110 2b Character Time out Indicator CTI 001 3 THRE Interrupt 000 4 Modem Interrupt U1IER3 identifies an interrupt corresponding to the UART1 Rx FIFO and modem signals All other combinations of U1IER3 1 not listed above are reserved 100 101 111 Interrupt Identification Reserved user software should not write ones to reserved bits The value read from a 5 Reserved s NA reserved bit is not defined 4 7 6 FIFO Enable These bits are equivalent to U1FCRO Interrupts are handled as described in Table 94 Given the status of U1IIR 3 0 an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt The U1IIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine The UART1 RLS interrupt U11IR3 12011 is the highest priority interrupt and is set whenever any one of f
248. our error conditions occur on the UART1Rx input overrun error OE parity error PE framing error FE and break interrupt BI The UART1 Rx error condition that set the interrupt can be observed via U1LSR4 1 The interrupt is cleared upon an U1LSR read The UART1 RDA interrupt U11IR3 12010 shares the second level priority with the CTI interrupt U11IR3 12110 The RDA is activated when the UART1 Rx FIFO reaches the trigger level defined in U1FCR7 6 and is reset when the UART1 Rx FIFO depth falls below the trigger level When the RDA interrupt goes active the CPU can read a block of data defined by the trigger level The CTI interrupt U11IR3 12110 is a second level interrupt and is set when the UART1 Rx FIFO contains at least one character and no UART1 Rx FIFO activity has occurred in 3 5 to 4 5 character times Any UART1 Rx FIFO activity read or write of UART1 RSR will clear the interrupt This interrupt is intended to flush the UART1 RBR after a message has been received that is not a multiple of the trigger level size For example if a peripheral wished to send a 105 character message and the trigger level was 10 characters the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts depending on the service routine resulting in the transfer of the remaining 5 characters UART1 137 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2
249. patent to use the components in the 12C system provided the system conforms to the 12C specifications defined by Philips This specification can be ordered using the code 9398 393 40011 Definitions Short form specification The data in a short form specification is extracted from a full data sheet with the same type number and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 60134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or se
250. periodically serviced care must be taken to avoid problems due to the interaction of these features First the BOOT1 and or BOOTO pin s must be biased to ground using pulldown resistors not transistors driven from RESET low because RESET is not driven low during a Watchdog Reset Second if either or both of the BOOT1 0 pins are used as inputs in the application the application designer must ensure that the external driver will not be enabled during an internal Reset generated by the Watchdog Timer One way to do this is to use one of the CS3 0 outputs to enable the driver If these two conditions cannot be met an external Watchdog facility can be used Watchdog 214 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Watchdog 215 May 03 2004 Philips Semiconductors ARM based Microcontroller BLOCK DIAGRAM The block diagram of the Watchdog is shown below in the Figure 42 FEED Preliminary User Manual LPC2114 2124 2212 2214 FEED ERROR SEQUENCE 1 WDFEED LEEED OK WDTV CURRENT WD REGISTER TIMER COUNT SHADOW BIT ENABLE COUNT E WDMOD REGISTER Counter is enabled only when the WDEN bit is set and a valid feed sequence is done WDEN and WDRESET are sticky bits Once set they can t be cleared until the Watchdog underflows or an external reset occurs WDEN 2 WDTOF WDINT WDRESET INTERRUPT
251. pherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt s being enabled Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined Selection of a single function on a port pin completely excludes all other functions otherwise available on the same pin The only partial exception from the above rule of exclusion is the case of inputs to the A D converter Regardless of the function that is selected for the port pin that also hosts the A D input this A D input can be read at any time and variations of the voltage level on this pin will be reflected in the A D readings However valid analog reading s can be obtained if and only if the function of an analog input is selected Only in this case proper interface circuit is active in between the physical pin and the A D module In all other cases a part of digital logic necessary for the digital function to be performed will be active and will disrupt proper behavior of the A D REGISTER DESCRIPTION The Pin Control Module contains 2 registers as shown in Table 57 below Table 57 Pin Connect Block Register Map Name Description Access Reset Value Address PINSELO Pin function select register O Read Write 0x0000 0000 0xE002C000 PINSEL1 Pin function select register 1 Read Write 0x1540 0000 0xE002C004 See Table 63 PINSEL2 Pin function select register 2 Read Write and Table
252. philips com acrobat various 8XC552_5620VERVIEW_2 paf for the status codes and actions 12C Interface 150 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 e Slave Address W DATA A DATA A A P RS S o Um A Data Transferred A n Bytes Acknowledge 1 Read Acknowledge SDA low From Master to Slave Not Acknowledge SDA high From Slave to Master START condition STOP Condition S Repeated START Condition Figure 30 Format of slave receiver mode Slave Transmitter Mode The first byte is received and handled as in the slave receiver mode However in this mode the direction bit will indicate that the transfer direction is reversed Serial data is transmitted via SDA while the serial clock is input through SCL START and STOP conditions are recognized as the beginning and end of a serial transfer In a given application lc may operate as a master and as a slave In the slave mode the 12C hardware looks for its own slave address and the general call address If one of these addresses is detected an interrupt is requested When the microcontroller wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted If bus arbitration is lost in the master mode I C switches to the slave mode immediately and can detec
253. ponding bit in the PWMIR will be high Otherwise the bit will be low Writing a logic one to the corresponding IR bit will reset the interrupt Writing a zero has no effect Table 132 PWM Interrupt Register PWMIR 0xE0014000 Function Description PWMMRO Interrupt Interrupt flag for PWM match channel 0 1 7 s De EE MN D E ERO Pulse Width Modulator PWM 187 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 PWM Timer Control Register PWMTCR 0xE0014004 The PWM Timer Control Register PWMTCR is used to control the operation of the PWM Timer Counter The function of each of the bits is shown in Table 133 Table 133 PWM Timer Control Register PWMTCR 0xE0014004 PWMTCR Function Description When one the PWM Timer Counter and PWM Prescale Counter are enabled for Counter Enable counting When zero the counters are disabled When one the PWM Timer Counter and the PWM Prescale Counter are Counter Reset synchronously reset on the next positive edge of pclk The counters remain reset until TCR 1 is returned to zero Reserved user software should not write ones to reserved bits The value read from Reserved Tod NA a reserved bit is not defined PWM being enabled Otherwise a Match event will not occur to cause shadow register contents to become effective When one PWM mode is enabled PWM mode causes shadow registers t
254. pth falls below the trigger level When the RDA interrupt goes active the CPU can read a block of data defined by the trigger level The CTI interrupt UOIIR3 12110 is a second level interrupt and is set when the UARTO Rx FIFO contains at least one character and no UARTO Rx FIFO activity has occurred in 3 5 to 4 5 character times Any UARTO Rx FIFO activity read or write of UARTO RSR will clear the interrupt This interrupt is intended to flush the UARTO RBR after a message has been received that is not a multiple of the trigger level size For example if a peripheral wished to send a 105 character message and the trigger level was 10 characters the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts depending on the service routine resulting in the transfer of the remaining 5 characters Table 81 UARTO Interrupt Handling Interrupt Interrupt Interrupt UOIIR 3 0 Priority Type Source Reset 0001 none 0110 Highest P E OE or PE or FE or BI UOLSR Read UORBR Read or 0100 Second a Data Rx data available or trigger level reached in FIFO UOFCRO 1 VARTO FIFO Available drops below trigger level Minimum of one character in the Rx FIFO and no character input or removed during a time period depending on how many Character Time characters are in FIFO and what the trigger level is set at 3 5 1100 Second TRAS to 4 5 character times UO RBR Read out Indication The exact t
255. r Increment Interrupt Generator Figure 40 RTC block diagram Alarm Registers Alarm Mask Register The RTC includes a number of registers The address space is split into four sections by functionality The first eight addresses are the Miscellaneous Register Group The second set of eight locations are the Time Counter Group The third set of eight locations contain the Alarm Register Group The remaining registers control the Reference Clock Divider The Real Time Clock includes the register shown in Table 141 Detailed descriptions of the registers follow Real Time Clock 198 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 141 Real Time Clock Register Map Description R Address Interrupt Location Register 0xE0024000 ACA AA E CC 0177 00 ZA PEC FONERA RET AREN C O E E CTIME2 32 Consolidated Time Register 2 0xE002401C EET HE MN 6 Minutes Register Minutes Minutes Register RW RW oxE0024024 WoUR s Rows Rene Sn pow o paoman f 7 E sov ay fear Reiter mom Nets eer Yo YEAR 12 Years Register R W 0xE002403C ereas cnp eee I SC Auov NamvwawtrbardYmr IZA ALYEAR 12 Alarm value for Year R W 0xE002407C PREFRAC 75 Prescae vane anao RW 9 ZA Registers in the RTC other than those that are part of the Prescaler are not affected by chip Reset These registers must be initialized
256. real monitor is used in interrupt mode RM_EXECUTECODE_SIZE NA RealMonitor 259 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 execute code buffer size Also refer to RM OPT EXECUTECODE option RM_OPT_GATHER_STATISTICS FALSE This option enables or disables the code for gathering statistics about the internal operation of RealMonitor RM_DEBUG FALSE This option enables or disables additional debugging and error checking code in RealMonitor RM_OPT_BUILDIDENTIFIER FALSE This option determines whether a build identifier is built into the capabilities table of RMTarget Capabilities table is stored in ROM RM_OPT_SDM_INFO FALSE SDM gives additional information about application board and processor to debug tools RM_OPT_MEMORYMAP FALSE This option determines whether a memory map of the board is built into the target and made available through the capabilities table RM_OPT_USE_INTERRUPTS TRUE This option specifies whether RMTarget is built for interrupt driven mode or polled mode RM_FIFOSIZE NA This option specifies the size in words of the data logging FIFO buffer CHAIN_VECTORS FALSE This option allows RMTarget to support vector chaining through HAL ARM HW abstraction API RealMonitor 260 May 03 2004 Philips Semiconductors Preliminary User manual LPC2114 2124 2212 2214 Purchase of Philips 12C components conveys a license under the Philips 12C
257. requirements Access WST setting cycle Max frequency WST gt 0 round up to integer Required memory access time 2 WST1 tram 20ns Standard fma WST1 gt 2 tram lt tcvc 22 WST1 20ns Read tram 20ns tcvc 14 WST2 twrite tcyc 5ns Standard max lt WST2 gt twnirE lt teyc 1 WST2 5ns Write tram 5ns tcvc External Memory Controller EMC 47 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 External Memory Controller EMC 48 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 4 SYSTEM CONTROL BLOCK SUMMARY OF SYSTEM CONTROL BLOCK FUNCTIONS The System Control Block includes several system features and control registers for a number of functions that are not related to specific peripheral devices These include Crystal Oscillator External Interrupt Inputs Memory Mapping Control PLL Power Control Reset VPB Divider Wakeup Timer Each type of function has its own register s if any are required and unneeded bits are defined as reserved in order to allow future expansion Unrelated functions never share the same register addresses PIN DESCRIPTION Table 11 shows pins that are associated with System Control block functions Table 11 Pin summary
258. ress space between On Chip Static RAM and External Memory Labelled Reserved for On Chip Memory in Figure 2 This is an address range from 0x4000 3FFF to Ox7FFF DFFF External Memory other than that provided by the EMC in the 144 pin package Reserved regions of the AHB and VPB spaces See Figure 3 Unassigned AHB peripheral spaces See Figure 4 Unassigned VPB peripheral spaces See Figure 5 For these areas both attempted data access and instruction fetch generate an exception In addition a Prefetch Abort exception is generated for any instruction fetch that maps to an AHB or VPB peripheral address Within the address space of an existing VPB peripheral a data abort exception is not generated in response to an access to an undefined address Address decoding within each peripheral is limited to that needed to distinguish defined registers within the peripheral itself For example an access to address OXE000D000 an undefined address within the UARTO space may result in an access to the register defined at address OxXE000C000 Details of such address aliasing within a peripheral space are not defined in the LPC2114 2124 2212 2214 documentation and are not a supported feature Note that the ARM core stores the Prefetch Abort flag along with the associated instruction which will be meaningless in the pipeline and processes the abort only if an attempt is made to execute the instruction fetched from the illegal address This prevents accid
259. return to the interrupted instruction by using the following code MSR cpsr c 10x52 Disable irg move to IRQ mode RealMonitor 257 Non vectored app irqDispatch mentioned in this example User can setup May 03 2004 Philips Semiconductors ARM based Microcontroller MSR spsr r12 STMFD sp r0 LDR r0 STR El SUBS pc VICBaseAddr rO 4VICVectAddrOffset LDMFD sp fr12 r14 r0 r14 4 Preliminary User Manual LPC2114 2124 2212 2214 Restore SPSR from r12 Acknowledge Non Vectored irq has finished Restore registers Return to the interrupted instruction user interrupt did not happen so call rm irghandler2 This handler is not aware of the VIC interrupt priority hardware so trick rm_irghandler2 to return here STMFD sp ip pc LDR pc rm irghandler2 rm irqhandler2 returns here MSR cpsr c 0x52 MSR spsr STMFD sp LDR r0 VICBaseAddr STR r1 r0 VICVectAddrOffset LDMFD sp SUBS pc END RealMonitor r12 r0 P odiri2 rli4 r0 r14 4 Disable irq move to IRQ mode Restore SPSR from r12 Acknowledge Non Vectored irq has finished Restore registers Return to the interrupted instruction 258 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 REALMONITOR BUILD OPTIONS RealMonitor was built with the following options RM OPT DATALOGGING FALSE
260. rget instruction If so execution continues without the need for a Flash read cycle For a forward branch there is also a chance that the new address is already contained in one of the Prefetch Buffers If it is the branch is again taken with no delay When a branch outside the contents of the Branch Trail and Prefetch buffers is taken one Flash Access cycle is needed to load the Branch Trail buffers Subsequently there will typically be no further fetch delays until another such Instruction Miss occurs The Flash memory controller detects data accesses to the Flash memory and uses a separate buffer to store the results in a manner similar to that used during code fetches This allows faster access to data if itis accessed sequentially A single line buffer is provided for data accesses as opposed to the two buffers per Flash bank that are provided for code accesses There is no prefetch function for data accesses Memory Accelerator Module Blocks The Memory Accelerator Module is divided into several functional blocks A Flash Address Latch for each bank An Incrementer function is associated with the Bank O Flash Address latch Two Flash Memory Banks Instruction Latches Data Latches Address Comparison latches Wait logic Figure 18 shows a simplified block diagram of the Memory Accelerator Module data paths In the following descriptions the term fetch applies to an explicit Flash read request from the ARM prefetch is use
261. riting zeroes has no effect d des eiu E Read A OD OxE0028008 0xE0028018 0xE0028028 oxE0028038 S Ie Hay controis tne Write IOODIR IO1DIR IO2DIR IO3DIR direction of each port pin GPIO Port Output clear register This register controls the state of output btc ihn Ped write 9900 0xE002800C 0xE002801C 0xE002802C 0xE002803C T Only IOOCLR IO1CLR IO2CLR IOSCLR clears the corresponding bits in the IOSET register Writing zeroes has no effect GPIO 116 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 GPIO Pin Value Register IOOPIN 0xE0028000 IO1PIN 0xE0028010 IO2PIN 0xE0028020 IO3PIN 0xE0028030 This register provides the value of the GPIO pins Register s value reflects any outside world influence on the GPIO configured pins only Monitoring of non GPIO configured port pins using IOPIN register will not be valid since activities on non GPIO configured pins are not indicated in the IOPIN register Selection of a single function on a port pin completely excludes all other functions otherwise available on the same pin The only partial exception from the above rule of exclusion is in the case of inputs to the A D converter Regardless of the function that is selected for the port pin that also hosts the A D input this A D input can be read at any time and variations of the voltage level on this pin will be reflected in the A D readings Ho
262. rning then it might create problems due to difference in the C compiler implementation from different vendors The suggested parameter passing scheme reduces such risk The flash memory is not accessible during a write or erase operation IAP commands which results in a flash write erase operation use 32 bytes of space in the top portion of the on chip RAM for execution The user program should not be use this space if IAP flash programming is permitted in the application Table 179 IAP Command Summary IAP Command Command Code Described in Prepare sector s for write operation 50 Table 180 Flash Memory System and Programming 235 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Command Code Command Parameter 0 parameter table Parameter 1 ARM Register rO ARM Register r1 Parameter n Status Code Result 0 Command result table Result 1 Result n Figure 46 IAP Parameter passing Prepare sector s for write operation This command makes flash write erase operation a two step process Table 180 IAP Prepare sector s for write operation command description Command Prepare sector s for write operation Command code 50 Input Paramo Start Sector Number Param1 End Sector Number Should be greater than or equal to start sector number CMD SUCCESS Status Code BUSY INVALID SECTOR
263. rol DLAB Set Stick pariy Parity Word Length Ryw Break Parity Enable Select Register Select UO Line Rx 0xE000C014 UOLSR Status FIFO TEMT THRE 0x60 Register Error oxEo00co1c UoscR UO Scratch 8 bit data Pad sd UART1 UO Receiver UORBR un Register 0xE000C000 Introduction 23 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 LSB Access 8 bit data Table 2 LPC2114 2124 2212 2214 Registers Address Offset Name Description U1 Receiver Buffer Register U1RBR DLAB 0 U1DLL Pg Divisor DLAB 1 Latch Pg U1 Interrupt EE Enable 0xE0010004 Register is U1 Divisor 111 9 edel FIFOs Enabled Enabled ms uR2 IIR1 0x01 ID Register 0xE0010008 U1 FIFO U1FCR Control Rx Trigger oe WO Register Enable U1 Line 0xE001000C U1LCR Control LAB 99 Sick i Word Length pyw Break Parity Select Register Select 1T ELS oe L m aco DLAB 0 9 Register U1 Modem 0xE0010010 Mcd Control BL RTS DTR Rw Register U1 Line Rx 0xE0010014 U1LSR Status FIFO TEMT THRE 0x60 Register Error 0xE001001C Utscn Y Scratch 8 bit data Pad Register U1 Modem Trailing U1 Delta Delta Delta 0xE0010018 MSR Status DCD DSR CTS DCD Edge DSR CTS Register RI PWM PWM Int Int Int 0xE0014000 EM Interrupt IR Register MR3 MR2 MRI ES Int Int Int ES PWM Timer PWM PWM CTR CTR egister oxeoo14008 PWM PWM Timer 32 bit
264. rt from 0x00000000 as in the case of external reset The Watchdog time out flag WDTOF can be examined to determine if the Watchdog has caused the reset condition The WDTOF flag must be cleared by software Watchdog 211 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 REGISTER DESCRIPTION The Watchdog contains 4 registers as shown in Table 158 below Table 158 Watchdog Register Map ON Reset Name Description Access Value Address Watchdog mode register This register contains the basic mode and Read Set 0 OxE0000000 status of the Watchdog Timer WDTC Muda timer constant register This register determines the time out Read Write OxE0000004 WDMOD WDFEED Watchdog feed sequence register Writing AAh followed by 55h to this Write Only NA OxE0000008 register reloads the Watchdog timer to its preset value WDTV Watchdog timer value register This register reads out the current value Read Only OxFF 0xE000000C of the Watchdog timer Reset Value refers to the data stored in used bits only It does not include reserved bits content Watchdog 212 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Watchdog Mode Register WDMOD 0xE0000000 The WDMOD register controls the operation of the Watchdog as per the combination of WDEN and RESET bits WDEN WDRESET 0 X Debug Operate without the Watchdog run
265. s VICRawintr VICFIQStatus and VICIRQStatus Also before the next interrupt can be serviced it is necessary that write is performed into the VICVectAddr register before the return from interrupt is executed This write will clear the respective interrupt flag in the internal interrupt priority hardware In order to disable the interrupt at the VIC you need to clear corresponding bit in the VICIntEnClr register which in turn clears the related bit in the VICIntEnable register This also applies to the VICSoftInt and VICSoftIntClear in which VICSoftIntClear will clear the respective bits in VICSoftInt For example if VICSoftIntZ0x0000 0005 and bit 0 has to be cleared VICSoftIntClear 0x0000 0001 will acomplish this Before the new clear operation on the same bit in VICSoftInt using writing into VICSoftIntClear is performed in the future VICSoftIntClear 0x0000 0000 must be assigned Therefore writing 1 to any bit in Clear register will have one time effect in the destination register If the watchdog is enabled for interrupt on underflow or invalid feed sequence only then there is no way of clearing the interrupt The only way you could perform return from interrupt is by disabling the interrupt at the VIC using VICIntEnCIr Example Assuming that UARTO and SPIO are generating interrupt requests that are classified as vectored IRQs UARTO being on the higher level than SPIO while UART1 and C are generating non vectored IRQs the following could be
266. s and return codes are in ASCII format CMD SUCCESS is sent by ISP command handler only when received ISP command has been completely executed and the new ISP command can be given by the host Exceptions from this rule are Set Baud Rate Write to RAM Read Memory and Go commands Table 163 ISP Command Summary ISP Command Usage Described in Unlock U Unlock Code gt Table 164 CNNMNEEAT A ME E Unlock Unlock code Table 164 ISP Unlock command description Command U Input Unlock code 23130 CMD SUCCESS Return Code INVALID CODE PARAM ERROR This command is used to unlock flash Write Erase amp Go commands Example U 23130 lt CR gt lt LF gt unlocks the flash Write Erase amp Go commands Flash Memory System and Programming 225 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Set Baud Rate Baud Rate stop bit gt Table 165 ISP Set Baud Rate command description Command B um Baud Rate 9600 19200 38400 57600 115200 230400 P Stop bit 1 2 CMD_SUCCESS Ret rn Code INVALID_BAUD_RATE INVALID_STOP_BIT PARAM_ERROR This command is used to change the baud rate The new baud rate is effective after the command handler sends the CMD SUCCESS return code Example B 57600 1 lt CR gt lt LF gt sets the serial port to baud rate 57600 bps and 1 stop bit Table 166 Correlation between po
267. s mode is available in LPC2212 2214 only and must not be specified when LPC2114 2124 are used Warning Improper setting of this value may result in incorrect operation of the device Reserved user software should not write ones to reserved bits The value read from a 7 2 Reserved P NA reserved bit is not defined The hardware reset value of the MAP bits is 00 for LPC2114 2124 2212 2214 parts The apparent reset value that the user will see will be altered by the Boot Loader code which always runs initially at reset User documentation will reflect this difference Memory Mapping Control Usage Notes Memory Mapping Control simply selects one out of three available sources of data sets of 64 bytes each necessary for handling ARM exceptions interrupts For example whenever a Software Interrupt request is generated ARM core will always fetch 32 bit data residing on 0x0000 0008 see Table 3 ARM Exception Vector Locations on page 37 This means that when MEMMAPT 1 0 210 User RAM Mode read fetch from 0x0000 0008 will provide data stored in 0x4000 0008 If MEMMAPT 1 0 201 User Flash Mode read fetch from 0x0000 0008 will provide data stored in on chip Flash location 0x0000 0008 In case of MEMMAPT 1 0 200 Boot Loader Mode read fetch from 0x0000 0008 will provide data availble also at Ox7FFF E008 Boot Block remapped from on chip Flash memory System Control Block 59 May 03 2004 Philips Semiconductors Preliminary U
268. s of SWI handler here Prefetch Address DCD rm prefetchabort handler Provided by RealMonitor Abort Address DCD rm dataabort handler Provided by RealMonitor FIQ Address DCD 0 User can put address of FIQ handler here AREA init code CODE ram end EQU 0x4000xxxx Top of on chip RAM init AER KK KR RARA RARA RARA RAR RRA RAR RRA RR RR Ck kk Kk CK RARA RARA I ko kk Set up the stack pointers for various processor modes Stack grows downwards Fe A A RARA RARA RARA A A kk kk I I I A A A kk ko I ke I x x f LDR r2 ram_end Get top of RAM MRS r0 CPSR Save current processor mode Initialize the Undef mode stack for RealMonitor use BIC rl r0 0x1f ORR riy ub FOID MSR CPSR Cp 1 Keep top 32 bytes for flash programming routines Refer to Flash Memory System and Programming chapter SUB sp r2 0x1F Initialize the Abort mode stack for RealMonitor BIC rl r0 0x1f ORR rl r1 0x17 MSR CESR Gp ul Keep 64 bytes for Undef mode stack SUB sp r2 0x5F RealMonitor 256 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Initialize the IRQ mode stack for RealMonitor and User BIC rl r0 0x1f ORR rl rl 0x12 MSR CPSR c rl Keep 32 bytes for Abort mode stack SUB sp r2 40x7F Return to the original mode MSR CPSR G roO Initialize the stack for user application Keep 256 bytes for IRQ mode stack SUB sp r2 0x17F
269. s of on chip Flash memory To blank Description check a single sector use the same Start and End sector numbers Read Part ID Status Code Table 184 IAP Read Part ID command description Command Read Part ID Command Code 54 Input E parameters None Reut ResultO Part Identification Number This command is used to read the part identification number Read Boot code version Table 185 IAP Read Boot Code version command description Command Read boot code version input Command code 55 p Parameters None ResultO 2 bytes of boot code version number It is to be interpreted as lt byte1 Major gt lt byte0 Minor gt This command is used to read the boot code version number Flash Memory System and Programming 238 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Compare Table 186 IAP Compare command description Command Compare Command Code 56 ParamO DST Starting Flash or RAM address from where data bytes are to be compared This address should be a word boundary Param1 SRC Starting Flash or RAM address from where data bytes are to be compared This address should be a word boundary Param2 Number of bytes to be compared Count should be in multiple of 4 CMD SUCCESS COMPARE ERROR Status Code COUNT ERROR Byte count is not multiple of 4 ADDR ERROR ADDR NOT MAPPED Result0 Offset of
270. same voltage as Vgg but should be SSA isolated to minimize noise and error V 58 PLL Analog Ground OV reference This should nominally be the same voltage as Vss but See ee should be isolated to minimize noise and error 17 49 EN 1 8V Core Power Supply This is the power supply voltage for internal circuitry V 63 Analog 1 8V Core Power Supply This is the power supply voltage for internal circuitry This 18A should be nominally the same voltage as V18 but should be isolated to minimize noise and error V3 v 3 3V Pad Power Supply This is the power supply voltage for the I O ports V 7 Analog 3 3V Pad Power Supply This should be nominally the same voltage as V3 but should 3A be isolated to minimize noise and error Level on this pin is used as a reference for AD convertor Pin Configuration 97 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 LPC2212 2214 PINOUT P2 21 D21 P0 19 MAT1 2 MOSI1 CAP1 2 P1 27 TDO P1 28 TDI VSSA PLL P2 20 D20 P2 19 D19 P2 18 D18 P2 17 D17 P2 16 D16 P2 15 D15 P2 14 D14 P2 13 D13 P1 29 TCK P2 12 D12 P2 11 D11 P0 20 MAT1 3 SSEL1 EINT3 P0 18 CAP1 3 MISO1 MAT1 3 P2 10 D10 P1 30 TMS 127 126 24 122 1 0 3 144 140 37 36 134 33 2 1 1 1 130 29 P2 3 D3 P2 22 D22 VSS v3 P2 2 D2 VSS P2 1 D1 P0 21 PWM5 CAP1 3 v3 P0 22 CAPO 0 MATO O VSS P0 23 P1 20 TRACESYNC P1 19 TRACEPKT3 P0 17 CAP1 2 S
271. ser Manual ARM based Microcontroller LPC2114 2124 2212 2214 PLL PHASE LOCKED LOOP The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz only The input frequency is multiplied up into the cclk with the range of 10 MHz to 60 MHz using a Current Controlled Oscillator CCO The multiplier can be an integer value from 1 to 32 in practice the multiplier value cannot be higher than 6 on the LPC2114 2124 2212 2214 due to the upper frequency limit of the CPU The CCO operates in the range of 156 MHz to 320 MHz so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency The output divider may be set to divide by 2 4 8 or 16 to produce the output clock Since the minimum output divider value is 2 it is insured that the PLL output has a 50 duty cycle A block diagram of the PLL is shown in Figure 15 PLL activation is controlled via the PLLCON register The PLL multiplier and divider values are controlled by the PLLCFG register These two registers are protected in order to prevent accidental alteration of PLL parameters or deactivation of the PLL Since all chip operations including the Watchdog Timer are dependent on the PLL when it is providing the chip clock accidental changes to the PLL setup could result in unexpected behavior of the microcontroller The protection is accomplished by a feed sequence similar to that of the Watchdog Timer De
272. ser code The reserved ARM interrupt vector location 0x0000 0014 should contain the 2 s complement of the check sum of the remaining interrupt vectors This causes the checksum of all of the vectors together to be 0 The boot loader code disables the overlaying of the interrupt vectors from the boot block then calculates the checksum of the interrupt vectors in sector 0 of the flash If the signatures match then the execution control is transferred to the user code by loading the program counter with Ox 0000 0000 Hence the user flash reset vector should contain a jump instruction to the entry point of the user application code If the signature is not valid the auto baud routine synchronizes with the host via serial port 0 The host should send a synchronization character and wait for a response The host side serial port settings should be 8 data bits 1 stop bit and no parity The auto baud routine measures the bit time of the received synchronization character in terms of its own frequency and programs the baud rate generator of the serial port It also sends an ASCII string Synchronized lt CR gt lt LF gt to the host In response to this the host should send the received string Synchronized lt CR gt lt LF gt The auto baud routine looks at the received characters to verify synchronization If synchronization is verified then OK lt CR gt lt LF gt string is sent to the host The host should respond by sending the crystal frequency
273. set if PWMMR 1 matches it When zero this feature Stop on PWMMR1 When one the PWMTC and PWMPC will be stopped and PWMTCR O will be set to P 0 if PWMMR 1 matches the PWMTC When zero this feature is disabled When one an interrupt is generated when PWMMR2 matches the value in the EN Interrupton PWMMR2 PWMTC When zero this interrupt is disabled ES Reset on PWMMR2 d the PWMTC will be reset if PWMMR2 matches it When zero this feature Stop on PWMMR3 When one the PWMTC and PWMPC will be stopped and PWMTCR O will be set to P 0 if PWMMR3 matches the PWMTC When zero this feature is disabled When one an interrupt is generated when PWMMR4 matches the value in the Mo AMS PWMTC When zero this interrupt is disabled Reset on PWMMR4 When one the PWMTC will be reset if PWMMR4 matches it When zero this feature is disabled Stop on PWMMR4 When one the PWMTC and PWMPC will be stopped and PWMTCR O will be set to P 0 if PWMMR4 matches the PWMTC When zero this feature is disabled When one an interrupt is generated when PWMMR5 matches the value in the IDIGIEUDC ON MAS PWMTC When zero this interrupt is disabled Reset on PWMMR5 M e the PWMTC will be reset if PWMMR5 matches it When zero this feature Stop on PWMMR2 When one the PWMTC and PWMPC will be stopped and PWMTCR O0 will be set to P 0 if PWMMR 2 matches the PWMTC When zero this feature is disabled When one an interrupt is generated when PWMMR3 matches the value in the o ON EWN MMES PWMTC When z
274. sh memory sector where Boot Block resides is not available for user to store code Sector Number Flash Memory System and Programming 223 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 CODE READ PROTECTION This feature is available as of Bootloader revision 1 61 Code read protection is enabled by programming the flash address location 0x1FC User flash sector 0 with value 0x87654321 2271560481 Decimal Address 0x1FC is used to allow some room for the fig exception handler When the code read protection is enabled the JTAG debug port external memory boot and the following ISP commands are disabled Read Memory Write to RAM Go Copy RAM to Flash The ISP commands mentioned above terminate with return code CODE READ PROTECTION ENABLED The ISP erase command only allows erasure of all user sectors when the code read protection is enabled This limitation does not exist if the code read protection is not enabled IAP commands are not affected by the code read protection Flash Memory System and Programming 224 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 ISP Commands The following commands are accepted by the ISP command handler Detailed return codes are supported for each command The command handler sends the return code INVALID COMMAND when an undefined command is received Command
275. should not write ones to reserved bits The value read from a Reserved n 1 reserved bit is not defined MAM USAGE NOTES When changing MAM timing the MAM must first be turned off by writing a zero to MAMCR A new value may then be written to MAMTIM Finally the MAM may be turned on again by writing a value 1 or 2 corresponding to the desired operating mode to MAMCR For system clock slower than 20 MHz MAMTIM can be 001 For system clock between 20 MHz and 40 MHz Flash access time is suggested to be 2 CCLKs while in systems with system clock faster than 40 MHz 3 CCLKs are proposed Memory Accelerator Module MAM 77 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Memory Accelerator Module MAM 78 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 6 VECTORED INTERRUPT CONTROLLER VIC FEATURES ARM PrimeCell Vectored Interrupt Controller 32 interrupt request inputs 16 vectored IRQ interrupts 16 priority levels dynamically assigned to interrupt requests Software interrupt generation DESCRIPTION The Vectored Interrupt Controller VIC takes 32 interrupt request inputs and programmably assigns them into 3 categories FIQ vectored IRQ and non vectored IRQ The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and
276. shown below in Figure 47 Serial JTAG PORT Parallel EmbeddedICE Interface Interface Protocol EmbeddedlCE Converter nuu nuu oa HOST RUNNING DEBUGGER ARM7TDMI S TARGET BOARD Figure 47 EmbeddedICE Debug Environment Block Diagram EmbeddedICE Logic 244 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 21 EMBEDDED TRACE MACROCELL FEATURES Closely track the instructions that the ARM core is executing 10 pin interface 1 External trigger input All registers are programmed through JTAG interface Does not consume power when trace is not being used THUMB instruction set support APPLICATIONS As the microcontroller has significant amounts of on chip memories it is not possible to determine how the processor core is operating simply by observing the external pins The ETM provides real time trace capability for deeply embedded processor cores It outputs information about processor execution to a trace port A software debugger allows configuration of the ETM using a JTAG interface and displays the trace information that has been captured in a format that a user can easily understand DESCRIPTION The ETM is connected directly to the ARM core and not to the main AMBA system bus It compresses the trace information and exports it t
277. sor Latches UART1 134 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 UART1 Receiver Buffer Register U1RBR 0xE0010000 when DLAB 0 Read Only The U1RBR is the top byte of the UART1 Rx FIFO The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface The LSB bit 0 represents the oldest received data bit If the character received is less than 8 bits the unused MSBs are padded with zeroes The Divisor Latch Access Bit DLAB in U1LCR must be zero in order to access the U1RBR The U1RBR is always Read Only Table 88 UART1 Receiver Buffer Register U1RBR 0xE0010000 when DLAB 0 Read Only Reset Value Function Description Receiver Buffer The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 Rx un Register FIFO defined UART1 Transmitter Holding Register U1THR 0xE0010000 when DLAB 0 Write Only The U1THR is the top byte of the UART1 Tx FIFO The top byte is the newest character in the Tx FIFO and can be written via the bus interface The LSB represents the first bit to transmit The Divisor Latch Access Bit DLAB in U1LCR must be zero in order to access the U1THR The U1THR is always Write Only Table 89 UART1 Transmit Holding Register U1THR 0xE0010000 when DLAB 0 Write Only Function Description Writing to the UART1 Transmit Holding Register causes
278. ssible ISP baudrates and external crystal frequency in MHz ISP Baudrate VS 9600 19200 38400 57600 External Crystal Frequency 10 0000 re o CI IR ICI wmm 6 3 1 9m 00 0 IS IS LLL EC EOS apo PE ICT IE mI Los wc mdp E 230400 18 4320 19 6608 24 5760 Echo setting Table 167 ISP Echo command description Command A Input Setting ON 1 OFF 0 CMD SUCCESS Sr The default setting for echo command is ON When ON the ISP command handler sends the Description received serial data back to the host Example A 0 lt CR gt lt LF gt turns echo off Flash Memory System and Programming 226 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Write to RAM start address number of bytes gt The host should send the data only after receiving the CMD SUCCESS return code The host should send the check sum after transmitting 20 UU encoded lines The checksum is generated by adding raw data before UU encoding bytes and is reset after transmitting 20 UU encoded lines The length of any UU encoded line should not exceed 61 characters bytes i e it can hold 45 data bytes When the data fits in less then 20 UU encoded lines then the check sum should be of actual number of bytes sent The ISP command handler compares it with the check sum of the received bytes If the check sum matches then the ISP command handler responds
279. st be greater than or equal to 1 Table 155 Prescaler Integer Register PREINT 0xE0024080 PREINT Function Description Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Prescaler Integer Contains the integer portion of the RTC prescaler value 0 Prescaler Fraction Register PREFRAC 0xE0024084 15 13 Reserved This is the fractional portion of the prescale value and may be calculated as PREFRAC pclk PREINT 1 x 32768 Table 156 Prescaler Fraction Register PREFRAC 0xE0024084 PREFRAC Function Description Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Prescaler Fraction Contains the fractional portion of the RTC prescaler value 0 15 Reserved Real Time Clock 208 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Example of Prescaler Usage In a simplistic case the pclk frequency is 65 537 kHz So PREINT int pclk 32768 1 2 1 and PREFRAC pclk PREINT 1 x 32768 1 With this prescaler setting exactly 32 768 clocks per second will be provided to the RTC by counting 2 pclks 32 767 times and 3 pclks once In a more realistic case the pclk frequency is 10 MHz Then PREINT int pclk 32768 1 2 304 and PREFRAC pclk PREINT 1 x 32768 5 760 In this case 5 76
280. t Clear Register IOOCLR 0xE002800C IO1CLR 0xE002801C IO2CLR 0xE002802C lO3CLR OxE002803C 0 ees 118 Table 69 GPIO Direction Register IOODIR OxE0028008 IO1DIR 0xE0028018 IO2DIR 0xE0028028 IO3DIR 0xE0028038 oooccoocccocccc eee 118 Table 70 UARTO Pin Description 0 0 seascair RII IA 121 Table 71 UARTO Register Map isses rm 122 Table 72 UARTO Receiver Buffer Register UORBR OXE000C000 when DLAB 0 Read Only 123 Table 73 UARTO Transmit Holding Register UOTHR 0xE000C000 when DLAB 0 Write Only 123 Table 74 UARTO Divisor Latch LSB Register UODLL OXE000C000 when DLAB 1 123 Table 75 UARTO Divisor Latch MSB Register UODLM OxE000C004 when DLAB 1 123 Table 76 UARTO Interrupt Enable Register Bit Descriptions UOIER OXE000C004 when DLAB 0 124 Table 77 UARTO Interrupt Identification Register Bit Descriptions UOIIR OXE000C008 Read Only 124 Table 78 UARTO Interrupt Handling ooooooooccrorr RII 125 Table 79 UARTO FIFO Control Register Bit Descriptions UOFCR 0xE000C008 126 Table 80 UARTO Line Control Register Bit Descriptions UOLCR OxEOOOCOOC 127 Table 81 UARTO Line Status Register Bit Descriptions UOLSR 0xE000C014 Read Only 128 Table 82 UARTO Scratchpad Register UOSCR OxEQOOCO1C 2 lesen 129 Table 83 UARTI Pin Description
281. t O in IOOSET corresponds to P0 0 Bit 31 in IOOSET corresponds to P0 31 0 GPIO Output Clear Register GPIO 117 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 IOOCLR 0xE002800C IO1CLR 0xE002801C IO2CLR 0xE002802C IO3CLR 0xE002803C This register is used to produce a LOW level at port pins if they are configured as GPIO in an OUTPUT mode Writing 1 produces a LOW level at the corresponding port pins and clears the corresponding bits in the IOSET register Writing O has no effect If any pin is configured as an input or a secondary function writing to IOCLR has no effect Table 71 GPIO Output Clear Register IOOCLR 0xE002800C IO1CLR 0xE002801C IO2CLR 0xE002802C IO3CLR 0xE002803C Value after Description Reset Output value CLEAR bits Bit 0 in IOOCLR corresponds to P0 0 Bit 31 in IOOCLR corresponds to P0 31 0 GPIO Direction Register IOODIR 0xE0028008 IO1DIR 0xE0028018 IO2DIR 0xE0028028 IO3DIR 0xE0028038 This register is used to control the direction of the pins when they are configured as GPIO port pins Direction bit for any pin must be set according to the pin functionality Table 72 GPIO Direction Register IOODIR 0xE0028008 IO1DIR 0xE0028018 IO2DIR 0xE0028028 IO3DIR 0xE0028038 Value after Description Reset Direction control bits 0 INPUT 1 OUTPUT Bit 0 in IOODIR controls PO O
282. t for TIMERO channel 2 AIN2 A D converter input 2 This analog input is always connected to its pin CAP0 3 Capture input for TIMERO channel 3 MATO 3 Match output for TIMERO channel 3 AIN3 A D converter input 3 This analog input is always connected to its pin EINT3 External interrupt 3 input CAPO 0 Capture input for TIMERO channel 0 Port 1 Port 1 is a 32 bit bi directional I O port with individual direction controls for each bit The operation of port 1 pins depends upon the pin function selected via the Pin Connect Block Only pins 16 through 31 of port 1 are available Note All Port 1 pins are 5V tolerant with built in pull up resistor that sets input level to high when corresponding pin is used as input P1 16 TRACEPKTOTrace Packet bit 0 Standard I O port with internal pull up P1 17 TRACEPKT1Trace Packet bit 1 Standard I O port with internal pull up P1 18 TRACEPKT2Trace Packet bit 2 Standard I O port with internal pull up P1 19 TRACEPKT3Trace Packet bit 3 Standard I O port with internal pull up P1 20 TRACESYNCTrace Synchronization Standard I O port with internal pull up LOW on this pin while RESET is LOW enables pins P1 25 16 to operate as a Trace port after reset Important LOW on pin P1 20 while RESET is LOW enables pins P1 25 16 to operate as a Trace port after reset PIPESTATO Pipeline Status bit O Standard I O port with internal pull up PIPESTAT1 Pipeline Status bit 1 Standard I O port with i
283. t its own slave address in the same serial transfer Slave Address R DATA A e A 0 Write Data Transferred 1 Read n Bytes Acknowledge A Acknowledge SDA low From Master to Slave A Not Acknowledge SDA high From Slave to Master S START condition P STOP Condition Figure 31 Format of slave transmitter mode PIN DESCRIPTION Table 101 12C Pin Description Pin Name Description Serial Data I C data input and output The associated port pin has an open drain output in POR order to conform to 12C specifications Input Serial Clock I C clock input and output The associated port pin has an open drain output in SCL 2 pa Output order to conform to I C specifications 12C Interface 151 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 REGISTER DESCRIPTION The I C interface contains 7 registers as shown in Table 102 below Table 102 I C Register Map Name Description Access Reset Value Address 12CONSET C Control Set Register Read Set 0 0xE001C000 I2STAT 12C Status Register Read Only 0xE001C004 I2DAT PC Data Register Read Write ME j 0xE001C008 mon E E A ELE Reset Value refers to the data stored in used bits only It does not include reserved bits content 12C Interface 152 May 03 2004 Philips Semiconductors Preliminary User Manual ARM b
284. t maximum clock rate For critical code size applications the alternative 16 bit Thumb Mode reduces code by more than 3096 with minimal performance penalty With their comapct 64 and 144 pin packages low power consumption various 32 bit timers combination of 4 channel 10 bit ADC or 8 channel 10 bit ADC 64 and 144 pin packages respectively and up to 9 external interrupt pins these microcontrollers are particularly suitable for industrial control medical systems access control and point of sale Number of available GPIOs goes up to 46 in 64 pin package In 144 pin packages number of available GPIOs tops 76 with external memory in use through 112 single chip application Being equipped wide range of serial communications interfaces they are also very well suited for communication gateways protocol converters and embedded soft modems as well as many other general purpose applications FEATURES 16 32 bit ARM7TDMI S microcontroller in a 64 or 144 pin package 16 kB on chip Static RAM 128 256 kB on chip Flash Program Memory at least 10 000 erate write cycles over the whole temperature range 128 bit wide interface accelerator enables high speed 60 MHz operation External 8 16 or 32 bit bus 144 pin package only In System Programming ISP and In Application Programming IAP via on chip boot loader software Flash programming takes 1 ms per 512 byte line Single sector or full chip erase takes 400 ms EmbeddedICE RT int
285. t specified timer values based on four match registers It also includes four capture inputs to trap the timer value when an input signal transitions optionally generating an interrupt PIN DESCRIPTION Table 121 gives a brief summary of each of the Timer related pins Table 121 Pin summary Pin name Pin direction Pin Description Capture Signals A transition on a capture pin can be configured to load one of the Capture Registers with the value in the Timer Counter and optionally generate an interrupt Capture functionality can be selected from a number of pins Also if for example 2 pins are selected to provide CAPO 2 function in parallel their inputs will be logically ored and this value will be processed as a single input CAPO 3 0 CAPO 0 can be selected from on up to 3 pins at the same time CAP1 3 0 CAPO 1 can be selected from on up to 2 pins at the same time CAPO 2 can be selected from on up to 3 pins at the same time CAPO 3 can be selected from on 1 pin CAP1 0 can be selected from on 1 pin CAP1 1 can be selected from on 1 pin CAP1 2 can be selected from on up to 2 pins at the same time CAP1 3 can be selected from on up to 2 pins at the same time External Match Output 0 1 When a match register 0 1 MR3 0 equals the timer counter TC this output can either toggle go low go high or do nothing The External Match Register EMR controls the functionality of this output Match Output functionality can be selected o
286. tails are provided in the description of the PLLFEED register The PLL is turned off and bypassed following a chip Reset and when by entering power Down mode PLL is enabled by software only The program must configure and activate the PLL wait for the PLL to Lock then connect to the PLL as a clock source Register Description The PLL is controlled by the registers shown in Table 21 More detailed descriptions follow Warning Improper setting of PLL values may result in incorrect operation of the device Table 21 PLL Registers Address Name Description Access PLL Control Register Holding register for updating PLL control bits Values 0xE01FC080 PLLCON written to this register do not take effect until a valid PLL feed sequence has taken R W place PLL Configuration Register Holding register for updating PLL configuration 0xE01FC084 PLLCFG values Values written to this register do not take effect until a valid PLL feed sequence has taken place shadow registers that actually affect PLL operation PLL Status Register Read back register for PLL control and configuration information If PLLCON or PLLCFG have been written to but a PLL feed 0xE01FC088 PLLSTAT sequence has not yet occurred they will not reflect the current PLL state Reading this register provides the actual values controlling the PLL as well as the status of the PLL PLL Feed Register This register enables loading of the PLL control and 0xE01FC08C PLLFE
287. tation Embedded Trace Macrocell Specification ARM IHI 0014E PIN DESCRIPTION Table 191 ETM Pin Description Pin Name Description Trace Clock The trace clock signal provides the clock for the trace port PIPESTAT 2 0 TRACESYNC and TRACEPKT 3 0 signals are referenced to the rising edge of the trace clock This clock is not generated by the ETM block It is to be derived from the system clock The clock should be balanced to provide sufficient hold time for the trace data signals Half TRACECLK rate clocking mode is supported Trace data signals should be shifted by a clock phase from TRACECLK Refer to Figure 3 14 page 3 26 and figure 3 15 page 3 27 in ETM7 Technical Reference Manual ARM DDI 0158B for example circuits that implements both half rate clocking and shifting of the trace data with respect to the clock For TRACECLK timings refer to section 5 2 on page 5 13 in Embedded Trace Macrocell Specification ARM IHI 0014E PIPESTAT 2 0 Output Pipe Line status The pipeline status signals provide a cycle by cycle indication of what is happening in the execution stage of the processor pipeline Trace synchronization The trace sync signal is used to indicate the first packet of a group TRACESYNG Output of trace packets and is asserted HIGH only for the first packet of any branch address Trace Packet The trace packet signals are used to output packaged address and data information related to the pipeline status All packe
288. te parts of the flash image to the RAM and then execute the IAP call Copy RAM to Flash repeatedly with proper offset Flash Memory System and Programming 240 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 20 EMBEDDEDICE LOGIC FEATURES No target resources are required by the software debugger in order to start the debugging session Allows the software debugger to talk via a JTAG Joint Test Action Group port directly to the core Inserts instructions directly in to the ARM7TDMI S core The ARM7TDMI S core or the System state can be examined saved or changed depending on the type of instruction inserted Allows instructions to execute at a slow debug speed or at a fast system speed APPLICATIONS The EmbeddedICE logic provides on chip debug support The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol convertor EmbeddedICE protocol convertor converts the Remote Debug Protocol commands to the JTAG data needed to access the ARM7TDMI S core present on the target system DESCRIPTION The ARM7TDMI S Debug Architecture uses the existing JTAG port as a method of accessing the core The scan chains that are around the core for production test are reused in the debug state to capture information from the databus and to insert new information into the core or the memory There are two JTAG style scan chains withi
289. ted every PR 1 cycles of R W 0xE000400C 0xE000800C pclk TOPR T1PR Prescale Counter The 32 bit PC is a counter which is incremented to the value stored in PR When the value in PR is reached the TC R W 0xE0004010 0xE0008010 is incremented MCR Match Control Register The MCR is used to control if an interrupt R W 0xE0004014 0xE0008014 is generated and if the TC is reset when a Match occurs TOMCR T1MCR Match Register 0 MRO can be enabled through the MCR to reset the TC stop both the TC and PC and or generate an interrupt R W 0xE00040181 0xE0008018 every time MRO matches the TC a 0xE000401C 0xE000801C MR1 Match Register 1 See MRO description aw oo TOMR1 T1MR1 tad 0xE0004020 0xE0008020 MR2 Match Register 2 See MRO description LEGEN TOMR2 T1MR2 Sud 0xE0004024 0xE0008024 MR3 Match Register 3 See MRO description MOE TOMR3 T1MR3 Capture Control Register The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether R W 0xE0004028 0xE0008023 or not an interrupt is generated when a capture takes place 0xE000402C 0xE000802C TOCRO T1CRO OxE0004030 0xE0008030 TOCR1 T1CR1 OxE0004034 0xE0008034 TOCR2 T1CR2 OxE0004038 0xE0008038 TOCR3 T1CR3 0xE000403C 0xE000803C TOEMR T1EMR P MRO Capture Register 0 CRO is loaded with the value of TC when there is an event on the CAPO O CAP1 0 input CR1 Capture Register 1 See CRO description EN O D
290. ters in the U1THR at one time since the last THRE 1 event This delay is provided to give the CPU time to write data to UTTHR without a THRE interrupt to decode and service A THRE interrupt is set immediately if the UART1 THR FIFO has held two or more characters at one time and currently the U1THR is empty The THRE interrupt is reset when a U1THR write occurs or a read of the U1IIR occurs and the THRE is the highest interrupt U11IR3 12001 The modem interrupt U11IR3 1 2000 is the lowest priority interrupt and is activated whenever there is any state change on modem inputs pins DCD DSR or CTS In addition a low to high transition on modem input RI will generate a modem interrupt The source of the modem interrupt can be determined by examining U1MSR3 0 A U1MSR read will clear the modem interrupt UART1 138 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 UART1 FIFO Control Register U1FCR 0xE0010008 The U1FCR controls the operation of the UART1 Rx and Tx FIFOs Table 95 UART1 FCR Bit Descriptions U1FCR 0xE0010008 Function Description Active high enable for both UART1 Rx and Tx FIFOs and U1FCR7 1 access This bit FIFO Enable must be set for proper UART1 operation Any transition on this bit will automatically clear the UART1 FIFOs Rx FIFO Reset Writing a logic 1 to U1 FCR1 will clear all bytes in UART1 Rx FIFO and reset the pointer logic This bit is se
291. th execution As of Bootloader rev 1 61 this command is blocked when code read protection is enabled Example X G 0 A lt CR gt lt LF gt branches to address 0x0000 0000 in ARM mode Erase sector s start sector number end sector number gt Table 173 ISP Erase sector command description Command E input Start Sector Number P End Sector Number Should be greater than or equal to start sector number CMD SUCCESS BUSY INVALID SECTOR Return Code SECTOR NOT PREPARED FOR WRITE OPERATION CMD LOCKED PARAM ERROR CODE READ PROTECTION ENABLED This command is used to erase a sector or multiple sectors of on chip Flash memory The boot sector can not be erased by this command To erase a single sector use the same Start and End sector numbers As of Bootloader rev 1 61 this command is blocked when code read protection is enabled Example X E 2 3 lt CR gt lt LF gt erases the flash sectors 2 and 3 Description Flash Memory System and Programming 230 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Blank check sector s start sector number end sector number gt Table 174 ISP Blank check sector s command description Command l inn t Start Sector Number P End Sector Number Should be greater than or equal to start sector number CMD SUCCESS SECTOR NOT BLANK followed by Offset of the first non blank word location
292. th this bit number Writing zeroes to bits in VICSoftInt has no effect see VICSoftIntClear Software Interrupt Clear Register VICSoftintClear OXFFFFF01C Write Only This register allows software to clear one or more bits in the Software Interrupt register without having to first read it Table 42 Software Interrupt Clear Register VICSoftintClear OXFFFFF01C Write Only VICSoftlntClear Function Reset Value 1 writing a 1 clears the corresponding bit in the Software Interrupt register thus releasing 31 0 the forcing of this request 0 writing a O leaves the corresponding bit in VICSoftInt unchanged Raw Interrupt Status Register VICRawintr OXFFFFF008 Read Only This register reads out the state of the 32 interrupt requests and software interrupts regardless of enabling or classification Table 43 Raw Interrupt Status Register VICRawintr OXFFFFF008 Read Only ViCRawintr Function Reset Value 1 the interrupt request or software interrupt with this bit number is asserted 0 0 the interrupt request or software interrupt with this bit number is negated 31 0 Vectored Interrupt Controller VIC 82 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Interrupt Enable Register VICIntEnable OXFFFFF010 Read Write This register controls which of the 32 interrupt requests and software interrupts contribute to FIQ or IRQ Table 44 I
293. the SPSR irq Vectored Interrupt Controller VIC 88 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 This means that on entry to the IRQ interrupt service routine one can see the unusual effect that an IRQ interrupt has just been taken while the bit in the SPSR is set In the example above the F bit will also be set in both the CPSR and SPSR This means that FIQs are disabled upon entry to the IRQ service routine and will remain so until explicitly re enabled FIQs will not be re enabled automatically by the IRQ return sequence Although the example shows both IRQ and FIQ interrupts being disabled similar behavior occurs when only one of the two interrupt types is being disabled The fact that the core processes the IRQ after completion of the MSR instruction which disables IRQs does not normally cause a problem since an interrupt arriving just one cycle earlier would be expected to be taken When the interrupt routine returns with an instruction like SUBS pc lr 4 the SPSR IRQ is restored to the CPSR The CPSR will now have the bit and F bit set and therefore execution will continue with all interrupts disabled However this can cause problems in the following cases Problem 1 A particular routine maybe called as an IRQ handler or as a regular subroutine In the latter case the system guarantees that IRQs would have been disabled prior to the routine being called
294. the data to be stored in the UART1 transmit FIFO The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available Transmit Holding Register UART1 Divisor Latch LSB Register U1DLL 0xE0010000 when DLAB 1 UART1 Divisor Latch MSB Register U1DLM 0xE0010004 when DLAB 1 The UART1 Divisor Latch is part of the UART1 Baud Rate Generator and holds the value used to divide the VPB clock pclk in order to produce the baud rate clock which must be 16x the desired baud rate The U1DLL and U1DLM registers together form a 16 bit divisor where U1DLL contains the lower 8 bits of the divisor and U1DLM contains the higher 8 bits of the divisor A h0000 value is treated like a h0001 value as division by zero is not allowed The Divisor Latch Access Bit DLAB in UTLCR must be one in order to access the UART1 Divisor Latches Table 90 UART1 Divisor Latch LSB Register U1DLL 0xE0010000 when DLAB 1 Function Description Divisor Latch The UART1 Divisor Latch LSB Register along with the U1DLM register determines the LSB Register baud rate of the UART1 UART1 135 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 91 UART1 Divisor Latch MSB Register U1DLM 0xE0010004 when DLAB 1 Function Description Divisor Latch The UART1 Divisor Latch MSB Register along with the U1DLL register determines the MSB Register
295. the slave The clock is programmable to be active high or active low The SPI is only active during a data transfer Any other time it is either in its inactive state or tri stated Slave Select The SPI slave select signal is an active low signal that indicates which slave is currently selected to participate in a data transfer Each slave has its own unique slave select signal input The SSEL must be low before data transactions begin and normally stays low for the duration of the transaction If the SSEL signal goes high any time during a data transfer the transfer is considered to be aborted In this event the slave returns to idle and any data that SSEL1 SSELO was received is thrown away There are no other indications of this exception This signal is not i directly driven by the master It could be driven by a simple general purpose l O under software SCK1 SCKO control Note LPC2114 2124 2212 2214 configured to operate as SPI master MUST select SSEL functionality on an apropriate pin and have HIGH level on this pin in order to act as a master slave drives the signal high impedance Master Out Slave In The MOSI signal is a unidirectional signal used to transfer serial data MOSI1 MOSIO from the master to the slave When a device is a master serial data is output on this signal Master In Slave Out The MISO signal is a unidirectional signal used to transfer serial data from the slave to the master When a device is a sla
296. tialy disastrous chain of events can be prevented in two ways 1 Application code should be set up in a way to prevent the spurious interrupts to ever happen Simple guarding of changes to the VIC may not not be enough since for example glitches on level sensitive interrupts can also cause spurious interrupts 2 VIC default handler should be set up and tested properly Details and Case Studies on Spurious Interrupts This chapter contains details that can be obtained from the official ARM website http Awww arm com FAQ section under the Technical Support link http www arm com support faqip 3677 html What happens if an interrupt occurs as it is being disabled Applies to ARM7TDMI If an interrupt is received by the core during execution of an instruction that disables interrupts the ARM7 family will still take the interrupt This occurs for both IRQ and FIQ interrupts For example consider the follow instruction sequence MRS r0 cpsr ORR rO rO dI Bit OR F Bit disable IRQ and FIQ interrupts MSR cpsr c r0 If an IRQ interrupt is received during execution of the MSR instruction then the behavior will be as follows The IRQ interrupt is latched The MSR cpsr rO executes to completion setting both the bit and the F bit in the CPSR The IRQ interrupt is taken because the core was committed to taking the interrupt exception before the I bit was set in the CPSR The CPSR with the I bit and F bit set is moved to
297. tions ooooooooorro RII 259 6 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 List of Figures Figure 1 LPC2114 2124 2212 2214 Block Diagram 2 1 eee 19 Figure 2 System Memory Map oococococ hmmm 33 Figure 3 Peripheral Memory Map o ooocococ RR HH 3 3n 34 Figure 4 AHB Peripheral Map o oooocoococo RR y ee 35 Figure 5 VPB Peripheral Map oo0oooooccoorrcare e Rh rn 36 Figure 6 Map of lower memory is showing re mapped and re mappable areas 128 kB Flash 39 Figure 7 32 Bit Bank External Memory Interfaces llee e 44 Figure 8 16 Bit Bank External Memory Interfaces lll e 45 Figure 9 8 Bit Bank External Memory Interface llllelee nh 45 Figure 10 External memory read access WST1 0 and WST1 1 examples 0 0005 46 Figure 11 External memory write access WST2 0 and WST2 1 examples o oooooooooooo 46 Figure 12 Oscillator modes and models a slave mode of operation b oscillation mode of operation C external crystal model used for CX1 X2 evaluation 0 0c eee eee eee 52 Figure 13 FOSC selection algorithm 0 0 ccc n 53 Figure 14 External Interrupt LogiC 0oo0ooooooorrorearr RR IA In 58 Figure 15 PLL Block Diagram lt een ek e e eme RR erm m Rm RR s 61 Figure 16 Reset Block Diagram including Wakeup Timer 00 0 eee ee 69 Fig
298. ts are eight bits in length A packet is output over two cycles In the first cycle Packet 3 0 is output and in the second cycle Packet 7 4 is output EXTIN O External Trigger Input TRACEPKT 3 0 Output RESET STATE OF MULTIPLEXED PINS On the LPC2114 2124 2212 2214 the ETM pin functions are multiplexed with P1 25 16 To have these pins come as a Trace port connect a weak bias resistor 4 7 KQ between the P1 20 TRACESYNC pin and Vas To have them come up as port pins do not connect a bias resistor to P1 20 TRACESYNC and ensure that any external driver connected to P1 20 TRACESYNC is either driving high or is in high impedance state during Reset Embedded Trace Macrocell 246 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 REGISTER DESCRIPTION The ETM contains 29 registers as shown in Table 192 below They are described in detail in the ARM IHI 0014E document published by ARM Limited which is available via the Internet at http www arm com Table 192 ETM Registers Register Name Description Access encoding ETM Control Controls the general operation of the ETM Read Write 000 0000 ETM Configuration Code Allows a debugger to read the number of each type of resource Read Only 000 0001 Trigger Event Holds the controlling event Write Only 000 0010 Memory Map Decode Control ridi register used to statically configure the memory map Write Only 000
299. ts of the clock divider counter RTCCIF Table 144 Clock Tick Counter Bits CTC 0xE0024004 Function Description Reserved user software should not write ones to reserved bits The value read from a reserved bit Reserved is not defined Prior to the Seconds counter the CTC counts 32 768 clocks per second Due to the RTC Prescaler these 32 768 time increments may not all be of the same duration Refer to the Reference Clock Divider Prescaler description for details Clock Tick Counter Real Time Clock 201 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Clock Control Register CCR 0xE0024008 The clock register is a 4 bit register that controls the operation of the clock divide circuit Each bit of the clock register is described in Table 145 Table 145 Clock Control Register Bits CCR 0xE0024008 Function Description Clock Enable When this bit is a one the time counters are enabled When it is a zero they are disabled so that they may be initialized CTC Reset When one the elements in the Clock Tick Counter are reset The elements remain 1 CTCRST j reset until CCR 1 is changed to zero CTTEST Test Enable These bits should always be zero during normal operation CLKEN Counter Increment Interrupt The Counter Increment Interrupt Register CIIR gives the ability to generate an interrupt every time a counter is increm
300. tter mode master receiver mode slave transmitter mode and slave receiver mode 12C Interface 147 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 D SDA SCL m Other Device with IC Other Device with IC LPC2114 2124 Interface Interface LPC2212 2214 Figure 24 I2C Bus Configuration 12C Operating Modes Master Transmitter Mode In this mode data is transmitted from master to slave Before the master transmitter mode can be entered I2ZCONSET must be initialized as shown in Figure 25 12EN must be set to 1 to enable the I C function If the AA bit is 0 the 12C interface will not acknowledge any address when another device is master of the bus so it can not enter slave mode The STA STO and SI bits must be 0 The SI Bit is cleared by writing 1 to the SIC bit in the I2CONCLR register I2CONSET Figure 25 Slave Mode Configuration The first byte transmitted contains the slave address of the receiving device 7 bits and the data direction bit In this mode the data direction bit R W should be 0 which means Write The first byte transmitted contains the slave address and Write bit Data is transmitted 8 bits at a time After each byte is transmitted an acknowledge bit is received START and STOP conditions are output to indicate the beginning and
301. tware should not write ones to reserved bits The value read from a reserved bit is not defined Pulse Width Modulator PWM 191 May 03 2004 Enable PWM Match 6 Latch Z gt x Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Pulse Width Modulator PWM 192 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 16 A D CONVERTER FEATURES 10 bit successive approximation analog to digital converter Input multiplexing among 4 pins LPC21 14 2124 or 8 pins LPC2212 2214 Power down mode Measurement range 0 to 3 V 10 bit conversion time gt 2 44 uS Burst conversion mode for single or multiple inputs Optional conversion on transition on input pin or Timer Match signal DESCRIPTION Basic clocking for the A D converter is provided by the VPB clock A programmable divider is included to scale this clock to the 4 5 MHz max clock needed by the successive approximation process A fully accurate conversion requires 11 of these clocks PIN DESCRIPTIONS Table 137 A D Pin Description Pin Name Pin Description Analog Inputs The A D converter cell can measure the voltage on any of these 8 input signals but the 64 pin packages restrict the choice to Ain3 0 Note that these analog inputs are always connected to their pins even if the Pin Multiplexing Register assigns them to port pins A simple sel
302. uctors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Rules for Single Edge Controlled PWM Outputs 1 All single edge controlled PWM outputs go high at the beginning of a PWM cycle unless their match value is equal to 0 2 Each PWM output will go low when its match value is reached If no match occurs i e the match value is greater than the PWM rate the PWM output remains continuously high Rules for Double Edge Controlled PWM Outputs Five rules are used to determine the next value of a PWM output when a new cycle is about to begin 1 The match values for the next PWM cycle are used at the end of a PWM cycle a time point which is coincident with the beginning of the next PWM cycle except as noted in rule 3 2 A match value equal to 0 or the current PWM rate the same as the Match channel 0 value have the same effect except as noted in rule 3 For example a request for a falling edge at the beginning of the PWM cycle has the same effect as a request for a falling edge at the end of a PWM cycle 3 When match values are changing if one of the old match values is equal to the PWM rate it is used again once if the neither of the new match values are equal to 0 or the PWM rate and there was no old match value equal to 0 4 If both a set and a clear of a PWM output are requested at the same time clear takes precedence This can occur when the set and clear match values are the same as in or when the set or
303. ummary of System Control Registers 0 00 e eect eee eee 76 Table 38 MAM Control Register MAMCR OxEQ1FCOOO 0 77 Table 39 MAM Timing Register MAMTIM OXEO1FC004 0 ccc ee 77 Table 40 VIC Register Map 1 0 0 cect hmm rr 80 Table 41 Software Interrupt Register VICSoftInt OXFFFFF018 Read Write 82 Table 42 Software Interrupt Clear Register VICSoftlntClear OXFFFFF01C Write Only 82 Table 43 Raw Interrupt Status Register VICRawlntr OXFFFFFO008 Read Only 82 Table 44 Interrupt Enable Register VICINtEnable OXFFFFF010 Read Write 83 Table 45 Software Interrupt Clear Register VICIntEnClear OXFFFFF014 Write Only 83 Table 46 Interrupt Select Register VICIntSelect OxFFFFFOOC Read Write 83 Table 47 IRQ Status Register VICIRQStatus OXFFFFF000 Read Only oococcccocccc 83 Table 48 IRQ Status Register VICFIQStatus OXFFFFF004 Read Only 000 eee eee 84 Table 49 Vector Control Registers VICVectCntl0 15 OxFFFFF200 23C Read Write 84 Table 50 Vector Address Registers VICVectAddr0 15 OxFFFFF100 13C Read Write 84 Table 51 Default Vector Address Register VICDefVectAddr OXFFFFF034 Read Write 84 Table 52 Vector Address Register VICVectAddr OXFFFFFO30 Read Write 85 Table 53 Prote
304. unter with a programmable 32 bit Prescaler Four 32 bit capture channels take a snapshot of the timer value when an input signal transitions A capture event may also optionally generate an interrupt DESCRIPTION The PWM is based on the standard Timer block and inherits all of its features although only the PWM function is pinned out on the LPC2114 2124 2212 2214 The Timer is designed to count cycles of the peripheral clock pclk and optionally generate interrupts or perform other actions when specified timer values occur based on seven match registers It also includes four capture inputs to save the timer value when an input signal transitions and optionally generate an interrupt when those events occur The PWM function is in addition to these features and is based on match register events The ability to separately control rising and falling edge locations allows the PWM to be used for more applications For instance multi phase motor control typically requires three non overlapping PWM outputs with individual control of all three pulse widths and positions Two match registers can be used to provide a single edge controlled PWM output One match register PWMMR0 controls the PWM cycle rate by resetting the count upon match The other match register controls the PWM edge position Additional single edge controlled PWM outputs require only one match register each since the repetition rate is the same for all PWM outputs Multiple single
305. upt Enable Register UOIER OXE000C004 when DLAB 0 The UOIER is used to enable the four UARTO interrupt sources Table 79 UARTO Interrupt Enable Register Bit Descriptions UOIER OXE000C004 when DLAB 0 Function Description 0 Disable the RDA interrupt RBR Interrupt 1 Enable the RDA interrupt Enable UOIERO enables the Receive Data Available interrupt for UARTO It also controls the Character Receive Time out interrupt 0 Disable the THRE interrupt THRE Interrupt 1 Enable the THRE interrupt Enable UOIER1 enables the THRE interrupt for UARTO The status of this interrupt can be read from UOLSR5 0 Disable the Rx line status interrupts 1 Enable the Rx line status interrupts UARTO Interrupt Identification Register UOIIR OxXE000C008 Read Only The UOIIR provides a status code that denotes the priority and source of a pending interrupt The interrupts are frozen during an UOIIR access If an interrupt occurs during an UOIIR access the interrupt is recorded for the next UOIIR access Table 80 UARTO Interrupt Identification Register Bit Descriptions UOIIR OXEO00CO008 Read Only Function Description 0 At least one interrupt is pending Interrupt 1 No pending interrupts Pending Note that UOIIRO is active low The pending interrupt can be determined by evaluating UOIER3 1 011 1 Receive Line Status RLS 010 2a Receive Data Available RDA Interrupt 110 2b Character Time out Ind
306. ure 17 VPB Divider Connections Rn 71 Figure 18 Simplified Block Diagram of the Memory Accelerator Module lisse sess 74 Figure 19 Block Diagram of the Vectored Interrupt Controller llis 87 Figure 20 LPC2114 2124 64 pin package sssseseseeeeee e n 93 Figure 21 LPC2212 2214 144 pin package ococccococcoc eee eee 98 Figure 22 UARTO Block DiagraM o coocoocor RR 131 Figure 23 WARTI Block Dragram 15 2 ta nae EGRE pa ee ak ee ESTE a a 146 Figure 24 12C Bus Configuration 00 0 ccc e 148 Figure 25 Slave Mode Configuration 0 II n 148 Figure 26 Format in the master transmitter mode 0 2 00 cece ee 149 Figure 27 Format of master receiver MOde ooocoococoo e 149 Figure 28 A master receiver switch to master transmitter after sending repeated START 150 Figure 29 Slave Mode Configuration s a sssaaa aeaaaee cette eee 150 Figure 30 Format of slave receiver Mode 0 ec tte ae 151 Figure 31 Format of slave transmitter mode 0 0 0 cette eee 151 Figure 32 126 Architecture 2 cacti dl phe eh TE bee ao Sg Gate vee ayer 158 Figure 33 SPI Data Transfer Format CPHA 0 and CPHA 1 0 0 0 eee eee 160 Figure 34 SPI Block Diagram rnain e k e E a a E a e a EOE SEEE D RALE EOE OnE a 167 Figure 35 A timer cycle in which PR 2 MRx 6 and both interrupt and reset on match are enabled 176 Figure 36 A timer cycle in which
307. ure the voltage on any AIN pin regardless of the pin s setting in the Pin Select register Pin Connect Block on page 109 selecting the AIN function improves the conversion accuracy by disabling the pin s digital receiver A D Converter 195 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 A D Converter 196 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 17 REAL TIME CLOCK FEATURES Measures the passage of time to maintain a calendar and clock Ultra Low Power design to support battery powered systems Provides Seconds Minutes Hours Day of Month Month Year Day of Week and Day of Year Programmable Reference Clock Divider allows adjustment of the RTC to match various crystal frequencies DESCRIPTION The Real Time Clock RTC is designed to provide a set of counters to measure time during system power on and off operation The RTC has been designed to use little power making it suitable for battery powered systems where the CPU is not running continuously Idle mode Real Time Clock 197 May 03 2004 Philips Semiconductors ARM based Microcontroller ARCHITECTURE Clock Generator Time Counters Counter Enables REGISTER DESCRIPTION Preliminary User Manual LPC2114 2124 2212 2214 Reference Clock Divider Prescaler Interrupt Enable Comparators Counte
308. used reserved bits are marked with and represented as gray fields Access to them is restricted as already described Table 2 LPC2114 2124 2212 2214 Registers Address Offset WD WD Watchdog WD WD WDRE Description Watchdog oxE0000004 wprc met 32 bit data R W OxFF constant register Watchdog 0xE0000008 Teed 8 bit data OxAA fallowed by 0x55 WO NA sequence register Introduction 20 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Table 2 LPC2114 2124 2212 2214 Registers Address Cet Offset Name Description Access Watchdog OxE000000C WDTV timer value 32 bit data RO register TIMERO oxE0004000 TOIR TO Interrupt CR3 CR2 CR1 CRO MR3 MR2 MR1 MRO R W Register Int Int Int Int Int Int Int Int 0xE0004004 ToTcR 10 Control GTR SADA ES Register Reset Enable 0xE0004008 TOTC 32 bit data oxEooo400C ToPR 10 Prescale 32 bit data Register oxEo004010 Topc 10 Prescale 32 bit data CIEN Counter Stop Reset Stop i Int on 4 reserved bits on on MR3 on TO Match MR3 MR3 MR2 0xE0004014 TOMCR Control R W Register T Int on p ben Int on MEM MRO MRO MRO 0xE0004018 Tomro 10 Match 32 bit data R W Register 0 0xE000401C TomR1 10 Match 32 bit data R W Register 1 0xE0004020 Tomre 10 Match 32 bit data R W Register 2 0xE0004024 ToMRa 10 Match 32 bit data R W Register 3 Int on 4
309. used if the system can guarantee that FIQs are never disabled while IRQs are enabled It does not address problem one Vectored Interrupt Controller VIC 90 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 VIC USAGE NOTES If user s code is runing from the on chip RAM and an aplication uses interrupts interrupt vectors must be re mapped to flash address 0x0 This is necessary because all the exception vectors are located at addresses 0x0 and above This is easily achieved by configuring MEMMAP register located in System Control Block to User RAM mode Application code should be linked such that at 0x4000 0000 the Interrupt Vector Tabe IVT will reside Although multiple sources can be selected VICIntSelect to generate FIQ request only one interrupt service routine should be dedicated to service all available present FIQ request s Therefore if more than one interrupt sources are classified as FIQ the FIQ interrupt service routine must read VICFIQStatus to decide based on this content what to do and how to process the interrupt request However it is recommended that only one interrupt source should be classified as FIQ Classifying more than one interrupt sources as FIQ will increase the interrupt latency Following the completion of the desired interrupt service routine clearing of the interrupt flag on the peripheral level will propagate to corresponding bits in VIC register
310. ve serial data is output on this signal When MISO1 MISOO vp e ores RM a device is a master serial data is input on this signal When a slave device is not selected the When a device is a slave serial data is input on this signal SPI Interface 163 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 REGISTER DESCRIPTION The SPI contains 5 registers as shown in Table 115 All registers are byte half word and word accessible Table 115 SPI Register Map Generic Reset SPI SEN Name Description Address amp Address amp Value Name Name SPI Control Register This register controls the operation of 0 0xE0020000 0xE0030000 the SPI SOSPCR S1SPCR Read 0xE0020004 0xE0030004 SPSR SPI Status Register This register shows the status of the SPI EMEN SOSPSR S1SPSR SPCR the SPI can be read from this register SPCCR SPI Clock Counter Register This register controls the Read 0xE002000C 0xE003000C frequency of a master s SCK Write SOSPCCR S1SPCCR SPINT SPI Interrupt Flag This register contains the interrupt flag for Read 0xE002001C 0xE003001C the SPI interface Write SOSPINT S1SPINT Reset Value refers to the data stored in used bits only It does not include reserved bits content SPI Data Register This bi directional register provides the transmit and receive data for the SPI Transmit data is Read 0xE0020008 0xE0030008 provided to
311. vidual peripheral functions Allowing elimination of power consumption by peripherals that are not needed Power Control Register PCON 0xE01FCOCO The PCON register contains two bits Writing a one to the corresponding bit causes entry to either the Power Down or Idle mode If both bits are set Power Down mode is entered Table 30 Power Control Register PCON 0xE01FCOCO PCON Function Description Idle mode when 1 this bit causes the processor clock to be stopped while on chip IDL peripherals remain active Any enabled interrupt from a peripheral or an external interrupt source will cause the processor to resume execution 0 Power Down mode when 1 this bit causes the oscillator and all on chip clocks to be 1 stopped A wakeup condition from an external interrupt can cause the oscillator to re start the PD bit to be cleared and the processor to resume execution Reserved user software should not write ones to reserved bits The value read from a 7 2 Reserved m i NA reserved bit is not defined System Control Block 66 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 Power Control for Peripherals Register PCONP 0xE01FC0C4 The PCONP register allows turning off selected peripheral functions for the purpose of saving power A few peripheral functions cannot be turned off i e the Watchdog timer GPIO the Pin Connect block and the System Control
312. w control scheme ISP Command Abort Commands can be aborted by sending the ASCII control character ESC This feature is not documented as a command under ISP Commands section Once the escape code is received the ISP command handler waits for a new command Interrupts during ISP Boot block Interrupt vectors located in the boot sector of the flash are active after any reset Interrupts during IAP The on chip flash memory is not accessible during erase write operations When the user application code starts executing the interrupt vectors from the user flash area are active The user should either disable interrupts or ensure that user interrupt vectors are active in RAM and that the interrupt handlers reside in RAM before making a flash erase write IAP call The IAP code does not use or disable interrupts Flash Memory System and Programming 219 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 RAM used by ISP command handler ISP commands use on chip RAM from 0x4000 0120 to 0x4000 01FF The user could use this area but the contents may be lost upon reset Flash programming commands use the top 32 bytes of on chip RAM The stack is located at RAM top 32 The maximum stack usage is 256 bytes and it grows downwards RAM used by IAP command handler Flash programming commands use top 32 bytes of on chip RAM The maximum stack usage in the user allocated stack space is 128 b
313. wever valid analog reading s can be obtained if and only if the function of an analog input is selected Only in this case proper interface circuit is active in between the physical pin and the A D module In all other cases a part of digital logic necessary for the digital function to be performed will be active and will disrupt proper behavior of the A D Table 69 GPIO Pin Value Register IOOPIN 0xE0028000 IO1PIN 0xE0028010 IO2PIN 0xE0028020 IO3PIN 0xE0028030 Value after Reset GPIO pin value bits Bit 0 in IOOPIN corresponds to P0 0 Bit 31 in IOOPIN corresponds to P0 31 Undefined Description GPIO Output Set Register IOOSET 0xE0028004 IO1SET 0xE0028014 IO2SET 0xE0028024 IO3SET 0xE0028034 This register is used to produce a HIGH level output at the port pins if they are configured as GPIO in an OUTPUT mode Writing 1 produces a HIGH level at the corresponding port pins Writing O has no effect If any pin is configured as an input or a secondary function writing to IOSET has no effect Reading the IOSET register returns the value of this register as determined by previous writes to IOSET and IOCLR or IOPIN as noted above This value does not reflect the effect of any outside world influence on the I O pins Table 70 GPIO Output Set Register IOOSET 0xE0028004 IO1SET 0xE0028014 IO2SET 0xE0028024 IO3SET 0xE0028034 Value after Description Reset Output value SET bits Bi
314. xcept in level sensitive mode when the pin is in its active state is in its active state In level sensitive mode this bit is set if the EINT3 function is selected for its pin and the pin is in its active state In edge sensitive mode this bit is set if the EINT3 function is selected for its pin and the selected edge occurs on the pin Up to three pins can be selected to perform EINT3 function see P0 9 P0 20 and P0 30 description in Pin Configuration chapter This bit is cleared by writing a one to it except in level sensitive mode when the pin is in its active state Reserved user software should not write ones to reserved bits The value read 7 4 Reserved qu NA from a reserved bit is not defined External Interrupt Wakeup Register EXTWAKE 0xE01FC144 In level sensitive mode this bit is set if the EINT2 function is selected for its pin and the pin is in its active state In edge sensitive mode this bit is set if the EINT2 function is selected for its pin and the selected edge occurs on the pin Up to two pins can be selected to perform EINT2 function see P0 7 and P0 15 description in Pin Configuration chapter This bit is cleared by writing a one to it except in level sensitive mode when the pin Enable bits in the EXTWAKE register allow the external interrupts to wake up the processor if it is in Power Down mode The related EINTn function must be mapped to the pin in order for the wakeup process to take p
315. y 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 12C SCL Duty Cycle Registers I2SCLH 0xE001C010 and I2SCLL 0xE001C014 Software must set values for registers I2SCLH and I2SCLL to select the appropriate data rate I2SCLH defines the number of pclk cycles for SCL high IPSCLL defines the number of pclk cycles for SCL low The frequency is determined by the following formula Bit Frequency fo I2SCLH I2SCLL Where fc x is the frequency of pclk The values for I2SCLL and I2SCLH don t have to be the same Software can set different duty cycles on SCL by setting these two registers But the value of the register must ensure that the data rate is in the 12C data rate range of 0 through 400KHz So the value of I2SCLL and I2SCLH has some restrictions Each register value should be greater than or equal to 4 Table 108 I2C SCL High Duty Cycle Register I2SCLH 0xE001C010 Reset I2SCLH Function Description Value 15 0 Count Count for SCL HIGH time period selection Ox 0004 Table 109 I C SCL Low Duty Cycle Register I2SCLL 0xE001C014 Reset I2SCLL Function Description Value 15 0 Count Count for SCL LOW time period selection Ox 0004 Table 110 I2C Clock Rate Selections for VPB Clock Divider 1 I2SCLL Bit Frequency kHz At fcc x MHz amp VPB Clock Divider 1 I2SCLH poe a a HEBEL H Za t E s ms me
316. ytes and it grows downwards RAM used by RealMonitor The RealMonitor uses on chip RAM from 0x4000 0040 to 0x4000 011F The user could use this area if RealMonitor based debug is not required The Flash boot loader does not initialize the stack for the RealMonitor Flash Memory System and Programming 220 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 BOOT PROCESS FLOWCHART Initialize WatchDog Yes Flag Set User Code nter ISP Valid Mode P0 14 LOW Auto Baud Successful Receive crystal frequency Run ISP Command Handler Figure 44 Boot Process flowchart Bootloader revisions before 1 61 Flash Memory System and Programming 221 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 CRP Enabled Yes WatchDog Yes Flag Set Enable Debug Boot External Enter ISP Ye User Code Valid CRP Enabled Ye Execute External Execute Internal User code User code S S Run Auto Baud Auto Baud Successful Yes Receive crystal frequency Run ISP Command Handler Figure 45 Boot Process flowchart Bootloader revisions 1 61 and later Code Read Protection Flash Memory System and Programming 222 May 03 2004 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2114 2124 2212 2214 SECTOR NUMBERS Some IAP and ISP commands operate on

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