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DM7820/DM9820 User`s Manual

1. Pin PORTx PERIPH SEL 00 01 10 11 Port1 4 FIFOO Out 4 FIFO1 Out 4 Port1 5 FIFOO Out b FIFO1 Out 5 Port1 6 FIFOO Out 6 FIFO1 Out 6 Port1 7 FIFOO Out 7 FIFO1 Out 7 Port1 8 FIFOO Out 8 FIFO1 Out 8 Port1 9 FIFOO Out 9 FIFO1 Out 9 Port1 10 FIFOO Out 10 FIFO1 Out 10 Port1 11 FIFOO Out 11 FIFO1 Out 11 Port1 12 FIFOO Out 12 FIFO1 Out 12 Port1 13 FIFOO Out 13 FIFO1 Out 13 Port1 14 FIFOO Out 14 FIFO1 Out 14 Port1 15 FIFOO Out 15 FIFO1 Out 15 Port2 0 PWMO A FIFOO Out 0 FIFO1 Out 0 Port2 1 PWMO_A FIFOO Out 1 FIFO1 Out 1 Port2 2 PWMO B TC AO OUT FIFOO Out2 FIFO1 Out 2 Port2 3 PWMO B TC A1 OUT FIFOO Out 3 FIFO1 Out 3 Port2 4 PWMO C TC A2 OUT FIFOO Out4 FIFO1 Outj4 Port2 5 PWMO C TC BO OUT FIFOO Out 5 FIFO1 Out 5 Port2 6 PWMO D TC B1 OUT FIFOO Out 6 FIFO1 Out 6 Port2 7 PWMO D TC B2 OUT FIFOO Out7 FIFO1 Out 7 Port2 8 PWM1 A ProgClkO OUT FIFOO Out8 FIFO1 Out 8 Port2 PWM1 A ProgClk1 OUT FIFOO Out9 FIFO1 Out 9 Port2 10 PWM1 B ProgCik2 OUT FIFOO Out 10 FIFO1 Out 10 Port2 11 PWM1 B ProgCIk3 OUT FIFOO Out 11 FIFO1 Out 11 Port2 12 PWM1 C Strobe1 pos FIFOO Out 12 FIFO1 Out 12 Port2 13 PWM1 C Strobe2 pos FIFOO Out13 FIFO1 Out 13 Port2 14 PWM1 D Strobe1 neg FIFOO Out 14 FIFO1 Out 14 Port2 15 PWM1 D Strobe2 neg FIFOO Out 15 FI
2. PORTx_PERIPH_SEL_H This register selects the peripheral for Port 0 Port 1 or Port 2 when it is a peripheral output i e PORTx_MODE 1 This register selects the peripheral for bits 15 8 15 14 13 12 11 10 9 Px_15 Px_14 Px_13 Px_12 RW 00 RW 00 RW 00 RW 00 7 6 5 4 3 2 1 Px 11 Px 10 Px 9 Px 8 RW 00 RW 00 RW 00 RW 00 Table 5 Peripheral Outputs Pin PORTx_PERIPH_SEL 00 01 10 11 PortO 0 FIFOO Out 0 FIFO1 Out 0 Port0 1 FIFOO Out 1 FIFO1 Out 1 PortO 2 FIFOO Out 2 FIFO1 Out 2 PortO 3 FIFOO Out 3 FIFO1 Out 3 PortO 4 FIFOO Out 4 FIFO1 Out 4 PortO 5 FIFOO Out 5 FIFO1 Out 5 Port0 6 FIFOO Out 6 FIFO1 Out 6 PortO 7 FIFOO Out 7 FIFO1 Out 7 Port0 8 FIFOO Out 8 FIFO1 Out 8 PortO 9 FIFOO Out 9 FIFO1 Out 9 Port0 10 FIFOO Out 10 FIFO1 Out 10 PortO 11 FIFOO Out 11 FIFO1 Out 11 Port0 12 FIFOO Out 12 FIFO1 Out 12 Port0 13 FIFOO_Out 13 FIFO1 Out 13 Port0 14 FIFOO Out 14 FIFO1 Out 14 Port0 15 FIFOO Out 15 FIFO1 Out 15 Port1 0 FIFOO Out 0 FIFO1 Out 0 Port1 1 FIFOO Out 1 FIFO1 Out 1 Port1 2 FIFOO_Out 2 FIFO1 Out 2 Port1 3 FIFOO_Out 3 FIFO1 Out 3 DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 33 Table 5 Peripheral Outputs
3. RC 0 RW 0 Field Description INT STAT 7 0 Interrupt Status 1 Interrupt condition has occurred Write 1 to clear Interrupts are asserted on the positive edge of the clock INT_ENA 7 0 Interrupt Enable 1 Interrupt is enabled 0 disabled Interrupt source are 7 Reserved Reserved Underflow Overflow Empty Full Write Request Read Request OANWAOO FIFOn_IN_CLK This register selects the input clock to the FIFO At every positive edge of the input clock a word is read into the FIFO from the input source 15 5 4 0 Reserved CLOCK_SEL 4 0 R 0 RW 0 Field Description CLOCK_SEL 4 0 Selects the input clock input to this FIFO channel Value definitions are 31 PCI Write to FIFOn RW PORT 30 PCI Read from FIFOn RW PORT 29 Prog Clock 3 Interrupt 28 Prog Clock 2 Interrupt 27 Prog Clock 1 Interrupt 26 Prog Clock 0 Interrupt 25 PWM1 Interrupt 24 PWMO Interrupt 23 Reserved 22 Reserved 21 Incremental Encoder 1 Interrupt 20 Incremental Encoder 0 Interrupt 19 Reserved 18 82C54 Interrupt 17 Advanced Interrupt 1 Interrupt 16 Advanced Interrupt 0 Interrupt 15 Inverted Strobe2 14 Inverted Strobe1 13 Strobe2 12 Strobe1 11 Prog Clock 3 DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 38 Field Description 10 Prog Clock 2 Prog Clock 1 Prog Clock 0 82C54 TC B2 82C54 TC B1
4. 0x024E Reserved E ADVINT1_PORTO_CMP CO 15 0 Port 0 Compare Value used for interrupt on match e ADVINT1 PORT1 CMP b 15 0 Port 1 Compare Value used for interrupt on match AN ADVINT1 PORT2 CMP b 15 0 Port 2 Compare Value used for interrupt on lt 0x0256 Reserved register when an interrupt occurs EE register when an interrupt occurs 0x025C ADVINT1 PORT2 CAPT b 15 0 Port 2 Capture Value on Port 2 is written to this E on when an interrupt occurs 0x025E Reserved a Incremental Encoder 0 0x0280 INCENCO_ID b 15 0 ID Register 0x0002 0x0282 INCENCO_INT b 11 8 Interrupt Status 1 Interrupt condition has occurred Write 1 to clear b 3 0 Interrupt Enable 1 Interrupt is enabled 0 disabled Interrupt source are 3 Encoder B Negative Rollover 2 Encoder B Positive Rollover 1 Encoder A Negative Rollover O Encoder A Positive Rollover 0x0284 INCENCO CLOCK b 3 0 Master Clock Source 15 0 Clock Bus 15 0 0x0286 INCENCO MODE b 15 8 Phase Filter Writing a 1 to a specific bit masks out a phase transition b 7 6 Reserved b 5 Differential Mode 1 Pseudo differential mode 0 Single ended mode b 4 Input Filter 1 Enable Input Filter 0 Disable Input Filter b 3 Join 1 Operate as single 32 bit Encoder 0 Operate as two 16 bit Encoders b 2
5. 1 External Index is enabled b 1 Hold Register 1 Hold values register 0 Allow value register to change b 0 Count Enable 1 Encoder is enabled 0 Encoder is cleared Pulse Width Modulator 0 0x0302 PWMO MODE b 0 1 Enable PWM 0 Disable PWM 0x0304 PWMO_CLK b 7 4 Period Clock Source 15 0 Clock_Bus 15 0 b 3 0 Width Clock Source 15 0 Clock_Bus 15 0 E 0x0306 0x0308 PWMO PERIOD b 15 0 Period of PWM Cycle is Width _ Clock _ Frequency PWMx PERIOD 1 0x030A Reserved E 0x0310 PWMO_WIDTHA______ b 15 0 Width of output A pulse in Period Clock cycles 0x0312 Resered 0x0314 PWMO WIDTHB b 15 0 Width of output B pulse in Period Clock cycles 0x0316 Reserved AA 0x0318 PWMO_WIDTHC b 15 0 Width of output C pulse in Period Clock cycles 0x031A_ Reserved LI DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 25 Table 4 DM7820 DM9820 Memory Map Offset Register Name Register Function Hex Ox031E Reseved OT Pulse Width Modulator 1 0x0342 PWM1 MODE b 0 T Enable PWM 0 Disable PWM 0x0344 PWM1 CLK b 7 4 Period Clock Source 15 0 Clock Bus 15 0 b 3 0 Width Clock Source 15 0 Clock Bus 15 0 0x0346 Reserved 0x0348 PWM1_PERIOD b 15 0 Period of PWM Cycle is Width _ Clock _ Frequency PWMx _ PERIOD 1 d n ER d fs NEM RCRUM _0x03
6. H GATE L f OUT H Mode 5 GATE f OUT EE 1 RS GATE f f p E 8 951 4 8940 ura EE Note n is the value set in the counter Figures in these diagrams refer to counter values Reading Counter Values All MSM82C54 2 counting is down counting the counting being in steps of 2 in mode 3 Counter values can be read during counting by 1 direct reading 2 counter latching read on the fly and 3 read back command Direct reading Counter values can be read by direct reading operations Since the counter value read according to the timing of the RD and CLK signals is not guaranteed it is necessary to stop the counting by a gate input signal or to interrupt the clock input temporarily by an external circuit to ensure that the counter value is correctly read Counter latching In this method the counter value is latched by writing counter latch command thereby enabling a stable value to be read without effecting the counting in any way at all The output latch OL of the selected counter latches the count value when a counter latch command is written The count value is held until it is read by the CPU or the control word is set again If a counter latch command is written again before reading while a certain counter is latched the second counter latch command is ignored and the value latched by the first counter latch command is maintained DM7820 DM9820 User s Manua
7. Prog Clock 0 Start Event Advint0 One Shot Data In any Data in clock Prog Clock 0 Data out clock Prog Clock 2 before AdvIntO Data out clock PCI Read after Adv IntO DReq0 Read Ready DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 15 Board Operation and Programming PCI Interface This board attaches to the PCI bus using a PLX PCI9056 The PCI9056 is operating in C Mode Most of the registers in the PLX chip are automatically programmed at power up by the on board EEPROM or by the system BIOS The only PLX registers that the user needs to access are the DMA registers found on page 66 and the Configuration Registers found in Table 3 below For more information on the PLX PCI9056 bridge chip contact PLX Technologies www plxtech com Table 3 PCI Configuration Registers PCI Config Register Name Register Address Hex 0x04 PCI Status PClCommand 0x10 PCI Base Address Register 0 Memory Access to PLX9056 Registers 0xi4 PCIBase Address Register 1 WO Access to PLX9056 Registers 0xi8 PCI Base Address Register 2 Memory Access to Digital lO Registers 0x20 Reserved o 0x24 PR 0x28 Reserved ooo 0x30 Reseved OOOO 0x34 Reserved Reserved 0x38 AE Device Memory The DM7820 DM9820 is a memory mapped device The address for the memory mapped registers can be found in Base Address Register
8. Each level must be enabled in the previous level Figure 3 shows a block diagram of the interrupt sources Note that there are some other sources in the PLX bridge chip consult the datasheet for more details DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 13 DMA Channel 0 Done D QL J KEN i y 3m x DMAMODEOQ 10 STATI DMA Channel One INTCSR 18 DG j DMAMODEQ 17 v D rz DMAPRO 2 x_ENAI a DMA Channel 1 Done y 0c D Q Ei bes 1 FE a J D Q DMAMODE1 10 DMA Channel 1 TC INTCSRT 9 Dg Jr DMAMODE1 17 INT_STAT 16 0 DMAPR1 2 Da Da al INT_ENA 16 0 CNTRL 20 Modules Control Block PLX Figure 3 Interrupt Diagram Advanced Triggering Examples The modules on the DM7820 DM9820 can be combined to generate a broad range of complex sampling scenarios The following example shows how to use the Advanced Interrupt and 4 counters to capture N words before and M words after an event Programmable Clock 0 is the sample clock and is used to clock data into the FIFO It is started after all of the other Programmable clocks are initialized As soon as it starts Programmable Clock 1 starts counting samples to be captured before the triggering event This is also known as pre fill When it expires it starts Programmable Clock 2 which r
9. The transfer may be complete either because the DMA transfer finished successfully or that the DMA transfer was aborted when software set the Abort bit DMACSRO 2 1 Reading 0 indicates the Channel transfer is not complete 7 5 Reserved Yes No 000b 000b DMAARB DMA Arbitration Bit Description Read Write Value Value after to Use Reset 18 0 Reserved Yes Do not 0 0 Modify 20 19 DMA Channel Priority Writing 00b indicates a Yes Yes 00b 00b rotational priority scheme Writing 01b indicates Channel 0 has priority Writing 10b indicates Channel 1 has priority Value of 11b is reserved 31 21 Reserved Yes Do not 0000 0000 Modify 0000 0011 001b 001b DMATHR DMA Threshold Bit Description Read Write Value Value after to Use Reset 3 0 DMA Channel 0 PCI to Local Almost Full Yes Yes Oh D COPLAF Number of full Lword x 2 entries plus 1 times 2 in the FIFO before requesting the Local Bus for writes Nybble values Oh through Eh may be used Refer to Table 12 15 COPLAF gt COLPAE DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 71 7 4 DMA Channel 0 Local to PCI Almost Empty Yes Yes Oh x COLPAE Number of empty Lword x 2 entries plus 1 times 2 in the FIFO before requesting the Local Bus for reads Nybble values Oh through Eh may be used Refer to Table 12 15 COPLAF gt COLPAE 11 8 DMA Channel 0 Local to PCl Almost Full Yes Yes
10. b 15 13 Reserved b 12 8 Stop Clock 31 16 Interrupt_Bus 15 0 15 1 Clock_Bus 15 1 0 No Stop Clock b 7 5 Reserved b 4 0 Start Trigger 31 16 Interrupt_Bus 15 0 15 1 Clock_Bus 15 1 0 Start Immediate 0x0188 PRGCLK2_PERIOD b 15 0 Period of Clock Output frequency is Master _ Clock _ Frequency PRG _CLK _ PERIOD 1 Programmable Clock 3 0x01CO PRGCLK3 ID b 15 0 ID Register 0x1000 0x01C2 PRGCLK3 MODE b 15 2 Reserved b 1 0 00 Disabled 01 Continuous 10 Reserved 11 One Shot 0x01C4 PRGCLK3 SOURCE b 15 4 Reserved b 3 0 Master Clock Source 15 0 Clock_Bus 15 0 0x01C6 PRGCLK3_START_STOP b 15 13 Reserved b 12 8 Stop Clock 31 16 Interrupt_Bus 15 0 15 1 Clock_Bus 15 1 0 No Stop Clock b 7 5 Reserved b 4 0 Start Trigger 31 16 Interrupt_Bus 15 0 15 1 Clock_Bus 15 1 0 Start Immediate 0x01C8 PRGCLK3 PERIOD b 15 0 Period of Clock Output frequency is Master _ Clock _ Frequency PRG _CLK _ PERIOD 1 Advanced Interrupt 0 0x0200 ADVINTO ID b 15 0 ID Register 0x0001 DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 22 Table 4 DM7820 DM9820 Memory Map Offset Register Name Register Function Hex ADVINTO_INT_MODE b 1 0 Interrupt Mode 3 Event Mode 2 Match Mode 1 Strobe Mode Disabled 0 0x0204 ADVINTO_CLK b 3 0 Sample Clock Source 15 0 Clock_Bus 15 0 0x0206 0x0208 ADVINTO PORTO MASK b 15 0 Por
11. 0 Selection 01 Counter 1 Selection 10 Counter Z2 Selection 11 Read Back Command Table 8 Read Load RL 1 0 Count Value Reading Loading format setting RL 1 0 Set Contents 00 Counter Latch Operation 01 Reading Loading of Least Significant Byte LSB 10 Reading Loading of Most Significant Byte MSB 11 Reading Loading of LSB followed by MSB Table 9 Mode M 2 0 Operation waveform mode setting M 1 0 Set Contents Min Count Max Count Value Value 000 Mode 0 Interrupt on Terminal Count 1 0 001 Mode 1 Programmable One Shot 1 0 x10 Mode 2 Rate Generator 2 0 x11 Mode 3 Square Wave Generator 2 0 100 Mode 4 Software Triggered Strobe 1 0 101 Mode 5 Hardware Triggered Strobe 1 0 x denotes not specified Count value of 0 executed 0x10000 count DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 56 Table 10 BCD Operation count mode setting BCD Set Contents 0 Binary Count 16 bit Binary 1 BCD Count 4 decade Binary Coded Decimal After setting Read Load Mode and BCD in each counter as outlined above next set the desired count value In some Modes the count value is set first In next clock loading is performed and then counting starts This count value setting must conform to the Read Load format set in advance Note that the internal counters are reset to OOOOH during control word setting The counter
12. 11 9 P2 10 11 P2 9 13 P2 8 15 P1 15 17 P1 14 19 P1 13 21 P1 12 23 P1 11 25 P1 10 27 P1 9 29 P1 8 31 Pin Signal 2 Strobe1 4 GND 6 GND 8 GND 10 GND 12 GND 14 GND 16 GND 18 GND 20 GND 22 GND 24 GND 26 GND 28 GND 30 GND 32 GND RTD Embedded Technologies Inc 7 Table 2 CN11 Pin Assignments Signal Pin Pin Signal P1 7 GND P1 6 GND P1 5 GND P1 4 GND P1 3 GND P1 2 GND P1 1 GND P1 0 GND 5V 2A max GND See Table 5 and Table 6 for peripheral pin assignments PC 104 ISA Connectors DM7820 The PC 104 connectors carry the signals of the PC 104 Plus ISA bus Refer to PC 104 Plus Specification Revision 1 0 for the pinout of this connector This is a pass through connector The DM7820 connects to the power and ground pins only and does not use any of the signals PC 104 Express Bus Connectors DM9820 The PC 104 Express connectors provide the PCI Express bus connections CN1 is on the top and CN2 is on the bottom Refer to the PC 104 Express Specification Revision 1 0 for the pinout of these connectors The DM9820 connects to one of the PCle x1 links on the PCle bus connector and passes through the x16 link It will automatically detect the direction to the host so it can be stacked above or below the CPU PC 104 Plus PCI Connector The
13. 11 10 9 8 FIFO1 FIFOO PCIK3 PCIK2 PClk1 PCIKO PWM1 PWMO RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Reserved IncEnc1 IncEncO Rsvd 82C54 Advint1 AdvintO R 00 RW 0 RW 0 R 0 RW 0 RW 0 RW 0 Field Description Advint0 Interrupt from Advance Interrupt block at 0x0200 0 Interrupt Disabled 1 Interrupt Enabled Advint1 Interrupt from Advance Interrupt block at 0x0240 0 Interrupt Disabled 1 Interrupt Enabled 82C54 Interrupt 82C54 Timer Counter block at 0x0080 0 Interrupt Disabled 1 Interrupt Enabled IncEncO Interrupt from Incremental Encoder block at 0x0280 0 Interrupt Disabled 1 Interrupt Enabled IncEnc1 Interrupt from Incremental Encoder block at 0x02CO0 0 Interrupt Disabled 1 Interrupt Enabled PWMO Interrupt from Pulse Width Modulator block at 0x0300 0 Interrupt Disabled 1 7 Interrupt Enabled DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 28 PWM1 Interrupt from Pulse Width Modulator block at 0x0340 0 Interrupt Disabled 1 Interrupt Enabled PCIKO Interrupt from Programmable Clock block at 0x0100 0 Interrupt Disabled 1 Interrupt Enabled PCIk1 Interrupt from Programmable Clock block at 0x0140 0 Interrupt Disabled 1 Interrupt Enabled PCIK2 Interrupt from Programmable Clock block at 0x0180 0 Interrupt Disabled 1 Interrupt Enabled PCIK3 Interrupt from Programmable Clock block a
14. 24 digital input output lines along with a 5V pin and ground pins The pin assignments for CN10 are shown in Table 1 Note Pin 1 can be identified by a square solder pad Pins 2 50 have round solder pads Table 1 CN10 Pin Assignments Signal Signal P2 7 Strobe2 P2 6 GND P2 5 GND P2 4 GND P2 3 GND P2 2 GND DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 6 Table 1 CN10 Pin Assignments Signal Pin P2 1 P2 0 PO 15 PO 14 PO 13 PO 12 PO 11 PO 10 PO 9 PO 8 PO 7 PO 6 PO 5 PO 4 PO 3 PO 2 PO 1 PO 0 5V 2A max Pin Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND See Table 5 and Table 6 for peripheral pin assignments Connector CN11 Digital Input Output Connector CN11 provides 24 digital input output lines along with a 5V pin and ground pins The pin assignments for CN11 are shown in Table 2 Note Pin 1 can be identified by a square solder pad Pins 2 50 have round solder pads Table 2 CN11 Pin Assignments DM7820 DM9820 User s Manual Signal Pin P2 15 1 P2 14 3 P2 13 5 P2 12 7 P2
15. 5 Port0 13 Port1 5 Port1 13 INCENCn_ID ID register to identify this block 15 0 ID_Register R Field Description ID_Register15 0 Value of 0x0002 indicates Dual Incremental Encoder DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 49 INCENCn_INT This register provides the status and enables for the encoder interrupts 15 12 11 10 9 8 Reserved STAT B NEG STAT B POS STAT A NEG STAT A POS R 0 RC 0 RC 0 RC 0 RC 0 3 2 1 0 Reserved ENA B NEG ENA B POS ENA A NEG ENA A POS R 0 RW 0 RW 0 RW 0 RW 0 Field Description STAT_B_NEG Indicates channel B has transitioned from 0x0000 to OxFFFF Negative rollover 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear STAT_B_POS Indicates channel B has transitioned from OxFFFF to 0x0000 Positive rollover 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear STAT_A_NEG Indicates channel A has transitioned from 0x0000 to OxFFFF Negative rollover 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear STAT_A_POS ENA B NEG Indicates channel A has transitioned from OxFFFF to 0x0000 Positive rollover 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to c
16. 82C54 TC BO 82C54 TC A2 82C54 TC A1 82C54 TC A0 Reserved 25 MHz OO N Q P O1 O OO oO FlIFOn OUT CLK This register selects the output clock to the FIFO At every positive edge of the output clock a new word available at the FIFO output 15 5 4 0 Reserved CLOCK SEL 4 0 R 0 RW 0 Field CLOCK SEL 4 0 Description Value definitions are 31 PCI Write to FIFOn RW PORT Selects the input clock input to this FIFO channel 30 PCI Read from FIFOn RW PORT 29 Prog Clock 3 Interrupt 28 Prog Clock 2 Interrupt 27 Prog Clock 1 Interrupt 26 Prog Clock 0 Interrupt 25 PWM1 Interrupt 24 PWMO Interrupt 23 Reserved 22 Reserved 21 Incremental Encoder 1 Interrupt 20 Incremental Encoder 0 Interrupt 19 Reserved 18 82C54 Interrupt 17 Advanced Interrupt 1 Interrupt 16 Advanced Interrupt O Interrupt 15 Inverted Strobe2 14 Inverted Strobe1 13 Strobe2 12 Strobe1 11 Prog Clock 3 10 Prog Clock 2 Prog Clock 1 Prog Clock 0 82C54 TC B2 82C54 TC B1 82C54 TC BO OO Jo o DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 39 Field Description 82C54 TC A2 82C54 TC A1 82C54 TC AO Reserved 25 MHz OANWA FIFOn IN DATA DREQ This register selects the FIFO data input and PLX DMA Request source For the Write Request and Read Request signals internal buffers are monitored to signal when data can be sent i
17. Boot the system and verify that all of the hardware is working properly Note f multiple PCI devices are configured to use the same PCI slot number the system will not boot DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 10 Installing Software Drivers are required to use the DM7820 DM9820 They are provided along with example programs on the CD that ships with the board and are also available from the RTD website www rtd com For further information on installing the drivers review README TXT in the driver archive file DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 11 Functional Overview Internal Architecture A diagram of the standard I O is shown in Figure 4 Each digital I O pin can be an input output or peripheral output The peripheral outputs are the Pulse Width Modulators FIFO Timer Counters etc Peripheral 3 Peripheral 2 1 Peripheral 1 Peripheral O PENS D Q 0 ao PORTx_OUTPUT a PORTx_PERIPH_SEL PORTx_TRISTATE D qac PORTx_MODE Q D Data Readback PORTx INPUT Figure 2 Digital UO Block Diagram FIFOs The DM7820 DM9820 provides two FIFOs to buffer data going into and out of the board Each FIFO is 16 bit wide and 2 097 661 Words deep The input strobe output strobe and data input for each FIFO can be individually selected The output data is made available to the peripheral outpu
18. DM9820 Memory Map Offset Register Name Register Function Hex 0x00CO FIFOO ID b 15 0 ID Register 0x2011 0x00C2 FIFOO_INT b 15 8 Interrupt Status 1 Interrupt condition has occurred Write 1 to clear b 7 0 Interrupt Enable 1 Interrupt is enabled 0 disabled Interrupt source are 7 Reserved 6 Reserved Underflow Overflow Empty Full Write Request Read Request 0x00C4 FIFOO_IN_ CLK b 15 5 Reserved b 4 0 Input Clock Select 31 PCI Write 30 PCI Read 29 16 Interrupts 13 0 15 0 Clock_Bus 15 0 0x00C6 FIFOO_OUT_CLK b 15 5 Reserved b 4 0 Input Clock Select 31 PCI Write 30 PCI Read 29 16 Interrupts 13 0 15 0 Clock_Bus 15 0 0x00C8 FIFOO_IN_DATA_DREQ b 15 10 Reserved b 9 8 DREQO Source 3 Not Full 2 Write Request 1 Not Empty 0 Read Request b 7 4 Reserved b 3 0 Input Data Select 3 FIFOO Output 2 Port2 1 PortO O PCI Data Ox00CA FIFOO_CON_STAT b 15 10 Reserved b 9 Write Request non sticky b 8 Read Request non sticky b 7 1 Reserved b 0 1 Enable 0 Clear 0x00CC FIFOO_RW_PORT b 15 0 Read Write Port Word access only FIFO Channel 1 0x00DO FIFO1_ID b 15 0 ID Register 0x2011 DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 19 Table 4 DM7820 DM9820 Memory Map Offset Register Name Register Function Hex 0x00D2 FIFO1_INT b 15 8 Interrupt Status 1 Interrupt co
19. DMAARB ee toos scan IP M kic erdum i Sr E cadera 71 DMA TAR 2 0 erii UP bunen met Mi edit Db 71 DMADAT E E eg leie dee ee BEER 73 d MR 73 Additional Information 5 2 tt eater dtd tna ec ete etg es TI PLX PCI9059 tue AA tot n b e eer TT 82054 Timer Counter Programming essen nennen enne rne 77 Interrupt Prograimtmirig EE 77 DG Characteristics 2 im e e ER ER e AN 78 Absolute Maximum RattingS sese nene mene menn nennen nennen 78 DC Input Output Levels ae tt edad ee Hed dete eeu en 78 Limited Warranty aene dee bau dedu 79 Table of Figures Figure 1 DM7820 DM9820 Block Diaoram cnn mem emere A Figure 2 Digital FO Block Diagram sseeeee enm emnes 12 Figure 3 Interrupt Diagralm ue heme i 14 Figure 4 Digital FO Block Diagram ernn E nennen nnns 31 Figure 5 Incremental Encoder Signals enne 49 Figure 6 PWM QUIDUt ini red Ede eH n PR t a ee Edere ere Pann 53 Figure 7 Counter latching executed for counter 1 Read Load 2 byte setting 63 Table of Tables Table 1 CN10 Pin Assigniments 2 22 rea oe reta tdt 6 Table 2 CN11 Pin Assignments dan A cin enim cnr 7 Table 3 PCI Configuration Registers AA 16 Table 4 DM7820 DM9820 Memory Map 17 Table 5 Peripheral Outputs nnne nnne nemen tenementis 33 Table 6 Incremental Encoder Inputs eene eene 49 Table 7 Select Counter SC 1 0 Selection of set counter nc nnnnnno 56 Table 8 Read Load R
20. PC 104 Plus connector carries the signals of the PC 104 Plus PCI bus Refer to PC 104 Plus Specification for the pinout of this connector The DM9820 connects to the power and ground pins only and does not use any of the signals The DM7820 uses this connector for communication with the CPU PCI Configuration Options DM7820 Only To install the DM7820 into the stack the PCI Slot Number must be configured correctly This is done by the PCI Slot Selector located at SW1 There are four possible PCI Slot Numbers 0 3 Each PCI device PC 104 Plus or PCI 104 must a use a different slot number The slot number is related to the position of the board in the stack Slot 0 represents the PCI device closest to the CPU Slot 3 represents the PCI devices farthest away from the CPU Note In a PC 104 Plus or PCI 104 system all PCI devices should be located on one side of the CPU board above or below the add on cards The CPU should not be located between two PCI devices DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 8 Switch SW1 PCI Slot Selector When the PC 104 Plus Specification was first introduced it only allowed for three PCI add on cards to be bus masters Version 2 0 of the PC 104 Plus specification was released in November 2003 This version of the specification which the DM7820 is designed for adds support for all 4 PCI slots to be bus masters There are two methods for compatibility with CPUs designe
21. PCI bus and robustly guards against over run and under run conditions However it does not allow for the FIFO to be completely filled of emptied There is a total of 45 M words per second of available bandwidth for the entire FIFO system This bandwidth is allocated between all input and output sources This is assuming that at least 256 Words stay in the FIFO at all times to maximize bursting e the Read Request and Write Request are used for DREQ If only one word is available in the FIFO i e Not Empty is used as for DREQ the available bandwidth drops to 3 75 M words per second When a FIFO is looped the data must be read and written The table below shows examples of configurations and their maximum data rate Note that for uniform sampling samples are taken at uniform sampling intervals the data rate must be an integer divisor of the 25 MHz overall clock Description Max Data Rate One FIFO in use burst capture only 25 MHz One FIFO in use burst output only 25 MHz One FIFO in use continuous capture or output 12 5 MHz Two FIFOs in use continuous capture output 12 5 MHz 6 25 MHz Two FIFOs in use continuous capture output 11 MHz non uniform sampling 11 MHz Board Interrupts There are three levels of interrupt sources for this board the interrupt sources generated in the PLX chip the interrupt sources generated by the modules in the Control Block and the interrupt sources within the modules
22. Selects the FIFO Input Data Value definitions for FIFOO are 3 FIFOO Output 2 Port2 1 PortO O PCI Data Value definitions for FIFO1 are 3 Incremental Encoder 1 Channel B Value 2 Incremental Encoder 1 Channel A Value 1 Port1 O PCI Data DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 40 FIFOn_CON_STAT This register is used to enable the FIFO When the FIFO is disabled it is internally reset and all data is flushed from it This register also is used to read the current status of the Write Request and Read Request signals that are used for DMA Requests For these signals internal buffers are monitored to signal when data can be sent into and read from the FIFO The Write Request is asserted when there is at least 256 words of space available in the FIFO and negated when there is less than 128 words available The Read Request is asserted when at least 256 words of data is in the FIFO and negated when there is less than 128 words of data Using these signals guarantees a burst of at least 128 words which provides for efficient communication over the PCI bus and robustly guards against over run and under run conditions However it does not allow for the FIFO to be completely filled of emptied 15 10 9 8 7 1 0 Reserved WRITE_REQ READ_REQ Reserved ENA R 0 R x R 0 R 0 RW 0 Field Description WRITE_REQ Current Write Request Statu
23. T Interrupt when this bit is 1 when selected ADVINTn_PORTx_CAPT The Capture register latches the input ports when an interrupt is generated All values are latched regardless of the Mask register or if the port is an input or output 15 14 13 12 11 10 9 8 Px_15 Px_14 Px_13 Px_12 Px_11 Px_10 Px_9 Px_8 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0 Px_7 Px_6 Px_5 Px_4 Px_3 Px 2 Px 1 Px 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Field Description Px_ 15 0 Captured Value Bit definitions are 0 Input was 0 at last interrupt T Input was 1 at last interrupt Dual Incremental Encoder n Each Incremental Encoder block provides two encoder channels with 16 bit counters These two channels can be linked into a single 32 counter An Incremental Encoder is used to detect the relative position of a shaft or linear actuator A typical implementation is a slotted wheel with two optical sensors positioned such that when one sensor is positioned over a slot the other is positioned between slots The output of the optical sensors is shown in Figure 5 with one sensor named A and the other named B At every edge of the A or B input the counter either increments or decrements The direction can be interpreted from the state of the signals i e which signal leads DM7820 DM9820 User
24. The peripheral outputs are the Pulse Width Modulators FIFO Timer Counters etc DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 30 Peripheral 3 Peripheral 2 1 Peripheral 1 Peripheral O PS D Q 0 SC PORTx_OUTPUT EE PORTx_PERIPH_SEL PORTx_TRISTATE DA PORTx_MODE Q D Data Readback PORTx INPUT Figure 4 Digital UO Block Diagram PORTx OUTPUT Sets the value for Port 0 Port 1 or Port 2 when it is a standard output 15 14 13 12 11 10 9 8 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Px_7 Px_6 Px_5 Px_4 Px_3 Px_2 Px_1 Px_0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Field Description Px_ 15 0 Value to output 0 Low 1 High PORTx_INPUT Returns the current value of Port 0 Port 1 or Port 2 15 14 13 12 11 10 9 8 DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 31 7 6 5 4 3 2 1 0 Px_7 Px_6 Px_5 Px_4 Px_3 Px_2 Px_1 Px_0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Field Description Px_ 15 0 Current pin value PORTx_TRISTATE 0 Pin is Low 1 Pin is High This register selects if each bit in Port 0 Port 1 or Port 2 is an input or an output 15 14 13 12 11 10 9 8 Px 15 Px 14 Px 13 Px 12 Px 11 Px 10 Px 9 Px 8 RW
25. continues using the new count value The operation for 2 byte count is as follows DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 59 1 First byte writing does not affect the counting operation 2 After the second byte is written the new count value is loaded to the CE at the falling edge of the next clock pulse This means that the counting operation is retriggered by software The output strobe is set to L level upon input of N 1 clock pulses after the new count value N is written Mode 5 Application Hardware trigger strobe Output operation The output is initially set to H level When the counter value becomes 0 after triggering by the rising edge of the gate pulse the output goes to L level during one clock pulse and then restores H level Count value load timing Even after the control word and initial count value are written loading to the CE does not occur until the input of the clock pulse succeeding the trigger For the clock pulse for CE loading the count value is not decremented If the initial count value is N therefore the output is not set to L level until N 1 clock pulses are input after triggering Gate function The initial count value is loaded to the CE at the falling edge of the clock pulse succeeding gate triggering The count sequence can be retriggered The gate pulse does not affect the output Count value writing during counting The count value writing does not a
26. not generated 15 1 0 Reserved ENA R 0 RW 0 Fied Description ENA Enables or disabled the PWM 0 Disabled 1 Enabled PWMn_CLK This register selects the clock sources for the period and width of the PWM output 15 8 7 4 3 0 Reserved PER_CLK 3 0 WIDTH CLK 3 0 R 0 RW 0 RW 0 Field Description PER_CLK 3 0 Selects the master clock for the period counter Value definitions are 15 Inverted Strobe2 14 Inverted Strobe1 13 Strobe2 12 Strobe1 11 Prog Clock 3 10 Prog Clock 2 Prog Clock 1 Prog Clock 0 82C54 TC B2 82C54 TC B1 82C54 TC BO 82C54 TC A2 82C54 TC A1 wWA00 Oo O DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 54 Field Description 2 82C54 TC AO 1 Reserved 0 25 MHz WIDTH_CLK 3 0 Selects the master clock for the width counter See above for value definitions PWMn_PERIOD Sets the maximum width of the PWM outputs If the period clock and width clock are the same PWMn CLK PER CLK PWMn_CLK WIDTH_CLK this will also set the PWM period See Figure 6 on page 53 for more details 15 0 PERIOD 15 0 RW 0 Field Description PERIOD 15 0 The period of the output is the next period clock after PERIOD 1 Width _ Clock _ Frequency PWMn_WIDTHx Sets the width of output x of the pulse width modulator The width is based on the clock se
27. of the CPU The DM9820 can be installed into a PC 104 Express or PCle 104 stack It can be located above or below the CPU Static Precautions Keep your board in its antistatic bag until you are ready to install it into your system When removing it from the bag hold the board at the edges and do not touch the components or connectors Handle the board in an antistatic environment and use a grounded workbench for testing and handling of your hardware Steps for Installing 1 Shut down the PC 104 system and unplug the power cord Ground yourself with an anti static strap Set the PCI Slot Selector as described in the previous chapter Boo bh If any other PCI add on cards are to be included in the stack be sure that their PCI slot numbers are configured correctly Slot 0 for the board closest to the CPU Slot 1 for the next board etc 5 Line up the pins of the DM7820 DM9820 s connectors with the corresponding bus connectors of the stack Make sure that both connectors are lined up 6 Apply pressure to both bus connectors and gently press the board onto the stack The board should slide into the matching bus connectors Do not attempt to force the board as this can lead to bent broken pins 7 Attach any cables to the DM7820 DM9820 8 If any boards are to be stacked above the DM7820 DM9820 install them 9 Attach any necessary cables to the PC 104 Plus stack 10 Re connect the power cord and apply power to the stack 11
28. s Manual RTD Embedded Technologies Inc 48 Figure 5 Incremental Encoder Signals The encoders include a Phase Filter that prevents the counter from counting on certain transitions This allows the encoders to count pulses and other specialized applications Encoder inputs can be configured as single ended or pseudo differential In pseudo differential mode the and inputs must be the inverse of each other in order for the encoder to see a change Digital filtering can be selected With digital filtering a transition on a line is only considered valid if it remains constant for four clock cycles The clock can be selected Separate interrupts are generated for positive and negative rollover Positive rollover occurs when the counter is at its maximum value and receives a signal to count up Negative rollover occurs when the counter is at 0 and receives a signal to count down Because separate interrupts are generated the counter can be easily expanded in software The Incremental Encoder inputs are show in Table 6 below Table 6 Incremental Encoder Inputs Pin Encoder 0 Encoder 1 Channel A Channel B Channel A Channel B A PortO 0 PortO 8 Port1 0 Port1 8 A PortO 1 PortO 9 Port1 1 Port1 9 B PortO 2 PortO 10 Port1 2 Port1 10 B Port0 3 Port0 1 1 Port1 3 Port1 11 Index PortO 4 PortO 12 Port1 4 Port1 12 Index PortO
29. the clock input to this channel of the Timer Counter Value definitions are 15 Inverted Strobe2 14 Inverted Strobe1 13 Strobe2 12 Strobe1 11 Prog Clock 3 10 Prog Clock 2 Prog Clock 1 Prog Clock 0 82C54 TC B2 82C54 TC B1 82C54 TC BO 82C54 TC A2 82C54 TC A1 82C54 TC AO Reserved 5MHz OO N OQ 4 O1 O OO oO FIFO Channel n The DM7820 DM9820 provides two FIFOs to buffer data going into and out of the board Each FIFO is 4MB in size The input strobe output strobe and data input for each FIFO can be individually selected The output data is made available to the peripheral outputs and also the PCI interface Each FIFO is attached to a DMA Channel in the PLX chip FIFOO is attached to DMAO and FIFO1 is attached to DMA1 FIFOn ID ID register to identify a FIFO Block 15 0 ID_Register R Field Description ID_Register15 0 Value of 0x2011 indicates SDRAM FIFO Block FIFOn_INT Enable and status for the interrupts generated by the FIFOs An Overflow condition occurs when the FIFO is full and it is written to It can also occur when the FIFO is written to too fast An Underflow occurs when the FIFO is empty and the output clock toggles or when the FIFO is read from too fast When the FIFO is disabled the Full Empty and both requests are asserted 15 8 7 0 INT STAT 7 0 INT ENA 7 0 DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 37
30. the four outputs is individually adjustable The PWM can use separate clocks for width and period The width clock is used to decrement the counter When the counter reaches zero it will wait for the next period clock to re load the counter with the period value In a typical PWM implementation the same clock is used for width and period By using separate clocks a high resolution can be achieved with low duty cycle outputs For example if a 1 MHz clock is used for the period clock and the PERIOD register is set to its maximum value and a 10 MHz clock is used for the width clock the duty cycle range is 0 to 10 with a full 16 bit resolution across that range Note that if the PERIOD register is set to its maximum value a duty cycle of 100 cannot be achieved An interrupt is generated at the beginning of every period The width register is checked at the beginning of every period If the width register is modified in the middle of a period the output will not be affected until the next period DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 53 PWMn_ID ID register to identify this block 15 0 ID_Register R Field Description ID_Register15 0 Value of 0x0003 indicates Pulse Width Modulator PWMn_MODE This register is used to enable and disable the Pulse Width Modulator When disabled all non inverted outputs are low and all inverted outputs are high and interrupts are
31. value 0000H can t be read The program sequence of the MSM82C54 2 is flexible Free sequence programming is possible as long as the two following rules are observed i Write the control word before writing the initial count value in each counter ii Write the initial count value according to the count value read write format specified by the control word Note Unlike the MSM82C53 2 the MSM82C54 2 allows count value setting for another counter between LSB and MSB settings Mode definition Mode 0 e Application Event counter e Output operation The output is set to L level by the control word setting and kept at L level until the counter value becomes 0 e Gate function H level validates the count operation and L level invalidates it The gate does not affect the output e Count value load timing after the control word and initial count value are written the count value is loaded to the CE at the falling edge of the next clock pulse The first clock pulse does not cause the count value to be decremented In other words if the initial count value is N the output is not set to H level until the input of N 1 the clock pulse after the initial count value writing e Count value writing during counting The count value is loaded in the CE at the falling edge of the next clock and counting with the new count value continues The operation for 2 byte count is as follows o The counting
32. 0 External Index is disabled 1 External Index is enabled b 1 Hold Register 1 Hold values register 0 Allow value register to change b 0 Count Enable 1 Encoder is enabled 0 Encoder is cleared 0x0288 INCENCO VALUEA b 15 0 Value for Encoder A 0x028A INCENCO VALUEB b 15 0 Value for Encoder B Dual Incremental Encoder 1 DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 24 Table 4 DM7820 DM9820 Memory Map Offset Register Name eee uci Function Hex 0x02C0 INCENC1_ID lic RN 0 ID Register 0x0002 0x02C2 INCENC1 INT b 11 8 Interrupt Status 1 Interrupt condition has occurred Write 1 to clear b 3 0 Interrupt Enable 1 Interrupt is enabled 0 disabled Interrupt source are 3 Encoder B Negative Rollover 2 Encoder B Positive Rollover 1 Encoder A Negative Rollover O Encoder A Positive Rollover 0x02C4 INCENC1 CLOCK b 3 0 Master Clock Source 15 0 Clock Bus 15 0 0x02C6 INCENC1 MODE b 15 8 Phase Filter Writing a 1 to a specific bit masks out a phase transition b 7 6 Reserved b 5 Differential Mode 1 Pseudo differential mode 0 Single ended mode b 4 Input Filter 1 Enable Input Filter 0 Disable Input Filter b 3 Join 1 Operate as single 32 bit Encoder 0 Operate as two 16 bit Encoders b 2 0 External Index is disabled
33. 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Px_7 Px_6 Px_5 Px_4 Px_3 Px_2 Px_1 Px_0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Field Description Px_ 15 0 Select input or output 0 Input 1 Output PORTx_MODE Selects if each pin in Port 0 Port 1 or Port 2 is a standard I O controlled by PORTx TRISTATE or a peripheral output controlled by PORTx_PERIPH_SEL 15 14 13 12 11 10 9 8 Px 15 Px 14 Px_13 Px_12 Px_11 Px_10 Px_9 Px_8 RW 0 RW 0 Rw 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Px_7 Px_6 Px_5 Px_4 Px_3 Px_2 Px_1 Px_0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Field Description Px_ 15 0 Port Mode 0 Standard I O controlled by PORTx_ TRISTATE 1 Peripheral controlled by PORTx_PERIPH_SEL DM7820 DM9820 User s Manual 32 RTD Embedded Technologies Inc PORTx_PERIPH SEL L This register selects the peripheral for Port 0 Port 1 or Port 2 when it is a peripheral output i e PORTx MODE 1 This register selects the peripheral for bits 7 0 15 14 13 12 11 10 9 Px_7 Px_6 Px_5 Px_4 RW 00 RW 00 RW 00 RW 00 7 6 5 4 3 2 1 Px_3 Px_2 Px_1 Px_0 RW 00 RW 00 RW 00 RW 00
34. 0 RW 0 RW 0 RW 0 RW 0 Field Description DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 51 Field Description PHASE FLT 7 0 Phase Filter Selects if a particular state transition will cause the encoder counter to change For each bit 0 Transition will change counter 1 Transition will not change counter The bit assignments for the transitions are Bit Previous Current Direction State B A State B A 7 00 10 Down 6 10 11 Down 5 11 01 Down 4 01 00 Down 3 10 00 Up 2 11 10 Up 1 01 11 Up 0 00 01 Up DIFF Selects single ended or differential mode 0 Single Ended Only inputs are used 1 Pseudo Differential FILTER Enable the input filter 0 Filter is disabled 1 Filter is enabled JOIN Used to join the two channels into a single 32 bit counter When the channels are joined only the Channel A inputs are used 0 Channels are independent 1 Channels are joined IDX EN Index Enable When enabled a high input on the Index input clears the counter 0 Index Inputs Disabled 1 Index Input Enabled HOLD Register Hold When enabled the encoder continues counting in the background but the VALUE registers remain constant 0 VALUE registers are not held 1 VALUE registers are held ENA Enable for this incremental encoder 0 Encoder is disabled 1 Encoder is enabled
35. 0 0 0 1 0 Read back status counter 0 L d 3 L L L L Note The latch command at this time point is ignored and the first latch command is valid If both the count and status are latched the status latched in the first counter read operation is read The order of count latching and status latching is irrelevant The count s of the next one or two reading operations is or are read DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 65 PLX Registers The PLX9056 PCI Accelerator on the DM7820 DM9820 contains several registers to control interrupts and the two DMA engines These engines allow data to be transferred on demand with no load on the processor The following sections describe the registers used for programming the DMA engines This information is taken from PLX PCI9065BA Datasheet For more information please consult the datasheet Memory Map Overview Table 11 shows the memory map of the DM7820 DM9820 DMA registers These are found at the memory offset from BARO or the I O offset from BAR1 Table 11 PLX DM7820 DM9820 Memory Map DMA Channel 0 0x90 __ DMADPRO DMA Channel Descriptor Pointer 0x94 DMAMODE1 _ DMA Channel 1 Mode Ox9C OxAO DMALADR1 DMA Channel 1 Local Address OxAO 0x98 DMASIZ1 DMA Channel 1 Transfer Size Bytes 0xA4 _ DMADPR1 DMA Channel 1 Descriptor Pointer OxA9 DMACSR
36. 1 Counter 1 selection D4 1 Counter 0 selection Do 0 Fixed It is possible to latch multiple counters by using the read back command Latching of a read counter is automatically canceled but other counters are kept latched If multiple read back commands are written for the same counter commands other than the first one are ignored It is also possible to latch the status information of each counter by using the read back command The status of a certain counter is read when the counter is read The counter status format is as follows Bits D5 to DO indicate the mode programmed by the most recently written control word Bit D7 indicates the status of the output pin Use of this bit makes it possible to monitor the counter output so the corresponding hardware may be omitted D7 De D5 D4 D3 Do D Do NULL COUNT OUTPUT RL1 RLO M2 M1 MO BCD Dz 1 Output pin status is 1 0 Output pin status is 0 De 1 Null count 0 Count value reading is effective Ds Dg Programmed mode of counter See the control word format Null count indicates the count value finally written in the counter register CR has been loaded in the counter element CE The time when the count value was loaded in the CE depends on the mode of each counter and it cannot be known by reading the counter value because the count DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 64 value does not tell the new count value if the counter is l
37. 1 DMA Channel 1 Command Status DMADAO DMA Channel 0 PCI Dual Address Cycle Upper Address DMADA1 DMA Channel 1 PCI Dual Address Cycle Upper Address AA TN INTCSR Interrupt Control Status Where two addresses are given the left column is the address when DMAMODEn 20 0 and the right column is the address when DMAMODEn 20 71 DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 66 DMA Register Description DMAMODEn DMA Mode Bit Description Read Write Value after Reset Value to Use 1 0 Local Bus Data Width Writing of the following values indicates the associated bus data width 00b 8 bit 01b 16 bit 10b or 11b 32 bit Yes Yes 11b 11b 5 2 Internal Wait State Counter Address to Data Data to Data 0 to 15 Wait States Yes Yes Oh Oh TA READY Input Enable Writing 1 enables READY input Writing 0 disables READY input Yes Yes Continuous Burst Enable When bursting is enabled DMAMODEO 8 1 writing 1 enables Continuous Burst mode and writing 0 enables Burst 4 mode Writing 1 additionally enables BTERM input which when asserted overrides the READY input state if READY is enabled DMAMODEO 6 71 Notes This bit is referred to as the BTERM Input Enable bit Refer to Section 4 2 5 of the PCI9056 datasheet for further details Local Burst Enable Writing 1 enables Local bursting Writing O disables Local burst
38. 2 Generally the registers are 16 bits wide However they can be read and written as 8 16 or 32 bits There are a few exceptions as noted in the memory map Memory Map Overview Table 4 shows the memory map of the DM7820 DM9820 digital I O registers These are found at the offset from BAR2 DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 16 Table 4 DM7820 DM9820 Memory Map Offset Register Name Register Function Hex Board Control 0x0000 FPGA VERSION b 15 8 Type ID b 7 0 Version 0x0002 SVN_VERSION b 15 0 Extended Version 0x0004 BOARD_RESET Write 0xA5A5 to reset board 0x0006 2 et I EET REESE _ _ _ MSTR 0 PCI Master Capable 1 Not PCI E Capable Read ad Only interrupt b 15 0 Interrupt Status Reading a 1 indicates interrupt condition has occurred Write a 1 to clear an interrupt bit EIA o 0x003E Standard UO 0x0052 PORT2 INPUT b 15 0 Read only valuefromPort2 0x0058 STROBE STATUS b 9 STR2 TRI 0 strobe2 is input 1 srobe2 is output b 8 STR1 TRI 0 strobe1 is input 1 srobe1 is output b 5 STR2 OUT Value for strobe2 when an output b 4 STR1 OUT Value for strobe1 when an output b 1 STR2 IN Current value of Strobe2 b 0 STR1 IN Current value of Strobe1 0x005A Reserved 0x005E DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 17 Table 4 DM7820 DM9820 Memory M
39. 4 13 8 7 6 5 0 Reserved INT_STAT 5 0 Reserved INT_ENA 5 0 R 00 RC 0 R 00 RW 0 Field Description INT STAT 5 0 DM7820 DM9820 User s Manual asserted on the positive edge of the clock Interrupt Status 1 Interrupt condition has occurred Write 1 to clear Interrupts are RTD Embedded Technologies Inc 35 Field Description INT_ENA 5 0 disabled Interrupt source are TC B2 OANWAH 4o O UJ o Interrupt Enable 1 Interrupt is enabled 0 TC_xy_CONTROL This register selects the input clock and gate source for the 82C54 Timer Counters Note that the maximum input frequency to the Timer Counters is 10 MHz hardware to prevent a Timer Counter from using its own output clock as its input clock Also no provision is made in 15 13 12 8 7 4 3 0 Reserved GATE SEL 4 0 Reserved CLOCK SEL 3 0 R 00 RW 0 R 00 RW 0 Field Description GATE SEL 4 0 31 Port2 15 16 Port2 0 13 Strobe2 12 Strobe1 11 Prog Clock 3 10 Prog Clock 2 Prog Clock 1 Prog Clock 0 82C54 TC B2 82C54 TC B1 82C54 TC BO 82C54 TC A2 82C54 TC A1 82C54 TC A0 q 0 OANWAHRUAONWO Selects the gate input to this channel of the Timer Counter Value definitions are 15 Inverted Strobe2 14 Inverted Strobe1 DM7820 DM9820 User s Manual 36 RTD Embedded Technologies Inc Field Description CLOCK_SEL 3 0 Selects
40. 52_ Reserved ou DEENEN 0x0354 PWM1_WIDTHB______ b 15 0 Width of output B pulse in Period Clock cycles 7 ox0356_ Reserved OX035A_ Reserved Ox035E Reserved 82C54 Timer Counter A 0x1010 TCB COUNTER O b 7 0 CounterOkRegister__________________ 0x1014 TCB COUNTER 1 b 7 0 Counter Register Detailed Register Description The following sections provide a detailed description of the individual registers In the following register description sections each register is described by a register table The first row of the table lists the bits D15 through DO The second row lists the field name for each bit The third row lists the properties of that bit R bit can be read W bit can be written to and C bit can be cleared The last row lists the value of the bit after reset The register table is then followed by a description of each of the fields where applicable An N A for the reset value indicates that the reset value is not applicable read the field descriptions for more information DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 26 Bits marked as Reserved in the field name are unused and reads will always return their reset value These bits should not be modified during writes for future compatibility System Block FPGA_VERSION This register provides the version and type ID of the Digital UO FPGA The version can be used to identify the specific build of
41. DM7820 DM9820 User s Manual Versatile High Speed Digital VO O TUTO RTD Embedded Technologies Inc Real Time Devices Accessing the Analog World BDM 610010036 Rev B ISO9001 and AS9100 Certified DM7820 DM9820 User s Manual RTD EMBEDDED TECHNOLOGIES INC 103 Innovation Blvd State College PA 16803 0906 Phone 1 814 234 8087 FAX 1 814 234 5218 E mail sales rtd com techsupport rtd com Web Site http www rtd com Manual Revision History RevA Initial Release Rev B Better DREQ description on page 40 Improved description of FIFO on page 12 Improved description of FIFOn CON STAT on page 41 Corrected PWM Period formula on page 55 Added DM9820 information Published by RTD Embedded Technologies Inc 103 Innovation Boulevard State College PA 16803 Copyright 2009 by RTD Embedded Technologies Inc All rights reserved Specification and features described in this manual may change without notice The RTD Embedded Technologies Logo is a registered trademark of RTD Embedded Technologies dspModule cpuModule and utilityModule are trademarks of RTD Embedded Technologies PC 104 PC 104 Plus PCI 104 PC 104 Express and PCle 104 are registered trademark of PC 104 Consortium All other trademarks appearing in this document are the property of their respective owners Table of Contents InttOGLictlOri 2 rone red tbe e np need deni ne 1 Product OVerview x n ttt oTi ined bo Lan ciet tiet ce La
42. E at the falling edge of the next clock pulse The output is set to L level upon lapse of N clock pulses after writing the initial count value N Counter synchronization by software is possible in this way Count value writing during counting Count value writing does not affect the current counting operation sequence If new count value writing completes and the gate trigger arrives before the end of current counting operation the count value is loaded to the CE at the falling edge of next clock pulse and counting continues from the new count value If no gate trigger arrives the new count value is loaded to the CE at the end of the current counting operation cycle In mode 2 count value of 1 is prohibited Mode 3 Application Baud rate generator square wave generator DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 58 Output operation Same as mode 2 except that the output duty is different The output is set to H level by control word setting When the count becomes half the initial count value the output is set to L level and kept at L level during the remainder of the count Mode 3 repeats the above sequence periodically If the initial count value is N the output becomes a square wave with a period of N Gate operation H level validates counting and L level invalidates it If the gate signal is set to L level when the output is L level the output is immediately set to
43. FO1 Out 15 STROBE STATUS This register can be used to check the status of the strobe signals as well as configure the strobes as outputs 15 10 9 8 Reserved STR2 TRI STR1 TRI R 0000 00 RW 0 RW 0 7 6 5 4 3 2 1 0 Reserved STR2_OUT STR1_OUT Reserved STR2_IN STR1_IN R 00 RW 0 RW 0 R 00 R x R x Field Description STR1_IN Current State of Strobe 1 0 Low 1 High DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 34 Field Description STR2_IN Current State of Strobe 2 0 Low 1 High STR1_OUT Value to drive on Strobe 1 when an output 0 Low 1 High STR2_OUT Value to drive on Strobe 2 when an output 0 Low 1 High STR1 TRI Selects Input or Output for strobe 1 0 Input 1 Output STR2 TRI Selects Input or Output for strobe 2 0 Input 1 Output 82C54 Timer Counter Control The Timer Counter Control section is used to select the clock gates and interrupt sources for the 82C54 Timer Counters The actual Timer Counter registers are found in the 82C54 Timer Counter n section on page 55 TC_ID ID register to identify the Timer Counter Block 15 ID_Register R p ID_Register15 0 Value of 0x1001 indicates Timer Counter Control Block TC_INT Enable and status for the interrupts generated by the 82C54 Timer Counters 15 1
44. H level The initial count value is reloaded at the falling edge of the clock pulse succeeding the next gate trigger The gate can be used for counter synchronization in this way Count value load timing After the control word and initial count value are written the count value is loaded to the CE at the falling edge of the next clock pulse Counter synchronization by software is possible in this way Count value writing during counting The count value writing does not affect the current counting operation When the gate trigger input arrives before the end of a half cycle of the square wave after writing the new count value the new count value is loaded in the CE at the falling edge of the next clock pulse and counting continues using the new count value If there is no gate trigger the new count value is loaded at the end of the half cycle and counting continues Even number counting operation The output is initially set to H level The initial count value is loaded to the CE at the falling edge of the next clock pulse and is decremented by 2 by consecutive clock pulses When the counter value becomes 2 the output is set to L level the initial value is reloaded and then the above operation is repeated Odd number counting operation The output is initially set to H level At the falling edge of the next clock pulse the initial count value minus one is loaded in the CE and then the value is decremented by 2 by consec
45. INCENCn VALUEy Returns the current value of this incremental encoder channel When INCENCx_MODE JOIN 1 INCENCx VALUEB contains the most significant word and INCENCx VALUEA contains the least significant word A 16 bit read should be used to read this register when not joined INCENCx MODE JOIN 0 and a 32 bit read should be used when joined INCENCx MODE JOIN 1 Otherwise the value can change between read operations Another option is to set INCENCx MODE HOL D 7 1 read the contents of the register and then set INCENCx MODE HOLD 0 This register can only be written to when INCENCx_MODEJ ENA 0 This allows the counter to be pre loaded with a known position value DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 52 15 0 VALUE 15 0 R W 0 Field Description VALUE 15 0 The current value of this incremental encoder channel Quad Pulse Width Modulator n The Pulse Width Modulator block provides four PWM outputs Each output consists of a non inverted and inverted signal These signals are available on select pins as peripheral outputs The period and width of the output is set with 16 bit resolution PERIOD 1 Width Clock Freq WIDTH Width Clock Freq Period Clock Edge Output Output Interrupt Figure 6 PWM Output All of the PWM outputs have the same period The pulse width of each of
46. Interrupt Enable Writing 1 enables PCl to Local Doorbell interrupts Used in conjunction with the Local Interrupt Output Enable bit INTCSR 16 Clearing the P2LDBELL register bits that caused the interrupt also clears the interrupt Yes Yes 0 0 DM7820 DM9820 User s Manual 74 RTD Embedded Technologies Inc 18 DMA Channel 0 Interrupt Enable Writing 1 enables DMA Channel 0 interrupts Used in conjunction with the DMA Channel 0 Interrupt Select bit DMAMODEO 17 Setting the DMA Channel 0 Clear Interrupt bit DMACSRO 3 1 also clears the interrupt Yes 0 1 19 DMA Channel 1 Interrupt Enable Writing 1 enables DMA Channel 1 interrupts Used in conjunction with the DMA Channel 1 Interrupt Select bit DMAMODE1 17 Setting the DMA Channel 1 Clear Interrupt bit DMACSR1 3 1 also clears the interrupt Yes Yes 0 1 20 Local Doorbell Interrupt Active Reading 1 indicates the Local Doorbell interrupt is active No 21 22 23 DMA Channel 0 Interrupt Active Reading 1 indicates the DMA Channel 0 interrupt is active DMA Channel 1 Interrupt Active Reading 1 indicates the DMA Channel 1 interrupt is active Built In Self Test BIST Interrupt Active Reading 1 indicates the BIST interrupt is active The BIST interrupt is enabled by writing 1 to the PCI Built In Self Test Interrupt Enable bit PCIBISTR 6 1 Clearing the Enable bit PCIBISTR 6 0 also clears th
47. L 1 0 Count Value Reading Loading format setting 56 Table 9 Mode M 2 0 Operation waveform mode setting nsssessenensneseennrrnnsenstrnrrnnnnnssrenre nna 56 Table 10 BCD Operation count mode settimg eem 57 Table 11 PLX DM7820 DM9820 Memory Map 66 Table 12 DMA Threshold Nybble Values A 72 Introduction Product Overview The DM7820 DM9820 is designed to provide high speed digital I O for PC 104 Plus Systems It interfaces with the PCI bus and uses large FIFOs and DMA transfers to allow for efficient data management Several peripherals including Pulse Width Modulators Incremental Encoders and Programmable Clocks are also provided Board Features Digital UO 48 Diode protected I O lines 24 mA source and sink current Compatible with DMR and DOP expansion boards Deep FIFOs with DMA Two 2M Word FIFOs Each FIFO is attached to a separate DMA channel 25 MHz bursted throughput 12 5 MHZ continuous throughput FIFO can be looped Pulse Width Modulators Eight PWM outputs Single ended or Differential Outputs 16 bit resolution Separate period and width clocks provide full resolution at low duty cycles Optional Interrupt generations Incremental Encoders Four Incremental Encoder channels Single ended or Pseudo differential Inputs Variable frequency input filtering Max input speed of 40ns per transition 16 bit resolution Two channels can be combined for 32 bit resolu
48. NT AS PROVIDED ABOVE UNDER NO CIRCUMSTANCES WILL RTD EMBEDDED TECHNOLOGIES BE LIABLE TO THE PURCHASER OR ANY USER FOR ANY DAMAGES INCLUDING ANY INCIDENTAL OR CONSEQUENTIAL DAMAGES EXPENSES LOST PROFITS LOST SAVINGS OR OTHER DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PRODUCT SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR CONSUMER PRODUCTS AND SOME STATES DO NOT ALLOW LIMITATIONS ON HOW LONG AN IMPLIED WARRANTY LASTS SO THE ABOVE LIMITATIONS OR EXCLUSIONS MAY NOT APPLY TO YOU THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND YOU MAY ALSO HAVE OTHER RIGHTS WHICH VARY FROM STATE TO STATE DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 79
49. Oh D COLPAF Number of full word x 2 entries plus 1 times 2 in the FIFO before requesting the PCI Bus for writes Nybble values Oh through Eh may be used Refer to Table 12 15 12 DMA Channel 0 PCI to Local Almost Empty Yes Yes Oh D COPLAE Number of empty Lword x 2 entries plus 1 times 2 in the FIFO before requesting the PCI Bus for reads Nybble values Oh through Eh may be used Refer to Table 12 19 16 DMA Channel 1 PCI to Local Almost Full Yes Yes Oh D C1PLAF Number of full Lword x 2 entries plus 1 times 2 in the FIFO before requesting the Local Bus for writes Nybble values Oh through Eh may be used Refer to Table 12 15 CIPLAF gt C1LPAE 23 20 DMA Channel 1 Local to PCI Almost Empty Yes Yes Oh x C1LPAE Number of empty Lword x 2 entries plus 1 times 2 in the FIFO before requesting the Local Bus for reads Nybble values Oh through Eh may be used Refer to Table 12 15 C1PLAF gt C1LPAE 27 24 DMA Channel 1 Local to PCI Almost Full Yes Yes Oh D C1LPAP Number of full Lword x 2 entries plus 1 times 2 in the FIFO before requesting the PCI Bus for writes Nybble values Oh through Eh may be used Refer to Table 12 31 28 DMA Channel 1 PCI to Local Almost Empty Yes Yes Oh D C1PLAB Number of empty Lword x 2 entries plus 1 times 2 sin the FIFO before requesting the PCI Bus for reads Nybble values Oh through Eh may be used Refer to Tabl
50. P b 15 13 Reserved b 12 8 Stop Clock 31 16 Interrupt_Bus 15 0 15 1 Clock_Bus 15 1 0 No Stop Clock b 7 5 Reserved b 4 0 Start Trigger 31 16 Interrupt_Bus 15 0 15 1 Clock_Bus 15 1 0 Start Immediate 0x0108 PRGCLKO_PERIOD b 15 0 Period of Clock Output frequency is Master _ Clock _ Frequency PRG _CLK _ PERIOD 1 Programmable Clock 1 0x0140 PRGCLK1_ID b 15 0 ID Register 0x1000 PRGCLK1_MODE b 15 2 Reserved b 1 0 00 Disabled 01 Continuous 10 Reserved 11 One Shot 0x0144 PRGCLK1 CLK b 15 4 Reserved b 3 0 Master Clock Source 15 0 Clock_Bus 15 0 0x0146 PRGCLK1_START_STOP b 15 13 Reserved b 12 8 Stop Clock 31 16 Interrupt_Bus 15 0 15 1 Clock_Bus 15 1 0 No Stop Clock b 7 5 Reserved b 4 0 Start Trigger 31 16 Interrupt_Bus 15 0 15 1 Clock_Bus 15 1 0 Start Immediate 0x0148 PRGCLK1_PERIOD b 15 0 Period of Clock Output frequency is Master _ Clock _ Frequency PRG _CLK _ PERIOD 1 Programmable Clock 2 0x0180 PRGCLK2_ID b 15 0 ID Register 0x1000 DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 21 Table 4 DM7820 DM9820 Memory Map Offset Register Name Register Function Hex 0x0182 PRGCLK2 MODE b 15 2 Reserved b 1 0 00 Disabled 01 Continuous 10 Reserved 11 One Shot 0x0184 PRGCLK2_CLK b 15 4 Reserved b 3 0 Master Clock Source 15 0 Clock_Bus 15 0 0x0186 PRGCLK2_START_STOP
51. PCI Accelerator contact PLX Technologies at www plxtech com 82C54 Timer Counter Programming For more information about programming the MSM82C54 Timer Counter Chips contact Oki Semiconductor at wwwz okisemi com Interrupt Programming For more information about interrupts and writing interrupt service routines refer to the following book Interrupt Driven PC System Design by Joseph McGivern ISBN 0929392507 DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 77 DC Characteristics Absolute Maximum Ratings DIO Vin Operating Temp Output Standard VIH VOH IOL V Min V Min mA 1 DIO Vin DC overshoot must be limited to either 5 5V or 10mA and DC undershoot must be limited to either 0 5V or 10mA 2 DIO pins may be driven to 2 0V or 7 0V provided these voltages last no longer than 11ns with a forcing current no greater than 100mA 3 Inputs are terminated with 33Q resistors and protection diodes 4 DIO inputs should not be tied to voltages when the board is not powered DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 78 Limited Warranty RTD Embedded Technologies Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from RTD EMBEDDED TECHNOLOGIES INC This warranty is limited to the original purchaser of product and is not
52. and re enabled for it to start again The clock should be disabled before modifying this register 15 13 12 8 7 5 4 0 STOP TRG 4 START TRG A 0 Field Description DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 43 Field Description START TRG 4 0 Selects the start trigger Value definitions are 31 FIFO1 Interrupt 30 FIFOO Interrupt 29 Prog Clock 3 Interrupt 28 Prog Clock 2 Interrupt 27 Prog Clock 1 Interrupt 26 Prog Clock 0 Interrupt 25 PWM1 Interrupt 24 PWMO Interrupt 23 Reserved 22 Reserved 21 Incremental Encoder 1 Interrupt 20 Incremental Encoder 0 Interrupt 19 Reserved 18 82C54 Interrupt 17 Advanced Interrupt 1 Interrupt 16 Advanced Interrupt 0 Interrupt 15 Inverted Strobe2 14 Inverted Strobe1 13 Strobe2 12 Strobe1 11 Prog Clock 3 10 Prog Clock 2 Prog Clock 1 Prog Clock 0 82C54 TC B2 82C54 TC B1 82C54 TC BO 82C54 TC A2 82C54 TC A1 82C54 TC AO Reserved Start Immediate OO N OQ PO O OO oO DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 44 Field Description STOP_TRG 4 0 Selects the stop trigger Value definitions are 31 FIFO1 Interrupt 30 FIFOO Interrupt 29 Prog Clock 3 Interrupt 28 Prog Clock 2 Interrupt 27 Prog Clock 1 Interrupt 26 Prog Clock 0 Interrupt 25 PWM1 Interrupt 24 PWMO Interrupt 23 Reserved 22 Reserved 21 Incremental Encoder 1 Interrupt 20 Incremental Encoder 0 Interrupt 19 Reserved 18 82C54 Interr
53. ap Offset Register Name Register Function Hex 0x0060 PORTO PERIPH SEL L b 15 14 PortO 7 _Periph_Select b 13 12 Port0 6 _Periph_Select b 11 10 PortO 5 Periph Select b 9 8 PortO 4 Periph Select b 7 6 PortO 3 Periph Select b 5 4 Port0 2 Periph Select b 3 2 Port0 2 Periph Select b 1 0 PortO 0 Periph Select 0x0062 PORTO PERIPH SEL H b 15 14 Port0 15 Periph Select b 13 12 PortO 14 Periph Select b 11 10 PortO 13 Periph Select b 9 8 PortO 12 Periph Select b 7 6 PortO 11 Periph Select b 5 4 PortO 10 Periph Select b 3 2 Port0 9 Periph Select b 1 0 PortO 8 Periph Select 0x0064 PORT PERIPH SEL L 0x0066 PORTI PERIPH SELA 0x0088 PORT2 PERIPH SELL CS 0x006A_ PORT2 PERIPH_SELH woore 0x007E 82C54 Timer Counter Control 0x0080 TC ID b 15 0 ID Register equals 0x1001 0x0082 TC INT b 15 14 Reserved b 13 8 Interrupt Status 1 Interrupt condition has occurred Write 1 to clear Interrupts are asserted on the positive edge of the clock b 7 6 Reserved b 5 0 Interrupt Enable 1 Interrupt is enabled 0 disabled Interrupt source are 0x0084 b 15 13 Reserved b 12 8 Gate Select m Porta 19 0 Ue AORE BUS TISE 0x008E TC B2 CONTROL b 7 4 Reserved b 3 0 Clock Select 15 2 Clock_Bus 15 2 1 reserved 0 5MHz FIFO Channel 0 DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 18 Table 4 DM7820
54. atched The null count operation is shown below Operation A Control word register writing B Count register CR writing Result Null count 1 Null count 1 C New count loading to CE CR gt CE Null count 0 Note The null count operation for each counter is independent When the 2 byte count is programmed the null count is set to 1 when the count value of the second byte is written If status latching is carried out multiple times before status reading other than the first status latch is ignored Simultaneous latching of the count and status of the selected counter is also possible For this purpose set bits D4 and D3 COUNT and STATUS bits to 00 This is functionally the same as writing two separate read back commands at the same time If counter status latching is carried out multiple times before each reading other than the first one is ignored here again The example is shown below Command CounterO Counter 1 Counter 2 Contents D Dg Del D4 D3 D2 Di Do Count Status Count Status Count Status Read back status and count 111 0 0 0 0 1 0 counter 0 L L 1 1 1 0 0 1 0 0 Read back status counter 1 L L L 1 1 1 0 1 1 0 0 Read back status counter 1 and 2 L L St deed Ces L 1 1 0 141 0 0 0 Read back status counter 2 L L L L L Read back status and count L 1 11 0 0 0 1 0 0 counter 1 L L L ene L L 1 1 1
55. c icd Ate 41 PROGGLKin ID oreet NRI NIRE ERE ue 42 PROGCLKA MODE cena a a EE 42 PROCURAN Rer DEE 42 PRGGLKA START STOP seria Sat A ee eed 43 PROGCUKN PERIOD sa 0 A A dN ele ea eS 45 Advanced Interr pt Messrs ed EENS 46 ADVINTA Dee EE A 46 ADVINT nv INT MODE A WE eel ee cd 46 ADVINTO CLK EE 47 ADVINTns PORT TEE 47 ADVINTmDnzZPORETX CMP iit edet p e ibid 48 ADVINTA PORDE CAPT EE 48 Dual Incremental Encoder n toot EE AE EE SE 48 INGCENGnm ID 5 three rt ade 49 Nleizie eM nee 50 INC ENGR e EE 51 le Gelee 51 Ile AY RTE 52 Quad Pulse Widtli Modulatorn ceo e rere Ee eek teu eere rho eene Ei 53 PAM Dit casa rs dt da e 54 PWMri le DEE 54 AIO EE 54 PWM PERIOD KEE 55 PWM WD P OE 55 82654 Timen GOUMIER EE 55 DESCRIP THON OF OPERATION ciae uota ent i teta e eiae eate e eoo AER 56 Control Word and Count Value Program 56 Mode delinition Zeg CES 57 Mode 20 erc SE eee cota re Saale rae ata bers EEN 57 Moderato EET 58 WY ieee rt a ES lt e RS eRe A loo ci 58 Mode Ee 58 Reading Counter Values ege dated cite ents dat a ee een ete 62 Elle ne DEET 62 Counter latching EE 62 Read Back Command Operation 63 PLX Ee EE 66 dE usw dE Me EE 66 DMA Register Description EE 67 DMAMODEN 0 coa meae Eten e potete maestus ep etc adden Ed 67 RV EE 13 pb rta Pe eee e ed Sont E UU SUE ae 69 DMALAPA DRI NEE 69 DMA SIAT rete pP gege ee nU en pe EEE T E NE 70 E R TE 70 DVA E EE 70
56. d for the older PC 104 Plus Specification One method is to use slot positions 4 7 instead of the usual 0 3 The second is to short solder jumper B1 The PCI Slot Number can be configured as follows Switch PCI Slot Number Compatibility Master Position 0 Slot 0 closest to CPU 4 yes 1 Slot 1 4 yes 2 Slot 2 4 yes 3 Slot 3 4 yes 4 Slot 0 closest to CPU 3 yes 5 Slot 1 3 yes 6 Slot 2 3 If JP2 7 Slot 3 3 If JP2 Jumper JP2 Bus Master Control Install JP2 to enable bus mastering when in Slot 2 or Slot 3 in three bus master mode Solder Blob B1 Force Three Master The DM7820 offers a configuration solder blob at location B1 If this solder blob is open the default the board supports bus mastering in all 4 PCI slots when SW1 is in position 0 3 If it is closed the board will work in a 3 bus master configuration If B1 is closed SW1 positions 0 3 will be identical to positions 4 7 Note The DM7820 comes with solder blob B1 open by default This should be compatible with most PC 104 Plus CPUs There is no need to change this blob unless you are having compatibility problems with your specific CPU DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 9 Board Installation Installing the Hardware The DM7820 can be installed into a PC 104 Plus or PCI 104 stack It can be located above or below the CPU as long as all PCI add on cards are on the same side
57. e 12 Table 12 DMA Threshold Nybble Values Nybble Value Setting Nybble Value Setting Nybble Value Setting 0h 4 Lwords 5h 24 Lwords Ah 44 Lwords 1h 8 Lwords 6h 28 Lwords Bh 48 Lwords 2h 12 Lwords 7h 32 Lwords Ch 52 Lwords 3h 16 Lwords 8h 38 Lwords Dh 58 Lwords 4h 20 Lwords 9h 40 Lwords Eh 60 Lwords DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 72 DMADAn DMA PCI Dual Address Cycle Upper Address Bit Description Read Write Value after Reset Value to Use Upper 32 Bits of the PCI Dual Address Cycle 31 0 PCI Address during DMA Cycles If set to Oh the PCI 9056 performs a 32 bit address DMA access Yes Yes Oh INTCSR Interrupt Control Status Register Bit Description Read Write Value after Reset Value to Use Writing 1 enables LSERR to be asserted upon detection of a Local parity error or PCI Abort Yes Writing 1 enables LSERR to be asserted upon detection of an SERR assertion in Host mode or detection of a PCI parity error Generate PCI Bus SERR Interrupt When set to 0 writing 1 asserts the PCI Bus SERR interrupt Yes Yes Yes Yes or a messaging queue outbound overflow Mailbox Interrupt Enable Writing 1 enables a Local interrupt output LINTo to be asserted when the PCI Bus writes to MBOXO through MBOX3 To clear a LINTo interru
58. e interrupt Note Refer to the PCIBISTR register for a description of the self test Yes Yes Yes No No No 24 25 Reading 0 indicates the Direct Master was the Bus Master during a Master or Target Abort Reading 0 indicates that DMA Channel 0 was the Bus Master during a Master or Target Abort Yes Yes No No 26 Reading 0 indicates that DMA Channel 1 was the Bus Master during a Master or Target Abort Yes No 27 Reading O indicates that the PCI 9056 asserted a Target Abort after 256 consecutive Master Retries to a Target No 28 Reading 1 indicates that the PCI Bus wrote data to MBOXO Enabled only if the Mailbox Interrupt Enable bit is set INTCSR 3 1 No 29 Reading 1 indicates that the PCI Bus wrote data to MBOX1 Enabled only if the Mailbox Interrupt Enable bit is set INTCSR 3 1 No 30 Reading 1 indicates that the PCI Bus wrote data to MBOX2 Enabled only if the Mailbox Interrupt Enable bit is set INTCSR 3 1 Yes No DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 75 31 Reading 1 indicates that the PCI Bus wrote data to MBOX3 Enabled only if the Mailbox Interrupt Enable bit is set INTCSR 3 1 Yes No DM7820 DM9820 User s Manual 76 RTD Embedded Technologies Inc Additional Information PLX PCI9056 For more information about the PLX PCI9056
59. emoves samples from the FIFO at the same rate that they are stored keeping a constant number of samples in the FIFO When the triggering event happens Programmable Clock 2 is stopped and the FIFO begins to fill Also the triggering event starts Programmable Clock 3 which counts the number of samples to be captured after the triggering event When Programmable Clock 3 expires it stops Programmable Clock 0 and data collection ends The triggering event can also generate an interrupt that changes the FIFO output to PCI Read and start DMA transfers This allows the data to be moved to system memory before data collection has ended e Advint0 o Set to event desired o During the Interrupt Service Routine Change FIFO output clock to PCI Read Start DMA transfers e Prog Clock 0 Sample Input Clock o Period sample period DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 14 INTA o o Master Clock any Start Event always Stop Event Prog Clock 3 Continuous operation e Prog Clock 1 Pre capture clock o o o o Period N samples before event Master Clock Prog Clock 0 Start Event always One shot e Prog Clock 2 Sample output clock o o o o o Period same as Prog Clock 0 Master Clock same as Prog Clock 0 Start Event Prog Clock 1 Stop Event Advint 0 Continuous e Prog Clock 3 Post Capture clock o o Period M samples after event Master Clock
60. ffect the current counting sequence If the gate trigger is generated after the new count value is written and before the current counting ends the new count value is loaded to the CE at the falling edge of the next clock pulse and counting continues using the new count value The various roles of the gate input signals in the above modes are summarized in the following table 7 Gate Mo da n L Level Falling Edge Rising Edge H Level 0 Counting not possible Counting possible 1 Start of counting 2 Retriggering 1 Counting not possible f 2 e GE forced to H level Start of counting Counting possible 1 Counting not possible d l 3 2 Counter output forced to H level Start of counting Counting possible 4 Counting not possible Counting possible 5 1 Start of counting 2 Retriggering DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 60 Mode 0 CLK MAA E esrb b A E d AND 4 2 WR Ve 43 2 4 que 2 1 0 our GATE H EZ WR n 4 L 4 GATE m 4 ae A OUT Mode 1 ele AAA WR mgl 1 A uie EC org WR n 4 n 2 4 3 OUT GATE H L LT LJ GATE Al os 4 3 2 1 7 7 OUT n 4 lemp Mode 3 WR n 4 n 3 4 4 2 4 2 4 9 3 92 3 3 OUT GATE H p p EEEE 4 2 0 42 X 2 our nz5 DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 61 Mode A SJUUUUUUU UU UU UL 4 3 2 1 0 L OUT GATE
61. ial count value is N the one shot pulse interval equals N clock pulses The one shot pulse is not repetitive Gate function The gate signal setting to L level after the gate trigger does not affect the output When it is set to H level again from L level gate retriggering occurs the CR count value is loaded again and counting continues Count value writing during counting It does not affect the one shot pulse being counted until retriggering occurs Mode 2 Application Rate generator real time interrupt clock Output operation The output is set to H level by control word setting When the initial count value is decremented to 1 the output is set to L level during one clock pulse and is then set to H level again The initial count value is reloaded and the above sequence repeats In mode 2 the same sequence is repeated at intervals of N clock pulses if the initial count value is N for example Gate function H level validates counting and L level invalidates it If the gate signal is set to L level when the output pulse is L level the output is immediately set to H level At the falling edge of the clock pulse succeeding the trigger the count value is reloaded and counting starts The gate input can be used for counter synchronization in this way Count value load timing After the control word and initial count value is written the count value is loaded to the C
62. ing Yes Yes Yes Yes Scatter Gather Mode Writing 1 indicates DMA Scatter Gather mode is enabled For Scatter Gather mode the DMA source and destination addresses and byte count are loaded from memory in PCI or Local Address spaces Writing O indicates DMA Block mode is enabled Yes Yes 10 Done Interrupt Enable Writing 1 enables an interrupt when done Writing O disables an interrupt when done If DMA Clear Count mode is enabled DMAMODEO 16 1 the interrupt does not occur until the byte count is cleared Yes Yes Local Addressing Mode Writing 1 holds the Local Address Bus constant Writing 0 indicates the Local Address is incremented Yes Yes DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 67 Demand Mode Writing 1 causes the DMA Controller to operate in Demand mode In Demand mode the DMA Controller transfers data when its DREQO input is asserted Asserts DACKO to indicate the current Local Bus transfer is in response to DREQO input The DMA Controller transfers Lwords 32 bits of data This may result in multiple transfers for an 8 or 16 bit bus Yes Yes 0 1 13 14 Memory Write and Invalidate Mode for DMA Transfers When set to 1 the PCI 9056 performs Memory Write and Invalidate cycles to the PCI Bus The PCI 9056 supports Memory Write and Invalidate sizes of 8 or 16 Lwords The size is specified in the System Cache Line S
63. ite 1 to clear IncEnc1 Interrupt from Incremental Encoder block at 0x02CO0 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear PWMO Interrupt from Pulse Width Modulator block at 0x0300 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear PWM1 Interrupt from Pulse Width Modulator block at 0x0340 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear PCIKO Interrupt from Programmable Clock block at 0x0100 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear PCIK1 Interrupt from Programmable Clock block at 0x0140 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear PCIK2 Interrupt from Programmable Clock block at 0x0180 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear PCIK3 Interrupt from Programmable Clock block at 0x01C0 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear FIFOO Interrupt from FIFO block at 0Ox00CO 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear FIFO1 Interrupt from FIFO block at OxX00DO 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear Standard UO A diagram of the standard I O is shown in Figure 4 Each digital I O pin can be an input output or peripheral output
64. ize bits PCICLSR 7 0 If a size other than 8 or 16 is specified the PCI 9056 performs Write transfers rather than Memory Write and Invalidate transfers Transfers must start and end at cache line boundaries PCICR 4 must be set to 1 EOT Enable Writing 1 enables the EOT input pin Writing O disables the EOT input pin If DMAMODEO 14 and DMAMODE1 14 00b the EOT pin becomes the DMPAF pin Yes Yes Yes 0 X Yes 0 0 15 Fast Slow Terminate Mode Select Writing 0 sets the PCI 9056 into Slow Terminate mode As a result BLAST is asserted on the last Data transfer to terminate the DMA transfer Writing 1 sets the PCI 9056 into Fast Terminate mode and indicates the PCI 9056 DMA transfer terminates immediately when EOT if enabled is asserted or during DMA Demand mode when DREQO is de asserted Yes Yes 0 0 Clear Count Mode Writing 1 clears the byte count in each Scatter Gather descriptor when the corresponding DMA transfer is complete Yes Yes 0 X 17 Interrupt Select Writing 1 routes the interrupt to the PCI interrupt INTA Writing O routes the interrupt to the Local interrupt output LINTo Yes Yes 0 1 18 DAC Chain Load When set to 1 enables the descriptor to load the PCI Dual Address Cycles value Otherwise the descriptor loads the DMADACO register contents Yes Yes 0 X 19 EOT End Link Used only for DMA Scatter Gather transfers Value of 1 indica
65. l RTD Embedded Technologies Inc 62 The MSM82C54 2 features independent reading and writing from and to the same counter When a counter is programmed for the 2 byte counter value the following sequence is possible 1 Count value LSB reading New count value LSB writing 2 3 Count value MSB reading 4 New count value MSB writing An example of a counter latching program is given below MVIA OUT n3 IN n1 MOV B A IN n1 MOV C A 0100xxxx Denotes counter latching Write in control word address n3 The counter value at this point is latching Reading of the LSB of the counter value latched from counter 1 nl Conter 1 address Reading of MSB from counter 1 Figure 7 Counter latching executed for counter 1 Read Load 2 byte setting Read Back Command Operation Use of the read back command enables the user to check the count value program mode output pin state and null count flag of the selected counter The command is written in the control word register and the format is as shown below For this command the counter selection occurs according to bits D3 D2 and D1 DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 63 D7 De Ds Du D3 D2 Di Do 1 1 COUNT STATUS CNT2 CNT CNTO 0 CS 0 Ap Ay 1 RD 1 WR 0 Ds 0 Selected counter latch operation D4 0 Selected counter status latch operation D3 1 Counter 2 selection Do
66. la 1 Board STEE 1 Digital Ou a e a a e edo 1 Deep FIFOs With DMA ott te Edge AE e 1 P lse Width Modulators 22s sii ives ia aem te ae EENS dE eh 1 Incremental ENcoders oi dec ae n dee deeg E 1 Advanced ui ue EE 2 Programmable ClOCKS iaa EES 2 82054 imer GCotnters 1o Nn deri dere erg ir ta epa Rol Eeer 2 Physical ADUE S 2r irt it b e ere be bee dere bred 2 Avallable Optlonis oerte eto t ectetur e p e eap eer en tates 2 Getting Technical Support x et dete ee 3 Hardware Description tee Eee hava buts t rea bu t be des e bo ee re b eta 4 Block DITE Ve TKE TAE EE EE ero A curent dr Cent eet sd te ie e Lon 4 Connector and Jumper Locations enne eret rrerennnnn 5 BLOE 5 BIO EE 6 External UC Connections ierit eee ER ge e dada 6 Connector CN10 Digital Input Output 6 Connector CN11 Digital Input Output 7 PC 104 ISA Connectors DM 8O20 eene ener nn enne nnns 8 PC 104 Express Bus Connectors DM9820 eene ener 8 PC 104 Plus PCI Connector nee nem eren n nene nrnr nest nnn n nene ntnen nns n nnne 8 PCI Configuration Options DM7820 Om 8 Switch SW1 PCI Slot Gelechor sess entren nannte 9 Jumper JP2 Bus Master Control 9 Solder Blob B1 Force Three Master 9 Board Installations 2 038 Asia erre RR RR RARI dene EC a 10 Installing the ee UE 10 leede tee EE 10 Steps for Installing te OPE De P ed 10 Installin Eer TEE 11 Furictiorial OVerVIGW sarat teva ia ean ete Rede e baee du xe ro
67. lear Enables interrupt when channel B transitions from 0x0000 to OxFFFF Negative rollover 0 Interrupt is disabled 1 Interrupt is enabled ENA B POS Enables interrupt when channel B transitions from OxFFFF to 0x0000 Positive rollover 0 Interrupt is disabled 1 Interrupt is enabled EMA A NEG Enables interrupt when channel A transitions from 0x0000 to OxFFFF Negative rollover 0 Interrupt is disabled 1 Interrupt is enabled ENA A POS DM7820 DM9820 User s Manual 50 Enables interrupt when channel A transitions from OxFFFF to 0x0000 Positive rollover 0 Interrupt is disabled 1 Interrupt is enabled RTD Embedded Technologies Inc INCENCn_CLK This register selects the clock source for sampling the encoder inputs 15 4 3 0 Reserved CLOCK_SEL 3 0 R 0 RW 0 Field Description CLOCK_SEL 3 0 Selects the master clock Value definitions are 15 Inverted Strobe2 14 Inverted Strobe1 13 Strobe2 12 Strobe1 11 Prog Clock 3 10 Prog Clock 2 Prog Clock 1 Prog Clock 0 82C54 TC B2 82C54 TC B1 82C54 TC BO 82C54 TC A2 82C54 TC A1 82C54 TC AO Reserved 25 MHz OO N OQ PO O OO INCENCn MODE This register selects the mode of operation for the Incremental Encoder 15 8 PHASE FLT 7 0 RW 0 7 6 5 4 3 2 1 0 Reserved DIFF FILTER JOIN IDX_EN HOLD ENA R 0 RW 0 RW
68. lected in PWMn_CLK WIDTH_CLK The width is defined as the time that the non inverted output is high and the inverted output is low The width register is checked at the beginning of every period If the width register is modified in the middle of a period the output will not be affected until the next period Note that with PWMn_PERIOD set to the maximum value and the period clock and width clock set to the same source a 100 duty cycle is not possible 15 0 WIDTH 15 0 Field Description WIDTH 15 0 The width of the output WIDTH Width _ Clock _ Frequency 82C54 Timer Counter n The following section is taken from the MSM82C54 Datasheet from Oki Semiconductors For information on programming the 82C54 timer counters please consult the datasheet DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 55 DESCRIPTION OF OPERATION MSM82C54 2 functions are selected by control words from the CPU In the required program sequence the control word setting is followed by the count value setting and execution of the desired timer operation Control Word and Count Value Program Each counter operating mode is set by control word programming The control word format is outlined below D7 Dg Ds D4 D3 Do D4 Do T Select Counter Read Load Mode BCD CS 0 Ao A421 1 RD 1 WR 0 Table 7 Select Counter SC 1 0 Selection of set counter SC 1 0 Set Contents 00 Counter
69. n descriptor Same as DMA Block mode 2 Interrupt after Terminal Count Writing 1 causes Yes Yes Oh D an interrupt to be asserted after the terminal count for this descriptor is reached Writing 0 disables interrupts from being asserted 3 Direction of Transfer Writing 1 indicates Yes Yes Oh x transfers from the Local Bus to the PCI Bus Writing O indicates transfers from the PCI Bus to the Local Bus 31 4 Next Descriptor Address XOh aligned Yes Yes Oh D DMADPRO 3 0 0h DMACSRn DMA Channel n Command Status Bit Description Read Write Value Value after to Use Reset 0 Enable Writing 1 enables the channel to transfer Yes Yes Oh 1 data Writing O disables the channel from starting a DMA transfer and if in the process of transferring data suspends the transfer pause 1 Start Writing 1 causes the channel to start Yes Yes Oh x transferring data if the channel is enabled Set DM7820 DM9820 User s Manual 70 RTD Embedded Technologies Inc 2 Abort Writing 1 causes the channel to abort the Yes Yes Oh x current transfer The DMA Channel 0 Enable bit Set must be cleared DMACSRO 0 0 Sets the DMA Channel 0 Done bit DMACSRO 4 1 when the abort is complete 3 Clear Interrupt Writing 1 clears DMA Channel O Yes Yes Oh X interrupts Clr 4 Done Reading 1 indicates the transfer is Yes No Oh x complete
70. ndition has occurred Write 1 to clear b 7 0 Interrupt Enable 1 Interrupt is enabled 0 disabled Interrupt source are 7 Reserved 6 Reserved Underflow Overflow Empty Full Write Request Read Request 0x00D4 FIFO1_IN CLK 5 Reserved b 4 0 Input Clock Select 31 PCI Write 30 PCI Read 29 16 Interrupts 13 0 15 0 Clock_Bus 15 0 0x00D6 FIFO1_OUT_CLK b 15 5 Reserved b 4 0 Input Clock Select 31 PCI Write 30 PCI Read 29 16 Interrupts 13 0 15 0 Clock_Bus 15 0 0x00D8 FIFO1_IN DATA DREQ b 15 10 Reserved b 9 8 DREQ Source 3 Not Full 2 Write Request 1 Not Empty O Read Request b 7 4 Reserved b 3 0 Input Data Select 3 Incremental Encoder B1 2 Incremental Encoder BO 1 Port1 O PCI Data Ox00DA FIFO1_CON_STAT b 15 10 Reserved b 9 Write Request non sticky b 8 Read Request non sticky b 7 1 Reserved b 0 1 Enable 0 Clear 0x00DC FIFO1_RW_PORT b 15 0 Read Write Port Word access only Programmable Clock 0 0x0100 PRGCLKO_ID b 15 0 ID Register 0x1000 DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 20 Table 4 DM7820 DM9820 Memory Map Offset Register Name Register Function Hex PRGCLKO_MODE b 15 2 Reserved b 1 0 00 Disabled 01 Continuous 10 Reserved 11 One Shot 0x0104 PRGCLKO_CLK b 15 4 Reserved b 3 0 Master Clock Source 15 0 Clock_Bus 15 0 0x0106 PRGCLKO_START_STO
71. nto and read from the FIFO The Write Request is asserted when there is at least 256 words of space available in the FIFO and negated when there is less than 128 words available The Read Request is asserted when at least 256 words of data is in the FIFO and negated when there is less than 128 words of data Using these signals guarantees a burst of at least 128 words which provides for efficient communication over the PCI bus and robustly guards against over run and under run conditions However it does not allow for the FIFO to be completely filled of emptied The Not Full and Not Empty request source should only be used if the amount of data in the FIFO is known or to finish filling emptying the FIFO The DMA engine on the PLX PCI9056 will complete an additional double word transfer after the request is negated Therefore using the Not Full and Not Empty request source will generally result in an over run under run condition whenever the signal is negated The DREQ signals are in an undefined state when the FIFO is disabled The DMA engine should only be enabled after the FIFO is enabled FIFOn CON STAT ENA 15 10 9 8 7 2 1 0 Reserved DREQ_SRC 1 0 Reserved IN_DATA 1 0 R 0 RW 0 R 0 RW 0 Field Description DREQ_SRC 1 0 Selects the source for the DREQn signal to the PLX chip Value definitions are 3 Not Full 2 Write Request 1 Not Empty O Read Request IN_DATA 1 0
72. nuous mode the clock will generate a pulse train with the specified period In one shot mode the clock will generate a single pulse one period time after it is started The clock must be disabled when transitioning between modes 00 Disabled 01 Continuous 10 Reserved 11 One Shot Must be disabled and re enabled to produce a second pulse PRGCLKn_CLK This register selects the master clock for the programmable clock The clock should be disabled before modifying this register 15 4 3 0 CLOCK_SEL 3 0 Field Description CLOCK SEL 3 0 Selects the master clock Value definitions are 15 Inverted Strobe2 14 Inverted Strobe1 13 Strobe2 12 Strobe1 11 Prog Clock 3 10 Prog Clock 2 DM7820 DM9820 User s Manual 42 RTD Embedded Technologies Inc Field Description Prog Clock 1 Prog Clock 0 82C54 TC B2 82C54 TC B1 82C54 TC BO 82C54 TC A2 82C54 TC A1 82C54 TC A0 Reserved 25 MHz OO N OQ PO O OO PRGCLKn START STOP This register selects the Start and Stop Trigger for the programmable clock The clock will not begin generating an output until the first positive edge of the Start Trigger The first edge of the programmable clock output will occur one period after the Start Trigger edge If in continuous mode the clock will continue to run until the first edge of the Stop Trigger After the clock has stopped it must be disabled
73. og Clock 0 82C54 TC B2 82C54 TC B1 82C54 TC BO 82C54 TC A2 82C54 TC A1 82C54 TC AO Reserved 25 MHz OANWAHRUAONWO ADVINTn_PORTx_MASK This register determines if a bit is checked for the match and event interrupts Note If Match mode is selected and all bits are masked an interrupt will be generated immediately 15 14 13 12 11 10 9 8 Px_15 Px_14 Px_13 Px_12 Px_11 Px_10 Px_9 Px_8 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Px_7 Px_6 Px_5 Px_4 Px_3 Px_2 Px_1 Px_0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Field Description Px_ 15 0 Bit mask Bit definitions are 0 Bit is used for match event 1 Bit is ignored DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 47 ADVINTn_PORTx_CMP The compare register is used for the Match interrupt When all selected bits in this register match all selected bits on the input ports an interrupt is generated 15 14 13 12 11 10 9 8 Px_15 Px_14 Px_13 Px_12 Px_11 Px_10 Px_9 Px_8 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Px_7 Px_6 Px_5 Px_4 Px_3 Px_2 Px_1 Px_0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Field Description Px_ 15 0 Compare Value Bit definitions are 0 Interrupt when this bit is 0 when selected
74. operation is suspended when the first byte is written The output is immediately set to L level No clock pulse is required o After the second byte is written the new count value is loaded to the CE at the falling edge of the next clock o For the output to go to H level again N 1 clock pulse are necessary after new count value N is written e Count value writing when the gate signal is L level The count value is also loaded to the CE at the falling edge of the next clock pulse in this case When the gate signal is set DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 57 to H level the output is set to H level after the lapse of N clock pulses Since the count value is already loaded in the CE no clock pulse for loading in the CE is necessary Mode 1 Application Digital one shot Output operation The output is set to H level by the control word setting It is set to L level at the falling edge of the clock succeeding the gate trigger and kept at L level until the counter value becomes 0 Once the output is set to H level it is kept at H level until the clock pulse succeeding the next trigger pulse Count value load timing After the control word and initial count value are written the count value is loaded to the CE at the falling edge of the clock pulse succeeding the gate trigger and set the output to L level The one shot pulse starts in this way If the init
75. pdated at every interrupt or event PORTx y xor ADVINTn_ PORTx_CAPTIy and not ADVINTn PORTx MASK y 1 ADVINTn ID ID register to identify an Advanced Interrupt Block 15 0 ID_Register R Field Description ID_Register15 0 Value of 0x0001 indicates Advanced Interrupt ADVINTn_INT_MODE Selects the mode for this interrupt Event mode will generate an interrupt when any selected input pin changes Match mode will generate an interrupt when the port s match a pre set value bits can be individually selected or masked Strobe mode will generate an interrupt on the rising edge of the Strobe1 or Strobe2 signal 15 2 1 0 Reserved MODE 1 0 RW 0 RW 0 Field Description MODE 1 0 Interrupt Mode Value definitions are 3 Event Mode 2 Match Mode 1 Strobe Mode O Disabled DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 46 ADVINTn_CLK This register selects the clock source for sampling the ports when in Match or Compare mode In Strobe mode this register selects the actual strobe signal and the 25 MHz clock always serves as the sampling clock 15 4 3 0 Reserved CLOCK_SEL 3 0 R 0 RW 0 Field Description CLOCK SEL 3 0 Selects the master clock Value definitions are 15 Inverted Strobe2 14 Inverted Strobe1 13 Strobe2 12 Strobe1 11 Prog Clock 3 10 Prog Clock 2 Prog Clock 1 Pr
76. pt Enable bit INTCSR 8 Clearing the L2PDBELL register bits that caused the interrupt also clears the interrupt PCI Abort Interrupt Enable Value of 1 enables a Master Abort or Master detection of a Target Abort to assert a PCI interrupt INTA Used in conjunction with the PCI Interrupt Enable bit INTCSR 8 Clearing the Received Master and Target Abort bits PCISR 13 12 also clears the PCI interrupt Yes Yes Yes 0 0 Yes 0 0 11 12 Local Interrupt Input Enable Writing 1 enables a Local interrupt input LINTi assertion to assert a PCI interrupt INTA Used in conjunction with the PCI Interrupt Enable bit INTCSR 8 De asserting LINTi also clears the interrupt Retry Abort Enable Writing 1 enables the PCI 9056 to treat 256 consecutive Master Retries to a Target as a Target Abort Writing 0 enables the PCI 9056 to attempt Master Retries indefinitely Yes Yes Yes 0 0 Yes 0 0 13 PCI Doorbell Interrupt Active When set to 1 indicates the PCI Doorbell interrupt is active Yes No 0 0 14 PCI Abort Interrupt Active When set to 1 indicates the PCI Master or Target Abort interrupt is active Yes No 0 0 15 Local Interrupt Input Active When set to 1 indicates the Local interrupt input LINTi is active Yes No 0 0 16 Local Interrupt Output Enable Writing 1 enables Local interrupt output LINTo Yes Yes 1 1 17 Local Doorbell
77. pt the Local Bus Master must read the Mailbox Used in conjunction with the Local Interrupt Output Enable bit INTCSR 16 Yes Power Management Interrupt Enable Writing 1 enables a Local interrupt output LINTo to be asserted when the Power Management Power State changes Yes Yes Power Management Interrupt When set to 1 indicates a Power Management interrupt is pending A Power Management interrupt is caused by a change in the Power Management Control Status register Power State bits PMCSR 1 0 Writing 1 clears the interrupt Writable from the PCI Bus only in the DO power state Yes Yes Clr DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 73 Direct Master Write Direct Slave Read Local Data Parity Check Error Enable Writing 1 enables a Local Bus Data Parity Error signal to be asserted through the LSERR pin INTCSR O must be enabled for this to have an effect Yes 0 0 Direct Master Write Direct Slave Read Local Data Parity Check Error Status When set to 1 indicates the PCI 9056 has detected a Local data parity check error even if Parity Check Error is disabled INTCSR 6 0 Writing 1 clears this bit to 0 Yes Yes Clr 0 0 PCI Interrupt Enable Writing 1 enables PCI interrupts INTA Yes Yes 1 1 10 PCI Doorbell Interrupt Enable Writing 1 enables Local to PCl Doorbell interrupts Used in conjunction with the PCI Interru
78. s 0 Not ready to receive data 1 Ready to receive data READ REQ Current Read Request Status 0 Not ready to send data 1 Ready to send data ENA FIFO Enable 0 FIFO is disabled and cleared 1 FIFO is enabled Elton RW PORT This register provides the PCI bus access to the FIFO Reads from this register return the current data that is available at the output of the FIFO and can be programmed to clock the next data out of the FIFO Writes to this register can be programmed to write data into the FIFO Accesses to this register must be word 16 bit or larger 15 0 DATA 15 0 RW 0 Field Description DATA The read or write data to the FIFO Programmable Clock n There are four programmable clocks on the DM7820 DM9820 They can be cascaded The Programmable Clocks use a master clock and divide it down by an integer An interrupt is generated at every positive edge of the clock output DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 41 PROGCLKn ID ID register to identify a Programmable Clock Block 15 ID Register R Field Description ID Register15 0 Value of 0x1000 indicates Programmable Clock PROGCLKn MODE Selects the mode that the Programmable Clock 15 2 1 0 Reserved MODE RW 0 RW 00 Field Description MODE Selects continuous or one shot mode In conti
79. s the DMA Done bit DMACSRO 4 1 31 22 Reserved Yes No 0 0 DMAPADRn DMA PCI Address Bit Description Read Write Value Value after to Use Reset 31 0 PCI Address Indicates from where in PCI Yes Yes Oh x Memory space DMA transfers reads or writes start Value is a physical address DMALAPADRn DMA Local Address Bit Description Read Write Value Value after to Use Reset 31 0 DMA Channel Local Address Indicates from Yes Yes Oh x where in Local Memory space DMA transfers reads or writes start DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 69 DMASIZn DMA Transfer Size Bit Description Read Write Value Value after to Use Reset 22 0 Transfer Size Bytes Indicates the number of Yes Yes Oh X bytes to transfer during a DMA operation 30 23 Reserved Yes No Oh Oh 31 Ring Management Valid When Ring Yes Yes 0 X Management Valid Mode is enabled DMAMODE0O 20 1 indicates the validity of this DMA descriptor DMAPRn DMA Channel n Descriptor Pointer Bit Description Read Write Value Value after to Use Reset 0 Descriptor Location Writing 1 indicates PCI Yes Yes Oh 1 Address space Writing 0 indicates Local Address space 1 End of Chain Writing 1 indicates end of chain Yes Yes Oh x Writing 0 indicates not end of chai
80. t 0 Mask 0 Bit is used for match event 1 Bit is ignored 0x020A ADVINTO_PORT1_MASK b 15 0 Port 1 Mask 0 Bit is used for match event 1 Bit is ignored 0x020C ADVINTO_PORT2_MASK b 15 0 Port 2 Mask 0 Bit is used for match event 1 Bit is ignored 0x020E_ Reseved A AAA AA A AA e nud ADVINTO PORTO CMP b 15 0 Port 0 Compare Value used for interrupt on match poe ADVINTO PORT1 CMP b 15 0 Port 1 Compare Value used for interrupt on match EE ADVINTO PORT2 CMP b 15 0 Port 2 Compare Value used for interrupt on match ESAS 0x0216 Reserved register when an interrupt occurs TTT P egster nen an empacar OO register when an interrupt occurs register when an interrupt occurs ee eee A A 0x021E Reserved Advanced Interrupt 1 ADVINT1_INT_MODE b 1 0 Interrupt Mode 3 Event Mode 2 Match Mode 1 Strobe Mode Disabled 0 0x0244 ADVINT1_CLK b 3 0 Sample Clock Source 15 0 Clock_Bus 15 0 0x0246 0x0248 ADVINT1 PORTO MASK b 15 0 Port 0 Mask 0 Bit is used for match event 1 Bit is ignored 0x024A ADVINT1_PORT1_MASK b 15 0 Port 1 Mask 0 Bit is used for match event 1 Bit is ignored DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 23 Table 4 DM7820 DM9820 Memory Map Hex 0x024C ADVINT1_PORT2_MASK b 15 0 Port 2 Mask 0 Bit is used for match event T Bit is ee
81. t 0x01C0 0 Interrupt Disabled 4 Interrupt Enabled FIFOO Interrupt from FIFO block at OxXDOCO 0 Interrupt Disabled 1 Interrupt Enabled FIFO1 Interrupt from FIFO block at OxX00DO 0 Interrupt Disabled 1 Interrupt Enabled INT_STATUS This register shows if any of the interrupt conditions has occurred This is a sticky register bits remain set until cleared by writing a 1 Interrupts do not have to be enabled in INT_ENABLE in order for status bits to be set 15 14 13 12 11 10 9 FIFO1 FIFOO PCIK3 PCIK2 PClk1 PCIKO PWM1 PWMO RC 0 RC 0 RC 0 RC 0 RC 0 RC 0 RC 0 RC 0 7 6 5 4 3 2 1 0 Reserved IncEnc1 IncEncO Rsvd 82C54 Advint1 AdvintO R 00 RC 0 RC 0 R 0 RC 0 RC 0 RC 0 Field Description AdvintO Interrupt from Advance Interrupt block at 0x0200 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear Advint1 Interrupt from Advance Interrupt block at 0x0240 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear 82C54 Interrupt 82C54 Timer Counter block at 0x0080 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear IncEncO Interrupt from Incremental Encoder block at 0x0280 0 Interrupt has not occurred DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 29 1 Interrupt has occurred Wr
82. tes that when EOT is asserted the DMA transfer ends the current Scatter Gather link and continues with the remaining Scatter Gather transfers Value of 0 indicates that when EOT is asserted the DMA transfer ends the current Scatter Gather transfer and does not continue with the remaining Scatter Gather transfers Yes DM7820 DM9820 User s Manual 68 RTD Embedded Technologies Inc 20 Ring Management Valid Mode Enable Value of Yes Yes 0 x O indicates the Ring Management Valid bit DMASIZO 31 is ignored Value of 1 indicates the DMA descriptors are processed only when the Ring Management Valid bit is set DMASIZO 31 1 If the Valid bit is set the transfer count is 0 and the descriptor is not the last descriptor in the chain The DMA Controller then moves to the next descriptor in the chain Note Descriptor Memory fields are re ordered when this bit is set 21 Ring Management Valid Stop Control Value of Yes Yes 0 D 0 indicates the DMA Scatter Gather controller continuously polls a descriptor with the Valid bit set to O invalid descriptor if Ring Management Valid Mode is enabled DMAMODEO 20 1 Value of 1 indicates the Scatter Gather controller stops polling when the Ring Management Valid bit with a value of 0 is detected DMASIZ0 31 0 In this case the CPU must restart the DMA Controller by setting the Start bit DMACSRO 1 1 A pause clearing the Start bit DMACSRO 1 0 set
83. the board The type ID can be used to identify a particular feature set 15 8 7 0 TYPE_ID VERSION R XXXX XXXX R XXXX XXXX Field Description TYPE ID FPGA Type Identifier 0x10 Standard FPGA VERSION FPGA Version Identifier SVN_VERSION This register provides the source code revision control version It is updated every time the FPGA is compiled 15 0 VERSION R XXXX XXXX XXXX XXXX VERSION FPGA Source Version Identifier BOARD RESET Writing a value of OxA5A5 to this register resets the board All internal registers are set to their default values Note The 82C54 Timer Counters are not affected by this register RESET W 0000 0000 0000 0000 Field Description RESET Write OxA5A5 to reset the board All other writes are DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 27 ignored Reads will return all Zeros BRD_STAT This register contains status information for the board 15 1 0 Reserved MSTR R 0 R N Field Description MSTR Indicates if the board is PCI master capable based on the rotary switch and jumper settings 0 PCI Master 1 Not PCI Master INT_ENABLE This register controls which interrupt sources are used to generate a local interrupt 15 14 13 12
84. the board manual and application software DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 3 Hardware Description Block Diagram Below is a block diagram of the DM7820 DM9820 Primary board components are in bold while external I O connections and jumpers are italicized DM7820 DM9820 Block Diagram 48 Digital I O Digital 1 O FPGA 82C54 Timer Counters PLX PCI9056 or PEX8311 Figure 1 DM7820 DM9820 Block Diagram DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 4 Connector and Jumper Locations DM7820 The following diagram shows the location of all connectors and jumpers on the DM7820 Fora description of each jumper and connector refer to the following sections DM7820 Connector and Jumper Locations PC 104 Plus Connector JP2 PCI Master Control CN11 Digital I O Digital UO Slot Selection PC 104 Connector DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 5 DM9820 The following diagram shows the location of all connectors and jumpers on the DM9820 Fora description of each jumper and connector refer to the following sections DM9820 Connector and Jumper Locations PC 104 Plus Connector pass through CN11 Digital I O Digital UO PC 104 Express Connector External LO Connections The following sections describe the external UO connections of the DM7820 DM9820 Connector CN10 Digital Input Output Connector CN10 provides
85. tion Connect to FIFO for position sampling DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 1 Advanced Interrupts Two Advanced Interrupt Modules Interrupt on Match Change or Strobe All 48 bits are captured when the interrupt is generated Any combination of the 48 bits can be monitored Programmable Clocks Four programmable clocks Maximum frequency of 25 MHz Can be started and stopped by an interrupt or another clock Continuous or One Shot Operation Can be cascaded 82C54 Timer Counters Six Timer Counter Channels Fully programmable Input clock and gate driven from internal or external source 10 MHz maximum input Physical Attributes Size 3 6 L x 3 8 W x 0 6 H 90mm L x 96mm W x 15mm HI Weight 0 22 Ibs 0 10 Kg Operating Temperature 40 C to 85 C Storage Temperature 55 C to 125 C Power Requirements Typical 1 5 W 5 VDC Available Options The DM7820 DM9820 is a modular design Custom feature sets are available Please contact RTD Embedded Technologies for more information on custom boards DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 2 Getting Technical Support For help with this product or any other product made by RTD you can contact RTD Embedded Technologies via the following methods Phone 1 814 234 8087 E Mail techsupport rtd com Be sure to check the RTD web site http www rtd com frequently for product updates including newer versions of
86. transferable During the one year warranty period RTD EMBEDDED TECHNOLOGIES will repair or replace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid to RTD EMBEDDED TECHNOLOGIES All replaced parts and products become the property of RTD EMBEDDED TECHNOLOGIES Before returning any product for repair customers are required to contact the factory for an RMA number THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY PRODUCTS WHICH HAVE BEEN DAMAGED AS A RESULT OF ACCIDENT MISUSE ABUSE such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by RTD EMBEDDED TECHNOLOGIES acts of God or other contingencies beyond the control of RTD EMBEDDED TECHNOLOGIES OR AS A RESULT OF SERVICE OR MODIFICATION BY ANYONE OTHER THAN RTD EMBEDDED TECHNOLOGIES EXCEPT AS EXPRESSLY SET FORTH ABOVE NO OTHER WARRANTIES ARE EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND RTD EMBEDDED TECHNOLOGIES EXPRESSLY DISCLAIMS ALL WARRANTIES NOT STATED HEREIN ALL IMPLIED WARRANTIES INCLUDING IMPLIED WARRANTIES FOR MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE LIMITED TO THE DURATION OF THIS WARRANTY IN THE EVENT THE PRODUCT IS NOT FREE FROM DEFECTS AS WARRANTED ABOVE THE PURCHASER S SOLE REMEDY SHALL BE REPAIR OR REPLACEME
87. ts and also the PCI interface Each FIFO is attached to a DMA Channel in the PLX chip FIFOO is attached to DMAO and FIFO1 is attached to DMA1 FIFOO can have its input data attached to its output data In this case the same data is repeated forever This is useful for some types of pattern generation Internally the FIFO system consists of a single 8MB SDRAM device with 255 word input and output buffers for each channel When data is available in the input buffer it is moved into the area of SDRAM device for that channel When data is in the SDRAM device and there is room available in the output buffer data is moved to the output buffer All of the internal data movement is handled automatically Greatest data efficiency is achieved when there is at least 128 words of data in the FIFO DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 12 The FIFO also provides Write Request and Read Request signals For these signals the internal buffers are monitored to signal when data can be sent into and read from the FIFO The Write Request is asserted when there is at least 256 words of space available in the FIFO and negated when there is less than 128 words available The Read Request is asserted when at least 256 words of data is in the FIFO and negated when there is less than 128 words of data Using these signals guarantees a burst of at least 128 words which provides for efficient communication over the
88. ue pax e tada tt fae eR t deed aaa 12 te Ieren CEET 12 iae ce 12 Board Interrupts ui eee aped im E dde ee iesu bid 13 Advanced Triggering Examples TE 14 Board Operation and Programing nennen emnes 16 PCI Interface ccoo AA dE EE ee de ee 16 Device Memory occitano 16 Memory Map Overview ssssssessse nennen enne e nnns enne nne nennen nenne nnns 16 Detailed Register Description coccion renean taedet atn a ea eia nd 26 Siculis Em 27 FPGA VERSION cic EDS 27 SVN VERSI N tadas a A a eae ee ae eA 27 BOARD RESET oi Ee ane ea ad ee 27 BRD STA EE 28 INT ENABLE 2 ni ptt Ee dae tee dct tee dd e 28 ICH RR cT c LEER M RIETI 29 Standard Dic a teens tel hers at on ted tata eter adios toate A aon 30 PORT Re NR NEE EE 31 PORT IN PU T eeh eared ee 31 POR TX TRISTATE EE 32 POR Tx MODE ie e E 32 PORT PERIPH SEL rita a ten Ife a REP accra 33 PORTX BERIPEISSED H 2 2 rrt int ier lid e 33 STROBE STATUS EE 34 82C54 Timer Counter Control 35 OG eID sien i edite Eegen E D bdo ture toma remitente nes nebst s de 35 yeu EET 35 TOX CONTRO Ls EEN 36 FIFO Ghatnnelipizs nissan hacer eere qe EE 37 PIF On e 8 EE 37 FIR On INIT ibt os terere terae tite int DO ua bets Ide 37 FIEOnIN Gli o m ctum ita m dier rua ito a echo ds 38 FIFOn OU CDI a tecto za edere eat eem eia tela dete d ves teen eas 39 FIFOti IN DATA DREQ ire cA ce etd a ee 40 FIF OM CON STAT EE 41 FIFON RW RER eee e Me Hte de 41 Programmable Clock Ti iie
89. upt 17 Advanced Interrupt 1 Interrupt 16 Advanced Interrupt 0 Interrupt 15 Inverted Strobe2 14 Inverted Strobe1 13 Strobe2 12 Strobe1 11 Prog Clock 3 10 Prog Clock 2 Prog Clock 1 Prog Clock 0 82C54 TC B2 82C54 TC B1 82C54 TC BO 82C54 TC A2 82C54 TC A1 82C54 TC AO Reserved Do Not Stop OO N OQ PO O OO PROGCLKn PERIOD Sets the period of the programmable clock 15 0 PERIOD 15 0 RW 0 PERIOD 15 0 The frequency of the output clock is Master _ Clock _ Frequency PERIOD 1 DM7820 DM9820 User s Manual RTD Embedded Technologies Inc 45 Advanced Interrupt n Two Advanced Interrupt block are provided that can generate an interrupt on a match event or strobe The match and event interrupts are across all 48 digital I O The bits can be individually selected When an interrupt is generated the data on all of the ports is latched into the Capture registers Bits are tested regardless of if a pin is an input or output A Match interrupt is generated when all un masked bits in the Compare register match the input value of the port This is when the following expression is true for ALL ports x and bits y PORTx y xor ADVINTn_ PORTx CMPIy and not ADVINTn PORTx MASKIy 0 An Event interrupt is generated when any un masked input port bit changes This is when the following expression is true for ANY ports x and bits y Note that the Capture register is u
90. utive clock pulses When the counter value becomes 0 the output is set to L level and then the initial count value minus 1 is reloaded to the CE The value is then decremented by 2 by consecutive clock pulses When the counter value becomes 2 the output is again set to H level and the initial count value minus 1 is again reloaded The above operations are repeated In other words the output is set to H level during N 1 2 counting and to L level during N 1 2 counting in the case of odd number counting Mode 4 Application Software trigger strobe Output operation The output is initially set to H level When the counter value becomes 0 the output goes to L level during one clock pulse and then restores H level again The count sequence starts when the initial count value is written Gate function H level validates counting and L level invalidates counting The gate signal does not affect the output Count value load timing After the control word and initial count value are written the count value is loaded to the CE at the falling edge of the next clock pulse The clock pulse does not decrement the initial count value If the initial count value is N the strobe is not output unless N 1 clock pulses are input after the initial count value is written Count value writing during counting The new count value is written to the CE at the falling edge of the next clock pulse and counting

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