SVGA+ Rev3 XL SERIES 852 X 600 ACTIVE MATRIX
Contents
1. 44 14 APPENDIX B COMPOSITE SIGNAL INPUT CONNECTIONS rnnnnnvnnnnvnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnr 45 15 APPENDIX C REVISION HISTORY rrnnnvnnnnnvnnnvvnnnnvennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnr 46 Rev 4 SVGA Rev3 XL Series User s Manual i AeMagin LIST OF FIGURES Figure 3 1 Microdisplay functional block diagram eee Figure 7 1 Mechanical Characteristics Figure 9 1 Analog Inputs Block Diagram Figure 9 2 Input Multiplexer Block Diagram Figure 9 3 Dual Sample amp Hold Block Diagram Figure 9 4 OLED I V Characteristic Log and Linear scale Figure 9 5 Sample Circuit Designs Using External References esses ener trennen nnne nnne 19 Figure 9 6 Luminance as a Function of YER Figure 9 7 Typical Contrast Ratio as a Function of Vblack Figure 9 8 Serial Interface Protocol sese eee Figure 10 1 Register EE Figure 13 1 Microdisplay Carrier Board Electrical Diagram sss sese eee 44 LIST OF TABLES TABLE 2 1 GENERAL CHARACTERISTICS eee TABLE 3 1 SVGA MICRODISPLAY VIDEO FORMATS TABLE 4 1 INPUT OUTPUT DESCRIPTION sese TABLE 5 1 ABSOLUTE MAXIMUM RATINGSS sees nennen eene tre nen enee tete nenne nete ene etre enne TABLE 5 2 RECOMMENDED OPERATING CONDITIONS TABLE 5 3 DC CHARACTERISTICS DC CHARACTERISTICS eee2. Vbh is the reference level used during the light emission phase of the pixel driver operation which lasts most of the video frame Vbh switches the pixel driver current range down by roughly 100 times in order to bring it to the typical operating levels required by the OLED Vbh operates typically at 200 mV above Vbh Varying Vbh causes the current through the OLED to change and thus the luminance to change Since this is a global input it affects the entire display and therefore can be used for dimming control The relationship between Vbh and the luminance is exponential The dimming range can be over 1000 1 over 200 mV One consequence of this relationship is the high sensitivity to Vbh A few millivolts will yield a large luminance variation Rev 4 SVGA Rev3 XL Series User s Manual 19 A e AeMagin Note that bringing Vbh less than 100 mV above Vbl will result in a washed out display with no modulation as well as a high luminance level that will accelerate the display aging The graph below illustrate the luminance response as a function of Vbh for a color microdisplay For this measurement Vbl 2 0V Luminance vs Vbh 1000 100 2 10 9 Ou o c a c t 1 3 0 1 0 01 21 2 15 22 2 25 23 2 35 2 4 2 45 2 5 2 55 Vbh Volt Figure 9 6 Luminance as a Function of Vbh Vblack is a reference level used to reset the pixel driver to the black level at the beginning of each line Using an externally generat
3. 0C 0E 18 EC 16 D8 OG 32 80 00 08 SVGA 85 VGA 60 VGA 72 VGA 75 00 00 00 00 78 78 78 78 30 30 30 30 78 78 78 78 30 30 30 30 78 78 78 78 30 30 30 30 80 80 80 80 38 38 38 38 00 04 04 04 02 01 01 01 00 00 00 00 02 02 02 02 00 00 00 00 80 80 80 80 16 1D 3E 46 04 0B 0B 0B OF 08 09 0A 18 18 18 18 D4 8B A4 B4 1C 21 1D 11 D8 D8 D8 D8 0C 0C 0C 0C 32 32 32 32 80 80 80 80 00 00 00 00 08 08 08 08 Note The last two digits after the video format indicate the refresh rate in Hz SVGA Rev3 XL Series User s Manual VGA 85 00 78 30 78 30 78 30 80 38 04 01 00 02 00 80 3E 0B 0B 18 84 1A D8 OG 32 80 00 08 42 AeMagin 12 2 Other Modes TABLE 12 2 NON VESA MODES REGISTER SETTINGS ZOOM 75 DVD 60 NTSC 170 Notes 1 The last two digits after the video format indicate the refresh rate in Hz 2 Zoom stands for an 852 x 600 format 3 DVD stands for an 852 x 480 format 4 PAL settings support the following PAL standards I B G H D N Use NTSC settings for PAL M Rev 4 SVGA Rev3 XL Series User s Manual 43 AeMagin 13 APPENDIX A MICRODISPLAY CARRIER BOARD ELECTRICAL DIAGRAM AVDD H Rt
4. Ta 20 C GND 0V VDD 3 3V VAN 4V Vcommon 3 0 Parameter 0 0 0 0 0 0 00 0 0 Vol jDigialoupulowlevel S Ivblack External Black Reference Current V MONO MONO Analog input de level V RGB VESA Inputs signal level 0 O SVGA Mode 60 Hz refresh rate SVGA Mode 60 Hz refresh rate WENN CO NN Dissipation 3 0V Notes 1 The RED GREEN and BLUE inputs are CMOS inputs No termination other than those required by the driving source and cable characteristics are required 2 The MONO channel includes a dc restore circuit A non polarized ac coupling capacitor is required for proper operation TABLE 5 4 AC CHARACTERISTICS Ta 20 C GND 0 V VDD 3 3V Van 4 0V VCOMMON 3 0 Fvelk Video Clock Frequency 10 5625 Mz Ths Horizontal Syne frequency 157 53 KHz Thsw Hsyne Pulse Width The Tvs Vertical Sync Frequency 3 LL 8 Hz Tvsw Vane Pulse Width o 2 Ta Trst Reset Pulse Width 100 f J m Cpwm PWMOupuLod 1 4 8 J pF Cav Analog input capacitance d 5 J 8 Prr Note 1 Maximum refresh rate for SVGA mode is 85 Hz For interlaced mode the frame rate may be as low as 30 Hz SMPTE Modes Rev 4 SVGA Rev3 XL Series User s Manual 7 e AeMagin 5 1 Analog R G B Input Characteristics Input Characteristics per VESA VSIS rev 1 0 TABLE 5 5 INPUT CHARACTERISTICS 0 700 Volts 0 03
5. the OLED current measured at the Vcommon terminal is first measured when the video input has been set to black The Vcommon current is then recorded dark current and the video input is set to white maximum video input level The Vcommon current is then adjusted to add exactly 20 mA cm2 to the dark current The white luminance is then measured as well as the color coordinates The contrast is then obtained by taking a luminance measurement with the video inputs set to black without adjusting any other parameter Minimum Luminance is defined as the lowest luminance level for which a 100 1 contrast ratio is measurable Maximum Luminance is defined as the maximum luminance the microdisplay can provide while keeping the black level 0V data input at or below 1 cd m2 In order to reach the maximum value mentioned in the tables above it will be necessary to adjust the VCommon input to a lower level typically close to 4 5V The minimum and maximum luminance levels are obtained by adjusting the external voltage reference Vbh and Vbl being kept at a fixed level See section VOLTAGE REFERENCES page 9 Rev 4 SVGA Rev3 XL Series User s Manual 10 AeMagin 7 MECHANICAL CHARACTERISTICS Figure 7 1 Mechanical Characteristics Rev 4 SVGA Rev3 XL Series User s Manual AeMagin Connector J1 Manufactu
6. 24 A e AeMagin The serial interface consists of a serial controller and registers The serial controller follows most of the I2C slave device protocol clock stretching 1s not supported by this device An internal address decoder transfers the content of the data into appropriate registers The protocol will follow the address byte followed by register address data byte and register data byte sequence 3 bytes for each register access Serial address with write command Register address Register data The registers are designed to be read write Read mode is accomplished via a 4 byte sequence Serial address with write command Register address Serial address with read command Register data RANDOM REGISTER WRITE PROCEDURE 011001 x WA A AP 7 bit address E register address 1 data E Acknowledge Acknowledge STOP condition START condition WRITE command Acknowledge RANDOM REGISTER READ PROCEDURE 50011001 x WA AS 011001xRA AP 7 bit address T register address T 7 bit address t data Acknowledge Acknowledge Acknowledge START condition WRITE command READ condition NO Acknowledg STOP condition Figure 9 8 Serial Interface Protocol The serial controller is capable of slave mode only The x in the 7 bit address code is set by the SERADD input pin and is provided to allow a dual display and single controller configuration Slave Address 011001X where X 0 or 1 depending on the status of the SERADD pin Write Mode
7. 7 4 8 Luminance control base frequency register PIF 3 0 3 0 1 Pixel Clock Frequency Selection Default is Zoom 60 Hz 41 707 MHz PIBYP 7 0 Phase Interpolator Bypass 1 Bypassed 0 Not bypassed PHSEL 1 0 BRE PLL Clock phase selection when PIBYP 1 90 phase selection PHASE 4 0 40 0 PLL Clock phase adjustment when PiBYP 0 32 steps HSTART HSTART 7 0 Horizontal Active Start Counter VSTART VSTART5 0 5 0 18 Vertical Active Start Counter vstane Tee o Reemed 75 T HRK T mw mer 70 so Jr SSCS 1 POWN T Ww OWN 7 0 Bias Bock power down PowerDown Powe 6 0 BLACK Buffer power down i FowerDown POWs 5 0 VeHBuferpowerdow i PowerDown Pm 4 0 VBL Bufer power down iPower Domn pows 3 0 Phase interpolator Power down T PowerDown Pm 2 0 Eieren i PowerDown POWNO o 9 egene powerdown i PomerDomn ATB7 7 0 Power Down Source 1 PWDN Register 0 Internal SE eo 0 Rewwd ERLIEN EE __ Li E 1 i e eee Figure 10 1 Register Map Summary Note Reserved registers have a default power on value and do not need to be updated These registers are meant for device test and should be left as is Attempts at writing any of these registers may lead to permanent functional damage to the microdisplay Rev 4 SVGA Rev3 XL Series User s Manual 30 Ae
8. SVGA Rev2 XL OLED Microdisplay except the Rev3 requires input for the Vbh and Vbl terminals previously generated internally This change allows for a more monotonic behavior of the luminance as a function of temperature improving the integration of the SVGA microdisplay in rugged environment compatible systems This series of microdisplays was dubbed SVGA Super Video Graphics Array plus because they 52 more display columns than a standard SVGA display This design permits users to run either 1 standard SVGA 800 x 600 pixels to interface to the analog output of many portable computers or 2 852 x 480 using all the data available from a DVD player in a 16 9 wide screen entertainment format The SVGA can be made as a full color or monochrome microdisplay primarily for high performance and large view consumer OEM products such as games video data head wearable displays digital cameras video cameras and other portable electronics applications The display also has an internal NTSC and PAL monochrome video decoder suitable for low power night vision systems This product is designed to interface with most portable personal computers See Chapter 8 Handling prior to use of displays with or without glass covers This specification applies to the following SVGA Rev3 XL Series OLED microdisplay models Color EMA 100310 01 White monochrome EMA 100309 01 Green monochrome EMA 100311 01 NOTE Please refer to the D
9. Sequencer and Row Driver 21 9 7 Horizontal amp Burn in Geouencerg ener enne nnns nnn senes 22 9 8 Burn in compensation Sequencer esee enne nennen enne nnns nn nnns 23 9 9 eie sten EE 24 9 10 Sync PIOCOSSOE i ee SE 24 Oe Ser llntenate EE 24 9 11 1 Sequential Read Write Operation 25 9 12 Power On seouence esent tnen nnns inns Eai senes nsns sinn teen aa aeai Eaa nenas 26 9 13 Power Down Modos aaaea aandag ahann anha E ESENES EAA Ean Niat Tahaa Eai ER ERR 26 9 19 1 Automatic Power Down Mode 2 tin rcr dnne daredesasleedapbedeesnanreisdreskite 26 9 13 2 Manual Power Down Mode rrnrnnvnnernnvvnennnnvnrnrnnvnnnrvnvnnenennnnenennvnnnvsnrnnenennensnrnnnnensenrnnenennnssrnnnnenvenrnserene 26 9 14 Display Modes Configurations and Characteristics sese eee eee eee 27 9 14 1 ee 27 9 14 2 Interlaced Video RO eie iiinn iire aa er ar aeaa reah aiaa Erea Ea Aa eae E E E RENEA EEES 28 9 143 Zoom amp 16 9 uec En 28 10 REGISTER MAP SUMMARY i nnnnnvrnnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnr 29 11 DETAILED REGISTER DESCRIPTION rrnnnnnnnnvvnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennnnnnnnnnnnnnnennnnr 31 12 REGISTER TABLE CONFIGURATION rnnnnnnnnvvnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnr 42 121e VESA ee 42 e EE 43 13 APPENDIX A MICRODISPLAY CARRIER BOARD ELECTRICAL DIAGRAM
10. TABLE 3 1 SVGA MICRODISPLAY VIDEO FORMATS 800 x 600 Monochrome Interlaced Scan 800x 600 Monochrome Pseudo Interlaced Scan 852 x 480 Color 16 9 Format B52 x 600 Color NOTES 1 All progressive scan input modes should use the R G B video inputs All interlaced input modes should use the MONO composite video input However all progressive scan color modes are available in the primary monochrome which can be activated through the registers Other modes are also available 2 A pseudo interlaced scan is equivalent to a line doubling scan during which two adjacent rows are enabled at the same time A one row offset occurs every even field 3 800 x 600 Monochrome modes are compatible with all forms of PAL CCIR except for PAL M PAL M uses 525 lines thus 640 x 480 Monochrome modes should be used 4 The Zoom mode is the power on default operating mode of the microdisplay Selection between the non interlaced and interlaced modes is done through a register set via the on chip serial interface The power up default is a non interlaced Zoom 60Hz mode The serial interface also provides for user adjustments such as contrast brightness PLL parameters display orientation an externally hardwired control is also provided Standard VESA analog video modes do not carry the video clock which has to be regenerated on chip A clock recovery circuit based on a digital phase locked loop circuit provides a recovered pixel clock The PLL has defau
11. VCOVDD vec vec AVDD VAN 9 10 L E aee Tor Aur FERRITE ca i cs T COGND AUF AR RAF o e L uF 10UF AGND AGND AGND BEND VAN AVDD vec ves d ca L j R2 tuF 22K vec Van COMMON 9 us 22222 aca an cext 2 8 RST 33333 8808 28 1 38 2539 P 12 REXT 2252 SCAN a a 1 25k Sd ew TESTOUT o S PW e R S04 14 SERADD Istr se eg m TST SELo H BRT ERA e EN LR E up atep Po 32 VBLACK 2 ATEN 9 18 VBH p SL 25 14 SC T 53 VBH mest a U S bad R3 50K n sve LS S dT R5 is a dummy Te RED 27 c9 Gi Y 19 29 RED x 46 TU foopr Neo 2 2nF X7R resistor 20 GREEN S EN EXTFILN 21 48 VCOVDD used for netlist 22 J BLUE 34 coup VO x 23 separation E D Ei a ve veoenn L VCOGND purposes 26 RS 50 HS o aum VCLK zzzz ange 288 th DO NOT USE ANY E Suc 9999 na 229728 88 GND S 3333 22 829672 Ger FOOTPRINT Ho 8888 88 25595 set Connect AGND i cn C12 c13 EMA100009 up uF uF R tracks to GND at CON30 VAN 12 0K 1 pedestal of C7 T 4 4 only AGND COMMO AGND RS 0 S Gun 7 AGND x 3 7 DGND eMagin Corporation 2070 Route 52 Hopewel Junction NY 12533 All grounds connect w emagin com together at J1 only rie SVGA Rev Carrier Board Schematic B EMA 100069 ize Document Number Dae Monday October 15 2001 Est 1 ao 4 Figure 13 1 Microdisplay Carrier Board Electrical Diagram Rev 4 SVGA Rev3 XL Series User s Manual 44 AeMagin 14 APPEN
12. VMODE registers The priority is set by bit 6 VSCANS of the same register When VSCANS 0 the external input has priority When VSCANS 1 VSCAN has priority When U D GND or VSCAN 0 the display is scanned from top to bottom increasing row number sequence When U D VDD or VSCAN 1 the display is scanned from bottom to top decreasing row number sequence The table below summarizes the various vertical modes Interlaced modes are limited to a maximum of 300 and a minimum of 240 active rows per field The table is provided assuming VSCAN 0 The reverse direction start and end rows are symmetric with respect to the center of the array TABLE 9 2 VERTICAL SEQUENCER CONTROLS Pp 0 0 0 SVGA Zoom 600Rows Pp 0 o 1 VGA I169 480Row 0 1 O Ineracd2 6000Rows 0 1 7I Pseudolntelaced2 600 Rows 1 0 O Intraced1 480Rows 1 0 7 Pseudo Interlaced I 480 Rows LL 1 0 SVGA Zoom 600Rows SVGA Rev3 XL Series User s Manual 21 AeMagin The vertical sequencer gets inputs from the Sync Processor block and the serial interface The vertical sync with or without serration pulses non interlaced or interlaced pseudo interlaced mode the field polarity for interlaced pseudo interlaced modes and the horizontal clock come from the Sync Processor block Register VSTART is used to determine the start of the vertical active window In addition counters are used to sample the horizontal c
13. Vcc voltage Figure 9 5 11 25 09 Removed separate electrical levels for Hs Vs Table 5 3 Make reference to the Defect Criteria document and added cleaning handling and storage recommendations in section 8 0 08 18 10 Updated Figure 7 1 Assembly Drawing Ooo T y O Rev 4 SVGA Rev3 XL Series User s Manual 46
14. an even row Thus there is a one row vertical offset between odd and even fields In these modes all active rows are addressed for each field except for the first active row of the even field which is left unselected The table below summarizes the row selection and addressing for progressive interlaced and pseudo interlaced modes TABLE 9 3 MICRODISPLAY ROW SEQUENCE Input Active Display Row Sequence Row Period Number Progressive Interlaced Scan Pseudo Interlaced Pseudo Interlaced Scan Scan Odd Field Scan Odd Field Even Field NE MM The shift register is reset at the end or beginning of each frame For modes other than SVGA and Interlaced 1 all inactive rows are set to the off state black automatically The shift register is clocked at the line rate to minimize power dissipation as opposed to being clocked by the video clocked and gated by an enable signal 9 7 Horizontal amp Burn in Sequencers The horizontal sequencer generates the timing signals needed to control the sample and hold circuit switches The start and end of the sampling sequence depends on the video mode selected COLSEL 1 0 Rev 4 SVGA Rev3 XL Series User s Manual 22 AeMagin 9 8 Rev 4 The start and end of the active video line are centered with respect to the center of the display in order to avoid image miss registration when implementing a bi ocular headset The horizontal sequencer provides for left right support via the L R
15. be powered down if the R G B channels are selected via VSEL 1 0 Default after reset is PWRDNI 1 2 PWRDN2 Active only when ATB7 1 When active high disables and powers down the internal PLL circuit No clock will be recovered from Hsync while PWRDN2 1 When ATB7 0 PWRDN2 has no effect The PLL will be powered down if the VCLK pin is selected as the clock source CLKS 1 Default after reset is PWRDN2 0 3 PWRDN3 Active only when ATB7 1 When active high disables and powers down the Phase Interpolator circuit No fine adjustment of the clock phase can be effected while PWRDNG 1 Only the simple adjustments controlled by PHSEL 1 0 can be used When ATB7 0 PWRDNG has not effect The Phase Interpolator will be powered down if the PIBYP bit is set Default after reset is PWRDNO 0 4 PWRDN4 Active only when ATB7 1 When active high disables and powers down the VBL Output Buffer The VBL pin can then used as an input pin while PWRDN4 1 When ATB7 0 PWRDNA has not effect on the VBL buffer Default after reset is PWRDNA 0 5 PWRDNS Active only when ATB7 1 When active high disables and powers down the VBH Output Buffer The VBH pin can then used as an input pin while PWRDNS 1 When ATB7 0 PWRDNS has not effect on the VBH buffer Default after reset is PWRDN2 0 6 PWRDN6 Active only when ATB7 1 When active high disables and powers down the VBLACK Output Buffer The VBLACK pin can then used as a
16. input pin or an internal bit HSCAN of the HMODE register The reference used L R or HSCAN is determined by the value of bit HSCANS bit 4 of the HMODE register When HSCANS 1 HSCAN determines the horizontal shift direction The power up default is HSCANS 0 Assuming HSCANS 1 when HSCAN 0 the image starts at the left side of the display IC The image is displayed on a line by line basis starting at the leftmost column of the display window When HSCAN the image starts at the right side of the display window The HSTART register is used to set the starting point of the active sampling window HSTART is programmed in units of the pixel clock The power up default is set to 84h 132d which corresponds to the default Zoom Q 60Hz settings Bits HSEL 2 0 of register HMODE are used to configure the display format for the horizontal sequencer TABLE 9 4 MICRODISPLAY HORIZONTAL MODE CONTROLS HSEL2 HSEL1 HSEL 0 Horizontal Mode BENE ree 800 Columns NENNEN IU Lu 640 Columns 0 5 O oma ooo 800 Columns NENNEN ua 800 Columns 852 Columns All starts and ends occur on a color group boundary Burn in compensation Sequencer For all modes except 16 9 and Zoom modes the start and end column positions can be shifted by 5 columns at a programmable rate to minimize visible pattern burn in when use of the display fixed image is anticipated This is done to smooth out sharp edges that may arise in g
17. proper startup and stabilization the following power on sequence should be used 1 Turn on VCC 2 Turn on VAN and wait for it to reach a minimum of 3 3V 3 Turn on VCOMMON A 10 to 50 ms ramp is a good starting point for implementation into a circuit design Also eMagin Corporation recommends that the registers are configured after VCC is up and before VAN and VCOMMON are brought up 9 13 Power Down Modes The circuit provides power down modes to minimize power consumption Two modes of operations are provided to the user Automatic Power Down Mode 9 13 1 Automatic Power Down Mode In the Automatic mode functional blocks are powered down based on the display configuration For example in the power up default mode the sync separator and MONO input buffer blocks are automatically powered down 9 13 2 Manual Power Down Mode In the Manual mode the user can via the POWERDOWN and ATB registers control independently the power down of most functional blocks This mode is the preferred approach to set the microdisplay in its minimum power consumption mode also known as sleep mode To do so the ATB7 bit must be set to VDD and all bits of the POWERDOWN register must also be set to VDD The contents of the registers will be preserved and the serial interface will remain functional Rev 4 SVGA Rev3 XL Series User s Manual 26 AeMagin 9 14 Display Modes Configurations and Characteristics 9 14 1 VESA Modes TABLE 9 5 VESA
18. scan mode 1 40 85 Hr Rate Interlaced sean mode f 30 Ir s m u u Z el s 1 Fill Factor Emissive Area vs total subpixel area Note 1 Specification refers to value producing no visible image flicker Rev 4 SVGA Rev3 XL Series User s Manual AeMagin TABLE 6 3 EMA 100311 01 MONOCHROME GREEN MICRODISPLAY OPTICAL CHARACTERISTICS OR Wie to Black Contrast Ratio 101 f I U Area Uniformity JL 80 90 100 mp et cu EE Dm EE NENNEN NN OS Gray Levels Levels Refresh Progressivescan mode 40 85 E Rate Interlaced scan mode 30 8 Hz Pixel Sub Pixel With Pith 5 Le Cell SubPixc High Pic 3 pom Fill Factor Emissive Area vs total subpixel area Note 1 Specification refers to value producing no visible image flicker Optical characteristics are measured in accordance with the VESA Flat Panel Display Measurement Standard Rev 1 0 A copy of the standard is available at the VESA website www vesa org 6 1 Measurement Conditions Luminance contrast and chromaticity measurements are performed in a dark ambient environment at room temperature on a dedicated automated test bench The reference used for the luminance measurement is the OLED current density set to 20 mA cm2 This reference is purely for reference purposes and corresponds approximately to the typical luminance value In order to account for possible leakage effects
19. 4 5 and 6 Set to I for power down and register 18h ATB bit 7 Set to 1 to allow use of register 17h The output impedance of the internal Vblack reference generator is high enough that an override is possible even without powering it down Care must be taken when designing an external voltage reference circuit for Vbl and Vbh An application schematic is provided below that can serve as a basis for a production design A different approach relying on operational amplifiers in lieu of shunt regulators is possible A4 7 K Ohm pull down resistor is then recommended at both Vbl and Vbh inputs to maximize stability vcc ur vcc VDC C vBLACK R14 OPEN C15 15uF R18 T 24K as R11 510 D3 TLV431 D2 ei TLV431 m c17 R21 10uF TuF R22 510 7418TO 2 43V ADJUSTABLE C v8H 7 15K C18 15uF t 1 51 wi n A1 B2 Stw2 a T Ee 4 end sva K SJ VDD SCL e u5 AD5243 10 D4 scl Del TLV431 I2C Address SEh SDA gt gt R23 R24 ka 36 5K 36 5K Figure 9 5 Sample Circuit Designs Using External References Vbl is the reference level used during the programming phase of the pixel driver operation During this phase the pixel driver is programmed at a higher current value than needed for image restitution This is done for settling time reasons This level is active one row per frame for each pixel driver
20. 5 Volts 0 07 Volts 0 000 Volts Max period period TT EE period 1 LSB Integral Linearity Error 1 LSB Po Differential Linearity Error I LSB Po Video Channel to Video 6 of any output voltage over the full Noise injection ratio 0 5 of Max Luminance Voltage All Sources Frequency Channel Output Skew period Overshoot Undershoot 12 of step function voltage level over the full voltage range Note 1 With respect to GND Rev 4 SVGA Rev3 XL Series User s Manual 8 AeMagin 6 OPTICAL CHARACTERISTICS TABLE 6 1 EMA 100310 01 COLOR MICRODISPLAY OPTICAL CHARACTERISTICS Conditions Ta 20 C GND 0 V VDD 3 3V Van 4 0V Vcommon 3 0 L FrontLuminance 05 14 400 Cdm CR White to Black Contrast Ratio 3001 LU Vu Area Uniformity 1 80 90 10 I Gray Ng 64 256 Levels Levels Refresh Progressive scan mode JL 4 8 E Rate Interlaced scan mode 30 85 Ez Pre Sub Pier wian Pen 5 am E um Emissive Area vs total subpixel area 50 Ia 65 Note 1 Specification refers to value producing no visible image flicker TABLE 6 2 EMA 100309 01 MONOCHROME WHITE MICRODISPLAY OPTICAL CHARACTERISTICS Ld FrontLuminance 05 f 900 1800 Cd m CR White to Black Contrast Ratio 3004 Ul Area Uniformity 1 80 90 100 I E Gray Levels Levels Refresh Progressive
21. 72 809Hz 520 lines 480 lines 40 lines 9 lines 3 lines 28 lines P 31 500MHz VGA 640x480 H 31 469KHz 800 pixels 640 pixels 160 pixels 16 pixels 96 pixels 48 pixels 60Hz non interlaced V 59 940Hz 525 lines 480 lines 45 lines 10 lines 2 lines 33 lines P 25 175MHz Synchronization pulses Hsync and Vsync polarities must follow the VESA DMT standard TABLE 9 6 SYNCHRONIZATION PULSES POLARITY Mode VGA 60Hz VGA VGA VGA SVGA SVGA SVGA SVGA Rev 4 SVGA Rev3 XL Series User s Manual 27 AeMagin 9 14 2 Interlaced Video Modes TABLE 9 7 INTERLACED VIDEO MODES Mode Frequency Total Active 170M 640 x480 H 15 734 KHz 780 pixels 640 pixels 30Hz interlaced V 30 Hz Frame 60Hz Field 262 5 lines 240 lines P 12 27 MHz PAL 800x600 H 19 8KHz 944 pixels 768 pixels 25 Hz interlaced V 25 Hz Frame 50Hz field 312 5 lines 288 lines P 1475MHz 9 14 3 Zoom amp 16 9 Modes TABLE 9 8 ZOOM AND 16 9 VIDEO MODES Mode Frequency Total Active Blanking Front Porch Sync Back Pulse Porch 16 9 852x480 H 43 265 KHz 852 192 56 pixels 56 80 pixels 85Hz non interlaced pixels pixels pixels V 85 000Hz 509 lines 480 lines 29 lines I line 3 lines 25 lines P 45 168MHz 16 9 852x480 H 37 5 KHz 1052 852 200 16 pixels 64 120 pixels 75Hz non interlaced pixels pixels pixels pixels V 75 000Hz 500 lines 480 lines 20 lines
22. Address is 64 or 66 if SERADD 1 Read Mode Address is 65 or 67 is SERADD 1 9 11 1 Sequential Read Write Operation The serial controller allows for both sequential and read operational modes For either mode the host needs only set the initial register address followed by as many data bytes as needed taking care not to issue a STOP condition until all desired data bytes have been transmitted or received Interface maximum frequency 400 KHz Rev 4 SVGA Rev3 XL Series User s Manual 25 AeMagin Details of the timing of the SDA and SCL signals can be found in the I2C Standard available on the Philips website The SDA pin is pulled up via a 2 2 Kilo Ohm resistor that is mounted on the microdisplay carrier peb 9 12 Power On sequence When VAN is applied without ramping to the OLED Microdisplay chip the voltage at the gate of the current source is close to ground As the storage capacitor is discharged to the reference level the current increases Since the current source is on current flows through the OLED and causes the flash seen when the display is initially turned on Ramping VAN to 3 3 volts before turning on VCOMMON allows the storage capacitor discharge to track the supply and keep the current source at or close to turn off In addition having VCOMMON at GND reduces the voltage that can be applied to the OLED to a maximum of VAN and so this reduces the amount of current that can flow through the OLED To ensure
23. AeMagin SVGA Rev3 XL SERI ES 852 X 600 ACTIVE MATRIX OLED MICRODISPLAY USER S SPECI FI CATI ON Revision 4 For Part Numbers EMA 100309 01 EMA 100310 01 EMA 100311 01 AeMagin TABLE OF CONTENTS 1 INTRODUCTION ee 1 2 GENERAL CHARACTERISTICS 1 esu ren cr tarte n docu a aer esa reenn enrere ennenen enre 2 3 FUNCTIONAL OVER VIEW tnr Eon Exe hun dE EES 3 4 INPUT OUTPUT DESCRIPTION 2c citeriore educi aano nic kane inne ce nor nre 5 5 ELECTRICAL CHARACTERISTICS 5 4 eege eege eege 6 5 1 Analog R G B Input Characteristics eee eee eee eee 8 6 OPTICAL CHARACTERISTICS Lunestad 9 6 1 Measurement Conditions 3 ipeo ent ie ei eee ti Bea rr a tire Eden 10 MECHANICAL CHARACTERISTICS nnnnnvennnnvnnnnnvnnnvnennnnvnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennr 11 CLEANING HANDLING AND STORAGE RECOMMENDATIONS eren 13 8 3 Static Charge Prevention esssssssissssseseeeeseee innen nnne entr st aaaeei aiia niaaa 13 8 4 Protection from Dust and Dirt 14 8 5 Short Term SIorage um aa a aa e SER svete RN avus atas RE Ree ERAN 14 8 6 Long Term Storage EE 14 9 DETAILED FUNCTIONAL DESCRIPTION esse sees vese sese ereer ereer ereenn ereenn eee 15 9 T Input BE NE 15 9 2 Data Sampling ci eoe eee Ge 17 93 Pixel ell iio tee T MT rere 17 9 4 Pixel Be VE 18 9 5 Voltage References IDEE IL SES EeE 18 9 6 Vertical
24. DEL Index 16h Mode Read Write Bit Name Bit Reset Value Description HDEL 7 0 0 7 OCh Break before make switch delay The value that is programmed into HDEL sets the gap between the closure of two of the analog switches used in the pixel driver The default value should not be changed for normal operation Name POWERDOWN Index 17h Mode Read Write Bit Name Bit Reset Value Description PWRDNO 0 0 RGB Channels power down enable PWRDNI 1 1 MONO Channel power down enable PWRDN2 2 0 PLL power down enable PWRDN3 3 0 Phase Interpolator power down enable PWRDN4 4 0 VBL Buffer power down enable PWRDNS 5 0 VBH Buffer power down enable PWRDN6 6 0 VBLACK Buffer power down enable PWRDN7 7 0 Bias block power down enable Bit Name Description Rev 4 SVGA Rev3 XL Series User s Manual 39 e AeMagin 0 PWRDNO Active only when ATB7 1 When active high disables and powers down the R G and B analog input channels No input at the RED GREEN and BLUE pins will be processed while PWRDNO 1 When ATB7 0 PWRDNO has not effect The R G B channels will be powered down if the MONO channel is selected via VSEL 1 0 Default after reset is PWRDNO 0 1 PWRDNI Active only when ATB7 1 When active high disables and powers down the MONO analog input channel No input at the MONO input pin will be processed while PWRDNI 1 The sync separator circuit will also be disabled When ATB7 0 PWRDNI has not effect The MONO channel will
25. DIX B COMPOSITE SIGNAL INPUT CONNECTIONS TABLE 14 1 MINIMUM CONNECTIONS REQUIRED FOR COMPOSITE INPUT Pin Notes Pin 1 Power Pin 2 Reset should be pulled high through an RC network to VDD to ensure that reset stays on low for 100 usecs after all other lines have stabilized Pin 3 2 2kQ pull up to VDD Pin 4 Note there is a 2 2kQ pull up resistor on the display board Pin 6 Should be grounded for normal operation Pin 7 Should be grounded for normal operation Pin 8 Should be grounded for normal operation Pin 9 Power Pin 10 Power Pin 11 Ground Pin 13 Vbh Pin 14 Vbl Pin 17 Ground Pin 19 Ground Pin 21 Ground Pin 23 Ground Pin 24 For mono NTSC input attach a 01uF ceramic coupling capacitor A 75 termination resistor to ground on the signal side of the capacitor is recommended to prevent reflection and noise in the transmission line After the chip has reset enters the high state load the NTSC settings into the registers through the IC serial bus Anytime the chip is reset the register values must be reloaded Rev 4 SVGA Rev3 XL Series User s Manual 45 AeMagin 15 APPENDIX C REVISION HISTORY Revision Level Date Scope 09 18 07 Initial Release 2 02 06 06 Removed CIE sprecifications from Table 2 1 Values are in Tables 6 1 through 6 4 Replaced External Reference Circuit Diagram with version showing
26. ECOMMENDED OPERATING CONDITIONS Parameter 1 Min Typ Max VDD VAN Vcommon Common electrode bias z 30 0 VDC Vbh Tst 55 J 90 Ta 20 25 PD Power Dissipation J Note The above data represents commercial performance specifications measured at 20 C Performance will vary at temperatures above or below 20 C Operation at higher or lower temperatures is possible but may require compensation via biasing to maintain the 20 C optimum performance Half life is reduced at high temperatures Operation may be possible outside the temperature ranges specified in Table 5 2 especially for short term use but such use is considered outside the basic specification range Operation outside the recommended operating conditions will void any warranty The consumer OEM specification for acceptable operating and storage temperature range is different from the above chart refer to the SVGA 3D specifications for this parameter Rev 4 SVGA Rev3 XL Series User s Manual 6 A4 eMagi aemagin Contact eMagin customer service regarding potential use of the display under other conditions Warranties for use under other operating conditions require formal written documentation specifically extending the warranty to these conditions Statement of potential acceptable use under alternate conditions by company personnel does not constitute a warranty extension TABLE 5 3 DC CHARACTERISTICS DC CHARACTERISTICS
27. I line 3 lines 16 lines P 39 45MHz 16 9 852x480 H 31 468KHz 1012 852 144 24 pixels 96 40 pixels 60Hz non interlaced pixels pixels pixels pixels V 59 94Hz 525 lines 480 lines 66 lines 16 lines 6 lines 23 lines P 31 84MHz Zoom 852x600 H 46 875KHz 1108 852 256 16 pixels 80 160 pixels 75Hz non interlaced pixels pixels pixels pixels V 75 0Hz 625 lines 600 lines 25 lines I line 3 lines 21 lines P 51 937MHz Zoom 852x600 H 37 642KHz 1108 852 256 40 pixels 128 88 pixels 60Hz non interlaced pixels pixels pixels pixels V 59 94Hz 628 lines 600 lines 28 lines I line 4 lines 23 lines P 41 707MHz Synchronization pulses polarities for Zoom and 16 9 modes TABLE 9 9 ZOOM AND 16 9 MODES SYNCHRONIZATION PULSES POLARITY Zoom 60Hz Zoom 75Hz 16 9 60Hz 16 9 75Hz 16 9 85Hz Hsync Polarity Vsync Polarity Rev 4 SVGA Rev3 XL Series User s Manual 28 AeMagin 10 REGISTER MAP SUMMARY Register Name Access Bit Name Bit Reset Description Index Value Hex Hex o sm a ox 7 PULockFlag toLocked O NotLoed sma 63 beet REV 1 Silicon Revision Number RGAIN RGAIN 7 0 80 50 Red channel gain control 2 nom WW mor 17 Reeve ROFF 60 40 50 Red channel offset control GGAIN GGAIN 7 0 80 50 Green channel gain control Co som WW sor 7 9 eee GOFF 60 40 50 Green channel offset con
28. MODES Mode Frequency Total Active Blanking Front Porch Sync Back Proch Border Pulse Border SVGA 800x600 H 53 674KHz 1048 pixels 800 pixels 248 pixels 32 pixels 64 pixels 152 pixels 85Hz non interlaced V 85 061Hz 631 lines 600 lines 31 lines I line 3 lines 27 lines P 56 250MHz SVGA 800x600 H 46 875KHz 1056 pixels 800 pixels 256 pixels 16 pixels 80 pixels 160 pixels 75Hz non interlaced Y 75 000Hz 625 lines 600 lines 25 lines 1 line 3 lines 21 lines P 49 500MHz SVGA 800x600 H 48 077KHz 1040 pixels 800 pixels 240 pixels 56 pixels 120 pixels 64 pixels 72Hz non interlaced V 72 188Hz 666 lines 600 lines 66 lines 37 lines 6 lines 23 lines P 50 000MHz SVGA 800x600 H 37 879KHz 1056 pixels 800 pixels 256 pixels 40 pixels 128 pixels 88 pixels 60Hz non interlaced v 60 317Hz 628 lines 600lines 28 lines I line 4 lines 23 lines P 40 000MHz VGA 640x480 H 43 269K Hz 832 pixels 640 pixels 192 pixels 56 pixels 56 pixels 80 pixels 85Hz non interlaced Y 85 008Hz 509 lines 480lines 29 lines 1 line 3 lines 25 lines P 36 000MHz VGA 640x480 H 37 500KHz 840 pixels 640 pixels 200 pixels 16 pixels 64 pixels 120 pixels 75Hz non interlaced v 75 000Hz 500 lines 480lines 20 lines 1 line 3 lines 16 lines P 31 500MHz VGA 640x480 H 37 861KHz 832 pixels 640 pixels 192 pixels 24 pixels 40 pixels 128 pixels 72Hz non interlaced V
29. Magin 11 DETAILED REGISTER DESCRIPTION Name STATUS Index Oh Mode Read Only Bit Name Bit Reset Value Description REV 0 2 00h Circuit Revision Initial Value is 000 Will increase by 1 for each all layer change STAT 6 3 3 6 00h Reserved LOCK 7 N A PLL lock status Bit Name Description 7 LOCK PLL Lock Status 0 Unlocked I Locked Name RGAIN Index 01h Mode Read Write Bit Name Bit Reset Value Description RGAIN 0 7 80h Red Data Channel gain control Bit Name Description 0 7 RGAIN Controls the gain of the Red Analog Input The 8 bit value spans a range of one half to one and a half the signal s full scale value The default reset value is a gain of 1 80h value Name ROFF Index 02h Mode Read Write Bit Name Bit Reset Value Description ROFF 0 6 40h Red Data Channel offset control Bit Name Description 0 6 ROFF Controls the dc offset of the Red Analog Input The 6 bit value spans a range of one half to one and a half the signal s full scale value The default reset value is zero offset 40h value 7 ROFF7 Reserved Rev 4 SVGA Rev3 XL Series User s Manual 31 AeMagin Name GGAIN Index 03h Mode Read Write Bit Name Bit Reset Value Description GGAIN 0 7 80h Green Data Channel gain control Bit Name Description 0 7 GGAIN Controls the gain of the Green Analog Input The 8 bit value spans a range of one half to one and a half the signal s full scale value The default reset value is a
30. SOMHz VGA 640x480 75Hz 0 0 42400MHz SVGA 800x600 60Hz 0 1 50 0 MHz SVGA 800x600 72Hz 1 0 49 5 MHz SVGA 800x600 75Hz 56 25 MHz SVGA 800x600 85Hz 0 0 0 e Note When setting the FBD and PSD values the user must select the matching PIF setting For modes other than those directly supported by the SVGA Microdisplay and mentioned above there is no guarantee of performance even if the PIF setting is set to the closest value of the programmed frequency output 4 7 PIF 7 4 Reserved Name PD Rev 4 SVGA Rev3 XL Series User s Manual 37 AeMagin Index 12h Mode Read Write Bit Name Bit Reset Value Description PHASE 0 4 00h PLL Clock Phase Adjustment when PIBYP 0 PHSEL 5 6 00h PLL Clock Phase Adjustment when PIBYP I PIBYP 7 0 Phase Interpolator bypass selection Bit Name Description 0 4 PHASE Selects the clock edge offset in 32 discrete steps from zero to one clock period This selection is active only when PIBYP 0 5 6 PHSEL Selects one of 4 clock edge offsets when PIBYP 1 PHSEL1 PHSEL 0 Clock Edge Offset L0 None EN DE ENDE NEM EE L1 k 0 H18 amp 6 7 PIBYP Phase Interpolator Bypass Enable When active High the Phase interpolator circuit is bypassed and only 4 phase shifts are available The PIBYP mode can be used when a simple adjustment is sufficient allowing the PI circuit to be powered down Name HSTART Index 13h Mode Rea
31. ame AMTEST Index 19h Mode Read Write Bit Name Bit Reset Value Description AMTEST 7 0 0 7 00h Reserved for testing This register is reserved for wafer level testing and is of no use for normal operation Bit Name Description 7 AMTEST 7 0 Reserved Name TRIM Index 1Ah Mode Read Write Bit Name Bit Reset Value Description TRIM 7 5 5 7 00h Trim value read back read only TRIM 4 4 0 Trim mode continuous startup TRIM 3 3 0 Trim override enable active high TRIM 2 0 0 2 00h Trim override input The TRIM register controls an internal calibration resistor used by the Input Buffer circuit and aimed at compensating non linearities in the silicon The default configuration is for an automatic and periodic calibration every Vsync An override bit allows the user to modify the trim resistor setting with the 3 least significant bits Rev 4 SVGA Rev3 XL Series User s Manual 41 AeMagin 12 REGISTER TABLE CONFIGURATION Recommended values for use with on chip PLL selected For use with external clock change bit 5 of HMODE from 0 to 1 12 1 VESA Modes Rev 4 TABLE 12 1 VESA MODES REGISTER SETTINGS SVGA 60 00 78 30 78 30 78 30 80 38 00 02 00 02 00 80 1E 0C 0C 00 D4 19 D8 0C 32 80 00 08 SVGA 72 00 78 30 78 30 78 30 80 38 00 02 00 02 00 80 0E 04 oD 00 B4 DB D8 OG 32 80 00 08 SVGA 75 00 78 30 78 30 78 30 80 38 00 02 00 02 00 80 1E
32. andard gt 150 cd m front luminance SVGA 60Hz VESA mode 0 to 0 7 V compatible with VESA VSIS standard 0 to 1 0 V compatible with SMTPE 170M amp PAL 56 MHz maximum VESA mode up to 85Hz frame rate 13 MHz minimum SMPTE 170 mode 30 Hz frame rate Digital 3 3 V CMOS 3 3 Volts DC 50 mA maximum 4 0 Volts DC 50 mA maximum 3 0 Volts DC 50 mA maximum 40 C to 65 C 55 C to 90 85 RH non condensing nominal values of five 1000 pixel zones located in the four extreme corners and the center zone of display Rev 4 SVGA Rev3 XL Series User s Manual AeMagin 3 FUNCTIONAL OVERVIEW Boye Input buff Tast put buffer puts Gain Offset Column Driver MONO control Composite Serial Bus Host Slee gt Interface Recovery E 852x600 amp amp RGB Registers Phase 2 Pixel Array Power Interpolator T ge Vsync XE Voltage Power Vbl Vbh References Control Down Logic Control COMMON Figure 3 1 Microdisplay functional block diagram Four 4 analog video inputs are provided Red Green Blue and Composite Monochrome The R G B input signals are dc coupled analog signals with external vertical and horizontal synchronization signals compatible with the VESA VSIS standard The integrated circuit provides for progressive scan color and monochrome modes using the three primary color inputs R G and B A dedicated monochrome composite video input MONO compatible with the SMPTE 170M a
33. ck This includes start and end of active video sampling 9 3 Pixel Cell There are 2 556 pixel cells 852 x 3 per active row 600active rows Each cell is a 5 x 15 micron rectangle yielding a 15 x 15 micron square color group RGB The pixel cell output stage is a current source configured around a PMOS transistor The current flows from the VAN power input to the OLED s anode terminal The OLED is typically represented as a diode OLEDs generate an amount of light that is proportional to the current density flowing through the device Rev 4 SVGA Rev3 XL Series User s Manual 17 AeMagin Current mA OLED LV Curve OLED I V Curve 100 80 70 10 60 50 1 E g 40 2 0 1 30 S 0 01 10 0 001 Je 0 P Voltage V Voltage V Figure 9 4 OLED I V Characteristic Log and Linear scale The pixel cell operates at VAN power to maximize the dynamic range of the display technology as well as accommodate its life dependent voltage characteristic The cathodes of all OLED pixels are electrically connected to the COMMON pin via an internal electrode that surrounds the array 9 4 Pixel Driver The pixel driver block buffers the sampled signal to an output tuned to the array characteristics There are as many pixel drivers as there are dual SAH stages At the beginning of each video line the pixel driver output is reset to the black level This will ensu
34. d Write Bit Name Bit Reset Value Description HSTART 0 7 D8h Horizontal Active Start Count The value that is programmed into HSTART sets the number of clock cycles after the leading edge of Hsync at which the analog input signal will be sampled into the Microdisplay minus 5 This gap is equivalent to the sum of the Sync pulse width plus the Back Porch as defined in the VESA Display Monitor Timing Specification Name VSTART Index 14h Mode Read Write Bit Name Bit Reset Value Description VSTART 0 5 1Bh Vertical Active Start Count VSTRT 7 6 6 7 00h Reserved The value that is programmed into VSTART sets the number Hsync after the leading edge of Vsync at which the first analog input signal line will be sampled into the Microdisplay minus 3 This gap is equivalent to the sum of the Sync pulse width plus the Back Porch as defined in the VESA Display Monitor Timing Specification Rev 4 SVGA Rev3 XL Series User s Manual 38 AeMagin Name HBLK Index 15h Mode Read Write Bit Name Bit Reset Value Description HBLK 7 0 0 7 D8h Reset to black pulse width The value that is programmed into HBLK sets the width in Tclk increments of a reset to black duration at the beginning of each display row The higher the value the longer the reset duration This setting minimizes residual charge in the array matrix that could contribute to ghost images or crosstalk The default value has been calculated for the SVGA 60Hz format Name H
35. do not require any special termination The MONOCHROME analog input is the output of the Video Sync Processor and consists of a video signal that has been stripped of the synchronization pulses and de restored to ground The first stage of the buffer circuit provides for removal of the CRT gamma provided by the host for use with the MONO input only as well as a correction to accommodate the internal non linearities of the data path In the primary monochrome mode the Red Green and Blue inputs are summed weighted sum with equal weights to yield a monochrome white video signal prior to entering the second stage The buffer circuit includes gain and offset adjustments controlled via the serial interface Digital potentiometers are used to adjust the signal characteristics Each channel includes two registers one for amplitude contrast and one for offset brightness Each control has a 50 range and defaults to I Gain and 0 Offset at power up RGAIN 7 0 ROFF 6 0 GGAIN 7 0 GOFF 6 0 Gain amp Offset BGAIN 7 0 BOFF 6 0 MGAIN 7 0 MOFF 6 0 CRT Gamma Removal Figure 9 1 Analog Inputs Block Diagram Following the gain and offset stage three 3 1 multiplexers channel the selected input Color White or Mono to one of three data channels that are fed to the Data Sampling functional block Each channel maps into 852 cells per row SVGA Rev3 XL Series User s Manual 15 AeMagin The input selection is controlled by t
36. ed voltage level can improve the display contrast ratio significantly albeit with a higher variability from display to display Adjusting Vblack only affects the black level 0V video input and has no impact on the maximum luminance The internal Vblack reference circuit output is nominally 3 45V An optimum value for an externally generated Vblack 1s 3 60 V The reference is a dc level reference that requires very little current less than 50 micro Amperes The graph below shows the typical contrast ratio dark ambient measurement as a function of Vblack for the SVGA Rev3 Color microdisplay Two curves were taken for two different values of Vbl for information purposes For reference when Vbl 1 6V Vbh 1 805V When Vbl 2 0V Vbh 2 218V Rev 4 SVGA Rev3 XL Series User s Manual 20 SVGA Color Contrast vs Vblack 600 m c 500 400 z Part 1 Vbl 1 6V 5 300 g s Part 1 Vbl 2 0V 200 100 0 T T T T T T T T 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 Vblack Volts Figure 9 7 Typical Contrast Ratio as a Function of Vblack 9 6 Vertical Sequencer and Row Driver Rev 4 The row driver is designed around a 600 stage shift register For nomenclature and reference purposes Row I is set arbitrarily to be the top row when viewing the display with the I O pads on the left The shift register is bi directional The direction is set by the U D external input or by bit 5 VSCAN in the
37. eene nene 7 TABLE 5 4 AC CHARACTERISTICS sse enne nee nne nr innere teen tne tnnt enee teens nenne nne trennen EEEE EEEE nee TABLE 5 5 INPUT CHARACTERISTICS TABLE 6 1 EMA 100310 01 COLOR MICRODISPLAY OPTICAL CHARACTERISTICR eee 9 TABLE 6 2 EMA 100309 01 MONOCHROME WHITE MICRODISPLAY OPTICAL CHARACTERISTICS 9 TABLE 9 1 INPUT MULTIPLEXER SELECTION CONTROLS TABLE 9 2 VERTICAL SEQUENCER CONTROLS TABLE 9 3 MICRODISPLAY ROW SEQUENCE TABLE 9 4 MICRODISPLAY HORIZONTAL MODE CONTROLS TABLE 9 5 VESA MODES teeen terere etn tnit tb eth NEE TABLE 9 6 SYNCHRONIZATION PULSES POLARITY esee emen rennen nete ennt TABLE 9 7 INTERLACED VIDEO MODBES sss eee ener nennen tenere tentent teen enne TABLE 9 8 ZOOM AND 16 9 VIDEO MODES TABLE 9 9 ZOOM AND 16 9 MODES SYNCHRONIZATION PULSES POLARITY cmm 28 TABLE 12 1 VESA MODES REGISTER SETTINGS essere eene etre ne tenen TABLE 12 2 NON VESA MODES REGISTER SETTINGS TABLE 15 1 MINIMUM CONNECTIONS REQUIRED FOR COMPOSITE INPUT cm 45 Rev 4 SVGA Rev3 XL Series User s Manual il AeMagin 1 INTRODUCTION eMagin s SVGA Rev3 OLED Microdisplay continues the SVGA series of microdisplays with a resolution of 852x3x600 pixels and compatibility with multiple video sources The SVGA Rev3 XL OLED Microdisplay is nearly identical to the
38. efect Criteria Document C15 100000 xx for specifics on Defect types Rev 4 SVGA Rev3 XL Series User s Manual 1 AeMagin 2 GENERAL CHARACTERISTICS TABLE 2 1 GENERAL CHARACTERISTICS Parameter Format Color Pixel Aspect Ratio Color Pixel Pitch Color Pixel Arrangement Viewing Area Mechanical Envelope Weight White Chromaticity Gray Levels Uniformity Contrast Ratio White Luminance Maximum Video Inputs R G B Inputs Monochrome Input Video Signal Bandwidth Control amp Serial Interface Power Interface Logic Analog Supply Vdd Van Vcommon Operating Ambient Temperature Storage Temperature Humidity Note 1 The above data represents consumer and commercial performance specifications measured at 20 C Performance will vary at temperatures above or below 20 C Operation may be possible outside this temperature ranges especially for short term use but such use is considered outside of the basic commercial specification range For additional information about special operating conditions and methods of test contact eMagin Technical Support Note 2 At 100 of gray level brightness and 60 Cd m luminance Luminance uniformity measured between the Specification 852 x3 x 600 pixels Square 15 um R G B Vertical Stripe 12 78 x 9 mm 19 78x 15 2x 5 mm 1 8 grams X 0 30 0 03 y 0 35 0 03 Up to 256 per primary color gt 85 gt 100 1 Intrinsic Measured per VESA FPDM St
39. gain of 1 80h value Name GOFF Index 04h Mode Read Write Bit Name Bit Reset Value Description GOFF 0 6 40h Green Data Channel offset control Bit Name Description 0 6 GOFF Controls the dc offset of the Green Analog Input The 6 bit value spans a range of one half to one and a half the signals full scale value The default reset value is zero offset 40h value 7 GOFF7 Reserved Name BGAIN Index 05h Mode Read Write Bit Name Bit Reset Value Description BGAIN 0 7 80h Blue Data Channel gain control Bit Name Description 0 7 BGAIN Controls the gain of the Blue Analog Input The 8 bit value spans a range of one half to one and a half the signal s full scale value The default reset value is a gain of I 80h value Rev 4 SVGA Rev3 XL Series User s Manual 32 AeMagin Name Index Mode Bit Name BOFF Bit Name 0 6 BOFF 7 BOFF7 Name Index Mode Bit Name MGAIN 0 7 Bit Name 0 7 MGAIN Name Index Mode Bit Name MOFF Bit Name 0 6 MOFF 7 MOFF7 Rev 4 BOFF 06h Read Write Bit Reset Value Description 0 6 40h Blue Data Channel offset control Description Controls the dc offset of the Blue Analog Input The 6 bit value spans a range of one half to one and a half the signal s full scale value The default reset value is zero offset 40h value Reserved MGAIN 07h Read Write Bit Reset Value Description 80h Mono Data Channel gain control Description Cont
40. he VMODE register accessible via the serial interface The lower two bits COLSEL1 and COLSELO are used TABLE 9 1 INPUT MULTIPLEXER SELECTION CONTROLS 0 0 J Codr R G B HL 1 wie w w w 1 0 Composite M M M L X le Rm GG Jj M O 3 1 Analog Muxl jor 3 1 Analog Mux2 To Data Sampling pam 3 1 Analog Mux3 COLSEL 1 0 Figure 9 2 Input Multiplexer Block Diagram Rev 4 SVGA Rev3 XL Series User s Manual 16 AeMagin 9 2 Data Sampling The output of the multiplexers is fed to multiple dual sample and hold stages The design approach is a pipeline mode where the raster line input data is sampled then held to allow for propagation to the relevant pixel cell while allowing for the sampling to continue uninterrupted using the second sampling capacitor The stages are optimized to achieve the best balance between low power via bandwidth reduction and minimum loading of the buffer and performance uniformity noise and internal propagation delays FROMBUFFER E TO PIXEL DRIVER gt Figure 9 3 Dual Sample amp Hold Block Diagram S1 The analog switches are designed to minimize charge injection and dynamic power dissipation The sample and hold amplifier is a unity gain element with low fan out requirements Its output is fed directly to the pixel driver circuit The sequence controlling which SAH is being selected is generated by the column sequencer blo
41. he following measures are recommended to minimize ESD occurrences When handling the microdisplay operated under a flow of ionized air to discharge the panel Use a conductive wrist strap connected to earth ground via a 10 M Ohm resistor Wear non chargeable clothes Keep stored displays away from charged materials SVGA Rev3 XL Series User s Manual 13 e AeMagin 8 4 Protection from Dust and Dirt It is also recommended that all display handling operations take place in a clean environment The use of ionized nitrogen gas is the preferred method of removing particles from the surface 8 5 Short Term Storage For short term storage one to two weeks or less the displays should be kept in their original container at room ambient and the typical controlled office environment 8 6 Long Term Storage For displays that will be stored for a longer period a few weeks and up it is recommended to keep displays stored in a dry environment near or at room ambient 20 C typically whenever possible prior to installation into an optical subsystem There are several ways to achieve this Dry storage cabinet Dry Nitrogen cabinet Nitrogen sealed bag Vacuum sealed bag with desiccant Rev 4 SVGA Rev3 XL Series User s Manual 14 AeMagin 9 DETAILED FUNCTIONAL DESCRIPTION 9 1 Input Buffer Rev 4 The Input Buffer assumes DC coupled RED GREEN and BLUE analog inputs The inputs are high impedance CMOS inputs and
42. ine is desired this number is the default SVGA 60Hz mode then the value programmed into FBD 10 0 is 1054 or 41Eh Small adjustments with count may be necessary to compensate for variations between different implementations of the standards The value that is programmed into PSD 1 0 is the divider factor for the VCO clock output before it is routed to the Phase Interpolator module Rev 4 SVGA Rev3 XL Series User s Manual 36 H j 0 2 25 t dp I The default value after reset is PSD 1 0 01 divide by 4 Note The internal oscillator has a maximum internal frequency of 200 MHz Any combination of FBD 10 0 and PSD 1 0 that would result in the oscillator exceeding that frequency should be avoided to prevent permanent damage to the circuit Name PIF Index 11h Mode Read Write Bit Name Bit Reset Value Description PIF 3 0 0 3 OCh Phase Interpolator Reference Frequency Selection PIF 7 4 4 7 00h Reserved Bit Name Description 0 3 PIF 3 0 Determines the reference pixel clock frequency for the phase interpolator Default value is SVGA 60Hz 40 MHz o 0 o J 0 J Reserved L0 o o 1 AUT MHz Zoom 852x600 60Hz Pp oo 0 1 o 5L037MHz Zoom852x600 975Hz LJ o 23945MHz 852x480 75Hz A 1 45168MHz 852x480 85Hz LL 0 1475MHz PAL Q25Hz 0 0 25175MHz VGA 640x480 60Hz H 1 23L50MHz VGA 640x480 72Hz 1 0 23L
43. ivated 0 Screen saver mode deactivated 1 Screen saver mode activated Name BR_L BR_U Index OBh 0Ch Mode Read Write Bit Name Index Bit Reset Value Description BR_L 7 0 OBh 0 7 00h Reserved BR_U 7 0 OCh 0 7 02h Reserved These registers are reserved for wafer level testing and are of no use for normal operation Name HRATE L HRATE U Index ODh OEh Mode Read Write Bit Name Index Bit Reset Value Description HRATE 7 0 ODh 0 7 00h Horizontal Frame Shift Rate LSBs HRATE 15 8 OEh 0 7 80h Horizontal Frame Shift Rate MSBs The value that is programmed into HRATE 15 0 determines in units of vertical periods the rate of single column shift left or right for the display frame An internal 16 bit counter advances at every Vsync until its output equals the value programmed into HRATE 15 0 At that time the display frame is shifted by one column The Default value is 8000h which for a 60Hz refresh rate corresponds to one shift every 546 seconds or approximately 9 minutes Name PLL L PLL U Index OFh 10h Mode Read Write Bit Name Index Bit Reset Value Description FBD 7 0 OFh 0 7 1Eh PLL Feedback Divider LSBs FBD 10 8 10h 0 2 04h PLL Feedback Divider MSBs PSD 1 0 10h 3 4 Olh PLL Post Scaler Divider PLL U 7 5 10h 5 7 00h Reserved The value that is programmed into FBD 10 0 is equal to the number of pixel clock period per horizontal period minus 2 For instance 1f a total of 1056 clock periods per l
44. lock and or the serration pulses The start of the active vertical window is determined by a match between the output of the counters and the value in the register VSTART The end of active scan occurs when the shift register runs out A new vertical start strobe is required to start the shift register again For interlaced modes the odd field maps to the odd rows and the even field maps to the even rows The field polarity output from the Sync Processor is used in conjunction with the vertical sync signal to control the odd even rows selection The row shift register can be started at various stages depending on the video mode selected by the user Selected cells of the shift register have input multiplexers to allow for alternate start end points The shift register can also be configured for interlaced and pseudo interlaced scan operations These settings are determined by the VSEL 2 0 bits in the VMODE register In a progressive scan mode rows are addressed in a sequential manner In an interlaced scan mode every other row is addressed in a sequential manner The polarity of the addressed rows depends on the value of the FIELD bit internal output of the Sync Processor function Thus the first active row may be an odd or even row The unaddressed rows are left unselected In a pseudo interlaced mode rows are addressed as pairs in a sequential manner Depending on the value of the FIELD bit the first row of the first pair may be an odd or
45. lt power on settings which can be overridden via the serial interface An external video clock input VCLK is also available and is enabled disabled via the serial interface Default power up mode is VCLK input disabled Rev 4 SVGA Rev3 XL Series User s Manual 4 AeMagin 4 INPUT OUTPUT DESCRIPTION Connector Part Number Hirose DF12D 3 0 30DP 0 5V TABLE 4 1 INPUT OUTPUT DESCRIPTION EEN 1 I DD Power Power input for the analog and logic circuits 3 3V nominal RESET System Reset Input active low Used to asynchronously reset the entire microdisplay 100 us minimum active Em s amp 1I Clock port for the serial interface 400 KHz Max 4 SDA I O Data port for the serial interface Open collector output with 2 2K on board pull up resistor 5 PWM Io Logic output Reserved for test Pe ka or right or bottom 8 SERADD I Serial Interface LSB address bit Must be connected 9 VAN Power InputpowerforPixel Array 40 VDC nomina 12 VBLACK VO Internal Reference Voltage Monitor Output External Input VBH I ExtemalReference Voltage nn VBL I ExtemalReference Voltage nn NC Open NotUsed 0 0 0 0 0 0 0 NC Open NetUsd 00 000 0 0 y GND Power 1Cpowerretumterminal y RED I Analog video signal inputs 0t0 0 7 V peak to peak GND Power _ ICpowerreturn terminal i O GREEN I Analog video signal input
46. n input pin while PWRDNG 1 When ATB7 0 PWRDN6 has not effect on the VBLACK buffer Default after reset is PWRDNO 0 7 PWRDN7 Active only when ATB7 1 When active high disables and powers down the Bias circuit While PWRDN7 I no internal bias levels or current will be generated preventing all circuit operation except for the digital only blocks such as the serial interface and register controller When ATB7 0 PWRDN7 has no effect Default after reset is PWRDN7 0 Rev 4 SVGA Rev3 XL Series User s Manual 40 AeMagin Name ATB Index 18h Mode Read Write Bit Name Bit Reset Value Description ATB 6 4 0 0 4 6 00h Reserved for internal use ATB5 5 0 MONO Input Bias Source Selection ATB7 7 0 Power down source selection External Automatic Bit Name Description 0 6 ATB 6 4 0 Reserved 5 ATB5 Active high input used to set the black level bias when selecting the MONO input channel ATB5 must be set to I logic high level in order to properly set the black level reference for this mode ATBS5 must be set to 0 logic low level for modes using the R G B inputs 7 ATB7 Active high enable for using the POWERDOWN register as the controlling source for circuit block power downs When ATB7 0 functional blocks are powered down based on the VMODE and HMODE register settings When ATB7 1 the settings in the POWERDOWN register control the functional blocks power down state Default after reset is PWRDNO 0 N
47. nd PAL standards is provided for monochrome only interlaced video sources In the primary monochrome mode the input R G B signals are internally converted to a monochromatic white signal and applied to all three data channels simultaneously The secondary monochrome mode uses the dedicated interlaced composite video monochrome input In either monochrome mode the input data is applied equally to the three sub pixels of each color group These modes are meant for microdisplays delivered without color filters The circuit includes a synchronization processing function that extracts the synchronization signals and restores the input signal dc level In the color mode each color input data is delivered in a raster format and fed to an input buffer and a set of sample and hold stages connected in parallel to the input The output of the sample and hold SAH circuits is applied to the array on a line by line basis during a typical horizontal period At each pixel cell resides a storage element capacitor which is used to control a current source Gray scale is achieved by generating different current levels through the pixel cell driver circuit The array is addressed one row at a time as are conventional flat panel displays Two external voltage references are required to provide for setting the luminance level Rev 4 SVGA Rev3 XL Series User s Manual 3 AeMagin The SVGA microdisplay has built in settings for the following video formats
48. on interlaced SVGA 800 x600 60 72 75 amp 85 Hz non interlaced Interlaced 480 active lines 240 per field timing and levels per SMPTE 170M Interlaced 600 active lines 300 per field levels per SMPTE 170M The Clock recovery circuit can be entirely bypassed and powered down by setting the CLKS bit to GND in the HMODE register In this mode the external pin VCLK is used as the source clock for the microdisplay 9 10 Sync Processor The Sync Processor primary function is to extract the synchronization signals from the composite monochrome video input MONO and output the recovered horizontal vertical and field polarity signals In addition it provides dc restore for the sync stripped video signal For non interlaced video modes the Sync Processor conditions the input HS horizontal synchronization signal via a Schmitt buffer before output to the PLL and other functional blocks The interlaced mode recovery functions are disabled power down when not in use in order to provide for lower operating power NOTE The MONO analog input pin is designed for an ac coupled signal The SVGA microdisplay does not provide the ac coupling function which is left to the display integrator A dc coupled input can be used provided the black level is maintained at a stable reference Failure to do so will result in abrupt luminance changes and possible loss of synchronization 9 11 Serial Interface Rev 4 SVGA Rev3 XL Series User s Manual
49. raphics mode with fixed patterns such as cursors or icons A programmable 16 bit counter HRATE 15 0 is strobed by the vertical synchronization pulse When the count terminates the start and end columns are shifted by one position When the number of shifts has reached five 5 the direction of shift is reversed and so on The compensation mode is selected via the user interface as is the count The default power up value for HRATE 15 0 is 8000h which corresponds to a 9 minute per column shift At 60 Hz the column shift rate can be adjusted from 0 to 18 minutes eMagin does not warranty against fixed pattern burn in effects It is the customer s responsibility to minimize use of the display with fixed patterns for extended periods Automatic turn off of the display when not in use is recommended to minimize luminance loss or pattern burn in The luminance reduction rate increases at high temperatures so added attention to minimizing fixed pattern use should be taken above 40 C Should a fixed pattern burn in occur fixed patterns can typically be mostly erased by running the screen for long periods of time with random motion video e g TV screen savers or movies inverse patterns to the burn on pattern or all white screens For additional information please contact eMagin Technical Support SVGA Rev3 XL Series User s Manual 23 AeMagin 9 9 Clock Recovery The integrated circuit includes a clock recovery unit based on a pha
50. re a consistent reference level on the data lines and reduce the impact of potential residual charges The Pixel driver is designed around a current source operated in the sub threshold region 1n order to output the low current required by the OLED to generate modulated light The driver works in two phases a programming phase and a run phase During the programming phase which lasts for one row period the output of the sample and hold charges the pixel storage capacitor with a current approximately 100 times greater than the value needed for light emission This provides for enough settling time over the specified refresh rate range During the run phase which lasts for one entire frame period minus one row period the pixel driver output current is scaled down by switching the drive transistor into its sub threshold operation region This is achieved by changing the storage capacitor reference level This method preserves the dynamic range as well as the linearity of the overall transfer function 9 5 Voltage References Rev 4 Three reference voltage levels are used in the pixel driver circuit Vblack Vbl and Vbh Vblack can be generated internally or provided externally Vbl and Vbh require external bias SVGA Rev3 XL Series User s Manual 18 e AeMagin The power on condition for the Vblack is the internal reference This setting can be overridden by powering down the internal references after power up using register 17h PDWN bits
51. rer Manufacturer Part Number Mating Connector Information Manufacturer Manufacturer Part Number Weight Printed Circuit Board Material Printed Circuit Board Tolerances Rev 4 SVGA Rev3 XL Series User s Manual Hirose DF12D 3 0 30DP 0 5V Hirose DF12A 3 0 30DS 0 5V 1 9 g nominal FR4 0 8 mm both axes 12 AeMagin 8 CLEANING HANDLING AND STORAGE RECOMMENDATIONS 8 1 Cleaning When cleaning the displays we recommend the use of TECH SPEC lens cleaner manufactured by Edmund Optics Inc and Alpha wipes 1010 8 2 General handling considerations Do not expose the display to strong acids bases or solvents Do not expose the display surface to UV or other strong ionizing radiation Temperatures in excess of the specified operating and storage range can cause irreversible damage to the display Do not allow sharp objects to contact the exposed regions of the silicon display chip Avoid immersion of the display in any liquid The glass cover slip protects the display surface from most forms of damage and may be cleaned using techniques appropriate for fine lenses Avoid applying force to the glass relative to the display chip in compressive tensile and sheer directions Fig 3 Best method of handling the displays p ES Fig 4 Avoid this method of display handling 8 3 Static Charge Prevention Rev 4 The microdisplay is sensitive to electro static discharge damage T
52. ription VSEL Determine the Vertical Mode for the display operation Default is SVGA L0 0 0 SVGA Zoom 6000Rows L0 o 1 VGA I69 480Row 0 1 O 9 Ineraced2 600Rows 0 1 1 Pseudolnterlaced2 600 Rows 1 0 0 Ineraced 1 480 Rows 1 0 1 Pseudolnterlaced I 480 Rows 1 1 0 SVGA Zoom 6000Rows VSCAN Determines the vertical scan direction Default is Scan Down 0 0 Scan Down Top to Bottom 1 Scan Up Bottom to Top VSCANS Determines the source of the vertical direction control Bit5 or the U D external pin Default is the U D external pin I Direction determined by status of VSCAN 0 Direction determined by status of U D pin GND Scan Down top to bottom VDD Scan Up bottom to top SVGA Rev3 XL Series User s Manual 34 e AeMagin 7 SRESET Circuit software reset When active resets all the circuit s registers and power downs all functional blocks except the serial interface The circuit will remain in this reset state until SRESET is deactivated When coming out of reset the circuit will self initialize to the SVGA 60Hz mode Default value is deactivated 0 SRESET inactive I SRESET active Name HMODE Index OAh Mode Read Write Bit Name Bit Reset Value Description HSEL 0 2 04h Horizontal Mode Selection HSCAN 3 0 Horizontal Scan Direction Selection HSCANS 4 0 Horizontal Scan Direction Source Selection CLKS 5 0 Circuit System Clock Source Selec
53. rols the gain of the Mono Analog Input The 8 bit value spans a range of one half to one and a half the signal s full scale value The default reset value is a gain of 1 80h value MOFF 08h Read Write Bit Reset Value Description 0 6 40h Mono Data Channel offset control Description Controls the dc offset of the Mono Analog Input The 6 bit value spans a range of one half to one and a half the signal s full scale value The default reset value is zero offset 40h value Reserved SVGA Rev3 XL Series User s Manual 33 AeMagin Name VMODE Index 09h Mode Read Write Bit Name Bit Reset Value Description COLSEL 0 1 00h Color Mode Selection VSEL 2 4 00h Vertical Sequence Mode Selection VSCAN 5 0 Vertical Scan Direction Selection VSCANS 6 0 Vertical Scan Direction Source Selection SRESET 7 0 Software Reset active high bit Bit Name Description 0 1 COLSEL Determine which data input is used RGB or MONO and the chromaticity of the RGB Bit 2 4 Rev 4 mode color or white only COLSEL 1 COLSEL 0 Color Mode 0 0 RGB inputs selected Default o 0 Whiite Only Mode selected 1 O MONO inputselected The White only mode selection will result in every subpixel of a color group to be addressed with the normalized sum of the R G and B input signals This mode should be selected only for monochrome white applications or for microdisplay specially ordered without color filters Name Desc
54. s 0 to 0 7 V peakto peak GND Power ICpowerreturn terminal _ o o i Y O BLUE OND MONO Power IC power return terminal I Analog video signal inputs 0 to 0 7 V peak to peak Power IC power return terminal Composite Video input 1 0 V peak to peak nominal Lm input TI TT L level VCLK Video data input clock logic input Used when the internal clock TJ MN ee T NC om Nat ss Ne Open NetUsd MN 15 18 20 21 22 23 mm 28 29 30 Rev 4 SVGA Rev3 XL Series User s Manual 5 AeMagin 5 ELECTRICAL CHARACTERISTICS TABLE 5 1 ABSOLUTE MAXIMUM RATINGS Parameter Min 5 Input Voltage Range Output Voltage Range Storage Temperature Junction Temperature Latch up current NENNEN Ilu Vesd Electrostatic Discharge Human Body Model Stresses at or above those listed in this table may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the following tables is not implied Exposure to absolute maximum rated temperatures or voltages in the chart below for extended periods may affect device reliability Prolonged exposure to high temperatures will shorten the luminance half life Protection diodes are suggested between Vcommon and ground to protect against power supply spikes TABLE 5 2 R
55. se locked loop circuit The PLL s modulus divider is programmed through the serial interface Its default power up value is set for a 60Hz SVGA video mode The circuit regenerates the pixel clock based on the horizontal synchronization input line locked system This signal is generated by the Sync Processor and has been conditioned to provide a short rise fall time The on chip voltage controlled oscillator is fed by the phase detector through an external low pass filter resistor capacitor combination The output of the VCO feeds a programmable post scaler divide by 1 2 4 8 and 16 and the feedback divider A post scaler is required to ensure compatibility of a single VCO with VGA through SXGA video formats as well as the interlaced video modes lower frequency In addition a charge pump gain control is provided to match the pump s output to the frequency selected The PLL circuit provides for fine phase adjust via a dedicated register PI2 A programmable delay controls the clock phase with respect to the recovered HSYNC signal The unit delay is 1 32 of the clock period after the post scaler The phase interpolator circuit can be bypassed and powered down by setting the PIBYP bit to 1 in the PI2 register In this configuration only four phase selections are possible 0 90 180 and 270 degrees The IC supports eight VESA standard monitor timing configurations and up to two interlaced timings VGA 640 x 480 60 72 75 amp 85 Hz n
56. tion HMODE6 6 0 Reserved HSOFT 7 1 Screen Saver Enable Bit Name Description 0 2 HSEL Determines the horizontal mode for the display Default is SVGA HSEL2 HSEL1 HSEL 0 Horizontal Mode rd 800 Columns ee 640 Columns po I 1 0 SVGA 00 Columns Interlaced 2 Pseudo Interlaced 2 800 Columns x x 16 9 amp zoom 852Columns 3 HSCAN Determines the horizontal scan direction Default is Scan Right 0 0 Scan Right Left to Right I Scan Left Right to Left 4 HSCANS Determines the source of the horizontal direction control Bit3 or the U D external pin Default is U D external pin Direction determined by status of HSCAN 0 Direction determined by status of L R pin GND Scan Right left to right VDD Scan Left right to left 5 CLKS Determines the source of the circuit system clock PLL or the VCLK external pin Default is internal PLL 0 Clock source is internal PLL I Clock source is external pin VLCK When CLKS 1 the PLL and Phase Interpolator are powered down Rev 4 SVGA Rev3 XL Series User s Manual 35 AeMagin Bit Name Description 6 HMODE6 Reserved 7 HSOFT Activates deactivates the horizontal screen saver mode When activated the image frame will be moved left to right and right to left over a 5 pixel span at a rate determined by the value of HRATE See below register index OEh and OFh This mode is not applicable to the horizontal Zoom mode Default is screen saver mode act
57. trol BGAIN BGAIN 7 0 80 50 Blue channel gain control 06 T so Ww sor 7 0 Jet som so 4 sr 50 Ble channel ofeetcontal iE MGAIN MGAIN 701 80 50 Mono channel gain control as mor WW mor T7 0 Rees MOFF 60 40 50 Mono channel offset control SRESET Software Reset Clears all registers to default setting powerdowns analog blocks and holds until released 1 7 VSCANS 6 0 Vertical Scan Direction Source 1 VMODES 0 U D VSCAN 5f 0 Vertical Scan Direction 1 Up 0 Down VSEL 24 0 Vertical Sequence Mode select COLSEL 1 0 0 Color Mode 00 rgb 01 white 10 composite mmer 6 Resened CLKS 5f 0 Clock Source 1 VCLK 0 PLL HSCANS 4 0 Horizontal Scan Direction Source 1 HMODE3 0 L R HSCAN 3 0 Horizontal Scan Direction 0 Left 1 Right HSEL Horizontal Mode Select 3 T ser WW sm 7 9 Reserves smear T7 59 esee oD HRATE L HRATE 7 0 rel 0 Horizontal Frame Shift Rate Counter lower bits HRATE_U HRATE 15 8 7 0 80 Horizontal Frame Shift Rate Counter upper bits PLL_L FBD 7 0 PLL Feedback Divider lower bits Continued PLL U ICPSEL 1 0 7 6 1 Charge Pump Current Control 5 wes aw Rev 4 SVGA Rev3 XL Series User s Manual 2 No AeMagin PLL U5 5 15 0 esee PSD 1 0 PLL Post Scaler Divider Register FBD 10 8 PLL Feedback Divider upper bits BREFQ 4 0
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