SuperHTM Family E10A-USB Emulator Additional
Contents
1. TMS TDI RESETP lt Reset signal User system Figure 1 2 Recommended Circuit for Connection between the H UDI Port Connector and MPU when the Emulator is in Use 14 Pin Type UVCC Connected ENESAS When the circuit is connected as shown in figure 1 3 the switches of the emulator are set as SW2 0 and SW3 1 For details refer to section 3 8 Setting the DIP Switches in the SuperH Family El0A USB Emulator User s Manual VccQ 3 3 V I O power supply Pulled up at 4 7 kQ or more all VecQ VecQ VecQ VccQ H UDI port connector SH7750 14 pin type QFP 208 lt Reset signal User system Figure 1 3 Circuit for Connection between the H UDI Port Connector and MPU when the Emulator is in Use 14 Pin Type UVCC Not Connected Note When UVCC is not connected and the user system is turned off note that the leakage current flows from the emulator to the user system ENESAS Section 2 Specifications of the Software when Using the SH7750 2 1 Differences between the SH7750 SH7750S and the Emulator 1 When the emulator system is initiated it initializes the general registers and part of the control registers as shown in table 2 1 When the emulator is initiated from the workspace a value to be entered is saved in a session Table 2 1 Register Initial Values at Emulator Link Up Register Emulator at Link Up RO to R14 H 00000000 R15 SP H 00000000 RO2. 5 198 TRST Input C 4 200 TDO Output A 6 194 ASEBRK Output B 7 193 BRKACK TMS Input B 6 197 TDI Input B 5 199 RESETP Output B 1 2 User reset N C GND TT uvece a Outpt D GND GND 3 Output gt Input to or output from the user system The slash means that the signal is active low The emulator monitors the GND signal of the user system and detects whether or not the user system is connected If the VccQ pin is not connected to the UVCC the I O voltage of the user system interface will be fixed to 3 3 V This pin can be connected to GND Pin 1 mark H UDI port connector top view la ob NIN 23 0 H UDI port connector 6 x 2 54 15 24 top view Joea Pin 1 mark Unit mm Figure 1 1 Pin Assignments of the H UDI Port Connector ENESAS 1 5 1 5 1 Recommended Circuit between the H UDI Port Connector and the MPU Recommended Circuit 14 Pin Type Figure 1 2 shows a recommended circuit for connection between the H UDI port connector and the MPU when the emulator is in use Figure 1 3 shows a circuit for connection when UVCC is not connected Notes 1 Do not connect anything to the N C pins of the H UDI port connector 2 When a network resistance is used for pull up it may be affected by a noise Separate TCK from other resistances The pattern between the H UDI port connector and the MPU must be as short as possible Do not connect the signal lines to other comp
3. channels the total elapsed cycle and the elapsed cycle for the specified program area can be measured and the ratio of the execution time in the specified program area to the total execution time can be obtained Notes 1 The counter for performance measurement has 48 bits A maximum of 2 2 8 x 10 counts and 16 3 day cycles when the CPU operating frequency is 200 MHz can be measured If a counter overflow occurs the count becomes invalid 2 When performance measurement conditions are set canceled or initialized the settings in the UBC are not guaranteed 3 Set the same start and end PC values for both channels 1 and 2 If different PC values are set the last settings become valid 4 When the start and end PC values are set with this command the value that has been previously set for UBC becomes invalid 5 For details on command line syntax refer to the online help 25 ENESAS 2 Displaying the measured result The measured result is displayed in the Performance Analysis window or the PERFORMANCE_ANALYSIS command with hexadecimal 32 bits Note Ifa performance counter overflows as a result of measurement will be displayed 3 Initializing the measured result To initialize the measured result select Initialize from the popup menu in the Performance Analysis window or specify INIT with the PERFORMANCE_ANALYSIS command 2 2 7 Note on Using the Profile Function While the profile function is
4. count the number of times the instruction has not been fetched in one cycle e When a cache miss occurs during an overrun fetch generated at exception TLB miss count When the TLB miss is canceled by an exception DT and ET having a higher priority than that of the TLB miss Instruction fetch count e When the instruction fetch request by the CPU EF and EA is accepted e Does not count when the cache is bypassed from the external bus to supply the instruction to the CPU at instruction cache miss Instruction issue count Counts one when two instructions are issued at the E same time Counts one to three when instruction fetch E and E2 exception instruction address error instruction TLB miss exception or instruction TLB protection violation exception occurs FPU instruction issue count c Counting method e Counts one when two instructions are issued at EFP the same time e The following shows the FPU instructions LDS Rm FPUL LDS L Rm FPUL LDS Rm FPSCR LDS L Rm FPSCR STS FPUL Rn STS L FPUL Rn STS FPSCR Rn STS L FPSCR Rn Others instructions that the instruction code is H Fxxx One of the following methods can be specified by each of measurement channels 1 and 2 1 Counted by the CPU operating clock 2 Counted by the ratio of the CPU operating clock to the bus clock 24 ENESAS When the above method 1 is specified one CPU operating clock cycle is counted as one
5. execution an interrupt that is generated at the program execution start or end including a step operation can be traced in realtime 2 Notes on Setting the Trace Acquisition Window 1 When the Acquire continuous trace check box is selected do not perform memory access during emulation 2 When internal I O trace or LDTLB instruction trace is performed select the Acquire continuous trace check box 3 When the Acquire continuous trace check box is selected 32 trace information data can be acquired In this case however since the user program stops at constant intervals the processing speed is decreased compared with the case where the Acquire continuous trace check box is not selected ENESAS 4 Trace information cannot be acquired for the following branch instructions e The BF and BT instructions whose displacement value is 0 e Branch to H A0000000 by reset 5 When the Acquire continuous trace check box is selected and when either the Get trace information of internal I O area radio button internal I O trace enabled or the Get trace information of LDTLB instruction radio button is selected LDTLB instruction trace enabled with the Break Condition 5 dialog box e An internal I O trace cannot be made with the Step In command e The LDTLB instruction and internal I O trace cannot be performed with the Step Over command 6 Do not use the continuous trace for a program in which an SGR value is referred to
6. set is determined when the BREAKPOINT is set Accordingly even if the VP_MAP table is modified after BREAKPOINT setting the BREAKPOINT address remains unchanged When a BREAKPOINT is satisfied with the modified address in the VP_MAP table the cause of termination displayed in the status bar and the System Status window is ILLEGAL INSTRUCTION not BREAKPOINT 12 When a BREAKPOINT is set to the cacheable area the cache block containing the BREAKPOINT address is filled immediately before and after user program execution 13 While a BREAKPOINT is set the contents of the instruction cache are disabled at execution completion 14 If an address of a BREAKPOINT cannot be correctly set in the ROM or flash memory area a mark will be displayed in the BP area of the address on the Source or Disassembly window by refreshing the Memory window etc after Go execution However no break will occur at this address When the program halts with the break condition the mark disappears 1 jean 2 2 5 Notes on Setting the Break Condition Dialog Box and the BREAKCONDITION_ SET Command 1 When Go to cursor Step In Step Over or Step Out is selected the settings of Break Condition 4 are disabled 2 Break Condition 4 is disabled when an instruction to which aBREAKPOINT has been set is executed Accordingly do not seta BREAKPOINT to an instruction which satisfies Break Condition 4 3 When a Break Condition is satisfied e
7. the online help 27 ENESAS 28 ENESAS SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH7750 Publication Date Rev 1 00 March 15 2004 Rev 2 00 March 19 2007 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Communication Div Renesas Solutions Corp 2007 Renesas Technology Corp All rights reserved Printed in Japan RenesasTechnology Corp Sales Strategic Planning Div Nippon Bldg 2 6 2 Ohte machi Chiyoda ku Tokyo 100 0004 Japan ENESAS RENESAS SALES OFFICES http www renesas com Refer to http www renesas com en network for the latest and detailed information Renesas Technology America Inc 450 Holger Way San Jose CA 95134 1368 U S A Tel lt 1 gt 408 382 7500 Fax lt 1 gt 408 382 7501 Renesas Technology Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel lt 44 gt 1628 585 100 Fax lt 44 gt 1628 585 900 Renesas Technology Shanghai Co Ltd Unit 204 205 AZIACenter No 1233 Lujiazui Ring Rd Pudong District Shanghai China 200120 Tel lt 86 gt 21 5877 1818 Fax lt 86 gt 21 6887 7898 Renesas Technology Hong Kong Ltd 7th Floor North Tower World Finance Centre Harbour City 1 Canton Road Tsimshatsui Kowloon Hong Kong Tel lt 852 gt 2265 6688 Fax lt 852 gt 2730 6071
8. 750 and Test program manual HS0005TM01HJ and for HS0005KCUO1H HS0005TMO1HE and HSO005KCU02H provided on a CD R Note Additional document for the MPUs supported by the emulator is included Check the target MPU and refer to its additional document ENESAS 1 2 Connecting the E10A USB Emulator with the User System To connect the EIOA USB emulator hereinafter referred to as the emulator the H UDI port connector must be installed on the user system to connect the user system interface cable When designing the user system refer to the recommended circuit between the H UDI port connector and the MCU In addition read the EIOA USB emulator user s manual and hardware manual for the related device 1 3 Installing the H UDI Port Connector on the User System Table 1 2 shows the recommended H UDI port connectors for the emulator Table 1 2 Recommended H UDI Port Connectors Connector Type Number Manufacturer Specifications 14 pin connector 2514 6002 Minnesota Mining amp 14 pin straight type Manufacturing Ltd Note Do not place any components within 3 mm of the H UDI port connector 1 4 Pin Assignments of the H UDI Port Connector Figure 1 1 shows the pin assignments of the H UDI port connector Note Note that the pin number assignments of the H UDI port connector shown on the following pages differ from those of the connector manufacturer ENESAS Input SH7750 Pin No PinNo Signal Output BGA256 HQFP208 A TCK Input A
9. BT The number of times branches are taken branches to be counted are the same as mode B Instruction execution count E 22 The number of times instructions are issued ENESAS Table 2 7 Measurement Items cont Event Keyword Description Two instruction concurrent E2 execution count The number of times two instructions are issued at the same time FPU instruction execution EFP count The number of times FPU instruction is issued TRAPA instruction ETR execution count The number of times the TRAPA instruction is executed Interrupt count normal INT The number of interrupts generally except for NMI Interrupt count NMI NMI The number of NMI interrupts Instruction cache fill cycle ECF The number of instruction cache fill cycles Operand cache fill cycle OCF The number of operand cache fill cycles Elapsed time cycle TM Note For the non cache operand accesses due to the PREF instruction or TLB c 0 the correct value cannot be counted The number of cycles for elapsed time The events can be counted even in the conditions shown in table 2 8 in addition to the normal count conditions ENESAS 23 Table 2 3 Performance Count Conditions Event All count conditions Count Condition Target Mode When the event to be counted up is canceled by an All exception Instruction cache miss count e Includes instruction fetch for the cache off area EC to
10. Condition 3 is satisfied ENESAS 5 When execution resumes from the address where aBREAKPOINT is specified single step operation is performed at the address before execution resumes Therefore realtime operation cannot be performed 6 When a BREAKPOINT is set to the slot instruction of a delayed branch instruction the PC value becomes an illegal value Accordingly do not set a BREAKPOINT to the slot instruction of a delayed branch instruction 7 When the Normal option is selected in the Memory area group box in the General page of the Configuration dialog box aBREAKPOINT is set to a physical address or a virtual address according to the SH7750 or SH7750S MMU state during command input when the VPMAP_SET command setting is disabled The ASID value of the SH7750 or SH7750S PTEH register during command input is used When VPMAP_SET command setting is enabled aBREAKPOINT is set to a physical address into which address translation is made according to the VP_MAP table However for addresses out of the range of the VP_MAP table the address to which a BREAKPOINT is set depends on the SH7750 or SH7750S MMU state during command input Even when the VP_MAP table is modified after BREAKPOINT setting the address translated at BREAKPOINT setting is valid 8 When the Physical option is selected in the Memory area group box in the General page of the Configuration dialog box aBREAKPOINT is set to a physical address A BREAKPOINT is se
11. REJ10B0115 0200 Everywhere you imagine y gE NESAS SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH7750 Renesas Microcomputer Development Environment System SuperH Family SH7750 Series E10A USB for SH7750 HS7750KCU01HE Rev 2 00 Revision Date Mar 19 2007 Renesas Technology www renesas com Notes regarding these materials This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document including but not limited to product data diagrams charts programs algorithms and application circuit examples You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use When exporting the products or technology described herein you should follow the applicable export control laws a
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13. When method 2 is specified the count is incremented by 3 4 6 8 12 or 24 according to the clock frequency ratio ratio of the CPU clock to the bus clock In this case the execution time can be calculated by the following expression T CxB 24 T Execution time B Time of one bus clock cycle C Count When the ratio of the CPU clock to the bus clock is changed in the user program it is recommended to select method 2 above to count the number of cycles The following shows examples to measure the performance of the user program by the performance measurement function i Measuring cache hit ratio Specify measurement channel 1 to count the cache misses for data read and write and specify measurement channel 2 to count operand accesses read and write to the cacheable area while the cache is enabled Specify with both the channels the measurement from the start to the end of user program execution With the above command settings the cache miss count and the access count to the cacheable area can be measured and the cache hit ratio in the executed user program can be obtained ii Measuring ratio of execution time in specified program area to total execution time Specify measurement channel 1 to measure the elapsed cycle count from the start to the end of user program execution Specify measurement channel 2 to measure the elapsed cycle count during execution from the specified start PC to the specified end PC With both the
14. _BANK to R7_BANK H 00000000 PC H A0000000 SR H 700000F0 GBR H 00000000 VBR H 00000000 MACH H 00000000 MACL H 00000000 PR H 00000000 DBR H 00000000 SGR H 00000000 SPC H 00000000 SSR H 000000F0 FPUL H 00000000 FPSCR H 00040001 FRO to FR15 H 00000000 XFO to XF15 H 00000000 2 The emulator uses the H UDI do not access the H UDI ENESAS 3 Low Power States Sleep Standby and Module Standby For low power consumption the SH7750 and SH7750S have sleep standby and module standby modes The sleep and standby modes are switched using the SLEEP instruction When the emulator is used the sleep mode can be cleared by either normal clearing or by the satisfaction of a break condition including BREAK key input In the latter case the user program breaks The standby mode can be cleared with the normal clearing function or BREAK key input and after the standby mode is cleared the user program operates correctly Note however that if a command has been entered in standby mode or module standby mode no commands can be used from the emulator after the standby mode is cleared Note After the sleep mode is cleared by a break execution restarts at the instruction following the SLEEP instruction If the memory is accessed or modified in sleep mode the sleep mode is cleared and execution starts at the instruction following the SLEEP instruction Although the SH7750S supports the hardware standby function if the emulator enters the hardware
15. being used in addition to the description in section 5 8 12 in the SuperH Family EIOA USB Emulator User s Manual the following functions cannot be used 1 Continuous trace function When the profile function is enabled do not use the continuous trace function that can be used in the internal trace function The profile data cannot be measured correctly 2 Internal trace function When the profile function is enabled mode selection of the internal trace is disabled since all items of the internal trace modes are selected in the emulator 3 Halt function When the profile function is enabled do not use the halt function for the internal trace 2 2 8 Interrupts During emulation any interrupt to the SH7750 or SH7750S can be used Whether or not to process interrupts during emulator command execution or in command input wait state can be specified When no interrupt is processed during user program execution or in command input wait state While the emulator is executing the user program or is in command input wait state interrupts are not processed generally However if an internal interrupt or an edge sensitive external interrupt occurs in command input wait state the emulator holds the interrupt and executes the interrupt processing routine when the GO command is entered When interrupts are processed during user program execution or in command input wait state 26 ENESAS Notes To process the non maskable i
16. ct the Get trace information of internal I O Area radio button in the Break Condition 5 dialog box and the Acquire continuous trace check box of the Branch trace page LDTLB instruction execution trace 14 Traces and displays the address that executes the LDTLB instruction To use this function select the Get trace information of LDTLB instruction radio button in the Break Condition 5 dialog box and the Acquire continuous trace check box of the Branch trace page ENESAS 1 Notes on the Trace Window 1 If an interrupt is generated at the program execution start or end including a step operation the emulator address may be acquired In such a case the following message will be displayed Ignore this address because it is not a user program address 2 If a TLB error occurs while acquired trace information is displayed the following error message will be displayed Figure 2 1 Message Box for Clearing a TLB Error After a TLB error trace acquisition cannot be performed 3 When MMU settings are modified or when a user program is changed between GO command completion and trace display the displayed mnemonics or operand may not be correct 4 If a completion type exception occurs during exception branch acquisition the next address to the address in which an exception occurs is acquired 5 When a user interrupt is enabled by the INTERRUPT command during the emulator command wait state or user program
17. document may not be reproduced or duplicated in any form in whole or in part without prior written approval from Renesas Please contact a Renesas sales office if you have any questions regarding the information contained in this document Renesas semiconductor products or if you have any other inquiries Contents Section 1 Connecting the Emulator with the User System 1 1 1 Components of the Emulator oononncnnonnnnnnnoncnnnconnconnnnnnnnnonnnono nono conan cnn nono crac rca nano rn conan 1 1 2 Connecting the EIOA USB Emulator with the User System oooononncnnnninccnonnconnnanonancnnncnos 2 1 3 Installing the H UDI Port Connector on the User System u ursserssersnessnennennneennennnennn 2 1 4 Pin Assignments of the H UDI Port Connector ooococnnonnnonononcnnncononononononenonn conan ran crono nenn 2 1 5 Recommended Circuit between the H UDI Port Connector and the MPU 4 1 5 1 Recommended Circuit 14 Pin Type eee eeseeseeeseeeeeeeeeseeesseeeseeeeeeeeeaees 4 Section 2 Specifications of the Software when Using the SH775O 7 2 1 Differences between the SH7750 SH7750S and the Emulator enneeee 7 2 2 Specific Functions for the Emulator when Using the SH77S0 uu22u422usse nennen 11 2 2 1 Break Condition Functions 00 0 eee eeceeseeseeeeeesecesesececeeeeseeeaeseaeesaeesseesseenees 11 22 2 Trace Functions ici ciclista oi 13 2 2 3 Notes on Using the JTAG Cl
18. e displayed for NAME in the Performance Analysis window Table 2 7 Measurement Items Event Keyword Description Operand access count OARW read and write with cache The number of times the operand access is performed on the cacheable area when the cache is enabled both read and write accesses Internal RAM operand OARAM access count The number of times the internal RAM area is accessed All operand access count OA The number of all operand accesses Internal I O area access IOA count The number of times the internal I O area is accessed Operand cache read and DCRW write miss count The number of times operand cache misses occur at data reading or writing Instruction cache miss EC The number of times instruction cache misses count UTLB miss count DT The number of times UTLB misses occur at data access Instruction TLB miss count ET ITLB and UTLB misses The number of times UTLB and ITLB misses occur at instruction access Instruction fetch count EF The number of times instructions are fetched from the cacheable area when the cache is enabled All instruction fetch count EA The number of times all instructions are fetched Branch instruction B execution count The number of times branch instructions are issued instructions to be counted BF other than displacement 0 BF S and BT other than displacement 0 BT S BRA BRAF and JMP Branch taken count
19. er is 1 do not use BREAKPOINTs 2 Ifa break is specified for an address that is close to an address whose instruction generates a manual reset a manual reset may be generated instead of a break Therefore to ensure the performance of a break specify a break for an address that is four addresses before the address whose instruction generates an exception ENESAS The emulator has sequential break functions Table 2 5 shows the sequential break conditions Table 2 5 Sequential Break Conditions Break Condition Description Sequential break condition 2 1 Program is halted when Break Condition 2 and Break Condition 1 are satisfied in that order Break Condition 2 1 should be set Sequential break condition 3 2 1 Program is halted when Break Condition 3 Break Condition 2 and Break Condition 1 are satisfied in that order Break Condition 3 2 1 should be set Sequential break condition 4 3 2 1 Program is halted when Break Condition 4 Break Condition 3 Break Condition 2 and Break Condition 1 are satisfied in that order Break Condition 4 3 2 1 should be set 2 2 2 Trace Functions The emulator does not support the AUD function Table 2 6 shows the internal trace functions 13 ENESAS Table 2 6 Internal Trace Functions Function Branch instruction trace Description Traces and displays the branch instructions The branch source address and branch destination address for the eight latest branch instructions are displa
20. ll be about 45 ms Interrupt When the NMIB bit in the ICR register is 1 the NMI interrupt is accepted during break and the program is executed from the NMI interrupt vector If the program cannot return normally from the NMI interrupt routine or the value in the general purpose register is not guaranteed a communication timeout error will occur Memory Access during User Program Break The emulator can download the program for the flash memory area refer to section 6 22 Download Function to the Flash Memory Area in the SuperH Family EIOA USB Emulator User s Manual Other memory write operations are enabled for the RAM area Therefore an operation such as memory write or BREAKPOINT should be set only for the RAM area When the memory area can be written by the MMU do not perform memory write BREAKPOINT break or downloading Cache Operation during User Program Break When cache is enabled the emulator accesses the memory by the following methods e Atmemory write Writes through the cache then writes to the memory e At memory read Does not change the cache write mode that has been set Therefore when memory read or write is performed during user program break the cache state will be changed When the half of operand cache is used as an internal RAM and memory fill is performed in this area the verify option must be disabled Memory fill is not performed correctly if the verify option is enabled Loading Sessions Infor
21. mation in JTAG clock of the Configuration dialog box cannot be recovered by loading sessions Thus the TCK value will be 0 625 MHz ENESAS 11 10 Window Display and modification When End is set in the UBC Mode list box of the Configuration dialog box do not change values of the User Break Controller because it is used by the emulator For each watchdog timer register there are two registers to be separately used for write and read operations Table 2 2 Watchdog Timer Register Register Name Usage Register WTCSR W Write Watchdog timer control status register WTCNT W Write Watchdog timer counter WTCSR R Read Watchdog timer control status register WTCNT R Read Watchdog timer counter Note The watchdog timer operates only when the user program is executed Do not change the value of the frequency change register in the IO window or Memory window The internal I O registers can be accessed from the IO window However note the following when accessing the SDMR register of the bus state controller Before accessing the SDMR register specify addresses to be accessed in the I O register definition file SH7750 IO and then activate the High performance Embedded Workshop After the I O register definition file is created the MPU s specification may be changed If each I O register in the I O register definition file differs from addresses described in the hardware manual change the I O register definiti
22. mulation may stop after two or more instructions have been executed ENESAS If a PC break address condition is set to the slot instruction after a delayed branch instruction user program execution cannot be terminated before the slot instruction execution execution stops before the branch destination instruction In the Configuration dialog box if User is set while the UBC mode list box has been set Break Condition 5 6 are available 19 ENESAS 2 2 6 Performance Measurement Functions The emulator supports the performance measurement function 1 Setting the performance measurement conditions To set the performance measurement conditions use the CPU Performance dialog box and the PERFORMANCE_SET command When any line on the Performance Analysis window is clicked with the right mouse button the popup menu is displayed and the CPU Performance dialog box is displayed by selecting Setting GPU Performance GPU performance GPU performance Channel 1 FF Don t care Mode Operand access countread write with cache 7 Count clock Cpu clock IV Use range Channel 2 Y Don t care Mode UTLB miss Count clock Gu clock O Ratio for Cpu and Bus clock Use range Start address 4 End address H FFFFFFFF Figure 2 3 CPU Performance Dialog Box Note For the command line syntax refer to the online help 20 ENESAS The emulator measures how many times the conditi
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25. nterrupt and peripheral module interrupts during emulator command execution and in command input wait state use the INTERRUPT command Input the INTERRUPT command into the command line window To process only the non maskable interrupt Specify nonmask in the lt interrupt_enable gt option of the INTERRUPT command To process the non maskable interrupt and peripheral module interrupts Specify all in the lt interrupt_enable gt option of the INTERRUPT command To switch to the mode in which no interrupt is processed Specify disable in the lt interrupt_enable gt option of the INTERRUPT command Check that the interrupt handler operates normally before using this function In addition do not execute a non limited loop or the sleep instruction in the interrupt handler If the processing of the handler does not end the emulator generates a Communication Timeout error When interrupts are accepted during user program execution and emulator command execution state user interrupt processing is not traced In this case continuous trace is not enabled Use the NOP instruction at the delay slot after the RTE instruction in the interrupt handler If a user interrupt is inserted while the user program breaks until the processing ends do not set a BREAKPOINT in the interrupt handler The emulator may generate a Communication Timeout error Use the Break Condition function For details on window function and command line syntax refer to
26. ock TCK oooconnncccnonccionncononcnoncconnncnonccnnnccnonccnnnccnnne 16 2 2 4 Notes on Setting the Breakpoint Dialog BOX oooooncnnnnnicnnncnnocononcnnnccnnnanonanonnnos 16 2 2 5 Notes on Setting the Break Condition Dialog Box and the BREAKCONDITION_ SET Command eccoooconccnccnonononononnnnncnncanonononcnnncnncncnnos 18 2 2 6 Performance Measurement Functions uesessnessnesnnennnennnennnnnennnnnnnnsnnnnnnnnnnnnen 20 2 2 7 Note on Using the Profile Function oconocnnnnnonnnnnnonnnononononononanona conan ona nn nonn conan 26 22 8 INIELWPIS 1 0 een in BASS IR kei 26 RENESAS ENESAS Section 1 Connecting the Emulator with the User System 1 1 Components of the Emulator The E10A USB emulator supports the SH7750 and SH7750S Table 1 1 lists the components of the emulator Table 1 1 Components of the Emulator Classi Quan fication Component Appearance tity Remarks 1 HS0005KCUO01H Depth 65 0 mm Width 97 0 mm Height 20 0 mm Mass 72 9 g or HS0005KCU02H Depth 65 0 mm Width 97 0 mm Height 20 0 mm Mass 73 7 g Hard Emulator box ware User system interface gt 1 14 pin type cable Length 20 cm Mass 33 1 g USB cable 1 Length 150 cm Mass 50 6 g Soft SH7750 E10A USB 1 HS0005KCU01SR ware emulator setup Ce gt program SuperH Family HS0005KCUO1HJ E10A USB Emulator HSOOO5KCU01HE User s Manual Supplementary HS7750KCUO1HJ Information on Using HS7750KCU01HE the SH7
27. on file according to the description in the hardware manual The I O register definition file can be customized depending on its format Note that however the emulator does not support the bit field function As default SDMR2 and SDMR3 are specified in the I O register definition file as the SDMR registers in areas 2 and 3 respectively When the SH7750S is used the IPRD register is not displayed in the IO window To get it to display edit the I O register definition file SH7750 IO as follows and start the HEW In SH7750 IO locate IPRC 0xFFDOO00C W A Under this add IPRD OxFFDO0010 W A and save the file Verify In the IO window the verify function of the input value is disabled ENESAS 12 Illegal Instructions If illegal instructions are executed by STEP type commands the emulator cannot go to the next program counter 2 2 Specific Functions for the Emulator when Using the SH7750 2 2 1 Break Condition Functions In addition to BREAKPOINT functions the emulator has Break Condition functions Five types of conditions can be set under Break Condition 1 2 3 4 5 Table 2 3 lists these conditions of Break Condition Table 2 3 Types of Break Conditions Break Condition Type Description Address bus condition Address Breaks when the SH7750 or SH7750S address bus value or the program counter value matches the specified value Data bus condition Data Breaks when the SH7750 or SH7750S data bus val
28. onents on the board When the power supply of the user system is turned off supplying VccQ of the user system to the UVCC pin reduces the leakage current from the emulator to the user system A level shifter that is activated by the internal power supply or user power supply changed by the switch is installed in the interface circuit of the emulator If the user power is supplied to the UVCC pin the level shifter is not activated as long as no user power is supplied When the power supply of the user system is turned off no current flows from the user interface The I O voltage level of the user system interface can be the same as that of the VccQ To operate the emulator with low voltage lower than 3 3 V the VccQ must be supplied to the UVCC pin Make the emulator s switch settings so that the VccQ will be supplied SW2 1 and SW3 1 as shown in figure 1 2 The resistance values shown in figures 1 2 and 1 3 are recommended For the pin processing in cases where the emulator is not used refer to the hardware manual of the related MPU ENESAS When the circuit is connected as shown in figure 1 2 the switches of the emulator are set as SW2 1 and SW3 1 For details refer to section 3 8 Setting the DIP Switches in the SuperH Family El0A USB Emulator User s Manual VccQ 3 3 V I O power supply Pulled up at 4 7 kQ or more all VecQ VecQ VccQ VccQ H UDI port connector SH7750 14 pin type QFP 208 TCK TRST
29. ons of the user program specified with the performance analysis function are satisfied For this function two events can be measured simultaneously and the following conditions can be specified When the PC value is set the original UBC function is not available because the UBC is used to specify the measurement start and end PC values a Measurement range One of the following ranges can be specified by either of measurement channels 1 and 2 1 From the start to the end of the user program execution 2 From the satisfaction of the condition set in Start address to the satisfaction of the condition set in End address When the first range is specified the measurement result includes a several cycle error for one user program execution Therefore do not specify this range when the step is to be executed In addition the user program execution stops when continuous trace is used again do not specify the first range in this case Note When the range is specified be sure to select the Use range check box set the measurement start and end conditions for Start address and End address respectively and then execute the user program 21 ENESAS b Measurement item Items are measured with Channel 1 to 2 in the CPU Performance dialog box Maximum two conditions can be specified at the same time Table 2 7 shows the measurement items Options in table 2 7 are parameters for lt mode gt of the PERFORMANCE _SET command They ar
30. standby mode a TIMEOUT error will occur When the SLEEP instruction is executed by a step command and Step in the Run menu is used set Rate as 6 If 5 or lower value is set a communication timeout error will occur 4 Reset Signals The SH7750 and SH7750S reset signals are only valid during emulation started with clicking the GO or STEP type button If these signals are enabled on the user system in command input wait state they are not sent to the SH7750 or SH7750S Note Do not break the user program when the RESET or BREQ signal is being low or the RDY signal is being high A TIMEOUT error will occur If the BREQ signal is fixed to low or the RDY signal is fixed to high during break a TIMEOUT error will occur at memory access 5 Direct Memory Access Controller DMAC The DMAC operates even when the emulator is used When a data transfer request is generated the DMAC executes DMA transfer 6 Memory Access during User Program Execution When a memory is accessed from the memory window etc during user program execution the user program is resumed after it has stopped in the emulator to access the memory Therefore realtime emulation cannot be performed ENESAS 10 The stopping time of the user program is as follows Environment Host computer 1 GHz Pentium IN OS Windows 2000 SH7750 200 MHz CPU clock JTAG clock 20 MHz When a one byte memory is read from the command line window the stopping time wi
31. t after disabling the SH7750 or SH7750S MMU during program execution After setting the MMU is returned to the original state When a break occurs at the corresponding virtual address the cause of termination displayed in the status bar and the System Status window is ILLEGAL INSTRUCTION not BREAKPOINT 9 When the Virtual option is selected in the Memory area group box in the General page of the Configuration dialog box a BREAKPOINT is set to a virtual address A BREAKPOINT is set after enabling the SH7750 or SH7750S MMU during program execution After setting the MMU is returned to the original state When an ASID value is specified the BREAKPOINT is set to the virtual address corresponding to the ASID value The emulator sets the BREAKPOINT after rewriting the ASID value to the specified value and returns the ASID value to its original value after setting When no ASID value is specified the BREAKPOINT is set to a virtual address corresponding to the ASID value at command input 10 If a TLB error occurs during virtual address setting the following message box will be displayed ENESAS neadr x IN TLB ERROR EXPEYT 00000040 Figure 2 2 Message Box for Clearing a TLB Error If a program is executed again without clearing the BREAKPOINT set at the address in which the TLB error occurs a TLB error will occur again Accordingly clear the BREAKPOINT before execution An address physical address to which a BREAKPOINT is
32. ue matches the specified value Byte word or longword can be specified as the access data size ASID condition ASID Breaks when the SH7750 or SH7750S ASID value matches the specified condition Bus state condition There are two bus state condition settings Bus State Read write condition Breaks in the read or write cycle of the SH7750 or SH7750S Bus state condition Breaks when the operating state in an SH7750 or SH7750S bus cycle matches the specified condition LDTLB instruction break condition Breaks when the SH7750 or SH7750S executes the LDTLB instruction Internal I O break condition Breaks when the SH7750 or SH7750S accesses the internal VO Note For the window function or command line syntax refer to the online help 11 ENESAS Table 2 4 lists the combinations of conditions that can be set under Break Condition 1 2 3 4 5 Table 2 4 Dialog Boxes for Setting Break Conditions Dialog Box Break Condition 1 Break Condition 2 Break Condition 5 Dialog Box 3 4 Dialog Box Dialog Box Address bus condition O O X Address Data bus condition O x X Data ASID condition ASID O O X Read write O O X specification Data access O O X Before after execution O O X Sequential break O O X LDTLB instruction X X O break Internal I O access X X O break Note O Can be set in the dialog box X Cannot be set in the dialog box Notes 1 If the BL bit of the SR regist
33. um rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges Although Renesas endeavors to improve the quality and reliability of its products IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Please be sure to implement safety measures to guard against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other applicable measures Among others since the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed the risk of accident such as swallowing by infants and small children is very high You should implement safety measures so that Renesas products may not be easily detached from your products Renesas shall have no liability for damages arising out of such detachment This
34. with the interrupt handler In the emulator the contents of the SGR register are lost when the user program breaks Since the user program execution stops at constant intervals while the continuous trace is selected the contents of the SGR register will be lost 7 When continuous trace is used do not enable user interrupt by the INTERRUPT command during the emulator command wait state or user program execution 2 2 3 Notes on Using the JTAG Clock TCK Set the JTAG clock TCK frequency to lower than the frequency of the SH7750 or SH7750S peripheral module clock CKP 2 2 4 Notes on Setting the Breakpoint Dialog Box 1 2 When an odd address is set the next lowest even address is used A BREAKPOINT is accomplished by replacing instructions Accordingly it can be set only to the internal RAM area However aBREAKPOINT cannot be set to the following addresses e An address whose memory content is H 003B e An area other than the CSO to CS6 areas and the internal RAM area e An instruction in which Break Condition 4 is satisfied e A slot instruction of a delayed branch instruction In addition do not perform memory write BREAKPOINT or download even if the memory space can only be written by the MMU During step operation a BREAKPOINT is disabled Conditions set at Break Condition 3 are disabled when an instruction to which a BREAKPOINT has been set is executed Do not set a BREAKPOINT to an instruction in which Break
35. yed There are three kinds of branch instruction trace e Normal branch instruction trace Traces and displays the normal branch instructions The normal branch instructions are the BF BF S BT S BRA BRAF and JMP instructions To use this function select the Acquire normal branch instruction trace check box of the Branch trace page e Subroutine branch instruction trace Traces and displays the subroutine branch instructions The subroutine branch instructions are the BSR BSRF JSR and RTS instructions To use this function select the Acquire subroutine branch instruction trace check box of the Branch trace page e Exception branch instruction trace Traces and displays the exception branch instruction The exception branch instruction is the RTE instruction In addition all the exception and interrupt operations are traced To use this function select the Acquire exceptional branch instruction trace check box of the Branch trace page Continuous trace Acquires the trace information continuously This is called continuous trace For the branch instruction trace eight branch information can be repeatedly acquired a maximum of four times Select the Acquire continuous trace check box of the Branch trace page If continuous trace is selected realtime trace cannot be performed Internal I O trace Traces and displays the address and data that access the internal I O area To use this function sele
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