SMT368 User Manual - Sundance Multiprocessor Technology Ltd.
Contents
1. The result is a high speed de skewed clock driving the controller and the ZBT SRAM For more complete information please refer to the datasheet and to Xilinx application note xapp 136 Constraints File signal names ZZ CLKZBT are signals Zx CS2 N common to all memory components ZBT Bank name x21 2 ZBT signal Active level N Active low Figure 3 ZBT Constraints file signal names 4 1 7 Sundance High speed bus 4 x 60 pin connectors provide 4 x 40 I O connections between the FPGA and the outside world Note that there is no USER I O pins implemented for the SHB The SHB interface is available in the SMT6500 support package The FPGA I O banks hosting the SHB signals are powered using Vcco 3 3V Constraints File signal names SHBx CLK 0 Connector name x A B C or D Control signal Number corresponding to the Byte configuration where the control signal belongs 0 to 4 Figure 4 SHB Constraints file control signal names SHBx_Dy z Connector name x A B C or D Data bus D for Hw Y U or Z 0 15 Figure 5 SHB Constraints file data signal names 4 1 8 Sundance Low voltage differential signals Bus 1x 60 LVDS pairs I O connections between the FPGA and the outside world They allow interfacing to the Sundance mezzanine modules by implementing a SLB interface in the FPGA Sundance provides the interfaces to th2. ComPort Constraints file signal names EE 12 Figure 7 Schematics of the External Clock U O 13 Figure 8 CPLD state machune ENEE EEN EEN 14 Figure 9 PROM Mle e ME 16 Figure 10 ie geren EE 17 Figure 11 PROM GrOgramrming sss ss sese sss eee 18 Figure 12 Programming succeeded sss sss 19 Pgare ue Kee E 20 Piguire MPOB DOUlOm Vi E 21 Figure 15 Pinout J TAG header IPT 22 Figure 16 Pinout J TAG header TD 22 Figure 17 Boundary J TAG chain Xilinx iMPACT sss sese 23 Poar dos PIHOUL RR H OS ee 23 Figure 19 Pinout ELE ID OS E 8 ioeeseeiowsave dn sva reet td o Ub Ue roe ua ku VER aw a a Cnt UR Ux Deoa dios 23 Table 1 External Clock sped cdH secere T E 12 WEST 2 EE 13 Table 3 SW1 DIP switch for the configuration mode selection sss sss sees 14 Table 4 SW DIP switch for the configuration mode selection sss sss sees 15 Table 5 5W2 DIP switch Settings S di esedetar iov siccam iU D Nu ati eM miele iuum laces esc 21 Tact GHA 5 Last b ILL O 1 Introduction The SMT368 is a single size module based on a Virtex 4 FPGA XC4VSX35 and provides the following features e On board ZBTRAM memory e Four Sundance High speed Bus connections e One Sundance LVDS Bus connections allowing pairing with daughter modules e Four ComPort connections e Oneexternal clock I O e LEDs and user defined I O pins This variety of connectors and interfaces provides a wide range of development options for designers to explo
3. the 5V supplied through the TIM connectors The SMT368 requires an additional 3 3V power rail compatible and present on all the Sundance s carrier boards which must be provided by the two diagonally opposite mounting holes DC DC Converter An on board DC DC converter is used to supply power to the FPGA core Linear Voltage regulator Linear regulation is provided for the Vcco banks of the FPGA that are connected to the SLB when used in 2 5V mode LVDS 25 User Manual SMT368 Page 15 of 24 Last Edited 31 12 2008 13 53 00 4 3 3 Programming the Xilinx PROM DO NOT fit the SLB mezzanine before programming the PROM via J TAG It makes the J TAG fail It does not damage the board Plug the J TAG cable on J P1 The cable must be ordered from Sundance A standard Xilinx cable does not fit on J P1 Run Xilinx J TAG software Impact and connect to the target up to the stage showed on Figure 9 Proceed by selecting the PROM Browse to a PROM file of your choice filename mcs which is the configuration to be downloaded in the PROM Filename mcs should now be assigned to the PROM as per Figure 9 2 untitled Configuration Mode iMPACT File Edit View Mode Operations Output Help OBE 85 BAR ics CE cou Boundary 5can Slave Serial SelectMAP Desktop Configuration xcecla8 xcd ES ledstest mcs File File Figure 9 PROM file selection Right click on the PROM icon and select Program from
4. Unit Module Description Virtex 4 FPGA module User Manual for SMT368 Sundance Multiprocessor Technology Ltd Chiltern House Waterside Chesham Bucks HP5 IPS This document is the property of Sundance and may not be copied nor communicated to a third party without prior written permission Sundance Multiprocessor Technology Limited 2006 Certificate Number FM 55022 Revision History mee mem ate Tit 2 3 Corrected wrong sw1 positions for flash 03 04 07 E P configuration 2 4 Added section about programming the Xilinx 28 11 07 E P PROM 2 5 Added positioning and names of switches on 31 12 08 EP SW1 and SW2 in figure 13 PCB top view Table of Contents 1 Modu UON EE 6 2 Related D cumients sssceescicisncowesienasvee enstnnsienesesedesesnesdanatsesdecusensseseowsmesesecseds 6 ZA Ie ea Te cs H Ree re En D 22 Applicable R e et enn D 3 Acronyms Abbreviations and Definitions cccsccscsscsscesccsccsccsccsccsces 7 SJ JAOronyms ANG ADDPeVIGUODS eenegen ele egeh 7 OW MEN K lt 51 ee RN 7 4 Functional Description scccccccccccccccosoocccccecceccccccososoocccececcecccccossoooceeeceeee 8 LE PO PUO a BE 8 FL MOr OU E 8 4 12 Communication TOSOUICES cccccccessnnsssssssessccscccceccceeensasssssssssssceccesceceeneusansssssesseees 8 OR Ke PE eera E E E E A EE E 9 T GD RE 9 iw D PRON RE 9 AN NN HT 9 4 1 7 Sundance High speed bus ccccccccsccrsteresersesssssss
5. ated as per Figure 12 O untitled Configuration Mode iMPACT De Edit View Mode Operations Output Help Cab ld 4 Re in eut ae Ss CE E t i O e Boundary Scan Slave Serial SelectMAP Desktop Configuration xciazp xccl xcdvsxb ledstest mcs File File T Programming Succeeded INFO3MPACT 563 1 Please ensure proper connections as specified by the data book PROGRESS END End Operation Elapsed time 72 sec 4 For Help press F1 Configuration Mode Boundary Scan Parallel IV Figure 12 Programming succeeded 53 00 ea laaa alaa a CC ED ees AEPA E AAR AR ATARARATAR ARAR ARAR ARAR ARA H ZBTRAM _ l LE IHI IHI Ke v J SHB HHIHH TT JTAG PBRERRRRRRETRRRRE PSS PPP eee D External Glock VIew SHB PCB Top TTL I O Figure 13 TTE llun CPLD configuration SLB L Y b b Pob b bo b b b b amp PB b b b b b Ed C ar C RR 08 Y 38 98 9 4 3 MEC h ee vee ee e ee 6 6 6 6 6 6 66 8 e 9 Footprint 5 1 Top View 5 2 Bottom View Configuration PROM Figure 14 PCB Bottom view 6 Pinout 6 1 DIP switch SW2 The DIP switch SW2 is not used in the default firmware It is therefore connected to the CPLD for custom applications The following table describes the settings f
6. dissipation but a permanent airflow should always be maintained inbox to provide enough cooling for the system The fan header is a 2 pin 1 25mm and it is referenced J P2 7 Support Packages The SMT368 is supported by the SMT6500 software package available from SUNDANCE under Non Disclosure Agreement Please register on SUNDANCE Support Forum if you are not registered yet Then enter your company s forum to request the SMT6500 product Host side software to communicate with the SMT368 can be developed with the SMT6025 for Windows and the SMT6036 for Linux The SMT368 can be configured from a DSP module via a ComPort link The SMT6500 support package provide host interface to download the bitstream from the host and a library of software functions to run on the DSP See SMT6500 help file section Configuration library 8 Physical Properties EE 5V MTBF Power consumption ZBI 2 Watts CPLD 0 2Watts FPGA depending on the implemented design the power consumption can reach a maximum of 15Watts approx Sundance recommends you to analyse the FPGA power drawn by using Xilinx XPOWER before implementing your design in the FPGA This will tell you if you need to use the external power connector provided on our carrier boards 9 Safety This module presents no hazard to the user when in normal use 10 EMC This module is designed to operate from within an enclosed host system which is build to pro
7. e mezzanines supported on this module They allow interfacing to the outside world by implementing your own LVDS interface in the FPGA The FPGA I O banks hosting the SLB signals are powered using Vcco 2 5V 4 1 9 TIM Connectors TIM connectors provide 4 ComPorts to the FPGA ComPort 0 1 3 and 4 They allow interfacing to Sundance modules or to a host by implementing a ComPort interface in the FPGA The ComPort interface is available in the SMT6500 support package The FPGA I O banks hosting the ComPort signals are powered using Vcco 3 3V The TIM connectors also provide the power and ground rails reset and various control signals The references and the specification documents for these connectors are available from our website Constraints file signal names CxP STB N ComPort Connector name x 0 1 2 3 4 5 Control signal name STB STROBE RDY READY REQ REQUEST ACK ACKNOLEDGE Active level N Active low Figure 6 ComPort Constraints file signal names 4 1 10 DIP Switches Two four position DIP switches are connected to the CPLD SW1 provides control over the selection of the configuration bitstream source and SW2 can be used as I Os They are referenced SW1 and SW2 The SMT368 module provides an on board oscillator and an external clock I O e The on board oscillator provides a free running clock to the FPGA and CPLD The default is a 50MHz oscillator but other frequencies ca
8. enenenenccccccececcceccccccacccecenareresess 10 4 1 8 Sundance Low voltage differential signals Bus 11 SN Ter ND E eent erte 12 a NN ERT ee 12 ELE CIO ale SCIO e E PRETI DEN T REM En PE QOES PIDEN OS ME PA IU qu S creEe iUe EIE 12 TLZ ETD E 13 suo Nef O 13 42 Module DesceriDLiOE osassestta n teet EUR Debe eU a E EPIS AA EARS esu REP DAMES 13 ADA FPGA R 7515 Te irn E 13 42 E ln 14 oR TIM Ee enna EE 15 ALS Mterlace ee eigenen 15 43 1 Mechanical k enre e css ssesdssaseooasnssnsasacsosaransvansabooseisbunndssaebocsssasssasaesovasensesssebooccisness 15 AsO E ee eher e 15 4 3 3 Programming the Xilinx DROM sse 16 5 erte 20 lt OD VOW E 20 I2 POU E 21 6 Eege 21 2 ME E SiG EE 21 6 2 SHB Header 21 SD TAG lt Te T NT E E 21 DA TOSE A NT TS 23 DS TP EE 23 7 SUDDOEE Packages essrsrrrosireri tirir anna E EEE EEEE OE 23 8 Physical Properes iiid eder EIE IERI PEE RAE URS EKTEUFU EID REESE E AS e EI MMADHPO ONE 24 9 e lplngee T n 24 1 EMO p 24 Table of Figures and Tables Pouro eD EDO ieor E EE E E E EEO 8 Figure 2 FPGA connections to Bank1 Of ZBLL EE 9 Figure 3 ZBT Constraints file signal name 10 Figure 4 SHB Constraints file control signal names EE 10 Figure 5 SHB Constraints file data signal names EE 11 Figure 6
9. from the Knowledge Base in the Support forum Different schemes are available to provide a maximum flexibility in systems where the SMT368 is involved The FPGA can be configured in three different ways e Using the ComPort 3 CP 3 orComPort 0 CD 01 to provide the bitstream e Using the on board J TAG header J P1 and the J TAG programming tools e Using the on board Xilinx PROM The following table describes the settings for the jumper SW1 according to the various FPGA configuration modes From PROM Table 3 SW1 DIP switch for the configuration mode selection 4 2 2 FPGA Reset Scheme The CPLD is connected to the TIM global reset signal provided to the SMT3668 via its primary TIM connector P1 pin 30 The CPLD provides another signal called FPGAResetn that offers a better Reset control over the FPGA At power up or on reception of a low TIM global reset pulse the CPLD drives the FPGAResetn signal low and it keeps it low When the ENDKEY has been received the CPLD drives the FPGAResetn high Sundance recommends you to use the FPGAResetn signal for the Global Reset signal of your FPGA designs In this manner you can control your FPGA design Reset activity and you will also avoid possible conflicts on the ComPort_ 3 if your FPGA design implements it The Reset control is operated by the CPLD line FPGAResetn TIM Reset or TIM Config FPGA Configured and STARTKEY Received ENDKEY Rece
10. ging prototyping and development of your FPGA design em l 4 1 5 PROM Xilinx Flash PROM XCF32 Device package VOG48 This device contains 128 macro cells This device is programmed via J TAG The PROM automatically configures the FPGA at power up or reset It uses parallel FPGA configuration interface performing at up to 33MHz and it has a built in data decompressor compatible with the Xilinx advanced compression technology 4 436 ZBIRAM 0 Samsung NtRAM Device part number K7N32180 1M PC20 Up to 8MB of pipeline ZBT memory is provided with direct access to the FPGA DQ 17 0 A 20 0 Fe BEA BEB CS1n CKE ZZIADVILBONEN OE CLK output CLK FB input Figure 2 FPGA connections to Bank1 of ZBT The ZBTRAM is designed to sustain 100 bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write or vice versa The device is well suited for SDR applications that experience frequent bus turnarounds needs to operate on small data chunks especially one word chunks and needs to operate at higher frequencies than permitted by the flow through version The memory is split in 2x18 bit wide banks and is expected to be clocked at 166MHz with a speed grade 16 The 2 banks present independent address data and control busses To ensure high performance the FPGA design should generate de skewed controller and board level clocks using the clock feedback signal provided
11. ived FPGA Configured and ENDKEY Received Figure 8 CPLD state machine Note The Reset level on the SMT368 is active low 4 2 3 TIM config The TIM config is a special reset feature This signal comes from the TTM connector P1 pin 74 and it is available to the CPLD TIM Config is driven by another module on the same carrier board for instance from a DSP module running an application see the Chapter Config amp NMI DSP lines in the SMT6400 It can be enabled with the DIP swith SW1 Table 4 SW1 DIP switch for the configuration mode selection 4 3 Interface Description 4 3 1 Mechanical Interface This module conforms to the TIM standard Texas Instrument Module See TI TIM specification amp user s quide for single width modules It sits on a carrier board The carrier board provides power Ground communication links ComPort links between all the modules fitted and a pathway to the HOST for a non stand alone system The SMT368 requires an additional 3 3V power supply as present on all Sundance TIM carrier boards which must be provided by the two diagonally opposite mounting holes 4 3 2 Electrical Interface Do NOT connect any external TTL 5V signals to the SMT368 I Os as the FPGA is NOT 5V compliant This implies that the ComPorts and global bus lines of the carrier board MUST be LVTTL and that any device driving signals on the SHB connectors must drive at LVTTL 3 3V This module must have
12. module is conformed to the Texas Instruments Module standard for single size modules It sits on a carrier board that provides electrical connections power ground and communication links ComPort between all the modules fitted It is also a pathway to the host for a non stand alone system 4 1 Block Diagram Figure 1 Block Diagram 4 1 1 Major features e Blod Xilinx Virtex 4 XCAVSX35 configuration and reset schemes e Block2 ZBTRAM memory e Block3 I O connectors for general purpose or dedicated interfaces e Block Clocking scheme s BDO LEDs for development in use monitoring and general purpose use Please refer to the Sundance help file for the general description of the Sundance s boards from the TIM to the carrier board and the external world interfacing Please refer to the Sundance SMT6400 help file for the description of the communication resources provided by Sundance and available onto the SMT368 Page 8 of 24 Last Edited 31 12 2008 13 53 00 4 1 3 FPGA Xilinx Virtex 4 XC4VSX35 Device package FFG668 This device has 448 I O pin BGA package with a 10 speed grade It contains up to 34 560 logic cells and 192 XtremeDSP Slices 4 1 4 CPLD Xilinx CoolRunner IT XC2C128 Device package 6VQG100C This device has 100 I O pin QFP package with a 6 speed grade It provides the option to configure the FPGA via ComPort 3 orComPort_0 This is ideal for fast in systems debug
13. n be provided upon request to Sundance Note Please ask your Sundance technical or sale person when ordering if you need other frequencies e An external clock input output J 2 is provided directly to the FPGA via a 50 ohms MMBxX coax connector aan ae ov ow 38V Minimumvottage ON 2w 24V Freauen The frequency limitations are the ones of the ec FPGA Referto the Xilinx s user guide Table 1 External Clock specification User Manual SMT368 Page120f24 Last Edited 31 12 2008 13 53 00 J2 ib EXTCLK 2 LU SMB Figure 7 Schematics of the External Clock I O Constraints file signal names BOARDCLK On board oscillator input to the FPGA pin AF10 EXT CLK External Clock input to the FPGA pin AF11 IO LAP GC LC 4 There are six LEDs on the SMT368 e Four LEDs are connected to the FPGA and they are available as I Os es ms Ds Table 2 LEDs connections e One LED D1 is connected to the DONE pin of the FPGA to show that the FPGA is configured e One LED D2 is connected to a I O pin 99 of the CPLD There are four TTL I Os that are directly connected to the FPGA They are connected to the pin socket header J P3 4 2 Module Description 4 2 1 FPGA Configuration The general FPGA configuration is described in the SMT6500 help file Please refer to the chapter Configuring the FPGA section FPGA type TIM To illustrate the FPGA configuration please refer to the animated slideshow
14. or the positions of the SW2 Table 5 SW2 DIP switch settings 6 2 SHB Header The SHB connectors support LVTTL standard only They are referenced SHBA SHBB SHBC and SHBD 6 3 J TAG Header The J TAG header is a 2mm pitch pin socket and it is referenced J P1 It is compliant with the Xilinx Parallel cable IV All devices from the Block this J TAG header FPGA CPLD PROM are chained and they are accessible via Figure 16 Pinout J TAG header J P1 C untitled Configuration Mode iMPACT File Edit View Mode Operations Output Help Dek trega Boundary Scan Slave Serial Right click device to select operations xc2c128 File done PROGRESS END End Operation Elapsedtime 1 sec For Help press F1 FH seo gw SelectMAP Desktop Configuration xc4vsx35 File Boundary Scan Chain Contents Summary 3 There were 3 devices detected in the boundary scan chain JJ iMPACT wil now direct you to associate a programming or BSDL file with each device starting with the first OK Boundary Scan Parallel IV Configuration Mode Figure 17 Boundary J TAG chain Xilinx iMPACT 6 4 I Os Header The TTL I Os header is a 2mm pitch pin socket and it is referenced J P3 Figure 18 Pinout TTL I Os J P3 JP3 V33 D Figure 19 Pinout TTL I Os JP3 6 5 Fan Header A fan coupled with a heat sink can be mounted on the FPGA to provide heat
15. re the capabilities of the comprehensive family of Sundance modules and carrier boards 2 Related Documents 2 1 Referenced Documents Sundance help file Sundance SHB specification document Sundance SDB specification document Sundance SLB specification document Sundance SDL specification document TI TIM specification amp user s quide Sundance s documentation and user guides 2 2 Applicable Documents Texas Instruments specification amp user s guide ComPort specification document Refer to Chapter 12 Xilinx PROM XCF32PVOG48C SAMSUNG ZBTRAM datasheet XC2C128 CoolRunner II CPLD Virtex 4 user quide Xilinx Xapp136 3 Acronyms Abbreviations and Definitions 3 1 Acronyms and Abbreviations TIM DSP FPGA NtRAM ZBIRAM CP SDB SHB SLB 3 2 Definitions DSP Module Texas Instruments Module Digital Signal Processor Field Programmable Gate Array No Turnaround Random Access Memory Zero Bus Turnaround Random Access Memory ComPort Communication interface Sundance Digital Bus Communication interface Sundance High Speed Bus Communication interface Sundance LVDS Bus Communication interface A TIM module hosting a TI DSP and a Xilinx FPGA FPGA only Module A TIM with no on board DSP where the FPGA provides all functionality Firmware A proprietary FPGA design providing some sort of functionality sundance Firmware is the firmware running into a FPGA of a DSP module 4 Functional Description The
16. the menu Next select the same options as per Figure 10 and click O K on the 2 dialog windows Beware to leave unchecked verify as it takes ages to verify and to TICK LoadFPGA and Parallel Mode boxes The PROM option will not work if these latter 2 boxes are not ticked zi untitled Configuration Mode iMPACT File Edt View Mode Operations Output Help DG EH Apr e EE Xilinx iMPACT Boundary Scan Sla eue A Accurate programming is guaranteed only when followed by a successful verify Iw Erase Before Programming Verify OK IR Read Protect Write Protect RS FROM ledstestimcs virtex Il re Iw Load FPGA Secure Made Parallel Mode Program Key Use D4 force PROM CoolRunnerll Usercode 8 Hex Digits FFFFFFFF XPLA UES Enter up to 13 characters For Help press F1 Configuration Mode Parallel IV Figure 10 Program Options 53 00 ER untitled Configuration Mode iMPACT Operations Qutput Help DSU tenax s OE SEO ge Boundary 5can Slave Serial SelectMAP Desktop Configuration File Edit View Mode Oper xct3zp xcecl cH xcdvsx3b ledstestmcs File File Operation Status Executing command 649x679 Programming Revisione 0 done HI ontiguration Mode Bo Indary Scan Figure 11 PROM programming It can take more than 2 minutes 53 00 A successful programming is indic
17. vide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the output cables Short circuiting any output to ground does not cause the host PC system to lock up or reboot
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