HMS99C51 HMS99C52
Contents
1. Bit 7 6 5 4 3 2 1 0 SMOD 1 GFO PDE IDLE TF1 TR1 TFO TRO IE1 IT1 IEO ITO GATE C T M1 MT GATE C T M1 MO 5 5 2 SMO SM1 SM2 REN TB8 RB8 TI RI EA 2 ES ET1 EX1 ETO PT2 PS PT1 PX1 PTO PXO this bit location is reserved SFR bit and byte addressable SFR not bit addressable Jan 2003 Ver 1 0 HMS99C5X Series Table 3 Contents of SFRs SFRs in Numeric Order cont d Address Register Bit 7 6 5 4 3 2 1 0 C8H T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C T2 CP RL2 C9H T2MOD 1 5 3 T20Et DCEN CAH RC2L CBH RC2H CCH TL2 CDH TH2 DOH PSW CY AC FO RS1 RSO OV 1 FOH B T indicates resident in the HMS99C52 not in HMS99C51 8EH AO AO ALE Signal Disable bit 0 Enable ALE Signal Generated ALE Signal 1 Disable ALE Signal Not Generated ALE Signal 8FH x2 X2 CPU amp Peripheral Clock Select bit 0 Select 12 clock periods per machine cycle 1 Select 6 clock periods per machine cycle t C9H 2 T2OE Timer2 Output Enable bit 0 Disable Timer2 Output 1 Enable Timer2 Output2. SFR bit and byte addressable SFR not bit addressable this bit location is reserved Jan 2003 Ver 1 0 15 hynix HMS99C5X Series X2 MODE The HMS99C5X core needs only 6 clock periods per machine cycle This feature called X2 provides the fol lowing advantages Divide frequency crystals by 2 cheaper crystals while keeping same CPU power Save power consumption while keeping same CPU power oscillator power saving Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes Increase CPU power by 2 while keeping same crystal frequency In order to keep the original C51 compatibility a divider by 2 is inserted between the XTALI signal and the main clock input of the core phase generator This divider may be disabled by software X2 Mode Description The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals This allows any cyclic ratio to be accepted on XTAL I input In X2 mode as this divider is bypassed the signals on XTAL must have a cyclic ratio between 40 to 60 Figure 2 shows the clock generation block diagram X2 bit is validated on XTAL 1 2 rising edge to avoid glitches when switching from X2 to STD mode Figure 3 shows the mode switching waveforms XTAL1 fosc 2 0 State Machine 6 clokc cyles CPU control 1 2
3. CKCON Register Figure 2 Clock Generation Diagram The X2 bit in the CKCON register allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa At reset the standard speed is activated STD mode Setting this bit activates the X2 feature X2 mode CAUTION In order to prevent any incorrect operation while operating in X2 mode user must be aware that all peripherals using clock frequency as time reference UART timers will have their time reference divided by two For ex ample a free running timer generating an interrupt every 30 ms will then generate an interrupt every 15 ms UART with 2400 baud rate will have 4800 baud rate 16 Jan 2003 Ver 1 0 HMS99C5X Series ve XTAL1 2 B A 27772 0 CPU Clock r STD Mode STD Mode lt 2 Figure 3 Mode Swithcing Waveforms Jan 2003 Ver 1 0 17 HMS99C5X Series TIMER COUNTER 0 AND 1 Timer Counter 0 and 1 can be used in four operating modes as listed in Table 4 Table 4 Timer Counter 0 and 1 Operating Modes TMOD Input Clock Mode Description C T M1 MO internal external Max 0 8 bit timer counter with a X X 0 0 fosc 12x32 fosc 24x32 divide by 32 prescaler 1 16 bit timer counter X X 0 1 fosc 12 fosc 24 2 8 bit timer counter with X X 1 0 fosc 12 fosc 24 8 bit auto reload 3 Tim
4. Interrupt Unit Port 3 Pot3 gii Digit VO Serial Channel Figure 1 Block Diagram of the HMS99C5X series Jan 2003 Ver 1 0 9 hynix HMS99C5X Series CPU The HMS99C5X series is efficient both as a controller and as an arithmetic processor It has extensive facilities for binary and BCD arithmetic and excels in its bit handling capabilities Efficient use of program memory re sults from an instruction set consisting of 44 one byte 41 two byte and 15 three byte instructions With a 12 MHz crystal 58 of the instructions are executed in 1 0us 40MHz 300ns Special Function Register PSW MSB LSB Bit No 7 6 5 4 3 2 1 0 Add DO CY AC FO RS1 RS0 OV F1 PSW Bit Function Carry Flag AC Auxiliary Carry Flag for BCD operations General Purpose Flag RS1 RSO Register Bank select control bits 0 0 Bank 0 selected data address 00g 07H 0 1 Bank 1 selected data address 08 OFH 1 0 Bank 2 selected data address 10 17 1 1 Bank 3 selected data address 18 1FH OV Overflow Flag F1 General Purpose Flag P Parity Flag Set cleared by hardware each instruction cycle to indicate odd even number of one bits in the accumulator i e even parity Reset value of PSW is 00 10 Jan 2003 Ver 1 0 HMS99C5X Series SPECIAL FUNCTION REGISTERS All registers excep
5. 40 C to 85 Limit Values Un e Parameter Symbol Test Conditions Min Max it Input low voltage 5 except EA RESET VIL 0 5 0 2Vcc 0 1 V Vcc 5 5V Input low voltage EA 0 5 0 2Vcc 0 1 V 5 5 Input low voltage RESET 2 0 5 0 2 0 1 V 5 5V Input high voltage except 0 2Vcc _ XTAL1 EA RESET 0 9 5 j V 4 5V Input high voltage to XTAL1 0 7Vcc Vcc 0 5 V Vcc 4 5V Input high voltage to EA _ RESET Vin2 0 6Vcc Vcc 0 5 V 4 5V Output low voltage 1 ports 1 2 3 VoL 0 45 V 5 5V loc 1 6mA Output low voltage _ _ E 1 port 0 ALE PSEN 0 45 V 5 5V loi 3 2 Output high voltage VoH 2 4 _ V 4 5V ports 1 2 3 0 9Vcc 4 5V 10 Output high voltage 1 2 4 Vcc 4 5V 800 2 port 0 in external bus 0 9Vcc V 4 5V 80 2 mode ALE PSEN Logic 0 input current _ ports 1 2 3 lit 10 65 HA 0 45V Logical 1 to 0 transition cur 4 _ rent ports 1 2 3 ITL 65 650 uA V 2 0 Input leakage current P port 0 EA lu 1 0 45 lt VN lt Cio 1MHz Pin capacitance 10 pF Ta 25 Power supply current Active mode 4MHz 9 lcc 8 mA 5V 9 Idle mode 4MHz 4 4 A 5 9 Active
6. P32 __ IEO o eo e 1 TCON 1 gt gt 0 0 0 0 D gt P33 IE1 oo eo INT1 aA x TCON 3 IT1 EX1 EA PX1 TCON 2 IE 2 7 IP 2 gt Low level triggered Falling edge triggered Figure 5 Interrupt Request Sources Jan 2003 Ver 1 0 21 hynix Table 8 Interrupt Sources and their Corresponding Interrupt Vectors 599 5 Series Source Request Flags Vectors Vector Address RESET RESET 0000H IEO External interrupt 0 0003H TFO Timer 0 interrupt 000BH IE1 External interrupt 1 0013H TF1 Timer 1 interrupt 001BH RI Serial port interrupt 0023H TF2 EXF2 Timer 2 interrupt 002BH A low priority interrupt can itself be interrupted by a high priority interrupt but not by another low priority in terrupt A high priority interrupt cannot be interrupted by any other interrupt source If two requests of different priority level are received simultaneously the request of higher priority is serviced If requests of the same priority are received simultaneously an internal polling sequence determines which re quest is serviced Thus within each priority level there is a second priority structure determined by the polling sequence as shown in Table 9 Table 9 Interrupt Priority Within Level Interrupt Source Priority External Interrupt 0 IEO High Timer 0 Interrupt TFO 17 External Inte
7. 2003 Ver 1 0 HMS99C5X Series Logic Symbol Vcc Vss XTAL1 Boat or 2 8 bit Digital Port 1 RESET 8 bit Digital I O Port 2 m 8 bit Digital EA Vpp ALE PROG Port 3 ph 8 bit Digital PSEN Jan 2003 Ver 1 0 hynix HMS99C5X Series PIN DEFINITIONS AND FUNCTIONS Pin Number TARA Symbol picc warp Output 44 40 44 1 0 1 7 2 9 1 8 40 44 Porti 1 3 Port 1 is an 8 bit bidirectional port with internal pull ups Port 1 pins that have 1s written to them are pulled high by the internal pull up resistors and can be used as inputs As inputs port 1 pins that are externally pulled low will source current because of the pulls ups li in the DC characteristics Pins P1 0 and P1 1 also Porti also receives the low order address byte during program memory verification Port also serves alternate functions of Timer 2 2 1 40 P1 0 T2 Timer counter 2 external count input 3 2 41 1 1 T2EX Timer counter 2 trigger input In HMS99C52 2 1 40 P1 0 T2 Clock Timer counter 2 external count input Clock Out P3 0 P3 7 11 10 17 5 7 13 Port 3 13 19 Port 3 is an 8 bit bidirectional port with internal pull ups Port 3 pins that have 1s written to them are pulled high by the internal pull up resistors and can be used as inputs As inputs port 3 pins that are externally pull
8. 599 5 Series Symbol Pin Number PLCC PDIP MQFP 44 40 44 Input Output Function ALE PROG 33 30 27 The Address Latch Enable Program pulse Output pulse for latching the low byte of the address during an access to external memory In normal operation ALE is emitted at a constant rate of 1 6 the oscillator frequency and can be used for external timing or clocking Note that one ALE pulse is skipped during each access to external data memory This pin is also the program pulse input PROG during EPROM programming If desired ALE operation can be disabled by setting bit O of SFR location 8Ey With this bit set the pin is weakly pulled high The ALE disable feature will be terminated by reset Setting the ALE disable bit has no affect if the microcontroller is in external execution mode EA Vpp 35 31 29 External Access Enable Program Supply Voltage EA must be external held low to enable the device to fetch code from external program memory locations 00004 to FFFFH If EA is held high the device executes from internal program memory unless the program counter contains an address greater than its internal memory size This pin also receives the 12 75V programming supply voltage Vpp during EPROM programming Note however that if any of the Lock bits are programmed EA will be internally latched on reset P0 0 P0 7 36 43 32 39 30 37 Port 0 Port 0 is an 8 bi
9. 0 1 AC Inputs during testing are driven at Vcc 0 5V for logic 1 and 0 45V for a logic 0 Timing measurements are made a Viumin for a logic 1 and Vii max for a logic 0 0 45V Figure 9 AC Testing Input Output Waveforms Vioap 0 1 Vou 0 1 0 2Vcc 0 1 VLOAD Timing Reference Points Vioap 0 1 Vor 0 1 For timing purposes a port pin is no longer floating when a 100mV change from load voltage occurs and begins to float when 100mV change from the loaded level occurs lou gt 20mA Figure 10 Float Waveforms 0 2 Vcc 0 1 0 45V tCHCL tCLCH Figure 11 External Clock Cycle Jan 2003 1 0 35 hynix OSCILLATOR CIRCUIT CRYSTAL OSCILLATOR MODE C2 XTAL2 P LCC 44 Pin 20 P DIP 40 Pin 18 M QFP 44 Pin 14 599 5 Series DRIVING FROM EXTERNAL SOURCE XTAL2 P LCC 44 Pin 20 P DIP 40 Pin 18 M QFP 44 Pin 14 External Oscillator XTAL1 Signal XTAL1 P LCC 44 Pin 21 P LCC 44 Pin 21 P DIP 40 Pin 19 P DIP 40 Pin 19 M QFP 44 Pin 15 M QFP 44 Pin 15 a 4 C1 C2 30pF 10pF for Crystals For Ceramic Resonators contact resonator manufacturer Figure 12 Recommended Oscillator Circuits Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator Since each crystal and ceramic resonator have their own characteristics the user s
10. Max ALE pulse width tLHLL 43 2 40 ns Address setup to ALE tAVLL 17 25 ns Address hold after ALE 17 5 25 5 ns ALE low to valid instruction in 80 4tcLCL 87 ns ALE to PSEN tLLPL 22 20 ns PSEN pulse width tPLPH 95 30 ns PSEN to valid instruction in tPLIV 60 65 ns Input instruction hold after PSEN 0 0 ns Input instruction float after PSEN tpxizt 32 10 ns Address valid after PSEN tpxay t 37 5 ns Address to valid instruction in taviv 148 60 ns Address float to PSEN tAZPL 0 0 ns t Interfacing the HMS99C5X series to devices with float times up to 35 ns is permissible This limited bus contention will not cause any damage to port 0 Drivers Jan 2003 Ver 1 0 29 hynix HMS99C5X Series AC Characteristics for HMS99C5X series 24MHz External Data Memory Characteristics 1 24 MHz Oscillator n 120019 arameter Symbol Unit Min Max Min Max RD pulse width tRLRH 180 70 5 5 WR pulse width twLWH 180 70 5 Address hold after ALE tLLAX2 15 27 ns RD to valid data in tRLDV 118 90 ns Data hold after RD tRHDX 0 0 ns Data float after RD tRHDZ 63 2tcLcL 20 ns ALE to valid data in tLLDv 200 8tcLcL
11. RL2 TR2 EXEN2 T2EX internal Prot 16 bit Auto 0 0 1 0 0 X reload upon over fosc 12 Reload flow fosc 24 0 0 1 0 1 reload trigger fall ing edge 0 0 1 1 X 0 Down counting 0 1 1 X 1 Up counting 16 bit 0 1 1 X 0 X 16 bit Timer Coun fosc 12 Max Capture ter only up count fosc 24 ing 0 1 1 X 1 4 capture TH2 TL2 RC2H RC2L Baud Rate 1 X 1 X 0 X overflow fosc 12 Generator interrupt request fosc 24 TF2 1 X 1 X 1 extra external inter rupt Timer 2 Off X X 0 X X X 2 stops Note falling edge Jan 2003 Ver 1 0 19 hynix SERIAL INTERFACE USART The serial port is full duplex and can operate in four modes one synchronous mode three asynchronous modes as illustrated in Table 6 The possible baud rates can be calculated using the formulas given in Table 7 Table 6 USART Operating Modes 599 5 Series SCON Mode Baudrate Description SMO SM1 fosc Serial data enters and exits through RxD 0 0 0 712 TxD outputs the shift clock 8 bit are transmit ted received LSB first 8 bit UART 1 0 1 Timer 1 2 overflow rate 10 bits are transmitted through TxD or received RxD B foscor fosc 9 bit UART 32 64 11 bits are transmitted TxD or received RxD 9 bit UART 3 Like mode 2 except the variable baud rate Table 7 Formulas f
12. oscillator to restart and stabilize similar to power on reset Jan 2003 Ver 1 0 23 hynix HMS99C5X Series ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Ambient temperature under bias 40 to 85 Storage temperat re dede tete eut gea dm esee 65 to 150 Voltage on pins with respect to ground 0 5V to 6 5V Voltage on any pin with respect to ground 0 5V to 0 5V Input current on any pin during overload condition sss 10mA to 10mA Absolute sum of all input currents during overload condition esee I100mAI Power dissipation eee tete toon Cre RU ERE RETRO ERU RE etie eR 200mW Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage of the de vice This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rat ing conditions for longer periods may affect device reliability During overload conditions gt or Vin lt Vss the Voltage on pins with respect to ground Vss must not exceed the values defined by the absolute maxi mum ratings 24 Jan 2003 Ver 1 0 HMS99C5X Series DC Characteristics DC Characteristics for HMS99C51 52 5 10 1590 Vss 0V
13. reserved XXH 2 EBH reserved XXH 2 E4H reserved XXH 2 ECH reserved XXH 2 E5H reserved XXH 2 EDH reserved XXH 2 E6H reserved XXH 2 EEH reserved XXH 2 E7H reserved XXH 2 EFH reserved XXH 2 FOH B 00H F8H reserved XXH2 F1H reserved XXH 2 F9H reserved XXH2 F2H reserved XXH FAH reserved XXH2 F3H reserved XXH 2 FBH reserved XXH 2 F4H reserved XXH 2 FCH reserved XXH 2 F5H reserved XXH 2 FDH reserved XXH 2 F6H reserved XXH 2 FEH reserved XXH 2 F7H reserved XXH 2 FFH reserved XXH 2 1 2 3 4 These Registers are in the HMS99C52 only Bit addressable Special Function Register X means that the value is indeterminate and the location is reserved Bit addressable Special Function Register 12 Jan 2003 Ver 1 0 HMS99C5X Series Table 2 Special Function Registers Functional Blocks Contents Block Symbol Name Address after Reset CPU ACC Accumulator EOH 1 00H B B Register 1 00H DPH Data Pointer High Byte 83H 00H DPL Data Pointer Low Byte 82H 00H PSW Program Status Word Register DOH 1 00H SP Stack Pointer 81H 07H Interrupt System IE Interrupt Enable Register A8H 1 0X000000B 2 IP Interrupt Priority Register B8H 1 XX000000B 2 Ports PO Port 0 80H 1 FFH P1 Port 1 90H 1 FFH P2 Port 2 1 Port 3 BOH 1 FFH Serial Channels Power Control Register 87H OXXX0000B 2 SBUF Serial Channel Buf
14. 1 hynix PIN CONFIGURATION 44 PLCC Pin Configuration top view 599 5 Series N C Do not connect P0 4 AD4 P0 5 AD5 P0 6 AD6 P0 7 AD7 c pos 2298 INDEX 22242225 08 ooro fFF P15 7 39 P1 6 38 P1 7 37 RESET 10 36 RxD P3 0 35 12 34 P3 1 13 33 INTO P3 2 14 32 INTT P3 3 15 31 TO P3 4 16 30 T1 P3 5 17 29 8s 90 UD EN aa Vat Ele vau lg EA Vpp ALE PROG PSEN 2 7 A15 2 6 A14 2 5 A13 Jan 2003 Ver 1 0 HMS99C5X Series 40 PDIP Pin Configuration top view 2 P1 0 2 P1 1 1 2 P1 3 P1 4 P1 5 P1 6 P1 7 RESET RxD P3 0 TxD P3 1 INTO 2 P3 3 P3 4 1 5 WR P3 6 RD P3 7 XTAL2 XTAL1 Vss Y oc cn o o n nn nan 0 gt 40 39 38 37 36 3
15. 133 ns Address to valid data in tAVDV 220 155 ns ALE to WR or RD tLLWL 75 175 50 50 ns Address valid to WR or RD tAVWL 67 4 1 97 ns WR or RD high to ALE high 17 67 25 25 ns Data valid to WR transition tavwx 5 37 ns Data setup before WR tovwH 170 122 ns Data hold after WR twHox 15 27 ns Address float after RD tRLAZ 0 0 ns Advance Information 24MHz External Clock Drive Variable Oscillator Parameter Symbol Freq 3 5 to 24MHz Unit Min Max Oscillator period tcLcL 41 7 285 7 ns High time 12 ns Low time 12 ns Rise time tcLCH 1 12 ns Fall time tCHCL 5 12 ns 30 Jan 2003 Ver 1 0 HMS99C5X Series AC Characteristics for HMS99C5X series 40MHz version 5V 1096 15 Vss TA 40 C to 85 for port 0 ALE and PSEN outputs 100pF for all other outputs 80 External Program Memory Characteristics Variable Oscillator Parameter Symbol TOME OSEE T tcLeL 3 5 to 40MHz Unit Min Max Min Max ALE pulse width tLHLL 40 2 20 ns Address setup to ALE tAVLL 10 20 ns Address hold after ALE tLLAX 10 20 ns ALE low to valid instruction in 56 4tcLcL 65 ns ALE to PSEN t
16. 20 20 ns Data valid to WR transition tavwx 5 25 ns Data setup before WR tovwH 142 70 ns Data hold after WR twHax 10 20 ns Address float after RD tRLAZ 0 0 ns Advance Information 40MHz External Clock Drive Variable Oscillator Parameter Symbol Freq 3 5 to 40MHz Unit Min Max Oscillator period tcLcL 30 3 285 7 ns High time 11 5 ns Low time tcLCX 11 5 tcLcL tcHcx ns Rise time tcLCH 1 5 ns Fall time tCHCL 5 ns 32 Jan 2003 Ver 1 0 HMS99C5X Series lt lt tLHLL gt ALE 4 lt tavit gt lt F3 tv PSEN tAZPL tLLAX gt PORT 0 r taviv Figure 6 External Program Memory Read Cycle Jan 2003 Ver 1 0 33 hynix HMS99C5X Series ALE PSEN RD t tRHDZ DATA IN 0 7 from PCL INSTR IN PORT 0 T 4 tayw 2 P2 0 P2 7 or A8 A15 from DPH A8 A15 from PCH Figure 7 External Data Memory Read Cycle ALE tLLWL gt lt 0 4 INSTR IN lt lt PORT 2 P2 0 P2 7 or A8 A15 from DPH A8 A15 from Figure 8 External Data Memory Write Cycle 34 Jan 2003 Ver 1 0 HMS99C5X Series Vcc 0 5V 0 2Vcc 0 9 b Test Points 0 2Vcc
17. 5 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc P0 0 ADO P0 1 AD1 2 AD2 P0 3 AD3 P0 4 AD4 5 AD5 6 AD6 P0 7 AD7 EA ALE PROG PSEN P2 7 A15 P2 6 A14 P2 5 A13 P2 4 A12 P2 3 A11 P2 2 A10 P2 1 A9 2 0 8 Jan 2003 Ver 1 0 hynix 44 MQFP Pin Configuration top view HMS99C5X Series N C Do not connect P1 5 P1 6 P1 7 RESET RxD P3 0 N C TxD P3 1 INTO 2 P3 3 TO P3 4 T1 P3 5 1 4 P1 1 2 P1 0 T2 N C Voc P0 0 ADO P P1 3 P1 2 1 AD1 P0 2 AD2 P0 3 AD3 43 42 41 40 39 38 37 36 35 34 03 AON Ee o 12 13 14 15 16 17 18 19 20 22 33 32 31 30 29 28 27 26 25 24 23 P0 4 4 P0 5 AD5 P0 6 AD6 P0 7 AD7 WR P3 6 RD P3 7 XTAL2 XTAL1 Vss N C P2 0 A8 P2 1 A9 P2 2 A10 P2 3 A11 P2 4 A12 EA Vpp N C ALE PROG PSEN P2 7 A15 P2 6 A14 2 5 A13 Jan
18. ALE tLLAX2 53 30 ns RD to valid data in tRLDV 252 165 ns Data hold after RD tRHDX 0 0 ns Data float after RD tRHDZ 97 2 1 1 70 ns ALE to valid data in tLLDv 517 8tcLcL 150 ns Address to valid data in tAVDV 585 165 ns ALE to WR or RD tLLWL 200 300 50 50 ns Address valid to WR or RD tAVWL 203 4tcLcL 130 ns WR or RD high to ALE high 43 123 40 1 1 1 40 ns Data valid to WR transition tavwx 33 50 ns Data setup before WR tovwH 433 150 ns Data hold after WR twHax 33 50 ns Address float after RD tRLAZ 0 0 ns Advance Information 12MHz External Clock Drive Variable Oscillator Parameter Symbol Freq 3 5 to 12MHz Unit Min Max Oscillator period Vcc 5V tCLCL 83 3 285 7 ns High time 20 ns Low time 20 ns Rise time tcLCH 20 ns Fall time tCHCL 20 ns 28 Jan 2003 Ver 1 0 HMS99C5X Series AC Characteristics for HMS99C5X series 24MHz version 5V 1096 71596 Vss 40 C to 85 C for port 0 ALE and PSEN outputs 100pF for all other outputs 80 External Program Memory Characteristics Variable Oscillator Parameter Symbol 1 3 5 to 24 2 Unit Min Max Min
19. HYNIX SEMICONDUCTOR INC 8 BIT SINGLE CHIP MICROCONTROLLERS 599 51 599 52 User s Manual Ver 1 0 Semiconductor Version 1 0 Published by MCU Application Team 2002 Hynix semiconductor right reserved Additional information of this manual may be served by Hynix semiconductor offices in Korea or Distributors and Representatives listed at address directory Hynix semiconductor reserves the right to make changes to any information here in at any time without notice The information diagrams and other data in this manual are correct and reliable however Hynix semiconduc tor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual Device Naming Structure HMS99X5X XX 2 9 gt 8 Package Type NE Blank 40PDIP 8 9 PL 44PLCC 5 4 44 o 3 ROM size I 1 4k bytes 2 8k bytes Operating Voltage 4 5 5 5V HMS99C5X Series Selection Guide ROM size bytes Operating RAM size Device Name Operating Voltage V FLASH bytes Frequency MHz 45 55 4 128 599 51 40 8K 256 HMS99C52 40 HMS99C5X Series HMS99C51 Fully compatible to standard MCS 51 microcontroller Wide operating frequency up to 40MHz for more detail see HMS99C5X Series Selection Guide X2 Speed Improvement capability X2 Mode 6 clock
20. LLPL 15 15 ns PSEN pulse width tPLPH 80 20 ns PSEN to valid instruction in tPLIV 35 55 ns Input instruction hold after PSEN 0 0 ns Input instruction float after PSEN tpxizt 20 10 ns Address valid after PSEN tpxay t 25 5 ns Address to valid instruction in taviv 91 60 ns Address float to PSEN tAZPL 0 0 ns t Interfacing the HMS99C5X series to devices with float times up to 20 ns is permissible This limited bus contention will not cause any damage to port 0 Drivers Jan 2003 Ver 1 0 31 hynix HMS99C5X Series AC Characteristics for HMS99C5X series 40MHz External Data Memory Characteristics MHZ Clock robin 53 8 to A0MHz arameter Symbol Unit Min Max Min Max RD pulse width tRLRH 132 50 5 ns WR pulse width tWLWH 132 50 ns Address hold after ALE tLLAX2 10 20 ns RD to valid data in tRLDV 81 70 ns Data hold after RD tRHDX 0 0 ns Data float after RD tRHDZ 46 21101 15 ns ALE to valid data in tLLDv 153 90 ns Address to valid data in tAVDV 183 9tci cL 90 ns ALE to WR or RD tLLwL 71 111 20 3tcicL 20 ns Address valid to WR or RD tAVWL 66 4tcLCL 55 ns WR or RD high to ALE high 10 40
21. cified in the AC characteristics must be observed P2 0 P2 7 24 31 21 28 18 25 Port 2 Port 2 is an 8 bit bidirectional port with internal pull ups Port 2 pins that have 1s written to them are pulled high by the internal pull up resistors and can be used as inputs As inputs port 2 pins that are externally pulled low will source current because of the pulls ups in the DC characteristics Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses MOVX In this application it uses strong internal pull ups when emitting 1s During accesses to external data memory that use 8 bit addresses MOVX Ri port 2 emits the contents of the P2 special function register PSEN 32 29 26 The Program Store Enable The read strobe to external program memory when the device is executing code from the external program memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external data memory PSEN is not activated during fetches from internal program memory RESET 10 RESET A high level on this pin for two machine cycles while the oscillator is running resets the device An internal diffused resistor to Vss permits power on reset using only an external capacitor to Vcc Jan 2003 Ver 1 0 hynix
22. d Flat Package 44MQFP 13 45 12 95 2 10 10 UNIT 9 90 k 99 25 Y SEE DETAIL A A 1 EM 1 03 2 35 max 0 73 0 45 160 048 0 80 BSC DETAIL A Jan 2003 Ver 1 0
23. ed low will source current because of the pulls ups in the DC characteristics Port also serves the special features of the 80C51 family as listed below 11 10 5 P3 0 RxD receiver data input asynchronous or data input output synchronous of serial interface 0 13 11 7 P3 1 TxD transmitter data output asynchronous or clock output synchronous of the serial interface 0 14 12 8 P3 2 INTO interrupt 0 input timer 0 gate control 15 13 9 P3 3 INT1 interrupt 1 input timer 1 gate control 16 14 10 P3 4 TO counter 0 input 17 15 11 P3 5 T1 counter 1 input 18 16 12 6 the write control signal latches the data byte from port 0 into the external data memory 19 17 13 P3 7 RD the read control signal enables the external data memory to port 0 XTAL2 20 18 14 XTAL2 Output of the inverting oscillator amplifier Jan 2003 Ver 1 0 HMS99C5X Series Symbol Pin Number PLCC 44 PDIP MQFP 40 44 Input Output Function XTAL1 21 19 15 XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits To drive the device from an external clock source XTAL1 should be driven while XTAL2 is left unconnected There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is divided down by a divide by two flip flop Minimum and maximum high and low times as well as rise fall times spe
24. er counter 0 used as X X 1 1 fosc 12 fosc 24 one 8 bit timer counter and one 8 bit timer Timer 1 stops In the timer function C T 0 the register is incremented every machine cycle Therefore the count rate is fosc 12 In the counter function the register is incremented in response to a 1 10 0 transition at its corresponding exter nal input pin P3 4 TO P3 5 T1 Since it takes two machine cycles to detect a falling edge the max count rate is fosc 24 External inputs INTO and P3 2 P3 3 be programmed to function as a gate to facilitate pulse width measurements Figure 4 illustrates the input clock logic fosc gt 12 gt fosc 12 P3 4 TO a gt Timer 0 1 P3 5 T1 Input Clock Max fosc 24 1 TRO 1 TCON amp Gate 1 TMOD 21 P3 2 INTO P3 3 INT1 Figure 4 Timer Counter 0 and 1 Input Clock Logic 18 Jan 2003 Ver 1 0 HMS99C5X Series TIMER 2 Timer 2 is a 16 bit timer Counter with an up down count feature It can operate either as timer or as an event counter which is selected by bit C T2 T2CON 1 It has three operating modes as shown in Table 5 Table 5 Timer Counter 2 Operating Modes T2CON T2MOD T2CON P1 1 Input Clock Mode Remarks ROLL CP
25. eserved XXH 2 A3H reserved XXH 2 ABH reserved XXH 2 A4H reserved XXH 2 ACH reserved XXH 2 reserved XXH 2 ADH reserved XXH 2 A6H reserved XXH 2 AEH reserved XXH 2 A7H reserved XXH 2 AFH reserved XXH 2 BOH P3 1 FFH B8H IP 1 XX000000B 2 B1H reserved XXH 2 B9H reserved XXH2 B2H reserved XXH BAH reserved 2 B3H reserved XXH 2 BBH reserved XXH 2 B4H reserved XXH 2 BCH reserved XXH 2 B5H reserved XXH 2 BDH reserved XXH 2 B6H reserved XXH 2 BEH reserved XXH 2 B7H reserved XXH 2 BFH reserved XXH 2 Jan 2003 Ver 1 0 11 HMS99C5X Series Table 1 Special Function Registers in Numeric Order of their Addresses cont d Address Register eed Address Register COH reserved 3 2 1 00H reserved XXH 4 T2MOD XXXXXX00p 2 C2H reserved XXH 2 CAH 3 RC2L 00H C3H reserved XXH 2 CBH 9 RC2H 00H C4H reserved XXH 2 CCH 3 TL2 00H C5H reserved XXH CDH 3 TH2 00H C6H reserved XXH CEH reserved XXH2 C7H reserved XXH 2 CFH reserved XXH 2 DOH PSW 1 FFH D8H reserved XXH 2 D1H reserved XXH 2 D9H reserved XXH2 D2H reserved XXH DAH reserved 2 reserved XXH 2 DBH reserved XXH 2 D4H reserved XXH 2 DCH reserved XXH 2 D5H reserved XXH 2 DDH reserved XXH 2 D6H reserved XXH 2 DEH reserved XXH 2 D7H reserved XXH 2 DFH reserved XXH 2 EOH 1 00H E8H reserved 2 1 reserved XXH 2 E9H reserved XXH2 E2H reserved XXH EAH reserved XXH2 E3H
26. fer Reg 99H XXH 2 SCON Serial Channel 0 Control Reg 98H 1 00H Timer 0 Timer 1 TCON Timer 0 1 Control Register 88H 1 00H THO Timer 0 High Byte 8CH 00H TH1 Timer 1 High Byte 8DH 00H TLO Timer 0 Low Byte 8AH 00H TL1 Timer 1 Low Byte 8BH 00H TMOD Timer Mode Register 89H 00H Timer 2 T2CON Timer 2 Control Register C8H 1 00H T2MOD Timer 2 Mode Register C9H 00H RC2H Timer 2 Reload Capture Reg High Byte CBH 00H RC2L Timer 2 Reload Capture Reg Low Byte CAH 00H TH2 Timer 2 High Byte CDH 00H TL2 Timer 2 Low Byte CCH 00H AUXRO Aux Register 0 8bEH XXXXXXXOB 2 Power Saving PCON 9 Power Control Register 87H 0XXX0000B 2 Modes 1 Bit addressable Special Function register 2 X means that the value is indeterminate and the location is reserved 3 This special function register is listed repeatedly since some bit of it also belong to other functional blocks Table 3 Contents of SFRs SFRs in Numeric Order Address 80H Register PO Jan 2003 Ver 1 0 Bit 7 6 5 4 13 Table 3 Contents of SFRs SFRs in Numeric Order Address 81H 82H 83H 87H 88H 89H 8AH 8BH 8CH 8DH 8bEH 8FH 90H 98H 99H AOH A8H BOH B8H 14 Register SP DPL DPH PCON TCON TMOD TLO TL1 THO TH1 AUXRO CKCON P1 SCON SBUF P2 599 5 Series
27. hould consult the crystal manufacturer for ap propriate values of external components 36 Jan 2003 Ver 1 0 HMS99C5X Series Plastic Package P LCC 44 Plastic Leaded Chip Carrier 44PLCC 0 695 0 685 0 656 i 0 650 1O eio g H 4 L oo oo H 0 050 BSC 0 050 BSC UNIT INCH lt min 0 020 2415 86 olo L Oo oo 88 1 1 CL 0 012 0 0075 i 0 120 lt 0 090 0 180 0 165 Jan 2003 Ver 1 0 37 hynix Plastic Package P DIP 40 Plastic Dual in Line Package 599 5 Series 40DIP a 99 5 ast Vere ET ee eo od bar 2 075 2 045 gt oO 5 S Vv E 1 284 4 0 022 0 065 0 100BSC 0 015 gt lt 0 045 lt oo UNIT INCH 0 600 BSC 0 550 0 530 40 9 0 15 38 Jan 2003 Ver 1 0 HMS99C5X Series Plastic Package P MPQF 44 Plastic Metric Qua
28. mode 24 MHz 4 loc 25 mA 5V 7 Idle mode 24MHz 4 loc 10 ma 5 9 Active mode 40 MHz 4 lcc 30 5V Idle mode 40 MHz 4 15 5V Power Down Mode 4 22 mA 5V 50 Jan 2003 Ver 1 0 25 hynix HMS99C5X Series 1 D S9 6 26 Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VoL of ALE and port 3 The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 tran sitions during bus operation In the worst case capacitive loading gt 50pF at 3 3V gt 100pF at 5V the noise pulse on ALE line may exceed 0 8V In such cases it may be desirable to qualify ALE with a schmitt trigger or use an address latch with a schmitt trigger strobe input Capacitive loading on ports 0 and 2 may cause the Vou on ALE and PSEN to momentarily fall below the 0 9Vcc specifica tion when the address lines are stabilizing Icc Max at other frequencies is given by active mode 1 27 x fosc 5 73 idle mode 0 28 x fosc 1 45 except OTP devices where fosc is the oscillator frequency in MHz values are given in mA and measured at Vcc 5V active mode is measured with XTAL1 driven with tci cH tcHcL 5ns Vss 0 5V Vcc 0 5V XTAL2 EA 0 RESET Vcc all other pins are disconnected would be sligh
29. o 12 MHz External Program Memory Characteristics Variable Oscillator Parameter Symbol 1 3 5 to 12MHz Unit Min Max Min Max ALE pulse width ti HLL 127 2 40 ns Address setup to ALE tAVLL 43 40 ns Address hold after ALE 30 53 ns ALE low to valid instruction in E 233 4tcLcL 100 ns ALE to PSEN tLLPL 58 25 ns PSEN pulse width tPLPH 215 35 ns PSEN to valid instruction in tPLIV 150 100 ns Input instruction hold after PSEN tpxix 0 0 ns Input instruction float after PSEN tpxizt 63 20 ns Address valid after PSEN tpxav 75 8 ns Address to valid instruction in taviv E 302 115 ns Address float to PSEN tAZPL 0 0 ns t Interfacing the HMS99C5X series to devices with float times up to 75 ns is permissible This limited bus contention will not cause any damage to port 0 Drivers Jan 2003 Ver1 0 27 hynix HMS99C5X Series AC Characteristics for HMS99C5X series 12MHz External Data Memory Characteristics 1 12 MHz Oscillator n 12120289 arameter Symbol Unit Min Max Min Max RD pulse width tRLRH 400 100 5 5 WR pulse width twLWH 400 100 5 Address hold after
30. or Calculating Baud rates Baud Rate derived from Interface Mode Baudrate fosc 0 12 Oscillator SMOD 2 2 64 x fosc 5 u 1 3 x Timer 1 overflow Timer 1 16 bit timer 32 8 bit timer with 8 bit auto reload pSMOD fosc 1 3 32 12x 256b TH1 fosc Timer 2 1 3 32x 65536 b RC2H 21 20 Jan 2003 Ver 1 0 HMS99C5X Series INTERRUPT SYSTEM The 99 5 series provides 5 4K bytes ROM version or 6 above 8K bytes ROM version interrupt sourc es with two priority levels Figure 5 gives a general overview of the interrupt sources and illustrates the request and control flags High Priority Timer 0 Overflow TFO eo 25 ve 5 i Low ETO PTO Priority IE 1 IP 1 Timer 1 Overflow 1 eo e o TCON 7 gt PT1 IP 3 Timer 2 Overflow TF2 gt 1 ors eo n T2CON 7 3 4 P1 1 2 2 2 2 T2CON 6 5 IP 5 EXEN2 T2CON 3 RI 21 UART SCON 0 o o a ES PS SCON 1 Tm gt
31. rrupt 1 IE1 Timer 1 Interrupt TF1 Serial Channel RI TI Timer 2 Interrupt TF2 EXF2 Low 22 Jan 2003 Ver 1 0 HMS99C5X Series Power Saving Modes Two power down modes are available the Idle Mode and Power Down Mode The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode respectively If the Power Down mode and the Idle mode are set at the same time the Power Down mode takes precedence Table 10 gives a general overview of the power saving modes Table 10 Power Saving Modes Overview Entering Mode Instruction Leaving by Remarks Example Idle mode ORL PCON 01 Enabled interrupt CPU is gated off Hardware Reset CPU status registers maintain their data Peripherals are active Power Down mode ORL PCON 402H Hardware Reset Oscillator is stopped contents of on chip RAM and SFR s are maintained leaving Power Down Mode means redefinition of SFR contents In the Power Down mode of operation Vcc can be reduced to minimize power consumption It must be ensured however that Vcc is not reduced before the Power Down mode is invoked and that V is restored to its normal operating level before the Power Down mode is terminated The reset signal that terminates the Power Down mode also restarts the oscillator The reset should not be activated before V cc is restored to its normal operating level and must be held active long enough to allow the
32. s machine cycle 20MHz Equivalent to 40MHz 95V 4K bytes FLASH ROM 128 x 8Bit RAM 64K external program memory space 64K external data memory space Four 8 bit ports Two 16 bit Timers Counters USART Programmable ALE pin enable disable Low EMI Five interrupt sources two priority levels Power saving Idle and power down mode P DIP 40 P LCC 44 P MQFP 44 package Temperature Ranges 40 C 85 C Block Diagram FLASH ROM 3 lt gt vo Jan 2003 Ver 1 0 HMS99C5X Series HMS99C52 Fully compatible to standard MCS 51 microcontroller Wide operating frequency up to 40MHz for more detail see HMS99C5X Series Selection Guide X2 Speed Improvement capability X2 Mode 6 clocks machine cycle 20MHz Equivalent to 40MHz 95V 8K bytes FLASH ROM 256 x 8Bit RAM 64K external program memory space 64K external data memory space Four 8 bit ports Three 16 bit Timers Counters Timer2 with up down counter feature USART One clock output port Programmable ALE pin enable disable Low EMI Six interrupt sources two priority levels Power saving Idle and power down mode P DIP 40 P LCC 44 P MQFP 44 package Temperature Ranges 40 85 Block Diagram lt VO lt 10 2 lt 10 FLASH ROM 8K x8 lt gt vo Jan 2003 Ver 1 0
33. t program counter and four general purpose register banks reside in special func tion register area The 28 special function registers SFR include pointers and registers that provide an interface between the CPU and the other on chip peripherals There are also 128 directly addressable bits within the SFR area All SFRs are listed in Table 1 Table 2 and Table 3 In Table 1 they are organized in numeric order of their addresses In Table 2 they are organized in groups which refer to the functional blocks of the HMS99C5X series Table 3 illustrates the contents of the SFRs Table 1 Special Function Registers in Numeric Order of their Addresses cont d Address Register cy Address Register M 80H 1 88H TCON 1 00H 81H SP 07H 89H TMOD 00H 82H DPL 00H 8AH TLO 00H 83H DPH 00H 8BH TL1 00H 84H reserved 2 8 THO 00H 85H reserved 2 8DH TH1 00H 86H reserved 2 8EH AUXRO XXH 2 87H PCON 0 0000 2 8FH CKCON 2 90H 1 1 98 SCON 1 00H 91H reserved 00H 99H SBUF XXH 2 92H reserved XXH 2 9AH reserved XXH 2 93H reserved XXH 2 9BH reserved XXH 2 94H reserved XXH 2 9CH reserved XXH 2 95H reserved XXH 2 9DH reserved XXH 2 96H reserved XXH 2 9EH reserved XXH 2 97H reserved XXH 2 9FH reserved XXH2 2 3 IE 1 0X000000B 2 A1H reserved XXH 2 AQH reserved XXH 2 A2H reserved XXH 2 AAH r
34. t open drain bidirectional port Port 0 pins that have 1s written to them float and can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program and data memory In this application it uses strong internal pull ups when emitting 1s Port O also outputs the code bytes during program verification in the GMS97X5X External pull up resistors are required during program verification Vss 22 20 16 Circuit ground potential Vcc 44 40 38 Supply terminal for all operating modes N C 1 12 6 17 23 34 28 39 No connection Jan 2003 Ver 1 0 HMS99C5X Series FUNCTIONAL DESCRIPTION The HMS99C5X series is fully compatible to the standard 8051 microcontroller family Itis compatible with the general 8051 family While maintaining all architectural and operational characteristics of the general 8051 family Figure 1 shows a block diagram of the HMS99C5X series FRASH XTAL1 OSC amp TIMING 128 256x8 4K 8K XTAL2 lt 1 ft 1 RESET CPU EA Vpp gt Timer 0 Port 0 ALEIPROG 0 8 bit Digit PSEN lt Timer 1 Port 1 Port 1 8 bit Digit i Timer 2 Port 2 Pot2 2 Digit VO
35. tly higher if a crystal oscillator is used appr 1mA Idle mode is measured with all output pins disconnected and with all peripherals disabled XTAL1 driven with tci cH tcHcL 5ns Vss 0 5V Vcc 0 5V XTAL2 RESET EA Vss PortO Vcc all other pins are disconnected Power Down Mode is measured under following conditions EA Vcc RESET Vss XTAL2 N C XTAL1 Vss all other pins are disconnected Jan 2003 Ver 1 0 HMS99C5X Series AC Characteristics Explanation of the AC Symbols Each timing symbol has 5 characters The first character is always a t stand for time The other characters depending on their positions stand for the name of a signal or the logical status of that signal The following is a list of all the characters and what they stand for A Address T Time C Clock V Valid D Input Data W WR signal H Logic level HIGH X No longer a valid logic level I Instruction program memory contents Z Float L Logic level LOW or ALE P PSEN For example Q Output Data tavLL Time from Address Valid to ALE Low R RD signal tLLPL Time from ALE Low to PSEN Low AC Characteristics for HMS99C5X series 12MHz version 5V 10 15 Vss 40 C to 85 for port 0 ALE and PSEN outputs 100pF for all other outputs 80pF Variable clock Vcc 5V 1 3 5 MHz t
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