DSP56F802, 56F802
Contents
1. 8K x 16 bit words of Program Flash 1K x 16 bit words of Program RAM 2K x 16 bit words of Data Flash 1K x 16 bit words of Data RAM 2K x 16 bit words of Boot Flash e Programmable Boot Flash supports customized boot code and field upgrades of stored code through a variety of interfaces JTAG 1 1 3 Peripheral Circuits for 56F802 e Pulse Width Modulator PWM with six PWM outputs with deadtime insertion and fault protection supports both center and edge aligned modes e Two 12 bit Analog to Digital Converters ADCs 1 x 2 channel and 1 x 3 channel which support two simultaneous conversions ADC and PWM modules can be synchronized e Two General Purpose Quad Timers with two external pins or two GPIO e Serial Communication Interface SCI with two pins or two GPIO e Four multiplexed General Purpose I O GPIO pins 56F802 Technical Data Rev 9 4 Freescale Semiconductor 56F802 Description e Computer Operating Properly COP watchdog timer e External interrupts via GPIO e Trimmable on chip relaxation oscillator e External reset pin for hardware reset e JTAG On Chip Emulation OnCE for unobtrusive processor speed independent debugging e Software programmable Phase Locked Loop based frequency synthesizer for the controller core clock 1 1 4 Energy Information e Fabricated in high density CMOS with 5V tolerant TTL compatible digital inputs e Uses a single 3 3V power supply e On chip regulators for digital and analog2. BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH A EXACT SHAPE OF EACH CORNER IS OPTIONAL THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0 1 MM AND 0 25 DETAIL G gt gt Pe gt 32 S 0 TC MM FROM THE LEAD TIP MILLIMETERS ee DIM CMN MAX A 140 160 Ai 0 05 0 15 A2 135 145 b 030 045 bi 030 040 l 009 0 20 a 009 016 D 9 00 BSC DI 7 00 BSC e 0 80 BSC E 9 00 BSC EI 7 00 BSC L 0 50 O70 SECTION EP Li 1 00 REF ROTATED ga cw aI 79 REF 32 PLACES RI 0 08 0 20 R2 008 S 0 20 REF Figure 4 2 32 pin LQFP Mechanical Information Case 873A Please see www freescale com for the most current case outline 56F802 Technical Data Rev 9 Freescale Semiconductor 33 Part 5 Design Considerations 5 1 Thermal Design Considerations An estimation of the chip junction temperature Tj in C can be obtained from the equation Equation 1 T T Pp Roja Where Ta ambient temperature C Roya package junction to ambient thermal resistance C W Pp power dissipation in package Historically thermal resistance has been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance Equation 2 R Baue Roca Where Roya package junction to ambient thermal resistance C W Rejc package junction to case thermal resistance C W Roca package c
3. PWMAO P ANA PJ ANAG ANA ORIENTATION MARK ANA3 VREF ANA2 LJ FAULTAO Ra x Ke Fei N Oo O O E E E E a O 5 Figure 4 1 Top View 56F802 32 pin LQFP Package 56F802 Technical Data Rev 9 Freescale Semiconductor 31 Table 4 1 56F802 Pin Identification by Pin Number Pin No Signal Name Pin No Signal Name Pin No Signal Name Pin No Signal Name 1 PWMA4 9 TCS 17 Vppa 25 ANA4 2 PWMA5 10 TCK 18 Vasen 26 ANA6 3 TD1 11 TMS 19 VDD 27 ANA7 4 TD2 12 TDI 20 Vss 28 PWMAO 5 TXDO 13 VCAPC2 21 FAULTAO 29 VCAPC1 6 Vss 14 TDO 22 ANA2 30 PWMA1 7 Von 15 TRST 23 VREF 31 PWMA2 8 RXDO 16 RESET 24 ANA3 32 PWMA3 56F802 Technical Data Rev 9 32 Freescale Semiconductor Package and Pin Out Information 56F802 NOTES DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 CONTROLLING DIMENSION MILLIMETER DATUM PLANE A B AND D TO BE DETERMINED AT DATUM PLANE H DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C DIMENSIONS b DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THEN 0 08 MM DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTURSION 0 07 MM DIMENSIONS DI AND E1 DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE PROTRUSION IS 0 25 MM PER SIDE D1 AND E1 ARE MAXIMUM PLASTIC
4. Tnvh1 Tme l Trev Figure 3 6 Flash Mass Erase Cycle 3 5 Clock Operation The 56F802 device clock is derived from an on chip relaxation oscillator The internal PLL generates a master reference frequency that determines the speed at which chip operations occur The PRECS bit in the PLLCR phase locked loop control register word bit 2 must be set to 0 for internal oscillator use 3 5 1 Use of On Chip Relaxation Oscillator The 56F802 internal relaxation oscillator provides the chip clock without the need for an external crystal or ceramic resonator The frequency output of this internal oscillator can be corrected by adjusting the 8 bit IOSCTL internal oscillator control register Each bit added or deleted changes the output frequency of the oscillator allowing incremental adjustment until the desired frequency is achieved Figures 9 and 10 show the typical characteristics of the 56F802 relaxation oscillator with respect to temperature and trim value During factory production test an oscillator calibration procedure is executed which determines an optimum trim value for a given device 8MHz at 25 C This optimum trim value is then stored at address 103F in the Data Flash Information Block and recalled during a trim routine in the boot sequence executed after power up and RESET This trim routine automatically sets the oscillator frequency by programming the IOSCTL register with the optimum trim value 56F802 Technical Data Rev
5. includes TCS pin which is reserved for factory use and is tied to VSS Figure 2 1 56F802 Signals Identified by Functional Group 1 Alternate pin functionality is shown in parenthesis 56F802 Technical Data Rev 9 Freescale Semiconductor 9 2 2 Power and Ground Signals Table 2 2 Power Inputs No of Pins Signal Name Signal Description 2 Vop Power These pins provide power to the internal structures of the chip and should all be attached to Vpp 1 Vppa Analog Power This pin is a dedicated power pin for the analog portion of the chip and should be connected to a low noise 3 3V supply Table 2 3 Grounds No of Pins Signal Name Signal Description 2 Vss GND These pins provide grounding for the internal structures of the chip and should all be attached to Vss 1 Vasen Analog Ground This pin supplies an analog ground 1 TCS TCS This Schmitt pin is reserved for factory use and must be tied to Vsg for normal use In block diagrams this pin is considered an additional Vss Table 2 4 Supply Capacitors and VPP No of Signal Signal State During z S Pins Name Type Reset Signal Description 2 VCAPC Supply Supply VCAPC Connect each pin to a 2 2 uF or greater bypass capacitor in order to bypass the core logic voltage regulator required for proper chip operation For more information refer to Section 5 2 56F802 Technical Data Rev 9 10 Freescale Semicon
6. 9 22 Freescale Semiconductor Clock Operation Due to the inherent frequency tolerances required for SCI communication changing the factory trimmed oscillator frequency is not recommended If modification of the Boot Flash contents are required code must be included which retrieves the optimum trim value from address 103F in the Data Flash Information Block and writes it to the IOSCTL register Note that the IFREN bit in the Data Flash control register must be set in order to read the Data Flash Information Block Table 3 8 Relaxation Oscillator Characteristics Operating Conditions Vss Vggq 0 V Vpp Vppa 3 0 3 6 V Ta 40 to 85 C Characteristic Symbol Min Typ Max Unit Frequency Accuracy Af 2 5 Frequency Drift over Temp Af At 0 1 H C 0 1 DV Frequency Drift over Supply Af AV 1 Over full temperature range 8 4 8 3 8 2 8 1 Output Frequency 8 0 7 9 rs 40 25 5 15 35 55 15 85 Temperature C Figure 3 7 Typical Relaxation Oscillator Frequency vs Temperature Trimmed to 8MHz 25 C 56F802 Technical Data Rev 9 Freescale Semiconductor 11 7 DES e S O 10 20 30 40 50 60 70 80 90 AO BO CO DO EO FO Fi
7. Considerations Table 6 1 56F802 Ordering Information Supply Pin Ambient Part Voltage Package Type Count Frequency Order Number MHz 56F802 3 0 3 6 V Low Profile Plastic Quad Flat Pack LQFP 32 80 DSP56F802TA80 56F802 3 0 3 6 V Low Profile Plastic Quad Flat Pack LQFP 32 60 DSP56F802TA60 56F802 3 0 3 6 V Low Profile Plastic Quad Flat Pack LQFP 32 80 DSP56F802TA80E 56F802 3 0 3 6 V Low Profile Plastic Quad Flat Pack LQFP 32 60 DSP56F802TA60E This package is RoHS compliant 56F802 Technical Data Rev 9 37 Freescale Semiconductor 56F802 Technical Data Rev 9 38 Freescale Semiconductor Electrical Design Considerations 56F802 Technical Data Rev 9 Freescale Semiconductor 39 How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Jap
8. Pins Name Type Reset Signal Description 2 TD1 2 Input Input TD1 2 Timer D Channel 1 2 Output GPIOA1 2 Input Input Port A GPlO These pins are General Purpose UO GPIO pins that Output can be individually programmed as input or output pins After reset the default state is the quad timer input 56F802 Technical Data Rev 9 12 Freescale Semiconductor JTAG OnCE 2 8 JTAG OnCE Table 2 10 JTAG On Chip Emulation OnCE Signals No of Signal Signal State During Pins Name Type Reset Signal Description 1 TCK Input Input pulled Test Clock Input This input pin provides a gated clock to synchronize the Schmitt low internally test logic and shift serial data to the JTAG OnCE port The pin is connected internally to a pull down resistor 1 TMS Input Input pulled Test Mode Select Input This input pin is used to sequence the JTAG TAP Schmitt high internally controller s state machine It is sampled on the rising edge of TCK and has an on chip pull up resistor Note Always tie the TMS pin to Vpp through a 2 2K resistor 1 TDI Input Input pulled Test Data Input This input pin provides a serial input data stream to the Schmitt high internally JTAG OnCE port It is sampled on the rising edge of TCK and has an on chip pull up resistor 1 TDO Output Tri stated Test Data Output This tri statable output pin provides a serial output data stream from the JTAG OnC
9. ROJA W 7 Notes 1 Theta JA determined on 2s2p test boards is frequently lower than would be observed in an application Determined on 2s2p thermal test board 2 Junction to ambient thermal resistance Theta JA Roja was simulated to be equivalent to the JEDEC specification JESD51 2 in a horizontal configuration in natural convection Theta JA was also simulated on a thermal test board with two internal planes 2s2p where s is the number of signal layers and p is the number of planes per JESD51 6 and JESD51 7 The correct name for Theta JA for forced convection or with the non single layer boards is Theta JMA 3 Junction to case thermal resistance Theta JC Rgjc was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the case temperature The basic cold plate measurement technique is described by MIL STD 883D Method 1012 1 This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink 4 Thermal Characterization Parameter Psi JT Yj is the resistance from junction to reference point thermocouple on top center of case as defined in JESD51 2 Yj is a useful value to use to estimate junction temperature in steady state customer environments 56F802 Technical Data Rev 9 Freescale Semiconductor 15 5 Junction temperature is a function of on chip power dissipation package thermal resistance mounti
10. circuitry to lower cost and reduce noise e Wait and Stop modes available e Integrated power supervisor 1 2 56F802 Description The 56F802 is a member of the 56800 core based family of processors It combines on a single chip the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost effective solution Because of its low cost configuration flexibility and compact program code the 56F802 is well suited for many applications The 56F802 includes many peripherals that are especially useful for applications such as motion control home appliances encoders tachometers limit switches power supply and control engine management and industrial control for power lighting automation and HVAC The 56800 core is based on a Harvard style architecture consisting of three execution units operating in parallel allowing as many as six operations per instruction cycle The microprocessor style programming model and optimized instruction set allow straightforward generation of efficient compact code for both DSP and MCU applications The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications The 56F802 supports program execution from either internal or external memories Two data operands can be accessed from the on chip Data RAM per instruction cycle The 56F802 also provides and up to 4 General Purpose Input Outpu
11. lt 50 pF 2 04pf JTAG Timing Characteristic Symbol Min Max Unit TCK frequency of operation fop DC 10 MHz TCK cycle time tey 100 ns TCK clock pulse width tpw 50 ns TMS TDI data setup time tos 0 4 ns TMS TDI data hold time fou 1 2 ns TCK low to TDO data valid tpv 26 6 ns TCK low to TDO tri state tts 23 5 ns TRST assertion time TRST 50 ns 1 Timing is both wait state and frequency dependent For the values listed T clock cycle For 80MHz operation T 12 5ns 2 TCK frequency of operation must be less than 1 8 the processor rate 3 Parameters listed are guaranteed by design 56F802 Technical Data Rev 9 Freescale Semiconductor 29 TCK Input Vm Vir Vin Vull Figure 3 14 Test Clock Input Timing Diagram TCK Input DS toy ar gt J TDI TMS d Input Data Valid Input tov ra gt Output Output Data Valid tts M TDO eS Output DV lt Output Output Data Valid Figure 3 15 Test Access Port Timing Diagram TRST Input ttrst Figure 3 16 TRST Timing Diagram 56F802 Technical Data Rev 9 30 Freescale Semiconductor Package and Pin Out Information 56F802 Part 4 Packaging 4 1 Package and Pin Out Information 56F802 This section contains package and pin out information for the 32 pin LQFP configuration of the 56F802 PWMA3 PWMA2 PWMA1 VCAPC1
12. 0 325 mV Total Harmonic Distortion THD 55 60 dB Signal to Noise plus Distortion SINAD 54 56 E ei Effective Number of Bits ENOB 8 5 9 5 bit Spurious Free Dynamic Range SFDR 60 65 dB Spurious Free Dynamic Range SFDR 65 70 dB ADC Quiescent Current both ADCs lapc 50 mA Ver Quiescent Current both ADCs IVREF 12 16 5 mA 1 For optimum ADC performance keep the minimum Vapcin value gt 250mV Inputs less than 250mV volts may convert to a digital output code of 0 or cause erroneous conversions 2 Vper must be equal to or less than Vppa 0 3V and must be greater than 2 7V 3 Measured in 10 90 range 4 LSB Least Significant Bit 5 6 Guaranteed by characterization taic 1fapic 56F802 Technical Data Rev 9 28 Freescale Semiconductor 2 3 4 ADC analog input Parasitic capacitance due to package pin to pin and pin to package base coupling 1 8pf Parasitic capacitance due to the chip bond pad ESD protection devices and signal routing Equivalent resistance for the ESD isolation resistor and the channel select mux 500 ohms Sampling capacitor at the sample and hold circuit Capacitor 4 is normally disconnected from the input and is only connected to it at sampling time 1pf Figure 3 13 Equivalent Analog Input Circuit 3 10 JTAG Timing Table 3 14 JTAG Timing 3 Operating Conditions Vss Vssa 0 V Vpp Vppa 3 0 3 6 V Ta 40 to 85 C Cy
13. 3V 10 during normal operation without causing damage This 5V tolerant capability therefore offers the power savings of 3 3V I O levels while being able to receive 5V levels without being damaged Absolute maximum ratings given in Table 3 1 are stress ratings only and functional operation at the maximum is not guaranteed Stress beyond these ratings may affect device reliability or cause permanent damage to the device 56F802 Technical Data Rev 9 Freescale Semiconductor 13 The 56F802 DC and AC electrical specifications are preliminary and are from design simulations These specifications may not be fully tested or guaranteed at this early stage of the product life cycle Finalized specifications will be published after complete characterization and device qualifications have been completed CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields However normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level Table 3 1 Absolute Maximum Ratings Characteristic Symbol Min Max Unit Supply voltage Vpp Vss 0 3 Vss 4 0 V All other input voltages excluding Analog inputs Vum Vss 0 3 Vss 5 5V V Voltage difference Vpp to Vppa AVDp 0 3 0 3 V Voltage differe
14. 56F 802 Data Sheet Preliminary Technical Data 56F800 16 bit Digital Signal Controllers DSP56F802 Rev 9 01 2007 freescale com 2 freescale semiconductor 56F802 General Description e Up to 30 MIPS operation at 60MHz core frequency e 8K x 16 bit words 16KB Program Flash e Up to 40 MIPS operation at 80MHz core frequency e 1K x 16 bit words 2KB Program RAM e DSP and MCU functionality in a unified e 2K x 16 bit words 4KB Data Flash E EE 1K x 16 bit words 2KB Data RAM Eege addressing modes e JTAG OnCE port for debugging Hardware DO and REP loops e On chip relaxation oscillator e 6 channel PWM Module with fault input e 4 shared GPIO e Two 12 bit ADCs 1 x 2 channel 1 x 3 channel 32 pin LQFP Package e Serial Communications Interface SCI e Two General Purpose Quad Timers with 2 external outputs e PWM Outputs 6 PWMA gt Fault AO RESET VCAPC Von Vss Vopa Vssa i 2 y 9 JTAG Geht OnCE Digital Reg Analog Reg Bol Low Voltage Supervisor Interrupt Controller Program Controller Address 16x16 EE MAC Bit and Generation z Manipulation P d S Three 16 bit Input Registers S Hardware Looping Unit Unit EE EE Unit A A AA A Program Memory PAB 8188 x 16 Flash d B PLL Quad Timer C 1024 x 16 SRAM la PDB or Ke OPG Boot Flash ad 2 2048x 16 Flash XDB2
15. E port It is driven in the Shift IR and Shift DR controller states and changes on the falling edge of TCK 1 TRST Input Input pulled Test Reset As an input a low signal on this pin provides a reset signal to the Schmitt high internally JTAG TAP controller To ensure complete hardware reset TRST should be asserted at power up and whenever RESET is asserted The only exception occurs in a debugging environment since the OnCE JTAG module is under the control of the debugger In this case it is not necessary to assert TRST when asserting RESET Outside of a debugging environment RESET should be permanently asserted by grounding the signal thus disabling the OnCE JTAG module on the device Note For normal operation connect TRST directly to Vg If the design is to be used in a debugging environment TRST may be tied to Vgs through a 1K resistor Part 3 Specifications 3 1 General Characteristics The 56F802 is fabricated in high density CMOS with 5 volt tolerant TTL compatible digital inputs The term 5 volt tolerant refers to the capability of an I O pin built on a 3 3V compatible process technology to withstand a voltage up to 5 5V without damaging the device Many systems have a mixture of devices designed for 3 3V and 5V power supplies In such systems a bus may carry both 3 3V and 5V compatible I O voltage levels a standard 3 3V I O is designed to receive a maximum voltage of 3
16. Relaxation y Oscillator id Data Memory CGDB 2048 x 16 Flash XAB1 o 1024 x 16 SRAM SE d 16 Bit la A 56800 INTERRUPT IPBB Core SCHO CONTROLS CONTROLS t or 2 GPIO COP Watchdog ty Wy he includes TCS pin which is reserved for factory use and is tied to VSS 56F802 Block Diagram 56F802 Technical Data Rev 9 Freescale Semiconductor Part 1 Overview 1 1 56F802 Features 1 1 1 Processing Core e Efficient 16 bit 56800 family controller engine with dual Harvard architecture e As many as 40 Million Instructions Per Second MIPS at 80 MHz core frequency e Single cycle 16 x 16 bit parallel Multiplier Accumulator MAC e Two 36 bit accumulators including extension bits e 16 bit bidirectional barrel shifter e Parallel instruction set with unique processor addressing modes e Hardware DO and REP loops e Three internal address buses and one external address bus e Four internal data buses and one external data bus e Instruction set supports both DSP and controller functions e Controller style addressing modes and instructions for compact code e Efficient C compiler and local variable support e Software subroutine and interrupt stack with depth limited only by memory e JTAG OnCE debug programming interface 1 1 2 Memory e Harvard architecture permits as many as three simultaneous accesses to program and data memory e On chip memory including a low cost high volume Flash solution
17. als Table 2 7 Serial Communications Interface SCI0 Signals No of Signal Signal State During e SEH Pins Name Type Reset Signal Description 1 TXDO Output Input Transmit Data TXD0 SCIO transmit data output GPIOBO Input Ou Input Port B GPIO This pin is a General Purpose I O GPIO pin that can tput be individually programmed as an input or output pin After reset the default state is SCI output 56F802 Technical Data Rev 9 Freescale Semiconductor 11 Table 2 7 Serial Communications Interface SCI0 Signals Continued No of Signal Signal State During ae Pins Name Type Reset Signal Description 1 RXDO Input Input Receive Data RXD0 SCIO receive data input GPIOB1 Input Input Port B GPIO This pin is a General Purpose I O GPIO pin that can Output be individually programmed as an input or output pin After reset the default state is SCI input 2 6 Analog to Digital Converter ADC Signals Table 2 8 Analog to Digital Converter Signals Gage Ser Eed EE Signal Description 3 ANA2 4 Input Input ANA2 4 Analog inputs to ADC channel 1 2 ANAG6 7 Input Input ANA6 7 Analog inputs to ADC channel 2 1 VREF Input Input VREF Analog reference voltage Must be set to Vppa 0 3V for optimal performance 2 7 Quad Timer Module Signals Table 2 9 Quad Timer Module Signals No of Signal Signal State During ee
18. an 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com RoHS compliant and or Pb free versions of Freescale products have the unctionality and electrical characteristics of their non RoHS compliant and or non Pb free counterparts For further information see http www freescale com or contact your Freescale sales representative For information on Freescale s Environmental Products program go to http www freescale com epp nformation in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconduc
19. ase to ambient thermal resistance C W Bac is device related and cannot be influenced by the user The user controls the thermal environment to change the case to ambient thermal resistance Roca For example the user can change the air flow around the device add a heat sink change the mounting arrangement on the Printed Circuit Board PCB or otherwise change the thermal dissipation capability of the area surrounding the device on the PCB This model is most useful for ceramic packages with heat sinks some 90 of the heat flow is dissipated through the case to the heat sink and out to the ambient environment For ceramic packages in situations where the heat flow is split between a path to the case and an alternate path through the PCB analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted Again if the estimations obtained from Rgy do not satisfactorily answer whether the thermal performance is adequate a system level model may be appropriate Definitions A complicating factor is the existence of three common definitions for determining the junction to case thermal resistance in plastic packages e Measure the thermal resistance from the junction to the outside surface of the package case closest to the chip mounting area when that surfa
20. ce has a proper heat sink This is done to minimize temperature variation across the surface 56F802 Technical Data Rev 9 34 Freescale Semiconductor Electrical Design Considerations e Measure the thermal resistance from the junction to where the leads are attached to the case This definition is approximately equal to a junction to board thermal resistance e Use the value obtained by the equation T Ty Pp where Ty is the temperature of the package case determined by a thermocouple The thermal characterization parameter is measured per JESD51 2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case The thermocouple should be positioned so that the thermocouple junction rests on the package A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire When heat sink is used the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material A clearance slot or hole is normally required in the heat sink Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink Because of the experimental difficulties with this techni
21. ductor Interrupt and Program Control Signals 2 3 Interrupt and Program Control Signals Table 2 5 Program Control Signals No of Signal Signal State During f SE Pins Name Type Reset Signal Description 1 RESET Input Input Reset This input is a direct hardware reset on the processor When Schmitt RESET is asserted low the controller is initialized and placed in the Reset state A Schmitt trigger input is used for noise immunity When the RESET pin is deasserted the initial chip operating mode is latched from the EXTBOOT pin The internal reset signal will be deasserted synchronous with the internal clocks after a fixed number of internal clocks To ensure complete hardware reset RESET and TRST should be asserted together The only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the OnCE JTAG module In this case assert RESET but do not assert TRST 2 4 Pulse Width Modulator PWM Signals Table 2 6 Pulse Width Modulator PWMA Signals No of Signal Signal State During gs Pins Name Type Reset Signal Description 6 PWMAO 5 Output Tri stated PWMAO 5 These are six PWMA output pins 1 FAULTAO Input Input FAULTAO This fault input is used for disabling selected PWMA Schmitt outputs in cases where fault conditions originate off chip 2 5 Serial Communications Interface SCI Sign
22. e capability to directly drive standard opto isolators A smoke inhibit write once protection feature for key parameters is also included The PWM is double buffered and includes interrupt control to permit integral reload rates to be programmable from 1 to 16 The PWM modules provide a reference output to synchronize the Analog to Digital Converters The 56F802 incorporates two 12 bit Analog to Digital Converters ADCs with a total of five channels A full set of standard programmable peripherals is provided that include a Serial Communications Interface SCI and two Quad Timers Any of these interfaces can be used as General Purpose Input Outputs GPIO if that function is not required An on chip relaxation oscillator eliminates the need for an external crystal 1 3 State of the Art Development Environment Processor Expert PE provides a Rapid Application Design RAD tool that combines easy to use component based software application creation with an expert knowledge system e The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation compiling and debugging A complete set of evaluation modules EVMs and development system cards will support concurrent engineering Together PE Code Warrior and EVMs create a complete scalable tools solution for easy fast and efficient development 1 4 Product Documentation The four documents listed in Table 1 1 are required for a complete descriptio
23. elow 1 5V typical no matter how long the ramp up rate is The internally regulated voltage is typically 100 mV less than Vpp during ramp up until 2 5V is reached at which time it self regulates 160 IDD Digital IDD Analog IDD Total 120 T 80 D 40 L l 0 10 20 30 40 50 60 70 80 Freq MHz Figure 3 1 Maximum Run IDD vs Frequency see Note 6 in Table 3 4 3 3 AC Electrical Characteristics Timing waveforms in Section 3 3 are tested using the Nu and V levels specified in the DC Characteristics table In Figure 3 2 the levels of Vu and Nu for an input signal are shown Input Signal Midpoint Fall Time Rise Time Note The midpoint is Vu Vin Mul Figure 3 2 Input Signal Measurement References Figure 3 3 shows the definitions of the following signal states e Active state when a bus or signal is driven and enters a low impedance state e Tri stated when a bus or signal is placed in a high impedance state 56F802 Technical Data Rev 9 Freescale Semiconductor e Data Valid state when a signal level has reached Vo or Voy Flash Memory Characteristics e Data Invalid state when a signal level is in transition between Vo and Voy Data1 Valid Data Invalid State 3 4 Flash Memory Characteristics Data Active Data2 Valid Data wi Tri stated Figure 3 3 Signal States Table 3 5 Flash Memory Truth Table Da
24. et 1 Values for Vi_ Me Vin and Vox are defined by individual product specifications 56F802 Technical Data Rev 9 Freescale Semiconductor 7 Part 2 Signal Connection Descriptions 2 1 Introduction The input and output signals of the 56F802 are organized into functional groups as shown in Table 2 1 and as illustrated in Figure 2 1 In Table 2 2 through Table 2 10 each table row describes the signal or signals present on a pin Table 2 1 Functional Group Pin Allocations Functional Group Number of Detailed Pins Description Power Vpp or Vppa 3 Table 2 2 Ground Vss Vssa TCS 4 Table 2 3 Supply Capacitors 2 Table 2 4 Program Control 1 Table 2 5 Pulse Width Modulator PWM Port and Fault Input 7 Table 2 6 Serial Communications Interface SCI Port 2 Table 2 7 Analog to Digital Converter ADC Port including VREF 6 Table 2 8 Quad Timer Module Port 2 Table 2 9 JTAG On Chip Emulation OnCE 5 Table 2 10 1 Alternately GPIO pins 56F802 Technical Data Rev 9 Freescale Semiconductor Introduction Power Port Von Ground Port Vss Power Port VDDA Ground Port Vssa PWMAO 5 Other TE Supply Port Fault AO 56F802 TXDO GPIOBO p SCIO Port or RXDO GPIOB1 GPIO ANA2 4 ANA6 7 VREF ADCA Port TC TCK TMS JTAG OnCE Port IDI Quad TD1 2 GPIOA1 2 Timer D or a TDO GPIO TRST RESET Program Control
25. gure 3 8 Typical Relaxation Oscillator Frequency vs Trim Value 25 C 3 5 2 Phase Locked Loop Timing Table 3 9 PLL Timing 1 An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly The PLL is optimized for 8MHz input crystal Characteristic Symbol Min Typ Max Unit Frequency for the PLL fosc 4 8 10 MHz PLL output frequency fout 2 40 803 MHz PLL stabilization time 0 to 85 C tolls 10 ms PLL stabilization time 40 to 0 C tolls 100 200 ms 2 ZCLK may not exceed 80MHz For additional information on ZCLK and f 2 please refer to the OCCS chapter in the User Manual ZCLK fop 3 Will not exceed 60MHz for the DSP56F802TA60 device 4 This is the minimum time required after the PLL setup is changed to ensure reliable operation 56F802 Technical Data Rev 9 24 Freescale Semiconductor Reset Stop Wait Mode Select and Interrupt Timing 3 6 Reset Stop Wait Mode Select and Interrupt Timing Table 3 10 Reset Stop Wait Mode Select and Interrupt Timing Operating Conditions Vss Vssa 0 V Vpp Vppa 3 0 3 6 V Ta 40 to 85 C Cy lt 50pF Characteristic Symbol Min Max Unit RESET Assertion to Address Data and Control Signals High traz 21 ns Impedance Minimum RESET Assertion Duration tRa OMR Bit 6 0 275 000T ns OMR Bit 6 1 1287 ns RESET De a
26. im alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part e Ze oe freescale semiconductor Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners This product incorporates SuperFlash technology licensed from SST Freescale Semiconductor Inc 2005 All rights reserved DSP56F802 Rev 9 01 2007
27. measured with 50 duty cycle 5 6 Run operating Ipp measured using 8MHz clock source All inputs 0 2V from rail outputs unloaded All ports configured as inputs measured with all modules enabled 7 Wait Ipp measured using external square wave clock source fose 8MHZz into XTAL all inputs 0 2V from rail no DC loads less than 50pF on all outputs C 20pF on EXTAL all ports configured as inputs EXTAL capacitance linearly affects wait Ipp measured with PLL enabled 8 This low voltage interrupt monitors the Vppa external power supply Vppa is generally connected to the same potential as Vpp via separate traces If Vpp drops below Mc an interrupt is generated Functionality of the device is guaranteed under transient conditions when Vppa2V_eio between the minimum specified Vpp and the point when the Vego interrupt is generated 9 This low voltage interrupt monitors the internally regulated core power supply If the output from the internal voltage is regulator drops below Vgc an interrupt is generated Since the core logic supply is internally regulated this interrupt will not be generated unless the external power supply drops below the minimum specified value 3 0V 56F802 Technical Data Rev 9 Freescale Semiconductor 17 10 Power on reset occurs whenever the internally regulated 2 5V digital supply drops below 1 5V typical While power is ramping up this signal remains active for as long as the internal 2 5V is b
28. n and proper design with the 56F802 Documentation is available from local Freescale distributors Freescale semiconductor sales offices Freescale Literature Distribution Centers or online at www freescale com Table 1 1 56F802 Chip Documentation Topic Description Order Number 56800E Detailed description of the 56800 family architecture and 56800EFM Family Manual 16 bit core processor and the instruction set DSP56F801 803 805 807 Detailed description of memory peripherals and interfaces DSP56F801 7UM User s Manual of the 56F801 56F802 56F803 56F805 and 56F807 56F802 Electrical and timing specifications pin descriptions and DSP56F802 Technical Data Sheet package descriptions this document 56F802 Details any chip issues that might be present 56F802E Errata 56F802 Technical Data Rev 9 6 Freescale Semiconductor Data Sheet Conventions 1 5 Data Sheet Conventions This data sheet uses the following conventions OVERBAR This is used to indicate a signal that is active when pulled low For example the RESET pin is active when low asserted A high true active high signal is high or a low true active low signal is low deasserted A high true active high signal is low or a low true active low signal is high Examples Signal Symbol Logic State Signal State Voltage PIN True Asserted Vuen DIN False Deasserted ViH VoH PIN True Asserted Vin Vou PIN False Deasserted Vu M
29. nce Vsg to Vssa AVss 0 3 0 3 V Analog Inputs ANAx VREF VIN Vss 0 3 Vppa 0 3V V Current drain per pin excluding Vpp Vss amp PWM ouputs l 10 mA Table 3 2 Recommended Operating Conditions Characteristic Symbol Min Typ Max Unit Supply voltage digital Von 3 0 3 3 3 6 V Supply Voltage analog Vopa 3 0 3 3 3 6 V Voltage difference Vpp to Vppa AVpp 0 1 0 1 V Voltage difference Vsg to Vssa AVss 0 1 0 1 V 56F802 Technical Data Rev 9 14 Freescale Semiconductor General Characteristics Table 3 2 Recommended Operating Conditions Characteristic Symbol Min Typ Max Unit ADC reference voltage VREF 2 7 VpDA V Ambient operating temperature Ta 40 85 C 1 VREF must be 0 3V below Vppa Table 3 3 Thermal Characteristics Value Note Characteristic Comments Symbol Unit s 32 pin LQFP Junction to ambient Rosa 50 2 C W 2 Natural convection Junction to ambient 1m sec RoJMA 47 1 C W 2 Junction to ambient Four layer board 2s2p RoJMA 38 7 C W 1 2 Natural convection 2s2p Junction to ambient 1m sec Four layer board 2s2p Roma 37 4 C W 1 2 Junction to case Rosc 17 8 C W 3 Junction to center of case Yor 3 07 C W 4 UO pin power dissipation Pio User Determined WwW Power dissipation P D P D Ipp xX Von P vo W Junction to center of case PDMAX TJ TA
30. ng site board temperature ambient temperature air flow power dissipation of other components on the board and board thermal resistance See Section 5 1 from more details on thermal design considerations TJ Junction Temperature TA Ambient Temperature 3 2 DC Electrical Characteristics Table 3 4 DC Electrical Characteristics Operating Conditions Vss Vssa 0 V Vpp Vppa 3 0 3 6 V Ta 40 to 85 C Cy lt 50pF Characteristic Symbol Min Typ Max Unit Input high voltage XTAL EXTAL Vue 2 25 2 75 V Input low voltage XTAL EXTAL Vue 0 0 5 V Input high voltage Schmitt trigger inputs Vins 2 2 GH 5 5 V Input low voltage Schmitt trigger inputs Vils 0 3 0 8 V Input high voltage all other digital inputs Vin 2 0 5 5 V Input low voltage all other digital inputs Vu 0 3 0 8 V Input current high pullup pulldown resistors disabled Vij Vpp Ju 1 1 uA Input current low pullup pulldown resistors disabled Vin Vss liL 1 1 uA Input current high with pullup resistor Vin Vpp liHPU 1 1 uA Input current low with pullup resistor Vin Vss Ju pu 210 50 LA Input current high with pulldown resistor Vij Vpp Jupp 20 180 LA Input current low with pulldown resistor Vij Vss Jupp 1 1 uA Nominal pullup or pulldown resistor value Rou Rpp 30 KQ Output tri state current low lozL 10 10 uA Output tri state current high lo
31. ons Vss Vssa 0 V Vpp Vppa 3 0 3 6 V Ta 40 to 85 C Cy lt 50pF Characteristic Symbol Min Max Unit Baud Rate BR fmax 2 5 80 Mbps RXD Pulse Width RXDpw 0 965 BR 1 04 BR ns TXD Pulse Width TXDpw 0 965 BR 1 04 BR ns 1 fmax is the frequency of operation of the system clock in MHz 2 The RXD pin in SCIO is named RXDO and the RXD pin in SCI1 is named RXD1 3 The TXD pin in SCIO is named TXDO and the TXD pin in SCI1 is named TXD1 4 Parameters listed are guaranteed by design RXD SCI receive data pin Input Figure 3 11 RXD Pulse Width TXD SCI receive data pin Input TXDpw Figure 3 12 TXD Pulse Width 56F802 Technical Data Rev 9 Freescale Semiconductor 27 3 9 Analog to Digital Converter ADC Characteristics Table 3 13 ADC Characteristics Characteristic Symbol Min Typ Max Unit ADC input voltages VADCIN 01 VREF V Resolution Res 12 12 Bits Integral Non Linearity INL 4 5 LSB4 Differential Non Linearity DNL 0 9 1 LSB Monotonicity GUARANTEED ADC internal clock faDic 0 5 5 MHz Conversion range Rap Vssa VDDA V Power up time tappu 2 5 msec Conversion time tapc 6 taic cycles Sample time taps 1 taic cycles Input capacitance Capi 5 pF Gain Error transfer gain EGAIN 1 00 1 10 1 15 Offset Voltage VOFFSET 10 23
32. que many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface From this case temperature the junction temperature is determined from the junction to case thermal resistance 5 2 Electrical Design Considerations CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields However normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level Use the following list of considerations to assure correct operation e Provide a low impedance path from the board power supply to each Vpp pin on the controller and from the board ground to each Vgg GND pin e The minimum bypass requirement is to place 0 1 uF capacitors positioned as close as possible to the package supply pins The recommended bypass configuration is to place one bypass capacitor on each of the Vpp Vsgs pairs including Vppa Vssa Ceramic and tantalum capacitors tend to provide better performance tolerances 56F802 Technical Data Rev 9 Freescale Semiconductor 35 Ensure that capacitor leads and associated printed circuit traces that connect to the chip V pp and Vss GND pins are less than 0 5 inch per capacitor lead Bypas
33. s the Vpp and Vgg layers of the PCB with approximately 100 uF preferably with ceramic or tantalum capacitors which tend to provide better performance tolerances Because the controller s output signals have fast rise and fall times PCB trace lengths should be minimal Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance This is especially critical in systems with higher capacitive loads that could create higher transient currents in the Vpp and GND circuits Take special care to minimize noise levels on the VREF Vppa and Vgga pins Designs that utilize the TRST pin for JTAG port or OnCE module functionality such as development or debugging systems should allow a means to assert TRST whenever RESET is asserted as well as a means to assert TRST independently of RESET TRST must be asserted at power up for proper operation Designs that do not require debugging functionality such as consumer products TRST should be tied low Because the Flash memory is programmed through the JTAG OnCE port designers should provide an interface to this port to allow in circuit Flash programming 56F802 Technical Data Rev 9 36 Freescale Semiconductor Part 6 Ordering Information Table 6 1 lists the pertinent information needed to place an order Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts Electrical Design
34. ssertion to First External Address Output tRDA 33T 34T ns Edge sensitive Interrupt Request Width tirw 1 5T ns 1 Inthe formulas T clock cycle For an operating frequency of 80MHz T 12 5ns 2 Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases e After power on reset When recovering from Stop state 3 Parameters listed are guaranteed by design General _____ Purpose UO Pin tic IRQA b General Purpose I O Figure 3 9 External Level Sensitive Interrupt Timing 56F802 Technical Data Rev 9 Freescale Semiconductor 25 3 7 Quad Timer Timing Table 3 11 Timer Timing 2 Operating Conditions Vss Vssa 0 V Vpp Vppa 3 0 3 6 V Ta 40 to 85 C Cy lt 50pF Characteristic Symbol Min Max Unit Timer input period Pin 4T 6 ns Timer input high low period PINHL 2T 3 ns Timer output period PouT 2T ns Timer output high low period POUTHL 1T ns 1 Inthe formulas listed T clock cycle For 80MHz operation T 12 5 ns 2 Parameters listed are guaranteed by design Timer Inputs Timer Outputs Figure 3 10 Timer Timing 56F802 Technical Data Rev 9 26 Freescale Semiconductor Serial Communication Interface SCI Timing 3 8 Serial Communication Interface SCI Timing Table 3 12 SCI Timing Operating Conditi
35. t GPIO lines depending on peripheral configuration The 56F802 controller includes 8K words 16 bit of Program Flash and 2K words of Data Flash each programmable through the JTAG port with 1K words of both Program and Data RAM A total of 2K words of Boot Flash is incorporated for easy customer inclusion of field programmable software routines that can be used to program the main Program and Data Flash memory areas Both Program and Data Flash memories can be independently bulk erased or erased in page sizes of 256 words The Boot Flash memory can also be either bulk or page erased A key application specific feature of the 56F802 is the inclusion of a Pulse Width Modulator PWM module This modules incorporates six complementary individually programmable PWM signal outputs to enhance motor control functionality Complementary operation permits programmable dead time 56F802 Technical Data Rev 9 Freescale Semiconductor 5 insertion and separate top and bottom output polarity control The up counter value is programmable to support a continuously variable PWM frequency Both edge and center aligned synchronous pulse width control 0 to 100 modulation are supported The device is capable of controlling most motor types ACIM AC Induction Motors both BDC and BLDC Brush and Brushless DC motors SRM and VRM Switched and Variable Reluctance Motors and stepper motors The PWMs incorporate fault protection with sufficient output driv
36. ta3 Valid Data Active Mode SEI YE SE OE4 PROG ERASE Masi NVSTR Standby L L L L L L L L Read H H H H L L L L Word Program H H L L H L L H Page Erase H L L L L H L H Mass Erase H L L L L H H H 1 X address enable all rows are disabled when XE 0 2 Y address enable YMUX is disabled when YE 0 3 Sense amplifier enable 4 Output enable tri state Flash data out bus when OE 0 5 Defines program cycle 6 Defines erase cycle 7 Defines mass erase cycle erase whole block 8 Defines non volatile store cycle Table 3 6 IFREN Truth Table Mode IFREN 1 IFREN 0 Read Read information block Read main memory block Word program Program information block Program main memory block Page erase Erase information block Erase main memory block Mass erase Erase both blocks Erase main memory block 56F802 Technical Data Rev 9 Freescale Semiconductor 19 Table 3 7 Flash Timing Parameters Operating Conditions Vgg Vssa 0 V Vpp Vppa 3 0 3 6V T4 40 to 85 C Cy lt 50pF Characteristic Symbol Min Typ Max Unit Figure Program time Tprog 20 us Figure 3 4 Erase time Terase 20 ms Figure 3 5 Mass erase time Tme 100 ms Figure 3 6 Data Retention DRET 10 30 years The following parameters should only be used in the Man
37. tor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such cla
38. ual Word Programming Mode PROG ERASE to NVSTR set Tnvs 5 us Figure 3 4 up time Figure 3 5 Figure 3 6 NVSTR hold time Tnvh 5 us Figure 3 4 Figure 3 5 NVSTR hold time mass erase Tnvh1 100 us Figure 3 6 NVSTR to program set up time Tpgs 10 us Figure 3 4 Recovery time Trev 1 us Figure 3 4 Figure 3 5 Figure 3 6 Cumulative program Thv 3 ms Figure 3 4 HV period Program hold time Tpgh Figure 3 4 Address data set up time Tads E Figure 3 4 Address data hold time Tadh Figure 3 4 1 One Cycle is equal to an erase program and read 2 Thv is the cumulative high voltage programming time to the same row before next erase The same address cannot be programmed twice before next erase 3 Parameters are guaranteed by design in smart programming mode and must be one cycle or greater The Flash interface unit provides registers for the control of these parameters 56F802 Technical Data Rev 9 20 Freescale Semiconductor Flash Memory Characteristics IFREN XADR XE Tadh lt m KOK e TDK KSE Tnvs Tprog NvSTR a JR Tpgs Tnvh baa Le a Trev Figure 3 4 Flash Program Cycle IFREN XE YE SE OE MAS1 0 ERASE NVSTR EE Tnvh Trev Terase Figure 3 5 Flash Erase Cycle 56F802 Technical Data Rev 9 Freescale Semiconductor 21 IFREN XADR XE MASI YE SE OE 0 ERASE NVSTR
39. zH 10 10 uA Input current high analog inputs Vin Vppa Jus 15 15 pA Input current low analog inputs Vin Vssa lita 15 15 pA Output High Voltage at IOH VoH Vpp 0 7 V 56F802 Technical Data Rev 9 16 Freescale Semiconductor Table 3 4 DC Electrical Characteristics Continued DC Electrical Characteristics Operating Conditions Vss Vssa 0 V Vpp Vppa 3 0 3 6 V Ta 40 to 85 C Cy lt 50pF Characteristic Symbol Min Typ Max Unit Output Low Voltage at IOL VoL 0 4 V Output source current loH 4 mA Output sink current let 4 mA PWM pin output source current loHP 10 mA PWM pin output sink current Jo 16 Gem mA Input capacitance Cin SH 8 pF Output capacitance Court 12 pF Vpp supply current r Run 80MHz Operation 120 130 mA Run 60MHz Operation 102 111 mA Wait 96 102 mA Stop 62 70 mA Low Voltage Interrupt external power supply Veo 2 4 2 7 3 0 V Low Voltage Interrupt internal power supply VEIc 2 0 2 2 2 4 V Power on Reset VPOR 1 7 2 0 Vv Schmitt Trigger inputs are FAULTAO TCS TCK TMS TDI RESET and TRST Analog inputs are ANA 0 7 XTAL and EXTAL Specification assumes ADC is not sampling PWM pin output source current measured with 50 duty cycle lppt lop IDDA Total supply current for Von Vppa 1 2 3 4 PWM pin output sink current
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