VS_DSP - VLSI Solution
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1. In 1 m 1 101 In In 1 m 1 110 In In m bit reverse 111 In In m n negative 7 6 Addressing Modes The addressing modes and their availability in short and full formats are summarized in Table 14 The addressing modes available in the implementation are controlled by the parameter Addressing mode mask which has enable bits for the modulo bit reversal and reserved addressing modes in the following manner reserved bitrev modulo For the details of how the modulus mode works see Chapter 3 1 2 7 7 Constant Loading The additional fields in the constant load instruction LDC look like 27 65 0 immediate register The immediates are assumed signed and will be sign extended if the register is wider than the immediate In case there are more bits in the immediate than in the register to be loaded the LSB part is taken The register number is encoded as in the full addressing load stores shown in Table 10 Version 4 3 2014 03 05 54 GIN LSI VS DSP 7 INSTRUCTION CODING Table 14 Addressing mode summary Mode full move code short move code Ta parameter Linear post inc dec In srrr0000RRRRRR srrrORRR 1 1 srrr0001RRRRRR N A I 2 srrr0010RRRRRR N A T 3 srrr0011RRRRRR N A I 4 Srr2. GIN LSI VS DSP VSDSP USER S MANUAL Revision History Rev Date Author Description 4 3 2014 03 05 HH Added details into saturation S and integer 1 mode bit descriptions removed outdated informa tion reformatted document 4 2 2008 03 14 PO Cleaned up version for software developers Version 4 3 2014 03 05 GIN LSI VS DSP This document 1998 2014 VLSI Solution Oy Information furnished by VLSI Solution Oy is believed to be accurate and reliable How ever no responsibility is assumed by VLSI Solution Oy for its use Specifications are subject to change without notice All rights reserved No part of this manual may be reproduced in any form or by any means without permission in writing from the copyright owner The descriptions contained herein do not imply the granting of license to make use or sell equipment constructed in accordance therewith Version 4 3 2014 03 05 GIN LSI VS DSP CONTENTS Contents 1 Introduction 8 2 Programming Model 9 2 1 Datapath PIT 10 Boe CDU MT 11 2 3 Multiplier 64 paras ea aa op ap a e 11 2 4 Barrel Shifter wo es iva ao a a a a 12 25 Guard Bit Registers i o od he ee eee EO eee ew MAS 12 26 Flags and Mode Bits sa 6 6 ww ces doy ee e Oe we Sa aw OR 13 2 6 1 Saturation S De eee ee QUE ADS 13 26 2 Integer l ssi wate d bd wee E dE eee REE Ree 13 2 6 9 Rounding R ss smu sms RUE Hed BOR E S E RR ORE Os 14 26
3. 6 3 1 Loop Register Restrictions 44 6 3 2 Conditional Jump Restrictions 45 ruction Coding 46 General Instruction Composition o oo 46 Oppode PIO lt uste saorad eed aa EOS aa 46 Control Instructions cs o oo GEES ethos o nme 46 Arithmetic Operands llle 49 Move ENCOdING vied pa tica y A TE ee dido e Dc ee 51 Addressing Modes i 2 wo dw ER a A oo 99 Constant Loading ass poa etorri ene Oe we a od E 54 4 3 2014 03 05 GIN LSI VS DSP CONTENTS 8 Contact Information 56 Version 4 3 2014 03 05 5 GIN LSI VS DSP LIST OF FIGURES List of Figures 1 VS DSP General Architecture 8 2 Processor programming model e e 9 9 Vo DSP datapath ss sp avi esca eps Aog ae A X xum Sd ws 10 Version 4 3 2014 03 05 6 GIN LSI VS DSP LIST OF TABLES List of Tables 1 Jump conditions ds x oot m ew oe ke ee kw ee oe ON 30 2 Operation Codes 6a a UOCE eR s Cp SKS 47 3 Control Instructions aros cepas eee ao a Rha E bd cad 47 4 ALU operand encoding o 002 eee 49 5 ALUTESUICODIMO bas UE e A SA AES 49 B MURCDCIANG aver 13 939 ua 3 90 23778 10 6 a E ee ae 50 MBM uw bx RU xm a ee dra dl a 50 8 Single operand ALU instructions 2 2 51 9 Registers in short move 52 10 Registers in full move 2 20000 e eee 53 11 Load Store codi
4. memory and registers During the access the instruction data and address buses are not available for instruction fetches The instruction is forced to NOP PC update and LE compare are supressed Op1 is A B C or D Op2 is In The next instruction can not be a change of flow instruction Coding parallel move 31 17 16 109 65 0 arithmetic opcode 0010101 srrr ppppRR RR Opi rrr Op2 s 1 store 0 load pppp post modification 7 7 or In Version 4 3 2014 03 05 34 GIN LSI VS DSP 6 INSTRUCTION SET REFERENCE LOOP Start a hardware loop delayed LOOP Opl addr Opl 5 LC addr gt LE PC 2 LS Flags L 0 This instruction starts a hardware loop The instruction carries a register number and an absolute loop end address which can be calculated by the assembler The LE indicates the address of the last instruction within the loop body The loop start is implicitly the second instruction from the LOOP instruction See section 5 2 for details Note the one delay slot associated to this instruction Coding 31 28 2726 25 22 21 6 554 0 0010 01 absolute address dirrrrr rrrrr Opi loop count nn nn absolute loop end address d don t care bit Version 4 3 2014 03 05 35 GIN LSI VS DSP 6 INSTRUCTION SET REFERENCE LoL Logical shift left LSL Op2 An for eachi bits 1 Op2 i gt Anli 1 0 gt A 0 Flags Z N V E C 0p2 bits 1 The instruct
5. s 1 store 0 load r address register p post modification mode R move source destination register In the double full move the 14 bit fields come directly after the instruction Version 4 3 2014 03 05 51 GIN LSI VS DSP 7 INSTRUCTION CODING 27 1413 0 srrrppppRRRRRR SrrrppppRRRRRR X full move Parallel move can be either one full move two short moves register to register move Y full move long X move or I bus move The coding of parallel moves is 16 1413 0 ObOsrrrppppRRRRRR full move b bus 0 X 1 Y 1615 87 0 1jsrrrpRRR srrrpRRR X short move 16 14131211 Y short move 0 001 00 ssssssdddddd 16 1413 109 reg to reg move Y bus 0 001 0100 srrrRRRrRRR 16 1413 109 long X move 0 001l0101srrrppppRR I bus move Table 9 Registers in short move Binary code Register 00a AO A1 Ola BO seo BI 10a cl 11a DD 2 4 DI The coding of the store load bit is given in Table 11 The rrr register is the number of the desired address register The src dest register number RRR RRR is given in Table 10 Source and target and the addressing mode in Table 12 See also section 7 6 for further description of the addressing modes available The post modification pppp is a four bit two s complement number 7 register The code
6. 0000 0000 1001 ONES F FFFF FFFF 1010 reserved reserved 1011 P S P1 PO 1100 A A2 A1 A0 1101 B B2 B1 BO 1110 C C2 C1 C0 1111 D D2 D1 DD Table 5 ALU result coding Binary code 16 bit register 40 bit register 000 AO reserved 001 A1 A 010 BO reserved 011 B1 B 100 CO reserved 101 C1 C 110 DO reserved 111 D1 D Table 4 ALU operand gives the encoding of Op1 and Op2 of the ALU fields alu op1 amp alu op2 S denotes sign extension Table 6 Mul operand gives the encoding of fields mac op1 and mac op2 Version 4 3 2014 03 05 49 GIN LSI VS DSP 7 INSTRUCTION CODING Table 6 Mul operand Binary code register 000 AO 001 A1 010 BO 011 B1 100 CO 101 Ci 110 DO 111 D1 The opcode of single operand arithmetic and logic instructions ABS LSR and MUL is encoded in the first operand field The encoding is 27 24 23 20 19 17 single opcode alu op2 alu result In MAC 27 25 24 23 22 20 19 17 mul opi mode mul op2 alu result In MUL 27 25 24 23 22 20 19 17 MUL opcode mode mul op2 mul opi Table 7 Mul mode Binary code op1 op2 00 signed signed 01 signed unsigned 10 unsigned signed 11 unsigned unsigned Table 7 Mul mode gives the encoding of the mode field The result field encoding is shown in Table
7. C gt A msb Flags Z N V E C op2 0 The instruction shifts right by one position The LSB bit is fed to carry and carry is fed into the MSB bit The operand Op2 is encoded as described in Table 4 ALU operand and the result coding in Table 5 Coding 31 28 27 24 23 2019 1716 0 1111 0011 rrrriAAA parallel move rrrr Op2 AAA target register MAC Multiply accumulate MAC Op1 Op2 An An P An Opl x Op2 P Flags Z N V E C The instruction performs one multiplication and adds the result of the previous multipli cation P to a register The multiplication operands are considered signed or unsigned see MUL multiplication mode and possible saturation are controlled by the appropriate mode bits Coding 31 28 27 24 23 2019 1716 0 OiOi1 rrrm mRRR AAA parallel move rrr Op1 RRR Op2 AAA target register mm data format MSU Multiply subtract MSU Op1 Op2 An A P gt An Opl x Op2 gt P Flags Z N V E C The instruction performs one multiplication and subtracts the result of the previous multiplication P from a register The multiplication operands are considered signed or unsigned see MUL Coding 31 28 27 24 23 2019 1716 0 0111 rrrmmRRRIAAA parallel move rrr Op1 RRR Op2 AAA target register mm data format Version 4 3 2014 03 05 37 GIN LSI VS DSP 6 INSTRUCTION SET REFERENCE MUL Multiply
8. Loop L 4 44 56 crop ds Eos RUE Rok dS ee RE 14 20 0 BRE us burma ae n R NR OR ar diede e cta dp e BRE 14 2 6 6 Negative N saca See Seb eee 9o UE RR d 14 2 6 7 Overflow V a ok eod osse T o Rios ie nd 14 28 0 9 EXIBISIBIHE s s ss EE a SEE e Os 14 2 6 9 CAMAS PEE 14 3 Data Address Generator 15 3 1 Post modification Modes a ma amora 262 e ee a n 15 3 1 1 Linear Post Increment Decrement 16 3 1 2 Modulo Post Increment Decrement 16 3 1 3 Bit Reversal gibis we de e ee de ww 17 4 Program control 18 El PCR eke ee owe ee Oe om EB ee ee ee A 18 Version 4 3 2014 03 05 3 O 4 2 4 3 4 4 4 5 4 6 VLSI VS DSP CONTENTS 5 Control Flow 5 1 5 2 5 3 5 4 5 5 6 Inst 6 1 6 2 6 3 7 Inst 7 1 7 2 7 3 7 4 7 5 7 6 7 7 Version LRO io dl i A a ae a eg de de 18 nC CT 19 MRO zou aca ded we rox wie RO s e E efe de up T e de Re ee ets 19 IPRO PRI o e aa dE om x wok 4 a ER Ox X ER OX X Rod 19 ES LE EC a ams ds we mox ox e Be m m e Ba Rm we e dex m uk 20 21 JUMPS y abs Sado dk he Hob boom el us 21 LOOPS green PITT 21 System IT 21 nis gs daa a a ps Aba a A 22 5 4 1 Interrupt Routines lt lt 22 gu p y Whe rs A e RA ob in 23 ruction Set Reference 24 list of IMSMUCHONS meus a a A e A o 2 N 24 Instruction Descriptions tos sis car e eee eee ee we wa 25 Instruction Sequence Restrictions 44
9. VS DSP 6 INSTRUCTION SET REFERENCE SUBC Subtraction of two operands with carry SUBC Op1 Op2 An Opl Op2 C A Flags Z N V E C The operand coding is shown in Table 4 ALU operand and the result coding in Ta ble 5 Coding 31 28 27 24 23 2019 1716 0 1001 RRRR TTrrrAaArn A parallel move RRRR Op1 rrrr Op2 AAA target register XOR Bitwise logic XOR operation XOR Opl Op2 A for eachi Opl i Op2 i gt Anli Flags Z N V 0 E C 0 The operand coding of Op1 and Op2 is shown in Table 4 ALU operand and the result coding in Table 5 XOR has also been used to implement NOT Coding 31 28 27 24 23 2019 1716 0 1101 RRRRjrrrriAAA parallel move RRRR Opt rrrr Op2 AAA target register Version 4 3 2014 03 05 43 GIN LSI VS DSP 6 INSTRUCTION SET REFERENCE 6 3 Instruction Sequence Restrictions There are certain sequences of instructions which due to the pipelined execution would produce undetermined results These sequences are either flagged as errors by the software tools or masked off by the hardware 6 3 1 Loop Register Restrictions When either the LE LC or LS register is loaded from memory with a LDX or LDY instruc tion the loop end comparison is not done This means that loop registers can not be loaded by instruction whose address is LE 2 If this is done further loop rounds are ignored and the execution continues li
10. a0 16 3 VS DSP STY mrO i6 41 STY 1r0 16 1 STY b2 16 1 STY d2 16 1 STY al 1671 STY a 16 import _CInterrupt CALL _CInterrupt LDC 0x200 mr0 LDX 16 a0 RESP a0 al LDX LDX LDX LDX LDC LDY RETI 16 80 i6 c2 16 82 16 15 3 3 3 3 3 LDY i6 1 a1 LDY i6 1 a1 LDY i6 1 d2 LDY i6 1 b2 LDY i6 1 1r0 INT GLOB ENA i7 16 mrO 5 CONTROL FLOW If registers in X space switch LDX and LDY C language interrupt type void CInterrupt void Must occur after add null p a otherwise unexpected things may happen 1f registers in X space switch LDX to STX STY i7 i7 LDX i6 1 i7 If regs in X switch STY LDX with STX LDY When an interrupt is taken the interrupt controller automatically disables all interrupts Writing to the memory mapped register INT GLOB ENA enables the interrupts The interrupts must be disabled during the RETI instruction execution and they will therefore be enabled in its delay slot The RETI will also clear the L flag and the restoring of MRO must therefore come before it if the flag is not cleared by the user 5 5 Halt In HALT the processor waits until an interrupt occurs The execution pipeline is stopped When an interrupt occurs the processor executes 3 instructions after the HALT instruc tion before executing the first interrupt instruction If the interrupt state machine is n
11. 0 e ldc 8191 10 ldy ii1 a0 load a0 post modification by 8191 3 1 2 Modulo Post Increment Decrement In modulo modification the modified address is kept inside the circular buffer This requires that the buffer start address is aligned to a power of two boundary according to the buffer size There are four different modulo modes The most used ones are the 1 and 1 updates masks 0x8000 and 0xa000 The lower bits of In give the size of the modulo buffer minus one e ldc 0x8000 BUFSIZE 1 il ldx i0 null no load post modification by 1 modulo BUFSIZE e ldc 0xa000 BUFSIZE 1 i1 ldx i0 null no load post modification by 1 modulo BUFSIZE The other modulo modes can modify the address by larger steps than 1 but they have restrictions on what the buffer size can be If the buffer size is 1 64 the modification can be 64 63 If the buffer size is a multiple of 64 from 64 to 4096 the modification can be 128 127 e ldc 0x2000 STEP amp 0x3f 6 BUFSIZE 1 amp 0x3f i1 ldx i0 null post modification by STEP modulo BUFSIZE e ldc 0x4000 STEP amp 0x7f 6 BUFSIZE 64 1 amp 0x3f i1 ldx i0 null post modification by STEP modulo BUFSIZE Version 4 3 2014 03 05 16 GIN LSI VS DSP 3 DATA ADDRESS GENERATOR 3 1 3 Bit Reversal In bit reversal addressing calculated addresses are kept within a buffer length 2 and when calculating the updated address carry is propagated towards the LSB
12. 1 PSeudo registers NULL and ONES are also available and contain all zeros and all ones respectively NULL and ONES are considered to be 16 bit registers for the purpose of determining the operation width The 40 bit operands are A B C and D P is only available as operand2 The register A is formed by concatenating A2 A1 A0 AO is the Isb part For 40 bit calculations also 16 bit registers are available as the other operand In this case the register is used as the middle part of the operand The Isb end is padded with 16 zeros and the sign is extended to the guard bits For example if register AO is used with an 40 bit operand the operand is xx 40 0000 xx means sign extension bits The result register of 40 bit operation must be one of A B C or D The result register of a 16 bit operation is one of the 16 bit registers AO D1 2 3 Multiplier The multiplier is a 16 x 16 signed unsigned integer fractional saturating unsaturating multiplier Both inputs can be interpreted either as signed or unsigned numbers to facilitate multi precision operations Results are written into a 32 bit P register The P register can be saved by executing ADD NULL P A at which time potentional fractional mode shift to left by 1 bit and saturation mode is applied The high and low parts will reside in the high and low parts of the target accumulator respectively If both fractional mode and saturation mode is on the result of signedxsigned mul
13. 1 LE less than or equal to zero N V S Z 1 010001 CC carry clear C 0 010010 EC extension clear E 0 010011 VC not overflow V 0 010100 NC not negative N 0 010101 ZC not zero Z 0 011000 GE greater than or equal to zero N V 5 20 011001 GT greater than zero N V S Z 0 Version 4 3 2014 03 05 30 NA JMPI Jump ignore delay slot increment index register VS DSP 6 INSTRUCTION SET REFERENCE JMPI addr Op1 n addr gt PC Opl n gt Opl O gt IPRO Identical to normal jump instruction but ignores the instruction in the delay slot a NOP is executed instead and jumps to zero page Also the index register specified is Flags no change optionally modified identical to LDX Op1 n NULL This instruction is used in interrupt vector jump table Do not use this instruction in normal code if interrupts are enabled Coding 31 28 27 24 2322 21 6554 32 0 0010 1010 absolute address mm rrr rrr address register dd don t care mm address mode 00 no update 01 1 11 1 Version 4 3 2014 03 05 31 GIN LSI VS DSP 6 INSTRUCTION SET REFERENCE JRcc Conditional delayed jump to the address in link register 0 JRcc if cond LRO PC Flags L 0 JRcc Conditional delayed jump to the address in link register 0 JRcc Op1 if cond LRO PC Opl IPRO Flags L 0 The JRcc instruction can be used for returns
14. 2 update Op1 Flags no change Coding double full moves 31 28 27 14 13 0 0011 X full move Y full move Coding parallel full move 31 28 27 24 23 2019 1716 1211 87 43 0 ooooldddd lddddddd ObOFF FFFF FFFF FFFF 0000 opcode allowing parallel moves dddd don t care b bus X Y 0 1 FFFFF full move bits of X Y Coding parallel short moves 31 28 27 24 23 2019 1716 12 11 87 43 0 oooojdddd dddd ddd ixxxx XXXXx YYYYYYYY xxxx short move bits of X yyyy short move bits of Y Version 4 3 2014 03 05 33 GIN LSI VS DSP 6 INSTRUCTION SET REFERENCE LDX Load register from X memory with 32 bit address LDX 002 Op3 Opl X Op2 Op3 gt Opl Flags no change STX Store register in X memory with 32 bit address ST X Opl Op2 Op3 Opl gt X Op2 Op3 Flags no change Load or store a register from or to X memory This instruction uses two index registers to generate a long 2xdataaddress memory address When Op2 is In Op3 is the corresponding modifier register In Coding parallel move 31 17 16 109 65 0 arithmetic opcode 0010100 srrr RRRRRR RRRRRR Opt rrr Op2 s 1 store 0 load LDI Load register from memory LDI Op2 Opl I Op2 gt Opl update Op2 Flags no change STI Store register to memory STI Opl Op2 Op1 gt I Op2 update Op Flags no change Transfer data between
15. 2014 03 05 27 GIN LSI VS DSP 6 INSTRUCTION SET REFERENCE ASR Arithmetic shift right ASR Op2 An for eachi gt 0 Op2 i gt Ali 1 Op2 msb gt A msb Flags Z N V E C op2 0 The instruction shifts right by one position The LSB bit is discarded and MSB of the source registers is fed into the MSB bit of the result 31 28 27 24 23 2019 1716 0 1111 0001 rrrriAAA parallel move Coding rrrr Op2 AAA target register EXP Count leading bits EXP Op2 A Flags Z N 0 V 0 E 0 C 0 Count leading zeros or ones according to MSB of the source The result is a unsigned integer in whose range of possible values are from 0 to 2n g If Op2 is 0 then result is O Note Result is always written to 16 bit register Note2 This instruction can be used in conjunction with ASHL instruction to specify the shift amount needed for normalization The operand coding is found in Table 4 ALU operand and the result coding in Table 5 Coding 31 28 27 24 23 2019 1716 0 1111 0101 rrrriAAA parallel move rrrr Op2 AAA target register Version 4 3 2014 03 05 28 GIN LSI VS DSP 6 INSTRUCTION SET REFERENCE CALLGOG Conditional delayed jump and save return address CALL addr PC LRO if cond addr PC Flags L 0 Identical to normal jump instruction but PC is saved to LRO This instruction replaces the sequence J addr LDC 9 1 LRO which is used in subro
16. 40 bit or 16 bit mode The width depends on the operands If one of the operands is 40 bits wide the opera tion is performed in 40 bits otherwise in 16 bits The multiplier unit is a 16 x 16 bit signed unsigned integer fractional saturating unsaturating multiplier Multiplier inputs can be AO A1 BO B1 CO C1 DO D1 The result goes to a 32 bit register P which can be used as the second ALU operand in 40 bit arith metic and is also used with MAC or MSU The 16 40 bit ALU implements the arith metic and logic instructions The ALU produces negative carry overflow zero and extension flags There is also a 16 40 bit barrel shifter Two internal data buses connect the dat apath registers to other registers and mem ories Version 4 3 2014 03 05 2 PROGRAMMING MODEL fract int shift saturation NULL ONES Figure 3 VS_DSP datapath GIN LSI VS DSP 2 2 ALU 2 PROGRAMMING MODEL The ALU can calculate either 40 bit or 16 bit operations The width depends on the operands if one of the operands is 40 bits wide the operation is 40 bits and the result is stored to a 40 bit register If both operands are 16 bits the operation and result are also 16 bits and the result is stored to a 16 bit register Exceptions to these rules are EXP ASHL and RND The result of EXP and RND is always 16 bit wide and Op2 of ASHL is always an 16 bit register The 16 bit operands are AO A1 BO B1 CO C1 DO D
17. 5 Table 4 ALU operand gives the encoding of Op2 of the ALU field alu op2 The single operand opcode encoding is given in Table 8 Version 4 3 2014 03 05 50 GIN LSI VS DSP 7 INSTRUCTION CODING Table 8 Single operand ALU instructions Binary code Operation 0000 ABS 0001 ASR 0010 LSR 0011 LSRC 0100 NOP 0101 EXP 0110 SAT 0111 RND 1000 ee reserved 1101 111X MUL 7 5 Move Encoding The move instructions are LDX LDY LDI STX STY and STI the X Y and denoting the desired data bus to be used There can be a maximum of two moves loads or stores in parallel one operating on the X bus and the other on Y bus Constant loading is described separately in section 7 7 There are two kinds of moves full moves and short moves The short moves use a restricted set of registers and restricted addressing modes The full moves have all registers and all addressing modes available The parallel moves can be done together with arithmetic operations and can either be one full or two short moves Long X and l bus moves are only available as parallel moves Double full move instruction has two full moves but can not be executed in parallel with other instructions The full move field is always the following 14 bit control field 13 109 65 0 STIIPPPPIRRRRER In short moves the move field is as follows 13 109 65 0 srrrip000 000RRR
18. 8 is for the additional address post modification modes found in In The In is the index register the number of which is generated by inverting the LSB bit of the number of register In The post modifications by the In are defined in Table 13 Version 4 3 2014 03 05 7 which is added to the address 52 GIN LSI VS DSP 7 INSTRUCTION CODING Table 10 Registers in full move Binary code Register 00000a AO A1 00001a BO B1 00010a CO Ci 00011a DO D1 001000 LRO 001001 LR1 001010 MRO 001011 reserved 001100 NULL update index reg amp flags 001101 LC 001110 LS 001111 LE optional 010rrr IO 17 100000 A2 100001 B2 100010 C2 100011 D2 100100 Move NOP no updates 100101 ee reserved 111101 111110 IPRO 111111 IPR1 Table 11 Load Store coding Binary code Mode 0 load 1 store Table 12 Addressing Modes Binary code Mode rrrpppp indirect In with post modify by pppp 7 7 rrr1000 indirect In with post modification specified in In Version 4 3 2014 03 05 53 GIN LSI VS DSP 7 INSTRUCTION CODING Table 13 Modifications by the In register Binary code Modification 000 In In m m positive 001 In In m 12 6 m 5 0 1 01 In In m 13 6 m 5 0 x 64 64 100 In
19. MUL Op1 Op2 Opl x Op2 P Flags no change Performs one multiplication The operands can be signed or unsigned multiplication mode and possible saturation are controlled by the appropriate mode bits There are different mnemonics for different format operands The data format can be Op1 signed Op2 signed MULSS Op1 unsigned Op2 signed MULUS Op1 signed Op2 un signed MULSU or Op1 unsigned Op2 unsigned MULUU The format SS is the default and MULSS can thus be written as plain MUL Coding 31 28 27 24 23 2019 1716 0 1iiij 1itm mRRRi rrr parallel move rrr 0p1 RRR 0p2 mm data format MVX MVY Register to register move MV X Op1 Op2 Opl gt Op2 Flags no change Moves a register to another register using X or Y data bus In parallel MVX any register can be used as a source or target The source is read on X bus switched to Y bus and written from Y bus In double MVX MVY two moves can be performed with a single instruction The source and destination registers must be from different execution units ALU DAG PCU Coding parallel move 31 17 16 12 11 65 0 arithmetic opcode 00100 ssssssdddddd Coding double move 31 28 27 24 23 18 17 12 11 65 0 0010 1011 SSSSSSIDDDDDD ssssss dddddad n reserved ssssss Y source dddddd Y tar get SSSSSS X source DDDDDD X target Version 4 3 2014 03 05 38 GIN LSI VS DSP 6 IN
20. STRUCTION SET REFERENCE NOP No operation NOP no ef fect Flags no change A parallel move NOP is a load operation to NOP register A total NOP is LDC to NOP Coding 31 28 27 24 23 2019 1716 0 1111 0100 ddddiddd parallel move ddd don t care NOT Bitwise logic NOT operation NOT Op2 An for each i Op2 i gt Anli Flags Z N V 0 E C 0 The operand Op2 coding is shown in Table 4 ALU operand the target can be one of the registers In hardware this is equal to an XOR with register ONES Coding 31 28 27 24 23 2019 1716 0 1101 1001 rrrriAAA parallel move rrrr Op2 AAA target register OR Bitwise logic OR operation OR Op1 Op2 A for each i Opl i Op2fi gt A i Flags Z N V 0 E C 0 The operands are encoded as described in Table 4 ALU operand and the result coding in Table 5 The target is one of the registers Coding 31 28 27 24 23 2019 1716 0 1100 rrrriRRRRIAAA parallel move rrrr Op1 RRRR Op2 AAA target register 2This instruction is implemented as a single instruction software macro Version 4 3 2014 03 05 39 GIN LSI VS DSP 6 INSTRUCTION SET REFERENCE RESP Restore P register RESP Op1 Op2 Opl gt P0 Op2 gt P1 Flags no change This instruction restores the P contents from two arithmetic registers The saving of the P shall be done as described in section 2 3 The operands are en
21. The lower boundary of the buffer is a multiple of 2 The boundary is decided by finding the highest 1 bit in In 12 0 3 MSBs of In should contain 110 to select bit reversal addressing LSBs of In should contain the reversed adder value normally 2 In In In 12 0 propagate carry towards LSB Example 64 point k 6 FFT in buffer 0x3000 0x303f getting the next entry after 0x3030 15 87 0 In 00110000 00110000 0x3030 Tn 110 0000000100000 0xc020 updated In 00110000 00001000 0x3008 The previous example shows the normal usage although other values than power of two are possible The next example shows how to go backwards instead of forwards by setting In 12 0 to 2 1 instead of 2 1 Example 64 point k 6 FFT in buffer 0x3000 0x303f getting the previous entry before 0x3030 15 87 0 tn 00110000 00110000 0x3030 Tn 110 0000000111111 OxcO3f updated In 00110000 00010000 0x3010 Version 4 3 2014 03 05 GIN LSI VS DSP 4 PROGRAM CONTROL 4 Program control Program control unit ecu performs instruction fetch and decode control flow changes and interrupt fetching In addition to the program counter PC program control unit has two link registers which are used for indirect jumps LRO and LR1 Mode register MRO holds the mode and flag bits Loop control has three registers LS LE and LC Program counter is not di
22. address instead of PC address if condition cc is true LRO is used to save the return address for subroutine calls so executing JRcc at the end of the subroutine returns to the caller If nested subroutines are needed the previous LRO must be saved and restored by the caller Version 4 3 2014 03 05 18 GIN LSI VS DSP 4 PROGRAM CONTROL 4 3 LR1 LR1 is used in interrupt returns RETI causes instruction to be fetched from LR1 address instead of PC address PC is copied to LR1 on interrupts If nested interrupts are needed LR1 must be saved and restored by the interrupt service routine See section 5 4 1 for the save and restore routines 4 4 MRO MRO is the processor mode status flag register 15 87 0 dddddSIRiLddZNVEC mode bits flags Bit flag Meaning saturation mode integer 1 fractional 0 mult mode rounding mode loop flag zero flag negative flag overflow flag extension flag carry flag oO m lt Z N r lt D 0 In the end of an interrupt MRO is restored from the stack Thus explicit moves override the evaluation of flags The mode bits and flags are described in more detail in section 2 6 4 5 IPRO IPR1 IPRO is the instruction page register and is used to implement 32 bit code address space It holds the upper 16 bits of instruction address IPRO can be changed by JRcc or JMPI instruction In interrupts IPRO is copied to IPR1 at i
23. ail sales vIsi fi URL http www visi fi For technical support or suggestions regarding this document please participate at http www vsdsp forum com For confidential technical discussions contact support visi fi Version 4 3 2014 03 05 56
24. coded as multiplica tion operands Coding 31 28 27 24 23 20 19 16 15 12 11 87 43 0 0010 0010 dRRRirrrdidddd dddd dddd dddd rrr Op1 RRR Op2 ddd don t care bits RETI Delayed return from interrupt RETI LR1 PC Flags L 0 RETI Delayed return from interrupt RETI Opl LR1 PC Opl gt IPRO Flags L 0 The RETI instruction is used for returns from interrupts similarly as JRcc is used for returns from subroutines For description of interrupt mechanism and the correct use of RETI see chapter 5 Coding 31 28 27 24 2322 0 0010 00010 31 28 27 24 2322 98 65 0 0 0101000111 rrr rrr Op1 IO I7 Version 4 3 2014 03 05 40 GIN LSI VS DSP 6 INSTRUCTION SET REFERENCE RND Round and saturate a 40 bit ALU register to 32 bits RND Op2 An Flags Z N V E 0 C 0 Round long ALU register to top 24 bits If mode bit R is set uses convergent 0 rounding round exact x 5 values towards even numbers otherwise round towards 0 After the number is rounded it is saturated to the lowest 16 bits of the intermediary 24 bit result The result is a signed integer Note Result is always written to 16 bit register The operand coding is found in Table 4 ALU operand and the result coding in Table 5 Coding 31 28 27 24 23 20 19 1716 0 1111 0111 rrrriAAA parallel move rrrr Op2 AAA targe
25. e flags that are part of the condition must be unaltered in the preceding instruction Other flags can be modified 5 2 Loops The loop mechanism has three registers which are loop start register LS loop end register LE and loop count register LC Change of flow instructions can not be at loop end address or immediately before that LOOP instruction starts a hardware loop LOOP instruction has one delay slot i e loop start address is LOOP 2 This results from the fact that instruction at LOOP 1 delay slot is fetched before loop registers are updated by LOOP instruction Loop can also be initiated by setting LS LE and LC to appropriate values When the instruction fetch address equals LE the value of LC is checked If LC is not equal to zero it is decremented by 1 and PC is loaded with LS If LC is equal to zero executing continues linearly from the next instruction 5 3 System Reset System reset forces the processor to a known reset state After reset is released the processor starts executing instructions from reset address onwards All registers except LE and PC are zeroed on reset LE is set to all ones PC is set to reset vector normally 0x4000 Version 4 3 2014 03 05 21 GIN LSI VS DSP 5 CONTROL FLOW 5 4 Interrupts Interrupts are vectored using a jump table The external interrupt peripheral supplies an interrupt vector to core The vector is an address in the range 0x20 0x3f These addresses must hold a jump
26. enerate core clock Version 4 3 2014 03 05 8 GIN LSI VS DSP 2 PROGRAMMING MODEL 2 Programming Model The processor programming model is shown in Fig 2 The processor contains arith metic address and control registers n n pa pa P1 PO LC PRI g da da D2 D1 Do le 17 LE iPRO ce C1 CO 14 15 LS PC B2 B1 BO 12 13 LR1 A2 A1 AO 10 H LRO MRO Figure 2 Processor programming model Arithmetic registers are the 16 bit registers AO A1 BO B1 CO C1 DO D1 andthe 8 bit guard bit registers A2 B2 C2 D2 The multiplier pipeline register PO P1 is also shown There is no guard bit register for P because a single multiplication result always fits into 32 bit register The arithmetic registers can be used either as 16 bit registers mentioned above or as 40 bit registers A B C D P Address registers are the 16 bit index registers IO I1 IT Control registers are the program counter PC link registers LRO LR1 and mode register MRO Loop hardware registers are LS LE LC and page registers IPRO IPR1 Version 4 3 2014 03 05 9 GIN LSI VS DSP 2 1 Datapath This picture shows the VSDSP datapath The ALU has eight 16 bit arithmetic reg isters AO A1 BO DO D1 and four 8 bit guard bit registers A2 D2 These can be combined to form 40 bit accumu lators A B C and D Calculation can be performed in
27. esult is set the flag is set Otherwise the flag is cleared 2 6 7 Overflow V Set if an arithmetic overflow occurs in the ALU result Otherwise cleared 2 6 8 Extension E If the ALU is operating in the 40 bit mode and bits 39 31 are all the same either all ones or all zeros the flag is cleared Otherwise the flag is set If the ALU is operating in the 16 bit mode the flag is cleared 2 6 9 Carry C If a carry is generated in an addition or a borrow is not generated in a subtraction the flag is set The flag is set also in ASR LSR and LSRC if the LSB bit of the operand is logical 1 Otherwise the flag is cleared Version 4 3 2014 03 05 GIN LSI VS DSP 3 DATA ADDRESS GENERATOR 3 Data Address Generator The data address generator uses index registers IO I7 to generate X and Y data bus addresses each cycle Each register In has a corresponding register pair In You get In by inverting the LSB bit of the number of register In For example the pair of 13 is 12 and the pair of 12 is 13 Any In can be used as a X or Y data bus address If needed In specifies a post modification for In 32 bit X addresses are formed by concatenating In and In but these are only useful with chips that have external data buses 3 1 Post modification Modes There are two post modification modes specified in the instruction post modification by 7 7 or post modification by In ldx i0 a0 load a0 no p
28. from subroutines as well as for other jumps with run time calculated addresses The return addresses are typically loaded by an LDC instruction Flags and their combinations can be used as jump conditions as shown in Table 1 Jump conditions The instruction immediately before the JRcc must not change the flags that are used in the jump condition Other flags can be changed Unconditional return can be done with the always condition Note the one delay slot associated to this instruction Coding 31 28 27 24 2322 65 0 0010 0000 0 condition 31 28 27 24 2322 98 65 0 0010 00001 rrricondition cccccc condition rrr Op1 IO I7 LDC Load constant to a register LDC constant Opl constant Opl Flags no change The register Op1 coding is shown in Table 10 Target full move The assembler understands numbers in different bases e g hexadecimal decimal binary while the immediate is finally coded in binary format A single constant load can be done in an instruction and no parallel arithmetic can be used The constant is LSB aligned and sign extended if needed Coding 31 2928 22 21 65 0 000 constant RRRRRR RRRRRR Op1 Version 4 3 2014 03 05 32 GIN LSI VS DSP 6 INSTRUCTION SET REFERENCE LDX Load register from X memory LDX Opl Op2 X Op1 gt Op2 update Op1 Flags no change LDY Load register from Y memory LDY Op1 0p2 Y Op1 Op
29. from the P register Normally a zero will be fed into the LSB If saturating to the largest positive value the LSB will be set to one Integer mode must not be changed between multiplication operations MUL MAC MSU and the use of the result ADD SUB Results may be unpredictable Version 4 3 2014 03 05 GIN LSI VS DSP 2 PROGRAMMING MODEL 2 6 3 Rounding R If the rounding mode bit is set RND will round using convergent O rounding otherwise RND will always round towards 0 2 6 4 Loop L Loop flag is needed with 32 bit code space The loop flag is set by the interrupt mech anism to disable loop end detection This prevents false loop end detections when an interrupt causes the execution to transfer to zero page from another page Normally there is no need for the user to set or clear the loop flag e Interrupt sets the loop flag e MRO load can set or clear the loop flag e JR RETI J CALL and LOOP instructions clear the loop flag e JMPI does not affect the loop flag 2 6 5 Zero Z If the ALU is operating in the 40 bit mode and bits 39 0 of the ALU result are all clear the flag is set If the ALU is operating in the 16 bit mode and bits 15 0 of the ALU result are all clear the flag is set Otherwise the flag is cleared 2 6 6 Negative N If the ALU is operating in the 40 bit mode and bit 39 of the ALU result is set the flag is set If the ALU is operating in the 16 bit mode and bit 15 of the ALU r
30. gt Ali Flags Z N V 0 E C 0 The operand coding is found in Table 4 ALU operand and the result coding in Table 5 Coding 31 28 27 24 23 2019 1716 0 1011 RRRRITITrriAAA parallel move RRRR Op1 rrrr Op2 AAA target register ASHL Arithmetic multi bit shift ASHL Op1 Op2 An if Op2 gt 0 Opl lt lt Op2 gt A else Opl gt gt Op2 gt A Flags Z N V E C When Op2 is positive then the source is shifted left Op2 bits Bits shifted out of position 40 are lost but for the last bit is copied to the carry flag Zeros are supplied to the vacated positions on the right When Op2 is negative then the source is shifted right abs Op2 bits Bits shifted out of position O are lost but the last bit is copied to the carry flag Copies of the MSB are supplied to the vacated positions on the left arithmetic shift If a zero shift count is specified the carry bit is cleared Overflow flag is set if MSB is changed any time during the shift operation This can only happen when shifting left Note if the number of shifts exceeds the range of 40 40 or 16 16 for 16 bit source result then the result is undefined Note2 Op2 is always 16 bit register The operand coding is found in Table 4 ALU operand and the result coding in Table 5 Coding 31 28 27 24 23 2019 1716 0 1010 RRRRITrrriAAA parallel move RRRR Op1 rrrr Op2 AAA target register Version 4 3
31. he link register should be saved beforehand in case of a subroutine al ready being executed The return address is calculated at compilation linking time not run time This allows also jumps by loading the link register and then executing the Version 4 3 2014 03 05 46 GIN LSI VS DSP 7 INSTRUCTION CODING Table 2 Operation Codes Binary code Operation Parallel 000X LDC none 0010 Control none 0011 Double moves none 0100 ADD yes 0101 MAC yes 0110 SUB yes 0111 MSU yes 1000 ADDC yes 1001 SUBC yes 1010 ASHL yes 1011 AND yes 1100 OR yes 1101 XOR yes 1110 reserved 1111 Single op instructions yes Table 3 Control Instructions Binary code Operation Sub fields Additional fields 0000dddddddd JRcc condition 0001dddddddd RETI 0010dxxxyyyd RESP X 0p2 y op1 Oinnnnnnnnnn LOOP loop end Isb n loop end msb register loop count 1000nnnnnnnn Jcc n address msb address lsb condition 1001nnnnnnnn CALLcc n address msb address lsb condition 1010nnnnnnnn JMPI n address msb address lsb index reg 1011nnnnnnnn MVX MVY move fields 1101nnnnnnnn HALT 111000000000 ee reserved 111111111111 JRcc instruction The linking can be done also in the delay slot The LR1 loading takes place automatically when interrupt processing is started In the l
32. ill sign extend over the desired value This is usually an issue only in interrupt handlers Version 4 3 2014 03 05 12 GIN LSI VS DSP 2 PROGRAMMING MODEL 2 6 Flags and Mode Bits The processor mode register includes mode bits and status flags The bits affecting or being affected by the datapath are 15 87 0 dddddSIRJLddZNVEC mode bits flags Bit flag Meaning saturation mode integer 1 fractional 0 mult mode rounding mode loop flag zero flag negative flag overflow flag extension flag carry flag O m lt Z N HI D 0 2 6 1 Saturation S If the saturation mode bit is set the ALU operations and register P read operations will saturate their result in case of an over underflow The overflow flag will be set but its interpretation is that saturation has taken place in the ALU If the mode bit is clear the operations will not saturate their outputs and the overflow flag will have its normal meaning Saturation mode must not be changed between multiplication operations MUL MAC MSU and the use of the result ADD SUB Results may be unpredictable 2 6 2 Integer 1 If the integer mode bit is set the multiplier result is interpreted as an integer and thus no re alignment is needed Otherwise the multiplier result is assumed to be a fractional number with two leading sign bits which will be re aligned by a single left shift when read
33. ion 4 3 2014 03 05 25 GIN LSI VS DSP 6 INSTRUCTION SET REFERENCE ABS Absolute value ABS Op2 An Op2 gt An Flags Z N V E C The operand is conditionally negated two s complement operation and placed in the target register The coding of Op2 is given in Table 4 ALU operand and the result coding in Table 5 The absolute value of the minimum integer fraction 1 0 is the maximum integer in the saturation mode Coding 31 28 27 24 23 2019 1716 0 1111 0000 rrrriAAA parallel move rrrr Op2 AAA target register ADD Addition of two operands ADD Op1 Op2 An Opl Op2 An Flags Z N V E C The operand coding is shown in Table 4 ALU operand and the result coding in Ta ble 5 LSL is constructed with ADD Op1 Op1 An Coding 31 28 27 24 23 2019 1716 0 O1OO RRRR rrrr AAA parallel move RRRR Op1 rrrr Op2 AAA target register ADDC Addition of two operands with carry ADDC Op1 Op2 An Opl Op2 C An Flags Z N V E C The operand coding is shown in Table 4 ALU operand and the result coding in Ta ble 5 LSLC is constructed with ADDC Op1 Op1 An Coding 31 28 27 24 23 2019 1716 0 1000 RRRR rrrz AA A parallel move RRRR Op1 rrrr Op2 AAA target register Version 4 3 2014 03 05 26 GIN LSI VS DSP 6 INSTRUCTION SET REFERENCE AND Bitwise AND of two operands AND Op1 Op2 An for each i Opl i Op2 i
34. ion shifts left by one position This instruction is implemented in hardware as ADD Op2 Op2 A Note P is not available as an operand for this instruction Coding 31 28 27 24 23 20 19 1716 0 O100 rrrr rrrr AAA parallel move rrrr Op2 AAA target register Lobo Logical shift left with carry LSLC Op2 An for each i lt bits 1 Op2 i gt Anli 1 C A 0 Flags Z N V E C 0p2 bits 1 The instruction shifts left by one position This instruction is implemented in hardware as ADDC Op2 Op2 A Note P is not available as an operand for this instruction Coding 31 28 27 24 23 2019 1716 0 1000 rrrr jrrrriAAA parallel move rrrr Op2 AAA target register LSR Logical shift right LSR Op2 An for eachi gt 0 Op2 i gt Ai 1 0 gt A msb Flags Z N V E C op2 0 The instruction shifts right by one position The LSB bit is discarded and zero is fed into the MSB bit The operand Op2 is encoded as described in Table 4 ALU operand and the result coding in Table 5 Coding 31 28 27 24 23 2019 1716 0 1111 0010 rrrriAAA parallel move rrrr Op2 AAA target register This instruction is implemented as a single instruction software macro Version 4 3 2014 03 05 36 GIN LSI VS DSP 6 INSTRUCTION SET REFERENCE LORG Logical shift right with carry LSRC Op2 An for eachi gt 0 Op2li gt Anli 1
35. nearly The LDC instruction does not have this restriction and the loop hardware uses the value loaded with an LDC if it is needed on the same cycle Also the LOOP instruction does not have the restriction so single instruction loops are allowed illegal_example ldc loop_endi le ldx 10 Le le comparison not done nop loop_endl nop legal_example ldc 2 1c ldc loop start ls ldc loop end2 1e le comparison is done nop loop end2 nop Version 4 3 2014 03 05 44 GIN LSI VS DSP 6 INSTRUCTION SET REFERENCE 6 3 2 Conditional Jump Restrictions The instruction immediately before the jump instruction JRcc or Jcc must not change the flags that affect the jump condition For example if the jump is a JCC jump if carry clear the instruction immediately before must not change the C flag In practice this means that instruction must not be an ALU instruction X and Y memory accesses can be made since they do not affect the carry clear condition example ldx i0 1 NULL must not change C flag jcc jump_target nop jump delay slot The reason for this restriction is the fact that the jump condition is determined during the decode phase In a normal linear execution the instruction immediately before the jump does not affect the jump The situation is different if the jump instruction is canceled due to an interrupt When execution returns from the interrupt to the normal execution flow the instruc
36. ng avs ire rra E e a e 53 12 Addressing Modes o 53 13 Modifications by the Tn register 0 54 14 Addressing mode summary ss users a go wow x oec E OOo Rs 55 Version 4 3 2014 03 05 7 GIN LSI VS DSP 1 INTRODUCTION 1 Introduction Interrupt arbitrator PROGRAM CONTROL ADDRESS CALCULATION X address ALU Y address ALU Boot loader Peripheral interface X and Y PLL clock generator Program X memory memory Y memory memor y Peripheral devices Figure 1 VS_DSP General Architecture VSDSP consists of these units e Datapath an arithmetic logic unit ALU and a multiplier unit VSDSP also contains a barrel shifter e Data Adaress Calculation Two dedicated address calculation units provide ad dresses for simultaneous operations on X and Y memory buses e Program Control Instruction fetch instruction address generation and instruc tion decode The program control also includes harware loop control e Buses Internal buses transfer data between different units and memories There are also other subsystems that are not part of the core e Memory Internal RAM and ROM e Peripherals Memory mapped peripherals such as interrupt arbiter serial port GPIO timers DA and or AD converters External Bus Switch Some chips have external memory buses e Clock Generator A phase locked loop PLL can g
37. nterrupt cycle 2 Version 4 3 2014 03 05 19 GIN LSI VS DSP 4 PROGRAM CONTROL 4 6 LS LE LC LS holds the loop start address LE holds the loop end address LC holds the loop count LOOP instruction copies instruction fetch address to LS loads LE with loop end address specified in the LOOP instruction and copies LC from the specified register When instruction fetch occurs from LE address and the L flag is not set LC is tested If LC Z 0 it is decremented by one new loop round starts by copying LS to PC If LC 0 fetch continues from the next address LE is initiated with all ones in system reset Version 4 3 2014 03 05 20 GIN LSI VS DSP 5 CONTROL FLOW 5 Control Flow The control flow behaviour follows the three stage pipelining of the processor opera tion The change of flow instructions are all delayed with one delay slot following the instruction There can not be another change of flow instruction in the delay slot In this sense also LOOP is considered as a change of flow instruction in addition to J Jcc JRcc CALLcc and RETI The JMPI instruction is also a change of flow instruction and has the same kind of timing behaviour as other change of flow instructions but the instruction in the delay slot is canceled executed as NOP and can therefore be a change of flow instruction This feature is mostly used in the interrupt vector table 5 1 Jumps Jump conditions are taken from the flags in MRO Th
38. oop instruction there is a register number containing the loop count All registers except the double size accumulators can be used The loop end address is given as Version 4 3 2014 03 05 47 GIN LSI VS DSP 7 INSTRUCTION CODING an immediate at most 20 bits value The loop start address will be loaded automat ically from the PC The loop registers LC LS LE should not be loaded within the two instructions preceding a loop end to avoid implementation dependent ambiguities in the loop behavior In the full size moves the load store operations can use all the addressing modes and all registers These moves do not allow any control operations in parallel See section 7 5 for move encoding RESP is a special instruction to restore the P register The rest of the control instructions are reserved for future extensions Version 4 3 2014 03 05 48 GIN LSI VS DSP 7 INSTRUCTION CODING 7 4 Arithmetic Operands The operands of two operand arithmetic and logic instructions ADD SUB AND OR XOR are encoded in the second field of these instructions The field is composed as follows 27 24 23 20 19 17 alu opi alu op2 alu result Table 4 ALU operand encoding Binary code register composition 0000 AO S A0 0000 0001 Al S A1 0000 0010 BO S B0 0000 0011 B1 S B1 0000 0100 CO S C0 0000 0101 C1 S C1 0000 0110 DO S D0 0000 0111 D1 S D1 0000 1000 NULL 0
39. ost modification ldx 10 6 a0 load a0 post modification by 6 lax 10 7 a0 load a0 post modification by 7 ldx i0 a0 load a0 post modification by TO i e I1 The modification by In i e using uses the most significant bits of In to specify the post modification mode linear post modification modulo post modification and bit reverse In 15 13 Mask Modification 000 0x0000 In In m n positive 001 0x2000 In In m 12 6 m 5 0 1 oix 0x4000 In In m 13 6 m 5 0 x 64 64 100 0x8000 In In 1 m 1 101 0xa000 In In 1 m 1 110 0xc000 In In m bit reverse 111 0xe000 In In m n negative When modulo addressing is used modulo logic keeps the address within a circular buffer The buffer length does not need to be a power of two but the starting address of the buffer must be aligned to the nearest larger or equal power of two The bit reverse modification is useful for FFT and DFT implementations Version 4 3 2014 03 05 GIN LSI VS DSP 3 DATA ADDRESS GENERATOR 3 1 1 Linear Post Increment Decrement Linear post modification can be an immediate 7 7 modification or modification by In In the case of a negative modifier In contains the value in two s complement format e ldx i0 5 a0 load a0 post modification by 5 e ldc 10 i1 ldx i0 null no load post modification by 1
40. ot in the idle state when HALT goes to execution HALT instruction has no effect and is executed like a NOP Version 4 3 2014 03 05 23 CNS VS DSP mm 6 INSTRUCTION SET REFERENCE 6 Instruction Set Reference 6 1 List of Instructions The following table lists all basic and optional instructions The operands of each in struction mode bits affecting the operation and the flags affected are also shown Mnemonic meaning operands result S I RILIZ N V E C ABS absolute value Areg Areg u XIXIXIX x ADD add 2xAreg Areg ul x x x x x ADDC add with carry 2xAreg c Areg ul x x x x x u AND logical AND 2xAreg Areg x x 0 x 0 ASHL n b arithmetic shift 2xAreg Areg ul x x x x x ASR 1 b arithmetic right shift Areg Areg x 0 0 x x CALLcc conditional call addr cc PC LRO Ofulujufu u EXP count leading bits Areg Areg x 0 0 0 0 HALT wait for an interrupt x ee LE Jcc conditional jump addr cc PC O TU TU TU TU u JMPI jump ignore delay slot addr In PC In JRcc conditional jump with LRO LRO cc In PC Oljulfululu u LDC load constant imm reg LDX load on X bus In In reg J LDY load on Y bus In In reg LDI load on bus In In Areg LOOP sta
41. rO100RRRRRR N A I 5 srrr0101RRRRRR N A I 6 srrr0110RRRRRR N A I 7 srrr0111RRRRRR N A I 1 srrr1111RRRRRR N A 1 2 srrr1110RRRRRR N A 1 3 srrr1101RRRRRR N A 1 4 srrr1100RRRRRR N A 1 5 srrri011RRRRRR N A mE 1 6 srrr1010RRRRRR N A mE 1 7 srrr1001RRRRRR N A am a Linear post inc dec In m m gt 0 srrri000RRRRRR srrriRRR 000 mmmm mmmm Ij em m lt 0 Srrri1OOORRRRRR srrriRRR 111 mmmm mmmm RN s Modulo post inc dec In n m srrr1000RRRRRR srrriRRR 001 nnnn mmmm amm 0 In n mx64 srrr1000RRRRRR srrriRRR Oin nnnn mmmm amm 0 1 1 m srrr1000RRRRRR srrriRRR 100 mmmm mmmm amm 0 In 1 m srrr1000RRRRRR srrriRRR 101 mmmm mmmm amm 0 Hu Bit reversal In m bit rev srrr1000RRRRRR srrriRRR 110 mmmm mmmm amm Register as source destination An SrrrppppOOORRR SrrrpRRR A ext srrrpppp1000RR N A g gt 0 LRO LR1 srrrpppp00100R N A MRO MR1 srrrpppp00101R N A NULL srrrpppp001100 N A NOP srrrpppp100100 N A LC srrrpppp001101 N A mE lc gt 1 LS srrrpppp001110 N A lc gt 1 LE srrrpppp001111 N A lc gt 1 In N 0 7 srrrppppO10RRR N A m Version 4 3 2014 03 05 55 GIN LSI VS DSP 8 CONTACT INFORMATION 8 Contact Information VLSI Solution Oy Entrance G 2nd floor Hermiankatu 8 FI 33720 Tampere FINLAND Fax 358 3 3140 8288 Phone 358 3 3140 8200 Commercial e m
42. rectly accessible Instruction Address Generator contains all pcu registers Instruction Address Genera tor drives Instruction Address Bus from PC LRO LR1 interrupt address or from instruc tion jump address To achieve 32 bit instruction address space large code two page registers are used IPRO holds the uppermost part of the instruction address IPRO and PC together deter mine the instruction address IPRO is copied to IPR1 during interrupts Interrupt Controller processes interrupts It implements the interrupt state machine Interrupt Controller receives external interrupt and drives interrupt fetch signal to In struction Address Generator Interrupt Controller makes sure that previous interrupt has been processed before new interrupt request is presented to Instruction Address Generator 4 1 PC PC is the program counter It is not directly accessible by the programmer PC is loaded with the fetch address 1 value on all cycles except when new loop round starts In this case PC is loaded with LS PC is kept at the old value if the instruction data and address buses are used by LDI or STI In interrupts PC is copied to LR1 In instruction fetches instruction address bus IAB is driven either from PC LRO LR1 decoded instruction jump target address reset vector address interrupt vector ad dress or calculated address for LDI or STI 4 2 LRO LRO is used in indirect jumps JRcc causes instruction to be fetched from LRO
43. rt loop reg addr Lregs 0 LSL 1 b logical left shift Areg Areg x x x x X LSLC LSL with carry Areg c Areg x x x x x LSR 1 b logical right shift Areg Areg x 0 0 x x LSRC LSR with carry Areg c Areg x x 0 x x MAC multiply accumulate 2xAreg Areg P uu XIX X IX X MSU multiply subtract 2xAreg Areg P uu XIX XIX X MUL multiply 2xAreg P ulu MVX register move reg reg MVY register move reg reg NOP no operation NOT logical NOT Areg Areg x x 0 x 0 OR logical OR 2xAreg Areg x x 0 x 0 RESP restore P 2xAreg P RETI jump with LR1 LR1 In PC 0 RND round to 16 bits Areg Areg ul x x x 0 0 SAT saturate to 32 bits Areg Areg x x x 0 0 STX store on X bus In In reg mem STY store on Y bus In In reg mem STI store on bus In In mem Areg SUB subtract 2xAreg Areg u XIXIXIX x SUBC SUB with carry 2xAreg c Areg u X X X X X U XOR logical XOR 2xAreg Areg x x 0 x 0 Operands and result reg register In index Tn modifier addr address cc condition code c carry in imm immediate data Lregs loop registers P multiplier result PC program counter mem memory location Mode bits and flags x
44. sets flag u uses bit 0 sets flag to 0 Version 4 3 2014 03 05 24 GIN LSI VS DSP 6 2 6 INSTRUCTION SET REFERENCE Instruction Descriptions The instruction description includes the mnemonic and a one line description of the operation the syntax and mathematical expression of the operation comments on the use and other specific information and finally the coding of the instruction The operand fields or other further refinements are given in accompanying tables Several operations can be executed in parallel when they are using different fields of the instruction word e g ALU operations and two parallel moves with indirect address ing are possible see instruction composition in chapter 7 In assembler the parallel operations are separated by a semicolon The following lists the main rules One instruction can contain Any single operation LDC 1234 10 J label ALU operation and any load or store sub a0 a1 b0 ldx i1 4 i0 ALU operation and any register move add a1 null a0 mv a2 al Two register moves there are some register bank restrictions mv a0 i0 mv a1 i1 One X and one Y load or store ldx i6 1 a0 ldy i6 a1 ldx i0 7 a0 sty a0 i2 1 ALU operation and one restricted X and one restricted Y load or store mac a0 ai b ldx i0 a0 ldy i2 a1 In restricted short load store one can only use the modification or no modifica tion and the data register must be an ALU register Vers
45. t register SAT Saturate 40 bit ALU register to 32 bits SAT Op2 A Flags Z N V E 0 C 0 Saturate 40 bit register to 32 bit range This is different from saturation mode set in MRO register which saturates ALU results to 40 bit range The overflow flag is set if Op2 was out of 32 bit range and saturation was made Note Saturation mode bit in MRO register does not affect this instruction The operand coding is shown in Table 4 ALU operand and the result coding in Ta ble 5 Coding 31 28 27 24 23 2019 1716 0 1111 0110 rrrriAAA parallel move rrrr Op2 AAA target register Version 4 3 2014 03 05 41 GIN LSI VS DSP 6 INSTRUCTION SET REFERENCE STX Store a register in X memory STX Op1 Op2 Opl gt X Op2 update Op2 Flags no change See LDX for the general load store capability description and the encoding of the move fields STY Store a register in Y memory STY Op1 Op2 Opl gt Y Op2 update Op2 Flags no change See LDX for the general load store capability description and the encoding of the move fields SUB Subtraction of two operands SUB Op1 Op2 An Opl Op2 gt A Flags Z N V E C The operand coding is shown in Table 4 ALU operand and the result coding in Ta ble 5 Coding 31 28 27 24 23 2019 1716 0 0110 RRRRITITrriAAA parallel move RRRR Op1 rrrr Op2 AAA target register Version 4 3 2014 03 05 42 GIN LSI
46. table with JMPI instructions which jump to the start of the appropriate interrupt routine In interrupts LR1 is used to save the return address When main program is interrupted return address is automatically copied to LR1 Interrupts normally end with a RETI jump to LR1 or a JRcc jump to LRO When generating an interrupt request the interrupt peripheral automatically disables further interrupts by increasing its interrupt disable count register If nested interrupts are required the interrupt handler must save LR1 before enabling further interrupts Note that if you call C compiled routines from the interrupt handler you must also save P and the guard bit registers 5 4 1 Interrupt Routines A typical interrupt jump table looks like the following org 0x20 JMPI int routineO SP 1 JMPI int routinel SP 1 JMPI int routine2 SP 1 Here the JMPI instructions also increases the stack pointer The start of the interrupt handler must save the processor state before enabling inter rupts in the interrupt controller The end of the handler restores the processor state Depending whether only 16 bit or both 16 and 32 bit code model will be used in the program a different kind of a saving and restoring is used Version 4 3 2014 03 05 22 NA The following is a 16 bit small code space C safe interrupt stub int routineO STX STX STX STX STX ADD STX i7 i6 i5 16 a2 i6 c2 16 ad 16 null p a
47. tion immediately before the jump has been executed The jump condition is determined again this time with different flags Version 4 3 2014 03 05 45 GIN LSI VS DSP 7 INSTRUCTION CODING 7 Instruction Coding 7 1 General Instruction Composition The instruction is composed of a 4 bit opcode and additional fields as described below 31 28 27 65 0 ooooliiiiiiiiiiiiiiiiiiiiiiYYYYyy immediate target 31 28 27 0 OoOooo j ccccccccccccccccccccccccocococce opcode control instruction 31 28 27 14 13 0 OOOO XXXXXXXXXXXXXX 2 20 9 253 2 3 ed esr opcode X full move Y full move 31 2827 17 16 0 0000 aaaaaaaaaaajnnnnnnnnnnnmnmmmm opcode arithmetic operands parallel moves 7 2 Opcode Field The encoding of operations is shown in Table 2 The control and double move exten sions to the opcode are described in the following section 7 3 Control Instructions The absolute address in jump instructions is at most 20 bits The conditional jumps Jcc are taken when the condition given in the instruction is true See Table 1 Jump condition for the condition field coding The flag and mode bits can be masked by the implementation parameter Modemask see Chapter 4 Return JRcc and return from interrupt RETI use the link registers to restore the Pc The linking return address storage is done by a constant load instruction to the link register LRO t
48. tiplication 0x8000 x 0x8000 is Ox7fffffff To get a raw value for P necessary in interrupts that manipulate the register fractional mode must be turned off before saving the register P can be restored by executing RESP A0 A1 Fractional mode does not have an effect on this operation Version 4 3 2014 03 05 11 GIN LSI VS DSP 2 4 Barrel Shifter 2 PROGRAMMING MODEL The barrel shifter can operate in both 40 bit and 16 bit mode In 40 bit mode it can shift 0 39 bits logically left when operand2 is positive or up to 39 bits arithmetically right when operand2 is negative The result is undefined if the value of the operand2 register is out of range 39 39 In 16 bit mode Operand2 must be in range 15 15 The last bit shifted out is copied to the carry flag When shifting left the overflow flag is set if the msb bit is changed during shifting When overflow happens in the saturation mode overflow flag is set and result is saturated 2 5 Guard Bit Registers Guard bit registers behave as an extension of registers A1 B1 C1 and D1 Whenever the arithmetic register A1 is written to as a 16 bit register either from a data bus or from ALU the value is sign extended to A2 Writes to B1 C1 and D1 behave in the same way This does not happen when ALU operates in 40 bit mode and the result is written to A If you restore 40 bit values remember to write to the guard bit register last otherwise a write to A1 B1 C1 D1 w
49. utine calls Note the one delay slot associated to this instruction The address which is saved to LRO is the CALL instruction address 2 The instruction in the delay slot is always executed regardless of the condition Coding 31 28 27 24 2322 21 65 0 0010 1001 absolute address condition HALT Halt the processor and wait for an interrupt HALT Flags no change The processor is halted to a low power state Normal execution is resumed when an interrupt occurs Coding 31 28 27 24 23 0 00101101 Version 4 3 2014 03 05 29 EUA JEC VS DSP 6 INSTRUCTION SET REFERENCE Conditional delayed jump to absolute address Jcc addr if cond addr gt PC else PC 1 5 PC Flags and their combinations can be used as jump conditions as shown in Table 1 Jump conditions The instruction immediately before the Jcc must not change the flags that are used in the jump condition Other flags can be changed Note the one Flags L 0 delay slot associated to this instruction Coding 31 28 27 24 2322 21 65 0 0010 1000 absolute address condition Table 1 Jump conditions Binary code Abbrev Name definition 000000 always 000001 CS carry set C 1 000010 ES extension set E 1 000011 VS overflow V 1 000100 NS negative N 1 000101 ZS zero Z 1 001000 LT less than zero N V S 1 00100
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