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NXP P89LPC9102, P89LPC9103, P89LPC9107 User`s Manual

1. Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary FMDATA Program Flash data E5H 00 00000000 IENO Interrupt enable 0 A8H EA EWDRT EBO ES ESR ET1 ETO 00 00000000 Bit address EF EE ED EC EB EA E9 E8 IEN1 Interrupt enable 1 E8H EAD EST EC EKBI ool 00x00000 Bit address BF BE BD BC BB BA B9 B8 IPO Interrupt priority O B8H PWDRT PBO PS PSR PT1 PTO ool x0000000 IPOH Interrupt priority O high B7H PWDRT PBOH PSH PT1H PTOH ool x0000000 H PSRH Bit address FF FE FD FC FB FA F9 F8 IP1 Interrupt priority 1 F8H PAD PST PC PKBI ool 00x00000 IP1H Interrupt priority 1 high F7H PADH PSTH PCH PKBIH ool 00x00000 KBCON Keypad control register 94H PATN KBIF ool xxxxxx00 _SEL KBMASK Keypad interrupt mask 86H KBMASK KBMASK 00 XXXXX00X register 2 K KBPATN Keypad pattern register 93H KBPATN KBPATN FF XXXXX11Xx 2 1 Bit address 87 86 85 84 83 82 81 80 Po Port 0 80H CMPREF CINIA CIN1B KBI2 KBI1 2 CLKIN Bit address 97 96 95 94 93 92 91 90 P1 Port 1 90H RST RXD TXD POM1 Port 0 output mode 1 84H POM1 5 POM1 4 POM1 3 POM1 2 POM1 1 FF 11111111 POM2 Port 0 output mode 2 85H POM2 5 POM2 4 POM2 3 POM2 2 POM2 1 00 00000000 PiM1 Port 1 output mode 1 91H P1M1 1 P1M1 0 FF 11111111 P1M2 Port 1 output mode 2 92H P1M2
2. state Table 41 Real time Clock System Timer clock sources FOSC2 0 RCCLK RTCS1 0 RTC clock source CPU clock source 000 x XX undefined undefined 001 010 011 0 00 External clock input Internal RC oscillator 01 DIVM 10 11 Internal RC oscillator DIVM 1 00 External clock input Internal RC oscillator 01 10 11 Internal RC oscillator 100 0 00 External clock input Watchdog oscillator 01 DIVM 10 11 Watchdog oscillator DIVM 1 00 External clock input Internal RC oscillator 01 10 11 Internal RC oscillator 101 x XX undefined undefined 110 111 0 00 External clock input External clock input DIVM 01 10 11 External clock input DIVM 1 00 External clock input Internal RC oscillator 01 10 11 Internal RC oscillator Table 42 Real time Clock Control register RTCCON address D1h bit allocation Bit 7 6 5 3 2 1 0 Symbol RTCF RTCS1 RTCSO ERTC RTCEN Reset 0 1 1 x x 0 0 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 53 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Table 43 Real time Clock Control register RTCCON address D1h bit description Bit Symbol Description O RTCEN Real time Clock enable The Real time Clock will be enabled if this bit is logic 1 Note that this bit will not power down the Real time Clock The RTCPD bit PCONA 7 if set will power down and dis
3. Philips Semiconductors UM1 01 1 2 9397 750 13919 2 7 2 8 P89LPC9102 9103 9107 User manual ADC1 CLKIN ____ tT pact RC OSCILLATOR LK LK WITH CLOCK D OSEE gt omn H Be CPU gt DOUBLER OPTION 7 3728 MHz or 14 7456 MHz gt WATCHDOG l WoT OSCILLATOR 400 kHz PCLK TIMERO TIMER 1 002aaa973 Fig 11 Block diagram of P89LPC9102 oscillator control ADC1 CLKIN m pact RC OSCILLATOR L WITH CLOCK a CPU DOUBLER OPTION gt 7 3728 MHz or 14 7456 MHz WATCHDOG OSCILLATOR 400 kHz PCLK TIMERO TIMER 1 BAUD RATE GENERATOR VATT Fig 12 Block diagram of P89LPC9103 P89LPC9107 oscillator control 002aaa974 CPU Clock CCLK wake up delay The P89LPC9102 9103 9107 has an internal wake up timer that delays the clock until it stabilizes depending to the clock source used CCLK modification DIVM register The OSCCLK frequency can be divided down by an integer up to 510 times by configuring a dividing register DIVM to provide CCLK This produces the CCLK frequency using the following formula CCLK frequency fosc 2N Where fosc is the frequency of OSCCLK Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 27 of 91 Philips Semiconductors UM1 01 1 2 2 9 P89LPC9102 9103 9107 User manual N is the value of DIVM Si
4. Fig 20 Block diagram of reset Table 33 Reset Sources register RSTSRC address DFh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BOF POF R_BK R_WD R_SF R_EX Reset x x 1 1 0 0 0 0 1 The value shown is for a power on reset Other reset sources will set their corresponding bits Table 34 Reset Sources register RSTSRC address DFh bit description Bit Symbol Description 0 REX external reset Flag When this bit is logic 1 it indicates external pin reset Cleared by software by writing a logic O to the bit or a Power on reset If RST is still asserted after the Power on reset is over R_EX will be set R_SF software reset Flag Cleared by software by writing a logic 0 to the bit or a Power on reset 2 RWD Watchdog timer reset flag Cleared by software by writing a logic 0 to the bit or a Power on reset NOTE UCFG1 7 must be 1 3 RBK break detect reset If a break detect occurs and EBRR AUXR1 6 is set to logic 1 a system reset will occur This bit is set to indicate that the system reset is caused by a break detect Cleared by software by writing a logic 0 to the bit or on a Power on reset P89LPC9103 P89LPC9107 4 POF Power on Detect Flag When Power on Detect is activated the POF flag is set to indicate an initial power up condition The POF flag will remain set until cleared by software by writing a logic 0 to the bit Note On a Power on reset both BOF and this bit will be set while the o
5. RETI Return from interrupt 1 2 32 AJMP addr 11 Absolute jump unconditional 2 2 016E1 LJMP addr 16 Long jump unconditional 3 2 02 SJMP rel Short jump relative address 2 2 80 JC rel Jump on carry 1 2 2 40 JNC rel Jump on carry 0 2 2 50 JB bit rel Jump on direct bit 1 3 2 20 JNB bit rel Jump on direct bit 0 3 2 30 JBC bit rel Jump on direct bit 1 and clear 3 2 10 JMP A DPTR Jump indirect relative DPTR 1 2 73 JZ rel Jump on accumulator 0 2 2 60 JNZ rel Jump on accumulator 0 2 2 70 CJNE A dir rel Compare A direct jne relative 3 2 B5 CJNE A d rel Compare A immediate jne relative 3 2 B4 CJNE Rn d rel Compare register immediate jne relative 3 2 B8 to BF CJNE Ri d rel Compare indirect immediate jne relative 3 2 B6 to B7 DJNZ Rn rel Decrement register jnz relative 2 2 D8 to DF DJNZ dir rel Decrement direct byte jnz relative 3 2 D5 MISCELLANEOUS NOP No operation 1 1 00 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 88 of 91 Philips Semiconductors UM10112 17 Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Sem
6. BRGR1 and BRGRO must only be loaded when the Baud Rate Generator is disabled the BRGEN bit in the BRGCON register is logic 0 This avoids the loading of an interim value to the baud rate generator CAUTION If either BRGRO or BRGR1 is written when BRGEN 1 the result is unpredictable Table 45 UART baud rate generation SCON 7 SCON 6 PCON 7 BRGCON 1 _ Receive transmit baud rate for UART SMO SM1 SMOD1 SBRGS 0 0 X X CCLK 16 0 1 0 0 CCLK 256 TH1 64 1 0 CCLK 256 TH1 32 X 1 CCLK BRGR1 BRGRO 16 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 55 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Table 45 UART baud rate generation SCON 7 SCON 6 PCON 7 BRGCON 1 Receive transmit baud rate for UART SMO SM1 SMOD1 SBRGS 1 0 0 X CCLK 32 1 xX CCLK 16 1 1 0 0 CCLK 256 TH1 64 1 0 CCLK 256 TH1 32 X 1 CCLK BRGR1 BRGRO 16 Table 46 Baud Rate Generator Control register BRGCON address BDh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SBRGS BRGEN Reset xX xX X X X xX 0 0 Table 47 Baud Rate Generator Control register BRGCON address BDh bit description Bit Symbol 0 BRGEN Description Baud Rate Generator Enable Enables the baud rate generator BRGR1 and BRGRO can only be written when BRGEN 0 1 SBRGS Select Baud Rate G
7. Continuous conversions continue until terminated by the user This mode is selected by setting the BURST1 bit in the ADMODA register Dual channel continuous conversion mode Any combination of two of the four input channels can be selected for conversion The result of the conversion of the first channel is placed in the first result register The result of the conversion of the second channel is placed in the second result register The first channel is again converted and its result stored in the third result register The second channel is again converted and its result placed in the fourth result register See Table 12 An interrupt is generated if enabled after every set of four conversions two conversions per channel This mode is selected by setting the SCC1 bit in the ADMODA register Table 12 Result registers and conversion results for dual channel continuous conversion mode Result register Contains AD1DATO First channel first conversion result AD1DAT1 Second channel first conversion result AD1DAT2 First channel second conversion result AD1DAT3 Second channel second conversion result Single step This special mode allows single stepping in an auto scan conversion mode Any combination of the four input channels can be selected for conversion After each channel is converted an interrupt is generated if enabled and the A D waits for the next start condition The result of each channel is placed in
8. TMM1 1 when the ADCS11 and ADCS10 bits 00 6 ENADCI1 Enable A D Conversion complete Interrupt 1 When set will cause an interrupt if the ADCI1 flag is set and the A D interrupt is enabled 7 ENBI1 Enable A D boundary interrupt 1 When set will cause an interrupt if the boundary interrupt 1 flag BNDI1 is set and the A D interrupt is enabled Table 16 A D Mode Register A ADMODA address COh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BNBI1 BURST1 SCC1 SCAN1 Reset 0 0 0 0 0 0 0 0 Table 17 A D Mode Register A ADMODA address COh bit description Bit Symbol Description 0 3 reserved 4 SCAN1 when 1 selects single conversion mode auto scan or fixed channel for ADC1 5 SCC1 when 1 selects fixed channel continuous conversion mode for ADC1 6 BURST1 when 1 selects auto scan continuous conversion mode for ADC1 7 BNBI1 ADC1 boundary interrupt flag When set indicates that the converted result from ADC 1 is outside of the range defined by the ADC1 boundary registers Table 18 A D Mode Register B ADMODB address Ath bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLK2 CLK1 CLKO ENDAC1 BSA1 Reset 0 0 0 0 0 0 0 0 Table 19 A D Mode Register B ADMODB address Ath bit description Bit Symbol Description 0 reserved 1 BSA1 ADC1 Boundary Select All When 1 BNDI1 will be set if any ADC1 input exceeds the boundary limits When 0 BNDI1 will be set on
9. Table 59 Keypad Pattern register KBPATN address 93h bit description Bit Symbol Access Description 0o reserved 1 2 KBPATN 1 2 R W Keyboard pattern bit 1 to bit 2 3 7 reserved Table 60 Keypad Control register KBCON address 94h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol PATN_SEL KBIF Reset xX xX xX xX xX xX 0 0 Table 61 Keypad Control register KBCON address 94h bit description Bit Symbol Access Description 0 KBIF R W Keypad Interrupt Flag Set when Port 0 matches user defined conditions specified in KBPATN KBMASK and PATN_SEL Needs to be cleared by software by writing logic 0 1 PATN_SEL R W Pattern Matching Polarity selection When set Port 0 has to be equal to the user defined Pattern in KBPATN to generate the interrupt When clear Port 0 has to be not equal to the value of KBPATN register to generate the interrupt 2 7 reserved Table 62 Keypad Interrupt Mask register KBMASK address 86h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol KBMASK 2 KBMASK 1 Reset x x X xX X 0 0 x 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 68 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Table 63 Keypad Interrupt Mask register KBMASK address 86h bit description Bit Symbol 0 Description reserved 1 2 KBMASK 1 2
10. load command clears page reg FMADRH page_hi FMADRL page_lo write my page address to addr regs for 1 0 1 lt 16 i i 1 FMDATA dbytes il FMCON EP erase amp prog page command Fm_stat FMCON read the result status if Fm_stat amp Ox0F 0 prog_fail 1 else prog_fail 0 return prog_fail In circuit programming ICP In Circuit Programming is a method intended to allow commercial programmers to program and erase these devices without removing the microcontroller from the system The In Circuit Programming facility consists of a series of internal hardware resources to facilitate remote programming of the P89LPC9102 9103 9107 through a two wire serial interface Philips has made in circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area The ICP function uses five pins Vpp Vss P0 5 P0 4 and RST Only a small connector needs to be available to interface your application to an external programmer in order to use this feature Power on reset code execution The P89LPC9102 9103 9107 contains two special Flash elements the BOOT VECTOR and the Boot Status Bit Following reset the P89LPC9102 9103 9107 examines the contents of the Boot Status Bit If the Boot Status Bit is set to zero power up execution starts at location OOOOH which is the normal start address of the user s application code When the Boot Status Bit is set to a one t
11. lt gt 002aaa971 Fig 1 P89LPC9102 logic symbol Voo Vss DAC1 AD13 gt CINIA gt RST CLKIN gt CMPREF gt gt PORT1 lt 4 RXD AD11 gt KBI2 gt PORT 0 4 gt gt TXD apie CINIB P89LPC9103 AD10 gt KBI1 gt 002aaa972 Fig 2 P89LPC9103 logic symbol Voo Vss DAC1 AD13 gt CINIA gt gt RST CLKIN gt CMPREF gt lt lt lt gt bron 1 RXD AD11 KBI2 gt p gt TXD PORT apie s CINE ORT 0 P89LPC9107 _ T0 AD10 gt KBI1 gt CLKOUT T1 4 gt gt 002aab084 Fig 3 P89LPC9107 logic symbol 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 3 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual 1 2 Pin Configuration terminal 1 index area PO 2 KBI2 AD11 10 P0 3 CIN1B AD12 P1 5 RST 9 PO 4 CIN1A AD13 DAC1 Vss LPC9102 8 P0 5 CMPREF CLKIN C6 P0 7 T1 CLKOUT 002aaa969 Transparent top view Fig 4 P89LPC9102 pinning HVSON10 terminal 1 index area PO 2 KBI2 AD11 10 P0 3 CIN1B AD12 P1 5 RST 9 PO 4 CIN1A AD13 DAC1 Vss LPC9103 8 PO 5 CMPREF CLKIN P1 0 TXD 6 P1 1 RXD 002aaa970 Transparent top view Fig 5 P89LPC9103 pinning HVSON10 P0 2 KBI2 AD11 P0 3 CIN1B AD12 n c O n c P1 5 RST P0 4 CIN1
12. 1 P1M2 0 002 00000000 PCON Power control register 87H SMOD1 SMODO BOPD BOI GF1 GFO PMOD1 PMODO 00 00000000 PCONA Power control register A B5H RTCPD VCPD ADPD SPD ool 00000000 PCONB reserved for Power control B6H OOL XXXXXXXX register B s1O ONPUOTIWAS sd jiyd Jenuew 1 3SN 2016 016 20169d 168d CLLOLINN jenuew Jesf soog Aseniqas LL LO Ady 1640 SL 6L6EL OSZ L666 paniased S Y U IY 700 A N S9140149813 Sdiltyd OxfIPUIUOY Table 5 P89LPC9103 special function registers continued indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary Bit address D7 D6 D5 D4 D3 D2 D1 DO PSW Program status word DOH CY AC FO RS1 RSO OV F1 P 00 00000000 PTOAD Port 0 digital input disable F6H PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 00 xx00000x RSTSRC _ Reset source register DFH BOF POF R_BK R_WD R_SF R_EX 4 RTCCON Real time clock control D1H RTCF RTCS1 RTCSO ERTC RTCEN oom 011xxx00 RTCH Real time clock register high D2H ool 00000000 RTCL Real time clock register low D3H ool 00000000 SADDR Serial port address register A9H 00 00000000 SADEN Serial port address enable B9H 00 00000000 SBUF Serial port data buffer register 99H XX XXXXXXXX Bit address 9F 9E 9D 9C 9B 9A 99 98 SCON Serial p
13. 2 1 KBPATN Keypad pattern register 93H KBPATN KBPATN FF XXXXX1 1X 2 1 Bit address 87 86 85 84 83 82 81 80 PO Port 0 80H CLKOUT CMPREF CINIA CIN1B CIN2A KBI1 2 T1 CLKIN KBI2 Bit address 97 96 95 94 93 92 91 90 P1 Port 1 90H RST TO POM1 Port 0 output mode 1 84H POM1 7 POM1 5 POM1 4 POM1 3 POM1 2 POM1 1 FF 11111111 POM2 Port 0 output mode 2 85H _ POM2 7 POM2 5 POM2 4 POM2 3 POM2 2 POM2 1 00 00000000 PiM1 Port 1 output mode 1 91H P1M1 2 FF 11111111 P1M2 Port 1 output mode 2 92H P1M2 2 ool 00000000 PCON Power control register 87H BOPD BOI GF1 GFO PMOD1 PMODO 00 00000000 PCONA Power control register A B5H RTCPD VCPD ADPD ool 00000000 PCONB reserved for Power control B6H OOL XXXXXXXX register B Bit address D7 D6 D5 D4 D3 D2 D1 DO PSW Program status word DOH CY AC FO RS1 RSO OV F1 P 00 00000000 PTOAD Port 0 digital input disable F6H PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 00 xx00000x s1O ONPUOTIWAS sdijiud jenuew J9Sf 2016 016 20169d 168d CLLOLINN jenuew Jesf go0z Aseniqas LL LO Ady 6L6EL OSZ L666 Table 4 indicates SFRs that are bit addressable P89LPC9102 special function registers continued Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary RSTSRC Reset source
14. 5 3 6 3 7 4 1 5 1 5 2 5 3 5 4 5 5 5 6 5 7 6 1 6 2 6 3 7 1 8 1 8 2 8 3 8 4 8 5 Introduction 200 ee eee eee eee 3 Logic symbols 2002000000 3 Pin Configuration 20055 4 Special function registers 12 Memory organization 24 IGIOCKS ones cece a ose ea ar ese ete od 25 Enhanced CPU 20 00 25 Clock definitions 5 25 Clock output 2 0 0 0 eee eee ee 25 On chip RC oscillator option with clock doubler MOdEh sss ceeds ee ete oe elastin dG Ute Sd at ae 25 Watchdog oscillator option 26 External clock input option 26 CPU Clock CCLK wake up delay 27 CCLK modification DIVM register 27 Low power select 2 0 5 28 A D converter 2 0 cee cece eee eee 28 F atureS eccess Peak a Bae eee ees 28 A D operating modes 29 Trigger modes 00 e eee eee 31 DAC output to a port pin with high impedance 32 Clock divider 220 0000 eee 32 I O pins used with A D converter functions 32 Power down and idle mode 32 Interrupts lt 0 222 aside che cee tee 34 Interrupt priority structure 35 VO ports ase eset yee sie cee te news 37 Port configurations 00 37 Quasi bidirectional output configuration 37 Open drain output configuration 38 Input on
15. 94 INCA Increment A 1 1 04 INC Rn Increment register 1 1 08 to OF INC dir Increment direct byte 2 1 05 INC Ri Increment indirect memory 1 1 06 to 07 DEC A Decrement A 1 1 14 DEC Rn Decrement register 1 1 18 to 1F DEC dir Decrement direct byte 2 1 15 DEC Ri Decrement indirect memory 1 1 16 to 17 INC DPTR Increment data pointer 1 2 A3 MUL AB Multiply A by B 1 4 A4 DIV AB Divide A by B 1 4 84 DAA Decimal Adjust A 1 1 D4 LOGICAL ANL A Rn AND register to A 1 1 58 to 5F ANL A dir AND direct byte to A 2 1 55 ANL A Ri AND indirect memory to A 1 1 56 to 57 ANL A data AND immediate to A 2 1 54 ANL dir A AND A to direct byte 2 1 52 ANL dir data AND immediate to direct byte 3 2 53 ORL A Rn OR register to A 1 1 48 to 4F ORL A dir OR direct byte to A 2 1 45 ORL A Ri OR indirect memory to A 1 1 46 to 47 ORL A data OR immediate to A 2 1 44 ORL dir A OR A to direct byte 2 1 42 ORL dir data OR immediate to direct byte 3 2 43 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 86 of 91 Philips Semiconductors UM10112 P89LPC9102 9103 9107 User manual Table 84 Instruction set summary Mnemonic Description Bytes Cycles Hex code XRL A Rn Exclusive OR register to A 1 1 68 to 6F XRL A dir Exclusive OR direct byte to A 2 1 65
16. Flash sector 256 bytes or page 16 bytes The Chip Erase operation will erase the entire program memory Two Flash programming methods are available On chip erase and write timing generation contribute to a user friendly programming interface The P89LPC9102 9103 9107 Flash reliably stores memory contents even after 100 000 erase and program cycles The cell is designed to optimize the erase and programming mechanisms The P89LPC9102 9103 9107 uses Vpp as the supply voltage to perform the Program Erase algorithms Features e In Circuit serial Programming ICP with industry standard commercial programmers e IAP Lite allows individual and multiple bytes of code memory to be used for data storage and programmed under control of the end application e Programming and erase over the full operating voltage range e Read Programming Erase using IAP Lite e Any flash program operation in 2 ms 4 ms for erase program e Programmable security for the code in the Flash for each sector e gt 100 000 typical erase program cycles for each byte e 10 year minimum data retention Flash programming and erase The P89LPC9102 9103 9107 program memory consists 256 byte sectors Each sector can be further divided into 16 byte pages In addition to sector erase and page erase a 16 byte page register is included which allows from 1 byte to 16 bytes of a given page to be programmed at the same time substantially reducing overall programming time Usin
17. Idle mode and Power down mode Table 3 P89LPC9107 pin description Symbol Pin Type Description PO 1 to P0 5 1 0 Port 0 Port 0 is an I O port with a user configurable output type During reset Port 0 PO 7 latches are configured in the input only mode with the internal pull up disabled The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 5 1 Port configurations on page 37 for details The Keypad Interrupt feature operates with Port 0 pins All pins have Schmitt triggered inputs Port 0 also provides various special functions as described below PO 1 KBI1 5 0 P0 1 Port 0 bit 1 AD10 l KBI1 Keyboard input 1 AD10 ADC1 channel 0 analog input P0 2 KBI2 1 1 0 P0 2 Port 0 bit 2 AD11 l KBI2 Keyboard input 2 AD11 ADC1 channel 1 analog input P0 3 CIN1B 14 1 0 P0 3 Port 0 bit 3 AD12 l CIN1B Comparator 1 positive input l AD12 ADC1 channel 2 analog input 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 7 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Table 3 P89LPC9107 pin description continued Symbol Pin Type Description P0 4 CIN1A 12 1 0 P0 4 Port 0 bit 4 AD13 DAC1 l CIN1A Comparator 1 positive input l AD13 ADC1 channel 3 analog input O DAC1 Digita
18. P0 4 Port 0 bit 4 AD13 DAC1 CIN1A Comparator 1 positive input AD13 ADC1 channel 3 analog input O DAC1 Digital to analog converter output P0 5 8 I O P0 5 Port 0 bit 5 ae CMPREF Comparator reference negative input CLKIN External clock input PO 7 T1 6 0 P0 7 Port 0 bit 7 CLKOUT 0 T1 Timer counter 1 external count input or overflow PWM output CLKOUT Clock output P1 2 P1 5 1 0 Port 1 Port 1 is an I O port with a user configurable output type During reset Port 1 latches are configured in the input only mode with the internal pull up disabled The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected Each of the configurable port pins are programmed independently Refer to Section 5 1 Port configurations for details P1 5 is input only All pins have Schmitt triggered inputs Port 1 also provides various special functions as described below P1 2 T0 5 I O P1 2 Port 1 bit 2 I O TO Timer counter 0 external count input or overflow PWM output 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 5 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Table 1 P89LPC9102 pin description continued Symbol Pin Type Description P1 5 RST 2 l P1 5 Port 1 bit 5 input only l RST External Reset input durin
19. P89LPC9102 9103 9107 has a simple Real time Clock System Timer that allows a user to continue running an accurate timer while the rest of the device is powered down The Real time Clock can be an interrupt or a wake up source see Figure 26 The Real time Clock is a 23 bit down counter The clock source for this counter can be either the CPU clock CCLK or an external Clock Input CLKIN There are three SFRs used for the RTC 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 51 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual RTCCON Real time Clock control RTCH Real time Clock counter reload HIGH bits 22 15 RTCL Real time Clock counter reload LOW bits 14 7 The Real time clock system timer can be enabled by setting the RTCEN RTCCON 0O bit The Real time Clock is a 23 bit down counter initialized to all 0 s when RTCEN 0 that is comprised of a 7 bit prescaler and a 16 bit loadable down counter When RTCEN is written with logic 1 the counter is first loaded with RTCH RTCL 1111111 and will count down When it reaches all 0 s the counter will be reloaded again with RTCH RTCL 1111111 and a flag RTCF RTCCON 7 will be set wake up from power down power on reset RTC RESET Y 7 BIT PRESCALER CCLK internal oscillators 23 BIT DOWN COUNTE
20. Vpp 1 program 11 total x x xX x operating range is 2 4 V to 3 6 V med power down 11 any mode 1 brownout X X X Brownout disabled Vpp other than total detect operating range is 2 4 V to 3 6 V power down powered However BOPD is default to down logic 0 upon power up 0 brownout o0 brownout X X Brownout reset enabled Vpp detect active detect operating range is 2 7 V to 3 6 V generates Upon a brownout reset BOF reset RSTSRC 5 will be set to indicate the reset source BOF can be cleared by writing logic 0 to the bit 1 brownout 1 enable 1 global Brownout interrupt enabled Vpp detect brownout interrupt operating range is 2 7 V to 3 6 V generates an interrupt enable Upon a brownout interrupt BOF interrupt RSTSRC 5 will be set BOF can be cleared by writing logic 0 to the bit 0 X Both brownout reset and 0 interrupt disabled Vpp operating range is 2 4 V to 3 6 V However BOF RSTSRC 5 will be set when Vpp falls to the Brownout Detection trip point BOF can be cleared by writing logic 0 to the bit 6 2 Power on detection The Power On Detect has a function similar to the Brownout Detect but is designed to work as power initially comes up before the power supply voltage reaches a level where the Brownout Detect can function The POF flag RSTSRC 4 is set to indicate an initial power on condition The POF flag will remain set until cleared by software by writing logic 0 to th
21. WDT can be used in timer mode and be enabled to produce an interrupt IENO 6 if desired The Watchdog Safety Enable bit WDSE UCFG1 4 along with WDTE is designed to force certain operating conditions at power up Refer to Table 64 for details Figure 36 shows the watchdog timer in Watchdog mode It consists of a programmable 13 bit prescaler and an 8 bit down counter The down counter is clocked decremented by a tap taken from the prescaler The clock source for the prescaler is either PCLK or the Watchdog oscillator selected by the WDCLK bit in the WDCON register Note that switching of the clock sources will not take effect immediately see Section 13 3 The Watchdog asserts the watchdog reset when the Watchdog count underflows and the watchdog reset is enabled When the watchdog reset is enabled writing to WDL or WDCON must be followed by a feed sequence for the new values to take effect If a watchdog reset occurs the internal reset is active for at least one Watchdog clock cycle PCLK or the Watchdog oscillator clock If CCLK is still running code execution will begin immediately after the reset cycle If the processor was in Power down mode the watchdog reset will start the oscillator and code execution will resume after the oscillator is stable Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 69 of 91 Philips Semiconductors UM1 01 1 2 P89LPC910
22. XRL A Ri Exclusive OR indirect memory to A 1 1 66 to 67 XRL A data Exclusive OR immediate to A 2 1 64 XRL dir A Exclusive OR A to direct byte 2 1 62 XRL dir data Exclusive OR immediate to direct byte 3 2 63 CLRA Clear A 1 1 E4 CPLA Complement A 1 1 F4 SWAP A Swap Nibbles of A 1 1 C4 RLA Rotate A left 1 1 23 RLC A Rotate A left through carry 1 1 33 Rotate A right RRA 1 1 03 RRC A Rotate A right through carry 1 1 13 DATA TRANSFER MOV A Rn Move register to A 1 1 E8 to EF MOV A dir Move direct byte to A 2 1 E5 Move indirect memory to A MOV A Ri 1 1 E6 to E7 MOV A data Move immediate to A 2 1 74 MOV Rn A Move A to register 1 1 F8 to FF MOV Rn dir Move direct byte to register 2 2 A8 to AF MOV Rn data Move immediate to register 2 1 78 to 7F MOV dir A Move A to direct byte 2 1 F5 MOV dir Rn Move register to direct byte 2 2 88 to 8F MOV dir dir Move direct byte to direct byte 3 2 85 MOV dir Ri Move indirect memory to direct byte 2 2 86 to 87 MOV dir data Move immediate to direct byte 3 2 75 MOV Ri A Move A to indirect memory 1 1 F6 to F7 MOV Ri dir Move direct byte to indirect memory 2 2 A6 to A7 MOV Ri data Move immediate to indirect memory 2 1 76 to 77 MOV DPTR data Move immediate to data pointer 3 2 90 MOVC A A DPTR Move code byte relative DPTR to A 1 2 93 MOVC A A PC Move code byte relative PC to A 1 2 94 MOVX A Ri Move external data A8 to A 1 2 E2 to E3 MOVX A DPTR Move external data A16 to A 1
23. a power cycle Vpp must fall below Vpor see P89LPC9102 9103 Data sheet Static characteristics before power is reapplied in order to ensure a power on reset Reset can be triggered from the following sources see Figure 20 e External reset pin during power on or if user configured via UCFG1 Required for external clock frequency above 12 MHz e Power on Detect Brownout Detect e Watchdog timer e Software reset e UART break detect reset P89LPC9103 P89LPC9107 For every reset source there is a flag in the Reset Register RSTSRC The user can read this register to determine the most recent reset source These flag bits can be cleared in software by writing a logic 0 to the corresponding bit More than one flag bit may be set e During a power on reset both POF and BOF are set but the other flag bits are cleared e For any other reset any previously set flag bits that have not been cleared will remain set 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 45 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual RPE UCFG1 6 a5 pn d WDTE UCFG1 7 watchdog timer reset software reset SRST AUXR1 3 gt chip reset power on detect UART break detect 1 EBAR AUxR1 6 _ _ brownout detect reset BOPD Poons _ 1 P89LPC9103 P89LPC9107 002aab050
24. cleared the reception of the next character will begin Refer to Figure 28 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 58 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual s1 m si6 st af si6 si 3 si6 si 16 s1 he si6 st ase si6 si a si6 si A st6 si si6 st at s16 si ae s16 si zit si6 si nee si6 write to l SBUF shift l l l l l l l l transmit RXD data out TxD shiftclock LI LI LILIN LSE LS LI LIT 23 TI WRITE to SCON fl clear RI RI l RXD g DO j D1 j D2 g D3 g D4 g D5 g D6 j D7 data in TXD shift clock I l J receive 002aaa925 Fig 28 Serial Port Mode 0 double buffering must be disabled 10 11 More about UART Mode 1 Reception is initiated by detecting a 1 to 0 transition on RXD RXD is sampled at a rate 16 times the programmed baud rate When a transition is detected the divide by 16 counter is immediately reset Each bit time is thus divided into 16 counter states At the 7th 8th and 9th counter states the bit detector samples the value of RXD The value accepted is the value that was seen in at least 2 of the 3 samples This is done for noise rejection If the value accepted during the first bit time is not 0 the receive circuits are reset and the receiver goes back to looking for another 1 to 0 transition This provides reject
25. command is issued to FMCON the page register contents and all of the update flags will be cleared When FMDATA is written the value written to FMDATA will be stored in the page register at the location specified by the lower 4 bits of FMADRL In addition the update flag for that location will be set FMADRL will auto increment to the next location Auto increment after writing to the last byte in the page register will wrap around to the first byte in the page register but will not affect FMADRL 7 4 Bytes loaded into the page register do not have to be continuous Any byte location can be loaded into the page register by changing the contents of FMADRL prior to writing to FMDATA However each location in the page register can only be written once following each LOAD command Attempts to write to a page register location more than once should be avoided FMADRH and FMADRL 7 4 are used to select a page of code memory for the erase program function When the erase program command is written to FMCON the locations within the code memory page that correspond to updated locations in the page register will have their contents erased and programmed with the contents of their corresponding locations in the page register Only the bytes that were loaded into the page register will be erased and programmed in the user code array Other bytes within the user code memory will not be affected Writing the erase program command 68H to FMCON will start
26. enable B9H 00 00000000 SBUF Serial port data buffer register 99H XX XXXXXXXX Bit address 9F 9E 9D 9C 9B 9A 99 98 SCON Serial port control 98H SMO FE SM1 SM2 REN TB8 RB8 Tl RI 00 00000000 SSTAT Serial port extended status BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 00000000 register SP Stack pointer 81H 07 00000111 Bit address 8F 8E 8D 8C 8B 8A 89 88 TCON Timer 0 and 1 control 88H TF1 TR1 TFO TRO 00 00000000 THO Timer 0 high 8CH 00 00000000 TH1 Timer 1 high 8DH 00 00000000 TLO Timer 0 low 8AH 00 00000000 TL1 Timer 1 low 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H T1iM1 T1MO TOM1 TOMO 00 00000000 TRIM Internal oscillator trim register 96H RCCLK ENCLK TRIM 5 TRIM 4 TRIMS TRIM 2 TRIM 1 TRIM O 61 7 WDCON Watchdog control register A7H PRE2 PRE1 PREO WDRUN WDTOF WODCLK BSN WDL Watchdog load C1H FF 11111111 WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H 1 Unimplemented bits in SFRs labeled are X unknown at all times Unless otherwise specified ones should not be written to these bits since they may be used for other purposes in future derivatives The reset values shown for these bits are logic Os although they are unknown when read s1O ONPUOTIWAS sdijiud Jenuew J9Sf 2016 016 20169d 168d CLLOLINN jenuew 1 sN LO A3H goog Asenigas LL L6 0 Z 6L6EL OSZ Z6 6 paniased S Y u IY Y0OZ A N S9140149913 Sdiliyd Afiuuoy All ports
27. geada as agi eagen e ee eee 55 Baud Rate generator and selection 55 Updating the BRGR1 and BRGRO SFRs 55 Framing error 2 2 0 nau uiaiia 56 Break detect 00000220 eee 56 More about UART Mode O 58 More about UART Mode 1 59 More about UART Modes 2 and3 60 Framing error and RI in Modes 2 and 3 with SM2 Treen re bt daar dh de wn hid 60 Break detect 200000 cess 61 Double buffering 000 61 Double buffering in different modes 61 Transmit interrupts with double buffering enabled Modes 1 2 and 3 61 The 9th bit bit 8 in double buffering Modes 1 2 and 3 0000 62 Multiprocessor communications 63 Automatic address recognition 64 Analog comparator 2 20005 65 Comparator configuration 65 Internal reference voltage 66 Comparator interrupt 66 Comparator and power reduction modes 66 Comparator configuration example 67 Keypad interrupt KBI 00005 67 Watchdog Timer WDT 2 2 055 69 Watchdog function 69 Feed sequence 2 0 0 20005 70 Watchdog clock source 72 Watchdog timer in Timer mode 74 Power down operation 74 Periodic wake up from power down without an external oscillator 24 74 Additional feat
28. input that also has a glitch suppression circuit Please refer to the P89LPC9102 9103 9107 data sheet Dynamic characteristics for glitch filter specifications Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 39 of 91 Philips Semiconductors UM1 01 1 2 9397 750 13919 5 6 5 7 P89LPC9102 9103 9107 User manual VDD strong PORT PIN port latch N data input data O lt lt O lt glitch rejection 002aaa917 Fig 19 Push pull output Port 0 analog functions The P89LPC9102 9103 9107 incorporates one Analog Comparator In order to give the best analog performance and minimize power consumption pins that are being used for analog functions must have both the digital outputs and digital inputs disabled Digital outputs are disabled by putting the port pins into the input only mode as described in the Port Configurations section see Figure 18 Digital inputs on Port 0 may be disabled through the use of the PTOAD register Bits 1 through 5 in this register correspond to pins PO 1 through PO 5 of Port 0 respectively Setting the corresponding bit in PTOAD disables that pin s digital input Port bits that have their digital inputs disabled will be read as logic 0 by any instruction that accesses the port On any reset PTOAD bits 1 through 5 default to logic Os to enable the digital functions Additional port features After powe
29. is compared to the value of Port 0 The Keypad Interrupt Flag KBIF in the Keypad Interrupt Control Register KBCON is set when the condition is matched while the Keypad Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 67 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Interrupt function is active An interrupt will be generated if it has been enabled by setting the EKBI bit in IEN1 register and EA 1 The PATN_SEL bit in the Keypad Interrupt Control Register KBCON is used to define equal or not equal for the comparison In order to use the Keypad Interrupt as an original KBI function like in the 87LPC76x series the user needs to set KBPATN OFFH and PATN_SEL 0 not equal then any key connected to PortO which is enabled by KBMASK register is will cause the hardware to set KBIF 1 and generate an interrupt if it has been enabled The interrupt may be used to wake up the CPU from Idle or Power down modes This feature is particularly useful in handheld battery powered systems that need to carefully manage power consumption yet also need to be convenient to use In order to set the flag and cause an interrupt the pattern on Port 0 must be held longer than six CCLKs Table 58 Keypad Pattern register KBPATN address 93h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol KBPATN 2 KBPATN 1 Reset xX xX xX xX xX 1 1 x
30. is enabled Comparator output is stable 10 microseconds after CE1 is set 6 reserved reserved 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 65 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual comparator P0 4 CINIA P0 3 CIN1B change detect interrupt P0 5 CMPREF VREF 002aaa979 Fig 32 Comparator input and output connections 11 2 Internal reference voltage An internal reference voltage Vref may supply a default reference when a single comparator input pin is used Please refer to the P89LPC9102 9103 Data sheet for specifications 11 3 Comparator interrupt The comparator has an interrupt flag CMF1 contained in its configuration register This flag is set whenever the comparator output changes state The flag may be polled by software or may be used to generate an interrupt The interrupt will be generated when the interrupt enable bit EC in the IEN1 register is set and the interrupt system is enabled via the EA bit in the IENO register When the comparator is disabled the comparator s output CO1 goes HIGH If the comparator output was LOW and then is disabled the resulting transition of the comparator output from a LOW to HIGH state will set the comparator flag CMF1 This will cause an interrupt if the comparator interrupt is enabled The user should theref
31. operates with Port 0 pins All pins have Schmitt triggered inputs Port 0 also provides various special functions as described below PO 1 KBI1 4 1 0 P0 1 Port 0 bit 1 AD10 l KBI1 Keyboard input 1 AD10 ADC1 channel 0 analog input P0 2 KBI12 1 VO P0 2 Port 0 bit 2 AD11 l KBI2 Keyboard input 2 l AD11 ADC1 channel 1 analog input P0 3 CIN1B 10 1 0 P0 3 Port 0 bit 3 AD12 l CIN1B Comparator 1 positive input l AD12 ADC1 channel 2 analog input PO 4 CIN1A 9 1 0 P0 4 Port 0 bit 4 AD13 DAC1 l CIN1A Comparator 1 positive input AD13 ADC1 channel 3 analog input O DAC1 Digital to analog converter output P0 5 CMPREF 6 1 0 P0 5 Port 0 bit 5 CLKIN l CMPREF Comparator reference negative input l CLKIN External clock input 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 6 of 91 Philips Semiconductors UM10112 P89LPC9102 9103 9107 User manual Table 2 P89LPC9103 pin description continued Symbol Pin Type Description P1 0 to P1 5 0 Port 1 Port 1 is an I O port with a user configurable output type During reset Port 1 latches are configured in the input only mode with the internal pull up disabled The operation of the configurable Port 1 pins as inputs and outp
32. the erase program process and place the CPU in a program idle state The CPU will remain in this idle state until the erase program cycle is either completed or terminated by an interrupt When the program idle state is exited FMCON will contain status information for the cycle If an interrupt occurs during an erase programming cycle the erase programming cycle will be aborted and the OI flag Operation Interrupted in FMCON will be set If the application permits interrupts during erasing programming the user code should check the Ol flag FMCON 0 after each erase programming operation to see if the operation was aborted If the operation was aborted the user s code will need to repeat the process starting with loading the page register The erase program cycle takes 4 ms 2 ms for erase 2 ms for programming to complete regardless of the number of bytes that were loaded into the page register Erasing programming of a single byte or multiple bytes in code memory is accomplished using the following steps e Write the LOAD command 00H to FMCON The LOAD command will clear all locations in the page register and their corresponding update flags Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 77 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual e Write the address within the page register to FMADRL Since the loading the page regist
33. the registers Mode 0 operation is the same for Timer 0 and Timer 1 See Figure 21 8 2 Mode 1 Mode 1 is the same as Mode 0 except that all 16 bits of the timer register THn and TLn are used See Figure 22 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 48 of 91 Philips Semiconductors UM1 01 1 2 8 3 8 4 8 5 P89LPC9102 9103 9107 User manual Mode 2 Mode 2 configures the Timer register as an 8 bit Counter TLn with automatic reload as shown in Figure 23 Overflow from TLn not only sets TFn but also reloads TLn with the contents of THn which must be preset by software The reload leaves THn unchanged Mode 2 operation is the same for Timer 0 and Timer 1 Mode 3 When Timer 1 is in Mode 3 it is stopped The effect is the same as setting TR1 0 Timer 0 in Mode 3 establishes TLO and THO as two separate 8 bit counters The logic for Mode 3 on Timer 0 is shown in Figure 24 TLO uses the Timer 0 control bits TOC T TRO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus THO now controls the Timer 1 interrupt Mode 3 is provided for applications that require an extra 8 bit timer With Timer 0 in Mode 3 an P89LPC9102 9103 9107 device can look like it has three Timer Counters Note When Timer 0 is in Mode 3 Timer 1 can be turned on and off by switching it i
34. to the ICP or programmer mode If the Configuration Write Protect Writ CWP bit in BOOTSTAT 6 is a 1 writes to the configuration bytes are disabled If the Configuration Write Protect Writ CWP bit in BOOTSTAT 6 is a 0 writes to the configuration bytes are enabled The CWP bit is set by programming the BOOTSTAT register This bit is cleared by using the Clear Configuration Protection command 67h MOV FMCON 67H MOV FMDATA 96H The Clear Configuration Protection command can be disabled in IAP Lite mode by programming to a 1 the Disable Clear Configuration Protection DCCP bit in BOOTSTAT 7 When DCOP is set the CCP command may still be used in ICP mode This bit is cleared by writing the Clear Configuration Protection command in ICP mode IAP Lite error status It is not possible to use the Flash memory as the source of program instructions while programming or erasing this same Flash memory During an IAP Lite erase program or CRC the CPU enters a program idle state The CPU will remain in this program idle state until the erase program or CRC cycle is completed These cycles are self timed When the cycle is completed code execution resumes If an interrupt occurs during an erase programming or CRC cycle the erase programming or CRC cycle will be aborted so that the Flash memory can be used as the source of instructions to service the interrupt An IAP Lite error condition will be flagged by setting the carry fla
35. used with the TOM2 bit in the TAMOD register to determine the 1 TOM1 Timer 0 mode see Table 38 2 TOC T Timer or Counter selector for Timer 0 Cleared for Timer operation input from CCLK Set for Counter operation input from TO input pin P89LPC9102 P89LPC9107 3 reserved 4 TIMO Mode Select for Timer 1 These bits are used with the T1M2 bit in the TAMOD register to determine the 5 Timi Timer 1 mode see Table 38 6 T1C T Timer or Counter Selector for Timer 1 Cleared for Timer operation input from CCLK Set for Counter operation input from T1 input pin P89LPC9102 P89LPC9107 7 reserved 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 47 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Table 37 Timer Counter Auxiliary Mode register TAMOD address 8Fh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TiM2 TOM2 Reset xX xX xX 0 xX xX xX 0 Table 38 Timer Counter Auxiliary Mode register TAMOD address 8Fh bit description Bit Symbol Description 0 TOM2 Mode Select for Timer 0 These bits are used with the TOM2 bit in the TAMOD register to determine the Timer 0 mode see Table 38 1 3 reserved 4 T1M2 Mode Select for Timer 1 These bits are used with the T1M2 bit in the TAMOD register to determine the Timer 1 mode see Table 38 The following ti
36. worun woror woo 002aaa939 WDCON A7H Fig 36 Watchdog timer in Timer Mode WDTE 0 13 4 Watchdog timer in Timer mode Figure 36 shows the watchdog timer in Timer Mode In this mode any changes to WDCON are written to the shadow register after one Watchdog clock cycle A Watchdog underflow will set the WDTOF bit If IENO 6 is set the Watchdog underflow is enabled to cause an interrupt WDTOF is cleared by writing a logic 0 to this bit in software When an underflow occurs the contents of WDL is reloaded into the down counter and the watchdog timer immediately begins to count down again A feed is necessary to cause WDL to be loaded into the down counter before an underflow occurs Incorrect feeds are ignored in this mode 13 5 Power down operation The WDT oscillator will continue to run in power down consuming approximately 50 uA as long as the WDT oscillator is selected as the clock source for the WDT Selecting PCLK as the WDT source will result in the WDT oscillator going into power down with the rest of the device see Section 13 3 Power down mode will also prevent PCLK from running and therefore the Watchdog is effectively disabled 13 6 Periodic wake up from power down without an external oscillator Without using an external oscillator source the power consumption required in order to have a periodic wake up is determined by the power consumption of the internal oscillator source used to produce th
37. 0 00000000 PiM1 Port 1 output mode 1 91H P1M1 1 P1M1 0 FF 11111111 P1M2 Port 1 output mode 2 92H P1M2 1 P1M2 0 002 00000000 PCON Power control register 87H SMOD1 SMODO BOPD BOI GF1 GFO PMOD1 PMODO 00 00000000 PCONA Power control register A B5H RTCPD VCPD ADPD SPD ool 00000000 PCONB reserved for Power control B6H OOL XXXXXXXX register B s1O ONPUOTIWAS sd jiyd Jenuew 1 3SN 2016 016 20169d 168d CLLOLINN jenuew Jesf soog Aseniqas LL LO Ady L6 40 ZZ 6L6EL OSZ Z6 6 paniased S Y U IY Y0OZ A N S91u0149813 Sdiltyd Af yuuoy Table 6 P89LPC9107 special function registers continued indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary Bit address D7 D6 D5 D4 D3 D2 D1 DO PSW Program status word DOH CY AC FO RS1 RSO OV F1 P 00 00000000 PTOAD Port 0 digital input disable F6H PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 00 xx00000x RSTSRC _ Reset source register DFH BOF POF R_BK R_WD R_SF R_EX 4 RTCCON Real time clock control D1H RTCF RTCS1 RTCSO ERTC RTCEN oom 011xxx00 RTCH Real time clock register high D2H ool 00000000 RTCL Real time clock register low D3H ool 00000000 SADDR Serial port address register A9H 00 00000000 SADEN Serial port address
38. 0 513 1 28 ms 85 5 us 255 131 073 327 7 ms 21 8 ms 101 0 1 025 2 56 ms 170 8 us 255 262 145 655 4 ms 43 7 ms 110 0 2 049 5 12 ms 341 5 us 255 524 289 1 31s 87 4 ms 111 0 4097 10 2 ms 682 8 ms 255 1 048 577 2 62 s 174 8 ms 13 3 Watchdog clock source The watchdog timer system has an on chip 400 KHz oscillator The watchdog timer can be clocked from either the Watchdog oscillator or from PCLK refer to Figure 34 by configuring the WDCLK bit in the Watchdog Control Register WDCON When the Watchdog feature is enabled the timer must be fed regularly by software in order to prevent it from resetting the CPU 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 72 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual After changing WDCLK WDCON 0 switching of the clock source will not immediately take effect As shown in Figure 36 the selection is loaded after a Watchdog feed sequence In addition due to clock synchronization logic it can take two old clock cycles before the old clock source is deselected and then an additional two new clock cycles before the new clock source is selected Since the prescaler starts counting immediately after a feed switching clocks can cause some inaccuracy in the prescaler count The inaccuracy could be as much as two old clock source counts plus two new clock cycles Note When switching clocks it is importan
39. 0000 ADMODB A D mode register B A1H CLK2 CLK1 CLKO ENDAC1 BSA1 00 000x0000 AD1BH A D_1 boundary high register C4H FF 11111111 AD1BL A D_1 boundary low register BCH 00 00000000 AD1DATO A D_1 data register 0 D5H 00 00000000 AD1DAT1 A D_1 data register 1 D6H 00 00000000 AD1DAT2 A D_1 data register 2 D7H 00 00000000 AD1DAT3 A D_1 data register 3 F5H 00 00000000 AUXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENTO SRST 0 DPS ool 000000x0 Bit address F7 F6 F5 F4 F3 F2 F1 FO B B register FOH 00 00000000 BRGRO Baud rate generator rate low BEH 00 00000000 BRGR18 Baud rate generator rate high BFH 00 00000000 BRGCON Baud rate generator control BDH SBRGS BRGEN 00B xxxxxx00 CMP1 Comparator 1 control register ACH CE1 CP1 CN1 CO1 CMF1 00 xx000000 DIVM CPU clock divide by M 95H 00 00000000 control DPTR Data pointer 2 bytes DPH Data pointer high 83H 00 00000000 DPL Data pointer low 82H 00 00000000 FMADRH Program Flash address high E7H 00 00000000 FMADRL Program Flash address low E6H 00 00000000 FMCON Program Flash Control E4H BUSY HVA HVE SV Ol 70 01110000 Read Program Flash Control FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD Write 7 6 5 4 3 2 1 0 s1O ONPUOTIWAS sdijiud Jenuew J9Sf 2016 016 20169d 168d CLLOLINN jenuew Jesf soog Aseniqas LL LO Ady L6 0 Z 6L6EL OSZ Z6 6 paniased S Y U IY 700 A N S91u0149813 Sdiltyd Oxf PUIUOY Table 6 i
40. 1111111 AD1BL A D_1 boundary low register BCH 00 00000000 AD1DATO A D_1 data register 0 D5H 00 00000000 AD1DAT1 A D_1 data register 1 D6H 00 00000000 AD1DAT2 A D_1 data register 2 D7H 00 00000000 AD1DAT3 A D_1 data register 3 F5H 00 00000000 AUXR1 Auxiliary function register A2H CLKLP EBRR SRST 0 DPS ool 000000x0 Bit address F7 F6 F5 F4 F3 F2 F1 FO B B register FOH 00 00000000 BRGRO Baud rate generator rate low BEH 00 00000000 BRGR18 Baud rate generator rate high BFH 00 00000000 BRGCON Baud rate generator control BDH SBRGS BRGEN 00B xxxxxx00 CMP1 Comparator 1 control register ACH CE1 CP1 CN1 CO1 CMF1 00 xx000000 DIVM CPU clock divide by M 95H 00 00000000 control DPTR Data pointer 2 bytes DPH Data pointer high 83H 00 00000000 DPL Data pointer low 82H 00 00000000 FMADRH Program Flash address high E7H 00 00000000 FMADRL Program Flash address low E6H 00 00000000 FMCON Program Flash Control E4H BUSY HVA HVE SV Ol 70 01110000 Read Program Flash Control FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD Write 7 6 5 4 3 2 1 0 s1O ONPUOTIWAS sdijiud Jenuew J9Sf 2016 016 20169d 168d CLLOLINN jenuew Jesf soog Aseniqas LL LO Ady 1640 ZL 6L6EL OSZ L666 pansased S Y uU IY 700 A N 91u0149813 Sdiliyd Af yuuoy Table 5 indicates SFRs that are bit addressable P89LPC9103 special function registers continued
41. 2 9103 9107 User manual Table 64 Watchdog timer configuration WDTE UCFG1 7 WDSE UCFG1 4 FUNCTION 0 xX The watchdog reset is disabled The timer can be used as an internal timer and can be used to generate an interrupt WDSE has no effect The watchdog reset is enabled The user can set WDCLK to choose the clock source The watchdog reset is enabled along with additional safety features 1 WDCLK is forced to 1 using watchdog oscillator 2 WDCON and WDL register can only be written once 3 WDRUN is forced to 1 and cannot be cleared by software watchdog oscillator PCLK PRE2 PRE1 PREO WDCLK AFTER A WATCHDOG FEED SEQUENCE DECODE Fig 34 Watchdog prescaler to watchdog down counter after one prescaler count delay 002aaa938 9397 750 13919 13 2 Feed sequence The watchdog timer control register and the 8 bit down counter See Figure 35 are not directly loaded by the user The user writes to the WDCON and the WDL SFRs At the end of a feed sequence the values in the WDCON and WDL SFRs are loaded to the control register and the 8 bit down counter Before the feed sequence any new values written to these two SFRs will not take effect To avoid a watchdog reset the watchdog timer needs to be fed via a special sequence of software action called the feed sequence prior to reaching an underflow To feed the Watchdog two write instructions must b
42. 2 EO MOVX Ri A Move A to external data A8 1 2 F2 to F3 MOVX DPTR A Move A to external data A16 1 2 FO PUSH dir Push direct byte onto stack 2 2 Co POP dir Pop direct byte from stack 2 2 DO XCH A Rn Exchange A and register 1 1 C8 to CF XCH A dir Exchange A and direct byte 2 1 C5 XCH A Ri Exchange A and indirect memory 1 1 C6 to C7 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 87 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Table 84 Instruction set summary Mnemonic Description Bytes Cycles Hex code XCHD A Ri Exchange A and indirect memory nibble 1 1 D6 to D7 BOOLEAN Mnemonic Description Bytes Cycles Hex code CLR C Clear carry 1 1 C3 CLR bit Clear direct bit 2 1 C2 SETBC Set carry 1 1 D3 SETB bit Set direct bit 2 1 D2 CPLC Complement carry 1 1 B3 CPL bit Complement direct bit 2 1 B2 ANL C bit AND direct bit to carry 2 2 82 ANL C bit AND direct bit inverse to carry 2 2 BO ORL C bit OR direct bit to carry 2 2 72 ORL C bit OR direct bit inverse to carry 2 2 AO MOV C bit Move direct bit to carry 2 1 A2 MOV bit C Move carry to direct bit 2 2 92 BRANCHING ACALL addr 11 Absolute jump to subroutine 2 2 116F1 LCALL addr 16 Long jump to subroutine 3 2 12 RET Return from subroutine 1 2 22
43. 31 Transmission with and without double buffering write to i SBUF TX interrupt f f f f single buffering DBMOD SSTAT 7 0 early interrupt INTLO SSTAT 6 0 is shown TXD ue It f if f f f j double buffering DBMOD SSTAT 7 1 early interrupt INTLO SSTAT 6 0 is shown no ending TX interrupt DBISEL SSTAT 4 0 TX interrupt TXD write to SBUF 1 1 1 1 TX interrupt f f f f f double buffering DBMOD SSTAT 7 1 early interrupt INTLO SSTAT 6 0 is shown with ending TX interrupt DBISEL SSTAT 4 1 002aaa928 9397 750 13919 10 18 The 9th bit bit 8 in double buffering Modes 1 2 and 3 If double buffering is disabled DBMOD i e SSTAT 7 0 TB8 can be written before or after SBUF is written provided TB8 is updated before that TB8 is shifted out TB8 must not be changed again until after TB8 shifting has been completed as indicated by the Tx interrupt Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 62 of 91 Philips Semiconductors UM1 01 1 2 9397 750 13919 P89LPC9102 9103 9107 User manual If double buffering is enabled TB8 MUST be updated before SBUF is written as TB8 will be double buffered together with SBUF data The operation described in Section 10 17 becomes as follows The double buffer is empty initially The CPU writes to TB8 The CPU writes to SBUF The SBUF TB8 data
44. 9 15 7 Flash write enable This device has hardware write enable protection This protection applies during IAP Lite mode and applies to both the user code memory space and the user configuration bytes UCFG1 BOOTVEC and BOOTSTAT This protection does not apply to the ICP programming mode If the Activate Write Enable AWE bit in BOOTSTAT 7 is a 0 an internal Write Enable WE flag is forced set and writes to the flash memory and configuration bytes are enabled If the Active Write Enable AWE bit is a 1 then the state of the internal WE flag can be controlled by the user The WE flag is SET by writing the Set Write Enable 08H command to FMCON followed by a key value 96H to FMDATA MOV FMCON 08H MOV FMDATA 96H The WE flag is CLEARED by writing the Clear Write Enable OBH command to FMCON followed by a key value 96H to FMDATA or by a reset MOV FMCON 0BH MOV FMDATA 96H Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 81 of 91 Philips Semiconductors UM1 01 1 2 9397 750 13919 15 8 13 9 15 10 P89LPC9102 9103 9107 User manual Configuration byte protection In addition to the hardware write enable protection described above the configuration bytes may be separately write protected These configuration bytes include UCFG1 BOOTVEC and BOOTSTAT This protection applies to the IAP Lite programming mode and does not apply
45. 9103 9107 User manual Table 66 Watchdog Timer Control register WDCON address A7h bit description Bit Symbol Description 0 WDCLK Watchdog input clock select When set the Watchdog oscillator is selected When cleared PCLK is selected If the CPU is powered down the Watchdog is disabled if WDCLK 0 see Section 13 5 Note If both WDTE and WDSE are set to 1 this bit is forced to 1 Refer to Section 13 3 for details 1 WDTOF Watchdog Timer Time Out Flag This bit is set when the 8 bit down counter underflows In Watchdog mode a feed sequence will clear this bit It can also be cleared by writing logic 0 to this bit in software 2 WDRUN Watchdog Run Control The watchdog timer is started when WDRUN 1 and stopped when WDRUN 0 This bit is forced to logic 1 Watchdog running and cannot be cleared to zero if both WDTE and WDSE are set to 1 3 4 reserved PREO PRE1 Clock Prescaler Tap Select Refer to Table 67 for details PRE2 Table 67 Watchdog timeout vales PRE2 to PREO WDL in decimal Timeout Period Watchdog Clock Source in Watchdog clock 400 KHz Watchdog 12 MHz CCLK 6 MHz cycles Oscillator Clock CCLK 2 Watchdog Nominal Clock 000 0 33 82 5 us 5 50 us 255 8 193 20 5 ms 1 37 ms 001 0 65 162 5 us 10 8 us 255 16 385 41 0 ms 2 73 ms 010 0 129 322 5 us 21 5 us 255 32 769 81 9 ms 5 46 ms 011 0 257 642 5 us 42 8 us 255 65 537 163 8 ms 10 9 ms 100
46. A AD13 DAC1 Vss LPC9107 P0 5 CMPREF CLKIN PO 1 KBI1 AD10 Vpp P1 0 TXD P1 2 T0 P1 1 RXD P0O 7 T1 CLKOUT 002aab083 Fig 6 P89LPC9107 pinning TSSOP14 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 4 of 91 Philips Semiconductors UM10112 P89LPC9102 9103 9107 User manual Table 1 P89LPC9102 pin description Symbol Pin Type Description PO 1 to P0 5 I O Port 0 Port 0 is an I O port with a user configurable output type During reset Port 0 PO 7 latches are configured in the input only mode with the internal pull up disabled The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 5 1 Port configurations for details The Keypad Interrupt feature operates with Port 0 pins All pins have Schmitt triggered inputs Port 0 also provides various special functions as described below PO 1 KBI1 4 I O P0 1 Port 0 bit 1 AD10 KBI1 Keyboard input 1 AD10 ADC1 channel 0 analog input PO 2 KBI2 1 0 P0 2 Port 0 bit 2 AD11 l KBI2 Keyboard input 2 AD11 ADC1 channel 1 analog input PO 3 CIN1IB 10 I O P0 3 Port 0 bit 3 AD12 CIN1B Comparator 1 positive input AD12 ADC1 channel 2 analog input PO 4 CINIA 9 I O
47. E1 These configurations are shown in Figure 33 When the comparator is first enabled the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds The corresponding comparator interrupt should not be enabled during that time and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service Table 56 Comparator Control register CMP1 address ACh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CE1 CP1 CN1 CO1 CMF1 Reset xX X 0 0 0 X 0 0 Table 57 Comparator Control register CMP1 address ACh CMP2 address ADh bit description Bit Symbol Description QO CMF1 Comparator interrupt flag This bit is set by hardware whenever the comparator output CO1 changes state This bit will cause a hardware interrupt if enabled Cleared by software 1 CO1 Comparator output synchronized to the CPU clock to allow reading by software 2 reserved CN1 Comparator negative input select When logic 0 the comparator reference pin CMPREF is selected as the negative comparator input When logic 1 the internal comparator reference Vref is selected as the negative comparator input 4 CP1 Comparator positive input select When logic 0 CINNA is selected as the positive comparator input When logic 1 CINnB is selected as the positive comparator input 5 CE1 Comparator enable When set the corresponding comparator function
48. EL OSZ 2666 pansased SIYGH IY Y0OZ A N S91u0149813 Sdiliyd OHI PUIUCY Table 4 P89LPC9102 special function registers indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary Bit address E7 E6 E5 E4 E3 E2 E1 E0 ACC Accumulator EOH 00 00000000 ADCON1 A D control register 1 97H ENBI1 ENADCI1 TMM1 ADCI1 ENADC1 ADCS11 ADCS10 00 00000000 ADINS A D input select A3H ADI13 AD12 ADI11 AD10 00 00000000 ADMODA A D mode register A COH BNDI1 BURST1 SCC1 SCAN1 00 00000000 ADMODB A D mode register B A1H CLK2 CLK1 CLKO ENDAC1 BSA1 00 000x0000 AD1BH A D_1 boundary high register C4H FF 11111111 AD1BL A D_1 boundary low register BCH 00 00000000 AD1DATO A D_1 data register 0 D5H 00 00000000 AD1DAT1 A D_1 data register 1 D6H 00 00000000 AD1DAT2 A D_1 data register 2 D7H 00 00000000 AD1DAT3 A D_1 data register 3 F5H 00 00000000 AUXR1 Auxiliary function register A2H CLKLP EBRR SRST 0 DPS ool 000000x0 Bit address F7 F6 F5 F4 F3 F2 F1 FO B B register FOH 00 00000000 CMP1 Comparator 1 control register ACH CE1 CP1 CN1 CO1 CMF1 00 xx000000 DIVM CPU clock divide by M 95H 00 00000000 control DPTR Data pointer 2 bytes DPH Data pointer high 83H 00 00000000 DPL Data pointer low 82H 00 00000000 FMADRH Program Flash address high E7H 00 00000000 FMADRL Program Flash
49. Keypad interrupt mask bit 1 to bit 2 3 7 reserved 1 The Keypad Interrupt must be enabled in order for the settings of the KBMASK register to be effective 13 Watchdog Timer WDT 9397 750 13919 13 1 The watchdog timer subsystem protects the system from incorrect code execution by causing a system reset when it underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count The watchdog timer can only be reset by a power on reset Watchdog function The user has the ability using the WDCON and UCFG 1 registers to control the run stop condition of the WDT the clock source for the WDT the prescaler value and whether the WDT is enabled to reset the device on underflow In addition there is a safety mechanism which forces the WDT to be enabled by values programmed into UCFG1 either through IAP or a commercial programmer The WDTE bit UCFG1 7 if set enables the WDT to reset the device on underflow Following reset the WDT will be running regardless of the state of the WDTE bit The WDRUN bit WDCON 2 can be set to start the WDT and cleared to stop the WDT Following reset this bit will be set and the WDT will be running All writes to WOCON need to be followed by a feed sequence see Section 13 2 Additional bits in WDCON allow the user to select the clock source for the WDT and the prescaler When the timer is not enabled to reset the device on underflow the
50. Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 64 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual interpreting the don t cares as ones the broadcast address will be FF hexadecimal Upon reset SADDR and SADEN are loaded with Os This produces a given address of all don t cares as well as a Broadcast address of all don t cares This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature 11 Analog comparator One analog comparator is provided on the P89LPC9102 9103 9107 Input and output options allow use of the comparator in a number of different configurations Comparator operation is such that the output is a logic 1 which may be read in a register and or routed to a pin when the positive input one of two selectable pins is greater than the negative input selectable from a pin or an internal reference voltage Otherwise the output is a zero The comparator may be configured to cause an interrupt when the output value changes 11 1 Comparator configuration Each comparator has a control register CMP1 and is shown in Table 57 The overall connections to the comparator is shown in Figure 32 There are eight possible configurations for the comparator as determined by the control bits in the corresponding CMP1 register CP1 CN1 and O
51. NFIGURABLE ON CHIP oe CLKIN OSCILLATOR RC OSCILLATOR WITH CLOCK BROWNOUT RESET DOUBLER OPTION 002aaa967 Fig 7 P89LPC9102 block diagram 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 9 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual P89LPC9103 ACCELERATED 2 CLOCK 80C51 CPU Pat TKB 5 TXD FLASH RXD internal bus PORT 1 128 BYTE AD10 PORT 0 AD11 Po 1 5 lt __ 1 CONFIGURABLE I Os C gt ADC1 DAC1 ADi DAC1 KBI1 KEYPAD REAL TIME CLOCK KBI2 INTERRUPT SYSTEM TIMER WATCHDOG TIMER n TIMER 0 AND OSCILLATOR TIMER 1 PROGRAMMABLE CPU e ANALOG CIN1A OSCILLATOR DIVIDER clock COMPARATORS CIN1B bara CLKIN CONFIGURABLE ON CHIP POWER MONITOR RC OSCILLATOR WITH CLOCK DOUBLER OPTION OSCILLATOR POWER ON RESET BROWNOUT RESET 002aaa968 Fig 8 P89LPC9103 block diagram 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved 10 of 91 User manual Rev 01 11 February 2005 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual P89LPC9107 ACCELERATED 2 CLOCK 80C51 CPU Pa 1kB TAD FLASH gt lt RXD internal bus 128 BYTE PORT 0 PO 1 5 P0 7 CONFIGURABLE I Os ADC1 DAC1 AD12 KBI1 REALTIME cLocK KBI2 SYSTEM TIMER WATCHDOG TIMER
52. No liability will be accepted by the publisher for any consequence of its use Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights Date of release 11 February 2005 Document number 9397 750 13919 Published in the Netherlands
53. R A Interrupt if enabled shared with WDT Fig 26 Real time clock system timer block diagram m a i RTC underflow flag RTC enable RTC clk select ERTC 002aab227 9397 750 13919 9 1 9 2 9 3 Real time clock source RTCS1 0 RTCCON 6 5 are used to select either the external clock input or CCLK as the clock source for the RTC if either the Internal RC oscillator or the internal WD oscillator is used as the CCLK If CCLK is derived from the external clock input on P0 5 then the RTC can use CCLK external clock input DIVM or the external input as its clock source Changing RTCS1 0 RTCS1 0 cannot be changed if the RTC is currently enabled RTCCON 0 1 Setting RTCEN and updating RTCS1 0 may be done in a single write to RTCCON However if RTCEN 1 this bit must first be cleared before updating RTCS1 0 Real time clock interrupt wake up If ERTC RTCCON 1 EWDRT IEN1 6 0 and EA IENO 7 are set to logic 1 RTCF can be used as an interrupt source This interrupt vector is shared with the watchdog timer It can also be a source to wake up the device Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 52 of 91 Philips Semiconductors UM10112 P89LPC9102 9103 9107 User manual 9 4 Reset sources affecting the Real time clock Only power on reset will reset the Real time Clock and its associated SFRs to their default
54. Rev 01 11 February 2005 29 of 91 Philips Semiconductors UM1 01 1 2 9397 750 13919 3 2 4 3 2 5 3 2 6 P89LPC9102 9103 9107 User manual See Table 10 An interrupt if enabled will be generated after all selected channels have been converted If only a single channel is selected this is equivalent to single channel single conversion mode This mode is selected by setting the SCAN1 bit in the ADMODA register Table 11 Result registers and conversion results for fixed channel continuous conversion mode Result register Contains AD1DATO Selected channel first conversion result AD1DAT1 Selected channel second conversion result AD1DAT2 Selected channel third conversion result AD1DAT3 Selected channel forth conversion result Auto scan continuous conversion mode Any combination of the four input channels can be selected for conversion by setting a channel s respective bit in the ADINS register The channels are converted from LSB to MSB order in ADINS A conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel See Table 10 An interrupt if enabled will be generated after all selected channels have been converted The process will repeat starting with the first selected channel Additional conversion results will again cycle through the result registers of the selected channels overwriting the previous results
55. Table 10 An interrupt if enabled will be generated after the conversion completes The input channel is selected in the ADINS register This mode is selected by setting the SCAN1 bit in the ADMODA register Table 10 Input channels and Result registers for fixed channel single auto scan single and autoscan continuous conversion modes Result register Input channel Result register Input channel AD1DATO AD10 AD1DAT2 AD12 AD1DAT1 AD11 AD1DAT3 AD13 Fixed channel continuous conversion mode A single input channel can be selected for continuous conversion The results of the conversions will be sequentially placed in the four result registers Table 11 An interrupt if enabled will be generated after every four conversions Additional conversion results will again cycle through the four result registers overwriting the previous results Continuous conversions continue until terminated by the user This mode is selected by setting the SCC1 bit in the ADMODA register Auto scan single conversion mode Any combination of the four input channels can be selected for conversion by setting a channel s respective bit in the ADINS register The channels are converted from LSB to MSB order in ADINS A single conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel Koninklijke Philips Electronics N V 2004 All rights reserved User manual
56. To TIMER 0 AND OSCILLATOR C gt TIMER J CIN1A PROGRAMMABLE ceu K comparaTORS OSCILLATOR DIVIDER clock CIN1B N CLKOUT CONFIGURABLE ON CHIP POWER MONITOR CLKIN OSCILLATOR RC OSCILLATOR POWER ON RESET WITH CLOCK BROWNOUT RESET DOUBLER OPTION 002aab100 Fig 9 P89LPC9107 block diagram 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 11 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual 1 3 Special function registers Remark Special Function Registers SFRs accesses are restricted in the following ways e User must not attempt to access any SFR locations not defined e Accesses to any defined SFR locations must be strictly for the functions for the SFRs e SFR bits labeled 0 or 1 can only be written and read as follows Unless otherwise specified must be written with 0 but can return any value when read even if it was written with 0 It is a reserved bit and may be used in future derivatives 0 must be written with 0 and will return a 0 when read 1 must be written with 1 and will return a 1 when read 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 12 of 91 jenuew s s g00z Aseniqas LL LO Ady 1640 L 6L6
57. UM10112 P89LPC9102 9103 9107 User manual eee Rev 01 11 February 2005 User manual H Document information Info Content P89LPC9102 P89LPC9103 P89LPC9107 Technical information for the P89LPC9102 P89LPC9103 and P89LPC9107 devices Keywords Abstract PHILIPS Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Revision history Rev Date Description 01 20050211 Initial version 9397 750 13919 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 2 of 91 Philips Semiconductors UM10112 1 Introduction P89LPC9102 9103 9107 User manual The P89LPC9102 9103 9107 are single chip microcontrollers designed for applications demanding high integration low cost solutions over a wide range of performance requirements The P89LPC9102 9103 9107 is based on a high performance processor architecture that executes instructions in two to four clocks six times the rate of standard 80C51 devices Many system level functions have been incorporated into the P89LPC9102 9103 9107 in order to reduce component count board space and system cost 1 1 Logic symbols Voo Vss DAC1 4 AD13 CINIA gt Pont RST CLKIN gt CMPREF lt _ gt TO AD11 gt KBI2 gt ane CINIB PORT 0 P89LPC9102 AD10 gt KBI1 gt CLKOUT T1
58. able this block regardless of RTCEN 1 ERTC Real time Clock interrupt enable The Real time Clock shares the same interrupt as the watchdog timer Note that if the user configuration bit WOTE UCFG1 7 is logic 0 the watchdog timer can be enabled to generate an interrupt Users can read the RTCF RTCCON 7 bit to determine whether the Real time Clock caused the interrupt 2 4 reserved RTCSO Real time Clock source select see Table 41 6 RTCS1 RTCF Real time Clock Flag This bit is set to logic 1 when the 23 bit Real time Clock reaches a count of logic 0 It can be cleared in software 10 UART P89LPC9103 P89LPC9107 9397 750 13919 The P89LPC9103 9107 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source The P89LPC9103 9107 does include an independent Baud Rate Generator The baud rate can be selected from the oscillator divided by a constant Timer 1 overflow or the independent Baud Rate Generator In addition to the baud rate generation enhancements over the standard 80C51 UART include Framing Error detection break detect automatic address recognition selectable double buffering and several interrupt options The UART can be operated in four modes as described in the following sections 10 1 Mode 0 Serial data enters and exits through RXD TXD outputs the shift clock 8 bits are transmitted or received LSB first The baud rate is
59. address low E6H 00 00000000 FMCON Program Flash Control E4H BUSY HVA HVE SV Ol 70 01110000 Read Program Flash Control FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD Write 7 6 5 4 3 2 1 0 FMDATA Program Flash data E5H 00 00000000 IENO Interrupt enable 0 A8H EA EWDRT EBO ET1 ETO 00 00000000 s1O ONPUOTIWAS sdijiud jenuew J9Sf 2016 016 20169d 168d CLLOLINN jenuew 1 sN soog Aseniqas LL LO Ady L6 40 HL 6L6EL OSZ Z6 6 pansased S Y u IY Y0OZ A N S91u0149813 Sdiliyd Oxf PUIUOY Table 4 P89LPC9102 special function registers continued indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary Bit address EF EE ED EC EB EA E9 E8 IEN1 Interrupt enable 1 E8H EAD EC EKBI ool 00x00000 Bit address BF BE BD BC BB BA B9 B8 IPO Interrupt priority O B8H PWDRT PBO PT1 PTO ool x0000000 IPOH Interrupt priority O high B7H PWDRT PBOH PT1H PTOH ool x0000000 H Bit address FF FE FD FC FB FA F9 F8 IP1 Interrupt priority 1 F8H PAD PC PKBI ool 00x00000 IP1H Interrupt priority 1 high F7H PADH PCH PKBIH ool 00x00000 KBCON Keypad control register 94H PATN KBIF ool xxxxxx00 _SEL KBMASK Keypad interrupt mask 86H KBMASK KBMASK 00 XXXXX00X register
60. al interrupt input If enabled when the P89LPC9102 9103 9107 is put into Power down mode or Idle mode the interrupt will cause the processor to wake up and resume operation Refer to Section 6 3 Power reduction modes for details 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 35 of 91 Philips Semiconductors UM10112 P89LPC9102 9103 9107 User manual RTCF ERTC RTCCON 1 WDOVF BOF EBO EKBI EWDRT CMF EC EA IEO 7 TF1 ET1 TFO ETO ENADCI1 TH ADCI1 ENBI1 BNDI1 EAD ob wake up if in power down interrupt to CPU 002aaa976 Fig 14 Interrupt sources interrupt enables and power down wake up sources P89LPC9102 RTCF ERTC RTCCON 1 WDOVF BOF EBO EKBI EWDRT CMF EC ot EA IEO 7 TF1 ET1 TI and RI RI ES ESR TI EST TFO ETO ENADCI1 ADCI1 ENBI1 BNDI1 EAD wake up if in power down interrupt to CPU 002aaa977 Fig 15 Interrupt sources interrupt enables and power down wake up sources P89LPC9103 P89LPC9107 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual 5 I O ports The P89LPC9102 9103 9107 has t
61. all respects except baud rate The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Section 10 6 Baud Rate generator and selection on page 55 In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in Mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 SFR space The UART SFRs are at the following locations shown in Table 44 Table 44 UART SFR addresses Register Description SFR location PCON Power Control 87H SCON Serial Port UART Control 98H SBUF Serial Port UART Data Buffer 99H SADDR Serial Port UART Address A9H SADEN Serial Port UART Address Enable B9H SSTAT Serial Port UART Status BAH BRGR1 Baud Rate Generator Rate HIGH Byte BFH BRGRO Baud Rate Generator Rate LOW Byte BEH BRGCON Baud Rate Generator Control BDH Baud Rate generator and selection The P89LPC9103 9107 enhanced UART has an independent Baud Rate Generator The baud rate is determined by a value programmed into the BRGR1 and BRGRO SFRs The UART can use either Timer 1 or the baud rate generator output as determined by BRGCON 2 1 see Figure 27 Note that Timer T1 is further divided by 2 if the SMOD1 bit PCON 7 is set The independent Baud Rate Generator uses CCLK Updating the BRGR1 and BRGRO SFRs The baud rate SFRs
62. are in input only high impedance state after power up BRGR1 and BRGRO must only be written if BRGEN in BRGCON SFR is logic 0 If any are written while BRGEN 1 the result is unpredictable The RSTSRC register reflects the cause of the UM10112 reset Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset value is xx110000 After reset the value is 111001x1 i e PRE2 to PREO are all logic 1s WDRUN 1 and WDCLK 1 WDTOF bit is logic 1after watchdog timer reset and is logic 0 after power on reset Other resets will not affect WDTOF On power on reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM register The only reset source that affects these SFRs is power on reset s1o ONpuOTIWAS sdijiud Jenuew 13SN 2016 016 20L6 Dd 168d CLLOLINN Philips Semiconductors UM10112 1 4 Memory organization P89LPC9102 9103 9107 User manual O3FFh 0300h 02FFh 0200h 01FFh 0100h OOFFh 000h SECTOR 3 SECTOR 2 SECTOR 1 SECTOR 0 1 kB flash code memory space Fig 10 P89LPC9102 9103 9107 memory map SPECIAL FUNCTION REGISTERS DIRECTLY ADDRESSABLE DATA 128 BYTES ON CHIP DATA MEMORY STACK DIRECT AND INDIRECT ADDRESS 4 REG BANKS R 7 0 data memory DATA IDATA 002aab049 The various P89LPC9102 9103 9107 memory spaces are as follows DATA 128 bytes of i
63. are written while BRGEN 1 the result is unpredictable The RSTSRC register reflects the cause of the UM10112 reset Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset value is xx110000 After reset the value is 111001x1 i e PRE2 to PREO are all logic 1s WDRUN 1 and WDCLK 1 WDTOF bit is logic 1after watchdog timer reset and is logic 0 after power on reset Other resets will not affect WDTOF On power on reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM register The only reset source that affects these SFRs is power on reset s1o ONpuOTIWAS sdijiud Jenuew 13SN 2016 016 20L6 Dd 168d CLLOLINN jenuew Jesp soog Aseniqas LL LO Ady L6 40 02 6L6EL OSZ L666 paniased SUSU IY 700 A N S9140149813 Sdiliyd Oxf PUIUOY Table 6 P89LPC9107 special function registers indicates SFRes that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary Bit address E7 E6 E5 E4 E3 E2 E1 E0 ACC Accumulator EOH 00 00000000 ADCON1 A D control register 1 97H ENBI1 ENADCI1 TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10 00 00000000 ADINS A D input select A3H ADI13 AD12 ADI11 AD10 00 00000000 ADMODA A D mode register A COH BNDI1 BURST1 SCC1 SCAN1 00 0000
64. ation ranking is only used to resolve pending requests of the same priority level 4 1 Interrupt priority structure Table 22 Interrupt priority level Priority bits IPxH IPx Interrupt priority level 0 0 Level 0 lowest priority 0 1 Level 1 1 0 Level 2 1 1 Level 3 There are four SFRs associated with the four interrupt levels IPO IPOH IP1 IP1H Every interrupt has two bits in IPx and IPxH x 0 1 and can therefore be assigned to one of four levels as shown in Table 22 Table 23 Summary of interrupts Description Interrupt flag Vector Interrupt enable Interrupt Arbitration Power bit s address bit s priority ranking down wake up Timer 0 interrupt TFO OOOBh ETO IENO 1 IPOH 1 IPO 1 4 No Timer 1 interrupt TF1 001Bh ET1 IENO 3 IPOH 3 IP0 3 10 No Serial port Tx and Rx 9103 TI and RI 0023h ES ESR IENO 4 IPOH 4 IP0 4 13 No 9107 Serial port Rx 9103 9107 RI Brownout detect BOF 002Bh EBO IENO 5 IPOH 5 IP0 5 2 Yes Watchdog timer Real time clock WDOVF RTCF 0053h EWDRT IEN0 6 IPOH 6 IP0 6 3 Yes KBI interrupt KBIF 003Bh EKBI IEN1 1 IPOH 0 IP0 0 8 Yes Comparator 1 interrupt CMF1 0043h EC IEN1 2 IPOH 0 IP0 0 11 Yes Serial port Tx 9103 9107 TI 006Bh EST IEN1 6 IPOH 0 IP0 0 12 No ADC ADCI1 BNDI1 0073h EAD IEN1 7 IP1H 7 IP1 7 15 lowest No 4 1 1 External interrupt inputs The P89LPC9102 9103 9107 has a Keypad Interrupt function This can be used as an extern
65. ative to DPTR value MOV DPTR data16 Load the Data Pointer with a 16 bit constant MOVC A A DPTR Move code byte relative to DPTR to the accumulator MOVX A DPTR Move data byte the accumulator to data memory relative to DPTR 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 75 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual MOVX DPTR A Move data byte from data memory relative to DPTR to the accumulator Also any instruction that reads or manipulates the DPH and DPL registers the upper and lower bytes of the current DPTR will be affected by the setting of DPS The MOVX instructions have limited application for the P89LPC9102 9103 9107 since the part does not have an external data bus However they may be used to access Flash configuration information see Flash Configuration section or auxiliary data XDATA memory Bit 2 of AUXR1 is permanently wired as a logic 0 This is so that the DPS bit may be toggled thereby switching Data Pointers simply by incrementing the AUXR1 register without the possibility of inadvertently altering other bits in the register 15 Flash memory 9397 750 13919 15 1 15 2 15 3 The P89LPC9102 9103 9107 Flash memory provides in circuit electrical erasure and programming The Flash can be read and written as bytes The Sector and Page Erase functions can erase any
66. bidirectional mode The open drain port configuration is shown in Figure 17 An open drain port pin has a Schmitt triggered input that also has a glitch suppression circuit Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 38 of 91 Philips Semiconductors UM1 01 1 2 5 4 5 5 9397 750 13919 P89LPC9102 9103 9107 User manual Please refer to the P89LPC9102 9103 9107 data sheet Dynamic characteristics for glitch filter specifications PORT t PIN port latch data J gt t input data glitch rejection 002aaa915 Fig 17 Open drain output Input only configuration The input port configuration is shown in Figure 18 It is a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC9102 9103 9107 data sheet Dynamic characteristics for glitch filter specifications input PORT data 4 PIN glitch rejection 002aaa916 Fig 18 Input only Push pull output configuration The push pull output configuration has the same pull down structure as both the open drain and the quasi bidirectional output modes but provides a continuous strong pull up when the port latch contains a logic 1 The push pull mode may be used when more source current is needed from a port output The push pull port configuration is shown in Figure 19 A push pull port pin has a Schmitt triggered
67. bits 6 2 TRIM 2 or 7 as required and writing the result to this register 3 TRIM 3 4 TRIM 4 5 TRIM 5 6 ENCLK when 1 CCLK 2 is output on the CLKOUT pin 7 RCCLK when 1 selects the RC Oscillator output as the CPU clock CCLk 2 5 Watchdog oscillator option The Watchdog has a separate oscillator which has a frequency of 400 kHz This oscillator can be used to save power when a high clock frequency is not needed 2 6 External clock input option In this configuration the processor clock is derived from an external source driving the PO 5 CMPREF CLKIN pin The rate may be from 0 Hz up to 18 MHz This pin may also be used as a standard port pin When using an external clock input frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at power up until Vpp has reached its specified level When system power is removed Vpp will fall below the minimum specified operating voltage When using an external clock input frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when Vpp falls below the minimum specified operating voltage These requirements for clock frequencies above 12 MHz do not apply when using the internal RC oscillator in clock doubler mode 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 26 of 91
68. cle aborted due to an interrupt or reset FMCMD 0 W Command byte bit 0 1 SV R Security violation Set when an attempt is made to program erase or CRC a secured sector or page FMCMD 1 W Command byte bit 1 2 HVE R High voltage error Set when an error occurs in the high voltage generator FMCMD 2 W Command byte bit 2 3 HVA R High voltage abort Set if either an interrupt or a brown out is detected during a program or erase cycle Also set if the brown out detector is disabled at the start of a program or erase cycle FMCMD 3 W Command byte bit 3 4 7 R reserved 4 7 FMCMD 4 W Command byte bit 4 4 7 FMCMD 5 W Command byte bit 5 4 7 FMCMD 6 W Command byte bit 6 4 7 FMCMD 7 W Command byte bit 7 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 78 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual An assembly language routine to load the page register and perform an erase program operation is shown below KKK KEKE KEK KERR KKK EKER RK KERR KEKE RRR KEKE KK ERK KKK KEK KKKEKEKE 1 pgm user code skkxk xkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk k I i Inputs R3 number of bytes to program byte R4 page address MSB byte a R5 page address LSB byte i R7 pointer to data buffer in RAM byte Outputs R7 status byte s C clear on no er
69. d in RB8 The UART can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8 1 This feature is enabled by setting bit SM2 in SCON One way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that follow The slaves that weren t being addressed leave their SM2 bits set and go on about their business ignoring the subsequent data bytes Note that SM2 has no effect in Mode 0 and must be logic 0 in Mode 1 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 63 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual 10 20 Automatic address recognition Automatic address recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons This feature saves a great deal of software overhead b
70. d sector x CANNOT be erased in ISP or IAP modes 3 7 reserved Table 79 Effects of Security Bits EDISx SPEDISx MOVCDISx Effects on Programming 0 0 0 None 0 0 1 Security violation flag set for sector CRC calculation for the specific sector Security violation flag set for global CRC calculation if any MOVCDISx bit is set Cycle aborted Memory contents unchanged CRC invalid Program erase commands will not result in a security violation 0 1 x Security violation flag set for program commands or an erase page command Cycle aborted Memory contents unchanged Sector erase and global erase are allowed 1 X X Security violation flag set for program commands or an erase page command Cycle aborted Memory contents unchanged Global erase is allowed 15 12 Boot Vector register Table 80 Boot Vector BOOTVEC bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BOOTV4 BOOTV3 BOOTV2 BOOTV1 BOOTVO Factory default 0 0 0 1 1 1 1 1 value Table 81 Boot Vector BOOTVEC bit description Bit Symbol Description 0 4 BOOTV 0 4 Boot vector If the Boot Vector is selected as the reset address the P89LPC9102 9103 9107 will start execution at an address comprised of 00h in the lower eight bits and this BOOTVEC as the upper eight bits after a reset 5 7 reserved continued gt gt 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 Februar
71. d to speed up LOW to HIGH transitions on a quasi bidirectional port pin when the port latch changes from a logic 0 to a logic 1 When this occurs the strong pull up turns on for two CPU clocks quickly pulling the port pin HIGH The quasi bidirectional port configuration is shown in Figure 16 Although the P89LPC9102 9103 9107 is a 3 V device most of the pins are 5 V tolerant If 5 V is applied to a pin configured in quasi bidirectional mode there will be a current flowing from the pin to Vpp causing extra power consumption Therefore applying 5 V to pins configured in quasi bidirectional mode is discouraged A quasi bidirectional port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC9102 9103 9107 data sheet Dynamic characteristics for glitch filter specifications port latch data VDD 2 CPU P CLOCK DELAY strong very weak weak gt o input data 3 glitch rejection 002aaa914 Fig 16 Quasi bidirectional output 9397 750 13919 5 3 Open drain output configuration The open drain output configuration turns off all pull ups and only drives the pull down transistor of the port pin when the port latch contains a logic 0 To be used as a logic output a port configured in this manner must have an external pull up typically a resistor tied to Vpp The pull down for this mode is the same as for the quasi
72. disabled Note that except for the first character written when buffer is empty the location of the transmit interrupt is determined by INTLO When the first character is written the transmit interrupt is generated immediately after SBUF is written 5 CIDIS Combined Interrupt Disable When set 1 Rx and Tx interrupts are separate When cleared 0 the UART uses a combined Tx Rx interrupt like a conventional 80C51 UART This bit is reset to logic 0 to select combined interrupts 6 INTLO Transmit interrupt position When cleared 0 the Tx interrupt is issued at the beginning of the stop bit When set 1 the Tx interrupt is issued at end of the stop bit Must be logic 0 for mode 0 Note that in the case of single buffering if the Tx interrupt occurs at the end of a STOP bit a gap may exist before the next start bit 7 DBMOD Double buffering mode When set 1 enables double buffering Must be logic 0 for UART mode 0 In order to be compatible with existing 80C51 devices this bit is reset to logic 0 to disable double buffering 9397 750 13919 10 10 More about UART Mode 0 In Mode 0 a write to SBUF will initiate a transmission At the end of the transmission TI SCON 1 is set which must be cleared in software Double buffering must be disabled in this mode Reception is initiated by clearing RI SCON 0 Synchronous serial transfer occurs and RI will be set again at the end of the transfer When RI is
73. e OSCCLK frequency CCLK CPU clock output of the DIVM clock divider There are two CCLK cycles per machine cycle and most instructions are executed in one to two machine cycles two or four CCLK cycles RCCLK The internal 7 373 MHz RC oscillator output 14 7456 MHz with clock doubler enabled PCLK Clock for the various peripheral devices and is CCLK 2 Clock output The P89LPC9102 9103 9107 supports a user selectable clock output function on the CLKOUT pin allowing external devices to synchronize to the P89LPC9102 9103 9107 This output is enabled by the ENCLK bit in the TRIM register The frequency of this clock output is that of the CCLK If the clock output is not needed in Idle mode it may be turned off prior to entering Idle saving additional power Note on reset the TRIM SFR is initialized with a factory preprogrammed value Therefore when setting or clearing the ENCLK bit the user should retain the contents of other bits of the TRIM register This can be done by reading the contents of the TRIM register into the ACC for example modifying bit 6 and writing this result back into the TRIM register Alternatively the ANL direct or ORL direct instructions can be used to clear or set bit 6 of the TRIM register On chip RC oscillator option with clock doubler mode The P89LPC9102 9103 9107 has a TRIM register that can be used to tune the frequency of the RC oscillator During reset the TRIM value i
74. e P89LPC9102 9103 9107 incorporates power monitoring functions designed to prevent incorrect operation during initial power on and power loss or reduction during operation This is accomplished with two hardware functions Power on Detect and Brownout Detect Brownout detection The Brownout Detect function determines if the power supply voltage drops below a certain level The default operation for a Brownout Detection is to cause a processor reset However it may alternatively be configured to generate an interrupt by setting the BOI PCON 4 bit and the EBO IENO 5 bit Enabling and disabling of Brownout Detection is done via the BOPD PCON 5 bit bit field PMOD1 0 PCON 1 0 and user configuration bit BOE UCFG1 5 If BOE is in an unprogrammed state brownout is disabled regardless of PMOD1 0 and BOPD If BOE is in a programmed state PMOD1 0 and BOPD will be used to determine whether Brownout Detect will be disabled or enabled PMOD1 0 is used to select the power reduction mode If PMOD1 0 11 the circuitry for the Brownout Detection is disabled for lowest power consumption BOPD defaults to logic 0 indicating brownout detection is enabled on power on if BOE is programmed If Brownout Detection is enabled the brownout condition occurs when Vpp falls below the Brownout trip voltage Vgo see P89LPC9102 9103 Static characteristics and is negated when Vpp rises above Vego If Brownout Detection is disabled the operating voltage ran
75. e bit Note that if BOE UCFG1 5 is programmed BOF RSTSRC 5 will be set when POF is set If BOE is unprogrammed BOF is meaningless 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 42 of 91 Philips Semiconductors UM1 01 1 2 6 3 P89LPC9102 9103 9107 User manual Power reduction modes The P89LPC9102 9103 9107 supports three different power reduction modes as determined by SFR bits PCON 1 0 see Table 28 Table 28 Power reduction modes PMOD1 PMODO PCON 1 PCON 0 Description 0 0 Normal mode default no power reduction 0 1 Idle mode The Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated Any enabled interrupt source or reset may terminate Idle mode 1 0 Power down mode The Power down mode stops the oscillator in order to minimize power consumption The P89LPC9102 9103 9107 exits Power down mode via any reset or certain interrupts brownout Interrupt or keyboard Real time Clock System Timer Watchdog and comparator trips Waking up by reset is only enabled if the corresponding reset is enabled and waking up by interrupt is only enabled if the corresponding interrupt is enabled and the EA SFR bit IENO 7 is set In Power down mode the internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is
76. e sequentially executed successfully Between the two write instructions SFR reads are allowed but writes are not allowed The instructions should move A5H to the WFEED1 register and then 5AH to the WFEED2 register An incorrect feed sequence will cause an immediate watchdog reset The program sequence to feed the watchdog timer is as follows CLR EA disable interrupt MOV WFEED1 0A5h do watchdog feed part 1 MOV WFEED2 05Ah do watchdog feed part 2 SETB EA enable interrupt Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 70 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual This sequence assumes that the P89LPC9102 9103 9107 interrupt system is enabled and there is a possibility of an interrupt request occurring during the feed sequence If an interrupt was allowed to be serviced and the service routine contained any SFR writes it would trigger a watchdog reset If it is known that no interrupt could occur during the feed sequence the instructions to disable and re enable interrupts may be removed In Watchdog mode WDTE 1 writing the WDCON register must be IMMEDIATELY followed by a feed sequence to load the WDL to the 8 bit down counter and the WOCON to the shadow register If writing to the WDCON register is not immediately followed by the feed sequence a watchdog reset will occur For example setting WDRUN 1 OV ACC WDCON g
77. e start bit 8 data bits and two stop bit times For Modes 2 and 3 this consists of the start bit 9 data bits and one stop bit The break detect bit is cleared in software or by a reset The break detect can be used to reset the device and force the device into ISP mode This occurs if the UART is enabled and the the EBRR bit AUXR1 6 is set and a break occurs 10 15 Double buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted Double buffering allows transmission of a string of characters with only one stop bit between any two characters provided the next character is written between the start bit and the stop bit of the previous character Double buffering can be disabled If disabled DBMOD i e SSTAT 7 0 the UART is compatible with the conventional 80C51 UART If enabled the UART allows writing to SnBUF while the previous data is being shifted out 10 16 Double buffering in different modes Double buffering is only allowed in Modes 1 2 and 3 When operated in Mode 0 double buffering must be disabled DBMOD 0 10 17 Transmit interrupts with double buffering enabled Modes 1 2 and 3 Unlike the conventional UART when double buffering is enabled the Tx interrupt is generated when the double buffer is ready to receive new data The following occurs during a transmission assuming eight data bits 1 The double buffer is empty init
78. e wake up The Real time clock running from the internal RC oscillator can be used The power consumption of this oscillator is approximately 300 uA Instead if the WDT is used to generate interrupts the current is reduced to approximately 50 pA Whenever the WDT underflows the device will wake up 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 74 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual 14 Additional features The AUXR1 register contains several special purpose control bits that relate to several chip features AUXR1 is described in Table 69 Table 68 AUXR1 register address A2h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLKLP EBRR ENT1 ENTO SRST 0 DPS Reset 0 0 0 0 0 0 x 0 Table 69 AUXR1 register address A2h bit description Bit Symbol Description 0 DPS Data Pointer Select Chooses one of two Data Pointers 1 Not used Allowable to set to a logic 1 2 0 This bit contains a hard wired 0 Allows toggling of the DPS bit by incrementing AUXR1 without interfering with other bits in the register 3 SRST Software Reset When set by software resets the P89LPC9102 9103 9107 as if a hardware reset occurred ENTO When set the P1 2 pin is toggled whenever Timer 0 overflows The output frequency is therefore one half of the Timer 0 overflow rate Refer to the Timer Counters section for detai
79. enabled In Power down mode the power supply voltage may be reduced to the RAM keep alive voltage VRAM This retains the RAM contents at the point where Power down mode was entered SFR contents are not guaranteed after Vpp has been lowered to VRAM therefore it is recommended to wake up the processor via Reset in this situation Vpp must be raised to within the operating range before the Power down mode is exited When the processor wakes up from Power down mode it will start the oscillator immediately and begin execution when the oscillator is stable Oscillator stability is determined by counting 256 clocks after start up for the internal RC or external clock input configurations Some chip functions continue to operate and draw power during Power down mode increasing the total power used during power down These include Brownout Detect Watchdog timer if WOCLK WDCON 0O is logic 1 e Comparator Note Comparator can be powered down separately with PCONA 5 set to logic 1 and comparator disabled Real time Clock System Timer unless RTCPD is logic 1 1 1 Total Power down mode This is the same as Power down mode except that the Brownout Detection circuitry and the voltage comparator is also disabled to conserve additional power Note that a brownout reset or interrupt will not occur Voltage comparator interrupt and Brownout interrupt cannot be used as a wake up source The internal RC oscillator is disabled unless both the RC oscillato
80. enerator as the source for baud rates to UART in modes 1 and 3 see Table 45 for details reserved 9397 750 13919 10 8 10 9 Timer 1 Overflow SBRGS 0 J Ah PCLK based o Baud Rate Modes 1 and 3 SMOD1 0 T SBRGS 1 Baud Rate Generator CCLK based 002aaa419 Fig 27 Baud rate generation for UART Modes 1 3 Framing error A Framing error occurs when the stop bit is sensed as a logic 0 A Framing error is reported in the status register SSTAT In addition if SMODO PCON 6 is 1 framing errors can be made available in SCON 7 If SMODO is 0 SCON 7 is SMO It is recommended that SMO and SM1 SCON 7 6 are programmed when SMODO is logic 0 Break detect A break detect is reported in the status register SSTAT A break is detected when any 11 consecutive bits are sensed LOW Since a break condition also satisfies the requirements for a framing error a break condition will also result in reporting a framing error Once a break condition has been detected the UART will go into an idle state and remain in this idle state until a stop bit has been received The break detect can be used to reset the device and force the device into ISP mode by setting the EBRR bit AUXR1 6 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 56 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Table 48 Serial P
81. er uses FMADRLJ 3 0 and since the erase program command uses FMADRH and FMADRL 7 4 the user can write the byte location within the page register FMADRL 3 0 and the code memory page address FMADRH and FMADRL 7 4 at this time e Write the data to be programmed to FMDATA This will increment FMADRL pointing to the next byte in the page register e Write the address of the next byte to be programmed to FMADRL if desired Not needed for contiguous bytes since FMADRL is auto incremented All bytes to be programmed must be within the same page e Write the data for the next byte to be programmed to FMDATA e Repeat the writing of FMADRL and or FMDATA until all desired bytes have been loaded into the page register e Write the page address in user code memory to FMADRH and FMADRL 7 4 if not previously included when writing the page register address to FMADRL 3 0 e Write the erase program command 68H to FMCON starting the erase program cycle e Read FMCON to check status If aborted repeat starting with the LOAD command Table 70 Flash Memory Control register FMCON address E4h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol R HVA HVE SV Ol Symbol W FMCMD 7 FMCMD 6 FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 FMCMD O Reset 0 0 0 0 0 0 0 0 Table 71 Flash Memory Control register FMCON address E4h bit description Bit Symbol Access Description 0 Ol R Operation interrupted Set when cy
82. erial port mode see Table 50 SMO FE_ The use of this bit is determined by SMODO in the PCON register If SMODO 0 this bit is read and written as SMO which with SM1 defines the serial port mode If SMODO 1 this bit is read and written as FE Framing Error FE is set by the receiver when an invalid stop bit is detected Once set this bit cannot be cleared by valid frames but is cleared by software Note UART mode bits SMO and SM1 should be programmed when SMOD0 is logic 0 default mode on any reset Table 50 Serial Port modes SM0 SM1 UART mode UART baud rate 00 Mode 0 shift register CCLK 16 default mode on any reset 01 Mode 1 8 bit UART Variable see Table 45 10 Mode 2 9 bit UART CCLK 32 or CCLK 16 11 Mode 3 9 bit UART Variable see Table 45 Table 51 Serial Port Status register SSTAT address BAh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol DBMOD INTLO CIDIS DBISEL FE BR OE STINT Reset x xX X x X x 0 0 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 57 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Table 52 Serial Port Status register SSTAT address BAh bit description Bit Symbol 0 STINT Description Status Interrupt Enable When set 1 FE BR or OE can cause an interrupt The interrupt used vector address 0023h is shared with RI CIDIS 1 or the c
83. et WDCON SETB ACC 2 set WD_RUN 1 OV WDL 0FFh New count to be loaded to 8 bit down counter CLR EA disable interrupt OV WDCON ACC write back to WDCON after the watchdog is enabled a feed must occur immediately OV WFEED1 0A5h do watchdog feed part 1 OV WFEED2 05Ah do watchdog feed part 2 SETB EA enable interrupt In timer mode WDTE 0 WDCON is loaded to the control register every CCLK cycle no feed sequence is required to load the control register but a feed sequence is required to load from the WDL SFR to the 8 bit down counter before a time out occurs The number of Watchdog clocks before timing out is calculated by the following equations telks 2 PR wpL 1 1 1 where PRE is the value of prescaler PRE2 to PREO which can be the range 0 to 7 and WDL is the value of Watchdog load register which can be the range of 0 to 255 The minimum number of tclks is telks 2 04 1 1 33 2 The maximum number of tclks is telks 2 255 1 1 1048577 3 Table 67 shows sample P89LPC9102 9103 9107 timeout values Table 65 Watchdog Timer Control register WDCON address A7h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol PRE2 PRE1 PREO WDRUN WDTOF WDCLK Reset 1 1 1 x X 1 1 0 1 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 71 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102
84. fixed at 146 of the CPU clock frequency 10 2 Mode 1 10 bits are transmitted through TXD or received through RXD a start bit logic 0 8 data bits LSB first and a stop bit logic 1 When data is received the stop bit is stored in RB8 in Special Function Register SCON The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Section 10 6 Baud Rate generator and selection 10 3 Mode 2 11 bits are transmitted through TXD or received through RXD start bit logic 0 8 data bits LSB first a programmable 9th data bit and a stop bit logic 1 When data is transmitted the 9th data bit TB8 in SCON can be assigned the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 When data is received the 9th data bit goes into RB8 in Special Function Register SCON and the stop bit is not saved The baud rate is programmable to either 1 16 or 1 32 of the CCLK frequency as determined by the SMOD1 bit in PCON Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 54 of 91 Philips Semiconductors UM1 01 1 2 10 4 10 5 10 6 10 7 P89LPC9102 9103 9107 User manual Mode 3 11 bits are transmitted through TXD or received through RXD a start bit logic 0 8 data bits LSB first a programmable 9th data bit and a stop bit logic 1 Mode 3 is the same as Mode 2 in
85. g Flash as data storage IAP Lite The Flash code memory array of this device supports IAP Lite operations Any byte in a non secured sector of the code memory array may be read using the MOVC instruction and thus is suitable for use as non volatile data storage IAP Lite provides an erase program function that makes it easy for one or more bytes within a page to be Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 76 of 91 Philips Semiconductors UM1 01 1 2 9397 750 13919 P89LPC9102 9103 9107 User manual erased and programmed in a single operation without the need to erase or program any other bytes in the page IAP Lite is performed in the application under the control of the microcontroller s firmware using four SFRs and an internal 16 byte page register to facilitate erasing and programing within unsecured sectors These SFRs are e FMCON Flash Control Register When read this is the status register When written this is a command register Note that the status bits are cleared to 0 s when the command is written e FMDATA Flash Data Register Accepts data to be loaded into the page register e FMADRL FMADRH Flash memory address low Flash memory address high Used to specify the byte address within the page register or specify the page within user code memory The page register consists of 16 bytes and an update flag for each byte When a LOAD
86. g and status information returned The status information returned is shown in Table 73 If the application permits interrupts during erasing programming or CRC cycles the user code should check the carry flag after each erase programming or CRC operation to see if an error occurred If the operation was aborted the user s code will need to repeat the operation Table 73 IAP Lite error status Bit Flag Description O Ol Operation Interrupted Indicates that an operation was aborted due to an interrupt occurring during a program or erase cycle 1 SV Security Violation Set if program or erase operation fails due to security settings Cycle is aborted Memory contents are unchanged CRC output is invalid 2 HVE High Voltage Error Set if error detected in high voltage generation circuits Cycle is aborted Memory contents may be corrupted 3 7 undefined User configuration bytes A number of user configurable features of the P89LPC9102 9103 9107 must be defined at power up and therefore cannot be set by the program after start of execution These features are configured through the use of an Flash byte UCFG1 shown in Table 75 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 82 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Table 74 Flash User Configuration Byte UCFG1 bit allocation Bit 7 6 5 4 3 2 1 0 Sy
87. g power on or if selected via UCFG1 When functioning as a reset input a LOW on this pin resets the microcontroller causing I O ports and peripherals to take on their default states and the processor begins execution at address 0 Also used during a power on sequence to force In System Programming mode When using an oscillator frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at power up until Vpp has reached its specified level When system power is removed Vpp will fall below the minimum specified operating voltage When using an oscillator frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when Vpp falls below the minimum specified operating voltage Vss 3 l Ground 0 V reference Vpp 7 l Power supply This is the power supply voltage for normal operation as well as Idle mode and Power down mode Table 2 P89LPC9103 pin description Symbol Pin Type Description PO 1 to P0 5 1 0 Port 0 Port 0 is an I O port with a user configurable output type During reset Port 0 latches are configured in the input only mode with the internal pull up disabled The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 5 1 Port configurations for details The Keypad Interrupt feature
88. ge for Vpp is 2 4 V to 3 6 V If the P89LPC9102 9103 9107 device is to operate with a power supply that can be below 2 7 V BOE should be left in the unprogrammed state so that the device can operate at 2 4 V otherwise continuous brownout reset may prevent the device from operating Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 41 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual An application that uses the internal RC oscillator in clock doubler mode and uses Brownout detect should program the BOE bit so that a brownout condition will be detected when Vpp falls below 2 7 V If Brownout Detect is enabled BOE programmed PMOD1 0 11 BOPD 0 BOF RSTSRC 5 will be set when a brownout is detected regardless of whether a reset or an interrupt is enabled BOF will stay set until it is cleared in software by writing logic 0 to the bit Note that if BOE is unprogrammed BOF is meaningless If BOE is programmed and a initial power on occurs BOF will be set in addition to the power on flag POF RSTSRC 4 For correct activation of Brownout Detect certain Vpp rise and fall times must be observed Please see the P89LPC9102 9103 Data sheet for specifications Table 27 Brownout options BOE PMOD1 0 BOPD BOI EBO EA IENO 7 Description UCFG1 5 PCON 1 0 PCON 5 PCON 4 IENO 5 0 erased XX X X X X Brownout disabled
89. he contents of the Boot Vector is used as the high byte of the execution address and the low byte is set to OOH The factory default settings for these devices are shown in Table 72 below Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 80 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Table 72 Default Boot vector Product Flash size End address Signature bytes Sector Page Default Boot Mfgid Id Id2 Size size vector P89LPC9102 9103 9 1K x8 O3FFh 15h DDh 1Bh 256x8 16x8 OOh 107 15 6 Hardware activation of Boot Vector address Execution using the Boot Vector can be forced during a power on sequence see Figure 37 This is accomplished by powering up the device with the reset pin initially held low and holding the pin low for a fixed time after Vpp rises to its normal operating value This is followed by three and only three properly timed low going pulses Fewer or more than three pulses will result in the device not entering this mode Timing specifications may be found in the data sheet for this device This has the same effect as having a non zero status bit This allows an application to be built that will normally execute the user code but can be manually forced into executing from an alternate address VDD tvR tRH RST t RE oa 002aaa912 Fig 37 Hardware activation of Boot Vector address 9397 750 1391
90. hree I O ports Port 0 Port 1 and Port 3 Ports 0 and 1 are 8 bit ports and Port 3 is a 2 bit port The exact number of I O pins available depends upon the clock and reset options chosen see Table 24 Table 24 Number of I O pins available Clock source Reset option Number of I O pins 8 pin package On chip RC oscillator or watchdog oscillator No external reset except during power up 8 External RST pin supported 7 External clock input No external reset except during power up 7 External RST pin supported 6 Clock source Reset option Number of I O pins 8 pin package On chip oscillator or watchdog oscillator No external reset except during power up 8 1 Required for operation with external clock frequency above 12 MHz 5 1 Port configurations All but one I O port pin on the P89LPC9102 9103 9107 may be configured by software to one of four types on a pin by pin basis as shown in Table 25 These are quasi bidirectional standard 80C51 port outputs push pull open drain and input only Two configuration registers for each port select the output type for each port pin P1 5 RST can only be an input and cannot be configured Table 25 Port output configuration settings PxM1 y PxM2 y Port output mode 0 0 Quasi bidirectional 0 1 Push pull 1 0 Input only high impedance 1 1 Open drain 5 2 Quasi bidirectional output configuration Quasi bidirectional outputs can be used both as a
91. ializing the comparator Comparator 1 is configured to use the CIN1A and CMPREF inputs and generates an interrupt when the comparator output changes CMPINIT MOV PTOAD 030h Disable digital INPUTS on pins CINIA CMPREF ANL POM2 0CFh Disable digital OUTPUTS on pins that are used ORL P0M1 030h for analog functions CIN1A CMPREF MOV CMP1 020h Turn on comparator 1 and set up for Positive input on CINIA Negative input from CMPREF pin Output to CMP1 pin enabled CALL delayl0us start up for at least 10 microseconds before use ANL CMP1 0FEh Clear comparator 1 interrupt flag SETB EC Enable the comparator interrupt The priority is left at the current value SETB EA Enable the interrupt system if needed RET Return to caller The interrupt routine used for the comparator must clear the interrupt flag CMF1 before returning 12 Keypad interrupt KBI 9397 750 13919 The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern This function can be used for bus address recognition or keypad recognition The user can configure the port via SFRs for different tasks There are three SFRs used for this function The Keypad Interrupt Mask Register KBMASK is used to define which input pins connected to Port 0 are enabled to trigger the interrupt The Keypad Pattern Register KBPATN is used to define a pattern that
92. ially 2 The CPU writes to SBUF 3 The SBUF data is loaded to the shift register and a Tx interrupt is generated immediately 4 If there is more data go to 6 else continue 5 If there is no more data then If DBISEL is logic 0 no more interrupts will occur 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 61 of 91 Philips Semiconductors UM10112 P89LPC9102 9103 9107 User manual If DBISEL is logic 1 and INTLO is logic 0 a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter which is also the last data If DBISEL is logic 1 and INTLO is logic 1 a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter which is also the last data Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following 6 If there is more data the CPU writes to SBUF again Then If INTLO is logic 0 the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter If INTLO is logic 1 the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter Goto3 Fig
93. iconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits standard cells and or software described or contained herein in order to improve design and or 9397 750 13919 P89LPC9102 9103 9107 User manual performance When the product is in full production status Production relevant changes will be communicated via a Customer Product Process Change Notification CPCN Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no licence or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 89 of 91 Philips Semiconductors UM10112 18 Contents P89LPC9102 9103 9107 User manual 1 1 1 1 2 1 3 1 4 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 1 3 2 3 3 3 4 3
94. ion of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated RI 0 and either SM2 0 or the received stop bit 1 If either of these two conditions is not met the received frame is lost If both conditions are met the stop bit goes into RB8 the 8 data bits go into SBUF and RI is activated 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 59 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual TX clock fl fl fl fl fl fl fl fl jl fl fl fl fl fl write to fl SBUF shift ji ji 1 ji fl fl fl fl fl transmit tart TXB w Lo XD XXX XX e X Y stop bi TI d KO INTLO 0 INTLO 1 clock sant RXD arwa i Lo XXE XX EX E Xe XL Y stops RI receive 002aaa926 Fig 29 Serial Port Mode 1 only single transmit buffering case is shown 10 12 More about UART Modes 2 and 3 Reception is the same as in Mode 1 The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated a RI 0 and b Either SM2 0 or the received 9th data bit 1 If either of these conditions i
95. is loaded to the shift register and a Tx interrupt is generated immediately BOND 5 If there is more data go to 7 else continue on 6 6 If there is no more data then If DBISEL is logic 0 no more interrupt will occur If DBISEL is logic 1 and INTLO is logic 0 a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter which is also the last data If DBISEL is logic 1 and INTLO is logic 1 a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter which is also the last data 7 If there is more data the CPU writes to TB8 again 8 The CPU writes to SBUF again Then If INTLO is logic 0 the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter If INTLO is logic 1 the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter 9 Go to 4 10 Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following 10 19 Multiprocessor communications UART modes 2 and 3 have a special provision for multiprocessor communications In these modes 9 data bits are received or transmitted When data is received the 9th bit is store
96. l to analog converter output P0 5 CMPREF 11 1 0 P0 5 Port 0 bit 5 CLKIN CMPREF Comparator reference negative input l CLKIN External clock input PO 7 T1 8 VO P0 7 Port 0 bit 7 CLKOUT VO T1 Timer counter 1 external count input or overflow PWM output l CLKOUT Clock output P1 0 to P1 2 1 0 Port 1 Port 1 is an I O port with a user configurable output type During reset Port 1 P1 5 latches are configured in the input only mode with the internal pull up disabled The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected Each of the configurable port pins are programmed independently Refer to Section 5 1 Port configurations on page 37 for details P1 5 is input only All pins have Schmitt triggered inputs Port 1 also provides various special functions as described below P1 0 TXD 6 0 P1 0 Port 1 bit 0 O TXD Serial port transmitter data P1 1 RXD 9 1 0 P1 1 Port 1 bit 1 l RXD Serial port receiver data P1 2 T0 7 1 0 P1 2 Port 1 bit 2 1 0 TO Timer counter 0 external count input or overflow PWM output P1 5 RST 3 l P1 5 Port 1 bit 5 input only l RST External Reset input during Power on or if selected via UCFG1 When functioning as a reset input a LOW on this pin resets the microcontroller causing I O ports and peripherals to take on their default states and the processor begin
97. limit interrupt enable DAC output to a port pin with high impedance The ADODATS register is used to hold the value fed to the DAC After a value has been written to ADODAT3 the DAC output will appear on the DACO pin The DAC output is enabled by the ENDACO bit in the ADMODB register See Table 19 Clock divider The A D converter requires that its internal clock source be in the range of 500 kHz to 3 3 MHz to maintain accuracy A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose See Table 19 I O pins used with A D converter functions The analog input pins used with for the A D converter have a digital input and output function In order to give the best analog performance pins that are being used with the ADC or DAC should have their digital outputs and inputs disabled and have the 5 V tolerance disconnected Digital outputs are disabled by putting the port pins into the input only mode as described in the Port Configurations section see Table 25 Digital inputs will be disconnected automatically from these pins when the pin has been selected by setting its corresponding bit in the ADINS register and the A D or DAC has been enabled Pins selected in ADINS will be 3 V tolerant provided that the A D is enabled and the device is not in power down otherwise the pin will remain 5 V tolerant Power down and idle mode In idle mode the A D converter if enabled will continue to function and can ca
98. lips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 50 of 91 Philips Semiconductors UM10112 P89LPC9102 9103 9107 User manual TOC T 0 overflow Pos gt on T9 TFO gt interrupt TO pin l control 8 bits TOC T 1 toggle TRO eat TO pin ENTO overflow PCLK on TF1 gt interrupt control 8 bits TR1 oOo 002aab058 1 Tn pin functions available on P89LPC9102 P89LPC9107 Fig 24 Timer counter 0 Mode 3 two 8 bit counters PCLK overflow TFn gt interrupt reload THn on falling transition and 256 THn on rising transition toggle TRn ENTn 002aab059 1 Tn pin functions available on P89LPC9102 P89LPC9107 Fig 25 Timer counter 0 or 1 in mode 6 PWM auto reload 8 6 Timer overflow toggle output P89LPC9102 P89LPC9107 Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs The same device pins that are used for the TO and T1 count inputs and PWM outputs are also used for the timer toggle outputs This function is enabled by control bits ENTO and ENT1 in the AUXR1 register and apply to Timer 0 and Timer 1 respectively The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on In order for this mode to function the C T bit must be cleared selecting PCLK as the clock source for the timer 9 Real time clock system timer The
99. ls P89LPC9102 5 ENT1 When set the PO 7 pin is toggled whenever Timer 1 overflows The output frequency is therefore one half of the Timer 1 overflow rate Refer to the Timer Counters section for details P89LPC9102 6 EBRR UART Break Detect Reset Enable If logic 1 UART Break Detect will cause a chip reset and force the device into ISP mode P89LPC9103 7 CLKLP Clock Low Power Select When set reduces power consumption in the clock circuits Can be used when the clock frequency is 8 MHz or less After reset this bit is cleared to support up to 12 MHz operation 14 1 Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely as if an external reset or watchdog reset had occurred If a value is written to AUXR1 that contains a logic 1 at bit position 3 all SFRs will be initialized and execution will resume at program address 0000 Care should be taken when writing to AUXR1 to avoid accidental software resets 14 2 Dual Data Pointers The dual Data Pointers DPTR adds to the ways in which the processor can specify the address used with certain instructions The DPS bit in the AUXR1 register selects one of the two Data Pointers The DPTR that is not currently selected is not accessible to software unless the DPS bit is toggled Specific instructions affected by the Data Pointer selection are INC DPTR Increments the Data Pointer by 1 JMP A DPTR Jump indirect rel
100. ly configuration 39 Push pull output configuration 39 Port O analog functions 40 Additional port features 40 Power monitoring functions 41 Brownout detection 41 Power on detection s aunan 42 Power reduction modes 43 Reset 2c cite iad cee cece erect canes 45 ReSOLVOCION oii woe ob eee ewe ee es 46 Timers Oand1 22 20 c ee eee eee 47 Mode ie Sk lad nas a he chats gum eye haw Bee 48 Mod li 2 226 44een dey ck dee wider ae Yes 48 Mode 2 pocnes et tem a kw Ee A 49 Mode ee ccdiiei eiae a E 49 Mode 6 P89LPC9102 P89LPC9107 49 9397 750 13919 8 6 9 9 1 9 2 9 3 9 4 10 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 10 10 10 11 10 12 10 13 10 14 10 15 10 16 10 17 10 18 10 19 10 20 11 11 1 11 2 11 3 11 4 11 5 12 13 13 1 13 2 13 3 13 4 13 5 13 6 14 Timer overflow toggle output P89LPC9102 P89LPC9107 00 00 e eee 51 Real time clock system timer 51 Real time clock source 52 Changing RTCS1 0 52 Real time clock interrupt wake up 52 Reset sources affecting the Real time clock 53 UART P89LPC9103 P89LPC9107 54 MOG 0 isin cia eke basta ees whe 54 Mode d aaea e cers cece pace aR aotee ann ate 54 Mode 2 ih eio bobs bid a 54 Mode 23 iis deyi ea tod Gee es 55 SFR space isaac
101. ly if the AD10 input exceeded the boundary limits reserved ENDAC1 When 1 selects DAC mode for ADC1 when 0 selects ADC mode 4 reserved 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 33 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Table 19 A D Mode Register B ADMODB address Ath bit description Bit Symbol Description 5 CLKO Clock divider to produce the ADC clock Divides CCLK by the value indicated below 6 CLK1 The resulting ADC clock should be 3 3 MHz or less A minimum of 0 5 MHz is required to maintain A D accuracy PERE CLK2 0 divisor 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 Table 20 A D Input Select register ADINS address A3h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol AIN13 AIN12 AIN11 AIN10 Reset 0 0 0 0 0 0 0 0 Table 21 A D Input Select register ADINS address A3h bit description Bit Symbol Description 0 3 reserved AIN10 when set enables the AD10 pin for sampling and conversion 5 AIN11 when set enables the AD11 pin for sampling and conversion 6 AIN12 when set enables the AD12 pin for sampling and conversion 7 AIN13 when set enables the AD13 pin for sampling and conversion 4 Interrupts 9397 750 13919 The P89LPC9102 supports nine interrupt sources timers 0 and 1 brownout detect
102. mbol WDTE RPE BOE WDSE IRCDBL FOSC2 FOSC1 FOSCO Unprogrammed 0 1 1 0 0 0 1 1 value Table 75 Flash User Configuration Byte UCFG1 bit description Bit Symbol Description 0 FOSCO CPU oscillator type select See Section 2 Clocks on page 25 for additional information Combinations 1 FOSC1 other than those shown in Table 76 are reserved for future use and should not be used 2 FOSC2 3 IRCDBL When set 1 this bit doubles the frequency of the internal RC oscillator 4 WDSE Watchdog Safety Enable bit Refer to Table 76 for details 5 BOE Brownout Detect Enable see Section 6 1 Brownout detection on page 41 6 RPE Reset pin enable When set 1 enables the reset function of pin P1 5 When cleared P1 5 may be used as an input pin NOTE During a power up sequence the RPE selection is overridden and this pin will always functions as a reset input After power up the pin will function as defined by the RPE bit Only a power up reset will temporarily override the selection defined by RPE bit Other sources of reset will not override the RPE bit 7 WDTE Watchdog timer reset enable When set 1 enables the watchdog timer reset When cleared 0 disables the watchdog timer reset The timer may still be used to generate an interrupt Refer to Table 76 for details Table 76 Oscillator type selection FOSC 2 0 Oscillator configuration 000 undefined 001 undefined 010 undefi
103. mer modes are selected by timer mode bits TnM 2 0 000 8048 Timer TLn serves as 5 bit prescaler Mode 0 001 16 bit Timer Counter THn and TLn are cascaded there is no prescaler Mode 1 010 8 bit auto reload Timer Counter THn holds a value which is loaded into TLn when it overflows Mode 2 011 Timer 0 is a dual 8 bit Timer Counter in this mode TLO is an 8 bit Timer Counter controlled by the standard Timer 0 control bits THO is an 8 bit timer only controlled by the Timer 1 control bits see text Timer 1 in this mode is stopped Mode 3 100 Reserved User must not configure to this mode 101 Reserved User must not configure to this mode 110 PWM mode see Section 8 5 111 Reserved User must not configure to this mode 5 7 reserved 8 1 Mode 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer which is an 8 bit Counter with a divide by 32 prescaler Figure 21 shows Mode 0 operation In this mode the Timer register is configured as a 13 bit register As the count rolls over from all logic 1s to all logic Os it sets the Timer interrupt flag TFn The count input is enabled to the Timer when TRn 1 TRn is a control bit in the Special Function Register TCON Table 40 The 13 bit register consists of all 8 bits of THn and the lower 5 bits of TLn The upper 3 bits of TLn are indeterminate and should be ignored Setting the run flag TRn does not clear
104. n input and output without the need to reconfigure the port This is possible because when the port outputs a logic HIGH it is weakly driven allowing an external device to pull the pin LOW When the pin is driven LOW it is driven strongly and able to sink a large current There are three pull up transistors in the quasi bidirectional output that serve different purposes One of these pull ups called the very weak pull up is turned on whenever the port latch for the pin contains a logic 1 This very weak pull up sources a very small current that will pull the pin HIGH if it is left floating A second pull up called the weak pull up is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level This pull up provides the primary source current for a quasi bidirectional pin that is outputting a 1 If this pin is pulled LOW by an external device the weak pull up turns off and only the very weak 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 37 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual pull up remains on In order to pull the pin LOW under these conditions the external device has to sink enough current to overpower the weak pull up and pull the port pin below its input threshold voltage The third pull up is referred to as the strong pull up This pull up is use
105. n will cause a reset 5 BOPD Brownout Detect power down When logic 1 Brownout Detect is powered down and therefore disabled When logic 0 Brownout Detect is enabled Note BOPD must be logic 0 before any programming or erasing commands can be issued Otherwise these commands will be aborted 6 SMODO Framing Error Location When logic 0 bit 7 of SCON is accessed as SMO for the UART When logic 1 bit 7 of SCON is accessed as the framing error status FE for the UART P89LPC9103 7 SMOD1 Double Baud Rate bit for the serial port UART when Timer 1 is used as the baud rate source When logic 1 the Timer 1 overflow rate is supplied to the UART When logic 0 the Timer 1 overflow rate is divided by two before being supplied to the UART See Section 10 P89LPC9103 Table 31 Power Control register A PCONA address B5h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RTCPD VCPD ADPD SPD Reset 0 0 0 0 0 0 0 0 Table 32 Power Control register A PCONA address B5h bit description Bit Symbol Description 0 reserved 1 SPD Serial Port UART power down When logic 1 the internal clock to the UART is disabled Note that in either Power down mode or Total Power down mode the UART clock will be disabled regardless of this bit P89LPC9103 reserved i reserved 4 ADPD A D Converter power down When logic 1 turns off the clock to the ADC To fully power down the ADC the user should als
106. nce N ranges from 0 to 255 the CCLK frequency can be in the range Of fose to fosc 510 for N O CCLK fosc This feature makes it possible to temporarily run the CPU at a lower rate reducing power consumption By dividing the clock the CPU can retain the ability to respond to events other than those that can cause interrupts i e events that allow exiting the Idle mode by executing its normal program at a lower rate This can often result in lower power consumption than in Idle mode This can allow bypassing the start up time in cases where Power down mode would otherwise be used The value of DIVM may be changed by the program at any time without interrupting code execution Low power select The P89LPC9102 9103 9107 is designed to run at 18 MHz CCLK maximum However if CCLK is 8 MHZ or slower the CLKLP SFR bit AUXR1 7 can be set to a logic 1 to lower the power consumption further On any reset CLKLP is logic 0 allowing highest performance This bit can then be set in software if CCLK is running at 8 MHz or slower 3 A D converter 3 1 9397 750 13919 The P89LPC9102 9103 9107 has an 8 bit 4 channel multiplexed successive approximation analog to digital converter module ADC1 and one DAC module DAC1 A block diagram of the A D converter is shown in Figure 13 The A D consists of a 4 input multiplexer which feeds a sample and hold circuit providing an input signal to one of two comparator inputs The control logic in c
107. ncremented in response to a 1 to 0 transition on its corresponding external input pin TO or T1 The external input is sampled once during every machine cycle When the pin is HIGH during one cycle and LOW in the next cycle the count is incremented The new count value appears in the register during the cycle following the one in which the transition was detected Since it takes 2 machine cycles 4 CPU clocks to recognize a 1 to 0 transition the maximum count rate is 1 4 of the CPU clock frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for at least one full machine cycle The Timer or Counter function is selected by control bits TnC T x 0 and 1 for Timers 0 and 1 respectively in the Special Function Register TMOD Timer 0 and Timer 1 have five operating modes modes 0 1 2 3 and 6 which are selected by bit pairs TnM1 TnMO in TMOD and TnM2 in TAMOD Modes 0 1 2 and 6 are the same for both Timers Counters Mode 3 is different The operating modes are described later in this section Table 35 Timer Counter Mode register TMOD address 89h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol T1C T TiM1 T1MO TOC T TOM1 TOMO Reset 0 0 0 0 0 0 0 0 Table 36 Timer Counter Mode register TMOD address 89h bit description Bit Symbol Description 0 TOMO Mode Select for Timer 0 These bits are
108. ndicates SFRs that are bit addressable P89LPC9107 special function registers continued Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary FMDATA Program Flash data E5H 00 00000000 IENO Interrupt enable 0 A8H EA EWDRT EBO ES ESR ET1 ETO 00 00000000 Bit address EF EE ED EC EB EA E9 E8 IEN1 Interrupt enable 1 E8H EAD EST EC EKBI ool 00x00000 Bit address BF BE BD BC BB BA B9 B8 IPO Interrupt priority O B8H PWDRT PBO PS PSR PT1 PTO ool x0000000 IPOH Interrupt priority O high B7H PWDRT PBOH PSH PT1H PTOH ool x0000000 H PSRH Bit address FF FE FD FC FB FA F9 F8 IP1 Interrupt priority 1 F8H PAD PST PC PKBI ool 00x00000 IP1H Interrupt priority 1 high F7H PADH PSTH PCH PKBIH ool 00x00000 KBCON Keypad control register 94H PATN KBIF ool xxxxxx00 _SEL KBMASK Keypad interrupt mask 86H KBMASK KBMASK 00 XXXXX00X register 2 K KBPATN Keypad pattern register 93H KBPATN KBPATN FF XXXXX11Xx 2 1 Bit address 87 86 85 84 83 82 81 80 Po Port 0 80H CMPREF CINIA CIN1B KBI2 KBI1 2 CLKIN Bit address 97 96 95 94 93 92 91 90 P1 Port 1 90H RST RXD TXD POM1 Port 0 output mode 1 84H POM1 5 POM1 4 POM1 3 POM1 2 POM1 1 FF 11111111 POM2 Port 0 output mode 2 85H POM2 5 POM2 4 POM2 3 POM2 2 POM2 1 0
109. ned 011 Internal RC oscillator 7 373 MHz 2 5 100 Watchdog Oscillator 400 kHz 20 30 tolerance 101 undefined 110 undefined 111 External clock input on CLKIN 15 11 User security bytes This device has three security bits associated with each of its eight sectors as shown in Table 77 Table 77 Sector Security Bytes SECx bit allocation Bit 7 6 5 4 3 2 1 0 Symbol z EDISx SPEDISx MOVCDISx Unprogrammed 0 0 0 0 0 0 0 0 value 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 83 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Table 78 Sector Security Bytes SECx bit description Bit Symbol Description 0 MOVCDISx MOVC Disable Disables the MOVC command for sector x Any MOVC that attempts to read a byte in a MOVC protected sector will return invalid data This bit can only be erased when sector x is erased 1 SPEDISx Sector Program Erase Disable x Disables program or erase of all or part of sector x This bit and sector x are erased by either a sector erase command ISP IAP commercial programmer or a global erase command commercial programmer 2 EDISx Erase Disable ISP Disables the ability to perform an erase of sector x in ISP or IAP mode When programmed this bit and sector x can only be erased by a global erase command using a commercial programmer This bit an
110. nternal data memory space 00h 7Fh accessed via direct or indirect addressing using instruction other than MOVX and MOVC All or part of the Stack may be in this area SFR Special Function Registers Selected CPU registers and peripheral control and status registers accessible only via direct addressing CODE 64 kB of Code memory space accessed as part of program execution and via the MOVC instruction The P89LPC9102 9103 9107 has 1 kB of on chip Code memory Table 7 Data RAM arrangement Type Data RAM DATA Directly and indirectly addressable memory Size bytes 128 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 24 of 91 Philips Semiconductors UM1 01 1 2 2 Clocks P89LPC9102 9103 9107 User manual 9397 750 13919 2 1 2 2 2 3 2 4 Enhanced CPU The P89LPC9102 9103 9107 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices A machine cycle consists of two CPU clock cycles and most instructions execute in one or two machine cycles Clock definitions The P89LPC9102 9103 9107 device has several internal clocks as defined below OSCCLK Input to the DIVM clock divider OSCCLK is selected from one of the clock sources and can also be optionally divided to a slower frequency see Figure 12 and Section 2 8 CCLK modification DIVM register Note fosc is defined as th
111. nto and out of its own Mode 3 It can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt Mode 6 P89LPC9102 P89LPC9107 In this mode the corresponding timer can be changed to a PWM with a full period of 256 timer clocks see Figure 25 Its structure is similar to mode 2 except that e TFn n 0 and 1 for Timers 0 and 1 respectively is set and cleared in hardware e The LOW period of the TFn is in THn and should be between 1 and 254 and e The HIGH period of the TFn is always 256 THn e Loading THn with 00h will force the Tx pin HIGH loading THn with FFh will force the Tx pin LOW Note that interrupt can still be enabled on the LOW to HIGH transition of TFn and that TFn can still be cleared in software like in any other modes Table 39 Timer Counter Control register TCON address 88h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TF1 TR1 TFO TRO Reset 0 0 0 0 0 0 0 0 Table 40 Timer Counter Control register TCON address 88h bit description Bit Symbol Description Oo reserved 1 reserved 2 reserved 3 reserved 4 TRO Timer 0 Run control bit Set cleared by software to turn Timer Counter 0 on off 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 49 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Table 40 Timer Coun
112. o set the ENADC1 and ENADCO bits in registers ADCON1 and ADCONO 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 44 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Table 32 Power Control register A PCONA address B5h bit description Bit Symbol Description 5 VCPD Analog Voltage Comparator power down When logic 1 the voltage comparator is powered down User must disable the voltage comparator prior to setting this bit reserved RTCPD Real time Clock power down When logic 1 the internal clock to the Real time Clock is disabled 7 Reset The P1 5 RST pin can function as either an active LOW reset input or as a digital input P1 5 The RPE Reset Pin Enable bit in UCFG1 when set to 1 enables the external reset input function on P1 5 When cleared P1 5 may be used as an input pin NOTE During a power on sequence The RPE selection is overridden and this pin will always functions as a reset input An external circuit connected to this pin should not hold this pin LOW during a Power on sequence as this will keep the device in reset After power on this input will function either as an external reset input or as a digital input as defined by the RPE bit Only a power on reset will temporarily override the selection defined by RPE bit Other sources of reset will not override the RPE bit NOTE During
113. ombination with the successive approximation register SAR drives a digital to analog converter which provides the other input to the comparator The output of the comparator is fed to the SAR 002aaa975 Fig 13 A D converter block diagram Features e An 8 bit 4 channel multiplexed input successive approximation A D converter e Four A D result registers e Six operating modes Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 28 of 91 Philips Semiconductors UM1 01 1 2 9397 750 13919 3 2 3 2 1 3 2 2 3 2 3 P89LPC9102 9103 9107 User manual Fixed channel single conversion mode Fixed channel continuous conversion mode Auto scan single conversion mode Auto scan continuous conversion mode Dual channel continuous conversion mode Single step mode e Three conversion start modes Timer triggered start Start immediately Edge triggered e 8 bit conversion time of gt 3 9 us at an ADC clock of 3 3 MHz e Interrupt or polled operation e Boundary limits interrupt e DAC output to a port pin with high output impedance e Clock divider e Power down mode A D operating modes Fixed channel single conversion mode A single input channel can be selected for conversion A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel See
114. ombined TI RI CIDIS 0 When cleared 0 FE BR OE cannot cause an interrupt Note FE BR or OE is often accompanied by a RI which will generate an interrupt regardless of the state of STINT Note that BR can cause a break detect reset if EBRR AUXR1 6 is set to logic 1 OE Overrun Error flag is set if a new character is received in the receiver buffer while it is still full before the software has read the previous character from the buffer i e when bit 8 of a new byte is received while RI in SCON is still set Cleared by software BR Break Detect flag A break is detected when any 11 consecutive bits are sensed LOW Cleared by software FE Framing error flag is set when the receiver fails to see a valid STOP bit at the end of the frame Cleared by software DBISEL Double buffering transmit interrupt select Used only if double buffering is enabled This bit controls the number of interrupts that can occur when double buffering is enabled When set one transmit interrupt is generated after each character written to SBUF and there is also one more transmit interrupt generated at the beginning INTLO 0 or the end INTLO 1 of the STOP bit of the last character sent i e no more data in buffer This last interrupt can be used to indicate that all transmit operations are over When cleared 0 only one transmit interrupt is generated per character written to SBUF Must be logic 0 when double buffering is
115. ore disable the comparator interrupt prior to disabling the comparator Additionally the user should clear the comparator flag CMF1 after disabling the comparator 11 4 Comparator and power reduction modes The comparator may remain enabled when power down or Idle mode is activated but is disabled automatically in Total Power down mode If the comparator interrupt is enabled except in Total Power down mode a change of the comparator output state will generate an interrupt and wake up the processor The comparator consumes power in power down and Idle modes as well as in the normal operating mode This should be taken into consideration when system power consumption is an issue To minimize power consumption the user can power down the comparator by disabling the comparator and setting PCONA 5 to logic 1 or simply putting the device in Total Power down mode 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 66 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual CIN1A CIN1A C CMPREF Got Vper 1 23 V Goi 002aaa051 002aab052 a CP1 CN1 00 b CP1 CN1 01 CIN1B L CIN1B L CMPREF coi Vrer 1 23V vel 002aab053 002aab054 c CP1 CN1 10 d CP1 CN1 11 Fig 33 Comparator configurations 11 5 Comparator configuration example The code shown below is an example of init
116. ort Control register SCON address 98h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SMO0 FE SM1 SM2 REN TB8 amp RB8 TI RI Reset X xX xX xX xX xX 0 0 Table 49 Serial Port Control register SCON address 98h bit description Bit Symbol Description 0 RI Receive interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or approximately halfway through the stop bit time in Mode 1 For Mode 2 or Mode 3 if SMODO it is set near the middle of the 9th data bit bit 8 If SMODO 1 it is set near the middle of the stop bit see SM2 SCON 5 for exceptions Must be cleared by software 1 TI Transmit interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or at the stop bit see description of INTLO bit in SSTAT register in the other modes Must be cleared by software 2 RB8 The 9th data bit that was received in Modes 2 and 3 In Mode 1 SM2 must be 0 RB8 is the stop bit that was received In Mode 0 RB8 is undefined TB8 The 9th data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired REN Enables serial reception Set by software to enable reception Clear by software to disable reception SM2 Enables the multiprocessor communication feature in Modes 2 and 3 In Mode 2 or 3 if SM2 is set to 1 then RI will not be activated if the received 9th data bit RB8 is 0 In Mode 0 SM2 should be 0 In Mode 1 SM2 must be 0 6 SMi With SMO defines the s
117. ort control 98H SMO FE SM1 SM2 REN TB8 RB8 Tl RI 00 00000000 SSTAT Serial port extended status BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 00000000 register SP Stack pointer 81H 07 00000111 Bit address 8F 8E 8D 8C 8B 8A 89 88 TCON Timer 0 and 1 control 88H TF1 TR1 TFO TRO 00 00000000 THO Timer 0 high 8CH 00 00000000 TH1 Timer 1 high 8DH 00 00000000 TLO Timer 0 low 8AH 00 00000000 TL1 Timer 1 low 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H T1iM1 T1MO TOM1 TOMO 00 00000000 TRIM Internal oscillator trim register 96H RCCLK ENCLK TRIM 5 TRIM 4 TRIMS TRIM 2 TRIM 1 TRIM O 61 7 WDCON Watchdog control register A7H PRE2 PRE1 PREO WDRUN WDTOF WODCLK BSN WDL Watchdog load C1H FF 11111111 WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H 1 Unimplemented bits in SFRs labeled are X unknown at all times Unless otherwise specified ones should not be written to these bits since they may be used for other purposes in future derivatives The reset values shown for these bits are logic Os although they are unknown when read s1O ONPUOTIWAS sdijiud Jenuew J9Sf 2016 016 20169d 168d CLLOLINN jenuew 1 sN LO A3H goog Asenigas LL L6 40 6L 6L6EL OSZ L666 paniased S YGH IY 700 A N S91u0149813 Sdiliyd Afiyuuoy All ports are in input only high impedance state after power up BRGR1 and BRGRO must only be written if BRGEN in BRGCON SFR is logic 0 If any
118. r has been selected as the system clock AND the RTC is enabled The following are the wake up options supported Watchdog timer if WOCLK WDCON 9O is logic 1 Could generate Interrupt or Reset either one can wake up the device Keyboard Interrupt Real time Clock System Timer unless RTCPD i e PCONA 7 is logic 1 Note Using the internal RC oscillator to clock the RTC during power down may result in relatively high power consumption Lower power consumption can be achieved by using an external low frequency clock when the Real time Clock is running during power down 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 43 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Table 29 Power Control register PCON address 87h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SMOD1 SMODO BOPD BOI GF1 GFO PMOD1 PMODO Reset 0 0 0 0 0 0 0 0 Table 30 Power Control register PCON address 87h bit description Bit Symbol Description 0 PMODO Power Reduction Mode see Section 6 3 PMOD1 2 GFO General Purpose Flag 0 May be read or written by user software but has no effect on operation 3 GF1 General Purpose Flag 1 May be read or written by user software but has no effect on operation 4 BOI Brownout Detect Interrupt Enable When logic 1 Brownout Detection will generate a interrupt When logic 0 Brownout Detectio
119. r up all pins are in Input Only mode Please note that this is different from the LPC76x series of devices e After power up all I O pins except P1 5 may be configured by software e Pin P1 5 is input only Every output on the P89LPC9102 9103 9107 has been designed to sink typical LED drive current However there is a maximum total output current for all ports which must not be exceeded Please refer to the P89LPC9102 9103 9107 data sheet for detailed specifications All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals The slew rate is factory set to approximately 10 ns rise and fall times Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 40 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Table 26 Port output configuration Port pin Configuration SFR bits PxM1 y PxM2 y Alternate usage Notes PO 1 POM1 1 POM2 1 KBI1 AD10 Refer to Section 5 6 Port 0 P0 2 POM1 2 POM2 2 KBI2 AD11 ec Tor Usage as i analog inputs P0 3 POM1 3 POM2 3 KBI3 CIN1B AD12 P0 4 POM1 4 POM2 4 CIN1A AD13 DAC1 P0 5 POM1 5 POM2 5 KBI5 CMPREF CLKIN PO 7 POM1 7 POM2 7 T1 CLKOUT P1 0 P1M1 0 P1M2 0 TXD P1 1 P1M1 1 P1M2 1 RXD P1 2 P1M1 2 P1M2 2 TO P1 5 P1M1 5 P1M2 5 RST 6 Power monitoring functions 9397 750 13919 6 1 Th
120. register DFH BOF POF R_WD R_SF R_EX B RTCCON Real time clock control D1H RTCF RTCS1 RTCSO ERTC RTCEN se 011xxx00 RTCH Real time clock register high D2H ools 00000000 RTCL Real time clock register low D3H ools 00000000 SP Stack pointer 81H 07 00000111 TAMOD Timer 0 and 1 auxiliary mode 8FH TiM2 TOM2 00 XXxXOXxx0 Bit address 8F 8E 8D 8C 8B 8A 89 88 TCON Timer 0 and 1 control 88H TF1 TR1 TFO TRO 00 00000000 THO Timer 0 high 8CH 00 00000000 TH1 Timer 1 high 8DH 00 00000000 TLO Timer 0 low 8AH 00 00000000 TL1 Timer 1 low 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H TiM1 T1MO TOM1 TOMO 00 00000000 TRIM Internal oscillator trim register 96H RCCLK ENCLK TRIMS TRIM4 TRIMS TRIM 2 TRIM 1 TRIM O E 6 WDCON Watchdog control register A7H PRE2 PRE1 PREO WDRUN WDTOF WDCLK 4i WDL Watchdog load C1H FF 11111111 WFEED1 Watchdog feed 1 C2H WFEED2_ Watchdog feed 2 C3H 1 Unimplemented bits in SFRs labeled are X unknown at all times Unless otherwise specified ones should not be written to these bits since they may be used for other purposes in future derivatives The reset values shown for these bits are logic Os although they are unknown when read 2 All ports are in input only high impedance state after power up 3 The RSTSRC register reflects the cause of the UM10112 reset Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset val
121. ror set on error X skkxkx xkx xk xkxkkk kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk 1 LOAD EQU 00H EP EQU 68H PGM_USER MOV FMCON LOAD load command clears page register MOV FMADRH R4 get high address MOV FMADRL R5 get low address MOV A R7 i MOV RO A get pointer into R0 LOAD_PAGE MOV FMDAT RO write data to page register INC RO point to next byte DJNZ R3 LOAD_PAGE do until count is zero MOV FMCON EP else erase amp program the page OV R7 FMCON copy status for return MOV A R7 read status ANL A 0FH save only four lower bits JNZ BAD i CLR c clear error flag if good RET and return BAD SETB set error flag RET and return A C language routine to load the page register and perform an erase program operation is shown below include lt REG904 H gt unsigned char idata dbytes 16 data buffer unsigned char Fm_stat status result bit PGM_USER unsigned char unsigned char bit prog_fail 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved Rev 01 11 February 2005 79 of 91 User manual Philips Semiconductors UM1 01 1 2 9397 750 13919 15 4 15 5 P89LPC9102 9103 9107 User manual void main prog_fail PGM_USER 0x03 0xF0 bit PGM_USER unsigned char page_hi unsigned char page_lo define LOAD0x00 clear page register enable loading define EP0x68 erase amp program page unsigned char i loop count FMCON LOAD
122. rotection command If Programmed to 1 the Clear Configuration Protection CCP command is disabled in IAP Lite mode This command can still be used in ICP mode If programmed to 0 the CCP command can be used in all programming modes This bit is set by programming the BOOTSTAT register This bit is cleared by writing the Clear Configuration Protection CCP command in ICP mode 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 85 of 91 Philips Semiconductors UM10112 16 Instruction set P89LPC9102 9103 9107 User manual Table 84 Instruction set summary Mnemonic Description Bytes Cycles Hex code ARITHMETIC ADD A Rn Add register to A 1 1 28 to 2F ADD A dir Add direct byte to A 2 1 25 ADD A Ri Add indirect memory to A 1 1 26 to 27 ADD A data Add immediate to A 2 1 24 ADDC A Rn Add register to A with carry 1 1 38 to 3F ADDC A dir Add direct byte to A with carry 2 1 35 ADDC A Ri Add indirect memory to A with carry 1 1 36 to 37 ADDC A data Add immediate to A with carry 2 1 34 SUBB A Rn Subtract register from A with borrow 1 1 98 to 9F SUBB A dir Subtract direct byte from A with borrow 2 1 95 SUBB A Ri Subtract indirect memory from A with 1 1 96 to 97 borrow SUBB A data Subtract immediate from A with borrow 2 1
123. s execution at address 0 Also used during a power on sequence to force In System Programming mode When using an oscillator frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at power up until Vpp has reached its specified level When system power is removed Vpp Will fall below the minimum specified operating voltage When using an oscillator frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when Vpp falls below the minimum specified operating voltage Vss 4 l Ground 0 V reference Vpp 10 l Power supply This is the power supply voltage for normal operation as well as Idle mode and Power down mode 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 8 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual P89LPC9102 ACCELERATED 2 CLOCK 80C51 CPU Pa OR ee internal bus AD10 PORT 1 AD11 PAEAS C CONFIGURABLE I Os ADC1 DAC1 Aa DAC1 F PORT 0 REAL TIME CLOCK Poles PO 7 C gt CONFIGURABLE 1 Os C C SYSTEM TIMER KBI1 TO KEYPAD K X TIMER 0 KBI2 INTERRUPT TIMER 1 TH WATCHDOG TIMER X ANALOG CINTA AND OSCILLATOR COMPARATORS CIN1B NY PROGRAMMABLE OSCILLATOR DIVIDER CPU clock CLKOUT CO
124. s initialized to a factory pre programmed value to adjust the oscillator frequency to 7 373 MHz 1 Note the initial value is better than 1 please refer to the data sheet for behavior over temperature End user applications can write to the TRIM register to adjust the on chip RC oscillator to other frequencies Increasing the TRIM value will decrease the oscillator frequency The P89LPC9102 9103 9107 has a clock doubling mode that doubles the frequency provided by the internal RC oscillator to run at 14 7456 MHz This mode is enabled when the IRCDBL bit UCFG1 3 is set Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 25 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Table 8 On chip RC oscillator trim register TRIM address 96h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RCCLK ENCLK TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM O Reset 0 0 Bits 5 0 loaded with factory stored value during reset Table 9 On chip RC oscillator trim register TRIM address 96h bit description Bit Symbol Description 0 TRIM O Trim value Determines the frequency of the internal RC oscillator During reset these bits are 1 TRIM1 loaded with a stored factory calibration value When writing to either bit 6 or bit 7 of this register care should be taken to preserve the current TRIM value by reading this register modifying
125. s not met the received frame is lost and RI is not set If both conditions are met the received 9th data bit goes into RB8 and the first 8 data bits go into SBUF write to fl SBUF shift j I j j transmit tart TxD i LEXO be Ka Xba XE K bE KB KX THEY sop Bh a ee eee INTLO 0 INTLO RX clock L__JIL_IL_IL_JL___JLLLLLPLLPLILL_IL RXD aora ot Lo XO XEXE XbA X05 X e XE X eY stop bit RI d k SMODO 0 SMODO 1 I receive 002aaa927 Fig 30 Serial Port Mode 2 or 3 only single transmit buffering case is shown 10 13 Framing error and RI in Modes 2 and 3 with SM2 1 If SM2 1 in modes 2 and 3 RI and FE behaves as in the following table 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 60 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Table 53 FE and RI when SM2 1 in Modes 2 and 3 Mode PCON 6 RB8 RI FE SMODO 2 0 0 No RI when RB8 0 Occurs during STOP bit 1 Similar to Figure 30 with SMODO 0 RI occurs during Occurs during STOP bit RB8 one bit before FE 3 1 0 No RI when RB8 0 Will NOT occur 1 Similar to Figure 30 with SMODO 1 RI occurs during Occurs during STOP bit STOP bit 10 14 Break detect A break is detected when 11 consecutive bits are sensed LOW and is reported in the status register SSTAT For Mode 1 this consists of th
126. t and the ADCS11 and ADCS10 bits See Table 15 Start immediately Programming this mode immediately starts a conversion This start mode is available in all A D operating modes This mode is selected by setting the ADCS11 and ADCS10 bits in the ADCON1 register See Table 15 Edge triggered An A D conversion is started by rising or falling edge of P1 4 Once a conversion has started additional edge triggers are ignored until the conversion has completed The edge triggered start mode is available in all A D operating modes This mode is selected by setting the ADCS11 and ADCS10 bits in the ADCON1 register See Table 15 Boundary limits interrupt The A D converter has both a HIGH and LOW boundary limit register After the four MSBs have been converted these four bits are compared with the four MSBs of the boundary HIGH and LOW registers If the four MSBs of the conversion are outside the limit an interrupt will be generated if enabled If the conversion result is within the limits the Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 31 of 91 Philips Semiconductors UM1 01 1 2 3 4 3 5 3 6 3 7 P89LPC9102 9103 9107 User manual boundary limits will again be compared after all eight bits have been converted An interrupt will be generated if enabled if the result is outside the boundary limits The boundary limit may be disabled by clearing the boundary
127. t that the old clock source is left enabled for two clock cycles after the feed completes Otherwise the Watchdog may become disabled when the old clock source is disabled For example suppose PCLK WCLK 0 is the current clock source After WCLK is set to logic 1 the program should wait at least two PCLK cycles 4 CCLKs after the feed completes before going into Power down mode Otherwise the Watchdog could become disabled when CCLK turns off The Watchdog oscillator will never become selected as the clock source unless CCLK is turned on again first MOV WFEED1 0A5H 4 N MOV WFEED2 05AH watchdog oscillator m PRESCALER 8 BIT DOWN t4 roe pa H esinen T A A A i Paez J Pre pre J worn woror woon 002aaa980 WDCON A7H 1 Watchdog timer reset can also be caused by an invalid feed sequence or by writing to WDCON not immediately followed by a feed sequence Fig 35 Watchdog timer in Watchdog mode WDTE 1 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 73 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual MOV WFEED1 0A5H N MOV WFEED2 05AH watchdog oscillator eH PRESCALER Lo 8 BIT DOWN inierr nt PCLK i PRESCALER O COUNTER pee ee A A A f PRE2 PRE1 WDRUN TOE WDCLK Pree pre1 preo
128. ta is used to differentiate between the two slaves Slave 0 requires a 0 in bit 0 and it ignores bit 1 Slave 1 requires a 0 in bit 1 and bit 0 is ignored A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1 A unique address for slave 1 would be 1100 0001 since a 1 in bit O will exclude slave 0 Both slaves can be selected at the same time by an address which has bit 0 0 for slave 0 and bit 1 0 for slave 1 Thus both could be addressed with 1100 0000 In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0 Table 55 Slave 0 1 2 examples Example 1 Example 2 Example 3 Slave 0 SADDR 1100 0000 Slave 1 SADDR 11100000 Slave 2 SADDR 11000000 SADEN 1111 1001 SADEN 11111010 SADEN 11111100 Given 1100 Given 1110 0X0X Given 1110 00XX OXX0 In the above example the differentiation among the 3 slaves is in the lower 3 address bits Slave 0 requires that bit O 0 and it can be uniquely addressed by 1110 0110 Slave 1 requires that bit 1 0 and it can be uniquely addressed by 1110 and 0101 Slave 2 requires that bit 2 0 and its unique address is 1110 0011 To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100 since it is necessary to make bit 2 1 to exclude slave 2 The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN Zeros in this result are treated as don t cares In most cases 9397 750 13919
129. ter Control register TCON address 88h bit description Bit Symbol Description 5 TFO Timer 0 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the processor vectors to the interrupt routine or by software except in mode 6 where it is cleared in hardware TR1 Timer 1 Run control bit Set cleared by software to turn Timer Counter 1 on off TF1 Timer 1 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the interrupt is processed or by software except in mode 6 see above when it is cleared in hardware overflow peik TnC T 0 ats gt on cae ie TFn interrupt Tn pin TnC T 1 control ENTn 002aab055 1 Tn pin functions available on P89LPC9102 P89LPC9107 Fig 21 Timer counter 0 or 1 in Mode 0 13 bit counter eae TnC T 0 overflow 0 on eae E an TFn gt interrupt Tn pin TCT 1 control toggle ENTn 002aab056 1 Tn pin functions available on P89LPC9102 P89LPC9107 Fig 22 Timer counter 0 or 1 in mode 1 16 bit counter TnC T 0 flow PCLK TLn wi terrupt Tn pin lt Er o control _ amp bits en f erup n toggle TRn si w pin 8 bits ENTA 002aab057 1 Tn pin functions available on P89LPC9102 P89LPC9107 Fig 23 Timer counter 0 or 1 in Mode 2 8 bit auto reload 9397 750 13919 Koninklijke Phi
130. the result register which corresponds to Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 30 of 91 Philips Semiconductors UM1 01 1 2 9397 750 13919 3 2 7 3 3 3 3 1 3 3 2 3 3 3 3 3 4 P89LPC9102 9103 9107 User manual the selected input channel See Table 10 May be used with any of the start modes This mode is selected by clearing the BURST1 SCC1 and SCAN1 bits in the ADMODA register Conversion mode selection bits The A D uses three bits in ADMODA to select the conversion mode These mode bits are summarized in Table 13 below Combinations of the three bits other than the combinations shown are undefined Table 13 Conversion mode bits BURST1 SCC1 Scani ADC1 conversion BURSTO SCCO Scan0 ADCO conversion mode mode 0 0 single step 0 0 0 single step 1 fixed 0 0 1 fixed channel single channel single auto scan single auto scan single 0 1 0 fixed channel 0 1 0 fixed channel continuous continuous dual channel dual channel continuous continuous 1 0 0 auto scan 1 0 0 auto scan continuous continuous Trigger modes Timer triggered start An A D conversion is started by the overflow of Timer 0 Once a conversion has started additional Timer 0 triggers are ignored until the conversion has completed The Timer triggered start mode is available in all A D operating modes This mode is selected by the TMM1 bi
131. ther flag bits are cleared 5 BOF Brownout Detect Flag When Brownout Detect is activated this bit is set It will remain set until cleared by software by writing a logic 0 to the bit Note On a Power on reset both POF and this bit will be set while the other flag bits are cleared 6 7 reserved 7 1 Reset vector Following reset the P89LPC9102 9103 9107 will fetch instructions from either address 0000h or the Boot address The Boot address is formed by using the Boot Vector as the HIGH byte of the address and the LOW byte of the address 00h The Boot address will 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 46 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual be used if a UART break reset P89LPC9103 P89LPC9107 occurs or the non volatile Boot Status bit BOOTSTAT 0 1 or the device has been forced into ISP mode Otherwise instructions will be fetched from address 0000H 8 Timers 0 and 1 The P89LPC9102 9103 9107 has two general purpose counter timers which are upward compatible with the 80C51 Timer 0 and Timer 1 Both can be configured to operate either as timers or event counters see Table 36 An option to automatically toggle the Tx pin upon timer overflow has been added In the Timer function the timer is incremented every PCLK In the Counter function the register is i
132. ue is s1O ONPUOTIWAS sdijiud pansased s YGU Ily 700 A N 91u0149813 Sdiliyd OxfIPUIUOY L6 40 GL xx110000 4 After reset the value is 111001x1 i e PRE2 to PREO are all logic 1s WORUN 1 and WDCLK 1 WDTOF bit is logic 1 after watchdog timer reset and is logic 0 after power on reset Other resets will not affect WDTOF 5 On power on reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM register 6 The only reset source that affects these SFRs is power on reset jenuew J9Sf 2016 016 20169d 168d CLLOLINN jenuew Jesp soog Aseniqas LL LO Ady L6 40 OL 6L6EL OSZ L666 pansased S YG IY 700 A N SO U0N98 9 Sdiliyd OxfIPUIUOY Table 5 P89LPC9103 special function registers indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary Bit address E7 E6 E5 E4 E3 E2 E1 E0 ACC Accumulator EOH 00 00000000 ADCON1 A D control register 1 97H ENBI1 ENADCI1 TMM1 ADCI1 ENADC1 ADCS11 ADCS10 00 00000000 ADINS A D input select A3H ADI13 AD12 ADI11 AD10 00 00000000 ADMODA A D mode register A COH BNDI1 BURST1 SCC1 SCAN1 00 00000000 ADMODB A D mode register B A1H CLK2 CLK1 CLKO ENDAC1 BSA1 00 000x0000 AD1BH A D_1 boundary high register C4H FF 1
133. ures 20545 75 continued gt gt Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 90 of 91 Philips Semiconductors UM10112 14 1 Software reset 0 20 00 cee eee 14 2 Dual Data Pointers 15 Flash memory 200 e cece eee eee eee 15 1 F atures ede tenet ee ae ba dato 15 2 Flash programming and erase 15 3 Using Flash as data storage IAP Lite 15 4 In circuit programming ICP 15 5 Power on reset code execution 15 6 Hardware activation of Boot Vector address 15 7 Flash write enable 15 8 Configuration byte protection 15 9 IAP Lite error status 15 10 User configuration bytes 15 11 User security bytes 15 12 Boot Vector register 0 15 13 Boot status register 16 Instruction Set 0 2c e cece eee eee 17 Disclaimers 000 c eee e rece e ee eee PHILIPS 81 P89LPC9102 9103 9107 User manual Koninklijke Philips Electronics N V 2004 All rights are reserved Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner The information presented in this document does not form part of any quotation or contract is believed to be accurate and reliable and may be changed without notice
134. use the device to exit idle mode when the conversion is completed if the A D interrupt is enabled In Power down mode or Total Power down mode the A D does not function If the A D is enabled it will consume power Power can be reduced by disabling the A D Table 14 A D Control register 1 ADCON1 address 97h bit allocation Bit 6 5 4 3 2 1 0 Symbol ENBI1 ENADCI1 TMM1 ADCI1 ENADC1 ADCS11 ADCS10 Reset 0 0 0 0 0 0 0 Table 15 A D Control register 1 ADCON1 address 97h bit description Bit Symbol Description 0 ADCS10 A D start mode bits 11 10 1 ADCS11 00 Timer Trigger Mode when TMM1 1 Conversions starts on overflow of Timer 0 Stop mode when TMM1 0 no start occurs 01 Immediate Start Mode Conversions starts immediately 10 Reserved 2 ENADC1 Enable A D channel 1 When set 1 enables ADC1 Must also be set for D A operation of this channel 9397 750 13919 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 32 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual Table 15 A D Control register 1 ADCON1 address 97h bit description Bit Symbol Description 3 ADCI1 A D Conversion complete Interrupt 1 Set when any conversion or set of multiple conversions has completed Cleared by software reserved 5 TMM1 Timer Trigger Mode 1 Selects either stop mode TMM1 0 or timer trigger mode
135. uts depends upon the port configuration selected Each of the configurable port pins are programmed independently Refer to Section 5 1 Port configurations for details P1 5 is input only All pins have Schmitt triggered inputs Port 1 also provides various special functions as described below P1 0 TXD 5 1 0 P1 0 Port 1 bit 0 O TXD Serial port transmitter data P1 1 RXD 6 1 0 P1 1 Port 1 bit 1 l RXD Serial port receiver data P1 5 RST 2 l P1 5 Port 1 bit 5 input only l RST External Reset input during Power on or if selected via UCFG1 When functioning as a reset input a LOW on this pin resets the microcontroller causing I O ports and peripherals to take on their default states and the processor begins execution at address 0 Also used during a power on sequence to force In System Programming mode When using an oscillator frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at power up until Vpp has reached its specified level When system power is removed Vpp Will fall below the minimum specified operating voltage When using an oscillator frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when Vpp falls below the minimum specified operating voltage Vss l Ground 0 V reference Vpop l Power supply This is the power supply voltage for normal operation as well as
136. watchdog timer RTC keyboard comparator 1 and the A D converter The P89LPC9103 supports nine interrupt sources timers 0 and 1 serial port Tx serial port Rx combined serial port Rx Tx brownout detect watchdog timer RTC keyboard comparator and the A D converter Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IENO or IEN1 The IENO register also contains a global disable bit EA which disables all interrupts Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IPO IPOH IP1 and IP1H An interrupt service routine in progress can be interrupted by a higher priority interrupt but not by another interrupt of the same or lower priority The highest priority interrupt service cannot be interrupted by any other interrupt source If two requests of different priority levels are pending at the start of an instruction the request of higher priority level is serviced Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 11 February 2005 34 of 91 Philips Semiconductors UM1 01 1 2 P89LPC9102 9103 9107 User manual If requests of the same priority level are pending at the start of an instruction an internal polling sequence determines which request is serviced This is called the arbitration ranking Note that the arbitr
137. y 2005 84 of 91 Philips Semiconductors UM10112 P89LPC9102 9103 9107 User manual 15 13 Boot status register Table 82 Boot Status BOOTSTAT bit allocation Bit 7 6 5 4 3 2 1 0 Symbol DDCP CWP AWP BSB Factory default value 0 0 0 0 0 0 0 1 Table 83 Boot Status BOOTSTAT bit description Bit Symbol 0 BSB Description Boot Status Bit If programmed to 1 the P89LPC9102 9103 9107 will always start execution at an address comprised of OOH in the lower eight bits and BOOTVEC as the upper bits after a reset See Section 7 1 Reset vector on page 46 reserved 5 AWP Activate Write Protection bit When this bit is cleared the internal Write Enable flag is forced to the set state thus writes to the flash memory are always enabled When this bit is set the Write Enable internal flag can be set or cleared using the Set Write Enable SWE or Clear Write Enable CWE commands to FMCON 6 CWP Configuration Write Protect bit Protects inadvertent writes to the user programmable configuration bytes UCFG1 BOOTVEC and BOOTSTAT If programmed to 1 the writes to these registers are disabled If programmed to 0 writes to these registers are enabled This bit is set by programming the BOOTSTAT register This bit is cleared by writing the Clear Configuration Protection CCP command to FMCON followed by writing 96H to FMDATA 7 DDCP Disable Clear Configuration P
138. y eliminating the need for the software to examine every serial address which passes by the serial port This feature is enabled by setting the SM2 bit in SCON In the 9 bit UART modes mode 2 and mode 3 the Receive Interrupt flag RI will be automatically set when the received byte contains either the Given address or the Broadcast address The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses All of the slaves may be contacted by using the Broadcast address Two special Function Registers are used to define the slave s address SADDR and the address mask SADEN SADEN is used to define which bits in the SADDR are to be used and which bits are don t care The SADEN mask can be logically ANDed with the SADDR to create the Given address which the master will use for addressing each of the slaves Use of the Given address allows multiple slaves to be recognized while excluding others The following examples will help to show the versatility of this scheme Table 54 Slave 0 1 examples Example 1 Example 2 Slave 0 SADDR 11000000 Slave 1 SADDR 11000000 SADEN 11111101 SADEN 11111110 Given 110000X0 Given 1100 000X In the above example SADDR is the same and the SADEN da

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