Quartus II Introduction Using Schematic Designs
Contents
1. Type Message i Info Writing out detailed assembly data for power analysis i Info Assembler is generating device programming files i Info Quartus II Assembler was successful O errors O warnings A Warning Skipped module PowerPlay Power Analyzer due to the assignment FLOW ENABLE POWER ANALYZER i Info Quartus II Full Compilation was successful O errors 10 warnings Locate mm ______________________E 22 100 00 00 20 Figure 20 Display after a successful compilation 6 1 Errors Quartus II software displays messages produced during compilation in the Messages window If the block diagram design file is correct one of the messages will state that the compilation was successful and that there are no errors If the Compiler does not report zero errors then there is at least one mistake in the schematic entry In this case a message corresponding to each error found will be displayed in the Messages window Double clicking on an error message will highlight the offending part of the circuit in the Graphic Editor window Similarly the Compiler may display some warning messages Their details can be explored in the same way as in the case of error messages The user can obtain more information about a specific error or warning message by selecting the message and pressing the F1 function key To see the effect of an error open the file light bdf Remove the wire connecting the output of the top AND gate to the OR gate To d2. a x Entity by Cyclone II gt light lt EP2C35F672C6 amp Hierarchy Tasks Flow Compilation Files dF Design Units A x Customize Task x o gt x H h A Compile Design Analysis amp Synthesis E Fitter Place amp Route Assembler Generate program v gt Type Message fal light bd Table of Contents vl x9 2 deh EA EB Flow Settings E Flow Non Default Global Settings E5 Flow Elapsed Time EB Flow OS Summary Flow Log E Analysis amp Synthesis Compilation Report 8 Flow Summary Flow Status Quartus IT version Revision Name Top level Entity Name Family Device Timing Models Total logic elements Total combinational Functions Dedicated logic registers Total registers Total pins Total virtual pins Total memory bits Embedded Multiplier 9 bit elements Total PLLs Z2 Vve Drv seh amp Flow Failed Fri May 06 10 07 26 20 11 0 Build 157 04 27 2011 5J Full ve light light Cyclone II EP2C35F672C6 Final N 4 until Partition Merge NjA until Partition Merge NjA until Partition Merge N 4 until Partition Merge NjA until Partition Merge NjA until Partition Merge NjA until Partition Merge N 4 until Partition Merge NjA until Partition Merge A Warning Primitive AND2 of instance inst not used Warning Primitive NOT of instance inst4 not used Error Node ins
3. 22 U 00 00 00 Figure 19 The completed schematic diagram 6 Compiling the Designed Circuit The entered schematic diagram file light bdf is processed by several Quartus II tools that analyze the file synthesize the circuit and generate an implementation of it for the target chip These tools are controlled by the application program called the Compiler Run the Compiler by selecting Processing gt Start Compilation or by clicking on the toolbar icon that looks like a purple triangle Your project must be saved before compiling As the compilation moves through various stages its progress is reported in a window on the left side of the Quartus II display Successful or unsuccessful compilation is indicated in a pop up box Acknowledge it by clicking OK which leads to the Quartus II display in Figure 20 In the message window at the bottom of the figure various messages are displayed In case of errors there will be appropriate messages given When the compilation is finished a compilation report is produced A tab showing this report is opened automat ically as seen in Figure 20 The tab can be closed in the normal way and it can be opened at any time either by selecting Processing gt Compilation Report or by clicking on the icon The report includes a number of sections listed on the left side Figure 20 displays the Compiler Flow Summary section which indicates that only one logic element and three pins are n
4. gt Pointer 24 25 ns Interval 24 23 ns Stark fs End 160 0 ns 320 0 ns 450 0 ns 640 0 ns 00 0 ns 960 0 ns Value at 1 1 1 1 1 1 O ps Oo 00 00 00 Figure 31 The Waveform Editor window 24 Altera Corporation University Program May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS Simulation Waveform Editor light vwf File Edit view Help amp RJA fr A BR XE Xe es BR Master Time Bar gt Pointer 196 71 ns Interval 196 71 ns Stare fs End 170 0 ns 160 0 ns 200 0 ns I I Value at Oo 00 00 00 Figure 32 The augmented Waveform Editor window 6 Next we want to include the input and output nodes of the circuit to be simulated Click Edit gt Insert gt Insert Node or Bus to open the window in Figure 33 It is possible to type the name of a signal pin into the Name box or use the Node Finder to search your project for the signals Click on the button labeled Node Finder to open the window in Figure 34 The Node Finder utility has a filter used to indicate what type of nodes are to be found Since we are interested in input and output pins set the filter to Pins all Click the List button to find the input and output nodes as indicated on the left side of the figure Insert Mode or Bus Name Type INPUT Cancel Value type 9 Level g Node Finder Radix Signed Decimal Bus width Start index Display gray code count as binary coun
5. _ Critical Warning A Error 2 J Flag 11 00 00 04 it Figure 22 Error messages Quartus Il D MyWork UniversityProgram introtutorial light light Sle File Edit View Project Assignments Processing Tools Window Help DHgate ome Arr gyeny SOOO A eo Project Navigator E x a Woebt pa H amp B 2 ao d Cyclone Il EP2C2 T iLL E gt Fis Tasks oO ox Task 4s E i Compile E Type Message A amp A Warning Primitive AND2 of instance lien not wed pos r A a i PREN pe r Dii iis Ps System Extra Info Info t6 Warning t2 _Critical warning _Error 3 J N Suppressed Flag alna 7 l1 0000 04 Figure 23 Identifying the location of the error 7 Pin Assignment During the compilation above the Quartus II Compiler was free to choose any pins on the selected FPGA to serve as inputs and outputs However the DE series board has hardwired connections between the FPGA pins and the other components on the board We will use two toggle switches labeled SWo and SW to provide the external inputs x and x2 to our example circuit These switches are connected to the FPGA pins listed in Table 2 We will connect the output f to the green light emitting diode labeled LEDGp Its FPGA pin assignment can also be found in Table Altera Corporation University Program 19 May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS DEO DE2 70_ _DE2 115 PIN_J6 PIN_L22 PIN_N25 PIN_AA23 PI
6. hold the mouse button and drag the mouse to the right until the drawn line reaches the pinstub on the top input of the AND gate Release the mouse button when you see a box appear which leaves the line connecting the two pinstubs Next draw a wire from the input pinstub of the leftmost NOT gate to touch the wire that was drawn above it Note that a dot will appear indicating a connection between the two wires Use the same procedure to draw the remaining wires in the circuit If a mistake is made a wire can be selected by clicking on it and removed by pressing the Delete key on the keyboard Upon completing the diagram click on the icon to activate the Selection Tool Now changes in the appearance of the diagram can be made by selecting a particular symbol or wire and either moving it to a different location or deleting it The final diagram is shown in Figure 19 save it Altera Corporation University Program 15 May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS Quartus II D MyWork UniversityProgram introtutorial light light File Edit View Project Assignments Processing Tools window Help OSHS teeooie MY VSYS OK He Project Navigator Gx i light bdF Ej L Ep Entity BH amp B no Ay Cyclone I EP2C35Fe light Ay Hierarchy Fil p Tasks a x ay Task bl Ge compile E sna E B Fitte E WF Assay System J4 Processin Extra Info Info A Warning N Critical Warning A Error JN Suppressed f Flag j 243
7. Designed Circuit Before implementing the designed circuit in the FPGA chip on the DE series board it is prudent to simulate it to ascertain its correctness The QSim tools can be used to simulate the behavior of a designed circuit Before the circuit can be simulated it is necessary to create the desired waveforms called test vectors to represent the input signals It is also necessary to specify which outputs as well as possible internal points in the circuit the designer wishes to observe The simulator applies the test vectors to a model of the implemented circuit and determines the expected response We will use the Quartus II Waveform Editor to draw the test vectors as follows Edit for IS1500 You cannot start QSim from the Start Menu See the Laboratory Exercise Instructions lab PM 1 Seleet Ste A Pregranis gt Atera gt Urversty Pregrart gt sintatern _tee QS to open the QSim tools which will display the window in Figure 30 2 Select File gt Open Project to display a popup window in which you can browse your directories and choose a project file gpf file Select the project you wish to simulate and clickOK 3 Generate the node finder files by selecting Processing gt Generate Node Finder Files 4 From QSim open the Waveform Editor window by selecting File gt New Simulation Input File Altera Corporation University Program 23 May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS get started open an existin
8. Directory Ds My work UniversityProgram introtutorial does not exist Do you want bo create it Figure 5 Quartus II software can create a new directory for the project 6 Altera Corporation University Program May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS New Project Wizard Add Files page 2 of 5 Select the design files you want to include in the project Click Add All to add all design files in the project directory to the project Note you can always add design files to the project later File name m File Name Type Library Design Entry Synthesis Tool HDL Version Add all Remove U p Down Properties Specify the path names of any non default libraries Figure 6 The wizard can include user specified design files 3 The wizard makes it easy to specify which existing files Gf any should be included in the project Assuming that we do not have any existing files click Next which leads to the window in Figure 7 New Project Wizard Family amp Device Settings page 3 of 5 Select the Family and device you want to target for compilation Device Family Show in Available devices list Family Cyclone II i Package Any Devices all i Pin count lany Target device Speed grade Any _ Auto device selected by the Fitter Show advanced devices Specific device selected in Available devices list HardCopy compatible only Other nja Available de
9. device specifications before relying on any published information and before placing orders for products or services This document is being provided on an as is basis and as an accommodation and therefore all warranties repre sentations or guarantees of any kind whether express implied or statutory including without limitation warranties of merchantability non infringement or fitness for a particular purpose are specifically disclaimed Altera Corporation University Program 37 May 2011
10. information for that project in a single directory folder in the file system To begin a new logic circuit design the first step 1s to create a directory to hold its files To hold the design files for this tutorial we will use a directory introtutorial The running example for this tutorial is a simple circuit for two way light control Start the Quartus II software You should see a display similar to the one in Figure 2 This display consists of several windows that provide access to all the features of Quartus II software which the user selects with the computer mouse Most of the commands provided by Quartus II software can be accessed by using a set of menus that are located below the title bar For example in Figure 2 clicking the left mouse button on the menu named File opens the menu shown in Figure 3 Clicking the left mouse button on the entry Exit exits from Quartus II software In general whenever the mouse is used to select something the eft button is used Hence we will not normally specify which button to press In the few cases when it is necessary to use the right mouse button it will be specified explicitly Altera Corporation University Program 3 May 2011 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS Quartus Il File Edit View Project Assignments Processing Tools Window Help amp Dnd 6 e o Dy cv 7 SVS D gt YOO Compilation Hierarchy Task B gt Compile Design E P Analysis amp Sy
11. the images may be slightly different Contents Typical CAD Flow Getting Started Starting a New Project Schematic Design Entry Compiling the Design Pin Assignment Simulating the Designed Circuit Programming and Configuring the FPGA Device Testing the Designed Circuit Altera Corporation University Program 1 May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS 2 Background Computer Aided Design CAD software makes it easy to implement a desired logic circuit by using a programmable logic device such as a field programmable gate array FPGA chip A typical FPGA CAD flow is illustrated in Figure 1 Design Entry Functional Simulation Timing requirements met Yes Programming and Configuration Figure 1 Typical CAD flow The CAD flow involves the following steps e Design Entry the desired circuit is specified either by means of a schematic diagram or by using a hardware description language such as Verilog or VHDL e Synthesis the entered design is synthesized into a circuit that consists of the logic elements LEs provided in the FPGA chip e Functional Simulation the synthesized circuit is tested to verify its functional correctness this simulation does not take into account any timing issues 2 Altera Corporation University Program May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS Fitting the CAD Fitter tool determines the placement of the LEs def
12. 1 1 Functional Simulation To perform the functional simulation return to the QSim Window and select Assign gt Simulation Settings to open the Simulation Settings window in Figure 37 Click the Browse button and select the light vwf file you created Altera Corporation University Program 27 May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS Choose Functional as the simulation type and click OK Before running the functional simulation it is necessary to create the required netlist which is done by selecting Processing gt Generate Functional Simulation Netlist A simulation run is started by Processing gt Start Simulation or by using the icon E At the end of the simulation Quartus II software indicates its successful completion and displays a Simulation Report illustrated in Figure 38 If your report window does not show the entire simulation time range click on the report window to select it and choose View gt Fit in Window Observe that the output f is as specified in the truth table of Figure 11 Simulation Settings Simulation Settings Specify WWF File Dany Work UniversityPragrampintrotuboriallight wF Browse Simulation Type f Functional Timing Cancel Figure 37 Specifying the simulation type Simulation Waveform Editor light sim vwf Read Only File Edit View Help RJA A BE XE Xe i Master Time Bar gt Pointer 53 62 ns Interval 53 62 ns Stark OoOo
13. End OoOo 120 0 ns 160 0 ns 200 0 ns I I Oo 00 00 00 Figure 38 The result of functional simulation 8 1 2 Timing Simulation Having ascertained that the designed circuit is functionally correct we should now perform the timing simulation to see how it will behave when it is actually implemented in the chosen FPGA device Select Assign gt Simulation Settings to get to the window in Figure 37 choose Timing as the simulation type and click OK Run the simulator which should produce the waveforms in Figure 39 Observe that there is a delay of about 6 ns in producing a change in the signal f from the time when the input signals x and x2 change their values This delay is due to the propagation delays in the logic element and the wires in the FPGA device 28 Altera Corporation University Program May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS Simulation Waveform Editor light sim vwi Read Only File Edit view Help amp 1 IHM WE Vy 00 e E Or h BY MS Xe lel E Master Time Bar gt Pointer 65 57 ns Interval 65 57 ns Stark End fs 120 0 ns 160 0 ns 200 0 ns I I Value at O ps BO BO BO 00 00 00 Figure 39 The result of timing simulation 9 Programming and Configuring the FPGA Device The FPGA device must be programmed and configured to implement the designed circuit The required config uration file is generated by the Quartus II Compiler s Assembler m
14. N_AB28 PIN_H5 PIN_L21 PIN_N26 PIN_AB26 PIN_AC28 LEDGo PIN_J1 PIN_U22 PIN_AE22 PIN_W27 PIN_E21 Table 2 DE Series Pin Assignments Assignment Editor D MyWork UniversityProgram introtutorial light light Sle File Edit View Tools Window Help To Assignment Mame Enabled Entity Comment lt NeW gt gt ZANEN This cell shows the status of the assignment in the current row Oo 00 00 00 Figure 24 The Assignment Editor window Pin assignments are made by using the Assignment Editor Select Assignments gt Assignment Editor to reach the window in Figure 24 shown here as a detached window In the Category drop down menu select All Click on the lt lt new gt gt button located near the top left corner to make a new item appear in the table Double click the box under the column labeled To so that the Node Finder button amp appears Click on the button not the drop down arrow to reach the window in Figure 25 In the Filter drop down menu select Pins all Then click the List button to display the input and output pins to be assigned f xl and x2 Click on x1 as the first pin to be assigned and click the gt button this will enter x1 in the Selected Nodes box Click OK x1 will now appear in the box under the column labeled To Alternatively the node name can be entered directly by double clicking the box under the To column and typing in the node name Follow this by double clicking on the box to
15. at holds the file in the File Name box and press OK Of course you can also browse to find the desired file 22 Altera Corporation University Program May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS ag Import Assignments Specify the source and categories of assignments to import roname J iJ Cotes Copy existing assignments into light qs bak before importing Advanced Figure 29 Importing the pin assignment For convenience when using large designs all relevant pin assignments for the DE series board are given in individ ual files For example the DE2 pin assignments can be found in the DE2_pin_assignments gqsf file in the directory tutorials design_files which is included on the CD ROM that accompanies the DE series board and can also be found on Altera s DE series web pages This file uses the names found in the DE2 User Manual If we wanted to make the pin assignments for our example circuit by importing this file then we would have to use the same names in our Block Diagram Schematic design file namely SW 0 SW I and LEDG O for x1 x2 and f respectively Since these signals are specified in the DE2_pin_assignments qsf file as elements of vectors SW and LEDG we must refer to them in the same way in our design file For example in the DE2_pin_assignments qsf file the 18 toggle switches are called SW 17 to SW O In a design file they can also be referred to as a vector SW 17 0 8 Simulating the
16. ditor A simple file format that can be used for this purpose is the Quartus II Settings File QSF format The format for the file for our simple project on a DE2 board is set_location_assignment PIN_N25 to x1 set_location_assignment PIN_N26 to x2 set_location_assignment PIN_AE22 to f By adding lines to the file any number of pin assignments can be created Such gqsf files can be imported into any design project If you created a pin assignment for a particular project you can export it for use in a different project To see how this is done open again the Assignment Editor to reach the window in Figure 27 Select Assignments gt Export Assignment which leads to the window in Figure 28 Here the file light qsf is available for export Click on OK If you now look in the directory you will see that the file light gsf has been created Export Assignments 4ssignments to export File name De IMyWork UniversityProgramsintrotutorial fatom_netlists light gsf lenad Export assignments hierarchy path Export back annotated routing Save intermediate synthesis results Save a node level netlist of the entire design into a persistent source File Figure 28 Exporting the pin assignment You can import a pin assignment by choosing Assignments gt Import Assignments This opens the dialogue in Figure 29 to select the file to import Type the name of the file including the gsf extension and the full path to the directory th
17. eeded to implement this tiny circuit on the selected FPGA chip 16 Altera Corporation University Program May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS Quartus II D MyWork UniversityProgram introtutorial light light File Edit View Project Assignments Processing Tools Window Help ODeld 6 4 Se ie IY IGED SO Project Navigator of x tal light bo F Table of Contents ES Flow Summary ES Flow Settings ES Flow Non Default Global Settings ES Flow Elapsed Time E Flow OS Summary Flow Log H E Analysis amp Synthesis Ge C Fitter H J Assembler H E TimeQuest Timing Analyzer Entity Ay Cyclone Il EP2CS5FA72C6 ae light d Design Units dy Hierarchy Files Tasks a x Compilation Report x oe Flow Summary Flow Status Quartus IT Version Revision Name Top level Entity Marne Family Device Timing Models Tokal logic elements Total combinational Functions Dedicated logic registers Total registers Total pins Total virtual pins Total memory bits Embedded Multiplier 39 bit elements Total PLLs Successful Thu May 05 17 08 40 21 11 0 Build 157 04 27 2011 5 Full ve light light Cyclone II EP2CS5F672C6 Final 1 33 216 lt 1 1 33 2160 lt 1 O 33 2160 3 3 475 01 o O 483 840 0 of 7oCo of4fo Flow Compilation ka Compile Design H e Analysis amp Synthesis cH We Fitter Place amp Route HM Assembler Generate program w jili
18. g Quartus II project by selecting File gt Open Project produce an input waveform file select File gt Hew Simulation Input the displayed window create the desired input waveforms Give it a suitable name and sare it Specify a setting for simulation select Assign gt Simulation Settings the pop up dialog box choose a specific VWF file and specify either functional or timing simulation Run the simulation by selecting Processing gt Start Simulation Warning If you recompile your Quartus II project with new changes the Node Finder files may be invalid Ta prevent invalid nodes from showing up in the Node Finder tegenerate the Node Finder tiles HY Selecting Processing gt Generate Node Pinker Files amp iterE Fou recompiled your project El version 11 0 Build 157 04 27 2011 5 Full version Figure 30 The QSim Window 5 The Waveform Editor window is depicted in Figure 31 Save the file under the name light vwf note that this changes the name in the displayed window Set the desired simulation to run from 0 to 200 ns by selecting Edit gt Set End Time and entering 200 ns in the dialog box that pops up Selecting View gt Fit in Window displays the entire simulation range of 0 to 200 ns in the window as shown in Figure 32 You may wish to resize the window to its maximum size Simulation Waveform Editor Waveform wwf File Edit View Help RA ee ch BY XB YG il Be Master Time Bar
19. i Quartus II Introduction Using Schematic Designs 1 Introduction This tutorial presents an introduction to the Quartus II CAD system It gives a general overview of a typical CAD flow for designing circuits that are implemented by using FPGA devices and shows how this flow is realized in the Quartus II software The design process is illustrated by giving step by step instructions for using the Quartus H software to implement a very simple circuit in an Altera FPGA device The Quartus II system includes full support for all of the popular methods of entering a description of the desired circuit into a CAD system This tutorial makes use of the schematic design entry method in which the user draws a graphical diagram of the circuit Two other versions of this tutorial are also available which use the Verilog and VHDL hardware description languages respectively The last step in the design process involves configuring the designed circuit in an actual FPGA device To show how this is done it is assumed that the user has access to the Altera DE series Development and Education board connected to a computer that has Quartus II software installed A reader who does not have access to the DE series board will still find the tutorial useful to learn how the FPGA programming and configuration task is performed The screen captures in the tutorial were obtained using the Quartus II version 11 0 if other versions of the software are used some of
20. in Figure 42 An LED on the board will light up when the configuration data has been downloaded successfully If you see an error reported by Quartus II software indicating that programming failed then check to ensure that the board is properly powered on Edit for IS1500 at KTH pages 32 36 deleted Altera Corporation University Program 31 May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS Copyright 1991 2011 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending applications mask work rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of
21. ined in the netlist into the LEs in an actual FPGA chip it also chooses routing wires in the chip to make the required connections between specific LEs e Timing Analysis propagation delays along the various paths in the fitted circuit are analyzed to provide an indication of the expected performance of the circuit e Timing Simulation the fitted circuit is tested to verify both its functional correctness and timing e Programming and Configuration the designed circuit is implemented in a physical FPGA chip by pro gramming the configuration switches that configure the LEs and establish the required wiring connections This tutorial introduces the basic features of the Quartus II software It shows how the software can be used to design and implement a circuit specified by means of a schematic diagram It makes use of the graphical user interface to invoke the Quartus I commands Doing this tutorial the reader will learn about e Creating a project e Entering a schematic diagram e Synthesizing a circuit from the schematic diagram e Fitting a synthesized circuit into an Altera FPGA e Assigning the circuit inputs and outputs to specific pins on the FPGA e Simulating the designed circuit e Programming and configuring the FPGA chip on Altera s DE series board 3 Getting Started Each logic circuit or subcircuit being designed with Quartus II software is called a project The software works on one project at a time and keeps all
22. is listed in the window in Figure 40 If the file is not already listed then click Add File and select it This is a binary file produced by the Compiler s Assembler module which contains the data needed to configure the FPGA device The extension sof stands for SRAM Object File Click on the Program Configure check box as shown in Figure 42 30 Altera Corporation University Program May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS gt Hardware Setup Hardware Settings JTAG Settings Select a programming hardware setup to use when programming devices This programming hardware setup applies only to the current programmer window Currently selected hardware LISB Blaster USB 0 v Available hardware items Hardware Add Hardware USB Blaster Remove Hardware Figure 41 The Hardware Setup window lt gt Programmer D MyWork UniversityProgram introtutorial light light light cdf File Edit View Processing Tools Window Help 2 lt Hardware setup US6 Blaster USB 0 Mode JTS kr Progress Po L Enable real time ISF to allow background programming For Max I and MAX Y devices Device Checksum Usercode Program verify Blank Examine Wi Start Configure Check mi st O02F84BB FFFFFFFF op mi Auto Detect Delete Gab Add File S change File fet Save File ce Add Device ei Down Figure 42 The updated Programmer window Now press Start in the window
23. is usually the same as the top level design entity that will be included in the project Choose light as the name for both the project and the top level entity as shown in Figure 4 Press Next Since we have not yet created the directory introtutorial Quartus II software displays the pop up box in Figure 5 asking if it should create the desired directory Click Yes which leads to the window in Figure 6 Note for IS1500 The New Project Wizard will initially suggest your home folder as a working directory At the end of the suggested path add the following gqp introtutorial We suggest qp as the name of the folder that will contain all your Quartus Projects The complete path should now be something like home student gp introtutorial If you use a computer managed by your school home student will be replaced by something completely different Altera Corporation University Program 5 May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS New Project Wizard Directory Name Top Level Entity page 1 of 5 Wiha is the working directory For this project Des WworkUniversityProgramlintrotutorial laad What is the name of this project light LJ What is the name of the top level design entity For this project This name is case sensitive and must exactly match the entity name in the design File light LJ Lise Existing Project Settings Figure 4 Creation of a new project F Quartus II T
24. l automatically to synthesize the current design Simulation lt None gt lt None gt Run gate level simulation automatically after compilation Timing Analysis lt None gt lt None gt Run this tool automatically after compilation Formal Yerification lt None gt Board Level Timing lt None gt Symbol lt None gt Signal Integrity lt None gt Boundary Scan lt None gt __ Figure 8 Other EDA tools can be specified 5 The user can specify any third party tools that should be used A commonly used term for CAD software for electronic circuits is EDA tools where the acronym stands for Electronic Design Automation This term is used in Quartus II messages that refer to third party tools which are the tools developed and marketed by companies other than Altera Since we will rely solely on Quartus II tools we will not choose any other tools Press Next 6 A summary of the chosen settings appears in the screen shown in Figure 9 Press Finish which returns to the Altera Corporation University Program May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS main Quartus II window but with light specified as the new project in the display title bar as indicated in Figure 10 Mew Project Wizard Summary page 5 of 5 When you click Finish the project will be created with the Following settings Project directory DAMy Work UniversityProgram introtutorial Project na
25. me light Top level design entity light Number of Files added oO Number of user libraries added 0 Device assignments Family name Cyclone II Device EP2C35F6 2C6 EDA tools Design entry synthesis lt None gt lt None gt Simulation lt None gt lt None gt Timing analysis lt None gt lt None gt Operating conditions Core voltage Junction temperature range Figure 9 Summary of project settings Altera Corporation University Program 9 May 2011 QUARTUS IT INTRODUCTION USING SCHEMATIC DESIGNS Quartus II D MyWork UniversityProgram introtutorial light light SEE File Edit view Project Assignments Processing Tools Window Help amp T DUALA o Ey Ky See o gt 7 51D Project Navigator Entity amp Cyclone II EP2C35F672C6 gt E Files dg Design Units QUARTUS AERA a B P Compile Design E e Analysis amp Synthesis dih 3 E Fitter Place amp Route g View Quartus II T Information E Assembler Generate programming files a wk Testa Am ol ate a rin i 5 Documentation Type Message System Ji Processing _Extra Info_ _Info_ _Warning_ _Critical warning _ _Error_ _Suppressed_ _Flag_ Message t Location Locate 0 00 00 00 Messages Figure 10 The Quartus II display for a created project 5 Design Entry Using the Graphic Editor As a design e
26. mplement as Clock Enable Implement as Output of Logic Cell Input Delay From Gual Purpose Clock Pin to Fan Qut Destinations 4ccepts wildcards groups Input Delay From Pin to Input Register Accepts wildcards groups Input Delay From Pin to Internal Cells 4ccepts wildcards groups E Iteration limit For constant Verilog loops Iteration limit For non constant Yerilog loops Keep synchronous clearipreset behavior For DOIG INPUT when unmap DO weysivwyg primitives Location 4ccepts wildcards groups k EAE Figure 26 The available assignment names for a DE series board Assignment Editor D MyWork UniversityProgram introtutorial light light FB Fie Edit wiew Tools Window Help Assignment Mame Value Enabled Entity Comment Location PIN_N25 Ves Location PIN_N26 Ves Location PIN SE22 Yes This cell shows the status of the assignment in the current row 0 o00000 Figure 27 The complete assignment Altera Corporation University Program 21 May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS The DE series board has fixed pin assignments Having finished one design the user will want to use the same pin assignment for subsequent designs Going through the procedure described above becomes tedious if there are many pins used in the design A useful Quartus II feature allows the user to both export and import the pin assignments from a special file format rather than creating them manually using the Assignment E
27. n Files AHEL File Block Diagram Schematic File EDIF File Osys System File State Machine File SystemVerilog HDL File Tel Script File HEL File erilog HDL File Memory Files Hexadecimal Intel Format File Memory Initialization File Verification Debugging Files In Systerm Sources and Probes File Logic Analyzer Interface File SignalTap IT Logic Analyzer File Other Files 4HDL Include File Block Symbol File Chain Description File Synopsys Design Constraints File Text File Figure 12 Choose to prepare a block diagram Save As Save in EO introtutorial ka hy Recent Documents Desktop My Computer hy Network Places db File name Save as type ligh Block Diagram Schematic File bdt I Add file to current project Figure 13 Name the file Cancel 1 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS Quartus II D MyWork UniversityProgram introtutorial light light File Edit View Project Assignments Processing Tools window Help Dea Ss BB ome IY LORS Tr SD Project Navigator ox Pi light bd F E Entity Ay Cyclone I EP2C35Fe light Ay Hierarchy Fi Tasks a x ty Task Gi compile E sna E B Fitte E e Asse System J4 Processin Extra Info Info A Warning N Critical Warning JN Error JN Suppressed f Flag j 159 7 Oo 00 00 00 Figure 14 Graphic Editor window 5 1 Importing Logic Gate Symbols The Graphic Editor provides a number
28. noii Jayvee Tr Oe Project Navigator ax i light bdf E ER Entity oH amp jB no Ay Cyclone I EP2C35Fe light dy Hierarchy Fis P 7 Task 4 Ge Compile E Ana E B Fitte E e Ass L System Processin Extra Info Info y Warning IN Critical Warning fN Error Jf Suppressed f Flag j 529 11 0 00 00 00 Figure 17 Import the input and output pins Assign names to the input and output symbols as follows Make sure nothing is selected by clicking on an empty spot in the Graphic Editor window Point to the top input symbol and double click the mouse The dialog box in Figure 18 will appear Type the pin name x1 and click OK Similarly assign the name x2 to the other input and f to the output Alternatively it 1s possible to change the name of an element by double clicking on the name and typing a new one directly 14 Altera Corporation University Program May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS m Pin Properties General Format To create multiple pins enter a name in AHOL bus notation For example name 3 0 or enter a comma seperated list of names Pn name s Default value WCC Figure 18 Naming of a pin 5 3 Connecting Nodes with Wires The symbols in the diagram have to be connected by drawing lines wires Click on the icon 1 in the toolbar to activate the Orthogonal Node Tool Position the mouse pointer over the right edge of the x1 input pin Click and
29. nthesis dia ET E Fitter Place amp Route g Guatusa ll E Assembler Generate programming files a information no e ee a oin pe iy E j i F Documentation Type Message Message BS Location Locate 0 00 00 00 Figure 2 The main Quartus II display Edit View Project Assignments Pr Chrl H a Open Chrl a Close Chrl F4 New Project Wizard Open Project Ctrl J Save Project Close Project fl Save Chrl 5 Save 45 Gil Save al Ctrl 5hift 5 File Properties Create f Update Export Convert Programming Files R Page Setup ch Print Preview amp Print Ctrl F Recent Files Recent Projects Exit Alk F4 Figure 3 An example of the File menu 4 Altera Corporation University Program May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS For some commands it is necessary to access two or more menus in sequence We use the convention Menu1 gt Menu2 gt Item to indicate that to select the desired command the user should first click the left mouse button on Menu1 then within this menu click on Menu2 and then within Menu2 click on Item For example File gt Exit uses the mouse to exit from the system Many commands can be invoked by clicking on an icon displayed in one of the toolbars To see the command associated with an icon position the mouse over the icon and a tooltip will appear that displays the command name 3 1 Quartus II Online Help Q
30. o this click on the icon click the mouse on the wire to be removed to select it and press Delete Compile the erroneous design by clicking on the icon A pop up box will ask if the changes made to the light bdf file should be saved click Yes After trying to compile the circuit Quartus II software will display a pop up box indicating that the compilation was not successful Acknowledge it by clicking OK The compilation report Altera Corporation University Program 17 May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS summary given in Figure 21 now confirms the failed result In the Table of Contents panel expand the Analysis amp Synthesis part of the report and then select Messages to have the messages displayed as shown in Figure 22 The Compilation Report can be dispayed as a separate window as in Figure 22 by right clicking its tab and selecting Detach Window and can be reattached by clicking Window gt Attatch Window Double click on the first error message which states that one of the nodes is missing a source Quartus II software responds by displaying the light bdf schematic and highlighting the OR gate which is affected by the error as shown in Figure 23 Correct the error and recompile the design Quartus II D MyWork UniversityProgram introtutorial light light File Edit Daehd amp t SB na amp 2 fight Project Navigator View Project Assignments Processing Tools Window Help
31. odule Altera s DE series board allows the configuration to be done in two different ways known as JTAG and AS modes The configuration data is transferred from the host computer which runs the Quartus II software to the board by means of a cable that connects a USB port on the host computer to the leftmost USB connector on the board To use this connection it is necessary to have the USB Blaster driver installed If this driver is not already installed consult the tutorial Getting Started with Altera s DE Series Boards for information about installing the driver Before using the board make sure that the USB cable is properly connected and turn on the power supply switch on the board In the JTAG mode the configuration data is loaded directly into the FPGA device The acronym JTAG stands for Joint Test Action Group This group defined a simple way for testing digital circuits and loading data into them which became an IEEE standard If the FPGA is configured in this manner it will retain its configuration as long as the power remains turned on The configuration information is lost when the power is turned off The second possibility is to use the Active Serial AS mode In this case a configuration device that includes some flash memory is used to store the configuration data Quartus II software places the configuration data into the configuration device on the DE series board Then this data is loaded into the FPGA upon power up or reconfigu
32. of libraries which include circuit elements that can be imported into a schematic Double click on the blank space in the Graphic Editor window or click on the icon in the tool bar that looks like an AND gate A pop up box in Figure 15 will appear Expand the hierarchy in the Libraries box as shown in the figure First expand libraries then expand the library primitives followed by expanding the library logic which comprises the logic gates Select and2 which is a two input AND gate and click OK Now the AND gate symbol will appear in the Graphic Editor window Using the mouse move the symbol to a desirable location and click to place it there Import the second AND gate by simply moving the mouse pointer to a new position and clicking to place another AND gate symbol there A symbol in the Graphic Editor window can be moved by clicking the icon in the toolbar that looks like a mouse cursor then clicking the symbol you want to move and dragging it to a new location with the mouse button pressed Next select or2 from the library and import the OR gate into the diagram Then select not and import two instances of the NOT gate Rotate the NOT gates into proper position by using the Rotate left 90 icon de Arrange the gates as shown in Figure 16 12 Altera Corporation University Program May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS Libraries SE cflalteraf 10 1 quartusilibraries H E megaFunctions H E others B EE primi
33. ration Thus the FPGA need not be configured by the Quartus II software if the power is turned off and on The choice between the two modes is made by the RUN PROG switch on the DE series board The RUN position selects the JTAG mode while the PROG position selects the AS mode 9 1 JTAG Programming The programming and configuration task is performed as follows Flip the RUN PROG switch into the RUN position Select Tools gt Programmer to reach the window in Figure 40 Here it is necessary to specify the programming Altera Corporation University Program 29 May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS hardware and the mode that should be used If not already chosen by default select JTAG in the Mode box Also if the USB Blaster is not chosen by default press the Hardware Setup button and select the USB Blaster in the window that pops up as shown in Figure 41 lt gt Programmer D MyWork UniversityProgram introtutorial light light light cdf File Edit View Processing Tools Window Help 2 A Hardware Setup Mode JTAG wt Progress Po L Enable real time ISF to allow background programming For Ma I and MAX Y devices Wc i Device Checksum Usercode Program verify Blank Examine 5e pi Start Configure Check ight O02F84BB FFFFFFFF mi Stop en Suto Detect W Delete ie Change File fet Save File o fi Down Figure 40 The Programmer window Observe that the configuration file light sof
34. s top and dragging it horizontally This reference line is used in analyzing the timing of a circuit move it to the time O position The waveforms can be drawn using the Selection Tool which is activated by selecting the icon in the toolbar To simulate the behavior of a large circuit it is necessary to apply a sufficient number of input valuations and observe the expected values of the outputs In a large circuit the number of possible input valuations 26 Altera Corporation University Program May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS may be huge so in practice we choose a relatively small but representative sample of these input valuations However for our tiny circuit we can simulate all four input valuations given in Figure 11 We will use four 50 ns time intervals to apply the four test vectors We can generate the desired input waveforms as follows Click on the waveform for the x node Once a wave form is selected the editing commands in the Waveform Editor can be used to draw the desired waveforms Commands are available for setting a selected signal to 0 1 arbitrary value inverting its existing value INV or defining a clock waveform Each command can be activated by using the Edit gt Value command or via the toolbar for the Waveform Editor The Edit menu can also be opened by right clicking on a waveform Set x to 0 in the time interval O to 100 ns which is probably already set by default Nex
35. t Figure 33 The Insert Node or Bus dialogue Altera Corporation University Program 25 May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS W Node Finder Ea Lookin port m Modes Found Selected Modes Type Input Input Mutpue Figure 34 Selecting nodes to insert into the Waveform Editor Click on the x signal in the Nodes Found box in Figure 34 and then click the gt sign to add it to the Selected Nodes box on the right side of the figure Do the same for x2 and f Click OK to close the Node Finder window and then click OK in the window of Figure 33 This leaves a fully displayed Waveform Editor window as shown in Figure 35 Simulation Waveform Editor light vwf File Edit view Help IDETE ESAE Master Time Bar gt Pointer 196 71 ns Interval 196 71 ns Stare fe End 120 0 ns 160 0 ns 700 0 ns Value at O ps BO BO Ba Oo 00 00 00 Figure 35 The nodes needed for simulation 7 We will now specify the logic values to be used for the input signals x and x2 during simulation The logic values at the output f will be generated automatically by the simulator To make it easy to draw the desired waveforms the Waveform Editor displays by default vertical guidelines and provides a drawing feature that snaps on these lines which can otherwise be invoked by choosing the Snap To Grid button Observe also a solid vertical line which can be moved by pointing to it
36. t set x to 1 in the time interval 100 to 200 ns Do this by pressing the mouse at the start of the interval and dragging it to its end which highlights the selected interval and choosing the logic value 1 in the toolbar Make x2 1 from 50 to 100 ns and also from 150 to 200 ns which corresponds to the truth table in Figure 11 This should produce the image in Figure 36 Observe that the output f is displayed as having an unknown value at this time which is indicated by a hashed pattern its value will be determined during simulation Save the file Simulation Waveform Editor light vwf File Edit view Help RJA e A BY a a lla asier Tn Bar CI C Pomer rass mena sl ee 120 0 ns 160 0 ns 200 0 ns I I I Value at O ps BO BO Ba Oo 00 00 00 Figure 36 Setting of test values 8 1 Performing the Simulation A designed circuit can be simulated in two ways The simplest way is to assume that logic elements and intercon nection wires in the FPGA are perfect thus causing no delay in propagation of signals through the circuit This is called functional simulation A more complex alternative is to take all propagation delays into account which leads to timing simulation Typically functional simulation is used to verify the functional correctness of a circuit as it is being designed This takes much less time because the simulation can be performed simply by using the logic expressions that define the circuit 8
37. the right of this new x1 entry in the column labeled Assignment Name Now the drop down menu in Figure 26 appears Scroll down and select Location Accepts wildcards groups Instead of scrolling down the menu to find the desired item you can just type the first letter of the item in the Assignment Name box In this case the desired item happens to be the first item beginning with L Finally double click the box in the column labeled Value Type the pin assignment corresponding to SWo for your DE series board as listed in Table 2 Use the same procedure to assign input x2 and output f to the appropriate pins listed in Table 2 An example using a DE2 board is shown in Figure 27 To save the assignments made choose File gt Save You can also simply close the Assignment Editor window in which case a pop up box will ask if you want to save the changes to assignments click Yes Recompile the circuit so that it will be compiled with the correct pin assignments 20 Altera Corporation University Program May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS Mode Finder Lookin light wt Include subentities Nodes Found Selected Nodes 4ssignments Type Assignments Unassigned Gutput Unassigned Input Unassigned Figure 25 The Node Finder displays the input and output names Assignment Name Value Enabled Entity Comment Tag Location 4ccepts wildcards qroups Ignore SOFT Buffers Ignore Yerilog initial constructs I
38. tives H E buffer EE logic F andiz ai F and3 EI and4 F and 1 ands EF bandiz Mame w Repeat insert mode Insert symbol as block Launch Megavvizard Plug In MegaWizard Plug In Manager Figure 15 Choose a symbol from the library Quartus II D MyWork UniversityProgram introtutorial light light File Edit View Project Assignments Processing Tools Window Help OsSEE S tS oa ne A A arv Project Navigator ox i light bd F Ej Entity dy Cyclone I EP2C35F light Bre Tasks oO x Task 4 E Compile E e Ana E B Fitte E ie assem gt Message System Processing A Extra Info Info N Warning IN Critical Warning A Error Jf Suppressed fa Flag j WaS i Oo 00 00 00 Figure 16 Import the gate symbols into the Graphic Editor window Altera Corporation University Program 13 May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS 5 2 Importing Input and Output Symbols Having entered the logic gate symbols it is now necessary to enter the symbols that represent the input and output ports of the circuit Use the same procedure as for importing the gates but choose the port symbols from the library primitives pin Import two instances of the input port and one instance of the output port to obtain the image in Figure 17 Quartus II D MyWork UniversityProgram introtutorial light light File Edit View Project Assignments Processing Tools window Help DSHS tea
39. tz2 is missing source H x Error Quartus II Analysis amp Synthesis was unsuccessful 1 error 2 warnings x Error Quartus II Full Compilation was unsuccessful 3 errors 2 warnings wi a a D pa i a 18 Message 0 of 18 t Location Locate Figure 21 Compilation report for the failed design 220 48 11 00 00 04 Altera Corporation University Program May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS Compilation Report D MyWork UniversityProgram introtutorial light light File Edit Tools Window Help Table of Contents i Analysis amp Synthesis Messages EJ Flow Summary ES Flow Settings ES Flow Non Default Global Settings ES Flow Elapsed Time ES Flow OS Summary Flow Log Analysis amp Synthesis A i Info Command quartus map read settings files on write settings files off i Info Parallel compilation is enabled and will use 4 of the 4 processors detecti 1 i Info Found 1 design units including 1 entities in source file light bdt i Info Elaborating entity light for the top level Hierarchy Warning Primitive AND2 of instance inst not used Wearning Primitive NOTY of instante insti not weed Errors Node insta is missing source Error Quartus II Analysis amp Synthesis was unsuccessful 1 error 2 warnings Summary E C Settings ES Parallel Compilation Ww Messages it Processing 10 Extra Info J Info 6 warning 2
40. uartus IT software provides comprehensive online documentation that answers many of the questions that may arise when using the software The documentation is accessed from the Help menu To get some idea of the extent of documentation provided it is worthwhile for the reader to browse through the Help menu If no web browser is specified Quartus will complain with an error message To specify a web browser go to Tools gt Options gt General gt Internet Connectivity Specify a path to a web browser in the web browser field The user can quickly search through the Help topics by selecting Help gt Search which opens a dialog box into which keywords can be entered Another method context sensitive help is provided for quickly finding documen tation for specific topics While using most applications pressing the F1 function key on the keyboard opens a Help display that shows the commands available for the application 4 Starting a New Project To start working on a new design we first have to define a new design project Quartus II software makes the designer s task easy by providing support in the form of a wizard Create a new project as follows 1 Select File gt New Project Wizard to reach the window in Figure 4 which asks for the name and directory of the project 2 Set the working directory to be introtutorial of course you can use some other directory name of your choice if you prefer The project must have a name which
41. vices Name Core oltage LEs User I Os Memory Bits EP2C6AF25618 1 24 6256 162 165888 EP2C8F256C6 1 2 6256 182 165888 EP2C8F256C 1 2 6256 182 165888 lt Companion device HardCopy Limit DSP amp RAM to HardCopy device resources Figure 7 Choose the device family and a specific device Note for IS1500 We use the DE2 board with a Cyclone I EP2C35F672C6 device Select Pin count 672 and Speed 6 to reduce the number of choices Altera Corporation University Program 7 May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS 4 We have to specify the type of device in which the designed circuit will be implemented Choose the Cyclone series device family for your DE series board We can let Quartus II software select a specific device in the family or we can choose the device explicitly We will take the latter approach From the list of available devices choose the appropriate device name for your DE series board A list of devices names on DE series boards can be found in Table 1 Press Next which opens the window in Figure 8 Cyclone III EP3C16F484C6 Cyclone II EP2C20F484C7 Cyclone H EP2C35F672C6 Table 1 DE series FPGA device names New Project Wizard EDA Tool Settings page 4 of 5 Specify the other EDA tools used with the Quartus II software to develop your project EDA tools Tool Type _Tool Name Format s Run Tool Automatically lt none gt lt None gt Run this too
42. xample we will use the two way light controller circuit shown in Figure 11 The circuit can be used to control a single light from either of the two switches x and x2 where a closed switch corresponds to the logic value 1 The truth table for the circuit is also given in the figure Note that this is just the Exclusive OR function of the inputs x and x2 but we will implement it using the gates shown X f 0 0 0 f 01 1 10 1 m 1 1 0 Figure 11 The light controller circuit The Quartus II Graphic Editor can be used to specify a circuit in the form of a block diagram Select File gt New to get the window in Figure 12 choose Block Diagram Schematic File and click OK This opens the Graphic Editor window The first step is to specify a name for the file that will be created Select File gt Save As to open the pop up box depicted in Figure 13 In the box labeled Save as type choose Block Diagram Schematic File bdf In the box labeled File name type light to match the name given in Figure 4 which was specified when the project was 10 Altera Corporation University Program May 2011 QUARTUS II INTRODUCTION USING SCHEMATIC DESIGNS created Put a checkmark in the box Add file to current project Click Save which puts the file into the directory introtutorial and leads to the Graphic Editor window displayed in Figure 14 Altera Corporation University Program May 2011 E Z New Quartus IT Project Desig
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