Evaluation Module User Manual
Contents
1. HEADPHONE DSP56852EVM RE10520B REV gt 55 lo o 1610 369 85 oo LEDS ee P3 P4 LINE OUT Figure 1 2 56F801EVM Jumper Reference Table 1 1 56F801EVM Default Jumper Options icici Comment JG1 Enable on board Byte selectable SRAM via CS1 CS2 U3 1 2 3 4 JG2 Enable on board Word selectable SRAM via CSO U2 1 2 JG3 Use on board XTAL crystal input for oscillator 1 2 JG4 Use on board EXTAL crystal input for oscillator 2 3 JG5 Enable SCI Port to RS 232 transceiver 1 2 3 4 JG6 Enable SPI Port to Serial EEPROM Data FLASH 1 2 3 4 5 6 amp 7 8 JG7 Enable on board Parallel JTAG Host Target Interface NC JG8 Enable RS 232 output NC JG9 Enable SSI Port for CODEC data 1 2 3 4 5 6 7 8 9 10 JG10 Enable GPIO for CODEC control 1 2 3 4 5 6 Introduction Rev 3 Freescale Semiconductor 1 3 56852EVM Connections An interconnection diagram is shown in Figure 1 3 for connecting the PC and the external 12 0V DC AC power supply or external 5 0V DC lab power supply to the 56852EVM board Parallel Extension Cable 56852EVM PC2. DSP56852EVM Schematics Rev 3 Appendix A 5 Freescale Semiconductor 40 99UU0D pue ZEZ SU 4104106 s V eJnBi4 3 I 5 v 2 Ol JO 19945 u is q adsa 2002 01 Menuer Aepsuny ojeg y NSQ INA3cS89S8dSG Jequnw 9215 jueuinooq HOLO3NNOO 222 58 1HOd IOS 0152 61 087 4 0609 17 087 98268 euozuy 1013 1523 0012 UOISIAIG 51 pJepuels H IavSIQ cec sa 89r HITVNH CEC SH 318VN3 22 59 IV3aSreceXVIN 44030H04 aAOLOANNOO anya 11050804 NIZI cec Ssa NO39H04 NISH 17098 1985 8 094 1 024 gt 1 Ag et aLNOTH 514 axa INOEL NIEL 512 10021 21 gt gt 11011 NI LL 5 sor 3 Freescale Semiconductor DSP56852EVM User Manual Rev 3 Appendix A 6 99po2 oeJejS 49 94 ISS 9 V 4 H a
3. Freescale Semiconductor DSP56852EVM User Manual Rev 3 en 01 HTAVSIA Z T H ISVNH ALAJ AAMOT NVUS ON ALAJ WVUS Hee 2 WIgVNH CHOM Was ton NOILdO 01140 318VN3 0S9 8 318VN3 050 155 AP H ML 294 1 919112 89 sou 1 919112 89 SSA an 235 SSA an 211 SSA a 5 199 SSA 81 EE Tor 0 i IM 3M um 0993 089 ge GA 30 30 Agero 1 aan 91V 91V 91v 9100 SLY 9100 SLY SLY sa Sd 10 bly nv 20 tr 7100 ELV ely oe ig 100 ev 21 aid GE Hs ony 010 TE 6Y A Ut ev ez 1d Sr 10 9v 90 SV 20 za L d ev 20 8 LY 10 ov 00 1 en 0 450 180 3 052 ATG 9TXM8ZT Appendix A 4 1 31 1219S 46 rv 4 0 JO 12945 ubiseq 0850 2002 01 Aepsinul leq y ezIS JequnN NSQ WA32S899dSQ AYOWAW WOHddd WEIEHSS 14 9L 0152 61 087 XvJ 0605 61 087 78268 euozuy 101113 1523 0012 UOISIAIG 51 PIEPUEIS 45 10 654 15 10 8SH e 05 8110805 1
4. Appendix A 9 I0Jo2UUo e onst aNd aNd Ag et axl lt lt _ voul 250 55 61 1 vv V AIS NOLS Sv ov 1 axis 91 9 lt 13534 GN9 55 5415 Sia 050 sad GN9 OSIN xous vid 5 55 ann ZIV 81 eid 9d tid OSIN eia sa NO ISOW va old a tad 2989 4 vua AIS 125 dNS S0 lt G 1 ISON saas 2 Lad 050 qxus E 18 ELV HM AND 61V 02 V 81 Toii LIV SIV 8v 50 555 027 sa 189 6v 0S9 oga DSP56852EVM Schematics Rev 3 Freescale Semiconductor seiddng Jamoq 6 V 91n614 I 9 2 Ol 10 6 1994 adsa 2002 01 Aepsuny oejeg y NSQ WAacS8d9SdSG Jequinw 9215 jueuinooq 53114405 HdMOd L 0152 61 087 0609 2 7 087 78268 euozuy adwal 101113 1523 0012 UOISIAIG pJepuels AG T ST ZT MOTA AS Z ST MOTA
5. E T 1 i 1 1 41 VA0 S AE 8 Agvet Agvet 5 LNIOd LNIOd LSEL NT ANNONS DOTYNY vAdS 088vVWI 280 Jj 8 2752 M TETTE ee SS GE 1E N 1 2 RN ENTM le 5 0 0 0 jnio 0 3110 0 Ano 3ni0 0 2 739 1 90 ego 190 099 675 870 179 970 579 AE E 5 5 5 5 AE E AE E AE AE AE Agvet VPEXOTVL SPZEXYW 818190 O0DVVL vOOVVL TIOHGSYLV gt 9TTZLSD OITELSD 5 3ni0 0 31100 31100 anyo jnio 0 jnio 0 0 0 5 tro 270 179 070 680 859 150 920 560 veo 650 g i o Ag e Ag e AS b AS 1 AS 1 AS 1 AG e Ag e Ag e Ag e Ag e Ag e zss89sasa 22 Hi Sow Maes da ee Bebe ee bum eee Ec Nd eh de eee 5 9 o LL DSP56852EVM User Manual Rev 3 Appendix A 12 Freescale Semiconductor Appendix B DSP56852EVM Bill of Material Qty Description Ref Designators Vendor Part s Integrated Circuits 1 DSP56852 U1 Freescale DSP56852VF120 2 GS72116 U2 U3 GSI GS72116ATP 7 1 AT45D
6. Sow 300MS gt gt ZHWN882 21 5 Y SW Ae e T 308338 7 yor TIM 810 AN ait 92m TIN 93W ocu wn z dues 10 1 HN cin f 33W _ ui ND 9 sibi 3122000 anzzoo o S09 Ut gan 919 ype foams 188 812 SW Sours IAOW poari Aus INIT Ex 02 55 1101 nun Ino dii HE 11071 UF 39027 T Mu ON Ho is Ase 1nou Sir 1nod 5 oF NT dir td 019 TITON NI ONE d Ed 6 9 F 8 v Appendix A 7 DSP56852EVM Schematics Rev 3 Freescale Semiconductor 1o 9 uuoo pue soej19 U OVI V 4 3 jo 19945 ubiseg 1450 2002 01 Aepsuny 29180 vi 8 a NSQ WA3eS89SdSQ JequinN 9215 a a jueuinooq HOLOANNOD ANY 39V3H31NI LADYVL LSOH 1311VdVd 018 1 08 XV3 0608 19 087 E 78298 euozuy 101113 1523 0012 Jeu vm se D UOISIAIG Sjonpo4d 15 45 002
7. Freescale Semiconductor 1 1 demonstrate the functionality of that software and interface with the customer s application specific device s The 56852EVM is flexible enough to allow a user to fully exploit the 56852 s features to optimize the performance of their product as shown in Figure 1 1 SPI Data RESET SPI FLASH LOGIC RESET 1M bit IRQ IRQ Interface MODE RS 232 DSub LOGIC MOBE Interface 9 Pin 50 Address Program Memory Data amp 128Kx16 bit SRAM Control Peripheral CS1 CS2 Daughter Data Memory Card 128Kx16 bit SRAM Connector Memory Daughter Card Connector Stereo 16 bit Stereo Line In JTAG ISSI Connecta JTAG EOnCE Codec Stereo Line Out Amp Headphone Jack Parallel DSub JTAG Debug 29 Interface GPIO LEDs 1 8V Power Supply XTAL EXTAL 3 3V 1 8V 3 3V amp amp GND 5 0V Figure 1 1 Block Diagram of the 56852EVM 1 2 56852EVM Configuration Jumpers Ten jumper groups JG1 JG10 shown in Figure 1 2 are used to configure various features on the 56852EVM board Table 1 1 describes the default jumper group settings DSP56852EVM User Manual Rev 3 1 2 Freescale Semiconductor 56852EVM Configuration Jumpers
8. 96852 Evaluation Module User Manual 56F850 16 bit Digital Signal Controllers DSP56852EVMUM Rev 3 07 2005 freescale com NA NA freescale semiconductor TABLE OF CONTENTS Preface vii Chapter 1 Introduction RENE ANICE quEAZSTQRE talents 1 1 127 SOSS2EVM Lonfipgutation oes Yd nns 1 2 L3 SORZBVMLLOBBECUOBR Les EERE 1 4 Chapter 2 Technical Summary bea dicia _ he Dues eb oed 2 2 22 FPropram and Data Memory aiia ous ee becuse det EA ac tiiki 2 3 221 SRAM BIER sobre ska rare ses RE 2 3 2 2 2 oe 2 3 23 SPI Serial EEPROM Data FLASH Memory 2 5 24 R5 232 Serial Communications 2 6 E 2 7 20 Operas Do crs u Rod oh Be rr 2 8 S 040 20 same prinsen ske eed ers 2 8 u oo 2 9 2 8 1 JL Ais C OME oe Ee usu 2 10 2 8 2 Parallel JTAG Interface Connector sssssaawawsaama aa 2 11 29 Lora dope dues 2 13 NCC POENAE 2 14 all Powa SUGGS gt 2 15 ha 2 16 2 12 1 Analog 2 17 2122 Digtal IIS 2 17
9. 2 13 Daughter Card RUSO Lau u u aaa 2 19 2 13 1 Memory Daughter Card Expansion Connector 2 19 2 13 2 Peripheral Daughter Card Expansion Connector 2 21 J Ten PAR been he ee 2 22 Table of Contents Rev 3 Freescale Semiconductor i Appendix A DSP56852EVM Schematics Appendix B DSP56852EVM Bill of Material DSP56852EVM User Manual Rev 3 ii Freescale Semiconductor 1 1 1 2 1 3 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 LIST OF FIGURES Block Diagram of the 508 52EVML 1 2 M Jumper Referenc 1 3 Connecting the 56852EVM aida ded eed bd ER EIE 1 4 Schematic Diagram of the External CSO Memory Interface 2 3 Schematic Diagram of the External CS1 CS2 Memory Interface 2 4 SPI EEPROM Memory Block Diggins uai icc R4 EROR ORCI AR itatis 2 5 Schematic Diagram or the RS 232 Interface is ioa dao 2 6 Schematic Diagram of the Clock 2 7 Schematic Diagram of the Debug LED Interface 2 9 Block Diagram of the Parallel JTAG 2 11 Schematic Diagram of the User Interrupt 2 13 Schematic Diagram o
10. fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized a
11. 00994 T SEL 2 Siu i tie x oe Aux Figs 002 000 10 13938 d s lt M fr H L_pnce uod vid 158177 Lasay lt or Tasau T7 13598 T7 ars Too ABBE ree yy ET 101 jebrel pzeog uo yrs wszaa nr uuo 18 eeu mu 1034805 180d fo or 289 92 Lo 9 wyo 15 ars 99 01H boar Ne e DE AS APER pve 99A 1HOd Lo on SEC sar ezu we 30 1804 1 7 2 2 2 ro LAZ hye anj AAA ISUL T 5 TT oz 1581 IHOd Flo M gar 101 3 fi 18098 Fo SAL evl bg 719 WoL vr biz WoL 1H0d el avt SNL Y on SWI IHOd Y otr iu G wig 13538 1809 TT y 8m 0 2 su k k 0 2 1804 OWLE DSP56852EVM User Manual Rev 3 Freescale Semiconductor Appendix A 8 10 D9UUOD uoisuedx3 8 0L jo 8 19945 ubiseq qdsq ueuBiseq 2002 0 Aepsinul ejeg NSQ WASA S89SdSd JequnnN 9215 SHOLO3NNOO NOISNVdX3 QHVO HALHONVG enu 0152 61 087 XvJ 0605 61 087 8068 euozuy 10113 1523 0012 UOISIAIG 51 5 dsa TND
12. 15 450 QVr0OVrZOW 0 2 0 2 Naw ET 9031 drin 07097195 0 2 1 UT 18d PEH san avin QVvr0OVrZ29N 0 2 daa i BE Hj 5 tod 5 9 70371 arin 0709719 1 vid y 231 A 09709715 oz MOTIHA 524 Y vod 2031 avin dvr0ovrLon 0 2 daa AR t T zd iaa vein 9 lt lt ax lt SS lt IsoW lt osin lt 259 0214 25895450 13838 Iy 1383u ga VSSA 39 SNL SNL AE E 0 YOT 1561 1SHL 9SSA SSSA YSSA ESSA ZSSA ISSA 900A saga ah 1 zta 7 9 ora 9 0 ES 40 7 55 2 20 FE 90 3 s EISSA sa 2088 LISSA za Fer 10 291 010 9004 oa LNOW19 0 0 650 61 1000A LK 134 0XL gt 03d axu ISON 59 4 SAHS ISON OSINY vOd WOHS OSIN SSI T 9d S41S SS HOS L 24 215 28 5 gt 104 88 axis 009 0 18 1 1 3 1 1 DSP56852EVM User Manual Rev 3 Freescale Semiconductor Appendix A 2 8 poN 1008 12010 Josey Z Y 3 a T O
13. 3 3V noted as a negative value Blue Text Linkable on line refer to Chapter 7 License Bold Reference sources See paths emphasis www freescale com DSP56852EVM User Manual Rev 3 viii Freescale Semiconductor Definitions Acronyms and Abbreviations Definitions acronyms and abbreviations for terms used in this document are defined below for reference Codec DSP EEPROM EOnCE EVM GPIO IC ISSI JTAG LED MBGA MPIO PCB PLL ROM SCI COder DECoder a part used to convert analog signals to digital coder and digital signals to analog decoder Digital Signal Processor or Digital Signal Processing Electrically Erasable Programmable Read Only Memory Enhanced On Chip Emulation a debug bus and port created by Freescale to enable a designer to create a low cost hardware interface for a professional quality debug environment Evaluation Module a hardware platform which allows a customer to evaluate the silicon and develop his application General Purpose Input and Output port on Freescale s family of controllers does not share pin functionality with any other peripheral on the chip and can only be set as an input output or level sensitive interrupt input Integrated Circuit Improved Synchronous Serial Interface port on Freescale s family of controllers Joint Test Action Group a bus protocol interface used for test and debug Light Emitting Diode MAP Ball Grid Arra
14. 9 8 v 01 0 9 19945 ubiseq 0450 ueufiseq 2002 01 Aepsiny 29180 g v 607 1 325895450 JqunN 9215 jueuinooq 93009 O3H3IS 118 91 ISS 0078 T t 32985 _ 09 6 0 0192 61 089 xv3 060 617 087 00 2T 0 78298 euozuy adway 10118 1583 0012 DURE 00 02 6 0 UOISIAIG 51 PIEPUEIS 454 00 vc 0 0 1300W 00 2 0 0 we SLIHZE HELSVN 00 87 0 0 0 GHIONIHS Ace ZEN S LAN 9AN ny y 0N9 NOLDHS s pano VAU S SSVdA8 Fabs ORES aniy 9 Y SSVdA8 au B L dan 0 02 83W 3192 Tad axu ype f oaas El P LIW 034 gt vino En We I Rison 20 5 T anol z NHd dil andy 2 x00 ani Or NHd ONE So 1109 I3938 93000 1 59 Km 54 zva 120 ONASI 03000 9 s 996 zm 51983300 ej akas 11045 03000 1 2 8105 23002 85 dob AA TIN A ae 20 02 07 81250 SY NOLNAS Leu gy CNS YANS ZS wero 00 Egi o vAo s yk 08 NIIS 23002 W108 1104 93009 WQ san anvo ONASS X108 23402 oso zHWS8zZ 60 ER Nad 55 9NASd 93009 ano eae N d Au 13538 For ns 030027 ot pey 599 3qons 2 82 ZI i F A 2 300 5 99 dn
15. GND 12 GND 13 GND 14 GND 15 SRXD 16 5 17 MOSI SRFS 18 CS1 PA1 19 SCK SCLK 20 CS2 PA2 21 GND 22 GND 23 MOSI 24 GND 25 MISO 26 GND 27 GND 28 GND 29 ss 30 GND 31 MISO SRCK 32 GND 33 SS STFS 34 GND 35 RESET 36 GND 37 GND 38 GND 39 STXD 40 GND 41 SCK STCK 42 GND Technical Summary Rev 3 Freescale Semiconductor 2 21 Table 2 12 Peripheral Daughter Card Connector Description Continued J2 Pin Signal Pin Signal 43 IRQB 44 RXD 45 IRQA 46 TXD 47 3 3V 48 3 3V 49 GND 50 GND 51 5 0V 2 14 Test Points The 56852EVM board has a total of seven test points Three digital GND test points are located in corners of the board The 5 0VA and AGND test points are located in the analog corner of the board The 1 8V and 3 3V test points are located in the power supply section of the board DSP56852EVM User Manual Rev 3 2 22 Freescale Semiconductor Appendix A DSP56852EVM Schematics DSP56852EVM Schematics Rev 3 Freescale Semiconductor Appendix 1 sq31 pue 10sse oJd 26896 eJnBi4 3 Ol JO 19945 ubiseq 0490 1 200201 Aepsiny 29180 vt NSGWAAZS89SdSO 925 5031 9 830 pue 105592014 25895450 0152 61 087 4 060S Lp 087 78258 euozuy 101119 1523 0012 UOISIAIG S ONPOld
16. connect his own SPI port peripheral Since the SPI port and ISSI port are multiplexed on the 56852 the SPI port jumpers need to be removed to use the ISSI port The header details are shown in Table 2 1 Data FLASH Enable Serial EEPROM 56852 SPI Port Connector Data FLASH MOSI SRFS SDI MISO SRCK SDO SCLK STCK SS STFS PC3 Figure 2 3 SPI EEPROM Memory Block Diagram Table 2 1 SPI Port Connector Description JG6 Pin Signal Pin Signal 1 SS STFS PC3 2 cs 3 MISO SRCK 4 SDO 5 MOSI SRFS 6 SDI 7 SCLK STCK 8 SCK Technical Summary Rev 3 Freescale Semiconductor 2 5 2 4 RS 232 Serial Communications The 56852EVM provides an RS 232 interface by the use of an RS 232 level converter Maxim MAX3245EEAI designated as U6 Refer to the RS 232 schematic diagram in Figure 2 4 The RS 232 level converter transitions the SCI UART s 3 3V signal levels to RS 232 compatible signal levels and connects to the host s serial port via connector P6 Flow control is not provided but could be implemented using uncommitted GPIO signals The pinout of connector P6 is listed in Table 2 2 The RS 232 level converter transceiver can be disabled by placing a jumper at JG8 RS 232 Level Converter Interface Jumper Removed Enable RS 232 Jumper Pin 1 2 Disable RS 232 Figure 2 4 Schematic Diagram of the RS 232 Interface Table
17. out of the device The ISSI port which is multiplexed with the SPI port consists of independent transmitter and receiver sections and is used for serial communication with the codec On the controller side the Serial Transmit Data pin STXD is an output when data is being transmitted to the codec The Serial Receive Data pin SRXD is an input when data is being received from the codec These two pins are connected to the codec s Serial Data Input SDIN and Serial Data Output SDOUT pins The controller s Transmit Serial Clock pin STCK provides the serial bit rate clock for the ISSI interface It is connected to the CODEC s Serial Port Clock pin SCLK Data is transmitted on the rising edge of SCLK and is received on the falling edge of SCLK The controller s GPIO PORT C Bit 4 pin PC4 is programmed to control the codec s Active Low Reset signal RESET The Serial Transmit Frame Sync pin STFS is programmed to control the codec s Frame Sync signal FSYNC This signal is sampled by SCLK with a rising edge indicating a new frame is about to start The FSYNC frequency is always the system s sample rate It may be an input to the codec or it may be an output from the codec in data mode Technical Summary Rev 3 Freescale Semiconductor 2 17 The basic codec digital connections are shown in Figure 2 12 Table 2 9 and Table 2 10 The codec s MODE is set by the three MODE selection resistors R66 R68 In the factory default se
18. the features of the 56800E architecture The tools and examples provided with the 56852EVM facilitate evaluation of the feature set and the benefits of the family Serving as a platform for real time software development The tool suite enables the user to develop and simulate routines download the software to on chip or on board RAM run it and debug it using a debugger via the JTAG Enhanced OnCE EOnCE port The breakpoint features of the EOnCE port enable the user to easily specify complex break conditions and to execute user developed software at full speed until the break conditions are satisfied The ability to examine and modify all user accessible registers memory and peripherals through the EOnCE port greatly facilitates the task of the developer Serving as a platform for hardware development The hardware platform enables the user to connect external hardware peripherals The on board peripherals can be disabled providing the user with the ability to reassign any and all of the controller s peripherals The EOnCE port s unobtrusive design means that all memory on the board and on the chip is available to the user 1 1 56852EVM Architecture The 56852EVM facilitates the evaluation of various features present in the 56852 part The 56852EVM can be used to develop real time software and hardware products based on the 56852 The 56852EVM provides the features necessary for a user to write and debug software Introduction Rev 3
19. 2 2 RS 232 Serial Connector Description 6 Pin Signal Pin Signal 1 Jumper to 6 amp 4 6 Jumper to 1 amp 4 2 TXD 7 Jumper to 8 3 RXD 8 Jumper to 7 4 Jumper to 1 amp 6 9 N C 5 GND DSP56852EVM User Manual Rev 3 2 6 Freescale Semiconductor Clock Source 2 5 Clock Source The 56852EVM uses a 4 00MHz crystal Y1 connected to its External Crystal Inputs EXTAL and XTAL To achieve its 120MHz maximum operating frequency the 56852 uses its internal PLL to multiply the input frequency by 30 An external oscillator source can be connected to the controller by using the oscillator bypass connectors JG3 and JG4 see Figure 2 5 If the input frequency is above 4MHz then the EXTAL input should be jumpered to ground by adding a jumper between JG4 pins 1 and 2 The input frequency would then be injected on JG3 s pin 2 If the controller needs to be synchronized to the codec s sample frequency then the controller s input frequency should be jumpered using the 12 2280MHz codec frequency If the input frequency is below 4MHz then the input frequency can be injected on JG4 s pin 2 EXTERNAL OSCILLATOR HEADERS JG4 4 00mHz 12 2880MHz Figure 2 5 Schematic Diagram of the Clock Interface Technical Summary Rev 3 Freescale Semiconductor 2 7 2 6 Operating Mode The 56852EVM provides a boot up MODE selection switch 55 This switch is used to select the operati
20. B011 U4 Atmel AT45DB011B SC 1 CS4218 U5 Crystal Semiconductor CS4218 KQ 1 MAX3245 U6 Maxim MAX3245EEAI 1 3 3V Voltage Regulator U7 ON Semiconductor MC33269DT 3 3 1 1 8V Voltage Regulator U8 ON Semiconductor MC33269DT ADJ 1 74LCX244 U9 ON Semiconductor MC74LCX244ADW 1 74AC00 U10 Fairchild 74 005 1 12 288MHz OSC U11 Epson SG 531P 12 288MC 1 LM4880 U12 National Semiconductor LM4880M 1 5 0V Voltage Regulator U13 ON Semiconductor MC33269DT 5 1 74AC04 U14 ON Semiconductor MC74ACO4AD 1 DS1818 U16 Dallas Semiconductor DS1818 Resistors 1 243 0 1 R1 SMEC RC73L2430HMFT 1 107 1 R2 SMEC RC73L1070HMFT 12 2700 R3 R8 R72 R77 SMEC RC73L2A2700HMJT 2 510 R10 R11 SMEC RC73L2A51OHMJT DSP56852EVM Bill of Material Rev 3 Freescale Semiconductor Appendix B 1 Qty Description Ref Designators Vendor Part s Resistors Continued 5 5 1KQ R9 R12 R14 R48 SMEC RC73L2A5 1KOHMJT 6 47K Q R15 R17 R18 R78 R83 R84 SMEC RC73L2A47KOHMJT 1 10M Q R16 SMEC RC73L2A10MOHMJT 4 5 62K Q 1 R19 R20 R23 R25 SMEC RC73L2A5 62KOHMFT 23 10K Q R21 R22 R24 R26 R29 SMEC RC73L2A10KOHMJT R31 R34 R36 R38 R58 R61 R64 R70 R71 R79 R82 R85 2 39 2K 1 R27 R28 SMEC RC73L2A39 2KOHMFT 13 1KQ R32 R33 R50 R57 R62 R63 SMEC RC73L2A1KOHMJT R65 4 20 0K Q 1 R37 R39 R42 R44 SMEC RC73L20 0KOHMFT 3 470K Q R41 R43 R86 SM
21. CS1 and CS2 uses a 128K x 16 bit Fast Static RAM GSI GS72116 labelled U3 for external memory expansion see the FSRAM schematic diagram in Figure 2 2 Using CS1 and CS2 this memory bank can be configured as byte 8 bit or word 16 bit accessable program memory data memory or both Additionally CS1 and CS2 can be configured to assign this memory s size and starting address to any modulo address space Technical Summary Rev 3 Freescale Semiconductor 2 3 This memory bank will operate with one wait state access while the 56852 is running at 120MHz and can be disabled by removing the jumpers at JG1 GS72116 0 16 000 0015 WE LB HB CE Jumper Pin 1 2 Enable SRAM Low Byte Jumper Pin 3 4 Enable SRAM High Byte Figure 2 2 Schematic Diagram of the External CS1 CS2 Memory Interface DSP56852EVM User Manual Rev 3 2 4 Freescale Semiconductor SPI Serial EEPROM Data FLASH Memory 2 3 SPI Serial EEPROM Data FLASH Memory A 1M bit 3 3V SPI serial EEPROM Data FLASH Memory Atmel AT45DB011B SC is provided on the 56852EVM reference Figure 2 3 This memory connects directly to the SPI Port through a header on the 56852 It can be used to load program code and data into the 56852 s internal or external memory spaces Jumper block JG6 is provided to allow the user to disconnect the on board SPI EEPROM Data FLASH from the SPI port and allow him to
22. EC RC73L2A470KOHMJT 0 10K R45 SMEC RC73L2A10KOHMJT 2 00 R66 R67 SMEC RC73JP2A 0 00 R68 SMEC RC73JP2A Inductors 4 1 0mH FERRITE BEAD L1 L4 Panasonic EXC ELSA35V LEDs 2 Red LED LED1 LED4 Hewlett Packard HSMS C650 2 Yellow LED LED2 LED5 Hewlett Packard HSMY C650 3 Green LED LED3 LED6 LED7 Hewlett Packard HSMG C650 Diode 1 S2B FM401 D1 Vishay DL4001DICT 1 50V 1A BRIDGE RECT D2 DIODES DF02S DSP56852EVM User Manual Rev 3 Appendix B 2 Freescale Semiconductor Qty Description Ref Designators Vendor Part s Capacitors 1 470uF 16V DC C1 ELMA RV 16V471MH10R 21 O 1uF C2 C4 C6 C20 C30 C32 C34 C36 C38 C40 C42 C44 C46 C48 C50 C51 C53 C54 C56 C58 SMEC MCCE104K2NR T1 6 47uF 16V DC C3 C5 C7 C19 C22 C24 ELMA RV2 16V470M R 2 0 33uF C8 C13 SMEC MCCE334K3NR T1 2 470pF C9 C11 SMEC MCCE471J2NO T1 9 1 25V DC C10 C12 C21 C23 C25 C29 SMEC MCCE105K3NR T1 2 0 0022uF C14 C15 SMEC MCCE222K2NR T1 3 0 47 uF C16 C18 SMEC MCCE474K3NR T1 12 0 01 C33 C35 C37 C39 C41 SMEC MCCE103K2NR T1 C45 C47 C49 C52 C55 C57 Jumpers 3 1 x 2 2mm Header JG2 JG7 JG8 SAMTEC TMM 102 02 S S 2 3 x 1 2mm Header JG3 JG4 SAMTEC TMM 103 02 S S 1 4 x 2 2mm Header JG6 SAMTEC TMM 104 02 S D 2 2 x 2 2mm Header JG1 JG5 SAMTEC TMM 102 02 S D 1 5 x 2 2mm Header
23. EVM User Manual Rev 3 Index 2 Freescale Semiconductor How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or
24. JG9 SAMTEC TMM 105 02 S D 1 3 x 2 2mm Header JG10 SAMTEC TMM 103 02 S D Test Points 4 Black Test Point TP1 TP3 TP6 TP7 Keystone 5001 1 Red Test Point TP2 Keystone 5000 1 White Test Point TP4 Keystone 5002 1 Yellow Test Point TP5 Keystone 5004 Crystals 1 4 00MHz Crystal Y1 CTS ATSO4ASM T DSP56852EVM Bill of Material Rev 3 Freescale Semiconductor Qty Description Ref Designators Vendor Part s Connectors 1 DB25M Connector 1 AMPHENOL 617 C025P AJ121 1 2 1mm coax P2 Switchcraft RAPC 722 Power Connector 3 1 8 Stereo Jack P3 P5 Switchcraft 35RAPC4BHN2 1 DE9S Connector P6 AMPHENOL 617 C009S AJ120 2 51 Pin HD Connector J1 J2 BERG 91930 21151 1 7 x 2 Bergstick J3 SAMTEC TSW 107 07 S D 1 2 Pin Terminal Block TB1 On Shore Technology ED500 2DS Switches 3 SPST Pushbutton 51 53 Panasonic EVQ PADO5R 2 3 Position DIP SW 54 55 CTS 209 3LPST Transistors 1 2N2222A Q1 ZETEX FMMT2222ACT Miscellaneous 19 2mm Shunt SH1 SH19 Samtec 2SN BK G 4 Rubber Feet RF4 3M SJ5018BLKC DSP56852EVM User Manual Rev 3 Appendix B 4 Freescale Semiconductor Clock Source 2 7 Codec Preface ix Codec sample rate selector 2 2 Connecting the DSP56852EVM Cables 1 4 Connectors Memory Daughter Card Expansion 2 19 D Daughter Card Connectors 2 19 Daughter Card Expansion interface 2 1 Debug
25. L 2 19945 ubiseg 0450 ueuBiseq 2002 ot Aienuep ejeq V 921 NSC WA32989SdS pan 15 SOU SGOW 1008 42012 13S3H SHL 0198 61 09 XvV4 060S ELr 087 78568 euozuy odwal 101113 1523 0012 UOISIAIG 51 pJepuels 45 8 8 818154 10 7 3oeles HdOW 3008 sta yJ lt vid rr eld T 55 Ag et zeo lt lt NOLLNENSNS LASHA dno ES 301 StH goul cs M01 NOLLNGHSNd H NI Ag e 1 lt lt anyo 060 VOYI lt lt _ lt 15 M01 NOLLINGHSNd VOUI V1X3 lt Ag e lt ZHN88Z 21 wo oiu ZHNW00 LA DSP56852EVM Schematics Rev 3 Appendix A 3 Freescale Semiconductor AiowawW NVYS 250 159 234g 052 lt 5 7 0 JO 6 19945 ubiseq 0850 ueubiseq 2002 90 1940120 Aepuns ejeq y 184 NSG WAdzS89SdSa 9215 AHON3N 259 159 3148 v1va pue 050 enu 019 17 087 Xv3 0609 17 087 78258 euozuy 101113 1523 0012 UOISIAIG Sionpo4d PIEPUEIS dsa
26. MOTU A8 I XOj 1 LOT m DAOL 401 L aniy T SZ T MOA zu 19 I ubrus 1 erz LH POv La69zeeon 3 amores ASI AAA r AL 21 z an amp amp 1069 Bo 100A anyo amas 5 10692660 1 LNOA LNOA 10074 10074 UOLVINDHA A AOS CHI yr li 4031 0 2 u AE e qva8 3114434 VAN 99 VA0 S v1 qva8 3114434 O 9 1 Ge 075 4 gt DW OGAZT L LAENI TVNIHLXH DSP56852EVM User Manual Rev 3 Freescale Semiconductor Appendix A 10 lt lt AX sde ssed g 70 anbi4 E 0 JO 01 1eeus ubiseq qdsq 1 6 2002 01 Aepsinul ejeg V lt NSQ INA3cS89S8dSG Jequnw 9215 SdVO SSVdA8 911 0152 61 087 4 0609 17 08 8068 euozuy 101113 1523 0012 UOISIAIG S12npo4d dsa e gt LSHL INIOd 1545 LNIOd 1541 441 S EX E x ae Um T i 1 D g 541 tdl L 941 241 anyo 4110 0 anyo jnio 0 850 199 940 SSO 6 s s
27. SP56800E Reference Manual DSP56800ERM Provides a detailed description of the core processor including internal status and control registers and a detailed description of the family instruction set Refer to these documents for detailed information about chip functionality and operation They can be found on this URL www freescale com DSP56852EVM User Manual Rev 3 2 2 Freescale Semiconductor Program and Data Memory 2 2 Program and Data Memory The 56852EVM contains two 128K x16 bit Fast Static RAM banks SRAM bank 0 is controlled by CSO and SRAM bank l is controlled by CS1 and 52 2 2 1 SRAM Bank 0 SRAM bank 0 which is controlled by CSO uses a 128K x16 bit Fast Static RAM GSI GS72116 labeled U2 for external memory expansion see the FSRAM schematic diagram in Figure 2 1 CSO can be configured to use this memory bank as 16 bit program memory data memory both Additionally CSO can be configured to assign this memory s size and starting address to any modulo address space This memory bank will operate with one wait state access while the 56852 is running at 120MHz and can be disabled by removing the jumper at JG2 6572116 0 16 000 0015 Jumper Pin 1 2 Enable SRAM Jumper Removed Disable SRAM Figure 2 1 Schematic Diagram of the External CSO Memory Interface 2 2 2 SRAM Bank 1 SRAM bank 1 which is controlled by
28. board Parallel Host Target Interface and a interface connector for external Target Interface support Two interface connectors are provided to support each of these debugging approaches These two connectors are designated the JTAG connector and the Host Parallel Interface Connector Technical Summary Rev 3 Freescale Semiconductor 2 9 2 8 1 JTAG Connector The connector on the 56852 allows the connection of an external Host Target Interface for downloading programs and working with the 56852 s registers This connector is used to communicate with an external Host Target Interface which passes information and data back and forth with a host processor running a debugger program Table 2 5 shows the pin out for this connector Table 2 5 JTAG Connector Description J3 Pin Signal Pin Signal 1 TDI 2 GND 3 TDO 4 GND 5 TCK 6 GND 7 NC 8 KEY 9 RESET 10 TMS 11 3 3V 12 NC 13 DE 14 TRST When this connector is used with an external Host Target Interface the parallel JTAG interface should be disabled by placing a jumper in jumper block JG7 Reference Table 2 6 for this jumper s selection options Table 2 6 Parallel JTAG Interface Disable Jumper Selection JG7 Comment No jumpers On board Parallel JTAG Interface Enabled 1 2 Disable on board Parallel JTAG Interface DSP56852EVM User Manual Rev 3 2 10 Freescale Semiconduct
29. compatible Computer E Connect cable r nP2 10 to Parallel Printer port 5 0V with 2 1mm 49 ov Lab receptacle connector Supply Figure 1 3 Connecting the 56852EVM Cables Perform the following steps to connect the 56852EVM cables 1 Connect the parallel extension cable to the Parallel port of the host computer 2 Connect the other end of the parallel extension cable to P1 shown in Figure 1 3 on the 56F801EVM board This provides the connection which allows the host computer to control the board 3 Make sure that the external 12 0V DC 1 2A switching power supply or the external 5 0V DC 1A lab power supply is not plugged into a 120V AC power source 4 Connect the 2 1mm output power plug from the external switching power supply into P2 shown in Figure 1 3 on the 56852EVM board Optionally attach an external 5 0V DC lab power supply via the 2 pin terminal block TB1 5 Apply power to the external power supply The green Power On LED LED7 will illuminate when power is correctly applied DSP56852EVM User Manual Rev 3 1 4 Freescale Semiconductor Chapter 2 Technical Summary The 56852EVM is designed as a versatile controller development card for developing real time software and hardware products to support a new generation of applications in digital and wireless messaging digital answering machines feature phones modems and digital cameras The power of
30. ector 54 Peripheral Daughter Card Expansion Connector to allow the user to connect his own SCI ISSI SPI or GPIO compatible peripheral to the controller J2 Memory Daughter Card Expansion Connector to allow the user to connect his own memory or memory device to the controller J1 On board power regulation from an external 12V DC supplied power input P2 On board power regulation from an optional 5V DC supplied power input TB 1 Light Emitting Diode LED power indicator LED7 Six on board real time user debugging LEDs LED 1 6 Boot MODE selector 55 Manual RESET push button 53 Manual interrupt push button for IRQA S1 Manual interrupt push button for S2 2 1 56852 The 56852EVM uses a Freescale DSP56852VF120 part designated as U1 on the board and in the schematics This part will operate at a maximum speed of 120MHz A full description of the 56852 including functionality and user information is provided in these documents DSP56852 Technical Data DSP56852 Provides features list and specifications including signal descriptions DC power requirements AC timing requirements and available packaging DSP56852 User s Manual DSP56852UM Provides an overview description of the controller and detailed information about the on chip components including the memory and I O maps peripheral functionality and control status register descriptions for each subsystem D
31. f the RESET 2 14 Schematic Diagram of the Power 2 15 Codec Analog COnnectioBS 2 17 CSA 15 Siero PURO UU IE do doe od 2 18 List of Figures Rev 3 Freescale Semiconductor iii DSP56852EVM User Manual Rev 3 Freescale Semiconductor 1 1 2 1 22 s3 2 4 2 5 2 6 dus 2 8 2 9 2 10 2 11 2 15 LIST OF TABLES 56F801EVM Default Jumper 1 3 SPI Port Connector Descriptio u uy ios adiac 2 5 RS 232 Serial Connector us du ded br RA ER E ded or Rob rends 2 6 Operatins Mode Soloolloll uu aqu eye e a es eee Kees 2 8 pla js idees 2 8 JTAG Connector u be oe ER e DUE RR ek oS 2 10 Parallel JTAG Interface Disable Jumper Selection 2 10 Parallel JTAG Interface Connector Description 2 12 Codec Sample Rate 2 16 SSI Port Connector 2 18 GPIO Port Connector DOSerDllOB uu os vada 2 19 Memory Daughter Card Connector Description 2 19 Peripheral Daughter Card Connector Description 2 21 List of Tables Rev 3 Freescale Semiconductor V DSP56852EVM User Manual Rev 3 vi Freescale Semiconductor Preface This reference manual describes
32. ging 2 8 DSP Preface ix DSP56852EVM 1 M bit Serial EEPROM Data FLASH 2 1 12 0V DC power supply 2 15 128Kx16 bit of data memory U3 2 1 128Kx16 bit of memory U2 2 1 16 bit 1 8V 3 3V Digital Signal Processor 2 1 16 bit stereo codec interface 2 1 4 00MHz crystal oscillator 2 1 external oscillator frequency input 2 1 FSRAM 2 1 ISSI compatible peripheral 2 2 JTAG port interface 2 1 On board power regulation 2 2 Parallel Host Target Interface 2 1 real time debugging 2 8 RS 232 interface 2 1 SCI compatible peripheral 2 2 test points 2 22 E EEPROM Preface ix EOnCE Preface ix EVM Preface ix F FSRAM 2 3 G GPIO Preface ix 2 2 INDEX H Host Parallel Interface Connector 2 9 Host Target Interface 2 9 IC Preface ix ISSI Preface ix J JTAG Preface ix 1 1 2 1 connector 2 10 Jumper Group 1 3 JG1 1 3 JG10 1 3 JG2 1 3 163 1 3 JG4 1 3 JG5 1 3 JG6 1 3 JG7 1 3 108 1 3 JG9 1 3 L LED Preface ix MBGA Preface ix MPIO Preface ix Operating Mode 2 8 P PCB Preface ix PLL Preface ix Index Rev 3 Freescale Semiconductor Index 1 R RAM Preface ix ROM Preface ix RS 232 interface 2 1 2 6 level converter 2 6 schematic diagram 2 6 RS 232 Serial Communications 2 6 5 SCI Preface ix SPI Preface x 2 2 SRAM Preface x external data 2 1 external program 2 1 SSI Preface x stereo 16 bit codec interface 2 1 Stereo headphone interface 2 1 WS Preface x DSP56852
33. gure 2 8 S1 allows the user to generate a hardware interrupt for signal line IRQA S2 allows the user to generate a hardware interrupt for signal line IRQB These two switches allow the user to generate interrupts for his user specific programs 3 3V 56852 10K 51 5 0 IRQA 0 1 lt 3 3V 10K S2 5 e IRQB OAUF zx Figure 2 8 Schematic Diagram of the User Interrupt Interface Technical Summary Rev 3 Freescale Semiconductor 2 13 2 14 2 10 Reset and the user RESET push button refer to Figure 2 9 Logic is provided on the 56852 to generate an internal Power On RESET Additional reset logic is provided to support the RESET signals from the JTAG connector the Parallel JTAG Interface JTAG_RESET RESET RESET PUSHBUTTON EE d MANUAL RESET TRST JTAG_TAP_RESET Figure 2 9 Schematic Diagram of the RESET Interface DSP56852EVM User Manual Rev 3 Freescale Semiconductor Power Supply 2 11 Power Supply The main power input 12 0V DC AC to the 56852EVM is through a 2 1mm coax power jack An optional 5 0V DC power supply input is available through a 2 pin terminal block TB1 A 12 0V DC 1 2A power supply is provided with the 56852EVM however less than 500mA is required by the EVM The remaining current is available for user daughter card applications when connected to the daughter card interface The power regulati
34. in detail the hardware on the 56852 Evaluation Module Audience This document is intended for application developers who are creating software for devices using the Freescale 56852 part Organization This manual is organized into two chapters and two appendixes Chapter 1 Introduction provides an overview of the EVM and its features Chapter 2 Technical Summary describes in detail the 56852 hardware Appendix A DSP56852EVM Schematics contains the schematics of the 56852EVM Appendix DSP56852EVM Bill of Material provides a list of the materials used on the 56852EVM board Suggested Reading More documentation on the 56852 and the 56852EVM kit may be found at URL www freescale com Preface Rev 3 Freescale Semiconductor vii Conventions This manual uses the following notational conventions Term or Value Symbol Examples Exceptions Active High Signals No special symbol AO Logic One attached to the signal CLKO name Active Low Signals Noted with an WE In schematic drawings Logic Zero overbar in text and in OE Active Low Signals may be most figures noted by a backslash WE Hexadecimal Values Begin with a sym bol 80 Decimal Values No special symbol 10 attached to the 34 number Binary Values Begin with the letter b1010 b attached to the b0011 number Numbers Considered positive 5 Voltage is often shown as unless specifically 10 positive
35. ng mode of the controller as it exits RESET Refer to the DSP56852 User s Manual for a complete description of the chip s operating modes Table 2 3 shows the two operation modes available on the 56852 Table 2 3 Operating Mode Selection Operating Mode 55 Comment 0 1 2 3 4 amp 5 6 Bootstrap from External byte wide memory 1 3 4 amp 5 6 Bootstrap from SPI 2 1 2 amp 5 6 Normal Expanded mode 3 5 6 Development Expanded mode 2 Debug LEDs Six on board Light Emitting Diodes LEDs are provided to allow real time debugging for user programs These LEDs will allow the programmer to monitor program execution without having to stop the program during debugging refer to Figure 2 6 Table 2 4 describes the control of each LED Table 2 4 LED Control Controlled by User LED Port Signal LED1 Port A PA2 LED2 Port C PC4 LED3 Port C PC5 LED4 Port C PC3 LED5 Port E PE1 LED6 Port E PEO Setting PA2 PC5 PC3 PEI or PEO to a Logic One value will turn on the associated LED DSP56852EVM User Manual Rev 3 2 8 Freescale Semiconductor Debug Support INVERTING BUFFER YELLOW LED AN GREEN LED AN RED KR YELLOW LED AK 4 GREEN LED VVVVVV Figure 2 6 Schematic Diagram of the Debug LED Interface 2 8 Debug Support The 56852EVM provides an on
36. on on the 56852EVM provides 5 0V DC voltage regulation for the codec s analog circuits and to the additonal voltage regulation logic on the EVM The additonal voltage regulation logic provides 1 8V DC voltage regulation for the controller s core and 3 3V DC voltage regulation for the controller s I O memory parallel interface and supporting logic refer to Figure 2 10 Power applied to the 56852EVM is indicated with a Power On LED referenced as LED7 P2 12 0V DC 5 0V Power Regulator Condition 3 3V Regulator 56852EVM PARTS 1 8V Regulator Figure 2 10 Schematic Diagram of the Power Supply Technical Summary Rev 3 Freescale Semiconductor 2 15 2 12 Stereo Codec A 16 bit audio quality stereo codec Crystal Semiconductor 54218 is connected to the 56852 s ISSI port to support audio voice and signal analysis applications The codec is clocked with a 12 288MHz oscillator This allows the codec to operate between a sample frequency of 8KHz and 48KHz The sample rate can be manually set by setting the appropriate switch positions on DIP switch S4 The sample rate selections possible using this three position DIP switch are detailed in Table 2 8 The codec supports 3 3V digital levels eliminating the need for voltage level translation circuitry Additionally a set of zero ohm resistors are
37. or Debug Support 2 8 2 Parallel JTAG Interface Connector The Parallel JTAG Interface Connector P1 allows the 56852 to communicate with a Parallel Printer Port on a Windows PC reference Figure 2 7 Using this connector the user can download programs and work with the 56852 s registers Table 2 7 shows the pin out for this connector When using the parallel JTAG interface the jumper at JG7 should be removed as shown in Table 2 6 DB 25 Connector Parallel JTAG Interface TDI IN OUT TDO OUT IN P_TRST OUT TMS OUT TCK OUT P_RESET OUT P_DE OUT JG7 Jumper Removed Enable JTAG Jumper Pin 1 2 Disable JTAG I F Figure 2 7 Block Diagram of the Parallel JTAG Interface Technical Summary Rev 3 Freescale Semiconductor 2 11 Table 2 7 Parallel JTAG Interface Connector Description P1 Pin Signal Pin Signal 1 NC 14 NC 2 PORT RESET 15 PORT IDENT 3 PORT TMS 16 NC 4 PORT TCK 17 NC 5 PORT TDI 18 GND 6 PORT TRST 19 GND 7 PORT DE 20 GND 8 PORT IDENT 21 GND 9 PORT VCC 22 GND 10 NC 23 GND 11 PORT TDO 24 GND 12 NC 25 GND 13 PORT CONNECT DSP56852EVM User Manual Rev 3 Freescale Semiconductor External Interrupts 2 9 External Interrupts Two on board push button switches are provided for external interrupt generation as shown in Fi
38. pplication Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part 2 freescale semiconductor Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners This product incorporates SuperFlash technology licensed from SST Freescale Semiconductor Inc 2005 All rights reserved DSP56827EVMUM Rev 3 07 2005
39. provided on the EVM to allow a user to disconnect the on board codec from the ISSI port and allow him to connect his own codec to the ISSI port see Figure 2 12 The on board codec has analog signal conditioning logic allowing direct connection to its line level input and line level output signals through two 1 8 stereo jacks reference Figure 2 11 Table 2 8 Codec Sample Rate Selector SW 4 SW 4 SW 4 Position 3 Position 2 Position 3 Sample Rate MF6 MF7 MF8 ON ON ON 48 00KHz ON ON OFF 32 00KHz ON OFF ON 24 00KHz ON OFF OFF 19 20KHz OFF ON ON 16 00KHz OFF ON OFF 12 00KHz OFF OFF ON 9 60KHz OFF OFF OFF 8 00KHz DSP56852EVM User Manual Rev 3 2 16 Freescale Semiconductor Stereo Codec 2 12 1 Analog Input Output The 56852EVM uses jacks for line level stereo input line level stereo output and stereo headphone output A National Semiconductor LM4880 provides the drive required for the use of headphones This device offers a THD which is superior by a factor of two to the CS4218 s on chip headphone drive circuitry The basic Analog codec connections are shown in Figure 2 11 CS4218 RIN1 LOUTL Line Level Line Level Input LIN1 LOUTR Output LM4880 Headphone Output Figure 2 11 Codec Analog Connections 2 12 2 Digital Interface The serial interface of the codec transfers digital audio data and control data into and
40. ry bus signals are connected to the Memory Daughter Card Expansion connector J1 Table 2 11 shows the port signal to pin assignments Table 2 11 Memory Daughter Card Connector Description 1 Pin Signal Pin Signal 1 A10 2 11 3 AQ 4 CS1 5 A8 6 A15 7 A7 8 A14 9 A20 10 A19 11 WR 12 A13 13 DO 14 A12 15 D1 16 D8 17 D2 18 D9 Technical Summary Rev 3 Freescale Semiconductor 2 19 Table 2 11 Memory Daughter Card Connector Description Continued 1 Pin Signal Pin Signal 19 GND 20 GND 21 D3 22 D10 23 D4 24 D11 25 D5 26 D12 27 D6 28 D13 29 A18 30 A17 31 D7 32 D14 33 cso 34 D15 35 0 36 RD 37 1 38 39 16 40 GND 41 2 42 5 43 44 4 45 19 53 46 CS2 47 3 3V 48 3 3V 49 GND 50 GND 51 5 0V DSP56852EVM User Manual Rev 3 2 20 Freescale Semiconductor 2 13 2 Peripheral Daughter Card Expansion Connector Daughter Card Connectors The controller s peripheral port signals are connected to the Peripheral Daughter Card Expansion connector J2 Table 2 12 shows the port signal to pin assignments Table 2 12 Peripheral Daughter Card Connector Description J2 Pin Signal Pin Signal 1 CS0 PA0 2 CS1 PA1 3 A20 CLKO 4 CS2 PA2 5 A17 TIOO 6 A18 TIO1 7 GND 8 GND 9 GND 10 GND 11
41. the 16 bit 56852 combined with the on board 128K x 16 bit external program data static RAM SRAM 128K x 16 bit external data program SRAM RS 232 interface stereo 16 bit codec interface Daughter Card Expansion interface and parallel interface makes the 56852EVM ideal for developing and implementing many audio and voice algorithms as well as for learning the architecture and instruction set of the 56852 processor The main features of the 56852EVM with board and schematic reference designators include 56852 16 bit 1 8V 3 3V Digital Signal Processor operating at 120MHz 01 External fast static RAM FSRAM memory configured as 128Kx16 bit of memory U2 with 1 wait state at 120MHz via CSO 128Kx16 bit of memory U3 with 1 wait state at 120MHz via CS1 CS2 M bit Serial EEPROM Data FLASH U4 4 00MHz crystal oscillator for controller frequency generation 1 Optional external oscillator frequency input connectors JG3 JG4 Joint Test Action Group port interface connector for an external debug Host Target Interface J3 On board Parallel Host Target Interface with a connector for a PC printer port cable P1 RS 232 interface for easy connection to a host processor U6 and P6 16 bit stereo codec interface U5 JG9 JG10 P3 and P4 Stereo headphone interface U12 and P5 Technical Summary Rev 3 Freescale Semiconductor 2 1 Codec sample rate sel
42. tting of MODE 4 the codec is set to be the Master of the ISSI bus with its data word set at 32 bits per frame i e 16 bits Left channel and 16 bits Right channel The sample rate is selected on the Sample Rate Selector switch S4 see Table 2 8 for selection options Codec control information is sent over a separate serial port using 5 as the Control Chip Select signal CCS PEO as the Control Data Input signal CDIN and PEI as the Control Clock signal CCLK CODEC Enable Logic CS4218 SDIN SDOUT SCLK FSYNC RESET Figure 2 12 CS4218 Stereo Audio Codec Table 2 9 SSI Port Connector Description JG9 Pin Controller Signal Pin Codec Signal 1 STXD 2 SDIN 3 SRXD 4 SDOUT 5 STCK 6 SCLK 7 STFS 8 FSYNC 9 PC4 10 RESET DSP56852EVM User Manual Rev 3 2 18 Freescale Semiconductor Table 2 10 GPIO Port Connector Description JG10 Pin Controller Signal Pin Codec Signal 1 PC5 2 CCS 3 PEO 4 CDIN 5 PE1 6 CCLK 2 13 Daughter Card Connectors The EVM board contains two daughter card expansion connectors One connector J1 contains the controller s external memory bus signals The other connector J2 contains the controller s peripheral port signals 2 13 1 Memory Daughter Card Expansion Connector Daughter Card Connectors The controller s external memo
43. y package Multi Purpose Input and Output port on Freescale s family of controllers shares package pins with other peripherals on the chip and can function as a GPIO Printed Circuit Board Phase Locked Loop Random Access Memory Read Only Memory Serial Communications Interface port on Freescale s family of controllers Preface Rev 3 Freescale Semiconductor ix SPI Serial Peripheral Interface port on Freescale s family of controllers SRAM Static Random Access Memory SSI Synchronous Serial Interface port on Freescale s family of controllers WS Wait State References The following sources were referenced to produce this manual 1 DSP56800E Reference Manual Freescale Semiconductor 2 DSP56852 Digital Signal Processor User s Manual Freescale Semiconductor 3 DSP56852 Digital Signal Processor Technical Data Freescale Semiconductor DSP56852EVM User Manual Rev 3 x Freescale Semiconductor Chapter 1 Introduction The 56852EVM is used to demonstrate the abilities of the 56852 and to provide a hardware tool allowing the development of applications that use the 56852 The 56852EVM is an evaluation module board that includes a 56852 part 16 bit stereo codec external memory and a daughter card expansion interface The daughter card expansion connectors are for signal monitoring and user feature expandability The 56852EVM is designed for the following purposes Allowing new users to become familiar with
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