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M68HC05 Applications Guide

1. Effecton 2 o otc um o Operation Description CCR 58 85 o oz HINZC lt o ROL opr DIR 39 94 5 ROLA E INH 49 3 ROLX Rotate Byte Left through Carry Bit ttt INH 59 3 ROL b7 50 IX1 69 ff 6 ROL X IX 79 5 ROR opr DIR 36 99 5 RORA 46 3 RORX Rotate Byte Right through Carry Bit gt 1 111 INH 56 3 ROR opr X b7 50 IX1 66 ff 6 ROR X IX 76 5 RSP Reset Stack Pointer SP lt 00FF INH 9 2 SP c SP 1 Pull CCR SP lt SP 1 Pull A RTI Return from Interrupt SP lt SP 1 Pull X 111111111 INH 80 9 SP c SP 1 Pull PCH SP c SP 1 Pull PCL SP lt SP 1 Pull PCH RTS Return from Subroutine SP lt SP 1 Pull PCL INH 81 6 SBC opr IMM 2 SBC opr DIR 2 dd 3 SBC opr Subtract Memory Byte and Carry Bit from eae EE EXT Cc2 hhll 4 SBC opr X Accumulator M C IX2 D2 ee ff 5 SBC E2 ff 4 SBC X IX F2 3 SEC Set Carry Bit C 1 1 INH 99 2 SEI Set Interrupt Mask 1 1 1 INH 9 2 STA opr DIR B7 dd 4 STA opr EXT C7 hhll 5 STA oprX Store Accumulator in Memory M lt A t t 1 2 D7 eeff 6 STA E7 ff 5 STA F7 4 STOP Stop Oscillator and Enable IRQ Pin 0 INH
2. 285 ROL Rotate Left thru 286 ROR Rotate Right thru 287 RSP Reset Stack 288 RTI Return from 289 RTS Return from 5 290 SBC Subtract with 291 SEC Set Carry 292 SEI Set Interrupt Mask 293 STA Store Accumulator 294 STOP Enable IRQ Stop Oscillator 295 STX Store Index Register X in 296 SUB SUPA Ch MCCC 297 SWI Software 298 TAX Transfer Accumulator to Index Register 299 TST Test for Negative or 7 300 TXA Transfer Index Register to Accumulator 301 WAIT Enable Interrupt Stop Processor 302 M68HCO5 Applications Guide Rev 4 0 234 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com A 2 Introduction Freescale Semiconductor Inc Instruction Set Details Introduction This section contains complete detailed information for all 68 05 instructions The instructions are arranged in alphabetical order with the instruction mnemonic set in larger type for easy reference T
3. Figure 3 6 M68HC05 CPU Block Diagram M68HC05 Applications Guide Rev 4 0 88 MC68HC705C8 Functional Data For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc MC68HC705C8 Functional Data Central Processor Unit 0000 9 PORT A DATA REGISTER 00 32 BYTES PORT DATA REGISTER 01 jo see mul PORT C DATA REGISTER 02 UNUSED PORT D FIXED INPUT REGISTER 03 Hs D Id PORT A DATA DIRECTION REGISTER 04 PORT DATA DIRECTION REGISTER 05 1 132 BYTES PORT DATA DIRECTION REGISTER 06 E UNUSED 07 050 y UNUSED 09 SPI CONTROL REGISTER 0A RAM SPI STATUS REGISTER 508 008F 176 BYTES SPI DATA 1 0 REGISTER 0C doco 529 SCI BAUD RATE REGISTER 500 bk SCI CONTROL REGISTER 1 0E 227 SCI CONTROL REGISTER 2 0F ad SCI STATUS REGISTER 510 50100 USER RAM SCI DATA REGISTER 11 PROM 96BYTES TIMER CONTROL REGISTER 12 96 BYTES i TIMER STATUS REGISTER 13 RAM1 0 RAM1 1 INPUT CAPTURE REGISTER HIGH 14 m adis INPUT CAPTURE REGISTER LOW 15 OUTPUT COMPARE REGISTER HIGH 16 OUTPUT COMPARE REGISTER LOW 17 TIMER COUNT REGISTER HIGH 18 TIMER COUNT REGISTER LOW 19
4. 132 3 9 4 Serial Communications Interface SCI Interrupt 132 3 9 5 Serial Peripheral Interface SPI Interrupt 132 3 10 133 DIT MONUI EL fence tesa ew he henson a dra ic Ra 133 Se QUUM Bi a ee eee 136 3 11 Serial Communications Interface SCI 136 3 11 1 SCI Transmitter a I EC 137 0 dr ee 139 141 3 11 3 1 Baud Rate Register BAUD 141 3 11 3 2 Serial Communications Control Register One 1 144 M68HCO05 Applications Guide Rev 4 0 74 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Contents 3 11 3 3 Serial Communications Control Register Two 2 144 3 11 3 4 Serial Communications Status Register 6 5 145 3 11 3 5 Serial Communications Data Register SCDAT 146 PONS picid cher 147 3 11 5 Hardware Procedures 148 3 11 6 Software 148 3 11 6 1 Initialization 148 3 11 6 2 Normal Transmit 149 3
5. eee 303 Bc 303 Review 5 304 B 4 Review Questions Answers and Explanations 318 M68HC05 Applications Guide Rev 4 0 14 Table of Contents MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Guide M68HC05 List of Figures Figure Title Page 1 1 Typical Computer 24 1 2 Temperature Control 26 1 5 Thermostat Project Block 28 21 MCU Expanded Block Diagram 81 2 2 M68HC05 CPU 5 39 2 3 Memory and LO 42 2 4 Typical Memory Map 43 2 5 Example 47 26 Flowchart and lt 48 2 7 Delay Routine Flowchart and Mnemonics 49 2 8 Explanation of Assembler Listing 51 2 9 Assembler esc xD 52 2 10 Memory of Example 56 2 11 Subroutine Call 61 2 12 Playing Computer Worksheet 64 2 13 Completed 1
6. VDD PAL PA3 PM BAS LCD DISPLAY MODULE CONTRAST F 20 CHARACTERS X 2 LINES VIEW ANGLE PA7 MC68HC705C8 PGMR BOARD KEYPAD PIEZO BEEPER VDD EE Tk 01 uF oN 1 16 E HEAT gt OPI oe 3 7 MC1413 193 2 15 FAN gt id 24VAC RETURN 3 14 MC145041 10 PDO RDI SERIAL A D PD1 TDO PD2 MISO o PD3 MOSI PD4ISCK 555 s PD7 e uuu 0 1 Figure 4 1 Thermostat Project Schematic Diagram M68HC05 Applications Guide Rev 4 0 198 Applications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Thermostat Project Details During development it was convenient to use potentiometers rather than temperature sensors because doing so allowed us to simulate temperature changes In the final application we would use an actual temperature sensor such as that shown in Figure 4 2 VpD 1 2k 324 do aM34C 1 TO A D 0 01 pF 0 1 UF ae 2 INPUT 10k 30k lt Figure 4 2 Precision Temperature Sensing Circuit The LCD display is used to show the keypad entries of time of day the temperature limits the current temperature and the selection of heating or cooling operation The keypad can be a 4x4 array or
7. 156 3123 2 22 2252 d RRER EE UE E ERR aa 156 2 1831 Serial Data Pins MISO MOSI 156 3 12 3 2 Serial Clock SOCK 157 3 12 3 3 Slave 158 FOS 158 3 12 4 1 Serial Peripheral Control Register SPCR 158 3 12 4 2 Serial Peripheral Status Register SPSR 160 3 12 4 3 Serial Peripheral Data I O Register SPDR 161 M68HCO5 Applications Guide Rev 4 0 10 Table of Contents MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents 3 13 SPI Application Example 161 3 14 Programmable 163 3 14 14 Functional Description 2266 vrnrasrcaons 166 3 14 2 Timer Counter and Alternate Counter Registers 168 3 4 3 1 169 3 14 4 Input Capture 170 3145 Output Gompare Concept 172 3 14 6 Output Compare Operation 174 3 14 7 Timer Control Register TCR 175 3 14 8 Timer Status Register TSR 175 3 14 9 Timer Application 177 3 15 STOP WAIT Instr
8. Appendix Instruction Set Details 55 5015 233 P MOE ee sn pe ee die eee ge wees 235 68 05 Instruction 1 237 ADC Add with 238 ADD Add without 239 AND Logical AND 240 ASL Arithmetic Shift 241 ASR Arithmetic Shift 242 Branch if Carry 243 BCLR n Clear Bit in 244 BCS Branch if Carry 5 245 BEQ Branch 246 BHCC Branch if Half Carry Clear 247 BHCS Branch if Half Carry Set 248 BHI Branch if 249 BHS Branch if Higher or Same 250 BIH Branch if Interrupt Pin is High 251 BIL Branch if Interrupt Pin is Low 252 BIT Bit Test Memory with Accumulator 253 BLO Branch 254 BLS Branch if Lower or 255 BMC Branch if Interrupt Mask is Clear 256 BMI Branch if MINUS CECI ER eee 257 BMS Branch if Interrupt Mask is Set 258 BNE Bra
9. 1 1 1 None affected Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Operand s Cycles Code and Cycles BMI rel REL 2B rr 3 The following table is a summary of all branch instructions Test Boolean Mnemonic Opcode Complementary Branch Comment r gt m C Z 0 BHI 22 BLS 23 Unsigned gt 0 5 24 r lt m BLO BCS 25 Unsigned r m Z 1 BEQ 27 26 Unsigned r lt m C Z 1 BLS 23 r gt m BHI 22 Unsigned r lt m C BLO BCS 25 gt 5 24 Unsigned Carry 1 BCS 25 No Carry BCC 24 Simple r 0 2 1 27 r 0 BNE 26 Simple Negative N BMI 2B Plus BPL 2A Simple Mask 1 5 2 Mask 0 BMC 2C Simple Half Carry H 1 BHCS 29 No Half Carry BHCC 28 Simple IRQ Pin High BIH 2 IRQ Low BIL 2E Simple Always BRA 20 Never BRN 21 Unconditional r register ACCA or X m memory operand M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details For More Information On This Product Go to www freescale com 257 Freescale Semiconductor Inc Instruction Set Details BMS Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Branch if Interrupt Mask is Set B MS lt PC 0002 Rel if I 1 Tests the state of the bit in the CCR and causes a branch if is set i e if interrupts are
10. 6 6 6 lt a a uia 2 did 291989 2u1988 S S 2 Hid 213589 413SH8 S S ula 2 Hid 94108 S S uia 2 Hid 91359 913SH8 S S uia 2 Hid 44108 su1 0ug S S uia 2 Hid 81458 S13SH8 S S uia e Yia 6 S S 2 did tlasa vlasya S S 2 Hid S S uia 2 Hid 13SH E 13SH8 S Hia 2 Hid S S uid 2 Hid 21458 c13SH8 S 2 6 S ula e Ya 6 1359 12668 2 Hia 04108 04109098 S S 2 Hid 01359 013SH8 9 S NES uonejndiuey dd be be ted dd M68HC05 Applications Guide Rev 4 0 Go to www freescale com MC68HC705C8 Functional Data For More Information On This Product MOTOROLA Freescale Semiconductor Inc MC68HC705C8 Functional Data 3 9 Interrupts NOTE Systems often require that normal processing be interrupted so that some external event may be serviced The MC68HC705C8 may be interrupted by one of five different methods any one of four maskable hardware interrupts IRQ SPI SCI or timer and one nonmaskable software interrupt SWI Interrupts such as timer SPI and SCI have several flags which will cause the interrupt Generally interrupt flags are located in read only status registers their equivalent en
11. G3 Freescale Semiconductor Inc Microcontroller Operation KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK Simple 68HC05 Program Read sw connected to bit 7 of port When sw closes on when port C bit 6 0 then repeat Debounc xoxo DDRB DDRC TEMPI 00A0 i INIT Port B Some pins of port C EQU 01 EQU 02 EQU 05 EQU 06 EQU S9F ORG SAO s in 705C8 RAM LDA SFF STA DDRC LDA 5 0 5 Example light LED for about 1 Sec LED wait for sw release sw 50ms on amp off CK CK Ck Ck Ck Ck CI KKK KKK KKK KKK KKK KKK KKK KKK KKK C Ck Ck KKK KKK KKK ko Ax kx x X of my board 1 closed Direct address Direct address Data direction control por Data direction control por One byte temp storage location of port 5 of port C LED tt Hgs B C Program will start at 00A0 Begin initialization Set port C to act as outputs is configured as inputs by default from reset Red amp green LEDs and beeper off Turn off red LED happen to be connected to devices which don t apply to this example program The SEO pattern turns off my stuff amp turns off red LED TOP DLYLP OFFLP DLY50 Subroutin LDA w A D en Gl D H PORTB TOP DLY50 6 PORTC 20 DLY50 LYLP
12. A8eM3 M3eR3 R3 A3 Set if there was carry from bit 3 cleared otherwise R7 Set if MSB of result is set cleared otherwise 7 R7 R6 R5 eR4 R3e eR2 R1 RO Set if all bits of the result are cleared cleared otherwise 7 7 7 R7 R7 A7 Set if there was carry from the MSB of the result cleared otherwise Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles ADD opr IMM AB 2 ADD opr DIR BB dd 3 ADD opr EXT CB hh 4 ADD X IX FB 3 ADD opr X ff 4 ADD opr X IX2 DB ee ff 5 M68HC05 Applications Guide Rev 4 0 MOTOROLA For More Information On This Product Go to www freescale com Instruction Set Details 239 Freescale Semiconductor Inc Instruction Set Details AND AND Logical AND Operation lt Description Performs the logical AND between the contents of ACCA and the contents of M and places the result in ACCA Each bit of ACCA after the operation will be the logical AND of the corresponding bits of M and of ACCA before the operation Condition Codes and Boolean Formulae R7 Set if MSB of result is set cleared otherwise 7 R7 R6 R5 R4 R3 eR2 R1 RO Set if all bits of the result are cleared cleared otherwise Source Forms Addressing Source A
13. PORTB OFFLP LY50 TOP to delay Read sw at MSB of Port B Loop till MSB 1 Neg trick Delay about 50 ms to debounce Turn on LED bit 6 to zero Decimal 20 assembles to 14 Delay 50 ms Loop counter for 20 loops 20 times 20 19 19 18 1 0 Turn LED back off Loop here till sw off Debounce releas Look for next sw closure 50ms Saves original accumulator value but X will always be zero on return DLY50 OUTLP INNRLP p OQ D TEMP 1 32 INNRLP OUTLP TEMPI Save accumulator in RAM Do outer loop 32 times X used as inner loop count O FF FF FE 1 0 256 loops 6cyc 256 1 puS cyc 1 536ms 32 315 1545 32 1 uS cyc 49 440ms Recover saved Accumulator val Return Figure 2 9 Assembler Listing M68HCO05 Applications Guide Rev 4 0 52 Microcontroller Operation MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation Programming The second line shown in Figure 2 8 is another assembler directive The mnemonic ORG which is short for originate tells the assembler where the program will start the address of the start of the first instruction following the ORG directive line ORG directives may be used more than once in a program to tell the assembler to put different parts of the program in spec
14. 100 LPAS10 1 5 100 100 5 10 10 LPAS10 ASC10 10 Save original binary value ASCII lt sp gt Tenative 100 s digit ASCII zero Tenative 10 s Tenative 1 s Get value to convert Branch if value positive ASCII minus sign Get orig value again Loop to find 10 s digit Trial addition till addition fails If 0 conversion done exit Too far back up Now between 9 amp 1 Change to positive Add to 1 s digit Update RAM location Conversion done exit Value gt 100 If less skip 100 s Put ASCII 1 in 100 s Get value again Take 100 away Increments 10 s Trial subtraction Loop till trial sub fails Too far Add back now 0 9 Add to ASCII 1 s Update RAM location RETURN from CNVERT A D Offsets to compensate sensors Analog temp OFFO OFF1 KKKKKKKKKKKKKKK FCB FCB ORG FDB 60 60 SIFFI INIT Gl A D reading Offset Offset correction for sensor 1 Offset correction for sensor 2 Reset vector address Reset vector 232 Applications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Guide M68HC05 A 1 Contents Appendix A Instruction Set Details ON ie ota tt ani 235 M68HC05 Instruction 237
15. WIET 238 ADD Add without 239 AND Logical AND 240 ASL Arithmetic Shift Lal 241 ASR Arithmetic Shift Right 242 Branch if Carry 243 BCLR n Clear 244 BCS Branch if Carry Set 245 BEQ Branch if 246 BHCC Branch if Half Carry Clear 247 BHCS Branch if Half Carry Set 248 BHI Branch if 249 BHS Branch if Higher or Same 250 BIH Branch if Interrupt Pin is High 251 BIL Branch if Interrupt Pin is Low 252 BIT Bit Test Memory with Accumulator 253 BLO Branch 254 BLS Branch if Lower or 255 BMC Branch if Interrupt Mask is Clear 256 BMI Branch if 257 BMS Branch if Interrupt Mask is 258 BNE Branch if Nor 259 BPL 1 260 BRA Branch 261 BRCLR n Branch if Bit is Clear
16. Cycles Code and Cycles BRSET 0 opr rel DIR bit 0 00 dd rr 5 BRSET 1 opr rel DIR bit 1 02 dd rr 5 BRSET 2 opr rel DIR bit 2 04 dd rr 5 BRSET 3 DIR bit 3 06 dd rr 5 BRSET 4 opr rel DIR bit 4 08 dd rr 5 BRSET 5 opr rel DIR bit 5 0A dd rr 5 BRSET 6 opr rel DIR bit 6 0 rr 5 BRSET 7 opr rel DIR bit 7 rr 5 M68HC05 Applications Guide Rev 4 0 264 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com BSET n Operation Description Condition Codes Freescale Semiconductor Inc Instruction Set Details M68HOC05 Instruction Set Set Bit in Memory BSET n Mn lt 1 Set bit n 7 6 5 0 in location M All other bits in M are unaffected can be any RAM or register address in the 0000 to 00FF area of memory i e direct addressing mode is used to specify the address of the operand and Boolean H 7 1 1 1 None affected Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Cycles Code and Cycles BSET 0 opr DIR bit 0 10 dd 5 BSET 1 opr DIR bit 1 12 dd 5 BSET 2 opr DIR bit 2 14 dd 5 BSET 3 opr DIR bit 3 16 dd 5 BSET 4 opr DIR bit 4 18 dd 5 BSET 5 opr DIR bi
17. lt Update Fan Heat and Cool outputs SEC Exit unless sec 0 or 30 DOHVAC 0 so do HVAC 30 XHVAC Exit if not 0 or 30 HVACM O off 1 2 cool 3 fan HM10 If not 0 go see if 1 PORTC Fan Heat Cool Beep ADen E RS R W SEO Set fan heat cool all high off PORTC Update port XHVAC amp Exit 1 Check for mode 1 heat HM20 If not go see if 2 5rPORTC Turn off cool output GOAL Get target temp 6 PORTC HONQ If not see if it should be Heat on turn off when indoor temp gt goal 1 Heat off 20 HCOOL Z Q D 15 HH UJ 00 U UJ Q H PAW BLS BCLR BCLR LDA STA BRA CMP BCLR BSET BSET BRA BSET LDA BRSET Goal 1 for hysteresis INTMP GOAL 1 lt INTMP Turn off XHVAC NO just leave 6 PORTC Turn off heat 7 PORTC Turn off fan HVACON Turn off flag to indicate off XHVAC Then leave turn on when indoor temp lt goal 1 Goal 1 for hysteresis INTMP GOAL 1 INTMP Turn on XHVAC NO just leave 7 PORTC Turn on fan 6 PORTC Turn on heat 1 HVACON Set flag to indicate on XHVAC Then leave 2 Check for mode 2 cool HCOOL Branch if cool mode 2 7 PORTC Turn on fan 6 PORTC Turn off heat 5 PORTC Turn off cool XHVAC Then leave 6 PORTC Turn off heat output GOAL Get target temp 5 PORTC CONQ If not see if it should be M68HC05 Applications Guide
18. 4X 4 KEYPAD Figure 4 4 Port B Summary BIT7 6 5 4 3 2 1 BIT 0 DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRCO 06 DDRC l l 1 1 1 1 1 1 1 1 INIT TO FF OUT OUT OUT OUT OUT OUT OUT OUT ALL OUTPUTS 02 PORTC PC6 PC5 PC4 PC3 PC2 1 PCO PIN NAMES REF FAN HEAT COOL BEEP A D LCD LCD LCD THERMOSTAT RELAY RELAY RELAY SEL E RS RN FUNCTION 21 22 23 24 25 26 21 28 MCU PIN NUMBER RED GREEN 6 4 5 LCD PIN NUMBER LED LED LOW TRUE SELECT TO SERIAL A D Y TRANSFER 0 QUIET 1 BEEP FOR DEVELOPMENT USE LOW TRUE TO LIGHT LEDs ON PGMR BOARD FOR FINAL SWITCH TO HIGH TRUE Figure 4 5 Port C Summary M68HCO05 Applications Guide Rev 4 0 MOTOROLA Applications 201 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications 503 PORTD 1110404 PD NO PDS PD4 02 PDI PDO PIN 55 SCK MOS miso REF 1 SPI sci ALTERNATE USE REF PULL AD AD THERMOSTAT UP SCK DOUT FUNCTION 36 34 33 32 31 30 29 MCU PIN NUMBER 33 54 S5 56 RS232 R 5232 BOARD ON OFF OFF OFF AVOID INTERFERENCE WITH THERMOSTAT APPLICATION Figure 4 6 Port D Summary After selecting major components and completing a preliminary hardware design plan and begin writing software programs You first write small
19. TURN OFF HEATING NO TURN OFF HEATING TURN ON HEATING COOLING SELECTED YES NO ca 7 YES gt Y Figure 1 2 A Temperature Control Flowchart M68HC05 Applications Guide Rev 4 0 26 General Description MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description Project Description Some applications have costly sensors and control mechanisms The cost of the sensors required for input and the cost of the control devices required for output are usually much greater than the cost of a standard MCU The advantage of an MCU system is the use of software to replace complex and expensive hardware previously required The cost of the software is a tradeoff against the cost of the additional hardware and the space it requires Programming allows use of complex functions that could not easily be accomplished with hard wired devices Changes in functions can be made and programs can be improved or replaced with few or no hardware changes 1 7 Project Description A basic thermostat controller was chosen for this project because it should be familiar to all readers and because it includes the fundamental elements common to all MCU applications Figure 1 3 illustrates a home thermostat controller that can control both heating and air conditioning Since the thermostat is based on an MCU complex functions can be added
20. Update OCMP hi 036a b6 al LDA TEMP Get previous saved OCMP low 036c b7 17 STA OCMPLO Update OCMP 10 after OCMP hi Ck CK ck Ck Ck CK Ck Ck CK C Ck CC Ck CK C Ck Ck C Ck Ck CK C Ck Ck Ck Ck CK Ck Ck CK SC Ck CK Ck Ck CK Sk Ck Ck CK Ck Ck CK Sk Ck Ck CK Ck Ck Ck Ck Ck SK Ck Ck Ck kk Ck Ck Sk Sk Pk kA kx You add low half first due to possible carry then add high byte including any carry ADC You should update out compare high byte first to avoid an erroneous compare value compare lockout 2 after till OCMPLO prevents this potential problem m CK Ck Ck CK CC CC C CK C Ck C CC Ck CK C C CC Ck Ck Ck CK Ck Ck CK Ck Ck CK Ck Ck CK Sk Ck Ck CK Ck Ck Ck Sk Ck Ck Ck Ck Ck Ck kk Ck Pk Sk Sk Pk ko Sk Kk ko xo 036e Oc 13 fd LOOP BRCLR 6 TSR LOOP Checks for out comp flag 0371 b6 17 LDA OCMPLO To clear OCF flag 0373 3a a0 EC TENSEC Ten seconds count down 0375 26 7 LOOP Loop until 10 sec done 0375 20 db BRA BEGIN Repeat so PC6 toggles 10 Sec Figure 3 49 Timer Application Example Program M68HC05 Applications Guide Rev 4 0 178 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data STOP WAIT Instruction Effects STOP OSCILLATOR OSCILLATOR ACTIVE AND ALL CLOCKS TIMER SCI AND SPI SET I BIT CLOCKS ACTIVE IN CC REGISTER CPU CLOCKS STOPPED EXT EXT
21. Which of the four programs requires the fewest bytes of program memory A 10 gt B PROG2 6 PROM 9 D 8 Which of the four programs produces the shortest pulse width logic one at the pin A PROG 6 O B PROG2 5 gt C PROM 4 O D PROG4 12 Which of the four programs produces the longest period A PROG1 15 PROG2 13 11 gt D PROG4 24 Notice the loop executes twice to make a single period M68HC05 Applications Guide Rev 4 0 332 Review Questions MOTOROLA For More Information On This Product Go to www freescale com 36 37 38 Freescale Semiconductor Inc Review Questions Review Questions Answers and Explanations Sometimes it is important to change the level on a pin without disturbing values in the CPU accumulator and other CPU registers Which of the four programs uses no CPU registers other than the program counter PC PROG1 uses gt B 2 BSET and BCLR use CPU registers uses and D PROG4 uses Which of the four programs produces a square wave equal high and low times A 1 6 9 O B PROG2 5 8 PROM 4 7 gt D PROG4 12 12 Some instructions affect only a single bit in memory location whereas others affect all bits in a memory location Which of the four programs do
22. Xen e 1 LSB KX lls do Edad ur i Figure 3 36 Data Clock Timing Diagram 3 12 3 2 Serial Clock 5 SCK is used to synchronize the movement of data both in and out of the device through the MOSI and MISO pins The SCK pin is an output when the SPI is configured as a master and an input when the SPI is configured as a slave When the SPI is configured as a master the SCK signal is derived from the internal MCU bus clock When the master initiates a transfer eight clock cycles are automatically generated on the SCK pin In both the master and slave SPI devices data is shifted on one edge of the SCK signal and sampled on the opposite edge where data is stable Two bits SPRO SPR1 in the SPCR location 0A of the master device select the clock rate Both master and slave devices must be programmed to similar timing modes for proper data transfers as controlled by the CPOL and CPHA bits in the SPCR M68HCO05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 157 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8 705 8 Functional Data 3 12 3 3 Slave Select SS The SS pin behaves differently on master devices than on slave devices On a slave this pin is used to enable the SPI slave for a transfer On a master the SS pin is normally pulled high externally 3 12 4 Reg
23. Watchdog Timer 97 3 6 4 3 Clock Monitor 99 3 7 Addressing 554 ea bo eh 99 3 7 1 Inherent Addressing 101 3 7 2 Immediate Addressing Mode 103 Sd Extended Addressing 104 3 7 4 Direct Addressing 105 3 7 5 Indexed Addressing Modes 108 3 7 5 1 indexed No 1 108 3 7 9 2 Indexed 8 110 3 7 5 3 Indexed 16 Bit Offset 112 3 7 6 Relative Addressing MS 27 4 Bit Test and Branch Instructions 115 3 7 8 Instructions Organized by 115 Instruction Set Summary 119 o9 WMG SNE dn 128 LEON Software Interrupt 129 3 9 2 External Interrupt 131 M68HCO5 Applications Guide Rev 4 0 MOTOROLA Table of Contents 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 3 9 3 Timer 1 0 T 22 212 5 7 01275572 132 3 9 4 Serial Communications Interface 5 Interrupt 132 3 9 5 Ser
24. ckok ck ckok A kokck Keypad Correspondance Table 1st entry of each pair is Row Col bit pattern 2nd entry of each pair is ASCII equiv of key COL gt 1234 5 This is layout of keypad ROW l gt 223 A ROW 2 45 6B ROW 3 gt 7 8 9 ROW 4 gt lt 0 gt Port layout is R4 R3 R2 R1 2 3 4 R s ins C s outs 0600 18 31 KYTBL FCB 618 71 Row 1 Col 1 Top Left 0602 28 34 FCB 28 4 Row 2 Col 1 0604 48 37 FCB 48 7 Row 3 Col 1 0606 88 3c FCB 88 Row 4 Col 1 0608 14 32 FCB 14 2 Row 1 Col 2 060a 24 35 FCB 24 5 Row 2 1 2 060c 44 38 FCB 44 8 Row 3 1 2 060e 84 30 FCB 84 0 Row 4 1 2 0610 12 33 FCB 52207 3 1 1 3 0612 22 36 9225 66 Row 2 Col 3 0614 42 39 FCB 542579 3 1 3 0616 82 3e FCB 82 Row 4 Col 3 0618 11 41 FCB 11 A Row 1 Col 4 061a 21 42 FCB 2 1 4 061 41 43 3 1 4 061 81 21 281 4 Row 4 Col 4 Bot Right M68HC05 Applications Guide Rev 4 0 MOTOROLA Applications 229 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Listing Thermostat Example Sheet 19 of 21 Ck CK ck Ck Ck CK Ck Ck CK CC C CK Ck Ck CK Ck C CK Ck Ck CK CC CC Ck Ck CK Ck Ck CK Ck CK Ck Ck CK Sk Ck Ck Kk Ck Ck kk Ck Kk Sk Sk Pk Sk WCTRL Write control w
25. ia 80 3 4 1 Pin FONCIONS de ROS 81 3 4 1 1 Migs i hu 81 3 4 1 2 81 3 4 1 3 IRQ Maskable Interrupt 82 3 4 1 4 ie dees 82 3 4 1 5 oa Qd dedo RE XO OE T 82 3 4 1 6 jr 83 3 4 1 7 Oe dpa xa ded wes 83 3 4 1 8 af EUR ORE dd 83 3 4 1 9 C Cad re aote dd dob Kei Fd ACORDE 83 DOLI POPOD kads wa we gri 55455555 c a qd wid 85 3 4 1 11 PD5S PDO and PDT ig tic cece hide dye eee ee 85 3 4 2 Typical Basic 5 85 3 5 87 3 5 1 Bm TYPES La diced d dp 87 3 5 2 Memory Map Sek de ee Seles 88 36 555555584 aa 88 3 6 1 ic o 90 3 6 1 1 90 3 6 1 2 Index 91 3 6 1 3 Condition Code Register 91 3 6 1 4 Padam COUME La ee EX RR OE Ra ROGER Ra 93 3 5 1 5 Stack POMEL aaa quor SCORE doe dub dor or RR e ede de 94 M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 73 For More Information On This Product Go to www freescale com Fr
26. 0001 Advance to return address 4 PCL SP lt SP 0001 Push low order return address onto stack SP lt SP 0001 Push high order return address onto stack X SP lt SP 0001 Push index register onto stack ACCA SP lt SP 0001 Push accumulator onto stack SP lt SP 0001 Push CCR onto stack bit 1 PCH xFFC Vector fetch x 1 or 3 depending on PCL xFFD M68HC05 device The program counter is incremented by one The program counter index register and accumulator are pushed onto the stack The CCR bits are then pushed onto the stack with bits Z and C going into bit positions 4 0 and bit positions 7 6 and 5 containing ones The stack pointer is decremented by one after each byte of data is stored on the stack The interrupt mask bit is then set The program counter is then loaded with the address stored in the SWI vector located at memory locations n 0002 and n 0003 where n is the address corresponding to a high state on all lines of the address bus The address of the SWI vector can be expressed as xFFC xFFD where x is 1 or 3 depending on the M68HC05 device being used This instruction is not maskable by the bit H 2 1 1 1 1 E 14 Set Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Operand
27. 2 1 1 REL 20 3 DIR 60 01 5 DIR 61 03 rr 5 DIR 62 05 dd rr 5 EE DIR 63 07 rr 5 e en BRCLR n opr rel Branch if Bit n Clear lt 2 rel 0 1 DIR b4 09 dd rr 5 DIR 65 dd rr 5 DIR 66 OD dd rr 5 DIR 67 OF dd rr 5 BRN Branch Never PC lt PO 2 rel 1 0 REL 21 3 DIR 60 00 dd rr 5 DIR 61 02 dd rr 5 DIR 62 04 5 DIR 63 06 dd rr 5 IE BRSET n opr rel Branch if Bit n Set PC lt 2 rel Mn 1 1 DIR b4 08 dd rr 5 DIR 65 dd rr 5 DIR 66 0 dd rr 5 DIR 67 OE dd rr 5 DIR b0 10 dd 5 DIR b1 12 dd 5 DIR b2 14 dd 5 03 16 dd 5 BSET n opr Set Bit n Mn lt 1 DIR 64 18 dd 5 DIR 65 1A dd 5 DIR b6 1 dd 5 DIR b7 1E dd 5 PC lt PC 2 push PCL SP lt SP 1 push PCH BSR rel Branch to Subroutine SP SP 1 REL rr 6 lt PC M68HC05 Applications Guide Rev 4 0 122 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Instruction Set Summary Table 3 6 Instruction Set Summary Sheet 3 of 6 Effecton
28. 167 3 44 16 Bit Counter Reads 168 3 45 Input Capture Operation 171 3 46 Output Compare 172 3 47 Timer Control 5 175 M68HCO05 Applications Guide Rev 4 0 16 List of Figures MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Figures Figure Title Page 3 48 Timer Status 176 3 49 Timer Application Example 178 3 50 179 3 61 2 5454 ee CR OR RR 183 3 52 Option 5 184 4 1 Thermostat Project Schematic Diagram 198 4 2 Precision Temperature Sensing 199 4 3 POA oso 200 4 4 EDU S SUNNY 201 4 5 Pot O SUMMAY 201 4 6 202 4 7 Display Checkout 204 4 8 Display Checkout Program 5 205 4 9 Keypad Checkout 208 4 10 Keypad Checkout Program Listing 209 4 11 Main Program 211 M68HCO5 Applications Guide
29. 2 LDX opr DIR BE dd 3 LDX opr EXT cE hhll 4 LDX opr X Load Index Register with Memory Byte X lt 1 1 x2 pElee ffl 5 LDX opr X IX1 ff 4 LDX X IX FE 3 LSL opr DIR 38 99 5 LSLA tt INH 48 3 LSLX Logical Shift Left Same as ASL Ch o ttt INH 58 3 LSL opr X b7 50 IX1 68 ff 6 LSL X IX 78 5 LSR opr DIR 34 99 5 LSRA INH 44 3 LSRX Logical Shift Right 0 0 242 54 3 LSR opr X b7 50 IX1 64 ff 6 LSR X IX 74 5 MUL Unsigned Multiply X A lt X x A 0 0 INH 42 11 NEG opr M lt M 00 M DIR 30 99 5 NEGA A lt A 00 INH 40 3 NEGX Negate Byte Two s Complement X lt X 00 X 1 111 50 3 NEG opr X M lt M 00 M 1 60 ff 6 NEG X M lt M 00 M IX 70 5 NOP No Operation INH 190 2 opr 2 ORA opr DIR dd 3 ORA opr EXT CA hhll 4 ORA opr X Logical OR Accumulator with Memory A lt v 2 1 IX2 5 ORA IX1 EA ff 4 ORA IX FA 3 M68HCO05 Applications Guide Rev 4 0 124 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Instruction Set Summary Table 3 6 Instruction Set Summary Sheet 5 of 6
30. 1 1 1 None affected Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Operand s Cycles Code and Cycles BEQ rel REL 27 rr 3 The following table is a summary of all branch instructions Test Boolean Mnemonic Opcode Complementary Branch Comment r gt m C Z 0 BHI 22 BLS 23 Unsigned 0 BHS BCC 24 rm BLO BCS 25 Unsigned r m Z 1 BEQ 27 26 Unsigned lt C Z 1 BLS 23 r gt m BHI 22 Unsigned r lt m C 1 BLO BCS 25 BHS BCC 24 Unsigned Carry 1 BCS 25 No Carry BCC 24 Simple r 0 2 1 27 r 0 BNE 26 Simple Negative N 1 BMI 2B Plus BPL 2A Simple Mask 1 5 2D Mask 0 BMC 2 Half Carry H 1 BHCS 29 No Half Carry BHCC 28 Simple IRQ Pin High BIH 2F IRQ Low BIL 2E Simple Always BRA 20 Never BRN 21 Unconditional r register ACCA or X m memory operand M68HCO5 Applications Guide Rev 4 0 246 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc Instruction Set Details M68HC05 Instruction Set Branch if Half Carry Clear BHCC PC lt PC 0002 Rel if H 0 Tests the state of t
31. 26 Unsigned r lt m C Z 1 BLS 23 r gt m BHI 22 Unsigned rm C 1 BLO BCS 25 BHS BCC 24 Unsigned Carry 1 BCS 25 No Carry BCC 24 Simple r 0 2 1 27 r 0 BNE 26 Simple Negative N 1 BMI 2B Plus BPL 2A Simple Mask 1 5 2D Mask 0 BMC 2 Half Carry H 1 BHCS 29 No Half Carry BHCC 28 Simple IRQ Pin High BIH 2F IRQ Low BIL 2E Simple Always BRA 20 Never BRN 21 Unconditional r register ACCA or X m memory operand M68HC05 Applications Guide Rev 4 0 252 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc Bit Test Memory with Accumulator e Instruction Set Details M68HC05 Instruction Set BIT Performs the logical AND comparison of the contents of ACCA and the contents of M and modifies the condition codes accordingly Neither the contents of ACCA or M are altered Each bit of the result of the AND would be the logical AND of the corresponding bits of ACCA and M R7 Set if MSB of result is set cleared otherwise 7 R7 R6 R5 R4 R3 eR2 R1 Set if result is 00 cleared otherwise Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s
32. BHS BCC 24 Unsigned Carry 1 BCS 25 No Carry BCC 24 Simple r 0 2 1 27 r 0 BNE 26 Simple Negative N 1 BMI 2B Plus BPL 2A Simple Mask 1 5 2D Mask 0 BMC 2 Half Carry H 1 BHCS 29 No Half Carry BHCC 28 Simple IRQ Pin High BIH 2F IRQ Low BIL 2E Simple Always BRA 20 Never BRN 21 Unconditional r register ACCA or X m memory operand M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details 251 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Details BIL Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Branch if Interrupt Pin is Low L PC lt PC 0002 Rel if IRQ 0 Tests the state of the external interrupt pin and causes a branch if the pin is low See BRA instruction for further details of the execution of the branch H 7 1 1 1 None affected Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles BIL rel REL 2E rr 3 The following table is a summary of all branch instructions Test Boolean Mnemonic Opcode Complementary Branch Comment C Z 0 BHI 22 BLS 23 Unsigned 0 BHS BCC 24 rm BLO BCS 25 Unsigned r m Z 1 BEQ 27
33. v 6 5 Ad v dq EE XLS UI X 8401S 9 Za S 2 2 S 6 29 24 VIS AOW S V 8101S 9 5 v r4 5 v 5 2 2 2 X peo 6 6 9d v 2 93 94 v 99 9g val Aoway peo So o 2 sei g sejo 29 s g 2 1 sejo 9 sei g 8 2 sa Ag 591245 s g woul 4 do do do do do do 1 5 18 91 5 0 18 8 50 ON sopow suononaijsu 51 o qer MOTOROLA MC68HC705C8 Functional Data For More Information On This Product M68HCO05 Applications Guide Rev 4 0 116 Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Addressing Modes uomneuuojJur 19 7 6 9 qe BuisseJppe ap esn 11546 pue u128 19 10 3 LON 9 5 1389 195 118 9 ees 419g 129 0 11g LL L ev TNN Adin 9 ag v v 2 151 T 1 79
34. 02 LDA 502 0117 01 93 JSR WCTRL Home 011 38 LDA 538 011 01 93 JSR WCTRL Function Set 8 bit 2 line 5X7 011 Oc LDA 50 0121 01 93 JSR WCTRL Display on Cursor off 0124 06 LDA 506 0126 01 93 JSR WCTRL Entry mode Inc addr no shift END INITIALIZATION Figure 4 10 Keypad Checkout Program Listing Sheet 1 of 2 M68HC05 Applications Guide Rev 4 0 MOTOROLA Applications 209 For More Information On This Product Go to www freescale com 0129 0125 012d 012 0131 0133 0136 0138 0135 013 013 0141 0142 0143 0145 0147 014 014 014 0151 0153 0156 0158 015 015 015 0160 0163 0173 0175 0177 0179 017b 017d 017f 0181 0183 0185 0187 0189 018b 018d 018f 0191 M68HC05 Applications Guide Rev 4 0 a6 b7 b6 a4 27 d6 b7 bl 27 5a 5a 2a 20 b7 a6 cd b6 cd a6 b7 b6 a4 26 cd 20 18 28 48 88 24 44 84 12 22 42 82 11 21 41 81 Of 01 01 0 fa 01 le 01 01 01 06 2 01 9d 80 01 9 01 Of 01 01 0 fa 01 4 31 34 33 3c 32 35 38 30 33 36 39 41 42 43 21 65 73 74 FOUND 23 ad TILRLS 65 Freescale Semiconductor Inc Applications Turn all cols Reads rows in upper 4 Loo
35. 175 3 14 9 Timer Application 177 415 STOP WAIT Instruction Effects 177 3 15 1 Low Power Consumption 177 3 15 2 Effects On Chip Peripherals 180 M68HCO05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 75 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8 705 8 Functional Data 3 2 Introduction 2192 1 Timer Action During Stop 180 3 15 2 2 5 Action During Stop Mode 180 2158 3 3 SPI Action During Stop Mode 181 315 24 Wait Mode 181 3 16 OTPROM EPROM Prearamming uisus acer 182 182 pps Dog 182 3 16 3 Program 5 183 3 164 Option la 184 MC68HC705C8 microcontroller MCU is a member of the M68HC05 Family of low cost single chip microcontrollers The HCMOS technology used on the MC68HC705C8 combines smaller size and higher speeds with the low power and high noise immunity of CMOS An additional advantage of CMOS is that circuitry is fully static CMOS microcontrollers may be operated at any clock rate less than the guaranteed maximum This feature may be used to co
36. 8 ff 4 EOR IX F8 3 INC opr M lt M 1 DIR 94 5 lt A 1 INH 3 INCX Increment Byte X lt X 1 1 111 INH 5 3 INC oprX lt 1 1 6 6 M lt 1 IX 7 5 M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 123 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Table 3 6 Instruction Set Summary Sheet 4 of 6 Effecton 2 o otc 5 2 Operation Description CCR 58 85 9 Ge 2 HINZC lt o JMP opr DIR BC dd 2 JMP opr EXT 3 JMP opr X Unconditional Jump PC lt Jump Address x DC ee ff 4 JMP opr X IX1 EC ff 3 JMP X IX 2 dd opr PC n n 1 2 or 3 EL boven 2 JSR opr EXT CD hhll 6 Push PCL SP SP 1 JSR opr X Jump to Subroutine 1X2 DD ee 8 7 Push PCH SP lt 5 1 lt Effective Address E ED ff 6 JSR X IX FD 5 LDA opr IMM 2 LDA opr DIR Be dd 3 LDA opr _ EXT 6 hh Il 4 LDA opr X Load Accumulator with Memory Byte lt 112 2 De lee ff 5 LDA IXi Ee ff 4 LDA X 3 LDX opr IMM
37. Review Questions Review Questions Answers and Explanations 14 What frequency crystal would be used an MC68HC705C8 to get a 500 ns internal processor clock O A 1 0 MHz O B 2 0 MHz gt 4 0 MHz see 3 4 1 7 OSC1 and OSC2 or Figure 3 24 Rate Generator Division D 8 0 MHz 15 For an MC68HC705C8 with a 4 0 MHz crystal what amount of time corresponds to a single count of the 16 bit timer A 500 ns O B 1 0 us gt C 2 0 us see Figure 3 43 Programmable Timer Block Diagram and 3 14 2 Timer Counter and Alternate Counter Registers O D 4 0 us 16 Foran MC68HC705C8 with a 4 0 MHz crystal what is the fastest baud rate available for the SCI UART type serial interface O A 131 072 kbaud gt 125 kbaud see top entry in 4 0 column of Table 3 10 Prescaler Baud Rate Frequency Output O C 19 2 kbaud O D 9600 baud 17 Foran MC68HC705C8 with a 4 0 MHz crystal what is the fastest master mode bit rate available for the SPI synchronous serial peripheral interface gt 1 Mbit sec see table in 3 12 4 1 Serial Peripheral Control Register SPCR O B 500 kbits sec O C 250 kbits sec O D 125 kbits sec Only a master SPI device produces a serial clock As a slave the fastest bit rate the SPI can accept would be the crystal frequency divided by 2 or 2 MHz for a 4 MHz crystal M68HC05 Applications Guide Rev 4 0 MOTOROLA Review Questions 323 For More Information On This
38. You begin the process by preparing a worksheet like that shown in Figure 2 12 This sheet includes the mnemonic program and the machine code that it assembles to You could alternately choose to use a listing positioned next to the worksheet The worksheet also includes the CPU register names across the top of the sheet with ample room below to write new values as the registers change in the course of the program STACK CONDITION INDEX PROGRAM POINTER ACCUMULATOR CODES REGISTER COUNTER 111HINZC LDA 02 LOAD IMMEDIATE VALUE JSR SUBBY STA DECREMENT ACCUMULATOR SUBBY LOOP TILL ACCUMULATOR Figure 2 12 Playing Computer Worksheet M68HCO5 Applications Guide Rev 4 0 64 Microcontroller Operation MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation CPU Operation On this worksheet there is an area for keeping track of the stack After you become comfortable with how the stack works you would probably leave this section off but it will be instructive to leave it here for now As a value is saved on the stack you will cross out any prior value and write the new value to its right in a horizontal row You must also update decrement the SP value by crossing out any prior value and writing the new value beneath it under the SP heading at the top of the worksheet As avalue is recovered from the stack you would update increment t
39. 66 3 1 MC68HC705C8 Microcontroller Block Diagram 79 3 2 40 Dual In Line Package Pin Assignments 80 3 3 44 Lead PLCC Package Pin Assignments 81 3 4 Oscillator 84 3 5 Basic ConrneclloliS uad coo ODORE REOR 86 3 6 M68HC05 CPU Block Diagram 88 3 7 MC68HC705C8 Memory Map 89 3 8 Programming 90 3 4 Accumulator 90 3 10 Index Register X iua acd paci eR o CORR OC ER CR Re diee 91 3 11 Condition Code Register CCR 91 M68HC05 Applications Guide Rev 4 0 MOTOROLA List of Figures 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Figures Figure Title Page Program Counter PG ok 93 S13 Bk pee eee 94 3 14 Hardware Interrupt Flowchart 130 3 15 Interrupt Stacking 1897 3 16 Port A and Data Direction A Registers 134 3 17 B and Data Direction Registers 134 3 18 Port C and Data Direction C Registers 134 3 19 Parallel Port I O 135 3 20 Port D Fixed Input POM mrs ue RR 136 3
40. ALT COUNT REGISTER HIGH 1A ALT COUNT REGISTER LOW 1B 7680 BYTES EPROM PROGRAM REGISTER COP RESET REGISTER 1D COP CONTROL REGISTER 1E UNUSED 1F 1EFF 1F00 BOOT ROM 223 BYTES 1FDE 0 SPIVECTOR HIGH 1FF4 SIDE OPTION REGISTER SPI VECTOR LOW 1FF5 MSN SCI VECTOR HIGH 1FF6 51 0 SCI VECTOR LOW 1FF7 LOIN TIMER VECTOR HIGH 1FF8 16BYTES TIMER VECTOR LOW 1FF9 1FEF IRQ VECTOR HIGH 1FFA IRQ VECTOR LOW 1FFB 1FF3 CNUSED 4 BNTES SWI VECTOR HIGH 1FFC 1FF4 USER PROM SWI VECTOR LOW 1FFD VECTORS RESET VECTOR HIGH BYTE 1FFE 1FFF 12 BYTES RESET VECTOR LOW BYTE 1FFF Refer to 3 16 4 Option Register for an explanation of software selectable memory configurations Figure 3 7 MC68HC705C8 Memory Map M68HCO05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 89 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8 705 8 Functional Data 3 6 1 Registers The CPU contains five registers as shown in Figure 3 8 Registers in the CPU are memories inside the microprocessor not part of the memory map 7 0 ACCUMULATOR A INDEX REGISTER X 12 7 5 0 0101 01070 111 STACK POINTER SP 15 12 0 010 0 PROGRAM COUNTER PC 7 4 3 2 1 0 CONDITION CODE REGISTER 111 1 H N Z cc a ZERO NEGATIVE INTERRUPT MASK
41. ASL ROL ASL ROL BOT 4 11110011 Initial value SAO For 00AO 4510000001 Initial value SA1 For 00 1 SA1 Comment left off SAO intentionally SA1 SAO NOP O A 00A00 00A1 11110011 10000001 O B 00A00 00A1 11001100 00000100 00A00 00A1 11001110 00000111 gt D 00A00 00A1 11001110 00000100 See ASL and ROL instruction definitions in Appendix A Instruction Set Details Play computer to see how this sequence works This is a 16 bit version of the multibyte shift sequence described in the ROL instruction description Refer to the following four program listings to answer questions 33 through 38 These programs demonstrate four different ways to generate pulses at port A bit 0 of an MC68HC705C8 All four programs assume that port A has been configured as outputs by the data direction register DDRA equal FF 0100 0102 0104 0106 0108 b7 b7 20 01 00 00 00 6 PROCESSOR CLOCK INT M68HCO5 Applications Guide Rev 4 0 PAO PIN PROGI LDA 01 PROG1 LDA STA LDA STA BRA 01 00 500 500 PROG1 2 Pattern for bit 0 high 4 Write to port A 2 Pattern for bit 0 low 4 Write to port A 3 Repeat loop continuously STA 00 STA 00 BRA STA 500 500 lt PULSE HIGH 6 PROGI 01 PERIOD 15 _______ gt 330 Go to www freescale com Review Questions For More Information On This Produ
42. Four I O pins located at port D are associated with SPI data transfers They are the serial clock SCK PD4 the master in slave out MISO PD2 data line the master out slave in MOSI PD3 data line and the active low slave select SS PD5 When the SPI system is not utilized the four pins SS SCK MISO and MOSI are configured as general purpose inputs PD5 PD4 PD3 and PD2 In a master configuration the master start logic receives an input from the CPU in the form of a write to the SPI data register and originates the serial clock SCK based on the internal processor clock This clock is also used internally to control the state controller as well as the 8 bit shift register Data is parallel loaded into the 8 bit shift register during the CPU write to SPDR and then shifted out serially to the MOSI pin for application to the serial input line of the slave device s At the same time data is applied serially from a slave device through the MISO pin to the 8 bit shift register After the eighth shift in a transfer data is parallel transferred to the read buffer where it is available to the internal data bus during a CPU read cycle The SPIF status flag is used by the master and slave devices to indicate when a transfer is complete 3 12 3 Pin Descriptions The four pins are discussed in the following paragraphs 3 12 3 1 Serial Data Pins MISO MOSI The master in slave out MISO and master out slave in MOSI data pi
43. N HNI VXL 2 e 2 HNI usa dON 9 2 HNI dSH 2 2 HNI 19 2 2 HNI 2 2 HNI 93 2 HNI 2 HNI XYL 2 N E 2a N N B N N a LXI 419 9 LXI 161 S LXI 9 9 9 S 9 XI 161 16 161 16 S 9 S XI LXI 2 HNI HNI usv usv Xusv vusv usv S 9 XLSL HNI XONI 6 HNI 6 HNI X108 6 HNI XISVX SV HNI x419 HNI HNI 1 80 419 6 S 2 Hd 2 VISL 151 v HN Hd 2 VONI ONI 5 HNI voaa 9 jou 9 HNI 6 HNI VISWISV 6 uia 161 16 2 HNI HNI Ys 951 51 vas 951 S 9 S LXI HNI HNI WOO XINOO VINOO WOO 9 6 6 S 9 2 HNI uou Yoy VHOH S 9 S HNI LL HNI XSAN 6 HNI VON dew epoodo eiqer SAN S 6 6 og nS a gt og tn I em I em 6 6 019 599 6 6 519 6
44. 01 LDA 1 Olac b7 STA HR HR 1 Olae 20 18 BRA Exit 01b0 al ARNS1 CMP 12 HR 12 Olb2 26 14 BNE XTIME If not just exit 0104 b6 LDA AMPM 0156 a8 01 EOR 00000001 Invert Am Pm bit 01b8 b7 a8 STA AMPM 0 AM 1 PM Olba 26 Oc BNE XTIME If not AM now just exit Olbc 3c a9 INC DAY DAY DAY 1 01 b6 a9 LDA DAY 01 0 al 08 CMP 8 Day rollover Olc2 26 04 BNE XTIME If not just exit 01 4 01 LDA 1 01c6 7 a9 STA DAY Set Day to 1 SUN 01c8 81 XTIME RTS RETURN from TIME M68HC05 Applications Guide Rev 4 0 MOTOROLA Applications 217 For More Information On This Product Go to www freescale com Listing Thermostat Example 01c9 01c9 Olcb Olcd Oct 0141 0143 0145 01 7 01 9 Oldd Oldf Olel 01e4 01e6 01e8 Olea Oleb Olec Olee 01 0 01f3 01f5 01f7 01f9 Olfb 01 Olff 0201 0203 0205 0207 0209 0205 020 0208 0211 0213 0215 M68HC05 Applications Guide Rev 4 0 b6 26 a6 b6 a4 27 20 1 26 d6 by b1 27 5a 5a 2a b7 a6 b7 20 al 26 a6 b7 b6 a4 26 a6 b7 20 al 26 ot 81 b3 Oe Of 01 01 0 3e b3 3a 01 le 06 01 01 06 b3 06 b3 02 b4 la fe 10 Of 01 01 0 Oc b3 06 02 b3 Freescale Semiconductor Inc Applications Sheet 7 of 21 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK KKK ko ko KK KYPAD Check for amp deco
45. 1 Heat 2 1 3 Fan Only 00ab GOAL RMB 1 Goal temp setting End of values accessed by offset from ENTRY 00ac INTMP RMB 1 Current Indoor Temperature 00ad OUTMP RMB 1 Current Outdoor Temperatur 00ae ASC100 RMB 1 ASCII hundreds digit lt sp gt 1 or 2 00af ASC10 RMB 1 ASCII tens digit 0 thru 9 0050 5 1 RMB 1 ASCII ones digit 0 thru 9 0051 MODE RMB 2 Current Mode for user interfce Modes 0 Inactive display shows current time temp etc 1 Set Time HR 2 Set Time MIN 3 Set Time AM PM 4 Set Time DAY 5 Set HVAC Mode Off Heat Cool Fan Only 6 Set Target Temperatur 0052 RMB 1 0 off 1 on running now 00b3 KEYVAL RMB 1 Keypad key ASCII or debounce stat 0054 RMB 1 Beeper request 2 gt single 100mS beep 8 gt double beep 26 gt 1 sec beep 0055 ACTIMR RMB 1 Activity timer Set 60 sec on key decrement 1 sec if 0 mode reverts to 0 0056 ENTFLG RMB 1 New entry flag 0 1 1 Entries default to current value when new If user enters a single digit the tens digit is cleared If user enters more digits they shift in from rt so new digit is 1 s old 1 s becomes 10 s and old 10 s falls off left lost M68HC05 Applications Guide Rev 4 0 MOTOROLA Applications 2138 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Listing Thermostat Example Sheet 3 of 21 0100 ORG 0100
46. 1FF9 All interrupt flags have corresponding enable bits ICIE OCIE and TOIE in the timer control register TCR location 12 Reset clears all enable bits thus preventing an interrupt from occurring during the reset time period The actual processor interrupt is generated only if the bit in the condition code register is also cleared The general sequence for clearing an interrupt is a software sequence of accessing the status register while the flag is set followed by a read or write of the associated control register 3 9 4 Serial Communications Interface SCI Interrupt An interrupt in the SCI occurs when one of the interrupt flag bits in the serial communications status register is set provided the bit in the condition code register is clear and the enable bit in the serial communication control register 2 location 0F is enabled Software in the serial interrupt service routine must determine the priority and cause of the SCI interrupt by examining the interrupt flags and the status bits located in the serial communications status register location 10 The general sequence for clearing an interrupt is a software sequence of accessing the status register while the flag is set followed by a read or write of the associated control register 3 9 5 Serial Peripheral Interface SPI Interrupt An interrupt in the occurs when one of the interrupt flag bits in the serial peripheral status register location 0B is set p
47. 3 16 4 Option Register The option register see Figure 3 52 is used to select memory RAM ROM configurations enable PROM security and select the MCU IRQ pin sensitivity BIT 7 6 5 4 3 2 1 BIT 0 0 0 0 0 PROM MOTOROLA 1 0 RESET CONDITION L SELECT IRQ SENSITIVITY 1 EDGE amp LEVEL 0 EDGE ONLY MOTOROLA USE ONLY 1 OR 0 L EPROM SECURITY BIT IMPLEMENTED IN EPROM OTPROM L SELECT MEMORY TYPE IN 0100 015F AREA 0 96 BYTES PROM 1 96BYTES RAM SELECT MEMORY TYPE IN 0020 004F AREA 0 48 BYTES PROM 1 32 BYTES RAM Figure 3 52 Option Register RAMO The bit determines the amount and type of memory in the 0020 005F area 0 48 bytes of PROM 0020 005F 1 32 bytes of RAM 0030 005F When is selected by 1 the 16 bytes from 0020 002F are unused This bit is readable and writable at all times allowing selection of the desired memory configuration during program execution Reset clears the RAMO bit RAM1 The RAM bit determines the type of memory in the 0100 015F area 0 96 bytes of PROM 1 96 bytes of RAM This bit is readable and writable at all times allowing selection of the desired memory configuration during program execution Reset clears the RAM1 bit M68HC05 Applications Guide Rev 4 0 184 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
48. Compares the contents of to the contents of and sets the condition codes which may be used for arithmetic and logical conditional branching The contents of both ACCA and M are unchanged 7 Set if MSB of result is set cleared otherwise 7 R7 R6eR5 R4 R3 R2 R1 Set if all bits of the result are cleared cleared otherwise 7 7 7 e 7 7 7 Set if absolute value of the contents of memory is larger than the ab solute value of the accumulator cleared otherwise Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles CMP opr IMM 1 2 DIR 1 3 CMP opr EXT C1 hh 4 1 3 CMP opr X 1 E1 ff 4 CMP opr X IX2 D1 ee ff 5 M68HC05 Applications Guide Rev 4 0 270 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc Complement Instruction Set Details M68HC05 Instruction Set COM lt FF or lt FF M or X eX FF X Replaces the contents of ACCA X or M with its ones complement Each bit of the contents of ACCA X or M is replaced with the complement of that b
49. For More Information On This Product Go to www freescale com Listing Thermostat Example Freescale Semiconductor Inc Applications Sheet 17 of 21 0475 d6 06 80 LPSIN LDA MSINS X Get next ASCII char 0478 cd 06 3a JSR WDAT Loop prints IN 047b 5c INCX 047c a3 05 CPX 5 047 26 5 BNE LPSIN Loop till 5 chars 0480 b6 LDA INTMP Indoor temp 0482 06 JSR CNVERT Convert to ASCII 0485 cd 06 56 JSR SHOW2 Display as 2 digits 0488 06 5 JSR LCDDF Display 048b LDA 5 0 Left end of 2nd line 048d cd 06 20 JSR WCTRL Reposition entry point 0490 20 LDA 520 ASCII lt sp gt 0492 3d b2 TST HVACON Heat cool running 0494 27 02 ARNAST If not go around asterisk 0496 2a LDA ASCII asterisk 0498 06 ARNAST JSR WDAT Show lt sp gt or 0495 5 CLRX Message offset from MHVAC 049c b6 bl LDA MODE Get Mode in A 049e al 05 CMP 5 Mode HVACM set 04a0 26 04 BNE 5 Skip if not 5 04 2 6 ad LDA ENTRY Use ENTRY rather than HVACM 04a4 20 02 BRA AE5B 4 b6 AE LDA HVACM HVAC mode 04a8 27 Oe 5 HVD If HVACM 0 display OFF 4 06 LDX 6 Offset to HEAT 04ac 1 01 CMP 1 Heat mode 04 27 08 HVD If so display 04b0 ae Oc LDX 12 Offset to COOL 0452 al 02 CMP 12 Cool mode 0454 27 02 HVD If so display 0456
50. Rev 4 0 MOTOROLA Instruction Set Details For More Information On This Product Go to www freescale com 273 Freescale Semiconductor Inc Instruction Set Details EOR Exclusive OR Memory with Accumulator EOR Operation lt ACCA Description Performs the logical exclusive OR between the contents of ACCA and the contents of M and places the result in ACCA Each bit of ACCA after the operation will be the logical exclusive OR of the corresponding bits of M and ACCA before the operation Condition Codes and Boolean Formulae R7 Set if MSB of result is set cleared otherwise 7 R7 R6 R5 R4 R3 eR2 R1 Set if result is 00 cleared otherwise Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Operand s Cycles Code and Cycles EOR opr IMM A8 i 2 EOR opr DIR B8 dd 3 EOR opr EXT C8 hh Il 4 EOR X IX F8 3 EOR opr X 1 E8 ff 4 EOR opr X IX2 D8 ee ff 5 M68HC05 Applications Guide Rev 4 0 274 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc lt ACCA 01 Increment or lt M 01 Instruction Set D
51. therefore this alternate register should be used to read the timer counter in all cases except when intending to clear TOF This will avoid the possibility of the TOF being unintentionally cleared M68HC05 Applications Guide Rev 4 0 176 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data STOP WAIT Instruction Effects 3 14 9 Timer Application Example Figure 3 49 shows an example program to produce a 10 second delay after the timer counter is read In this case the timer counter and the output compare functions are used in the software program The two key programming instructions that you should note are 1 the read and or write instructions at the alternate counter and output compare registers and 2 the addition of 16 bit numbers 3 15 STOP WAIT Instruction Effects The STOP and WAIT instructions put the MC68HC705C8 MCU into low power consumption modes These instructions also affect the programmable timer the and the SPI systems A STOP WAIT flowchart is shown in Figure 3 50 3 15 1 Low Power Consumption Modes The STOP instruction places the MC68HC705C8 in its lowest power consumption mode In the STOP mode the internal oscillator is turned off causing all internal processing to be halted During the stop mode the bit in the condition code register is cleared to enable external interrupts
52. will be modified by subtracting an offset constant Ck CK ck Ck C CK Ck Ck CK KKK KKK K KKK KKK KKK KK KK KKK KKK CK C Ck C Ck Ck CK Sk Ck Ck kk Sk Pk Sk kx A kx 0309 A2D EQU Check temp sensors 0309 b6 a2 LDA TIC If 0 1 or 2 write to SPI 030b a1 02 CMP 2 030d 22 24 BHI XA2D Tite cxt 030 48 ASIA Move TIC 0 2 to upper nibble 0310 48 ASLA 0311 48 ASLA 0312 48 ASLA 4 bit left shift 0313 3d Ob TST SPSR Reads SPIF part of SPIF clear 0315 17 02 BCLR 3 PORTC Drive low true SA D CE to 0 0317 b7 Oc STA SPDR Initiates a transfer Requests conversion of next channel and returns data from previous channel Ch 0 Indoor Ch 1 Outdoor 0319 Of Ob fd SPIFLP BRCLR 7 SPSR SPIFLP Wait for SPI Xfer complete 031c 16 02 BSET 3 PORTC Drive low true SA D CE to 1 031e b6 a2 LDA TIC If O Exit 1 or 2 Read A D data 0320 27 11 BEQ XA2D 0 so exit 0322 56 0c LDA SPDR Get A D data 0324 02 a2 07 BRSET 1 TIC ADCH1 Tic 2 data is Ch 1 0327 c0 06 ea SUB OFFO A D Ch 0 subtract offset 032a b7 STA INTMP update indoor temperature 032c 20 05 BRA XA2D amp Exit 032e c0 06 eb ADCHI SUB OFF1 A D Ch 1 subtract offset 0331 b7 STA OUTMP Update outdoor temperature 0333 81 XA2D RTS RETURN From A2D M68HC05 Applications Guide Rev 4 0 MOTOROLA Applications 223 For More Information On This Product Go to www freescale com Listing Thermostat Exampl
53. 01 CLEAR 02 HOME 38 FUNCTION SET 0E DISPLAY ON CURSOR OFF 06 ENTRY MODE START WITH ASCII A gt DLP WRITE DATA TO LCD NEXT LETTER A B C S T YES STOP Figure 4 7 Display Checkout Flowchart If the example program is too large to fit in the 176 bytes of RAM 0050 to 00FF you will have to program the example into EPROM and provide a reset vector To provide a reset vector for a program example that begins with the label BEGIN put the following two lines at the end of your program ORG FDB 1FFE BEGIN The example programs provided do not include a size byte or a reset vector you will have to add whichever is appropriate for your situation M68HC05 Applications Guide Rev 4 0 204 Applications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Thermostat Project Details KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK KKK KKK TRYLCD LCD Check out program Initialize LCD module display ABCDEF 5 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK ko Register Equates 0000 PORTA EQU 00 LCD display data 0001 PORTB EQU 501 Keypad Row4 3 2 1 Coll 2 3 4 0002 PORTC EQU 02 Fan Heat Cool Beep ADen E RS R W 0004 DDRA EQU 504 Data direction Port A
54. 042 6 ad LDA ENTRY Use ENTRY rather than MIN 0431 06 a6AE2 JSR CNVERT Convert MINs to ASCII 0434 cd 06 56 JSR SHOW2 Display as 2 digits 0437 a6 20 LDA 520 5 lt 5 gt 0439 06 JSR WDAT lt Sp gt to LCD 043 LDA AMPM Current AMPM indicator 043e a3 03 CPX 3 Mode AMPM set 0440 26 02 BNE AE3 Skip if not 3 0442 6 ad LDA ENTRY Use ENTRY rather than AMPM 0444 4d Check for 0 0445 26 04 ITSPM If not its PM 0447 41 LDA ASCII 0449 20 02 BRA SHOWAP Display A for AM 044b 50 ITSPM LDA P If it wasn t AM 044d cd 06 3a SHOWAP JSR WDAT Show A or P 0450 20 LDA 520 ASCII lt Sp gt 0452 cd 06 3a JSR WDAT To LCD 0455 LDA 4 Offset from MDAY 0457 a3 04 CPX 4 Mode DAY set 0459 26 04 BNE 4 Skip if not 4 045b be a5 LDX ENTRY Use ENTRY rather than DAY 045d 20 02 BRA DAYLP Print Entry day 045f be a9 AE4 LDX DAY DAY 1 to 7 0461 04 DAYLP ADD 4 Advance pointer to next MDAY entry 0463 5a DECX 1 gt 0 or n gt n 1 0464 26 fb BNE DAYLP till X 0 A will 4 DAY 0466 97 TAX Move offset to X 0467 d6 06 8a SHODAY LDA MDAY X Get next char 046a a1 04 CMP 4 End of message 046 27 06 BEQ DUNDAY If done printing day 046e 06 JSR WDAT Send char to LCD 0471 5c INCX Point at next char 0472 20 3 BRA SHODAY Loop till 04 found 0474 5f DUNDAY CLRX Loop index M68HCO05 Applications Guide Rev 4 0 MOTOROLA Applications 227
55. Code and Cycles Freescale Semiconductor Inc Instruction Set Details M68HC05 Instruction Set Branch Always B RA PC lt PC 0002 Rel Unconditional branch to the address given by the foregoing formula in which Rel is the relative offset stored as a twos complement number in the last byte of machine code corresponding to the branch instruction PC is the address of the opcode for the branch instruction The source program specifies the destination of any branch instruction by its absolute address either as a numerical value or as a symbol or expression which can be numerically evaluated by the assembler The assembler calculates the relative address Rel from the absolute address and the current value of the location counter H 7 1 1 1 None affected Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles BRA rel REL 20 rr 3 The following table is a summary of all branch instructions Test Boolean Mnemonic Opcode Complementary Branch Comment r gt m 2 0 22 lt BLS 23 Unsigned r m C 0 BHS BCC 24 r lt m BLO BCS 25 Unsigned r m Z 1 BEQ 27 26 Unsigned r lt m C Z 1 BLS 23 r gt m BHI 22 Unsigned rm C BLO BCS 25 gt 5 24 Unsigned Carry C BCS 25 No Carry BCC 24 Simple r 0 27 r 0 BNE 26 Simple Negative N 1 BMI 2B Plus BPL
56. Cycles BIT opr IMM A5 i 2 BIT opr DIR B5 dd 3 BIT opr EXT C5 hh 4 IX F5 3 BIT opr X 5 ff 4 BIT IX2 D5 ee ff 5 M68HC05 Applications Guide Rev 4 0 MOTOROLA For More Information On This Product Go to www freescale com Instruction Set Details 253 BLO Operation Description Condition Codes and Boolean Formulae Source Forms Freescale Semiconductor Inc Instruction Set Details BLO Branch if Lower Same as BCS lt 0002 Rel i e if ACCA lt if C 1 unsigned binary numbers If the BLO instruction is executed immediately after execution of a CMP or SUB instruction the branch will occur if the unsigned binary number in ACCA was less than the unsigned binary number in M See BRA instruction for further details of the execution of the branch 1 1 1 a None affected Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Operand s Cycles Code and Cycles BLO rel REL 25 rr 3 The following table is a summary of all branch instructions Test Boolean Mnemonic Opcode Complementary Branch Comment r gt m 2 0 22 lt BLS 23 Unsigned 0 BHS BCC 24 rm BLO BCS 25 Unsigned r m Z 1 BEQ 27 26 Unsigned r lt m C Z 1 BLS 23 r gt m BHI 22 Unsigned rm
57. During the LDA 02 instruction at 1 the accumulator was loaded with the value 2 during the DECA instruction at 9 the accumulator was decremented to 1 which is not equal to zero Thus at 14 the branch condition was true and the twos complement offset FD or 3 was added to the internal PC which was 0203 at the time to get the value 0200 Repeat of cycles 9 through 13 except that when the DECA instruction at 15 was executed this time the accumulator went from 01 to 00 62 Microcontroller Operation MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation CPU Operation 20 Since the accumulator is now equal to zero the BNE 19 branch condition is not true and the branch will not be taken 21 CPU reads the RTS opcode 81 from 0203 22 26 The RTS takes six cycles During the last five cycles of this instruction the SP is incremented to 00FE the high order return address 01 is read from the stack 00FE the SP is incremented again to 00FF the low order return address 05 is read from the stack 00FF and the PC is loaded with this recovered return address 0105 27 CPU reads the STA direct opcode B7 from location 0105 28 CPU reads the low order direct address 02 from location 0106 29 30 The STA direct instruction takes a total of four cycles During these last two cycl
58. IRQ INTERRUPT IRQ INTERRUPT INTERNAL TIMER INTERRUPT i INTERNAL SCI INTERRUPT TURN ON OSCILLATOR DELAY TO STABILIZE INTERNAL SPI INTERRUPT 1 FETCH RESET VECTOR OR 2 SERVICE INTERRUPT A SAVE CPU REGS ON STACK SETI IN CC REGISTER C VECTOR TO INTERRUPT SERVICE ROUTINE Figure 3 50 STOP WAIT Flowchart The WAIT instruction also places the MC68HC705C8 a low power consumption mode but the wait mode consumes somewhat more power than the STOP mode In the wait mode all CPU processing is stopped however the internal clock the programmable timer SPI and SCI systems if enabled remain active During the wait mode the bit in the condition code register is cleared to enable all interrupts All other registers and memory remain unaltered and all parallel I O lines remain unchanged This state continues until any interrupt or reset is sensed At M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 179 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8 705 8 Functional Data this time the program counter is loaded with the interrupt vector at memory location 1FF4 1FFF which contains the starting address of the interrupt or reset service routine 3 15 2 Effects on On Chip Peripherals The STOP instruction causes the oscillator to be turned off which halts
59. N T PARALLEL DATA TO CPU DATA BUS RECEIVER Figure 3 29 Double Buffering M68HCO5 Applications Guide Rev 4 0 146 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Serial Communications Interface SCI 3 11 4 Data Formats The standard NRZ data formats used for communications are shown in Figure 3 30 The upper portion of this figure shows the normal 8 bit data format the lower portion of the figure shows the 9 bit data format The 9 bit data format is selected by setting the M control bit in SCCR1 to 1 The basic characteristics of the NRZ format are as follows 1 A high level indicates a logic one and a low level a logic zero 2 The idle line is high prior to message transmission reception 3 Astart bit logic zero is transmitted received as the first bit of data in a character 4 Datais transmitted received LSB first 5 The last bit in a character bit 10 or 11 is a high stop bit 6 A break is a low logic zero for 10 or 11 bit times START BIT STOP BIT NEXT START BIT 0 1 2 3 4 5 6 1 8 Alili uj START BIT STOP BIT NEXT START BIT 1 Control bit M selects optional ninth 9 data bit Figure 3 30 Data Formats M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 147 For More Information On This Product Go to www f
60. None affected Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Operand s Cycles Code and Cycles JSR opr DIR BD dd 5 JSR opr EXT CD hh 6 JSR 5 JSR opr 1 ff 6 JSR opr X IX2 DD ee ff 7 M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details 277 For More Information On This Product Go to www freescale com LDA Operation Description Condition Codes and Boolean Formulae Source Forms Freescale Semiconductor Inc Instruction Set Details Load Accumulator from Memory ACCA LDA Loads the contents of memory into the accumulator The condition codes are set according to the data R7 Set if MSB of result is set cleared otherwise 7 R7 R6 R5 eR4 R3e R2 R1 RO Set if result is 00 cleared otherwise Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Operand s Cycles Code and Cycles LDA opr IMM A6 2 LDA opr DIR B6 dd 3 LDA opr EXT C6 hh 4 LDA X F6 3 LDA opr X 1 6 ff 4 LDA opr X IX2 D6 ee ff 5 M68HC05 Applications Guide Rev 4 0 278 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com LDX Operation Description Condition Codes and Boolean Formulae Source Forms Ad
61. PCO 06 DDRC RESET CONDITION ALL INPUTS 02 PORTC RESET CONDITION PIN NAMES REF Figure 3 18 Port C and Data Direction C Registers M68HC05 Applications Guide Rev 4 0 134 MC68HC705C8 Functional Data For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc MC68HC705C8 Functional Data Microcontroller Input Output Any port A B or C pin is configured as an output if its corresponding DDR bit is set to a logic one A pin is configured as an input if its corresponding DDR bit is cleared to a logic zero At power on or reset all DDRs are cleared which configure all port A B and C pins as inputs The DDRs are capable of being written to or being read by the processor Refer to Figure 3 19 and Table 3 9 When a port pin is configured as an output a read of the data register actually reads the value of the output data latch and not the I O pin CONNECTIONS TO INTERNAL DATA BUS A DATA DIRECTION REGISTER BIT LATCHED OUTPUT DATA BIT 9 1 Output buffer enables latched output to drive pin when DDR bit is 1 output 2 Input buffer enabled when DDR bit is 0 input 3 Input buffer enabled when DDR bit is 1 output Figure 3 19 Parallel Port I O Circuitry Table 3 9 I O Pin Functions RW DDR Pin Function The I O pin is in input mode Data is written into the output 0 0 data la
62. Rev 4 0 MOTOROLA List of Figures 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Figures M68HC05 Applications Guide Rev 4 0 18 List of Figures MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Guide M68HC05 Table 2 1 3 1 3 2 3 3 3 5 3 6 3 7 3 8 3 9 3 10 3 11 3 12 4 1 List of Tables Title Page Decimal Binary and Hexadecimal Equivalents 33 COP Timeout Period versus 1 98 Register Memory 116 Read Modify Write 117 Branch 118 Control 5 5 119 Instruction Set Summary 121 Opcode 127 Vector Address for Interrupts and Reset 129 e pack Xd A REA o 135 Prescaler Baud Rate Frequency Output 142 Transmit Baud Rate 143 ASCII Hexadecimal Code Conversion 151 Thermostat Project Parts 5 199 M68HC05 Applications Guide Rev 4 0 MOTOROLA List of Tables 19 For More Information On This Product Go to www freesca
63. Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 121 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Table 3 6 Instruction Set Summary Sheet 2 of 6 Effecton 2 lt p ee Operation Description CCR 58 85 9 32 6 amp o BIL Branch if IRQ Pin Low lt 2 rel IRQ 0 REL 2E rr 3 opr IMM 5 2 BIT opr DIR B5 dd 3 BIT opr EXT C5 hhll 4 BIT opr X Bit Test Accumulator with Memory Byte A M 111 2 05 5 BIT opr X IX1 E5 ff 4 BIT X IX F5 3 BLO rel Branch if Lower Same as BCS PC lt PC 2 1 1 1 REL 25 3 5 Branch if Lower or Same lt 2 rel Cv 2 1 REL 23 3 BMC Branch if Interrupt Mask Clear 2 rel 1 0 REL 2 3 Branch if Minus lt PC 2 3 1 REL 28 3 5 Branch if Interrupt Mask Set PC lt 2 1 1 REL 2D rr 3 BNE rel Branch if Not Equal lt 2 rel Z 0 REL 26 rr 3 BPL Branch if Plus lt PO 2 rel N 0 REL 2 3 BRA rel Branch Always PC
64. X points at applicable value to be changed HR MIN AMPM DAY etc 0290 2a Oc BPL ranch if legal 0292 e6 a5 ENTRY X Get current value 0294 b7 a5 STA ENTRY Revert to current legal value 0296 6 CLR ENTFLG So next treated as first 0298 la LDA 26 26 50mS 1 3 sec 029 b7 STA BEEPM 1S 200mS off 100mS on 029 20 18 BRA KEYFE Acknowledge entry attempt 029 e7 a5 LEGENT STA ENTRY X Update value being set 02 0 08 LDA 8 100mS on 200mS off 100mS on 02a2 b7 STA BEEPM Double beep 02a4 3c bl NXTMOD INC MODE Adv to next setting 02 6 b6 bl LDA MODE Check for past 6 02a8 al 07 CMP 7 lt 7 O2aa 25 02 BLO NOCLR If OK skip clear 02 CLR MODE Rollover to 0 O2ae be bl NOCLR LDX MODE use as index to current 0250 a5 DA ENTRY X Get current value of entry 0252 b7 a5 STA ENTRY Use current as default setting 02b4 b6 CLR ENTFLG Indicate next is lst 0256 fe KEYFE LDA 5 0258 b7 b3 STA KEYVAL Acknowledge key closures O2ba 81 XUSER RTS RETURN from USER M68HC05 Applications Guide Rev 4 0 MOTOROLA Applications 221 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Listing Thermostat Example 02bb 02 02bf 02 1 02 3 02c5 02c7 02c9 02cb 02cd 02cf 02d0 02d2 02d4 02d6 0248 02da 02db 02dd 02df 02 1 02 3 02 5 02 7 02 9 02eb 02ed 02ef 02 1 0262 0254 0266 026
65. all internal CPU processing as well as the operation of the programmable timer SCI and SPI The oscillator starts again when an external interrupt IRQ or RESET occurs 3 15 2 1 Timer Action During Stop Mode When the MCU enters the STOP mode the timer counter stops counting the internal processor clock is stopped It remains at that particular count value until an interrupt or reset occurs If the interrupt an external low on the IRQ pin the counter resumes from its stopped value as if nothing had happened If a reset occurs the counter is forced to F FFC 3 15 2 2 SCI Action During Stop Mode When the MCU enters the STOP mode the baud rate generator driving the receiver and transmitter is stopped which halts all SCI activity If the STOP instruction is executed during a transmitter transfer that transfer is halted When the STOP mode is exited that particular transmission resumes if the exit is the result of a low input to the IRQ pin Since the STOP mode interferes with SCI character transmission make sure that the SCI transmitter is idle when the STOP instruction is executed If the receiver is receiving data when the STOP instruction is executed received data sampling is stopped baud rate generator stops and the remainder of the data is lost The stop mode should not be used while SCI characters are being received M68HC05 Applications Guide Rev 4 0 180 MC68HC705C8 Functional Data MOTOROLA For More Inf
66. all output 0005 DDRB EQU 05 Direction Port 7 4in 3 O0out 0006 DDRC EQU 506 Data direction Port all output RAM Equates 009 59 One byte temp storage location 009 EQU SOF One byte temp storage location 0100 ORG 100 Set Port data patterns and directions 0100 8 TRYLCD LDA SE8 Fan Heat Cool Beep ADen E RS R W 0102 b7 02 STA PORTC Initial Thermostat control values 0104 a6 ff LDA 0106 7 04 STA DDRA Port A all outputs 0108 b7 06 STA DDRC Port C all outputs LCD display peripheral needs to be initialized 010 01 LDA 501 010 cd 01 2f JSR WCTRL Clear 010 02 LDA 502 0111 01 2f JSR WCTRL Home 0114 38 LDA 538 0116 cd 01 2f JSR WCTRL Function Set 8 bit 2 line 5 7 0119 LDA 0 0115 01 2f JSR WCTRL Display on Cursor off Olle 06 LDA 506 0120 01 2 JSR WCTRL Entry mode Inc addr no shift 0123 41 LDA ASCE 0125 01 49 DLP JSR WDAT Display a character 0128 4c INCA To next ASCII character 0129 al 54 CMP ABCDEFGHIJKLMNOPORS amp stop 0125 26 8 BNE DLP Loop till T 012d 20 fe HERE BRA HERE Stop Figure 4 8 Display Checkout Program Listing Sheet 1 of 2 M68HC05 Applications Guide Rev 4 0 MOTOROLA Applications 205 For More Information On This Product Go to www freescale com 012 0131 0133 0135 0137 0 239 013a 013c 013e 0140 0143 0144 0146 0148 0149 0146 014 014
67. depending upon the state of a particular bit in memory or various condition code bits If the condition checked by the branch instruction is true program flow proceeds to a specified location in memory If the condition checked by the branch is not true the CPU proceeds to the instruction following the branch instruction Decision blocks in a flowchart correspond to conditional branch instructions in the program Most branch instructions contain two bytes one for the opcode and one for a relative offset byte Branch on bit clear BRCLR and branch on bit set BRSET instructions require three bytes the opcode a one byte direct address to specify the memory location to be tested and the relative offset byte The relative offset byte is interpreted by the CPU as a twos complement signed value If the branch condition checked is true this signed offset is added to the PC and the CPU reads its next instruction from this calculated new address If the branch condition is not true the CPU just continues to the next instruction after the branch instruction The following excerpt from Figure 2 9 demonstrates a useful way to use a conditional branch based on the N condition code bit that is sometimes overlooked TOP LDA PORTB Read sw at MSB of Port B BPL TOP Loop till MSB 1 Neg trick JSR DLY50 Delay about 50 ms to debounce The first line means load accumulator with the value at I O port B of the MCU The most significant bit of thi
68. dissipation The timer the timer prescaler and the on chip peripherals continue to operate because they are potential sources of an interrupt Wait causes enabling of interrupts by clearing the bit in the CCR and stops clocking of processor circuits Interrupts from on chip peripherals may be enabled or disabled by local control bits prior to execution of the WAIT instruction When the RESET or IRQ input goes low or when any on chip system requests interrupt service the processor clocks are enabled and the reset IRQ or other interrupt service request is processed H 7 C Formulae 1 1 1 0 ER 0 Cleared Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Operand s Cycles Code and Cycles WAIT INH 8F 2 M68HCO05 Applications Guide Rev 4 0 302 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Guide M68HC05 Appendix B Review Questions B 1 Contents EC REPARARE RA 303 B3 Review 5 304 B 4 Review Questions Answers and Explanations 318 B 2 Introduction The 50 review questions presented are based directly on the text of this applications guide These review questions are repeated with the proper answers indicating the p
69. inclusive OR Exclusive OR NOT Negation twos complement x Multiplication MPU Registers Program Counter PCH PC High Byte PCL PC Low Byte SP Stack Pointer REL Relative Address one byte Operands none ii dd dd rr hh Il none ff ee ff rr The opcode map is shown in Table 3 7 M68HC05 Applications Guide Rev 4 0 120 MC68HC705C8 Functional Data For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc MC68HC705C8 Functional Data Instruction Set Summary Table 3 6 Instruction Set Summary Sheet 1 of 6 Effecton 2 o 5 8 2 seule Operation Description CCR 58 85 o 52 5 2 6 IMM 9 ii 2 ADC DIR dd 3 ADC opr m EXT c9 hhll 4 ADC oprX Add with Carry A lt C 1 11111 I2 pglee ffl 5 ADC I1 E9 ff 4 ADC IX 9 3 ADD opr ii 2 ADD opr DIR BB dd 3 ADD opr EXT CB hhll 4 ADD oprX Add without Carry lt M t t t1 1 x2 pBlee ffl 5 ADD IX1 EB ff 4 ADD IX FB 3 AND opr A4 ii 2 AND opr DIR B4 dd 3 AND opr EXT C4 hhll 4 AND oprX Logical AND lt M I2 p4le
70. n 7 6 5 0 in location M All other bits in M are unaffected M can be any RAM or register address in the 0000 to 00FF area of memory i e direct addressing mode is used to specify the address of the H 7 C Formulae 1 1 1 None affected Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Operand s Cycles Code and Cycles BCLR 0 DIR bit 0 11 dd 5 BUR 1 opr DIR bit 1 13 dd 5 BCLR 2 opr DIR bit 2 15 dd 5 BCLR 3 opr DIR bit 3 17 dd 5 BCLR 4 opr DIR bit 4 19 dd 5 BUR 5 opr DIR bit 5 1B dd 5 BUR 6 opr DIR bit 6 1D dd 5 BCLR 7 DIR bit 7 1F dd 5 M68HC05 Applications Guide Rev 4 0 244 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com BCS Operation Description Condition Codes and Boolean Freescale Semiconductor Inc Instruction Set Details M68HC05 Instruction Set Branch if Carry Set Same as BLO lt 0002 Rel if C 1 BCS Tests the state of the C bit in the CCR and causes a branch if C is set See BRA instruction for further details of the execution of the branch H 2 Formulae 1 1 1 None affected Source Forms A
71. 0 0648 ae 14 LDX 20 20 6 1US 120US 064a 5aL120 DECX Delay loop 120uUS 064b 26 fd BNE L120 20 19 L9 18 2 1 0 064d b6 a0 LDA TEMPA Restore A 064f be al LDX TEMPX Restore X 0651 81 RTS RETURN M68HC05 Applications Guide Rev 4 0 230 Applications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Thermostat Project Details Listing Thermostat Example Sheet 20 of 21 CK CC C CK C Ck CK C CC Ck Ck KKK KK KKK KKK KKK KKK KKK Kk Ck Ck kk Ck Ck Sk Sk Pk kv SHOW3 Display 3 ASCII chars on LCD rd R ASC100 ASC10 ASC1 SHOW Display 2 ASCII chars on LCD 2 5 10 5 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK 0652 b6 ae SHOW3 LDA 5 100 Get ASCII 100 s digit 0654 ad e4 BSR WDAT Send to LCD 0656 b6 af SHOW2 LDA 5 10 Get ASCII 10 s digit 0658 ad 0 BSR WDAT Send to LCD 065a b6 bo IDA ASC1 Get ASCII 1 s digit 065 BSR WDAT Send to LCD 065 81 RTS RETURN Ck CK ck Ck CK C Ck CK CC CC C Ck CK KKK KKK KK KKK KKK KKK KKK KKK CK Ck Ck Ck kk Ck Kk Sk Sk Pk kv LCDDF Display F on LCD xk CK Sk Ck Ck CK Ck Ck CK CC Ck CK C C CK C C CK Ck Ck CK CC CC Ck Ck CK Ck Ck Ck CK Ck CK Ck Ck CK Sk Ck Ck CK Ck Ck Ck kk Ck Kk Sk Sk Pk Mk 065f a6 df LCDDF LDA SDF Get ASCII degrees symbol
72. 0002 Rel if C 20 Tests the state of the C bit in the CCR and causes a branch if C is clear See BRA instruction for further details of the execution of the branch H 7 1 1 1 None affected Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles BCC rel REL 24 rr 3 The following table is a summary of all branch instructions Test Boolean Mnemonic Opcode Complementary Branch Comment r gt m C Z 0 BHI 22 r lt m BLS 23 Unsigned 0 BHS BCC 24 rm BLO BCS 25 Unsigned r m Z 1 BEQ 27 26 Unsigned lt C Z 1 BLS 23 r gt m BHI 22 Unsigned rm C 1 BLO BCS 25 BHS BCC 24 Unsigned Carry 1 BCS 25 No Carry BCC 24 Simple r 0 2 1 27 r 0 BNE 26 Simple Negative N 1 BMI 2B Plus BPL 2A Simple Mask 1 5 2D Mask 0 BMC 2 Half Carry H 1 BHCS 29 No Half Carry BHCC 28 Simple IRQ Pin High BIH 2F IRQ Low BIL 2E Simple Always BRA 20 Never BRN 21 Unconditional r register ACCA or X m memory operand M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details 243 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Details BCLR Operation Description Condition Codes and Boolean Clear Bit in Memory BCLR n Mn 0 Clear bit n
73. 0151 0153 0155 0157 0159 015 015 015 0160 bf b7 14 15 ae 5a 26 al 22 cd 5a 26 be 81 bf b7 12 14 15 13 5a 26 b6 be 81 9f 00 02 0 2 14 02 06 01 9f 9f 9e 00 02 02 02 02 14 fd 9e 9f 48 WCTRL L120U L5M ARN5M ANRTS Freescale Semiconductor Inc Applications KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK WCTRL Write control word to LCD peripheral 2 Return with original Delay 4 5mS if Enter with control word in accumulator value of 01 or 02 else delay 12015 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK EMPX PORTA 2 2 L 20 1200 502 RN5M ANRTS H EMPX Save X Write control word to LCD gt I gt 0 20 6 115 12015 Delay loop 12015 20 21954L9 L8 55 L 0 Commands 01 amp 02 req extra delay If command 02 skip long delay JSR RTS TAKES 12 just want delay TAKES 3 0 gt 1 on first pass 3 Loop 256 18 105 4 608mS Delay Restore X RETURN P P KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK WDAT Write data word to LCD peripheral Enter with data word in accumulator Return with original values of X amp Delay 12015 after data write KKKKKKKKKKKKKKKKKKKKK
74. 0661 ad 7 BSR WDAT Send to LCD 0663 46 LDA Get ASCII capitol F 0665 ad d3 BSR WDAT Send to LCD 0667 81 RTS RETURN Normal LCD display format HH MMADAYINI100 F 2 0 20200 1st line of display is 500 1 513 2nd line of display is 540 553 Miscellaneous LCD message segments Used in DSPLAY sub 0668 4f 46 46 20 20 MHVAC FCC OFF These 4 messages accessed by 066d 04 FCB 04 X offset from MHVAC 04 is 066e 48 45 41 54 20 ECC HEAT used to mark the end of a string 0673 04 FCB 04 0674 43 4f 4f 4c 20 FCC COOL 0679 04 FCB 04 067a 46 41 4e 20 20 FCC 067 04 FCB 504 0680 20 20 49 4e 20 MSINS 0685 20 4 55 54 20 MSOUT OUT 068 53 55 4e MDAY FCC SUN These messages accessed by 068d 04 FCB 04 xoffset from MDAY 04 is 068e 4 4f 4e ECC MON used to mark the end of a string 0691 04 FCB 04 0692 54 55 45 FCC 0695 04 504 0696 57 45 44 WED 0699 04 FCB 04 069a 54 48 55 FCC THU 069d 04 FCB 04 069e 46 52 49 FCC 06al 04 FCB 04 0 2 53 41 54 FCC 5 5 04 FCB 504 M68HC05 Applications Guide Rev 4 0 MOTOROLA Applications 231 For More Information On This Product Go to www freescale com Listing Thermostat Example 06a6 06a8 0650 0652 0654 0656 0608 06ba 06bc 06be 06 0 06 2 06 4 06 6 06 8 06c9 06cb 06cd 06cf 0641 0643 0645 0647 0649 06db 06
75. 1 2 Li AED 81 3 4 1 3 IRQ Maskable Interrupt 82 3 4 1 4 errr eee 82 3 4 1 5 Tem 82 3 4 1 6 De eccL CT 83 3 4 1 7 JSOT aNd OSOZ kite meque Red m do did 83 3 4 1 8 Gc ick dab ds dca Rode obo eec EO OR dea edd aie 83 3 4 1 9 E 83 M68HC05 Applications Guide Rev 4 0 8 Table of Contents MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents 3241 10 PER RU dedos o RO de 85 3 4 1 11 PDS5 PD0 and PDT Ead wed 85 3 4 2 Typical Basic 5 85 35 asa wig En eee 87 3 5 1 Memory 87 3 5 2 Memo Map 2 ccd s 88 3 6 Cane Processor UE 88 3 6 1 90 3 5 1 1 re p IER E QUE e EGER RR 90 3 5 1 2 Index Register wa dez n nare 91 3 6 1 3 Condition Code 91 3 6 1 4 Program COUME 93 3 5 1 5 ACR FOMEI kc suae peewee d e are ad qd Gas 94 3 6 2 Arithmetic Logic Unit ALU 94 3 6 3 o MIT 95 3 6 4 95 3 6 4 1 POPE 95 3 6 4 2 Computer Operating Properly
76. 11 6 3 Normal Receive 149 3 11 7 SCI Application 150 3 12 Synchronous Serial Peripheral Interface SPI 153 3 121 DEDE a ia hie we dehet 155 3 122 Functional Descrplli uui poo porn o oor deae 156 2 12 3 Pin Deseriptong o reci ca naaman aede d ka 156 3 12 3 1 Serial Data Pins MISO MOSI 156 sna CICER OUI E EXER R 157 41522 58 158 3 124 Registers aci aac Oro dide Roe de dob Fal Rw eee 158 3 12 4 1 Serial Peripheral Control Register SPCR 158 3 12 4 2 Serial Peripheral Status Register SPSR 160 3 12 4 3 Serial Peripheral Data I O Register SPDR 161 3 13 Application 161 3 14 Programmable 163 3 14 1 Functional Description 166 3 14 2 Timer Counter and Alternate Counter Registers 168 3 14 3 Input Capture 169 3 14 4 Input Capture 170 3 14 5 Output Compare Concept 172 3 14 6 Output Compare Operation 174 3 14 7 Timer Control Register TCR 175 3 14 8 Timer Status Register TSR
77. 2 ff 4 SBC opr X IX2 D2 ee ff 5 M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details For More Information On This Product Go to www freescale com 291 SEC Operation Description Condition Codes and Boolean Formulae Freescale Semiconductor Inc Instruction Set Details C bit 1 Set Carry Bit SEC Sets the C bit in the CCR SEC may be used to set up the C bit prior to a shift or rotate instruction that involves the C bit C 7 Set Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode _ Operand s Cycles Code and Cycles SEC INH 99 2 M68HC05 Applications Guide Rev 4 0 292 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com SEI Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc bit 1 Instruction Set Details M68HC05 Instruction Set Set Interrupt Mask Bit SEI Sets the interrupt mask bit in the CCR The microprocessor is inhibited from servicing interrupts while the bit is set Set Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles 9B 2 M68HC05 Applications Guide Rev 4 0 MOTOROL
78. 21 SCI Transmitter Block 138 3 22 SCI Receiver Block 140 3 23 Baud Rate 141 2 24 Rate Generator Division 142 3 25 Serial Communications Control Register 144 3 26 Serial Communications Control Register Two 144 3 27 Serial Communications Status Register 145 3 28 Serial Communications Data Register 146 3 29 Double Buffering 146 3 30 i hh eho eo dabo ar Oe 147 3 31 SCI Normal Transmit Operation Flowchart 149 3 32 SCI Normal Receive Operation Flowchart 149 3 33 5 Application Example Program 152 3 34 SPI Block Diagram 154 3 35 Shift Register Operation 155 3 36 Data Clock Timing 157 3 37 Serial Peripheral Control 158 3 38 Serial Peripheral Status 160 3 39 Serial Peripheral Data I O Register 161 3 40 SPI Application Example 162 3 41 SPI Application Example Flowchart 164 3 42 Application Example 165 3 43 Programmable Timer Block
79. 8192 of memory Values for this register are expressed as four hexadecimal digits where the upper order three bits of the corresponding 16 bit binary address are always zero The condition code CC register is an 8 bit register holding status indicators that reflect the result of some prior CPU operation The three high order bits of this register are not used and always stay at logic one M68HCO05 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation 39 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation 2 4 4 Memory Uses Branch instructions use these status bits to make simple either or decisions The stack pointer SP is used as a pointer to the next available location in a last in first out LIFO stack The stack can be thought of as a pile of cards each holding a single byte of information At any given time the CPU can put a card on top of the stack or take a card off the stack Cards within the stack cannot be used unless all the cards piled on top are removed first The CPU accomplishes this stack effect by way of the SP The SP points to a memory location pigeon hole which is thought of as the next available card When the CPU pushes a piece of data onto the stack the data value is written into the pigeon hole pointed to by the SP the SP is then decremented so it points at the next previous memory location pigeon hole When the C
80. 8E 2 STX opr DIR dd 4 STX opr EXT CF hhll 5 STX opr X Store Index Register In Memory lt X t f IX2 DF 6 STX opr X 1 ff 5 STX X IX FF 4 SUB opr 2 SUB DIR 0 dd 3 SUB opr EXT CO hhll 4 SUB Subtract Memory Byte from Accumulator lt M t tit lee f 5 SUB opr X EO ff 4 SUB X IX FO 3 M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 125 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Table 3 6 Instruction Set Summary Sheet 6 of 6 Effecton 2 o o 8 5 2 yc Operation Description CCR 58185 52 818 16 c PC 1 Push PCL SP lt SP 1 Push PCH SP lt SP 1 Push X SP lt SP 1 Push A Le SWI Software Interrupt SP SP 1 Push CCR 1 INH 83 10 SP lt SP 1 1 1 lt Interrupt Vector High Byte PCL lt Interrupt Vector Low Byte TAX Transfer Accumulator to Index Register X lt INH 97 2 TST opr DIR 94 4 TSTA 40 3 TSTX Test Memory Byte for Negative or Zero M 00 t t INH 150 3 TST opr X IX1 6D ff 5 TST IX 7D 4 TXA Transfer Index Register to Accumulator lt X INH 2 WAI
81. 9 LL 9 2 26 29 1v HSV 146 9 4 v9 9 vl 4 2 ve 79 8 vy YSI iui HIUS 1e91607 9 z 89 9 8 9 2 88 L 89 8v 151 497 1801607 9 2 99 9 9 4 2 96 99 9 HOU Aveo 9 2 69 9 6 9 z 68 69 6v Aue m 1 sz 9 2 09 9 0 S 2 08 05 DAN 9 2 9 9 eZ 9 2 es WOO 9 2 39 9 9 e JE g L ds 4p 410 12210 9 v9 9 YZ 9 2 vv 9 99 9 or 9 2 98 og Ov jueuieJou so o 9 3 epoo sejo 9 3 epoo sajo 9 sei g lt 2 2 sa Ag 2 sayAg epoo waun uonoun do do do do do a x eY4M AJIpoj pee 6 6 1 1 M68HC05 Applications Guide Rev 4 0 117 MC68HC705C8 Functional Data For More Information On This Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Table 3 4 Branch Instructions Relative Addressing Mode Function Mnemonic Opcode T Bytes Cycles Branch Always BRA 20 2 3 Bra
82. All other registers and memory remain unaltered and all I O lines remain unchanged This state continues until an external interrupt IRQ or RESET is sensed at which time the internal oscillator is turned on The external interrupt or reset causes the program counter to vector to memory location 1FFA and 1FFB or 1FFE and 1FFF These locations contain the starting address of the interrupt or reset service routine respectively M68HCO05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 177 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8 705 8 Functional Data KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK Simple 68 05 Timer Program Example i Ck CK ck Ck Ck CK Ck Ck CK CC C CK C Ck CK Ck CCS CC Ck CK Ck Ck Ck CK Ck Ck CK Ck Ck kk Sk Pk kv kx X 0006 DDRC EQU 06 Data direction control port C 0002 PORTC EQU 02 Direct address of port C LED 0016 OCMPHI EQU 16 Output compare high reg 0017 OCMPLO EQU Sl Output compare low reg 0013 TSR EQU 13 ICF OCF TOF 0 0 0 0 0 00a0 TENSEC EQU SAO Used to count 39 out compares 00 1 SAI One byte temp for 16 bit OCMP add 0350 ORG 350 0350 40 INIT LDA 34501000000 Make DDR bit for LED a one 0352 b7 06 STA DDRC So Red LED pin is an output 0354 a6 40 BEGIN LDA 01000000 Port bit 6 is red LED 0356 b8 02 EOR PORTC Toggle
83. Begin initialization Baud rate to 4800 2MHz Xtal Set up SCCRI Store in SCCR1 register Set up SCCR2 Store in SCCR2 register Checks for receive data Store received ASCII data in temp Convert LSB of ASCII char to hex ORA 530 3 LSB LSB CMP 539 need to change to 41 46 BLS ARN1 Branch if 30 39 OK ADD 7 Add offset ARN1 STA TEMP LO Store LSB of hex in TEMPLO LDA TEMP Read the original ASCII data LSRA Shift right 4 bits LSRA LSRA LSRA ORA 530 ASCII for is 3N 0 9 539 3A 3F need to change to 41 46 BLS ARN2 Branch if 30 39 ADD 7 Add offset ARN2 STA MS nibble of hex to LDA 500 Load hex value for lt CR gt BSR SENDATA Carriage return LDA 50 Load hex value for lt LF gt BSR SENDATA Line feed LDA S Load hex value for 5 BSR SENDATA Print dollar sign LDA TEMPHI Get high half of hex value BSR SENDATA Print LDA TEMP LO Get low half of hex value BSR SENDATA Print BRA START Branch back to start Get an SCI character return w it GETDATA BRCLR 5 SCSR GETDATA RDRF 1 LDA SCDAT OK get RTS Return from GETDATA Send an SCI character call sub w it in A SENDATA BRCLR 7 SCSR SENDATA TDRE 1 STA SCDAT RTS OK send Return from SENDATA Figure 3 33 SCI Application Example Program M68HC05 Applications Guide Rev 4 0 152 MC68HC705C8 Functional Data MOTOROLA For More
84. C 1 BLO BCS 25 BHS BCC 24 Unsigned Carry C BCS 25 No Carry BCC 24 Simple r 0 Zu BEQ 27 rzo BNE 26 Simple Negative N21 BMI 2B Plus BPL 2A Simple Mask 1 5 2 Mask 0 BMC 2 Half Carry H 1 5 29 No Half Carry BHCC 28 Simple IRQ Pin High 2 IRQ Low BIL 2E Simple Always E BRA 20 Never BRN 21 Unconditional r register or X m memory operand M68HC05 Applications Guide Rev 4 0 254 Instruction Set Details For More Information On This Product Go to www freescale com MOTOROLA BLS Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc Instruction Set Details M68HC05 Instruction Set Branch if Lower or Same B LS lt 0002 Rel if C Z 1 i e if ACCA lt M unsigned binary numbers Causes a branch if C is set or Z is set If the BLS instruction is executed immediately after execution of a CMP or SUB instruction the branch will occur if the unsigned binary number in ACCA was less than or equal to the unsigned binary number in M See BRA instruction for further details of the execution of the branch H 2 1 1 1 None affected Source Addressing Machine Code HCMOS BLS rel REL 23 rr 3 The following table is a summary of all branch i
85. C b7 Set if before the shift the MSB of ACCA or M was set cleared oth erwise Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Cycles Code and Cycles LSLA INH A 48 3 LSLX INH X 58 3 LSL opr DIR 38 dd 5 LSL X 78 5 LSL opr X IX1 68 ff 6 M68HC05 Applications Guide Rev 4 0 280 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com LSR Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc Instruction Set Details M68HC05 Instruction Set Logical Shift Right gt 0 b7 LSR Shifts all bits of ACCA X or M one place to the right Bit 7 is loaded with zero Bit 0 is shifted into the C bit N 0 Cleared 7 R7 R6 R5 eRA4 R3 R2 R1 RO Set if result is 00 cleared otherwise C Set if before the shift the LSB of ACCA X or M was set cleared oth erwise Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles LSRA INH A 44 3 LSRX INH X 54 3 LSR opr DIR 34 dd 5 LSR X IX 74 5 LSR opr X 64 ff 6 M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details For More Information On This Product Go to www freescale com 281 Freesc
86. For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Listing Thermostat Example Applications Thermostat Project Details Sheet 6 of 21 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK KK KKKKKKKK When When When When When 5 Update Time of day amp Day of week If TIC not 0 just skip EC rolls 59 IN rolls 59 R rolls 11 DAY rolls 7 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK KKK 2 MPM chgs 1 gt 0 whole routine gt 0 inc MIN gt 0 inc HR change AMPM 1 gt 0 or 0 gt 1 inc DAY set to 1 gt 8 Sun 018 Update Time of day 8 Day of week 018c 3d a2 TST TIC Check for TIC zero 018e 26 38 BNE XTIME If not just exit 0190 3c a3 INC SEC SEC SEC 1 0192 3c LDA 60 0194 bl a3 CMP SEC Did SEC gt 60 0196 26 30 BNE XTIME If not just exit 0198 3f a3 CLR SEC Seconds rollover 019a 3c a7 INC MIN MIN MIN 1 019 bl a7 CMP MIN A still 60 MIN 60 019 26 28 If not just exit 01 0 a7 CLR MIN Minutes rollover 01 2 3c HR HR 1 01 4 b6 LDA HR For comparisons 01 6 al Od CMP 13 HR 13 01 8 26 06 ARNS1 If not skip Olaa
87. LDA 01 0122 cd 06 20 JSR WCTRL Clear 0125 a6 02 LDA 502 0127 06 20 JSR WCTRL Home 012 38 LDA 538 012 06 20 JSR WCTRL Function Set 8 bit 2 1 5X7 012 Oc LDA 50 0131 06 20 JSR WCTRL Display on Cursor off 0134 06 LDA 506 0136 06 20 JSR WCTRL Entry mode Inc addr no shift M68HC05 Applications Guide Rev 4 0 214 Applications MOTOROLA For More Information On This Product Go to www freescale com Listing Thermostat Ex Freescale Semiconductor Inc Applications Thermostat Project Details ample Sheet 4 of 21 set time to 12 00 AM SUN 0139 3f a2 CLR TEC Init 50mS counter 013b 3f a3 CLR SEC Init seconds to 0 013d a6 Oc LDA 12 Hr 12 013 b7 5 HR 0141 a7 CLR MIN 00 0143 3f CLR AMPM AM 0 0145 01 LDA 1 Sun 1 Sat 7 0147 b7 a9 STA DAY Day Sunday 0149 3f bl CLR MODE Set user interface to inactive 014b 3f b3 CLR KEYVAL Say no key closed 014d CLR BEEPM Set beeper request to off 014f b2 CLR HVACON Indicate HVAC Equip not running now 0151 3f aa CLR HVACM Set HVAC Equip mode to off 0153 48 LDA 72 0155 b7 ab STA GOAL Set default goal temp to 72 F END of INITIALIZATION M68HC05 Applications Guide Rev 4 0 MOTOROLA Applications 215 For More I
88. MC68HC705C8 Functional Data OTPROM EPROM Programming SEC The SEC bit is implemented as a PROM bit During PROM programming the SEC bit is set to enable the security feature to disable the bootloader This bit is normally cleared security disabled for an OTPROM device For an EPROM device clearing is accomplished by exposing the EPROM to UV light until the SEC bit is erased Bit 2 Factory use logic one or logic zero IRQ When the IRQ bit is set logic one the IRQ pin is negative edge and level sensitive When the IRQ bit is cleared logic zero the IRQ pin is negative edge sensitive Reset sets the IRQ bit The IRQ bit can only be written once following each reset M68HCO05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 185 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data M68HCO05 Applications Guide Rev 4 0 186 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Guide M68HC05 4 1 Contents 4 2 Introduction Section 4 Applications A WU ect E RET was 187 43 Hardware Development Methods 189 4 4 Software Development 191 4 4 1 ocior dr d RERO dob ORE EIC 193 4 4 2 Third Party SOBMBIG 194 45 Ther
89. O register or RAM location in the 0000 through 00FF area of memory O B can be used to access any location in the 8K byte memory map O C can be used only with indexed addressing modes O D can be used to access any on chip RAM location 50 Which of the following statements best describes what happens during an SPI data transfer between two MC68HC705C8 MCUs A slave device transfers an 8 bit character to a master device A master device transfers an 8 bit character to a slave device O C Amaster and a slave exchange 8 bit data characters D A master device sends a start bit 8 data bits and a stop bit to a slave M68HC05 Applications Guide Rev 4 0 MOTOROLA Review Questions 317 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions B 4 Review Questions Answers and Explanations The questions that seem to give the most trouble are 40 35 and 13 in that order The problem on 35 is that it is a tricky question The loop in PROG4 must be executed twice to make one period on the port pin On 40 some persons who got the wrong answer seemed to be tricked by the indirect nature of this operation and chose D thinking it was the closest thing to a correct answer Almost all those who got 35 wrong chose A which has the longest loop time but not the longest period The majority of those who missed 13 seemed to think that the RAM locations
90. Product Go to www freescale com Freescale Semiconductor Inc Review Questions 18 How many bit times are there in one SCI character frame O 8 O 9 10 gt D 10 or 11 see Figure 3 30 Data Formats Dont forget to count the start and stop bit times 19 To assure an orderly startup reset forces the CPU to begin executing instructions in a predictable repeatable way Which of the following statements best describes how the CPU proceeds from reset O A The CPU fetches the instruction from 1FFF and executes it O B The CPU loads the program counter PC register with the address 1FFE and begins executing instructions O C The CPU begins executing instructions starting at address 0000 gt D The CPU loads the program counter PC with the address stored at 1FFE 1FFF and then begins executing instructions starting at that address See 2 4 3 CPU Registers Think about the other three answers you should see that they do not make sense 20 change the SCI baud rate what address would you write to gt A 0000 000 0000 D 100 See memory Figure 2 4 Typical Memory or Figure 3 7 MC68HC705C8 Memory Map or see Figure 3 23 Baud Rate Register See also 2 4 5 Memory Maps M68HCO5 Applications Guide Rev 4 0 324 Review Questions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review
91. Rev 4 0 296 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com SUB Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc Subtract ACCA lt ACCA Instruction Set Details M68HC05 Instruction Set SUB Subtracts the contents of M from the contents of ACCA and places the result in ACCA N R7 Set if MSB of result is set cleared otherwise 7 R7 R6 R5 R4 R3e eR2 R1 Set if all bits of the result are cleared cleared otherwise 7 7 7 7 R7 7 The bit carry flag in the condition code register gets set if the ab solute value of the contents of memory is larger than the absolute val ue of the accumulator cleared otherwise Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles SUB opr IMM 0 2 SUB opr DIR BO dd 3 SUB opr EXT CO hh I 4 SUB X IX FO 3 SUB opr X 1 EO ff 4 SUB opr X 2 DO ee ff 5 M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details For More Information On This Product Go to www freescale com 297 Freescale Semiconductor Inc Instruction Set Details SWI Operation Description Condition Codes and Boolean Software Interrupt SWI
92. Row 4 Col 1 Row 1 Col 2 Row 2 Col 2 Row 3 Col 2 Row 4 Col 2 Row 1 Col 3 Row 2 Col 3 Row 3 Col 3 Row 4 Col 3 Row 1 Col 4 Row 2 Col 4 Row 3 Col 4 Row 4 Col 4 Bot Right Figure 4 10 Keypad Checkout Program Listing Sheet 2 of 2 210 Applications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Thermostat Project Details MEASURE 50mS INTERVALS SCHEDULE NEXT OCF TO OCCUR IN 50mS AND CLEAR OCF FLAG MODULE 20 COUNTER TO COUNT 50 5 TICs gt TIC COUNTS 0 1 2 18 19 0 ETC TWENTY 50mS TICs EQUAL 1 SECOND ARNCL Figure 4 11 Main Program Flowchart MAJOR TASK SUBPROGRAMS MODULES EACH IS CALLED ONCE PER 50mS THOUGH gt ASUBPROGRAM MAY DECIDE TO DO LITTLE OR NOTHING DEPENDING ON THE STATE OF VARIABLES SUCH AS TIC M68HC05 Applications Guide Rev 4 0 MOTOROLA Applications 211 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Listing Thermostat Example Sheet 1 of 21 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK MC68HC705C8 Example Development Project x R A Home Thermostat with indoor outdoor R temperature and time of day x This example uses an LCD disp
93. Semiconductor Inc Applications Guide M68HC05 1 2 1 3 1 4 1 5 1 6 1 7 2 1 2 2 2 3 2 4 2 4 1 2 4 2 2 4 3 2 4 4 2 4 5 2 5 2 6 2 6 1 2 6 2 2 6 3 Table of Contents Section 1 General Description CEDE Se ee re ee er ee er ee eee eee 21 VON dalek ap TT 21 eee E d NUR 22 lo edil i bh ee ke 23 Computer Systems Description 24 Microcontroller Applications Overview 26 Project Vnitr dcc OR 27 Section 2 Microcontroller Operation HO eee ee 29 IARE ah DoD ao Re de dee den 30 Number Systems 31 Computer oc RET 34 Computer 22 deduce ud aw adea ran qd ud md 36 Computer 37 albo o c eee 38 Memory TT 40 Menon ch ch T TO OE 42 44 iid dco ode d ERR 45 FONERA Ld a Rode CERE HR Ob OE ob d ERR D UR RON 46 Mnemonic Source 46 Software Delay Program 49 M68HCO05 Applications Guide Rev 4 0 MOTOROLA Table of Contents 7 For More Information On This Product Go to www freescale com Freescale Semiconducto
94. The thermostat could include a timed setback feature that allows specifying certain times of the day when there will be reduced demand for heating or air conditioning thus giving some energy savings A more unusual feature would be to measure the outdoor temperature and control the indoor to outdoor temperature difference This would be very difficult to accomplish with a conventional electromechanical thermostat M68HCO05 Applications Guide Rev 4 0 MOTOROLA General Description 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description DATA ENTRY CRYSTAL LCD DISPLAY KEYPAD ae LILILILI INTERFACE INDOOR MICROCONTROLLER TEMPERATURE SENSOR OUTDOOR TEMPERATURE SENSOR Figure 1 3 Thermostat Project Block Diagram The four fundamental elements of this system are inputs outputs time and a microcontroller to tie the other elements together The inputs include push buttons a keypad to enter time and temperature information into the MCU and sensors to measure the indoor and outdoor temperatures Outputs include a display to show system conditions and signals to the interfaces that control the heating and air conditioning equipment Time is derived from a crystal connected to the MCU As we will see later this crystal would be used by the CPU even if the application did not have time of da
95. Unsigned lt C Z 1 BLS 23 r gt m BHI 22 Unsigned r lt m C 1 BLO BCS 25 gt 5 24 Unsigned Carry 1 BCS 25 No Carry BCC 24 Simple r 0 2 1 27 r 0 BNE 26 Simple Negative N 1 BMI 2B Plus BPL 2A Simple Mask 1 5 2D Mask 0 BMC 2 Half Carry H 1 BHCS 29 No Half Carry BHCC 28 Simple Pin High 2F IRQ Low BIL 2 Always BRA 20 Never BRN 21 Unconditional r register ACCA or X m memory operand M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details 263 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc BRSET n Branch if Bit n is Set BRSET n Operation PC lt 0003 Rel if bit n of M 1 Description Tests bit n n 2 7 6 5 0 of location M and branches if the bit is set M can be any RAM or register address in the 0000 to 00FF area of memory i e direct addressing mode is used to specify the address of the The C bit is set to the state of the bit tested When used along with an appropriate rotate instruction BRSET n provides an easy method for performing serial to parallel conversions Condition Codes and Boolean H 7 1 Setif Mn 1 cleared otherwise Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode
96. WAKEUP METHOD SELECT 0 IDLE LINE 1 ADDRESS MARK SELECT SCI DATA LENGTH 0 8 BITS 1 9 BITS L NINTH TRANSMIT BIT IF M 1 NINTH RECEIVE IF M 1 Figure 3 25 Serial Communications Control Register One 3 11 3 3 Serial Communications Control Register Two SCCR2 The serial communications control register two SCCR2 shown in Figure 3 26 is the main control register for the SCI subsystem This register can enable disable the transmitter or receiver enable the system interrupts and provide the wakeup enable bit and a send break code bit The TIE TCIE RIE and ILIE bits are local interrupt enable controls which determine whether SCI status flags will be polled or generate hardware interrupt requests BIT BIT 0 7 6 5 4 3 2 1 Cx Tue Te s sem 0 0 0 0 0 0 0 0 RESET CONDITION SEND BREAK RECEIVER WAKEUP FUNCTION ENAB LE SCI RECEIVER ENABLE SCI TRANSMITTER IDLE LINE INTERRUPT ENABLE RECEIVER INTERRUPT ENABLE TRANSMISSION COMPLETE INTERRUPT ENABLE TRANSMITTER INTERRUPT ENABLE Figure 3 26 Serial Communications Control Register Two M68HCO05 Applications Guide Rev 4 0 144 MC68HC705C8 Functional Data For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc MC68HC705C8 Functional Data Serial Communications Interface SCI In a typical system TE a
97. Z bit and causes a branch if Z is set The following is a list of all M68HCO5 instructions that can use the relative addressing mode Instruction Mnemonic Branch if Carry Clear BCC Branch is Carry Set BCS Branch if Equal BEQ Branch if Half Carry Clear BHCC Branch if Half Carry Set BHCS Branch if Higher BHI Branch if Higher or Same BHS Branch if Interrupt Line is High BIH Branch if Interrupt Line is Low BIL Branch if Lower BLO Branch if Lower or Same BLS Branch if Interrupt Mask is Clear Branch if Minus BMI M68HCO05 Applications Guide Rev 4 0 114 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Addressing Modes Instruction Mnemonic Branch if Interrupt Mask Bit is Set BMS Branch if Not Equal BNE Branch if Plus BPL Branch Always BRA Branch if Bit n is Clear BRCLR Branch if Bit n is Set BRSET Branch Never BRN Branch to Subroutine BSR 3 7 7 Bit Test and Branch Instructions These instructions use direct addressing mode to specify the location being tested and relative addressing to specify the branch destination This applications guide treats these instructions as direct addressing mode instructions Some older Motorola documents call the addressing mode of these instructions BTB for bit test and branch 3 7 8 Instructions Organized by Type Table 3 2 through Table 3 5 show the MC68HC05 instruc
98. a branch instruction which depends on a condition code bit is encountered you can mentally work backwards to decide whether or not the branch should be taken Next the storage of values on the stack would be skipped although it is still a good idea to keep track of the SP value because itis fairly common to have programming errors resulting from incorrect values in the SP A fundamental operating principle of the stack is that over a period of time the same number of items must be removed from the stack as were put on the stack Just as left parentheses must be matched with right parentheses in a mathematical formula JSRs and BSRs must be matched one for one to subsequent RTSs in a program Errors which cause this rule to be broken will appear as erroneous SP values while playing computer Even an experienced programmer will play computer occasionally to solve some difficult problem The procedure the experienced programmer would use is much less formal than what was explained here but it still amounts to placing yourself in the role of the CPU and working out what happens as the program is executed 2 8 On Chip Peripherals A peripheral is a block of circuitry which performs some useful function under control of the CPU One example of a peripheral is a universal asynchronous receiver transmitter UART which acts as an interface between a computer and an asynchronous serial communication link The most common example of such a communica
99. ae 12 LDX 18 Offset to FAN must be 0468 d6 06 68 HVD LDA 04bb al 04 CMP 4 End of message 04 27 06 BEQ DUNHVD If so skip ahead 04bf cd 06 3a JSR WDAT Else display nxt char 04c2 5c INCX Point at next 0483 20 3 BRA HVD Continue loop 04c5 b6 ab DUNHVD LDA GOAL Goal temp setting 04c7 be bl LDX MODE Get mode in X 04c9 a3 06 CPX 6 Mode GOAL set 04cb 26 02 Skip if not 6 04 a5 LDA ENTRY Use ENTRY rather than GOAL 04cf cd 06 a6 AEG JSR CNVERT Convert to ASCII 04 2 cd 06 56 JSR SHOW2 Display as 2 digits 04d5 cd 06 5 JSR LCDDF Display 04d8 5f CLRX Loop index 04d9 d6 06 85 LPSOT LDA MSOUT X Get message character 04dc cd 06 3a JSR WDAT Send to LCD 04df 5c INCX Nxt char of OUT 04e0 a3 05 CPX 5 04 2 26 5 LPSOT Loop for 5 characters 04 4 ad LDA OUTMP Outdoor temp 04 6 cd 06 JSR CNVERT Convert to ASCII 04 9 06 52 JSR SHOW3 Display as 3 digits 04ec cd 06 5f JSR LCDDF Display O4ef 81 RTS RETURN from DSPLAY M68HC05 Applications Guide Rev 4 0 228 Applications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Thermostat Project Details Listing Thermostat Example Sheet 18 of 21 0600 ORG 0600 Temp ORG to get subs away from main KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK SUBROUTINES amp CONSTANT TABLES FR k k k
100. an expanded flowchart of the 50 ms delay subroutine A subroutine is a relatively small program which performs some commonly required function Even if the function needs to be performed many times in the course of a program the subroutine only has to be written once Each place where this function is needed the programmer would call the subroutine with a branch to subroutine BSR or jump to subroutine JSR instruction START SUBROUTINE 6 SR SAVE ACCUMULATOR DLY50 STA TEMPI 4 LOAD VALUE CORRESPONDING 505 LDA 82 2 _ gt OUTLP A INNRLP 3 1 DECREMENT COUNT a ET hu 2 DECA 3 NO COUNT EXPIRED BNE OUTLP 3 Y 2 YES RESTORE ACCUMULATOR TEMPI 3 RETURN FROM SUBROUTINE RTS 6 Figure 2 7 Delay Routine Flowchart and Mnemonics Before starting to execute the instructions in the subroutine the address of the instruction which follows the JSR or BSR is automatically stored in temporary RAM memory locations When the CPU finishes executing the instructions within the subroutine a return from subroutine RTS instruction is performed as the last instruction in the subroutine The RTS instruction causes the CPU to recover the previously saved return M68HC05 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation 49 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation a
101. architecture encompasses the most important concepts of digital binary computers thus the information presented in this applications guide will be applicable even if you go on to study other architectures The number of wires in the address bus determines the total possible number of pigeon holes the number of wires in the data bus determines the amount of information that can be stored in each pigeon hole In the MC68HC705C8 the address bus is 13 bits making a maximum of 819249 separate pigeon holes in MCU jargon you would say this CPU can access 8K locations Since the data bus in the MC68HC705C8 is eight bits each pigeon hole can hold one byte of information One byte is eight binary digits or two hexadecimal digits or one ASCII character or a decimal value from 0 to 255 Different CPUs have different sets of CPU registers The differences are primarily the number and size of the registers Figure 2 2 shows the CPU registers found an M68HCO5 While this is a relatively simple set of CPU registers it is representative of all types of CPU registers and can be used to explain all of the fundamental concepts The A register an 8 bit scratch pad register is also called an accumulator because it is often used to hold one of the operands or the result of an arithmetic operation The X register is an 8 bit index register which can also serve as a simple scratch pad The main purpose of an index register is to point at an area in
102. by computers M68HC05 Applications Guide Rev 4 0 30 Microcontroller Operation MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation Number Systems NES OSCILLATOR mm AND oen CLOCKS CENTRAL PROCESSOR UNIT CRYSTAL CPU RESET PROGRAM MEMORY POWER m ADDRESS BUS DATA MEMORY GROUND 10 AND PERIPHERALS gt DIGITAL DIGITAL INPUTS 4 OUTPUTS gt Figure 2 1 MCU Expanded Block Diagram 2 3 Number Systems Computers work best with information in a different form than people use Humans typically work in the base 10 decimal numbering system probably because we have ten fingers Digital binary computers work in the base 2 binary numbering system because this allows all information to be represented by sets of digits which can only be zeros or ones In turn a one or zero can be represented by the presence or absence of a logic voltage on a signal line or the on and off states of a simple switch M68HC05 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation 31 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation In decimal base 10 numbers the weight of each digit is ten times as great as the digit immediately to its right The rightmos
103. create a prototype system Figure 3 5 is the schematic diagram for a simple MC68HC705C8 system This circuit can be used as the basis for any MC68HC705C8 application In most cases the circuitry for the power supply and oscillator can be used as shown in this diagram All unused inputs are terminated in an appropriate manner M68HCO05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 85 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data MC68HC705C8 Vpp 10k TYP AVAVA AVAVA A A AJ SYSTEM 20 ZIL POWER a nee RA d ANN 10M AA A 4 0 MHz PB4 5 A A V 9 PB6 A A N ZH Aut PULLUP 18pp 18pF PB7 9 RESISTORS RECOMMENDED ai FOR s PCO UNUSED A A VN INPUTS PC2 PC3 34064 As 1 4 7k 5 A A J 9 PC6 RESET GND PDO RDI PDI TDO NAN Vpp PD2 MISO A A N PD3 MOSI A A N 41k 04 5 A A NJ d PD5 SS PD7 A A N d Figure 3 5 Typical Basic Connections M68HC05 Applications Guide Rev 4 0 86 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor I
104. down into four sets of three bits each The second problem was that octal is not as compact as hexadecimal For example the ASCII value for capital A is 10000012 in binary 4116 in hexadecimal and 1018 in octal When a human is talking about the ASCII value for A it is easier to say four one than it is to say one zero one When mentally translating from hexadecimal to binary it is easy to convert each hexadecimal digit into four binary bits It is more difficult to make the octal to binary translation because you have to remember to throw away the leading zero of the first group of three binary bits You probably had to think twice about that last statement and that is exactly the point Binary coded decimal BCD is a hybrid notation used to express decimal values in binary form BCD uses four binary bits to represent each decimal digit Since four binary digits can express 16 different M68HC05 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation 35 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation physical quantities there will be six bit value combinations that are considered invalid specifically the hexadecimal values A through F Values are kept in pseudo decimal form during calculations When the computer does a BCD add operation it performs a binary addition and then adjusts the result back to BCD form As a simple ex
105. for a 2 MHz crystal M68HC05 Applications Guide Rev 4 0 162 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Programmable Timer The SPCR needs to be initialized once For each transfer there is a four step sequence 1 Enable the slave In this example the general purpose output provides the enable signal to the MC74HC595 peripheral 2 Write data to SPDR to initiate the transfer 3 Wait for SPIF The slave cannot be disabled until the transfer is finished 4 Disable the slave The flowchart and mnemonics for the SPI application example are shown in Figure 3 41 Assume this application program has been assembled and downloaded to an MC68HC705C8 You can test this program by using an oscilloscope connected to the MC74HC595 parallel data outputs pins 1 7 and 15 The program is arranged to increment the 8 bit parallel bit value each time the switch is pressed Figure 3 42 is the complete listing for the SPI application example program 3 14 Programmable Timer The programmable timer can be used for many purposes including input waveform measurements while simultaneously generating an output waveform The architecture of the main timer is primarily a software driven system Software can be written for measuring pulse widths and frequencies for controlling timer output signals or for timing
106. frequency This system is based on a free running 16 bit counter a 16 bit output compare register and a 16 bit input capture register The CPU controls the timing of output signals through the output compare mechanism To schedule an output change to occur at a specific time a specific count of the free running counter a 16 bit value corresponding to the desired time is written to the output compare register When the free running counter matches the value in the output compare register the planned output change occurs The CPU detects the time of an event or measures the period of an input signal with the input capture mechanism The CPU can select either positive or negative edges detected on an MCU pin to trigger the input capture mechanism When the selected edge occurs the current value in the free running counter which corresponds to the time the edge occurred is captured by transferred to the input capture register The CPU can later read the value in the input capture register and determine the exact time when the edge occurred M68HC05 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation 71 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation 2 8 4 Memory Peripherals Memory systems are also a form of peripheral The uses for different types of memory were discussed earlier but the logic required to support these memories was
107. have a convenient way to track locations A memory map is a pictorial representation of the total MCU memory space Figure 2 4 is a typical memory map showing a subset of the memory resources in the MC68HC705C8 Some memory areas reserved for Motorola use were purposely left out of this figure to make it easier to understand The complete version of this memory map can be found in the Figure 3 7 MC68HC705C8 Memory Map M68HCO5 Applications Guide Rev 4 0 42 Microcontroller Operation MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation Computer Codes 0000 PORT DATA REGISTER 00 32 BYTES PORT B DATA REGISTER 01 001F PORT C DATA REGISTER 02 0020 PORT D FIXED INPUT REGISTER 03 MOTOROLA USE SEE INSET PORT A DATA DIRECTION REGISTER 04 48 BYTES PORT B DATA DIRECTION REGISTER 05 PORT DATA DIRECTION REGISTER 06 004F UNUSED 07 0050 UNUSED 08 UNUSED 09 RAM SPI CONTROL REGISTER 0A 176 BYTES SPI STATUS REGISTER 0B 00BF SPIDATA 1 0 REGISTER 0 500 0 SCI BAUD RATE REGISTER 00 SCICONTROL REGISTER 1 0 64 BYTES SCI CONTROL REGISTER 2 0F 00FF SCISTATUS REGISTER 10 0100 SCI DATA REGISTER 11 TI
108. in the stack are cleared as values are recovered from the stack during a return from subroutine this assumption is incorrect A few others got the stacking order reversed The key to getting 13 right was to play computer very carefully 1 The instruction set of a CPU is O A a software program written by an end user O B the same for all computers gt C determined by the wiring within the CPU See 2 3 Number Systems and 2 4 Computer Codes O D the data sheet for a microprocessor 2 Which numbering system offers the best compromise between the needs of a CPU and those of a human O A Binary O B Octal O C Decimal gt D Hexadecimal See 2 3 Number Systems and 2 4 Computer Codes A few engineers who were around in the days of the PDP 8 or work a lot with minicomputers that still carry on the octal tradition may argue about this answer The text 2 4 Computer Codes and modern microcontroller data sheets explain why hexadecimal is the best choice M68HC05 Applications Guide Rev 4 0 318 Review Questions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions Review Questions Answers and Explanations A specific 8 bit value in a computer memory can mean different things depending on its context The value could be a number a code representing an alphabetic character a code for an instruction opcode etc The hexadecimal value 42 c
109. is executed regardless of the state of the interrupt mask I bit in the condition code register The interrupt service routine address is specified by the contents of memory location 1FFC and 1FFD M68HC05 Applications Guide Rev 4 0 MC68HC705C8 Functional Data 129 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc MC68HC705C8 Functional Data FROM RESET lt I BIT IN CC REGISTER SET YES NO EXT IRQ INTERRUPT CLEAR IRQ REQUEST LATCH INTERN TIMER INTERRUPT STACK A SET I BIT IN CC REGISTER INTERNAL SCI INTERRUPT INTERN LOAD PC FROM VECTOR SPI INTER IRQ 1FFA 1FFB TIMER 1FF8 1FF9 SCI 1FF6 1FF7 NO SPI 1FF4 1FF5 FETCH NEXT INSTRUCTION RTI YES RESTORE REGISTERS INSTRUCTION FROM STACK f CC A X PC NO EXECUTE INSTRUCTION Figure 3 14 Hardware Interrupt Flowchart M68HC05 Applications Guide Rev 4 0 130 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Interrupts TOWARD LOWER ADDRESSES LOWEST STACK ADDRESS 15 00 0 INTERRUPT RETURN TOWARD HIGHER ADDRESSES HIGHEST STACK ADDRESS IS 00FF NOTE When an interrupt occurs CPU regist
110. is this value being read It may be helpful to look at the machine code as well as the mnemonic instructions 0003 SAM 03 SAM equal 8 bit value 1400 LARRY EQU 1400 LARRY equal a 16 bit value 0100 ORG 100 Set program starting point 0100 ae 02 TOP LDX 502 Initialize index register 0102 d6 14 00 LDA LARRY X Read value into O A 0002 O B 1400 O C 1402 O D 1600 After executing the following instruction sequence from START to END what value will be in the stack pointer SP 0100 9 START RSP Reset SP to SOOFF 0101 cd 02 00 JSR SUB Call SUB 0104 cd 02 00 JSR SUB Call SUB again 0107 9d END NOP Done 0200 81 SUB RTS Just Return O A 0200 O B 00FB O C 00FD O D 00FF A microcontroller is O A the CPU part of a digital binary computer O B the same thing as a microprocessor O C any system that includes an MCU integrated circuit O D acomputer system including a CPU memory and peripherals a single M68HC05 Applications Guide Rev 4 0 312 Review Questions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions Review Questions 32 After executing the following instruction sequence from TOP to BOT what values will be in locations 00A0 and 00A1 respectively 0100 0102 0104 0106 0108 010 010 010 0110 A 00A0 00A1 11110011 b
111. is used to identify which pigeon hole is being accessed and the data bus is used to convey information either from the CPU to the memory location pigeon hole or from the memory location to the CPU In the Motorola implementation of this architecture there are a few special pigeon holes called CPU registers inside the CPU which act as a small scratch pad and control panel for the CPU These CPU registers are similar to memory in that information can be written into them and remembered However it is important to remember that these registers are directly wired into the CPU and are not part of the addressable memory available to the CPU All information other than the CPU registers accessible to the CPU is envisioned by the CPU to be in a single row of several thousand pigeon holes This organization is sometimes called a memory mapped system because the CPU treats all memory locations alike whether they contain program instructions variable data or input output controls There are other computer architectures but this applications guide is not intended to explore these variations Fortunately the M68HC05 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation 37 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation 2 4 3 CPU Registers Motorola architecture we are discussing is one of the easiest to understand and use This
112. larger An audible alarm can be used along with the display if desired The project parts list is shown in Table 4 1 Only the parts not commonly available are listed Table 4 1 Thermostat Project Parts List Item and Description Suggested Source LCD Display Module 20 Characters by 2 Lines Digi Key Wholesale OP220 ND Keypad 4 by 4 Matrix of Momentary Push Button Switches Any Piezo Beeper Solid State Buzzer Radio Shack 273 060A A D Converter Serial Interface to SPI Motorola Special Functions MC145041 Relay Driver Translates 0 5 V MCU Signals to High Current Inductive Load Drive Motorola Interface MC1413 or ULN2003 Relays Coil 5 V Contacts 24 VAC 1A SPST Minimum Radio Shack 275 243 or Other Op Amp For Precision Temp Sensor Circuits QUAD Op Amp Motorola Linear LM324 Precision Temperature Sensor TO 92 Pkg National Semiconductor LM34C 1 This is only a partial parts list Parts commonly found in lab stock are not shown M68HCO05 Applications Guide Rev 4 0 MOTOROLA Applications For More Information On This Product Go to www freescale com 199 Freescale Semiconductor Inc Applications 4 5 2 Project Programming M68HC05 Applications Guide Rev 4 0 Figure 4 3 through Figure 4 6 MCU port summary information act as a handy reference to the software programmer in the thermostat proje
113. light for about one second and then go out The LED will not light again until the switch has been released and closed again The length of time the switch is held closed will not affect the length of time the LED is lighted Although this program is very simple it demonstrates the most common elements of any MCU application program First it demonstrates how a program can sense input signals such as switch closures Second this is an example of a program controlling an output signal Third the LED on time of about one second demonstrates one way a program can be used to measure real time Because the algorithm is sufficiently complicated it cannot be accomplished in a trivial manner with discrete components at minimum a one shot IC with external timing components would be required This example demonstrates that an MCU and a user defined program software can replace complex circuits M68HCO05 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation 45 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation 2 6 1 Flowchart Figure 2 5 is a flowchart of the example program Flowcharts are often used as a planning tool for writing software programs because they show the function and flow of the program under development The importance of notes comments and documentation for software cannot be overemphasized Just as you would not consider a circu
114. many applications The timing of the main loop determines the delays between activities in the complete application program A real time of day clock can easily be developed using the main loop time and simple software counters Figure 4 11 is the flowchart for this basic loop structure The complete listing for the thermostat project is included at the end of this section After a reset there are a series of instructions to initialize ports peripheral systems and software variables After this initialization the main loop is entered and repeated continuously as long as power is applied M68HC05 Applications Guide Rev 4 0 MOTOROLA Applications 207 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications KEYTRY NO YES NO NEXT TABLE ENTRY POINTER POINTER 2 INIT MCU HARDWARE PORTS GET ROW COL PATTERN FROM TABLE AND DRIVE COLUMNS DELAY 50mS DEBOUNCE POINT AT LAST TABLE ENTRY gt KYLOOP FOUND READ ASCII FROM TABLE AND DISPLAY ON LCD 1ST ROW LEFT TILRLS DELAY 50mS DEBOUNCE Figure 4 9 Keypad C M68HC05 Applications Guide Rev 4 0 heckout Flowchart 208 Applications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Thermostat Project Details KKKK
115. not discussed ROM and RAM memories are very straightforward and require no support logic other than address select logic to distinguish one location from another EPROM erasable programmable ROM and EEPROM electrically erasable programmable ROM memories require support logic for programming and erasure in the case of EEPROM The peripheral support logic the MC68HC705C8 is like having a PROM programmer built into the MCU A control register includes control bits to select between programming and normal modes and to enable the high voltage programming supply 2 8 5 Other On Chip Peripherals There are many other peripherals available on MCUs see other members of the M68HC05 Family of MCUs These other peripherals include analog to digital A D converters liquid crystal display drivers LCD and vacuum fluorescent display drivers VFD M68HC05 Applications Guide Rev 4 0 72 Microcontroller Operation MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Guide M68HC05 3 1 Contents Section 3 MC68HC705C8 Functional Data cor 76 33 3 REC COO 77 3 3 1 Hardware 77 3 3 2 SOONG lt 78 2 224 General lt 78 Fins and
116. of a common piece of hardware since only the control program needs to be changed M68HC05 Applications Guide Rev 4 0 MOTOROLA General Description 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description 1 5 Computer Systems Description Whatever their size all computer systems consist of the same fundamental parts CPU I O devices memory program s and a timing reference clock as shown in Figure 1 1 The CPU processes information in accordance with a program of instructions and data in a particular language called machine code The CPU controls all the system operations and provides control signals for enabling and disabling the various peripherals and I O devices Input devices supply information to the MCU from the outside world Some input devices convert analog signals into digital signals that the MCU can understand and manipulate Other input devices translate real world information into the 0 to 5 Vdc signals required by MCUs Examples of this are a temperature sensor a switch a keypad anda typewriter style keyboard A computer system might have one number of these input devices PROGRAM mea SWITCH FETE LCD DISPLAY E INPUTS CENTRAL OUTPUTS PROCESSOR UNIT V CPU V BEEPER KEYPAD a TEMPERATURE SENSOR CRYSTAL Figure 1 1 A T
117. of the free running counter once during every four internal processor clocks If a match is found the output compare flag OCF bit is set and the output level OLVL bit is clocked by the output compare circuit pulse to the TCMP pin After a processor write cycle to the most significant byte of the output compare register 16 the output compare function is inhibited until the least significant byte 17 is also written You must write to both bytes locations if the most significant byte is written first Because neither the output compare flag OCF bit or output compare register is affected by reset take care when initializing the output compare function with software The following procedure is recommended 1 Write to the high byte of the output compare register to inhibit fur ther compares until the low byte is written 2 Read the timer status register to clear the CCF bit if it is already set 3 Write to the low byte of the output compare register to enable the output compare function The purpose of this procedure is to prevent the OCF bit from being set between the writes to the high and low halves of the 16 bit output compare register A software example follows B7 16 STA OCMPHI Inhibit output compare B6 13 LIDA TSR Clear OCF bit if set BF 17 STX OCMPLO Ready for next compare M68HC05 Applications Guide Rev 4 0 174 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go t
118. on chip timer system Refer to output compare register in 3 14 Programmable Timer 3 4 1 7 OSC1 and OSC2 The MC68HC705C8 can accept either a crystal ceramic resonator or external input to control the internal oscillator The internal processor clock is derived by dividing the oscillator frequency fosc by two The circuit shown in Figure 3 4 a is recommended when using crystal The internal oscillator is designed to interface with an AT cut parallel resonant quartz crystal or a ceramic resonator up to 4 MHz The crystal and components should be mounted as close as possible to the input pins to minimize output distortion and startup stabilization time A ceramic resonator may be used in place of the crystal in cost sensitive applications The circuit in Figure 3 4 a is recommended when using ceramic resonator or a crystal The manufacturer of the particular ceramic resonator being considered should be consulted for specific information An external clock be applied to the OSC1 input with the OSC2 pin not connected as shown in Figure 3 4 b 3 4 1 8 PA7 PAO These eight I O lines comprise port A Each port A pin can be software programmed to act as an input or output 3 4 1 9 7 These eight lines comprise port B Each port B pin can be software programmed to act as an input or output M68HCO05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 83 For More Information On This Pr
119. peripheral systems These displays help programmer understand the operation of a program under development better than the other methods of software development A simulator can show internal conditions that are not visible from outside the MCU In other development methods the programmer has to deduce this information indirectly Two disadvantages of the simulator approach are operating speed and accuracy of emulation In terms of speed the simulator runs much slower than a real MCU would although this is often fast enough so the programmer does not notice any problems Since simulators are based on a software emulation of specified MCU operation there can be subtle differences between the way the simulator behaves and the way a real MCU behaves Ideally these differences are small enough not to be significant in reality the differences sometimes cause problems M68HC05 Applications Guide Rev 4 0 194 Applications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Software Development Methods A compiler is similar to an assembler but it translates a higher level language into a machine readable object file rather than translating mnemonic assembly language One common high level language is The object of programming in C or some other high level language instead of assembly language is to improve productivity and to avoid learning the assembl
120. program Each instruction opcode tells the CPU how many if any and what type of operands go with that instruction In this way the CPU can remain M68HCO05 Applications Guide Rev 4 0 54 Microcontroller Operation MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation CPU Operation aligned to instruction boundaries even though the mixture of opcodes and operands looks confusing to us Most application programs would be located in ROM EPROM or OTPROM This example program is loaded into an area of RAM to avoid having to program and later erase the EPROM There is no special requirement that instruction must be ina ROM type memory to execute As far as the CPU is concerned any program is just a series of binary bit patterns which are sequentially processed Carefully study the program listing in Figure 2 9 and the memory map of Figure 2 10 Find the first instruction of the DLY50 subroutine in Figure 2 9 and then find the same two bytes in Figure 2 10 You should have found the following line from near the bottom of Figure 2 9 00c3 b7 9f DLY50 STA TEMP 1 Save accumulator in PAM The outlined section of memory in Figure 2 10 is the area you should have identified 2 7 CPU Operation This section will first discuss the detailed operation of CPU instructions and then explain how the CPU would execute the example program The detailed descr
121. red LED on PGMR board 0358 b7 02 STA PORTC Red LED will change every 10 Sec 035a 27 LDA 39 10 sec 38 rev 9 632 ticks 035 b7 STA TENSEC Counter for timer out compares xk CK ck Ck C CK Ck Ck CK CC CC Ck Ck CK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KKK KKK KKK CK Sk Ck Ck kk Sk Pk Sk kx ke kx X For XTAL 2MHz Int proc clk 1MHz Timer 4 makes 1 count 4 5 Counter rolls from SFFFF to 0 every 65 536 counts 262 144 mS 10 Sec 262 144 mS 38 revs of timer amp 9 632 counts remainder 10 Sec 2 500 000 counts 4uS count 38 65 536 2 490 368 2 500 000 2 490 368 9632 9632 decimal 25A0 time 10 Sec read initial count add 9632 remainder count store to out compare reg Schedule a compare When OCF flag 1 clear it amp next compare will occur when timer counts 65 536 counts count the first compare plus 3B more compares full revs Ck Ck CK Ck Ck CK Ck Ck C CK Ck C CK CC SCC CK Ck Ck CK Ck C CK Ck Ck CK kc Ck CK Ck Ck CK CI Ck CK Ck Ck Ck Ck Ck CK Ck Ck CC Ck CK Ck Ck Ck Ck CK Sk Ck Ck Sk Sk Pk Sk kx ke kx 035e a6 a0 LDA 5 0 Lower half hex equiv of 9632 0360 bb 17 ADD OCMP LO Low half of a 16 bit add 0362 b7 al STA TEMP Temp store until OCMPHI is added 0364 25 LDA 525 Upper half hex equiv of 9632 0366 b9 16 ADC OCMPHI High half of 16 bit add w carry 0368 b7 16 STA
122. that an edge has been detected anda local interrupt enable bit to determine whether or not the corresponding input capture function will generate a hardware interrupt request See Figure 3 45 15 8 7 0 COUNTER HIGH BYTE COUNTER LOW BYTE EE NENNEN D 16 BIT INPUT CAPTURE LATCH STATUS FLAG IEDG 0 FOR FALLING EDGES REQUEST ATIMER IEDG 1 FOR RISING EDGES INTERRUPT ICIE Figure 3 45 Input Capture Operation EDGE SELECT AND DETECT The two 8 bit registers locations 14 most significant byte and 15 least significant byte comprising the 16 bit input capture register are read only and are used to latch the value of the free running counter after a defined transition is sensed by the corresponding input capture edge detector The level transition which triggers the counter transfer is defined by the input edge bit IEDG in the timer control register The free running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag ICF is set or clear There is an uncertainty about the exact value latched due to the resolution of the counter and synchronization delays The input capture register always contains the free running counter value which corresponds to the most recent input capture Reset does not affect the contents of the input capture register M68HCO05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 F
123. the freeware BBS M68HC05 Applications Guide Rev 4 0 MOTOROLA Applications 195 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications 4 5 Thermostat Project Details The major steps for the project to be developed are as follows 1 Select the application in this case a home thermostat 2 Define the functions desired for the thermostat a b d e Read display existing indoor outdoor temperature Enter display desired indoor outdoor temperature Enter display time of day Select heating or cooling Operate heater or compressor 3 Determine the hardware required based on the functions a b m xx 7 Q i j k A microcontroller 68 705 8 Temperature sensing devices A D converters MC 145041 Keypad Display Relays relay drivers Audible alarm device Pullup resistors Bypass capacitors Power supply Circuit board 4 Develop simple programs to test the hardware circuits Develop the main program for the desired functions The program s to be written for this project are as follows a b M68HCO5 Applications Guide Rev 4 0 A program to test the audible alarm A program to test the display A program to test the display and keypad A program to test the basic software organization 196 Applications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semi
124. the sequence ASL LOW ROL MID ROL HIGH could be used where LOW MID and HIGH refer to the low order middle and high order bytes of the 24 bit value respectively N R7 Set if MSB of result is set cleared otherwise Z R7 e R6 e R5 e R4 e R2 e R1 Set if result is 00 cleared otherwise C b7 Set if before the rotate the MSB of ACCA or M was set cleared oth erwise Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles ROLA INH A 49 3 ROLX INH X 59 3 ROL opr DIR 39 dd 5 ROL X 79 5 ROL opr X 69 ff 6 M68HC05 Applications Guide Rev 4 0 286 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc Instruction Set Details M68HC05 Instruction Set Rotate Right thru Carry ROR 07 b0 C Fe Shift all bits of ACCA X or M one place to the right Bit 7 is loaded from the C bit The rotate operations include the carry bit to allow extension of the shift and rotate operations to multiple bytes For example to shift a 24 bit value right one bit the sequence LSR HIGH ROR MID ROR LOW could be used where LOW MID and HIGH refer to th
125. to www freescale com Freescale Semiconductor Inc Microcontroller Operation Computer Codes The simplest kind of I O memory locations are a simple input port and a simple output port In an 8 bit MCU a simple input port would consist of eight pins that can be read by the CPU A simple output port would consist of eight pins that the CPU can control write to In practice a simple output port location is usually implemented with eight latches and feedback paths that allow the CPU to read back what was previously written to the address of the output port Figure 2 3 shows the equivalent circuit for one bit of RAM one bit of an input port and one bit of a typical output port having readback capability In a real MCU this circuit would be repeated eight times to make a single 8 bit RAM location input port or output port When the CPU stores a value to the address that corresponds to the RAM bit in Figure 2 3 a the WRITE signal is activated to latch the data from the data bus line into the flip flop 1 This latch is static and remembers the value written until a new value is written to this location or power is removed When the CPU reads the address of this RAM bit the READ signal is activated which enables the multiplexer at 2 This multiplexer couples the data from the output of the flip flop into the data bus line In a real MCU RAM bits are actually much simpler than shown here but they are functionally equivalent to thi
126. to generate output signals or for timing program delays 3 14 1 Functional Description The timer features are as follows e 16 Bit Free Running Counter with Prescaler e Overflow Flag to Extend Timing Range e 16 Bit Output Compare Register e 16 Bit Input Capture Register Three Interrupt Sources The block diagram of the timer is shown in Figure 3 43 The programmable timer capabilities are provided by using ten addressable 8 bit registers and two external pins output level TCMP and edge input TCAP The 10 registers are as follows Counter High Register location 18 Counter Low Register location 19 Alternate Counter High Register location 1A Alternate Counter Low Register location 1B Input Capture High Register location 14 Input Capture Low Register location 15 Output Compare High Register location 16 Output Compare Low Register location 17 Timer Control Register TCR location 12 Timer Status Register TSR location 13 Because the timer has a 16 bit architecture the counter and alternate counter input capture and output compare values are represented by two 8 bit registers The two 8 bit registers contain the high and low byte of each timer function value see Figure 3 44 M68HC05 Applications Guide Rev 4 0 166 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Progra
127. 05 dd rr 5 BRCLR 3 opr rel DIR bit 3 07 dd rr 5 BRCLR 4 opr rel DIR bit 4 09 dd rr 5 BRCLR 5 opr rel DIR bit 5 OB dd rr 5 BRCLR 6 opr rel DIR bit 6 OD dd rr 5 BRCLR 7 opr rel DIR bit 7 OF dd rr 5 M68HC05 Applications Guide Rev 4 0 262 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Details M68HC05 Instruction Set BRN Branch Never B RN Operation PC lt PC 0002 Description Never branches In effect this instruction can be considered as a two byte NOP no operation requiring three cycles for execution Its inclusion in the instruction set is to provide a complement for the BRA instruction The instruction is useful during program debug to negate the effect of another branch instruction without disturbing the offset byte Condition Codes and Boolean 7 1 None affected Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Operand s Cycles Code and Cycles BRN rel REL 21 rr 3 The following table is a summary of all branch instructions Test Boolean Mnemonic Opcode Complementary Branch Comment r gt m C Z 0 BHI 22 BLS 23 Unsigned 0 BHS BCC 24 rm BLO BCS 25 Unsigned r m Z 1 BEQ 27 26
128. 05C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Programmable Timer One of the easiest uses for an output compare function is to produce a pulse of a specific duration First a value corresponding to the leading edge of the pulse is written to the output compare register The output compare is configured to automatically set the TCMP output either high or low depending on the polarity of the pulse being produced After this compare occurs the output compare is reprogrammed to automatically change the output pin back to its inactive level at the next compare A value corresponding to the width of the pulse is added to the original output compare register value and this result is written to the output compare register Since the pin state changes occur automatically at specific values of the free running counter the pulse width can be controlled accurately to the resolution of the free running counter independent of software latencies By repeating the actions for generating pulses you can generate an output signal of a specific frequency and duty cycle Another use of the output compare function is to generate a specific delay For example suppose you want to produce a 1 millisecond delay to time programming of an EPROM byte First go through the initial programming steps to the point where the programming supply has be
129. 1 Active low clocks selected SCK idles high This bit is used in conjunction with the clock phase control bit to produce the desired clock data relationship between master and slave CPHA The clock phase bit in conjunction with the CPOL bit controls the relationship between the data on the MISO and MOSI pins and the clock produced or received at the SCK pin CPHA selects one of two fundamentally different clocking protocols to allow the SPI system to communicate with virtually any synchronous serial peripheral device SPR1 SPRO These two serial peripheral rate bits select one of four bit rates to be used as SICK if the device is a master they have no effect in the slave mode Frequency if Frequency if SPR1 SPRO Clock XTAL XTAL Divided By is 4 0 MHz is 2 MHz 0 2 1 0 MHz 500 0 kHz 0 1 4 500 0 kHz 250 0 kHz 1 0 16 125 0 kHz 62 50 kHz 1 1 32 62 5 kHz 31 25 kHz M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 159 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8 705 8 Functional Data 3 12 4 2 Serial Peripheral Status Register SPSR This read only register Figure 3 38 contains status flags which indicate the completion of an SPI transfer and the occurrence of certain SPI system errors The flags are automatically set by the SPI events the flags are cleared by automatic software
130. 193 018 TIME EQU Update Time of day 018c 3d a2 TST TLE Check for TIC zero 018 26 38 BNE XTIME If not just exit 0190 3c a3 INC SEC SEC SEC 1 0192 3c LDA 60 0194 bl a3 CMP SEC Did SEC gt 60 A2 O B 3C O C 93 O D 01 The following instruction reads the current value of the 8 bit variable TIC and internally tests for a negative or zero value At what physical address is the variable TIC located 018 3 a2 TST LLC Check for TIC zero O A 01 A2 O B 018D O C 31DA2 D 00A2 After executing the following sequence of instructions what value will be in the accumulator BEGIN LDA 580 BPL LABEL INCA LABEL DECA DECA 7E 7F 80 81 M68HC05 Applications Guide Rev 4 0 306 Review Questions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions Review Questions 13 After executing the following instruction sequence from START to END what value will be in memory location 00FF 0100 9C START RSP Reset SP to SOOFF 0101 cd 02 00 JSR SUB Call SUB 0104 cd 02 00 JSR SUB Call SUB again 0107 9d END NOP Done 0200 81 SUB RTS Just Return O A 00 O B 01 O C 04 O D 07 14 What frequency crystal would be used on an MC68HC705C8 to get a 500 ns internal processor clock O A 1 0 M
131. 2 o 5 8 um o Operation Description CCR 58 85 o oz 2 HINZC lt 9 CLC Clear Carry Bit 0 98 2 CLI Clear Interrupt Mask 1 0 0 INH 9 2 M lt 00 DIR 3F 99 5 CLRA lt 00 INH 4F 3 CLRX Clear Byte X lt 00 0 1 INH 3 CLR opr X 00 IX1 eF ff 6 CLR X lt 00 7F 5 CMP opr ii 2 CMP opr DIR B1 dd 3 CMP opr EXT 1 4 oprX Compare Accumulator with Memory Byte A 1 111 2 01 5 opr X ff 4 CMP X IX F1 3 COM opr M M FF M DIR 33 99 5 COMA A lt FF INH 43 5 COMX Complement Byte One s Complement Xe X FF X t t 1 53 3 Me M 1 1 63 ff 6 M e M FF M IX 73 5 CPX opr IMM ii 2 CPX opr DIR B3 dd 3 CPX opr EXT Cc3 hhll 4 CPX oprX Compare Index Register with Memory Byte X M t t t 2 03 5 CPX IX1 E3 ff 4 3 DEC opr M lt M 1 DIR 3A 99 5 DECA lt A 1 4A 3 DECX Decrement Byte 9 1 t t INH 5 3 DEC M lt M 1 x1 6A ff 6 DEC M lt M 1 5 opr IMM A8 ii 2 EOR opr DIR B8 dd 3 EOR opr EXCLUSIVE OR Accumulator with Memory M _ EXT Cc8 hhll 4 EOR opr X Byte Ses BAM IX 5
132. 262 BRN Branch 263 BRSET n Branch if Bit n is Set 264 M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details For More Information On This Product Go to www freescale com 233 Freescale Semiconductor Inc Instruction Set Details BSET Set Bitin 265 BSR Branch to 5 266 CLC Clear Carry BILL a oid dado Ee CORE 267 CLI Clear Interrupt Mask Bit 268 OLR cus ab Denn 269 CMP Compare Accumulator with Memory 270 271 CPX Compare Index Register with Memory 272 DEC Deb BITIBDE 273 EOR Exclusive OR Memory with Accumulator 274 INC Increment undae ok hee eked eek 275 ded a 276 JSR Jump to Subroutine 277 LDA Load Accumulator from 278 LDX Load Index Register from Memory 279 LSL Logical Shift 280 LSR Logical Shift Right nce ewer ax ewe 281 MUL Multiply Unsigned 282 NEG Negate 283 284 1
133. 2A Simple Mask 1 5 2 Mask 0 BMC 2C Simple Half Carry H 1 BHCS 29 No Half Carry BHCC 28 Simple IRQ Pin High BIH 2F IRQ Low BIL 2E Simple Always BRA 20 Never BRN 21 Unconditional r register ACCA or X m memory operand M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details 261 For More Information On This Product Go to www freescale com Instruction Set Details BRCLR n Operation Description Condition Codes and Boolean Freescale Semiconductor Inc Branch if Bit n is Clear PC lt 0003 Rel BRCLRn if bitn of M 0 Tests bit n n 7 6 5 0 of location M and branches if the bit is clear M can be any RAM or I O register address in the 0000 to 00FF area of memory direct addressing mode is used to specify the address of the operand The C bit is set to the state of the bit tested When used along with an appropriate rotate instruction BRCLR n provides an easy method for performing serial to parallel conversions H 2 1 1 t Set if Mn 1 cleared otherwise Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Operand s Cycles Code and Cycles BRCLR 0 rel DIR bit 0 01 dd rr 5 BRCLR 1 opr rel DIR bit 1 03 dd rr 5 BRCLR 2 opr rel DIR bit 2
134. 4 N 0105 87 27 26 STA 02 0106 02 28 29 30 Figure 2 11 Subroutine Call Sequence M68HCO05 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation 61 For More Information On This Product Go to www freescale com M68HC05 Applications Guide Rev 4 0 Freescale Semiconductor Inc Microcontroller Operation 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19 CPU reads A6 opcode from location 0100 LIDA immediate CPU reads immediate data 02 from location 0101 into the accumulator CPU reads CD opcode from location 0102 JSR extended CPU reads high order extended address 02 from 0103 CPU reads low order extended address 00 from 0104 CPU builds full address of subroutine 0200 CPU writes 05 to 00FF and decrements SP to 00 Another way to say this is push low order half of return address on stack CPU writes 01 to 00FE and decrements SP to 00FD Another way to say this is push high order half of return address on stack The return address that was saved on the stack is 0105 which is the address of the instruction that follows the JSR instruction CPU reads 4A opcode from location 0200 This is the first instruction of the called subroutine The DECA instruction takes three cycles 9 10 and 11 CPU reads BNE opcode 26 from location 0201 CPU reads relative offset from 0202
135. 4 2 Timer Counter and Alternate Counter Registers The 16 bit free running counter or counter register starts from a count of 0000 as the MCU is coming out of reset and then counts up continuously When the maximum count is reached FFFF the counter rolls over to a count of 0000 sets an overflow flag and continues to count up As long as the MCU is running in a normal operating mode there is no way to reset change or interrupt the counting of this counter This counter which may be read at any time to tell what time it is is always a read only register The prescaler gives the timer a resolution of 2 0 us if the MCU crystal is 4 MHz internal processor clock is 2 0 MHz Including 0 the counter M68HC05 Applications Guide Rev 4 0 168 68 705 8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Programmable Timer repeats every 65 536 counts F FFF 65 535 Because the free running counter is preceded by a fixed divide by four prescaler the value in the free running counter repeats every 262 144 internal processor clock cycles The double byte free running counter can be read from either of two locations 18 19 or 1A 1B These registers are called the counter register and the counter alternate register respectively Normally a timer read is made from the counter alternate reg
136. 5 0016 OCMP EQU 16 Output Compare Reg Hi 16 Lo 17 0018 TCNT EQU 18 Timer Count Reg Hi 18 Lo 19 001a ALTCNT EQU 1 Alternate Count Reg 51 Lo 1B RAM Equates 00a0 ORG SAO Using to debug and monitor uses lower RAM 00 0 RMB I One byte temp storage location 00a1 TEMPX RMB a One byte temp storage location 00a2 TIC RMB 50mS Tics 00 19 20 Tics 1 Sec 00a3 SEC RMB T Current Time Seconds 00 59 M68HC05 Applications Guide Rev 4 0 212 Applications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Thermostat Project Details Listing Thermostat Example Sheet 2 of 21 00 4 BCDEO RMB it s easier 1 BCD equivalent of ENTRY to roll in new digits to a BCD buffer vs binary Next 7 entries are accessed by indexed addressing using 1 byte offset from ENTRY The offset is MODE in X and the value at ENTRY X is the value that is subject to change in the selected mode 00 5 RMB 1 Binary value being entered by user 00a6 HR RMB 1 Current Time Hour 1 12 binary 00 7 RMB 1 Current Time Minute 00 59 binary 00 8 RMB L Current Time AM 0 PM 1 00 9 DAY RMB ul Day of Wk 1 Sun 7 Sat RMB L HVAC Equipment Mode Modes 0 Off
137. 6 PCS PC4 PC3 Figure 3 3 44 Lead PLCC Package Pin Assignments The following subsections provide a description of the pin functions Power is supplied to the MCU using these two pins Vpp is power and Vss is ground The MCU can operate from a single 5 volt nominal power supply 3 4 1 2 Vpp The Vpp pin is used when programming the one time programmable ROM OTPROM or EPROM Programming voltage 14 75 Vdc is applied to this pin when programming the PROM Normally this pin is connected to Vpp CAUTION not connect Vpp pin to Vss GND It will damage the MCU M68HCO05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 81 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data 3 4 1 3 IRQ Maskable Interrupt Request 3 4 1 4 RESET 3 4 1 5 TCAP IRQ is a software programmable option which provides two different choices of interrupt triggering sensitivity These options are 1 negative edge sensitive triggering only or 2 both negative edge sensitive and level sensitive triggering In the latter case either a negative edge or a low level input to the IRQ pin will produce an interrupt The MCU completes the current instruction before it responds to the interrupt request When the IRQ pin goes low a small synchronization delay occurs and a logic one is latched internally to signify an interrupt has been requested When the MCU co
138. 68HC805C4 and later programmed into less expensive MC68HC705C8 OTP MCUs for production quantities Motorola produces a line of low cost about 500 evaluation boards EVMs which can be used for high speed interactive development To use this development approach you would build a prototype of your system with a socket where the MCU will go Instead of an MCU you would connect the EVM into this socket The EVM emulates the actions of areal MCU but allows visibility into the internal activities of the MCU M68HC05 Applications Guide Rev 4 0 190 Applications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Software Development Methods Some of the possible uses for an EVM include examination and modification of memory locations executing a user program until a certain instruction is found or looking at a program in mnemonic form You can also trace individual instructions and look at the contents of registers and memory before and after executing each instruction 4 4 Software Development Methods The development of programs for MCU based systems requires the use of slightly different techniques from those used with hardware based systems MCU based systems are programmed with instructions which control the MCU whereas hardware based systems are programmed by changing wired connections This section describes program development techniques for MCU based sys
139. 68HCO5 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 151 For More Information On This Product Go to www freescale com 000d 000 0002 0011 0010 00 0 00 1 00 2 0500 0500 0502 0504 0506 0508 050 050 0508 0511 0513 0515 0517 0519 0515 0514 0512 0520 0521 0522 0523 0525 0527 0529 0525 0524 0526 0531 0533 0535 0537 0539 0535 0534 0532 0541 0543 0546 0548 0549 054 054 30 00 0 05 0 Of 30 02 07 2 0 30 39 02 07 1 18 14 24 10 1 2 08 9 10 11 10 43 fd Freescale Semiconductor Inc MC68HC705C8 Functional Data KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK Simple 68 05 SCI Program Example KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK BRATE EQU 50 SCCR1 EQU 50 SCCR2 EQU SOF SCDAT EQU 11 SCSR EQU 10 TEMP EQU SAO TEMPHI EQU A1 TEMPLO EQU 5 2 ORG 500 INITIAL LDA 00110000 5 BRATE LDA 00000000 SCCR 1 LDA 00001100 5 SCCR2 START JSR GETDATA STA TEMP AND SOF SCP1 SCP0 SCR2 SCR1 SCRO R8 T8 M WAKE TIE TCIE RIE TE SBK Read RDR Write TDR TC IDLE OR NF FE One byte temp storage location Upper byte changed to ASCII Lower byte changed to ASCII Program will start at 0500
140. 7 a6 b7 38 39 38 39 9d 3 0 81 1 1 0 1 0 511110011 Initial value SAO For 00A0 510000001 Initial value SA1 For 00 1 SA1 Comment left off SAO intentionally SA1 SAO 10000001 O B 00A0 00A1 11001100 00000100 O C 00A0 00A1 11001110 00000111 D 00A0 00A1 11001110 00000100 Refer to the following four program listings to answer questions 33 through 38 These programs demonstrate four different ways to generate pulses at port A bit 0 of an MC68HC705C8 All four programs assume that port A has been configured as outputs by the data direction register DDRA equal FF 0100 0102 0104 0106 0108 0100 0102 0104 0100 0102 0103 0105 0107 0100 0102 0104 0106 b7 a6 b7 20 10 11 20 00 00 01 00 00 00 01 00 8 PROG1 PROG2 PROG3 LOOP 3 PROG4 LDA STA LDA STA BRA BSET BCLR BRA LDA CLRX TA TX RA DA OR TA RA 501 500 500 500 PROG1 0 00 0 00 PROG2 501 500 500 LOOP 3 00 501 500 4 O1 WB BW Wb CO Pattern for bit 0 high Write to port A Pattern for bit 0 low Write to port A Repeat loop continuously Set port A bit 0 Clear port A bit 0 Repeat loop continuously Pattern for bit 0 high Pattern for bit 0 low Write to port A Write to port A Repeat loop c
141. 8 02fa 02fc 02fe 0300 0302 0304 0306 0308 b6 be a3 26 al al 23 a3 26 4d 2b al 23 a3 26 4d 2b al 2 3 a3 26 al 25 al 253 a3 26 4d 2b al 23 a3 26 al 25 al 23 57 81 5 bl 01 08 01 04 3b 02 07 04 35 30 03 07 04 01 25 04 08 01 04 07 19 05 07 04 03 06 08 32 04 63 02 5 Sheet 11 of 21 M GOAL CHKPNT a utility subroutine used by USER routine me Checks for entry within legal limits which depend on value being changed HR 1 12 MIN 0 59 and so If legal bit will be 0 Positive On return has enrty value SFF if illegal X points at value to be changed ENTRY X may be used to access value to be changed CHKPNT LDA ENTRY For compares to chk limits LDX MODE For compares amp as return pointer CPX 1 Set HR BNE TRI2 not CMP 1 lt 1 BLO TRI2 illegal will ripple through CMP 112 1 12 BLS OKENT Valid HR entry TRI2 CPX 2 Set MIN BNE TRI3 not TSTA lt 0 BMI TRI3 illegal will ripple through CMP 59 0 59 7 BLS OKENT Valid MIN entry TRI3 CPX 3 Set AMPM BNE TRI4 not TSTA lt 0 BMI TRI4 illegal will ripple through CMP 1 0 1 BLS OKENT Valid AMPM entry TRI4 CPX 4 Set DAY BNE TRI5 not CMP 1 lt 1 BLO TRI5 illegal will ripple t
142. 8HC05 Applications Guide Rev 4 0 MOTOROLA General Description 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description 1 3 Definitions Section 3 MC68HC705C8 Functional Data contains functional data for the Motorola MC68HC705C8 MCU This section gives you specific information needed to use this MCU in an application More information be found in slightly different form in BR594 D the MC68HC705C8 Technical Summary which is available separately Section 4 Applications shows you how to develop applications and gives you the thermostat project details Appendix A Instruction Set Details provides a detailed description of each instruction in the MC68HCO5 instruction set Appendix B Review Questions contains review questions answers and explanations The heart of a computer is the central processor unit CPU A microprocessor is a CPU on a single chip A computer system is a CPU plus peripherals such as input output 1 0 devices memory a program and a timing reference A microcontroller is a very small product that contains many of the functions found in any computer system A microcontroller uses a microprocessor as its CPU as well as memory and peripherals on the same chip A microcontroller MCU is packaged as a single chip that can be programmed by the user with a series of instructions loaded into its memory M68HC05 Applications
143. 9 20 SP1 LDA 520 ASCII space lt sp gt 040b cd 06 3a JSR WDAT Send a space to LCD 040 81 RTS RETURN from BLINKR M68HCO05 Applications Guide Rev 4 0 226 Applications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Thermostat Project Details Listing Thermostat Example Sheet 16 of 21 Ck CK ck Ck C CK Ck Ck CK CC C CK Ck Ck CK KKK KKK KKK KK KKK KKK KKK KKK Sk Ck Ck Kk Ck Ck kk Ck Kk Sk Sk Pk kv DSPLAY Writes full 40 character display of current system conditions to the LCD display peripheral x Following is a typical LCD display Hee Qe 1 6 UON 5 720 1 02 F 040 00 DSPLAY LDA 500 Left end of lst line on LCD 0411 cd 06 20 JSR CTRL Position entry point 0414 be bl LDX MODE Use for mode compares 0416 b6 LDA HR 0418 a3 01 CPX 1 Mode HR set 041 26 02 Skip if not 1 041 6 ad LDA ENTRY Use ENTRY rather than HR 041 06 JSR CNVERT Convert HRs to ASCII 0421 cd 06 56 JSR SHOW2 Display as 2 digits 0424 a6 3a LDA 5 1 0426 06 JSR WDAT To LCD 0429 b6 a7 LDA MIN 042b a3 02 CPX 2 Mode MIN set 042d 26 02 BNE 2 Skip if not 2
144. A Instruction Set Details For More Information On This Product Go to www freescale com 293 STA Freescale Semiconductor Inc Instruction Set Details Store Accumulator in Memory STA Operation M lt ACCA Description Stores the contents of ACCA in memory The contents of ACCA remain unchanged Condition Codes and Boolean 7 Formulae 1 1 1 a 7 Set if MSB of result is set cleared otherwise Z A7 e A4 A2 A1 AO Set if result is 00 cleared otherwise Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Cycles Code and Cycles STA opr DIR B7 i 4 STA opr EXT C7 hh 5 STA X IX F7 4 STA opr X IX1 E7 ff 5 STA opr X IX2 D7 ee ff 6 M68HC05 Applications Guide Rev 4 0 294 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com STOP Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc Instruction Set Details M68HC05 Instruction Set Enable IRQ Stop Oscillator STOP Reduces power consumption by eliminating all dynamic power dissipation This results in 1 timer prescaler cleared 2 timer interrupts disabled 3 timer interrupt flag cleared 4 external interrupt request enabled and 5 osc
145. Add with Carry ADC Description Adds the contents of the C bit to the sum of the contents of ACCA and M and places the result in ACCA Condition Codes and Boolean Formulae 1 1 1 Set if there was carry from bit 3 cleared otherwise R7 Set if MSB of result is set cleared otherwise 7 R7 R6 R5 eR4 R3e eR2 R1 RO Set if all bits of the result are cleared cleared otherwise C 7 7 7 R7 R7 A7 Set if there was carry from the MSB of the result cleared otherwise Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Operand s Cycles Code and Cycles ADC opr IMM AQ i 2 ADC opr DIR 9 3 ADC opr EXT C9 hh 4 ADC F9 3 ADC opr X 9 ff 4 ADC opr X IX2 D9 ee ff 5 M68HC05 Applications Guide Rev 4 0 238 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com ADD Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc Add without Carry lt Instruction Set Details M68HC05 Instruction Set ADD Adds the contents of M to the contents of ACCA and places the result in ACCA 1 1 1
146. Application Example Flowchart M68HC05 Applications Guide Rev 4 0 164 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Programmable Timer KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK Simple 68 05 SPI Program Example 0001 EQU 501 Direct address of port sw 0002 PORTC EQU 02 Direct address of port C LED 0005 DDRB EQU 05 Data direction control port B 0006 DDRC EQU 506 Data direction control port 000 SPCR EQU 0A SPIE SPE MSTR CPOL CPHA SPRI SPRO 0005 SPSR EQU SOB SPIF WCOL MODF 7 000c SPDR EQU SOC SPI Data Register 009 SPIVAL EQU 59 One byte RAM storage location 009 TEMPI EQU S9F One byte temp storage location 0250 ORG 250 Program will start at 0250 0250 a6 ff INIT LDA 5 Begin initialization 0252 b7 06 STA DDRC Set port C to act as outputs Port B is configured as inputs by default from reset 0254 LDA SE8 Red amp grn LED amp beep off SPI EN off 0256 p7 02 STA PORTC Turn off red LED Some pins of port C my board happen to be connected to devices which don t apply to this example program The SE8 pattern turns off
147. C05 Applications Guide Rev 4 0 304 Review Questions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions Review Questions 5 many 8 bit memory locations would be needed to hold the ASCII representation of the name FRED O A 16 O B 4 7 O D 2 6 Which of these CPU registers in the MC68HC705C8 contains the most bits O A The accumulator A O B The index register X O C The condition code register CCR O D The program counter PC 7 Which CPU register in the MC68HC705C8 would most likely point to the next instruction that the CPU will execute O A The accumulator A O B The index register X O C The stack pointer SP O D The program counter PC 8 During execution of a subroutine where would the CPU save the return address All except one of the following address pairs is incorrect due to improper memory type or address A 1FFE 1FFF B 00EC 00ED O C 00AE 00AF O D 015E 015F 9 How many different opcodes correspond to the LDA load accumulator instruction A 1 O B 3 C 6 O D 16 M68HC05 Applications Guide Rev 4 0 MOTOROLA Review Questions 305 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions 10 11 12 In the following partial listing what 8 bit value or code is present in memory location 0
148. CONDITION CODES 7 0 H N Z BEFORE 1 1 1 1 1 1 1 1 FF 1 1 LA 1 1 0 0 EXECUTE THE FOLLOWING INSTRUCTION 02 ADD 2 ADD 2 ACCUMULATOR ACCUMULATOR CONDITION CODES 7 0 H 2 AFTER 0 0 0 0 0 0 0 1 01 1 1 0 0 1 CONDITION CODES AND ACCUMULATOR REFLECT THE RESULTS OF THE ADD INSTRUCTION Set because there was carry from bit to bit 4 of the accumulator change Clear because result is not negative bit 7 of accumulator is 0 Z Clear because result is not zero Set because there was a carry out of bit 7 of the accumulator 3 6 1 4 Program Counter The program counter is a 13 bit register that contains the address of the next instruction or instruction operand to be fetched by the processor 15 12 0 000 PROGRAM COUNTER PC Figure 3 12 Program Counter PC Normally the program counter advances one memory location at a time as instructions and instruction operands are fetched Jump branch and interrupt operations cause the program counter to be loaded with a memory address other than that of the next sequential location M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 93 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data 3 6 1 5 Stack Pointer The stack pointer is a 13 bit register that contains the addr
149. Ck CK Ck Ck CK Ck Ck CK Ck Ck CK Ck C CK Ck Ck CK CI Ck CK Ck Ck Ck Ck Ck CK Ck CK Ck Ck C Ck Ck CK Sk Ck Ck kk Sk Pk Sk Sk kA A kx KK 039d LCD EQU LCD Display Update 039d a6 80 LDA 580 Left end of lst row 039 06 20 JSR WCTRL Position entry point 03a2 b6 a2 LDA TIC 50mS periods 0 19 03a4 27 09 BEQ TICO Only update once sec 03a6 al 0a CMP 110 TIC 10 at mid second 03a8 26 08 BNE XLCD If not 0 or 10 just leave 03aa cd 03 b3 JSR BLINKR Blanks colon or value being set 03ad 20 03 BRA XLCD Exit 03af cd 04 Of TICO JSR DSPLAY Update the LCD display 0352 81 XLCD RTS RETURN from LCD M68HC05 Applications Guide Rev 4 0 MOTOROLA Applications 225 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Listing Thermostat Example Sheet 15 of 21 Following subroutines support the LCD main task 0353 BLINKR EQU Blink colon or user entry 03b3 be bl LDX MODE Mode 0 03b5 26 07 BNE not see if mode 1 0357 82 LDA 582 Cursor position of colon 03b9 06 20 JSR WCTRL Send cursor position to LCD 03bc 20 4b BRA 5 1 Send 1 ASCII space and leave O3be 5a DECX Mode 1 03bf 26 07 GILEZ If not see if mode 2 03 1 80 LDA 580 Cursor position of HR 03c3 cd 06 20 JSR WCTRL Send cursor position to
150. E errors are very unlikely and are typically ignored The second type of link involves two remote devices where each is connected to a modem In M68HCO05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 145 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8 705 8 Functional Data this type of link errors are more likely and both computers would typically use a protocol that permits retransmission when an error is detected 3 11 3 5 Serial Communications Data Register SCDAT The SCI SCDAT data register see Figure 3 28 has two functions it is the transmit data register when written to and the receive data register when read Both the transmitter and receiver are double buffered see Figure 3 29 so back to back characters can be handled easily even if the CPU is delayed in responding to the completion of an individual character 7 6 5 4 3 2 1 BIT 0 11 SCDAT Figure 3 28 Serial Communications Data Register TRANSMITTER PARALLEL DATA FROM CPU DATA BUS TDRE flag set each time new data is transferred from the TDR buffer to the TRANSMIT serial shift register TDR BUFFER SERIAL DATA OUT TRANSMIT SHIFTER 5 START BIT STOP BIT START BIT RECEIVE SHIFTER n RDR BUFFER RDRF flag set each time new data is transferred from the serial shift register Y Y to the RDR buffer
151. FFF M68HC05 Applications Guide Rev 4 0 96 68 705 8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Central Processor Unit 3 6 4 2 Computer Operating Properly COP Watchdog Timer Reset The COP watchdog timer system is intended to detect software errors When the COP is being used software is responsible for keeping a free running watchdog timer from timing out If the watchdog timer times out it is an indication that software is no longer being executed in the intended sequence thus a system reset is initiated Since the COP timer relies on the internal bus clock in order to detect a software failure a clock monitor is also included to guard against a failure of the clock When the COP timer is enabled the clock monitor should also be enabled since the COP timer cannot detect failures of the internal bus clock The COP control register 1E as shown below is used to control the COP watchdog timer and clock monitor functions BIT 7 6 5 4 3 2 1 0 corr ewe core 0 0 0 1 0 0 0 0 RESET CONDITION x zm L SELECT COP TIME OUT PERIOD COP WATCHDOG TIMER ENABLE CLOCK MONITOR ENABLE COP SYSTEM FLAG 1 Cleared on external or POR reset set on COP or clock monitor fail resets COPF Computer Op
152. FFF corresponds to the last memory location selected when the CPU drives all 13 address lines of the internal address bus to logic one The labels within the vertical rectangle identify what kind of memory RAM PROM I O registers etc resides in a particular area of memory Some areas such as registers need to be shown in more detail because it is important to know the names of each individual location The vertical rectangle can be interpreted as a row of 8192 pigeon holes memory locations Each of these 8192 memory locations contains eight bits of data as shown in the inset in Figure 2 4 The first 256 memory locations 0000 00FF can be accessed with the direct addressing mode of many CPU instructions In this addressing mode the CPU assumes that the upper two hexadecimal digits of address are always zeros thus only the two low order digits of the address need to be explicitly given in the instruction All on chip registers and 176 bytes of RAM are located in the 0000 00FF area of memory In the memory map Figure 2 4 the expansion of the area of memory identifies each register location with the two low order digits of its address rather than the full four digit address For example the two digit hexadecimal value 00 appears to the right of the port A data register which is actually located at address 0000 in the memory map Now that we have some background knowledge of computer memory we can continue wit
153. Freescale Semiconductor Inc oye digital dna intelligence everywhere M68HC05 Applications Guide M68HC05 Microcontrollers Rev 4 3 2002 WWW MOTOROLA COM SEMICONDUCTORS For More Information On This Product o to www freescale com Freescale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor Inc M68HC05 Applications Guide To provide the most up to date information the revision of our documents on the World Wide Web will be the most current Your printed copy may be an earlier revision To verify you have the latest information available refer to http Awww motorola com semiconductors The following revision history table summarizes changes contained in this document For your convenience the page number designators have been linked to the appropriate location Motorola and the Stylized M Logo are registered trademarks of Motorola Inc DigitalDNA is a trademark of Motorola Inc Motorola Inc 1989 1996 2002 M68HC05 Applications Guide Rev 4 0 MOTOROLA Applications Guide 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Revision History Revision History Date 2 Description mio m April 1997 3 0 Format and organizational changes Throughout Updated to current publication styles Appendix A Instruction Set Det
154. Guide Rev 4 0 22 General Description MOTOROLA For More Information On This Product Go to www freescale com 1 4 Background Freescale Semiconductor Inc General Description Background Before MCUs controllers were hard wired electronic devices whose operation was determined by the circuits and wires contained within them The operation of an MCU based controller is determined primarily by its program instead of its components and wires Any function that can be implemented using hard wired digital integrated circuits ICs can also be implemented and performed by an MCU As the size and complexity of the devices increase MCUs become attractive for two reasons 1 hard wired approach requires adding ICs to perform more complex tasks whereas MCUs require only a longer program 2 Microcontrollers are more versatile Any change in a hard wired system usually involves replacing ICs and rerouting wires Most modifications to an MCU system are made simply by changing the program MCUs are very useful where many decisions or calculations are required It is easier to use the computational power of a computer than to use discrete logic Microcontrollers are now being used to replace existing designs because they are far simpler to use than conventional IC logic Since the MCU approach is programmable many additional features are possible at little or no added cost Programmability makes possible multiple use
155. HALF CARRY FROM BIT 3 Figure 3 8 Programming Model 3 6 1 1 Accumulator The accumulator is an 8 bit general purpose register used to hold operands results of the arithmetic calculations and data manipulations Itis also directly accessible to the CPU for nonarithmetic operations The accumulator is used during the execution of a program when the contents of some memory location are loaded into the accumulator Also the store instruction causes the contents of the accumulator to be stored at some prescribed memory location 7 0 ACCUMULATOR A Figure 3 9 Accumulator A M68HC05 Applications Guide Rev 4 0 90 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Central Processor Unit 3 6 1 2 Index Register The index register is used for indexed modes of addressing or may be used as an auxiliary accumulator This 8 bit register can be loaded either directly or from memory have its contents stored in memory or its contents can be compared to memory In indexed instructions the X register provides an 8 bit value that is added to an instruction provided value to create an effective address The instruction provided value can be 0 1 or 2 bytes long 7 0 INDEX REGISTER Figure 3 10 Index Register 3 6 1 3 Condition Code Register The condition code register contains five status indicators
156. HCMOS Modes Machine Forms Mode Opcode Operand s Cycles Code and Cycles JMP opr DIR BC dd 2 JMP opr EXT hh 3 JMP X IX FC 2 JMP opr X IX1 EC ff 3 JMP opr X IX2 DC ee ff 4 M68HC05 Applications Guide Rev 4 0 276 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com JSR Operation Description Condition Codes and Boolean Formulae Source Forms Freescale Semiconductor Inc Instruction Set Details M68HC05 Instruction Set JSR n 1 2 3 depending on address mode Push low order return address onto stack Push high order return address onto stack Load PC with start address of requested subroutine Jump to Subroutine lt PC PCL SP lt SP 0001 SP lt SP 0001 PC lt Effective Addr The program counter is incremented by n so that it points to the opcode of the instruction that follows the JSR instruction n 2 1 2 or 3 depending on the addressing mode The PC is then pushed onto the stack eight bits at a time least significant byte first Unused bits in the program counter high byte are stored as ones on the stack The stack pointer points to the next empty location on the stack A jump occurs to the instruction stored at the effective address The effective address is obtained according to the rules for EXTended or INDexed addressing
157. Hz O B 2 0 MHz O C 4 0 MHz O D 8 0 MHz 15 For an MC68HC705C8 with a 4 0 MHz crystal what amount of time corresponds to a single count of the 16 bit timer A 500 ns O B 1 0 us 2 0 us D 4 0 us 16 Foran MC68HC705C8 with a 4 0 MHz crystal what is the fastest baud rate available for the SCI UART type serial interface O A 131 072 kbaud O B 125 kbaud O C 19 2 kbaud D 9600 baud M68HC05 Applications Guide Rev 4 0 MOTOROLA Review Questions 307 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions 17 20 For an MC68HC705C8 with a 4 0 MHz crystal what is the fastest master mode bit rate available for the SPI synchronous serial peripheral interface O A 1 Mbit sec O B 500 kbits sec O C 250 kbits sec O D 125 kbits sec How many bit times are there in one SCI character frame 8 9 10 D 100r 11 To assure an orderly startup reset forces the CPU to begin executing instructions in a predictable repeatable way Which of the following statements best describes how the CPU proceeds from reset O A The CPU fetches the instruction from 1FFF and executes it O B The CPU loads the program counter PC with the address 1FFE and begins executing instructions O C The CPU begins executing instructions starting at address 0000 O D The CPU loads the program counter PC with the address stor
158. Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Synchronous Serial Peripheral Interface SPI 3 12 Synchronous Serial Peripheral Interface SPI The SPI subsystem included in the MC68HC705C8 allows the MCU to communicate with peripheral devices Peripheral devices can be as simple as an ordinary TTL shift register or as complex as a complete subsystem such as an LCD display driver or an A D converter subsystem The SPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers SPI is an added feature for those applications that require more inputs and outputs than there are parallel I O pins on the MCU SPI offers very easy way to expand the function while using a minimum number of MCU pins The SPI block diagram is shown in Figure 3 34 SPI features are as follows e Full duplex three wire synchronous transfers Master or slave operation e 1 05 MHz maximum master bit frequency e 2 1 MHz maximum slave bit frequency Four programmable master bit rates Programmable clock polarity and phase Endoftransmission interrupt flag e Write collision flag protection An SPI subsystem can operate under software control in either complex or simple system configurations One master MCU and several slave MCUs Several MCUs interconnected in a multimaster system One master MCU and one or more slave perip
159. KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK WDAT L120 STX STA STA T T EMPX EMPA PORTA 1 2 2 1 L T 20 120 Write data word to LCD Ro se gt 1 gt 0 RS gt 0 20 6 1 5 12005 Delay loop 12015 20 L9519 L8 Restore Restore RETURN P Figure 4 8 Display Checkout Program Listing Sheet 2 of 2 M68HC05 Applications Guide Rev 4 0 206 Applications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Thermostat Project Details Since we now understand the LCD display we can use the display to check out the keypad interface To read a keypad key we must recognize a key closure delay to allow debounce and decode the position row column of the key This is an example of how the MCU can simplify the hardware design Software can be used to debounce the keys rather using complicated hardware circuits Software also allows many switches to be wired in a row column matrix so fewer I O lines are needed The flowchart in Figure 4 9 shows how keypad keys are detected Figure 4 10 is a listing of the keypad checkout program A real time loop structure was chosen for the thermostat project main program This basic structure can be used for
160. KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK KEYTRY KKKKKKKKKK Try out keypad debounce and decode software E Detect and debounce keys When a key found change it to ASCII and display on LCD Debounce release of key and look for more KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK Register Equates 0000 PORTA EQU 500 LCD display data 0001 PORTB EQU 501 Keypad Row4 3 2 1 Coll 2 3 4 0002 PORTC EQU 02 Fan Heat Cool Beep ADen E RS R W 0004 DDRA EQU 04 Data direction Port A all output 0005 DDRB EQU 05 Direction Port B 7 4in 3 0out 0006 DDRC EQU 06 Data direction Port C all output RAM Equates 009d KEYVAL EQU 9D Keypad key ASCII 009e TEMPA EQU 59 One byte temp storage location 009 EQU SOF One byte temp storage location 0100 ORG 100 Set Port data patterns and directions 0100 8 LDA SE8 Fan Heat Cool Beep ADen E RS R W 0102 b7 02 STA PORTC Initial Thermostat control values 0104 4f CLRA Row3 2 1 0 Coll 2 3 4 0105 b7 01 5 PORTB All cols initially off 0107 4a DECA to SFF 0108 b7 04 STA DDRA Port A all outputs 010a b7 06 STA DDRC Port C all Outputs 010 LDA SOF Rows in Cols outs 010 b7 05 STA DDRB Port B half ins half outs LCD display peripheral needs to be initialized 0110 01 LDA 501 0112 01 93 JSR WCTRL Clear 0115
161. LCD 03 6 20 3c BRA SP2 Send 2 ASCII spaces and leave 03 8 5a CIF2 DECX mode 2 03 9 26 07 CLES If not see if mode 3 03cb 83 LDA 583 Cursor position of MIN 03 06 20 JSR WCTRL Send cursor position to LCD 03d0 20 32 BRA SP2 Send 2 ASCII spaces and leave 03 2 5 CIF3 DECX mode 3 03 3 26 07 4 not see if mode 4 0345 86 LDA 586 Cursor position of 0347 cd 06 20 JSR WCTRL Send cursor position to LCD 20 2d BRA 5 1 Send 1 ASCII space and leave 5a CIF4 DECX Mode 4 03 26 07 CIF5 If not see if mode 5 03df a6 88 LDA 588 Cursor position of DAY 03 1 06 20 JSR WCTRL Send cursor position to LCD 03 4 20 16 BRA SP4 Send 4 ASCII spaces and leave 5 CIES DECX Mode 5 03e7 26 07 BNE MUSTB6 If not mode must be 6 03e9 cO LDA 5 0 Cursor position of HVAC Mode 0 06 20 JSR WCTRL Send cursor position to LCD 20 07 BRA SP5 Send 5 ASCII spaces and leave 05 6 LDA 5 6 Must be mode 6 03 2 cd 06 20 JSR WCTRL Cursor position of Goal Temp 0325 20 0 BRA SP2 Send 2 ASCII spaces and leave 03 7 20 SP5 LDA 520 ASCII space lt sp gt 0369 06 JSR WDAT Send a space to LCD 03fc 20 SP4 LDA 520 ASCII space lt sp gt 06 JSR WDAT Send a space to LCD 0401 cd 06 3a JSR WDAT Send a space to LCD 0404 20 SP2 LDA 520 ASCII space lt sp gt 0406 cd 06 3a JSR WDAT Send a space to LCD 040
162. MER CONTROL REGISTER 12 TIMER STATUS REGISTER 13 INPUT CAPTURE REGISTER HIGH 514 INPUT CAPTURE REGISTER LOW 15 OUTPUT COMPARE REGISTER HIGH 16 OUTPUT COMPARE REGISTER LOW 17 TIMER COUNT REGISTER HIGH 18 TIMER COUNT REGISTER LOW 19 USER PROM ALT COUNT REGISTER HIGH 1A 7680 BYTES ALT COUNT REGISTER LOW 1B EPROM PROGRAM REGISTER 1C COP RESET REGISTER 1D COP CONTROL REGISTER 1E UNUSED 1F 1EFF 1F00 SPI VECTOR HIGH 1FF4 SPI VECTOR LOW 1FF5 SCIVECTOR HIGH 1FF6 MOTOROLA USE SCI VECTOR LOW S1FF7 144 BYTES TIMER VECTOR HIGH 1FF8 TIMER VECTOR LOW 1FF9 IRQ VECTOR HIGH 1FFA IRQ VECTOR LOW 1FFB SWI VECTOR HIGH 1FFC USER PROM SWI VECTOR LOW 1FFD VECTORS RESET VECTOR HIGH BYTE 1FFE 1FFF 12 BYTES RESET VECTOR LOW BYTE 1FFF INSET BIT 7 BIT 0 PORT A DATA DIRECTION REGISTER 04 DDRA7 DDRAG DDRAS DDRA4 DDRA3 DDRA2 DDRA1 DDRAO Figure 2 4 Typical Memory Map M68HC05 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation 43 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation 2 5 Timing The four digit hexadecimal values along the left edge of Figure 2 4 are addresses beginning with 0000 at the top and increasing to 1FIFF at the bottom 0000 corresponds to the first memory location selected when the CPU drives all address lines of the internal address bus to logic zero 1
163. PU pulls a piece of data off the stack the SP is incremented so it points at the most recently used pigeon hole and the data value is read from that pigeon hole When the CPU is first started up or after a reset stack pointer RSP instruction the SP points to a specific memory location in RAM a certain pigeon hole The computer memory holds all information needed by the computer for instructions variable data and even status and controls Some memory locations contain fixed data like the instructions for the CPU and tables of constant data This information is typically held in a read only memory ROM although there is no special requirement that this information has to be located in ROM A second type of information used by computers is variable information that changes often during the operation of the system This type of data is typically held in a read write random access memory RAM Information can be read from or written to various locations in RAM in an arbitrary random order A third type of information found in a computer system is status and control information This type of memory location allows the computer system to get information to or from the outside world This type of memory location is unusual because the information can be sensed and or changed by something other than the CPU M68HC05 Applications Guide Rev 4 0 40 Microcontroller Operation MOTOROLA For More Information On This Product Go
164. Program will start at 0100 0100 is the start of EPROM in the 705 8 Initialization done at reset amp on detection of some errors 0100 9c INIT RSP Reset stack pointer to FF Set Port data patterns and directions 0101 a6 e8 LDA 5 8 Fan Heat Cool Beep ADen E RS R W 0103 b7 02 5 PORTC Initial values for Thermostat controls 0105 4 CLRA Row3 2 1 0 Col11 2 3 4 0106 b7 01 5 PORTB All cols initially off 010 8 4a DECA to SFF 0109 b7 04 STA DDRA Port A all outputs OlOb b7 06 STA DDRC Port C all outputs 010d a6 Of LDA SOF Rows in Cols outs OLOT bar 05 STA DDRB Port B half ins half outs Set up SPI to talk to ext serial A D converter MC145041 CAUTION 53 thru 56 on PGMR Board conflict with SPI 0111 56 03 WAITSW LDA PORTD wait till S3 on S4 55 S6 off 0113 a4 3C AND 53 only care about S3 thru 56 0115 al 20 CMP 20 53 54 S5 S6 off 0117 26 8 BNE WAITSWIf not wait till they are Previous 4 lines only needed for development on PGMR board 0119 50 LDA 550 SPIE SPE MSTR CPOL CPHA SPR1 SPRO 011b b7 Oa STA SPCR SPI as Master 2 5 norm low clock SCI not used in this application Timer output compare used to time 50mS loop Olld 4f CLRA ICIE OCIE 0 0 0 IEGE OLVL Olle b7 12 STA TCR no timer interrupts or pins used LCD display peripheral needs to be initialized 0120 01
165. QU 03 SAM equal an 8 bit value 1400 LARRY EQU 1400 LARRY equal a 16 bit value 0100 ORG 100 Set program starting point 0100 ae 02 TOP LDX 502 Initialize index register 0102 c6 01 00 LDA TOP Read value into A O A 0003 gt B 01 00 see 3 7 3 Extended Addressing Mode O C 0103 O D 0104 Although this instruction sequence has no practical use it would assemble and function The value loaded into A would be AE the opcode of the LDX immediate instruction If you were not familiar with the use of labels you could have looked at the machine code C6 01 00 The C6 indicates the extended addressing mode variation of the LDA instruction and 0100 is the address of the operand that would be loaded into A 27 Inthe following instruction sequence a value is read into the accumulator From what address is this value being read It may be helpful to look at the machine code as well as the mnemonic instructions 0003 SAM EQU 03 SAM equal an 8 bit value 1400 LARRY EQU 1400 LARRY equal a 16 bit value 0100 ORG 100 Set program starting point 0100 ae 02 TOP LDX 502 Initialize index register 0102 f6 LDA 0 X Read value into A O A 0000 gt 0002 see 3 7 5 1 Indexed No Offset O C 0003 O D 0102 At the time the LDA instruction is executed X contains 02 due to the previous instruction M68HC05 Applications Guide Rev 4 0 MOTOROLA Review Questions 327 For More Information On This Product Go
166. Questions Review Questions Answers and Explanations 21 The half carry bit H in the condition code register CCR O A is used in rounding results of arithmetic operations describes the C bit O B indicates that the MSB of the accumulator is 1 describes the N bit gt C may be used to adjust the results of BCD add operations O D indicates a borrow occurred during a subtract operation describes the C bit See Figure 3 11 Condition Code Register CCR and 2 4 1 Computer Memory 22 MC68HC705C8 system which uses no interrupts what is the maximum possible nesting depth for subroutines without causing errors If one subroutine called a second subroutine that would be a nesting depth of 2 2 gt B 32 see Figure 3 13 Stack Pointer SP O C 64 O D 128 Remember that each subroutine call uses two 8 bit memory locations to store the return address 23 Which of the following on chip systems would be used to detect problems with the oscillator O A Power on reset O B COP watchdog timer gt C Clock monitor see 3 6 4 2 Computer Operating Properly COP Watchdog Timer Reset and 3 6 4 3 Clock Monitor Reset D IRQ interrupt M68HC05 Applications Guide Rev 4 0 MOTOROLA Review Questions 325 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions 24 25 In the following instruction sequence a value is read in
167. ROM memory is normally erased by O A software instructions O B infrared light gt C ultraviolet light see 1 5 Computer Systems Description O D application of high voltage To program the OPTION register on the MC68HC705C8 O A program all bits as if they were EPROM O B program all bits as if they were RAM O C program one bit like RAM and the rest of the bits as if they were EPROM gt D program one bit like EPROM and the rest of the bits as if they were RAM see 3 16 4 Option Register In the MC68HC705C8 bit manipulation instructions BSET and BCLR gt can be used to access any on chip register RAM location in the 0000 through 00FF area of memory O B can be used to access any location in the 8K byte memory map O C can be used only with indexed addressing modes O D can be used to access any on chip RAM location See the description of BSET and BCLR in Appendix A Instruction Set Details M68HC05 Applications Guide Rev 4 0 336 Review Questions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions Review Questions Answers and Explanations 50 Which of the following statements best describes what happens during an SPI data transfer between two MC68HC705C8 MCUs A slave device transfers an 8 bit character to a master device O B Amaster device transfers an 8 bit character to a slave
168. Rev 4 0 x x x 224 Applications For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Applications Thermostat Project Details Listing Thermostat Example Sheet 14 of 21 Cool on turn off when indoor temp lt goal 1 0382 4c INCA Goal 1 for hysteresis 0383 bl ac CMP INTMP GOAL 1 INTMP Turn off 0385 23 15 BLS XHVAC NO just leave 0387 1a 02 BSET 5 PORTC Turn off cool 0389 1 02 BSET 7 PORTC Turn off fan 038b 52 CLR HVACON Turn off flag to indicate off 038d 20 0 BRA XHVAC Then leave Cool off turn on when indoor temp gt goal 1 038 4a DECA Goal 1 for hysteresis 0390 bl ac CMP INTMP GOAL 1 lt INTMP Turn on 0392 24 08 BHS XHVAC NO just leave 0394 1f 02 BCLR 7 PORTC Turn on fan 0396 1b 02 BCLR 5 PORTC Turn on cool 0398 a6 01 LDA 1 039a b7 b2 STA HVACON Set flag to indicate on 039c 81 XHVAC RTS RETURN from HVAC Ck CK Ck C CK Ck Ck CK C Ck CK Ck Ck KKK KKK KK KKK KKK KKK K KKK KK Ck Sk Ck Ck Ck Ck Ck kk Ck Kk Sk Sk kA kv kx LCD LCD Display Update If value is being set now display ENTRY rather than the current value and flash it like time colon Flash time colon if time not being set now else on Update current time if time not being set now Update HVAC active unless HVAC mode being set now Flash value to set if user is changing a setting Ck
169. Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 95 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data The following internal actions occur as the result of any MCU reset 1 gt 10 12 13 14 All data direction registers cleared to zero input Stack pointer configured to 00FF bit in the condition code register to logic one External interrupt latch cleared SCI disabled serial control bits TE 0 and RE 0 Other SCI bits cleared by reset include TIE TCIE RIE RWU SBK IDLE OR NF and FE Serial status bits TDRE and TC set SCI prescaler and rate control bits SCPO SCP1 cleared SPI disable serial output enable control bit SPE 0 Other SPI bits cleared by reset include SPIE MSTR SPIF WCOL and MODF All serial interrupt enable bits cleared SPIE TIE and TCIE SPI system configured as slave MSTR 0 Timer prescaler reset to zero state a Timer counter configured to FFFC b Timer output compare TCMP bit reset to zero All timer interrupt enable bits cleared ICIE OCIE and TOIE to disable timer interrupts d The OLVL timer bit is also cleared by reset STOP latch cleared WAIT latch cleared Internal address bus forced to restart vector on exit from reset upper byte of program counter is loaded from 1FFE and lower byte of program counter is loaded from 1
170. T Stop CPU Clock and Enable Interrupts 0 INH 8F 2 A Accumulator opr Operand one or two bytes Carry borrow flag PC Program counter CCR Condition code register PCH Program counter high byte dd Direct address of operand PCL Program counter low byte ddrr Direct address of operand and relative offset of branch instruction REL Relative addressing mode DIR Direct addressing mode rel Relative program counter offset byte ee ff High and low bytes of offset in indexed 16 bit offset addressing rr Relative program counter offset byte EXT Extended addressing mode SP Stack pointer ff Offset byte in indexed 8 bit offset addressing X Index register H Half carry flag 2 Zero flag hh II High and low bytes of operand address in extended addressing Immediate value Interrupt mask A Logical AND ii Immediate operand byte v Logical OR IMM Immediate addressing mode e Logical EXCLUSIVE OR INH Inherent addressing mode Contents of IX Indexed no offset addressing mode Negation two s complement 1 1 Indexed 8 bit offset addressing mode lt Loaded with IX2 Indexed 16 bit offset addressing mode If M Memory location Concatenated with N Negative flag 1 Set or cleared n Any bit Not affected M68HC05 Applications Guide Rev 4 0 126 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com apo Jo jequnv epoodo jorasug ep
171. able Bits e Communication may be Interrupt Driven Receiver Receiver Data Register Full Flag Error Detect Flags Framing Noise Overrun dle Line Detect Flag Receiver Wakeup Function idle or address bit Transmitter e Transmit Data Register Empty Flag Transmit Complete Flag for modem control Break Send 3 11 1 SCI Transmitter The SCI transmitter block diagram is shown in Figure 3 21 The heart of the transmitter is the transmit serial shift register near the top of the figure Usually this shift register obtains its data from the write only transmit buffer Data is transferred into the transmit buffer when software writes to the SCI data register SCDAT Whenever data is transferred into the shifter from the transmit buffer a zero is loaded into the LSB of the shifter to act as start bit and a logic one is loaded into the last bit position to act as a stop bit In the case of a preamble the shifter is M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 137 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data 1X BAUD RATE CLOCK loaded with all ones including the bit position usually holding the logic zero start bit A preamble is loaded each time the transmit enable bit is written from zero to one In the case of a send break command the shifter is loaded with all zeros including the last bit positio
172. able bits are located in associated control registers The interrupt flags and enable bits are never contained in the same register If the enable bit is a logic zero it blocks the interrupt from occurring but does not inhibit the flag from being set Reset clears all enable bits to preclude interrupts during the reset procedure The general sequence for clearing an interrupt is a software sequence of first accessing the status register while the interrupt flag is set followed by a read or write of an associated register When any of these interrupts occur and the enable bit is a logic one normal processing is suspended at the end of the current instruction execution Figure 3 14 shows how interrupts fit into the normal flow of CPU instructions Interrupts cause the processor registers to be saved on the stack and the interrupt mask I bit to be set to prevent additional interrupts The appropriate interrupt vector then points to the starting address of the interrupt service routine refer to Figure 3 15 and Table 3 8 for vector location Upon completion of the interrupt service routine the RTI instruction which is normally the last instruction of the routine causes the register contents to be recovered from the stack followed by a return to normal processing The interrupt mask bit I bit will be cleared if and only if the corresponding bit stored in the stack is zero M68HC05 Applications Guide Rev 4 0 128 MC68HC705C8 F
173. able from a Motorola distributor or directly from the MC68HC705C8 The shift register outputs QA QH of the MC74HC595 will be monitored with an oscilloscope In this example the MISO line is not used The shifter is selected by the general purpose output PC3 but could have been driven by any general purpose output The SS pin of the MC68HC705C8 is an input in master mode and must be tied high M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 161 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data 45 SYSTEM POWER Vpp V I GND PD3 MOSI SERIAL IN PARALLEL MONITOR PD4 SCK SHIFT CLK OUTPUTS W SCOPE 29 LAT CLK FROM PGMR BOARD OR MC68HC705C8 C74HC595 SERIAL TO PARALLEL SHIFT REGISTER Figure 3 40 SPI Application Example Diagram To initialize the SPI function the SPCR SPIE SPE MSTR CPOL CPHA SPR1 SPRO bits need to be written For this application the SPCR was initialized with 9601010000 or 50 SPIE 20 No interrupts involved in this application SPE 1 Enable the SPI system 0 Don t bit MSTR 1 MC68HC705C8 is the master CPOL 20 Selects clock rest at low value CPHA 0 MC74HC595 accepts data at rising clock edge SPR1 20 Internal processor clock divide by two SPRO 0 Shift rate 2 500 kHz
174. achine Forms Mode Opcode Cycles Code and Cycles BSR rel REL AD rr 6 M68HC05 Applications Guide Rev 4 0 266 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com CLC Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc C bit 0 Instruction Set Details M68HOC05 Instruction Set Clear Carry Bit CLC Clears the C bit in the CCR CLC may be used to set up the C bit prior to a shift or rotate instruction involving the C bit H 2 C 1 1 1 0 0 Cleared Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles CLC INH 98 2 M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details For More Information On This Product Go to www freescale com 267 CLI Operation Description Condition Codes and Boolean Freescale Semiconductor Inc Instruction Set Details Clear Interrupt Mask Bit bit lt 0 CLI Clears the interrupt mask bit in the CCR When the bit is clear interrupts are enabled There is a one E clock cycle delay in the clearing mechanism for the bit so that if interrupts were previously disabled the next instruction after a CLI will always be executed even if there was an interrupt pending prior to e
175. ails Corrected March 2002 40 MP accumulator with 270 Appendix A Instruction Set Details Corrected 297 Boolean formulae for subtract SUB instruction NOTE As this document was originally released in 1989 there have been some changes in Motorola s procedures For example there are references in this document to an electronic bulletin board system BBS for freeware BBS has been replaced with the World Wide Web For freeware and any other referenced documentation please refer to http Awww motorola com semiconductors M68HC05 Applications Guide Rev 4 0 4 Applications Guide For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Applications Guide M68HC05 List of Sections Section 1 General Description 21 Section 2 Microcontroller Operation 29 Section 3 MC68HC705C8 Functional Data 73 Section 4 187 Appendix A Instruction Set Details 233 Appendix Review Questions 303 M68HC05 Applications Guide Rev 4 0 MOTOROLA List of Sections 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Sections M68HCO5 Applications Guide Rev 4 0 6 List of Sections MOTOROLA For More Information On This Product Go to www freescale com Freescale
176. al a 16 bit value 0100 ORG 100 Set program starting point 0100 ae 02 TOP LDX 502 Initialize index register 0102 a6 05 LDA 505 Read value into A O A 0005 O B 0102 O C 0103 O D a605 M68HC05 Applications Guide Rev 4 0 MOTOROLA Review Questions 309 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions 25 In the following instruction sequence a value is read into the accumulator From what address is this value being read It may be helpful to look at the machine code as well as the mnemonic instructions 0003 SAM EQU 03 SAM equal 8 bit value 1400 LARRY EQU 1400 LARRY equal a 16 bit value 0100 ORG 100 Set program starting point 0100 ae 02 TOP LDX 502 Initialize index register 0102 b6 05 LDA 05 Read value into A O A 0005 O B 0102 O C 0103 O D b605 26 In the following instruction sequence a value is read into the accumulator From what address is this value being read It may be helpful to look at the machine code as well as the mnemonic instructions 0003 SAM EQU 03 SAM equal an 8 bit value 1400 LARRY EQU 1400 LARRY equal a 16 bit value 0100 ORG 100 Set program starting point 0100 ae 02 TOP LDX 502 Initialize index register 0102 c6 01 00 LDA TOP Read value into A O A 0003 O B 01 00 O C 0103 O D 0104 M68HC05 Applications Guide Rev 4 0 310 Review Questions MOTOROLA For More In
177. ale Semiconductor Inc Instruction Set Details MUL Multiply Unsigned Operation lt Xx A MUL Description Multiplies the eight bits in the index register by the eight bits in the accumulator to obtain a 16 bit unsigned number in the concatenated index register and accumulator After the operation X contains the upper 8 bits of the 16 bit result Condition Codes and Boolean 7 Formulae 1 1 1 EN 0 H 0 Cleared 0 Cleared Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Operand s Cycles Code and Cycles MUL INH 42 11 M68HC05 Applications Guide Rev 4 0 282 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com NEG Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc Instruction Set Details M68HC05 Instruction Set Negate N EG lt or X lt lt M Replaces the contents of ACCA with its twos complement Note that the value 80 is left unchanged R7 Set if MSB of result is set cleared otherwise 2 R7 R6 e R5 R4 e R2 R1 Set if result is 00 cleared otherwise R7 R6 R5 R44 R3 R2 R1 RO Set if there is a b
178. ample consider the BCD addition of 949 149 1049 The computer adds 0000 10015 0000 00015 0000 10102 but 1010215 equivalent to Aig which is not a valid BCD value When the computer finishes the calculation a check is performed to see if the result is still a valid BCD value If there was any carry from one BCD digit to another or if there was any invalid code a sequence of steps would be performed to correct the result to proper BCD form 0000 1010 is corrected to 0001 00005 BCD 10 in this example In most cases it is inefficient to use BCD notation in computer calculations It is better to change from decimal to binary as information is entered do all computer calculations in binary and change the binary result back to BCD or decimal as needed for display First not all computers are capable of doing BCD calculations because they need a digit to digit carry indicator which is not present on all computers though Motorola MCUs do have this half carry indicator Secondly forcing the computer to emulate human behavior is inherently less efficient than allowing the computer to work in its native binary system 2 4 1 Computer Memory Before the operation of the CPU can be discussed in detail some conceptual knowledge of computer memory is required In many beginning programming classes memory is presented as being similar to a matrix of pigeon holes where you can save messages and other information The pigeon holes we are refer
179. ation On This Product Go to www freescale com Freescale Semiconductor Inc 8 705 8 Functional Data The following is a list of all M68HCO5 instructions that can use the inherent addressing mode M68HC05 Applications Guide Rev 4 0 Instruction Arithmetic Shift Left Arithmetic Shift Right Clear Carry Bit Clear Interrupt Mask Bit Clear Complement Decrement Increment Logical Shift Left Logical Shift Right Multiply Negate No Operation Rotate Left thru Carry Rotate Right thru Carry Reset Stack Pointer Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Bit Enable IRQ Stop Oscillator Software Interrupt Transfer Accumulator to Index Register Test for Negative or Zero Transfer Index Register to Accumulator Enable Interrupt Halt Processor Mnemonic ASLA ASLX ASRA ASRX CLC CLI CLRA CLRX COMA COMX DECA DECX INCA INCX LSLA LSLX LSRA LSRX MUL NEGA NEGX NOP ROLA ROLX RORA RORX RSP RTI RTS SEC SEI STOP SWI TAX TSTA TSTX TXA WAIT 102 68 705 8 Functional Data For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc MC68HC705C8 Functional Data Addressing Modes 3 7 2 Immediate Addressing Mode In the immediate addressing mode the operand is contained in the byte immediately following the opcode This mode is used to hold a value or constant which is known at the time the program is wr
180. based on the information in this document Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expe
181. ble amount of time to respond to the event software can tell exactly when the event occurred M68HC05 Applications Guide Rev 4 0 MOTOROLA 68 705 8 Functional Data 169 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data By recording the times for successive edges on an incoming signal software can determine the period and or pulse width of the signal To measure a period two successive edges of the same polarity are captured To measure a pulse width two alternate polarity edges are captured For example to measure the pulse width for a high going pulse capture the time at a rising edge and subtract this time from the time captured for the subsequent falling edge When the period or pulse width is known to be less than a full 16 bit counter overflow period the measurement is very straightforward The counter repeats every 65 536 timer clocks which is equivalent to 262 144 internal processor clock cycles For period or pulse widths that extend over the full 16 bit counter period write software to keep track of the overflows of the 16 bit counter Examples where measurement of a period or pulse width would be used are the period of a pendulum swing or the AC line frequency to distinguish between 50 and 60 Hz Another important use for the input capture function is to establish a time reference In this case an input capture function is used
182. branch to TOP if bit 7 of port B is clear In this particular case the second sequence is better than the first sequence for several reasons The second sequence is more straightforward less chance for confusion it takes one less byte of machine code and it executes one cycle faster than the three line sequence However in some cases the operand PORTB is needed in the accumulator for some other reason thus the first instruction sequence based on the N bit trick becomes the slightly better choice From a practical point of view the differences between these two approaches are very small and either would work well in an application 2 7 1 4 Subroutine Calls and Returns The jump to subroutine JSR and branch to subroutine BSR instructions automate the process of leaving the normal linear flow of a program to go off and execute a set of instructions and then return to where the normal flow left off The set of instructions outside the normal program flow is called a subroutine A JSR or BSR instruction is used to go from the running program to the subroutine and a return from subroutine RTS instruction is used to return to the program from which the subroutine was called The following shows lines of an assembler listing which will be used to demonstrate how the CPU executes a subroutine call Assume that the M68HC05 Applications Guide Rev 4 0 60 Microcontroller Operation MOTOROLA For More Information On This Produc
183. cale Semiconductor Inc 8 705 8 Functional Data Figure 3 24 Table 3 10 and Table 3 11 illustrate the divider chain used to obtain the baud rate clock transmit clock For example using 4 2 crystal the internal processor clock is 2 MHZ The divided frequencies shown in Table 3 10 represent baud rates which are the highest transmit baud rate Tx that can be obtained by a specific crystal frequency and only using the prescaler division Lower baud rates may be obtained by providing a further division using the SCI rate select bits shown below for some representative prescaler outputs CRYSTAL FREQUENCY FIXED 2 5 1 5 0 PRESCALER CONTROL N SCR2 SCRO SCISELECT RATE CONTROL M INTERNAL gt PROCESSOR CLOCK 5 PRESCALER OUTPUT FREQUENCY IS 16 TIMES THE VALUES IN TABLE 3 4 RECEIVER CLOCK 16X BAUD RATE FREQUENCY IS 16 TIMES THE VALUES IN TABLE 3 6 TRANSMITTER CLOCK 1X BAUD RATE Figure 3 24 Rate Generator Division Table 3 10 Prescaler Baud Rate Frequency Output SCP Bit Clock 1 Crystal Frequency MHz 1 0 Divided By 4 194304 4 0 2 4576 2 0 1 8432 0 0 1 131 072 kHz 125 000 kHz 76 80 kHz 62 60 kHz 57 60 kHz 0 1 3 43 691 kHz 41 666 kHz 25 60 kHz 20 833 kHz 19 20 kHz 1 0 4 32 768 kHz 31 250 kHz 19 20 kHz 15 625 kHz 14 40 kHz 1 1 13 10 082 kHz 9600 Hz 5 907 kHz 4800 Hz 4430 Hz 1 The c
184. ce Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc Instruction Set Details M68HC05 Instruction Set Branch if Higher BHI lt PC 0002 Rel if 7 20 i e if gt unsigned binary numbers Causes a branch if both C and Z are cleared If the BHI instruction is executed immediately after execution of a CMP or SUB instruction the branch will occur if the unsigned binary number in ACCA was greater than the unsigned binary number in M See BRA instruction for further details of the execution of the branch H 2 1 1 1 None affected Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles BHI rel REL 22 rr 3 The following table is a summary of all branch instructions Test Boolean Mnemonic Opcode Complementary Branch Comment r gt m C Z 0 BHI 22 BLS 23 Unsigned 0 BHS BCC 24 rm BLO BCS 25 Unsigned r m Z 1 BEQ 27 26 Unsigned r lt m C Z 1 BLS 23 r gt m BHI 22 Unsigned rm C 1 BLO BCS 25 BHS BCC 24 Unsigned Carry 1 BCS 25 No Carry BCC 24 Simple r 0 2 1 27 r 0 BNE 26 Simple Negative N 1 BMI 2B Plus BPL 2A Simple Mask 1 5 2D Mask 0 BMC 2 Half Carry H 1 BHCS 29 No Half Carry BHCC 28 Simple IRQ Pin High 2F IRQ Low BIL 2E Simple Always BRA 20 Never BRN 21 Unco
185. code A6 would have been chosen instead of B6 Field 6 is called the comment field and is not used by the assembler to translate the program into machine code Rather the comment field is used by the programmer to document the program Although the CPU does not use this information during program execution a good programmer knows that it is one of the most important parts of a good program The comment 6 for this line of the program says read sw at MSB of port B This comment tells someone who is reading the listing why port B is being read which is essential for understanding how the program works An entire line can be made into a comment line by using an asterisk as the first character in the line In addition to good comments in the listing it is also important to document programs with a flowchart or other detailed information explaining the overall flow and operation of the program 2 6 5 CPU View of a Program Figure 2 10 a memory map of the MC68HC705C8 shows how the example program fits in the memory of the MCU This figure is the same as Figure 2 4 except that a different portion of the memory space has been expanded to show the contents of all locations in the program Figure 2 10 shows that the CPU sees the example program as a linear sequence of binary codes including instructions and operands in successive memory locations The CPU begins this program with its program counter PC pointing at the first byte in the
186. conductor Inc Applications Thermostat Project Details The programs written for this thermostat application will be written in assembly language on a PC using the MCU instruction set commands An assembler program contained in the PC memory will translate the programs into machine language i e a series of binary codes of 0 and 1 which the MCU understands This code will be put into the OTPROM or EPROM to be debugged 4 5 1 Hardware Details The best way to learn about MCUs is to try this application example thermostat project and develop additional projects in your area of interest Even if you choose not to duplicate this thermostat project you can still benefit from studying the documentation in this example Figure 4 1 is the schematic diagram for the thermostat project For development the MC68HC705C8 is being replaced by the M68HC05 board In this schematic diagram only the I O circuitry is shown To see the other MCU connections refer to the schematic diagram of the PGMR board in the Programmer Board User s Manual included with the PGMR board M68HC05 Applications Guide Rev 4 0 MOTOROLA Applications 197 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications
187. ct MOTOROLA Freescale Semiconductor Inc Review Questions Review Questions Answers and Explanations 0100 10 00 PROG2 5 0 500 5 Set port bit 0 0102 11 00 BCLR 0 500 5 Clear port Abit 0 0104 20 fa BRA PROG2 3 Repeat loop continuously BSET 0 00 BCLR 0 00 BRA BSET 0 00 PROG2 PROCESSOR CLOCK INT PAO PIN PROG2 5 PERIOD 132 0100 a6 01 PROG3 LDA 501 2 Pattern for bit 0 high 0102 5f CLRX 3 Pattern for bit 0 low 0103 7 00 LOOP3 STA 00 4 Write to port A 0105 bf 00 STX 00 4 Write to port A 0107 20 fa BRA LOOP3 3 Repeat loop continuously LDA CLRX STA 00 STX 00 BRA STA 00 STX 00 BRA 501 PROG3 PROG3 PROCESSOR CLOCK INT PROG3 G MK PERIOD 11 M68HC05 Applications Guide Rev 4 0 MOTOROLA Review Questions 331 For More Information On This Product Go to www freescale com PROCESSOR CLOCK INT PAO PIN PROG4 LDA 00 EOR 501 33 34 35 Freescale Semiconductor Inc Review Questions 0100 b6 00 PROG4 LDA 00 3 Read present port A data 0102 a8 01 EOR 501 2 Form new port A pattern 0104 b7 00 STA 00 4 Write to port A 0106 20 8 BRA PROG4 3 Repeat loop continuously STA 00 BRA LDA 00 EOR STA 00 PROG4 01 LDA 00 EOR 5 500 PROG4 5501 PULSE HIGH 12 5 lt lt PERIOD 24 gt
188. ct These figures summarize the most important information needed by the programmer BIT 7 6 5 4 3 2 1 BIT 0 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRAO 04 DDRA l l l l l l l 1 1 1 1 1 1 1 1 INIT TO FF OUT OUT OUT OUT OUT OUT OUT OUT ALL OUTPUTS 00 PORTA A A A A PAT PA6 5 4 PA2 1 0 NAMES REF LCD LCD LCD LCD LCD LCD LCD LCD THERMOSTAT DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATAO FUNCTION 4 5 6 7 8 9 10 MCU PIN NUMBER 14 13 12 11 10 9 8 7 LCD PIN NUMBER SEE PORT C FOR LCD SIGNALS E RS AND R W Figure 4 3 Port A Summary 200 For More Information On This Product Go to www freescale com Applications MOTOROLA Freescale Semiconductor Inc Applications Thermostat Project Details BIT7 6 5 4 3 2 1 BIT 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRBO 05 DDRB 1 0 0 0 0 1 1 1 1 INIT TO 0 IN IN IN IN OUT OUT OUT OUT HALF IN HALF OUT 501 PORTB PB7 PB6 5 4 PB3 PB2 PBO PIN NAMES REF BOT TOP LEFT RIGHT THERMOSTAT Row lt INPUTS gt Row OUTPUTS gt COL FUNCTION 19 18 17 16 15 14 13 12 MCU PIN NUMBER 1 2 3 A 2 e oe e 10k 4 5 6 B mx 0k AAVV Rests Saar
189. d the second to specify the direct address where the accumulator will be stored The two bytes are shown as B7 dd in the machine code column of the table We will be discussing the addressing modes in more detail later but the following brief description will help in understanding how the CPU executes this instruction In direct addressing modes the CPU assumes the address is in the range of 0000 through 001 thus there is no need to include the upper byte of address of the operand in the instruction since it is always 00 The table at the bottom of the STA description found in Appendix A Instruction Set Details shows that the direct addressing version of the STA instruction takes four CPU cycles to execute During the first cycle of this STA instruction the CPU reads the opcode B7 which identifies the instruction as the direct addressing version of the STA instruction and advances the PC to the next memory location During the second cycle the CPU places the value from the PC on the internal address bus and reads the low order byte of the direct address 02 for example The CPU uses the third cycle of this STA instruction to internally construct the full address where the accumulator is to be stored and also advances the PC so it points to the next address in memory the address of the opcode of the next instruction M68HCO5 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation 57 For More Infor
190. dd 06 06e1 06e3 06e5 06e7 06e9 06ea 06eb lffe lffe M68HC05 Applications Guide Rev 4 0 b7 a6 b7 a6 b7 b7 b6 2a a6 b7 b6 2b 24 0 40 bb b7 20 al 25 b7 b6 a0 0 2 bb b7 81 3G 01 a0 20 ae 30 af 0 19 2 0 af Oa fa 25 af Oa bo la 64 08 31 ae a0 64 af af Oa 00 Freescale Semiconductor Inc Applications Sheet 21 of 21 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK KKKKKKKK CNVERT 105 CVPOS LPAS10 XVERT ASC100 STA DA pope DPPH FG W Di Uum ruzuututu mut HOCH LO DA TA DA UB NC UB PL EC DD DD STA RTS E CNVERT Convert binary value to ASCII Enter with binary value Result stored ASC100 5 10 5 1 100 s digit defaults to blank sp gt but could be 1 or minus depending on valu 5 10 and ASC1 digits default to zeros Result can be 99 through 127 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK TEMPA 520 5 100 0 ASC10 ASC1 TEMPA CVPOS 5 100 5 10 10 105 5 10 10 ASC1 5
191. ddress thus the CPU continues the program with the instruction following the JSR or BSR instruction that originally called the subroutine The delay routine of Figure 2 7 involves an inner loop INNRLP within another loop OUTLP The inner loop consists of two instructions executed 256 times before X reaches 00 and the BNE branch condition fails This amounts to six cycles at 1 us cycle times 256 which equals 1 536 ms for the inner loop The outer loop executes 32 times The total execution time for the outer loop is 32 1536 9 or 32 1545 49 44 ms The miscellaneous instructions in this routine other than those in the outer loop total 21 cycles thus the total time required to execute the DLY50 routine is 49 461 ms including the time required for the JSR instruction that calls DLY50 16 bit timer system in the MC68HC705C8 can also be used to measure time The timer based approach is actually preferred because the CPU can perform other tasks during the delay and the delay time is not dependent on the exact number of instructions executed as it is in DLY50 2 6 4 Assembler Listing After a complete program or subprogram is written it must be converted from mnemonics into binary machine code that the CPU can later execute A separate computer system such as an IBM PC is used to perform this conversion to machine language A computer program called an assembler is used The assembler reads the mnemonic version of the progra
192. ddressing Machine Code HCMOS Modes Machine Forms Mode Opcode Operand s Cycles Code and Cycles AND opr IMM A4 i 2 AND DIR 3 AND opr EXT C4 hh 4 AND X IX F4 3 AND opr X 1 4 ff 4 AND opr X IX2 D4 ee ff 5 M68HC05 Applications Guide Rev 4 0 240 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com ASL Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc Instruction Set Details M68HC05 Instruction Set Arithmetic Shift Left Same as LSL ree ASL Shifts all bits of the ACCA X or M one place to the left Bit 0 is loaded with a zero The C bit in the CCR is loaded from the most significant bit of ACCA X or M R7 Set if MSB of result is set cleared otherwise 7 R7 R6 R5 R4 R3 eR2 R1 Set if all bits of the result are cleared cleared otherwise C b7 Set if before the shift the MS B of the shifted value was set cleared otherwise Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles ASLA INH A 48 3 ASLX INH X 58 3 ASL opr DIR 38 dd 5 ASL X IX 78 5 ASL opr X 68 ff 6 M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details For More Information On This Prod
193. ddressing Source Addressing Machine Code HCMOS Modes Machine Forms mode Opcode Cycles Code and Cycles BCS rel REL 25 rr 3 The following table is a summary of all branch instructions Test Boolean Mnemonic Opcode Complementary Branch Comment r gt m C Z 0 BHI 22 r lt m BLS 23 Unsigned r2m C20 BHS BCC 24 r lt m BLO BCS 25 Unsigned r m Z 1 BEQ 27 26 Unsigned lt C Z 1 BLS 23 r gt m BHI 22 Unsigned r lt m 1 5 25 BHS BCC 24 Unsigned Carry 1 BCS 25 No Carry BCC 24 Simple r 0 2 1 27 r 0 BNE 26 Simple Negative N 1 BMI 2B Plus BPL 2A Simple Mask 1 5 2 Mask 0 BMC 2C Simple Half Carry H 1 BHCS 29 No Half Carry BHCC 28 Simple IRQ Pin High 2 IRQ Low BIL 2E Simple Always BRA 20 Never BRN 21 Unconditional r register or X m memory operand M68HCO05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details For More Information On This Product Go to www freescale com 245 Freescale Semiconductor Inc Instruction Set Details BEQ Branch if Equal BEQ Operation lt 0002 Rel if Z 1 Description Tests the state of the Z bit in the CCR and causes a branch if Z is set Following a CMP or SUB instruction BEQ will cause a branch if the arguments were equal See BRA instruction for further details of the execution of the branch Condition Codes and Boolean H 7
194. de 58 271 3 Conditional 59 2 7 1 4 Subroutine Calls and Returns 60 2 7 2 Playing e dod o GEO RR RU EO EE RR ERR 63 28 On Chp 553395555 hd 68 2 8 1 Serial Communications Interface 5 70 2 8 2 Serial Peripheral Interface 70 2 8 3 Timer 71 2 8 4 72 2 8 5 Other On Chip 5 72 M68HCO5 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation 29 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation 2 2 Introduction A microcontroller unit MCU is a complete computer system on a single silicon chip In a great many controller applications the MCU can satisfy all system requirements with no additional integrated circuits ICs Due to very low cost and a high degree of flexibility these powerful new MCU devices are finding their way into many applications that were previously accomplished with combinational logic or even by mechanical means As a result there are many experienced engineers who need to become familiar with the function and application of Motorola MCUs This section which is specifically designed for those engineers is also a good reference fo
195. de keys 0 00 01 20 SFE SFF KYPAD CHK401 00 KYLOOP 01 FOUND CHK4FE CHK4FF XKYPAD KEYVAL indicates ASCII equivalent of key or debounce status as follows no key pressed key closed 50mS ago look for any closure 7F key found debounced amp decoded not seen key recognized by some task wait for release key released 50mS ago debounce release KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKEK 9 D D WE D p E Zh 2 C E Dd Dd x x 49 H D WQWWE D H D wW Pe Z Jg QUuUQOUot debounce decode now Check for amp decode keys KEYVAL KEYVAL indicates what to do CHK401 If not 0 Check for 01 50 Turn all cols PORTB Reads rows in upper 4 SFO Mask away cols XKYPAD Exit if no key KEYVAL 501 XKYPAD Exit key will be decoded in 50mS 501 KEYVAL 501 CHK4FE not 0 Check for SFE 30 Pointer to last pair in KYTBL KYTBL X Get row col pattern PORTB Drive cols PORTB Check for row amp col match FOUND key found Point to next pair of entries in KYTBL KYLOOP Loop if more entri
196. delays The programmable timer is based on a 16 bit free running counter preceded by a prescaler that divides the internal processor clock by four A timer overflow function allows software to extend its timing capability beyond the range of 16 bits All activities of the timer are referenced to this one free running counter so all timer functions have a known relationship to each other From the MCU viewpoint physical time is represented by the count in this free running counter and the counter can be read at any time to tell what time it is M68HCO5 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 163 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data FLOWCHART MNEMONIC PROGRAM INIT LDA 5 DDRC SET INITIAL CONDITIONS LDA 0 PORT OUTPUTS 5 PORTC DATA PATTERN 1110 0000 PORT CLR SPIVAL INITIALIZE SPI 6 SET SPIVAL 0 4401010000 SPCR gt NO TOP LDA PORTB BPL TOP YES DELAY TO DEBOUNCE JSR DLY50 ENABLE 74 595 SEND DATA VIA SPI 2 LDA SPIVAL INCREMENT SPIVAL STA SPDR INC SPIVAL NO DONE SPIF 21 HERE BRCLR 7 SPSR HERE DISABLE 74HC595 BSET 3 PORTC TURN ON LED FOR BCLR 6 PORTC LDA 320 DLYLP JSR DLY50 DECA BNE DLYLP BSET 6 PORTC OFFLP BRSET 7 PORTB OFFLP DELAY TO DEBOUNCE Figure 3 41 SPI
197. device gt A master and a slave exchange 8 bit data characters D A master device sends a start bit 8 data bits and a stop bit to a slave See 3 12 1 Data Movement M68HC05 Applications Guide Rev 4 0 MOTOROLA Review Questions 337 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions M68HC05 Applications Guide Rev 4 0 338 Review Questions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOW TO REACH US USA EUROPE LOCATIONS NOT LISTED Motorola Literature Distribution P O Box 5405 Denver Colorado 80217 1 303 675 2140 or 1 800 441 2447 JAPAN Motorola Japan Ltd SPS Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 8573 Japan 81 3 3440 3569 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 TECHNICAL INFORMATION CENTER 1 800 521 6274 HOME PAGE http Awww motorola com semiconductors Information in this document is provided solely to enable system and software implementers to use Motorola products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits
198. disabled See BRA instruction for further details of the execution of the branch H 7 1 1 1 None affected Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles BMS rel REL 2D rr 3 The following table is a summary of all branch instructions Test Boolean Mnemonic Opcode Complementary Branch Comment C Z 0 BHI 22 BLS 23 Unsigned 0 BHS BCC 24 rm BLO BCS 25 Unsigned r m Z 1 BEQ 27 26 Unsigned r lt m C Z 1 BLS 23 r gt m BHI 22 Unsigned rm C 1 BLO BCS 25 BHS BCC 24 Unsigned Carry 1 BCS 25 No Carry BCC 24 Simple r 0 2 1 27 r 0 BNE 26 Simple Negative N 1 BMI 2B Plus BPL 2A Simple Mask 1 5 2D Mask 0 BMC 2 Half Carry H 1 BHCS 29 No Half Carry BHCC 28 Simple IRQ Pin High BIH 2F IRQ Low BIL 2E Simple Always BRA 20 Never BRN 21 Unconditional r register ACCA or X m memory operand M68HC05 Applications Guide Rev 4 0 258 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc Instruction Set Details M68HC05 Instruction Set Branch if Not Equal BN E PC PC 0002 Rel
199. dress location Both write operations must occur in the correct order prior to timeout but any number of instructions may be executed between the two write operations The elapsed time between adjacent software reset sequences must never be greater than the COP timeout period 215 XTAL 4 0 MHz XTAL 3 5796 XTAL 2 0 MHz XTAL 1 0 MHz CM1 CMO Div E 2 0 MHz 1 7897 MHz E 1 0 MHz E 0 5 MHz By Timeout Timeout Timeout Timeout 0 0 1 16 38 ms 18 31 ms 32 77 ms 65 54 ms 0 1 4 65 54 ms 73 24 ms 131 07 ms 262 14 ms 1 0 16 262 14 ms 292 95 ms 524 29 ms 1 048 1 1 64 1 048 1 172 2 097 4 194 M68HCO5 Applications Guide Rev 4 0 98 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Addressing Modes Upon detection of a timeout condition the COP watchdog timer if enabled by COPE 1 will cause a system reset to be generated This reset is issued to the external system via the bidirectional RESET pin for four bus cycles 3 6 4 3 Clock Monitor Reset When a clock failure is detected by the clock monitor and CME 1 a system reset will be generated When CME is set the clock monitor detects the absence of the internal bus clock for more than a certain period of time When CME is cleared the clock monitor is disabled The timeout period is dependent on pr
200. dressing Modes Machine Code and Cycles Freescale Semiconductor Inc Instruction Set Details M68HC05 Instruction Set Load Index Register from Memory LDX X lt Loads the contents of the specified memory location into the index register The condition codes are set according to the data N R7 Set if MSB of result is set cleared otherwise 7 R7 R6 R5 eR4 R3e R2 R1 RO Set if result is 00 cleared otherwise Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles LDX opr IMM AE i 2 LDX opr DIR BE dd 3 LDX opr EXT CE hh 4 LDX X IX FE 3 LDX opr X ff 4 LDX opr X IX2 DE ee ff 5 M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details 279 For More Information On This Product Go to www freescale com LSL Operation Description Condition Codes and Boolean Formulae Freescale Semiconductor Inc Instruction Set Details Logical Shift Left Same as ASL LSL Shifts all bits of the ACCA X or M one place to the left Bit 0 is loaded with zero The C bit in the CCR is loaded from the most significant bit of ACCA X or M R7 Set if MSB of result is set cleared otherwise Z R7 R6 R5 eRA4 R3 R2 R1 RO Set if result is 00 cleared otherwise
201. e Rev 4 0 192 Applications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Software Development Methods 4 4 1 Freeware Motorola has an electronic bulletin board system BBS dedicated to support Motorola microprocessor units MPUs and microcontroller units MCUs Freeware the name for this BBS is on line 24 hours a day except when system maintenance is required The following is a sample of the available freeware topics 8 Bit MCUs 16 and 32 Bit MPUs Evaluation Boards EVBs and Evaluation Modules EVMs Development Systems HDS 200 and HDS 300 IBM PC Software Tools assemblers etc Conference and Special Interest Groups To use the BBS you need to obtain the following hardware and software items 1 1200 2400 baud modem 2 A terminal or personal computer PC with communications software e g Kermit ProComm etc 3 Atelephone line Use the following procedure to log onto the freeware line 1 Set systems character format to 8 bit no parity 1 stop bit 2 Dial 512 891 3733 or 512 891 FREE 3 Aseries of questions will appear Enter the requested information to log on You are now a registered user 4 Follow the menus for the desired functions e g download upload mail conferences etc On line help is also available M68HC05 Applications Guide Rev 4 0 MOTOROLA Applications 193 For More Informa
202. e 0334 0334 0336 0338 033 9336 033 0340 0342 0344 0346 0348 034 034 034 0350 0353 0354 0356 0358 035a 0356 035 0360 0361 0363 0365 0367 0369 0366 036 036f 0371 0373 0375 0377 0379 0375 0374 0376 al 26 b6 26 b6 aa b7 20 al 26 1 b6 0 4 bl 24 Ic le Sak 20 4a bl 23 a ld b7 20 al 21 la 20 le b6 0a a3 04 le 60 aa 08 02 0 02 54 01 23 02 02 0 44 02 02 b2 3G ac 37 02 02 01 b2 2d 02 08 02 02 02 21 02 ab 02 0 Freescale Semiconductor Inc Applications Sheet 13 of 21 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK DOHVAC 10 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK HVAC Update Fan Heat and Cool outputs Low true outputs will be buffered to drive 24VAC relay coils in HVAC equipment high true in final Heat and Cool requests should not permit short cycle ie a min delay is required between changes Once Heat or Cool requested do not turn off for at least 30 sec Also enforce 30 sec minimum off time to restart Allow 1 around target temp as hysteresis 0 Off 1 Heat 2 Cool 3 Fan Only Zi UE AH DW UO AUP PP Pee El U XD p C
203. e 3 12 4 3 Serial Peripheral Data I O Register SPDR The SPDR Figure 3 39 in the master MCU device is used to transmit data to and receive data from the slave device Only a write to this register in a master will initiate transmission reception of data The data is then loaded directly into the 8 bit shift register where eight bits are shifted out on the MOSI pin to the slave while another eight bits are simultaneously shifted in on the MISO pin to the 8 bit shift register At the completion of data transmission the SPIF status bit is set A write or read of the SPDR after reading SPSR with SPIF set will clear SPIF BIT7 6 5 4 3 2 1 BIT 0 Figure 3 39 Serial Peripheral Data I O Register 3 13 SPI Application Example The example application and program are similar to the one shown in 2 6 Programming except the SPI function will be added A switch is connected to an input pin When the switch is closed the program will send data out to a peripheral device using the SPI function and will cause an LED connected to an output pin to light for about one second and then go out The peripheral device used in this application is an MC74HC595 serial to parallel shift register Hardware setup the SPI control register and the software program will be discussed briefly Figure 3 33 shows the hardware connections for the SPI application example The SPI signals at the left of the diagram come from the board an M68HC05 PGMR avail
204. e Operand s Cycles CPX opr IMM 2 DIR B3 dd 3 CPX opr EXT C3 hh 4 3 CPX opr X ff 4 CPX opr X IX2 D3 ee ff 5 M68HC05 Applications Guide Rev 4 0 272 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com DEC Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc Decrement Instruction Set Details M68HC05 Instruction Set DEC lt ACCA 01 or M lt M 01 or X lt X 01 Subtract one from the contents of ACCA X or M The N and Z bits in the CCR are set or cleared according to the result of this operation The C bit is in the CCR is not affected therefore the only branch instructions that are useful following a DEC instruction are BEQ BNE BPL and BMI 1 1 N R7 Set if MSB of result is set cleared otherwise 2 R7 e R6 e R5 R4 R3 R2 R1 Set if result is 00 cleared otherwise Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles DECA NH A 4A 3 DECX INH X 5A 3 DEC opr DIR 3A dd 5 DEC X 7 5 6A ff 6 DEX is recognized by the Assembler as being equivalent to DECX M68HC05 Applications Guide
205. e contents of is 00 cleared otherwise Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Cycles Code and Cycles TSTA INH A 4D 3 TSTX INH X 5D 3 TST opr DIR 3D dd 4 TST X 70 4 TST 1 6D ff 5 M68HCO5 Applications Guide Rev 4 0 300 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc Instruction Set Details M68HC05 Instruction Set Transfer Index Register to Accumulator lt X Loads the accumulator with the contents of the index register The contents of the index register are not altered H 2 1 1 1 None affected Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles TXA INH OF 2 M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details For More Information On This Product Go to www freescale com 301 Freescale Semiconductor Inc Instruction Set Details WAIT Description Condition Codes and Boolean Enable Interrupt Stop Processor WAIT Reduces power consumption by eliminating most dynamic power
206. e low order middle and high order bytes of the 24 bit value respectively R7 Set if MSB of result is set cleared otherwise 7 R7e R6eR5 R4 R3 R2 R1 Set if all bits of the result are cleared cleared otherwise Set if before the rotate the LSB of was set cleared otherwise Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles RORA INH A 46 3 RORX INH X 56 3 ROR opr DIR 36 dd 5 ROR X IX 76 5 ROR 66 ff 6 M68HCO5 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details 287 For More Information On This Product Go to www freescale com Operation Description Condition Codes and Boolean Freescale Semiconductor Inc Instruction Set Details Reset Stack Pointer SP lt 00FF Resets the stack pointer to the top of the stack RSP H 7 C Formulae 1 1 1 None affected Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Operand s Cycles Code and Cycles RSP INH 9 2 M68HC05 Applications Guide Rev 4 0 288 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com RTI Operation Description Condition Codes and Boolean Formulae Source Forms Addr
207. ead back an arbitrary value which you just wrote to that address O A 0004 O B 0050 O C 00FF gt D 1000 see Figure 3 7 MC68HC705C8 Memory Map 0050 and 00FF are RAM addresses and can obviously be read back after being written 0004 is the data direction register for port A see 3 10 1 Parallel 42 For an MC68HC705C8 which of the four following addresses would be the best address to store a product serial number and a variable which changed once a second Refer to the memory map on page 46 O A 0000 O B 002F C 00FF gt D 015F see description of RAM1 3 16 4 Option Register This question was intended to point out that the RAM1 control bit in the OPTION control register can be controlled by software to alternately M68HCO5 Applications Guide Rev 4 0 334 Review Questions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions Review Questions Answers and Explanations enable RAM or PROM during normal operation The result is that both the RAM and the PROM are usable although software is required to choose which is active at any particular time You could enable the PROM and program a serial number into location 015F before shipping a product You could turn on the PROM during startup to read the serial number then change to enable the RAM to use the RAM located at 015F as the storage location fo
208. ed at 1FFE 1FFF and then begins executing instructions starting at that address To change the SCI baud rate what address would you write to O A 000D O B 000E O C 0D00 O D 100E M68HC05 Applications Guide Rev 4 0 308 Review Questions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions Review Questions 21 The half carry bit in the condition code register CCR is used in rounding results of arithmetic operations indicates that the MSB of the accumulator is 1 may be used to adjust the results of BCD add operations indicates a borrow occurred during a subtract operation 22 MC68HC705C8 system which uses interrupts what is the maximum possible nesting depth for subroutines without causing errors If one subroutine called a second subroutine that would be a nesting depth of 2 2 32 64 O D 128 23 Which of the following on chip systems would be used to detect problems with the oscillator O A Power on reset O B COP watchdog timer O C Clock monitor D IRQ interrupt 24 Inthe following instruction sequence a value is read into the accumulator From what address is this value being read It may be helpful to look at the machine code as well as the mnemonic instructions 0003 SAM EQU 03 SAM equal 8 bit value 1400 LARRY EQU 1400 LARRY equ
209. eescale Semiconductor Inc 8 705 8 Functional Data 3 6 2 Arithmetic Logic Unit ALU 2 94 3 6 3 d iir 0 Dp TCR 95 3 6 4 iaa ioo d ab nba coded 95 3 6 4 1 Power On Reset sc ced iene ee we ere ae ee ene itis 95 3 6 4 2 Computer Operating Properly Watchdog Tne ROSEL ERROR RR d 97 3 6 4 3 Clock Monitor 99 3 7 Addressing gt gt 2 6 95 53 99 3 7 1 Inherent Addressing 101 3 7 2 Immediate Addressing 103 3 7 8 Extended Addressing 104 3 7 4 Direct Addressing 105 3 7 8 Indexed Addressing Modes 108 3 5 5 1 Indexed 1 108 3 7 5 2 Indexed 110 3 7 5 3 Indexed 16 Bit Offset 112 3 7 6 Relative Addressing 113 57 4 Bit Test and Branch Instructions 115 3 7 8 Instructions Organized by 115 3 8 Instruction Sel 5 119 de ee 128 3 9 1 Software Interrupt 129 3 9 2 External 131 3 9 3 Tier DG cicada ke CE deo
210. effl 5 AND opr X E4 ff 4 AND X IX F4 3 ASL opr DIR 38 99 5 ASLA INH 48 3 ASLX Arithmetic Shift Left Same as LSL Cj 0 58 3 ASL opr X b7 bO 1 1 68 ff 6 ASL X IX 78 5 ASR opr DIR 37 99 5 ASRA 47 3 ASRX Arithmetic Shift Right ss 57 3 ASR b7 50 IX1 67 ff 6 ASR X IX 77 5 BCC rel Branch if Carry Bit Clear lt PO 2 rel 0 1 1 REL 24 3 DIR 60 11 dd 5 DIR 61 13 dd 5 DIR 62 15 dd 5 63 17 dd 5 BCLR opr Clear n Mn 0 DIR b4 19 dd 5 DIR 65 1B dd 5 DIR b6 1 dd 5 DIR b7 1F dd 5 BCS rel Branch if Carry Bit Set Same as BLO lt PO 2 1 REL 25 3 BEQ rel Branch if Equal lt 2 2 1 REL 27 3 BHCC rel Branch if Half Carry Bit Clear lt 2 rel H 0 REL 28 3 Branch if Half Carry Bit Set 2 rel 1 REL 29 3 Branch if Higher lt 2 rel Cv 2 0 REL 22 rr 3 BHS rel Branch if Higher or Same lt PC 2 rel 20 REL 24 3 BIH Branch if IRQ Pin High lt 2 rel IRQ 1 REL 2F rr 3 M68HC05 Applications Guide
211. emory with Accumulator Increment Jump Jump to Subroutine Load Accumulator from Memory Load Index Register from Memory Logical Shift Left Logical Shift Right Negate Inclusive OR Rotate Left thru Carry Rotate Right thru Carry Subtract with Carry Store Accumulator in Memory Store Index Register in Memory Subtract Test for Negative or Zero The following is a list of all M68HCO5 instructions that can use the indexed 8 bit offset addressing mode Mnemonic ADC ADD AND ASL ASR BIT CLR CMP COM CPX DEC EOR INC JMP JSR LIDA LDX LSL LSR NEG ORA ROL ROR SBC STA STX SUB TST M68HCO05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data For More Information On This Product Go to www freescale com 111 Freescale Semiconductor Inc MC68HC705C8 Functional Data 3 7 5 3 Indexed 16 Bit Offset In the indexed 16 bit offset addressing mode the effective address is the sum of the contents of the 8 bit index register and the two bytes following the opcode The content of the index register is not changed These instructions are three bytes one for the opcode and two for a 16 bit offset Example Program Listing 0200 6 07 00 LDA 50700 Load accumulator from location pointed to by index reg X 0700 Execution Sequence 0200 06 1 0201 07 2 0202 00 3 4 5 Explanation 1 CPU reads opcode D6 load accumulator using indexed 16 bit offset addressing m
212. en enabled EPGM bit has been written to one Now read the current value of the main timer counter and add a number corresponding to 1 millisecond XTAL 2 MHZ INT CLK 1 MHz 1 timer count 4 us thus 1 ms 250 decimal FA Write this sum to the output compare register so that an output compare will occur when the counter gets to this value In this example the actual EPROM programming time started just before the current time was read from the counter and ended after responding to the output compare and turning off EPGM The small delays for setting up the output compare and the latency for responding to the output compare were not considered because they only make the EPROM programming time longer by a few microseconds As you become a more advanced user of output compare functions you will learn how to correct these details although it is often not necessary This program would have to run from RAM since the EPROM is not usable during programming M68HC05 Applications Guide Rev 4 0 MOTOROLA 68 705 8 Functional Data 173 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data 3 14 6 Output Compare Operation The output compare register is a 16 bit register composed of two 8 bit registers at locations 16 most significant byte and 17 least significant byte The contents of the output compare register are compared with the contents
213. er has not yet been read an overrun condition occurs In the overrun condition data is not transferred and the overrun OR status flag is set to indicate the error M68HCO05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 139 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data 16 BAUD RATE CLOCK 10 11 BIT Rx SHIFT REGISTER PIN BUFFER ALL ONES WAKE UP LOGIC SCDAT Rx BUFFER READ ONLY SCCR2 SCI CONTROL 2 SCI Tx SCI INTERRUPT INTERNAL REQUESTS REQUEST DATA BUS Figure 3 22 SCI Receiver Block Diagram M68HC05 Applications Guide Rev 4 0 140 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com 3 11 3 Registers Freescale Semiconductor Inc MC68HC705C8 Functional Data Serial Communications Interface SCI There are three receiver related interrupt sources in the SCI These flags can be polled by software or when enabled cause SCI interrupt request The receive interrupt enable RIE control bit enables the RDRF and OR status flags to generate hardware interrupt requests The idle line interrupt enable ILIE control bit allows the IDLE status flag to generate interrupt requests The SCI system includes five regis
214. erand ii During the second cycle of the instruction the CPU reads the contents of the byte following the opcode into the accumulator and advances the PC to point at the next location in memory i e the opcode byte of the next instruction While the accumulator was being loaded the N and Z bits in the condition code register were set or cleared according to the data that was loaded into the accumulator The Boolean logic formulae for these bits appears near the middle of the instruction set page The Z bit will be set if the value loaded into the accumulator was 00 otherwise the Z bit will be cleared The N bit will be set if the most significant bit of the value loaded was a logic one otherwise N will be cleared The N negative condition code bit may be used to detect the sign of a twos complement number In twos complement numbers the most M68HCO5 Applications Guide Rev 4 0 58 Microcontroller Operation MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation CPU Operation significant bit is used as a sign bit one indicates a negative value and zero indicates a positive value The N bit may also be used as a simple indication of the state of the most significant bit of a binary value 2 7 1 3 Conditional Branch 00 8 b6 01 2 00 c3 Branch instructions allow the CPU to select one of two program flow paths
215. erating Properly Flag Reading the COP control register clears COPF 1 COP or clock monitor reset has occurred 0 No COP or clock monitor reset has occurred CME Clock Monitor Enable CME is readable and writable at any time 1 Clock monitor enabled 0 Clock monitor disabled M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 97 For More Information On This Product Go to www freescale com 8 705 8 Functional Data Table 3 1 COP Timeout Period versus CM1 and Freescale Semiconductor Inc COPE Computer Operating Properly Enable 1 COP timeout enabled 0 COP timeout disabled CM1 and CMO Computer Operating Properly Mode These two bits are used to select the COP watchdog timeout period see Table 3 1 The actual timeout period is dependent on the system bus clock frequency but for reference purposes Table 3 1 shows the relationship between the CM1 and CMO select bits and the COP timeout period for various system clock frequencies E stands for the system bus clock The default reset condition of the COP mode bits CMI and CM is cleared which corresponds to the shortest timeout period The COP reset register 1D is used to keep the COP watchdog timer from timing out BIT7 2 1 BIT 0 10 COPRR The sequence required to reset the COP watchdog timer is 1 Write 55 to the COP reset register at location ID 2 Write AA to the same ad
216. ero after an RTI was executed After any reset is set and can only be cleared by a software instruction Negative N The bit is set to one when the result of the last arithmetic logical or data manipulation is negative bit 7 of the MSB in the result is a logic one The N bit has other uses By assigning an often tested flag bit to the MSB of a register or memory location you can test this bit simply by loading the accumulator with the contents of that location Zero Z The Z bit is set to one when the result of the last arithmetic logical or data manipulation is zero Carry Borrow C The C bit is used to indicate whether or not there was a carry from an addition or a borrow as a result of a subtraction Shift and rotate instructions operate with and through the carry bit to facilitate multiple word shift operations This bit is also affected during bit test and branch instructions The following illustration is an example of the way condition code bits are affected by arithmetic operations The H bit is not useful after this operation because the accumulator was not a valid BCD value before the operation M68HC05 Applications Guide Rev 4 0 92 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Central Processor Unit ASSUME INITIAL VALUES IN ACCUMULATOR AND CONDITION CODES ACCUMULATOR
217. ers are saved on the stack in the order PCL PCH X A CC Onarreturn from interrupt registers are recovered from the stack in reverse order Figure 3 15 Interrupt Stacking Order 3 9 2 External Interrupt If the interrupt mask I bit of the condition code register has been cleared and the external interrupt pin IRQ has gone low then the external interrupt is recognized When the interrupt is recognized the current state of the CPU is pushed onto the stack and the I bit is set This masks further interrupts until the present one is serviced The interrupt service routine address is specified by the contents of memory location 1FFA and 1FFB The MC68HC705C8 MCU IRQ pin sensitivity is software programmable Either negative edge and level sensitive triggering or negative edge sensitive triggering are available The MC68HC705C8 MCU uses the option register residing at location 1FDF to control the IRQ pin sensitivity M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 131 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data 3 9 3 Timer Interrupt There are three different interrupt flags that will cause a timer interrupt whenever they are set and enabled These three interrupt flags are found in the three MSBs of the timer status register TSR location 13 and all three will vector to the same interrupt service routine 1FF8
218. es KEYVAL No key found set KEYVAL 0 KYTBL 1 XGet key equiv from table KEYVAL 20 lt KEYVAL lt S7F 2 BEEPM Request beep as feedback XKYPAD Exit SFE KEYVAL SFE not check for SFF 50 Turn on all cols PORTB Reads rows in upper 4 SFO Mask away cols XKYPAD Exit if key still closed 5 KEYVAL Set KEYVAL SFF XKYPAD amp Exit SFF KEYVAL SFF XKYPAD If not exit KEYVAL Set KEYVAL 500 RETURN from KYPAD 218 Applications MOTOROLA For More Information On This Product Go to www freescale com Listing Thermostat Example Freescale Semiconductor Inc Applications Thermostat Project Details Sheet 8 of 21 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKEK BEEP Update audible beeper Single 1005 beep on key closure feedback mn Beep 100mS on 2000ff 1000n entry accepted x Beep 1 second to indicate entry error KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK 0216 BEEP EQU Update audible beep 0216 b6 LDA BEEPM BEEPM indicates what to do 0218 26 04 BNE ACTIV Branch if beeper active 021 19 02 BCLR 4 PORTC Turn off beeper 021 20 10 BRA XBEEP amp Exit 021 b4 Times beeps Accumulator has undecre
219. es not make any assumptions about other bits in port A O A PROG1 amp PROG2 gt B PROG2 amp PROG4 C PROG3 amp PROG4 D PROG4 amp 1 Programs 1 and 3 force bits 7 through 1 of port A to zero programs 2 and 4 affect only bit 0 39 MC68HC705C8 which of the following pins is input only pin O A RESET Port D bit 4 SCK gt C Port D bit 7 see Figure 3 1 MC68HC705C8 Microcontroller Block Diagram O D Port A bit 7 This question was intended to emphasize that reset is not an input only pin M68HC05 Applications Guide Rev 4 0 MOTOROLA Review Questions 333 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions 40 What does the following sequence of instructions do 0100 a6 08 START LDA 08 Comments left off intentionally 0102 b7 le STA S1E 0104 8e STOP O A Reset the COP watchdog timer and return to normal program gt B Force a hardware RESET see 3 6 4 3 Clock Monitor Reset O C Store a value 08 in RAM and stop processing D Enables the clock monitor and the COP watchdog timer This question was intended to show a way to force a reset with software which may be useful in some applications This question also reinforces important aspects of the clock monitor system and the STOP instruction 41 For the four following addresses which one would not allow you to r
220. es of the instruction the CPU constructs the complete address where the accumulator will be stored by appending 00 assumed value for the high order half of the address due to direct addressing mode to the 02 read during 28 The accumulator 00 at this time is then stored to this constructed address 0002 2 7 2 Playing Computer Playing computer is a learning exercise where you pretend to be a CPU that is executing a program Programmers often mentally check programs by playing computer as they read through a software routine While playing computer it is not necessary to break instructions down to individual processor cycles Instead instructions are treated as a single complete operation rather than several detailed steps The following paragraphs demonstrate the process of playing computer by going through the subroutine call exercise of Figure 2 11 The playing computer approach to analyzing this sequence is much less detailed than the cycle by cycle analysis done earlier on Figure 2 11 but it accomplishes the same basic goal i e it shows what happens as the CPU executes the sequence After seeing how to do this exercise M68HC05 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation 63 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation you should attempt the same thing with a larger program such as the example of Figure 2 10
221. ess of the next free location on the stack During an MCU reset or the reset stack pointer RSP instruction the stack pointer is set to location 00FF The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack 12 7 5 0 1 1 STACK POINTER SP Figure 3 13 Stack Pointer SP When accessing memory the seven MSBs of the SP are permanently set to 0000011 These seven bits are appended to the six LSB bits to produce an address within the range of 00FF to 00 0 Subroutines and interrupts may use up to 64 decimal locations If 64 locations are exceeded the stack pointer wraps around and loses the previously stored information A subroutine call occupies two locations on the stack an interrupt uses five locations 3 6 2 Arithmetic Logic Unit ALU The arithmetic logic unit ALU is used to perform the arithmetic and logical operations defined by the instruction set The various binary arithmetic operations circuits decode the instruction in the instruction register and set up the ALU for the desired function Most binary arithmetic is based on the addition algorithm and subtraction is carried out as negative addition Multiplication is not performed as a discrete instruction but as a chain of addition and shift operations within the ALU under control of CPU control logic The multiply instruction MUL requires 11 internal processor c
222. essing Modes Machine Code and Cycles Freescale Semiconductor Inc Instruction Set Details M68HOC05 Instruction Set Return from Interrupt 0001 T CCR 0001 T ACCA 0001 TX 0001 T PCH 0001 T PCL Restore CCR from stack Restore ACCA from stack Restore X from stack Restore PCH from stack Restore PCL from stack RTI The condition codes accumulator the index register and the program counter are restored to the state previously saved on the stack The 1 bit will be reset if the corresponding bit stored on the stack is zero 2 1 1 1 1 Set or cleared according to the byte pulled from the stack Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles RTI INH 80 9 M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details For More Information On This Product Go to www freescale com 289 Freescale Semiconductor Inc Instruction Set Details RTS Return from Subroutine Operation SP SP SP SP 0001 T PCH 0001 T PCL Restore PCH from stack Restore PCL from stack RTS Description The stack pointer is incremented by one The contents of the byte of memory that is pointed to by the stack pointer is loaded into the high order byte of the program counter The stack pointer is again incremented by one The contents of the byte of memory at the address now contained
223. etails M68HOC05 Instruction Set Add one to the contents of ACCA X or M INC or X lt X 01 The N and Z bits in the CCR are set or cleared according to the results of this operation The C bit in the CCR is not affected therefore the only branch instructions that are useful following a INC instruction are BNE BPL and BMI 7 1 1 N R7 Set if MSB of result is set cleared otherwise 2 R7 e R6 e R5 R4 R3 R2 e R1 Set if result is 00 cleared otherwise Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles INCA INH A 4C 3 INCX INH X 5C 3 INC opr DIR 3C dd 5 INC X 7 5 INC opr X 6 ff 6 INX is recognized by the Assembler as being equivalent to INCX M68HCO05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details For More Information On This Product Go to www freescale com 275 Freescale Semiconductor Inc Instruction Set Details JMP Jump JMP Operation PC lt Effective Address Description A jump occurs to the instruction stored at the effective address The effective address is obtained according to the rules for EXTended DIRect or INDexed addressing Condition Codes and Boolean H 7 Formulae 1 1 1 None affected Source Forms Addressing Source Addressing Machine Code
224. f the H bit in the CCR and causes a branch if H is set This instruction is used in algorithms involving BCD numbers See BRA instruction for further details of the execution of the branch Condition Codes and Boolean H 7 1 None affected Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Operand s Cycles Code and Cycles BHCS rel REL 29 rr 3 The following table is a summary of all branch instructions Test Boolean Mnemonic Opcode Complementary Branch Comment r gt m C Z 0 BHI 22 BLS 23 Unsigned r m C 0 BHS BCC 24 rm BLO BCS 25 Unsigned r m Z 1 BEQ 27 26 Unsigned r lt m C Z 1 BLS 23 r gt m BHI 22 Unsigned r m 1 BLO BCS 25 r2m BHS BCC 24 Unsigned Carry C21 BCS 25 No Carry BCC 24 Simple r 0 Z 1 BEQ 27 r 0 BNE 26 Simple Negative N 1 BMI 2B Plus BPL 2A Simple Mask 1 BMS 2D Mask 0 BMC 2C Simple Half Carry H 1 5 29 No Half Carry BHCC 28 Simple IRQ Pin High 2F IRQ Low BIL 2E Simple Always 20 Never BRN 21 Unconditional r register ACCA or X memory operand M68HC05 Applications Guide Rev 4 0 248 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com Operation Description Condition Codes and Boolean Formulae Sour
225. f the result n 7 6 5 0 g CCR activity summary figure notation Bit not affected Bit forced to zero Bit forced to one Bit set or cleared according to results of operation Oe Il M68HC05 Applications Guide Rev 4 0 236 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Details M68HC05 Instruction Set Machine coding notation dd Low order 8 bits of a direct address 0000 00FF high byte assumed to be 0000 ee Upper 8 bits of 16 bit offset ff Lower 8 bits of 16 bit offset or 8 bit offset One byte of immediate data hh High order byte of 16 bit extended address Low order byte of 16 bit extended address rr Relative offset i Source form notation opr Operand one or two bytes depending on address mode rel Relative offset used in branch and bit manipulation instructions M68HC05 Instruction Set The following pages contain complete detailed information for all M68HCO5 instructions The instructions are arranged in alphabetical order with the instruction mnemonic set in larger type for easy reference M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details 237 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Details ADC Operation lt ACCA C
226. formation On This Product Go to www freescale com 27 28 Freescale Semiconductor Inc Review Questions Review Questions In the following instruction sequence a value is read into the accumulator From what address is this value being read It may be helpful to look at the machine code as well as the mnemonic instructions 0003 1400 0100 0100 ae 02 0102 6 O A 0000 O B 0002 0003 D 0102 SAM LARRY TOP EQU EQU ORG LDX LDA 03 SAM equal an 8 bit value 1400 LARRY equal a 16 bit value 100 Set program starting point 502 Initialize index register 0 X Read value into A In the following instruction sequence a value is read into the accumulator From what address is this value being read It may be helpful to look at the machine code as well as the mnemonic instructions 0003 1400 0100 0100 ae 02 0102 e6 03 O A 0002 O B 0003 O C 0005 O D 0105 SAM LARRY TOP EQU EQU ORG LDX LDA 03 SAM equal an 8 bit value 1400 LARRY equal a 16 bit value 100 Set program starting point 502 Initialize index register SAM X Read value into A M68HC05 Applications Guide Rev 4 0 MOTOROLA Review Questions 311 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions 29 30 31 In the following instruction sequence a value is read into the accumulator From what address
227. h our discussion of the CPU A high frequency clock source typically derived from a crystal connected to the MCU is used to control the sequencing of CPU instructions Typical MCUs divide the basic crystal frequency by two or more to arrive at a bus rate clock Each memory read or write takes one bus rate clock cycle In the case of the MC68HC705C8 MCU a 4 MHz M68HCO05 Applications Guide Rev 4 0 44 Microcontroller Operation MOTOROLA For More Information On This Product Go to www freescale com 2 6 Programming Freescale Semiconductor Inc Microcontroller Operation Programming maximum crystal oscillator clock is divided by two to arrive at a 2 MHz maximum internal processor clock Each substep of an instruction takes one cycle of this internal processor clock 500 ns Most instructions take two to five of these substeps thus the CPU is capable of executing about 500 000 instructions every second At this point we will write a short program in mnemonic form translate it into machine code and discuss how the CPU would execute the program This exercise will provide insight into the internal operation of the CPU and computers in general The instruction set explanations and the process of writing programs will be more understandable with this background Our program will read the state of a switch connected to an input pin When the switch is closed the program will cause an LED connected to an output pin to
228. he value of SP by crossing out the old value and writing the new value below it You would then read the value from the location now pointed to by the SP and put it wherever it belongs in the CPU e g in the upper or lower half of the PC Figure 2 13 shows how the worksheet will look after working through the whole JSR sequence Follow the numbers in square brackets as the process is explained During the process many values were written and later crossed out a line has been drawn from the square bracket to either the value or the crossed out mark to show which item the reference number applies to Beginning the sequence the PC should be pointing to 0100 1 and the SP should be pointing to 00FF 2 due to an earlier assumption The CPU reads and executes the LDA 02 instruction load accumulator with the immediate value 02 thus you write 02 in the accumulator column 3 and replace the PC value 4 with 0102 which is the address of the next instruction The load accumulator instruction affects the N and Z CCR bits Since the value loaded was 02 the Z bit would be cleared and the N bit would be cleared 5 This information can be found in Appendix A Since the other bits in the CCR are not affected by the LIDA instruction we have no way of knowing what they should be at this time so we put question marks in the unknown positions for now 5 M68HCO05 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operatio
229. he H bit in the CCR and causes a branch if H is clear This instruction is used in algorithms involving BCD numbers See BRA instruction for further details of the execution of the branch H 7 1 1 1 None affected Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles BHCC rel REL 28 rr 3 The following table is a summary of all branch instructions Test Boolean Mnemonic Opcode Complementary Branch Comment r gt m C Z 0 BHI 22 BLS 23 Unsigned 0 BHS BCC 24 rm BLO BCS 25 Unsigned r m Z 1 BEQ 27 26 Unsigned r lt m C Z 1 BLS 23 r gt m BHI 22 Unsigned rm 1 BLO BCS 25 BHS BCC 24 Unsigned Carry 1 BCS 25 No Carry BCC 24 Simple r 0 Z 1 BEQ 27 r 0 BNE 26 Simple Negative N 1 BMI 2B Plus BPL 2A Simple Mask 1 5 2D Mask 0 BMC 2C Simple Half Carry H 1 BHCS 29 No Half Carry BHCC 28 Simple IRQ Pin High BIH 2F IRQ Low BIL 2E Simple Always BRA 20 Never BRN 21 Unconditional r register ACCA or X m memory operand M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details 247 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Details BHCS Branch if Half Carry Set BHCS Operation PC lt PC 0002 Rel if 1 Description Tests the state o
230. he nomenclature listed below is used in the following definitions a Operators e lt Contents of Register Memory Location Shown inside Parentheses Is Loaded with read gets Is Pulled from Stack Is Pushed onto Stack Boolean AND Arithmetic Addition Except Where Used as Inclusive OR in Boolean Formula Boolean Exclusive OR Multiply Concatenate Negate Twos Complement M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details 235 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Details CPU Registers ACCA Accumulator CCR Condition Code Register X Index Register PC Program Counter PCH Program Counter Higher Order Most Significant 8 Bits PCL Program Counter Lower Order Least Significant 8 Bits SP Stack Pointer c Memory and Addressing M Amemory location or absolute data depending on addressing mode Rel Relative offset i e the twos complement number stored in the last byte of machine code corresponding to a branch instruction d Condition Code Register CCR bits Half Carry Bit 4 Interrupt Mask Bit 3 Negative Indicator Bit 2 Zero Indicator Bit 1 Carry Borrow Bit 0 2 LI Bit status BEFORE execution 7 6 5 0 of ACCA of X Bitn of M f Bit status AFTER execution Hn Bit o
231. herals The majority of all applications use one MCU device as the master This master initiates and controls the transfer of data to or from one or more slave peripheral devices that receive or supply the data being transferred Slaves can read data from or transfer data to the master only after the master instructs an action to occur This system configuration will be discussed in this applications guide M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 153 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data INTERNAL PROCESSOR MSB LSB 8 BIT SHIFT REGISTER DIVIDER 2 4 16 32 READ DATA BUFFER SPI CLOCK MASTER SELECT SPR1 MSTR SPE SPI CONTROL 5 2 5 5585 SPI STAUS REGISTER SPI CONTROL REGISTER SPIINTERRUPT INTERNAL REQUEST DATA BUS Figure 3 34 SPI Block Diagram M68HC05 Applications Guide Rev 4 0 154 68 705 8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Synchronous Serial Peripheral Interface SPI 3 12 1 Data Movement There is no need to specify the direction of data movement for each transfer because the master simultaneously transmits and receives serial data
232. hexadecimal values corresponding to 10 through 15 because each hexadecimal digit can represent 16 different quantities whereas our customary numbers only include the 10 unique symbols 0 through 9 Thus some other single digit symbols had to be used to represent the hexadecimal values for 10 through 15 M68HCO5 Applications Guide Rev 4 0 32 Microcontroller Operation MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation Number Systems Table 2 1 Decimal Binary and Hexadecimal Equivalents Base 10 Decimal Base 2 Binary Base 16 Hexadecimal 0 0000 0 1 0001 1 2 0010 2 3 0011 3 4 0100 4 5 0101 5 6 0110 6 7 0111 7 8 1000 8 9 1001 9 10 1010 1011 B 12 1100 13 1101 D 14 1110 E 15 1111 F 16 0001 0000 10 17 0001 0001 11 100 0110 0100 64 255 11111111 1024 0100 0000 0000 400 65 535 1111 1111 1111 1111 FFFF To avoid confusion about whether a number is decimal or hexadecimal hexadecimal numbers are preceded by the symbol For example 64 means decimal sixty four whereas 64 means hexadecimal six four which is equivalent to decimal 100 Some other computer manufacturers follow hexadecimal values with a capital H as in 64H Hexadecimal is a good way to express and discuss numeric information processed by computers because it is easy for people to mentally convert between hexadecimal d
233. hrough CMP 7 1 7 BLS OKENT Valid DAY entry TRIS CPX 5 Set HVAC Mode BNE TRI6 If not TSTA lt 0 BMI TRI6 illegal will ripple through CMP 3 0 3 BLS OKENT Valid HVACM entry TRI6 CPX 6 Set GOAL Temp BNE BADENT Illegal entry CMP 50 lt 50 F BLO BADENT illegal CMP 99 lt or 99 F BLS OKENT Valid goal temp BADENT LDA 5 negative value to set OKENT STA ENTRY Sets or clears N RTS Return from CHKPNT There is more to this exit than is obvious X MODE so X points at entry to be changed HR MIN AMPM DAY HVAC has entry or FF if it was illegal After return N bit of CCR indicates whether entry was OK or not STA ENTRY was used to make bit reflect sign of ENRTY rather than the result of a compare M68HC05 Applications Guide Rev 4 0 222 Applications For More Information On This Product Go to www freescale com MOTOROLA Listing Thermostat Example Freescale Semiconductor Inc Applications Thermostat Project Details Sheet 12 of 21 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK A2D sensors via SPI 145041 send addr 0 ignore return data send addr 1 return data is ch 0 val send addr 2 return data is ch 1 val Check t If TIC 0 Tf TIC 1 527 If TIC gt 2 To compensate skip A2D routine for sensor amp op amp offset A D result
234. ial Peripheral Interface SPI Interrupt 132 3 10 133 dodo PRSE RR CR UP RE 133 S002 err PETIT 136 3 11 Serial Communications Interface SCI 136 IS Lu oae bob edo dea 137 3 11 2 SCI Recevet 139 OILS REGSE ua us 141 3 11 3 1 Baud Rate Register BAUD 141 3 11 3 2 Serial Communications Control Register 6 1 144 3 11 33 Communications Control Register Two 5 2 144 3 11 3 4 Serial Communications Status Regisler SOSR 145 3 11 3 5 Serial Communications Data Register SCDAT 146 We FOUN tak 147 3 115 Hardware 148 3 11 6 Software 148 3 11 6 1 Initialization 148 3 11 6 2 Normal Transmit 149 3 11 6 3 Normal Receive 149 3 11 7 SCI Application 150 3 12 Synchronous Serial Peripheral Interface 153 3 121 Data M vement 155 3 12 2 Functional
235. ications Guide Rev 4 0 46 Microcontroller Operation MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation Programming FLOWCHART SET INITIAL CONDITIONS PORT C ALL OUTPUTS DATA PATTERN 1110 0000 TO PORT C YES DELAY TO DEBOUNCE TURN ON LED DELAY 1 SECOND TURN OFF LED YES NO DELAY TO DEBOUNCE Figure 2 5 Example Flowchart M68HCO05 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation 47 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation FLOWCHART MNEMONIC PROGRAM BEGIN SET INITIAL CONDITIONS INT A SUR PORT C ALL OUTPUTS LDA E0 DATA PATTERN 1110 0000 TO PORT C STA PORTC READ SWITCH TOP LDA PORTB NO BPL TOP YES DELAY TO DEBOUNCE JSR DLY50 TURN ON LED BCLR 6 PORTC LDA 20 DELAY 1 SECOND DLYLP JSR DLY50 DECA DLYLP TURN OFF LED BSET 6 PORTC gt YES OFFLP BRSET 7 PORTB OFFLP NO DELAY TO DEBOUNCE JSR DLY50 BRA TOP Figure 2 6 Flowchart and Mnemonics M68HC05 Applications Guide Rev 4 0 48 Microcontroller Operation MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation Programming 2 6 3 Software Delay Program Figure 2 7 shows
236. ies current user function 2d 0 Inactive display shows current time temp etc e 1 Set Time 2 Set Time MIN 3 Set Time 4 Set Time DAY 5 Set HVAC Mode Off Heat Cool Fan Only 6 Set Target Temperatur MODE reverts to O inactive if no keys for 1 min To activate modes press A until desired value x to be changed is blinking Next enter desired setting numbers and press enter Current program does not use B or C keys g CK CK Ck Ck Ck Ck C CC Ck Ck Ck CI C CC CC Ck C C CC CK CC Ck Ck CC Ck Ck C CSS Ck Ck Ck Ck Ck ko E A Kk ko Sk ko Ax kx User Interface to set time temp etc SEC Seconds 0 CHKEY If not skip ACTIMR ACTIMR Decrement activity timer ARMCLR No activity for 1 minute MODE Force to inactive CHKEY Did ACTIMR roll neg ACTIMR If so clear it KEYVAL Get key value 520 Ignore key if lt 520 or gt 7 XUSER2 Exit if lt 520 57 gt STF is invalid VALKEY Valid XUSER May be too far to branch valid key has been detected VALKEY NOFST DX 2H x lt zu HAQDAWHDWDATDATDANE 2 pop 2 pop D D 60 60 seconds ACTIMR Set to timeout in 1 min KEYVAL A NXTMOD Advance to next setting 0 ASCII 0 RYENT Branch if lt 0 9 ASCII 9 BRANCH IF gt 9 NTFLG First in entry OFST Skip if
237. if Z 0 Tests the state of the Z bit in the CCR and causes a branch if Z is clear Following a compare or subtract instruction BEQ will cause a branch if the arguments were not equal See BRA instruction for further details of the execution of the branch H 2 1 1 1 None affected Source Addressing Machine Code HCMOS BNE rel REL 26 rr 3 The following table is a summary of all branch instructions Test Boolean Mnemonic Opcode Complementary Branch Comment r gt m C Z 0 BHI 22 BLS 23 Unsigned 0 BHS BCC 24 rm BLO BCS 25 Unsigned r m Z 1 BEQ 27 26 Unsigned r lt m C Z 1 BLS 23 r gt m BHI 22 Unsigned rm C 1 BLO BCS 25 BHS BCC 24 Unsigned Carry C BCS 25 No Carry BCC 24 Simple r 0 2 1 27 r 0 BNE 26 Simple Negative N 1 BMI 2B Plus BPL 2A Simple Mask 1 5 2 Mask 0 BMC 2 Half Carry H 1 BHCS 29 No Half Carry BHCC 28 Simple IRQ Pin High BIH 2F IRQ Low BIL 2 Always BRA 20 Never BRN 21 Unconditional r register ACCA or X m memory operand M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details 259 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Details BPL Operation Description Condition Codes and Boolean Form
238. ific places in memory Refer to the memory map of the MCU to select an appropriate memory location where a program should start In this assembler listing the first two fields 1 and 2 are generated by the assembler and the last four fields 3 4 5 and 6 are the original source program written by the programmer Field 3 is a label TOP which can be referred to in other instructions In our example program the last instruction was BRA which simply means the CPU will continue execution with the instruction that is labeled When the programmer is writing a program the addresses where instructions will be located are not typically known Worse yet in branch instructions rather than using the address of a destination the CPU uses an offset difference between the current PC value and the destination address Fortunately the programmer does not have to worry about these problems because the assembler takes care of these details through a system of labels This system of labels is a convenient way for the programmer to identify specific points in the program without knowing their exact addresses the assembler can later convert these mnemonic labels into specific memory addresses and even calculate offsets for branch instructions so that the CPU can use them Field 4 is the instruction field The LDA mnemonic is short for load accumulator Since there are six variations different opcodes of the
239. igits and their 4 bit binary equivalent The hexadecimal notation is much more compact than binary while maintaining the binary connotations M68HC05 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation For More Information On This Product Go to www freescale com 33 Freescale Semiconductor Inc Microcontroller Operation 2 4 Computer Codes Computers must handle many kinds of information other than just numbers Text alphanumeric characters and instructions must be encoded in such a way that the computer can understand this information The most common code for text information is the American Standard Code for Information Interchange or ASCII The ASCII code establishes a widely accepted correlation between alphanumeric characters and specific binary values Using the ASCII code 41 corresponds to capital A 20 corresponds to a space character etc The ASCII code translates characters to 7 bit binary codes but in practice the information is most often conveyed as 8 bit characters with the most significant bit equal to zero This standard code allows equipment made by various manufacturers to communicate because all of the machines use this same code Computers use another code to give instructions to the CPU This code is called an operation code or opcode Each opcode instructs the CPU to execute a very specific sequence of steps that together accomplish an intended operation Computers from differe
240. illator inhibited When the RESET or IRQ input goes low the oscillator is enabled a delay of 1920 processor clock cycles is initiated allowing the oscillator to stabilize the interrupt request vector or reset vector is fetched and the service routine is executed depending on which signal was applied External interrupts are enabled following the STOP command H 2 1 1 1 0 0 Cleared Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles STOP INH 8E 2 M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details 295 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Details STX Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Store Index Register X in Memory STX M lt X Stores the contents of X in memory The contents of X remain unchanged 7 Set if MSB of result is set cleared otherwise Z X7 e X6 o X5 e X4 o e X2 o X1 XO Set if result is 00 cleared otherwise Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles STX opr DIR BF ji 4 STX opr EXT CF hh 5 STX X IX FF 4 STX opr X IX1 EF ff 5 STX opr X IX2 DF ee ff 6 M68HCO5 Applications Guide
241. in conjunction with an output compare function For example suppose an application requires an output signal to be activated a certain number of clock cycles after detecting an input event edge The input capture function would be used to record the time at which the edge occurred A number corresponding to the desired delay would be added to this captured value and stored in the output compare register Since both input captures and output compares are referenced to the same 16 bit counter the delay can be controlled to the resolution of the free running counter independent of software latencies An example of this use would be to fire a spark plug n microseconds after a timing pulse is sent from the engine flywheel 3 14 4 Input Capture Operation The input capture function includes a 16 bit latch input edge detection logic and interrupt generation logic The latch captures the current value of the free running counter when a selected edge is detected at the corresponding timer input pin The edge detection logic includes a control bit IEDG which enables the user s software to select the M68HC05 Applications Guide Rev 4 0 170 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Programmable Timer polarity of edge s that will be recognized The interrupt generation logic includes a status flag to indicate
242. in the stack pointer is loaded into the low order 8 bits of the program counter Condition Codes and Boolean 7 C Formulae 1 1 1 EN None affected Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode 5 Cycles Code and Cycles RTS INH 81 6 M68HCO5 Applications Guide Rev 4 0 290 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com SBC Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc ACCA lt M C Subtract with Carry Instruction Set Details M68HC05 Instruction Set SBC Subtracts the contents of M and the contents of C from the contents of ACCA and places the result in ACCA N R7 Set if MSB of result is set cleared otherwise 7 R7 R6 R5 R4 R3 eR2 R1 Set if result is 00 cleared otherwise 7 7 7 e 7 R7 A7 Set if absolute value of the contents of memory plus previous carry is larger than the absolute value of the accumulator cleared otherwise Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles SBC opr IMM A2 ii 2 SBC opr DIR B2 dd 3 SBC opr EXT C2 hh II 4 SBC X F2 3 SBC opr X 1
243. inal hexadecimal equivalent of the received character back to the terminal The program then waits for another character In practice the following would occur You type a number character on the keyboard It goes from the terminal to the MCU over the SCI receiver Use the example of the letter A The program translates to 4 1 then sends CR line feed 4 and 1 to the SCI transmitter When the transmission is complete the program goes back to the top for another keyboard number character to be sent over the SCI receiver Table 3 12 is a chart of the ASCII hexadecimal code conversion M68HC05 Applications Guide Rev 4 0 150 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Serial Communications Interface SCI Table 3 12 ASCII Hexadecimal Code Conversion ASCII Character Set 7 Bit Code 0 1 2 3 4 5 6 7 0 NUL DLE SP 0 P p 1 SOH DC1 1 2 STX DC2 2 B R b r 3 ETX DC3 3 5 5 4 DC4 4 D T d t 5 ENQ NAK 5 0 6 SYN amp 6 F V f V 7 BEL ETB 7 G W g 8 8 X h X 9 HT EM 9 Y i y A LF SUB J Z j 2 VT ESC K k C FF FS lt L V D CR GS M SO RS gt Y n F SI US 0 DEL M
244. ion On chip peripherals that can be configured and controlled by program instructions are also a new concept When residential electricity became common house plans required additional pages to document the location of switches and outlets The idea of how electricity went from one place to another was foreign to the architects of the day A new system of symbols and conventions had to be developed MCU based application projects are essentially the same as mechanical or discrete logic projects except for the addition of software programming Software programming is not entirely an added design task because the programmable nature of an MCU simplifies the hardware aspects of the project The normal order of events in MCU based projects is as follows 1 Proposal A marketing and or design group proposes preliminary requirements of a project to satisfy customer demand 2 Specification This step defines limits of operation but should not identify internal components preventing selection of the most cost effective solution to a problem 3 Breadboarding This procedure is primarily a hardware activity although some software is normally required to verify the accuracy of the hardware design 4 Software Development This step involves planning and implementation of software programs The programmer must know how the system is electrically interfaced to components outside the MCU because software programs control the operatio
245. iptions of typical CPU instructions are intended to make you think like a CPU We can then go through the example program using a teaching technique called playing computer in which you pretend you are the CPU interpreting and executing the instructions in a program 2 7 1 Detailed Operation of CPU Instructions Before seeing how the CPU would execute the example program it would help to know in detail how the CPU breaks down instructions into fundamental operations and performs these tiny steps to accomplish a desired instruction As we will see many small steps execute very quickly and very accurately within each instruction but none of the small steps is very complicated M68HCO05 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation 55 For More Information On This Product Go to www freescale com 50000 001F 0020 004F 0050 009F 00A0 00 0100 1EFF 1F00 1FF3 1FF4 1FFF Freescale Semiconductor Inc Microcontroller Operation 10 32 5 A6 00A0 MOTOROLA USE 48 BYTES RAM EXAMPLE PROGRAM USER PROM 7680 BYTES MOTOROLA USE 144 BYTES USER PROM VECTORS 12 BYTES 81 00D0 Figure 2 10 Memory Map of Example Program The logic circuitry inside the CPU would see
246. irst instruction loads A with the immediate value 80 which is negative The second instruction will not branch because the N condition code flag is set The CPU then increments A to 81 then decrements to 80 and finally decrements A again to 7F 13 After executing the following instruction sequence from START to END what value will be in memory location 00FF 0100 9 START RSP Reset SP to SOOFF 0101 02 00 JSR SUB Call SUB 0104 cd 02 00 JSR SUB Call SUB again 0107 9d END NOP Done 0200 81 SUB RTS Just Return O A 00 O B 01 O C 04 gt D 07 See 2 7 2 Playing Computer see also 2 4 4 Memory Uses In the course of executing this program segment the CPU would call a subroutine and store the return address at 00FF and 00FE then return from the subroutine which causes the return address to be recovered from the stack and the stack pointer to end up pointing at 00FF again When the second subroutine call is executed the return address now 0107 is saved on the stack at 00FF and 00FE with the 07 at 00FF The second return from subroutine causes this return address to be read from the stack Since no other value is stored to location 00FF during this program 07 will still be there at the end of the sequence M68HC05 Applications Guide Rev 4 0 322 Review Questions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
247. is programmable by software accessible registers Each 8 bit port has an associated 8 bit data direction register DDR as shown in Figure 3 16 Figure 3 17 and Figure 3 18 M68HCO05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 133 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data BIT7 BIT 0 ona oon one oon oon 0 i 0 0 0 i PORT OUTPUT REGISTER STATES NOT CHANGED BY RESET PAT PA6 5 4 1 PAO 04 DDRA RESET CONDITION ALL INPUTS 00 PORTA RESET CONDITION PIN NAMES REF Figure 3 16 Port A and Data Direction A Registers BIT7 BIT 0 oos coss on one oorr 0 0 0 0 0 PORT OUTPUT REGISTER STATES NOT CHANGED BY RESET PB7 PB6 5 4 PB2 0 505 DDRB RESET CONDITION ALL INPUTS 501 PORTB RESET CONDITION PIN NAMES REF Figure 3 17 Port B and Data Direction B Registers BIT 7 BIT 0 ower oon sores Sors oor 0 0 PORT OUTPUT REGISTER STATES CHANGED BY RESET PC6 PC5 PC4 PC3 PC2
248. ister unless the read sequence is intended to clear the timer overflow flag If a read of the free running counter register first addresses the most significant byte 18 it causes the least significant byte 19 to be transferred to a buffer This buffer value remains fixed after the first most significant byte read even if the user reads the most significant byte several times This buffer is accessed when reading the free running counter register least significant byte 19 thus completing a read sequence of the total 16 bit counter value The same read sequence applies to the counter alternate register A read sequence containing only a read of the least significant byte of the free running counter 19 will receive the count value at the time of the read In reading either the free running counter or counter alternate register if the most significant byte is read the least significant byte must also be read to complete the sequence 3 14 3 Input Capture Concept The input capture function is a fundamental element of the MC68HC705C8 timer architecture Input capture functions are used to record the time at which some external event occurred This is accomplished by latching the contents of the free running counter when a selected edge is detected at the related timer input pin edge input TCAP pin The time at which the event occurred is saved in the input capture register 16 bit latch Although it may take an undetermined varia
249. isters Three registers in the SPI provide control status and data storage functions These registers include the serial peripheral control register location 0A serial peripheral status register location 0 and serial peripheral data register location 0C 3 12 4 1 Serial Peripheral Control Register SPCR In most systems this register Figure 3 37 is written only once shortly after reset to initialize the SPI system BIT7 6 5 4 3 2 1 BIT 0 see comm son src 0 0 0 0 0 0 0 RESET CONDITION CLOCK PHASE BASIC PROTOCOL CLOCK POLARITY MASTER 1 OR SLAVE 0 MODE SELECT SPISYSTEM ENABLE INTERRUPT ENABLE SPI MASTER BIT RATE Figure 3 37 Serial Peripheral Control Register The SPCR bits have the following functions SPIE 0 SPI interrupts are disabled the most common configuration 1 SPI interrupt requests are enabled if SPIF and or MODF is set to one M68HCO5 Applications Guide Rev 4 0 158 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Synchronous Serial Peripheral Interface SPI SPE 0 SPI system is turned off 1 SPI system is turned on MSTR 0 SPI is configured as a slave 1 SPI is configured as a master CPOL 0 Active high clocks selected SCK idles low
250. it N 7 1 1 1 1 7 Set if MSB of result is set cleared otherwise 7 7 5 4 2 RO Set if result is 00 cleared otherwise C 1 Set Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles COMA INH A 43 3 COMX INH X 53 3 COM opr DIR 33 dd 5 COM X IX 73 5 COM opr X 63 ff 6 M68HCO5 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details For More Information On This Product Go to www freescale com 271 Freescale Semiconductor Inc Instruction Set Details CPX Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Compare Index Register with Memory X Compares the contents of the index register with the contents of memory and sets the condition codes which may be used for arithmetic and logical branching The contents of both ACCA and M are unchanged 7 Set if MSB of result is set cleared otherwise Z 7 2 1 Set if result is 00 cleared otherwise IX7 M7 M7eR7 R7e 1X7 Set if the absolute value of the contents of memory is larger than the absolute value of the index register cleared otherwise Source Addressing Machine Code HCMOS Forms Mode Opcod
251. it board design complete until there is a schematic diagram parts list and assembly drawing you should not consider a program complete until there is a commented listing and a comprehensive explanation of the program such as a flowchart 2 6 2 Mnemonic Source Code Once the flowchart or plan is completed the programmer develops a series of assembly language instructions to accomplish the functions called for in each block of the plan The programmer is limited to selecting instructions from the instruction set for the CPU being used in this case the 8 5 The programmer writes instructions in a mnemonic form which is easy to understand Figure 2 6 shows the mnemonic source code next to the flowchart of our example program so you can see what CPU instructions are used to accomplish each block of the flowchart The meanings of the mnemonics used in the right side of Figure 2 6 can be found in Appendix A Instruction Set Details During development of the program instructions it was noticed that a time delay was needed in three places A subroutine was developed that would generate a 50 ms delay This subroutine was used directly in two places for switch debouncing and made the one second delay easier to produce To keep this figure simple the comments that would usually be included within the source program for documentation are omitted The comments will be shown in the complete assembly listing in Figure 2 9 M68HCO05 Appl
252. ith the components of your application Also the PGMR board can be used with other members of the M68HC05 Family to increase your development choices In addition to the MC68HC705C8 8K EPROM device the PGMR can also operate with the MC68HC805C4 4K EEPROM device Each of these devices supports a slightly different approach to development With the EPROM approach MC68HC705C8 you would write a software program transfer this program into the EPROM in the MCU and reset the MCU to execute the program When you discover a mistake or want to make a change you remove the MCU from the PGMR board and erase the EPROM with an ultraviolet UV light source After the MCU is erased you can program the modified program into it and continue debugging finding errors After a program is developed with a windowed EPROM you can program the working software program into any of several OTP MCUs for use in your finished products The OTP MCU is identical to the windowed device used for development except that it is packaged in a less expensive plastic package Since this plastic package is opaque you cannot erase the on chip EPROM after it has been programmed MC68HC805C4 has 4 Kbytes of electrically erasable PROM EEPROM which allows easier erasure of programs during development EEPROM does not have to be erased with UV light In most other respects this MCU is the same as the MC68HC705C8 OTPROM MCU Thus programs can be developed with the MC
253. itten and which is not changed during program execution These are two byte instructions one for the opcode and one for the immediate data byte Example Program Listing 0200 02 LDA 502 Load accumulator w immediate value Execution Sequence 0200 5 6 1 0201 02 2 Explanation 1 CPU reads opcode A6 load accumulator with the value immediately following the opcode 2 CPU then reads the immediate data 02 from location 0201 and loads 02 into the accumulator The following is a list of all M68HCO5 instructions that can use the immediate addressing mode Instruction Mnemonic Add with Carry ADC Add ADD Logical AND AND Bit Test Memory with Accumulator BIT Compare Accumulator with Memory CMP Compare Index Register with Memory CPX Exclusive OR Memory with Accumulator EOR Load Accumulator from Memory LIDA Load Index Register from Memory LDX Inclusive OR ORA Subtract with Carry SBC Subtract SUB M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 103 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data 3 7 3 Extended Addressing Mode In the extended addressing mode the address of the operand is contained in the two bytes following the opcode Extended addressing references any location in the MCU memory space including I O RAM ROM and EPROM Extended addressing mode instructions are three bytes one f
254. k Ck Ck Ck CK Sk Ck Ck Sk Sk Sk Pk Sk Sk Pk Mk kx ko kx 0157 Od 13 fd MAIN BRCLR 6 TSR MAIN Loop here till OCF flag set 015a b6 17 LDA OCMP 1 Low byte of OC register 015 ab d4 ADD 5 4 Low half of 12500 015 b7 STA TEMPA Save till high half calculated 0160 b6 16 LDA OCMP High byte of OC register 0162 a9 30 ADC 530 High half of 12500 carry 0164 b7 16 STA OCMP Update OC reg 0166 b6 a0 LDA TEMPA Get low half of updated value 0168 b7 17 STA OCMP 1 Update low half of OC reg OC now old OC 12500 and OCF flag is clear 016 6 a2 LDA TIC Get current TIC value 016 4c INCA TIC TIC 1 016d b7 a2 STA TIC Update TIC 016 al 14 20 20th TIC 0171 25 02 BLO ARNCI If not skip next clear 0173 a2 CLR TIC Clear TIC on 20th End of synchronization to 50mS TIC Run main tasks and branch back to main within 50mS Sync OK as long as no 2 consecutive passes take more than 100mS 0175 01 8c ARNC1 JSR TIME Update time of day amp day of week 0178 cd 01 c9 JSR KYPAD Check service keypad 017b cd 02 16 JSR BEEP Update Beeper 017e cd 02 2f JSR USER User Interface to set time temp etc 0181 cd 03 09 JSR A2D Check Temp Sensors 0184 cd 03 34 JSR HVAC Update Heat Air Cond Outputs 0187 cd 03 9d JSR LCD Update LCD display 018a 20 cb BRA MAIN Back to Top amp wait for next TIC END of Main Loop KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK M68HCO5 Applications Guide Rev 4 0 216 Applications MOTOROLA
255. l This method is explained in Section 4 Applications Both methods described for programming the on chip EPROM OTPROM ultimately use a software program running in the MCU that is being programmed The programming software uses the program register PROG to control the EPROM programming process 3 16 3 Program Register The program register see Figure 3 51 is used for PROM programming BIT 7 6 5 4 3 2 1 BITO o o o o o fu 0 sc pros 0 0 0 0 0 0 0 0 RESET CONDITION PROGRAMMING POWER 0 1 ON LATCH CONTROL Figure 3 51 Program Register LAT Prior to a PROM write operation set the latch LAT bit This enables the PROM data and address buses to be latched for programming a PROM location Reset clears the LAT bit When the LAT bit is cleared PROM data and address buses are unlatched for normal CPU operations This bit which is both readable and writable must be cleared to allow PROM read operations PGM When the program PGM bit is set Vpp power is applied to the PROM for programming mode of operation Reset clears the PGM bit This bit which is readable is only writable when the LAT bit is set If the LAT bit is cleared the PGM bit cannot be set M68HCO05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 183 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8 705 8 Functional Data
256. lay a 4x4 x m keypad a piezo beeper and an MC145041 x 5 serial A D converter Software is configured in a real time loop and demonstrates timing techniques 5 and program modularity principles The project is complete enough to show the development process but is not intended to finished product Ck CK Ck C CK C Ck CK CC C CK Ck Ck CK Ck C CK Ck Ck CK Ck Ck CK Ck Ck CC Ck CK CC Ck Ck Ck Sk Sk P Sk kx o Register Equates 0000 PORTA EQU 00 LCD display data 0001 PORTB EQU 01 Keypad Row4 3 2 1 Coll 2 3 4 0002 PORTC EQU 02 Fan Heat Cool Beep ADen E RS R W 0003 PORTD EQU 03 in SS SCK MOSI MISO TxD RxD 0004 DDRA EQU 504 Data direction Port A all output 0005 DDRB EQU 05 Data direction Port 7 4in 3 0out 0006 DDRC EQU 06 Data direction Port C all output 000a SPCR EQU 0A SPIE SPE MSTR CPOL CPHA SPR1 SPRO 0005 SPSR EQU SOB SPIF WCOL MODF 000c SPDR EQU SOC SPI Data 000d BAUD EQU SOD SCP 1 SCP0 SCRZ SCR1 SCRO 000e SCCR1 EQU SOE R8 T8 M WAKE 0005 SCCR2 EQU SOF TIE TCIE RIE TE SBK 0010 SCSR EQU 10 TDRE IDLE OR NF FE 0011 SCDR EQU SII SCI Data 0011 RDR EQU 514 SCI Receive Data same as SCDR 0011 TDR EQU 11 SCI Transmit Data same as SCDR 0012 TCR EQU 12 ICIE OCIE TOIE 0 0 0 IEGE OLVL 0013 TSR EQU 13 ICF OCF TOF 0 0 0 0 0 0014 ICAP EQU 14 Input Capture Reg Hi 14 Lo 1
257. le Negative N 1 BMI 2B Plus BPL 2A Simple Mask 1 5 2 Mask 0 BMC 2C Simple Half Carry H 1 BHCS 29 No Half Carry BHCC 28 Simple IRQ Pin High BIH 2F IRQ Low BIL 2E Simple Always BRA 20 Never BRN 21 Unconditional r register ACCA or X memory operand M68HC05 Applications Guide Rev 4 0 250 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc Instruction Set Details M68HC05 Instruction Set Branch if Interrupt Pin is High BIH lt 0002 Rel if IRQ 1 Tests the state of the external interrupt pin and causes a branch if the pin is high See BRA instruction for further details of the execution of the branch H 7 1 1 1 None affected Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles BIH rel REL 2F rr 3 The following table is a summary of all branch instructions Test Boolean Mnemonic Opcode Complementary Branch Comment r gt m C Z 0 BHI 22 BLS 23 Unsigned 0 BHS BCC 24 rm BLO BCS 25 Unsigned r m Z 1 BEQ 27 26 Unsigned r lt m C Z 1 BLS 23 r gt m BHI 22 Unsigned rm C 1 BLO BCS 25
258. le Semiconductor Inc Review Questions Review Questions Answers and Explanations 30 After executing the following instruction sequence from START to END what value will be in the stack pointer SP 0100 9 START RSP Reset SP to SOOFF 0101 cd 02 00 JSR SUB Call SUB 0104 cd 02 00 JSR SUB Call SUB again 0107 9d END NOP Done 0200 81 SUB RTS Just Return O A 0200 O B 00FB O C 00FD gt D 00FF This is a variation of the exercise in 2 7 1 4 Subroutine Calls and Returns and Figure 2 11 Subroutine Call Sequence During execution the stack pointer will have the values FF FE FD FE FF FE FD FE FF 31 microcontroller is O A the CPU part of a digital binary computer B the same thing as a microprocessor O C any system that includes an MCU integrated circuit gt D a computer system including CPU memory and peripherals on a single I C See Section 2 Microcontroller Operation and 1 3 Definitions M68HC05 Applications Guide Rev 4 0 MOTOROLA Review Questions 329 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions 32 After executing the following instruction sequence from TOP to BOT what values will be in locations 00A0 and 00A1 respectively 0100 0102 0104 0106 0108 010 010 010 0110 b7 b7 38 39 38 39 9d 3 0 81 1 1 0 1 0 LDA
259. le com Freescale Semiconductor Inc List of Tables M68HC05 Applications Guide Rev 4 0 20 List of Tables MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Guide M68HC05 1 1 Contents 1 2 Introduction Section 1 General Description 12 Win 242 daba 21 DEMO uoo no dad Rd 22 Ve en C 23 15 Computer Systems Description 24 1 6 Microcontroller Applications Overview 26 Project DOSCHDION o caw deen Ee ein satine tiaia Qd ERES 27 Welcome to the world of microcontrollers In this applications guide we will develop a project using a Motorola MC68HC705C8 microcontroller unit MCU in a familiar application home thermostat The MC68HC705C8 is a member of the M68HC05 Family of MCUs The project will demonstrate only a few of the many possible microcontroller functions that you can use This guide assumes that you have no knowledge of microcontrollers and no MCU applications experience Section 1 General Description begins with definitions gives background information and describes computer systems An overview of microcontroller applications is also presented and an application project is discussed Section 2 Microcontroller Operation describes in detail how microcontrollers operate M6
260. load accumulator instruction additional information is required before the assembler can choose the correct binary opcode for the CPU to use during execution of the program Field 5 is the operand field providing information about the specific memory location or value to be operated on by the instruction The assembler uses both the instruction mnemonic and the operand specified in the source program to determine the specific opcode for the instruction The different ways of specifying the value to be operated on are called addressing modes a more complete discussion of addressing modes is M68HCO05 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation 53 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation presented later The syntax of the operand field is slightly different for each addressing mode so the assembler can determine the correct intended addressing mode from the syntax of the operand In this case the operand 5 is PORTB which the assembler automatically converts to 01 recall the EQU directive The assembler interprets 01 as a direct addressing mode address between 0000 and 00FF thus selecting the opcode 136 which is the direct addressing mode variation of the LIDA instruction If PCRTB had been preceded by a symbol that syntax would have been interpreted by the assembler as an immediate addressing mode value and the op
261. lock in the Clock Divided By column is the internal processor clock M68HC05 Applications Guide Rev 4 0 142 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Serial Communications Interface SCI The SCP1 SCP O bits in the baud rate register set the division factor N in Figure 3 24 for the baud rate divider Reset clears these bits setting the prescaler to divide by one The SCR2 SCR1 and SCRO bits are used to set the division factor M in Figure 3 24 for the baud rate divider Reset does not affect these bits Example From Table 3 11 find the crystal frequency used in this case 4 MHz Next find 9600 or a binary multiple of 9600 In this example you would select the bottom row which corresponds to SCP1 SCP0 1 1 divide by thirteen Next find the column in Table 3 11 that corresponds to 9600 Hz Find the desired baud rate in this column In this example you would select the top row which corresponds to SCR2 SCR1 SCRO 0 0 0 divide by one NOTE Table 3 11 illustrates how the SCI select bits can be used to provide lower transmitter baud rate by further dividing the prescaler output frequency The five examples are only representative samples In all cases the baud rates shown are transmit baud rates transmit clock and the
262. m also called the source version of the program and produces a machine code version of the program in a form that can be programmed into the memory of the MCU The assembler also produces a composite listing showing both the original source program mnemonics and the object code translation This listing is used during the debug phase of a project and as part of the documentation for the software program Figure 2 9 shows the listing which results from assembling the example program Comments were added before the program was assembled M68HC05 Applications Guide Rev 4 0 50 Microcontroller Operation MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation Programming Section 4 Applications should be thoroughly studied before attempting to run any of the sample programs in this guide Some of the sample programs were developed on another member of the M68HC05 Family which has a slightly different memory map than the MC68HC705C8 Minor modifications may be necessary to successfully run these programs on the MC68HC705C8 Refer to Figure 2 8 for the following discussion This figure shows some lines of the listing with reference numbers indicating the various parts of the line The first line is an example of an assembler directive line This line is not really part of the program rather it provides information to the assembler so that the real program ca
263. m straightforward to a design engineer accustomed to working with TTL logic or even relay logic What sets the MCU and its CPU apart from these other forms of digital logic is the packing density Very large scale integration VLSI techniques have made it possible to fit the equivalent of thousands of TTL integrated circuits on a single silicon die By arranging these logic gates to form a CPU you get a general purpose instruction executer M68HC05 Applications Guide Rev 4 0 56 Microcontroller Operation MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation CPU Operation capable of acting as a universal logic element By placing different combinations of instructions in the device it can perform virtually any definable function A typical instruction takes two to five cycles of the internal processor clock Although it is not normally important to know exactly what happens during each of these execution cycles it can help to go through a few instructions in detail to understand how the CPU works internally 2 7 1 1 Store Accumulator Direct Addressing Mode Look up the STA instruction in Appendix A Instruction Set Details In the table at the bottom of the page we see that B7 is the direct addressing mode version of the store accumulator instruction We also see that the instruction requires two bytes one to specify the opcode B7 an
264. mation On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation In this example the CPU appends the assumed value 00 because of direct addressing mode to the 02 that was read during the second cycle of the instruction to arrive at the complete address 0002 During the fourth cycle of this instruction the CPU places this constructed address 0002 on the internal address bus places the accumulator value on the internal data bus and asserts the write signal That is the CPU writes the contents of the accumulator to 0002 during the fourth cycle of the STA instruction This explanation left out certain details such as setting the condition code flags but it gives an idea of what occurs within the CPU during the execution of a single instruction 2 7 1 2 Load Accumulator Immediate Addressing Mode Next look up the LDA instruction in Appendix A Instruction Set Details The immediate addressing mode version of this instruction appears as A6 ii in the machine code column of the table at the bottom of the page This version of the instruction takes two internal processor clock cycles to execute The A6 opcode tells the CPU to get the byte of data that immediately follows the opcode and put this value in the accumulator During the first cycle of this instruction the CPU reads the opcode A6 and advances the PC to point to the next location in memory the address of the immediate op
265. may be reprogrammed with new instructions and data An OTPROM is atype of EPROM that is manufactured in an inexpensive plastic package Since the plastic package is opaque to ultraviolet light an OTPROM can be programmed only once Like ROM PROM EPROM and OTPROM are nonvolatile types of memory The program contains instructions and data The computer system uses the program to perform some desired processes The computer clock is used for timing and sequencing the various operations A crystal is usually used to provide the reference frequency for the clock M68HC05 Applications Guide Rev 4 0 MOTOROLA General Description 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description 1 6 Microcontroller Applications Overview The development of a new microcontroller application is limited only by skill and imagination since the elements of a microcontroller system are easily assembled MCU applications generally allow many new functions that make process control simpler and more powerful often at reduced cost Many applications require analog inputs and outputs The resulting system is the equivalent of a traditional analog controller with a number of control loops Control loops regulate an output as a function of one or more inputs Control loops are illustrated in the flowchart of Figure 1 2 START lt CONTROL LOOP TEMP TOO COLD
266. memory where the CPU will load read or store write information Sometimes an index register is called a pointer register We will learn more about index registers when we discuss indexed addressing modes M68HC05 Applications Guide Rev 4 0 38 Microcontroller Operation MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation Computer Codes 0 0 10 PROGRAM COUNTER PC 7 4 372 1 0 CONDITION CODE REGISTER 111 1 N Z CC CARRY ZERO NEGATIVE INTERRUPT MASK HALF CARRY FROM BIT 3 Figure 2 2 M68HC05 CPU Registers The program counter PC register is used by the CPU to keep track of the address of the next instruction to be executed When the CPU is reset starts up the PC is loaded from a specific pair of memory locations called the reset vector The reset vector locations contain the address of the first instruction to be executed by the CPU As instructions are executed logic in the CPU increments the PC such that it always points to the next piece of information that the CPU will need The number of bits in the PC exactly matches the number of wires in the address bus This determines the total potentially available memory space that can be accessed by a CPU In the case of an MC68HC705C8 the PC is 13 bits long therefore its CPU can access up to 8 Kbytes
267. mented version of BEEPM Beeper should be on unless BEEPM is between 3 and 6 0220 al 03 CMP 3 0222 25 08 BLO BPRON If lt 3 turn beeper on 0224 al 06 CMP 6 0226 22 04 BHI BPRON gt 6 turn beeper on 0228 19 02 BCLR 4 PORTC Turn beeper off 022 20 02 amp Exit 022 18 02 BSET 4 PORTC Turn beeper on 022 81 RTS RETURN from BEEP M68HCO5 Applications Guide Rev 4 0 MOTOROLA Applications 219 For More Information On This Product Go to www freescale com 0226 0226 0231 0233 0235 0237 0239 0235 0234 0236 0241 0243 0245 0247 024 024 024 0250 0252 0254 0256 0258 025 025 025 0260 0262 0264 0265 0266 0267 M68HC05 Applications Guide Rev 4 0 26 26 2 b6 al 25 al 23 CC ae bf al 27 al 25 al 22 26 48 48 48 48 a3 Oa b5 02 bl 02 b5 b3 20 04 03 02 41 52 30 33 39 2f b6 06 a5 a4 b6 Freescale Semiconductor Inc Applications Listing Thermostat Example Sheet 9 of 21 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK USER ARMCLR CHKEY baXUSER2 z uio s D USER User Interface to set time temp etc Variable named MODE identif
268. mmable Timer INTERNAL PROCESSOR CLOCK XTAL 2 FIXED DIVIDE BY 4 TIMER CONTROL REGISTER TIMER STATUS REGISTER TIMER INTERRUPT REQUEST INTERNAL DATA BUS Figure 3 43 Programmable Timer Block Diagram M68HCO05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 167 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data NOTE READ COUNTER HIGH BYTE READ COUNTER LOW BYTE LSB LATCH INTERNAL DATA BUS 1 LSB latch is normally transparent becomes latched when high byte of counter is read and becomes transparent again when low byte of counter is read Figure 3 44 16 Bit Counter Reads Generally accessing the low byte of a specific timer function allows full control of that function however an access of the high byte inhibits that specific timer function until the low byte is also accessed A read from the MSB causes the LSB to be latched at the next sequential address Set the I bit in the condition code register while manipulating both the high and low byte register of a specific timer function This prevents interrupts from occurring between the time that the high and low bytes are accessed A description of each register and the external pins is given in the following paragraphs 3 1
269. mode On chip oscillator 40 pin dual in line package 44 lead PLCC plastic leaded chip carrier package M68HCO05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 77 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8 705 8 Functional Data 3 3 2 Software Features Upward software compatible with the M146805 CMOS family e Efficient instruction set Versatile interrupt handling True bit manipulation Addressing modes with indexed addressing for tables e Memory mapped I O Two power saving standby modes 3 3 3 General Description Figure 3 1 shows the MC68HC705C8 MCU block diagram The central processor unit CPU contains the 8 bit arithmetic logic unit accumulator index register condition code register stack pointer program counter and CPU control logic Major peripheral functions are provided on chip On chip memory systems include bootstrap read only memory ROM programmable ROM EPROM or OTPROM and random access memory RAM On chip 1 0 devices include an asynchronous serial communications interface SCI a separate serial peripheral interface SPI and a 16 bit programmable timer system Self monitoring circuitry is included on chip to protect against system errors A computer operating properly COP watchdog system protects against software failures A clock monitor system generates a system reset if the clock i
270. mory with Accumulator Clear Compare Accumulator with Memory Complement Compare Index Register with Memory Decrement Exclusive OR Memory with Accumulator Increment Jump Jump to Subroutine Load Accumulator from Memory Load Index Register from Memory Logical Shift Left Logical Shift Right Negate Inclusive OR Rotate Left thru Carry Rotate Right thru Carry Subtract with Carry Store Accumulator in Memory Store Index Register in Memory Subtract Test for Negative or Zero The following is a list of all M68HCO5 instructions that can use the indexed no offset addressing mode Mnemonic ADC ADD AND ASL ASR BIT CLR CMP COM CPX DEC EOR INC JMP JSR LDA LDX LSL LSR NEG ORA ROL ROR SBC STA STX SUB TST M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data For More Information On This Product Go to www freescale com 109 Freescale Semiconductor Inc MC68HC705C8 Functional Data 3 7 5 2 Indexed 8 Bit Offset In the indexed 8 bit offset addressing mode the effective address is obtained by adding the contents of the byte following the opcode to the contents of the index register This mode of addressing is useful for selecting the kth element element table To use this mode the table must begin in the lowest 256 memory locations and may extend through the first 511 memory locations IFE is the last location which the instruction may access Indexed 8 bit offse
271. mostat Project 5 196 4 5 1 Hardware 197 4 5 2 Project 200 This section discusses the development of an application home thermostat project based on a microcontroller A typical MCU application involves hardware development software development and mechanical development Though separate to some degree all elements must work together as a system thus everyone working on the project should be somewhat familiar with the requirements of each element The principles of systematic project management including planning review prototyping and testing still apply Although genius and unusual creativity are assets to a microcontroller designer they not a requirement The majority of MCU applications result from simple systematic development Due to the nature of MCUs applications based on an MCU often include noteworthy features that cannot be found on similar products which do not use an MCU In this applications guide we assume some knowledge of the traditional mechanical and electrical aspects of a project What is new is the M68HCO05 Applications Guide Rev 4 0 MOTOROLA Applications 187 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications software program that allows the MCU to perform the desired functions of the applicat
272. mpletes current instruction the interrupt latch is tested If the interrupt latch contains a logic one and the interrupt mask bit I bit in the condition code register is clear the MCU then begins the interrupt sequence If the option is selected to include level sensitive triggering then the IRQ input requires an external resistor to Vpp for wired OR operation See 3 9 Interrupts for more detail concerning interrupts The RESET pin is an active low bidirectional control signal As an input the RESET pin initializes the MCU to a known startup state As an open drain output the RESET pin indicates an internal MCU failure detected by the computer operating properly COP watchdog timer or clock monitor circuitry This RESET pin is significantly different from the RESET signal used on other Motorola M68HCO05 Family devices Refer to 3 6 4 Resets and 3 9 Interrupts before designing circuitry to generate or monitor the RESET signal The TCAP pin provides the input to the input capture feature for the on chip programmable timer system Refer to input capture register in 3 14 Programmable Timer M68HCO05 Applications Guide Rev 4 0 82 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Pins and Connections 3 4 1 6 provides an output for the output compare feature of the
273. my stuff amp turns off red LED 0258 3f 9e CLR SPIVAL Start with 0 025a a6 50 LDA 34501010000 SPE MSTR norm lo fast clk 025c b7 0a STA SPCR Initialize SPI control reg 025e b6 01 TOP LDA PORTB Read sw at MSB of Port B 0260 2a fc BPL TOP Loop till MSB 1 Neg trick 0262 cd 02 86 JSR DLY50 Delay about 50 mS to debounce 0265 17 02 BCLR 3 PORTC Drive select of 74HC595 low 0267 b6 9e LDA SPIVAL Current data to send to SPI 0269 7 Oc STA SPDR Send SPI data 026b 3c 9e INC SPIVAL Add one to current SPI value 026d 0f Ob fd HERE BRCLR 7 SPSR HERE Wait for SPIF to set 0270 16 02 BSET 3 PORTC Drive select of 74HC595 hi 0272 1d 02 BCLR 6 PORTC Turn on LED bit 6 to zero 0274 a6 14 LDA 120 Decimal 20 assembles to 14 0276 cd 02 86 DLYLP JSR DLY50 Delay 50 mS 0279 4a DECA Loop counter for 20 loops 027a 26 fa BNE DLYLP 20 times 20 19 19 18 1 0 027o I1 02 BSET 6 PORTC Turn LED back off 027e 01 fd OFFLP BRSET 7 PORTB OFFLP Loop here till sw off 0281 cd 02 86 JSR DLY50 Debounce releas 0284 20 BRA TOP Look for next sw closure Figure 3 42 SPI Application Example Program M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 165 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8 705 8 Functional Data The input capture function can be used to automatically record latch the time when a selected transition was detected The output compare function can be used
274. n 65 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation STACK POINTER PT Sogrr 7 9 00F 0 18 00FE 119 00FF 0002 PORTC 00 21 00 00F D 00 01 l 00 05 6 ACCUMULATOR Boe CONDITION INDEX CODES REGISTER 111HINZC 00 1112727017 PROGRAM COUNTER 117 59100141 501010 502061121 0204 131 50200116 0206 171 9020320 0105 LOAD AN IMMEDIATE VALUE GO DO A SUBROUTINE STORE ACCUMULATOR TO PORT DECREMENT ACCUMULATOR LOOP TILL ACCUMULATOR 0 RETURN FROM SUBROUTINE Figure 2 13 Completed Worksheet Next the CPU reads the JSR SUBBY instruction Temporarily remember the value 0105 which is the address where the CPU should come back to after executing the called subroutine The CPU saves the low order half of the return address on the stack thus you write 05 6 at the location pointed to by the SP 00 and decrement the SP 7 to 00FE The CPU then saves the high order half of the return address on the stack you write 01 8 to 00FE and again decrement the SP 9 this time to 00FD To finish the SR instruction you load the PC with 0200 10 which is the address of the called subroutine M68HC05 Applications Guide Rev 4 0 66 Microcontroller Operation MOTOROLA For More Information On This Product Go to www freescale com Freescale Semico
275. n On This Product Go to www freescale com Freescale Semiconductor Inc 8 705 8 Functional Data 3 4 Pins and Connections The following paragraphs discuss the MCU pin assignments pin functions and basic connections Because the MC68HC705C8 is a CMOS device unused input pins must be terminated to avoid oscillation noise and added supply current The preferred method of terminating pins that can be configured for input or output is with individual pullup or pulldown resistors for each unused pin Pin assignments are shown in Figure 3 2 and Figure 3 3 PBO 2 PB3 PB4 5 PB6 PB7 Vss 1 2 3 4 5 6 7 8 9 VDD 05 1 05 2 7 PD5 SS PD4 SCK PD3 MOSI PD2 MISO PDI TDO PDO RDI PCO PC2 PC3 PC4 5 PC6 Figure 3 2 40 Dual In Line Package Pin Assignments M68HC05 Applications Guide Rev 4 0 80 MC68HC705C8 Functional Data For More Information On This Product Go to www freescale com MOTOROLA 3 4 1 Pin Functions 3 4 1 1 Vpp and Vss Freescale Semiconductor Inc MC68HC705C8 Functional Data Pins and Connections 5 4 PA2 1 PAO PBO 1 PB2 PB3 PB4 PD7 TCMP PD5 SS PD4 SCK PD3 MOSI PD2 MISO PDI TDO RDO RDI PCO NC PBS Vss 23 PC
276. n be converted properly into binary machine code EQU short for equate is used to give a specific memory location or binary number a name which can then be used in other program instructions In this case the EQU directive is being used to assign the name PORTB to the value 01 which is the address of port B in the MC68HC7050C8 It is easier for a programmer to remember the mnemonic name PCRTB rather than the anonymous numeric value 01 When the assembler encounters one of these names the name is automatically converted to its corresponding binary value in much the same way that instruction mnemonics are converted into binary instruction codes 0001 PORTB EQU 01 Direct address of port B sw 00a0 ORG SAO Program will start at 500 0 00 8 bo 01 LDA PORTB Read sw at MSB of Port B 1 2 3 4 5 6 gt Figure 2 8 Explanation of Assembler Listing M68HCO5 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation 51 For More Information On This Product Go to www freescale com 0001 0002 0005 0006 0091 00 0 00 0 00 2 00 4 00 6 00 8 00af 0051 0053 0056 0057 0059 0050 00be 00 1 00 3 00c5 00c7 00c8 00c9 00cb 00cc 00ce 0040 b7 a6 b7 b6 2a 1 4a le Oe cd 20 b7 a6 Df 5a 26 4a 26 b6 81 ff 06 0 02 01 fc 00 02 14 00 02 01 00 5 9f 20 fd 9 9f c3
277. n of these external components 5 System Integration This procedure involves putting together finished preliminary software and hardware 6 Testing This step is a design verification process In practice the steps occur in parallel to some degree and some changes normally occur during the development which impact all of the steps In this applications guide we assume you are familiar with M68HC05 Applications Guide Rev 4 0 188 Applications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Hardware Development Methods traditional design methods therefore we will only discuss how MCU based methods differ from traditional methods The first area of difference is in the hardware design where the flexibility of the software driven MCU simplifies the connection of external circuitry Signal polarity and timing are easily controlled by software to match the needs of external components The hardware design consists of connecting peripheral devices to general purpose I O lines and of checking the ability of software to control the connected devices The second and most significant area of difference between MCU based projects and discrete logic projects is the area of software development The preparation of programs replaces the development of complex logic circuits Instead of laboring over complex wire wrapped breadboards with an oscilloscope
278. n usually holding the logic one stop bit WRITE ONLY SCDAT Tx BUFFER 10 11 BIT TX SHIFT REGISTER PIN BUFFER PD1 D CONTROL TDO gt SIZE 89 J AM ENABLE PREAMBLE J AM 15 BREAK J AM O s TRANSFER Tx BUFFER zie SCCR1SCICONTROL 1 SCSR INTERRUPT STATUS FORCE PIN DIRECTION OUT TRANSMITTER CONTROL LOGIC ot SCI Rx REQUESTS TCIE SCCR2 SCI CONTROL 2 SCI INTERRUPT INTERNAL REQUEST DATA BUS Figure 3 21 SCI Transmitter Block Diagram M68HC05 Applications Guide Rev 4 0 138 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com 3 11 2 SCI Receiver Freescale Semiconductor Inc MC68HC705C8 Functional Data Serial Communications Interface SCI The T8 bit in SCI control register 1 SCCR1 acts like an extra high order bit ninth bit of the transmit buffer register This ninth bit is only used if the M bit in SCCR1 is set selecting the 9 bit data character format The M bit also controls the length of idle and break characters The status flag and interrupt generation logic are shown in Figure 3 21 The transmit data register empty TDRE and transmit complete TC status flags the SCI status register SCSR are automatically set by the transmitter logic These tw
279. nations 9 How many different opcodes correspond to the LDA load accumulator instruction 1 3 gt 6 see Appendix Instruction Set Details for a detailed description of the LDA instruction and 2 6 4 Assembler Listing O D 16 10 Inthe following partial listing what 8 bit value or code is present in memory location 0193 018 TIME EQU Update Time of day 018c 3d a2 TST TIC Check for TIC zero 018e 26 38 BNE XTIME If not just exit 0190 3c a3 INC SEC SEC SEC 1 0192 a6 3c LDA 60 0194 bl a3 CMP SEC Did SEC gt 60 O A A2 gt B 3C see 2 6 4 Assembler Listing and 2 6 5 CPU View of a Program O C 93 O D 01 11 The following instruction reads the current value of the 8 bit variable and internally tests for a negative or zero value At what physical address is the variable TIC located 018c 3d a2 TSE TIC Check for TIC zero O A 01A2 O B 018D O C 3DA2 gt D 00A2 see 3 7 4 Direct Addressing Mode M68HC05 Applications Guide Rev 4 0 MOTOROLA Review Questions 321 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions 12 After executing the following sequence of instructions what value will be in the accumulator BEGIN LDA 80 BPL LABEL INCA LABEL DECA DECA 7 gt 7F 80 D 81 The f
280. nc MC68HC705C8 Functional Data On Chip Memory 3 5 On Chip Memory 3 5 1 Memory Types The MC68HC705C8 memory includes 176 to 304 bytes of random access memory RAM 240 bytes of read only memory ROM and 7600 to 7744 bytes of programmable memory EPROM or RAM means that any word in the memory may be accessed without having to go through all the other words to get to it RAM is a volatile form of memory in that all the memory content is lost when the power is removed from the chip RAM contents may be retained by keeping at least 2 volts on Vpp Power requirements in this standby mode are very small ROM is very similar to RAM except unlike RAM it is not possible to change the contents of ROM after it is manufactured This type memory is useful only for storage of information or programs The special bootstrap mode allows programs to be downloaded through the on chip serial communications interface SCI into internal RAM to be executed The bootloaded program is used for a variety of tasks such as loading calibration values into internal EPROM or performing diagnostics on a finished module The MC68HC705C8 on chip ROM is called the bootloader ROM This ROM controls the loading process of the special bootstrap mode Erasable programmable ROM EPROM is nonvolatile memory that can be programmed the field by the user Nonvolatile memories retain their contents even when no power is applied Once it has been pr
281. nch Never BRN 21 2 3 Branch IFF Higher BH1 22 2 3 Branch IFF Lower or Same BLS 23 2 3 Branch IFF Carry Clear BCC 24 2 3 od d or Same BHS 24 2 3 Branch IFF Carry Set BCS 25 2 3 CET mo Branch IFF Not Equal BNE 26 2 3 Branch IFF Equal BEQ 27 2 3 Branch IFF Half Carry Clear BHCC 28 2 3 Branch IFF Half Carry Set BHCS 29 2 3 Branch IFF Plus BPL 2A 2 3 Branch IFF Minus BMI 2B 2 3 Branch IFF Interrupt Mask Bit is Clear 2 2 3 Branch IFF Interrupt Mask Bit is Set BMS 2D 2 3 Branch IFF Interrupt Line is Low BIL 2E 2 3 Branch IFF Interrupt Line is High BIH 2F 2 3 Branch to Subroutine BSR AD 2 6 M68HC05 Applications Guide Rev 4 0 118 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Instruction Set Summary Table 3 5 Control Instructions Relative Addressing Mode Function Mnemonic Speedo visa amp Transfer A to X TAX 97 1 2 Transfer X to A TXA 1 2 Set Carry Bit SEC 99 1 2 Clear Carry Bit CLC 98 1 2 Set Interrupt Mask Bit 9B 1 2 Clear Interrupt Mask Bit CLI 9A 1 2 Software Interrupt SWI 83 1 10 Return from Subroutine RTS 81 1 6 Return from Interrupt RTI 80 1 9 Reset Stack Pointer RSP 9C 1 2 No Operation NOP 9D 1 2 Stop STOP 8E 1 2 Wait WAIT 8F 1 2 3 8 Instruction Set Summary Computers use an operation code or opcode to give i
282. nch if Not 259 BEL Branch PIS aa quia doi doce 260 BRA Branch 261 BRCLR n Branch if Bit n is Clear 262 BRN Branch 263 BRSET n Branch if Bit is Set 264 BSET n Set Bitin 265 BSR Branch to Subroutine 266 ULL Clear Carry 267 CLI Clear Interrupt Mask Bit 268 OT epar or b 269 M68HCO05 Applications Guide Rev 4 0 12 Table of Contents MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents CMP Compare Accumulator with Memory 270 271 CPX Compare Index Register with Memory 272 DEC 273 EOR Exclusive OR Memory with 274 INC 275 JU a MIT 276 JSR Jump to Subroutine 277 LDA Load Accumulator from 278 LDX Load Index Register from Memory 279 LSL Logical Shift 280 LSR Logical PROBE soak ca ek
283. nd RE would be written to one to enable the transmitter and receiver subsystems ILIE RWU and SBK would seldom be used and would be written to zero If interrupts were not being used TIE TCIE and RIE would be written to zero If interrupts were used these three bits would be written to one For example in a system which does not use interrupts SCCR2 would be loaded with 0C during initialization 3 11 3 4 Serial Communications Status Register SCSR SCI status register SCSR in Figure 3 27 contains two transmitter status flags and five receiver related status flags The TDRE and RDRF bits are always used The TC and IDLE bits are not commonly used BIT 7 6 4 3 2 1 BIT 0 ww oe oe T7 T 9 1 1 0 0 0 0 0 RESET CONDITION FRAMING ERROR NOISE FLAG OVERRUN IDLE LINE DETECT RECEIVE DATA REGISTER FULL TRANSMISSION COMPLETE TRANSMIT DATA REGISTER EMPTY Figure 3 27 Serial Communications Status Register The OR NF and FE bits should be monitored and may or may not be used depending on the type of SCI system For errors to be corrected both the transmitting and receiving device must have a common method of handling errors There are two major types of communication links associated with the SCI An example of a direct connection would be an MCU connected to a personal computer In this direct connection link OR NF and F
284. nditional r register ACCA or X memory operand M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details 249 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Details BHS Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Branch if Higher or Same B HS Same as BCC PC lt PC 0002 Rel if C 20 i e if ACCA 2 M unsigned binary numbers If the BHS instruction is executed immediately after execution of a CMP or SUB instruction the branch will occur if the unsigned binary number in ACCA was greater than or equal to the unsigned binary number in M See BRA instruction for further details of the execution of the branch H 7 C 1 1 1 None affected Source Addressing Machine Code HCMOS BHS rel REL 24 rr 3 The following table is a summary of all branch instructions Test Boolean Mnemonic Opcode Complementary Branch Comment r gt m C Z 0 BHI 22 BLS 23 Unsigned 0 BHS BCC 24 rm BLO BCS 25 Unsigned r m Z 1 BEQ 27 26 Unsigned r lt m C Z 1 BLS 23 r gt m BHI 22 Unsigned rm C 1 BLO BCS 25 gt 5 24 Unsigned Carry 1 BCS 25 No Carry BCC 24 Simple r 0 Z1 BEQ 27 r 0 BNE 26 Simp
285. nductor Inc Microcontroller Operation CPU Operation The CPU fetches the next instruction Since the PC is 0200 the CPU executes the DECA instruction the first instruction in the subroutine You cross out the 02 in the accumulator column and write the new value 01 11 You also change the PC to 0201 12 Because the DECA instruction changed the accumulator from 02 to 01 which is not zero or negative the Z bit and N bit remain clear Since N and Z were already cleared at 5 you can leave them alone on the worksheet The CPU now executes the BNE SUBBY instruction Since the Z bit is clear the branch condition is met and the CPU will take the branch Cross out the 0201 under PC and write 0200 13 The CPU again executes the DECA instruction The accumulator is now changed from 01 to 00 14 which is zero and not negative thus the Z bit is set and the N bit remains clear 15 The PC advances to the next instruction 16 The CPU now executes the BNE SUBBY instruction but this time the branch condition is not true Z is set now so the branch will not be taken The CPU simply falls to the next instruction the RTS at 0203 Update the PC to 0203 17 The RTS instruction causes the CPU to recover the previously stacked PC Pull the high order half of the PC from the stack by incrementing the SP to 00FE 18 and by reading 01 from location 00FE Next pull the low order half of the address from the stack by inc
286. nformation On This Product Go to www freescale com Freescale Semiconductor Inc Applications Listing Thermostat Example Sheet 5 of 21 Ck CK Sk Ck Ck CK Ck Ck CK CC CK C Ck CK C Ck CK Ck Ck CK C Ck CC Ck CK Ck Ck Ck Ck Ck CK Ck Ck Ck Ck Ck C Sk Ck Ck Sk Sk Sk Pk Sk Sk kA Mk kx Kk kx MAIN Beginning of main program loop Loop is executed onc very 50mS exactly pass through all major task routines takes less than 505 and then time is wasted until the output compare flag gets set every 50mS When output compare triggers the flag is cleared amp 12500 is added to the compare 2 So the next trigger will occur in exactly 50mS 12500 4uS cnt 505 Xtal 2MHz bus 1MHz The variable keeps track of 50mS periods when TIC increments from 19 to 20 it is cleared to 0 and seconds are incremented e The keypad is checked every 50mS pass and a new d closure or release is not acted upon until the pass after it is first seen This acts E switch debounce The display is updated only when seconds change 2 Display call is at bottom of main loop so any change caused by a key is reflected in the display update gt Temperature readings only taken once sec Ck CK Ck Ck Ck CK Ck Ck CK CC CK C Ck CK CC CSS Ck CK CC CK Ck Ck CK Ck Ck Ck KC C Ck Ck CK C
287. not NTRY Clear ENTRY CDEQ amp its BCD equivalent NTFLG 0 gt 1 NO LONGER 1st Get hex 0 9 in left nibble H UJ Ed e z nnnn 0000 amp BCDEQ yyyy 220 Applications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Thermostat Project Details Listing Thermostat Example Sheet 10 of 21 0268 48 ASLA Roll new digit into BCD 0269 39 a4 ROL BCDEQ Equiv of ENTRY 026b 48 ASLA With 4 double byte 026 39 a4 ROL BCDEQ left shifts 026 48 ASLA 026 39 a4 ROL BCDEQ 0271 48 ASLA 0272 39 a4 ROL BCDEQ BCDEQ now yyyy nnnn 0274 b6 a4L DA BCDEQ 0276 a4 Of AND 50 Mask off 10 s 0278 b7 a5 STA ENTRY Temp save 1 5 027a b6 a4 LDA BCDEQ Get BCD again 027 44 LSRA Right justify 10 s 027 44 LSRA 027 44 LSRA 027 44 LSRA 0280 ae 0 LDX 10 0282 42 MUL A lt 10 BCD 10 s 0283 bb 5 DD ENTRY Add in ones 0285 b7 a5 STA ENTRY Now binary equiv of BCDEQ 0287 20 2d BRA KEYFE Acknowledge key and leave 0289 al 21 TRYENT CMP 028b 26 29 BNE KEYFE If not Ack key amp leave 028d cd 02 bb JSR CHKPNT Check for legal entry On return N bit indicates legal Positive amp
288. nputs and which will be outputs Although any one application is likely to need only one specific mixture of inputs and outputs twenty different applications are likely to need a dozen collective mixtures The ability to specify the direction of each pin at the time of use makes this MCU ideal for many different applications Control registers are controlled by the CPU in essentially the same way as a digital output port You could think of control status registers as internal I O registers connected to internal logic rather than to MCU pins To change the voltage level at an output pin the CPU writes a digital value to the address of the output port register The level 0 or 1 in each bit of the output port register controls the voltage level on a corresponding MCU pin In the case of a control register the state of a bit in the control register determines the logic level of an internal control signal rather than on a pin In Section 3 MC68HC705C8 Functional Data of this applications guide you will find more complete descriptions of the on chip peripherals in the MC68HC705C8 M68HC05 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation 69 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation 2 8 1 Serial Communications Interface SCI SCI system on the MC68HC705C8 is a UART type asynchronous serial communications interface The mos
289. ns are used for transmitting and receiving data serially MSB first LSB last When the SPI is configured as a master MISO is the master data input line and MOSI is the master data output line In the master device the MSTR control bit bit 4 of the serial peripheral control register is set to a logic one by the program to allow the master device to output data on its MOSI pin When the SPI is configured as a slave these pins reverse roles MISO becomes the slave data output line and MOSI becomes the slave data input line M68HC05 Applications Guide Rev 4 0 156 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Synchronous Serial Peripheral Interface SPI The timing diagram of Figure 3 36 shows the relationship between data and clock 5 As shown in Figure 3 36 four possible timing relationships may be chosen by using control bits CPCL and CPHA Setting CPCL is equivalent to putting an inverter in series with the clock signal CPHA selects one of two fundamentally different clocking protocols to allow the SPI system to communicate with virtually any synchronous serial peripheral device SCK CPOL 0 SCK CPOL 1 SS SLAVES SAMPLE INPUT 2 A MSB X BIT 6 X BITS XO 4X BT 3 XBT 2 ABIT LX 158 yy
290. nserve power since power consumption increases with higher clock frequencies Static operation may also be advantageous during product development Two software controlled power saving modes WAIT and STOP are available to conserve additional power These modes make the MC68HC705C8 especially attractive for automotive and battery driven applications M68HCO05 Applications Guide Rev 4 0 76 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 3 3 MCU Description MC68HC705C8 Functional Data MCU Description The hardware and software highlights of the MC68HC705C8 are shown in the following subsections 3 3 1 Hardware Features HCMOS technology 8 bit architecture Power saving stop wait and data retention modes 24 bidirectional I O lines 7 input only lines 2 timer pins 2 1 MHz internal operating frequency 5 volts 1 0 MHz 3 volts Internal 16 bit timer Serial communications interface SCI system Serial peripheral interface SPI system Ultraviolet UV light EPROM or one time programmable ROM OTPROM Selectable memory configurations Computer operating properly COP watchdog system Clock monitor On chip bootstrap firmware for programming Software programmable external interrupt sensitivity External pin timer SCI and SPI interrupts Master reset and power on reset Single 3 to 6 volt supply 2 volt data retention
291. nses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part MOTOROLA Motorola and the Stylized M Logo are registered in the U S Patent and Trademark Office digital dna is a trademark of Motorola Inc All other product or service names are the property of their respective owners Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Inc 2002 M68HCO05AG D For More Information On This Product Go to www freescale com
292. nstruction Set ORA Performs the logical inclusive OR between the contents of ACCA and the contents of M and places the result in ACCA Each bit of ACCA after the operation will be the logical inclusive OR of the corresponding bits of M and of ACCA before the operation H 2 1 1 N R7 Set if MSB of result is set cleared otherwise 2 R7 e R6 R5 R4 R2 Set if result is 00 cleared otherwise Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles ORA opr IMM AA i 2 ORA opr DIR BA dd 3 ORA opr EXT CA hh 4 3 ORA opr X EA ff 4 ORA 1X2 DA ee ff 5 M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details For More Information On This Product Go to www freescale com 285 Freescale Semiconductor Inc Instruction Set Details ROL Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Rotate Left thru Carry RO L c 07 lt c Shifts all bits of ACCA X or M one place to the left Bit 0 is loaded from the C bit The C bit is loaded from the MSB of ACCA X or M The rotate instructions include the carry bit to allow extension of the shift and rotate operations to multiple bytes For example to shift a 24 bit value left one bit
293. nstructions Test Boolean Mnemonic Opcode Complementary Branch Comment C Z 0 BHI 22 BLS 23 Unsigned 0 BHS BCC 24 rm BLO BCS 25 Unsigned r m Z 1 BEQ 27 26 Unsigned r lt m C Z 1 BLS 23 r gt m BHI 22 Unsigned rm C BLO BCS 25 gt 5 24 Unsigned Carry C BCS 25 No Carry BCC 24 Simple r 0 2 1 27 r 0 BNE 26 Simple Negative N 1 BMI 2B Plus BPL 2A Simple Mask 1 5 2 Mask 0 BMC 2C Simple Half Carry H 1 BHCS 29 No Half Carry BHCC 28 Simple IRQ Pin High BIH 2F IRQ Low BIL 2E Simple Always 20 21 Unconditional r register ACCA or X memory operand M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details 255 For More Information On This Product Go to www freescale com Operation Description Condition Codes and Boolean Freescale Semiconductor Inc Instruction Set Details Branch if Interrupt Mask is Clear lt 0002 Rel if l 0 BMC Tests the state of the bit in the CCR and causes a branch if is clear i e if interrupts are enabled See BRA instruction for further details of the execution of the branch H 2 1 1 1 None affected Source Forms Addressing Source Addres
294. nstructions to the CPU The instruction set for a specific CPU is the set of all opcodes that the CPU knows how to execute The CPU in the MC68HC705C8 MCU can understand 62 basic instructions some of which have several variations that require separate opcodes The IV168HC05 instruction set includes 210 unique instruction opcodes M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 119 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8 705 8 Functional Data Table 3 6 is an alphabetical listing of the M68HC05 instructions available to the user In listing all the factors necessary to program the table uses the following symbols Condition Code Symbols H Half Carry Bit 4 Interrupt Mask Bit 3 Negate Sign Bit 2 Z Zero Bit 1 Carry Borrow Bit 0 Contents of i e means the contents of memory location M lt is loaded with gets e AND Accumulator ACCA Accumulator CC Condition Code Reg Index Register M Any memory location Addressing Modes Inherent Immediate Direct for bit test instructions Extended Indexed 0 Offset Indexed 1 Byte Indexed 2 Byte Relative Abbreviation INH IMM DIR 1 Test and Set if True cleared otherwise Not Affected 2 Load CC from Stack 0 Cleared 1 Set Boolean Operators
295. nt manufacturers use different sets of opcodes because these opcodes are internally hard wired in the CPU logic The instruction set for a specific CPU is the set of all opcodes that the CPU knows how to execute Even though the opcodes differ from one computer to another all digital binary computers perform the same kinds of basic tasks in similar ways The CPU in the MC68HC05 MCU can understand 62 basic instructions Some of these basic instructions have several slight variations each requiring a separate opcode The instruction set of the MC68HC05 includes 210 unique instruction opcodes We will discuss how the CPU actually executes instructions a little later in this section after a few more basic concepts have been presented An opcode such as 4C is understood by the CPU but it is not very meaningful to a human To solve this problem a system of mnemonic instruction formats is used The 4C opcode corresponds to the INCA mnemonic which is read increment accumulator Although there is printed information to show the correlation between mnemonic instructions and the opcodes they represent this information is seldom used by a programmer because the translation process is automatically M68HC05 Applications Guide Rev 4 0 34 Microcontroller Operation MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation Computer Codes handled by a separate com
296. o www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Programmable Timer 3 14 7 Timer Control Register TCR The timer control register see Figure 3 47 is 8 bit read write register containing five control bits Three of these bits control interrupts associated with the three flag bits found in the timer status register The other two bits control 1 which edge is significant to the input capture edge detector i e negative or positive and 2 the next value to be clocked to the TCMP output pin in response to a successful output compare The TCMP pin is forced low during external reset and stays low until a valid compare changes it to a high BIT 7 6 5 4 3 2 1 BIT 0 Toce T Te s re 0 0 0 0 0 0 0 RESET CONDITION QUTPUT COMPARE LEVEL NPUT CAPTURE EDGE O FALLING 1 RISING TIMER OVERFLOW INTERRUPT ENABLE QUTPUT COMPARE INTERRUPT ENABLE NPUT CAPTURE INTERRUPT ENABLE Figure 3 47 Timer Control Register 3 14 8 Timer Status Register TSR The timer status register see Figure 3 48 is an 8 bit register with three read only bits that indicate the following status information 1 Aselected transition has occurred at the edge input TCAP pin with an accompanying transfer of the free running counter contents to the input capture register 2 Amatch has been found between the free running counter and the output c
297. o bits can be read at any time by software The transmit interrupt enable TIE and transmit complete interrupt enable TCIE control bits enable the TDRE and TC flags respectively to generate SCI interrupt requests The receiver block diagram is shown in Figure 3 22 SCI received data comes in on the RDI pin is buffered and drives the data recovery block The data recovery block is actually a high speed shifter operating at 16 times the bit rate the main receive serial shifter operates at one times the bit rate This higher speed sample rate allows the start bit leading edge to be located more accurately than a 1 x clock would allow The high speed clock also allows several samples to be taken within a bit time so logic can make an intelligent decision about the logic sense of a bit even in the presence of noise The data recovery block provides the bit level to the main receiver shift register and also provides a noise flag status indication The heart of the receiver is the receive serial shift register This register is enabled by the receive enable RE bit in the SCI control register 2 SCCR2 The M bit from the SCCR1 register determines whether the shifter will be 10 or 11 bits After detecting the stop bit of a character the received data is transferred from the shifter to the SCIDAT and the receive data register full RDRF status flag is set When a character is ready to be transferred to the receive buffer but the previous charact
298. o of the four programs do not make any assumptions about other bits in port A O A PROG1 amp PROG2 O B PROG2 amp PROG4 O C PROG3 amp PROG4 D PROG4 amp 1 39 68 705 8 which of the following pins is input only pin O A RESET O B Port D bit 4 SCK O C Port D bit 7 O D Port A bit 7 40 What does the following sequence of instructions do 0100 a6 08 START LDA 508 Comments left off intentionally 0102 b7 le STA SIE 0104 8e STOP O A Reset the COP watchdog timer and return to normal program O B Force a hardware RESET O C Store a value 08 in RAM and stop processing O D Enables the clock monitor and the COP watchdog timer 41 For the four following addresses which one would not allow you to read back an arbitrary value which you just wrote to that address O A 0004 O B 0050 O C 00FF O D 1000 M68HC05 Applications Guide Rev 4 0 MOTOROLA Review Questions 315 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions 42 43 44 45 46 For an MC68HC705C8 which of the four following addresses would be the best address to store a product serial number and a variable which changed once a second Refer to the Figure 3 7 MC68HC705C8 Memory Map of the applications guide O A 0000 002F 00FF D 015F If you discovered an incorrect value in a memory location as y
299. ocation 0050 into the accumulator M68HC05 Applications Guide Rev 4 0 106 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Addressing Modes Instruction Add with Carry Add Logical AND Arithmetic Shift Left Arithmetic Shift Right Clear Bit in Memory Bit Test Memory with Accumulator Branch if Bit n is Clear Branch if Bit n is Set Set Bit in Memory Clear Compare Accumulator with Memory Complement Compare Index Register with Memory Decrement Exclusive OR Memory with Accumulator Increment Jump Jump to Subroutine Load Accumulator from Memory Load Index Register from Memory Logical Shift Left Logical Shift Right Negate Inclusive OR Rotate Left thru Carry Rotate Right thru Carry Subtract with Carry Store Accumulator in Memory Store Index Register in Memory Subtract Test for Negative or Zero Mnemonic ADC ADD AND ASL ASR BCLR BIT BRCLR BIRSET BSET CLR CMP COM CPX DEC EOR INC JMP JSR LDA LDX LSL LSR NEG ORA ROL ROR SBC STA STX SUB TST The following is a list of all M68HCO5 instructions that can use the direct addressing mode M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data For More Information On This Product Go to www freescale com 107 Freescale Semiconductor Inc MC68HC705C8 Functional Data 3 7 5 Indexed Addressing Mode
300. ocessing parameters and will be between 5 and 100 us Thus a bus clock rate of 200 kHz or more will never cause a clock monitor failure and a bus clock rate of 10 kHz or less will definitely cause a clock monitor reset A clock monitor reset is issued to the external system via the bidirectional RESET pin for four bus cycles The clock monitor does not have a separate reset vector Special considerations are needed when using the STOP instruction with the clock monitor Since the STOP instruction causes the clocks to be halted the clock monitor will generate a reset sequence if enabled by CME 1 at the time the STOP instruction is entered 3 7 Addressing Modes The power of any computer lies in its ability to access memory The addressing modes of the CPU provide that capability The addressing modes define the manner in which an instruction is to obtain the data required for its execution Because of different addressing modes an instruction may access the operand in one of up to six different ways In this manner the addressing modes expand the basic 62 M68HC05 Family instructions into 210 distinct opcodes The 68 5 addressing modes that are used to reference memory are inherent immediate extended direct indexed no offset 8 bit offset and 16 bit offset and relative One and two byte direct M68HCO5 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 99 For More Information On This Produc
301. ode 2 CPU then reads 07 from location 0201 This 07 is interpreted as the high order half of a base address 3 CPU then reads 00 from location 0202 This 00 is interpreted as the low order half of a base address 4 CPU will add the value in the index register to the base address 0700 The results of this addition is the address that the CPU will use in the load accumulator operation 5 The CPU will then read the value from this address and load this value into the accumulator M68HC05 Applications Guide Rev 4 0 112 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Addressing Modes The following is a list of all M68HCO5 instructions that can use the indexed 16 bit offset addressing mode 3 7 6 Relative Addressing Mode Instruction Add with Carry Add Logical AND Bit Test Memory with Accumulator Compare Accumulator with Memory Compare Index Register with Memory Exclusive OR Memory with Accumulator Jump Jump to Subroutine Load Accumulator from Memory Load Index Register from Memory Inclusive OR Subtract with Carry Store Accumulator in Memory Store Index Register In Memory Subtract Mnemonic ADC ADD AND BIT CMP CPX EOR JMP JSR LDA LDX ORA SBC STA STX SUB The relative addressing mode is used only for branch instructions Branch instructions other than the branching ve
302. oded information This text representation makes it easier to develop the program Previously programs for computers had to be in binary form the native code of the computer Translate the source file The text file is then translated into a binary object file or S record encoded object file by an assembler This assembler program runs on the development station not on the MCU The assembler does not usually directly generate the final binary file i e the object code or executable file for the MCU since this file has to be transferred from the development station to the MCU The transfer process can create errors from external electrical noise Motorola has a file transfer form which encodes the MCU object file into ASCII data with a checksum for error detection This encoding is referred to as Motorola S records or 51 59 records Transfer the object file into the MCU The final step in developing MCU based systems is to transfer the S record or binary file the MCU program to the MCU itself We can take the binary or S record file and send it to program an external EPROM in an EPROM programmer send it to an EPROM programmer to program the MCU directly not all EPROM programmers support this or send the file to the MCU in bootstrap mode and have the MCU program itself In all cases the S record file is used and is translated to binary during the programming process so the MCU can use the object file M68HC05 Applications Guid
303. oduct Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data cn 4 ats MC68HC705C8 105627 10 XTAL LI 25pF 25 pF a Crystal Ceramic Resonator Oscillator Connections 4 gt gt MC68HC705C8 1017052 UNCONNECTED lt EXTERNAL CMOS CLOCK b External Clock Source Connections 4 Figure 3 4 Oscillator Connections M68HC05 Applications Guide Rev 4 0 84 MC68HC705C8 Functional Data For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc MC68HC705C8 Functional Data Pins and Connections 3 4 1 10 PC7 PCO These eight lines comprise port C Each port C pin can be software programmed to act as an input or output 3 4 1 11 PD5 PDO0 and PD7 These seven lines comprise port D During power on or reset these seven pins are configured as inputs When the SPI system is enabled four of these lines MISO PD2 MOSI PD3 SCK PD4 and SS PD5 are used by the SPI system When the SCI receiver is enabled the PDO RDI pin becomes the receive data input to the SCI When the SCI transmitter is enabled the PD1 TDO pin becomes the transmit data output for the 3 4 2 Typical Basic Connections There are MCU basic connections that can be used as the starting point for any application to minimize the time required to
304. oduct Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Serial Communications Interface SCI 3 11 6 2 Normal Transmit Operation Refer to Figure 3 31 a flowchart of the normal transmit operation FLOWCHART MNEMONIC PROGRAM START SUBROUTINE SENDATA BRCLR 7 SCSR SENDATA WRITE DATA ee STA SCDAT RETURN FROM SUBROUTINE 5 Figure 3 31 SCI Normal Transmit Operation Flowchart 3 11 6 3 Normal Receive Operation Refer to Figure 3 32 a flowchart of the normal receive operation FLOWCHART MNEMONIC PROGRAM START SUBROUTINE GETDATA BRCLR 5 SCSR GETDATA NO READ DATA FROM SCDAT LDA SCDAT RETURN FROM SUBROUTINE RTS Figure 3 32 SCI Normal Receive Operation Flowchart M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 149 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8 705 8 Functional Data 3 11 7 SCI Application Example Figure 3 33 is an example software program for communication between the SCI of the MCU and a dumb terminal The MCU will receive read an ASCII character that was sent by the dumb terminal The MCU will then translate the 8 bit binary character representing the ASCII character into two ASCII characters When this translation is completed the MCU will transmit a lt CR gt line feed a sign and the two characters that represent the orig
305. ogrammable ROM OTPROM MCUs are shipped in an erased state and are packaged in an opaque plastic package thus erasing operations cannot be performed on OTPROM MCUs Programming operations are controlled by software accessible control bits The software program which programs the internal EPROM OTPROM is located in either the on chip bootstrap ROM or internal RAM The first programming method uses a program in the bootstrap ROM to read information from an external 8K by 8 EPROM and to program this information into the on chip EPROM OTPROM The external EPROM is connected to I O port pins of the MC68HC705C8 In this programming method information to be programmed into the internal EPROM OTPROM is first programmed into the external EPROM using an industry standard PROM programmer A second programming method allows user programs developed on a personal computer to be downloaded to the MC68HC705C8 for programming into the on chip EPROM OTPROM This method eliminates the extra steps needed to program a separate 8K by 8 EPROM A small program that runs on the personal computer is M68HC05 Applications Guide Rev 4 0 182 68 705 8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data OTPROM EPROM Programming available through the Motorola FREEWARE bulletin board service BBS and can be downloaded for the price of the phone cal
306. ogrammed the EPROM cannot be written into but it can be read from as many times as necessary However EPROM can be erased by ultraviolet light and reprogrammed OTPROM is the same as EPROM except it can be programmed only once and cannot be erased M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 87 For More Information On This Product Go to www freescale com 3 5 2 Memory 3 6 Central Processor Unit Freescale Semiconductor Inc 8 705 8 Functional Data MC68HC705C8 MCU contains four selectable memory configurations as shown in Figure 3 7 The memory configurations are accessed via the option register 1FDF RAMO and RAM bits During reset the RAMO and control bits are forced to 0 RAMO and RAM bit states determine the amount of RAM and PROM which can be selected as follows RAMO RAM1 RAM Bytes PROM Bytes 0 0 176 7744 1 0 208 7696 0 1 272 7648 1 1 304 7600 MC68HC705C8 CPU is responsible for executing all software instructions in their programmed sequence for a specific application The CPU block diagram is shown in Figure 3 6 CPU CONTROL ARITHMETIC LOGIC UNIT ALU M68HC05 CPU U REGISTERS ACCUMULATOR INDEX REGISTER 01010 0 0 1 1 STACK POINTER 0 010 PROGRAM COUNTER CONDITION CODES 1 1 1 1 1 N Z C
307. ompare register 3 Afree running counter transition from FFFF to 0000 has been sensed timer overflow M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 175 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data NOTE BIT7 BIT 0 TSR 0 0 0 0 0 RESET CONDITION L TIMER OVERFLOW FLAG OUTPUT COMPARE FLAG INPUT CAPTURE FLAG Figure 3 48 Timer Status Register ICF The input capture flag ICF is set when a proper edge has been sensed by the input capture detector It is cleared by a processor access of the timer status register with ICF set followed by accessing the low byte 15 of the input capture register OCF The output compare flag OCF is set when the output compare register contents matches the contents of the free running counter OCF is cleared by accessing the timer status register with OCF set and then accessing the low byte 17 of the output compare register TOF The timer overflow flag TOF bit is set by a transition of the free running counter from FFFF to 0000 It is cleared by accessing the timer status register with TOF set and then accessing the least significant byte 19 of the free running counter The counter alternate register contains the same value as the free running counter but reading the alternate register does not clear TOF
308. on separate pins every transfer When an SPI transfer occurs an 8 bit character is shifted out on one data pin while a different 8 bit character is simultaneously shifted in on a second data pin see Figure 3 35 Another way to think of this is that an 8 bit shift register in the master and another in the slave are connected as a circular 16 bit shift register When a transfer occurs this distributed shift register is shifted eight bit positions so the characters in the master and slave are effectively exchanged Many simple slave devices are designed to only receive data from a master or only supply data to a master For example a serial to parallel shift register can act as an 8 bit output port An MCU configured as a master SPI device would initiate a transfer to send an 8 bit data value to the shift register Since the shift register does not send any data to the master the master would simply ignore whatever it received as a result of that transmission MOSI SPISHIFT REGISTER SPISHIFT REGISTER cn EBENEN gt RECEIVE BUFFER RECEIVE BUFFER SCK MC68HC705C8 MC68HC705C8 MASTER DEVICE SLAVE DEVICE Figure 3 35 Shift Register Operation M68HCO05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 155 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data 3 12 2 Functional Description
309. ons 319 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions Which of these CPU registers in the MC68HC705C8 contains the most bits O A The accumulator A O B The index register X O C The condition code register CCR gt D The program counter PC See Figure 2 2 M68HC05 CPU Registers The PC is 13 or 16 bits depending on whether or not you count the upper three bits that are fixed A and X are 8 bits each and CCR is 5 or 8 again depending on whether or not you count the upper three bits that are fixed 7 Which CPU register in the MC68HC705C8 would most likely point to the next instruction that the CPU will execute O A The accumulator A O B The index register X O C The stack pointer SP gt D The program counter PC see 2 4 3 CPU Registers During execution of a subroutine where would the CPU save the return address All except one of the following address pairs is incorrect due to improper memory type or address O A 1FFE 1FFF gt B 00EC 00ED O C 00AE 00AF O D 015E 015F See 3 6 1 5 Stack Pointer and 2 7 1 4 Subroutine Calls and Returns if you need help understanding subroutine calls M68HC05 Applications Guide Rev 4 0 320 Review Questions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions Review Questions Answers and Expla
310. ontinuously Read present port A data Form new port A pattern Write to port A Repeat loop continuously M68HCO5 Applications Guide Rev 4 0 MOTOROLA For More Information On This Product Go to www freescale com Review Questions 313 Freescale Semiconductor Inc Review Questions 33 34 35 36 37 Which of the four programs requires the fewest bytes of program memory A PROG O B PROG2 O C PROG3 O D PROG4 Which of the four programs produces the shortest pulse width logic one at the pin A 1 PROG2 PROG3 D PROG4 Which the four programs produces the longest period PROGI O B PROG2 O C PROG3 O D PROG4 Sometimes it is important to change the level on a pin without disturbing values in the CPU accumulator and other CPU registers Which of the four programs uses no CPU registers other than the program counter PC A PROGI O B PROG2 C PROG3 O D PROG4 Which of the four programs produces a square wave equal high and low times A PROG1 O B PROG2 C PROG3 O D PROG4 M68HC05 Applications Guide Rev 4 0 314 Review Questions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions Review Questions 38 Some instructions affect only a single bit in a memory location while others affect all bits in a memory location Which tw
311. oodo 10 861 SHO 19 91 Bexepul xl pepuerxa 1X4 2 10 JequinN G 1e8JO 19 8 pexepul XI paq SHO ON WNI epoodo JSN 0 794 1ueJeuu HNI 127 XI XLS XLS v S XI L EXI 6 usr S Instruction Set Summary LXI oc LXI MC68HC705C8 Functional Data a 2 2 LXI a lt LXI LXI oav v LXI tc o LLI LXI VLS S LXI v LXI lig v LXI LXI v LXI 99 v LXI Freescale Semiconductor Inc 16 9 i oc v lt we S tc VLS 9 val S S S S 985 S 1X3 tr culo Wt 7 X X lt X 5 55 X X X a gt LXI a 2 v n o gt ans S x 151 tc 2 Ajo gaj lt 0 v qi 6 uia ula 6 uia WO
312. or the opcode and two for the address of the operand Example Program Listing 0200 6 06 LDA 506 5 Load accumulator from extended addr Execution Sequence 0200 C6 1 0201 06 2 0202 5 5 3 and 4 Explanation 1 CPU reads opcode C6 load accumulator using extended addressing mode 2 CPU then reads 06 from location 0201 This 06 is interpreted as the high order half of an address 3 CPU then reads E5 from location 0202 This E5 is interpreted as the low order half of an address 4 CPU internally appends 06 to the E5 read to form the complete address 06E5 The CPU then reads whatever value is contained in the location 06E5 into the accumulator M68HC05 Applications Guide Rev 4 0 104 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Addressing Modes The following is a list of all M68HCO5 instructions that can use the extended addressing mode 3 7 4 Direct Addressing Mode Instruction Mnemonic Add with Carry ADC Add ADD Logical AND AND Bit Test Memory with Accumulator BIT Compare Accumulator with Memory CMP Compare Index Register with Memory CPX Exclusive OR Memory with Accumulator EOR Jump imp Jump to Subroutine JSR Load Accumulator from Memory LDA Load Index Register from Memory LDX Inclusive OR ORA Subtract with Carry SBC Store Accumulator in Memo
313. ord to LCD peripheral x Enter with control word in accumulator A s Return with original value of X R Delay 4 5mS if 501 or 02 else delay 12045 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK 0620 al WCTRL STX TEMPX Save X 0622 b7 00 STA PORTA write control word to LCD 0624 14 02 BSET 2 PORTC gt 1 0626 15 02 BCLR 2 PORTC gt 0 0628 ae 14 LDX 20 20 6 1uS 120 5 062 5a 11200 DECX Delay loop 12015 0625 26 fd BNE L120U 20 19 19 18 1 0 062d al 02 CMP 502 Commands 501 amp 02 req extra delay 062f 22 06 BHI ARN5M If command 02 skip long delay 0631 cd 06 39 L5M JSR ANRTS JSR RTS TAKES 12 just want delay 0634 5a DECX TAKES 3 X 0 gt 1 on first pass 0635 26 fa BNE L5M 3 Loop 256 18 1US 4 608mS Delay 0637 be al 5 LDX TEMPX Restore X 0639 81 ANRTS RTS RETURN KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK WDAT Write data word to LCD peripheral Enter with data word in accumulator Return with original values of X amp Delay 12018 after data write x KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK 063 bf al WDAT STX TEMPX Save X 063c b7 a0 STA TEMPA Save A 063e b7 00 STA PORTA Write data word to LCD 0640 12 02 BSET 1 PORTC RS gt 1 0642 14 02 BSET 2 PORTC gt 1 0644 15 02 BCLR 2 PORTC gt 0 0646 13 02 BCLR 1 PORTC RS gt
314. ormation On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data STOP WAIT Instruction Effects 3 15 2 3 SPI Action During Stop Mode When the MCU enters the stop mode the bit rate generator driving the SPI stops halting all master mode SPI operation Thus the master SPI is unable to transmit or receive data If the STOP instruction is executed during an SPI transfer that transfer is halted until the MCU exits the stop mode if the exit resulted from a logic low on the IRQ pin If the STOP mode is exited by a reset then the appropriate control status bits are cleared and the SPI is disabled If the device is in the slave mode when the STOP instruction is executed the slave SPI will still operate It can still accept data and clock information in addition to transmitting its own data back to a master device At the end of a transmission with a slave SPI in the STOP mode no flags are set until a logic low IRQ input results in an MCU wake up When the MCU enters the STOP mode all enabled output drivers TDO TCMP MISO MOSI and SCK ports remain active Any sourcing currents from these outputs will be part of the total supply current required by the device 3 15 2 4 Wait Mode Effects When the MCU enters the wait mode the CPU clock is halted All CPU action is suspended however the timer SCI and SPI systems remain active An interrupt from the timer SCI or SPI in addition
315. orrow in the implied subtraction from zero cleared otherwise The C bit will be set in all cases except when the contents of ACCA X or M prior to the NEG operation is 00 Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles NEGA INH A 40 3 NEGX INH X 50 3 NEG opr DIR 30 dd 5 NEG X IX 70 5 NEG opr X 60 ff 6 M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details 283 For More Information On This Product Go to www freescale com Instruction Set Details NOP Description Condition Codes Freescale Semiconductor Inc No Operation NOP This is a single byte instruction that causes only the program counter to be incremented No other registers are affected and Boolean 7 Formulae 1 1 1 None affected Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Operand s Cycles Code and Cycles NOP INH 9D 2 M68HCO5 Applications Guide Rev 4 0 284 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc Inclusive OR lt ACCA Instruction Set Details M68HC05 I
316. ortion of text from which the information was obtained M68HC05 Applications Guide Rev 4 0 MOTOROLA Review Questions 303 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions B 3 Review Questions 1 The instruction set of a CPU is O A asoftware program written by an end user the same for all computers O C determined by the wiring within the CPU D the data sheet for a microprocessor Which numbering system offers the best compromise between the needs of a CPU and those of a human O A Binary O B Octal O C Decimal O D Hexadecimal A specific 8 bit value in a computer memory can mean different things depending on its context The value could be a number a code representing an alphabetic character a code for an instruction opcode etc The hexadecimal value 42 could be interpreted by an MC68HC705C8 to mean any of the following things except one Choose the one answer which is not likely to be a correct interpretation of the value 42 O A The opcode for the MUL multiply instruction O B The decimal value 66 O C The address of an on chip control register O D The letter B Which of the following items requires the most memory bits O A The BCD representation of 125 O B The binary representation of 254 C The ASCII representation of the letter O D The binary equivalent of the octal number 75g M68H
317. ou were starting volume production which of the following memory types would require the longest time to correct the error O A RAM O B ROM O C EPROM O D EEPROM A microcontroller includes a central processor unit CPU O B memory O C I O devices O D all of the above A central processor unit CPU O A is part of a microcontroller MCU O B is acomplete computer system C contains memory and I O devices O D contains an MCU A memory is said to be volatile if it forgets its contents when power is removed for long periods of time Which of the following memory types is volatile O A ROM O B RAM O C EPROM O D EEPROM M68HCO05 Applications Guide Rev 4 0 316 Review Questions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions Review Questions 47 EPROM memory is normally erased by O A software instructions O B infrared light O C ultraviolet light O D application of high voltage 48 To program the OPTION register on the MC68HC705C8 O A program all bits as if they were EPROM O B program all bits as if they were RAM O C program one bit like RAM and the rest of the bits as if they were EPROM O D program one bit like EPROM and the rest of the bits as if they were RAM 49 n the MC68HC705C8 bit manipulation instructions BSET and BCLR A can be used to access any on chip I
318. ould be interpreted by an MC68HC705C8 to mean any of the following things except one Choose the one answer which is not likely to be correct interpretation of the value 42 O A The opcode for the MUL multiply instruction See Appendix A Instruction Set Details O B The decimal value 66 See Table 2 1 Decimal Binary and Hexadecimal Equivalents gt C The address of an on chip control register D The letter B See Table 3 12 ASCII Hexadecimal Code Conversion By elimination the correct response is answer C Looking at the memory map see Figure 3 7 MC68HC705C8 Memory Map you would find that address 42 is a RAM or PROM location whereas all on chip control registers except OPTION at 1 FDF are in the area from 0000 to 001 F 4 Which of the following items requires the most memory bits gt The BCD representation of 125 0001 0010 0101 or 12 bits O B The binary representation of 254 1111 1110 or 8 bits O C The ASCII representation of the letter A 1000001 or 0100 0001 7 or 8 bits O D The binary equivalent of the octal number 75g 111 101 or 6 bits See 2 3 Number Systems and 2 4 Computer Codes 5 many 8 bit memory locations would be needed to hold the ASCII representation of the name FRED O A 16 gt 4 See 2 4 Computer Codes Each ASCII character takes one byte 7 D 2 M68HC05 Applications Guide Rev 4 0 MOTOROLA Review Questi
319. p till a key is found Pointer to last pair in KYTBL Get row col pattern Check for row amp col match key found Point to next pair of entries Loop if more entries Key gone start over L 1 X Get key equiv from table Left end of 156 row Position entry point Get the ASCII key value Display the key Turn on all cols Reads rows in upper 4 till no key pressed Debounce releas Look for another key LDA SOF STA PORTB LDA PORTB AND SFO Mask away cols BEQ ANYK JSR DLY50 Debounce key LDX 30 LDA KYTBL X STA PORTB Drive cols CMP PORTB BE FOUND DECX DECX in KYTBL BPL KYLOOP BRA KEYTRY LDA KYTBI STA KEYVAL Save for now LDA 580 JSR WCTRL LDA KEYVAL JSR WDAT LDA 50 5 LDA PORTB AND SFO Mask away cols BNE TILRLS JSR DLY50 BRA KEYTRY KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK lst 2nd COL ROW ROW ROW ROW KYTBL xo X x gt V FCB FCB FCB FCB EGB FCB FCB FCB FCB FCB FCB FCB FCB FCB FCB FCB To 3 oa 518 528 1 4 548 7 588 lt 14 2 24 5 44 8 84 0 612 7 3 522 76 542 79 82 11 A 21 B 41 C 81 A Keypad Correspondance Table entry of each entry of each pair is Row Col bit pattern pair is ASCII equiv of key Row 1 Col 1 Top Left Row 2 Col 1 Row 3 Col 1
320. programs that exercise the basic parts of the project This procedure will expose any problems in the hardware design and will help you learn details of controlling major external peripherals Begin your project with a very simple program such as that shown in the assembler listing of Figure 2 9 Assembler Listing You can easily modify the program to suit the keypad switches rather than wiring a switch as called for in the Figure 2 9 Assembler Listing example Also you can modify the program to control the beeper rather than the red LED This first small program is meant to be very simple because you want to perform a crude check of the setup as opposed to testing your programming ability The simple example is not likely to have any significant programming problems Next write a short program to check the LCD display It is important to understand the operation of major elements such as this display before attempting a large program Since there are so many possible causes of complete failure in a large program you will have difficulty determining the source of your problems M68HC05 Applications Guide Rev 4 0 202 Applications MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Thermostat Project Details Figure 4 7 is a flowchart of the display checkout program Figure 4 8 is the listing for this small program Two subroutines WCTRL and WDAT were writ
321. puter program called an assembler An assembler is a program that converts a program written in mnemonics into a list of machine codes opcodes that can be used by a CPU An engineer develops a set of instructions for the computer in mnemonic form and then uses an assembler to translate these instructions into opcodes that the CPU can understand We will discuss instructions writing programs and assemblers later in this applications guide but you should understand that people prepare instructions for a computer in mnemonic form and the computer understands only opcodes thus a translation step is required to change the mnemonics to opcodes and this is the function of the assembler Before leaving this discussion of number systems and codes we will look at two additional codes you may have heard about Octal base 8 notation was used for some early computer work but is seldom used today Octal notation uses the numbers 0 through 7 to represent sets of three binary digits in the same way hexadecimal is used to represent sets of four binary digits The octal system had the advantage of using customary number symbols unlike the hexadecimal symbols A through F discussed earlier Two disadvantages caused octal to be abandoned for the hexadecimal notation used today First of all most computers use 4 8 16 or 32 bits per word these words do not break down nicely into sets of three bits Some early computers used 12 bit words which did break
322. r Inc 2 6 4 Assembler 5 50 265 CPU VIEN of PIOQ we oe eens e maru E eae 54 27 uds ena 55 2 7 1 Detailed Operation of CPU Instructions 55 2 7 1 1 Store Accumulator Direct Addressing Mode bf 2 7 1 2 Load Accumulator Immediate Addressing Mode 58 2 7 1 3 Condinonal BIG rire dE REODEXI 59 2 7 1 4 Subroutine Calls and Returns 60 2 7 2 5552 5 63 2 8 68 2 8 1 Serial Communications Interface 5 70 2 8 2 Serial Peripheral Interface 70 2 8 3 16 Bit Timer System 71 2 8 4 Memory Peripherals saa asc eb 72 2 8 5 Other On Chip 5 72 Section 3 MC68HC705C8 Functional Data al Jb PET PER DOE 13 V AME Mod 76 Bo x rd 77 3 3 1 Hardware 77 3 3 2 Software de 78 3 3 3 General Description pierrette CR 78 24 Pins GCBDDE HD ui i dua do dard bor d ede 80 3 4 1 Piw FUNCIONS METIRI 81 3 4 1 1 Yop iio 5555545 81 3 4
323. r a software variable 43 If you discovered an incorrect value in memory location as you were starting volume production which of the following memory types would require the longest time to correct the error O A RAM RAM values can be changed in a single bus cycle or about 1 us gt B ROM ROM changes require several weeks because new parts must be manufactured O C EPROM EPROM takes several minutes of exposure to UV light to erase O D EEPROM EEPROM can be changed in tens of milliseconds See 1 5 Computer Systems Description and 4 3 Hardware Development Methods 44 microcontroller includes a central processor unit CPU O B memory I O devices gt D all of the above see 1 3 Definitions 45 Acentral processor unit CPU gt A is part of a microcontroller MCU see 1 3 Definitions O B is acomplete computer system contains memory and I O devices O D contains an MCU M68HC05 Applications Guide Rev 4 0 MOTOROLA Review Questions 335 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions 46 47 48 49 A memory is said to be volatile if it forgets its contents when power is removed for long periods of time Which of the following memory types is volatile O A ROM gt B RAM O C EPROM O D EEPROM See 1 5 Computer Systems Description and 4 3 Hardware Development Methods An EP
324. r engineers who are familiar with MCUs from some other manufacturer The MCU block in Figure 1 3 Thermostat Project Block Diagram can be expanded as shown in Figure 2 1 to show the functional blocks within the MCU The CPU block is the central element of a digital binary computer much like mainframe computers used in business except that it is much smaller The goal of this section is to study the internal operation of this CPU and how it interacts with the other functional blocks within the MCU Although this discussion is based on a relatively simple CPU the principles apply to even the most powerful mainframe computers The CPU is a system of simple logic elements and buses that can sequentially interpret and execute a finite set of instructions Starting from a specific address in memory after reset the CPU mindlessly fetches and executes one simple instruction after another Each instruction is composed of several even simpler steps The small substeps comprising each instruction are determined by the wiring within the CPU The transistors logic gates and buses which comprise the CPU are called hardware The instructions the CPU follows to accomplish an application task are determined by an end user or design engineer and are called a software program Before we can get into the discussion of the internal operations of the CPU some basic concepts must be understood The following paragraphs discuss numbering systems and special codes used
325. receive clock is 16 times higher in frequency than the actual baud rate Table 3 11 Transmit Baud Rate Output SCR Bits Divided Representative Highest Prescaler Baud Rate Output 2 1 0 By 131 072 kHz 32 768 kHz 76 80 kHz 19 20 kHz 9600 Hz 0 0 0 1 131 072 2 32 768kHz 76 80 kHz 19 20 2 9600 2 0 0 1 2 65 536 2 16 384 38 40 kHz 9600 2 4800 Hz 0 1 0 4 32 768 kHz 8 192 kHz 19 20 kHz 4800 Hz 2400 Hz 0 1 1 8 16 384 kHz 4 096 kHz 9600 Hz 2400 Hz 1200 Hz 1 0 0 16 8 192 kHz 2 048 kHz 4800 Hz 1200 Hz 600 Hz 1 0 1 32 4 096 kHz 1 024 kHz 2400 Hz 600 Hz 300 Hz 1 1 0 64 2 048 kHz 512 Hz 1200 Hz 300 Hz 150 Hz 1 1 1 128 1 024 kHz 256 Hz 600 Hz 150 Hz 75 Hz M68HCO05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 143 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data 3 11 3 2 Serial Communications Control Register One SCCH 1 The serial communications control register one SCCR1 shown in Figure 3 25 includes three bits associated with the optional 9 bit data format The WAKE bit is used to select one of two methods of receiver wakeup Normal setup for bit M is 0 for 8 bit words The other register bits are not used in most systems In a typical system this register would be written to 00 during initialization BIT 7 6 5 4 3 2 1 0 T 0 0 0 0 RESET CONDITION
326. reescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data 3 11 5 Hardware Procedures Some simple hardware setup is required A universal standard RS232 cable is used to interconnect the SCI to a CRT terminal or the PC The user would usually have to provide an external level shifter buffer MC145406 to convert the RS232 typically 12 volts to the 0 5 volt logic levels used by the MC68HC705C8 3 11 6 Software Procedures The following paragraphs and flowcharts discuss software procedures These flowcharts illustrate how straightforward normal SCI operations are 3 11 6 1 Initialization Procedure The following list reflects the initialization procedure 1 Write to BAUD register SCP1 SCP0 SCR2 SCRO to set baud rate 2 Write to SCCR1 R8 T8 M WAKE to set character length and choose wakeup method 3 Write to SCCR2 TIE TCIE RIE RE RWU 5 to able desired interrupt sources To turn on the transmitter and re ceiver RWU and SBK would be written to zero during initialization The following is a reference list of interrupt enable control bits versus the interrupt source s they enable Enable Flags Interrupt Source Names TIE TDRE Transmit data register empty TCIE TC Transmit complete RIE RDRF OR Receive data register full overrun ILIE IDLE Idle line detect M68HC05 Applications Guide Rev 4 0 148 MC68HC705C8 Functional Data MOTOROLA For More Information On This Pr
327. rementing SP to 00FF 19 and by reading 05 from 00FF The address recovered from the stack replaces the value in the PC 20 The CPU now reads the STA 02 instruction from location 0105 Program flow has returned to the main program sequence where it left off when the subroutine was called The STA direct addressing mode instruction writes the accumulator value to the direct address 02 0002 which is port C on the MC68HC705C8 We can see from the worksheet that the current value in the accumulator is 00 therefore all eight pins of port C would be driven low provided they are configured as outputs at this time Since the original worksheet did not have a place marked for recording the value of port C you would make a place and write 00 there 21 M68HCO05 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation 67 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation For a larger program the worksheet would have many more crossed out values by the time you are done Playing computer on a worksheet like this is a good learning exercise but as a programmer gains experience the process would be simplified One of the first simplifications would be to quit keeping track of the PC because you learn to trust the CPU to take care of this for you Another simplification of the worksheet is to stop keeping track of the condition codes When
328. ring to are like the mailboxes in alarge apartment building This is a good analogy but needs a little refinement if it is to be used to explain the inner workings of a CPU We will confine our discussion to an 8 bit CPU so that we can be very specific M68HC05 Applications Guide Rev 4 0 36 Microcontroller Operation MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation Computer Codes In an 8 bit CPU each pigeon hole or mailbox can be thought of as containing a set of eight on off switches eight bits of data are called a byte of data Unlike a pigeon hole you cannot fit more information in by writing smaller and there is no such thing as an empty pigeon hole though the contents of a memory location can be unknown or undefined at a given time The switches would be in a row where each switch would represent a single binary digit A binary one corresponds to the switch being on and a binary zero corresponds to the switch being off Each pigeon hole memory location has a unique address so that information can be stored and reliably retrieved 2 4 2 Computer Architecture Motorola M68HC05 and M68HC11 8 bit MCUs have a specific organization which is called a Von Neumann architecture after an American mathematician of the same name In this architecture a CPU and a memory array are interconnected by an address bus and a data bus The address bus
329. rovided the I bit in the condition code register is clear and the enable bit in the serial peripheral control register location 0A is enabled The general sequence for clearing an interrupt is a software sequence of accessing M68HC05 Applications Guide Rev 4 0 132 68 705 8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Microcontroller Input Output the status register while the flag is set followed by a read or write of the associated control register 3 10 Microcontroller Input Output NOTE 3 10 1 Parallel I O Since inputs to and outputs from the MCU are usually digital 0 to 5 Vdc at low power interface logic is often needed to couple the MCU to external devices Interface logic can operate in parallel or serial form Parallel interfaces allow I O data transfer eight bits at a time to parallel ports on the MCU Serial interfaces transfer I O data one bit at a time through a serial communications interface SCI or serial peripheral interface SPI that are parts of the MCU Data transfers between the MCU and external logic are controlled by the MCU Tie all unused inputs I O ports to an appropriate logic level either Vpp or Voss The MC68HC705C8 MCU contains 31 general purpose parallel I O pins arranged in four ports Ports A B and C are 8 bit ports in which the direction of each pin
330. rsions of bit manipulation instructions generate two machine code bytes one for the opcode and one for the relative offset Because it is desirable to branch in either direction the offset byte is a signed twos complement offset with a range of 127 to 128 bytes with respect to the address of the instruction immediately following the branch instruction If the branch condition is true the contents of the 8 bit signed byte following the opcode offset are added to the contents of the program counter to form the effective branch address otherwise control proceeds to the instruction immediately following the branch instruction M68HC05 Applications Guide Rev 4 0 MOTOROLA 68 705 8 Functional Data For More Information On This Product Go to www freescale com 113 Freescale Semiconductor Inc 8 705 8 Functional Data A programmer specifies the destination of a branch as an absolute address or label which refers to an absolute address The Motorola assembler calculates the 8 bit signed relative offset which is placed after the branch opcode in memory Example Program Listing 0200 27 DEST Branch to DEST if Z 1 branch if equal or zero Execution Sequence 0200 27 1 0201 2 3 1 CPU reads opcode 27 branch if Z 1 relative addressing mode 2 CPU reads the offset rr 3 CPU internally tests the state of the
331. ry STA Store Index Register in Memory STX Subtract SUB The direct addressing mode is similar to the extended addressing mode except the upper byte of the operand address is assumed to be 00 Thus only the lower byte of the operand address needs to be included in the instruction Direct addressing allows you to efficiently address the lowest 256 bytes in memory This area of memory is called the direct page and includes on chip RAM and registers Direct addressing is efficient in both memory and time Direct addressing mode instructions are usually two bytes one for the opcode and one for the low order byte of the operand address M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data For More Information On This Product Go to www freescale com 105 Freescale Semiconductor Inc 8 705 8 Functional Data Example Program Listing 0200 b6 50 LDA 50 Load accumulator from direct address Execution Sequence 0200 5 6 1 0201 50 2 and 3 Explanation 1 CPU reads opcode B6 load accumulator using direct addressing mode 2 CPU then reads 50 from location 0201 This 50 is interpreted as the low order half of an address In direct addressing mode the high order half of the address is assumed to be 00 3 CPU internally appends 00 to the 50 read in the second cycle to form the complete address 0050 The CPU then reads whatever value is contained in the l
332. s In the indexed addressing mode the effective address is variable and depends upon two factors 1 the current contents of the index X register and 2 the offset contained in the byte s following the opcode Three types of indexed addressing exist in the MCU no offset 8 bit offset and 16 bit offset A good assembler should use the indexed addressing mode that requires the least number of bytes to express the offset 3 7 5 1 Indexed No Offset In the indexed no offset addressing mode the effective address of the instruction is contained in the 8 bit index register Thus this addressing mode can access the first 256 memory locations These instructions are only one byte Example Program Listing 0200 6 LDA x Load accumulator from location pointed to by index reg no offset Execution Sequence 0200 F6 1 2 3 Explanation 1 CPU reads opcode F6 load accumulator using indexed no offset addressing mode 2 CPU forms a complete address by adding 0000 to the contents of the index register 3 CPU then reads the contents of the addressed location into the accumulator M68HC05 Applications Guide Rev 4 0 108 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Addressing Modes Instruction Add with Carry Add Logical AND Arithmetic Shift Left Arithmetic Shift Right Bit Test Me
333. s Cycles Code and Cycles SWI INH 83 10 M68HC05 Applications Guide Rev 4 0 298 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc Instruction Set Details M68HC05 Instruction Set Transfer Accumulator to Index Register X ACCA TAX Loads the index register with the contents of the accumulator The contents of the accumulator are unchanged H 2 1 1 1 None affected Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles TAX INH 97 2 M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details For More Information On This Product Go to www freescale com 299 Freescale Semiconductor Inc Instruction Set Details TST Test for Negative or Zero TST Operation 00 00 00 Description Sets the condition codes N and Z according to the contents of ACCA X or M The contents of ACCA X and M are not altered Condition Codes and Boolean 7 Formulae 1 1 1 7 Set if the MSB of the contents of X is set cleared oth erwise Z 7 6 5 4 3 2 1 0 Set if th
334. s circuit When the CPU reads the address of the input port shown in Figure 2 3 b the READ signal is activated which enables the multiplexer at 3 The multiplexer couples the buffered data from the pin onto the data bus line A write to this address would have no meaning When the CPU stores a value to the address that corresponds to the output port in Figure 2 3 c the WRITE signal is activated to latch the data from the data bus line into the flip flop 4 The output of this latch which is buffered by the buffer driver at 5 appears as a digital level on the output pin When the CPU reads the address of this output port the READ signal is activated which enables the multiplexer at 6 This multiplexer couples the data from the output of the flip flop onto the data bus line M68HC05 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation 41 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation READ DATA BIT n n 0 1 0R 7 WRITE a RAM Bit READ 3 DATA BIT n DIGITAL n 0 1 0R 7 lt INPUT BUFFER b Input Port Bit READ 6 DATA n 5 DIGITAL n 0 1 0R 7 LR OUTPUT BUFFER DRIVER c Output Port with Readback Figure 2 3 Memory and I O Circuitry 2 4 5 Memory Maps Since there are several thousand memory locations in the MCU system it is important to
335. s lost or runs too slow An illegal opcode detection circuit provides a non maskable interrupt if an illegal opcode is detected M68HC05 Applications Guide Rev 4 0 78 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data MCU Description EPROM PROGRAMMING CONTROL PAT PA6 5 4 PA2 1 0 PROGRAM REGISTER EPROM OTPROM 7744 BYTES 144 BYTES CONFIGURABLE lt 2 0 lt PB7 PB6 5 4 PB2 PBO OPTION REGISTER RAM 176 BYTES UP TO 304 BYTES DATA DIRECTION B BOOT ROM 240 BYTES 9 PC6 5 PCS RESET ARITHMETIC LOGIC UNIT CONTROL RG ALU lt PC2 M68HCO5 CPU FE T PCO U REGISTERS ACCUMULATOR INDEX REGISTER im 010101111 STACK POINTER 01010 PROGRAM COUNTER WE CONDITION CODES TTITITHTTTN PD4 PD3 osc1 OSCILLATOR ae PDI 0502 lt PDO BAUD RATE COP WATCHDOG GENERATOR AND CLOCK MONITOR TCMP TIMER SYSTEM TCAP Figure 3 1 MC68HC705C8 Microcontroller Block Diagram M68HCO5 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 79 For More Informatio
336. s port is connected to a normally opened switch and a pulldown resistor When the switch is pressed closed a logic one is applied to the port pin If the LDA PCRTB instruction is executed when the switch is opened the N condition code bit will be cleared Conversely if the LDA PORTB instruction is executed when the switch is closed the N condition code bit will be set M68HCO05 Applications Guide Rev 4 0 MOTOROLA Microcontroller Operation 59 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation 00 8 01 fd 00ab 00 c3 The second line in the listing BPL TOP is read branch if plus to TOP In response to this instruction the CPU either branches back to the first line of this program or falls to the third line of the program depending on the condition of the N condition code bit If the N condition code bit is clear the CPU branches to the first line of the program This corresponds to the CPU interpreting the value previously read from port B as a positive value hence the instruction name branch if plus Tricks such as that just described are not the only way to read and respond to I O conditions The following two lines of code would accomplish the same effect as the three lines which used the N bit trick TOP BRCLR 7 PORTB TOP Loop till sw closed JSR DLY50 Delay about 50 ms to debounce The first line of this sequence is read
337. sequences and upon reset In the majority of all systems only the SPIF status bit is important BIT 7 6 5 4 3 2 1 BIT 0 Cr wet sm sw 0 0 0 RESET CONDITION MODE FAULT WRITE COLLISION SPI TRANSFER COMPLETE Figure 3 38 Serial Peripheral Status Register The bits in this register have the following functions SPIF When set to one the serial peripheral data transfer flag bit notifies the user that a data transfer between the MCU and an external peripheral device has been completed The transfer of data is initiated by the master device writing to its serial peripheral data register SPIF is automatically cleared by reading SPSR with SPIF set followed by an access of the SPI data register WCOL The write collision status bit notifies the user that an attempt was made to write to the serial peripheral data register while a data transfer with an external peripheral device was in progress The transfer continues uninterrupted and the write will be unsuccessful MODF This flag is set if the SS signal goes to its active low level while the SPI is configured as a master MSTR 1 In normal systems this would never be possible M68HC05 Applications Guide Rev 4 0 160 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data SPI Application Exampl
338. sing Machine Code HCMOS Modes Machine Forms Mode Opcode Cycles Code and Cycles BMC rel REL 2C rr 3 The following table is a summary of all branch instructions Test Boolean Mnemonic Opcode Complementary Branch Comment r gt m C Z 0 BHI 22 BLS 23 Unsigned 0 BHS BCC 24 r lt m BLO BCS 25 Unsigned r m Z 1 BEQ 27 26 Unsigned r lt m C Z 1 BLS 23 r gt m BHI 22 Unsigned r lt m 1 BLO BCS 25 gt 5 24 Unsigned Carry 1 BCS 25 No Carry BCC 24 Simple r 0 2 1 27 r 0 BNE 26 Simple Negative N 1 BMI 2B Plus BPL 2A Simple Mask 1 5 2D Mask 0 BMC 2C Simple Half Carry H 1 BHCS 29 No Half Carry BHCC 28 Simple IRQ Pin High BIH 2 IRQ Low BIL 2E Simple Always BRA 20 Never BRN 21 Unconditional r register ACCA or X m memory operand M68HC05 Applications Guide Rev 4 0 256 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com Operation Description Condition Codes and Boolean Freescale Semiconductor Inc lt PC 0002 Rel Branch if Minus if N 1 Instruction Set Details M68HOC05 Instruction Set BMI Tests the state of the N bit in the CCR and causes a branch if N is set See BRA instruction for further details of the execution of the branch H 2
339. ssemblers use the same syntax rules and special characters refer to the documentation for the particular assembler that will be used Prefix Definition None Decimal Hexadecimal Octal Binary Single ASCII Character For each addressing mode an example instruction is explained in detail These explanations describe what happens in the CPU during each processor clock cycle of the instruction Numbers in square brackets refer to a specific CPU clock cycle M68HCO05 Applications Guide Rev 4 0 100 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Addressing Modes 3 7 1 Inherent Addressing Mode In inherent addressing mode all information required for the operation is already inherently known to the CPU and no external operand from memory or from the program is needed The operands if any are only the index register and accumulator These are always one byte instructions Example Program Listing 0200 4c INCA Increment accumulator Execution Sequence 0200 4c pre oie T3 Explanation 1 CPU reads opcode 4C increment accumulator 2 and 3 reads accumulator value adds one to it stores the new value in the accumulator and adjusts condition code flag bits as necessary M68HCO05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 101 For More Inform
340. t Go to www freescale com Freescale Semiconductor Inc 8 705 8 Functional Data addressing instructions access all data bytes in most applications Extended addressing uses three byte instructions to reach data anywhere in memory space The various addressing modes make it possible to locate data tables code conversion tables and scaling tables anywhere in the memory space Short indexed accesses are single byte instructions whereas the longest instructions three bytes permit accessing tables anywhere in memory A general description and examples of the various modes of addressing are provided in the following paragraphs The term effective address EA is used to indicate the memory address where the argument for an instruction is fetched or stored More details on addressing modes and a description of each instruction is available in Appendix A Instruction Set Details The information provided in the program assembly examples uses several symbols to identify the various types of numbers that occur in a program These symbols include 1 A blank or no symbol indicates a decimal number 2 A immediately preceding a number indicates it is a hexadecimal number e g 24 is 24 in hexadecimal or the equivalent of 36 in decimal As indicates immediate operand and the number is found in the location following the opcode A variety of symbols and expressions can be used following the character sign Since not all a
341. t Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation CPU Operation stack pointer SP points to address 00FF when the CPU encounters the JSR instruction at location 0102 0100 02 LDA 502 Load an immediate value 0102 cd 02 00 JSR SUBBY Go do a subroutine 0105 b7 02 STA 02 Store accumulator to port C 02 0 0 4a SUBBY DECA Decrement accumulator 0201 26 fd BNE SUBBY Loop till accumulator 0 0203 81 RTS Return from subroutine Refer to Figure 2 11 during the following discussion We will begin the explanation with the CPU executing the instruction LDA 02 at address 0100 The left side of the figure shows the normal program flow composed of TOP LIDA 20 JSR SUBBY and STA 02 in that order in consecutive memory locations The right half of the figure shows subroutine instructions SUBBY DECA BNE SUBBY and RTS Each number in square brackets indicates a cycle of the internal processor clock The cycle numbers will be used as references in the following explanation of this figure PE 0100 A6 1 15 9 4A 0200 SUBBY DECA TOP LDA 02 16 10 0101 02 2 17 11 0102 3 18 12 26 0201 BNE SUBBY JSR SUBBY 0103 02 4 19 13 FD 0202 _ 20 _ 0104 00 5 gt 1 81 0203 RTS 6 22 7 23 8 2
342. t 5 1A dd 5 BSET 6 opr DIR bit 6 1 dd 5 BSET 7 opr DIR bit 7 1E dd 5 M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details 265 For More Information On This Product Go to www freescale com BSR Operation Description Condition Codes Freescale Semiconductor Inc Instruction Set Details PC lt PC 0002 J PCL SP J PCL SP PC lt PC Rel Branch to Subroutine BSR Advance PC to return address lt SP 0001 Push low order return onto stack lt SP 0001 Push high order return onto stack Load PC with start address of requested subroutine The program counter is incremented by two from the opcode address i e so it points to the opcode of the next instruction which will be the return address The least significant byte of the contents of the program counter low order return address is pushed onto the stack The stack pointer is then decremented by one The most significant byte of the contents of the program counter high order return address is pushed onto the stack The stack pointer is then decremented by one A branch then occurs to the location specified by the branch offset See BRA instruction for further details of the execution of the branch and Boolean H 7 1 1 1 m None affected Source Forms Addressing Source Addressing Machine Code HCMOS Modes M
343. t addressing can be used for ROM RAM or I O This is a two byte instruction with the offset contained in the byte following the opcode The content of the index register X is not changed The offset byte supplied in the instruction is an unsigned 8 bit integer Example Program Listing 0200 e6 05 LDA 5 x Load accumulator from location pointed to by index reg X 505 Execution Sequence 0200 E6 1 0201 05 2 3 4 Explanation 1 CPU reads opcode E6 load accumulator using indexed 8 bit offset addressing mode 2 CPU then reads 05 from location 0201 This 05 is interpreted as the low order half of a base address The high order half of the base address is assumed to be 00 3 CPU will add the value in the index register to the base address 0005 The results of this addition is the address that the CPU will use in the load accumulator operation 4 The CPU will then read the value from this address and load this value into the accumulator M68HCO05 Applications Guide Rev 4 0 110 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Addressing Modes Instruction Add with Carry Add Logical AND Arithmetic Shift Left Arithmetic Shift Right Bit Test Memory with Accumulator Clear Compare Accumulator with Memory Complement Compare Index Register with Memory Decrement Exclusive OR M
344. t common use of this peripheral is to implement an RS 232 interface to a host computer system such as a personal computer The SCI system can be used to communicate over relatively long distances In normal applications the CPU simply writes data to a parallel data register to send a formatted serial character The SCI peripheral system takes care of all the details of transforming the data into the proper serial format including the addition of start and stop bits required to meet standards The transmitter even allows up to two characters to be queued up for transmission thus allowing the CPU more time to prepare additional characters The receiver portion of the SCI automatically detects the start of a character and intelligently samples the incoming serial data to assure correct reception even in noisy applications All activity related to receiving serial data and converting it to parallel data is performed within the SCI peripheral logic with no intervention of the CPU After a character is received the CPU simply reads a data byte from a receive data register A number of options are offered to allow various data rates baud rates alternate character formats and an automatic standby wakeup feature You can choose between software polling or interrupts for detection of SCI status 2 8 2 Serial Peripheral Interface SPI system on the MC68HC705C8 is separate from the SCI system and is used primarily for communica
345. t digit of a decimal integer is the ones place the digit to its left is the tens digit and so on In binary base 2 numbers the weight of each digit is two times as great as the digit immediately to its right The rightmost digit of the binary integer is the ones digit the next digit to the left is the twos digit next is the fours digit then the eights digit and so on Although computers are quite comfortable working with binary numbers of 8 16 or even 32 binary digits humans find it very inconvenient to work with so many digits at a time The base 16 hexadecimal numbering system offers a practical compromise One hexadecimal digit can exactly represent four binary digits thus an 8 bit binary number can be expressed by two hexadecimal digits The correspondence between a hexadecimal digit and the four binary digits it represents is simple enough that humans who work with computers easily learn to mentally translate between the two In hexadecimal base 16 numbers the weight of each digit is 16 times as great as the digit immediately to its right The rightmost digit of a hexadecimal integer is the ones place the digit to its left is the sixteens digit and so on Table 2 1 demonstrates the relationship between the decimal binary and hexadecimal representations of values These three different numbering systems are just different ways to represent the same physical quantities The letters A through F are used to represent the
346. tch 0 1 Data is written into the output data latch and output to the pin 1 0 The state of the I O pin is read 1 1 The I O pin is in output mode The output data latch is read 1 RW is an internal signal M68HCO05 Applications Guide Rev 4 0 MC68HC705C8 Functional Data 135 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8 705 8 Functional Data 3 10 2 Serial I O Port D see Figure 3 20 is a 7 bit fixed direction input port The SPI and SCI systems take control of port D pins when these systems are enabled During power on reset or external reset all seven pins PD5 PDO PD7 are configured as input ports because all special function output drivers are disabled For example with the SCI system enabled RE TE 1 PDO and PD1 inputs will read zero With the SPI system disabled SPE 0 PD5 PD2 will read the state of the pin at the time of the read operation The SCI function uses two of the pins 1 for its receive data input RDI and transmit data output TDO the SPI function uses four of the pins PD5 PD2 for its serial data input output MISO MOSI system clock SCK and slave select SS respectively 503 PORTD PD7 PAS USED 55 5 mosi miso TDO CN NAMES REF SPI SCI ALTERNATE USE REF Figure 3 20 Port D Fixed Input Port 3 11 Serial Communica
347. tems program is a series of instructions for the MCU The program gives the MCU alternatives to transact depending on what it learns as the result of executing previous instructions For instance to determine if a thermostat should operate the compressor or the heater we might program it as follows 1 Read the existing temperature 2 Read the desired temperature setting 3 Compare these two readings 4 If existing is less than desired operate heater 5 If existing is more than desired operate compressor To write a program you can draw a flowchart to show the decision process that must be performed to accomplish a specific task Flowcharts are not always necessary sometimes a list of steps will do depending upon the application complexity M68HCO5 Applications Guide Rev 4 0 MOTOROLA Applications 191 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications In general programming requires planning and developing rules algorithms flow charts Programs evolve by repeating the following steps several times 1 Generate the source the program mnemonic form A development station usually a personal computer is used to generate a text file This text file the source of the data to be run by the MCU is called the source program This text file is for the convenience of the programmer since the MCU understands only 8 bit bytes of enc
348. ten to simplify operations with the LCD display These subroutines will eventually become part of the final application program When this thermostat project was developed the programs were not correct at first because the data sheet for the LCD display module was imprecise The purpose of the small checkout programs is to work out these minor problems before beginning the large application program Application example programs shown in this applications guide can be tried in an MC68HC705C8 in one of two ways depending upon their size For small programs less than 176 bytes you can download the example program to RAM in the area 0051 00 and execute it without programming any EPROM so you don t have to erase EPROM to try another To use this method you must ORG your program at 0050 and the first byte must be the size of your example The following procedure will provide the needed size byte 1 Replace your ORG statement with the following two lines ORG 50 START FCB END START 2 After the last line in your program put END EQU 3 Assemble the example program and make sure it ends at or before 00FF M68HC05 Applications Guide Rev 4 0 MOTOROLA Applications 203 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications NOTE TRYLCD INITIALIZE MCU HARDWARE PORTS AND DDR REGISTERS WRITE CONTROL WORDS TO INITIALIZE LCD MODULE
349. ters BAUD SCCR1 SCCR2 SCSR and SCDAT and two external pins and RDI When the SCI receiver and or transmitter is enabled the SCI logic takes control of the pin buffers for the associated port D pin s When the SCI is disabled the TDO and RDI pins act as general purpose inputs The main function of each of these registers will be discussed Normally the SCCR1 SCCR2 and BAUD registers would be written once to initialize and then not used again An example of the software programming procedure is shown later in this section 3 11 3 1 Baud Rate Register BAUD The BAUD register see Figure 3 23 is used to select the baud rate for the SCI system Both the transmitter and receiver use the same data format and baud rate which is derived from the MCU bus rate clock The 5 1 5 bits function as a prescaler for the SCR2 SCRO bits Together these five bits provide multiple baud rate combinations for a given crystal frequency BIT 7 6 4 3 2 1 BIT 0 so 0 0 0 0 0 0 0 0 RESET CONDITION N J L SCI RATE SELECT SCI PRESCALER RATE SELECT DIVIDE PRESCALER OUTPUT DIVIDE INTERNAL BY 1 2 4 8 128 PROCESSOR CLOCK BY 1 3 4 OR 13 Figure 3 23 Baud Rate Register M68HCO5 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 141 For More Information On This Product Go to www freescale com Frees
350. that reflect the results of arithmetic and other operations of the CPU The five flags are half carry H negative N zero Z overflow V and carry borrow C CONDITION CODE REGISTER LEGE 22 26 CARRY ZERO NEGATIVE INTERRUPT MASK HALF CARRY FROM BIT 3 Figure 3 11 Condition Code Register CCR Half Carry Bit H The half carry flag is used for binary coded decimal BCD arithmetic operations and is affected by the ADD or ADC addition instructions The H bit is set to a one when a carry occurs between bits 3 and 4 M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 91 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8 705 8 Functional Data Interrupt Mask Bit The interrupt mask bit disables all maskable interrupt sources when the bit is set Clearing this bit enables the interrupts When any interrupt occurs the bit is automatically set after the registers are stacked but before the interrupt vector is fetched If an external interrupt occurs while the bit is set the interrupt is latched and processed after the bit is cleared therefore no interrupts from the IRQ pin are lost because of the bit being set After an interrupt has been serviced a return from interrupt RTI instruction causes the registers to be restored to their previous values Normally the bit would be z
351. the programmer sits at a computer terminal and develops sets of computer instructions 4 3 Hardware Development Methods When a project has been selected determine what hardware will be required for the final design input and output devices and power supply and what hardware can be used to make the prototype substitutions such as potentiometers for temperature sensors Two approaches can be used to develop a hardware circuit breadboarding for system based on M68HC05 MCU You can use an M68HC05 PGMR board or you can wire a complete circuit on another board with a socket for the MCU The PGMR board approach is the fastest since the basic wiring to the MCU is already done The complete circuit with a socket for the MCU has the advantage of not having to worry about interference between PGMR board functions and application requirements Since the PGMR board is also used to program information into the EPROM in the MCU there are a few areas where some conflict may occur between the planned application and components on the PGMR board The areas are small and usually easy to avoid For example the port D pins of the MCU are connected to switches on the PGMR board M68HC05 Applications Guide Rev 4 0 MOTOROLA Applications 189 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications To use these pins you would turn off the switches so that there is no conflict w
352. tion On This Product Go to www freescale com Freescale Semiconductor Inc Applications 4 4 2 Third Party Software Many third party vendors sell assemblers to translate mnemonic text files into machine readable files These assemblers are similar to the free assembler available on the Freeware BBS except that the third party assemblers offer additional features One common feature is the ability to use macros Macros are sets of instructions used repeatedly in a program A set of instructions can be typed into the program declared as a macro and be given a name When this set of instructions is needed again you would type the name of the macro where an instruction mnemonic would normally go The assembler recognizes the macro name and inserts the previously defined set of instructions at that point into the machine readable object file Macros improve programmer productivity and often improve the readability of the assembly language listing A simulator is a software program that runs on a personal computer or other computer system The simulator emulates the behavior of an MCU in the same way you would play computer see 2 7 2 Playing Computer Although a simulator does not operate as fast as the actual MCU it does operate much faster than you could play computer In a typical simulator the computer screen will display windows showing current and recent contents of memory and registers as well as the condition of I O pins and
353. tion link is the RS 232 or RS 422 serial port on a computer This standard is so universal that M68HC05 Applications Guide Rev 4 0 68 Microcontroller Operation MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation On Chip Peripherals almost every personal and mainframe computer made anywhere in the world has at least one such port Before the MCU was developed a computer designer had to use a separate UART integrated circuit to include this serial interface function in a computer Often a number of other miscellaneous logic gates were also needed to interface the UART to the CPU buses Since the level of integration allows thousands of logic gates to be included in a single MCU integrated circuit it is practical to put several peripherals including this UART function on the same chip along with the CPU and memories The on chip serial communications interface SCI in the MC68HC705C8 is a UART type peripheral It is important for the MCU manufacturer to select peripheral functions that will be useful to many potential users for inclusion on the MCU chip This pressure to make on chip peripherals satisfy the requirements of as many customers as possible causes the need for user selectable options to modify the operation of the on chip peripherals The MC68HC705C8 has control registers which allow a user to select which parallel I O pins will be i
354. tion set displayed by instruction type M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 115 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data 2 5 9 6 9 5 6 p usn eunnouqng duin 5 od od 99 od E E 21 1 v 6 6 2 6 84 v 99 5 Sg SV lig 1591 19 YM 6 6 v 2 3 53 v 5 9 r4 eg V XdO X oneuiuuy YM S La 5 L ld 6 LO LV 6 6 8 8 6 8 v 6 80 5 8 8 VAS a 2 8 HO 6 5 v vJ Vd v vo 5 vd VV VHO V HO S 6 vd va L vd 5 vO vd 0 MOOG V 6 v 2 2 eV 98S Howay penans 6 6 od v 2 6 L 0 6 09 6 2 og ov ans Kowa eqns V Aue 6 6 6d v 2 63 64 v 69 r4 68 r4 r4 6v OdV pue S v 5 5 go 5 2 av dav 0 9 5 6 2
355. tions Interface SCI SCI is one of two independent serial I O subsystems in the MC68HC705C8 The other serial I O system called SPI provides for high speed synchronous serial communication to peripherals or other MCUs The SCI is a full duplex UART type asynchronous system that can be used for communication between the MCU and a CRT terminal or a personal computer or several widely distributed MCUs can use their SCI subsystems to form a serial communications network The SCI uses standard nonreturn to zero NRZ format one start bit eight or nine data bits and a stop bit The most common data format is eight bits An on chip baud rate generator derives standard baud rate M68HC05 Applications Guide Rev 4 0 136 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Serial Communications Interface SCI frequencies from the MCU oscillator The SCI transmitter and receiver are functionally independent but use the same data format and baud rate In this applications guide baud rate and bit rate are used synonymously SCI Features Two Wire Serial Interface e Standard NRZ mark space Format Full Duplex Operation independent transmit and receive Software Programmable for One of 32 Different Baud Rates Software Selectable Word Length 8 or 9 bit words Separate Transmitter and Receiver En
356. tions with standard peripheral logic chips on the same circuit board as the MCU A few examples of the chips that can use SPI are serial to parallel and parallel to serial shift registers A D peripherals LCD peripherals and many others The SPI system works like a distributed 16 bit shift register in which half the shifter is in the MCU SPI and the other half is in the peripheral When the MCU initiates a transfer this distributed shifter is rotated eight M68HC05 Applications Guide Rev 4 0 70 Microcontroller Operation MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Microcontroller Operation On Chip Peripherals bit positions so that the data in the master MCU is effectively exchanged with the data in the peripheral slave In some cases the loop is incomplete and data is transferred only from the MCU to the peripheral or from the peripheral to the MCU An SPI system typically consists of amaster MCU and one or more slave peripherals Other configurations such as two MCUs or multiple master systems are possible but less common The SPI system includes options to select shift rate master or slave mode clock polarity and phase to allow compatibility with most synchronous serial peripheral devices from many manufacturers 2 8 3 16 Bit Timer System The MC68HC705C8 MCU includes a 16 bit timer system used to measure time and to produce signals of specific period or
357. to www freescale com Freescale Semiconductor Inc Review Questions 28 In the following instruction sequence a value is read into the accumulator From what address is this value being read It may be helpful to look at the machine code as well as the mnemonic instructions 0003 SAM EQU 03 SAM equal an 8 bit value 1400 LARRY EQU 1400 LARRY equal a 16 bit value 0100 ORG 100 Set program starting point 0100 ae 02 TOP LDX 02 Initialize index register 0102 e6 03 LDA SAM X Read value into A O A 0002 O B 0003 gt C 0005 see 3 7 5 2 Indexed 8 Bit Offset O D 0105 Don t forget to add the current value of X 02 to the value SAM 03 29 In the following instruction sequence a value is read into the accumulator From what address is this value being read It may be helpful to look at the machine code as well as the mnemonic instructions 0003 SAM EQU 03 SAM equal an 8 bit value 1400 LARRY EQU 1400 LARRY equal a 16 bit value 0100 ORG 100 Set program starting point 0100 ae 02 TOP LDX 502 Initialize index register 0102 14 00 LDA LARRY X Read value into A O A 0002 O B 1400 gt C 1402 see 3 7 5 3 Indexed 16 Bit Offset O D 1600 Don t forget to add the current value of X 02 to the value LARRY 1400 M68HC05 Applications Guide Rev 4 0 328 Review Questions MOTOROLA For More Information On This Product Go to www freescale com Freesca
358. to a logic low on the IRQ or RESET pins will cause the processor to resume normal processing The wait mode power consumption depends on how many systems are active The power consumption will be greatest when all the systems timer TCMP SCI and SPI are active The power consumption will be least when the SCI and SPI systems are disabled timer operation cannot be disabled in the wait mode If a nonreset exit from the wait mode is performed e g timer overflow interrupt exit the state of the remaining systems will be unchanged If a reset exit from the wait mode is performed all systems revert to the disabled reset state M68HC05 Applications Guide Rev 4 0 MOTOROLA MC68HC705C8 Functional Data 181 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data 3 16 OTPROM EPROM Programming 3 16 1 Erasing 3 16 2 Programming The OTPROM or EPROM programming technique is used to load a user program into the MC68HC705C8 MCU OTPROM or EPROM This type of programming is accomplished via a bootstrap mode of operation MC68HC705C8 EPROM MCUs are erased by exposure to a high intensity ultraviolet UV light with a wavelength of 2537 angstrom The recommended dose UV intensity x exposure time is 15 Ws cm UV lamps should be used without shortwave filters and the EPROM MCU should be positioned about one inch from the UV lamps MC68HC705C8 one time pr
359. to the accumulator From what address is this value being read It may be helpful to look at the machine code as well as the mnemonic instructions 0003 SAM EQU 03 SAM equal an 8 bit value 1400 LARRY EQU 1400 LARRY equal a 16 bit value 0100 ORG 100 Set program starting point 0100 ae 02 TOP LDX 02 Initialize index register 0102 a6 05 LDA 05 Read value into A O A 0005 O B 0102 gt C 0103 see 3 7 2 Immediate Addressing Mode O D a605 In the following instruction sequence a value is read into the accumulator From what address is this value being read It may be helpful to look at the machine code as well as the mnemonic instructions 0003 SAM EQU 503 SAM equal 8 bit value 1400 LARRY EQU 1400 LARRY equal a 16 bit value 0100 ORG 100 Set program starting point 0100 ae 02 TOP LDX 502 Initialize index register 0102 b6 05 LDA 05 Read value into A gt A 0005 see 3 7 4 Direct Addressing Mode O B 0102 O C 0103 O D b605 M68HCO05 Applications Guide Rev 4 0 326 Review Questions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Review Questions Review Questions Answers and Explanations 26 In the following instruction sequence a value is read into the accumulator From what address is this value being read It may be helpful to look at the machine code as well as the mnemonic instructions 0003 SAM E
360. uct Go to www freescale com 241 Freescale Semiconductor Inc Instruction Set Details ASR Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Arithmetic Shift Right ASR Shifts all of ACCA X or M one place to the right Bit 7 is held constant Bit 0 is loaded into the C bit of the CCR This operation effectively divides a twos complement value by two without changing its sign The carry bit can be used to round the result N R7 Set if MSB of result is set cleared otherwise Z R7e R6eR5 R4 R3 R2 R1 RO Set if all bits of the result are cleared cleared otherwise C Set if before the shift the LSB of the shifted value was set cleared otherwise Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles ASRA INH A 47 3 ASRX INH X 57 3 ASR opr DIR 37 dd 5 ASR X IX 77 5 ASR opr X 67 ff 6 M68HC05 Applications Guide Rev 4 0 242 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc Instruction Set Details M68HC05 Instruction Set Branch if Carry Clear BCC Same as BHS PC lt PC
361. uction Effects 177 3 15 1 Low Power Consumption 5 177 3 15 2 Effects On Chip Peripherals 180 3 1521 Timer Action During Stop 180 3 15 22 SOL Action During Stop Mode 180 3 15 2 3 SPI Action During Stop Mode 181 3 15 2 4 Wait Mode 181 3 16 OTPROM EPROM 182 522535155844 aE AAEE 182 mies Programimi 182 3 16 3 Program 5 183 3 16 4 Onloh cuscaasansesencuenusextadxm tesi 184 Section 4 Applications 0 nre 187 42 187 4 3 Hardware Development 189 4 4 Software Development 191 4 4 1 193 44 2 Third Party Sofware CO 194 45 Thermostat Project 196 4 5 1 Hardware 197 4 5 2 Project 200 M68HC05 Applications Guide Rev 4 0 MOTOROLA Table of Contents 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
362. ulae Source Forms Addressing Modes Machine Code and Cycles Branch if Plus B PL PC lt PC 0002 Rel if N 0 Tests the state of the N bit in the CCR and causes a branch if N is clear See BRA instruction for details of the execution of the branch H 2 1 1 1 None affected Source Addressing Machine Code HCMOS BPL rel REL 2A rr 3 The following table is a summary of all branch instructions Test Boolean Mnemonic Opcode Complementary Branch Comment r gt m C Z 0 BHI 22 BLS 23 Unsigned 0 BHS BCC 24 rm BLO BCS 25 Unsigned r m Z 1 BEQ 27 26 Unsigned r lt m C Z 1 BLS 23 r gt m BHI 22 Unsigned rm C 1 BLO BCS 25 BHS BCC 24 Unsigned Carry 1 BCS 25 No Carry BCC 24 Simple r 0 2 1 27 r 0 BNE 26 Simple Negative N 1 BMI 2B Plus BPL 2A Simple Mask 1 5 2D Mask 0 BMC 2 Half Carry H 1 BHCS 29 No Half Carry BHCC 28 Simple Pin High 2F IRQ Low BIL 2E Simple Always BRA 20 Never BRN 21 Unconditional r register ACCA or X memory operand M68HC05 Applications Guide Rev 4 0 260 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine
363. unctional Data 171 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8 705 8 Functional Data 3 14 5 Output Compare Concept The output compare function is also a fundamental element of the MC68HC705C8 timer architecture Output compare functions are used to program an action to occur at a specific time i e when the 16 bit counter reaches a specific value The value in the output compare register is compared with the value of the free running counter on every fourth bus cycle When the output compare register matches the counter value an output is generated which sets an output compare status flag and transfers the level of the OLVL bit to the TCMP output pin see Figure 3 46 Change the values in the output compare register and the output level bit after each successful comparison to control an output waveform or to establish a new elapsed timeout An interrupt can also accompany a successful output compare if the corresponding interrupt enable bit OCIE is set OLVL 0 TO FORCE TCMP PIN TO 0 VALID COMPARE OLVL 1 TO FORCE TCMP PIN HIGH ON VALID COMPARE PIN CONTROL LOGIC 15 8 7 0 COUNTER HIGH BYTE COUNTER LOW BYTE ff di 16 BIT OUTPUT COMPARE REGISTER or STAINS FERS REQUEST A TIMER INTERRUPT LOCAL INTERRUPT MASK ENABLE _ gt OCIE Figure 3 46 Output Compare Operation M68HCO5 Applications Guide Rev 4 0 172 MC68HC7
364. unctional Data MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68HC705C8 Functional Data Interrupts Table 3 8 Vector Address for Interrupts and Reset Vector Register Name Interrupts Interrupt Address N A N A Reset RESET 1FFE 1FFF N A N A Software SWI 1FFC 1FFD N A N A External interrupt IRQ 1FFA 1FFB Timer ICF Input capture OFC Output compare TIMER 1FF8 1FF9 Status Timer overflow TDRE Transmit buffer empty SCI TC Transmit complete Status RDRF Receiver buffer full 5 1FF6 1FF7 IDLE Idle line detect OR Overrun SPI SPIF Transfer complete Status Mode fault ud Reset and interrupt operations are often discussed together because they share the common concept of vector fetching to force a new starting point for further CPU operation Unlike interrupts there is no intention to ever return to whatever the CPU was doing before a reset occurred A low on the RESET input pin causes the program to vector to its starting address specified by the contents of memory location 1FFE and 1FFF The bit in the condition code register is also set Much of the MCU is configured forced to a known state during reset 3 9 1 Software Interrupt SWI The software interrupt is an executable instruction The action of the SWI instruction is similar to the hardware interrupts The SWI
365. we 281 MUL Multiply Unsigned 282 NEG 283 iu ee bod A oO ER 284 1 5 285 ROL Rotate Left thru 286 ROR Rotate Right thru 287 RSP Reset Stack 288 RTI Return from 289 RTS Return from Subroutine 290 SBC Subtract with 291 SEL 5 292 SEI Set Interrupt Mask 293 STA Store Accumulator 294 STOP Enable IRQ Stop Oscillator 295 STX Store Index Register X in Memory 296 SUB aaa 297 SWI Software 298 TAX Transfer Accumulator to Index Register 299 TST Test for Negative or 4 300 TXA Transfer Index Register to Accumulator 301 WAIT Enable Interrupt Stop Processor 302 M68HCO05 Applications Guide Rev 4 0 MOTOROLA Table of Contents 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix Review Questions
366. xecution of the CLI instruction H 2 1 1 1 0 0 Cleared Source Forms Addressing Source Addressing Machine Code HCMOS Modes Machine Forms Mode Opcode Operand s Cycles Code and Cycles CLI INH 9A 2 M68HC05 Applications Guide Rev 4 0 268 Instruction Set Details MOTOROLA For More Information On This Product Go to www freescale com Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Freescale Semiconductor Inc ACCA lt 00 Clear or lt 00 Instruction Set Details M68HC05 Instruction Set The contents of ACCA M or X are replaced with zeros X 00 CLR 0 Cleared Z 1 Set Source Addressing Machine Code HCMOS Forms Mode Opcode Operand s Cycles CLRA INH A 4F 3 CLRX INH X 5F 3 CLR opr DIR 3F dd 5 CLR X IX 7F 5 CLR opr X 6F ff 6 M68HC05 Applications Guide Rev 4 0 MOTOROLA Instruction Set Details For More Information On This Product Go to www freescale com 269 Freescale Semiconductor Inc Instruction Set Details CMP Operation Description Condition Codes and Boolean Formulae Source Forms Addressing Modes Machine Code and Cycles Compare Accumulator with Memory CM ACCA
367. y language of several different MCUs The compiler translates the high level language instructions into a machine readable object file for a particular MCU The greatest disadvantage of using a high level language anda compiler is the significant inefficiency introduced in translating to the MCU machine language The degree of inefficiency depends on the power of the MCU instruction set and the task being performed The M68HC05 has a relatively small instruction set compared to a mainframe or personal computer thus it is difficult and inefficient to use C language instructions in this MCU The inefficiency of using C language instructions also affects timing of I O operations For some applications where very fine control of timing is important it is better to use assembly language than to use C Inefficient programs also require more memory to perform a task For many applications the speed of the CPU is so great compared to the requirements of the application that the inefficiencies of high level language are unimportant Present day MCUs often have enough on chip memory so that program size may be unimportant Using high level language with the 68 5 is not recommended in most cases However at least one good C compiler is available for the M68HCOS If you want to use high level languages for Motorola MCUs you can get a list of names and addresses of third party vendors and products from a local Motorola representative or by calling
368. y requirements A program controls the entire operation of the thermostat Section 4 Applications of this manual contains project details M68HC05 Applications Guide Rev 4 0 28 General Description MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Applications Guide M68HC05 2 1 Contents Section 2 Microcontroller Operation 30 23 iuo DEOR IR 31 24 Gomputer xo oad ddp doe doe eed eal 34 2 4 1 Computer 36 2 4 2 Computer 37 2 4 3 GPU Regbis 38 2 4 4 Memory USES uoe dk ca eR Eh et EEL 40 2 4 5 42 ek dae ede Sp 44 26 Pen 24 2393 WE dob d o CERO OR 45 2 6 1 PIRE Gnd Rese e aes dae i d 46 252 Mnemonic Source 46 2 6 3 Software Delay Program 49 2 6 4 Assembler 5 50 2 6 5 CPU View of a 54 zl 094 pd d E EREA 55 2 1 Detailed Operation of CPU Instructions 55 2 7 1 1 Store Accumulator Direct Addressing Mode 57 2 7 1 2 Load Accumulator Immediate Addressing Mo
369. ycles to complete this chain of operations M68HC05 Applications Guide Rev 4 0 94 MC68HC705C8 Functional Data MOTOROLA For More Information On This Product Go to www freescale com 3 6 3 CPU Control 3 6 4 Resets Freescale Semiconductor Inc MC68HC705C8 Functional Data Central Processor Unit The CPU control circuitry sequences the logic elements of the ALU to carry out the required operations Reset is used to force the MCU system to a known starting address Peripheral systems and many control and status bits are also forced to a known state as a result of reset The following four conditions can cause reset in the MC68HC705C8 MCU 1 External active low input signal on the RESET pin 2 Internal power on reset POR condition 3 Internal computer operating properly COP watchdog system reset condition 4 Internal clock monitor reset condition 3 6 4 1 Power On Reset The power on reset occurs when a positive transition is detected on Vpp The power on reset is used strictly for power turn on conditions and should not be used to detect any drops in the power supply voltage There is no provision for a power down reset The power on circuitry provides for a 4064 cycle delay from the time that the oscillator becomes active If the external RESET pin is low at the end of the 4064 delay timeout the processor remains in the reset condition until RESET goes high M68HC05 Applications Guide
370. ypical Computer System M68HCO5 Applications Guide Rev 4 0 24 General Description MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Description Computer Systems Description Output devices are controlled by signals from the MCU An external interface is required by some output devices to translate the 0 to 5 Vdc MCU levels into different voltage or current levels Liquid crystal displays video display terminals and heating cooling equipment are examples of output devices Memory can store information including the instructions and data that the CPU uses The two basic memory types are random access memory RAM and read only memory ROM RAM is used for temporary storage of data and instructions The computer system can write information into and read information from a RAM in an arbitrary random order RAM is volatile in that its contents are lost when power is removed ROM has data and instructions a program stored permanently in it when it is manufactured The CPU can read information from a ROM but cannot write information into it ROM information is nonvolatile in that it does not change even when power is removed A programmable read only memory PROM is a type of ROM that can be programmed by the user An erasable programmable read only memory EPROM is a type of PROM that can be erased by exposing it to ultraviolet light Once erased an EPROM

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