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S3C84H5/F84H5

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1. 6 44 Increment eee rrr 6 45 Interrupt Return Spree errr eee errr errr errr err errr reer rere errr errr terri reer eee eee rere erie 6 46 Jump PPP Perret reer errr eer ere reer reer reer reer rere rere rer r eee errr eee ree eee eee ee eee eee 6 47 Jump Relative mmm HH HH HHhhenennenehnn nenne nennen 6 48 Load Perret teeter ee eer rere rere eer eee reer rere eee reer reer ere rere reer errr reer errr reer reer reer eee eer 6 49 Load Perret eee tree eer eer ee errr reer reer eter errr reer ere ee rere errr eer e tree C A 6 50 Load Bit mmmmmHM Henn 6 51 xxi S3C84H5 F84H5 MICROCONTROLLER List of Instruction Descriptions Continued Instruction Full Register Name Page Mnemonic Number LDC LDE Load Memory sasssssussssussssussssssssussnsassuscusssessssssensssusessausescussessuseusesscssuscusessassuscunsosuuseseunus 6 52 LDC LDE Load Memory 6 53 LDCD LDED Load Memory and Decrement sassssnssssnssssssesaussasussessensssunsesssssusussecussessussusensessuscusessaneuse 6 54 LDCI LDEI Load Memory and Increment sasassssassssusssunsssusssscussscussesaussssusssusessusenscusescusensausescussesuassss 6 55 LDCPD LDEP
2. 6 30 Compare Increment and Jump Equal 6 21 Compare Increment and Jump Non Equal m 6 32 Decimal Adjust 6 33 Decimal Adjust 4 A w 6 34 Decrement 6 35 Decrement Word mm 6 36 Disable Interrupts A A A A LAAA AA Am5AAARE 6 37 Divide Unsigned 6 38 Decrement and Jump if Non Zero mH HH HMM 6 39 Enable Interrupts CUwww S 0 S0 S0CS0NVS Anw LP 6 40 Enter Peer eee rere errr eer reer eer ere reer reer eee eee eee eee 6 41 Exit POPE eee eee teeter eee errr errr errr errr reer eee rere e ree etree tree etree eee eee 6 42 Idle Operation T R 6 43 Increment
3. 14 1 Programming Procedure 8 ihe ee e ERU eee eee ea 14 1 Serial I O Control Registers SIOCON 14 2 SIO Prescaler Register 5 24022222224 2 2 12 600000000 i eai E 14 3 viii S3C84H5 F84H5 MICROCONTROLLER Table of Contents Continued Chapter 15 UART Overview 1541 Programming Procedure 1 reete epe eee Ee Ege Dei iP Eo eR edge Fe EC i Het gba SR 15 1 UART Control Register 15 2 UART Interrupt Pending Register 15 4 UART Data Register ceeded ti rr editrice etie eere eode redeat dt 15 5 UART Baud Rate Data Register 15 6 Baud Rate Calc lations 25 e prote rre eH GE 15 6 Block EE 15 8 UART 0 Function Description 2 nete Erit terere oi etae 15 9 UART Mode 1 Function 15 10
4. 3 2 Indirect Register Addressing Mode IR 3 3 Indexed Addressing Mode X 3 7 Direct Address Mode DA 3 10 Indirect Address Mode IA 3 12 Relative Address Mode RA 3 13 Immediate Mode IM 3 14 S3C84H5 F84H5 MICROCONTROLLER Table of Conte
5. 9 8 old RE 9 12 Chapter 10 Basic Timer Overview 10 1 E ei 10 1 Basic Timer Control Register BTCON cccesceeeeeceeeeeeeeeeeeeeeaeeesaeeseeaeceeaeesecaeeseaeeseaeeesneeeeeaeetees 10 1 Basic Timer Function 10 3 S3C84H5 F84H5 MICROCONTROLLER vii Table of Contents Continued Chapter 11 8 Bit Timer A B 8 Bit Timer A 1 1 1 BMC fd suet chess bind 11 1 FUNCTION Descriptio 555552 EE 11 2 Timer Control Register TACON 11 3 Block et ai eaea 11 4 8 Bit Timer B Selene 1 1 5 ree ee e RR M d erede e RERUM cde RH e a tcm E o e 11 5 Block Diagram eaa DEUM A NU E ere A M ce S INE 11 5 Timer B Control Register TBGON e e aree tee eti 11 6 Timer B Pulse Wid
6. 1 5 Assignment Tee Te CC eee EERO ETE CEPT EPC ERR SE SEN E ER NNNM EM 1 6 Descriptions 1 7 10801116 1 11 2 Address Spaces Overview Wetec 4 ees 8888 55488 4858568 9 858 Program Memory ROM WiebhwatpecesSscciaccuseccdaumecrubaceseeseecnectrepenccunbecceuGouccnsacosbentheccecssebetececdsectanseecbeucestanccnuerscuws Register Architecture Register Page Pointer Register Set 1 Register Set 2 in terat aleve ose evi Perseo edes Prime Register Space Working Registers ro i DR DURER E EE SG ORC euis Using the Register Polnters noob mmo e de n edi ees Register Addressing Common Working Register Area 4 Bit Working Register Addressing 8 Bit Working Register Addressing System User Stack QE Chapter 3 Addressing Modes X 3 1 Register Addressing Mode R
7. interrupt mask register IMR enables un masks or disables masks interrupt levels interrupt priority register IPR controls the relative priorities of interrupt levels The interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Control Register Overview Control Register Function Description Interrupt mask register Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels IRQO IRQ7 Interrupt priority register Controls the relative processing priorities of the interrupt levels The seven levels of 53 8415 8419 organized into three groups A B and C Group A is IRQO and IRQ1 group B is IRQ2 IRQ3 and IRQ4 and group C is IRQ5 IRQ6 and IRQ7 Interrupt request register This register contains a request pending bit for each interrupt level System mode register This register enables disables fast interrupt processing dynamic global interrupt processing NOTE Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended ELECTRONICS 5 7 INTERRUPT STRUCTURE S3C84H5 F84H5 INTERRUPT PROCESSING
8. PWMCON 2 8 bit Comparator P2 1 PWM F3H Set1 Bank1 PWMDATAH 8 bit Data Register F3H Set1 Bank1 PWMDATAL 1 0 PWMCON 3 clear 8 bit up counter overflow DATA BUS 7 0 Figure 13 4 PWM Functional Block Diagram 13 6 ELECTRONICS S3C84H5 F84H5 10 BIT PWM PULSE WIDTH MODULATION PROGRAMMING TIP Programming the PWM Module to Sample Specifications iM lt lt Interrupt Vector Address gt gt ORG 0000H VECTOR ODAH INT_PWM i lt lt Initialize System and Peripherals gt gt ORG 0100H RESET DI Disable interrupt SB1 Extra command only for debugging LD OF7H 5FH Extra command only for debugging SBO Extra command only for debugging LD BTCON 10100011B Watchdog disable LD P2CONL 00001100B Configure P2 1 PWM output LD PWMCON 00000110B 580 64 counter interrupt enable LD 880 LD PWMDATAL 0 EI Enable interrupt iM lt lt Main loop gt gt MAIN JR t MAIN iM lt lt Interrupt Service Routines gt gt INT PWM PWM interrupt service routine AND PWMCON 11111110B Pending bit clear IRET END NOTE debug mode you have to include three extra commands in initial routine to operate Ports correctly If you omit these commands Port do not operate correctly After you have finished your program and before assembling you have to remove these three commands ELECTRONICS 13 7 S3C84H5 F84H5 SERIAL I O INTERFACE SERIA
9. 04H In the first example the destination working register RO contains the value 06H and the source general register the value 05H The statement LD R0 00H 2 loads the bit two value of the register into bit zero of the RO register leaving the value 07H in the register RO In the second example is the destination register The statement LD 0 loads bit zero of the register RO to the specified bit bit zero of the destination register leaving 04H in the general register 00H ELECTRONICS 6 51 INSTRUCTION SET S3C84H5 F84H5 LDC LDE Load Memory LDC LDE Operation Flags Format 1 2 3 4 5 6 T 8 9 10 NOTES dst src dst src dst lt src This instruction loads a byte from program or data memory into a working register or vice versa The source values are unaffected LDC refers to program memory and LDE to data memory The assembler makes Irr or rr values an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst sre dst src 2 10 C3 r Irr opc src dst 2 10 D3 Irr r opc dst src XS 3 12 E7 r XS rr opc src dst XS 3 12 F7 XS rr r opc dst src XL XLy 4 14 7 r XL rr opc src dst XL XL 4 14 B7 XL rr r opc dst 0000 DAL DA 4 14 r DA src 0000 DA 4 14 B7 DA r dst 0001
10. DA 4 14 7 DA 0001 DA DA 4 14 B7 DA r 1 The source src or the working register pair rr for formats 5 and 6 cannot use the register pair 0 1 2 For the formats 3 and 4 the destination XS rr and the source address XS rr are both one byte 3 Forthe formats 5 and 6 the destination XL rr and the source address XL rr are both two bytes 4 The DA and the r source values for the formats 7 and 8 are used to address program memory The second set of values used in the formats 9 and 10 are used to address data memory 5 LDE instruction can be used to read write the data of 64 Kbyte data memory 6 52 ELECTRONICS S3C84H5 F84H5 LDC LDE Load Memory LDC LDE Continued Examples Given RO 11H R1 INSTRUCTION SET 34H R2 01H 04H Program memory locations 0103H 0104H 0105 6DH 1104 88H External data memory locations 0103H 5FH 0104H 2AH 0105H LDC 2 LDE RO RR2 LDC RR2 RO LDE RR2 RO LDC RO 01H RR2 LDE RO 01H RR2 LDC 01H RR2 RO LDE 01H RR2 RO LDC RO 1000H RR2 LDE RO 1000H RR2 LDC R0 1104H LDE 1104 LDC 1105 LDE 1105H RO 7DH and 1104H 98H RO lt contents of program memory location 0104H RO 1AH R2 01H R3 04H RO lt contents of external data memory location 0104H RO 2AH R2 01H R3 04H 11H contents of RO is loaded into program memory
11. Figure 21 1 32 SOP 450A Package Dimensions ELECTRONICS 21 1 MECHANICAL DATA 53 84 5 4 5 32 SDIP 400 9 10 0 20 27 88 MAX 27 48 0 20 5 08 IM e 0 45 0 10 0 51 MIN 3 30 0 30 1 00 0 10 NOTE Dimensions in millimeters Figure 21 2 32 SDIP 400 Package Dimensions 21 2 ELECTRONICS S3C84H5 F84H5 16 COO MECHANICAL DATA 30 SDIP 400 8 94 0 2 27 88MAX 27 48 0 2 5 08 MAX A m e 0 56 0 1 1 12 0 1 0 51 3 30 0 3 NOTE Dimensions in millimeters Figure 21 3 30 Pin SDIP Package Dimensions ELECTRONICS 21 3 MECHANICAL DATA 53 84 5 4 5 28 BRHRHRRRHRHRRRHR 28 SOP 375 10 45 0 3 7 70 0 2 HHEHBBHHHHHBBHB 14 0 60 0 2 18 02 MAX 2 15 01 2 50 MAX 17 62 0 2 0 05 MIN 0 56 0 41 0 1 gt H gt H NOTE Dimensions are in millimeters Figure 21 4 28 SOP 375 Package Dimensions 21 4 ELECTRONICS S3C84H5 F84H5 DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy to use development support system on a turnkey basis The development support system is composed of a host system debugging tools and supporting software For a host System any standard com
12. assuming that it contains the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of the register 1BH from OFH to 10H ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET INCW Increment Word INCW dst Operation dst lt dst 1 The contents of the destination which must be an even address and the byte following that location are treated as a single 16 bit value that is incremented by one Flags C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 AO RR 1 Examples Given RO R1 02H register 02H OFH and register INCW RRO gt RO 1AH R1 INCW R1 gt Register 02H register 03H 00H In the first example the working register pair RRO contains the value 1AH in the register RO and 02H in the register R1 The statement INCW RRO increments the 16 bit destination by one leaving the value 03H in the register R1 In the second example the statement INCW R1 uses Indirect Register IR addressing mode to increment the contents of the general register 03H from OFFH to and the register 02H from OFH to 10H NOTE A system malfunction may occur if you use Zero Z flag FLAGS 6 re
13. 0 15 Indirect register or indirect working register QRn or reg reg 0 255 n 0 15 Irr Indirect working register pair only RRp p 0 2 14 IRR Indirect register pair or indirect working RRp or reg reg 0 254 even only register pair where p 0 2 14 X Indexed addressing mode reg Rn reg 0 255 n 0 15 XS Indexed short offset addressing mode addr RRp addr range 128 to 127 where p 0 2 14 XL Indexed long offset addressing mode addr RRp addr range 0 65535 where p 2 14 DA Direct addressing mode addr addr range 0 65535 RA Relative addressing mode addr addr a number from 127 to 128 that is an offset relative to the address of the next instruction IM Immediate addressing mode data data 0 255 IML Immediate long addressing mode data data 0 65535 ELECTRONICS 6 9 INSTRUCTION SET S3C84H5 F84H5 Table 6 5 OPCODE Quick Reference OPCODE MAP LOWER NIBBLE HEX 0 1 2 3 4 5 6 7 U 0 DEC DEC ADD ADD ADD ADD ADD BOR R1 IR1 1 2 r1 Ir2 R2 R1 IR2 R1 R1 IM rO Rb P 1 RLC RLC ADC ADC ADC ADC ADC BCP R1 IR1 1 2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b R2 P 2 INC INC SUB SUB SUB SUB SUB BXOR R1 IR1 r1 r2 1 12 R2 R1 IR2 R1 R1 IM rO Rb E 3 JP SRP 0 1 SBC SBC SBC SBC SBC BTJR IRR1 IM r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r2 b RA R 4 DA DA OR OR OR OR OR LDB R1 IR 1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM rO Rb 5
14. 15 6 ELECTRONICS S3C84H5 F84H5 UART Table 15 1 Commonly Used Baud Rates Generated by 16bit BRDATA BRDATAH BRDATAL Baud Rate Oscillation Clock Decimal Hex Decimal Hex 230 400 Hz 11 0592 MHz 0 02H 57 600 Hz 11 0592 MHz ELECTRONICS 14 7 UART S3C84H5 F84H5 BLOCK DIAGRAM 5 88 Internal Data Bus TB8 zz 16BIT 02 5 BRDATA CLK C Wu 50 RxD P2 6 Baud Rate CLK MS1 id Generator Zero Detector Write to UDATA gt Start Shift TxD P2 7 Control Tx Clock TIP Send RIE Interrupt TIE gt Rx Clock RIP Receive RE Rx RIE gt 0 H Control M Start Shift 1 to 0 Transition e gt 1 Detector Shift Bit Detector Value L H Shift Register 50 5 215 e NZ UDATA RxD P2 6 NZ 15 8 5 88 Internal Data Bus Figure 15 5 UART Functional Block Diagram TxD P2 7 ELECTRONICS S3C84H5 F84H5 UART MODE 0 FUNCTION DESCRIPTION UART In mode 0 UART is input and output through the RxD P2 6 pin and TxD P2 7 pin outputs the shift clock Data is transmitted or received in 8 bit units only The LSB of the 8 bit value is transmitted or received first Mode 0 Transmit Procedure 1 S
15. 2 5 to 3 3 V 2 5 5 0 RUN mode 4 MHz CPU clock Idle mode 10 MHz CPU clock Idle mode 4 MHz CPU clock Sub operating main osc stop 400 800 32768 Hz crystal oscillator Sub idle mode main osc stop 300 600 32768 Hz crystal oscillator Ipps 3 Vpp 4 5V to 5 5 V TA 25 C 150 400 Stop mode NOTES 1 Supply current does not include current drawn through internal pull up resistors or external output current loads 2 IDD1 and IDD2 include a power consumption of subsystem oscillator 3 IDD3 and IDD4 are the current when the main system clock oscillation stop and the subsystem clock is used 4 1005 is the current when the main and subsystem clock oscillation stop 5 All currents IDD1 IDD5 include the current consumption of LVR circuit Except the case that LVR is disabled 6 1005 is the same regardless of LVR on LVR off 20 4 ELECTRONICS S3C84H5 F84H5 ELECTRICAL DATA Table 20 4 A C Electrical Characteristics TA 25 to 85 C 2 5V to 5 5 V Parameter Conditions Unit Interrupt Input Vop 5 180 High Low Width Ports 2 RESETB Input tas Input Low Width NOTE User must keep more large value then min value Figure 20 1 Input Timing for External Interrupts Ports 2 tRSL RESET 0 2 VDD Figure 20 2 Input Timing for RESET ELECTRONICS 20 5 ELECTRICAL DATA S3C84H5 F84H5 Table 20 5 Main Oscillator Frequency fosc TA 25 85 C
16. 6 Interrupt Subgroup C Priority Control Bit 0 IRQ6 gt IRQ7 1 IRQ7 gt 1806 5 Interrupt Group C Priority Control Bit 0 gt IRQ6 IRQ7 806 IRQ7 gt 5 3 Interrupt Subgroup B Priority Control Bit IRQ3 gt IRQ4 1 IRQ4 gt IRQ3 2 Interrupt Group B Priority Control Bit 0 IRQ2 gt IRQ3 IRQ4 1 IRQ3 IRQ4 gt IRQ2 0 Interrupt Group A Priority Control Bit IRQO gt IRQ1 IRQ1 IRQO B ELECTRONICS 4 11 CONTROL REGISTERS S3C84H5 F84H5 IRQ Interrupt Request Register DCH Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R R R R Addressing Mode Register addressing mode only 7 Interrupt Level 7 IRQ7 Request Pending Bit EN Not pending Pending 6 Interrupt Level 6 IRQ6 Request Pending Bit Not pending 1 Pending 5 Interrupt Level 5 IRQ5 Request Pending Bit EN Not pending Pending 4 Interrupt Level 4 IRQ4 Request Pending Bit EN Not pending Pending 3 Interrupt Level 3 IRQ3 Request Pending Bit 0 Not pending 1 Pending 2 Interrupt Level 2 IRQ2 Request Pending Bit EN Not pending Pending 1 Interrupt Level 1 IRQ1 Request Pending Bit Not pending 1 Pending 0 Interrupt Level 0 Request Pending Bit EN Not pending 4 12 ELECTRONICS S3C84H5 F84H5 CONTROL REGISTER OSCCON Oscillator Control Register F2H Set1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W Addressing Mode 7
17. ADDRESSING MODES There are seven explicit addressing modes Register R Indirect Register IR Indexed X Direct DA Relative RA Immediate IM and Indirect IA For detailed descriptions of these addressing modes please refer to Chapter 3 Addressing Modes ELECTRONICS 6 1 INSTRUCTION SET S3C84H5 F84H5 Table 6 1 Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst src Load LDB dst src Load bit LDE dst src Load external data memory LDC dst src Load program memory LDED dst src Load external data memory and decrement LDCD dst src Load program memory and decrement LDEI dst src Load external data memory and increment LDCI dst src Load program memory and increment LDEPD dst src Load external data memory with pre decrement LDCPD dst src Load program memory with pre decrement LDEPI dst src Load external data memory with pre increment LDCPI dst src Load program memory with pre increment LDW dst src Load word POP dst Pop from stack POPUD dst src Pop user stack decrementing POPUI dst src Pop user stack incrementing PUSH src Push to stack PUSHUD dst src Push user stack decrementing PUSHUI dst src Push user stack incrementing NOTE LDE LDED LDEI LDEPP and LDEPI instructions can be used to read write the data from the 64 Kbyte data memory ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET Table 6 1 Instruction Group Summary Continued Mnemonic Operands I
18. Instruction Example OPCODE Woking Register 1 of 8 Sample Instruction LD 4BASE R1 Where BASE is 8 bit immediate value Figure 3 7 Indexed Addressing to Register File ELECTRONICS 3 7 ADDRESSING MODES INDEXED ADDRESSING MODE Continued MSB Points to RPO or RP1 Program Memory OFFSET OPCODE 4 bit Working Register Address LSB Selects or 8 Bits Sample Instructions LDC R4 04H RR2 LDE R4 04H RR2 NEXT 2 Bits gt Point to Working Register Pair S3C84H5 F84H5 Register File or Selected RP points to start of working register block Register Pair 16 Bit address added to offset p Program Memory Data Memory lt 16 Bits Value used in Instruction OPERAND 16 Bits The values in the program address RR2 04H are loaded into register R4 Identical operation to LDC example except that external program memory is accessed Figure 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 ELECTRONICS S3C84H5 F84H5 Program Memory OFFSET OFFSET 4 bit Working y dst src Register Address OPCODE INDEXED ADDRESSING MODE Continued MSB Points to RPO or NEXT 2 Bits VEM UIS 2252 Point to Working Register Pair Register File or Register Pair H ADDRESSING MODES Selected RP points
19. Vss Xour XIN TEST XTour nRESET P3 0 P3 1 SO P2 4 SCK P2 5 RxD P2 6 TxD P2 7 ADO P0 0 AD1 PO 1 ed uiid eA OROMAOCPANDARWN OQ O S3C84H5 S3F84H5 Top View 30 SDIP O 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD P1 3 T1OUT1 INT3 P1 2 TACAP INT2 P1 1 TACK BUZ INT1 P1 0 TAOUT INTO AVss AVREF P1 5 AD6 T1CAP1 P1 4 AD5 T1CK1 P2 3 AD7 SI P2 2 AD4 T1OUTO P2 1 T1CAP0 PWM P2 0 T1CK0 TBPWM P0 3 AD3 P0 2 AD2 Figure 1 3 S3C84H5 F84H5 Pin Assignment 30 pin SDIP ELECTRONICS 1 5 PRODUCT OVERVIEW PIN ASSIGNMENT S3C84H5 F84H5 Vss Xour XIN TEST XTour nRESET SO P2 4 SCK P2 5 RxD P2 6 TxD P2 7 ADO P0 0 AD1 PO 1 AD2 P0 2 01 00 Sec OQ O S3C84H5 S3F84H5 Top View 28 SOP 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD P1 3 T1OUT1 INT3 P1 2 TACAP INT2 P1 1 TACK BUZ INT1 P1 0 TAOUT INTO AVss AVREF P1 5 AD6 T1CAP1 P1 4 AD5 T1CK1 P2 3 AD7 SI P2 2 ADA T1OUTO P2 1 T1CAPO PWM P2 0 T1CKO TBPWM P0 3 AD3 Figure 1 4 S3C84H5 F84H5 Pin Assignment 28 pin SOP 1 6 ELECTRONICS S3C84H5 F84H5 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1 1 S3C84H5 F84H5 Pin Descriptions 32SOP 32SDIP 28SOP Circuit Share ge 5 PO 0 PO 3 I O Bit programmable port input or output mode selected by software
20. 1 12 4 ELECTRONICS S3C84H5 F84H5 16 BIT TIMER 1 0 1 Timer A Timer 1 Pending Register TINTPND EOH Set 1 Bank 1 R W Timer A match capture Not used interrupt must keep always 0 pending bit 0 No interrupt pending 1 Interrrupt pending Timer 1 1 overflow interrupt Timer A overflow pending bit pending interrupt 0 No interrupt pending 0 No interrupt pending 1 Interrrupt pending 1 Interrrupt pending Timer 1 1 match capture interrupt Timer 1 0 match capture interrupt pending bit pending bit 0 No interrupt pending 0 No interrupt pending 1 Interrrupt pending 1 Interrrupt pending Timer 1 0 overflow interrupt pending bit 0 No interrupt pending 1 Interrrupt pending Figure 12 2 Timer A Timer 1 0 1 Pending Register TINTPND ELECTRONICS 12 5 16 1 0 1 S3C84H5 F84H5 BLOCK DIAGRAM T1CON 7 5 0 Overflow f xx 1024 gt Data Bus Pending fxx 256 gt fxx 64 gt TINTPND fxx 8 gt fxx 1 gt 16 bit Up Counter 1 2 1 gt Read Only Vss gt T1CON 1 T1INT 16 bit Comparator P Pending TINTPND 16 bit Timer Buffer T1OUT T1PWM T1CON 4 3 16 bit Timer Data Register TI DATAH L T1CON 4 3 NOTES 1 When PWM mode match signal cannot clear counter 2 Pending bit is located at TINTPND register Figure 12 3 Timer 1 0 1 Functional Block Diagram 12 6 ELECTRONICS S3C84H5 F84H5 16 BIT TIM
21. For duplicate copies of this form and for additional ordering information please contact your local Samsung sales representative Samsung sales offices are listed on the back cover of this book 53 8418 8419 MASK OPTION SELECTION FORM Device Number 5308 write down the ROM code number Attachment Check one Diskette PROM Customer Checksum Company Name Signature Engineer Please answer the following questions Application Product Model ID Audio LCD Databank Caller ID LCD Game Industrials Home Appliance Office Automation 71 Other Please describe in detail its application For duplicate copies of this form and for additional ordering information please contact your local Samsung sales representative Samsung sales offices are listed on the back cover of this book
22. SBO Select Bank 0 SBO Operation BANK lt 0 The SBO instruction clears the bank address flag the FLAGS register FLAGS 0 to logic zero selecting the bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 4F Example The statement SBO clears FLAGS 0 to 0 selecting the bank 0 register addressing ELECTRONICS 6 75 INSTRUCTION SET S3C84H5 F84H5 SB1 Select Bank 1 SB1 Operation Flags Format Example BANK lt 1 The SB1 instruction sets the bank address flag in the FLAGS register FLAGS 0 to logic one selecting the bank 1 register addressing in the set 1 area of the register file NOTE Bank 1 is not implemented in some KS88 series microcontrollers No flags are affected Bytes Cycles Opcode Hex 1 4 The statement SB1 sets FLAGS 0 to 1 selectin the bank 1 register addressing if bank 1 is implemented in the microcontrooler s internla register file ELECTRONICS S3C84H5 F84H5 SBC subtract with Carry SBC Operation Flags Format Examples dst src dst dst src c INSTRUCTION SET The source operand along with the current value of the carry flag is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s com
23. sc X F LD LD DJNZ JR LD JP INC NOP r1 R2 r2 R1 r1 RA 1 cc DA r1 ELECTRONICS 6 11 INSTRUCTION SET S3C84H5 F84H5 CONDITION CODES The opcode of a conditional jump always contains a 4 bit field called the condition code cc This specifies under which conditions it is to execute the jump For example a conditional jump with the condition code for equal after a compare operation only jumps if the two operands are equal Condition codes are listed in Table 6 6 The carry C zero Z sign S and overflow V flags are used to control the operation of conditional jump instructions Table 6 6 Condition Codes Binary Mnemonic Description Flags Set 0000 F Always false 1000 Always true 0111 1 Carry C 1 1111 1 NC No carry 0 0110 1 Z Zero Z 1 1110 0 NZ Not zero Z 0 1101 PL Plus 5 0 0101 5 1 0100 Overflow V 1 1100 NOV No overflow V 0 0110 1 EQ Equal Z 1 1110 1 NE Not equal Z 0 1001 GE Greater than or equal S XOR V 0 0001 LT Less than S XOR V 1 1010 GT Greater than Z OR S XOR V 0 0010 LE Less than or equal Z OR S V 1 1111 1 UGE Unsigned greater than or equal 0 0111 9 ULT Unsigned less than 1 1011 UGT Unsigned greater than C 0 AND Z 0 1 0011 ULE Unsigned less than or equal C OR Z 1 NOTES 1 It indicate condition codes wh
24. 15 12 15 9 Connection Example for Multiprocessor Serial Data Communications 15 14 16 1 A D Converter Control Register ADCON UO 16 2 16 2 A D Converter Data Register ADDATAH ADDATAL TAM 16 3 16 3 A D Converter Circuit Diagram wA AA 16 3 16 4 A D Converter Timing Diagram 16 4 16 5 Recommended A D Converter Circuit for Highest Absolute Accuracy 16 5 17 1 Watch Timer Circuit 8 17 3 18 1 Low Voltage Reset Circuit 7mmmmHmmHmeRRRRHRRH HH 18 2 S3C84H5 F84H5 MICROCONTROLLER xiii List of Figures Concluded Figure Title Page Number Number 19 1 Pin Assignment 32 pin SOP SDIP 19 1 19 2 Assignment 30 pin SDIP 19 2 19 3 28 SOP 19 3 20 1 Input Timing for External Interrupts Ports 2 20 5 20 2 Input Timing for RESET eeHmmHmHmHRRHRHRHRRHIHHHMHHIHH 20 5 20 3 Clock Timing Measurement at 20 7 20 4 Mode Release Timing initiated by RESET 20 8 20 5 Stop Mode Main Release Timing Initiated by Interrupts mmm 20 9 20 6 Stop Mode Sub Release Timing Initiated by Interrupts m 20 9 20 7 Waveform for UART Timing 20 10 20 8 Operating Voltage
25. 5 16 ELECTRONICS S3C84H5 F84H5 INTERRUPT STRUCTURE GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM 00H FFH contains the addresses of interrupt service routines that correspond to each level in the interrupt structure Vectored interrupt processing follows this sequence Push the program counter s low byte value to the stack Push the program counter s high byte value to the stack Push the FLAG register values to the stack Fetch the service routine s high byte address from the vector location Fetch the service routine s low byte address from the vector location oa fF ON Branch to the service routine specified by the concatenated 16 bit vector address NOTE A 16 bit vector address always begins at an even numbered ROM address within the range of 0 NESTING OF VECTORED INTERRUPTS It is possible to nest a higher priority interrupt request while a lower priority request is being serviced To do this you must follow these steps 1 Push the current 8 bit interrupt mask register IMR value to the stack PUSH IMR Load the IMR register with a new mask value that enables only the higher priority interrupt Execute an El instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs 4 When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP IMR
26. OCOH Register 06H register 01H 00H In the first example the statement MULT 00H 02H multiplies the 8 bit destination operand in the register of the register pair 00H 01H by the source register 02H operand 09H The 16 bit product 0120H is stored in the register pair OOH 01H ELECTRONICS 6 59 INSTRUCTION SET S3C84H5 F84H5 NEXT Next NEXT Operation Flags Format Example Address 1P PC 6 60 0120 lt IP lt IP 2 The NEXT instruction is useful when implementing threaded code languages The program memory word that is pointed to by the instruction pointer is loaded into the program counter The instruction pointer is then incremented by two No flags are affected Bytes Cycles Opcode Hex opc 1 10 The following diagram shows an example of how to use the NEXT instruction Before After Data Address Data 43 Address 01 44 Address L 30 45 Address H Address Data 43 Address H 44 Address L 45 Address H 120 Next 130 ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET NOP No Operation NOP Operation No action is performed when the CPU executes this instruction Typically one or more NOPs are executed in sequence in order to affect a timing delay of variable duration Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1
27. PWM CONTROL REGISTER PWMCON The control register for the PWM module PWMCON is located at register address F5H PWMCON is used the 10 bit PWM modules Bit settings in the PWMCON register control the following functions PWM counter clock selection PWM data reload interval selection PWM counter clear counter stop start or resume operation PWM counter overflow 10 bit counter overflow interrupt control A reset clears all PWMCON bits to logic zero disabling the entire PWM module PWM Control Register F5H R W Reset 00H PWM input clock PWM OVF interrupt pending bit selection bits 0 No interrupt pending 00 fosc 64 0 Clear pending condition when write 01 fosc 8 1 Interrupt pending 10 fosc 2 PWM interrupt enable bit 0 Disable interrupt Not used for 1 Enable interrupt 53084 5 4 5 PWM counter enable bit 0 Stop counter 1 Start resume countering PWMDATA reload interval selection bit 0 reload from 10bit up counter overflow 1 reload from 8bit PWM counter clear bit up counter overflow 0 No effect 1 Clear the PWM counter Figure 13 3 PWM Control Register ELECTRONICS 13 5 10 PWM PULSE WIDTH MODULATION S3C84H5 F84H5 fosc 8 fosc fosc 64 fosc 2 PWMCON 6 7 2 bit Extend bit 8 bit up counter PWMDATAL PWMDATAH 8 bit Counter 2 bit Counter
28. S3C84H5 F84H5 ADDRESS SPACES USING THE REGISTER POINTERS Register pointers RPO and RP1 mapped to addresses D6H and D7H in set 1 are used to select two movable 8 byte working register slices in the register file After a reset RP point to the working register common area RPO points to addresses COH C7H and RP1 points to addresses 8 To change a register pointer value you load a new value to RPO and or RP1 using an SRP or LD instruction see Figures 2 6 and 2 7 With working register addressing you can only access those two 8 bit slices of the register file that are currently pointed to by RPO and RP1 You cannot however use the register pointers to select a working register space in set 2 COH FFH because these locations can be accessed only using the Indirect Register or Indexed addressing modes The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline it is recommended that RPO point to the lower slice and RP1 point to the upper slice see Figure 2 6 In some cases it may be necessary to define working register areas in different non contiguous areas of the register file In Figure 2 7 RPO points to the upper slice and RP1 to the lower slice Because a register pointer can point to either of the two 8 byte slices in the working register block you can flexibly define the working register area to support program requirements 55
29. The Samsung Arrangeable Microcontroller SAM Assembler SAMA is a universal assembler and generating an object code in the standard hexadecimal format Assembled program codes include the object code used for ROM data and required In circuit emulators program control data To assemble programs SAMA requires a source file and an auxiliary definition device name def file with device specific information HEX2ROM HEX2ROM file generates a ROM code from a HEX file which is produced by the assembler A ROM code is needed to fabricate a microcontroller which has a mask ROM When generating a ROM code file by HEX2ROM the value FF is automatically filled into the unused ROM area up to the maximum ROM size of the target device ELECTRONICS 22 1 DEVELOPMENT TOOLS S3C84H5 F84H5 TARGET BOARDS Target boards are available for all the S3C8 series microcontrollers All the required target system cables and adapters are included on the device specific target board 84 5 is a specific target board for the S3C84H5 F84H5 development IBM PC AT or Compatible RS 232C Emulator SMDS2 or SK 1000 1 Target PROM OTP Writer Unit Application System gt RAM Break Display Unit Probe Adapter Trace Timer Unit TB84H5 5 8 Base Unit Target Board EVA gt Power Supply Unit Chip Figure 22 1 SMDS or SK 1000 Product Configuration 22 2 ELECTRONICS S3C84H5 F84H5 TB84H5 TARG
30. 2 5V to 5 5 V Oscillator Clock Circuit Test Condition Min Typ Max Unit Main Crystal or Vpp 2 5V to 5 5 V Ceramic External Clock Vpp 2 5V to 5 5 V Main System Table 20 6 Main Oscillator Clock Stabilization Time TA 25 C 85 C 2 5V to 5 5 V fosc gt 400 kHz Main Ceramic Oscillation stabilization occurs when Vpp is equal to the minimum oscillator voltage range External Clock input High and Low width tyy tq Main System Oscillator twat When released by a reset 1 Stabilization Wait Time twarr When released by an interrupt 2 NOTES 1 fosc is the oscillator frequency 2 The duration of the oscillator stabilization wait time twa when it is released by an interrupt is determined by the settings in the basic timer control register BTCON 20 6 ELECTRONICS S3C84H5 F84H5 ELECTRICAL DATA 1 fosci u eo Figure 20 3 Clock Timing Measurement at X Table 20 7 Sub Oscillator Frequency fosc2 TA 2 25 85 2 5 to 5 5 V Oscillator Clock Circuit Test Condition Crystal XTour Crystal oscillation frequency C1 100 pF C2 100 pF R 3300 XTn and are connected with R and C by soldering Table 20 8 Subsystem Oscillator crystal Stabilization Time ts15 T4 25 NOTE Oscillation stabilization time is the time required for the o
31. 21H PC 1A47H and SP 0002H CALL 3521H gt SP 0000H Memory locations 0000H 0001H where 4AH is the address that follows the instruction CALL RRO gt SP 0000H 0000H 1AH 0001H 49H CALL 40H gt SP 0000H 0000H 1AH 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to the memory location 0000H The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed If the contents of the program counter and the stack pointer are the same as in the first example the statement CALL QRRO produces the same result except that the 49H is stored in stack location 0001H because the two byte instruction format was used The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed Assuming that the contents of the program counter and the stack pointer are the same as in the first example if the program address 0040H contains 35H and the program address 0041H contains 21H the statement CALL 40H produces the same result as in the second example ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET Complement Carry Flag CCF Operation C lt NOT C The carry flag C is complemented If C 1 the value of the car
32. 3 m prs exemalinenet mx 3 D2H P1 2 external interrupt 2 7 E e RE Poeran O 9 L3 Timer 1 0 match capture C2H Timer A overflow IRQ1 1 190 Timer underflow IRQO NOTES 1 Interrupt priorities are identified in inverse order 0 is the highest priority 1 is the next highest and so on 2 If two or more interrupts within the same level contend the interrupt with the lowest vector address usually has priority over one with a higher vector address The priorities within a given level are fixed in hardware 5 6 ELECTRONICS S3C84H5 F84H5 INTERRUPT STRUCTURE ENABLE DISABLE INTERRUPT INSTRUCTIONS El DI Executing the Enable Interrupts El instruction globally enables the interrupt structure All interrupts are then serviced as they occur according to the established priorities NOTE The system initialization routine executed after a reset must always contain an El instruction to globally enable the interrupt structure During the normal operation you can execute the DI Disable Interrupt instruction at any time to globally disable interrupt processing The El and Dl instructions change the value of bit 0 in the SYM register SYSTEM LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources four system level registers control interrupt processing
33. 5 Execute an IRET Depending on the application you may be able to simplify the procedure above to some extent ELECTRONICS 5 17 S3C84H5 F84H5 INSTRUCTION SET INSTRUCTION SET OVERVIEW The instruction set is specifically designed to support large register files that are typical of most S3C8 series microcontrollers There are 78 instructions The powerful data manipulation capabilities and features of the instruction set include A full complement of 8 bit arithmetic and logic operations including multiply and divide No special I O instructions I O control data registers are mapped directly into the register file Decimal adjustment included binary coded decimal BCD operations 16 bit word data be incremented decremented Flexible instructions for bit addressing rotate and shift operations DATA TYPES The CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit REGISTER ADDRESSING To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 16 bit data 16 bit program memory or data memory addresses For detailed information about register addressing please refer to Chapter 2 Address Spaces
34. A 12 5 12 3 Timer 1 0 1 Functional Block Diagram 12 6 13 1 10 PWM Basic Waveform 13 3 13 2 10 Bit Extended PWM 13 4 13 3 PWM Control Register PWMCON Pee eee eee ee eee eee rere eee eee eee reer eee eee rere rire 13 5 13 4 PWM Functional Block Diagram u a 13 6 14 1 Serial I O Interface Control Register SIOCON Spee eee eee ee ere eee eee eee eee eee eee ee 14 2 14 2 SIO Pre scaler Register SIOPS Seer eee eee eee eee errr ee eee eee rere eee e eee ert A 14 3 14 3 SIO Functional Block Diagram 14 3 14 4 Serial I O Timing Transmit Receive Mode Tx at falling SIOCON 4 0 14 4 14 5 Serial I O Timing in Transmit Receive Mode Tx at rising SIOCON 4 1 14 4 14 6 Serial I O Timing in Receive Only Mode 14 5 15 1 UART Control Register UARTCON ee 15 3 15 2 UART Interrupt Pending Register UARTPND LB 15 4 15 3 UART Data Register UDATA wA AAA 15 5 15 4 UART Baud Rate Data Register BRDATAH BRDATAL mm 15 6 15 5 UART Functional Block Diagram A 15 8 15 6 Timing Diagram for UART Mode 0 Operation T AAA trey 15 9 15 7 Timing Diagram for UART Mode 1 Operation LL CA 15 10 15 8 Timing Diagram for UART Mode 2 Operation w AMAA A
35. C Vpp OV Input Capacitance f 1 MHz unmeasured pins 10 pF are tied to Output Capacitance Capacitance 20 2 ELECTRONICS S3C84H5 F84H5 Table 20 3 D C Electrical Characteristics TA 25 C to 85 2 5V to 5 5 V ELECTRICAL DATA Unit fx 0 8MHz fxt 32 8kHz V LVR off fx 0 8MHz fxt 32 8kHz LVR on Input High Voltage V Vpp 2 5V to 5 5 V Xin and XT jp Input Low Voltage Vpp 2 5V to 5 5 V V All Ports and nRESET Vpp 2 5V to 5 5 V Xin and XTN Output High Voltage V 2 mA All Ports Output Low Voltage Vpp 5 0 V 16 mA V Ports 0 and 4 Vpp 5 0 V Io 4 mA Ports 1 2 and 3 Input High Leakage Vin Input Low Leakage Current Output High Leakage Current Output Low Leakage Current 2214 ELECTRONICS All input pins except jjj Vin Xin and XT iq XT our Viso All input pins except and Xin and XTin XTour Voo All output pins Vout 0 V All output pins ELECTRICAL DATA Table 20 3 D C Electrical Characteristics Concluded TA 25 to 85 C Vpp 2 5V to 5 5 V S3C84H5 F84H5 kQ mA uA Pull up Resistor Rp4 5 0 25 50 100 25 All I O pins except nRESET Ta 25 RESETB only Supply Current 0 Ipp1 2 4 5 V to 5 5 5 0 10 RUN mode 10 MHz CPU clock
36. H W H W S W H W S W H W S W H W S W H W S W H W S W S W S W S W S W S W S W S W S W S W higher priority than DEH within the level IRQ5 the priorities within each level are set at the factory 2 External interrupts are triggered by a rising or falling edge depending on the corresponding control register setting 5 4 Figure 5 2 S3C84H5 F84H5interrupt Structure ELECTRONICS S3C84H5 F84H5 INTERRUPT STRUCTURE INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3C84H5 F84H5 interrupt structure are stored in the vector address area of the internal 16 Kbyte ROM see Figure 5 3 You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the ROM is 0100H HEX 16 383 3FFFH 16 Kbyte 0100H lt RESET Address 255 FFH Interrupt Vector address Area 0 00H Figure 5 3 ROM Vector Address Area ELECTRONICS 5 5 INTERRUPT STRUCTURE S3C84H5 F84H5 Table 5 1 Interrupt Vectors Vector Address Request Reset Clear Decimal Hex Interrupt Source Interrupt Priority in 100H Basic timer WDT overflow nRESET UART transmit IRQ7 ae 1 mgs seme wm ms
37. MSB Bit 7 LSB Bit 0 ELECTRONICS S3C84H5 F84H5 CONTROL REGISTER ADCON A D Converter Control Register F7H Set1 Bit Identifier Lm ose jus JL afa faao RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R R W R W R W Addressing Mode ELECTRONICS Register addressing mode only Not used for the S8C84H5 F84H5 must keep always 0 A D Input Pin Selection Bits End of Conversion Bit Read only EN A D conversion opration is in progress A D conversion opration is complete 0 fxx 4 1 Not used Start or Enable Bit EN Disable operation 1 Start operation CONTROL REGISTERS S3C84H5 F84H5 BTCON Basic Timer Control Register D3H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Watchdog Timer Function Disable Code for System Reset 1 0 1 0 Disable watchdog timer function Other Vaules Enable watchdog timer function 3 2 Basic Timer Input Clock Selection Bits fxx 4096 9 fxx 1024 fxx 128 fxx 1 Not used 4 Basic Timer Counter Clear Bit 1 EN No effect Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer 2 EN No effect Clear both clock frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to 00H Immediately following the write operation the BTCON 1 value is automatically cle
38. NOTE When the case of select the fxx 128 for basic timer input clock before enter the stop mode tWAIT 128 x 16 x 1 32768 62 5 ms Figure 20 6 Stop Mode Sub Release Timing Initiated by Interrupts ELECTRONICS 20 9 ELECTRICAL DATA S3C84H5 F84H5 Table 20 10 UART Timing Characteristics in Mode 0 10 MHz TA 25 C to 85 2 5V to 5 5 V Load capacitance 80 pF Output data hold after clock rising edge Input data hold after clock rising edge NOTES 1 All timings are in nanoseconds ns and assume a 10 MHz CPU clock frequency 2 The unit tecpy means one CPU clock period Figure 20 7 Waveform for UART Timing Characteristics 20 10 ELECTRONICS S3C84H5 F84H5 ELECTRICAL DATA Table 20 11 A D Converter Electrical Characteristics TA 25 to 85 C 2 5V to 5 5 V Vss 0 Total accuracy Lee Vpp 5 12V LSB Integral linearity CPU clock 10 MHz 2 error AVggr 5 12 V Differential linearity AVss error Offset error of top Offset error of bottom Conversion time 1 10 bit us Analog input V voltage Analog input RAN 1000 MO impedance Analog reference 2 5 voltage Nm Analog input lADIN AVngr 5 pA current conversion time 20 us Analog block lADC AVREF 5V mA current 2 conversion time 20 us AVggr V convers
39. No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc Src dst 2 14 F3 Irr r Examples Given RO R6 21H and R7 OFFH LDCPI RR6 RO RR6 lt DRRG 1 the contents of RO is loaded into program memory location 2200H 21FFH 1H RO 7FH R6 22H R7 00H LDEPI RR6 RO RR6 lt DRRG 1 the contents of RO is loaded into external data memory location 2200H 21FFH 1H RO 7FH R6 22H R7 00H NOTE LDEPI instruction can be used to read write the data of 64 Kbyte data memory ELECTRONICS 6 57 INSTRUCTION SET LDW Load word LDW Operation Flags Format Examples dst src dst lt src S3C84H5 F84H5 The contents of the source a word are loaded into the destination The contents of the source are unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 C4 RR RR 8 C5 RR IR opc dst src 4 8 C6 RR IML Given R4 06H R5 1CH R6 05H R7 02H register OOH register 01H 02H register 02H 03H and register 03H OFH LDW LDW LDW LDW LDW LDW RR6 RR4 gt 00H 02H gt RR2 R7 gt 04H 01H gt RR6 1234H gt 02H 0FEDH gt R6 06H R7 1CH R4 06H R5 1CH Register OOH 03H register 01H OFH register 02H 03H register 03H R2 03H OFH Register 04H 03H reg
40. Selector A 32768Hz Circuit fx 256 fx Main System Clock 9 8304 2 Subsystem Clock 32768 Hz fw Watch timer Figure 17 1 Watch Timer Circuit Diagram ELECTRONICS 17 3 WATCH S3C84H5 F84H5 PROGRAMMING TIP Using the Watch Timer ORG 0000h VECTOR OD6h WT INT ORG 0100h INITIAL DI SB1 Extra command only for debugging 1016 LD 7 Extra command only for debugging 1016 SBO Extra command only for debugging te LD IMR 00010000b Enable IRQ3 interrupt LD SPH 00000000b Set stack area LD SPL 0FFh LD BTCON 1010001 1b Disable Watch dog LD WTCON 11001110b 0 5 kHz buzzer 1 955ms duration interrupt Interrupt enable fxt 32 768Hz El MAIN MAIN ROUTINE JR T MIAN WT_INT AND WTCON 11111110b pending clear IRET END NOTE In debug mode you have to include three extra commands in initial routine to operate Ports correctly If you omit these commands Port do not operate correctly After you have finished your program and before assembling you have to remove these three commands 17 4 ELECTRONICS S3C84H5 F84H5 LOW VOLTAGE RESET LOW VOLTAGE RESET OVERVIEW The 53 84 5 84 can be reset in four ways by external power on reset by the external reset input pin pulled low by the digital watchdog timing out by the Low Voltage reset circuit LVR During an external power on reset the voltage VDD is High level
41. contains overview tables for all mapped system and peripheral control register values as well as detailed one page descriptions in a standardized format You can use these easy to read alphabetically organized register descriptions as a quick reference source when writing programs Chapter 5 Interrupt Structure describes the 53084 5 84 5 interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part Il Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S3C8 series microcontrollers Several summary tables are presented for orientation and reference Detailed descriptions of each instruction are presented in a standard format Each instruction description includes one or more practical examples of how to use the instruction when writing an application program A basic familiarity with the information in Part will help you to understand the hardware module descriptions in Part Il If you are not yet familiar with the S3C8 series microcontroller family and are reading this manual for the first time we recommend that you first read Chapters 1 3 carefully Then briefly look over the detailed information in Chapters 4 5 and 6 Later you can reference the information in Part as necessary Part Il hardware Descriptions has detailed information about specific hardware components of the S3C84H5 F84H5 mic
42. data bit that was received in UART mode 2 0 or 1 If Parity enable mode PEN 1 even odd parity selection bit for receive data in UART mode 2 0 Even parity check for the received data 1 Odd parity check for the received data A result of parity error will be saved in RPE bit of the UARTPND register after parity checking of the received data CONTROL REGISTERS S3C84H5 F84H5 UARTCON UART Contro Register Continued F6H 0 Bit Identifier RESET Value Read Write 1 Receive interrupt enable bit 0 Disable Receive interrupt 1 Enable Receive interrupt 0 Transmit interrupt enable bit Disable Transmit interrupt 1 Enable Transmit Interrupt NOTES 1 In mode 2 if the MCE UARTCON 5 bit is set to 1 then the receive interrupt will not be activated if the received gth data bit is 0 In mode 1 if MCE 1 then the receive interrupt will not be activated if a valid stop bit was not received In mode 0 the MCE UARTCON 5 bit should be 2 The descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and transmit e Parity enable bits PEN are located in the UARTPND register at address bank 0 4 Parity enable and parity error check can be available in 9 bit UART mode Mode 2 only 4 36 ELECTRONICS S3C84H5 F84H5 CONTROL REGISTER UARTPND uanT Pending and parity control FAH Set1 Bit Id
43. location 0104H RR2 RO R2 R3 nochange 11H contents of RO is loaded into external data memory location 0104H RR2 RO R2 R3 nochange RO lt contents of program memory location 0105H 01H RR2 RO 6DH R2 01H R3 04H RO lt contents of external data memory location 0105H 01H RR2 RO R2 01H R3 04H 11H contents of RO is loaded into program memory location 0105H 01H 0104H 11H contents of RO is loaded into external data memory location 0105H 01H 0104H RO lt contents of program memory location 1104H 1000H 0104H RO 88H R2 01H R3 04H RO lt contents of external data memory location 1104H 1000H 0104H RO 98H R2 01H R3 04H RO lt contents of program memory location 1104H RO 88H RO lt contents of external data memory location 1104H RO 98H 11H contents of RO is loaded into program memory location 1105H 1105H lt 11H 11H contents of RO is loaded into external data memory location 1105H 1105H lt 11H NOTE The LDC and the LDE instructions are not supported by masked ROM type devices ELECTRONICS 6 53 INSTRUCTION SET S3C84H5 F84H5 LDCD LDED Load Memory and Decrement LDCD dst src LDED dst src Operation dst lt src r lt rr 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a work
44. the basic timer counter will increase at the rate of fxx 4096 If an external interrupt is used to release stop mode the BTCNT value increases at the rate of the preset clock source Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows When a 4 overflow occurs normal CPU operation resumes ELECTRONICS 10 3 BASIC S3C84H5 F84H5 Bit 1 RESET or STOP Bits 3 2 Basic Timer Control Register Write 1010xxxxB to disable fxx 4096 fxx 1024 8 Bit Up Counter BTCNT Read Only fxx 128 m Start the CPU note Bit 0 NOTE During a power on reset operation the CPU is idle during the required oscillation stabilization interval until bit 4 of the basic timer counter overflows Figure 10 2 Basic Timer Block Diagram 10 4 ELECTRONICS S3C84H5 F84H5 8 BIT TIMER A B 8 BIT TIMER A B 8 BIT TIMER A OVERVIEW The 8 bit timer A is an 8 bit general purpose timer counter Timer A has three operating modes you can select one of them using the appropriate TACON setting Interval timer mode Toggle output at TAOUT pin Capture input mode with a rising or falling edge trigger at the TACAP pin PWM mode TAPWM Timer A has the following functional components Clock frequency divider fxx divided by 1024 256 or 64 with multiplexer External clock input pin TACK 8 bit counter 8 bit comparator and 8 bit reference data
45. 1 3 1 12 ELECTRONICS S3C84H5 F84H5 PRODUCT OVERVIEW VDD Pull up Resistor Typical Value 50kQ Pull up Enable O gt jP VDD Port Data M Alternative output In Out Output Disable Normal Input Analog Input O Figure 1 9 Pin Circuit E P2 2 P2 3 P1 4 1 5 ELECTRONICS 1 13 PRODUCT OVERVIEW S3C84H5 F84H5 Open Drain P Channel Data Output N Channel Disable Figure 1 10 Pin Circuit Type G P3 0 P3 4 1 14 ELECTRONICS S3C84H5 F84H5 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3C84H5 F84H5 microcontroller has two types of address space Internal program memory ROM Internal register file RAM A 16 bit address bus supports program memory operations A separate 8 bit register bus carries addresses and data between the CPU and the register file The S3C84H5 F84H5 has an internal 16 Kbyte mask programmable ROM 16 Kbyte Flash ROM and 272 byte RAM ELECTRONICS 2 1 ADDRESS SPACES S3C84H5 F84H5 PROGRAM MEMORY ROM Program memory ROM stores program codes or table data The S3C84H5 F84H5 has 16 Kbytes of internal mask programmable program memory The program memory address range is therefore OH 3FFFH see Figure 2 1 The first 256 bytes of the ROM 0H OFFH are reserved for interrupt vector addresses Unused locations in this address range can be used as normal program memory If you use the vector address are
46. 12 4 Bit Working Register Addressing RP1 Selects RPO R6 OPCODE Register Instructi 01110 110 address 0110 1110 INC RS 76H Figure 2 13 4 Bit Working Register Addressing Example ELECTRONICS 2 17 ADDRESS SPACES S3C84H5 F84H5 8 BIT WORKING REGISTER ADDRESSING You can also use 8 bit working register addressing to access registers in a selected working register area To initiate 8 bit working register addressing the upper four bits of the instruction address must contain the value 1100 This 4 bit value 1100B indicates that the remaining four bits have the same effect as 4 bit working register addressing As shown in Figure 2 13 the lower nibble of the 8 bit address is concatenated in much the same way as for 4 bit addressing Bit 3 selects either RPO or RP1 which then supplies the five high order bits of the final address The three low order bits of the complete address are provided by the original instruction Figure 2 14 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 3 1 selects RP1 and the five high order bits in RP1 10101 become the five high order bits of the register address The three low order bits of the register address 011 are provided by the three low order bits of the 8 bit instruction address The five address bits from RP1 and the three address bits from the instruction are
47. 4 ELECTRONICS Register addressing mode only Not used for the 53 8418 8419 must keep always 0 Main System Oscillator Control Bit Main System Oscillator RUN Main System Oscillator STOP 1 Sub System Oscillator Control Bit Sub system oscillator RUN 1 Sub system oscillator STOP Not used for the S3C84H5 F84H5 must keep always 0 System Clock Selection Bit Main oscillator select 1 Subsystem oscillator select 4 1 CONTROL REGISTERS S3C84H5 F84H5 POCON Port Contro Register High Byte E6H Set RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P0 3 AD3 Configration Bits Input mode Input mode with pull up 1 0 Push pull output mode Alternative function mode AD3 input 5 4 3 2 0 0 Input mode 0 1 Input mode with pull up 1 Push pull output mode EHE Alternative function mode AD1 input 1 0 ADO Configration Bits 0 0 Input mode 0 1 Input mode with pull up Push pull output mode Alternative function mode ADO input NOTE debug mode you have to include three extra commands in initial routine to operate Ports correctly If you omit these commands Port do not operate correctly Reter to page 9 14 After you have finished your program and before assembling you have to remove these three commands ORG 100H SB1 Extra command only
48. 4 FF Example When the instruction NOP is executed in a program no operation occurs Instead there happens a delay in instruction execution time which is of approximately one machine cycle per each NOP instruction encountered ELECTRONICS 6 61 INSTRUCTION SET S3C84H5 F84H5 Logical OR OR Operation Flags Format Examples dst src dst lt dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination The contents of the source are unaffected The OR operation results in a 1 being stored whenever either of the corresponding bits in the two operands is a 1 otherwise a 0 is stored C Unaffected Z Setifthe result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 42 r r 6 43 r Ir opc src dst 3 6 44 R R 45 R IR opc dst src 3 6 46 R IM Given RO 15H R1 2AH R2 01H register 00H 08H register 01H 37H and register 08H 8AH OR RO R1 gt RO 3FH R1 2AH OR RO R2 gt RO 37H R2 01H register 01H 37H OR 00H 01H gt Register 00H register 01H 37H OR 01 000 gt Register 08H register 01H OR 00H 02H gt Register OOH OAH In the first example if the working register RO contains the value 15H and the regist
49. 7 to alternative function RXD P2 6 TXD P2 7 for UART module by setting the P1CONH register to appropriatly value Load an 8 bit value to the UARTCON control register to properly configure the UART 1 module For parity generation and check in UART mode 2 set parity enable bit UARTPND 5 to 1 For interrupt generation set the UART interrupt enable bit UARTCON 1 or UARTCON O to 1 When you transmit data to the UART buffer write transmit data to UDATA the shift operation starts When the shift operation transmit receive is completed UART pending bit UARTPND 1 or UARTPND 0O is set to 1 and an UART interrupt request is generated Par OD ELECTRONICS 14 1 UART UART CONTROL REGISTER UARTCON S3C84H5 F84H5 The control register for the UART is called UARTCON at address F6H It has the following control functions Operating mode and baud rate selection Multiprocessor communication and interrupt control Serial receive enable disable control 9th data bit location for transmit and receive operations mode 2 Parity generation and check for transmit and receive operations mode 2 UART transmit and receive interrupt control A reset clears the UARTCON value to 00H So if you want to use UART module you must write appropriate value to UARTCON 15 2 ELECTRONICS S3C84H5 F84H5 UART UART Control Register UARTCON F6H Set1 Bank 0 R W Reset Value 00H wo ps peo wes se s s e s O
50. Complete Set SIOCON 3 Figure 14 5 Serial I O Timing in Transmit Receive Mode Tx at rising SIOCON 4 1 14 4 ELECTRONICS S3C84H5 F84H5 SERIAL I O INTERFACE ot LMALI LIL UU UU Data Output m IRQS Start 2 Figure 14 6 Serial I O Timing Receive Only Mode 5 PROGRAMMING SIO ORG 0000H VECTOR _ OOH INT_SIO ORG 0100H INITIAL DI SB1 Extra command only for debugging LD OF7H 5FH Extra command only for debugging SBO Extra command only for debugging LD BTCON 10100010B Watch dog disable LD CLKCON 00011000B non divided CPU clock LD SPL 00H LD 2 10101111B 5 setting LD P2CONL 00101010B LD SIOCON 00100110B Enable SIO Interrupt LD SIOPS 420 setting baud rate EI ELECTRONICS 14 5 SERIAL I O INTERFACE 59 PROGRAMMING TIP SIO Continued MAIN CALL JP SUB SIO LD OR RET INT_SIO AND IRET NOTE 14 6 SUB_SIO MAIN SIODATA TRANSBUF SIOCON 00001000B SIOCON 11111110 Data transmit routine 1 byte transmission Shift start 8 bit transmit Pending bit clear S3C84H5 F84H5 In debug mode you have to include three extra commands in initial routine to operate Ports correctly If you omit these commands Port do not operate correctly After you have finished your program and before assembling you have to remove these three commands ELECTRONICS S3C84H5 F84H5 UART UART OVERVIEW The UAR
51. DIV Divide Unsigned DIV Operation Flags Format Examples dst src dst src dst UPPER lt REMAINDER dst LOWER QUOTIENT The destination operand 16 bits is divided by the source operand 8 bits The quotient 8 bits is stored in the lower half of the destination The remainder 8 bits is stored in the upper half of the destination When the quotient is gt 28 the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect Both operands are treated as unsigned integers C Set if the V flag is set and the quotient is between 28 and 29 4 cleared otherwise Z Setif the divisor or the quotient 0 cleared otherwise S Set if MSB of the quotient 1 cleared otherwise V Setif the quotientis gt 28 or if the divisor 0 cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Given RO 10H R1 03H R2 40H register 40H 80H DIVRRO R2 gt RO R1 40H DIVRRO R2 gt RO R1 20H DIVRRO 20H gt RO 03H R1 80H In the first example the destination working register pair RRO contains the values 10H RO and R1 and the register R2 contains the value 40H The statement DIV RRO R2 div
52. DOH Set 1 Bit Identifier 2 j s 5 2 3 9 RESET VALUE 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Timer Input Clock Selection Bits 0 fxx 4 1 fxx 8 opea 5 4 Timer B Interrupt Time Selection Bits Elapsed time for low data value fo 1 Elapsed time for high data value 1 0 Elapsed time for low and high data values 1 1 Not Used 3 Timer B Interrupt Enable Bit Disable Interrupt Enable Interrupt 2 Timer B Start Stop Bit Stop timer Start timer B 1 Timer B Mode Selection Bit 0 One shot mode 1 Repeating mode 0 Timer B Output flip flop Control Bit 0 T FF is low T FF is high NOTE fxxis selected clock for system ELECTRONICS 4 33 CONTROL REGISTERS S3C84H5 F84H5 TINTPND Timer A Timer 1 Interrupt Pending Register EOH Set1 Bank1 Bit Identifier 7 5 4 3 2 3 9 RESET VALUE 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Not used for the S3C84H5 F84H5 must keep always 0 5 Timer 1 1 Overflow Interrupt Pending Bit 0 No interrupt pending ES Clear pending bit when write Interrupt pending 4 Timer 1 1 Match Capture Interrupt Pending Bit 0 No interrupt pending 0 Clear pending bit when write Interrupt pending 3 Timer 1 0 Overflow Interrupt Pendin
53. Enable un mask 0 Interrupt Level 0 IRQO Enable Bit Disable mask 1 Enable un mask NOTE When an interrupt level is masked any interrupt requests that may be issued are not recognized by the CPU ELECTRONICS 4 CONTROL REGISTERS S3C84H5 F84H5 IPH instruction Pointer High Byte DAH Set 1 RESET VALUE X X X X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address High Byte The high byte instruction pointer value is the upper eight bits of the 16 bit instruction pointer address IP15 IP8 The lower byte of the IP address is located in the IPL register DBH IPL instruction Pointer Low Byte DBH Set 1 RESET VALUE Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is the lower eight bits of the 16 bit instruction pointer address IP7 IPO The upper byte of the IP address is located in the IPH register DAH 4 10 ELECTRONICS S3C84H5 F84H5 CONTROL REGISTER IPR Interrupt Priority Register FFH Set1 RESET Value X X X X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 and 1 Priority Control Bits for Interrupt Groups A B and C Group priority undefined 1 Group priority undefined
54. Enable Interrupt Falling Edge 11 Enable Interrupt Rising Edge 5 4 P1 2s Interrupt Enable Disable Selection Bit OX Disable Interrupt 10 Enable Interrupt Falling Edge 11 Enable Interrupt Rising Edge 3 2 P1 1 s Interrupt Enable Disable Selection Bit OX Disable Interrupt 10 Enable Interrupt Falling Edge 11 Enable Interrupt Rising Edge 1 0 P1 0 s Interrupt Enable Disable Selection Bit OX Disable Interrupt 10 Enable Interrupt Falling Edge 11 Enable Interrupt Rising Edge Figure 9 5 Port 1 Interrupt Enable Register PORT 2 Port 2 is an 8 bit I O port with individually configurable pins Port 2 pins are accessed directly by writing or reading the port 2 data register P2 at location E2H in set 1 bank 0 2 0 2 7 can serve as digital inputs outputs push pull or you can configure the following alternative functions General purpose digital I O Ilternative function ADC4 ADC7 SI TTICAPO T1OUT1 T1CKO TBPWM PWM Port 2 Control Register P2CONH P2CONL Port 2 has two 8 bit control registers 2 for 2 4 2 7 P2CONL for 2 0 2 3 A reset clears the P2CONH and P2CONL registers to OOH configuring all pins to input mode You use control registers settings to select input or output mode push pull and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using t
55. IDLE LED 11 This LED is ON when the evaluation chip 53 8410 is in idle mode STOP LED This LED is ON when the evaluation chip 53 8410 is in stop mode 22 4 Connector from External Trigger Sources of the Application System You can connect an external trigger source to one of the two external trigger channels CH1 or CH2 for the SMDS2 breakpoint and trace functions ELECTRONICS S3C84H5 F84H5 INTO TAOUT P1 0 INT1 BUZ TACK P1 1 INT2 TACAP P1 2 INTS T1OUT1 P1 3 VDD VSS XOUT XIN TEST Xtin Xtout nRESET TBPWM T1CKO P2 0 T1CAPO PWM P2 1 T1OUTO AD4 P2 2 AD5 T1CK1 P1 4 T1CAP1 AD6 P1 5 SI AD7 P2 3 SO P2 4 SCK P2 5 Rx P2 6 TX P2 7 J102 WD 1352068 Nid vv Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used P3 3 P3 2 P3 1 P3 0 P0 3 AD3 P0 2 AD2 P0 1 AD1 P0 0 ADO Avss Avref Figure 22 3 44 Pin Connector pin assignment for TB84H5 ELECTRONICS DEVELOPMENT TOOLS 22 5 DEVELOPMENT TOOLS S3C84H5 F84H5 Not used Not used Not used Not used Not used Not used INTO TAOUT P1 0 INT1 BUZ TACK P1 1 INT2 TACAP P1 2 Not used Not used Not used Not used Not used Not used P3 3 P3 2 P3 1 P3 0 AD2 P0 2 AD1 P0 1 Xin 0 5 55 XTin AVref XTout P2 7 TxD nRESE
56. IRQ amp interrupt Figure 5 6 Interrupt Mask Register IMR ELECTRONICS 5 11 INTERRUPT STRUCTURE S3C84H5 F84H5 INTERRUPT PRIORITY REGISTER IPR The interrupt priority register IPR set 1 bank 0 FFH is used to set the relative priorities of the interrupt levels in the microcontroller s interrupt structure After a reset all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine When more than one interrupt sources are active the source with the highest priority level is serviced first If two sources belong to the same interrupt level the source with the lower vector address usually has the priority This priority is fixed in hardware To support programming of the relative interrupt level priorities they are organized into groups and subgroups by the interrupt logic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 GroupA IRQO IRQ1 GroupB 2 IRQ4 Group C IRQ5 IRQ6 IRQ7 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relative priority of interrupt groups A B and C For example the setting 001B for these bits would select the group relationship gt gt A The setting 101B would select the relationship C gt B gt A The functions of the ot
57. Input Output Capacitance 20 2 D C Electrical Characteristics 20 3 Electrical Characteristics pe 20 5 Main Oscillator Frequency M 20 6 Oscillator Clock Stabilization Time 485485 3558858 88888 ceed 885 C 48 ET I E E 20 6 Sub Oscillator Frequency fosce Peer ree 20 7 Subsystem Oscillator crystal Stabilization Time tero ttre 20 7 Data Retention Supply Voltage in Stop Mode 20 8 UART Timing Characteristics in Mode 0 10 MHz 20 10 A D Converter Electrical Characteristics 5 45548 5 6 685488888854458485 8544 EC CED rr nor 20 1 1 LVR Low Voltage Reset Circuit Characteristics 5 55 85 488858 8 8 20 12 Power Selection Settings for TB84H5 22 4 Using Single Header Pins as the Input Path for External Trigger Sources 7 22 4 S3C84H5 F84H5 MICROCONTROLLER List of Programming Tips Description Chapter 2 Address Spaces Using the Page Pointer for RAM Setting the Register Pointers OCOD OC OTC EEC DCC CORE CE
58. Instructions Value used in OPERAND Instruction CALL RR2 JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory 3 4 ELECTRONICS S3C84H5 F84H5 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE Continued Register File MSB Points to RPO or RPO or Selected RP points Program Memory to start fo 4 bit working register Worki block orking 1 Register dst Address OPCODE Point to the Working Register 1 of 8 ADDRESS Sample Instruction Value used OPERAND OR R3 R6 Instruction Figure 3 5 Indirect Working Register Addressing to Register File ELECTRONICS 3 5 ADDRESSING MODES S3C84H5 F84H5 INDIRECT REGISTER ADDRESSING MODE Continued Register File MSB Points to RPO or RPO or RP1 Selected RP points to start of ki Program Memory foal ao 4 bit Working block Register Address dst SIC Register OPCODE Next 2 bit Point Pair Example Instruction to Working References either Register Pair Program Memory or 1 of 4 Data Memory 16 Bit address LSB Selects Program Memory points to or program Data Memory memory or data memory Value used in Instruction OPERAND Sample Instructions LCD R5 RR6 Program memory access LDE R3 RR14 External data memory access LDE RR4 R8 External data memory access Figure 3 6 Indirect Working Register Addressing to Pro
59. LD 00H 02H LD RO LOOP R1 LD LOOP RO R1 6 50 144414444144 14 02H LOOP register OFFH RO 10H RO 20H register 01H 20H Register 01H 01H RO 01H R1 20H RO 01H RO 01H R1 OAH register 01H Register OOH 20H register 01 Register 02 20H register Register OOH OAH Register OOH 01H register 01H Register OOH 01H register 01H register 02H 02H RO OFFH R1 Register OAH RO 01H R1 S3C84H5 F84H5 OAH 20H 01H 10H 02 OAH ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET LDB Load Bit LDB dst src b LDB dst b src Operation 4610 lt src b dst b lt 0 The specified bit of the source is loaded into bit zero LSB of the destination or bit zero of the source is loaded into the specified bit of the destination No other bits of the destination are affected The source is unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst sre opc dst b 0 src 3 6 47 ro Rb opc src b 1 dst 3 6 47 Rb ro NOTE Inthe second byte of the instruction format the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Examples Given RO 06H and general register 05H LDB R0 00H 2 RO register 05 LDB 00H 0 RO gt RO 06H register
60. POP POP AND AND AND AND AND BITC R1 IR1 1 2 1 12 R2 R1 IR2 R1 R1 IM r1 b N 6 COM COM TCM TCM TCM TCM TCM BAND R1 IR1 1 2 r1 Ir2 R2 R1 IR2 R1 R1 IM rO Rb 7 5 PUSH BIT R2 IR2 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b B 8 DECW DECW PUSHUD PUSHUI MULT MULT MULT LD RR1 IR1 IR1 R2 IR1 R2 R2 RR1 IR2 RR1 IM RR1 r1 x r2 B 9 RL RL POPUD POPUI DIV DIV DIV LD R1 IR1 IR2 R1 IR2 R1 R2 RR1 IR2 RR1 IM RR1 r2 x r1 L A INCW INCW CP CP CP CP CP LDC RR1 IR 1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 Irr2 xL E B CLR CLR XOR XOR XOR XOR XOR LDC R1 IR1 1 2 r1 Ir2 R2 R1 IR2 R1 R1 IM r2 Irr2 xL RRC RRC CPIJE LDC LDW LDW LDW LD R1 IR1 Ir r2 RA r1 Irr2 RR2 RR1 IR2 RR1 RR1 IML r1 Ir2 H D SRA SRA CPIJNE LDC CALL LD LD R1 IR1 Irr r2 RA 2 1 1 IR1 IM Ir1 r2 E E RR RR LDCD LDCI LD LD LD LDC R1 IR1 r1 Irr2 r1 Irr2 R2 R1 R2 IR1 R1 IM r1 Irr2 xs X F SWAP SWAP LDCPD LDCPI CALL LD CALL LDC R1 IR1 r2 Arr r2 lrr1 IRR1 IR2 R1 DA1 r2 Irr1 xs 6 10 ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET Table 6 5 OPCODE Quick Reference Continued OPCODE MAP LOWER NIBBLE HEX 8 9 C D E F U 0 LD LD DJNZ JR LD JP INC NEXT r1 R2 r2 R1 r1 RA 1 cc DA r1 3 ENTER 2 3 WFI R 4 SBO 5 SB1 N 6 IDLE 7 1 0 STOP B 8 DI B 9 EI L A RET E B IRET C RCF H D i
61. Port 2 control register high byte P2CONH 234 ECH o 9 9 Port 2 control register low byte P2CONL 235 EDH O Location EEH is not mapped Port 3 control register low byte P3CONL 239 01010101010 010 Location F1H is not mapped Oscilatorcontrolregister OSCCON wa EM 0 0 000 Location is not mapped eS eee UART data register UDATA 245 F5H UART control register UARTCON 246 F6H A D converter control register ADCON IHE A D converter data register high byte ADDATAH 248 F8H A D converter data register low byte ADDATAL 249 F9H 0 0 Port 2 pull up enable control register P2PUR 250 Location FBH is mapped OoOjoilojojo j jo Location FCH is factory use only Basic timer counter register BTCNT 253 0 0 0 0 1010 010 Location FEH is not mapped ELECTRONICS 8 3 RESET and POWER DOWN S3C84H5 F84H5 Table 8 3 S3C84H5 F84H5 Set 1 Bank 1 Register values after RESET Bit values after Reset Register Name Mnemonic Dec Hex Timer A 1 interrupt pending register 224 Timer A control register TACON 225 Timer A data register Timer counter register high byte T1DATAHO ow byte T1DATALO Timer 1 0 dat
62. Range 20 12 20 9 The Circuit Diagram to Improve EFT Characteristics mmm 20 13 21 1 32 SOP 450A Package Dimensions 21 1 21 2 32 SDIP 400 Package Dimensions 21 2 21 3 30 Pin SDIP Package Dimensions 21 3 21 4 28 5 375 Dimensions PPP ere reer eee eter reer 21 4 22 1 SMDS or 5 1000 Product Configuration 22 2 22 2 S3F8419 53 8418 53 84 5 Target Board Configuration 22 3 22 3 44 Connector pin assignment for TB84H5 eee eee eee eee ee eee eee eee ee eee eee 22 5 22 4 42 Pin Connector Pin Assignment for TB84Hb 22 6 22 5 TB84H5 Adapter Cable for 44pin Connector Package TAM 22 6 xiv S3C84H5 F84H5 MICROCONTROLLER Table Number 1 1 1 2 2 1 4 1 4 2 4 3 5 1 5 2 5 3 6 1 6 2 6 3 6 4 6 5 6 6 8 1 8 2 8 3 9 1 13 1 13 2 15 1 17 1 19 1 19 2 List of Tables Title N S3C84H5 F84H5 P
63. Reference Voltage Input Analog Input Pin NOTE The symbol signifies an offset resistor with a value of from 50 to 1000 Figure 16 5 Recommended A D Converter Circuit for Highest Absolute Accuracy ELECTRONICS AVref ADCO ADC7 S3C84H5 S3F84H5 AVss Vss A D CONVERTER Configure P0 0 P0 3 P1 4 P1 5 P2 2 P2 3 for analog input before A D conversions To do this you load the appropriate value to the POCONL P1CONH P2CONL for ADCO ADC7 registers Before the conversion operation starts you must first select one of the eight input pins ADCO ADC7 by writing the appropriate value to the ADCON register When conversion has been completed 50 clocks have elapsed the EOC ADCON 3 flag is set to 1 so The converted digital value is loaded to the output register ADDATAH 8 bit and ADDATAL 2 bit then the A D CONVERTER S3C84H5 F84H5 PROGRAMMING TIP Configuring A D Converter SB1 Extra command only for debugging 7019 LD 7 Extra command only for debugging 1016 SBO Extra command only for debugging 1016 LD POCON 11111111B PO 0 PO 3 A D Input MODE LD P1CONH 00001111B P1 4 P1 5 A D Input MODE LD P2CONL 11110000B P2 2 P2 3 A D Input MODE LD ADCON 400000001B Channel ADCO Conversion start ADO CHK TM ADCON 00001000 A D conversion end EOC check JR Z ADO CHK No LD ADOBUFH ADDATAH 8 bit Conversion data LD ADOBUFL ADD
64. a gate and loads the current counter value into the timer 1 data registers T1DATAHO T1DATALO for rising edge or falling edge You can select rising or falling edge to trigger this operation The timer 1 0 also gives you capture input source the signal edge at the T1CAPO pin You select the capture input by setting the value of the timer 1 0 capture input selection bit in the port 0 control register high POCONH set 1 0 Both kinds of timer 1 0 interrupts 1 T1INTO can be used in capture mode the timer 1 0 overflow interrupt is generated whenever a counter overflow occurs the timer 1 0 capture interrupt is generated whenever the counter value is loaded into the timer 1 data register By reading the captured data value in TIDATAHO T1DATALO and assuming a specific value for the timer 1 0 clock frequency you can calculate the pulse width duration of the signal that is being input at the T1CAPO pin In capture mode for Timer 1 1 a signal edge that is detected at the T1CAP1 pin opens a gate and loads the current counter value into the timer 1 data register T1DATAH1 T1DATAL1 for rising edge or falling edge You can select rising or falling edges to trigger this operation The timer 1 1 also gives you capture input source the signal edge at the T1CAP1 pin You select the capture input by setting the value of the timer 1 1 capture input selection bit in the port 0 control register low POCONL set 1 bank0 E
65. and the nRESET pin is forced Low level The nRESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock This brings the S3C84H5 F84H5 into a known operating status To ensure correct start up the user should take that reset signal is not released before the VDD level is sufficient to allow MCU operation at the chosen frequency The nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal CPU clock oscillation to stabilize The minimum required oscillation stabilization time for a reset is approximately 6 55 ms z218 fosc fosc 10MHz When a reset occurs during normal operation with both VDD and nRESET at High level the signal at the nRESET pin is forced Low and the reset operation starts All system and peripheral control registers are then set to their default hardware reset values see Table 8 1 The MCU provides a watchdog timer function in order to ensure graceful recovery from software malfunction If watchdog timer is not refreshed before an end of counter condition overflow is reached the internal reset will be activated The S3C84H5 F84H5 has built in low voltage reset circuit that allows detection of power voltage drop of external Vpp input level to prevent a MCU from malfunctioning in an unstable MCU power level This voltage detector works for the reset operation of MCU This Low Voltage reset
66. bit 0 No effect 1 Clear the timer A counter when write NOTE When th counter clear bit 3 is set the 8 bit counter is cleared and it also is cleared automatically Figure 11 1 Timer A Control Register TACON ELECTRONICS 11 3 8 S3C84H5 F84H5 BLOCK DIAGRAM TACON 2 TACON 7 6 Overflow Data Bus Pending TACON O TINTPND 1 f xx 1024 fxx 256 ue 8 bit Up Counter fxx 64 U Read Only gt X TACK TAINT 8 bit Comparator 0 Timer A Buffer Reg TAOUT TAPWM 5 4 Timer Data Register 5 4 Read Write Data Bus NOTES 1 When PWM mode match signal cannot clear counter 2 Pending bit is located at TINTPND register Figure 11 2 Timer A Functional Block Diagram 11 4 ELECTRONICS S3C84H5 F84H5 8 BIT TIMER A B 8 BIT TIMER B OVERVIEW The S3C84H5 F84H5 micro controller has an 8 bit timer called timer B Timer B which can be used to generate the carrier frequency of a remote controller signal Also it can be used as the programmable buzz signal generator that makes a sound with a various frequency from 200Hz to 20KHz These various frequencies can be used to generate a melody sound Timer B has two functions Asa normal interval timer generating a timer B interrupt at programmed time intervals ge
67. bit UARTCON 2 while the stop bit is ignored The baud rate for mode 2 is fosc 16 x 16bit BRDATA 1 clock frequency lt In parity enable mode PEN 1 gt The 9th data bit to be transmitted can be an automatically generated parity of 0 or 1 depending on a parity generation by means of TB8 bit UARTCON 3 When receiving the received 9th data bit is treated as a parity for checking receive data by means of the RB8 bit UARTCON 2 while the stop bit is ignored The baud rate for mode 2 is fosc 16 16bit BRDATA 1 clock frequency Mode 2 Transmit Procedure 1 Select the baud rate generated by 16bit BRDATA 2 Select mode 2 9 bit UART by setting UARTCON bits 6 and 7 to Also select the 9th data bit to be transmitted by writing TB8 to 0 or 1 and set PEN bit of UARTPND register to 0 if you don t use a parity mode If you want to use the parity enable mode select the parity bit to be transmitted by writing TB8 to 0 or 1 and set PEN bit of UARTPND register to 1 3 Write transmission data to the shift register UDATA F5H to start the transmit operation Mode 2 Receive Procedure 1 Select the baud rate to be generated by 16bit BRDATA 2 Select mode 2 and set the receive enable bit RE in the UARTCON register to 1 3 If you don t use a parity mode set PEN bit of UARTPND register to 0 to disable parity mode If you want to use the parity enable mode select the parity type to be check
68. concatenated to form the complete register address 10101011 Selects RPO Address CTT TT TTT address These address bits indicate 8 bit working register addressing Register pointer Three low order bits provides five high order bits 8 bit physical address Figure 2 14 8 Bit Working Register Addressing 2 18 ELECTRONICS S3C84H5 F84H5 ADDRESS SPACES Selects RP1 R11 8 bit address Register 1100 011 form instruction 10101 011 address 10 R11 R2 Specifies working register addressing Figure 2 15 8 Bit Working Register Addressing Example ELECTRONICS 2 19 ADDRESS SPACES S3C84H5 F84H5 SYSTEM AND USER STACK The S3C8 series microcontrollers use the system stack for data storage subroutine calls and returns The PUSH and POP instructions are used to control system stack operations The S3C84H5 F84H5 architecture supports stack operations in the internal register file Stack Operations Return addresses for procedure calls interrupts and data are stored on the stack The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction When an interrupt occurs the contents of the PC and the FLAGS register are pushed to the stack The IRET instruction then pops these values back to their original locations The stack address value is always decreased by one before a push operation and increased by on
69. even parity checking RB8 0 or the odd parity checking RB8 1 in the receive mode The parity enable generation checking functions are not available in UART mode 0 and 1 If you don t want to use a parity mode UARTCON 2 RB8 and UARTCON 3 TB8 are a normal control bit as the 9 data bit in this case PEN must be disable 0 in mode 2 Also it is needed to select the 9th data bit to be transmitted by writing TB8 to 0 or 1 The receive parity error flag RPE will be set to 0 or 1 depending on parity error whenever the 8 data bit of the receive data has been shifted UART DATA REGISTER UDATA UART Data Register UDATA F5H Set1 Bank 0 R W Reset Value FFH Transmit or Receive data Figure 15 3 UART Data Register UDATA ELECTRONICS 14 5 UART S3C84H5 F84H5 UART BAUD RATE DATA REGISTER BRDATAH BRDATAL The value stored in the UART baud rate register BRDATAH BRDATAL lets you determine the UART clock rate baud rate UART Baud Rate Data Register BRDATAH EEH Set1 Bank 1 R W Reset Value FFH BRDATAL Set Bank 1 R W Reset Value FFH Brud rate data Figure 15 4 UART Baud Rate Data Register BRDATAH BRDATAL BAUD RATE CALCULATIONS The baud rate is determined by the baud rate data register 16bit BRDATA Mode 0 baud rate fxx 16 x 16Bit BRDATA 1 Mode 1 baud rate fxx 16 x 16Bit BRDATA 1 Mode 2 baud rate fxx 16 x 16Bit BRDATA 1
70. input or push pull output Software assignable pull up resistor Alternately can be used as ADO AD3 P1 0 P1 5 Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up resistor Alternatively can be used as 0 TAOUT TACK TACAP T1CAP1 T1CK1 T1OUT1 AD5 AD6 ADCO ADC1 ADC2 ADC3 INTO INT3 TAOUT TACK TACAP T1CK1 T1CAP1 AD5 T1OUTI1 AD6 BUZ 10 13 18 21 AD7 16 19 SO SCK RxD 8 11 TxD T1CAPO 1 T1CKO PWM TBPWM P2 0 P2 7 I O Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up Alternately be used as ADCA4 ADC7 SI T1CAPO T1OUTO T1CKO SO SCK RxD TxD TBPWM PWM P3 0 P3 3 I O Bit programmable port input or output mode selected by software input or push pull N channel open drain output Software assignable pull up NOTE Pin numbers shown in parentheses are for the 28 pin SOP package 8 9 26 27 ELECTRONICS 1 7 PRODUCT OVERVIEW S3C84H5 F84H5 Table 1 1 S3C84H5 F84H5 Pin Descriptions Continued Pin Pin Circuit Type Description Type INTO INT3 Input pins for external interrupt 28 31 1 0 1 3 24 27 Alternatively used as general purpose digital input output port 1 ADCO ADC7 3 P2 2 P2 3 P1 4 P1 5 Analog input pins for A D converter module Alternatively used as general purpose digital
71. input output port 0 port1 and port 2 AVREF AVSS R Tx TACK 1 1 1 1 A D converter reference voltage and ground Serial data RxD pin for receive input and transmit output mode 0 Serial data TxD pin for transmit output and shift clock output mode 0 12 10 13 11 External clock input pins for timer A 25 TACAP Capture input pins for timer A TAOUT Pulse width modulation output pins for timer A Carrier frequency output pins for timer B xD D TBOUT i i T1CKO External clock input pins for timer 1 0 ins for timer 1 0 Capture input pins for timer 1 Timer 1 0 16 bit PWM mode output or counter match toggle output pins External clock input pins for timer 1 1 E Capture input pins 10 E Timer 1 1 16 bit PWM mode output or counter match toggle output pins resistor connected nternaly Fowrmune 1 0 BIN Main oscillator pins 20 22 D 5 E E E D 5 D 5 D 5 D 5 D 5 D 5 D 5 E T1CAPO T1OUTO T1CK1 T1CAP1 T1OUT1 nRESET TEST NOTE Pin numbers shown in parentheses are for the 28 pin SOP package 2 3 1 8 ELECTRONICS S3C84H5 F84H5 PRODUCT OVERVIEW Table 1 2 S3C84H5 F84H5 Pin Descriptions 30 SDIP Pin Pin Circuit Type Description Type 0 3 P1 0 P1 5 P2 0 P2 7 P3 0 P3 3 ELECTRONICS Bit programmable port input or output mode E 14 17 ADCO ADC1 selected by
72. keep 0 Not pending always 0 0 Clear pending bit when write UART parity enable disable 1 Interrupt pending 0 Disable 1 Enable UART receive parity error UART receive interrupt pending flag 0 No error 0 Not pending 1 Parity error 0 Clear pending bit when write 1 Interrupt pending NOTES In order to clear a data transmit or receive interrupt pending flag you must write a to the appropriate pending bit A 0 has no effect To avoid errors we recommend using load instruction except for LDB when manipulating UARTPND values Parity enable and parity error check can be available in 9 bit UART mode Mode 2 only Parity error bit RPE will be refreshed whenever 8th receive data bit has been shifted Figure 15 2 UART Interrupt Pending Register UARTPND 15 4 ELECTRONICS S3C84H5 F84H5 UART In mode 2 9 bit UART data by setting the parity enable bit PEN of UARTPND register to 1 the 9 data bit of transmit data will be an automatically generated parity bit Also the 9 data bit of the received data will be treated as a parity bit for checking the received data In parity enable mode PEN 1 UARTCON 3 TB8 UARTCON 2 RB8 will be a parity selection bit for transmit and receive data respectively The UARTCON 3 8 is for settings of the even parity generation TB8 0 or the odd parity generation TB8 0 in the transmit mode The UARTCON 2 RB8 is also for settings of the
73. mode AD7 7 6 P2 2 ADA T1OUT1 Configuration Bits 0 0 Input mode 0 1 Alternative function mode T1OUT1 1 0 Push pull output mode 1 1 Alternative function mode AD4 7 6 P2 1 PWM T1CAPO Configuration Bits 0 0 Input mode T1CAPO 0 1 Alternative function mode T1CAPO 1 0 Push pull output mode 1 1 Alternative function mode 7 6 P2 0 TBPWM T1CKO Configuration Bits 0 0 Input mode T1CKO 0 1 Alternative function mode T1CKO 1 0 Push pull output mode 1 1 Alternative function mode TBPWM Figure 9 7 Port 2 Low Byte Control Register P2CONL 9 10 ELECTRONICS S3C84H5 F84H5 PORTS Port 2 Pull up Control Register P2PUR Seti R W Reset value 00 7 P2 7 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 6 P2 6 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 5 P2 5 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 4 P2 4 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 3 P2 3 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 2 P2 2 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 1 P2 1 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 0 P2
74. of the AND instruction If the AND instruction uses the Flags register as the destination then two write will simultaneously occur to the Flags register producing an unpredictable result System Flags Register FLAGS D5H Set 1 R W Bank address status flag BA Fast interrupt status flag FS Carry flag C Zero flag 2 Sign flag S Half carry flag H Overflow flag V Decimal adjust flag 0 Figure 6 1 System Flags Register FLAGS 6 6 ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET FLAG DESCRIPTIONS C FIS BA Carry Flag FLAGS 7 The C flag is set to 1 if the result from an arithmetic operation generates a carry out from or a borrow to the bit 7 position MSB After rotate and shift operations have been performed it contains the last value shifted out of the specified register Program instructions can set clear or complement the carry flag Zero Flag FLAGS 6 For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero In operations that test register bits and in shift and rotate operations the Z flag is set to 1 if the result is logic zero Sign Flag FLAGS 5 Following arithmetic logic rotate or shift operations the sign bit identifies the state of the MSB of the result A logic zero indicates a positive number and a logic one indicates a negative number Overflow Flag FLAGS 4 The V flag is set to 1 when the result of a two s c
75. of the pulse starts NOTE debug mode you have to include three extra commands in initial routine to operate Ports correctly If you omit these commands Port do not operate correctly After you have finished your program and before assembling you have to remove these three commands 11 10 ELECTRONICS S3C84H5 F84H5 PROGRAMMING Using the Timer A 8 BIT TIMER A B Extra command only for debugging Extra command only for debugging Extra command only for debugging Set stack area Disable watch dog Enable TAOUT output Match interrupt enable ORG 0000h VECTOR 0 0 INT VECTOR 0 2 INT ORG 0100h INITIAL DI SB1 LD OF7H 5FH SBO LD SPH 00000000b LD SPL 00000000b LD BTCON 1010001 1b LD P1CONL 0ABH SB1 LD TADATA 80h LD TACON 01001010b 6 55 ms duration 10 MHz x tal SBO EI MAIN MAIN ROUTINE JR T MAIN TAMC INT Interrupt service routine IRET INT Interrupt service routine IRET END NOTE In debug mode you have to include three extra commands in initial routine to operate Ports correctly If you omit these commands Port do not operate correctly After you have finished your program and before assembling you have to remove these three commands ELECTRONICS 11 11 8 59 PROGRAMMING Using the Timer INITIAL MAIN TBUN_INT ORG VECTOR ORG 0000h OBEh TBUN INT 0
76. opc src dst 3 6 64 R R 6 65 R IR opc dst src 3 6 66 R IM Examples Given RO 0C7H R1 02H R2 12H registerOOH 2BH register 01H 02H and register 02H 23H TCM RO R1 gt RO 0C7H R1 02H 2 1 TCM RO R1 gt RO R1 02H register 02H 23H 2 0 TCM 00H 01H gt Register OOH 2BH register 01H 02H Z 1 TCM 00H 01H gt Register 2BH register 01H 02H register 02H 23H Z 1 TCM 00H 34 gt Register 00 2BH Z 0 In the first example if the working register RO contains the value 11000111B and the register R1 the value 02H 00000010B the statement TCM RO R1 tests bit one in the destination register for a 1 value Because the mask value corresponds to the test bit the Z flag is set to logic one and can be tested to determine the result of the TCM operation 6 84 ELECTRONICS S3C84H5 F84H5 TM Test under Mask TM Operation Flags Format Examples dst src dst AND src INSTRUCTION SET This instruction tests selected bits in the destination operand for a logic zero value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and the source operands are unaffected C Unaffected Set if the result is 0 cleared oth
77. pull up 1 0 Push pull output mode 1 1 N channel open drain output 1 0 P3 0 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output Figure 9 9 Port 3 Low Byte Control Register PSCONL 9 12 ELECTRONICS S3C84H5 F84H5 8 Programming Tip Using the Timer ORG 0000h VECTOR 0 0 INT VECTOR 0 2 INT ORG 0100h INITIAL LD SYM 00h LD IMR 00000010b LD SPH 00000000b LD SPL 00000000b LD BTCON 1010001 1b LD P1CONL 0ABH SB1 LD TADATA 80h LD TACON 01001010b SBO El MAIN MAIN ROUTINE JR T MAIN TAMC_INT Interrupt service routine IRET TAOV_INT Interrupt service routine IRET END ELECTRONICS PORTS Disable Global Fast interrupt gt SYM Enable IRQ1 interrupt Set stack area Disable watch dog Enable TAOUT output Match interrupt enable 6 55 ms duration 10 MHz x tal 9 13 5 59 PROGRAMMING Using Ports INITIAL MAIN NOTE 9 14 ORG JR END 0100h OF7H 5FH SPL 00000000b BTCON 10100011b CLKCON 18H POCON 0AAH P1CONH 0AAH P1CONL 0AAH P2CONH 0AAH P2CONL 0AAH P3CONL 0AAH P1 03FH P2 0FFH P3 0FH T MAIN Extra command only for debugging Extra command only for debugging 1 Extra command only for debugging Disable Watch dog PORTO PUSH PULL OUTPUT PORT1 PUSH PUL
78. register TADATA pins for capture input or PWM or match output TAOUT Timer A overflow interrupt IRQ1 vector C2H and match capture interrupt IRQ1 vector COH generation Timer A control register TACON set 1 bank1 E1H read write ELECTRONICS 11 1 8 S3C84H5 F84H5 FUNCTION DESCRIPTION Timer A Interrupts IRQ1 Vectors COH and C2H The timer A module can generate two interrupts the timer A overflow interrupt TAOVF and the timer A match capture interrupt TAINT TAOVF is interrupt level IRQ1 vector C2H TAINT also belongs to interrupt level IRQ1 but is assigned the separate vector address COH Timer A overflow interrupt pending condition is automatically cleared by hardware when it has been serviced Timer A match capture interrupt TAINT pending condition is also cleared by hardware when it has been serviced Interval Timer Function The timer A module can generate an interrupt the timer A match interrupt TAINT TAINT belongs to interrupt level IRQ1 and is assigned the separate vector address COH When the timer A match interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware In interval timer mode a match signal is generated and TAOUT is toggled when the counter value is identical to the value written to the timer A reference data register TADATA The match signal generates a timer A match interrupt TAINT vector COH and
79. register R1 is 07H 00000111B the statement BITR R1 1 clears bit one of the destination register R1 leaving the value 05H 00000101B ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET BITS sit set BITS dst b Operation dst b lt 1 The BITS instruction sets the specified bit within the destination without affecting any other bit in the destination Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst b 1 2 4 77 rb NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITS R1 3 gt R1 OFH If the working register R1 contains the value 07H 00000111B the statement BITS R1 3 sets bit three of the destination register R1 to 1 leaving the value OFH 00001111B ELECTRONICS 6 21 INSTRUCTION SET S3C84H5 F84H5 BOR Bit or BOR BOR Operation Flags Format Examples dst src b dst b src 4610 lt dst 0 OR src b Or dst b dst b OR src 0 The specified bit of the source or the destination is logically ORed with bit zero LSB of the destination or the source The resulting bit value is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Cleare
80. registers are disabled and reset to their default hardware values The program counter PC is loaded with the program reset address in the ROM 0100H When the programmed oscillation stabilization time interval has elapsed the instruction stored in ROM location 0100H and 0101H is fetched and executed NORMAL MODE RESET OPERATION In normal masked ROM mode the TEST is tied to Vas A reset enables access to the 16 Kbyte on chip ROM NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON ELECTRONICS 8 1 RESET and POWER DOWN S3C84H5 F84H5 HARDWARE RESET VALUES Table 8 1 8 2 and 8 3 list the reset values for CPU and system registers peripheral control registers and peripheral data registers following a reset operation The following notation is used to represent reset values 1 0 shows the reset bit value as logic one or logic zero respectively means that the bit value is undefined after a reset dash means that the bit is either not used or not mapped but read 0 is the bit value Table 8 1 S3C84H5 F84H5 Set 1 Register values after RESET Bit
81. started it resumes counting from the retained count value When there is a need to clear the counter you set PWMCON 3 to 1 You can select a clock for the PWM counter by set PWMCON 6 7 Clocks which you can select are fosc 64 FUNCTION DESCRIPTION PWM The 10 bit PWM circuits have the following components 8 bit comparator and extension cycle circuit 8 bit reference data register PWMDATAH 7 0 2 bit extension data register PWMDATAL 1 0 PWM output pins P2 1 PWM PWM Counter To determine the PWM module s base operating frequency the upper 8 bits of counter is compared to the PWM data PWMDATAH 7 0 In order to achieve higher resolutions the lower 2 bits of the PWMDATAL counter be used to modulate the stretch cycle To control the stretching of the PWM output duty cycle at specific intervals the lower 2 bits of PWMDATAL counter value is compared with the PWMDATAL 1 0 ELECTRONICS 13 1 10 PWM PULSE WIDTH MODULATION S3C84H5 F84H5 PWM Data and Extension Registers PWM duty data registers located in Set 1 Bank1 at address 4 determine the output value generated by each 10 bit PWM circuit To program the required PWM output you load the appropriate initialization values into the 8 bit reference data register PWMDATAH 7 0 and the 2 bit extension data register PWMDATAL 1 0 To start the PWM counter or to resume counting you set 2 to 1 A
82. the interrupt level of source The CPU generates an interrupt acknowledge signal Interrupt logic determines the interrupt s vector address The service routine starts and the source s pending bit is cleared to 0 by hardware or by software The CPU continues polling for interrupt requests INTERRUPT SERVICE ROUTINES Before an interrupt request is serviced the following conditions must be met Interrupt processing must be globally enabled El 5 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one level is currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The gt CPU then initiates an interrupt machine cycle that completes the following processing sequence Reset clear to 0 the interrupt enable bit in the SYM register SYM 0 to disable all subsequent interrupts Save the program counter PC and status flags to the system stack Branch to the interrupt vector to fetch the address of the service routine Pass control to the interrupt service routine When the interrupt service routine is completed the CPU issues an Interrupt Return IRET The IRET restores the PC and status flags setting SYM 0 to 1 It allows the CPU to process the next interrupt request
83. to start of working register block 16 Bit address added to Program Memory offset LSB Selects or Data Memory 16 Bits 16 Bits Value used in OPERAND Instruction Sample Instructions LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 Identical operation to LDC example except that external program memory is accessed LDE R4 1000H RR2 Figure 3 9 Indexed Addressing to Program or Data Memory ELECTRONICS 3 9 ADDRESSING MODES S3C84H5 F84H5 DIRECT ADDRESS MODE DA In Direct Address DA mode the instruction provides the operand s 16 bit memory address Jump JP and Call CALL instructions use this addressing mode to specify the 16 bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Program or Data Memory Program Memory Upper Address Byte lt Memory Address Used Lower Address Byte dst src 0 or 1 LSB Selects Program OPCODE Memory or Data Memory 0 Program Memory Data Memory Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H ldentical operation to LDC ex
84. transmit 3 Parity enable bits PEN is located in the UARTPND register at address 4 Parity enable and parity error check can be available in 9 bit UART mode Mode 2 only Figure 15 1 UART Control Register UARTCON ELECTRONICS 14 3 UART S3C84H5 F84H5 UART INTERRUPT PENDING REGISTER UARTPND The UART interrupt pending register UARTPND is located at address It contains the UART data transmit interrupt pending bit UARTPND O and the receive interrupt pending bit UARTPND 1 In mode 0 of the UART module the receive interrupt pending flag UARTPND 1 is set to 1 when the 8th receive data bit has been shifted In mode 1 or 2 the UARTPND 1 bit is set to 1 at the halfway point of the stop bit s shift time When the CPU has acknowledged the receive interrupt pending condition the UARTPND 1 flag must be cleared by software in the interrupt service routine In mode 0 of the UART module the transmit interrupt pending flag UARTPND O is set to 1 when the 8th transmit data bit has been shifted In mode 1 or 2 the UARTPND O bit is set at the start of the stop bit When the CPU has acknowledged the transmit interrupt pending condition the UARTPND 0 flag must be cleared by software in the interrupt service routine UART Pending Register UARTPND Set1 Bank 0 R W Reset Value 00H wool s repere s 2 Not used Not used UART transmit interrupt pending flag must keep always 0 must
85. values after RESET Register Name Timer B control register TBCON Timer B data register high byte TBDATAH 2 Timer B data register low byte TBDATAL Basic timer control register BTCON 1 1 Clock Control register CLKCON 212 System flags register FLAGS 21 Register pointer 0 m ne Register pointer 1 215 Stack ponies oe 216 Instruction Instruction pointer MON byte system mode register em oen o o lo x x x Register page poiner Lorn 8 2 ELECTRONICS S3C84H5 F84H5 RESET and POWER DOWN Table 8 2 S3C84H5 F84H5 Set 1 Bank 0 ees T values after RESET Address Bit values after Reset Register Name Mnemonic Dec Hex Port 0 data register PO EOH Port 2 data register P2 226 0 0 Port 3 data register P3 227 0 Location E4H is not mapped STOP control register STOPCON 229 esu 0 0 O O 0 0 Port 0 control register high byte POCON 230 01010101010 Location FBH is not mapped Port 1 control register high byte P1CONH 232 E8H 0 0 Port 1 control register low byte P1CONL eet Port 1 interrupt pending register PIINTPND 234 eam o 0 0 0 0 9 Port t interrupt controlregister Pint 235 EH 0 0 0 0 9
86. within the destination without affecting any other bit in the destination Flags C Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected Logos wm M Format Bytes Cycles Opcode Addr Mode Hex dst opc dst b 0 2 4 57 rb NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BITC R1 1 gt R1 05H If the working register R1 contains the value 07H 00000111 the statement BITC R1 1 complements bit one of the destination and leaves the value 05H 00000101B in the register R1 Because the result of the complement is not 0 the zero flag Z in the FLAGS register OD5H is cleared ELECTRONICS 6 19 INSTRUCTION SET S3C84H5 F84H5 BITR Bit Reset BITR Operation Flags Format Example dst b dst b lt 0 The BITR instruction clears the specified bit within the destination without affecting any other bit in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst b 0 2 4 77 rb NOTE Inthe second byte of the instruction format the destination address is four bits the bit address 0 is three bits and the LSB address value is one bit in length Given R1 07 BITR R1 1 gt R1 05H If the value of the working
87. 0 One shot mode 1 Repeating mode Timer B start stop bit 0 Stop timer B 1 Start timer Timer B interrupt enable bit 0 Disable interrupt 1 Enable interrupt Figure 11 4 Timer B Control Register TBCON S3C84H5 F84H5 Timer B Data High Byte Register TBDATAH D1H Set 1 Bank 0 R W MSB 7 81514131214 0 LSB Reset Value FFh Timer B Data Low Byte Register TBDATAL D2H Set 1 Bank 0 R W Reset Value FFh Figure 11 5 Timer B Data Registers TBDATAH TBDATAL ELECTRONICS S3C84H5 F84H5 8 BIT TIMER A B TIMER B PULSE WIDTH CALCULATIONS tHIGH tLOW 1 tLow m To generate the above repeated waveform consisted of low period time 1 and high period time t jc When T FF 0 ti ow TBDATAL 1 x 1 fx OH lt TBDATAL lt 100H where fx The selected clock TBDATAH 1 x 1 fx OH lt TBDATAH lt 100H where fx The selected clock When 1 ti ow TBDATAH 1 x 1 fx OH lt TBDATAH lt 100H where The selected clock TBDATAL 1 x 1 fx lt TBDATAL lt 100H where fx The selected clock To make tj oy 24 us and 15 us fosc 4 MHz fx 4 MHz 4 1 MHz When T FF 0 ti ow 24 us TBDATAL 1 fx TBDATAL 1 x tus TBDATAL 23 15 us TBDATAH 1 fx TBDATAH 1 x tus TBDATAH 14 When T FF 1 15 us TBDATAL 1 fx TBDATAL 1 x tu
88. 0 9 60 1 ADC 0 9 F 0 A F 66 1 0 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1 0 0 9 0 0 9 00 00 0 SUB 0 0 8 1 6 F FA 06 0 58 1 7 F 0 0 9 AO 60 1 1 6 F 1 6 F 9A 66 1 Flags C Set if there was a carry from the most significant bit cleared otherwise see table Z Setif result is 0 cleared otherwise S Setif result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 40 R 4 41 IR ELECTRONICS 6 33 INSTRUCTION SET S3C84H5 F84H5 DA Decimal Adjust DA Example Continued Given The working register RO contains the value 15 BCD the working register R1 contains 27 BCD and the address 27H contains 46 BCD ADD R1 RO 0 Bits 4 7 3 bits 0 3 C R1 lt 3CH DA R1 1 lt 06 If an addition is performed using the BCD values 15 27 the result should be 42 sum is incorrect however when the binary representations are added in the destination location using the standard binary arithmetic 0001 0101 15 0010 0111 27 0011 1100 3CH The DA instruction adjusts this result so that the correct BCD representation is obtained 0011 1100 0000 0110 0100 0010 42 Assuming the same values given above the statements SUB 27H RO C 0 lt 0 Bits 4 7 3 bits 0 3 1 DA R1 R1 lt 31 0 leave the value 31 BCD t
89. 0 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable Figure 9 8 Port 2 Pull up Control Register P2PUR ELECTRONICS 9 11 5 S3C84H5 F84H5 PORT 3 Port is 8 bit I O port that can be used for general purpose digital I O The pins are accessed directly by writing or reading the port 3 data register P3 at location E3H set 1 bank 0 P3 0 P3 3 can serve as inputs outputs push pull Port 3 Control Register PSCONL Port 3 has two 8 bit control registers PSCONH for 4 7 and P3CONL for P3 0 P3 3 A reset clears the P3CONH and P3CONL registers to OOH configuring all pins to input mode You use control registers settings to select input or output mode push pull Open drain and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 3 control registers must also be enabled in the associated peripheral module Port 3 Control Register Low Byte PSCONL Seti R W Reset value 00 7 6 P3 3 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 5 4 P3 2 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 N channel open drain output 3 2 P3 1 Configuration Bits 0 0 Input mode 0 1 Input mode with
90. 0000 0 e nnne entren nnne enne 5 11 Interrupt Priority Register i tete rr E e tima Ee 5 12 Interrupt Request Register IRQ sss nennen entente en nennen nennen 5 14 Interrupt Pending Function 11 Lenin acte Ene Fea ke Eo DE E Re ER SU ER eS e Rech De e RR eee cera 5 15 Interrupt Source Polling Sequence essct 5 16 Interrupt Service ROoUllries dde docet dete iniit 5 16 Generating interrupt Vector 5 17 Nesting of Vectored Interrupts cepere relig e dated 5 17 Chapter 6 Instruction Set Overview sasassssussusunseusassussnssessosusssssusnsesusesusssussessssenscussssusensausussussessessssensesusesusunsesusscusussusensssusonsaususcunssssessusensesuns 6 1 Data eed tod ce paci 6 1 REgister Addressitig itte tia iit te tetti 6 1 Addressing Modes eda sec ei eec i evt eddie Peer 6 1 Flags Register FLAGS lt lt ert ee e e dete tt eb HP 6 6 Elag Descriptloris eate oe Shade tdt o tee ius 6 7 Instr ctior Set NOtatlOn 1 D Senna p uon bari 6 8 Condition Codes tice eae nee aes E dee 6 12 Instruction Descriptions entro cm en ens 6 13 vi S3C84H
91. 01 10B in the register R1 ELECTRONICS 6 17 INSTRUCTION SET S3C84H5 F84H5 BCP Bit Compare BCP Operation Flags Format Example dst src b dst 0 src b The specified bit of the source is compared to subtracted from bit zero LSB of the destination The zero flag is set if the bits are the same otherwise it is cleared The contents of both operands are unaffected by the comparison Unaffected Set if the two bits are the same cleared otherwise Cleared to 0 Undefined Unaffected Unaffected lt Bytes Cycles Opcode Addr Mode Hex dst sre dst b 0 src 3 6 17 ro Rb NOTE the second byte of the instruction format the destination address is four bits the bit address 0 is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 01H BCP R1 01H 1 gt R1 register 01H 01H If the destination working register R1 contains the value 07H 00000111B and the source register 01H contains the value 01H 00000001B the statement BCP R1 01H 1 compares bit one of the source register 01H and bit zero of the destination register R1 Because the bit values are not identical the zero flag bit Z is cleared in the FLAGS register OD5H ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET BITC Complement BITC dst b Operation dst b lt NOT dst b This instruction complements the specified bit
92. 100h OF7H 5FH IMR 00000001b SPH 00000000b SPL 00000000b BTCON 10100011b P2CONL 03H TBDATAH 80h TBDATAL 80h TBCON 11101110b MAIN ROUTINE JR T MAIN Interrupt service routine IRET END S3C84H5 F84H5 Extra command only for debugging Extra command only for debugging Extra command only for debugging Enable IRQO interrupt Set stack area Disable Watch dog Enable TBPWM output Enable interrupt fxx 256 Repeat Duration 6 605ms 10 MHz x tal NOTE In debug mode you have to include three extra commands in initial routine to operate Ports correctly If you omit these commands Port do not operate correctly After you have finished your program and before assembling you have to remove these three commands 11 12 ELECTRONICS S3C84H5 F84H5 16 BIT TIMER 1 0 1 16 BIT TIMER 1 0 1 OVERVIEW The S3C84H5 F84Hb has two 16 bit timer counters The 16 bit timer 1 0 1 is 16 bit general purpose timer counter Timer 1 0 1 has three operating modes one of which you select using the appropriate T1 CONO T1CON1 setting is Interval timer mode Toggle output at TTOUTO pin Capture input mode with a rising or falling edge trigger at the T1CAPO T1CAP1 pin PWM mode T1PWMO T1PWM1 PWM output shares their output port with T1 OUTO T1OUT1 pin Timer 1 0 1 has the following functional components Clock frequency divider fxx divided by 1024 256 64 8 1 with mu
93. 2 6 TxD P2 7 ADO PO 0 AD1 PO 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Figure 19 2 Pin Assignment 30 pin SDIP I 19 2 ELECTRONICS S3C84H5 F84H5 Vss Xour XIN TEST XTIN XTour nRESET SO P2 4 SCK P2 5 RxD P2 6 TxD P2 7 ADO P0 0 AD1 PO 1 AD2 P0 2 079 ELECTRONICS gt 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Fo 53 84 5 S3F84H5 Top View ooco udoosom 28 SOP e LILELTLTLEEELTLTEIT ET E VDD P1 3 T10UT1 INT3S SCLK P1 2 TACAP INT2 SDAT P1 1 TACK BUZ INT1 P1 0 TAOUT INTO AVss AV REF P1 5 AD6 T1CAP1 P1 4 AD5 T1CK1 P2 3 AD7 SI P2 2 ADA4 T1OUTO P2 1 T1CAPO PWM P2 0 T1CKO TBPWM AD3 P0 3 Figure 19 3 Pin Assignment 28 pin SOP 19 3 S3C84H5 F84H5 Table 19 1 Descriptions of Pins Used to Read Write the Flash ROM Main Chip During Programming P1 2 SDAT Serial data pin output when reading Input when writing Input and push pull output port can be assigned SCLK Serial clock pin input only pin TEST VPP 4 Power supply pin for flash ROM cell writing indicates that MTP enters into the writing mode When 12 5 V is applied MTP is in writing mode and when 5 V is applied MTP is in reading mode Option VDD VSS Vpp Vss 32 1 32 pin Logic power supply pin 30 1 30 pin 28 1 28 pin Table 19 2 Comparison of S3F84H5 and S3C8
94. 2011 Alternative function mode T1CKO input 1 0 Push pull output mode Alternative function mode TBPWM mode NOTE debug mode you have to include three extra commands in initial routine to operate Ports correctly If you omit these commands Port do not operate correctly Reter to page 9 14 After you have finished your program and before assembling you have to remove these three commands ORG 100H SB1 Extra command only for debugging LD OF7H 5FH Extra command only for debugging SBO Extra command only for debugging 4 20 ELECTRONICS S3C84H5 F84H5 CONTROL REGISTER P2PUR Port 2 Pull up Resistor Control Register FAH Set1 Bit Identifier ezee lala e p 41 2 0 RESET Value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W 7 P2 7 Pull up Resistor Enable Disable Pull up resistor disable 1 Pull up resistor enable 6 P2 6 Pull up Resistor Enable Disable Pull up resistor disable Pull up resistor enable B 5 P2 5 Pull up Resistor Enable Disable Pull up resistor disable 1 Pull up resistor enable 4 1 4 Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 3 P2 3 Pull up Resistor Enable Disable 0 Pull up resistor disable 1 Pull up resistor enable 2 P2 2 Pull up Resistor Enable Disable Pull up resistor disable 1 Pull up resistor enable 1 P2 i Pull up Resistor Enable Disable Pull up resistor disable Pul
95. 2H 23H Register 29H register 01H 02H Register OOH 08H register 01H 2 register 02H 23H Register OOH 7FH In the first example if the working register RO contains the value 0C7H and if the register R1 contains the value 02H the statement RO R1 logically exclusive ORs the R1 value with the RO value and stores the result 0C5H in the destination register RO ELECTRONICS 6 87 S3C84H5 F84H5 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW The clock frequency generated for the Main clock of 53 84 5 84 by an external crystal can range from 1 MHz to 10 MHz The maximum CPU clock frequency is 10 MHz The and pins connect the external oscillator or clock source to the on chip clock circuit Also the subsystem clock frequency for the Watch timer by an external crystal can range from 30 kHz to 35 kHz The XT y and XTour pins connect the external oscillator or clock source to the on chip clock circuit SYSTEM CLOCK CIRCUIT The system clock circuit has the following components External crystal or ceramic resonator oscillation source or an external clock source Oscillator stop and wake up functions Programmable frequency divider for the CPU clock fxx divided by 1 2 8 or 16 System clock control register CLKCON Oscillator control register OSCCON and STOP control register STPCON C1 XIN XTIN S3C84H5 S3C84H5 S3F84H5 S3F84H5 E
96. 3 14 Immediate Addressing 3 14 ELECTRONICS S3C84H5 F84H5 CONTROL REGISTER CONTROL REGISTERS OVERVIEW Control register descriptions are arranged in alphabetical order according to register mnemonic More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part Il of this manual The locations and read write characteristics of all mapped registers in the S3C84H5 F84H5 register file are listed in Table 4 1 The hardware reset value for each mapped register is described in Chapter 8 RESET and Power Down Table 4 1 Set 1 Registers Demi Timer control register TBCON R W Timer B data register High Byte R W RW Basic timer control register BTCON R W Clock control register CLKCON R W R W Register pointer 0 R W Register pointer 1 R W R W R W Instruction pointer High Byte R W Stack pointer High Byte Instruction pointer Low Byte m R W Stack pointer Low Byte Interrupt request register Interrupt mask register System mode register R W R W R W Register page pointer ELECTRONICS 4 1 CONTROL REGISTERS S3C84H5 F84H5 Table 4 2 Set 1 Bank 0 Registers RegisterName Mnemonic Decimal nw EM RW Location E7H is not mapped Location EEH is not mapped Location FOH F1H is not mapped Oscillator control register OSCCO
97. 4H5 Features Characteristic S3F84H5 53 84 5 16 Kbyte Flash ROM 16K byte mask ROM Operating Voltage Vpp 2 8V to 55V 2 8 V to 55V MTP Programming Mode Vpp 5 V Vpp 12 5 V 0225 Pin Configuration 32 SDIP SOP 30 SDIP 28 SOP EPROM Programmability User Program multi time 19 4 ELECTRONICS S3C84H5 F84H5 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this chapter S3C84H5 F84H5 electrical characteristics are presented in tables and graphs The information is arranged in the following order Absolute maximum ratings Input output capacitance D C electrical characteristics electrical characteristics Oscillation characteristics Oscillation stabilization time Data retention supply voltage in stop mode UART timing characteristics in mode 0 A D converter electrical characteristics ELECTRONICS 20 1 ELECTRICAL DATA S3C84H5 F84H5 Table 20 1 Absolute Maximum Ratings Ta 25 C Parameter Conditions Rating Unit Supply Voltage 0 3 to 6 5 V Input Voltage All input ports 0 3 to Vpp 0 3 Output Voltage Vo All output ports 0 3 to Vpp 0 3 Output Current High One pin active 18 mA Output Current Low One I O pin active 30 All I O pins active 200 Operating 25 to 85 Temperature Storage Temperature 65 to 150 Table 20 2 Input Output Capacitance TA 25 C to 85
98. 4H5 interrupt structure recognizes eight interrupt levels The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels They are just identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no vector address assigned at all The maximum number of vectors that can be supported for a given level is 128 The actual number of vectors used for S3C8 series devices is always much smaller If an interrupt level has more than one vector address the vector priorities are set in hardware S3C84H5 F84H5 uses sixteen vectors Sources A source is any peripheral that generates an interrupt A source can be an external pin or a counter overflow Each vector can have several interrupt sources In the S3C84H5 F84H5 interrupt structure there are sixteen possible interrupt sources When service routine starts the respective pending bit should be either cleared automatically by hardware or cleared manually by program software The characteristics of the source s pending mechanism determine which method would be used to clear its respective pending bit ELECTRONICS
99. 5 1 INTERRUPT STRUCTURE S3C84H5 F84H5 INTERRUPT TYPES The three components of the S3C8 interrupt structure described before levels vectors and sources are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic There are three possible combinations of interrupt structure components called interrupt types 1 2 and 3 The types differ in the number of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V4 one source S4 Type 2 One level IRQn one vector V4 multiple sources S Type 3 One level IRQn multiple vectors V4 Vp multiple sources S4 S4 4 94 4 In the S3C84H5 F84H5microcontroller two interrupt types are implemented Levels Vectors Sources V1 IRQn AA 51 51 52 53 50 51 52 NOTES 1 The number of Sn and Vn value is expandable 2 In the S3C84H5 F84H5 implementation interrupt types 1 and 3 are used Figure 5 1 S3C8 Series Interrupt Types 5 2 ELECTRONICS S3C84H5 F84H5 INTERRUPT STRUCTURE S3C84H5 F84H5 INTERRUPT STRUCTURE The S3C84H5 F84H5 microcontroller supports sixteen interrupt sources All of the interrupt sources have a corresponding interrupt vector address Eight interrupt levels are recognized by the CPU in this device specific interrupt structure as shown in Figure 5 2 When multiple interrupt levels are active the int
100. 5 F84H5 MICROCONTROLLER Table of Contents continued Part Il Hardware Descriptions Chapter 7 Clock Circuit Overview sasasssassssssnssunsssussnsssssscusssusessssenseususcussnssusnscunsosussnsaussscusssssussesenseusussusensessuscusnsesusensssusonscessscunsossussaseusensus 7 1 System clock Circult 2 da eir Ge aede ede pe tete o Doe ae 7 1 Clock Status During Power Down 7 2 System Clock Control Register nene rennen 7 3 Chapter 8 RESET Power Down System Reset eei atate i ee exit o RB ety ie Ha RUE Dein gd 8 1 OVERVICW eee vee rip ae eco ec 8 1 Normal Mode Reset Operation isser rb nae eer eo Dr a be etas eget 8 1 Hardware Reset Values eie eae RH cV eoe pde 8 2 Powet Down Modes ore eR Rer tet e et dil Shiga dei don 8 5 510 M 8 5 esee Se ee nto MILII Ent 8 6 Chapter 9 Ports Overview sasassssssssssnssussssusonsasssscusssussssssenscssuscusenssssnscussssusonsaussscusisesssssssenseusussusenssssuscunsesusensssusonsausescunsessussesenseusus 9 1 Port Data Registers edente qt iet E C iie le te tee ee Pie ete e ee 9 2 xw EDS 9 3 Port IDCM LM EN NI od 9 4 POM
101. 7H Both kinds of timer 1 1 interrupts T1OVF1 T1INT1 can be used in capture mode the timer 1 1 overflow interrupt is generated whenever a counter overflow occurs the timer 1 1 capture interrupt is generated whenever the counter value is loaded into the timer 1 data register By reading the captured data value in TIDATAH1 T1DATAL1 and assuming a specific value for the timer 1 1 clock frequency you can calculate the pulse width duration of the signal that is being input at the T1CAP1 pin 12 2 ELECTRONICS S3C84H5 F84H5 16 BIT TIMER 1 0 1 PWM Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the T1OUTO T1OUT1 pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer 1 0 1 data registers In PWM mode however the match signal does not clear the counter but can generate a match interrupt Instead it runs continuously overflowing at FFFFH and then continuous increasing from OOOOH Whenever an overflow occur an overflow T1OVFO 1 interrupt can be generated Although you can use the match or overflow interrupts in the PWM mode these interrupts are not typically used in PWM type applications Instead the pulse at the T1OUTO T1OUT1 pin is held to low level as long as the reference data value is less than or equal to x the counter value and then the pulse is held to high level for as long as the data v
102. 8 The lower byte of the stack pointer value is located in register SPL D9H The SP value is undefined following a reset SPL stack Pointer Low Byte D9H Set 1 RESET Value X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address Low Byte The low byte stack pointer value is the lower eight bits of the 16 bit stack pointer address SP7 SP0 The upper byte of the stack pointer value is located in register SPH D8H The SP value is undefined following a reset ELECTRONICS 4 27 4 28 7 0 CONTROL REGISTERS S3C84H5 F84H5 STOPCON Stop Control Register E5H Seti RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Register addressing mode only Addressing Mode STOP Control Bits 10100101 Enable stop instruction Other values Disable stop instruction NOTE Before execute the STOP instruction You must set this STPCON register as 10100101b Otherwise the STOP instruction will not be executed ELECTRONICS S3C84H5 F84H5 CONTROL REGISTER _ System Mode Register DEH Set 1 Bit Identifier 8 5 4 3 2 3 RESET Value 0 0 0 0 0 Read Write R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Not used But you must keep always 0 4 2 Fast Interrupt Level Selection Bits 1 Fast Interrupt Enable Bit Lo Disable fast interrupt
103. A 1 indicates that an interrupt request has been generated for that level IRQ bit values are read only addressable using Register addressing mode You can read test the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however still detect the interrupt request by polling the IRQ register In this way you can determine which events occurred while the interrupt structure was globally disabled Interrupt Request Register IRQ DCH Set 1 R IRQ IRQ5 IRQ4 RQ6 Interrupt level request pending bit 0 IRQ interrupt is not pending 1 IRQ interrupt is pending Figure 5 9 Interrupt Request Register IRQ 5 14 ELECTRONICS S3C84H5 F84H5 INTERRUPT STRUCTURE INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared in the interrupt service routine Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically b
104. ATAL 2 bit Conversion data LD ADCON 400110001B Channel ADC3 fxx Conversion start TM ADCON 00001000 conversion end EOC check JR 7 No LD AD3BUFH ADDATAH 8 bit Conversion data LD AD3BUFL ADDATAL 2 bit Conversion data NOTE In debug mode you have to include three extra commands in initial routine to operate Ports correctly If you omit these commands Port do not operate correctly After you have finished your program and before assembling you have to remove these three commands 16 6 ELECTRONICS S3C84H5 F84H5 WATCH TIMER WATCH TIMER OVERVIEW Watch timer functions include real time and watch time measurement and interval timing for the system clock To start watch timer operation set bit and bit 6 of the watch timer mode register WTCON 1and 6 to 1 After the watch timer starts and elapses a time the watch timer interrupt is automatically set to 1 and interrupt requests commence in 1 955 ms or 0 125 0 25 and 0 5 second intervals The watch timer can generate a steady 0 5 kHz 1 kHz 2 kHz or 4 kHz signal to the BUZZER output BZOUT pin By setting WTCON 3 and WTCON 2 to 110 the watch timer will function in high speed mode generating an interrupt every 1 955 ms High speed mode is useful for timing events for program debugging sequences Real time and Watch time measurement Using a main system or subsystem clock source Buzzer output frequen
105. Addressing Modes Figure 2 3 Internal Register File Organization ELECTRONICS 2 5 ADDRESS SPACES S3C84H5 F84H5 REGISTER PAGE POINTER PP The S3C8 series architecture supports the logical expansion of the physical 256 byte internal register file using an 8 bit data bus into as many as 2 separately addressable register pages Page addressing is controlled by the register page pointer PP DFH In the S3C84H5 F84H5 microcontroller a paged register file expansion is implemented for data registers and the register page pointer must be changed to address other pages After a reset the page pointer s source value lower nibble and the destination value upper nibble are always 0000 automatically selecting page 0 as the source and destination page for register addressing Register Page Pointer PP DFH Set 1 R W MSB Destination register page selection bits Source register page selection bits 0000 Destination Page 0 0000 Source Page 0 NOTE Ahardware reset operation writes the 4 bit destination and source values shown above tho the register page pointer These values should be modified to other page Figure 2 4 Register Page Pointer PP 2 6 ELECTRONICS S3C84H5 F84H5 ADDRESS SPACES 8 Programming Using the Page Pointer for RAM clear LD SRP LD RAMCLO CLR DJNZ CLR LD LD RAMCL1 CLR DJNZ CLR ELECTRONICS PP 00H 0COH RO 0FFH RO RO RAMCLO GR
106. C COCO CER CCC CSCC OC Using the RPs to Calculate the Sum of a Series of Registers olen 8 L T E A Addressing the Common Working Register Area Standard Stack Operations Using PUSH and POP 9 Ports Using the Timer A sasssssusssssssssusssssussusensessuscusssssssessunsseusseseussessuscusessusenscussscunsnsausescuusesssssuseusesususses Using Ports sassssunssssussusansassuscunssousscsaussssussessusescussassuscunsssussenscussosunsessuseseussesensesssseusenscusuosusssuseusessuns Chapter 11 8 bit Timer A B To generate 38 kHz 1 3duty signal through P2 0 sasssssnssusussssensaususcussssussnsaunsssussnseussacunseususcuseusses To generate aone pulse signal through P2 0 sassssunssusssssssusasssasussesssssusunseussssusesseusescussesuusescunsecuns Using the Timer A sassssussssasssssussassussusensesssosussssssssscussssususcsaussusunscusessusenscusescussosausescunsesssssusensesusenses Using the Timer B Chapter 12 16 bit Timer 1 0 1 Using the Timer 1 0 sasssssussssussusensessuscusssssssssaussssunscssussusssssssnscsssssusscsse
107. CONTROL POINTS Interrupt processing can therefore be controlled in two ways globally or by specific interrupt level and source The system level control points in the interrupt structure are Global interrupt enable and disable by El and DI instructions or by direct manipulation of SYM O Interrupt level enable disable settings IMR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing be sure to include the necessary register file address register pointer information El Q Interrupt Request Register Polling RESET R Read only Cycle IRQO IRQ7 Interrupts Interrupt Priority Vector Register Interrupt Cycle Interrupt Mask Register Global Interrupt Control El DI SYM 0 manipulation Figure 5 4 Interrupt Function Diagram 5 8 ELECTRONICS S3C84H5 F84H5 INTERRUPT STRUCTURE PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral see Table 5 3 Table 5 3 Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register s Location s in seti Timer B underflow IRQO TBCON DOH TBDATAH TBDATAL D1H D2H Timer A over
108. D Load Memory with Pre Decrement sasssssnssssssssaussesusscusessssenscusessussessusesauusesusscussssusenseuses 6 55 LDCPD LDEPD Load Memory with Pre Decrement sasssssussssessssusssssnssunsssussnscusescusscssesesaunsesunscunsssuuensensas 6 56 LDCPI LDEPI Load Memory with Pre Increment sasssssusssssssssensusunscusussussnssusescussosusssusessesenscenscsunsesausese 6 57 LDW Load Word sassssussssssssscusssssuscusensususscusssesssnseusessussessusessunscessssusessesssscussssuseuscussosussesausescuns 6 58 MULT Multiply Unsigned sassssansssasssusunsesunscusssesasusaussssussesssesssensesusscussssnsenseussuscusseseuscusensesussenss 6 59 NEXT Next sasssssnssssussusunsassuscssessusensessussenssssssesaussscussesssssssussesuusessessussnseususcusssonssnsausescunsoseususeuses 6 60 NOP No Operation 6 61 Logical OR sassssssasssussscusessussssasusasunssunsssussenseusessussensusessussesssssuseusessuscussssussescunsscussesaussasens 6 62 POP Pop from Stack sassssssassssunssusussssscssussssunsesaussusunsesssscusesssssnscunsssussusaussesessesusssusensesunscussssos 6 63 POPUD Pop User Stack Decrementing sssnssssussasunsaususcusssssasnscunsesusnscusussesenseususcunesssususcensscunseuse 6 64 POPUI Pop User Stack Incrementing sasssssssssssssssunsassuscussesussnsassssc
109. D3 T1OUT1 T1CK1 T1CAP1 Port 0 Port 1 Xin iom SET 3 P2 0 P2 7 XTin gt RESETB 0 P2 XTout 4 2 1 nRESET x AD4 AD7 TBPWM PWM 8 Bit Port and Interrupt Control SI SO SCK RxD TxD Basic Timer g P1 0 TAOUT 3 3 0 4 E Timer Counter 4 P2 0 TBPWM 4 SABER T CPU 2 P0 0 P0 3 P2 0 T1CKO gt 16 81 3 2 1 o BI wp E Pent P1 3 T10UT1 Timer Counter 4k P2 2 P2 3 P1 4 T1CK1 gt 10 11 lt gt P1 5 T1CAP1 N REF SS P2 7 TxD p 16K Byte 528 Byte P2 6 RxD 4 UART ROM RAM 222 80 P23 SI P24 PWM 4 PWM 1 b P2 5 SCK 1 3 PRODUCT OVERVIEW PIN ASSIGNMENT S3C84H5 F84H5 Vss Xour XIN TEST XTour nRESET P3 0 P3 1 SO P2 4 SCK P2 5 RxD P2 6 TxD P2 7 ADO P0 0 AD1 P0 1 AD2 P0 2 Sk ek gh ms me ues ei OQ O S3C84H5 S3F84H5 Top View 32 SOP 32 SDIP O 32 31 30 29 28 27 26 25 23 22 21 20 19 18 17 VDD P1 3 T1OUT1 INT3 P1 2 TACAP INT2 P1 1 TACK BUZ INT1 P1 0 TAOUT INTO P3 3 P3 2 AVss AV REF P1 5 AD6 T1CAP1 P1 4 AD5 T1CK1 P2 3 AD7 SI P2 2 ADA T1OUTO P2 1 T1CAPO PWM P2 0 T1CKO TBPWM P0 3 AD3 Figure 1 2 S3C84H5 F84H5 Pin Assignment 32 pin SOP SDIP 1 4 ELECTRONICS S3C84H5 F84H5 PIN ASSIGNMENT PRODUCT OVERVIEW
110. EOC bit is automatically set to 1 and the result is dumped into the ADDATAH ADDATAL registers where it can be read The ADC module enters an idle state Remember to read the contents of ADDATAH and ADDATAL before another conversion starts Otherwise the previous result will be overwritten by the next conversion result NOTE Because the ADC does not use sample and hold circuitry it is important that any fluctuations in the analog level at the ADCO ADC7 input pins during a conversion procedure be kept to an absolute minimum Any change in the input level perhaps due to circuit noise will invalidate the result ELECTRONICS 16 1 A D CONVERTER S3C84H5 F84H5 A D CONVERTER CONTROL REGISTER ADCON The A D converter control register ADCON is located in set1 bank 0 at address F7H ADCON is read write addressable using 8 bit instructions only But the EOC bit ADCON 3 is read only ADCON has four functions Bits 6 4 select an analog input pin ADCO ADC7 Bit indicates the end of conversion status of the A D conversion Bits 2 1 select a conversion speed Bit 0 starts the A D conversion Only one analog input channel can be selected at a time You can dynamically select any one of the eight analog input pins ADCO ADC7 by manipulating the 3 bit value for ADCON 6 ADCON 4 A D Converter Control Register ADCON F7H Set 1 Bank 0 R W ADCON 3 bit is read only Not used Start or Enable bit must keep alway
111. ER 1 0 1 5 PROGRAMMING Using the Timer 1 0 INITIAL MAIN ORG VECTOR ORG SB1 LD LDW SBO 0000h 0C4h TIM1_INT 0100h SYM 00h Disable Global Fast interrupt Extra command only for debugging OF7H 5FH Extra command only for debugging Extra command only for debugging IMR 00001000b Enable IRQ2 interrupt SPH 00000000b Set stack area SPL 00000000b BTCON 10100011b Disable Watch dog T1CONO 01000110b Enable interrupt fxx 64 Interval Interval 1 536 ms 10 MHz x tal 1 0 400 00 T1DATALO FOh MAIN ROUTINE JR 1 INT NOTE T MIAN Interrupt service routine IRET END In debug mode you have to include three extra commands in initial routine to operate Ports correctly If you omit these commands Port do not operate correctly After you have finished your program and before assembling you have to remove these three commands ELECTRONICS S3C84H5 F84H5 10 BIT PWM PULSE WIDTH MODULATION 10 BIT PWM PULSE WIDTH MODULATION OVERVIEW This microcontroller has the 10 bit PWM circuit The operation of all PWM circuit is controlled by a single control register PWMCON The PWM counter is a 10 bit incrementing counter It is used by the 10 bit PWM circuits To start the counter and enable the PWM circuits you set PWMCON 2 to 1 If the counter is stopped it retains its current count value when re
112. ET BOARD DEVELOPMENT TOOLS The TB84H5 target board is used for the S3C84H5 and the S3F84H5 microcontroller It is supported by the SMDS2 or SK 1000 development system In Circuit Emulator Figure 22 2 TB84H5 Target Board Configuration To User Vcc orFF Jon RESET 8419 8 84 5 IDLE STOP 4 OO U2 WE 90 REV X 200X XX XX ON1 51 76 26 T1T2T3T4 50 60 70 80 SMDS2 SMDS2 w N 10 1 09 8 5 4101 J102 30 20 42SDIP 44QFP 1 42 1 160 40 150 AR1 5 5 35 130 CD 10 10 C16 30 90 100 110 120 15 SW1 15 25 JP1 AR2 7 d 20 22 N Figure 22 2 63 8419 S3F8418 S3F84H5 Target Board Configuration ELECTRONICS 44 40 DEVELOPMENT TOOLS S3C84H5 F84H5 Table 22 1 Power Selection Settings for TB84H5 To User Vcc Settings Operating Mode Comments To User To User TB84H5 ow SMDS2 or SK 1000 TB84H5 External VDD gt 5 target board evaluation chip The target system must have a power supply of SMDS2 or SK 1000 SMDS2 or SK 1000 supplies Vpp to the target board evaluation chip and the target system SMDS2 or SK 1000 supplies Vpp only to the its own Table 22 2 Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part Comments External Triggers
113. El and DI instructions for this purpose System Mode Register SYM DEH Set 1 R W Global interrupt enable bit 0 Disable all interrupts processing 1 Enable all interrupts processing Not used for the S3C84H5 F84H5 Fast interrupt level selection bits Fast interrupt enable bit 0 Disable fast interrupts processing 000 IRQO 1 Enable fast interrupts processing 00 1 IRQ1 010 IRQ2 011 IRQ3 100 IRQ4 101 IRQ5 1 1 0 IRQ6 111 IRQ7 Figure 5 5 System Mode Register SYM 5 10 ELECTRONICS S3C84H5 F84H5 INTERRUPT STRUCTURE INTERRUPT MASK REGISTER IMR The interrupt mask register IMR set 1 DDH is used to enable or disable interrupt processing for individual interrupt levels After a reset all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine Each IMR bit corresponds to a specific interrupt level bit 1 to IRQ1 bit 2 to IRQ2 and so on When the IMR bit of an interrupt level is cleared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1 Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH Set 1 RQ6 Interrupt level enable bit 0 Disable IRQ interrupt 1 Enable
114. INT1 T1OVF1 is interrupt level IRQ2 vector T1INT1 also belongs to interrupt level IRQ2 but is assigned the separate vector address C8H A timer 1 1 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced A timer 1 1 match capture interrupt T1INT1 pending condition is also cleared by hardware when it has been serviced Interval Mode match The timer 1 0 module can generate an interrupt the timer 1 0 match interrupt T1INTO T1INTO belongs to interrupt level IRQ2 and is assigned the separate vector address In interval timer mode a match signal is generated and T1OUTO is toggled when the counter value is identical to the value written to the Timer 1 reference data registers TTDATAHO and T1DATALO The match signal generates a timer 1 0 match interrupt T1INTO vector and clears the counter value The timer 1 1 module can generate an interrupt the timer 1 1 match interrupt T1INT1 T1INT1 belongs to interrupt level IRQ2 and is assigned the separate vector address C8H In interval timer mode a match signal is generated and T1OUT1 is toggled when the counter value is identical to the value written to the Timer 1 reference data register TI DATAH1 and T1DATAL1 The match signal generates a timer 1 1 match interrupt T1INT1 vector C8H and clears the counter value Capture Mode In capture mode for timer 1 0 a signal edge that is detected at the T1CAPO pin opens
115. L I O INTERFACE OVERVIEW Serial module SIO can interface with various types of external devices that require serial data transfer The components of each SIO function block are 8 bit control register SIOCON Clock selection logic 8 bit data buffer SIODATA 8 bit presale SIOPS 3 bit serial clock counter Serial data I O pins SI SO External clock input pin SCK SIO module can transmit or receive 8 bit serial data at a frequency determined by its corresponding control register settings To ensure flexible data transmission rates you can select an internal or external clock source PROGRAMMING PROCEDURE To program the SIO module follow these basic steps 1 2 Configure the I O pins at port 2 SO SCK SI by loading the appropriate value to the P2CONL H Register Load an 8 bit value to the SIOCON control register to properly configure the serial module In this operation SIOCON 2 must be set to 1 to enable the data shifter For interrupt generation set the serial I O interrupt enable bit SIOCON 1 to 1 When you the transmit data to the serial buffer write data to SIODATA and set SIOCON 3 to 1 the shift operation starts When the shift operation transmit receive is completed the SIO pending bit SIOCON O is set to 1 and SIO interrupt request is generated ELECTRONICS 14 1 SERIAL I O INTERFACE S3C84H5 F84H5 SERIAL I O CONTROL REGISTERS SIOCON The control registers for seria
116. L OUTPUT PORT1 PUSH PULL OUTPUT PORT2 PUSH PULL OUTPUT PORT2 PUSH PULL OUTPUT PORTS PUSH PULL OUTPUT S3C84H5 F84H5 In debug mode you have to include three extra commands in initial routine to operate Ports correctly If you omit these commands Port do not operate correctly After you have finished your program and before assembling you have to remove these three commands ELECTRONICS S3C84H5 F84H5 BASIC TIMER BASIC TIMER OVERVIEW BASIC TIMER BT You can use the basic timer BT in two different ways As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction signal the end of the required oscillation stabilization interval after a reset or a Stop mode release The functional components of the basic timer block are Clock frequency divider fxx divided by 4096 1024 128 with multiplexer 8 bit basic timer counter set 1 bank 0 read only Basic timer control register BTCON set 1 D3H read write BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function It is located in set 1 address D3H and is read write addressable using register addressing mode A reset clears BTCON to 00H This enables the watchdog function and selects a basic timer clock frequency of
117. LEVELS In the ADC function block the analog input voltage level is compared to the reference voltage The analog input level must remain within the range AVss to AVnge AVnge Vp Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step The reference voltage level for the first bit conversion is always 1 2 AVper CONVERSION TIMING The A D conversion process requires 4 steps 4 clock edges to convert each bit and 10 clocks to step up A D conversion Therefore total of 50 clocks is required to complete a 10 bit conversion With a 10 MHz CPU clock frequency one clock cycle is 400 ns 4 fxx If each bit conversion requires 4 clocks the conversion rate is calculated as follows 4 clocks bit x 10 bits step up time 10 clock 50 clocks 50 clock x 400 ns 20 us at 10 MHz 1 clock time 4 fxx ADCON O 1 50 ADC Clock Conversion Start ADDATA Previous ADDATAH 8 Bit ADDATAL 2 Bit Value Set up 40 Clock time 10 clock Figure 16 4 A D Converter Timing Diagram 16 4 ELECTRONICS S3C84H5 F84H5 INTERNAL A D CONVERSION PROCEDURE 1 2 Analog input must remain between the voltage range of AVss and AVper that a check can be made to verify that the conversion was successful ADC module enters an idle state The digital conversion result can now be read from the ADDATAH and ADDATAL register
118. MICROCONTROLLERS Samsung s S3C8 series of 8 bit single chip CMOS microcontrollers offers a fast and efficient CPU a wide range of integrated peripherals and various mask programmable ROM sizes The major CPU features are Efficient register oriented architecture Selectable CPU clock sources and Stop power down mode released by interrupt or reset Built in basic timer wi th watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels Each level can have one or more interrupt sources and vectors Fast interrupt processing within a minimum of four CPU clocks can be assigned to specific interrupt levels S3C84H5 F84H5 MICROCONTROLLER The S3C84H5 F84H5 single chip CMOS microcontrollers are fabricated using the highly advanced CMOS process technology based on Samsung s latest CPU architecture The 53 84 5 is a microcontroller with a 16K byte mask programmable ROM embedded The S3F84H5 is a microcontroller with a 16K byte Flash ROM embedded Using a proven modular design approach Samsung engineers have successfully developed the S3C84H5 F84H5 by integrating the following peripheral modules with the powerful 8 core Five programmable I O ports 32 SOP SDIP 22pins 30 SDIP 20pins 28 SOP 18pins including ports shared with segment common drive outputs Four bit programmable pins for external interrupts One 8 bit basic timer for oscillation stabilization and wat
119. N UART pending lege UARTPND contol register UARTCON 246 A D converter control register ADCON A D converter data dais 23 eet ape converter data register Low Byte ADDATAL 249 Fom Location FBH is not mapped Location FCH is factory use only Location FEH is not mapped interrupt priority register PR 25 FH RW 4 2 ELECTRONICS S3C84H5 F84H5 CONTROL REGISTER Table 4 3 Set 1 Bank 1 Registers RegisterName Mnemonic Hex RW RN RN imera counter regse EM R Timer 10 data register High Byte TiDATAHo RW Timer 1 0 data register Low Byte TIDAT amp o RW Timer 10 data register High Bye TIDATAHi 20 Timer 1 1 data register Low Byte em RW Timer 110 contolregiser EM RW controlregister o ew Timer 10 counter register Low Byte 28 n Ls 1 counter register High 0 T1CNTH1 R Timer 1 1 counter Eg Low eye R UART onua rare regtsor ign eye Sr zm ee UART baud rate data register e 25 BRDATAL R W SIO pre scalar register R W siOdataregister soona Serial I O control register SIOCON R W PWM data register High mx 0 re R
120. O PP 10H RO 0FFH RO RO RAMCL1 GRO Destination 0 Source 0 Page 0 RAM clear starts RO 00H Destination lt 1 Source 0 Page 1 RAM clear starts RO 00H 2 7 ADDRESS SPACES S3C84H5 F84H5 REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file locations COH FFH The upper 32 byte area of this 64 byte space EOH FFH is expanded two 32 byte register banks bank 0 and bank 1 The set register bank instructions SBO or SB1 are used to address one bank or the other A hardware reset operation always selects bank 0 addressing The upper two 32 byte areas bank 0 and bank 1 of set 1 EOH FFH contains 64 mapped system and peripheral control registers The lower 32 byte area contains 16 system registers DOH DFH and a 16 byte common working register area You can use the common working register area as a scratch area for data operations being performed in other areas of the register file Registers in set 1 locations are directly accessible at all times using Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Chapter 3 Addressing Modes REGISTER SET 2 The same 64 byte physical space that is used for set 1 locations COH FFH is logically duplicated to add another 64 bytes of register space This expanded area of the register file
121. P2 6 RxD Configration Bits Input mode RxD input Alternative function mode Not used Push pull output mode 3 2 0 0 Input mode SCK input 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 0 0 0 Input mode 0 1 Alternative function mode Not used 0 Push pull output mode 1 Alternative function mode SO output NOTE In debug mode you have to include three extra commands in initial routine to operate Ports correctly If you omit these commands Port do not operate correctly Reter to page 9 14 After you have finished your program and before assembling you have to remove these three commands ORG 100H 581 Extra command only for debugging LD OF7H 5FH Extra command only for debugging SBO Extra command only for debugging ELECTRONICS 4 19 CONTROL REGISTERS S3C84H5 F84H5 P2CONL Port 2 Control Register Low Byte EDH Seti RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 3 AD7 SI Configration Bits Input mode 51 input Alternative function mode Not used Push pull output mode Alternative function mode AD7 5 4 3 2 O 0 Input mode T1CAPO input 0 1 Alternative function mode Not used 1 Alternative function mode PWM mode 1 0 P2 0 TBPWM T1CKO Configration Bits fo fo Input mode T1CKO input
122. PROGRAMMING Setting the Register Pointers SRP 70H RPO lt 70H RP1 lt 78H SRP1 48H RPO lt nochange RP1 48H SRPO RPO lt nochange CLR RPO RPO lt OOH RP1 lt nochange LD RP1 0F8H RPO lt nochange RP1 lt OF8H Register File Contains 32 8 Byte Slices 00001 8 Byte Slice 16 Byte Contiguous Working 00000XXX 8 Byte Slice Register block Figure 2 7 Contiguous 16 Byte Working Register Block ELECTRONICS 2 11 ADDRESS SPACES S3C84H5 F84H5 F7H 7 8 Byte Slice i FOH RO Regi ster File Contai ns 32 8 Byte Slices a wor ki ng regi ster block 7H R15 00000 X X 8 Figure 2 8 Non Contiguous 16 Byte Working Register Block PROGRAMMING Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H 85H using the register pointer The register addresses from 80H through 85H contain the values 10H 11H 12H 13H 14H and 15 H respectively SRPO 80H lt 80H ADD RO R1 RO lt RO R1 ADC RO R2 RO lt RO R2 C ADC RO R3 RO lt RO R8 C ADC RO R4 RO lt RO R4 C ADC RO R5 RO lt RO R5 C The sum of these six registers 6FH is located in the register RO 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to c
123. S3C84H5 F84H5 8 BIT CMOS MICROCONTROLLERS USER S MANUAL Revision 1 ELECTRONICS Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages S3C84H5 F84H5 8 Bit CMOS Microcontrollers User s Manual Revision 1 Publication Number 21 S3 C84H5 F84H5 012006 2006 Samsung Electronics Typical parameters can and do vary in different applications All operating parameters including 5 must be validated for each customer application by the customer
124. T P2 6 RxD 1 2 0 2 5 5 PWM T1CAPO P2 1 P2 4 SO T1OUTO AD4 P2 2 P2 3 AD7 SI 0 INTS T1OUT1 P1 3 VDD VSS Xout 1352068 Nid ct Figure 22 4 42 Pin Connector Pin Assignment for TB84H5 Target Board Target System J102 1 2 AB gt gt 2 2 5 2 o Q 2 2 2 2 9 Figure 22 5 TB84H5 Adapter Cable 44pin Connector Package 22 6 ELECTRONICS 53 8 SERIES MASK ROM ORDER FORM Product description Device Number 5308 write down the ROM code number Product Order Form Package Pellet Wafer Package Marking Check One Standard Custom A L Custom B Max 10 chars Max 10 chars each line YWW YWW Device Name SEC YWW Device Name 0111 1 1 9 Assembly site code Y Last number of assembly year WW Week of assembly Delivery Dates and Quantities Deliverable Required Delivery Date Quantity Comments ROM code Not applicable See ROM Selection Form Customer sample Please answer the following questions For what kind of product will you be using this order New model C Upgrade of an existing model Replacement of an existing model Others If you are replacing an existing model please indicate the former product name What the main reasons you decided to use a Samsung microcontroller in y
125. T block has a full duplex serial port with programmable operating modes There is one synchronous mode and three UART Universal Asynchronous Receiver Transmitter modes Shift Register I O with baud rate of fxx 16 x 16bit BRDATA 1 8 bit UART mode variable baud rate fxx 16 16bit BRDATA 1 9 bit UART mode variable baud rate fxx 16 16bit BRDATA 1 UART receive and transmit buffers are both accessed via the data register UDATA is at address F5H Writing to the UART data register loads the transmit buffer reading the UART data register accesses a physically separate receive buffer When accessing a receive data buffer shift register reception of the next byte can begin before the previously received byte has been read from the receive register However if the first byte has not been read by the time the next byte has been completely received the first data byte will be lost Overrun error In all operating modes transmission is started when any instruction usually a write operation uses the UDATA register as its destination address In mode 0 serial data reception starts when the receive interrupt pending bit UARTPND 1 is 0 and the receive enable bit UARTCON 4 is 1 In mode 1 and 2 reception starts whenever an incoming start bit 0 is received and the receive enable bit UARTCON 4 is set to 1 PROGRAMMING PROCEDURE To program the UART modules follow these basic steps 1 Configure P2 6 and P2
126. T e XTour eS 32 768 kHz Figure 7 1 Main Oscillator Circuit Figure 7 2 Sub System Oscillator Circuit Crystal or Ceramic Oscillator Crystal Oscillator ELECTRONICS 7 1 CLOCK CIRCUIT S3C84H5 F84H5 CLOCK STATUS DURING POWER DOWN MODES The two power down modes Stop mode and ldle mode affect the system clock as follows Stop mode the main oscillator is halted Stop mode is released and the oscillator is started by a reset operation or an external interrupt with RC delay noise filter and can be released by internal interrupt too when the sub system oscillator is running and watch timer is operating with sub system clock Idle mode the internal clock signal is gated to the CPU but not to interrupt structure timers and timer counters Idle mode is released by a reset or by an external or internal interrupt Stop Release Sol 4 2 Main Ststem Sub system Oscillator Oscillator Circuit Circuit Selector 1 Watch Timer OSCCON 3 5 0 5 2 v n STOP OSC 1 8 1 4096 Basic Timer inst Timer Counter Frequency 2 4 Watch Timer fxx 256 Dividing 5 UART AID 11 1 2 1 8 1 16 System Clock CLKCON 4 3 a Selector 2 CPU Clock gt IDLE Instruction Figure 7 3 Syst
127. T1CKO SO SCK RxD TxD TBPWM PWM Bit programmable port input or output mode selected by software input or push pull N channel open drain output Software assignable pull up NOTE In debug mode you have to include three extra commands in initial routine to operate Ports correctly If you omit these commands Port do not operate correctly Reter to page 9 14 After you have finished your program and before assembling you have to remove these three commands ORG 100H 581 Extra command only for debugging LD OF7H 5FH Extra command only for debugging SBO Extra Command Only for Debugging ELECTRONICS 9 1 5 S3C84H5 F84H5 PORT DATA REGISTERS Table 9 2 gives you an overview of the register locations of all seven S3C84H5 F84H5 1 port data registers Data registers for ports 0 1 2 and 3 have the general format shown in Table 9 2 Table 9 2 Port Data Register Summary Register Name Mnemonic Decimal Hex Location R W 9 2 ELECTRONICS S3C84H5 F84H5 PORTS PORT 0 Port 0 is an 4 bit I O port that you can use two ways General purpose digital I O Alternative function ADO AD3 Port 0 is accessed directly by writing or reading the port 0 data register PO at location set 1 bank 0 Port 0 Control Register POCON Port 0 has one 8 bit control registers POCON for 0 0 3 A reset clears the POCON registers to OOH configuring all pins to input modes You us
128. UART Mode 2 Function Description iiri kn eere b Bae tpa i 15 11 Serial Communication for Multiprocessor Configurations seen 15 13 Chapter 16 A D Converter Overview 16 1 Function Description 16 1 A D Converter Control Register 0 10222 2 2000 00 00 00000 00000000000 n nne e nnn nnn nennen 16 2 Internal Reference Voltage Levels eese enne nennen nennen mentre nennen 16 4 Conversion timiligi s o iris I ete ORE D tede abide te tei eer 16 4 Internal A D Conversion 16 5 Chapter 17 Watch Timer oV e deed 17 1 Watch Timer Control Register WTCON enne nennen nnne nennen nnns 17 2 Watch Timer Circuit 17 3 Chapter 18 Low Voltage Reset jV MAE Sire Giles ih aac Bee I seeded dedi de dd ed ae ed LE 18 1 S3C84H5 F84H5 MICROCONTROLLER Table of Contents continued Chapter 19 MTP Overview eee eee eee eee eee eee eee eee eee ee eee eee eee e
129. Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W 7 SIO Shift Clock Selection Bit 0 Interval clock P S Clock 1 External clock SCk 6 Data Direction Control Bit 0 MSB first mode 1 LSB first mode 5 SIO Mode Selection Bit 0 Receive only mode 1 Transmit Receive mode 4 Shift Clock Edge Selection Bit 0 Tx at falling edges Rx at rising edges 1 Tx at rising edges Rx at falling edges 3 SIO Counter Clear and Shift Start Bit 0 No action 1 Clear 3 bit counter and start shifting 2 SIO Shift Operation Enable Bit 0 Disable shift and clock counter 1 Enable shift and clock counter 1 SIO Interrupt Enable Bit 0 Disable SIO interrupt 1 Enable SIO interrupt 0 SIO Interrupt Pending Bit 4 26 0 No interrupt pending 1 Interrupt pending Clear pending bit when write ELECTRONICS S3C84H5 F84H5 CONTROL REGISTER SIOPS SIO Prescaler Register Set1 Bank1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Baud rate Input clock fxx SIOPS 1 x4 or SCK input clock SPH stack Pointer High Byte D8H Set 1 RESET Value X X X X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address High Byte The high byte stack pointer value is the upper eight bits of the 16 bit stack pointer address SP15 SP
130. W PWM data register LOW PWMDATAL 24 PWM control register PWMCON 245 F5H R W Location F6 F7H is not mapped Watch timer control register WTCON 248 F8H R W Location are not mapped ELECTRONICS 4 3 CONTROL REGISTERS Name of individual bit or related bits Bit number s that is are appended to the register name for bit addressing Register ID Register name FLAGS System Flags Register S3C84H5 F84H5 Register location Register address in the internal hexadecimal register file Bit Identifier RESET Value Read Write Bit Addressing Mode 7 7 6 5 4 3 x x X x x R W R W R W R W R W Register addressing mode only Carry Flag C 4 0 Operation does not generate a carry or borrow condiidn 0 Operation generates carry out or borrow into high order bit 7 Zero Flag Z 0 Operation result is a non zero value 0 Operation result is zero Sign Flag 5 0 Operation generates positive number MSB 0 0 Operation generates negative number MSB 1 R Read only W Write only R W Read write Not used Type of addressing that must be used to address the bit 1 bit 4 bit or 8 bit Figure 4 1 Description of the effect of specific bit settings RESETvalue notation Not used Undetermined value 0 2 Logic zero 1 Logic one Register Description Format Bit number
131. WMCON PWM Control Register ESSE OH ESORESESESEEESSESHESERESEEESEEESEESEESERESS 4 24 Register Pointer 0 4 25 1 Register Pointer 1 4 25 SIOCON Serial Module Control Registers sesusssusssesssessoessossssssossssssosssosssossessoessoossosssossessoe ie 4 26 SIOPS SIO Prescaler Register URNA EE INR AERE C NER EUN E 4 27 SPH Stack Pointer High Byte 4 27 SPL Stack Pointer Low Byte mr rana aT EAE TEMERE Nie eta oon 4 27 STOPCON Stop Control Register 4 28 SYM System Mode Register 4 29 T1 CONO Timer 1 0 Control Register 4 30 T1 1 1 1 Control Register 4 31 Timer A Control Register SSH ESHER ESSE ESS ESSHESR SSSR ESORESSESRESORESORESSRESSSSRESSEES 4 32 TBCON Timer B Control Register wesusssssssessesssssssssssusesssssssusssusssssusssesssusssessossossso suse ssoess
132. a register Timer 1 0 data register Timer 1 1 data register high byte TIDATAH1 230 data register low byte T1DATAL1 231 control register T1CONO control register T1CON1 Timer 1 1 Timer 1 0 Timer 1 1 Timer 1 0 counter register high byte T1CNTHO 234 Timer 1 0 counter register low byte TICNTLO 235 Timer 1 1 counter register high byte T1CNTH1 236 Timer 1 1 counter register low byte T1ONTL1 UART baud rate data register high BRDATAH UART baud rate data register low BRDATA 239 SIO pre scalar register SIOPS 240 SIO data register SIODATA 241 Serial I O control register SIOCON 242 F2H PWM data register High PWMDATAH 243 PWM data register LOW PWM control register Watch timer control register WTCON 248 FH 10 0 0 0 0 0 070 Location F9H FFH not mapped 8 4 ELECTRONICS S3C84H5 F84H5 RESET and POWER DOWN POWER DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP opcode 7FH In Stop mode the operation of the CPU and all peripherals is halted That is the on chip main oscillator stops and the supply current is reduced to less than 3 pA except for the current consumption of LVR Low voltage Reset circuit All system functions stop when the clock freezes but data stored in the internal register file is retained Stop mode can be released in one of two ways by a reset or by interrupts NOTE Do not use stop mode if you are using
133. a to store a program code be careful not to overwrite the vector addresses stored in these locations The ROM address at which a program execution starts after a reset is 0100H Decimal HEX 16 383 3FFFH Internal Program S3F84H5 16Kbyte Memory 255 OFFH 0 03CH 0 00H Figure 2 1 Program Memory Address Space 2 2 ELECTRONICS S3C84H5 F84H5 ADDRESS SPACES Smart Option Smart option is the ROM option for starting condition of the chip The ROM addresses used by smart option are from 003CH to 003FH The default value of ROM is FFH ROM Address 003CH Not used ROM Address 003DH Not used ROM Address 003EH LVR on off control bit Not used 0 Disable 1 Enable NOTE The value of unused bits of O8CH 08DH 03EH and must be logic 1 Figure 2 2 Smart Option ELECTRONICS 2 3 ADDRESS SPACES S3C84H5 F84H5 REGISTER ARCHITECTURE In the S3C84H5 F84H5 implementation the upper 64 byte area of register files is expanded two 64 byte areas called set 1 and set 2 The upper 32 byte area of set 1 is further expanded two 32 byte register banks bank 0 and bank 1 and the lower 32 byte area is a single 32 byte common area In case of S3C84H5 F84H5 the total number of addressable 8 bit registers is 334 Of these 334 registers 13 bytes are for CPU and system control registers 49 bytes are for peripheral control and data registers 16 bytes are used as a shared working registers and 256 re
134. ack pointer location OOFCH 10H into the high byte of the program counter The stack pointer then pops the value in the location OOFEH 1AH into the PC s low byte and the instruction at the location 101AH is executed The stack pointer now points to the memory location 00 ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET RL Rotate Left RL dst Operation C dst 7 dst 0 lt dst 7 dst n 1 lt dst n n 0 6 The contents of the destination operand are rotated left one bit position The initial value of bit 7 is moved to the bit zero LSB position and also replaces the carry flag as shown in the figure below p Flags C Setifthe bit rotated from the most significant bit position bit 7 was 1 Set if the result is 0 cleared otherwise Set if the result bit 7 is set cleared otherwise Set if arithmetic overflow occurred cleared otherwise Unaffected Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 90 R 4 91 IR Examples Given Register register 01H 02H and register 02H 17H RL 00H Register OOH 55H C 1 RL 01H gt Register 01H 02H register 02H 2 C 0 In the first example if the general register OOH contains the value 10101010B the statement RL OOH rotates the OAAH value left one bit position leaving the new value 55H 01010101 and setting the carry and
135. alculate the sum of these registers the following instruction sequence would have to be used ADD 80H 81H 80H lt 80H 81H ADC 80H 82H 80H 80H 82H C ADC 80H 83H 80H 80H 83H C ADC 80H 84H 80H lt 80H 84H C ADC 80H 85H 80H lt 80H 85H C Now the sum of the six registers is also located in register 80H However this instruction string takes 15 bytes of instruction code rather than 12 bytes and its execution time is 50 cycles rather than 36 cycles 2 12 ELECTRONICS S3C84H5 F84H5 ADDRESS SPACES REGISTER ADDRESSING The S3C8 series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time With Register R addressing mode in which the operand value is the content of a specific register or register pair you can access any location in the register file except for set 2 With working register addressing you use a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register and the leas
136. alue is greater than gt the counter value One pulse width is equal to TIMER 1 0 1 CONTROL REGISTER T1CONO T1CON1 You use the timer 1 0 1 control register TI CONO 1 to Select the timer 1 0 1 operating mode Interval timer Capture mode PWM mode Select the timer 1 0 1 input clock frequency Clear the timer 1 0 1 counter TI CNTHO LO T1CNTH1 L1 Enable the timer 1 0 1 overflow interrupt Enable the timer 1 0 1 match capture interrupt T1CONO is located in set 1 and Bank 1 at address E8H and is read write addressable using Register addressing mode 1 is located set 1 and Bank 1 at address E9H and is read write addressable using Register addressing mode A reset clears TI CONO T1CON 1 to OOH This sets timer 1 0 1 to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer 1 0 1 interrupts To disable the counter operation please set T1CON 0 1 7 5 to 111B You can clear the timer 1 0 1 counter at any time during normal operation by writing a 1 to 0 1 3 The timer 1 0 overflow interrupt T1OVFO is interrupt level IRQ2 and has the vector address C6H And the timer 1 1 overflow interrupt T1OVF1 is interrupt level IRQ2 and has the vector address CAH To generate the exact time interval you should write 1 to 0 1 2 and clear appropriate pending bits of the TINTPND register To detect matc
137. ample except that external program memory is accessed Figure 3 10 Direct Addressing for Load Instructions 3 10 ELECTRONICS S3C84H5 F84H5 ADDRESSING MODES DIRECT ADDRESS MODE Continued Program Memory Next OPCODE Memory Address Used Upper Address Byte Lower Address Byte OPCODE Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instructions ELECTRONICS 3 11 ADDRESSING MODES S3C84H5 F84H5 INDIRECT ADDRESS MODE IA In Indirect Address IA mode the instruction specifies an address located in the lowest 256 bytes of the program memory The selected pair of memory locations contains the actual address of the next instruction to be executed Only the CALL instruction can use the Indirect Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Program Memory Next Instruction LSB Must be Zero dst OPCODE Current Instruction Lower Address Byte Program Memory Upper Address Byte Locations 0 255 Sample Instruction CALL 40H The 16 bit value in program memory addresses 40H and 41H is the subroutine start address Figure 3 12 In
138. an external clock source because Xy input must be restricted internally to Vgg to reduce current leakage Using RESET to Release Stop Mode Stop mode is released when the RESET signal is released and returns to high level all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained A reset operation automatically selects a slow clock 1 16 because CLKCON 3 and CLKCON 4 are cleared to After the programmed oscillation stabilization interval has elapsed the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H and 0101H Using an External Interrupt to Release Stop Mode External interrupts with an RC delay noise filter circuit can be used to release Stop mode Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller s current internal operating mode The external interrupts in the S3C84H5 F84HB interrupt structure that can be used to release Stop mode are External interrupts P1 0 P1 3 INTO INT3 Please note the following conditions for Stop mode release Ifyou release Stop mode using an external interrupt the current values in system and peripheral control registers are unchanged lf you use an external interrupt for Stop mode release you can also program the duration of the oscillation stabilization interval To do this you must make the appro
139. ared to 0 2 When you write a 1 to BTCON O the corresponding frequency divider is cleared to Immediately following the write operation the 0 value is automatically cleared to 0 3 The fxx is selected clock for system main OSC or sub OSC 4 6 ELECTRONICS S3C84H5 F84H5 CONTROL REGISTER CLKCON System Clock Control Register D4H Set 1 Bit Identifier 7 6 5 4 8 2 13 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W Addressing Mode Register addressing mode only 7 5 Not used for the S8C84H5 F84H5 must keep always 0 4 3 CPU Clock System Clock Selection Bits 1016 oopen 7 me 2 0 2 0 Not used for the 53 84 5 84 5 keep always 0 NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and CLKCON 4 ELECTRONICS 4 7 CONTROL REGISTERS S3C84H5 F84H5 FLAGS System Flags Register D5H Set 1 RESET Value X X X X X X 0 0 Read Write R W R W R W R W R W R W R R W Addressing Mode Register addressing mode only 7 Carry Flag C 0 Operation does not generate a carry or underflow condition 1 Operation generates a carry out or underflow into high order bit 7 6 Zero Flag Z EN Operation result is a non zero value Operation result is zero 5 Sign Flag S Operation generates a positive number MSB 0 Op
140. ation value 10H leaving 14H in the register R1 6 14 ELECTRONICS S3C84H5 F84H5 ADD aaa ADD Operation Flags Format Examples dst src dst dst src INSTRUCTION SET The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed C 2 6 9 Set if there is carry from the most significant bit of the result cleared otherwise Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise Set if arithmetic overflow occurred that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise Always cleared to 0 Set if a carry from the low order nibble occurred Bytes Cycles Opcode Addr Mode Hex dst src opc dst src 2 4 02 r r 6 03 r Ir opc src dst 3 6 04 R R 05 R IR dst src 3 6 06 R IM Given R1 12H R2 register 01H 21H register 02H register OAH ADD R1 R2 gt R1 15H R2 03H ADD R1 R2 gt R1 1CH R2 03H ADD 01H 02H gt Register 01H 24H register 02H ADD 01 002 gt Register 01H 2BH register 02H 03H ADD 01H 25H gt Register 01H 46H In the first example the destination working register R1 contains 12H and the source working register R2 contains 03H The statem
141. by writing TB8 to 0 or 1 and set PEN bit of UARTPND register to 1 Only 8 bits BitO to Bit7 of received data are available for data value 4 The receive operation starts when the signal at the RxD pin goes to low level ELECTRONICS 14 11 UART S3C84H5 F84H5 Tx Clock Write to Shift Register UARTDATA shi n n n TO start it X D2 Y o Y D4 X pe Y o X 2 7 Stop Bit TIP Transmit TB8 or Parity bit RB8 or Parity bit Rx ONN T 11 RxD Start Bit DO D1 D2 D3 D4 D5 D6 D7 Stop Bit Bt Detect Sampie Time UT Shift 2111 L JL J RIP Figure 15 8 Timing Diagram for UART Mode 2 Operation 15 12 ELECTRONICS S3C84H5 F84H5 UART SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS The S3C9 series multiprocessor communication features let a master S3C84H5 F84H5 send a multiple frame serial message to a slave device in a multi S3C84H5 F84H5 configuration It does this without interrupting other slave devices that may be on the same serial line This feature can be used only in UART mode 2 with the parity disable mode In mode 2 9 data bits are received The 9th bit value is written to RB8 UARTCON 2 The data receive operat
142. cation The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes Irr an even number for program memory and an odd number for external data memory Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst sre src dst 2 14 F2 Irr r Examples Given RO 77H R6 30H and R7 OOH LDCPD RR6 RO RR6 RR6 1 77H the contents of RO is loaded into program memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 OFFH RR6 lt RR6 1 77H the contents of RO is loaded into external data memory location 2FFFH 3000H 1H LDEPD RR6 RO NOTE LDEPD instruction can be used to read write the data of 64 Kbyte data memory 6 56 ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET LDCPI LDEPI Load Memory with Pre Increment LDCPI dst src LDEPI dst src Operation rm m 1 dst src These instructions are used for block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair and is first incremented The contents of the source location are loaded into the destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags
143. chdog function system reset Two 8 bit timer counter and Two 16 bit timer counter with selectable operating modes asynchronous UART One synchronous SIO One 10 bit PWM output 10 bit 8 channel A D converter Watch timer for real time The 53 84 5 84 5 is versatile microcontroller for home appliances and ADC applications etc They are currently available in 32 SOP SDIP 30 SDIP 28 SOP package ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES CPU SAM8RC CPU core Memory e 272 bytes internal register file e 16Kbytes internal multi time program memory Oscillation Sources e Main clock oscillator Crystal Ceramic CPU clock divider 1 1 1 2 1 8 1 16 Instruction Set e 78instructions e IDLE and STOP instructions added for power down modes Instruction Execution Time 400 ns at 10 MHz fosc minimum Interrupts e 16 interrupt sources with 16 vectors e 8level 16 vector interrupt structure Ports e Total 22 bit programmable pins 32 SOP SDIP Total 20 bit programmable pins 30 SDIP Total 18 bit programmable pins 28SOP Timers and Timer Counters e programmable 8 bit basic timer BT for oscillation stabilization control or watchdog timer function e 8 bit timer counter Timer A with three operating modes Interval mode capture mode and PWM mode e One8 bit timer Timer B with carrier frequency or PWM generator e Two 16 bit timer co
144. ck RPO 7 RP1 8 This 16 byte address range is called common area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between different pages Following a hardware reset register pointers RPO and RP1 point to the common working register area locations COH CFH 1100 0000 1 1100 1000 Figure 2 11 Common Working Register Area ELECTRONICS 2 15 ADDRESS SPACES S3C84H5 F84H5 PROGRAMMING TIP Addressing the Common Working Register Area As the following examples show you should access working registers in the common area locations using working register addressing mode only Examples 1 LD 0C2H 40H Invalid addressing mode Use working register addressing instead SRP 0COH LD R2 40H R2 C2H the value in location 40H Example 2 ADD 0C3H 45H Invalid addressing mode Use working register addressing instead SRP 0COH ADD R3 45H R3 45H 4 BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8 byte slice of working register space The address information stored in a register pointer serves as an addressing window that makes it possible for instructions to access working registers very efficiently using short 4 bit addresses When an ins
145. clears the counter If for example you write the value 10H to TADATA and 0AH to TACON the counter will increment until it reaches 10H At this point the Timer A interrupt request is generated the counter value is reset and counting resumes Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TAOUT pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the Timer A data register TADATA In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from 00H Although you can use the match signal to generate a timer A overflow interrupt interrupts are not typically used in PWM type applications Instead the pulse at the TAOUT pin is held to Low level as long as the reference data value is less than or equal to x the counter value and then the pulse is held to High level for as long as the data value is greater than gt the counter value One pulse width is equal to 256 Capture Mode In capture mode a signal edge that is detected at the TACAP pin opens a gate and loads the current counter value into the Timer A data register You can select rising or falling edges to trigger this operation Timer A also gives you capture input source the signal edge at the TACAP pin You select the capture
146. cy generator Timing tests in high speed mode ELECTRONICS 17 1 S3C84H5 F84H5 WATCH TIMER CONTROL REGISTER WTCON R W re wrcon wrcons wrcons Table 17 1 Watch Timer Control Register WTCON Set 1 Bank 1 F8H R W Bit Name Values Function Address WTCON 7 o Select fx 256 as the watch timer clock fx Main clock uM Select subsystem clock as watch timer clock WTCON 6 Disable watch timer interrupt _o Enable watch timer interrupt 4 fo 0 5 kHz buzzer BZOUT signal output JEN 1 kHz buzzer BZOUT signal output 2 kHz buzzer BZOUT signal output 1 1 4kHz buzzer BZOUT signal output 0 O Set watch timer interrupt to 0 5 6 0 1 Set watch timer interrupt to 0 25 s EN Set watch timer interrupt to 0 125 s Set watch timer interrupt to 1 955 ms WTCON 1 Disable watch timer clear frequency dividing circuits Enable watch timer 0 Interrupt is not pending clear pending bit when write Interrupt is pending NOTE Main system clock frequency fx is assumed to be 9 8304 MHz 17 2 ELECTRONICS S3C84H5 F84H5 WATCH TIMER WATCH TIMER CIRCUIT DIAGRAM BUZZER Output BZOUT 8 WTCON 6 6 fw 64 0 5 kHz fw 32 fw 16 2 fw 8 4 kHz Circuit WTCON 5 WTCON 4 WTCON 3 WTCON 2 WTCON 1 Enable Disable Frequency WTCON 7 Clock Dividing
147. d to O V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc dst b 0 src 3 6 07 ro Rb src 1 481 3 6 07 Rb ro NOTE the second byte of the 3 byte instruction format the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bit Given R1 07H and register 01H 03H BOR R1 01H 1 gt R1 07H register 01H 03H BOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example the destination working register R1 contains the value 07H 00000111B and the source register 01H the value 0000001 1B The statement BOR R1 01H 1 logically ORs bit one of the register 01H source with bit zero of R1 destination This leaves the same value 07H in the working register R1 In the second example the destination register 01H contains the value 0000001 1B and the Source working register R1 the value 07H 00000111B The statement BOR 01H 2 R1 logically ORs bit two of the register 01H destination with bit zero of R1 source This leaves the value 07H in the register 01H ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET BTJ Bit Test Jump Relative on False BTJRF dst src b Operation If src b is a 0 then PC PC dst The specified bit within the source operand is tested If it is a the relative address is added to the program counter and control passes to the sta
148. ddressing 3 13 3 14 Immediate Addressing 3 14 4 1 Register Description 4 4 S3C84H5 F84H5 MICROCONTROLLER xi List of Figures Continued Figure Title Page Number Number 5 1 S3C8 Series Interrupt Types wee eee eee eee 5 2 5 2 S3C84H5 F84HbInterrupt Structure 5 4 5 3 ROM Vector Address Area mme 5 5 5 4 Interrupt Function Diagram 5 8 5 5 System Mode Register SYM 5 10 5 6 Interrupt Mask Register IMR 0000 GA 5 11 5 7 Interrupt Request Priority Groups See eee eee eee eee eee ere eee eee eee reer eee eee 5 12 5 8 Interrupt Priority Register IPR 5 13 5 9 Interrupt Request Register IRQ 5 14 6 1 System Flags Register FLAGS 6 6 7 1 Main Oscillator Circuit Crystal or Ceramic Oscillator mmmemmm 7 1 7 2 Sub System Oscillator Circuit Crystal Oscillator AAA B S 7 1 7 3 System Clock Circuit Diagram LG 7 2 7 4 System Clock Control Register CLKCON See eee eee eee rete reer reer eee ert trite 7 3 7 5 Oscillator C
149. direct Addressing 3 12 ELECTRONICS S3C84H5 F84H5 ADDRESSING MODES RELATIVE ADDRESS MODE RA In Relative Address RA mode a twos complement signed displacement between 128 and 127 is specified in the instruction The displacement value is then added to the current PC value The result is the address of the next instruction to be executed Before this addition occurs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR Program Memory Next OPCODE Program Memory Address Used FEE m PC Value Displacement Current Instruction OPCODE Signed Displacement Value Sample Instructions JR ULT OFFSET Where OFFSET is a value in the range 127 to 128 Figure 3 13 Relative Addressing ELECTRONICS 3 13 ADDRESSING MODES S3C84H5 F84H5 IMMEDIATE MODE IM In Immediate IM addressing mode the operand value used in the instruction is the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers Program Memory OPERAND OPCODE The Operand value is in the instruction Sample Instruction LD RO ZOAAH Figure
150. e note Hex dst cc opc dst 2 6 ccB RA cc O to F NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits in length Given The carry flag 1 and LABEL X 1FF7H JR C LABEL X gt PC 1FF7H If the carry flag is set that is if the condition code is true the statement JR C LABEL X will pass control to the statement whose address is currently in the program counter Otherwise the program instruction following the JR will be executed ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET L D Load LD dst src Operation dst lt src The contents of the source are loaded into the destination The source s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst sre dst opc src 2 4 rc r IM 4 r8 r R src opc dst 2 4 r9 R r r OtoF opc dst src 2 4 C7 r Ir 4 D7 Ir r opc src dst 3 6 E4 R R 6 E5 R IR opc dst src 3 6 E6 R IM 6 D6 IR IM src dst 3 6 F5 IR R dst src 3 6 87 r x r src dst 3 6 97 r ELECTRONICS 6 49 INSTRUCTION SET LD Load LD Continued Examples Given RO 01H R1 OAH register OOH 01H register 01H 20H register 02H LD RO 10H LD R0 01H LD 01H RO LD R1 RO LD RO R1 LD 00H 01H LD 02H 00H LD 00H OAH LD 00H 10H
151. e Table 12 2 If for example the value in the extension PWMDATAH register is O0B and PWMDATAL register is 01B the 2nd cycle will be one pulse longer than the other cycles If the base duty cycle is 50 96 the duty of the 2nd cycle will therefore be stretched to approximately 5196 duty For example if you write 10B to the extension data register all odd numbered pulses will be one cycle longer If you write 11H to the extension data register all pulses will be stretched by one cycle except the 4th pulse PWM output goes to an output buffer and then to the corresponding PWM output pin In this way you can obtain high output resolution at high frequencies 13 2 ELECTRONICS S3C84H5 F84H5 10 BIT PWM PULSE WIDTH MODULATION Table 13 2 PWM output stretch Values for Extension Data Register PWMDATAL 1 0 PWMDATAL Bit Bit1 BitO Stretched Cycle Number 11 o HM 1 2 3 PWM Data 0H 100H 200H Clock 00000000B Xxxxxx00B 00000001B Register Values PWMDATAH PWMDATAL 10000000B XXxxxx00B 11111111B Xxxxxx00B Figure 13 1 10 Bit PWM Basic Waveform ELECTRONICS 13 3 10 PWM PULSE WIDTH MODULATION S3C84H5 F84H5 OH PWM Clock 4 MHz 00000010B XXxxxx01B PWMDATA 00001001B Wavetorm XXXXXX01 B Extended waveform Figure 13 2 10 Bit Extended PWM Waveform 13 4 ELECTRONICS S3C84H5 F84H5 10 BIT PWM PULSE WIDTH MODULATION
152. e after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 15 High Address A PCL PCL Top of stack RGH Top of stack Stack contents Stack contents after a call after an instruction interrupt v Low Address Figure 2 16 Stack Operations User Defined Stacks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers SPL SPH Register locations D8H and D9H contain the 16 bit stack pointer SP that is used for system stack operations The most significant byte of the SP address SP15 SP8 is stored in the SPH register D8H and the least significant byte SP7 SPO is stored in the SPL register D9H After a reset the SP value is undetermined Because only internal memory space is implemented in the S3C8415 C8419 F8419 the SPL must be initialized to an 8 bit value in the range 0 The SPH register is not needed and can be used as a general purpose register if necessary When the SPL register contains the only stack pointer value that is when it points to a system stack in the register file you can use the SPH register as a general purpose data register However if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register durin
153. e bit in length Examples Given R1 07H 00000111B and register 01H 00000011B BXOR R1 01H 1 gt R1 06H register 01H BXOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example the destination working register R1 has the value 07H 00000111B and the Source register 01H has the value 03H 00000011B The statement BXOR R1 01H 1 exclusive ORs bit one of the register 01H the source with bit zero of R1 the destination The result bit value is stored in bit zero of R1 changing its value from 07H to 06H The value of the source register 01H is unaffected ELECTRONICS 6 25 INSTRUCTION SET S3C84H5 F84H5 CALL Procedure CALL Operation Flags Format Examples dst SP SP 1 lt PCL SP lt SP 1 SP lt PCH PC lt dst The contents of the program counter are pushed onto the top of the stack The program counter value used is the address of the first instruction following the CALL instruction The specified destination address is then loaded into the program counter and points to the first instruction of a procedure At the end of the procedure the return instruction RET can be used to return to the original program flow RET pops the top of the stack back into the program counter No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 3 14 F6 DA opc dst 2 12 F4 IRR opc dst 2 14 D4 IA Given RO 35H R1
154. e condition code and the OPCODE are both four bits Examples Given The carry flag C 1 register 00 01H and register 01 20H Secs JP C LABEL_W gt LABEL_W 1000H PC 1000H JP 00 gt PC 0120H The first example shows a conditional JP Assuming that the carry flag is set to 1 the statement JP C LABEL_W replaces the contents of the PC with the value 1000H and transfers control to that location Had the carry flag not been set control would then have passed to the statement immediately following the JP instruction The second example shows an unconditional JP The statement JP 00 replaces the contents of the PC with the contents of the register pair and 01H leaving the value 0120H ELECTRONICS 6 47 INSTRUCTION SET S3C84H5 F84H5 JR Jump Relative JR Operation Flags Format Example cc dst If cc is true PC dst If the condition specified by the condition code cc is true the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See the list of condition codes at the beginning of this chapter The range of the relative address is 127 128 and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement No flags are affected Bytes Cycles Opcode Addr Mod
155. e control registers settings to select input or output mode push pull and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 0 control registers must also be enabled in the associated peripheral module Port 0 Control Register Low Byte E6H Set1 Bank0 R W Reset value 00H 6 5 4 3 2 7 6 PO 3 ADC3Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 Alternative function mode AD3 input 5 4 P0 2 AD2 Configuration Bits 00 Input mode 01 Input mode with pull up 1 0 Push pull output mode 1 1 Alternative function mode ADC2 input 3 2 1 ADC1 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 Alternative function mode ADC1 input 1 0 Configuration Bits 0 0 Input mode 0 1 Input mode with pull up 1 0 Push pull output mode 1 1 Alternative function mode ADCO input Figure 9 1 Port 0 Low Byte Control Register POCON ELECTRONICS 9 3 5 S3C84H5 F84H5 PORT 1 Port 1 is a 6 bit I O port with individually configurable pins that you can use two ways General purpose digital I O Alternative function INTO INT3 TAOUT TACK TACAP T1OUTO T1CK1 T1CAP1 AD5 AD6 Port 1 is accessed directly by writing or reading the port 1 data r
156. e eee ee eee eee eee eee A A AA A A A A A A AA A A A A A A A AAA A A AA AAA A A A A AA A A AA 1 9 1 Chapter 20 Electrical Data OVervie Ws eet Dee Nd 20 1 Chapter 21 Mechanical Data OVEN VIG Winton UE emat AN a a c CAR cl E EN le 21 1 Chapter 22 Development Tools Overview 22 1 SHINE e eins t faa t ta tme e e eld no S oet 22 1 SASM i uniebeuee edmiewa A dnnueadinumieime amari eun piti 22 1 SAMA Assembler Eee pe tete eie e eee o s 22 1 HEX2ROM re DUBIE UB rexit 22 1 Target 5 eves cde en sudeste 22 2 TB84H5 Board ss n ides c icd ee aduer m in een 22 3 IDLE LED ais 22 4 STOP LED RENE eee ed ande ee eae 22 4 S3C84H5 F84H5 MICROCONTROLLER List of Figures Figure Title Page Number Number 1 1 S3C84H5 F84H5 Block Diagram 1 3 1 2 S3C84H5 F84H5 Pin Assignment 32 pin SOP SDIP ARM 1 4 1 3 S3C84H5 F84H5 Pin Assignment 30 pin SDIP 1 5 1 4 S3C84H5 F84H5 Pin Assignment 28 pin SOP Pee eee errr rere eee eee ee eee eee e
157. e multiprocessor communications 1 Set all S3C84H5 F84H5 devices masters and slaves to UART mode 2 with parity disable Write the MCE bit of all the slave devices to 1 The master device s transmission protocol is First byte the address identifying the target slave device 9th bit 1 Next bytes data 9th bit 0 When the target slave receives the first byte all of the slaves are interrupted because the 9th data bit is 1 The targeted slave compares the address byte to its own address and then clears its MCE bit in order to receive incoming data The other slaves continue operating normally Full Duplex Multi S3C84H5 F84H5 Interconnect TxD RxD Master Slave 1 22 Slave S3C84H5 S3C84H5 S3C84H5 S3C84H5 F84H5 F84H5 F84H5 F84H5 Figure 15 9 Connection Example for Multiprocessor Serial Data Communications 15 14 ELECTRONICS S3C84H5 F84H5 A D CONVERTER A D CONVERTER OVERVIEW The 10 bit A D converter ADC module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10 bit digital values The analog input level must lie between the AVngr AVss values The A D converter has the following components Analog comparator with successive approximation logic D A converter logic resistor string type control register ADCON set 1 bank 0 F7H read write but ADCON 3 is read only Eight multipl
158. ee etter 1 6 1 5 Pin Circuit Type B nRESET AAA 1 11 1 6 Pin Circuit Type OTT 1 11 1 7 Pin Circuit Type 1 12 1 8 Pin Circuit Type D 5 P1 0 P1 3 Pee eee rere eee ee eee reer errr eee eee errr eee eee AAA A 1 12 1 9 Pin Circuit Type E P2 2 P2 3 P1 4 1 5 1 13 1 10 Pin Circuit Type G P3 0 P3 4 vw G AR 1 14 2 1 Program Memory Address Space 2 2 2 2 Smart Option Peer ee ere eee reer reer e rere etree etree o oaaee eee 2 3 2 3 Internal Register File Organization 2 5 2 4 Register Page Pointer PP 2 6 2 5 Set 1 Set 2 Prime Area Register 2 9 2 6 8 Byte Working Register Areas Slices 2 10 2 7 Contiguous 16 Byte Working Register Block 2 11 2 8 Non Contiguous 16 Byte Working Register Block M M M 9 9 eee 2 12 2 9 16 Bit Register Pair 2 1 3 2 10 Register File Addressing 2 14 2 11 Working Register 2 15 2 12 4 Working Register Addressing 2 17 2 13 4 Bit Working Register Addressing E
159. egister 04H register 01H 05H register 04 05H If the user stack pointer the register for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leaving the value 04H The 01H register value 05H is then loaded into the location addressed by the incremented user stack pointer ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET RCF Reset Carry Flag RCF RCF Operation C 0 The carry flag is cleared to logic zero regardless of its previous value Flags C Cleared to O No other flags are affected Format Bytes Cycles Opcode Hex 1 4 Given 1 or 0 The instruction RCF clears the carry flag to logic zero ELECTRONICS 6 69 INSTRUCTION SET S3C84H5 F84H5 RET Return RET Operation Flags Format Example PC SP SP lt SP 2 RET instruction is normally used to return to the previously executed procedure at the of the procedure entered by a CALL instruction The contents of the location addressed by the stack pointer are popped into the program counter The next statement to be executed is the one that is addressed by the new program counter value No flags are affected Bytes Cycles Opcode Hex opc 1 10 AF Given SP OOFCH SP 101AH and PC 1234 RET gt PC 101AH SP OOFEH The RET instruction pops the contents of the st
160. egister P1 at location E1H in set 1 bank 0 Port 1 Control Register P1CONH P1CONL Port 1 has two 6 bit control registers PI CONH for 4 1 5 and P1CONL for 1 0 1 3 A reset clears the P1CONH and P1CONL registers to OOH configuring all pins to input modes You use control registers settings to select input or output mode push pull and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 1 control registers must also be enabled in the associated peripheral module Port 1 Interrupt Enable Pending and Edge Selection Registers P1INT P1INTPND To process external interrupts at the port 1 pins three additional control registers are provided the port 1 interrupt enable register EAH SET1 BANK 0 the port 1 interrupt pending bits P1INTPND SET1 BANK 0 The port 1 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated The application program detects interrupt requests by polling the P1INTPND1 3 0 register at regular intervals When the interrupt enable bit of any port 1 pin is 1 a rising or falling edge at that pin will generate an interrupt request The corresponding P1INTPND1 bit is then automatically set to 1 and the IRQ level goes low to signal the CPU that an interrupt request is waiting W
161. egister UDATA F5H The start and stop bits are generated automatically by hardware Mode 1 Receive Procedure 1 Select the baud rate to be generated by 16bit BRDATA 2 Select mode 1 and set the RE Receive Enable bit in the UARTCON register to 1 3 The start bit low 0 condition at the RxD P1 4 pin will cause the UART module to start the serial data receive operation Tx Clock Write to Shift Register UDATA shit TxD start Bit DO x D1 X D2 X D3 x D4 X D5 X D6 07 Stop Bit TIP Transmit Bit Detect Sample Time Shift Figure 15 7 Timing Diagram for UART Mode 1 Operation 15 10 ELECTRONICS S3C84H5 F84H5 UART UART MODE 2 FUNCTION DESCRIPTION In mode 2 11 bits are transmitted through the TxD pin or received through the RxD pin Each data frame has four components Start bit 0 8 data bits LSB first Programmable 9th data bit or parity bit Stop bit 1 In parity disable mode PEN z 0 gt The 9th data bit to be transmitted can be assigned a value of 0 or 1 by writing the TB8 bit UARTCON 3 When receiving the 9th data bit that is received is written to the RB8
162. egisters Using the two 8 bit register pointers RP1 and RPO two working register slices can be selected at any one time to form a 16 byte working register block Using the register pointers you can move this 16 byte register block anywhere in the addressable register file except for the set 2 area The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces One working register s ice is 8 bytes eight 8 bit working registers RO R7 or R8 R15 One working register block is 16 bytes sixteen 8 bit working registers RO R15 All the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to one of the 24 slices in the register file other than set 2 The base addresses for the two selected 8 byte register slices are contained in register pointers and After a reset RPO and always point to the 16 byte common area in set 1 COH CFH FFH li 2 11111XXX Slice 31 De FOH Set 1 RP1 Registers R8 R15 Onl nly Each register pointer points to one 8 byte slice of the register CFH space selecting a total 16 ae COH byte working register block 00000XXX RPO Registers RO R7 10H FH lice 1 Slice Figure 2 6 8 Byte Working Register Areas Slices 2 10 ELECTRONICS
163. elect mode 0 by setting UARTCON 6 and 7 to 00B 2 Write transmission data to the shift register UDATA F5H to start the transmission operation Mode 0 Receive Procedure Select mode 0 by setting UATCON 6 and 7 to 00B 2 Clear the receive interrupt pending bit UARTPND 1 by writing a 0 to UARTPND 1 3 Setthe UART receive enable bit UARTCON 4 to 1 4 The shift clock will now be output to the TxD P2 7 pin and will read the data at the RxD P2 6 pin A UART receive interrupt vector E4H occurs when UARTCON 1 is set to 1 Write to Shift Register UDATA Shift 0 X v X 9 X o X P X m X 7 TxD Shift Clock TIP Write to UARTPND Clear RIP set RE Shift RxD Data In DO D1 D2 D3 D4 D5 D6 D7 grs ap Figure 15 6 Timing Diagram for UART Mode 0 Operation ELECTRONICS Transmit Receive UART S3C84H5 F84H5 UART MODE 1 FUNCTION DESCRIPTION In mode 1 10 bits are transmitted through the TxD P2 7 pin or received through the RxD P2 6 pin Each data frame has three components Start bit 0 8 data bits LSB first Stop bit 1 When receiving the stop bit is written to the bit in the UARTCON register The baud rate for mode 1 is variable Mode 1 Transmit Procedure 1 Select the baud rate generated by 16bit BRDATA 2 Select mode 1 8 bit UART by setting UARTCON bits 7 and 6 to 01B 3 Write transmission data to the shift r
164. em Clock Circuit Diagram 7 2 ELECTRONICS S3C84H5 F84H5 CLOCK CIRCUIT SYSTEM CLOCK CONTROL REGISTER CLKCON The system clock control register is located in set 1 address It is read write addressable and has the following functions Oscillator frequency divide by value After the main oscillator is activated and the fxx 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed fxx 8 fxx 2 or fxx 1 XTIN S3C84H5 L S3F84H5 XTOUT 32 768 kHz Figure 7 4 System Clock Control Register CLKCON ELECTRONICS 7 3 CLOCK CIRCUIT S3C84H5 F84H5 Oscillator Control Register OSCCON F2H Set 1 Bank 0 R W II Ile Not used must keep always 0 Not used must keep always 0 System clock selection bit 0 Main oscillator select 1 Subsystem oscillator select Subsystem oscillator control bit 0 Subsystem oscillator RUN 1 Subsystem oscillator STOP Mainsystem oscillator control bit 0 Mainsystem oscillator RUN 1 Mainsystem oscillator STOP NOTE When the CPU is operated with fxt sub oscillation clock it is possible to use the stop instruction but in this case before using stop instruction you must select fxx 128 for basic timer counter input clock Then the oscillation stabilization time is 62 5 1 32768 x 128 x 16 ms 100 ms Here the warm up time is from the time that the stop release signal acti
165. emonic Instruction Rotate and Shift Instructions RL dst RLC dst RR dst RRC dst SRA dst SWAP dst CPU Control Instructions CCF DI EI IDLE NOP RCF SBO SB1 SCF SRP src SRPO src SRP1 src STOP ELECTRONICS Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic Swap nibbles Complement carry flag Disable interrupts Enable interrupts Enter Idle mode No operation Reset carry flag Set bank 0 Set bank 1 Set carry flag Set register pointers Set register pointer 0 Set register pointer 1 Enter Stop mode INSTRUCTION SET S3C84H5 F84H5 FLAGS REGISTER FLAGS The flags register FLAGS contains eight bits which describe the current status of CPU operations Four of these bits FLAGS 7 FLAGS 4 can be tested and used with conditional jump instructions Two other flag bits FLAGS 3 and FLAGS 2 are used for BCD arithmetic The FLAGS register also contains a bit to indicate the status of fast interrupt processing FLAGS 1 and a bank address status bit FLAGS 0 to indicate whether register bank 0 or bank 1 is currently being addressed FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome
166. ent ADD R1 R2 adds 03H to 12H leaving the value 15H in the register R1 ELECTRONICS 6 15 INSTRUCTION SET AND Logical AND AND Operation Flags Format Examples dst src dst lt dst AND src S3C84H5 F84H5 The source operand is logically ANDed with the destination operand The result is stored in the destination The AND operation causes a 1 bit to be stored whenever the corresponding bits in the two operands are both logic ones otherwise a 0 bit value is stored The contents of the Source are unaffected Unaffected Set if the result is 0 cleared otherwise Always cleared to 0 Unaffected Unaffected opc dst src opc src opc dst src Set if the result bit 7 is set cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst src 52 r r 6 53 r Ir 6 54 R R 55 R IR 6 56 R IM Given R1 12H R2 register 01H 21H register 02H register OAH AND AND AND AND AND R1 R2 R1 R2 01H 02H 01H 02H 01H 25H m m m R1 02H R2 03H R1 02H R2 Register 01H Register 01H Register 01H 01H register 02H 00H register 02H 21H 03H 03H In the first example the destination working register R1 contains the value 12H and the source working register R2 contains 03H The statement AND R1 R2 logically ANDs the source operand 03H wit
167. entifier 8 5 4 3 2 j 41 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W 7 6 Not used for the S3F8415 F8419 must keep always 0 5 UART parity enable disable PEN 0 Disable 1 Enable 4 UART receive parity error RPE 0 No error Parity error 3 2 Not used for the S3F8415 F8419 must keep always 0 1 UART receive interrupt pending flag 0 Not pending 0 Clear pending bit when write 1 Interrupt pending 0 UART transmit interrupt pending flag 0 Not pending 0 Clear pending bit when write 1 Interrupt pending NOTES 1 In order to clear a data transmit or receive interrupt pending flag you must write a 0 to the appropriate pending bit 2 To avoid programming errors we recommend using load instruction except for LDB when manipulating UARTPND values 3 Parity enable and parity error check can be available in 9 bit UART mode Mode 2 only 4 Parity error bit RPE will be refreshed whenever 8th receive data bit has been shifted ELECTRONICS 4 37 CONTROL REGISTERS S3C84H5 F84H5 WTCON Watch Timer Control Register F8H Set1 Bank1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Watch Timer Clock Selection Bit 0 Main system clock divided by 256 fxx 256 Sub system clock fxt 6 Watch Timer Interrupt Enable Bit EN Disable watch timer interrupt Enable watch timer in
168. er R1 the value 2AH the statement OR RO R1 logical ORs the RO and R1 register contents and stores the result 3FH in the destination register RO Other examples show the use of the logical OR instruction with various addressing modes and formats ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET Pop from Stack POP dst Operation dst lt SP SP lt SP 1 The contents of the location addressed by the stack pointer are loaded into the destination The stack pointer is then incremented by one Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 50 R 51 IR Examples Given Register 01H register 01H 1BH SPH OD8H SPL OD9H OFBH and stack register OFBH 55H POP 00H gt Register OOH 55H SP OOFCH POP 00 gt Register OOH 01H register 01H 55H SP OOFCH In the first example the general register OOH contains the value 01H The statement POP OOH loads the contents of the location OOFBH 55H into the destination register and then increments the stack pointer by one The register OOH then contains the value 55H and the SP points to the location OOFCH ELECTRONICS 6 63 INSTRUCTION SET S3C84H5 F84H5 POPUD Pop User Stack Decrementing POPUD Operation Flags Format Example dst src dst lt src IR lt IR 1 This instruction is used for user defined stacks in the register file The contents
169. eration generates a negative number MSB 1 4 Overflow Flag V Operation result is lt 127 or gt 128 Operation resultis gt 127 or lt 128 3 Decimal Adjust Flag D EN Add operation completed Subtraction operation completed 2 Half Carry Flag H 0 No carry out of bit or no underflow into bit by addition or subtraction 1 Addition generated carry out of bit or subtraction generated underflow into bit 3 1 Fast Interrupt Status Flag FIS EN Interrupt return IRET in progress when read Fast interrupt service routine in progress when read 0 Bank Address Selection Flag BA 0 BankOis selected Bank 1 is selected 4 8 ELECTRONICS S3C84H5 F84H5 CONTROL REGISTER IMR Interrupt Mask Register DDH Set 1 RESET Value X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Interrupt Level 7 IRQ7 Enable Bit Disable mask 1 Enable un mask 6 Interrupt Level 6 IRQ6 Enable Bit Disable mask 1 Enable un mask 5 Interrupt Level 5 IRQ5 Enable Bit 0 Disable mask 1 Enable un mask 4 Interrupt Level 4 IRQ4 Enable Bit 0 Disable mask 1 Enable un mask 3 Interrupt Level 3 IRQ3 Enable Bit 0 Disable mask 1 Enable un mask 2 Interrupt Level 2 IRQ2 Enable Bit Disable mask 1 Enable un mask 1 Interrupt Level 1 IRQ1 Enable Bit 0 Disable mask 1
170. errupt priority register IPR determines the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interrupt level the interrupt with the lowest vector address is usually processed first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the program counter value and status flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed ELECTRONICS 5 3 INTERRUPT STRUCTURE S3C84H5 F84H5 Levels Vectors BEH IRQO COH IRQI C2H C6H IRQ2 C8H CAH CEH DOH _ j D2H D4H D6H IRQ4 D8H IRQ5 DAH IRQ6 DCH IRQ7 DEH NOTES 1 Within a given interrupt level the lower vector address has high priority For example DCH has Sources Timer B underflow Timer A match capture Timer A overflow Timer 1 0 match capture Timer 1 0 overflow Timer 1 1 match capture Timer 1 1 overflow P1 0 external interrupt P1 1 external interrupt P1 2 external interrupt P1 3 external interrupt Watch timer SIO receive transmit PWM overflow interrupt UART data receive UART data transmit Reset Clear
171. erwise Set if the result bit 7 is set cleared otherwise Always reset to 0 Unaffected Unaffected opc dst src opc src dst opc dst src Bytes Cycles Opcode Addr Mode Hex dst src 2 4 72 r r 6 73 r Ir 3 6 74 R R 75 R IR 3 6 76 R IM Given RO OC7H R1 02H R2 18H register OOH 2BH register 01H 02H and register 02H 23H TM TM TM TM TM RO R1 RO R1 00H 01H 00H 01H 00H 54H 14414 RO 0C7H R1 02H Z 0 RO 0C7H R1 02H register 02H 23H 2 0 Register OOH 2BH register 01H 02H Z Register OOH 2BH register 01H 02H register 02H 23H Z 0 Register OOH 2BH Z 1 In the first example if the working register RO contains the value OC7H 11000111B and the register R1 the value 02H 00000010B the statement TM RO R1 tests bit one in the destination register for a value Because the mask value does not match the test bit the 2 flag is cleared to logic zero and can be tested to determine the result of the TM operation ELECTRONICS 6 85 INSTRUCTION SET S3C84H5 F84H5 WEI wate for Interrupt WFI Operation The CPU is effectively halted before an interrupt occurs except that DMA transfers can still take place during this wait state The WFI status can be released by an internal interrupt including fast interrupt Flags No flags are affected Format Byt
172. es Cycles Opcode Hex opc 1 4n 3F 1 2 3 Example The following sample program structure shows the sequence of operations that follow a WFI statement Main program El Enable global interrupt WFI Wait for interrupt Next instruction Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed 6 86 ELECTRONICS S3C84H5 F84H5 Logical Exclusive OR XOR Operation Flags Format Examples dst src dst dst XOR src INSTRUCTION SET The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results in a 1 bit being stored whenever the corresponding bits in the operands are different Otherwise a 0 bit is stored C Unaffected Bytes Cycles Opcode Addr Mode Z Setifthe result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always reset to 0 D Unaffected H Unaffected Hex dst src dst src 2 4 B2 r r 6 B3 r Ir src dst 3 6 B4 R R 6 B5 R IR opc dst src 3 6 B6 R IM Given RO OC7H R1 02H R2 18H register OOH 2BH register 01H 02H register 02H 23H XOR XOR XOR XOR XOR RO R1 RO R1 00H 01H 00H 01H 00H 54H gt gt gt gt gt RO R1 02H RO 0 4 R1 02H register 0
173. essussuscessosunsosausnusensesuuseusesses 6 77 SCF Set Carry Flag sassssssssssssnsssssscusscusussusensausnscususssssnsausescussssusssscunsssusesususseseuscususcussscuusescunes 6 78 SRA Shift Right Arithmetic sasassssssssssnasunsasusscusussesusscussssussnssensssusensaususcussesssssesensesusssusessesunseune 6 79 SRP SRPO SRP 1 Set Register Pointer sssssssssssasunsaususcusesssssnscunsssussnsausoscussssussesaussesusnsesssssuseusessuscussssusenscusus 6 80 STOP Stop Operation sasusssnansassnscususcssscssassssensesusssseussssusnseusssceusensaussosunsssuusencussasuusesuessusenseoussoune 6 81 SUB Subtract sasssssussssssssssnssssussusussesssssusussusenscssuscussssuseseussssussssaunsscussessussscenseusescusesssussuscussenon 6 82 SWAP Swap Nibbles sassssunssssussusunscusessusensassnscussossssessunsssusssusussssssscusussusensassuscusesssusescunsosuusoseunes 6 83 Test Complement under Mask sasasssussssssnssunsesusssssussasunscussssussnsaunsesusssesaussassuscusssenusescunes 6 84 TM Test under Mask sassssunssssussssussaususcusescussnscussosunsosusssusensesuuscusessusensausuosunsosuususeusescunseusesees 6 85 WFI Wate for Interrupt sassssanssusussusunsassuscussssusenssensscusossasssuscsunseussscusunsusenscusessussoseusescussosussoscunes 6 86 XOR Logical Exclusive OR sasassssusssssnssunssssssnscussasusscussssusunscussseussuseusuocussossussusensesusseusensaususeune 6 87 xxii S3C84H5 F84H5 MICROCONTROLLER S3C84H5 F84H5 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8 SERIES
174. exed analog data input pins ADCO ADC7 10 bit A D conversion data output register ADDATAH ADDATAL FUNCTION DESCRIPTION To initiate an analog to digital conversion procedure at first you must configure P2 2 P2 3 P1 4 P1 5 to analog input before A D conversions because the 0 0 0 3 P2 2 P2 3 1 4 1 5 pins can be used alternatively as normal data or analog input pins To do this you load the appropriate value to the POCONL P2CONL and P1CONH for ADCO ADCY register And you write the channel selection data in the A D converter control register ADCON to select one of the eight analog input pins ADCn n 0 7 and set the conversion start or enable bit 0 A 10 bit conversion operation can be performed for only one analog input channel at a time The read write ADCON register is located in set 1 bank 0 at address F7H During a normal conversion ADC logic initially sets the successive approximation register to 200H the approximate half way point of an 10 bit register This register is then updated automatically during each conversion step The successive approximation block performs 10 bit conversions for one input channel at a time You can dynamically select different channels by manipulating the channel selection bit value ADCON 6 4 in the ADCON register To start the A D conversion you should set the enable bit ADCON 0 When a conversion is completed ADCON 3 the end of conversion
175. fected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 80 RR 8 81 IR Given RO 12H R1 34H R2 register OFH and register 31H 21H DECW RRO gt RO 12H R1 33H DECW R2 Register register 31H 20H In the first example the destination register RO contains the value 12H and the register R1 the value The statement DECW RRO addresses RO and the following operand 1 as a 16 bit word and decrements the value of R1 by one leaving the value 33H A system malfunction may occur if you use a Zero flag FLAGS 6 result together with a DECW instruction To avoid this problem it is recommended to use DECW as shown in the following example LOOP DECW RRO LD R2 R1 OR R2 RO JR NZ LOOP ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET DI Disable Interrupts DI Operation SYM 0 0 Bit zero of the system mode control register 5 0 is cleared to 0 globally disabling all interrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 8F Example Given SYM 01H DI If the value of the SYM register is 01H the statement DI leaves the new value 00H in the register and clears SYM 0 to 0 disabling interrupt processing ELECTRONICS 6 37 INSTRUCTION SET S3C84H5 F84H5
176. flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst sre src dst RA 3 12 C2 r Ir Example Given R1 02H R2 and register 02H CPIJE R1 R2 SKIP gt R2 04H PC jumps to SKIP location In this example the working register R1 contains the value 02H the working register R2 the value and the register 03 contains 02H The statement CPIJE R1 R2 SKIP compares the QR2 value 02H 00000010B to 02H 00000010B Because the result of the comparison is equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source register R2 is incremented by one leaving a value of 04H Remember that the memory location addressed by the CPIJE instruction must be within the allowed range of 127 to 128 ELECTRONICS 6 31 INSTRUCTION SET S3C84H5 F84H5 CPIJNE Compare Increment and Jump on Non Equal CPIJNE Operation Flags Format Example dst src RA If dst src 0 PC lt PC RA Ir Ir 1 The source operand is compared to subtracted from the destination operand If the result is not 0 the relative address is added to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction following the CPIJNE instruction is executed In either case the source pointer is incremented by one before the next instruction No flags are affected Bytes Cyc
177. flow IRQ1 TINTPND EOH bank 1 Timer A match capture TACON E1H bank 1 TADATA E2H bank 1 TACNT bank 1 IRQ2 T1DATAHO T1DATALO E5H bank 1 T1DATAH1 T1DATAL1 E6H E7H bank 1 Timer 1 1 match capture T1CONO 1 E8H E9H bank 1 Timer 1 1 overflow T1CNTHO T1CNTLO EAH EBH bank 1 T1CNTH1 T1CNTL1 ECH EDH bank 1 TINTPND EOH bank 1 P1 0 external interrupt IRQ3 P1CONL E9H bank 0 P1 1 external interrupt P1INT EBH bank 0 P1 2 external interrupt P1INTPND EAH bank 0 P1 3 external interrupt F3H bank 0 IRQ4 WTCON F8H bank 1 SIO receive transmit IRQ5 SIOCON SIODATA F1H F2H bank 1 PWM overflow IRQ6 PWMCON F5H bank 1 PWMDATAH PWMDATAL F3H F4H bank 1 UART receive transmit IRQ7 UARTCON F6H bank 0 UDATA UARTPND F5H F4H bank 0 BRDATAH BRDATAL EEH EFH bank 1 ELECTRONICS 5 9 INTERRUPT STRUCTURE S3C84H5 F84H5 SYSTEM MODE REGISTER SYM The system mode register SYM set 1 DEH is used to globally enable and disable interrupt processing see Figure 5 5 A reset clears SYM 0 to 0 The instructions El and DI enable and disable global interrupt processing respectively by modifying the bit 0 value of the SYM register In order to enable interrupt processing an Enable Interrupt El instruction must be included in the initialization routine which follows a reset operation Although you can manipulate 5 0 directly to enable and disable interrupts during the normal operation it is recommended to use the
178. for debugging LD OF7H 5FH Extra command only for debugging SBO Extra command only for debugging 4 14 ELECTRONICS S3C84H5 F84H5 CONTROL REGISTER P1CONH Port 1 Control Register High Byte E8H Bit Identifier 71 8 5 4 3 2 3 90 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W Addressing Mode Register addressing mode only 7 4 Not used for the S3C84H5 F84H5 must keep always 0 3 2 P1 5 T1CAP1 AD6 Configration Bits 1 EN 0 Input mode 1 1 input EN 1 Input mode with pull up T1CAP1 input 0 Push pull output mode Alternative function mode AD6 1 0 P1 4 T1CK1 AD5 Configration Bits EN 0 Input mode T1CK1 input EN 1 Input mode with pull up T1CK1 input 0 Push pull output mode 1 Alternative function mode AD5 NOTE In debug mode you have to include three extra commands in initial routine to operate Ports correctly If you omit these commands Port do not operate correctly Reter to page 9 14 After you have finished your program and before assembling you have to remove these three commands ORG 100H SB1 Extra command only for debugging LD OF7H 5FH Extra command only for debugging SBO Extra command only for debugging ELECTRONICS 4 15 CONTROL REGISTERS S3C84H5 F84H5 P1CONL Port 1 Control Register Low Byte E9H Set1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Reg
179. fy 4096 To disable the watchdog function write the signature code 1010B to the basic timer register control bits 7 4 The 8 bit basic timer counter BTCNT set 1 bank 0 FDH can be cleared at any time during normal operation by writing a 1 to BTCON 1 To clear the frequency dividers write a 1 to BTCON O ELECTRONICS 10 1 BASIC S3C84H5 F84H5 Basic Timer Control Register BTCON D3H Set 1 R W Watchdog timer enable bit Divider clear bit 1010B Disable watchdog function 0 No effect Other value Enable watchdog function 1 Clear divider Basic timer counter clear bit 0 No effect 1 Clear BTCNT Basic timer input clock selection bit 00 fxx 4096 01 fxx 1024 10 fxx 128 11 fxx 1 Not used Figure 10 1 Basic Timer Control Register BTCON 10 2 ELECTRONICS S3C84H5 F84H5 BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal BTOVF to generate a reset by setting 7 4 to any value other than 1010B The 1010 value disables the watchdog function A reset clears BTCON to 00H automatically enabling the watchdog timer function A reset also selects the CPU clock as determined by the current CLKCON register setting divided by 4096 as the BT clock The CPU is reset whenever a basic timer counter overflow occurs During normal operation the application program must pre
180. g Bit EN No interrupt pending ES Clear pending bit when write Interrupt pending 2 Timer 1 0 Match Capture Interrupt Pending Bit EN No interrupt pending ES Clear pending bit when write Interrupt pending 1 Timer A Overflow Interrupt Pending Bit EN No interrupt pending ES Clear pending bit when write Interrupt pending 0 Timer A Match Capture Interrupt Pending Bit 0 No interrupt pending 0 Clear pending bit when write Interrupt pending 4 34 ELECTRONICS S3C84H5 F84H5 CONTROL REGISTER UARTCON UART Control Register F6H Set1 Bit Identifier RESET Value Read Write 7 6 ELECTRONICS 5 24 2 a o 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Operating mode and baud rate selection bits 0 0 Mode 0 Shift Register fxx 16 16bit BRDATA 1 0 1 Mode 1 8 bit UART fxx 16 16bit BRDATA 1 Mode 2 9 bit UART fxx 16 16bit BRDATA 1 Multiprocessor communication enable bit for mode 2 only 0 Disable 1 Enable Serial data receive enable bit ofe If Parity disable mode PEN 0 location of the 9th data bit to be transmitted in UART mode 2 0 or 1 If Parity enable mode PEN 1 even odd parity selection bit for transmit data in UART mode 2 0 Even parity bit generation for transmit data 1 Odd parity bit generation for transmit data If Parity disable PEN 0 location of the 9
181. g Mode Register addressing mode only 7 5 Timer 1 1 Input Clock Selection Bits 0 0 fxx 1024 0 1 fxx 256 0 fxx 64 Ges Enema cook SSS Edemal clock ising edge SSS 4 3 Timer 1 1 Operating Mode Selection Bits lolo Interval mode 011 Capture mode Capture on rising edge can occur 1110 Capture mode Capture falling edge OVF can occur PWM mode 2 Timer 1 1 Counter Enable Bit Clear the timer 1 1 counter Auto clear bit 1 Timer 1 1 Match Capture Interrupt Enable Bit EN Disable interrupt Enable interrupt 0 Timer 1 1 Overflow Interrupt Enable 0 Disable overflow interrupt 1 Enable overflow interrupt ELECTRONICS 4 31 CONTROL REGISTERS S3F8415 F8419 TACON Timer A Control Register E1H Set1 Bank1 RESET VALUE 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Timer A Input Clock Selection Bits fxx 1024 fxx 256 Pr fo aes 3 Timer A Counter Clear Bit EN No effect Clear the timer A counter Auto clear bit 2 Timer A Overflow Interrupt Enable Bit EN Disable overflow interrupt Enable overflow interrupt 4 Timer Match Capture Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt 0 Timer A Start Stop Bit Stop Timer A Start Timer A 4 32 ELECTRONICS S3F8415 F8419 CONTROL REGISTER TBCON Timer B Control Register
182. g normal stack operations the value in the SPL register will overflow or underflow to the SPH register overwriting any other data that is currently stored there To avoid overwriting data in the SPH register you can initialize the SPL value to FFH instead of OOH 2 20 ELECTRONICS S3C84H5 F84H5 ADDRESS SPACES 55 PROGRAMMING TIP Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions LD PUSH PUSH PUSH PUSH POP POP POP POP ELECTRONICS SPL ZOFFH PP RPO RP1 R3 R3 RP1 RPO SPL lt FFH Normally the SPL is set to OFFH by the initialization routine Stack address OFEH PP Stack address OFDH lt RPO Stack address OFCH lt Stack address OFBH R3 Stack address OFBH Stack address OFCH RPO lt Stack address OFDH PP lt Stack address OFEH S3C84H5 F84H5 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter Instructions indicate the operation to be performed and the data to be operated on Addressing mode is the method used to determine the location of the data operand The operands specified in SAM8RCinstructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 series instruction set sup
183. gisters are for general purpose use You can always address set 1 register location regardless of which of the 2 register pages is currently selected The set 1 locations however can only be addressed using direct addressing modes The extension of register space into separately addressable areas sets banks and pages is supported by various addressing mode restrictions the select bank instructions SBO and 5 1 and the register page pointer PP Specific register types and the area in bytes that they occupy in the register file are summarized in Table 2 1 Table 2 1 S3C84H5 F84H5 Register Type Summary Register Type Number of Bytes General purpose registers including 16 byte common 272 working register area expanded 2 separately addressable register pages 1Page occupies 172 byte prime register area and the 64 byte set 2 area CPU and system control registers Mapped clock peripheral control and data registers Total Addressable Bytes 2 4 ELECTRONICS S3C84H5 F84H5 Seti Bank 1 ADDRESS SPACES Bank 0 System and Peripheral Control Registers Register Addressing Mode System and Peripheral Control Registers Register Addressing Mode General Purpose Register Register Addressing Mode Page 0 Set 2 General Purpose Data Registers Indirect Register Indexed Mode and Stack Operations Prime Data Registers All
184. gram or Data Memory 3 6 ELECTRONICS S3C84H5 F84H5 ADDRESSING MODES INDEXED ADDRESSING MODE X Indexed X addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address see Figure 3 7 You can use Indexed addressing mode to access locations in the internal register file or in external memory Please note however that you cannot access locations in set 1 using indexed addressing mode In short offset Indexed addressing mode the 8 bit displacement is treated as a signed integer in the range 128 to 4127 This applies to external memory accesses only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to that base address see Figure 3 9 The only instruction that supports indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructions support indexed addressing mode for internal program memory and for external data memory when implemented Register File RPO or RP1 Value used in points to Instruction OPERAND start of working register block Program Memory mu Base Address wee dst src
185. h capture or overflow interrupt pending condition when 1 0 T1INT1 or TTOVFO T1OVF1 is disabled the application program should poll the pending bit TINTPND register bank 1 address EOH When a 1 is detected a timer 1 0 1 match capture or overflow interrupt is pending When the sub routine has been serviced the pending condition must be cleared by software by writing a 0 to the interrupt pending bit If interrupts match capture or overflow are enabled the pending bit is cleared automatically by hardware ELECTRONICS 12 3 16 1 0 1 S3C84H5 F84H5 Timer 1 Control Register T1CONO E8H Set 1 Bank 1 R W T1CON1 E9H Set 1 Bank 1 R W Timer 1 clock source selection bit fxx 1024 Mm 0 Disable overflow interrupt 010 fxx 64 1 Enable overflow interrrupt 011 fxx 8 100 fxx Timer 1 match capture interrupt enable bit 101 External clock falling edge 0 Disable interrupt 110 External clock rising edge 1 Enable interrrupt 111 Counter stop Timer 1 overflow interrupt enable bit Timer 1 counter clear bit 0 No effect 1 Clear counter Auto clear bit Timer 1 operating mode selection bit 00 Interval mode 01 Capture mode capture on rising edge OVF can occur 10 Capture mode capture on falling edge OVF can occur 11 PWM mode NOTE Interrupt pending bits are located in TINTPND register Figure 12 1 Timer 1 0 1 Control Register T1CONO
186. h the destination operand value 12H leaving the value 02H in the register R1 ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET BAND Bit AND BAND dst src b BAND dst b src Operation dst 0 lt dst 0 AND src b Or dst b dst b AND src 0 The specified bit of the source or the destination is logically ANDed with the zero bit LSB of the destination or the source The resultant bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Flags C Unaffected Z Setifthe result is 0 cleared otherwise S Cleared to O V Undefined D Unaffected H Unaffected Format Bytes Cycles Addr Mode Hex dst src opc dst b 0 src 3 6 67 ro Rb src 1 dst 3 6 67 Rb ro NOTE Inthe second byte of the 3 byte instruction formats the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bitin length Examples Given R1 07H and register 01H 05H BAND R1 01H 1 gt R1 06H register 01H 05H BAND 01H 1 R1 gt Register 01H 05H R1 07H In the first example the source register 01H contains the value 05H 00000101B and the destination working register R1 contains 07H 00000111B The statement BAND R1 01H 1 ANDS the bit 1 value of the source register with the bit 0 value of the register R1 destination leaving the value 06H 0000
187. he instruction pointer The program memory word that is pointed to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex 1 14 1 diagram below shows example of how to use ENTER statement Before After Address Data Address Data IP 0050 IP 0043 Address Address PC 0040 Enter PC 0110 40 Enter Address H 41 Address H Address L 42 Address L 0022 Address H 0020 43 Address 110 20 00 21 IPL 50 22 Data 22 Data Stack Stack ELECTRONICS 6 41 INSTRUCTION SET S3C84H5 F84H5 EXIT exit EXIT Operation IP lt SP SP lt SP 2 lt This instruction is useful when implementing threaded code languages stack value is popped and loaded into the instruction pointer The program memory word that is pointed to by the instruction pointer is then loaded into the program counter and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 16 2F Example The diagram below shows an example of how to use an EXIT statement Before After Address Data Address Data IP 0050 0043 Address Data Address Data 0110 50 PCL old 60 Main 51 0022 140 20 21 IPL 50 M M 22 Data amory 22 Data S
188. he port 2 control registers must also be enabled in the associated peripheral module Port 2 Pull up control Registers P2PUR Using the port 2 pull up control register 2 FA SET1 BANKO you can configure pull up resistors to individual port 0 pins 9 8 ELECTRONICS S3C84H5 F84H5 PORTS Port 2 Control Register High Byte 2 Set1 R W Reset value 00 7 6 P2 7 TxD Configuration Bits 0 0 Input mode 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode TxD output 5 4 P2 6 RxD Configuration Bits 0 0 Input mode 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode RxD output 3 2 P2 5 SCK Configuration Bits 0 0 Input mode 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode SCK output 1 0 P2 4 SO Configuration Bits 0 0 Input mode 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function mode SO output Figure 9 6 Port 2 High Byte Control Register P2CONH ELECTRONICS 9 9 5 S3C84H5 F84H5 Port 2 Control Register Low Byte P2CONL EDH Set1 R W Reset value 00 7 6 P2 3 AD7 SI Configuration Bits 0 0 Input mode SI 0 1 Alternative function mode Not used 1 0 Push pull output mode 1 1 Alternative function
189. he address 27H QR1 ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET DEC Decrement DEC dst Operation dst dst 1 The contents of the destination operand are decremented by one Flags C Unaffected Z Setifthe result is 0 cleared otherwise S Setif result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst 451 2 4 00 R 4 01 IR Examples Given R1 and register 10H DEC R1 gt R1 02H DEC QR1 gt Register 03H OFH In the first example if the working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements the value 10H contained in the destination register 03H by one leaving the value OFH ELECTRONICS 6 35 INSTRUCTION SET S3C84H5 F84H5 DECW Decrement Word DECW Operation Flags Format Examples NOTE dst dst dst 1 The contents of the destination location which must be an even address and the operand following that location are treated as a single 16 bit value that is decremented by one C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaf
190. he currently selected working register area Figure 3 2 Working Register Addressing 3 2 ELECTRONICS S3C84H5 F84H5 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE IR In Indirect Register IR addressing mode the content of the specified register or register pair is the address of the operand Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Please note however that you cannot access locations COH FFH in set 1 using the Indirect Register addressing mode Program Memory Register File 8 bit Register File Address dst ADDRESS Point to One DECADE Register in Register One Operand File Instruction Example Address of Operand used by Instruction Value used in OPERAND Instruction Execution Sample Instruction RL SHIFT Where SHIFT is the label of an 8 bit register address Figure 3 3 Indirect Register Addressing to Register File ELECTRONICS 3 3 ADDRESSING MODES S3C84H5 F84H5 INDIRECT REGISTER ADDRESSING MODE Continued Register File REGISTER Example Instruction References OPCODE Points to uen ou Reed T Memory Address Points to Program Memory Program Memory Sample
191. hen the CPU acknowledges the interrupt request application software must the clear the pending condition by writing a 0 to the corresponding P1INTPND1 bit 9 4 ELECTRONICS S3C84H5 F84H5 PORTS Port 1 Control Register High Byte E8H Set1 Bank0 R W Reset value 00 7 4 Not used must keep always 0 3 2 P1 5 T1CAP1 AD6 Configuration Bits 0 0 Input mode T1CAP1 input 0 1 Input mode with pull up T1CAP1 input 1 0 Push pull output mode 1 1 Alternative function mode AD6 1 0 P1 4 T1CK1 AD5 Configuration Bits 00 Input mode T1CK1 input 0 1 Input mode with pull up T1CK1 input 1 0 Push pull output mode 1 1 Alternative function mode AD5 Figure 9 2 Port 1 High Byte Control Register P CONH ELECTRONICS 9 5 9 6 5 S3C84H5 F84H5 Port 1 Control Register Low Byte P1 CONL E9H Set1 Bank0 R W Reset value 00H 4 7 6 P1 3 T1OUTO INT3 Configuration Bits 0 0 Input mode Interrupt input INT3 0 1 Input mode with pull up Interrupt input INT3 1 0 Push pull output mode 1 1 Alternative function mode T1OUTO output 5 4 P1 2 TACAP INT2 Configuration Bits 0 0 Input mode Interrupt input INT2 TACAP 0 1 Input mode with pull up Interrupt input 2 1 0 Push pull output mode 1 1 Alternative function mode Not used 3 2 P1 1 TACK BUZ INT1 Configuration Bits 0 0 Input
192. hen you use an interrupt to release idle mode the CLKCON 4 and CLKCON 3 register values remain unchanged and the currently selected clock value is used The interrupt is then serviced When the return from interrupt IRET occurs the instruction immediately following the one that initiated idle mode is executed 8 6 ELECTRONICS S3C84H5 F84H5 PORTS l O PORTS OVERVIEW The S3C84H5 F84H5 microcontroller has five bit programmable I O ports PO P3 This gives a total of 22 I O pins Each port can be flexibly configured to meet application design requirements The CPU accesses ports by directly writing or reading port registers No special instructions are required Table 9 1 gives you a general overview of the S3C84H5 F84H5b I O port functions Table 9 1 S3C84H5 F84H5 Port Configuration Overview Port Configuration Options Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up resistor Alternately P0 0 P0 3 can be used as ADO ADS Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up resistor Alternatively 1 0 1 5 can be used as INTO INT3 TAOUT T1OUTO T1CK1 T1CAP1 AD5 AD6 Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up Alternately P2 0 P2 7 can be used ADC4 ADC7 SI T1CAP0 T10UT1
193. her IPR bit settings are as follows 5 controls the relative priorities of group C interrupts Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5 6 and 7 IPR 6 defines the subgroup C relationship IPR 5 controls the interrupt group C 0 controls the relative priority setting of IRQO and IRQ1 interrupts 5 12 ELECTRONICS S3C84H5 F84H5 INTERRUPT STRUCTURE Interrupt Priority Register IPR FFH Set 1 Bank 0 R W LSB 0 Group priority ua Group A D7 D4 D1 0 IRQO gt IRQ1 Undefined 1 IRQ1 gt IRQO B gt C gt A gt gt 0 IRQ2 gt IRQ3 IRQ4 B gt A gt C 1 IRQ3 IRQ4 gt IRQ2 C gt A gt B Subgroup B C gt B gt A 0 IRQ3 gt IRQ4 gt gt 1 IRQ4 gt Undefined 0 0 0 0 1 1 1 1 Group 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 Subgroup C 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6 Figure 5 8 Interrupt Priority Register IPR ELECTRONICS 5 13 INTERRUPT STRUCTURE S3C84H5 F84H5 INTERRUPT REQUEST REGISTER IRQ You can poll bit values in the interrupt request register IRQ set 1 DCH to monitor interrupt request status for all levels in the microcontroller s interrupt structure Each bit corresponds to the interrupt level of the same number bit O to IRQO bit 1 to IRQ1 and so on A 0 indicates that no interrupt request is currently being issued for that level
194. ich are related to two different mnemonics but which test the same flag For example Z and EQ are both true if the zero flag Z is set but after an ADD instruction Z would probably be used Following a CP instruction you would probably want to use the instruction EQ 2 For operations using unsigned numbers the special condition codes UGE ULT UGT and ULE must be used 6 12 ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This Chapter contains detailed information and programming examples for each instruction in the S3C8 series instruction set Information is arranged in a consistent format for improved readability and for quick reference The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Flag settings that may be affected by the instruction Detailed description of the instruction s format execution time and addressing mode s Programming example s explaining how to use the instruction ELECTRONICS 6 13 INSTRUCTION SET S3C84H5 F84H5 ADC Add with Carry ADC dst src Operation dst lt dst srct c The source operand along with the carry flag setting is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s comp
195. ides the 16 bit RRO value by the 8 bit value of the R2 source register After the DIV instruction RO contains the value 03H and R1 contains 40H The 8 bit remainder is stored in the upper half of the destination register RRO RO and the quotient in the lower half R1 ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET DJNZ Decrement and Jump if Non Zero DJNZ r dst Operation rer 1 If r 0 PC PC dst The working register being used as a counter is decremented If the contents of the register are not logic zero after decrementing the relative address is added to the program counter and control passes to the statement whose address is now in the PC The range of the relative address is 127 to 128 and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement NOTE In case of using DJNZ instruction the working register being used as a counter should be set at the one of location to OCFH with SRP SRPO or SRP1 instruction Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst r opc dst 2 8 jump taken rA RA 8 no jump r OtoF Example Given R1 02H and LOOP is the label of a relative address SRP 0COH DJNZ R1 LOOP DJNZ is typically used to control a of instructions In many cases a label is used as the destination operand instead of a numeric relative address value In the example the working register R1 c
196. in Descriptions 32SOP 32SDIP 28SOP s S3C84H5 F84H5 Pin Descriptions 30 SDIP S3C84H5 F84H5 Register Type Summary eee eee eee eee eee eee eee eee eee eee eee eee eee Set 1 Registers sassssuussssussussonscunsscusensuusessussssusssussussesssosusessusenscensesusnensuusescunsossusescussessuscuse Set 1 0 Registers sasssssusssusssssussssensssssssusessassuscussssssscsausessussesssesussssasenscusescusessusenos Set 1 Bank 1 Registers sasssssnssssssosaussassuscssussusessssusssensssusossaussseussesusscuszessssensaessscunsosaususe Interrupt Vectors Interrupt Control Register Overview sessssunssusassusenscussssusssscussecunscusisseassnscussscussescussscunseuee Interrupt Source Control and Data Registers sasassusassssssscussssusesusessussuscususcusesssuscsaussensus Instruction Group Summary Flag Notation Conventions Instruction Set Symbols sasasssnsssussssasssssunsssssesusenssssuscusessusenscussscussesussesaussusensesusscusessensnse Instruction Notation Conventions sassssssssssessssenssssussusensaususeusosssssnscunsesusesusunsesunseusescunsus
197. includes an analog comparator and Vref circuit The value of a detection voltage is 2 8V The on chip Low Voltage Reset features static reset when supply voltage is below a reference voltage value Typical 2 8 V Thanks to this feature external reset circuit can be removed while keeping the application safety As long as the supply voltage is below the reference value there is an internal and static RESET The MCU can start only when the supply voltage rises over the reference voltage When you calculate power consumption please remember that a static current of LVR circuit should be added a CPU operating current in any operating modes such as Stop Idle and normal RUN mode ELECTRONICS 18 1 LOW VOLTAGE RESET S3C84H5 F84H5 Watchdog nRESET nRESET E Internal System UD IE nRESET When the Voo level is lower than 2 8V NOTES 1 The target of voltage detection level is 2 8 V at 5 2 BGR is Band Gap voltage Reference Figure 18 1 Low Voltage Reset Circuit NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON 18 2 ELECTRONICS S3C84H5 F84H5 MTP MTP OVERVIEW The S3F84H5
198. ing edges SIO counter clear and shift start bit 0 No action 1 Clear 3 bit counter and start shifting Figure 14 1 Serial I O Interface Control Register SIOCON 14 2 ELECTRONICS S3C84H5 F84H5 SERIAL I O INTERFACE SIO PRESCALER REGISTER SIOPS The control register for serial I O interface module SIOPS is located in Set 1 Bank 1 at The value stored in the SIO prescaler registers SIOPS lets you determine the SIO clock rate baud rate as follows Baud rate Input clock Xin 4 SIOP 1 or external SCK input clock SIO Pre Scaler Registers SIOPS FOH Set1 Bank1 R W Baud rate Xin 4 SIOPS 1 Figure 14 2 SIO Pre scaler Register SIOPS 3 Bit Counter SIOCON O Clear Pending SIOCON 1 SIOCON 7 SIOCON 3 Interrupt Enable Shift Clock Source Select SIOCON 4 SIOCON 2 Edge Select Shift Enable SIOCON 5 1 Mode Select SIOPS F4H CLK g Bit SIO Shift Buffer SIODATA Prescaler SIOCON 6 Prescaler Value LSB MSB 1 SIOPS 1 First Mode Select gt 000 lt Figure 14 3 SIO Functional Block Diagram ELECTRONICS 14 3 SERIAL I O INTERFACE S3C84H5 F84H5 SCK C 1 1 1 SO Bor aos Y Y Transmit IRQS N Complete Set SIOCON 3 Figure 14 4 Serial 1 Timing in Transmit Receive Mode Tx at falling SIOCON 4 0 Transmit IRQS
199. ing register pair The contents of the source location are loaded into the destination location The memory address is then decremented The contents of the source are unaffected LDCD refers to program memory and LDED refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst sre dst src 2 10 E2 r Irr Examples Given R6 10H R7 33H R8 12H program memory location 1033H OCDH and external data memory location 1033H ODDH LDCD R8 RR6 contents of program memory location 1033H is loaded into R8 and RR6 is decremented by one R8 R6 10H R7 32H RR6 lt RR6 1 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is decremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 32H LDED R8 RR6 NOTE LDED instruction can be used to read write the data of 64 Kbyte data memory 6 54 ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET LDCI LDEI Load Memory and Increment LDCI dst src LDEI dst src Operation dst lt src rm rm 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destinatio
200. input by setting the value of the Timer A capture input selection bit in the port 0 control register POCONH set 1 bank 0 E6H When 1 0 is 00 or 017 the TACAP input or normal input is selected When POCONH 1 0 is set to 1X normal push pull output is selected Both kinds of timer A interrupts can be used in capture mode the timer A overflow interrupt is generated whenever a counter overflow occurs the timer A match capture interrupt is generated whenever the counter value is loaded into the Timer A data register By reading the captured data value in TADATA and assuming a specific value for the timer A clock frequency you can calculate the pulse width duration of the signal that is being input at the TACAP pin 11 2 ELECTRONICS S3C84H5 F84H5 8 BIT TIMER A B TIMER A CONTROL REGISTER TACON You use the timer A control register TACON to Select the timer A operating mode interval timer capture mode and PWM mode Select the timer A input clock frequency Clear the timer A counter TACNT Enable the timer A overflow interrupt or timer A match capture interrupt Clear timer A match capture interrupt pending conditions TACON is located in set 1 Bank 1 at address E1H and is read write addressable using Register addressing mode A reset clears TACON to This sets timer A to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer A interrupts Yo
201. ion is concluded with a stop bit You can program this function so that when the stop bit is received the serial interrupt will be generated only if RB8 2 To enable this feature you set the MCE bit in the UARTCON registers When the MCE bit is 1 serial data frames that are received with the 9th bit 0 do not generate an interrupt In this case the 9th bit simply separates the address from the serial data Sample Protocol for Master Slave Interaction When the master device wants to transmit a block of data to one of several slaves on a serial line it first sends out an address byte to identify the target slave Note that in this case an address byte differs from a data byte an address byte the 9th bit is 1 and in a data byte it is 0 The address byte interrupts all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave then clears its MCE bit and prepares to receive incoming data bytes The MCE bits of slaves that were not addressed remain set and they continue operating normally while ignoring the incoming data bytes While the MCE bit setting has no effect in mode 0 it can be used in mode 1 to check the validity of the stop bit For mode 1 reception if MCE is 1 the receive interrupt will be issue unless a valid stop bit is received ELECTRONICS 14 13 UART S3C84H5 F84H5 Setup Procedure for Multiprocessor Communications Follow these steps to configur
202. ion time 20 us AVper 5 nA when power down mode 1 Conversion time is the time required from the moment a conversion operation starts until it ends 2 lapc 5 operating current during A D conversion 3 fosc is the main oscillator clock NOTES ELECTRONICS 20 11 ELECTRICAL DATA S3C84H5 F84H5 Table 20 12 LVR Low Voltage Reset Circuit Characteristics TA 25 C Parameter Test Condition LVR Voltage Level LVR is enabled by smart option TA 25 C Main Oscillator Frequency CPU Clock 10 MHz 25V 55V Supply Voltage V Minimum instruction clock 1 4 Oscillator clock Figure 20 8 Operating Voltage Range 20 12 ELECTRONICS S3C84H5 F84H5 ELECTRICAL DATA VDD 104 Vss 53084 5 84 5 Figure 20 9 The Circuit Diagram to Improve EFT Characteristics NOTE improve EFT characteristics we recommend using power capacitor near S3C84H5 F84H5 like Figure 20 9 ELECTRONICS 20 13 S3C84H5 F84H5 MECHANICAL DATA 2 1 MECHANICAL DATA OVERVIEW The SSF84H5 is available in a 30 pin SDIP package Samsung 30 SDIP 400 and a 32 SOP package 32 5 450 and 32 pin SDIP package Samsung 32 SDIP 400 and a 28 pin SOP package 28 SOP 375 Package dimensions are shown in Figures21 1 and 21 2 0 1 0 20 0 05 lt gt 0 05 NOTE Dimensions in millimeters
203. is called set 2 For S3C84H5 F84H5 the set 2 address range COH FFH is accessible on pages 0 1 The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions You can use only Register addressing mode to access set 1 locations In order to access registers in set 2 you must use Register Indirect addressing mode or Indexed addressing mode The set 2 register area is commonly used for stack operations 2 8 ELECTRONICS S3C84H5 F84H5 ADDRESS SPACES PRIME REGISTER SPACE The lower 192 bytes 0 of the S3C84H5 F84H5 s a 256 byte register pages is called prime register area Prime registers can be accessed using any of the seven addressing modes see Chapter 3 Addressing Modes The prime register area on page 0 is immediately addressable following a reset In order to address prime registers on pages you must set the register page pointer PP to the appropriate source and destination values CPU and system control General purpose Peripheral and Figure 2 5 Set 1 Set 2 Prime Area Register ELECTRONICS 2 9 ADDRESS SPACES S3C84H5 F84H5 WORKING REGISTERS Instructions can access specific 8 bit registers or 16 bit register pairs using either 4 bit or 8 bit address fields When 4 bit working register addressing is used the 256 byte register file can be seen by the programmer as one that consists of 32 8 byte register groups or slices Each slice comprises of eight 8 bit r
204. ister 05H R6 12H R7 34H Register 02H OFH register OEDH OFH In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H 03H into the destination word 00H and 01H This leaves the value 03H the general register OOH and the value OFH in the register 01H Other examples show how to use the LDW instruction with various addressing modes and formats ELECTRONICS S3C84H5 F84H5 MULT Unsigned MULT Operation Flags Format Examples dst src dst dst x src INSTRUCTION SET The 8 bit destination operand the even numbered register of the register pair is multiplied by the Source operand 8 bits and the product 16 bits is stored in the register pair specified by the destination address Both operands are treated as unsigned integers Set if MSB of the result is a 1 cleared otherwise Bytes Cycles Opcode Addr Mode C Set if the result is gt 255 cleared otherwise Z Setifthe result is 0 cleared otherwise S V Cleared D Unaffected H Unaffected opc src dst Hex dst src 3 22 84 RR R 22 85 RR IR 22 86 RR IM Given Register 20H register 01H register 02H 09H register 06H MULT 00H 02H MULT MULT OOH 30H 00H 1 gt Register OOH 01H register 01 20H register 02H 09H Register register 01H
205. ister addressing mode only 7 6 P1 3 T1OUTO INT3 Configration Bits Input mode Interrupt input INT3 Input mode with pull up Interrupt input INT3 1 0 Push pull output mode Alternative function mode T1TOUTO mode 5 4 3 2 0 0 Input mode Interrupt input INT1 TACK Input mode with pull up Interrupt input INT1 TACK 0 Push pull output mode EN Alternative function mode BUZ out mode 1 0 P1 0 TAOUT INTO Configration Bits 0 0 Input mode Interrupt input INTO 0 1 Input mode with pull up Interrupt input INTO Push pull output mode Alternative function mode TAOUT mode NOTE debug mode you have to include three extra commands in initial routine to operate Ports correctly If you omit these commands Port do not operate correctly Reter to page 9 14 After you have finished your program and before assembling you have to remove these three commands ORG 100H SB1 Extra command only for debugging LD OF7H 5FH Extra command only for debugging SBO Extra command only for debugging 4 16 ELECTRONICS S3C84H5 F84H5 CONTROL REGISTER P1INTPND Port 1 Interrupt Pending Register EAH Set1 Bit Identifier eee RESET Value 0 0 0 0 Read Write R W R W R W R W Addressing Mode 7 4 ELECTRONICS Register addressing mode only Not used for S3C84H5 F84H5 P1 3 INT3 Interrupt Pending Bit 0 I
206. it Identifier 27 e 5 4 3 2 a a o RESET Value 1 1 0 0 0 Read Write R W R W R W R W R W Addressing Mode Register addressing only 7 3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RPO points to address COH in register set 1 selecting the 8 byte working register slice COH C7H 2 0 Not used for the S3C84H5 F84H5 RP1 Register Pointer 1 D7H Set 1 RESET Value 1 1 0 0 1 Read Write R W R W R W R W R W Addressing Mode Register addressing only 7 3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset points to address in register set 1 selecting the 8 byte working register slice C8H CFH 2 0 Not used for the S3C84H5 F84H5 ELECTRONICS 4 25 CONTROL REGISTERS S3C84H5 F84H5 SIOCON Serial I O Module Control Registers F2H Set1 Bank1 Bit Identifier 4 6 5 4 3 2 4 0 RESET
207. l I O interface SIOCON is located in Set1 Bank 1 at F2H It has the control settings for SIO module Clock source selection internal or external for shift clock Interrupt enable Edge selection for shift operation Clear 3 bit counter and start shift operation Shift operation transmit enable Mode selection transmit receive or receive only Data direction selection MSB first or LSB first A reset clears the SIOCON value to OOH This configures the corresponding module with an internal clock source at the SCK selects receive only operating mode and clears the 3 bit counter The data shift operation and the interrupt are disabled The selected data direction is MSB first SIO CONTROL REGISTERS SIOCON F2H Set 1 Bank 1 R W Reset 15151515121 SIO shift clock select bit SIO Interrupt pending bit 0 Internal clock P S clock 0 No interrupt pending 1 External clock SCK 0 Clear pending condition when write 1 2 Interruptis pending Data direction control bit 0 MSB first mode SlOinterrupt enable bit 1 LSB first mode 0 Disable SIO interrupt 1 E le SIO i SIO mode selction bit nable SIO interrupt 0 Rececive only mode 1 Transmit receive mode SIO shift operation enable bit 0 Disable shifter and clock counter Shift clock edge selction bit 1 Enable shfter and clock counter 0 Tx falling edges Rx at rising edges 1 Tx rising edges Rx at fall
208. l up resistor enable 1 0 P2 0 Pull up Resistor Enable Disable Pull up resistor disable 1 Pull up resistor enable ELECTRONICS 4 2 CONTROL REGISTERS S3C84H5 F84H5 P3CONL Port 3 Contro Register Low Byte EFH 1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 3 Configration Bits Input mode Input mode with pull up Push pull output mode N channel open drain output 5 4 43 43 0 0 Input mode 0 1 Input mode with pull up 1 Push pull output mode EHE N channel open drain output 1 0 0 Configration Bits O 0 Input mode 0 1 Input mode with pull up Push pull output mode N channel open drain output NOTE debug mode you have to include three extra commands in initial routine to operate Ports correctly If you omit these commands Port do not operate correctly Reter to page 9 14 After you have finished your program and before assembling you have to remove these three commands ORG 100H SB1 Extra command only for debugging LD OF7H 5FH Extra command only for debugging SBO Extra command only for debugging 4 22 ELECTRONICS S3C84H5 F84H5 CONTROL REGISTER PP Register Page Pointer DFH Set1 Bit Identifier 7 8 5 4 3 2 a 90 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing M
209. lement addition is performed In multiple precision arithmetic this instruction lets the carry value from the addition of low order operands be carried into the addition of high order operands Flags C Set if there is a carry from the most significant bit of the result cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise g Always cleared to 0 H Setif there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 12 r r 6 13 r Ir opc src dst 3 6 14 R R 15 R IR opc dst src 3 6 16 R IM Examples Given R1 10H R2 C flag 1 register 01H 20H register 02H register O3H ADC R1 R2 gt R1 14H R2 03H ADC R1 R2 gt R1 1BH R2 03H ADC 01H 02H gt Register 01H 24H register 02H 03H ADC 01H Q02H gt Register 01H 2BH register 02H 03H ADC 01H 11H gt Register 01H 32H In the first example the destination register R1 contains the value 10H the carry flag is set to 1 and the source working register R2 contains the value The statement ADC R1 R2 adds 03H and the carry flag value 1 to the destin
210. les Opcode Addr Mode Hex dst src opc src dst RA 3 12 D2 r Ir Given R1 02H R2 and register 04H CPIJNE R1 R2 SKIP gt R2 04H PC jumps to SKIP location The working register R1 contains the value 02H the working register R2 the source pointer the value 03H and the general register 03 the value 04H The statement CPIJNE R1 R2 SKIP subtracts 04H 00000100B from 02H 00000010B Because the result of the comparison is non equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source pointer register R2 is also incremented by one leaving a value of 04H Remember that the memory location addressed by the CPIJNE instruction must be within the allowed range of 127 to 128 ELECTRONICS S3C84H5 F84H5 DA Decimal Adjust INSTRUCTION SET DA dst Operation dst lt DA dst The destination operand is adjusted to form two 4 bit BCD digits following an addition or subtraction operation For addition ADD ADC or subtraction SUB SBC the following table indicates the operation performed The operation is undefined if the destination operand is not the result of a valid addition or subtraction of BCD digits Instruction Carry Bits 4 7 H Flag Bits 0 3 Number Added Carry Before DA Value Hex Before DA Value Hex to Byte After DA 0 0 9 0 0 9 00 0 0 0 8 0 A F 06 0 0 0 9 1 0 3 06 0 ADD 0 A F 0
211. ltiplexer External clock input pin T1CKO T1CK1 A 16 bit counter T1CNTHO LO T1CNTH1 L1 a 16 bit comparator and two 16 bit reference data register T1DATAHO LO T1 DATAH1 L1 I O pins for capture input 1 T1CAP1 or match output T1OUTO T1TOUT1 Timer 1 0 overflow interrupt IRQ2 vector C6H and match capture interrupt IRQ2 vector C4H generation Timer 1 1 overflow interrupt IRQ2 vector CAH and match capture interrupt IRQ2 vector C8H generation 0 control register TT CONO set 1 E8H Bank 1 read write 1 control register T1 CON1 set 1 E9H Bank 1 read write Timer 1 1 ELECTRONICS 12 1 16 1 0 1 S3C84H5 F84H5 FUNCTION DESCRIPTION Timer 1 0 1 Interrupts IRQ2 Vectors CAH C6H C8H and CAH The timer 1 0 module can generate two interrupts the timer 1 0 overflow interrupt T1OVFO and the Timer 1 0 match capture interrupt T1INTO T1OVFO is interrupt level IRQ2 vector C6H T1INTO also belongs to interrupt level IRQ2 but is assigned the separate vector address C4H A timer 1 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced A timer 1 0 match capture interrupt T1INTO pending condition is also cleared by hardware when it has been serviced The timer 1 1 module can generate two interrupts the timer 1 1 overflow interrupt T1OVF1 and the timer 1 1 match capture interrupt T1
212. ment SBC 1 2 subtracts the source value 03H and the C flag value 1 from the destination 10H and then stores the result OCH in the register R1 ELECTRONICS 6 77 INSTRUCTION SET S3C84H5 F84H5 SCF set Carry Flag SCF Operation C lt 1 The carry flag C is set to logic one regardless of its previous value Flags C Setto 1 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 DF Example The statement SCF sets the carry flag to 1 6 78 ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET SRA Shift Right Arithmetic SRA dst Operation dst 7 lt dst 7 C lt dst 0 dst n dst n 1 n 0 6 An arithmetic shift right of one bit position is performed on the destination operand Bit zero the LSB replaces the carry flag The value of bit 7 the sign bit is unchanged and is shifted into the bit position 6 Flags C Set if the bit shifted from the LSB position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 DO R 4 D1 IR Examples Given Register 9AH register 02H register OBCH and 1 SRA 00H gt Register 00 OCD C 0 SRA 02H gt Register 02H register 0 In the fir
213. mode Interrupt input INT1 TACK 0 1 Input mode with pull up Interrupt input INT1 TACK 1 0 Push pull output mode 1 1 Alternative function mode BUZ output 1 0 P1 0 TAOUT INTO Configuration Bits 0 0 Input mode Interrupt input INTO 0 1 Input mode with pull up Interrupt input 1 0 Push pull output mode 1 1 Alternative function mode TAOUT output Figure 9 3 Port 1 Low Byte Control Register P1CONL ELECTRONICS S3C84H5 F84H5 PORTS Port 1 Interrupt Pending Register P1INTPND EAH Seti 0 R W Reset value 00H 7 4 Not used for S3C84H5 F84H5 3 P1 3 INT3 Interrupt Pending bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 2 P1 2 INT2 Interrupt Pending bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 1 P1 1 INT1 Interrupt Pending bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 0 P1 0 INTO Interrupt Pending bit 0 Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending Figure 9 4 Port 1 Interrupt Pending Register P1INTPND ELECTRONICS 9 7 5 S3C84H5 F84H5 Port 1 Interrupt Enable Register Set R W Reset value 00H 7 6 P1 3 s Interrupt Enable Disable Selection Bit OX Disable Interrupt 10
214. n location The memory address is then incremented automatically The contents of the source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes Irr an even number for program memory an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 10 E3 r Irr Examples Given R6 10H R7 33H R8 12H program memory locations 1033H 1034H external data memory locations 1033H ODDH and 1034H OD5H LDCI R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is incremented by RR6 lt RR6 1 R8 R6 10H R7 34H LDEI R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is incremented by RR6 lt RR6 1 R8 ODDH R6 10H R7 34H NOTE LDEI instruction can be used to read write the data of 64 Kbyte data memory ELECTRONICS 6 55 INSTRUCTION SET S3C84H5 F84H5 LDCPD LDEPD Load Memory with Pre Decrement LDCPD dst src LDEPD dst src Operation rm m 1 dst lt src These instructions are used for block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair and is first decremented The contents of the source location are then loaded into the destination lo
215. ned 2 Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 FO R 4 F1 IR Given Register register 02H 03H and register 03H OA4H SWAP 00H gt Register OE3H SWAP 02H gt Register 02H register In the first example if the general register 00H contains the value 3EH 00111110B the statement SWAP 00H swaps the lower and the upper four bits nibbles in the register leaving the value OE3H 11100011B ELECTRONICS 6 83 INSTRUCTION SET S3C84H5 F84H5 TCM rest Complement under Mask TCM dst src Operation NOT dst AND src This instruction tests selected bits in the destination operand for a logic one value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask The TCM statement complements the destination operand which is then ANDed with the source mask The zero Z flag can then be checked to determine the result The destination and the source operands are unaffected Flags C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to O D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 62 r r 6 63 r Ir
216. nerate a programmable carrier pulse for a remote control signal at P1 0 BLOCK DIAGRAM TBCON 6 7 TBCON 2 PG iuo tad 0 f xx 4 gt f xx 8 gt 8 Bit 64 gt Down Counter TB Underflow TBCON 3 TBPWM P1 4 fxx 256 gt TBUF TBCON 1 Repeat Control TBCON 4 5 Timer B Data Timer B Data Low Byte Register High Byte Register Data Bus Data Bus NOTE Incase of setting TBCON 5 4 at 10 the value of the TBDATAL register is loaded into the 8 bit counter when the operation of the timer B starts And then if a underflow occurs in the counter the value of the TBDATAH register is loaded into the value of the 8 bit counter However if the next borrow occurs the value of the TBDATAL register is loaded into the value of the 8 bit counter To output TBPWM as carrier wave you have to set P4CONL 7 6 as 11 Figure 11 3 Timer B Functional Block Diagram ELECTRONICS 11 5 8 CONTROL REGISTER Timer Control Register DOH Set 1 Bank 0 R W Timer B input clock selection bit 00 fxx 4 01 fxx 8 10 fxx 64 11 fxx 256 Timer B interrupt time selection bit 00 Elapsed time for low data value 01 Elapsed time for high data value 10 Elapsed time for low and high data value 11 Invaild setting Timer B output flip flop control bit 0 T FF is low 1 T FF is high Timer B mode selection bit
217. nstruction Arithmetic Instructions ADC dst src Add with carry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ELECTRONICS 6 3 INSTRUCTION SET S3C84H5 F84H5 Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Program Control Instructions BTJRF dst src Bit test and jump relative on false BTJRT dst src Bit test and jump relative on true CALL dst Call procedure CPIJE dst src Compare increment and jump on equal CPIJNE dst src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit reset BITS dst Bit set BOR dst src Bit OR BXOR dst src Bit XOR TCM dst src Test complement under mask TM dst src Test under mask 6 4 ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET Table 6 1 Instruction Group Summary Concluded Mn
218. nterrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending P1 2 INT2 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending P1 1 INT1 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending P1 0 INTO Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 4 1 N CONTROL REGISTERS S3C84H5 F84H5 P1INT Port 1 Interrupt Enable EBH Set1 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 3 s Interrupt Enable Disble Selection Bit 5 4 1 Interrupt Enable Falling edge 1 1 Interrupt Enable Rising edge 3 3 1 Interrupt Enable Falling edge 1 1 Interrupt Enable Rising edge 1 0 1 0 Interrupt Enable Falling edge 4 18 ELECTRONICS S3C84H5 F84H5 CONTROL REGISTER P2CONH Port 2 Control Register High Byte ECH Bit Identifier 711 8 5 4 3 2 4 9 RESET Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 7 TxD Configration Bits 0 Input mode 1 Alternative function mode Not used 1110 Push pull output mode Alternative function mode TxD output 5 4
219. nts continued Chapter 4 Control Registers Overview 4 1 5 Interrupt Structure Overview 5 1 Interrupt eg unio S E S ud age diu RE cef ett 5 2 53C84H5 E84H5 Interrupt SITUCEUEe eere 5 3 Interrupt Vector Addresses rr ctun uter e Pepe 5 5 Enable Disable Interrupt Instructions El 5 7 System Level Interrupt Control Registers sssssssssssssseseeeeeenne nennen 5 7 Interrupt Processing Control Points candente ee ee ee ftiit 5 8 Peripheral Interrupt Control Registers sese enne 5 9 System Mode Register SYM eee iere dete reti Or ib ide Pea d ib 5 10 Interrupt Mask Register IMR 4111 2 1151 00000
220. o Ltd San 24 Nongseo Ri Giheung Eup Yongin City Gyeonggi Do Korea Box 37 Suwon 440 900 TEL 82 31 209 5238 FAX 82 31 209 6494 Home Page http Wwww samsung com Printed in the Republic of Korea Preface S3C84H5 F84H5 Microcontroller User s Manual is designed for application designers and programmers who are using the S3C84H5 F84H5 microcontroller for application development It is organized two main parts Part Programming Model Part Il Hardware Descriptions Part contains software related information to familiarize you with the microcontroller s architecture programming model instruction set and interrupt structure It has six chapters Chapter 1 Product Overview Chapter 4 Control Registers Chapter 2 Address Spaces Chapter 5 Interrupt Structure Chapter 3 Addressing Modes Chapter 6 Instruction Set Chapter 1 Product Overview is a high level introduction to S3C84H5 F84H5 with general product descriptions as well as detailed information about individual pin characteristics and pin circuit types Chapter 2 Address Spaces describes program and data memory spaces the internal register file and register addressing Chapter 2 also describes working register addressing as well as system stack and user defined stack operations Chapter 3 Addressing Modes contains detailed descriptions of the addressing modes that are supported by the S3C8 series CPU Chapter 4 Control Registers
221. ode 0 data TxD pin for transmit output P2 7 clock output mode 0 External clock input pins for timer ER 5 P1 1 TACAP Capture input pins for timer A D 5 P1 2 TAOUT Pulse width modulation output pins for timer 1 0 Carrier frequency output pins for timer D 5 2 0 T1CKO External clock input pins for timer 1 0 5 2 0 Capture input pins for timer 1 0 P2 1 T1OUTO Timer 1 0 16 bit PWM mode FA or D 5 P2 2 counter A toggle output pins T1CK1 External clock input pins for timer 1 1 E P1 4 T1CAP1 a Capture input pins for timer 1 1 a P1 5 Timer 1 1 16 bit PWM mode eu or P1 3 counter Mis toggle output pins nRESET System reset pin 7 ee VopVss Powerinutpns input pins 2222 1220 1 10 ELECTRONICS PRODUCT OVERVIEW S3C84H5 F84H5 PIN CIRCUITS VDD Pull Up Resistor In o i Schmitt Trigger Figure 1 5 Pin Circuit Type B nRESET VDD T P Channel Data Out Output N Channel Disable Figure 1 6 Pin Circuit Type C ELECTRONICS PRODUCT OVERVIEW S3C84H5 F84H5 VDD Pull up Enable Data Pin Circuit Output Type C Disable Figure 1 7 Pin Circuit Type D Port Data Pull up Pin enable Circuit Type C Alternative output Output Disable Noise Normal Input Figure 1 8 Pin Circuit Type D 5 1 0
222. ode Register addressing mode only 7 4 Destination Register Page Selection Bits 01010 0 Destination page 0 Other values Don t care 3 0 Source Register Page Selection Bits ro 2201 NOTE In the S3C84H5 F84H5 microcontroller the internal register file is configured as one page Pages 0 The pages 0 are used for the general purpose register file and data register ELECTRONICS 4 23 CONTROL REGISTERS S3C84H5 F84H5 PWMCON PwM Control Register F5H Set1 1 Bit Identifier 71 8 s 4 3 2 3 RESET Value 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W 7 6 PWM Input Clock Selection Bits 5 Not used for S3C84H5 F84H5 4 MDATA Reload Interval Selection Bit Reload from 10 bit up counter overflow 1 Reload from 8 bit up counter overflow 3 P M Counter Clear Bit No effect 1 Clear the PWM counter when write 2 M Counter Enable Bit Stop counter 1 Start Resume countering ail PWM Overflow Interrupt Enable Bit 8 Bit Overflow Disable interrupt 1 Enable interrupt 0 PWM Overflow Interrupt Pending Bit 0 No interrupt pending when read 0 Clear pending bit when write Interrupt is pending when read NOTE PWMCON 3 is not auto cleared You must pay attention when clear pending bit refer to page 13 7 4 24 ELECTRONICS S3C84H5 F84H5 CONTROL REGISTER RPO Register Pointer 0 D6H Set1 B
223. of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then decremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc sic dst 3 8 92 R IR Given Register 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H OOH gt Register OOH 41H register 02H 6FH register 42H 6FH 02H If the general register contains the value 42H and the register 42H the value 6FH the statement POPUD 02H 300H loads the contents of the register 42H into the destination register The user stack pointer is then decremented by one leaving the value 41H ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET POPUI Pop User Stack Incrementing POPUI dst src Operation dst lt src IR lt IR 1 The POPUI instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then incremented Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 8 93 R IR Example Given Register 01H and register 01H POPUI 02H Q00H gt Register 02H register 01 register 02H 70H If the general register OOH contains the value 01H and the register 01H the value 70H the statemen
224. omplement operation is greater than 127 or less than 128 It is cleared to 0 after a logic operation has been performed Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and it cannot be addressed as a test condition Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a subtraction borrows out of bit 4 It is used by the Decimal Adjust DA instruction to convert the binary result of a previous addition or subtraction into the correct decimal BCD result The H flag is normally not accessed directly by a program Fast Interrupt Status Flag FLAGS 1 The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing When set it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed Bank Address Flag FLAGS 0 The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected bank 0 or bank 1 The BA flag is cleared to 0 select bank 0 when the SBO instruction is executed and is set to 1 select bank 1 when the SB1 instruction is executed ELECTRONICS 6 7 INSTRUCTION SET INSTRUCTION SET NOTATION Table 6 2 Flag Notation Con
225. on IR lt IR 1 dst src This instruction is used to address user defined stacks in the register file PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst sre opc dst src 3 8 82 IR R Example Given Register 03H register O1H 05H and register 02H PUSHUD 00H 01H gt Register OOH 02H register 01H 05H register 02H 05H If the user stack pointer the register for example contains the value 03H the statement PUSHUD 00H 01H decrements the user stack pointer by one leaving the value 02H The 01H register value 05H is then loaded into the register addressed by the decremented user stack pointer ELECTRONICS 6 67 INSTRUCTION SET S3C84H5 F84H5 PUSHUI Push user Stack Incrementing PUSHUI Operation Flags Format Example dst src IR lt IR 1 dst lt src This instruction is used for user defined stacks in the register file PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst sre opc dst src 3 8 83 IR R Given Register 03H register O1H 05H and register 2AH PUSHUI 000H 01H gt R
226. ontains the value 02H and LOOP is the label for a relative address The statement DJNZ R1 LOOP decrements the register R1 by one leaving the value 01H Because the contents of R1 after the decrement are non zero the jump is taken to the relative address specified by the LOOP label ELECTRONICS 6 39 INSTRUCTION SET S3C84H5 F84H5 El Enable Interrupts Operation Flags Format Example SYM 0 lt 1 The El instruction sets bit zero of the system mode register 0 to 1 This allows interrupts to be serviced as they occur assuming they have the highest priority If an interrupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when the EI instruction is executed No flags are affected Bytes Cycles Opcode Hex 1 4 5 If the SYM register contains the value OOH that is if interrupts are currently disabled the statement EI sets the SYM register to 01H enabling all interrupts is the enable bit for global interrupt processing ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET ENTER Enter ENTER Operation SP lt SP 2 QSP lt IP IP PC PC lt IP 2 This instruction is useful when implementing threaded code languages The contents of the instruction pointer are pushed to the stack The program counter PC value is then written to t
227. ontrol Register OSCCON 7 4 7 6 STOP Control Register STOPCON 7 4 9 1 Port 0 Low Byte Control Register POCON LS 9 3 9 2 Port 1 High Byte Control Register P1CONH CT 9 5 9 3 Port 1 Low Byte Control Register P1CONL nA AA 9 6 9 4 Port 1 Interrupt Pending Register P1 INTPND 9 7 9 5 Port 1 Interrupt Enable Register 1 AA LAB BA 9 8 9 6 Port 2 High Byte Control Register P2CONH TA 9 9 9 7 Port 2 Low Byte Control Register P2CONL 9 10 9 8 Port 2 Pull up Control Register P2PUR 9 11 9 9 Port 3 Low Byte Control Register PSCONL 9 12 10 1 Basic Timer Control Register BTCON 10 2 10 2 Basic Timer Block Diagram T RRR A A 10 4 11 1 Timer A Control Register TACON UO AA 11 3 Timer A Functional Block Diagram P 11 4 11 3 Timer B Functional Block Diagram D 11 5 11 4 Timer B Control Register TBCON ULLA AAA 11 6 11 5 Timer B Data Registers TBDATAH TBDATAL 11 6 11 6 Timer Output Flip Flop Waveforms in Repeat Modem 11 8 xii S3C84H5 F84H5 MICROCONTROLLER List of Figures Concluded Figure Title Page Number Number 12 1 Timer 1 0 1 Control Register T1 CONO T1 1 000A 12 4 12 2 Timer A Timer 1 0 1 Pending Register TINTPND
228. os sesso uo 4 33 TINTPND Timer A Timer 1 Interrupt Pending Register ESVRRREERRERRRRERNREESERREEEINNMINESERAREENMREREEEREEEEENEA 4 34 UARTCON UART Control Register sessssssessesssessoessoessossesssesssessessssssesseessoesseessossessoessoossoe sss se sonis 4 35 UARTPND UART Pending and parity control CERE EL EE CLE 4 37 WTCON Watch Timer Control Register sesussssssssessssssesseessssssesssessessessssesssssseseessosssesssosesosso sso soun 4 38 S3C84H5 F84H5 MICROCONTROLLER xix Instruction Mnemonic ADC ADD AND BAND BCP BITC BITR BITR BITS BOR BTJRF BTJRT List of Instruction Descriptions Full Register Name Page Number Add with Carry 6 14 6 15 Logical 6 16 Bit AND 6 17 Bit Compare 6 18 Bit Complement 6 19 Bit Reset mm HH 6 20 Bit Reset mm Hh 6 20 Bit Set mmm HH MH Hh 6 21 Bit OR EDD 6 22 Bit Test Jump Relative on False 6 23 Bit Test Jump Relative on True 6 24 Bit 6 25 Call 6 26 Complement Carry Flag 6 27 Clear Peer reer eee eee eee eer reer rere errr rere eee errr eer ere errr eer eee errr eee eee eee 6 28 Complement 6 29
229. ough Carry RRC Operation Flags Format Examples 6 74 dst dst 7 lt lt dst 0 dst lt dst n 1 0 6 The contents of the destination operand the carry are rotated right one bit position initial value of bit zero LSB replaces the carry flag and the initial value of the carry flag replaces bit 7 MSB C Set if the bit rotated from the least significant bit position bit zero was 1 Z Setif the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination is changed during the rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 CO R 4 C1 IR Given Register 55H register 01H 02H register 02H 17H and 0 RRC 00H Register OOH 2AH C 1 RRC 01H gt Register 01H 02H register 02H OBH 1 In the first example if the general register OOH contains the value 55H 01010101B the statement RRC OOH rotates this value one bit position to the right The initial value of bit zero 1 replaces the carry flag and the initial value of the C flag 1 replaces bit 7 This leaves the new value 2AH 00101010B in the destination register The sign flag and the overflow flag are both cleared to 0 ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET
230. our product Please check all that apply Price Product quality Features and functions Development system Technical support Delivery time Used same MCU before Quality of documentation Samsung reputation Mask Charge US Won Customer Information Company Name Telephone number Signatures Person placing the order Technical Manager For duplicate copies of this form and for additional ordering information please contact your local Samsung sales representative Samsung sales offices are listed on the back cover of this book 53 8 SERIES REQUEST FOR PRODUCTION AT CUSTOMER RISK Customer Information Company Name Department Telephone Number Fax Date Risk Order Information Device Number 5308 write down the ROM code number Package Number of Pins Package Type Intended Application Product Model Number Customer Risk Order Agreement We hereby request SEC to produce the above named product in the quantity stated below We believe our risk order product to be in full compliance with all SEC production specifications and to this extent agree to assume responsibility for any and all production risks involved Order Quantity and Delivery Schedule Risk Order Quantity PCS Delivery Schedule Delivery Date s Quantity Signatures Person Placing the Risk Order SEC Sales Representative
231. perating mode and Transmit interrupt enable bit baud rate selection bits 0 Disable see table below 1 Enable Multiprocessor communication 1 Received interrupt enable bit enable bit mode 2 only 0 Disable 0 Disable 1 Enable 1 Enable If parity disable mode PEN 0 Serial data receive enable bit location of the 9th data bit that was received in 0 Disable UART mode 2 0 or 1 1 Enable PES If parity enable mode PEN 1 i 0 1 parity eee bit iol receive data in location of the 9th data bit to be transmitted in UART mode 2 0 Even parity check for the received data If parity enable mode PEN 1 1 Odd parity check for the received data Even odd parity selection bit for transmit data in UART mode 2 0 Even parity bit generation for transmit data 1 Odd parity bit generation for transmit data 2 MS1 50 Mode Description Baud Rate 0 0 O Shift register fxx 16 x 16bit BRDATA 1 0 1 1 8 bit UART fxx 16 x 16bit BRDATA 1 1 x 2 O9 bitUART fxx 16 x 16bit BRDATA 1 NOTES 1 In mode 2 if the UARTCON 5 bit is set to 1 then the receive interrupt will not be activated if the received 9th data bit is 0 In mode 1 if UARTCON 5 1 then the receive interrut will not be activated if a valid stop bit was not received 2 The descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and
232. plement of the source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operands C Setif a borrow occurred src dst cleared otherwise Set if the result is 0 cleared otherwise 2 8 Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise Cleared if there is a carry from the most significant bit of the low order four bits of the result Bytes Cycles Opcode Addr Mode D Always set to 1 H set otherwise indicating a borrow dst src opc src dst opc dst src Hex dst src 2 4 32 r r 6 33 r Ir 3 6 34 R R 6 35 R IR 3 6 36 R IM Given R1 10H R2 C 1 register 01H 20H register 02H and register 03H OAH SBC SBC SBC SBC SBC R1 R2 R1 R2 01H 02H 01H 02H 01H 8AH 24 EN gt R1 OCH R2 03H R1 05H R2 03H register O3H OAH Register 01H 1CH register 02H 03H Register 01H 15H register 02H register OAH Register 01H 95H C S and V 1 In the first example if the working register R1 contains the value 10H and the register R2 the value 03H the state
233. ports seven explicit addressing modes Not all of these addressing modes are available for each instruction The seven addressing modes and their symbols are Register R Indirect Register IR Indexed X Direct Address DA Indirect Address 1 Relative Address RA Immediate IM ELECTRONICS 3 1 ADDRESSING MODES S3C84H5 F84H5 REGISTER ADDRESSING MODE R In Register addressing mode R the operand value is the content of a specified register or register pair see Figure 3 1 Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space see Figure 3 2 Program Memory Register File 8 bit Register File Address dst OPERAND Point to One SFOSDE Register in Register One Operand File Instruction Value used Instruction Execution Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Figure 3 1 Register Addressing Register File MSB Point to RPO ot RP1 Selected RP points Program Memory io 4 bit of working Working Register 3 LSBs a OPERAND Point to the Pda Q CODE Working Register Two Operand Z iota Instruction Example Sample Instruction ADD R1 R2 Where 1 and R2 are registers in t
234. priate control and clock settings before entering Stop mode When the Stop mode is released by external interrupt the CLKCON 4 and CLKCON 3 bit pair setting remains unchanged and the currently selected clock value is used The external interrupt is serviced when the Stop mode release occurs Following the IRET from the service routine the instruction immediately following the one that initiated Stop mode is executed ELECTRONICS 8 5 RESET and POWER DOWN S3C84H5 F84H5 How to Enter into Stop Mode There are two steps to enter into Stop mode 1 Handling STOPCON register to appropriate value 10100101B 2 Writing Stop instruction keep the order IDLE MODE Idle mode is invoked by the instruction IDLE opcode 6FH In idle mode CPU operations are halted while some peripherals remain active During idle mode the internal clock signal is gated away from the CPU but all peripherals timers remain active Port pins retain the mode input or output they had at the time idle mode was entered There are two ways to release idle mode 1 Execute a reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slow clock fxx 16 because CLKCON 4 and CLKCON 3 are cleared to OOB If interrupts are masked a reset is the only way to release idle mode 2 Activate any enabled interrupt causing idle mode to be released W
235. processing Enable fast interrupt processing 0 Global Interrupt Enable Bit note Lo Disable global interrupt processing Enable global interrupt processing NOTE Following a reset you enable global interrupt processing by executing an El instruction not by writing a 1 to SYM O ELECTRONICS 4 2 CONTROL REGISTERS S3F8415 F8419 T1CONO Timer 1 0 Control Register E8H 1 Bank1 RESET Value 0 0 0 0 0 0 0 0 Read Write RAN R W R W RAN R W R W R W R W Addressing Mode Register addressing mode only 7 5 Timer 1 0 Input Clock Selection Bits fxx 1024 fxx 256 fxx 64 fxx 8 fxx 1 1 1 41 External clock falling edge External clock rising edge ENEN 4 3 Timer 1 0 Operating Mode Selection Bits ofai Capture mode Capture on rising edge OVF can occur Counter stop 1 0 Capture mode Capture on falling edge can occur PWM mode 2 Timer 1 0 Counter Enable Bit EN No effect Clear the timer 1 0 counter Auto clear bit 1 Timer 1 0 Match Capture Interrupt Enable Bit EN Disable interrupt Enable interrupt 0 Timer 1 0 Overflow Interrupt Enable 0 Disable overflow interrupt 1 Enable overflow interrupt 4 30 ELECTRONICS S3F8415 F8419 CONTROL REGISTER T1CON1 Timer 1 1 Control Register E9H Set1 1 RESET VALUE 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressin
236. puter that employs Win95 98 2000 as its operating system can be used A sophisticated debugging tool is provided both in hardware and software the powerful in circuit emulator SMDS2 or SK 1000 for the S3C7 S3C9 and S3C8 microcontroller families SMDS2 is a newly improved version of SMDS2 and SK 1000 is supported by a third party tool vendor Samsung also offers supporting software that includes debugger an assembler and a program for setting options SHINE Samsung Host Interface for In Circuit Emulator SHINE is a multi window based debugger for SMDS2 SHINE provides pull down and pop up menus mouse support function hot keys and context sensitive hyper linked help It has an advanced multiple windowed user interface that emphasizes ease of use Each window can be easily sized moved scrolled highlighted added or removed SASM The SASM is a re locatable assembler for Samsung s S3C8 series microcontrollers The SASM takes a source file containing assembly language statements and translates them into a corresponding source code an object code and comments The SASM supports macros and conditional assembly It runs on the MS DOS operating system As it produces the re locatable object codes only the user should link object files Object files can be linked with other object files and loaded into memory SASM requires a source file and an auxiliary register file device name reg with device specific information SAMA ASSEMBLER
237. rc 3 6 A6 R IM 1 Given R1 02H and R2 CP R1 R2 gt Set the C and S flags The destination working register R1 contains the value 02H and the source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative the C and the S flag values are 1 2 Given R1 05H and R2 OAH CP R1 R2 JP UGE SKIP INC R1 SKIP LD R3 R1 In this example the destination working register R1 contains the value 05H which is less than the contents of the source working register R2 OAH The statement R1 R2 generates C 1 and the JP instruction does not jump to the SKIP location After the statement LD R3 R1 executes the value 06H remains in the working register R3 ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET CPIJE Compare Increment and Jump on Equal CPIJE dst src RA Operation If dst src 0 PC lt PC Ir Ir 1 The source operand is compared to subtracted from the destination operand If the result is O the relative address is added to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction immediately following the CPIJE instruction is executed In either case the source pointer is incremented by one before the next instruction is executed Flags No
238. reset operation disables all PWM output The current counter value is retained when the counter stops When the counter starts counting resumes at the retained value PWM Clock Rate The timing characteristics of PWM output is based on the fosc clock frequency The PWM counter clock value is determined by the setting of PWMCON 6 7 Table 13 1 PWM Control and Data Registers PWM data registers PWMDATAH 7 0 F3H Set 1 Bank 1 8 PWM basic cycle frame value PWMDATAL 1 0 Set 1 Bank 1 2 bit extension stretch value PWM control registers PWMCON Set 1 Bank 1 PWM counter stop start resume and PWM counter clock settings PWM Function Description The PWM output signal toggles to Low level whenever the 8 bit counter matches the reference data register PWMDATAH If the value in the register is not zero an overflow of the 8 bits of counter causes the PWM output to toggle to High level In this way the reference value written to the reference data register determines the module s base duty cycle The value in the lower 2 bits of PWMDATAL counter is compared with the extension settings in the 2 bit extension data register PWMDATAL 1 0 This lower 2 bits of counter value together with extension logic and the PWM module s extension data register is then used to stretch the duty cycle of the PWM output The stretch value is one extra clock period at specific intervals or cycles se
239. rocontroller Also included in Part II are electrical mechanical OTP and development tools data It has 17 chapters Chapter 7 Clock Circuit Chapter 16 A D Converter Chapter 8 RESET and Power Down Chapter 17 Watch Timer Chapter 9 Ports Chapter 18 LCD Controller Driver Chapter 10 Basic Timer Chapter 19 Low Voltage RESET Chapter 11 8 bit Timer A B Chapter 20 Embedded Flash Memory Chapter 12 16 bit Timer 1 0 1 Interface Chapter 13 10 bit PWM Chapter 21 Electrical Data pulse width modulation Chapter 22 Mechanical Data Chapter 14 Serial I O Interface Chapter 23 Development Tools Chapter 15 UART Two order forms are included at the back of this manual to facilitate customer order for S3C84H5 F84H5 microcontrollers the Mask ROM Order Form and the Mask Option Selection Form You can photocopy these forms fill them out and then forward them to your local Samsung Sales Representative S3C84H5 F84H5 MICROCONTROLLER iii Table of Contents Part Programming Model Chapter 1 Product Overview S3C8 Series Microcontrollers A 88448548 COPECO CECE CEE 8 1 1 S3C84H5 F84H5 Microcontroller 1 1 dM 1 2 Block Diagram EEE AT T MIHI ITI I ITE 1 3 Assignment PPP 1 4 Assignment 2
240. ruction You must set the STPCON register as 101001016 Otherwise the STOP instruction will not execute ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET STOP Stop Operation STOP Operation The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode During Stop mode the contents of on chip CPU registers peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 The statement STOP halts all microcontroller operations ELECTRONICS 6 81 INSTRUCTION SET S3C84H5 F84H5 SUB subtract SUB dst src Operation dst lt dst src The source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand Flags C Setif a borrow occurred cleared otherwise 2 Set if the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite
241. ry flag is changed to logic zero If C O the value of the carry flag is changed to logic one Flags C Complemented No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4 EF Example Given The carry flag 0 CCF If the carry flag the CCF instruction complements it in the FLAGS register OD5H changing its value from logic zero to logic one ELECTRONICS 6 27 INSTRUCTION SET S3C84H5 F84H5 CLR clear CLR dst Operation dst 70 Flags Format Examples The destination location is cleared to O No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 BO R 4 B1 IR Given Register 4FH register 01H 02H and register 02H CLR 00H gt Register OOH OOH CLR 01H gt Register 01H 02H register 02H 00H In Register R addressing mode the statement CLR OOH clears the destination register OOH value to 00 In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register value to 00H ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET dst Operation dst lt NOT dst The contents of the destination location are complemented one s complement All 1s are changed to Os and vice versa Flags C Unaffected Z Setifthe result is 0 cleared otherwise S Setif the result bit 7 is
242. s Opcode Quick Reference Codes S3C84H5 F84H5 Set 1 Register values after RESET nnno S3C84H5 F84H5 Set 1 Bank 0 Register values after RESET m S3C84H5 F84H5 Set 1 Bank 1 Register values after RESET m S3C84H5 F84H5 Port Configuration Overview sasssssnsssssssusussassuscussssussescussssunseusassunsoson Port Data Register Summary sasssssnsssnsssussnssssuscunsesusssusussusunscussssussnsaususcunsesusesusessecunseuses PWM Control and Data Registers PWM output stretch Values for Extension Data Register PWMDATAL 1 0 Commonly Used Baud Rates Generated by 16bit BRDATA mmn Watch Timer Control Register WTCON Set 1 Bank 1 F8H R W Descriptions of Pins Used to Read Write the Flash ROM Comparison of S3F84H5 and S3C84H5 Features S3C84H5 F84H5 MICROCONTROLLER Page umber XV Table Number 20 1 20 2 20 3 20 4 20 5 20 6 20 7 20 8 20 9 20 10 20 11 20 12 22 1 22 2 xvi List of Tables Title Page Number Absolute Maximum Ratings 20 2
243. s TBDATAL 14 tL ow 24 us TBDATAH 1 TBDATAH 1 1 5 TBDATAH 23 ELECTRONICS 11 7 8 S3C84H5 F84H5 Timer B Clock 0H 100H Timer B Clock TBDATAL TBDATAH TBDATAL TBDATAH TBDATAL TBDATAH Figure 11 6 Timer B Output Flip Flop Waveforms in Repeat Mode S3C84H5 F84H5 8 BIT TIMER A B PROGRAMMING TIP To generate 38 kHz 1 3duty signal through P2 0 This example sets Timer B to the repeat mode sets the oscillation frequency as the Timer B clock source and TBDATAH and TBDATAL to make a 38 kHz 1 3 Duty carrier frequency The program parameters are 8 795 17 59 lt gt 37 9 kHz 1 3 Duty Timer is used in repeat mode Oscillation frequency is 16 MHz 0 0625 us fx fxx 4 4MHz 0 25 us TBDATAH 8 795 5 0 25 us 35 18 TBDATAL 17 59 us 0 25 us 70 36 Set P4 3 to TBPWM mode ORG 0100H Reset address START DI SB1 Extra command only for debugging LD OF7H 5FH Extra command only for debugging SBO Extra command only for debugging LD TBDATAL 35 1 Set 17 5 us LD 4 70 1 Set 8 75 us LD TBCON 00100111B Clock Source lt fxx 4 Disable Timer B interrupt Select repeat mode for Timer B Start Timer B operation Set Timer B Output flip flop T FF high LD P1CONLH 0COH Set P1 4 to TBPWM mode This command generates 38 kHz 1 3 duty p
244. s 0 0 Disable Operation 1 Start Operation A D Input Pin Selection bits 6 5 4 A D Input pin Clock Selection bit 000 ADCO 2 1 Conversion Clock 001 ADC1 0 O fxx 16 010 ADC2 0 1 fxx 8 011 10 fxx 4 100 ADC4 1 1 Notused 101 5 poe End of Conversion bit realy only 0 Conversion not complete 1 Conversion complete Figure 16 1 A D Converter Control Register ADCON 16 2 ELECTRONICS S3C84H5 F84H5 A D CONVERTER Conversion Data Register High Byte ADDATAH F8H Set 1 Bank 0 Read only MSB 7 6 5 41 3 2141 0 LSB Conversion Data Register Low Byte ADDATAL Set 1 Bank 0 Read only 5 x x x x x 4 0 LSB Figure 16 2 A D Converter Data Register ADDATAH ADDATAL ADCON 4 6 Select one input pin of the assigned ADCON 3 lu fxx 16 gt Clock M gt Selector ADCON 0 ADC Enable ADCO ADC7 uccessive P0 0 PO 3 Approximation P1 4 P1 5 Logic P2 2 P2 3 ADCON O 10 bit result is loaded into A D Conversion Data Register A D Conversion enable 10 bit D A Conversion Result ADDATAH Converter ADDATAL To Data bus Figure 16 3 A D Converter Circuit Diagram ELECTRONICS 16 3 A D CONVERTER S3C84H5 F84H5 INTERNAL REFERENCE VOLTAGE
245. s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BSI Certificate No FM24653 All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives Samsung Electronics C
246. scillator to it s normal oscillation when stop mode is released by interrupts ELECTRONICS 20 7 ELECTRICAL DATA S3C84H5 F84H5 Table 20 9 Data Retention Supply Voltage in Stop Mode TA 25 C to 85 2 5Vto 5 5 V Parameter Conditions i Unit Data Retention Stop mode V Supply Voltage Data Retention lpppon Stop mode 2 7 V uA Supply Current NOTE Supply current does not include current drawn through internal pull up resistors or external output current loads RESET occurs Oscillation n Stabilzation 31 Stop Mode gt 2 lt Data Retention gt Execution of STOP Instrction NOTE is the same as 4096 x 16 x 1 fosc Figure 20 4 Stop Mode Release Timing initiated by RESET 20 8 ELECTRONICS S3C84H5 F84H5 ELECTRICAL DATA Oscillation Stabilization Time 11 Mode Y Idle Mode lt Data Retention Mode gt VDD Execution of STOP Instruction Normal Operating Mode Interrupt NOTE _ twart is the same as 4096 x 16 x BT clock Figure 20 5 Stop Mode Main Release Timing Initiated by Interrupts Oscillation Stabilization Time 31 Stop Mode Y 2 lt Data Retention Mode gt VDD VDDDR Normal Operating Mode Execution of STOP Instruction Interrupt tWAIT 4
247. set cleared otherwise V Always reset to O D Unaffected H Unaffected Format Bytes Cycles Opcode Hex opc dst 2 4 60 4 61 Examples Given R1 07H and register 07H OF1H COM R1 gt R1 OF8H COM QR1 gt R1 07H register 07H OEH Addr Mode dst R IR In the first example the destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and logic zeros to logic ones leaving the value OF8H 11111000B In the second example Indirect Register IR addressing mode is used to complement the value of the destination register 07H 11110001B leaving the new value OEH 00001110B ELECTRONICS 6 29 INSTRUCTION SET S3C84H5 F84H5 Operation Flags Format Examples dst src dst src The source operand is compared to subtracted from the destination operand and the appropriate flags are set accordingly The contents of both operands are unaffected by the comparison C Setif a borrow occurred src dst cleared otherwise Z Setif the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 A2 r r 6 A3 r Ir opc src dst 3 6 4 R R A5 R IR opc dst s
248. signs and the sign of the result is of the same as the sign of the source operand cleared otherwise nd Always set to 1 T Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Addr Mode Hex dst src dst src 2 4 22 r r 23 r Ir opc src dst 3 6 24 R R 6 25 R IR opc dst src 3 6 26 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H register OAH SUB R1 R2 gt R1 OFH R2 03H SUB R1 R2 gt R1 08H R2 03H SUB 01H 02H gt Register 01H register 02H SUB 01H 02H gt Register 01H 17H register 02H SUB 01H 90H gt Register 01H 91H C S and V 1 SUB 01H 65H gt Register 01H OBCH S 1 V 0 In the first example if he working register R1 contains the value 12H and if the register R2 contains the value the statement SUB R1 R2 subtracts the source value 03H from the destination value 12H and stores the result OFH in the destination register R1 6 82 ELECTRONICS S3C84H5 F84H5 SWAP SWAP Operation swapped Flags Format Examples INSTRUCTION SET Swap Nibbles dst dst 0 3 dst 4 7 The contents of the lower four bits and the upper four bits of the destination operand are 7 43 0 1 Undefi
249. single chip CMOS microcontroller is the MTP Multi Time Programmable version of the S3C84H5 microcontroller It has an on chip Half Flash ROM instead of masked ROM The Half Flash ROM is accessed by serial data format The Half Flash ROM can be rewritten up to 100 times The 5 84 5 is fully compatible with the S3C84H5 in function in D C electrical characteristics and in pin configuration Because of its simple programming requirements the S3F84Hb is ideal for use as an evaluation chip for the S3C84H5 VDD Q P1 3 T10UT1 INT3 SCLK P1 2 TACAP INT2 SDAT P1 1 TACK BUZ INT1 S3C84H5 P1 0 TAOUT INTO P3 3 S3F84H5 ds AVss Top V Top View AV REF Vss 5 XTout nRESET P3 0 P3 1 SO P2 4 SCK P2 5 RxD P2 6 32 5 P1 5 AD6 T1CAP1 32 SDIP P1 4 AD5 T1CK1 P2 3 AD7 SI TxD P2 7 P2 2 AD4 T10UTO ADO PO 0 Q P2 1 T1CAP0 PWM AD1 P0 1 C 2 0 1 AD2 PO 2 AD3 P0 3 Figure 19 1 Pin Assignment 32 pin SOP SDIP ELECTRONICS 19 1 S3C84H5 F84H5 VDD Q P1 3 T1OUT1 INT3 SCLK P1 2 TACAP INT2 SDAT P1 1 TACK BUZ INT1 S3C84H5 P1 0 TAOUT INTO AVss S3F84H5 View P1 5 AD6 T1CAP1 P1 4 ADS T1CK1 P2 3 AD7 SI 30 SDIP P2 2 ADA T10UTO P2 1 TI CAPO PWM P2 0 T1CKO TBPWM O P0 3 AD3 P0 2 AD2 Vss Xour XIN TEST XTour nRESET P3 0 P3 1 SO P2 4 SCK P2 5 RxD P
250. software input or push pull output ADC2 ADC3 Software assignable pull up resistor Alternately be used as ADO AD3 Bit programmable port input or output mode D 5 22 23 INTO INT3 selected by software input or push pull output E 26 29 TAOUT TACK Software assignable pull up resistor Alternatively TACAP T1CK1 can be used as INTO INT3 TAOUT TACK 1 AD5 T1CAP1 T1CK1 0 1 AD5 AD6 T10UT1 AD6 BUZ Bit programmable port input or output mode E 10 13 ADC6 ADC7 selected by software input or push pull output D 5 18 21 SO SCK RxD Software assignable pull up TxD Alternately can be used as ADC4 ADC7 51 T1CAP 1 T1OUTO T1CKO SO SCK RxD TxD T1CKO PWM TBPWM PWM TBPWM Bit programmable port input or output mode G selected by software input or push pull N channel open drain output Software assignable pull up 1 9 PRODUCT OVERVIEW S3C84H5 F84H5 Table 1 2 S3C84H5 F84H5 Pin Descriptions Continued Share Pins INTO INT3 Input pins for external interrupt 1 0 1 3 Alternatively used as general purpose digital input output port 1 ADCO ADC7 Analog input pins for A D converter module 0 Alternatively used as general purpose digital P2 2 P2 3 input output port 0 port1 and port 2 P1 4 P1 5 De DUE AVagpAVss A D converter reference voltage and ground Serial data RxD pin for receive input and P2 6 transmit output m
251. ssssunsesunscussssaususeusescunsessounes Chapter 13 10 Bit PWM Pulse Width Modulation Programming the PWM Module to Sample Specifications Chapter 14 Serial I O Interface Chapter 16 A D Converter Configuring A D Converter ssssssunessassusassuscssssssassssussesusssususssssnsaususcussssssssssensesusseusussassuseusescusessuusuos Chapter 17 Watch Timer Using the Watch Timer sassssanssssassusunssassssensasussssaussucusisussssusesssusussunsessssssaussssunsesusscusesssussssessosunensos S3C84H5 F84H5 MICROCONTROLLER Page Number xvii List of Register Descriptions Register Full Register Name Page Identifier Number ADCON A D Converter Control Register 4 5 Basic Timer Control Register sesssssssssssssssssessesssasssesssusssssosssusssosssossossusssosesesssessoe 4 6 CLKCON System Clock Control Register OR ESOR SSSR SSSR SSSR ORESORESERESERESEEERESEEESS 4 7 FLAGS System Flags Register sessssssessesseessoesssessussussesssesssasssasHsspHssasEsESESESESHRRERE REPE EESE ERE HE HH HH 4 8 IMR Interrupt Mask Register 4 9 Instruction Pointer High Byte 4 10 Instruction Poin
252. st example if the general register 00H contains the value 10011010B the statement SRA 00H shifts the bit values in the register OOH right one bit position Bit zero clears the C flag and bit 7 1 is then shifted into the bit 6 position bit 7 remains unchanged This leaves the value 11001101B in the destination register ELECTRONICS 6 79 INSTRUCTION SET S3C84H5 F84H5 SRP SRPO SRP1 set Register Pointer SRP SRPO SRP1 Operation Flags Format Examples NOTE src src src If src 1 1 and src 0 Othen 3 7 lt src 3 7 If src 1 0 and src 0 1 then RP1 3 7 lt src 3 7 If src 1 Oand src 0 Othen 4 7 lt src 4 7 RPO 3 lt 0 RP1 4 7 src 4 7 RP1 3 lt 1 The source data bits one and zero LSB determine whether to write one or both of the register pointers RPO and RP1 Bits 3 7 of the selected register pointer are written unless both register pointers are selected RPO 3 is then cleared to logic zero and RP1 3 is set to logic one No flags are affected Bytes Cycles Opcode Addr Mode Hex src src 2 4 31 IM The statement SRP 40H sets the register pointer 0 RPO at the location OD6H to 40H and the register pointer 1 RP1 at the location OD7H to 48 The statement SRPO 50H would set RPO to 50H and the statement SRP1 68H would set 1 to 68H Before execute the STOP inst
253. sult together with an INCW instruction To avoid this problem it is recommended to use the INCW instruction as shown in the following example LOOP INCW RRO LD R2 R1 OR R2 RO JR NZ LOOP ELECTRONICS 6 45 INSTRUCTION SET S3C84H5 F84H5 IRET Interrupt Return IRET Operation Flags Format Example NOTE IRET Normal RET Fast FLAGS lt SP PC lt IP SP lt SP 1 FLAGS lt FLAGS lt SP FIS 0 SP lt SP 2 SYM 0 1 This instruction is used at the end of an interrupt service routine It restores the flag register and the program counter It also re enables global interrupts A normal IRET is executed only if the fast interrupt status bit FIS bit one of the FLAGS register OD5H is cleared 0 If a fast interrupt occurred IRET clears the FIS bit that was set at the beginning of the service routine All flags are restored to their original settings that is the settings before the interrupt occurred IRET Bytes Cycles Opcode Normal Hex opc 1 12 BF IRET Bytes Cycles Opcode Fast Hex opc 1 6 BF In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupt are enabled When an interrupt occurs the program counter and the instruction pointer are swapped This causes the PC to jump to the address 100H and the IP to keep the return address The last instruction in the service routine is normally a jump
254. t POPUI 02H 0O0H loads the value 70H into the destination general register 02H The user stack pointer the register is then incremented by one changing its value from 01H to 02H ELECTRONICS 6 65 INSTRUCTION SET S3C84H5 F84H5 PUSH Push to Stack PUSH Operation Flags Format Examples src SP lt SP 1 lt src A PUSH instruction decrements the stack pointer value and loads the contents of the source src into the location addressed by the decremented stack pointer The operation then adds the new value to the top of the stack No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Given Register 40H 4FH register 4 OAAH SPH OOH and SPL PUSH 40H gt Register 40H 4FH stack register OFFH 4FH SPH OFFH SPL OFFH PUSH 40H gt Register 40H 4FH register 4 OAAH stack register OFFH OAAH SPH OFFH SPL OFFH In the first example if the stack pointer contains the value 0000H and the general register 40H the value 4FH the statement PUSH 40H decrements the stack pointer from 0000 to OFFFFH It then loads the contents of the register 40H into the location OFFFFH and adds this new value to the top of the stack ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET PUSHUD Push User stack Decrementing PUSHUD dst src Operati
255. t significant byte is always stored in the next 1 odd numbered register Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8 byte working register space in the internal register file and a specific 8 bit register within that space LSB n Even address Figure 2 9 16 Bit Register Pair ELECTRONICS 2 13 ADDRESS SPACES COH BFH Register Pointers Each register pointer RP can independently point to one of the 24 8 byte slices of the register file other than set 2 After a reset RPO points to locations COH C7H and to locations C8H CFH that is to the common working register area NOTE the S3C84H5 F84H5 microcontroller pages 0 1 are implemented Pages 0 1 contain all of the addressable registers in the internal register file Page 0 Register Addressing Only All Addressing Modes Can be pointed by Register Pointer Figure 2 10 Register File Addressing 2 14 Special Purpose Registers General Purpose Register Bank 1 Bank 0 FFH Control Registers _ System Registers Don S3C84H5 F84H5 Page 0 Indirect Register Indexed Addressing Modes ELECTRONICS S3C84H5 F84H5 ADDRESS SPACES COMMON WORKING REGISTER AREA COH CFH After a reset register pointers RPO and RP1 automatically select two 8 byte register slices in set 1 locations COH CFH as the active 16 byte working register blo
256. tack Stack 6 42 ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET IDLE tdle Operation IDLE Operation See description The IDLE instruction stops the CPU clock while allowing the system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 6F instruction IDLE stops the CPU clock but it does not stop the system clock ELECTRONICS 6 43 INSTRUCTION SET S3C84H5 F84H5 INC Increment INC Operation Flags Format Examples 6 44 dst dst dst 1 The contents of the destination operand are incremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst opc 1 4 rE r r OtoF opc dst 2 4 20 R 21 IR Given RO 1BH register OOH OCH and register 1BH OFH INC RO RO 1CH INCOOH gt Register 00H INC RO RO 1BH register O1H 10H In the first example if the destination working register RO contains the value 1BH the statement INC RO leaves the value 1CH in that same register The second example shows the effect an INC instruction has on the register at the location
257. tement whose address is currently in the program counter Otherwise the instruction following the BTJRF instruction is executed Flags No flags are affected Format Bytes Cycles Opcode Addr Mode note Hex dst src opc src b 0 dst 3 10 37 RA rb NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Example Given R1 07H BTJRF SKIP R1 3 gt PC jumps to SKIP location If the working register R1 contains the value 07H 00000111 the statement BTJRF SKIP R1 3 tests bit 3 Because it is 0 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 23 INSTRUCTION SET S3C84H5 F84H5 BTJ Bit Test Jump Relative on True BTJRT Operation Flags Format Example dst src b If src b is a 1 then PC lt PC dst The specified bit within the source operand is tested If it is a 1 the relative address is added to the program counter and control passes to the statement whose address is now in the PC Otherwise the instruction following the BTJRT instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode note Hex dst src opc src b 1 dst 3 10 37 RA rb NOTE Inthe second byte of the instr
258. ter Low Byte SCRE Pee Pee DE 4 10 IPR Interrupt Priority Register cence ence een een eee He Dene RESO HE SSH ESHER EER ESERESESESESESRESHESESESRESSEESORESSESEEESES 4 11 IRQ Interrupt Request Register sesuessssssusssesseossossesseesssessosssossesseessoesssessessessoessoessosssoose soe nie 4 12 OSCCON Oscillator Control Register serssessssssssssasssussessesssesssesssessessesssesssusssussessosssosssssssosso sso soos 4 13 POCON Port 0 Control Register High Byte 4 14 P1CONH Port 1 Control Register High Byte eee nee nen een DSH ESOH SSSR 4 15 1 CONL Port 1 Control Register Low Byte ESE ESSEESR ESSE ESSN ESO 4 1 6 P1INTPND Port 1 Interrupt Pending Register FERES RB ERE ERE Ma 4 17 P1 INT Port 1 Interrupt Enable sasssssussssssssssnsssusesssunsacusseusessusenscussssusensausnseuusesusseusensesusscusessaneuse 4 18 P2CONH Port 2 Control Register High Byte 4 19 P2CONL Port 2 Control Register Low Byte ESR ESESESR ESSE ESOR ESS 4 20 P2PUR Port 2 Pull up Resistor Control Register 4 21 P3CONL Port 3 Control Register Low Byte wesssssssssusseessosssssssussussosssosssusssussessosssosssussse sese 4 22 PP Register Page Pointer 4 23 P
259. terrupt 5 4 Buzzer Signal Selection Bits KIEN 0 5 kHz buzzer BZOUT signal output 1 kHz buzzer BZOUT signal output 1 0 1 2 kHz buzzer BZOUT signal output 3 2 Watch Timer Speed Selection Bits 4 kHz buzzer BZOUT signal output ae 1 955 Interval 4 Watch Timer Enable Bit 0 Disable watch timer Clear frequency dividing circuits Enable watch timer 0 Watch Timer Interrupt Pending Bit EN Interrupt is not pending Clear pending bit when write Interrupt is pending 4 38 ELECTRONICS S3C84H5 F84H5 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8 series interrupt structure has three basic components levels vectors and sources The SAM8 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors When a specific interrupt level has more than one vector address the vector priorities are established in hardware A vector address can be assigned to one or more sources Levels Interrupt levels are the main unit for interrupt priority assignment and recognition All peripherals and I O blocks can issue interrupt requests In other words peripheral and I O operations are interrupt driven There are eight possible interrupt levels IRQO0 IRQ7 also called level 0 level 7 Each interrupt level directly corresponds to interrupt request number IRQn The total number of interrupt levels used in the interrupt structure varies from device to device The S3C84H5 F8
260. th 11 7 12 16 Bit Timer 1 0 1 Overview 12 1 0666 io ssc ci Eo tot e pete 12 2 Timer 1 0 1 Control Register T1 CONO 12 3 Block DC 12 6 13 10 bit PWM Pulse width Modulation Overview 13 1 Function Description 855584854 458 coud 8 4 8 6 13 1 13 1 PWM Control Register 13 5 Chapter 14 Serial I O Interface Overview
261. the overflow flags ELECTRONICS 6 71 INSTRUCTION SET S3C84H5 F84H5 RLC Rotate Left through Carry RLC Operation Flags Format Examples dst dst 0 C dst 7 dst n 1 lt n 0 6 The contents of the destination operand with the carry flag are rotated left one bit position The initial value of bit 7 replaces the carry flag C and the initial value of the carry flag replaces bit zero 7 0 Be C Setifthe bit rotated from the most significant bit position bit 7 was 1 Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination is changed during the rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 10 R 4 11 IR Given Register register 01H 02H and register 02H 17H 0 RLC 00H gt Register 00 54H C 1 RLC 01H gt Register 01H 02H register 02H 2EH C In the first example if the general register has the value 10101010B the statement RLC OOH rotates OAAH one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of the register 00H leaving the value 55H 01010101B The MSB of the register resets the carry flag to 1 and se
262. to IRET at the address FFH This loads the instruction pointer with 100H again and causes the program counter to jump back to the main program Now the next interrupt can occur and the IP is still correct at 100H OH FFH IRET 100H Interrupt Service Routine JP to FFH FFFFH In the fast interrupt example above if the last instruction is not a jump to IRET you must pay attention to the order of the last tow instruction The IRET cannot be immediately proceeded by an instruction which clears the interrupt status as with a reset of the IPR register ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET JP Jump JP cc dst Conditional JP dst Unconditional Operation If cc is true PC lt dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code cc is true otherwise the instruction following the JP instruction is executed The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair Control then passes to the statement addressed by the PC Flags No flags are affected Format 1 Bytes Cycles Opcode Addr Mode 2 dst cc opc dst 3 8 ccD DA cc O to F opc dst 2 8 30 IRR NOTES 1 3 byte format is used for a conditional jump and the 2 byte format for unconditional jump 2 In the first byte of the 3 byte instruction format conditional jump th
263. truction addresses a location in the selected working register area the address bits are concatenated in the following way to form a complete 8 bit address high order bit of the 4 bit address selects one of the register pointers 0 selects RPO 1 selects RP1 The five high order bits in the register pointer select an 8 byte slice of the register space The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2 11 the result of this operation is that the five high order bits from the register pointer are concatenated with the three low order bits from the instruction address to form the complete address As long as the address stored in the register pointer remains unchanged the three bits from the address will always point to an address in the same 8 byte register slice Figure 2 12 shows a typical example of 4 bit working register addressing The high order bit of the instruction INC R6 is 0 which selects RPO The five high order bits stored in RPO 01110B are concatenated with the three low order bits of the instruction s 4 bit address 110B to produce the register address 76H 01110110B 2 16 ELECTRONICS S3C84H5 F84H5 ADDRESS SPACES U Selects RPO or RP1 Address OPCODE 4 bit address Register pointer provides three provides five low order bits high order bits Together they create an 8 bit register address Figure 2
264. ts the overflow flag ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET RR Rotate Right RR dst Operation C dst 0 dst 7 dst 0 dst n lt dst n 1 n 0 6 The contents of the destination operand are rotated right one bit position The initial value of bit zero LSB is moved to bit 7 MSB and also replaces the carry flag C Flags C Set if the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination is changed during the rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 R 4 E1 IR Examples Given Register register 01H 02H and register 02H 17H RR 00H gt Register OOH 98H C 1 RR 01H gt Register 01H 02H register 02H 8BH C 1 In the first example if the general register OOH contains the value 31H 00110001B the statement RR 00H rotates this value one bit position to the right The initial value of bit zero is moved to bit 7 leaving the new value 98H 10011000 in the destination register The initial bit zero also resets the C flag to 1 and the sign flag and the overflow flag are also set to 1 ELECTRONICS 6 73 INSTRUCTION SET S3C84H5 F84H5 RRC Rotate Right thr
265. u can clear the timer A counter at any time during normal operation by writing a 1 to TACON 3 The timer A overflow interrupt is interrupt level IRQ1 and has the vector address C2H When a timer A overflow interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware To enable the timer A match capture interrupt IRQ1 vector COH you must write TACON 1 to 1 To generate the exact time interval you should write TACON 3 and 0 to 1 which cleared counter and interrupt pending bit When interrupt service routine is served the pending condition must be cleared by software by writing a 0 to the interrupt pending bit TINTPND O or TINTPND 1 Timer A Control Register E1H Set 1 Bank 1 R W Reset 00H Timer A input clock selection bit Timer A start stop bit 00 fxx 1024 0 Stop timer A 01 5 256 1 Start timer A 10 fxx 64 11 External clock TACK Timer A match capture interrupt Timer A operating mode selection bit enable bit 00 Interval mode TAOUT mode 0 Disable interrupt 01 Capture mode capture on rising edge 1 Enable interrrupt counter running OVF can occur 10 Capture mode capture on falling edge Timer A overflow interrupt enable bit counter running OVF can occur 0 Disable overflow interrupt 11 PWM mode OVF interrupt and match 1 Enable overflow interrrupt interrupt can occur Timer A counter clear
266. uction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 O7H BTJRT SKIP R1 1 If the working register R1 contains the value 07H 00000111 the statement BTJRT SKIP R1 1 tests bit one in the source register R1 Because it is a 1 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location addressed by the BTJRT instruction must be within the allowed range of 127 to 128 ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET BXOR Bit xor BXOR dst src b BXOR dst b src Operation dst 0 lt dst 0 XOR src b or dst b lt dst b XOR src 0 The specified bit of the source or the destination is logically exclusive ORed with bit zero LSB of the destination or the source The result bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Flags C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefinsed D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src opc dst b 0 src 3 6 27 ro Rb src 1 dst 3 6 27 Rb ro NOTE In the second byte of the 3 byte instruction format the destination or the source address is four bits the bit address b is three bits and the LSB address value is on
267. ulse signal through P1 4 NOTE In debug mode you have to include three extra commands in initial routine to operate Ports correctly If you omit these commands Port do not operate correctly After you have finished your program and before assembling you have to remove these three commands ELECTRONICS 11 9 8 S3C84H5 F84H5 5 PROGRAMMING To generate a one pulse signal through P2 0 This example sets Timer B to the one shot mode sets the oscillation frequency as the Timer B clock source and TBDATAH and TBDATAL to make a 40us width pulse The program parameters 4 Timer B is used in one shot mode Oscillation frequency is 4 MHz fx 1 4 clock 1 us TBDATAH 40 us 1 us 40 TBDATAL 1 P2 0 to TBPWM mode ORG 0100H Resetaddress START DI SB1 Extra command only for debugging LD OF7H 5FH Extra command only for debugging SBO Extra command only for debugging LD TBDATAH 40 1 Set 40 us LD TBDATAL 1 Set any value except 00H LD TBCON 00010001B Clock Source lt fxx 4 Disable Timer B interrupt Select one shot mode for Timer B Stop Timer B operation Set Timer B output flip flop T FF high LD P2CONL 03H Set P2 0 to TBPWM mode PULSE_OUT LD TBCON 00000101B Start Timer B operation to make the pulse at this point After the instruction is executed 0 75 us is required before the falling edge
268. unter Timer 10 11 with three operating modes Interval mode Capture mode and PWM mode Watch Timer e Real time and interval time measurement e Four frequency output to BUZ pin S3C84H5 F84H5 A D Converter e 10 bit resolution e Eight analog input channels e 20us conversion speed at 10MHz clock Asynchronous UART e One Asynchronous UART e Programmable baud rate generator e Supports serial data transmit receive operations with 8 bit 9 bit in UART PWM Module e One 10 bit programmable PWM output Serial I O e One synchronous serial I O module e Selectable transmit and receive rates Built in RESET Circuit LVR e Low Voltage check to make system reset 2 8V by smart option Oscillation Frequency e 1MHz to 10MHz external crystal oscillator Operating Temperature Range e 25 C 85 C Operating Voltage Range e LVRon LVR to 5 5 V 8MHz e LVR off 2 5 V to 5 5 V 8MHz e LVR off on 4 5 V to 5 5 V 10MHz Package Type 32 pin SOP SDIP 30 SDIP e 285 ELECTRONICS S3C84H5 F84H5 BLOCK DIAGRAM PRODUCT OVERVIEW P1 0 P1 5 INTO INT3 BUZ AD5 AD6 Figure 1 1 S3C84H5 F84H5 Block Diagram ELECTRONICS 0 0 0 3 TAOUT TACAP TACK ADO A
269. usssusussusussessuscussosussusaussscense 6 65 PUSH Push to Stack ssssssssunsssunsessussussnsausnssunssssssnscussseussnseussssunscusassusenscssuscusesssssuscussssussoncusescuse 6 66 PUSHUD Push User Stack Decrementing sassssunsssnsssssssssunsasussesaussssusscssusssseusesusssusensasusscusussuneuso 6 67 PUSHUI Push User Stack Incrementing sasusssnessssssssunsasussessessusenscussssusenscususeussscussnsausescunsessusese 6 68 RCF Reset Carry Flag sassssunssssussussssassuscussssuascscussesensesusosuseusassuscusssesssnsausuosunsosusssusessesusseusesees 6 69 RET Return sassssunssssassusussaususcussosusenssussscussssussssssussesssscssussusessassescunsessusesaussecusnseusessusensassuocussonsn 6 70 RL Rotate Left sassssusssssussssunsesuussusunsassussussseusenscussscusscssusescunsessusescussesusnseusessuseuscusescusessassuseues 6 71 RLC Rotate Left through Carry sasusssussssasssssnsasusssussunsesusscusessusenscussssussossususeussscusenscussscunsesuusens 6 72 RR Rotate Right 6 73 Rotate Right through Carry sassssunssusassusensessuscussssuassusensesunseusessusenseususcussosusensaensscunsesauseoe 6 74 SBO Select Bank 0 sassssunssssussussensessassusensaususcunsosussescunscsusosusessssssscesussussuscsssssusnensausescunsosuussusenes 6 75 SB1 Select Bank 1 sassasunssususssssnssusussusensaususcussessssssaussssusesusensesssscusessusenscsssscusessauseseussssussousenes 6 76 SBC Subtract with Carry sasussssussussnsesssssusssssasssaussssunscsasussusenseususcus
270. vates to the time that basic timer starts counting Figure 7 5 Oscillator Control Register OSCCON STOP Control Register STOPCON Set 1 Bank 0 R W STOP Control bits Other values Disable STOP instruction 10100101 Enable STOP instruction Figure 7 6 STOP Control Register STOPCON 7 4 ELECTRONICS S3C84H5 F84H5 RESET and POWER DOWN RESET AND POWER DOWN SYSTEM RESET OVERVIEW During a power on reset the voltage at Vpp goes to High level and the RESET pin is forced to Low level The RESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock This procedure brings 53084 5 84 5 into a known operating status To allow time for internal CPU clock oscillation to stabilize the RESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance The minimum required oscillation stabilization time for a reset operation is 1 millisecond Whenever a reset occurs during normal operation that is when both and RESET are High level the RESET pin is forced Low and the reset operation starts All system and peripheral control registers are then reset to their default hardware values In summary the following sequence of events occurs during a reset operation Interrupt is disabled watchdog function basic timer is enabled Ports 0 3 are set to input mode Peripheral control and data
271. vent the overflow and the accompanying reset operation from occurring To do this the BTONT value must be cleared by writing a 1 to BTCON 1 at regular intervals If a system malfunction occurs due to circuit noise or some other error condition the BT counter clear operation will not be executed and a basic timer overflow will occur initiating a reset In other words during the normal operation the basic timer overflow loop a bit 7 overflow of the 8 bit basic timer counter BTCNT is always broken by a BTONT clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop mode has been released by an external interrupt In Stop mode whenever a reset or an external interrupt occurs the oscillator starts The BTCNT value then starts increasing at the rate of 5 4096 for reset or at the rate of the preset clock source for an external interrupt When 4 overflows a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation In summary the following events occur when stop mode is released 1 During stop mode a power on reset or an interrupt occurs to trigger the Stop mode release and oscillation starts 2 If a power on reset occurred
272. ventions Flag Description 2 Zero flag 5 Sign flag V Overflow flag D Decimal adjust flag H Half carry flag 0 Cleared to logic zero 1 Set to logic one Set or cleared according to operation Value is unaffected X Value is undefined Table 6 3 Instruction Set Symbols Symbol Description dst Destination operand src Source operand Indirect register address prefix PC Program counter IP Instruction pointer FLAGS Flags register D5H RP Register pointer Immediate operand or register address prefix H Hexadecimal number suffix D Decimal number suffix B Binary number suffix opc Opcode S3C84H5 F84H5 ELECTRONICS S3C84H5 F84H5 INSTRUCTION SET Table 6 4 Instruction Notation Conventions Notation Description Actual Operand Range Condition code See list of condition codes in Table 6 6 r Working register only Rn 0 15 rb Bit b of working register Rn b n 0 15 b 0 7 ro Bit O LSB of working register Rn n 0 15 rr Working register pair RRp p 0 2 4 14 R Register or working register reg or Rn reg 0 255 n 0 15 Rb Bit b of register or working register reg b reg 0 255 b 0 7 RR Register pair or working register pair reg or RRp reg 0 254 even number only where p 0 2 14 IA Indirect addressing mode addr addr 0 254 even number only Ir Indirect working register only Rn
273. xample 2 17 2 14 8 Bit Working Register Addressing 2 18 2 15 8 Bit Working Register Addressing Example 2 19 2 1 6 Operations 2 20 3 1 Register Addressing 3 2 3 2 Working Register Addressing 3 2 3 3 Indirect Register Addressing to Register 3 3 3 4 Indirect Register Addressing to Program Memory NNLLA BN AN 3 4 3 5 Indirect Working Register Addressing to Register File mmm 3 5 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 3 7 Indexed Addressing to Register 3 7 3 8 Indexed Addressing to Program or Data Memory with Short Offset n 3 8 3 9 Indexed Addressing to Program or Data Memory rere ee eee eee rere reer eee eer ey 3 9 3 10 Direct Addressing for Load Instructions 3 10 3 11 Direct Addressing for Call and Jump Instructions M MM M ee4e 3 11 3 12 Indirect Addressing 4 4Aa 46 3 12 3 13 Relative A
274. y hardware interrupt logic sets the corresponding pending bit to 1 when a request occurs It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced The CPU acknowledges the interrupt source by sending an executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software In the S3C84H5 F84HB5 interrupt structure the timer underflow interrupt IRQO belongs to this category of interrupts in which pending condition is cleared automatically by hardware Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software The service routine must clear the appropriate pending bit before a return from interrupt subroutine IRET occurs To do this a 0 must be written to the corresponding pending bit location in the source s mode or control register In the S3C84H5 F84H5 interrupt structure pending conditions for IRQ3 IRQ4 IRQ5 IRQ6 and IRQ7 must be cleared in the interrupt service routine ELECTRONICS 5 15 INTERRUPT STRUCTURE S3C84H5 F84H5 INTERRUPT SOURCE POLLING SEQUENCE The NO a PON interrupt request polling and servicing sequence is as follows A source generates an interrupt request by setting the interrupt request bit to 1 The CPU polling procedure identifies a pending condition for that source The CPU checks

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