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C8051F060/1/2/3/4/5/6/7

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1. DATA BUS 2 zl 2 zl ACCUMULATOR B REGISTER STACK POINTER e a TMP1 TMP2 lt k SRAM PSW 4 ADDRESS mM ALU REGISTER 256 X 8 amp 8 B B DATA BUS i SFR ADDRESS BUFFER SFR_CONTROL De BUS SFR WRITE DATA DATA POINTER 8 INTERFACE gt SFR_READ DATA PC INCREMENTER no PROGRAM COUNTER PC MEN CADO MESS MEM_CONTROL _ lt MEMORY PRGM ADDRESS REG lt 216 INTERFACE MEM WRITE DATA a MEM READ DATA PIPELINE 58 CONTROL LOGIC YSTEM IR cock 1g _ gt INTERRUPT DEBUG_IR STOP D POWER CONTROL L IDLE REGISTER r 124 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Programming and Debugging Support A JTAG based serial interface is provided for in system programming of the Flash program memory and communication with on chip debug support logic The re programmable Flash can also be read and changed a single byte at a time by the application software using the MOVC and MOV xX instructions This feature allows program memory to be used for non volatile data storage as well as updating program code under software control The on chip debug support lo
2. Register name Notes 0x04 Interrupt Register 0x0000 Read Only 0x05 Test Register 0x0000 7 RX is determined by CAN bus 0x06 BRP Extension Register 0 0000 Write Enabled by TEST bit in CANOCN 0x08 Command Request 0x0001 CANOADR autoincrements IF1 index space 0x08 0x12 upon write to CANODATL 0x09 Command Mask 0x0000 CANOADR autoincrement upon write to CANODATL 0x0A IF1 Mask 1 OxFFFF CANOADR autoincrement upon write to CANODATL 0x0B IF1 Mask 2 OxFFFF CANOADR autoincrement upon write to CANODATL 0x0G IF1 Arbitration 1 0 0000 CANOADR autoincrement upon write to CANODATL 0x0D IF1 Arbitration 2 0 0000 CANOADR autoincrement upon write to CANODATL 0x0E IF1 Message Control 0x0000 CANOADR autoincrement upon write to CANODATL 0x0F IF1 Data A1 0x0000 CANOADR autoincrement upon write to CANODATL 0x10 IF1 Data A2 0x0000 CANOADR autoincrement upon write to CANODATL 0x11 IF1 Data B1 0x0000 CANOADR autoincrement upon write to CANODATL 0x12 IF1 Data B2 0x0000 CANOADR autoincrement upon write to CANODATL 0x20 IF2 Command Request 0x0001 CANOADR autoincrements IF1 index space 0x08 0x12 upon write to CANODATL 0x21 IF2 Command Mask 0x0000 CANOADR autoincrement upon write to CANODATL 0x22 IF2 Mask 1 OxFFFF CANOADR autoincrement upon write to CANODATL 0x23 IF2 Mask 2 OxFFFF CANOADR a
3. T4E XBR2 3 T4EX 4 2 4 e SYSCKE 1 7 CNVSTR2 e e e e e CNVSTE2 XBR3 2 X5 E F da dodo Re eRe lt lt lt 5 1S 0 19 0 1 2 205 SILICON LABS C8051F060 1 2 3 4 5 6 7 eral s enable bits are not set to a logic 1 then its ports are not accessible at the Port pins of the device Also note that the Crossbar assigns pins to all associated functions when the SMBus or UART1 are selected i e SMBus SPI UART It would be impossible for example to assign TXO to a Port pin without assigning RXO as well The SPI can operate in 3 or 4 wire mode with or without NSS Each com bination of enabled peripherals results in a unique device pinout All Port pins on Ports 0 through 3 that are not allocated by the Crossbar be accessed as General Pur pose I O GPIO pins by reading and writing the associated Port Data registers See Figure 18 9 Figure 18 11 Figure 18 14 and Figure 18 17 set of SFRs which are both byte and bit addressable The output states of Port pins that are allocated by the Crossbar are controlled by
4. 148 13 3 Intemupb Handler y 151 13 3 1 MCU Interrupt Sources and 151 13 3 2 External 151 13 3 3 5 153 13 3 4 Interrupt Latency 153 13 3 5 Interrupt Register Descriptions 154 13 4 Power Management 76 160 EST NBN em T 160 13 425108 161 pM 163 14 1 Power on uci RN UU TU 164 14 2 Power fail UU UU 164 14 3 External 164 14 4 Missing Clock Detector 165 14 5 ComparatorO 0 165 14 6 External CNVSTR2 Pin 165 14 7 Watchdog Timer 00 165 4 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 14 7 1 Enable Reset 000 166 2 TIS A 166 14 7 9 018408 WD T E DOKDHE uuu era tenen edere s tus ttbi epe euch inr xen etes 166 14 7 4 Set ng WDT Interval eco
5. PCAOCN WIC A A A OIWIC 1 F FIF FIFIF 6 n n n n 5143121110 n PCAOCPLn PCAOCPHn o 0 o aes Pt 3 Port DX 34 Crossbar LCEXn 0 X o o Note The signal at CEXn must be high or low for least 2 system clock cycles in order to be valid 306 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 25 2 2 Software Timer Compare Mode In Software Timer mode the PCAO counter timer is compared to the module s 16 bit capture compare reg ister PCAOCPHn and PCAOCPLn When a match occurs the Capture Compare Flag CCFn in PCAOCN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by software Setting the ECOMn and MATn bits in the register enables Software Timer mode Important Note About Capture Compare Registers When writing a 16 bit value to the PCAO Capture Compare registers the low byte should always be written first Writing to PCAOCPLn clears the ECOMnh bit to 0 writing to PCAOCPHn sets to 1 Figure 25 5 PCA Software Timer Mode Diagram Write to PCAOCPLn 0 Reset PCA Write to Interrupt PCAOCPHn PCAOCPLn PCAOCPHn
6. SYSCKE XBR1 7 CNVSTE2 XBR3 2 1 2 209 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 18 5 XBRO Port Crossbar Register 0 R W R W R W R W R W R W R W R W Reset Value CPOE ECIOE PCAOME UARTOEN SPIOEN SMBOEN 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0xE1 SFR Page F Bit7 CPOE Comparator 0 Output Enable Bit 0 CPO unavailable at Port pin 1 CPO routed to Port pin Bit6 ECIOE PCAO External Counter Input Enable Bit 0 PCAO External Counter Input unavailable at Port pin 1 PCAO External Counter Input 0 routed to Port pin Bits5 3 PCAO Module I O Enable Bits 000 All PCAO unavailable at port pins 001 routed to port pin 010 CEX1 routed to 2 port pins 011 CEX1 and CEX2 routed to 3 port pins 100 CEX1 CEX2 and CEX3 routed to 4 port pins 101 CEX1 CEX2 CEX3 and routed to 5 port pins 110 CEX1 CEX2 CEX3 and CEX5 routed to 6 port pins Bit2 UARTOEN UARTO I O Enable Bit 0 UARTO I O unavailable at Port pins 1 UARTO TX routed to P0 0 and RX routed to 1 Bit1 SPIOEN SPIO Bus I O Enable Bit 0 SPIO I O unavailable at Port pins 4 wire mode 1 SPIO SCK MISO MOSI and NSS routed to 4 Port pins 3 wire mode 1 SPIO SCK MISO
7. 87 Figure 7 2 Temperature Sensor Transfer 89 Figure 7 3 10 Bit ADC Track and Conversion Example Timing 90 Figure 7 4 ADC2 Equivalent Input 91 Figure 7 5 AMX2CF AMUX2 Configuration Register 92 Figure 7 6 AMX2SL AMUX2 Channel Select 93 Figure 7 7 ADC2CF ADC2 Configuration Register 94 Figure 7 8 ADC2H ADC2 Data Word MSB Register 95 Figure 7 9 ADC2L ADC2 Data Word LSB 95 Figure 7 10 ADC2CN ADC2 Control 96 Figure 7 11 ADC2GTH ADC2 Greater Than Data High Byte Register 97 Figure 7 12 ADC2GTL ADC2 Greater Than Data Low Byte Register 97 Figure 7 13 ADC2LTH ADC2 Less Than Data High Byte Register 98 10 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 7 14 ADC2LTL ADC2 Less Than Data Low Byte Register 98 Figure 7 15 ADC Window Compare Example Right Justified Single Ended Data 99 Figure 7 16 ADC Window Compare Example Left Justified Single Ended Data 99 Figure 7 17 A
8. 38 4 Pinout and Package Definitions J 39 5 16 Bit ADCs ADCO and ADC1 51 5 1 Single Ended or Differential Operation 52 5 1 1 Pseudo Differential 52 5 2 Voltage Reference I 53 5 3 ADG Modes 0 54 5 3 1 Starting CODVOFSIOE s ient tui preteen teint atus andes epe 54 5 3 2 Tracking MOGOUDGS 54 5 3 3 Settling Time 22 56 5 4 Calibration 66 5 5 ADCO Programmable Window Detector 69 6 Direct Memory Access Interface DMA 0 75 6 1 Writing to the Instruction Buffer 75 6 2 Instruction 76 6 3 XRAM Addressing and 76 6 4 Instruction Execution in Mode 0 77 6 5 Instructio
9. 87 Table 7 1 ADC2 Electrical Characteristics 2 101 8 DACs 12 Bit Voltage Mode DACO and DAC1 C8051F060 1 2 3 103 Table 8 1 DAC Electrical Characteristics 2 109 9 Voltage Reference 2 8051 060 2 2 2 111 Table 9 1 Voltage Reference Electrical Characteristics 112 10 Voltage Reference 2 8051 061 3 2 22 4 113 Table 10 1 Voltage Reference Electrical Characteristics 114 11 Voltage Reference 2 C8051F064 5 6 7 J 115 Table 11 1 Voltage Reference Electrical Characteristics 116 12 117 Table 12 1 Comparator Electrical Characteristics 122 CIP 51 Microcontroller SE 123 Table 13 1 CIP 51 Instruction Set Summary eese 126 Table 13 2 Special Function Register SFR Memory Map 141 Table 13 3 Special Function Registers esses 143 Table 13 4 Interrupt Summary nnn 152 14 ReS LEP S QU r 8S S E
10. Name 060 F061 064 F065 Type Description F062 F063 F066 F067 P7 2 AD2m 70 70 D I O Port 7 2 See Port Input Output section for complete D2 description P7 3 AD3m 69 69 D Port 7 3 See Port Input Output section for complete D3 description P7 4 AD4m 68 68 D I O Port 7 4 See Port Input Output section for complete 04 description P7 5 AD5m 67 67 D Port 7 5 See Port Input Output section for complete D5 description P7 6 AD6m 66 66 D Port 7 6 See Port Input Output section for complete D6 description P7 7 AD7m 65 65 D Port 7 7 See Port Input Output section for complete D7 description NC 1 2 3 17 59 25 94 160 62 95 64 44 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 RST 92 P4 6 RD P4 7 WR 90 VDD 89 DGND 5 7 15 99 TDO 98 TDI 97 96 80 6 0 8 0 79 P6 1 A9m A1 78 6 2 10 2 77 6 11 76 6 4 12 4 95 94 93 P4 5 ALE 88 P5 0 A8 87 P5 1 A9 86 5 2 10 85 P5 3 A11 84 P5 4 A12 83 P5 5 A13 82 P5 6 A14 81 e 91 DAC1 1 P6 5 A13m A5 VREF2 2 P6 6 A14m A6 VREFD 3 P6 7 A15m A7 VREF 4 P7 0 ADOm DO VBGAP1 5 P7 1 AD1m D1 VREF1 6 P7 2 AD2m D2 VRGND1 7 P7 3 AD3m D3 8 P7 4 AD4m D4 AIN1 9 P7 5 AD5m D5 AGND 10 P7 6 AD6m
11. 321 26 1 4 IDCODE Nie 321 Rev 1 2 7 SILICON LABS C8051F060 1 2 3 4 5 6 7 26 2 Flash Programming Commands sse 322 26 3 Debug UCI REOR 325 27 Document Change List 327 27 1 Revision 1 1 to Revision 1 8 327 8 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 List of Figures 1 System Overview l I 19 Figure 1 1 C8051F060 C8051F062 Block 21 Figure 1 2 C8051F061 C8051F063 Block 22 Figure 1 3 C8051F064 C8051F066 Block 23 Figure 1 4 C8051F065 C8051F067 Block 24 Figure 1 5 Comparison of Peak MCU Execution Speeds 25 Figure 1 6 On Board Clock and 26 Figure 1 7 On Chip Memory 27 Figure 1 8 Development In System Debug 28 Figure 1 9 Digital Crossbar 29 Figure 1 10 PCA Block uu hte te eH tur Rr x tenere
12. 263 22 UART0 21 265 Figure 22 1 Block Diagram nre renta kon retrait 265 Figure 22 2 UARTO Mode 0 Timing 7 267 Figure 22 3 UARTO Mode 0 200 267 Figure 22 4 UARTO Mode 1 Timing Diagram sese 267 Figure 22 5 UARTO Modes 2 Timing 269 Figure 22 6 UARTO Modes 1 2 and 3 Interconnect Diagram 270 Figure 22 7 UART Multi Processor Mode Interconnect Diagram 272 Figure 22 8 SCONO UARTO Control Register 274 Figure 22 9 SSTAO UARTO Status and Clock Selection Register 275 Figure 22 10 SBUFO UARTO Data Buffer Register 276 Figure 22 11 SADDRO UARTO Slave Address Register 276 Figure 22 12 SADENO UARTO Slave Address Enable Register 276 23 n 277 Figure 23 1 UART1 Block 2 20000000 0 277 Figure 23 2 UART1 Baud Rate 44040 0 278 Figure 23 3 UART Interconnect Diagram
13. eere 279 Figure 23 4 8 Bit UART Timing 279 Figure 23 5 9 Bit UART Timing 280 Figure 23 6 UART Multi Processor Mode Interconnect Diagram 281 Figure 23 7 SCON1 Serial Port 1 Control 282 Figure 23 8 SBUF1 Serial UART1 Port Data Buffer Register 283 LONE T UU ML 287 Figure 24 1 TO Mode 0 Block DISOFBETI ue eterne rene nix net 288 Figure 24 2 TO Mode 2 Block 289 Figure 24 3 TO Mode Block 290 Figure 24 4 TCON Timer Control 291 Figure 24 5 TMOD Timer Mode 292 14 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 24 6 CKCON Clock Control Register 293 Figure 24 7 TLO Timer 0 Low 442022 044 111 294 Figure 24 8 TL1 Timer 1 Low Byte 294 Figure 24 9 THO Timer 0 High 294 Figure 24 10 TH1 Timer 1 High 294 Figure 24 11 T2 and 4 Capture Mode Block Diagram 296 Figure 24 12 T2 3 and 4 Auto reload Mode Block Di
14. R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address OxFA SFR Page 0 Bits 7 0 PCAOH Counter Timer High Byte The PCAOH register holds the high byte MSB of the 16 bit PCAO Counter Timer 3 Rev 1 2 315 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 25 15 PCAOCPLn PCAO Capture Module Low Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito PCAOCPLO OxFB PCAOCPL1 0xFD 2 OxE9 PCAOCPL3 OxEB PCAOCPL4 OxED SFR Address OxE1 PCAOCPLO page 0 PCAOCPL1 page 0 PCAOCPL2 page 0 PCAOCPL3 page 0 PCAOCPL4 page 0 5 page 0 SFR Page Bits7 0 PCAOCPLn PCAO Capture Module Low Byte PCA0CPLn register holds the low byte LSB of the 16 bit capture module Figure 25 16 PCAOCPHn PCAO Capture Module High Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito OxFC PCAOCPH1 0xFD 2 0xEA 0xEC OxEE PCAOCPH5 0 2 page 0 1 0 2 0 page 0 page 0 page 0 SFR Address SFR Page Bits7 0 PCAOCPHn PCAO C
15. 205 Figure 18 4 Crossbar 2 4 000000000 209 12 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 18 5 XBRO Port Crossbar Register 0 210 Figure 18 6 XBR1 Port I O Crossbar Register 1 211 Figure 18 7 XBR2 Port I O Crossbar Register 2 212 Figure 18 8 Port I O Crossbar Register 213 Figure 18 9 PO Port0 Data Register 214 Figure 18 10 POMDOUT Port0 Output Mode 214 Figure 18 11 P1 Porti repetit citta cpu 215 Figure 18 12 Port1 Input Mode 215 Figure 18 13 P1MDOUT Output Mode 216 Figure 18 14 P2 Pore Data Register 216 Figure 18 15 P2MDIN Port2 Input Mode 217 Figure 18 16 PAMDOUT Port2 Output Mode 217 Figure 18 17 Port3 Data 024222
16. 267 22 1 3 Mode 2 9 Bit UART Fixed Baud Rate 269 22 1 4 Mode 3 9 Bit UART Variable Baud 270 22 2 Multiprocessor 271 22 2 1 Configuration of a Masked Address 271 22 2 2 Broadcast 271 22 3 and Transmission Error 272 23 277 23 1 Enhanced Baud Rate Generation esses 278 23 2 Operational MOUGS 279 23 2 h8 BICUAR eaten aes 279 23 2 2 9 Bit UART e ee eee 280 23 3 Multiprocessor 281 24 E E 287 24 1 Timer 0 and Timer 1 yx Fono nda yx a 287 24 1 1 Mode 0 13 bit Counter Timer 287 24 1 2 1 16 bit Counter Timer 289 24 1 3 Mode 2 8 bit Counter Timer with Auto Reload 289 24 1 4 Mode 3 Two 8 bit Counter Timers Timer 0 Only 290 24 2 Timer 2 Timer 3 a
17. R W R W R W R W R W R W R W R W Reset Value EAS1 EASO ERW3 EWR2 EWRO EAH1 EAHO 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0xA1 SFR Page 0 Bits7 6 EAS1 0 EMIF Address Setup Time Bits 00 Address setup time 0 SYSCLK cycles 01 Address setup time 1 SYSCLK cycle 10 Address setup time 2 SYSCLK cycles 11 Address setup time 3 SYSCLK cycles Bits5 2 EWR3 0 and RD Pulse Width Control Bits 0000 WR and RD pulse width 1 SYSCLK cycle 0001 WR and RD pulse width 2 SYSCLK cycles 0010 WR and RD pulse width 3 SYSCLK cycles 0011 WR and RD pulse width 4 SYSCLK cycles 0100 WR and RD pulse width 5 SYSCLK cycles 0101 WR and RD pulse width 6 SYSCLK cycles 0110 WR and RD pulse width 7 SYSCLK cycles 0111 WR and RD pulse width 8 SYSCLK cycles 1000 WR and RD pulse width 9 SYSCLK cycles 1001 WR and RD pulse width 10 SYSCLK cycles 1010 WR and RD pulse width 11 SYSCLK cycles 1011 WR and RD pulse width 12 SYSCLK cycles 1100 WR and RD pulse width 13 SYSCLK cycles 1101 WR and RD pulse width 14 SYSCLK cycles 1110 WR and RD pulse width 15 SYSCLK cycles 1111 WR and RD pulse width 16 SYSCLK cycles Bits1 0 1 0 EMIF Address Hold Time Bits 00 Address hold time 0 SYSCLK cycles 01 Address hold time 1 SYSCLK cycle 10 Address hold time 2 SYSCLK cycles 11 Address hold time 3 SYSCLK
18. 163 Figure 14 1 Reset SOI COS 163 Figure 14 2 Reset Timing 164 Figure 14 3 WDTCN Watchdog Timer Control 167 Figure 14 4 RSTSRC Reset Source Register 168 15 OSeIllatorS uu MOMENTO 171 Figure 15 1 Oscillator Diagram temen scia 171 Figure 15 2 OSCICL Internal Oscillator Calibration Register 172 Figure 15 3 OSCICN Internal Oscillator Control Register 172 Figure 15 4 CLKSEL Oscillator Clock Selection Register 173 Figure 15 5 OSCXCN External Oscillator Control Register 174 15 Flash MBITiOP amie 177 Figure 16 1 C8051F060 1 2 3 4 5 Flash Program Memory and Security Bytes 180 Figure 16 2 8051 066 7 Flash Program Memory and Security Bytes 181 Figure 16 3 FLACL Flash Access 182 Figure 16 4 FLSCL Flash Memory 084 184 Figure 16 5 PSCTL Program Store Read Write 185 17 External Data Memory Interface and On Chip
19. EDENDI STO 1 Crossbar Dee ts es te Ape ea 1909 ee i Port I O Figure 1 10 Block Diagram 30 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 1 6 Controller Area Network The C8051F060 1 2 3 devices feature a Controller Area Network CAN controller that implements serial communication using the CAN protocol The CAN controller facilitates communication on a CAN network in accordance with the Bosch specification 2 0A basic CAN and 2 0B full CAN The CAN controller con sists of a CAN Core Message RAM separate from the C8051 RAM a message handler state machine and control registers The CAN controller can operate at bit rates up to 1 Mbit second Silicon Labs CAN has 32 message objects each having its own identifier mask used for acceptance filtering of received messages Incoming data message objects and identifier masks are stored in the CAN message RAM All protocol functions for transmission of data and acceptance filtering is performed by the CAN controller and not by the C8051 MCU In this way minimal CPU bandwidth is used for CAN communication The C8051 configures the CAN controller accesses received data and passes data for transmission via Special Function Registers SFR in the C8051 SANTA 2 C8051F060 1 2 3 CAN Controller Figur
20. LA JAN b 1 Figure 4 3 100 Package Drawing 1 2 47 SILICON LABS C8051F060 1 2 3 4 5 6 7 c 0d L Od 0 0d SNL MOL oal 16 XLNVO XHNVO cd3dA N3NOIN 2 2 40 VDD 39 DGND 38 P23 37 2 4 36 2 5 35 2 6 34 2 7 33 P1 0 AIN2 0 48 47 0 4 46 P0 5 45 PO 6 44 0 7 43 P2 0 42 P2 1 41 CO O NY N Lo LO Nj 0 JM JO CO Lo N N IN N LO e re cO LL Y LO N N v NS OO IN c Lo LO LO LO LO 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 VBGAP 1 VREF1 VRGND1 AIN1 AGND AV CNVSTR1 CNVSTRO AV AGND AINO AINOG VRGNDO VREFO VBGAPO ONIV 2 Ld eNIV Ld F cNIV r Ld G eNIV S bd 9 ZNIV 9 Ld lt 1V1X oova SILICON LABS Figure 4 4 C8051F061 C8051F063 Pinout Diagram TQFP 64 Rev 1 2 48 C8051F060 1 2 3 4 5 6 7 z LLI oO gt gt gt gt gt gt m IN Oj N Je o O O JO JO LO LO O LO LO FLO O O o Js VBGAP1
21. 232 Figure 19 7 CANOTST CAN Test 00 44000012 233 Figure 19 8 CANOSTA CAN Status 233 20 System Management BUS I2C BUS SMBUSJO 235 Figure 20 1 SMBusO Block 235 Figure 20 2 Typical SMBUS Configuration eu e eom 236 Figure 20 3 SMBus 5 237 Figure 20 4 Typical Master Transmitter 238 Figure 20 5 Typical Master Receiver 238 Figure 20 6 Typical Slave Transmitter 239 Figure 20 7 Typical Slave Receiver 240 Figure 20 8 SMBOCN SMBus0 Control Register 243 Figure 20 9 SMBOCR SMBus0 Clock Rate Register 244 Figure 20 10 SMBODAT 5 0 Data 245 Figure 20 11 SMBOADR 5 0 Address 2 246 Figure 20 12 SMBOSTA SMBus0 Status Register 247 21 Enhanced Serial Perip
22. 139 Figure 13 10 SFBPAGE SFR Page Register aa 139 Figure 13 11 SFRNEXT SFR Next 140 Figure 13 12 SFRLAST SFR Last 22 140 Figure 13 13 SP Stack Pointer M 148 Figure 13 14 DPL Data Pointer Low Byte trn entran na denen a 148 Figure 13 15 Data Pointer High 2 2 148 Figure 13 16 PSW Program Status Word nante rne 149 Rev 1 2 11 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 13 17 ACC 000 440404 00 nennen 150 Figure 13 18 B 150 Figure 13 19 IE Interrupt Enable arteria c eno en ae 154 Figure 13 20 IP Interrupt Priority 1 rien rores rrr ranis 155 Figure 13 21 EIE1 Extended Interrupt Enable 1 156 Figure 13 22 EIE2 Extended Interrupt Enable 2 157 Figure 13 23 EIP1 Extended Interrupt Priority 1 022 44 158 Figure 13 24 EIP2 Extended Interrupt Priority 2 159 Figure 13 25 Power Control onis etras baile etnia ordine eni 161 14 Reset OCS u u u
23. 5 XBRO XBR1 XBR2 XBR3 1 2 4 5 CANODATL CANODATH CANOADR CANOTST DMAODAL DMAODAH DMAODSL DMAODSH DMAOIPT DMAOIDT REFOCN DACOL DACOH DACOCN REF1CN DACIL DAC1H DACICN REF2CN TMR2CN TMR2CF RCAP2L RCAP2H TMR2L TMR2H SMBOCR TMR3CF RCAP3L RCAP3H TMR3L TMR3H C8 TMR4CN TMR4CF RCAP4L RCAP4H TMR4L TMR4H P4 SMBOCN SMBOSTA SMBODAT SMBOADR ADCOGTL ADCOGTH ADCOLTL ADCOLTH CANOSTA ADC2GTL ADC2GTH ADC2LTL ADC2LTH SADENO AMXOSL ADCOCF ADCOL ADCOH a ADC1CF ADC1L ADC1H ALL PAGES 2 AMX2SL ADC2CF ADC2L ADC2H ADC0CPT ADC0CCF 1 9 2 3 B 4 C 5 D 6 E 7 F 1 Rev 1 2 141 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 13 2 Special Function Register SFR Memory Map OSCICN OSCICL 5 SFRPAGE SFRNEXT SFRLAST FLSCL ALL PAGES FLACL SADDRO ALL PAGES P1MDIN P2MDIN EMIOTC EMIOCN P2 n ALL PAGES POMDOUT P1MDOUT P2MDOUT P3MDOUT SCONO SBUFO SPIOCFG SPIODAT SPIOCKR SCON1 SBUF1 98 P4MDOUT P5MDOUT PeMDOUT P7MDOUT SSTAO ALL PAGES SFRPGCN CLKSEL TMOD TLO TL1 THO TH1 CKCON PSCTL CPTOCN CPTOMD 88 CPT1CN CPT1MD CPT2CN CPT2MD 142 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7
24. 5 0 2 0 PCA Capture 5 High page 316 PCAOCPLO OxFB 0 PCA Capture 0 Low page 316 PCAOCPL1 OxFD 0 PCA Capture 1 Low page 316 PCAOCPL2 OxE9 0 PCA Capture 2 Low page 316 OxEB 0 PCA Capture 3 Low page 316 PCAOCPL4 OxED 0 PCA Capture 4 Low page 316 PCAOCPL5 OxE1 0 PCA Capture 5 Low page 316 PCAOCPMO OxDA 0 PCA Module 0 Mode Register page 314 1 OxDB 0 PCA Module 1 Mode Register page 314 2 OxDC 0 Module 2 Mode Register page 314 0xDD 0 PCA Module 3 Mode Register page 314 PCA0CPM4 OxDE 0 PCA Module 4 Mode Register page 314 PCAOCPM5 OxDF 0 PCA Module 5 Mode Register page 314 PCAOH OxFA 0 PCA Counter High page 315 PCAOL OxF9 0 PCA Counter Low page 315 PCAOMD OxD9 0 PCA Mode page 313 PCON 0x87 All Pages Power Control page 161 PSCTL Ox8F 0 Program Store R W Control page 185 PSW OxDO All Pages Program Status Word page 149 RCAP2H 0xCB 0 Timer Counter 2 Capture Reload High page 301 RCAP2L 0 Timer Counter 2 Capture Reload Low page 301 RCAP3H 0xCB 1 Timer Counter 3 Capture Reload High page 301 RCAP3L 1 Timer Counter Capture Reload Low page 301 RCAP4H 0xCB 2 Timer Counter 4 Capture Reload High page 301 RCAP4L 2 Timer Counter 4 Capture Reload Low page 301 5 1 2 145 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 13 3 Special Function Registers Continued SFRs are listed in alphabetical order All undefined SFR locations are re
25. Match c Start Shik a Port I O 4 Frame Error Input Shift Register Detection 9 bits Load S p SADDRO SBUFO Match Detect SADENO 4 Read SBUFO SFR Bus es ee RX lt 0 Crossbar Teena pss sss e Rev 1 2 265 SILICON LABS C8051F060 1 2 3 4 5 6 7 22 1 UARTO Operational Modes UARTO provides four operating modes one synchronous and three asynchronous selected by setting configuration bits in the SCONO register These four modes offer different baud rates and communication protocols The four modes are summarized in Table 22 1 Table 22 1 UARTO Modes Mode Synchronization Baud Clock Data Bits Start Stop Bits 0 Synchronous SYSCLK 12 8 None 1 Asynchronous Timer 1 2 3 or 4 Overflow 8 1 Start 1 Stop 2 Asynchronous SYSCLK 32 or SYSCLK 64 9 1 Start 1 Stop 3 Asynchronous Timer 1 2 3 or 4 Overflow 9 1 Start 1 Stop 22 1 1 Mode 0 Synchronous Mode Mode 0 provides synchronous half duplex communication Serial data is transmitted and received on the The TXO pin provides the shift clock for both transmit and receive The MCU must be the master since it generates the shift clock for transmission in both directions see the interconnect diagram in Figure 22 3 Data transmission begins when an instruction writes a data byte to the SBUFO register Eight data bits are transferred LSB fi
26. 4 FILTER 28 SMBUS CONTROL LOGIC Arbitrati SMBUS Interrupt SCL Synchronization SCL IRQ lt Request Status Generation cento PL gt e SCL Generation Master Mode Xl e IRQ Generation i Data Path SDA les Control Control C P ey Port TI m m 4 4 B B A 00000006 7 MSBs 8 7 Y SMBODAT SDA muss 716151413 21110 lt FILTER e i 11111 8 8 5515 5 5515 6 5 4 312 1 0 Read i SMBOADR Oe FA E d 2 SFR Bus 2 Rev 1 2 235 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 20 2 shows a typical SMBus configuration The SMBusO interface will work at any voltage between 3 0 V and 5 0 V and different devices on the bus may operate at different voltage levels The bi directional SCL serial clock and SDA serial data lines must be connected to a positive power supply voltage through a pull up resistor or similar circuit Every device connected to the bus must have an open drain or open collector output for both the SCL and SDA lines so that both are pulled high when the bus is free The maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus will not exceed 300 ns and 1000 ns respectively Figure 20 2 Typical SMBus Configuration VDD 5V VDD 3V VDD 5V VDD 3V
27. Enable Crossbar Port I O a PCA Timebase e Rev 1 2 311 SILICON LABS C8051F060 1 2 3 4 5 6 7 25 3 Register Descriptions for Following are detailed descriptions of the special function registers related to the operation of PCAO Figure 25 10 PCAOCN Control Register R W R W R W R W R W R W R W R W Reset Value CF CR CCF5 CCF4 CCF3 CCF2 CCF1 CCFO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0xD8 SFR Page 0 Bit7 CF PCA Counter Timer Overflow Flag Set by hardware when the PCAO Counter Timer overflows from OxFFFF to 0x0000 When the Counter Timer Overflow CF interrupt is enabled setting this bit causes the CPU to vec tor to the CF interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software Bit6 CR Counter Timer Run Control This bit enables disables the PCAO Counter Timer 0 PCAO Counter Timer disabled 1 Counter Timer enabled Bit5 CCF5 PCAO Module 5 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF interrupt is enabled setting this bit causes the CPU to vector to the CCF interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software Bit4 CCF4 PCAO Module 4 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the C
28. 227 19 2 CAN N Registers M 228 19 2 1 Controller Protocol 228 19 2 2 Message Object Interface Registers 228 19 2 3 Message Handler 422 4 21 228 19 2 4 CIP 51 MCU Special Function 229 19 2 5 Using CANOADR CANODATH and CANDATL To Access CAN Registers 229 19 2 6 CANOADR Autoincrement Feature 229 20 System Management BUS 12 BUS SMBUSJO 235 20 1 Supporting 236 20 2 SMBus Protocol 236 20 2 err A 237 20 2 2 Clock Low 237 20 2 3 SCL Low 237 20 2 4 SCL High SMBus Free 237 20 5 SMBUS Transfer Modes r 238 20 3 1 Master Transmitter Mode enews 238 20 3 2 Master Receiver 238 20 3 3 fave Transmitter MOOUG iia on x ee 239 20 3 4 Slave Receiver 239 20 4 SMBus Special Function 241
29. 52 Figure 5 3 Voltage Reference Block 53 Figure 5 4 ADC Track and Conversion Example 55 Figure 5 5 ADCO and ADC1 Equivalent Input Circuits 56 Figure 5 6 AMXOSL AMUX Configuration Register 57 Figure 5 7 ADCOCF ADCO Configuration Register 58 Figure 5 8 ADC1CF ADC1 Configuration Register 59 Figure 5 9 ADCOCN ADCO Control Register 60 Figure 5 10 ADC1CN ADC1 Control Register 2 61 Figure 5 11 REFOCN Reference Control Register 0 62 Figure 5 12 REF1CN Reference Control Register 1 62 Figure 5 13 ADCOH ADCO Data Word MSB Register 63 Figure 5 14 ADCOL ADCO Data Word LSB Register 63 Figure 5 15 ADCO Data Word 64 Figure 5 16 ADC1H ADC1 Data Word MSB 65 Rev 1 2 9 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 5 17 ADC1L ADC1 Data Word LSB 2 1
30. AINO 1 0 DMAODSH DMAODSL AINOG _ Current XRAM Address AIN1 DMA0DAH DMA0DAL a Beginning XRAM Address X 3 DMAOCTH DMAOCTL DMAOCSH DMAOCSL Repeat Counter Limit Current Repeat Counter Value 6 1 Writing to the Instruction Buffer The Instruction Buffer has 64 8 bit locations that can be programmed with a sequence of DMA instructions Filling the Instruction Buffer is done with the Special Function Registers DMAOIPT DMA Instruction Write Address Register Figure 6 6 and DMAOIDT DMA Instruction Write Data Register Figure 6 7 Instruc tions are written to the Instruction Buffer at address DMAOIPT when the instruction word is written to DMAOIDT Reading the register DMAOIDT will return the instruction word at location DMAOIPT After a write or read operation on DMAOIDT the DMAOIPT register is automatically incremented to the next Instruction Buffer location Rev 1 2 75 SILICON LABS C8051F060 1 2 3 4 5 6 7 6 2 DMAO Instruction Format DMA instructions can request single ended data from both ADCO and ADC1 as well as the differential combination of the two ADC inputs The instruction format is identical to the DMAOIDT register shown in Figure 6 7 Depending on which bits are set to 1 in the instruction word either 2 or 4 bytes of data will be written to XRAM for each DMA instruction cycle excluding End Of Operati
31. 16 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 List of Tables 1 System Overview uu u l u da Musa EU vd RR A FREU V EP RA ded 19 Table 1 1 Product Selection Guide 20 2 Absolute Maximum Ratings J 37 Table 2 1 Absolute Maximum Ratings 37 3 Global DC Electrical Characteristics J 38 Table 3 1 Global DC Electrical Characteristics 38 4 Pinout and Package Definitions 39 Table 4 1 Pin Definitions 39 5 16 Bit ADCs ADCO and ADC1 J 51 Table 5 1 Conversion Timing tConv 2 2 04000 55 Table 5 2 16 Bit ADCO and ADC1 Electrical Characteristics 73 Table 5 3 Voltage Reference 0 and 1 Electrical Characteristics 74 6 Direct Memory Access Interface 75 Table 6 1 DMAO Instruction Set 20 0 76 T 10 Bit ADC ADC2 8051 060 1 2 3
32. 163 Table 14 1 Reset Electrical Characteristics 2 169 rj qc 171 Table 15 1 Internal Oscillator Electrical Characteristics 173 16 Flash Memory TET TIC M A 177 Table 16 1 Flash Electrical Characteristics 22 178 17 External Data Memory Interface and On Chip XRAM 187 Table 17 1 AC Parameters for External Memory Interface 202 T8 POPE u 203 Table 18 1 Port DC Electrical Characteristics 203 19 Controller Area Network CANO 8051 060 1 2 3 225 Rev 1 2 17 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 19 1 CAN Register Index and Reset Values 229 20 System Management BUS 12 BUS SMBUS 235 Table 20 1 5 05 Status Codes and States 248 21 Enhanced Serial Peripheral Interface SPIO 251 Table 21 1 5 Slave Timing Parameters 264 22 UART0 uu uu P 265 Table 22 T MOGGS uu u au 266 Table 22 2 Oscill
33. Logic SPI CONTROL LOGIC SPI IRQ Data Path Pin Interface Control Control Tx Data MOSI F d d Y C SPIODAT SCK Transmit Data Buffer O Pin Control 5 Port I O Shift Regist Logic S ift Register 5 4 8 2 1 0 Pas MSO Bi R Receive Data Buffer NSS CN Read ee spiopat 2 SFRBus 1 2 251 SILICON LABS C8051F060 1 2 3 4 5 6 7 21 1 Signal Descriptions The four signals used by SPIO MOSI MISO SCK NSS are described below 21 1 1 Master Out Slave In MOSI The master out slave in MOSI signal is an output from a master device and an input to slave devices It is used to serially transfer data from the master to the slave This signal is an output when SPIO is operat ing as a master and an input when SPIO is operating as a slave Data is transferred most significant bit first When configured as a master MOSI is driven by the MSB of the shift register in both 3 and 4 wire mode 21 1 2 Master In Slave Out MISO The master in slave out MISO signal is an output from a slave device and an input to the master device It is used to serially transfer data from the slave to the master This signal is an input when SPIO is operat ing as a master and an output when SPIO is operating as a slave Data is transferred most significant bit first The MISO pin is placed in a high impedance state when the SPI module is disabled and
34. VDD where f frequency of oscillation in MHz capacitor value XTAL1 XTAL2 pins in pF VDD Power Supply on MCU in volts 174 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 15 4 External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU the circuit should be configured as shown in Figure 15 1 Option 1 The External Oscillator Frequency Control value XFCN should be chosen from the Crystal column of the table in Figure 15 5 OSCXCN register For example an 11 0592 MHz crystal requires an XFCN setting of 111b When the crystal oscillator is enabled the oscillator amplitude detection circuit requires a settle time to achieve proper bias Introducing a blanking interval of at least 1 ms between enabling the oscillator and checking the XTLVLD bit will prevent a premature switch to the external oscillator as the system clock Switching to the external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior The recommended procedure is Step 1 Enable the external oscillator Step 2 Wait at least1 ms Step 3 Poll for XTLVLD gt 1 Step 4 Switch the system clock to the external oscillator Important Note on External Crystals Crystal oscillator circuits are quite sensitive to PCB layout and external noise The crystal should be placed as close as possible to the XTAL pins on the device The traces should be
35. 113 11 Voltage Reference 2 8051 064 5 6 7 115 12 ComparalOES 117 12 1 Comparator 119 13 CIP 51 Microcontroller 123 IN 125 13 1 1 Instruction and CPU 125 13 1 2 MOVX Instruction and Program Memory 125 13 2 130 13 2 1 Program Memory a 130 13 2 2 Data Memory r 131 13 2 3 General Purpose 131 13 2 4 Bit Addressable Locations 131 131 13 2 6 Special Function Registers 0 440 2122 132 19 2 D T SER Paging 132 13 2 5 2 Interrupts and SFR Paging 132 13 2 6 3 SFR Page Stack Example 134 13 2 7 Register Descriptions
36. 20 2 4 SCL High SMBus Free Timeout The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 us the bus is designated as free If an SMBus device is waiting to generate a Master START the START will be gen erated following the bus free timeout Rev 1 2 237 SILICON LABS C8051F060 1 2 3 4 5 6 7 20 3 SMBus Transfer Modes The SMBusO interface may be configured to operate as a master and or a slave At any particular time the interface will be operating in one of the following modes Master Transmitter Master Receiver Slave Transmitter or Slave Receiver See Table 20 1 for transfer mode status decoding using the SMBOSTA sta tus register The following mode descriptions illustrate an interrupt driven SMBusO application SMBusO may alternatively be operated in polled mode 20 3 1 Master Transmitter Mode Serial data is transmitted on SDA while the serial clock is output SCL SMBusO generates a START condition and then transmits the first byte containing the address of the target slave device and the data direction bit In this case the data direction bit R W will be logic 0 to indicate a WRITE operation The SMBus0 interface transmits one or more bytes of serial data waiting for an acknowledge from the slave after each byte To indicate the end of the serial transfer SMBusO generates a STOP condition Figure 20 4 Typical Master Transmitter Sequence S WJA Dat
37. C8051F061 25 64k 4352 25 x 241 07518 12 2 3 64 TQFP C8051F062 25 64k 4352 v v v 2 5 59 5 8 12 2 3 100 TQFP C8051F063 25 64k 4352 2 511 241415 8 V 12 2 3 6 C8051F064 25 64k 4352 v v 2 5 559 0 75 Y 3 100 TQFP C8051F065 25 64k 4352 vl 1215 241 40 75 Y 3 64 8051 066 25 32k 4352 v v 2 5 559 0 75 Y 3 1100 TQFP C8051F067 25 32k 4352 12 5 241 0 75 Y 3 64 TQFP 20 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 VDD j SS 20 0 VDD 2 VDD DigitalPower U BEND 8 UART 1 SFRBus AGND ae R os AIN2 0 5 5 ms JTAG 8 AIN2 7 mr B Logic Debug HW B E 22 0 1 TimersQ 1 D 1 z Reset 3 4 R 2R gt 7 E 9 64kbyte MONEN VDDMonitor yt PO P1 P2 X FLASH 5 P3 Latches BN 23 0 e ExternalOscillator XTAL2 Circuit System Clock 32X136 Trimmedinternal CANRAM cANTX Oscillator O E CANRX E vREF2 VREF VREF r 256byte n Temp VREFD ADC2 M Sensor 200ksps DACO e 10 Bit x DACI 4kbyte RAM P26 avo R CA lt E AGND aan oy 24 VREFO CP2 VRENDO Extemal Data Memory Bus AINO D AINOG 0 P4Latch 24 5 VBGAP BusControl
38. Figure 5 23 The CPTR bits in ADCOCPT allow the ADCOCCF register to read and write spe cific calibration coefficients Figure 5 19 shows the Calibration Coefficient locations Figure 5 19 Calibration Coefficient Locations ADCOCCF Bit6 Bit5 Bit4 Bit3 Bit2 Bit ADCOCPT Linearity Calibration Coefficients locations 0x00 through 0x12 Offset7 Offset6 Offset5 Offset4 Offset3 Offset2 Offset1 OffsetO Offset13 Offset12 Offset11 Offset10 Offset9 Offset8 Gain7 Gain6 Gain5 Gain4 Gain3 Gain2 Gain1 Gain12 Gain11 Gain10 Gain9 Gain8 The ADCs are calibrated for linearity in production Under normal circumstances no additional linearity calibration is necessary If linearity calibrations are desired they can be initiated by setting the ADCnLCAL bit to 1 When the calibration is finished the ADCnLCAL bit will be set to 0 by the hardware Linearity Calibration Coefficients are stored in the locations shown in Figure 5 19 Offset and gain calibrations can be performed using either internal or external voltages as calibration sources The ADCnSCAL bit determines whether the internal or external voltages are used in the calibra tion process To ensure accuracy offset calibration should be done prior to a gain calibration The offset and gain calibration coefficients are decoded in Figure 5 20 Offset calibration is initiated by setting the ADCnOCAL bit 1 When the calibration is fini
39. Rev 1 2 67 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 5 22 ADCOCPT ADC Calibration Pointer Register RW R W R W R W R W R W R W R W Reset Value INCR ADCSEL CPTR5 CPTR4 CPTR3 CPTR2 CPTR1 CPTRO 11010111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address SFR Page F Bit 7 INCR Pointer Address Automatic Increment 0 Disable Auto Increment 1 Enable Auto Increment CPTR5 0 will automatically be incremented after each read or write to ADCOCCF Bit 6 ADCSEL ADC Calibration Coefficient Select 0 Reads and Writes of ADCOCCF will access ADCO Calibration Coefficients 1 Reads and Writes of ADCOCCF will access ADC1 Calibration Coefficients Bits 5 0 CPTR5 0 Calibration Coefficent Pointer Select which Calibration Coefficient location will be accessed when ADCOCCF is read or written Figure 5 23 ADCOCCF ADC Calibration Coefficient Register R W R W R W R W R W R W R W R W Reset Value Variable Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address SFR Page F Bits 7 0 Calibration Coefficients at the location specified in ADCOCPT See Table 5 19 68 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 5 5 ADCO Programmable Window Detector The ADCO Programmable Window Detector continuously compares the ADCO output to user programmed limits and notifies the system when an out of bound condition is detected This is esp
40. TOE SMBus Timeout Enable Bit 0 No timeout when SCL is low 1 Timeout when SCL low time exceeds limit specified by Timer 4 if enabled e Rev 1 2 243 SILICON LABS C8051F060 1 2 3 4 5 6 7 20 4 2 Clock Rate Register Figure 20 9 SMBOCR 5 0 Clock Rate Register R W R W Reset Value 00000000 Bit4 Bito SFR Address 0xCF SFR Page 0 SMBOCR 7 0 SMBus0 Clock Rate Preset The SMBOCR Clock Rate register controls the frequency of the serial clock SCL in master mode The 8 bit word stored in the SMBOCR Register preloads a dedicated 8 bit timer The timer counts up and when it rolls over to 0x00 the SCL logic state toggles The SMBOCR setting should be bounded by the following equation where SMBOCR is the unsigned 8 bit value in register SMBOCR and SYSCLK is the system clock frequency in Hz SMBOCR lt 288 0 85 SYSCLK 1 125 10 The resulting SCL signal high and low times are given by the following equations Trow 256 SMBOCR SYSCLK Using the same value of SMBOCR from above the Bus Free Timeout period is given in the following equation 256 SMBOCR 1 Dp um SYSCLK 244 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 20 4 3 Data Register The SMBus0 Data register SMBODAT holds a byte of serial data to be transmitted or one that has just been received Software can read or write to this register while the SI flag is
41. 110 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 9 Voltage Reference 2 C8051F060 2 The voltage reference circuitry offers full flexibility in operating the ADC2 and DAC modules Two voltage reference input pins allow ADC2 and the two DACs to reference an external voltage reference or the on chip voltage reference output ADC2 may also reference the analog power supply voltage via the VREF multiplexer shown in Figure 9 1 The internal voltage reference circuit consists of a 1 2 V temperature stable bandgap voltage reference generator and a gain of two output buffer amplifier The internal reference may be routed via the VREF pin to external system components or to the voltage reference input pins shown in Figure 9 1 The maximum load seen by the VREF pin must be less than 200 uA to AGND Bypass capacitors of 0 1 uF and 4 7 uF are recommended from the VREF pin to AGND as shown in Figure 9 1 The Reference Control Register 2 REF2CN defined in Figure 9 2 enables disables the internal reference generator and selects the reference input for ADC2 The BIASE bit in REF2CN enables the on board refer ence generator while the REFBE bit enables the gain of two buffer amplifier which drives the VREF pin When disabled the supply current drawn by the bandgap and buffer amplifier falls to less than 1 pA typi cal and the output of the buffer amplifier enters a high impedance state If the internal bandgap is used as the reference voltage g
42. 187 Figure 17 1 EMIOCN External Memory Interface 189 Figure 17 2 EMIOCF External Memory Configuration 189 Figure 17 3 Multiplexed Configuration 190 Figure 17 4 Non multiplexed Configuration 191 Figure 17 5 EMIF Operating 192 Figure 17 6 EMIOTC External Memory Timing Control 194 Figure 17 7 Non multiplexed 16 bit MOVX 196 Figure 17 8 Non multiplexed 8 bit MOVX without Bank Select Timing 197 Figure 17 9 Non multiplexed 8 bit MOVX with Bank Select Timing 198 Figure 17 10 Multiplexed 16 bit MOVX Timing 199 Figure 17 11 Multiplexed 8 bit MOVX without Bank Select Timing 200 Figure 17 12 Multiplexed 8 bit MOVX with Bank Select Timing 201 18 Port Input Output1 203 Figure 18 1 Port Cell Block 203 Figure 18 2 Port Functional Block 204 Figure 18 3 Priority Crossbar Decode
43. 3 NSSMD 1 0 1x 4 Wire Master Mode SPIO operates in 4 wire mode and NSS is enabled as an output The setting of NSSMDO determines what logic level the NSS pin will output This configuration should only be used when operating SPIO as a master device See Figure 21 2 Figure 21 3 and Figure 21 4 for typical connection diagrams of the various operational modes Note that the setting of NSSMD bits affects the pinout of the device When in 3 wire master or 3 wire slave mode the NSS pin will not be mapped by the crossbar In all other modes the NSS signal will be mapped to a pin on the device See Section 18 Port Input Output on page 203 for general purpose port I O and crossbar information 252 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 21 2 SPIO Master Mode Operation A SPI master device initiates all data transfers on a SPI bus SPIO is placed in master mode by setting the Master Enable flag MSTEN SPIOCN 6 Writing a byte of data to the SPIO data register SPIODAT when in master mode writes to the transmit buffer If the SPI shift register is empty the byte in the transmit buffer is moved to the shift register and a data transfer begins The SPIO master immediately shifts out the data serially on the MOSI line while providing the serial clock on SCK The SPIF SPIOCN 7 flag is set to logic 1 at the end of the transfer If interrupts are enabled an interrupt request is generated when the SPIF flag is set While the S
44. 65 Figure 5 18 ADC1 Data Word 65 Figure 5 19 Calibration Coefficient 66 Figure 5 20 Offset and Gain Register 67 Figure 5 21 Offset and Gain Calibration Block 67 Figure 5 22 ADCOCPT ADC Calibration Pointer 68 Figure 5 23 ADCOCCF ADC Calibration Coefficient Register 68 Figure 5 24 ADCOGTH ADCO Greater Than Data High Byte Register 69 Figure 5 25 ADCOGTL ADCO Greater Than Data Low Byte Register 69 Figure 5 26 ADCOLTH ADCO Less Than Data High Byte Register 70 Figure 5 27 ADCOLTL ADCO Less Than Data Low Byte Register 70 Figure 5 28 16 Bit ADCO Window Interrupt Example Single Ended Data 71 Figure 5 29 16 Bit ADCO Window Interrupt Example Differential Data 72 6 Direct Memory Access Interface DMA 0 J 75 Figure 6 1 Block 75 Figure 6 2 Mode 0 0 77 Figure 6 3 Mode 1 Operation susce onto hee nd
45. Address SFR Address Ox8F SFR Page 0 Bits 7 3 UNUSED Read 00000b Write don t care Bit 2 SFLE Scratchpad Flash Memory Access Enable When this bit is set Flash MOVC reads and writes from user software are directed to the 128 byte Scratchpad Flash sector When SFLE is set to logic 1 Flash accesses out of the address range 0x00 0x7F should not be attempted Reads Writes out of this range will yield undefined results 0 Flash access from user software directed to the Program Data Flash sector 1 Flash access from user software directed to the Scratchpad sector Bit 1 PSEE Program Store Erase Enable Setting this bit allows an entire page of the Flash program memory to be erased provided the PSWE bit is also set After setting this bit a write to Flash memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction The value of the data byte written does not matter Note The Flash page con taining the Read Lock Byte and Write Erase Lock Byte cannot be erased by software 0 Flash program memory erasure disabled 1 Flash program memory erasure enabled Bit 0 PSWE Program Store Write Enable Setting this bit allows writing a byte of data to the Flash program memory using the MOVX write instruction The location must be erased prior to writing data 0 Write to Flash program memory disabled MOVX write operations target External RAM 1 Write to Flash program memory enabl
46. Each interrupt source can be individually programmed to one of two priority levels low or high A low prior ity interrupt service routine can be preempted by a high priority interrupt A high priority interrupt cannot be preempted Each interrupt has an associated interrupt priority bit in an SFR IP EIP2 used to configure its priority level Low priority is the default If two interrupts are recognized simultaneously the interrupt with the higher priority is serviced first If both interrupts have the same priority level a fixed priority order is used to arbitrate given in Table 13 4 13 3 4 Interrupt Latency Interrupt response time depends on the state of the CPU when the interrupt occurs Pending interrupts are sampled and priority decoded each system clock cycle Therefore the fastest possible response time is 5 system clock cycles 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR If an interrupt is pending when a RETI is executed a single instruction is executed before an LCALL is made to service the pending interrupt Therefore the maximum response time for an interrupt when no other interrupt is currently being serviced or the new interrupt is of greater priority occurs when the CPU is performing an RETI instruction followed by a DIV as the next instruction In this case the response time is 18 system clock cycles 1 clock cycle to detect the interrupt 5 clock cycles to execute the RETI 8 cl
47. Eee CPnMD1 CPnMDO Rev 1 2 117 SILICON LABS C8051F060 1 2 3 4 5 6 7 complete electrical specifications for the Comparator are given in Table 12 1 The Comparator response time may be configured in software using the CPnMD1 0 bits in register CPT nMD see Figure 12 4 Selecting a longer response time reduces the amount of power consumed by the comparator See Table 12 1 for complete timing and current consumption specifications Figure 12 2 Comparator Hysteresis Plot OUT CIRCUIT CONFIGURATION Positive Hysteresis Voltage Programmed with CPnHYP Bits VIN INPUTS Negative Hysteresis Voltage Programmed by CPnHYN Bits VIN VOH OUTPUT VOL Negative Hysteresis L Maximum Disabled Negative Hysteresis Positive Hysteresis Maximum Disabled Positive Hysteresis The hysteresis of the Comparator is software programmable via its Comparator Control register CPT nCN The user can program both the amount of hysteresis voltage referred to the input voltage and the positive and negative going symmetry of this hysteresis around the threshold voltage The Comparator hysteresis is programmed using Bits3 0 in the Comparator Control Register CPTnCN shown in Figure 12 3 The amount of negative hysteresis voltage is determined by the settings of the CPnHYN bits As shown in Figure 12 2 the negative hysteresis can be programmed to three different set tings or negative hyst
48. SDA SCL 20 1 Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents 1 The l2C bus and how to use it including specifications Philips Semiconductor 2 2 Specification Version 2 0 Philips Semiconductor 3 System Management Bus Specification Version 1 1 SBS Implementers Forum 20 2 SMBus Protocol Two types of data transfers are possible data transfers from a master transmitter to an addressed slave receiver WRITE and data transfers from an addressed slave transmitter to a master receiver READ The master device initiates both types of data transfers and provides the serial clock pulses on SCL Note multiple master devices on the same bus are supported If two or more masters attempt to initiate a data transfer simultaneously an arbitration scheme is employed with a single master always winning the arbitra tion Note that it is not necessary to specify one device as the master in a system any device who trans mits a START and a slave address becomes the master for that transfer A typical SMBus transaction consists of a START condition followed by an address byte Bits7 1 7 bit slave address R W direction bit one or more bytes of data and a STOP condition Each byte that is received by a master or slave must be acknowledged ACK with a low SDA during a high SCL see Figure 20 3 If the receiving device does not ACK the
49. SYSCLK 4 9600 EXTCLK 8 2400 SYSCLK 48 SYSCLK 48 EXTCLK 8 EXTCLK 8 EXTCLK 8 Don t TSCA1 SCAO and bit definitions can be found in Section 24 1 284 Rev 1 2 2 5 SILICON LABS C8051F060 1 2 3 4 5 6 7 230400 aud Rates Using an External Oscillator 2 SYSCLK 115200 SYSCLK 57600 SYSCLK 28800 SYSCLK 12 14400 SYSCLK 12 9600 SYSCLK 12 2400 SYSCLK 48 SYSCLK 48 115200 EXTCLK 8 57600 8 28800 EXTCLK 8 14400 EXTCLK 8 9600 230400 Dont tSCA1 SCAO and bit definitions can be found in Section 24 1 EXTCLK 8 Table 23 4 Timer Settings for Standard Baud Rates Using an External Oscillator SO O O O O OO O O O 115200 160 SYSCLK XX 57600 0 00 320 SYSCLK XX 28800 0 00 640 SYSCLK 4 01 14400 0 00 1280 SYSCLK 4 01 9600 0 00 1920 SYSCLK 12 00 2400 0 00 7680 SYSCLK 48 10 1200 230400 SYSCLK 48 115200 160 8 11 57600 0 00 320 8 11 28800 0 00 640 8 11 14400 0 00 1280 8 11 9600 Dont care TSCA1 SCAO bit definitions can be found in Section 24 1 EXTCLK 8 Ojocococ
50. WWW MSB MISO MOSI NSS Must Remain High Multi Master Mode 256 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 21 6 Slave Mode Data Clock Timing CKPHA 0 SCK CKPOL 0 CKPHA 0 SCK CKPOL 1 CKPHA 0 MOSI WWW ss WWW MISO me ms ma X ma ma m mo X NSS 4 Wire Mode Figure 21 7 Slave Mode Data Clock Timing 1 SCK i i i u CKPOL 0 CKPHA 1 L L L L L EN L Lo eet PT T L PT PTT CKPOL 1 1 f wes Y ses se 8c MISO MSB Bit 5 Bit 4 3 Bit 2 Bit 1 Bit 0 Bite Bita Jj bri NSS 4 Wire Mode Rev 1 2 257 SILICON LABS C8051F060 1 2 3 4 5 6 7 21 6 SPI Special Function Registers SPIO is accessed and controlled through four special function registers in the system controller SPIOCN Control Register SPIODAT Data Register SPIOCFG Configuration Register and SPIOCKR Clock Rate Register The four special function registers related to the operation of the SPIO Bus are described in the following figures Figure 21 8 SPIOCFG SPIO Configuration Register R R W R W R W R R R R Reset Value SPIBSY MSTEN CKPH
51. 0 AD2LJST 1 VREF 1023 1024 Ox03FF OxFFCO VREF 512 1024 0 0200 0 8000 VREF 256 1024 0x0100 0x4000 0 0x0000 0x0000 When in Differential Mode conversion codes are represented as 10 bit signed 2 s complement numbers Inputs are measured from VREF to VREF 511 512 Example codes are shown below for both right justi fied and left justified data For right justified data the unused MSBs of ADC2H are a sign extension of the data word For left justified data the unused LSBs in the ADC2L register are set to 0 Input Voltage Right Justified ADC2H ADC2L Left Justified ADC2H ADC2L AD2LJST 0 AD2LJST 1 VREF 511 512 OxO1FF Ox7FCO VREF 256 512 0x0100 0x4000 0 0x0000 0x0000 VREF 256 512 OxFFOO 0 000 VREF OxFEO0 0x8000 Important Note About ADC2 Input Configuration Port 1 pins selected as ADC2 inputs should be con figured as analog inputs To configure a Port 1 pin for analog input set to 1 the corresponding bit in regis ter P1 MDIN Port 1 pins used as ADC2 inputs will be skipped by the crossbar for peripheral assignments See Section 18 Port Input Output on page 203 for more Port configuration details The Temperature Sensor transfer function is shown in Figure 7 2 on Page 89 The output voltage is a single ended input to ADC2 when the Temperature Sensor is selected by bits AMX2AD3 0 in register AMX2SL Typical values for the Slope and Of
52. 11 ALE high and ALE low pulse width 4 SYSCLK cycles Rev 1 2 189 SILICON LABS C8051F060 1 2 3 4 5 6 7 17 4 Multiplexed and Non multiplexed Selection The External Memory Interface is capable of acting in a Multiplexed mode or a Non multiplexed mode depending on the state of the EMD2 EMIOCF 4 bit 17 4 1 Multiplexed Configuration In Multiplexed mode the Data Bus and the lower 8 bits of the Address Bus share the same Port pins AD 7 0 In this mode an external latch 74HC373 or equivalent logic gate is used to hold the lower 8 bits of the RAM address The external latch is controlled by the ALE Address Latch Enable signal which is driven by the External Memory Interface logic An example of a Multiplexed Configuration is shown in Figure 17 3 In Multiplexed mode the external MOVX operation can be broken into two phases delineated by the state of the ALE signal During the first phase ALE is high and the lower 8 bits of the Address Bus are pre sented to AD 7 0 During this phase the address latch is configured such that the Q outputs reflect the states of the D inputs When ALE falls signaling the beginning of the second phase the address latch outputs remain fixed and are no longer dependent on the latch inputs Later in the second phase the Data Bus controls the state of the AD 7 0 port at the time RD or WR is asserted See Section 17 6 2 Multiplexed Mode on page 199 for more informati
53. 114 11 Voltage Reference 2 C8051F064 5 6 7 115 Figure 11 1 Voltage Reference Functional Block 115 Figure 11 2 REF2CN Reference Control Register 2 116 12 GOMPGLALONS UTI MTM 117 Figure 12 1 Comparator Functional Block Diagram 117 Figure 12 2 Comparator Hysteresis 118 Figure 12 3 CPTnCN Comparator 0 1 and 2 Control Register 120 Figure 12 4 CPTnMD Comparator Mode Selection Register 121 T3 GIP 51 Microcontroller siib noix acf xad n Cri pni RU RN ERI UD da na 123 Figure 13 1 GIP 51 Block DISOESIT seen E etes 124 Figure 13 2 Memory 130 Figure 13 3 SFR urere MP 133 Figure 13 4 SFR Page Stack While Using SFR Page 0x0F To Access Port 5 134 Figure 13 5 SFR Page Stack After ADC2 Window Comparator Interrupt Occurs 135 Figure 13 6 SFR Page Stack Upon PCA Interrupt Occurring During an ADC2 ISR 136 Figure 13 7 SFR Page Stack Upon Return From PCA Interrupt 137 Figure 13 8 SFR Page Stack Upon Return From ADC2 Window Interrupt 138 Figure 13 9 SFRPGCN SFR Page Control
54. A DPTR Move code byte relative DPTR to A MOVC A A PC Move code byte relative PC to A A Ri Move external data 8 bit address to A MOVX Ri A Move A to external data 8 bit address MOVX A DPTR Move external data 16 bit address to A MOVX DPTR A Move A to external data 16 bit address NI N G5 NI N OI N O NI NI NI NI N N NI NIN NI N God Gd GO CO Gd IO NI OO NI IO NI NI NI N PUSH direct Push direct byte onto stack POP direct Pop direct byte from stack XCH A Rn Exchange Register with A XCH A direct Exchange direct byte with A A Exchange indirect RAM with A XCHD Ri Exchange low nibble of indirect RAM with A Boolean Manipulation CLR Clear Carry 1 1 CLR bit Clear direct bit 2 2 Set Carry 1 1 SETB bit Set direct bit 2 2 CPL C Complement Carry 1 1 CPL bit Complement direct bit 2 2 ANL C bit AND direct bit to Carry 2 2 SILICON LABS Rev 1 2 127 C8051F060 1 2 3 4 5 6 7 Table 13 1 CIP 51 Instruction Set Summary Continued Clock Mnemonic Description Bytes Cycles ANL bit AND complement of direct bit to Carry 2 2 ORL bit OR direct bit to carry 2 2 ORL bit OR com
55. Bits 3 0 AMX2AD3 0 AMX2 Address Bits 0000 1111b ADC input multiplexer channel selected per chart below AMX2AD3 0 Single Ended Measurement AMX2AD3 0 Differential Measurement AIN2 0 AIN2 0 AIN2 1 AINO1IC 0 AINO1IC 1 AIN2 1 AIN2 1 AIN2 0 AIN2 3 AIN2 2 AIN2 2 AIN23IC 0 AIN2 3 AIN2 2 AIN2 3 AIN2 4 AIN2 5 AIN23IC 1 AIN2 4 0 AIN2 4 AIN2 7 AIN2 6 1 AIN2 5 AIN2 5 AIN2 6 AIN2 6 AIN67IC 0 AIN2 7 AIN2 7 Temperature Sensor AIN67IC 1 Rev 1 2 93 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 7 7 ADC2CF ADC2 Configuration Register SFR Page 2 SFR Address R W R W R W R W R W R W R W R W Reset Value AD2SC4 AD2SC3 AD2SC2 AD2SC1 AD2SCO 11111000 Bit7 Bite Bit5 Bit4 Bit3 Bit2 Bit1 Bito Bits7 3 25 4 0 ADC2 SAR Conversion Clock Period Bits SAR Conversion clock is derived from system clock by the following equation where ADSC refers to the 5 bit value held in bits AD2SC4 AD2SC0 SAR Conversion clock requirements are given in Table 7 1 ADSC SISCLK CLK yap Bits2 0 UNUSED Read 000b Write don t care 94 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 7 8 ADC2H ADC2 Data Word MSB Register SFR Page 2 SFR Addr
56. DMAOCTH L e Rev 1 2 77 SILICON LABS C8051F060 1 2 3 4 5 6 7 6 5 Instruction Execution in Mode 1 When the DMA interface begins an operation cycle the DMA Instruction Status Register DMAOISW Figure 6 9 is loaded with the address contained within the DMA Instruction Boundary Register DMAOBND Figure 6 8 The instruction is fetched from the Instruction Buffer and the DMA Control Logic waits for data from the appropriate ADC s At the end of an instruction the Repeat Counter Registers DMAOCSH and DMAOCSL is decremented and the instruction will be repeated until the Repeat Counter reaches 0x0000 The Repeat Counter is then reset to the Repeat Counter Limit value Registers DMAOCTH and DMAOCTL and the DMA will increment DMAOISW to the next instruction address When the current DMA instruction is an End of Operation instruction the Instruction Status Register is reset to the Instruction Boundary Register If the Continuous Conversion bit bit 7 CCNV in the End of Operation instruction word is set to 1 the DMA will continue to execute instructions When CCNV is set to 0 the DMA will stop executing instructions at this point An example of Mode 1 operation is shown in Figure 6 3 Figure 6 3 DMA Mode 1 Operation XRAM DMAOCSH L 0x0000 INSTRUCTION 1 1 DMA0CSH L DMAOCTH 64 Bytes DMA0CSH L 0 0000 DMAOCSH L DMAOCTH L 0x01 DMAOBND 0x00 DMAOCSH L 0x0
57. Logic Debug HW AM 2 0 FLASH Timers 0 pa 873 RST Reset Memory 12 Drv 32 3 MONEN B VDD Monitor WDT OIM PUPPES P3 Latches P3 Drv 32k byte C8051F067 a 256 byte 0 1 External Oscillator xTAL2 X Circuit System Clock Trimmed Internal Oscillator 6 ver m CP1 lt ope AVDD AGND AV AGND VREFO VRGNDO adip External Data Memory Bus AINOG 16 Bit U EMIF AGND Control P5 Addr 15 8 DRV VRGND1 Interface Lii AIN1G J P7 VBGAP1 CNVSTR1 Figure 1 4 C8051F065 C8051F067 Block Diagram 24 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 1 1 CIP 51 Microcontroller Core 1 1 1 Fully 8051 Compatible The C8051F06x family of devices utilizes Silicon Labs proprietary CIP 51 microcontroller core The CIP 51 is fully compatible with the MCS 51 instruction set standard 803x 805x assemblers and compilers can be used to develop software The core has all the peripherals included with a standard 8052 including five 16 bit counter timers two full duplex UARTs 256 bytes of internal RAM 128 byte Special Function Register SFR address space and bit addressable I O Ports 1 1 2 Improved Throughput The CIP 51 employs a pipelined architecture that greatly increases its instruction throughput over the stan dard 8051 architecture In a standard 8051 all instructions except for MUL a
58. 0 3 x RST Input Low Voltage VDD RST Input Leakage Current RST 0 0 V 50 VDD for RST Output Valid 1 0 V AV for RST Output Valid 1 0 V VDD POR Threshold 2 40 2 55 2 70 V Minimum RST Low Time to 10 Ws Generate a System Reset RST rising edge after VDD Reset Time Delay crosses Vnsr threshold 80 100 120 ms Missing Clock Detector Time Time from last system clock to 100 220 500 us out reset initiation 1 2 169 SILICON LABS C8051F060 1 2 3 4 5 6 7 170 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 15 Oscillators C8051F060 1 2 3 4 5 6 7 devices include a programmable internal oscillator and an external oscillator drive circuit The internal oscillator can be enabled disabled and calibrated using the OSCICN and OSCICL registers as shown in Figure 15 1 The system clock can be sourced by the external oscillator cir cuit the internal oscillator or a scaled version of the internal oscillator The internal oscillator s electrical specifications are given in Table 15 1 Figure 15 1 Oscillator Diagram OSCICL OSCICN CLKSEL BB 2 Option 3 _ XTAL EIE m 9 XTAL2 E Option 4 H gt
59. 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 The PnMDOUT registers control the output modes of the port pins regardless of whether the Crossbar has allocated the Port pin for a digital peripheral or not The exceptions to this rule are the Port pins connected to SDA SCL if UARTO is in Mode 0 and RX1 if UART1 is in Mode 0 are always configured as Open Drain outputs regardless of the settings of the associated bits in the registers 18 1 3 Configuring Port Pins as Digital Inputs A Port pin is configured as a digital input by setting its output mode to Open Drain and writing a logic 1 to the associated bit in the Port Data register For example P3 7 is configured as a digital input by setting PSMDOUT 7 to a logic 0 and P3 7 to a logic 1 If the Port pin has been assigned to a digital peripheral by the Crossbar and that pin functions as an input for example RXO the UARTO receive pin then the output drivers on that pin are automatically disabled 18 1 4 Weak Pull ups By default each Port pin has an internal weak pull up device enabled which provides a resistive connec tion about 100 between the and VDD The weak pull up devices can be globally disabled by writ ing a logic 1 to the Weak Pull up Disable bit WEAKPUD XBR2 7 The weak pull up is automatically deactivated on any pin that is driving a logic 0 that is an output pin will not contend with its own pull up device The weak pull u
60. 1 P0 3 VREF1 2 0 4 VRGND1 3 0 5 4 P0 6 AN1 5 0 7 AGND 6 P2 0 AV 7 P2 1 CNVSTR1 8 41 2 2 C8051F065 067 AV 10 DGND AGND 11 2 3 AINO 12 2 4 13 2 5 VRGNDO 14 2 6 VREFO 15 2 7 VBGAPO 16 1 0 9 1 amp 1 6 5 32222282282 11228 Figure 4 5 C8051F065 C8051F067 Pinout Diagram TQFP 64 1 2 49 SILICON LABS C8051F060 1 2 3 4 5 6 7 d MIN NOM MAX mm mm mm 1 20 1 0 05 0 15 2 0 95 1 05 E1 0 17 0 22 0 27 ia 40 Di 10 00 e 10 50 1200 2 _ E Et 1000 1 nw L 0 45 0 60 0 75 1 Figure 4 6 64 Package Drawing 50 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 5 16 Bit ADCs ADCO and ADC1 The ADC subsystem for the C8051F060 1 2 3 4 5 6 7 consists of two 1 Msps 16 bit successive approxi mation register ADCs with integrated track and hold a Programmable Window Detector and
61. 1 l Y vo 1 Enable 16 bit Comparator 55 PCA p Timebase P e Rev 1 2 307 SILICON LABS C8051F060 1 2 3 4 5 6 7 25 2 3 High Speed Output Mode In High Speed Output mode a module s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module s 16 bit capture compare register PCAOCPHn and PCAOCPLn Setting the TOGn MATn and bits in the PCAOCPMn register enables the High Speed Output mode Important Note About Capture Compare Registers When writing a 16 bit value to the Capture Compare registers the low byte should always be written first Writing to clears the ECOMn bit to 0 writing to PCAOCPHn sets to 1 Figure 25 6 PCA High Speed Output Mode Diagram Write to PCAOCPLn Reset PCAOCPMn Write to PCAOCPHn 1 n PCA 00 0x Interrupt PCAOCPLn PCAOCPHn E EIE EIE 51413 211 0 NU P d 16 bit Comparator TOGn Toggle 4 FUND ERN 0 gt ba oo Crossbar Port I O p gt a PCAOL 308 1 2
62. 17 Capture P0 n input from pin e g Bit Bit 11 PO 1 etc 19 21 23 Update PO0 n output to pin e g Bit 9 Bit 11 PO 1 etc 24 26 28 30 32 Capture P1 n output enable from MCU follows numbering scheme 34 36 38 Update 1 output enable to pin follows PO n numbering scheme 25 27 29 31 33 Capture P1 n input from pin follows PO n numbering scheme 35 37 39 Update P1 n output to pin follows PO n numbering scheme 40 42 44 46 48 Capture P2 n output enable from MCU follows numbering scheme 50 52 54 Update P2 n output enable to pin follows PO n numbering scheme 41 43 45 47 49 Capture P2 n input from pin follows PO n numbering scheme 51 53 55 Update P2 n output to pin follows PO n numbering scheme 56 58 60 62 64 Capture P3 n output enable from MCU follows numbering scheme 66 68 70 Update P3 n output enable to pin follows PO n numbering scheme 57 59 61 63 65 Capture P3 n input from pin follows numbering scheme 67 69 71 Update P3 n output to pin follows PO n numbering scheme 72 Capture Reset Enable from MCU Update Reset Enable to RST pin 73 Capture Reset Input from RST Update Not used 74 76 78 80 82 Capture 5 0 P5 1 P5 2 P5 3 P5 5 P5 7 respectively output enable from 84 Update 5 0 P5 1 5 2 5 3 5 5 5 7 respectively output enable pint 75 77 79 81
63. 20 4 1 Gontrol Register pe 241 20 4 2 Clock Rate 244 20 4 245 20 4 4 Address 0 0 245 246 21 Enhanced Serial Peripheral Interface SPIO 251 21 1 Signal Descriptions T Tm 252 21 1 1 Master Out Slave 252 21 1 2 Master In Slave Out 5 0 252 A EIE Ic eee Siti 252 21 1 4 Slave Select 55 252 21 2 SPIO Master Mode 253 21 3 SPIO Slave Mode 255 21 4 SPIO Interrupt Sources 255 6 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 21 5 Serial Clock onte trn neret nene iens 256 21 6 5 Special Function 258 265 22 1 Operational 266 22 1 1 Mode 0 Synchronous Mode 266 22 1 2 Mode 1 8 Bit UART Variable Baud
64. Bit 0 58 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 5 8 ADC1CF ADC1 Configuration Register R W R W R W R W R W R W R W R W Reset Value AD1SC3 AD1SC2 AD1SC1 AD1SCO AD1SCAL AD1GCAL AD1LCAL AD1OCAL 11110000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address SFR Page 1 Bits 7 4 AD1SC3 0 ADC1 SAR Conversion Clock Period Bits SAR Conversion clock is divided down from the system clock according to the AD1SC bits AD1SC3 0 The number of system clocks used for each SAR conversion clock is equal to AD1SC 1 Note the ADC1 SAR Conversion Clock should be less than or equal to 25 MHz See Table 5 1 for conversion timing details AD1SCAL System Calibration Enable 0 Internal ground and reference voltage are used for offset and gain calibration 1 External voltages can be used for offset and gain calibration AD1GCAL Gain Calibration Read 0 Gain Calibration is completed or not yet started 1 Gain Calibration is in progress Write 0 No Effect 1 Initiates a gain calibration if is idle AD1LCAL Linearity Calibration Read 0 Linearity Calibration is completed or not yet started 1 Linearity Calibration is in progress Write 0 No Effect 1 Initiates a linearity calibration if is idle AD1OCAL Offset Calibration Read 0 Offset Calibration is completed or not yet started 1 Offset Calibration is in p
65. Figure 24 2 TO Mode 2 Block Diagram ey Pre scaled Clock SYSCLK T0 A TFO gt Interrupt Reload Crossbar INTO VF e Rev 1 2 289 SILICON LABS C8051F060 1 2 3 4 5 6 7 24 1 4 Mode 3 Two 8 bit Counter Timers Timer 0 Only In Mode 3 Timer 0 is configured as two separate 8 bit counter timers held in 0 and THO The counter timer in TLO is controlled using the Timer 0 control status bits in TCON and TMOD TRO GATEO and TFO TLO can use either the system clock or an external input signal as its timebase The THO register is restricted to a timer function sourced by the system clock or prescaled clock THO is enabled using the Timer 1 run control bit TR1 THO sets the Timer 1 overflow flag TF1 on overflow and thus controls the Timer 1 interrupt Timer 1 is inactive in Mode 3 When Timer 0 is operating in Mode 3 Timer 1 can be operated in Modes 0 1 or 2 but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt However the Timer 1 overflow can be used to generate baud rates for the SMBus and or UART and or initiate ADC conversions While Timer 0 is operating in Mode 3 Timer 1 run control is handled through its mode set tings To run Timer 1
66. REFOCN Reference Control Register 0 R W R W R W R W R W R W R W R W Reset Value BIASEO REFBEO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0xD1 SFR Page 0 Bits7 2 RESERVED Read 000000b Write 000000b Bit1 BIASEO ADCO Bias Generator Enable Bit Must be 1 if using ADCO 0 ADCO Internal Bias Generator Off 1 ADCO Internal Bias Generator On REFBEO Internal Reference Buffer for ADCO Enable Bit 0 Internal Reference Buffer for ADCO Off External voltage reference can be used 1 Internal Reference Buffer for ADCO On Internal voltage reference is driven on the VREFO pin Figure 5 12 REF1CN Reference Control Register 1 R W R W R W R W R W R W R W R W Reset Value BIASE1 REFBE1 00000000 Bit7 Bite Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xD1 SFR Page 1 Bits7 2 RESERVED Read 000000b Write 000000b BIASE1 ADC1 Bias Generator Enable Bit Must be 1 if using ADC1 0 ADC1 Internal Bias Generator Off 1 ADC1 Internal Bias Generator On Bito REFBE1 Internal Reference Buffer for ADC1 Enable Bit 0 Internal Reference Buffer for ADC1 Off External voltage reference can be used 1 Internal Reference Buffer for ADC1 On Internal voltage reference is driven on the VREF1 pin 62 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 5 13 ADCOH ADCO
67. SFR Page 3 Figure 6 15 DMAOCTL Repeat Counter Limit LSB Register SFR Address OxF9 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bits 7 0 Repeat Counter Limit Low Order Bits SFR Page 3 Figure 6 16 DMAO Repeat Counter MSB Register SFR Address OxFC R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Bits 7 0 Repeat Counter High Order Bits SFR Page 3 Figure 6 17 DMAOCSL DMAO Repeat Counter LSB Register SFR Address OxFB R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Bits 7 0 Repeat Counter Low Order Bits SILICON LABS Rev 1 2 85 C8051F060 1 2 3 4 5 6 7 86 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 7 10 ADC ADC2 C8051F060 1 2 3 The ADC2 subsystem for the C8051F060 1 2 3 consists of an analog multiplexer referred to as AMUX2 and a 200 ksps 10 bit successive approximation register ADC with integrated track and hold and pro grammable window detector see block diagram in Figure 7 1 The AMUX2 data conversion modes window detector can all be configured from within software via the Special Function Registers shown in Figure 7 1 A
68. SILICON LABS C8051F060 1 2 3 4 5 6 7 25 2 4 Frequency Output Mode Frequency Output Mode produces a programmable frequency square wave on the module s associated CEXn pin The capture compare module high byte holds the number of PCA clocks to count before the out put is toggled The frequency of the square wave is then defined by Equation 25 1 Equation 25 1 Square Wave Frequency Output F sar 2 PCAOCPHn Note value of 0x00 in the register is equal to 256 for this equation Where is the frequency of the clock selected by the CPS2 0 bits in the PCA mode register PCAOMD The lower byte of the capture compare module is compared to the PCAO counter low byte on a match CEXn is toggled and the offset held in the high byte is added to the matched value in Fre quency Output Mode is enabled by setting the ECOMn TOGn and PWMn bits in the PCAOCPMn register Important Note About Capture Compare Registers When writing a 16 bit value to the Capture Compare registers the low byte should always be written first Writing to PCAOCPLn clears the ECOMn bit to 0 writing to PCAOCPHn sets ECOMnh to 1 Figure 25 7 PCA Frequency Output Mode PCAOCPLn MIO P P T G M IC 1 6 n n n n PCAOCPHn 8 bit Adder Enable PCA Timebase Rev 1 2 309 SILICON
69. Table 13 3 Special Function Registers SFRs are listed in alphabetical order All undefined SFR locations are reserved Register Address SFR Page Description Page No B OxFO All Pages B Register page 150 ACC 0 0 All Pages Accumulator page 150 ADCOCCF 0xBB F ADCO Calibration Coefficient page 68 ADCOCF 0 0 ADCO Configuration page 58 ADCOCN OxE8 0 ADCO Control page 60 ADCOCPT ADCO Calibration Pointer page 68 ADCOGTH 0xC5 0 ADCO Greater Than High page 69 ADCOGTL 0xC4 0 ADC0 Greater Than Low page 69 ADC0H OxBF 0 ADCO Data Word High page 63 ADCOL OxBE 0 ADCO Data Word Low page 63 ADCOLTH 0xC7 0 ADCO Less Than High page 70 ADCOLTL 0xC6 0 ADCO Less Than Low page 70 ADC1CF 0xBC 1 ADC1 Configuration page 59 ADC1CN OxE8 1 ADC1 Control page 61 ADC1H OxBF 1 ADC1 Data Word High page 65 ADC1L OxBE 1 ADC1 Data Word Low page 65 ADC2CF 0xBC 2 ADC2 Configuration page 945 ADC2CN 0xE8 2 ADC2 Control page 96 5 ADC2GTH 0 5 2 ADC2 Greater Than High page 975 ADC2GTL OxC4 2 ADC2 Greater Than Low page 975 ADC2H OxBF 2 ADC2 Data Word High page 95 ADC2L OxBE 2 ADC2 Data Word Low page 95 5 ADC2LTH 0 7 2 ADC2 Less Than High page 98 5 ADC2LTL 0xC6 2 ADC2 Less Than Low page 98 5 AMXOSL OxBB 0 ADCO Multiplexer Channel Select page 57 AMX2CF OxBA 2 ADC2 Analog Multiplexer Configuration page 94 5 AMX2S
70. This flexibility allows the start of conversion to be triggered by software events external HW signals or a periodic timer overflow signal The two ADCs can operate independently or be synchronized to perform conversions at the same time Conversion completions are indicated by sta tus bits and can generate interrupts The resulting 16 bit data words are latched into SFRs upon comple tion of a conversion A DMA interface is also provided which can gather conversions from the ADCs and directly store them to on chip or external RAM ADCO also contains Window Compare registers which can be configured to interrupt the controller when ADCO data is within or outside of a specified range ADCO can monitor a key voltage continuously in back ground mode and not interrupt the controller unless the converted data is within the specified window I Write to ADOBUSY I Timer 3 Overflow I CNVSTRO I Timer 2 Overflow Start Conversion REF AINO S ADCO Window Compare Logic AINOG lt DC 0 2 to 0 6 V Configuration and Control Data Registers Registers lt DC 0 2 to 0 6 V I Write to AD1BUSY I Timer 3 Overflow I CNVSTR1 I Timer 2 Overflow Write to ADOBUSY Start Conversion REF Figure 1 12 16 Bit ADC Block Diagram e Rev 1 2 33 SILICON LABS C8051F060 1 2 3 4 5 6 7 1 9 10 Analog to Digital Conv
71. device erase will erase all Flash pages including the page containing the security bytes and the security bytes themselves The Reserved Area cannot be read from written to or erased at any time Accessing Flash from firmware residing below the Flash Access Limit 1 2 3 4 5 The Read and Write Erase Lock bytes security bytes do not restrict Flash access from user firmware Any page of Flash except the page containing the security bytes may be read from written to or erased The page containing the security bytes cannot be erased Unlocking pages of Flash can only be performed via the JTAG interface The page containing the security bytes may be read from or written to Pages of Flash can be locked from JTAG access by writing to the security bytes The Reserved Area cannot be read from written to or erased at any time Accessing Flash from firmware residing at or above the Flash Access Limit 1 The Read and Write Erase Lock bytes security bytes do not restrict Flash access from user firmware Any page of Flash at or above the Flash Access Limit except the page containing the security bytes may be read from written to or erased Any page of Flash below the Flash Access Limit cannot be read from written to or erased Code branches to locations below the Flash Access Limit are permitted The page containing the security bytes cannot be erased Unlocking pages of Flash can only be performed via the
72. ing section in this datasheet for further information e Rev 1 2 207 SILICON LABS C8051F060 1 2 3 4 5 6 7 18 1 6 Crossbar Pin Assignment Example In this example Figure 18 4 we configure the Crossbar to allocate Port pins for UARTO the SMBus all 6 PCA modules INTO and INT1 12 pins total Additionally we configure P1 2 P1 3 and P1 4 for Analog Input mode so that the voltages at these pins can be measured by ADC2 The configuration steps are as follows XBRO XBR1 and XBR2 are set such that UARTOEN 1 SMBOEN 1 PCAOME 110 INTOE 1 and INT1E 1 Thus XBRO 0x3D XBR1 0x14 and XBR2 0x40 1 2 We configure the desired Port 1 pins to Analog Input mode by setting P1MDIN to 0 P1 4 P1 3 and P1 2 are Analog Inputs so their associated P1MDIN bits are set to logic 0 We enable the Crossbar by setting XBARE 1 XBR2 0x40 UARTO has the highest priority so is assigned to TXO and P0 1 is assigned to The SMBus is next in priority order so 2 is assigned to SDA and P0 3 is assigned to SCL PCAO is next in priority order so 4 through P1 1 are assigned to CEXO through CEX5 P1MDIN is set to which configures 1 2 P1 3 and P1 4 as Analog Inputs causing the Crossbar to skip these pins INTO is next in priority order so it is assigned to the next non skipped pin which is P1 5 INT1 is next in priority order so it is assigned to P1 6 We
73. n n F 6 n nin n 0000 0 PCAOCPLn pce I CEXn Crossbar X Port Ko a 8 bit Comparator Enable PCA Timebase Overflow 310 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 25 2 6 16 Bit Pulse Width Modulator Mode Each PCAO module may also be operated in 16 Bit PWM mode In this mode the 16 bit capture compare module defines the number of PCAO clocks for the low time of the PWM signal When the PCAO counter matches the module contents the output on is asserted high when the counter overflows CEXn is asserted low To output a varying duty cycle new value writes should be synchronized with PCAO CCFn match interrupts 16 Bit PWM Mode is enabled by setting the ECOMn PWMn and PWM16n bits in the PCAOCPMn register For a varying duty cycle CCFn should also be set to logic 1 to enable match inter rupts The duty cycle for 16 Bit PWM Mode is given by Equation 25 3 Important Note About Capture Compare Registers When writing a 16 bit value to the PCAO Capture Compare registers the low byte should always be written first Writing to clears the ECOMn bit to 0 writing to sets to 1 Equation 25 3 16 Bit PWM Duty Cycle 65536 PCAOCPn DutyCycle 65536 Figure 25 9 PCA 16 Bit PWM Mode PCAOCPMn PCAOCPLn
74. or twelve external clock divided by eight or transitions on an external input pin as its clock source Timer 2 and 3 can be used to start an ADC Data Conversion and Timers 2 3 and 4 can schedule DAC outputs Timers 1 2 3 or 4 may be used to generate baud rates for UART 0 Only Timer 1 can be used to generate baud rates for UART 1 The Counter Timer Select bit C Tn bit TMRnCN 1 configures the peripheral as a counter or timer Clear ing C Tn configures the Timer to be in a timer mode i e the selected timer clock source as the input for the timer When C Tn is set to 1 the timer is configured as a counter i e high to low transitions at the Tn input pin increment or decrement the counter timer register Refer to Section 18 1 Ports 0 through 3 and the Priority Crossbar Decoder on page 205 for information on selecting and configuring external I O pins for digital peripherals such as the Tn pin Timer 2 3 and 4 can use either SYSCLK SYSCLK divided by 2 SYSCLK divided by 12 an external clock divided by 8 or high to low transitions on the Tn input pin as its clock source when operating in Counter Timer with Capture mode Clearing the C Tn bit 1 selects the system clock external clock as the input for the timer The Timer Clock Select bits 0 and TnM1 in TMRnCF can be used to select the sys tem clock undivided system clock divided by two system clock divided by 12 or an external clock pro vided at the XT
75. this reset The WDT consists of a 21 bit timer running from the programmed system clock The timer measures the period between specific writes to its control register If this period exceeds the programmed limit a WDT reset is generated The WDT can be enabled and disabled as needed in software or can be permanently enabled if desired Watchdog features are controlled via the Watchdog Timer Control Register WDTCN shown in Figure 14 3 e Rev 1 2 165 SILICON LABS C8051F060 1 2 3 4 5 6 7 14 7 1 Enable Reset WDT The watchdog timer is both enabled and reset by writing OxA5 to the WDTON register The user s applica tion software should include periodic writes of OxA5 to WDTCN as needed to prevent a watchdog timer overflow The WDT is enabled and reset as a result of any system reset 14 7 2 Disable WDT Writing OxDE followed by OxAD to the WDTCN register disables the WDT The following code segment illustrates disabling the WDT CLR EA disable all interrupts MOV WDTCN 0DEh disable software watchdog timer MOV WDTCN 0ADh SETB EA re enable interrupts The writes of OXDE and OxAD must occur within 4 clock cycles of each other or the disable operation is ignored Interrupts should be disabled during this procedure to avoid delay between the two writes 14 7 3 Disable WDT Lockout Writing OXFF to WDTCN locks out the disable feature Once locked out the disable operation is ignored until
76. which forces a System reset when VDD is 2 7 V When tied low the internal VDD monitor is disabled Recom mended configuration is to connect directly to VDD VREF 4 61 4 61 A Out Bandgap Voltage Reference Output VREFO 21 15 21 15 Bandgap Voltage Reference Output for ADCO ADCO Voltage Reference Input e SILICON LABS Rev 1 2 39 C8051F060 1 2 3 4 5 6 7 Table 4 1 Pin Definitions Continued Pin Numbers Name 060 F061 064 F065 Type Description F062 F063 F066 F067 VRGNDO 20 14 20 14 ADCO Voltage Reference Ground This pin should be grounded if using the ADC VBGAPO 22 16 22 16 AOut Bandgap Bypass Pin VREF1 6 2 6 2 I O Voltage Reference Output for ADC1 ADC1 Voltage Reference Input VRGND 1 7 3 7 3 ADC1 Voltage Reference Ground This pin should be grounded if using the ADC VBGAP1 5 1 5 1 A Out ADC1 Bandgap Bypass Pin VREF2 2 ADC2 Voltage Reference Input 62 ADC2 DACO DAC1 Voltage Reference Input VREFD 3 DACO and DAC1 Voltage Reference Input AINO 18 12 18 12 ADCO Signal Input See ADCO Specification for complete description AINOG 19 13 19 13 ADCO DC Bias Input ADCO Specification for complete description AIN1 9 5 9 5 ADC1 Signal Input See ADC1 Specification for complete description AIN1G 8 4 8 4 ADC1 DC Bias Input See A
77. wired OR VDD Monitor reset enable wired OR Reset enable SEDE ComparatorO T Ak O4 reset enable Missing WDT Funnel Clock Detector one shot p EN EN PRE 2 o 88 58 Internal 215 z Z Clock Generator Software Reset gt 51 xrAL2 4 vas Microcontroller Core System Reset Extended Interrupt Handler e Rev 1 2 163 SILICON LABS C8051F060 1 2 3 4 5 6 7 14 1 Power on Reset The C8051 F060 1 2 3 4 5 6 7 family incorporates a power supply monitor that holds the MCU in the reset state until VDD rises above the level during power up See Figure 14 2 for timing diagram and refer to Table 14 1 for the Electrical Characteristics of the power supply monitor circuit The RST pin is asserted low until the end of the 100 ms VDD Monitor timeout in order to allow the VDD supply to stabilize The VDD Monitor reset is enabled and disabled using the external VDD monitor enable pin MONEN On exit from a power on reset the PORSF flag RSTSRC 1 is set by hardware to logic 1 All of the other reset flags in the RSTSRC Register are indeterminate PORSF is cleared by all other resets Since all resets cause program execution to begin at the same
78. 0 Logic Low Output 1 Logic High Output open if corresponding PAMDOUT n bit 0 Read Regardless XBR2 and XBR3 Register settings 0 P2 n pin is logic low 1 P2 n pin is logic high 216 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 18 15 P2MDIN Port2 Input Mode Register R W R W R W R W R W R W R W R W Reset Value 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xAE SFR Page F Bits7 0 P2MDIN 7 0 Port 2 Input Mode Bits 0 Port Pin is configured in Analog Input mode The digital input path is disabled a read from the Port bit will always return 0 The weak pull up on the pin is disabled 1 Port Pin is configured in Digital Input mode A read from the Port bit will return the logic level at the Pin The state of the weak pull up is determined by the WEAKPUD bit XBR2 7 see Figure 18 7 Figure 18 16 P2MDOUT Port2 Output Mode Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bite Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xA6 SFR Page F Bits7 0 P2MDOUT 7 0 Port2 Output Mode Bits 0 Port Pin output mode is configured as Open Drain 1 Port Pin output mode is configured as Push Pull Note SDA SCL and when UARTO is in Mode 0 and RX1 when is in Mode 0 are always configured as Open Drain when they appear on Port pins Rev
79. 0xFFFF 1 72 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 5 2 16 Bit ADCO and ADC1 Electrical Characteristics VDD 3 0 V AV 3 0 V AVDD 3 0 V VREF 2 50 V REFBE 0 40 to 85 C unless otherwise specified Parameter Conditions Min Typ Max DC Accuracy Resolution 16 bits Integral Nonlinearity Single Ended 20 75 2 LSB C8051 F060 1 4 5 6 7 Differential 0 5 1 Integral Nonlinearity Single Ended 21 5 4 LSB C8051 F062 3 Differential 1 2 Differential Nonlinearity Guaranteed Monotonic 0 5 LSB Offset Error 0 1 Full Scale Error 0 008 5 Gain Temperature Coefficient 0 5 Dynamic Performance Sampling Rate 1 Msps AVDD 3 3V Signal to Noise Plus Distortion Fin 10 kHz Single Ended 86 dB Fin 100 kHz Single Ended 84 dB Fin 10 kHz Differential 89 dB Fin 100 kHz Differential 88 dB Total Harmonic Distortion Fin 10 kHz Single Ended 96 dB Fin 100 kHz Single Ended 84 dB Fin 10 kHz Differential 103 dB Fin 100 kHz Differential 93 dB Spurious Free Dynamic Range Fin 10 kHz Single Ended 97 dB Fin 100 kHz Single Ended 88 dB Fin 10 kHz Differential 104 dB Fin 100 kHz Differential 99 dB CMRR Fin 10 kHz 86 dB Channel Isolation 100 dB Timing SAR Clock Frequency 25 MHz Conversion Time in SAR 18 clocks Cloc
80. 1 if a new data byte is latched into the receive buffer before software has read the previous byte Note that the RXOVO bit is also used as the SM10 bit when written by user software The Frame Error bit FEO in register SSTAO reads 1 if an invalid low STOP bit is detected Note that the FEO bit is also used as the 5 00 bit when written by user software RXOVO and FEO bits do not generate interrupts 272 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 22 2 Oscillator Frequencies for Standard Baud Rates Oscillator frequency Divide Fac Timer 1 Reload Timer 2 3 or Resulting Baud Rate Hz MHz tor Value 4 Reload Value 24 0 208 OxF3 OxFFF3 115200 115384 22 1184 192 OxF4 OxFFF4 115200 18 432 160 OxF6 OxFFF6 115200 11 0592 96 OxFA OxFFFA 115200 3 6864 32 OxFE OxFFFE 115200 1 8432 16 OxFF OxFFFF 115200 24 0 832 0xCC OxFFCC 28800 28846 22 1184 768 OxDO OxFFDO 28800 18 432 640 OxD8 OxFFD8 28800 11 0592 348 OxE8 OxFFE8 28800 3 6864 128 OxF8 OxFFF8 28800 1 8432 64 OxFC OxFFFC 28800 24 0 2496 0x64 OxFF64 9600 9615 22 1184 2304 0x70 OxFF70 9600 18 432 1920 0x88 OxFF88 9600 11 0592 1152 0xB8 OxFFB8 9600 3 6864 384 OxE8 OxFFE8 9600 1 8432 192 OxF4 OxFFF4 9600 Assumes SMODO 1 and T1M 1 Numbers in parenthesis show the actual baud rate Rev 1 2 273 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 22
81. 1 Frame Error has been detected Bit6 RXOVO Receive Overrun Flag This flag indicates new data has been latched into the receive buffer before software has read the previous byte 0 Receive overrun has not been detected 1 Receive Overrun has been detected Bit5 TXCOLO Transmit Collision Flag t This flag indicates user software has written to the SBUFO register while a transmission is in progress 0 Transmission Collision has not been detected 1 Transmission Collision has been detected Bit4 SMODO UARTO Baud Rate Doubler Enable This bit enables disables the divide by two function of the UARTO baud rate logic for config urations described in the UARTO section 0 UARTO baud rate divide by two enabled 1 UARTO baud rate divide by two disabled Bits3 2 UARTO Transmit Baud Rate Clock Selection Bits SOTCLK1 SOTCLKO Serial Transmit Baud Rate Clock Source 0 0 Timer 1 generates UARTO TX Baud Rate 0 1 Timer 2 Overflow generates UARTO TX baud rate 1 0 Timer 3 Overflow generates UARTO TX baud rate 1 1 Timer 4 Overflow generates UARTO TX baud rate Bits1 0 UARTO Receive Baud Rate Clock Selection Bits Serial Receive Baud Rate Clock Source Timer 1 generates UARTO RX Baud Rate 0 1 Timer 2 Overflow generates UARTO RX baud rate 1 0 Timer 3 Overflow generates UARTO RX baud rate 1 1 Timer 4 Overflow generates UARTO RX baud rate SORCLK1 SORCLKO 0 0 t Note FEO and TXCOLO are flags only and no i
82. 1 and the received address matches the UARTO address as described in Section 22 2 If the above conditions are satisfied the eight bits of data are stored in SBUFO the ninth bit is stored in RB80 and the RIO flag is set If these conditions are not met SBUFO and RB80 will not be loaded and the RIO flag will not be set An interrupt will occur if enabled when either TIO or RIO are set The baud rate in Mode 2 is either SYSCLK 32 or SYSCLK 64 according to the value of the SMODO bit in register SSTAO Equation 22 5 Mode 2 Baud Rate SMODO y 5 YSCL B R 2 audRate 6A Figure 22 5 Modes 2 and 3 Timing Diagram MARK START er 9 p X ps os y y z y oe STOP BIT SPACE BITTIMES I A 4 4 4 4 4 4 4 4 4 4 BITSAMPLING Rev 1 2 269 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 22 6 UAHTO Modes 1 2 and 3 Interconnect Diagram C8051Fxxx TX TX gt lt C8051Fxxx RX RX 22 1 4 Mode 3 9 Bit UART Variable Baud Rate Mode 3 uses the Mode 2 transmission protocol with the Mode 1 baud rate generation Mode 3 operation transmits 11 bits a start bit 8 data bits LSB first a programmable ninth data bit and a stop bit The baud rate is derived from Timer 1 or Timer 2 3 or 4 overflows as defined by Equation 22 1 and Equation 22 3 Multiprocessor communications and hardware address recognition a
83. 16 shows an exam ple using left justified data with the same comparison values Figure 7 15 ADC Window Compare Example Right Justified Single Ended Data ADC2H ADC2L ADC2H ADC2L Input Voltage Input Voltage P1 x AGND P1 x AGND VREF x 1023 1024 OxO3FF AD2WINT not affected AD2WINT 1 0x0081 VREFx 128 1024 lt ADC2LTH ADC2LTL 0x0080 4 ADC2GTH ADC2GTL ia M 0 007 7 AD2WINT 1 i 0 0041 VREF 64 1024 0x0040 4 ADC2GTH ADC2GTL VREF x 64 1024 0x0040 4 ADC2LTH ADC2LTL 0x003F AD2WINT AD2WINT 1 not affected 0 0x0000 Figure 7 16 ADC Window Compare Example Left Justified Single Ended Data ADC2H ADC2L ADC2H ADC2L Input Voltage Input Voltage P1 x AGND VREF x 1023 1024 ASIE AD2WINT 1 not affected 0x2040 VREFx 128 1024 0 2000 ADC2LTH ADG2LTL 0 2000 ADC2GTH ADC2GTL 27277777775 OdFCO AD2WINT 1 aoa ee 0 1040 VREF x 64 1024 0 1000 lt ADC2GTH ADC2GTL VREF x 64 1024 0 1000 ADC2LTH ADC2LTL OxOFCO AD2WINT AD2WINT 1 not affected 0 0 0000 Rev 1 2 99 SILICON LABS C8051F060 1 2 3 4 5 6 7 7 3 2 Window Detector In Differential Mode Figure 7 17 shows two example window comparisons for right justified differen
84. 22 218 Figure 18 18 PSMDOUT Port3 Output Mode 218 Figure 19 19 P4 Porta Data Register a 221 Figure 18 20 PAMDOUT Port4 Output Mode 221 Figure 18 21 P5 Port5 Data Register a 222 Figure 18 22 PSMDOUT Port5 Output Mode Register 222 Figure 18 23 P6 Port6 Data 2 223 Figure 18 24 PeMDOUT Port6 Output Mode Register 223 Figure 18 25 P7 Port7 Data 044 42221 224 Figure 18 26 P7MDOUT Port7 Output Mode 224 19 Controller Area Network 8051 060 1 2 3 225 Figure 19 1 CAN Controller 226 Figure 19 2 Typical CAN Bus 226 Figure 19 3 CANODATH CAN Data Access Register High Byte 231 Figure 19 4 CANODATL CAN Data Access Register Low Byte 231 Figure 19 5 CANOADR CAN Address Index Register 2 232 Figure 19 6 CANOCN CAN Control
85. 3 0V Supply MA 15 2 External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal ceramic resonator capacitor or RC network A CMOS clock may also provide a clock input For a crystal or ceramic resonator configuration the crystal resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 15 1 In RC capacitor or CMOS clock configuration the clock source should be wired to the XTAL2 and or XTAL1 pin s as shown in Option 2 3 or 4 of Figure 15 1 The type of external oscillator must be selected in the OSCXCN register and the frequency control bits XFCN must be selected appropriately see Figure 15 5 15 3 System Clock Selection The CLKSL bit in register CLKSEL selects which oscillator generates the system clock CLKSL must be set to 1 for the system clock to run from the external oscillator however the external oscillator may still clock peripherals timers PCA when the internal oscillator is selected as the system clock The system clock may be switched on the fly between the internal and external oscillator so long as the selected oscil lator is enabled and settled The internal oscillator requires little start up time and may be enabled and selected as the system clock in the same write to OSCICN External crystals and ceramic resonators typi cally require a start up time before they are settled and ready for use as the syste
86. 3 4 5 6 7 2 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table of Contents 1 System Wis adi d aA VE eu Maid C vi dada dun 19 1 1 CIP 51 Microcontroller Core 25 1 1 1 Fully 8051 Compatible 25 1 1 2 improved Thro ghput Uu 25 1 1 3 Additional 26 27 1 3 JTAG Debug and Boundary 28 1 4 Programmable Digital I O and 29 1 5 Programmable Counter Array 30 1 6 Controller Area 2442222 31 roS PONS s 32 1 8 16 Bit Analog to Digital 33 1 9 10 Bit Analog to Digital 34 1 10 12 bit Digital to Analog 35 36 2 Absolute Maximum Ratings J 37 3 Global DC Electrical Characteristics
87. 5 6 7 23 2 Operational Modes UART1 provides standard asynchronous full duplex communication The UART mode 8 bit or 9 bit is selected by the STMODE bit SCON1 7 Typical UART connection options are shown below Figure 23 3 UART Interconnect Diagram 7 RX C8051 F xxx TX C8051Fxxx RX 23 2 1 8 Bit UART 8 Bit UART mode uses a total of 10 bits per data byte one start bit eight data bits LSB first and one stop bit Data are transmitted LSB first from the TX1 pin and received at the RX1 pin On receive the eight data bits are stored in SBUF1 and the stop bit goes into RB81 SCON1 2 Data transmission begins when software writes a data byte to the SBUF1 register The Transmit Inter rupt Flag SCON1 1 is set at the end of the transmission the beginning of the stop bit time Data recep tion can begin any time after the REN1 Receive Enable bit SCON1 4 is set to logic 1 After the stop bit is received the data byte will be loaded into the SBUF1 receive register if the following conditions are met must be logic 0 and if MCE1 is logic 1 the stop bit must be logic 1 In the event of a receive data over run the first received 8 bits are latched into the SBUF1 receive register and the following overrun data bits are lost If these conditions are met the eight bits of data is stored in SBUF1 the stop bit is stored in RB81 and the flag is
88. 55 44 55 44 D Port 0 7 See Input Output section for complete description P1 0 AIN2 0 36 33 36 33 D Port 1 0 See Port Input Output section for complete description ADC2 Input Channel 0 C8051F060 1 2 3 Only P1 1 AIN2 1 35 32 35 32 D Port 1 1 See Port Input Output section for complete description ADC2 Input Channel 1 C8051F060 1 2 3 Only P1 2 AIN2 2 34 31 34 31 D I O Port 1 2 See Port Input Output section for complete description ADC2 Input Channel 2 C8051F060 1 2 3 Only 1 2 3 33 30 33 30 D Port 1 3 See Port Input Output section for complete description ADC2 Input Channel 3 C8051F060 1 2 3 Only P1 4 AIN2 4 32 29 32 29 D I O Port 1 4 See Port Input Output section for complete description ADC2 Input Channel 4 C8051F060 1 2 3 Only P1 5 AIN2 5 31 28 31 28 D Port 1 5 See Port Input Output section for complete description ADC2 Input Channel 5 C8051F060 1 2 3 Only P1 6 AIN2 6 30 25 30 25 D Port 1 6 See Port Input Output section for complete description ADC2 Input Channel 6 C8051F060 1 2 3 Only P1 7 AIN2 7 29 24 29 24 D Port 1 7 See Port Input Output section for complete description ADC2 Input Channel 7 C8051F060 1 2 3 Only P2 0 46 43 46 43 D Port 2 0 See Port Input Output section for complete description P2 1 4
89. 6 7 Table 17 1 AC Parameters for External Memory Interface Parameter Description Min Max Units System Clock Period 40 ns Tacs Address Control Setup Time 0 ns Tacw Address Control Pulse Width 1 Tsyscik 16 ns TACH Address Control Hold Time 0 3 Tsysc_k ns TALEH Address Latch Enable High Time 1 TsyscuKk 4 ns TALEL Address Latch Enable Low Time 1 TsyscuKk 4 ns Twps Write Data Setup Time 19 ns TwpH Write Data Hold Time 0 3 Tsysc_k ns TRps Read Data Setup Time 20 ns Read Data Hold Time 0 ns 202 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 18 Port Input Output The C8051F06x family of devices are fully integrated mixed signal System on a Chip MCUs with 59 digital pins C8051F060 2 4 6 or 24 digital pins C8051F061 3 5 7 organized as 8 bit Ports All ports are both bit and byte addressable through their corresponding Port Data registers All Port pins support con figurable Open Drain or Push Pull output modes and weak pull ups Additionally Port 0 pins are 5 V toler ant A block diagram of the Port I O cell is shown in Figure 18 1 Complete Electrical Specifications for the Port I O pins are given in Table 18 1 Figure 18 1 Port I O Cell Block Diagram WEAK PULLUP P PUSH PULL VD
90. 7 The internal voltage reference circuit consists of a 1 2 V temperature stable bandgap voltage reference generator and a gain of two output buffer amplifier The internal reference may be routed to the VREF pin as shown in Figure 11 1 The maximum load seen by the VREF pin must be less than 200 pA to AGND Bypass capacitors of 0 1 uF and 4 7 uF are recommended from the VREF pin to AGND as shown in Figure 11 1 The Reference Control Register 2 REF2CN defined in Figure 11 2 enables disables the internal refer ence generator The BIASE bit in REF2CN enables the on board reference generator while the REFBE bit enables the gain of two buffer amplifier which drives the VREF pin When disabled the supply current drawn by the bandgap and buffer amplifier falls to less than 1 uA typical and the output of the buffer amplifier enters a high impedance state If the internal bandgap is used as the reference voltage generator BIASE and REFBE must both be set to logic 1 If the internal reference is not used REFBE may be set to logic 0 The electrical specifications for the Voltage Reference are given in Table 11 1 Figure 11 1 Voltage Reference Functional Block Diagram BIASE 1 2V j Ly Band Gap Recommended Bypass Capacitors e Rev 1 2 115 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 11 2 REF2CN Reference Control Register 2 R W R W R W R W R W R W R W R W Reset
91. AD2LJST ADC2 Left Justify Select 0 Data ADC2H ADC2L registers are right justified 1 Data in ADC2H ADC2L registers are left justified 96 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 7 3 Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC2 output registers to user pro grammed limits and notifies the system when a desired condition is detected This is especially effective in an interrupt driven system saving code space and CPU bandwidth while delivering faster system response times The window detector interrupt flag AD2WINT in register ADC2CN can also be used in polled mode The ADC2 Greater Than ADC2GTH ADC2GTL and Less Than ADC2LTH ADC2LTL registers hold the comparison values The window detector flag can be programmed to indicate when mea sured data is inside or outside of the user programmed limits depending on the contents of the ADC2 Less Than and ADC2 Greater Than registers Figure 7 11 ADC2GTH ADC2 Greater Than Data High Byte Register SFR Page 2 SFR Address 0 5 R W R W R W R W R W R W Reset Value 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit1 Bits7 0 High byte of ADC2 Greater Than Data Word Figure 7 12 ADC2GTL ADC2 Greater Than Data Low Byte Register SFR Page 2 SFR Address 0xC4 R W R W R W R W R W Reset Value 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bits7 0 Low byte of ADC
92. AINn and the AINnG pin AINnG must be a DC signal between 0 2 and 0 6 V In most systems AINnG will be connected to AGND If not tied to AGND the AINnG signal can be used to negate a limited amount of fixed offset but it is recommended that the internal offset calibration features of the device be used for this purpose When operating in differential mode AINOG and AIN1G should be tied together AINn must remain above AINnG in both modes for accurate conversion results 52 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 5 2 Voltage Reference The voltage reference circuitries for ADCO and ADC1 allow for many different voltage reference configura tions Each ADC has the capability to use its own dedicated on chip voltage reference or an off chip refer ence circuit A block diagram of the reference circuitry for one ADC is shown in Figure 5 3 The internal voltage reference circuit for each ADC consists of an independent temperature stable 1 2 V bandgap voltage reference generator with an output buffer amplifier which multiplies the bandgap refer ence by 2 The maximum load seen by the VREFn VREFO or VREF1 pin must be less than 100 UA to AGND Bypass capacitors of 0 1 uF and 47 uF are recommended from the VREFn to VRGNDn The voltage reference circuitry for each ADC is controlled in the Reference Control Registers REFOCN defined in Figure 5 11 is the Reference Control Register for ADCO and REF1CN defined in Figu
93. Address Enable Bits in this register enable corresponding bits in register SADDRO to determine the UARTO slave address 0 Corresponding bit in SADDRO is a don t care 1 Corresponding bit in SADDRO is checked against a received address 276 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 23 UART1 UART1 is an asynchronous full duplex serial port offering modes 1 of the standard 8051 UART Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates details in Section 23 1 Enhanced Baud Rate Generation on page 278 Received data buffering allows UART1 to start reception of a second incoming data byte before software has finished reading the previous data byte UART1 has two associated SFRs Serial Control Register 1 SCON1 and Serial Data Buffer 1 SBUF1 The single SBUF1 location provides access to both transmit and receive registers Reading SBUF1 accesses the buffered Receive register writing SBUF1 accesses the Transmit register With UART1 interrupts enabled an interrupt is generated each time a transmit is completed is set in SCON1 a data byte has been received is set SCON1 UART1 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine They must be cleared manually by software allowing software to determine the cause of the UART1 interrupt transmit complete or receive complete Figu
94. Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0x83 SFR Page All Pages Bits7 0 DPH Data Pointer High The DPH register is the high byte of the 16 bit DPTR DPTR is used to access indirectly addressed XRAM and Flash memory 148 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 13 16 PSW Program Status Word R W R W R W R W R W R W R W R W Reset Value CY AC FO RS1 RSO OV F1 PARITY 00000000 Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito Addressable SFR Address SFR Page All Pages Bit7 CY Carry Flag This bit is set when the last arithmetic operation resulted in a carry addition or a borrow subtraction It is cleared to 0 by all other arithmetic operations Bit6 AC Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into addition or a bor row from subtraction the high order nibble It is cleared to 0 by all other arithmetic opera tions Bit5 FO User Flag 0 This is a bit addressable general purpose flag for use under software control Bits4 3 RS1 RSO Register Bank Select These bits select which register bank is used during register accesses RS1 RSO Register Bank Address 0 0 0 0x00 0x07 0 1 1 0x08 OxOF 1 0 2 0x10 0x17 1 1 3 0x18 Ox1F Bit2 OV Overflow Flag This bit is set to 1 under the following circumstances An ADD ADDC or SUBB instruction causes a sign change overflow AMUL instruction
95. CNVSTRO 15 P0 1 AV 16 P0 2 AGND 17 P0 3 18 0 4 19 P0 5 VRGNDO 20 6 VREFO 21 7 VBGAPO 22 P3 0 AGND 23 P3 1 AV 24 P3 2 NC 25 P3 3 QN ea eal fo e e e e e eee 116 T Z IO o uy FB 9 G G E E Zu D nan ann gt O Q n n n n n n n n x x Q a Figure 4 2 C8051F064 C8051F066 Pinout Diagram TQFP 100 46 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 H 1 MIN D1 11 20 1 0 05 0 15 2 0 95 1 00 1 05 b 0 17 0 22 0 27 D 16 00 E1 E Di 14 00 0 50 E 116 00 E1 31400 100 b L 0 45 0 60 0 75 PIN 1 i DESIGNATOR
96. Data Memory Interface and On Chip XRAM on page 187 for more information about the External Memory Inter face 220 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 18 19 P4 Port4 Data Register R W R W R W R W R W R W R W R W Reset Value P4 7 P4 6 P4 5 11111111 Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Ad ressabl SFR Address 0xC8 SFR Page F Bits7 5 P4 7 5 Port4 Output Latch Bits Write Output appears on pins 0 Logic Low Output 1 Logic High Output open if corresponding PAMDOUT n bit 2 0 See Figure 18 20 Read Returns states of I O pins 0 P4 n pin is logic low 1 4 pin is logic high Bits 4 0 Reserved Write to 11111 Note P4 7 WR P4 6 RD and P4 5 ALE be driven by the External Data Memory Interface See Section 17 External Data Memory Interface On Chip XRAM page 187 for more information Figure 18 20 PAMDOUT Port4 Output Mode Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0x9C SFR Page F Bits7 5 P4MDOUT 7 5 Port4 Output Mode Bits 0 Port Pin output mode is configured as Open Drain 1 Port Pin output mode is configured as Push Pull Bits 4 0 Reserved Write to 00000 e Rev 1 2 221 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figu
97. Input Output section for complete description P5 7 A15 81 81 D Port 5 7 See Port Input Output section for complete description 6 0 8 80 80 Port 6 0 See Port Input Output section for complete description Bit 8 External Memory Address Bus Multiplexed mode Bit 0 External Memory Address Bus Non multi plexed mode P6 1 A9m 79 79 Port 6 1 See Port Input Output section for complete A1 description 6 2 10 78 78 Port 6 2 See Port Input Output section for complete A2 description P6 3 A11m 77 77 6 3 Input Output section for complete A3 description P6 4 A12m 76 76 D Port 6 4 See Port Input Output section for complete 4 description P6 5 A13m 75 75 D Port 6 5 See Port Input Output section for complete A5 description 6 6 14 74 74 D Port 6 6 See Port Input Output section for complete description P6 7 A15m 73 73 D Port 6 7 See Port Input Output section for complete A7 description P7 0 ADOm 72 72 D Port 7 0 See Port Input Output section for complete DO description Bit 0 External Memory Address Data Bus Multi plexed mode Bit 0 External Memory Data Bus Non multiplexed mode P7 1 AD1m 71 71 D Port 7 1 See Port Input Output section for complete D1 description Rev 1 2 43 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 4 1 Pin Definitions Continued Pin Numbers
98. Interrupt Flag 0 No Comparator Falling Edge Interrupt has occurred since this flag was last cleared 1 Comparator Falling Edge Interrupt has occurred Must be cleared by software Bits3 2 CPnHYP1 0 Comparator Positive Hysteresis Control Bits 00 Positive Hysteresis Disabled 01 Positive Hysteresis 5 mV 10 Positive Hysteresis 10 mV 11 Positive Hysteresis 20 mV Bits1 0 CPnHYN1 0 Comparator Negative Hysteresis Control Bits 00 Negative Hysteresis Disabled 01 Negative Hysteresis 5 mV 10 Negative Hysteresis 10 mV 11 Negative Hysteresis 20 mV NOTE Upon enabling a comparator the output of the comparator is not immediately valid Before using a comparator as an interrupt or reset source software should wait for a minimum of the specified Power up time as specified in Table 12 1 Comparator Electrical Characteris tics on page 122 120 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 12 4 CPTnMD Comparator Mode Selection Register R W R W R W R W R R R W R W Reset Value CPnRIE CPnFIE CPnMD1 CPnMDO 00000010 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address CPTOMD 0x89 CPT1MD 0x89 CPT2MD 0x89 SFR Page CPTOMD page 1 CPT1MD page 2 CPT2MD page 3 Bits7 6 UNUSED Read 00b Write don t care Bit 5 CPnRIE Comparator Rising Edge Interrupt Enable Bit 0 Comparator rising edge
99. JTAG interface The page containing the security bytes may be read from or written to Pages of Flash can be locked from JTAG access by writing to the security bytes The Reserved Area cannot be read from written to or erased at any time e Rev 1 2 183 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 16 4 FLSCL Flash Memory Control R W R W R W R W R W R W R W R W Reset Value FOSE FRAE Reserved Reserved Reserved Reserved Reserved FLWE 10000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO Address SFR Address 0xB7 SFR Page 0 Bit 7 FOSE Flash One Shot Timer Enable This is the timer that turns off the sense amps after a Flash read 0 Flash One Shot Timer disabled 1 Flash One Shot Timer enabled recommended setting Bit 6 FRAE Flash Read Always Enable 0 Flash reads occur as necessary recommended setting 1 Flash reads occur every system clock cycle Bits 5 1 RESERVED Read 00000b Must Write 00000b Bit 0 FLWE Flash Write Erase Enable This bit must be set to allow Flash writes erases from user software 0 Flash writes erases disabled 1 Flash writes erases enabled 184 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 16 5 PSCTL Program Store Read Write Control R W R W R W R W R W R W R W R W Reset Value SFLE PSEE PSWE 00000000 Bit7 Bit6 5 Bit4 Bit3 Bit2 Bit1 Bito SFR
100. LABS C8051F060 1 2 3 4 5 6 7 25 2 5 8 Bit Pulse Width Modulator Mode Each module can be used independently to generate pulse width modulated PWM outputs on its associ ated CEXn pin The frequency of the output is dependent on the timebase for the PCAO counter timer The duty cycle of the PWM output signal is varied using the module s PCAOCPLn capture compare register When the value in the low byte of the PCAO counter timer PCAOL is equal to the value in PCAOCPLn the output on the CEXn pin will be high When the count value in PCAOL overflows the CEXn output will be low see Figure 25 8 Also when the counter timer low byte PCAOL overflows from OxFF to 0 00 PCAOCPLn is reloaded automatically with the value stored in the counter timer s high byte PCAOH with out software intervention Setting the ECOMn and PWMn bits the PCAOCPMn register enables 8 Bit Pulse Width Modulator mode The duty cycle for 8 Bit PWM Mode is given by Equation 25 2 Important Note About Capture Compare Registers When writing a 16 bit value to the Capture Compare registers the low byte should always be written first Writing to PCAOCPLn clears the ECOMn bit to 0 writing to PCAOCPHn sets ECOMnh to 1 Equation 25 2 8 Bit PWM Duty Cycle 256 PCAOCPHn D utyCycle 256 Figure 25 8 PCA 8 Bit PWM Mode Diagram PCAOCPHn PCAOCPMn 1 M P N n
101. PEN Toggle Logic m gt 0 x gt Tn OxFF OxFF i SYSCLK 12 1 Port Pin External Clock 0 8 XTAL1 nc te MA TMRnL TMRnH CERIS Tn _ Crossbar THn TRn 2 gt gt MEX Interrupt E Capture gt T gt gt RCAPnL RCAPnH i TnEX Crossbar 296 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 24 2 3 Auto Reload Mode In Auto Reload Mode the counter timer can be configured to count up or down and cause an interrupt flag to occur upon an overflow underflow event When counting up the counter timer will set its overflow under flow flag TFn and cause an interrupt if enabled upon overflow underflow and the values in the Reload Capture Registers RCAPnH and RCAPnL are loaded into the timer and the timer is restarted When the Timer External Enable Bit EXENn bit is set to 1 and the Decrement Enable Bit DCENn is 0 a falling edge 1 to 0 transition on the TnEX pin configured as an input in the digital crossbar will cause a timer reload in addition to timer overflows causing auto reloads When is set to 1 the state of the TnEX pin controls whether the counter timer counts up increments or down decrements and will not cause an auto reload or interrupt event See Section 24 2 1 for information concerning configuration o
102. PT3 Timer 3 Interrupt Priority Control This bit sets the priority of the Timer 3 interrupts 0 Timer 3 interrupt set to low priority level 1 Timer 3 interrupt set to high priority level e Rev 1 2 159 SILICON LABS C8051F060 1 2 3 4 5 6 7 13 4 Power Management Modes The CIP 51 core has two software programmable power management modes Idle and Stop Idle mode halts the CPU while leaving the external peripherals and internal clocks active In Stop mode the CPU is halted all interrupts and timers except the Missing Clock Detector are inactive and the internal oscillator is stopped Since clocks are running in Idle mode power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering Idle Stop mode consumes the least power Figure 13 25 describes the Power Control Register PCON used to control the CIP 51 s power management modes Although the CIP 51 has Idle and Stop modes built in as with any standard 8051 architecture power management of the entire MCU is better accomplished by enabling disabling individual peripherals as needed Each analog peripheral can be disabled when not in use and put into low power mode Digital peripherals such as timers or serial buses draw little power whenever they are not in use Turning off the oscillator saves even more power but requires a reset to restart the MCU 13 4 1 Idle Mode Setting the Idle Mode Sele
103. Port Latches Comparators 204 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 18 1 Ports 0 through 3 and the Priority Crossbar Decoder The Priority Crossbar Decoder or Crossbar allocates and assigns Port pins on Port 0 through Port 3 to the digital peripherals UARTs SMBus PCA Timers etc on the device using a priority order The Port pins are allocated in order starting with and continue through P3 7 on the C8051F060 2 4 6 or P2 7 on the C8051F061 3 5 7 if necessary The digital peripherals are assigned Port pins in a priority order which is listed in Figure 18 3 with UARTO having the highest priority and CNVSTR2 having the lowest pri ority 18 1 1 Crossbar Pin Assignment and Allocation The Crossbar assigns Port pins to a peripheral if the corresponding enable bits of the peripheral are set to a logic 1 in the Crossbar configuration registers XBRO XBR1 XBR2 and shown in Figure 18 5 Figure 18 6 Figure 18 7 and Figure 18 8 For example if the UARTOEN bit XBRO 2 is set to a logic 1 the and pins will be mapped to P0 0 and PO 1 respectively Because UARTO has the highest pri ority its pins will always be mapped to P0 0 and P0 1 when UARTOEN is set to a logic 1 If a digital periph Figure 18 3 Priority Crossbar Decode Table P1MDIN z OxFF P2MDIN z OxFF PNOO 1 2 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7T 0 1 2 3 4 5 6 7 U
104. REF x 4096 65536 0x1000 ADCOLTH ADCOLTL ADOWINT 1 Given AMXOSL 0x00 ADCOLTH ADCOLTL 0x1000 ADCOGTH ADCOGTL 0x2000 An ADCO End of Conversion will cause an ADCO Window Compare Interrupt ADOWINT 1 if the resulting ADCO Data Word is gt 0x2000 or lt 0x1000 e SILICON LABS Rev 1 2 71 C8051F060 1 2 3 4 5 6 7 Figure 5 29 16 Bit ADCO Window Interrupt Example Differential Data Input Voltage ADCO Data AINO AIN1 Word REF x 32767 32768 Ox7FFF ADOWINT not affected 0x1001 0x1000 ADOWINT 1 REF x 1 32768 ADCOGTH ADCOGTL OxFFFE ADOWINT not affected 0x8000 Given AMXOSL 0x40 ADCOLTH ADCOLTL 0x1000 ADCOGTH ADCOGTL OxFFFF An ADCO End of Conversion will cause an ADCO Window Compare Interrupt ADOWINT 1 if the resulting ADCO Data Word is lt 0x1000 and gt OxFFFF In two s complement math OxFFFF 1 Input Voltage AINO AIN1 REF x 32767 32768 ADCO Data Word ADOWINT 1 REF x 4096 32768 0x1000 ADCOGTH ADCOGTL OTET ADOWINT not affected 0x0000 REF x 1 32768 OxFFFF ADCOLTH ADCOLTL ADOWINT 1 Given AMXOSL 0x40 ADCOLTH ADCOLTL OxFFFF ADCOGTH ADCOGTL 0x1000 An ADCO End of Conversion will cause an ADCO Window Compare Interrupt ADOWINT 1 if the resulting ADCO Data Word is lt OxFFFF or gt 0x1000 In two s complement math
105. Rate Bit6 UNUSED Read 1b Write don t care Bit5 MCE1 Multiprocessor Communication Enable The function of this bit is dependent on the Serial Port 0 Operation Mode S1MODE 0 Checks for valid stop bit 0 Logic level of stop bit is ignored 1 will only be activated if stop bit is logic level 1 S1MODE 1 Multiprocessor Communications Enable 0 Logic level of ninth bit is ignored 1 is set and an interrupt is generated only when the ninth bit is logic 1 Bit4 REN1 Receive Enable This bit enables disables the UART receiver 0 UART1 reception disabled 1 UART1 reception enabled Bit3 TB81 Ninth Transmission Bit The logic level of this bit will be assigned to the ninth transmission bit in 9 bit UART Mode It is not used in 8 bit UART Mode Set or cleared by software as required Bit2 RB81 Ninth Receive Bit RB81 is assigned the value of the STOP bit in Mode 0 it is assigned the value of the 9th data bit in Mode 1 Bit1 Transmit Interrupt Flag Set by hardware when a byte of data has been transmitted by UART1 after the 8th bit in 8 bit UART Mode or at the beginning of the STOP bit in 9 bit UART Mode When the UART1 interrupt is enabled setting this bit causes the CPU to vector to the UART1 interrupt service routine This bit must be cleared manually by software Receive Interrupt Flag Set to 1 by hardware when a byte of data has been received by UART1 set at the STOP bit sampling
106. Scan Logic Debug HW MONEN M VDD Monitor 2 64k byte C8051F064 ov ov 29 EI K Reset P1 P2 2 Latches 32k byte C8051F066 XJ P3 7 XTALI External Oscillator xTAL2 Circuit System Clock Trimmed Internal Oscillator 256 byte i RAM VREF Q VREF P2 2 CP1 P2 4 4kbyte RAM 2 C 20 AVDD AGND AV AGND VRGNDO XI XD XIX External Data Memory Bus 7 m AINOG Bus Control PA Ctrl Latch P4 EMIF Control Address Bus J P5 PS Addr 15 8 DRV B 5 Latch Cri Laten Latch Interface EEE P7 Latch Pata Latch v 7 VBGAPO CNVSTRO lt lt lt DX o AGND VREF1 VRGND1 XD pQ EI X P6 M P6 0 P6 7 AIN1 x 7 AIN1G P7 Data Bus DX gt gt 52 P7 q VBGAP1 CNVSTR1 gt Figure 1 3 C8051F064 C8051F066 Block Diagram Rev 1 2 23 SILICON LABS C8051F060 1 2 3 4 5 6 7 VoD VDD Digital Power 0 DGND DEND Ll Analog Power SFR Bus 2 0o0o0020 P1 Drv x JTAG Boundary Scan
107. Timer Counter 0 Low page 294 TL1 0 8 0 Timer Counter 1 Low page 294 TMOD 0x89 0 Timer Counter Mode page 292 TMR2CF 0xC9 0 Timer Counter 2 Configuration page 300 TMR2CN 0xC8 0 Timer Counter 2 Control page 299 TMR2H OxCD 0 Timer Counter 2 High page 302 TMR2L 0xCG 0 Timer Counter 2 Low page 301 TMR3CF 0xC9 1 Timer Counter 3 Configuration page 300 TMR3CN 0xC8 1 Timer Counter 3 Control page 299 0xCD 1 Timer Counter 3 High page 302 0xCG 1 Timer Counter 3 Low page 301 TMR4CF 0xC9 2 Timer Counter 4 Configuration page 300 TMR4CN 0xC8 2 Timer Counter 4 Control page 299 TMR4H 0xCD 2 Timer Counter 4 High page 302 146 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 13 3 Special Function Registers Continued SFRs are listed in alphabetical order All undefined SFR locations are reserved Register Address SFR Page Description Page No TMR4L 0xCC 2 Timer Counter 4 Low page 301 WDTCN OxFF All Pages Watchdog Timer Control page 167 XBRO OxE1 F Port Crossbar Control 0 page 210 XBR1 OxE2 F Port I O Crossbar Control 1 page 211 XBR2 OxE3 F Port I O Crossbar Control 2 page 212 XBR3 OxE4 F Port I O Crossbar Control page 213 1 Refers to a register in the C8051F060 2 4 6 only Refers to a register in the C8051F060 2 only Refers to a register in the C8051F061 3 only 4 Refers to a register in the C8051F060 1 2 3 only 75 Refers to a register in the C8051F064 5 6 7 o
108. a DMA inter face see block diagrams in Figure 5 1 and Figure 5 2 The ADCs can be configured as two separate single ended ADCs or as a differential pair The Data Conversion Modes Window Detector and DMA interface are all configurable under software control via the Special Function Registers shown in Figure 5 1 and Figure 5 2 The voltage references used by ADCO and ADC1 are selected as described in Section 5 2 The ADCs and their respective track and hold circuitry can be independently enabled or disabled with the Special Function Registers Either ADC can be enabled by setting the ADnEN bit in the ADC s Control reg ister ADCnCN to logic 1 The ADCs are in low power shutdown when these bits are logic 0 AV ADCO Data Bus AINO gt AINOG x 00 AD0BUSY W DC 0 2 to 0 6 V Start Conversion 01 Timer Overflow SYSCLK 10 CNVSTRO gt gt 11 Timer 2 Overflow Si jas gt lt lt lt lt lt gt 5 m assis aaa Addad amp lt I lt lt lt I lt lt lt lt lt ADC0CF ADC0CN ADC1 Data Bus AIN1 lt x AD1BUSY W DC 0 2 to 0 6 V Timer 3 Overfl
109. an LSB for example 0 25 to settle within 1 4 LSB tis the required settling time in seconds is the sum of the ADC input resistance and any external source resistance nis the ADC resolution in bits 16 Differential Mode Single Ended Mode AINO or Ray 30 2 Ray 30 Q Csampre 80pF Camre CoampLe CsaupLE d Convere 80pF AIN1 Dx Ry 30 Q Figure 5 5 ADCO and ADC1 Equivalent Input Circuits 56 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 5 6 AMXOSL AMUX Configuration Register R W R W R W R W R W R W R W R W Reset Value DIFFSEL 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address OXBB SFR Page 0 Bit 7 RESERVED Write to Ob Bit 6 DIFFSEL Fully Differential Conversion Mode Select Bit 0 Operate In Single Ended Mode 1 Operate In Differential Mode Bit 5 0 RESERVED Write to 000000b NOTE For single ended mode the ADCO Data Word is stored in ADCOH and ADCOL while the ADC1 Data Word is stored ADC1H and ADC1L In differential mode the combined ADC Data Word is stored in ADCOH and ADCOL and is a 2 s complement number ADC1 s Data Word single ended is also stored in ADC1H and ADC1L e Rev 1 2 57 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 5 7 ADCOCF ADCO Confi
110. and MOSI routed to 3 Port pins Bito SMBOEN SMBus0 Bus Enable Bit 0 SMBusO unavailable at Port pins 1 SMBusO SDA and SCL routed to 2 Port pins 210 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 R W Figure 18 6 XBR1 Port Crossbar Register 1 R W R W R W R W R W R W R W SYSCKE T2EXE 2 TIE INTOE TOE CP1E Bit7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SYSCKE SYSCLK Output Enable Bit 0 SYSCLK unavailable at Port pin 1 SYSCLK routed to Port pin T2EXE T2EX Input Enable Bit 0 T2EX unavailable at Port pin 1 2 routed to Port pin 2 2 Input Enable Bit 0 T2 unavailable at Port pin 1 T2 routed to Port pin INT1E 1 Input Enable Bit 0 INT1 unavailable at Port pin 1 INT1 routed to Port pin T1E T1 Input Enable Bit 0 T1 unavailable at Port pin 1 T1 routed to Port pin INTOE INTO Input Enable Bit 0 INTO unavailable at Port pin 1 INT1 routed to Port pin TOE TO Input Enable Bit 0 TO unavailable at Port pin 1 T1 routed to Port pin CP1E CP1 Output Enable Bit 0 CP1 unavailable at Port pin 1 CP1 routed to Port pin SFR Address 0 2 SFR Page F Reset Value 00000000 e Rev 1 2 SILICON LABS 211 C8051F060 1 2 3 4 5 6 7 R W Figure 18 7 XBR2 Port Crossbar Regis
111. as short as possible and shielded with ground plane from any other traces which could introduce noise or interference Crystal loading capacitors should be referenced to AGND 15 5 External RC Example If an RC network is used as an external oscillator source for the MCU the circuit should be configured as shown in Figure 15 1 Option 2 The capacitor should be no greater than 100 pF however for very small capacitors the total capacitance may be dominated by parasitic capacitance in the PCB layout To deter mine the required External Oscillator Frequency Control value XFCN in the OSCXCN Register first select the RC network value to produce the desired frequency of oscillation If the frequency desired is 100 kHz let 246 and 50 pF f 1 23 10 RC 1 23 10 246 50 0 1 MHz 100 kHz Referring to the table in Figure 15 5 the required XFCN setting is 010 15 6 External Capacitor Example If a capacitor is used as an external oscillator for the MCU the circuit should be configured as shown in Figure 15 1 Option 3 The capacitor should be no greater than 100 pF however for very small capacitors the total capacitance may be dominated by parasitic capacitance in the PCB layout To determine the required External Oscillator Frequency Control value XFCN in the OSCXCN Register select the capaci tor to be used and find the frequency of oscillation from the equations below Assume VDD 3 0 V and C 50 pF f K
112. directly The lower 8 bits of the effective address A 7 0 are determined by the contents of RO or R1 16 bit MOVX operations use the contents of DPTR to determine the effective address A 15 0 The full 16 bits of the Address Bus A 15 0 are driven during the off chip transaction e Rev 1 2 193 SILICON LABS C8051F060 1 2 3 4 5 6 7 17 6 Timing The timing parameters of the External Memory Interface can be configured to enable connection to devices having different setup and hold time requirements The Address Setup time Address Hold time RD and WR strobe widths and in multiplexed mode the width of the ALE pulse are all programmable in units of SYSCLK periods through EMIOTC shown in Figure 17 6 EMIOCFT 1 0 The timing for an off chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing parameters defined by the EMIOTC register Assuming non multiplexed operation the minimum execution time for an off chip XRAM operation is 5 SYSCLK cycles 1 SYSCLK for RD or WR pulse 4 SYSCLKs For multiplexed operations the Address Latch Enable signal will require a minimum of 2 additional SYSCLK cycles Therefore the minimum execution time for an off chip XRAM operation in multiplexed mode is 7 SYSCLK cycles 2 for ALE 1 for RD or WR 4 The programmable setup and hold times default to the maximum delay settings after a reset Figure 17 6 EMIOTC External Memory Timing Control
113. e Rev 1 2 313 SILICON LABS C8051F060 1 2 3 4 5 6 7 R W Figure 25 12 PCAOCPMn PCAO Mode Registers R W R W R W R W R W R W R W Reset Value PWM16n ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn 00000000 Bit7 SFR Page Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito OxDA 1 0xDB 2 0xDC 0xDD 4 OxDE PCAOCPM5 SFR Address OxDE page 0 1 0 PCAOCPM2 page 0 0 page 0 page 0 16 16 bit Pulse Width Modulation Enable This bit selects 16 bit mode when Pulse Width Modulation mode is enabled PWMn 1 0 8 bit PWM selected 1 16 bit PWM selected ECOMn Comparator Function Enable This bit enables disables the comparator function for module n 0 Disabled 1 Enabled CAPPn Capture Positive Function Enable This bit enables disables the positive edge capture for module n 0 Disabled 1 Enabled CAPNn Capture Negative Function Enable This bit enables disables the negative edge capture for module n 0 Disabled 1 Enabled MATn Match Function Enable This bit enables disables the match function for module n When enabled matches of the PCAO counter with a module s capture compare register cause the CCFn bit in P
114. gt E T gt 09 RCAPnL RCAPnH SMBus Timer 4 Only e Rev 1 2 297 SILICON LABS C8051F060 1 2 3 4 5 6 7 24 2 4 Toggle Output Mode Timer 2 3 and 4 have the capability to toggle the state of their respective output port pins T2 T3 or T4 to produce a 5096 duty cycle waveform output The port pin state will change upon the overflow or under flow of the respective timer depending on whether the timer is counting up or down The toggle frequency is determined by the clock source of the timer and the values loaded into RCAPnH and RCAPnL When counting DOWN the auto reload value for the timer is OXFFFF and underflow will occur when the value in the timer matches the value stored in RCAPnH RCAPnL When counting UP the auto reload value for the timer is RCAPnH RCAPnL and overflow will occur when the value in the timer transitions from OxFFFF to the reload value To output a square wave the timer is placed in reload mode the Capture Reload Select Bit in TMRnCN and the Timer Counter Select Bit in TMRnCN are cleared to 0 The timer output is enabled by setting the Timer Output Enable Bit in TMRnCF to 1 The timer should be configured via the timer clock source and reload underflow values such that the timer overflow underflows at 1 2 the desired output frequency The port pin assigned by the crossbar as the timer s output pin should be configured as a digital output see Section
115. includes a Windows 95 later development environment a serial adapter for connecting to the JTAG port and a target application board with a C8051F060 MCU installed All of the necessary communication cables and a wall mount power supply are also supplied with the development kit Silicon Labs debug environment is a vastly supe rior configuration for developing and debugging embedded applications compared to standard MCU emu lators which use on board ICE Chips and target cables and require the MCU in the application board to be socketed Silicon Labs debug environment both increases ease of use and preserves the performance of the precision on chip analog peripherals Silicon Labs Integrated Development Environment gt WINDOWS 95 OR LATER MEE JTAG x4 VDD GND Adapter Figure 1 8 Development In System Debug Diagram 28 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 1 4 Programmable Digital and Crossbar Three standard 8051 Ports 0 1 and 2 are available on the MCUs The C8051F060 2 4 6 have 4 addi tional 8 bit ports 3 5 6 and 7 and a 3 bit port port 4 for a total of 59 general purpose Pins The Ports behave like the standard 8051 with a few enhancements Each port pin can be configured as either a push pull or open drain output Also the weak pull ups which are normally fixed on an 8051 can be globally disabled providing additional power saving cap
116. locked byte returns undefined data Debugging code in a read locked sector is not possible through the JTAG interface The lock bits can always be read from and written to logic 0 regardless of the security setting applied to the block containing the security bytes This allows additional blocks to be protected after the block containing the security bytes has been locked Important Note To ensure protection from external access the block containing the lock bytes must be Write Erase locked On the 64 k byte devices C8051F060 1 2 3 4 5 the page containing the security bytes is OXFA00 OxFBFF and is locked by clearing bit 7 of the Write Erase Lock Byte On the 32 byte devices C8051F066 7 the page containing the security bytes is 0x7E00 0x7FFF and is locked by clearing bit 3 of the Write Erase Lock Byte If the page containing the security bytes is not Write Erase locked it is still possible to erase this page of Flash memory through the JTAG port and reset the security bytes When the page containing the security bytes has been Write Erase locked a JTAG full device erase must be performed to unlock any areas of Flash protected by the security bytes A JTAG full device erase is initiated by performing a normal JTAG erase operation on either of the security byte locations This operation must be initiated through the JTAG port and cannot be performed from firmware running on the device e Rev 1 2 179 SILICON LABS C8051F060 1 2
117. masking of the Timer 4 interrupt 0 Disable Timer 4 interrupt 1 Enable interrupt requests generated by the TF4 flag EADC1 Enable ADC1 End of Conversion Interrupt This bit sets the masking of the ADC1 End of Conversion Interrupt 0 Disable ADC1 Conversion Interrupt 1 Enable interrupt requests generated by the ADC1 Conversion Interrupt ET3 Enable Timer 3 Interrupt This bit sets the masking of the Timer 3 interrupt 0 Disable all Timer 3 interrupts 1 Enable interrupt requests generated by the flag e Rev 1 2 157 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 13 23 EIP1 Extended Interrupt Priority 1 R W R W R W R W R W R W R W R W Reset Value PADCO PCP2 PCP1 PPCAO PWADCO PSMBO PSPIO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xF6 SFR Page All Pages Bit7 PADCO ADC End of Conversion Interrupt Priority Control This bit sets the priority of the ADCO End of Conversion Interrupt 0 ADCO End of Conversion interrupt set to low priority level 1 ADCO End of Conversion interrupt set to high priority level Bit6 PCP2 Comparator2 CP2 Interrupt Priority Control This bit sets the priority of the CP2 interrupt 0 CP2 interrupt set to low priority level 1 CP2 interrupt set to high priority level Bit5 PCP1 Comparator1 CP1 Interrupt Priority Control This bit sets the priority of the CP1 interrupt 0 CP1 interrupt set to low pri
118. orientations as shown in the DACOCN register definition is functionally the same as DACO described above The electrical specifications for both DACO and DAC 1 are given in Table 8 1 104 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 8 2 DACOH DACO High Byte Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xD3 SFR Page 0 Bits7 0 DACO Data Word Most Significant Byte Figure 8 3 DACOL DACO Low Byte Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit2 Bito SFR Address 0xD2 SFR Page 0 Bits7 0 DACO Data Word Least Significant Byte 1 2 105 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 8 4 DACOCN DACO Control Register R W R W R W R W R W R W R W R W Reset Value DACOEN DACOMD1 DACOMDO DACODF2 DACODF1 DACODFO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xD4 SFR Page 0 Bit7 DAC0EN DAC0 Enable Bit 0 DAC0 Disabled DAC0 Output pin is disabled DAC0 is in low power shutdown mode 1 DAC0 Enabled DAC0 Output pin is active DACO is operational Bits6 5 UNUSED Read 00b Write don t care Bits4 3 DAC0MD1 0 DACO Mode Bits 00 DAC output updates occur on a write to DACOH 01 DAC output updates occur on Timer 3
119. out through the MISO pin by a master device controlling the SCK sig nal A bit counter in the SPIO logic counts SCK edges When 8 bits have been shifted through the shift reg ister the SPIF flag is set to logic 1 and the byte is copied into the receive buffer Data is read from the receive buffer by reading SPIODAT A slave device cannot initiate transfers Data to be transferred to the master device is pre loaded into the shift register by writing to SPIODAT Writes to SPIODAT are double buffered and are placed in the transmit buffer first If the shift register is empty the contents of the transmit buffer will immediately be transferred into the shift register When the shift register already contains data the SPI will load the shift register with the transmit buffer s contents after the last edge of the next or current SPI transfer When configured as a slave SPIO can be configured for 4 wire or 3 wire operation The default 4 wire slave mode is active when NSSMD1 SPIOCN 3 0 and NSSMDO SPIOCN 2 1 In 4 wire mode the NSS signal is routed to a port pin and configured as a digital input SPIO is enabled when NSS is logic 0 and disabled when NSS is logic 1 The bit counter is reset on a falling edge of NSS Note that the NSS sig nal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer Figure 21 4 shows a connection diagram between two slave devices in 4 wire slave mode and a mast
120. overflow 10 DAC output updates occur on Timer 4 overflow 11 DAC output updates occur on Timer 2 overflow Bits2 0 DACODF2 0 DACO Data Format Bits 000 most significant nibble of the DACO Data Word is in DACOH 3 0 while the least significant byte is in DACOL MSB LSB 001 most significant 5 bits of the DACO Data Word is in DACOH 4 0 while the least significant 7 bits are in DACOL 7 1 MSB LSB 010 most significant 6 bits of the DACO Data Word is in DACOH 5 0 while the least significant 6 bits are in DACOL 7 2 DACOH DACOL DACOH DACOL MSB LSB 1xx most significant 8 bits of the DACO Data Word is in DACOH 7 0 while the least MSB LSB 011 The most significant 7 bits of the DACO Data Word is in DACOH 6 0 while the least significant 5 bits are in DACOL 7 3 significant 4 bits are in DACOL 7 4 DACOH DACOL MSB LSB 106 Rev 1 2 5 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 8 5 DAC1H DAC1 High Byte Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xD3 SFR Page 1 Bits7 0 DAC1 Data Word Most Significant Byte Figure 8 6 DAC1L DAC1 Low Byte Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xD2 SFR Page 1 Bits7 0 DAC1 Data Word Least S
121. pin Update CAN RX Output to pin 4 Capture CAN TX Output Enable to pin Update CAN TX Output Enable to pin 5 Capture CAN TX Input from pin Update TX Output to pin 6 Capture External Clock from XTAL1 pin Update Not used 7 Capture Weak Pullup Enable from MCU Update Weak Pullup Enable to Port Pins 8 10 12 14 16 Capture output enable from MCU e g 8 Bit 10 PO 1 etc 18 20 22 Update output enable to pin e g Bit 8 P0 0oe Bit 10 1 etc 9 11 13 15 17 Capture P0 n input from pin e g Bit Bit 11 etc 19 21 23 Update PO0 n output to pin e g Bit 9 P0 0 Bit 11 PO 1 etc 24 26 28 30 32 Capture P1 n output enable from MCU follows numbering scheme 34 36 38 Update P1 n output enable to pin follows PO n numbering scheme 25 27 29 31 33 Capture P1 n input from pin follows PO n numbering scheme 35 37 39 Update P1 n output to pin follows numbering scheme 40 42 44 46 48 Capture P2 n output enable from follows numbering scheme 50 52 54 Update P2 n output enable to pin follows PO n numbering scheme 41 43 45 47 49 Capture P2 n input from pin follows PO n numbering scheme 51 53 55 Update P2 n output to pin follows PO n numbering scheme 56 58 60 62 64 Capture P3 n output enable from MCU follows numbering scheme 66 68 70 Update P3 n output enab
122. results in an overflow result is greater than 255 A DIV instruction causes a divide by zero condition The OV bit is cleared to 0 by the ADD ADDC SUBB MUL and DIV instructions in all other cases Bit F1 User Flag 1 This is a bit addressable general purpose flag for use under software control Bito PARITY Parity Flag This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even e Rev 1 2 149 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 13 17 ACC Accumulator R W Reset Value Bits7 0 B This register serves as a second accumulator for certain arithmetic operations B Register SFR Address OxFO SFR Page Pages R W R W R W R W R W R W R W ACC 7 ACC 6 ACC 5 ACC 4 ACC 3 ACC 2 ACC 1 0 00000000 Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Ad r ssable SFR Address 0 0 SFR Page All Pages Bits7 0 ACC Accumulator This register is the accumulator for arithmetic operations Figure 13 18 B B Register R W R W R W R W R W R W R W R W Reset Value B 7 B 6 B 5 B 4 B 3 B 2 B 1 0 00000000 Bit Bit7 Bit6 Bit5 Bit4 Bit2 Bit1 Bito Addressable 150 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 13 3 Interrupt Handler The CIP 51 includes an extended interrupt system supporting a total of 22 i
123. set If these conditions are not met SBUF1 and RB81 will not be loaded and the flag will not be set An interrupt will occur if enabled when either or is set Figure 23 4 8 Bit UART Timing Diagram MARK START 1 D2 D 04 D D D7 STOP a ar we jy m aris fp fff fff A BITSAMPLING Rev 1 2 279 SILICON LABS C8051F060 1 2 3 4 5 6 7 23 2 2 9 Bit UART 9 bit UART mode uses a total of eleven bits per data byte a start bit 8 data bits LSB first a programma ble ninth data bit and a stop bit The state of the ninth transmit data bit is determined by the value in TB81 SCON1 3 which is assigned by user software It can be assigned the value of the parity flag bit P in reg ister PSW for error detection or used in multiprocessor communications On receive the ninth data bit goes into RB81 SCON1 2 and the stop bit is ignored Data transmission begins when an instruction writes a data byte to the SBUF1 register The Transmit Interrupt Flag SCON1 1 is set at the end of the transmission the beginning of the stop bit time Data reception can begin any time after the Receive Enable bit SCON1 4 is set to 1 After the stop bit is received the data byte will be loaded into the SBUF1 receive register if the following conditions are met 1 RH must be logic 0 and 2 if MCE1 is logic 1 the 9th bit must be logic 1
124. set the UARTO TX pin output and the CEXO 3 outputs to Push Pull by setting POMDOUT OxF1 We explicitly disable the output drivers on the 3 Analog Input pins by setting the corresponding bits in the PI MDOUT register to 0 and in P1 to 1 Additionally the CEX5 4 output pins are set to Push Pull mode Therefore PIMDOUT 0x03 configure unused pins to Open Drain and P1 OxFF a logic 1 selects the high impedance state 208 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 18 4 Crossbar Example P1MDIN OxE3 XBRO 0x3D 1 0x14 XBR2 0x40 1 crossbar Register Bits CA PINIOJ 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7P 0 1 2 34 5 6 7 TXO sm E M EM e Poo UARTOEN 2 SPIOEN 1 SMBOEN 0 0 XBR2 2 o o o i i 2 2 XBRO 5 3 5 iB HB w heee e ECIOE XBRO 6 eoi CP2E XBR3 3 XBR3 1 TRE
125. sleep modes Low power track and hold mode is also useful when AMUX settings are frequently changed due to the settling time requirements described in Section 7 2 3 Settling Time Requirements on page 91 Figure 7 3 10 Bit ADC Track and Conversion Example Timing A ADC2 Timing for External Trigger Source CNVSTR2 AD2CM 1 0 10 12 3 4 5 6 7 8 9 10 t1 SAR Clocks LOW Power Convert POE ONS or Convert Mode AD2TM 0 Track or Convert Convert Track B ADC2 Timing for Internal Trigger Source Write 1 to AD2BUSY Timer 3 Timer 2 Overflow AD2CN 1 0 00 01 11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SAR Clocks OW POWE Track Convert Low Power Mode AD2TM 1 or Convert 1 2 3 456789101 SAR Clocks Track or AD2TM 0 Convert Convert Track 90 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 7 2 3 Settling Time Requirements A minimum tracking time is required before an accurate conversion can be performed This tracking time is determined by the AMUX2 resistance the ADC2 sampling capacitance any external source resistance and the accuracy required for the conversion Note that in low power tracking mode three SAR clocks are used for tracking at the start of every conversion For most applications these three SAR c
126. sopor epar 166 auos u NE KR eb E OU 171 15 1 Programmable Internal Oscillator 171 15 2 External Oscillator Drive Circuit 173 15 3 System Clock Selection 173 15 4 External Crystal 175 15 5 RG Examples uuu uu u EEEN 175 15 6 External Capacitor Example roten arce inni 175 16 FIASH qc 177 16 1 Programming The Flash 177 16 2 Non volatile Data Storage 178 DG ed CUE Options m ET 179 16 3 1 Summary of Flash Security 183 17 External Data Memory Interface and On Chip 187 17 1 Accessing XRAM c 187 17 1 1 16 Bit MOVX 187 17 1 2 8 Bit MOVX 2 2 0444 187 17 2 Configuring the External Memory 188 17 3 Poit Selection and Confi
127. the digital peripheral that is mapped to those pins Writes to the Port Data registers or associated Port bits will have no effect on the states of these pins A Read of a Port Data register or Port bit will always return the logic state present at the pin itself regard less of whether the Crossbar has allocated the pin for peripheral use or not An exception to this occurs during the execution of a read modify write instruction ANL ORL XRL CPL INC DEC DJNZ JBC CLR SETB and the bitwise MOV write operation During the read cycle of the read modify write instruc tion it is the contents of the Port Data register not the state of the Port pins themselves which is read Because the Crossbar registers affect the pinout of the peripherals of the device they are typically config ured in the initialization code of the system before the peripherals themselves are configured Once config ured the Crossbar registers are typically left alone Once the Crossbar registers have been properly configured the Crossbar is enabled by setting XBARE XBR2 4 to a logic 1 Until XBARE is set to a logic 1 the output drivers on Ports 0 through 3 are explicitly disabled in order to prevent possible contention on the Port pins while the Crossbar reg isters and other registers which can affect the device pinout are being written The output drivers on Crossbar assigned input signals like for example are explicitly disabled thus the values o
128. the next system reset Writing OXFF does not enable or reset the watchdog timer Applications always intending to use the watchdog should write OxFF to WDTON in the initialization code 14 7 4 Setting WDT Interval WDTON 2 0 control the watchdog timeout interval The interval is given by the following equation 3 WDTCN 2 0 4 xT where Tsyscik is the system clock period sysclk 166 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 For a 3 MHz system clock this provides an interval range of 0 021 ms to 349 5 ms WDTCN 7 must be logic 0 when setting this interval Reading WDTON returns the programmed interval WDTCN 2 0 reads 111b after a system reset Figure 14 3 WDTCN Watchdog Timer Control Register R W R W R W R W R W R W R W R W Reset Value xxxxx111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Biti Bito SFR Address 0xFF SFR Page All Pages Bits7 0 WDT Control Writing OxA5 both enables and reloads the WDT Writing OxDE followed within 4 system clocks by OxAD disables the WDT Writing OxFF locks out the disable feature Bit4 Watchdog Status Bit when Read Reading the WDTCN 4 bit indicates the Watchdog Timer Status 0 WDT is inactive 1 WDT is active Bits2 0 Watchdog Timeout Interval Bits WDTCN 2 0 bits set the Watchdog Timeout Interval When writing these bits WDTCN 7 must be set to 0 e Rev 1 2 167 SILICON LABS C8051F060 1 2 3 4 5 6 7 Fi
129. to 1 and an interrupt will occur if the interrupt is enabled See Section 13 3 Interrupt Handler on page 151 for further information concerning the configuration of interrupt sources As the 16 bit timer register increments and overflows TMRnH TMRnL the TFn Timer Overflow Underflow Flag TMRnCN 7 is set to 1 and an interrupt will occur if the interrupt is enabled The timer can be config ured to count down by setting the Decrement Enable Bit TMRnCF 0 to 1 This will cause the timer to decrement with every timer clock count event and underflow when the timer transitions from 0x0000 to OxFFFF Just as in overflows the Overflow Underflow Flag TFn will be set to 1 and an interrupt will occur if enabled Counter Timer with Capture mode is selected by setting the Capture Reload Select bit CP RLn 0 and the Timer 2 3 and 4 Run Control bit TRn TnCON 2 to logic 1 The Timer 2 and 4 respective External Enable EXENn TnCON 3 must also be set to logic 1 to enable a captures If EXENn is cleared transitions on TnEX will be ignored Figure 24 11 T2 3 and 4 Capture Mode Block Diagram TMRnCF nin MMGO E 1 0 n EN ui
130. to update program code and use the program memory space for non volatile data storage Refer to Section 16 Flash Memory on page 177 for further details 130 Rev 1 2 g SILICON LABS C8051F060 1 2 3 4 5 6 7 13 2 2 Data Memory The CIP 51 implements 256 bytes of internal RAM mapped into the data memory space from 0x00 through OxFF The lower 128 bytes of data memory are used for general purpose registers and scratch pad mem ory Either direct or indirect addressing may be used to access the lower 128 bytes of data memory Loca tions 0x00 through 0x1F are addressable as four banks of general purpose registers each bank consisting of eight byte wide registers The next 16 bytes locations 0x20 through Ox2F may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode The upper 128 bytes of data memory are accessible only by indirect addressing This region occupies the same address space as the Special Function Registers SFRs but is physically separate from the SFR space The addressing mode used an instruction when accessing locations above Ox7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs Instructions that use direct addressing above 0x7F will access the SFR space Instructions using indirect addressing above Ox7F access the upper 128 bytes of data memory Figure 13 2 illustrates the data memory organization of the CIP 51 13 2 3 Gener
131. when is logic 0 the state of the ninth data bit is unimportant If these conditions are met the eight bits of data are stored in SBUF1 the ninth bit is stored in RB81 and the flag is set to 1 If the above conditions are not met SBUF1 and RB81 will be loaded and the flag will be set to 1 A UARTI interrupt will occur if enabled when either or is set to 1 Figure 23 5 9 Bit UART Timing Diagram MARK START er X p X os X X vs X v X w oe STOP BIT SPACE E 5 5 555 4 A4 A 74 280 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 23 3 Multiprocessor Communications 9 Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit When a master processor wants to transmit to one or more slaves it first sends an address byte to select the target s An address byte differs from a data byte in that its ninth bit is logic 1 in a data byte the ninth bit is always set to logic 0 Setting the MCE1 bit SCON 5 of a slave processor configures its UART such that when a stop bit is received the UART will generate an interrupt only if the ninth bit is logic one RB81 1 signifying an address byte has been received In the UART interrupt handler software should compare the received address with the slave s own assigned 8 bit ad
132. 0 1 2 3 4 5 6 7 1 11 Analog Comparators The C8051F060 1 2 3 4 5 6 7 MCUs include three analog comparators on chip The comparators have software programmable hysteresis and response time Each comparator can generate an interrupt on its rising edge falling edge or both The interrupts are capable of waking up the MCU from sleep mode and Comparator 0 can be used as a reset source The output state of the comparators can be polled in soft ware or routed to Port I O pins via the Crossbar Outputs from the comparator can be routed through the crossbar The comparators can be programmed to a low power shutdown mode when not in use CPnOutput l Port Uo xe CROSSBAR Comparators cent 51 Interrupt CPn Handler and Comparator inputs Port 2 7 2 Figure 1 15 Comparator Block Diagram 36 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 2 Absolute Maximum Ratings Table 2 1 Absolute Maximum Ratings Parameter Conditions Min Units Ambient temperature under bias 55 125 C Storage Temperature 65 150 C Voltage on any pin except VDD AV AVDD and 0 3 VDD V Port 0 with respect to DGND 0 3 Voltage on any Port 0 Pin with respect to DGND 0 3 5 8 V Voltage on VDD AV or AVDD with respect to DGND 0 3 4 2 V Maximum Total current through VDD AV AVDD 800 mA DGND and AGND Maximum output current sunk
133. 000 DMAOCSH L DMAOCTH L 1 DMAOCSH L DMAOCTH L 78 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 6 6 Interrupt Sources The DMA contains multiple interrupt sources Some of these can be individually enabled to generate inter rupts as necessary The DMA Control Register DMAOCN Figure 6 4 DMA Configuration Register DMAOCF Figure 6 5 contain the enable bits and flags for the DMA interrupt sources When an interrupt is enabled and the interrupt condition occurs a DMA interrupt will be generated EIE2 7 is set to 1 The DMA flags that can generate DMAO interrupt are 1 DMA Operations Complete DMAOCN 6 DMAOINT occurs when all DMA operations have been completed and the DMA interface is idle 2 ADC1 Data Overflow Error DMAOCN 4 DMAODE1 occurs when the DMA interface cannot access XRAM for two conversion cycles of ADC1 This flag indicates that at least one conver sion result from ADC1 has been discarded 3 ADCO Data Overflow Error DMAOCN 3 DMAODEO occurs when the DMA interface cannot access XRAM for two conversion cycles of ADCO This flag indicates that at least one conver sion result from ADCO has been discarded 4 ADC1 Data Overflow Warning DMAOCN 1 DMAODO 1 occurs when data from ADCO becomes available and the DMA has not yet written the previous results to XRAM This inter rupt source can be enabled and disabled with the Data Overflow Warning Enable bit DMAOCN 2 DMAODO
134. 0000 0x0000 192 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 17 5 3 Split Mode with Bank Select When EMIOCF 3 2 are set to 10 the XRAM memory map is split into two areas on chip space and off chip space Effective addresses below the 4 kB boundary will access on chip XRAM space Effective addresses beyond the 4 kB boundary will access off chip space 8 bit MOVX operations use the contents of EMIOCN to determine whether the memory access is on chip or off chip The upper 8 bits of the Address Bus A 15 8 are determined by EMIOCN and the lower 8 bits of the Address Bus A 7 0 are determined by RO or R1 All 16 bits of the Address Bus A 15 0 are driven in Bank Select mode 16 bit MOVX operations use the contents of DPTR to determine whether the memory access is on chip or off chip and the full 16 bits of the Address Bus A 15 0 are driven during the off chip transac tion 17 5 4 External Only When 3 2 are set to 11 all MOVX operations are directed to off chip space On chip XRAM is not visible to the CPU This mode is useful for accessing off chip memory located between 0x0000 and the 4 kB boundary 8 bit MOVX operations ignore the contents of EMIOCN The upper Address bits A 15 8 are not driven identical behavior to an off chip access in Split Mode without Bank Select described above This allows the user to manipulate the upper address bits at will by setting the Port state
135. 051F33x The SPIO Clock Rate Register SPIOCKR as shown in Figure 21 10 controls the master mode serial clock frequency This register is ignored when operating in slave mode When the SPI is configured as a master the maximum data transfer rate bits sec is one half the system clock frequency or 12 5 MHz whichever is slower When the SPI is configured as a slave the maximum data transfer rate bits sec for full duplex operation is 1 10 the system clock frequency provided that the master issues SCK NSS in 4 wire slave mode and the serial input data synchronously with the slave s system clock If the master issues SCK NSS and the serial input data asynchronously the maximum data transfer rate bits sec must be less than 1 10 the system clock frequency In the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave i e half duplex operation the SPI slave can receive data at a maximum data transfer rate bits sec of 1 4 the system clock frequency This is provided that the master issues SCK NSS and the serial input data synchronously with the slave s system clock Figure 21 5 Master Mode Data Clock Timing SCK f CKPOL 0 CKPHA 0 L EM EM LJ L _ SCK a 1 1 WE 1 CKPOL 0 CKPHA 1 SCK CKPOL 1 0 u EN L CKPOL 1 CKPHA 1 cT T ff P EX
136. 1 Comparator Electrical Characteristics on page 122 12 1 Comparator Inputs The Port pins selected as comparator inputs should be configured as analog inputs in the Port 2 Input Con figuration Register for details on Port configuration see Section 18 1 3 Configuring Port Pins as Digital Inputs on page 207 The inputs for Comparator are on Port 2 as follows Comparator Input Port PIN CPO P2 6 P2 7 CP1 P2 2 CP1 P2 3 CP2 P2 4 2 P2 5 Rev 1 2 119 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 12 3 CPTnCN Comparator 0 1 and 2 Control Register R W R W R W R W R W R W R W R W Reset Value CPnOUT CPnRIF CPnFIF CPnHYP1 CPnHYPO CPnHYN1 CPnHYNO 00000000 Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address CPT0CN 0x88 CPT1CN 0x88 CPT2CN 0x88 SFR Pages CPT0CN page 1 CPT1CN page 2 CPT2CN page 3 Bit7 CPnEN Comparator Enable Bit Please see note below 0 Comparator Disabled 1 Comparator Enabled Bit6 CPnOUT Comparator Output State Flag 0 Voltage on CPn lt CPn 1 Voltage on gt Bit5 CPnRIF Comparator Rising Edge Interrupt Flag 0 No Comparator Rising Edge Interrupt has occurred since this flag was last cleared 1 Comparator Rising Edge Interrupt has occurred Must be cleared by software Bit4 CPnFIF Comparator Falling Edge
137. 1 2 217 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 18 17 P3 Port3 Data Register R W R W R W R W R W R W R W R W Reset Value P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 11111111 I Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Ad ressabl SFR Address 0 0 SFR Page All Pages Bits7 0 7 0 Port3 Output Latch Bits Write Output appears on I O pins XBRO XBR1 XBR2 Registers 0 Logic Low Output 1 Logic High Output open if corresponding bit 0 Read Regardless XBR1 XBR2 and XBR3 Register settings 0 P3 n pin is logic low 1 P3 n pin is logic high Note Although P3 is not brought out to pins on the C8051F061 3 5 7 devices the Port Data regis ter is still present and can be used by software See Configuring Ports which are not Pinned Out on page 219 Figure 18 18 Port3 Output Mode Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO SFR Address OxA7 SFR Page F Bits7 0 P3MDOUT 7 0 Port3 Output Mode Bits 0 Port Pin output mode is configured as Open Drain 1 Port Pin output mode is configured as Push Pull 218 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 18 2 Ports 4 through 7 C8051F060 2 4 6 only All Port pins on Ports 4 through 7 can be accessed as Gener
138. 13 25 PCON Power Control R W R W R W R W R W R W R W R W Reset Value STOP IDLE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x87 Bits7 2 Reserved Bit1 STOP STOP Mode Select Writing a 1 to this bit will place the CIP 51 into STOP mode This bit will always read 0 1 CIP 51 forced into power down mode Turns off internal oscillator Bit0 IDLE IDLE Mode Select Writing 1 to this bit will place the CIP 51 into IDLE mode This bit will always read 0 1 CIP 51 forced into IDLE mode Shuts off clock to CPU but clock to Timers Interrupts and all peripherals remain active See Note in Section 13 4 1 Idle Mode on page 160 SFR Page All Pages e Rev 1 2 161 SILICON LABS C8051F060 1 2 3 4 5 6 7 162 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 14 Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition On entry to this reset state the following occur CIP 51 halts program execution Special Function Registers SFRs are initialized to their defined reset values External port pins are forced to a known configuration Interrupts and timers are disabled All SFRs are reset to the predefined values noted in the SFR detailed descriptions The contents of internal data memory are unaffected during a reset any previously stored data is preserved Howeve
139. 14 4 Missing Clock Detector Reset The Missing Clock Detector is essentially a one shot circuit that is triggered by the MCU system clock If the system clock goes away for more than 100 us the one shot will time out and generate a reset After a Missing Clock Detector reset the MCDRSF flag RSTSRC 2 will be set signifying the MSD as the reset source otherwise this bit reads 0 The state of the RST pin is unaffected by this reset Setting the MCDRSF bit RSTSRC 2 see Section 15 Oscillators on page 171 enables the Missing Clock Detector 14 5 Comparator0 Reset ComparatorO can be configured as a reset input by writing a 1 to the CORSEF flag RSTSRC 5 Compar should be enabled using CPTOCN 7 see Section 12 Comparators page 117 prior to writing to CORSEF to prevent any turn on chatter on the output from generating an unwanted reset The Compara tor0 reset is active low if the non inverting input voltage CP0 pin is less than the inverting input voltage pin the MCU is put into the reset state After Reset the CORSEF flag RSTSRC 5 will read 1 signifying as the reset source otherwise this bit reads 0 The state of the RST pin is unaffected by this reset 14 6 External CNVSTR2 Pin Reset The external CNVSTR2 signal can be configured as a reset input by writing a 1 to the CNVRSEF flag RSTSRC 6 The CNVSTR2 signal can
140. 18 120 122 124 Capture P7 n output enable from MCU follows numbering scheme Update P7 n output enable to pin follows PO n numbering scheme 111 113 115 117 119 121 123 125 Capture P7 n input from pin follows numbering scheme Update P7 n output to pin follows PO n numbering scheme e SILICON LABS Rev 1 2 319 C8051F060 1 2 3 4 5 6 7 Table 26 2 Boundary Data Register Bit Definitions C8051F061 3 5 7 EXTEST provides access to both capture and update actions while Sample only performs a capture Bit Action Target 0 Capture Not used Update Not used 1 Capture Not used Update Not used 2 Capture CAN RX Output Enable to pin Update CAN RX Output Enable to pin 3 Capture CAN RX Input from pin Update RX Output to pin 4 Capture CAN TX Output Enable to pin Update CAN TX Output Enable to pin 5 Capture CAN TX Input from pin Update CAN TX Output to pin 6 Capture External Clock from XTAL1 pin Update Not used 7 Capture Weak Pullup Enable from MCU Update Weak Pullup Enable to Port Pins 8 10 12 14 16 Capture output enable from MCU e g 8 Bit 10 PO 1 etc 18 20 22 Update output enable to pin e g Bit 8 P0 0oe Bit 10 1 etc 9 11 13 15
141. 18 Port Input Output on page 203 Setting the timer s Run Bit TRn to 1 will start the toggle of the pin A Read Write of the Timer s Toggle Output State Bit TMRnCF 2 is used to read the state of the toggle output or to force a value of the output This is useful when it is desired to start the toggle of a pin in a known state or to force the pin into a desired state when the toggle mode is halted Equation 24 1 Toggle Mode Square Wave Frequency a FTCLK 54 2 65536 298 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 24 13 TMRnCN Timer 2 3 and 4 Control Registers R W R W R W R W R W R W R W R W Reset Value TFn EXFn EXENn TRn C Tn CP RLn 00000000 Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Addressable SFR Address TMR2CN 0xC8 TMR3CN 0xC8 TMR4CN 0xC8 SFR Page TMR2CN page 0 TMR3ON page 1 TMR4CN page 2 Bit7 Bit6 Bit5 4 Bit3 Bit2 Bit TFn Timer 2 3 and 4 Overflow Underflow Flag Set by hardware when either the Timer overflows from OxFFFF to 0x0000 underflows from the value placed in RCAPnH RCAPnL to OXFFFF in Auto reload Mode or underflows from 0x0000 to OxFFFF in Capture Mode When the Timer interrupt is enabled setting this bit causes the CPU to vector to the Timer interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software EXF
142. 198 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 17 6 2 Multiplexed Mode 17 6 2 1 16 bit MOVX EMIOCF 4 2 001 010 or 011 Figure 17 10 Multiplexed 16 bit MOVX Timing Muxed 16 bit WRITE ADDR 15 8 AD 7 0 ALE lt T T gt WDS WDH bo T T ACW RD P4 6 4 6 Muxed 16 bit READ ADDR 15 8 m ALEH LE 45 R P47 4 7 Rev 1 2 199 SILICON LABS C8051F060 1 2 3 4 5 6 7 17 6 2 2 8 bit MOVX without Bank Select EMIOCF 4 2 4001 or 011 Figure 17 11 Multiplexed 8 bit MOVX without Bank Select Timing Muxed 8 bit WRITE Without Bank Select ADDR 15 8 P6 AD 7 0 ALE RD P4 6 P4 6 Muxed 8 bit READ Without Bank Select ADDR 15 8 P6 AD 7 0 ALE RD 200 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 17 6 2 3 8 bit MOVX with Bank Select EMIOCF 4 2 010 Figure 17 12 Multiplexed 8 bit MOVX with Bank Select Timing Muxed 8 bit WRITE with Bank Select 15 8 AD 7 0 ALE RD Muxed 8 bit READ with Bank Select ADDR 15 8 AD 7 0 ALE P4 5 b P4 5 i Ace gt lt TACW P4 ACH gt RD Pa P46 WR P4 7 j i P4 7 Rev 1 2 201 SILICON LABS C8051F060 1 2 3 4 5
143. 2 3 4 5 6 7 234 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 20 System Management BUS 12C BUS SMBUSO The SMBusO interface is a two wire bi directional serial bus SMBus0 is compliant with the System Management Bus Specification version 1 1 and compatible with the 2 serial bus Reads and writes to the interface by the system controller are byte oriented with the SMBusO interface autonomously con trolling the serial transfer of the data A method of extending the clock low duration is available to accom modate devices with different speed capabilities on the same bus SMBus0 may operate as a master and or slave and may function on a bus with multiple masters SMBusO provides control of SDA serial data SCL serial clock generation and synchronization arbitration logic and START STOP control and generation Figure 20 1 SMBusO Block Diagram SFR Bus 2 SMBOCN SMBOSTA SMBOCR 5 5 5 5 5 C6lee cie ele UNNIT T I A T O RS le S S A O 76543210 6 5 4 3 2 1 0 B Clock Divide Logic 4 5 5
144. 2 3 4 5 6 7 Figure 25 11 PCAOMD PCAO Mode Register R W R W R W R W R W R W R W R W Reset Value CIDL 52 51 50 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0xD9 SFR Page 0 Bit7 CIDL Counter Timer Idle Control Specifies behavior when CPU is in Idle Mode 0 continues to function normally while the system controller is in Idle Mode 1 operation is suspended while the system controller is in Idle Mode Bits6 4 UNUSED Read 000b Write don t Bits3 1 52 50 PCAO Counter Timer Pulse Select These bits select the timebase source for the PCAO counter CPS2 CPS1 CPSO Timebase 0 0 0 System clock divided by 12 0 0 1 System clock divided by 4 0 1 0 Timer 0 overflow 0 1 1 High to low transitions rate system clock divided by 4 1 0 0 System clock 1 0 1 External clock divided by 81 1 1 0 Reserved 1 1 1 Reserved ECF PCA Counter Timer Overflow Interrupt Enable This bit sets the masking of the PCAO Counter Timer Overflow CF interrupt 0 Disable the CF interrupt 1 Enable a PCAO Counter Timer Overflow interrupt request when CF PCAOCN 7 is set TNote External clock divided by 8 is synchronized with the system clock and external clock must be less than or equal to the system clock frequency to operate in this mode
145. 2 Greater Than Data Word e Rev 1 2 97 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 7 13 ADC2LTH ADC2 Less Than Data High Byte Register SFR Page 2 SFR Address OxC7 R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bits7 0 High byte of ADC2 Less Than Data Word Figure 7 14 ADC2LTL ADC2 Less Than Data Low Byte Register SFR Page 2 SFR Address 0 6 R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bito Bits7 0 Low byte of ADC2 Less Than Data Word 98 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 7 3 1 Window Detector In Single Ended Mode Figure 7 15 shows two example window comparisons for right justified single ended data with ADC2LTH ADC2LTL 0x0080 128d and ADC2GTH ADC2GTL 0x0040 64d In single ended mode the input voltage can range from 0 to VREF 1023 1024 with respect to AGND and is represented by a 10 bit unsigned integer value In the left example an AD2WINT interrupt will be generated if the ADC2 conversion word ADC2H ADC2L is within the range defined by ADC2GTH ADC2GTL and ADC2LTH ADC2LTL if 0x0040 lt ADC2H ADC2L lt 0 0080 In the right example and AD2WINT interrupt will be generated if the ADC2 conversion word is outside of the range defined by the ADC2GT and ADC2LT registers if ADC2H ADC2L lt 0x0040 or ADC2H ADC2L gt 0x0080 Figure 7
146. 25 9 16 Bit PWM 311 Figure 25 10 PCAOCN PCA Control Register 312 Figure 25 11 PCAOMD PCAO Mode 2 313 Figure 25 12 Capture Compare Mode Registers 314 Figure 25 13 PCAOL PCAO Counter Timer Low 315 Figure 25 14 PCAOH PCAO Counter Timer High Byte 315 Figure 25 15 PCAOCPLn PCAO Capture Module Low Byte 316 Figure 25 16 PCAO Capture Module High Byte 316 26 JTAG IEEE 1149 1 317 Figure 26 1 IR JTAG Instruction 317 Figure 26 2 DEVICEID JTAG Device ID 321 Figure 26 3 FLASHCON JTAG Flash Control 323 Figure 26 4 FLASHDAT JTAG Flash Data 324 Figure 26 5 FLASHADR JTAG Flash Address 324 27 Document Change List u UU I 327 Rev 1 2 15 SILICON LABS C8051F060 1 2 3 4 5 6 7
147. 3 4 5 6 7 Figure 16 1 C8051F060 1 2 3 4 5 Flash Program Memory Map and Security Bytes Readand Write EraseSecurity Bits SFLE 0 Bit 7 is MSB Memory Block B i OxE000 0xFBFD ae Read Lock Byte OxFBFF 0x8000 0x9FFF Write EraseLockByte 0x6000 0x7FFF OxFBFD 2 0x4000 0x5FFF 1 0x2000 0x3FFF 0 0x0000 0x1FFF FlashAccess Limit SFLE 1 0x007F 0x0000 Program Data ScratchpadMemory Memory Space Dataonly Flash Read Lock Byte Bits7 0 Each bit locks a corresponding block of memory Bit7 is MSB 0 Read operations are locked disabled for corresponding block across the JTAG interface 1 Read operations are unlocked enabled for corresponding block across the JTAG inter face Flash Write Erase Lock Byte Bits7 0 Each bit locks a corresponding block of memory 0 Write Erase operations are locked disabled for corresponding block across the JTAG interface 1 Write Erase operations are unlocked enabled for corresponding block across the JTAG interface NOTE When the block containing the security bytes is locked the security bytes may be written but not erased Flash Access Limit The Flash Access Limit is defined by the setting of the FLACL register as described in Figure 16 3 Firmware running at or above this address is prohibited from using the MOVX and MOVC instructions to read write or erase Flash locations below this address 180 Rev 1 2 SILI
148. 30 Figure 1 11 CAN Controller Overview 2 22 444 000 31 Figure 1 12 16 Bit ADC Block 33 Figure 1 13 10 ADC Diagram 34 Figure 1 14 DAC System Block Diagram 35 Figure 1 15 Comparator Block Diagram suc oon o 36 2 Absolute Maximum Ratings J J J 37 3 Global DC Electrical Characteristics J 38 4 Pinout and Package Definitions J 39 Figure 4 1 C8051F060 C8051F062 Pinout Diagram 100 45 Figure 4 2 C8051F064 C8051F066 Pinout Diagram TQFP 100 46 Figure 4 3 TQFP 100 Package 47 Figure 4 4 C8051F061 C8051F063 Pinout Diagram TQFP 64 48 Figure 4 5 C8051F065 C8051F067 Pinout Diagram TQFP 64 49 Figure 4 6 TQFP 64 Package 50 5 16 Bit ADCs ADCO and 5 51 Figure 5 1 16 Bit ADCO and ADC1 Control Path 51 Figure 5 2 16 bit ADCO and ADC1 Data Path Diagram
149. 4 ADC2 Window AIN2 3 i Compare i Logic AIN2 4 A ADC Data AIN2 5 Registers AIN2 6 5 um gt Complete i AIN2 7 XC Interrupt Write to AD2BUSY eo Start Conversion Timer Overflow AGND I CNVSTR2 Input AV I Timer 2 Overflow Single ended Differential Measurement Figure 1 13 10 Bit ADC Diagram 34 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 1 10 12 bit Digital to Analog Converters The C8051F060 1 2 3 MCUs have two integrated 12 bit Digital to Analog Converters DACs The MCU data and control interface to each DAC is via the Special Function Registers The MCU can place either or both of the DACs in a low power shutdown mode The DACs are voltage output mode and include a flexible output scheduling mechanism This scheduling mechanism allows DAC output updates to be forced by a software write or scheduled on a Timer 2 3 or 4 overflow The DAC voltage reference is supplied from the dedicated VREFD input pin on C8051F060 2 devices or via the VREF2 pin on C8051F061 3 devices which is shared with ADC2 The DACs are espe cially useful as references for the comparators or offsets for the differential inputs of the ADCs SFRS cest and n Interrupt Control pn DAC1 Figure 1 14 DAC System Block Diagram 1 2 35 SILICON LABS C8051F06
150. 5 configures UARTO such that when a stop bit is received UARTO will gen erate an interrupt only if the ninth bit is logic 1 RB80 1 and the received data byte matches the UARTO slave address Following the received address interrupt the slave will clear its SM20 bit to enable inter rupts on the reception of the following data byte s Once the entire message is received the addressed slave resets its SM20 bit to ignore all transmissions until it receives the next address byte While SM20 is logic 1 UARTO ignores all bytes that do not match the UARTO address and include a ninth bit that is logic 1 22 2 2 Broadcast Addressing Multiple addresses can be assigned to a single slave and or a single address can be assigned to multiple slaves thereby enabling broadcast transmissions to more than one slave simultaneously The broadcast address is the logical OR of registers SADDRO and SADENO and 0 of the result are treated as don t cares Typically a broadcast address of OxFF hexadecimal is acknowledged by all slaves assuming don t care bits as 15 The master processor can be configured to receive all transmissions or a protocol can be implemented such that the master slave role is temporarily reversed to enable half duplex trans mission between the original master and slave s Example 4 SLAVE 1 Example 5 SLAVE 2 Example 6 SLAVE 3 SADDRO 00110101 SADDRO 00110101 SADDRO 00110101 SADENO 00001111 SADENO 11110011
151. 5 42 45 42 D Port 2 1 See Port Input Output section for complete description P2 2 44 41 44 41 Port 2 2 See Port Input Output section for complete description P2 3 43 38 43 38 D I O Port 2 3 See Port Input Output section for complete description P2 4 42 37 42 37 Port 2 4 See Port Input Output section for complete description Rev 1 2 41 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 4 1 Pin Definitions Continued Pin Numbers Name F060 F061 F064 F065 Type Description F062 F063 F066 F067 P2 5 41 36 41 36 D I O Port 2 5 See Port Input Output section for complete description P2 6 40 35 40 35 D I O Port 2 6 See Port Input Output section for complete description P2 7 39 34 39 34 D Port 2 7 See Port Input Output section for complete description P3 0 54 54 D Port 3 0 See Port Input Output section for complete description P3 1 53 53 D Port 3 1 See Port Input Output section for complete description P3 2 52 52 D Port 3 2 See Port Input Output section for complete description P3 3 51 51 D Port 3 3 See Port Input Output section for complete description P3 4 50 50 D 3 4 See Port Input Output section for complete description P3 5 49 49 D Port 3 5 See Port Input Output section for complete description P3 6 48 48 D Port 3 6 See Port Input Output section for complete des
152. 51F060 1 2 3 4 5 6 7 Mode after receiving a STOP condition from the master Figure 20 7 Typical Slave Receiver Sequence S SLA Data Byte P Received by SMBus S START Interface STOP A ACK W WRITE Transmitted by SLA Slave Address SMBus Interface 240 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 20 4 SMBus Special Function Registers The 5 0 serial interface is accessed and controlled through five SFRs SMBOCN Control Register SMBOCR Clock Rate Register SMBOADR Address Register SMBODAT Data Register and SMBOSTA Sta tus Register The five special function registers related to the operation of the SMBusO interface are described in the following sections 20 4 1 Control Register The SMBusO0 Control register SMBOCN is used to configure and control the SMBusO interface All of the bits in the register can be read or written by software Two of the control bits are also affected by the SMBusO hardware The Serial Interrupt flag SI SMBOCN 3 is set to logic 1 by the hardware when a valid serial interrupt condition occurs It can only be cleared by software The Stop flag STO SMBOCN 4 is set to logic 1 by software It is cleared to logic 0 by hardware when a STOP condition is detected on the bus Setting the ENSMB flag to logic 1 enables the SMBusO interface Clearing the ENSMB flag to logic 0 dis ables the SMBusO interface and removes it from the bus
153. 7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Page 2 Bits7 4 UNUSED Read 0000b Write don t care Bit3 AD2VRS ADC2 Voltage Reference Select 0 ADC2 voltage reference from VREF2 pin 1 ADC2 voltage reference from AV Bit2 TEMPE Temperature Sensor Enable Bit 0 Internal Temperature Sensor Off 1 Internal Temperature Sensor On Bit1 BIASE ADC DAC Bias Generator Enable Bit Must be 1 if using ADC2 or DACs 0 Internal Bias Generator Off 1 Internal Bias Generator On REFBE Internal Reference Buffer Enable Bit 0 Internal Reference Buffer Off Table 9 1 Voltage Reference Electrical Characteristics VDD 3 0 V AV 3 0 V 40 to 85 C unless otherwise specified R W R W R W R W R W R W R W R W Reset Value AD2VRS TEMPE BIASE REFBE 00000000 SFR Address 0xD1 1 Internal Reference Buffer On Internal voltage reference is driven on the VREF pin Parameter Conditions Min Typ Max Units Internal Reference REFBE 1 Output Voltage 25 ambient 2 36 2 43 2 48 V VREF Power Supply Current 50 VREF Short Circuit Current 30 mA VREF Temperature Coefficient 15 Load Regulation Load 0 to 200 uA to AGND 0 5 VREF Turn on Time 1 4 7 uF tantalum 0 1 uF ceramic 2 ms bypass VREF Turn on Time 2 0 1 ceramic bypass 20 us VREF Turn on Time 3 no bypass cap 10 us External Reference REFBE 0 Input Volt
154. 8 UARTO Control Register R W R W R W R W R W R W R W R W Reset Value SM00 SM10 SM20 RENO TB80 RB80 TIO RIO 00000000 Bit Bit7 Bit6 5 Bit4 Bit3 Bit2 Bit1 Bito Addressable SFR Address 0x98 SFR Page 0 Bits7 6 5 00 5 10 Serial Port Operation Mode Write When written these bits select the Serial Port Operation Mode as follows 5 00 5 10 0 0 Mode 0 Synchronous Mode 0 1 Mode 1 8 Bit UART Variable Baud Rate 1 0 Mode 2 9 Bit UART Fixed Baud Rate 1 1 Mode 3 9 Bit UART Variable Baud Rate Reading these bits returns the current UARTO mode as defined above Bit5 SM20 Multiprocessor Communication Enable The function of this bit is dependent on the Serial Port Operation Mode Mode 0 No effect Mode 1 Checks for valid stop bit 0 Logic level of stop bit is ignored 1 RIO will only be activated if stop bit is logic level 1 Mode 2 and 3 Multiprocessor Communications Enable 0 Logic level of ninth bit is ignored 1 RIO is set and an interrupt is generated only when the ninth bit is logic 1 and the received address matches the UARTO address or the broadcast address Bit4 RENO Receive Enable This bit enables disables the UARTO receiver 0 UARTO reception disabled 1 UARTO reception enabled Bit3 TB80 Ninth Transmission Bit The logic level of this bit will be assigned to the ninth transmission bit in Modes 2 and 3 I
155. 83 Capture P5 0 P5 1 P5 2 P5 3 P5 5 P5 7 respectively input from pint 85 Update P5 0 P5 1 P5 2 P5 3 P5 5 P5 7 respectively output to pint 86 88 90 92 94 Capture P6 n output enable from MCU follows numbering scheme t 96 98 100 Update P6 n output enable to pin follows PO n numbering scheme t 320 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 26 2 Boundary Data Register Bit Definitions C8051F061 3 5 7 Continued EXTEST provides access to both capture and update actions while Sample only performs a capture Bit Action Target 87 89 91 93 95 Capture P6 n input from pin follows PO n numbering scheme t 97 99 101 Update P6 n output pin follows numbering scheme t 102 104 106 P7 n output enable from MCU follows numbering scheme t 108 110 112 114 Update 7 output enable to pin follows numbering scheme t 116 103 105 107 Capture P7 n input from pin follows PO n numbering scheme t 109 111 113 115 Update P7 n output to pin follows numbering scheme t 117 Not connected to pins in this device package 26 1 1 EXTEST Instruction The EXTEST instruction is accessed via the IR The Boundary DR provides control and observability of all the device pins as well as the Weak Pullup feature All inputs to on chip logic are set to logic 1 26 1 2 SAMPLE Instr
156. A CKPOL SLVSEL NSSIN SRMT RXBMT 00000111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0x9A SFR Page 0 Bit 7 SPIBSY SPI Busy read only This bit is set to logic 1 when a SPI transfer is in progress Master or slave Mode Bit 6 MSTEN Master Mode Enable 0 Disable master mode Operate in slave mode 1 Enable master mode Operate as a master Bit 5 CKPHA SPIO Clock Phase This bit controls the SPIO clock phase 0 Data centered on first edge of SCK period t 1 Data centered on second edge of SCK Bit 4 CKPOL SPIO Clock Polarity This bit controls the SPIO clock polarity 0 SCK line low in idle state 1 SCK line high in idle state Bit 3 SLVSEL Slave Selected Flag read only This bit is set to logic 1 whenever the NSS pin is low indicating SPIO is the selected slave It is cleared to logic 0 when NSS is high slave not selected This bit does not indicate the instantaneous value at the NSS pin but rather a de glitched version of the pin input Bit 2 NSSIN NSS Instantaneous Pin Input read only This bit mimics the instantaneous value that is present on the NSS port pin at the time that the register is read This input is not de glitched Bit 1 SRMT Shift Register Empty Valid in Slave Mode read only This bit will be set to logic 1 when all data has been transferred in out of the shift register and there is no new information available to read from the transmit buffer or write to the rece
157. ADC2 whereby conversions are performed on demand During conversion the AD2BUSY bit is set to logic 1 and reset to logic 0 when the conversion is complete The falling edge of AD2BUSY triggers an interrupt when enabled and sets the ADC2 interrupt flag AD2INT Note When polling for ADC conversion completions the ADC2 interrupt flag AD2INT should be used Converted data is available in the ADC2 data registers ADC2H and ADC2L when bit AD2INT is logic 1 Note that when Timer 2 or Timer overflows are used as the conversion source low byte overflows are used if the timer is in 8 bit mode and high byte overflows are used if the timer is in 16 bit mode See Section 24 Timers on page 287 for timer configuration e Rev 1 2 89 SILICON LABS C8051F060 1 2 3 4 5 6 7 7 2 2 Tracking Modes The AD2TM bit in register ADC2CN controls the ADC2 track and hold mode In its default state the ADC2 input is continuously tracked except when a conversion is in progress When the AD2TM bit is logic 1 ADC2 operates low power track and hold mode In this mode each conversion is preceded by a track ing period of 3 SAR clocks after the start of conversion signal When the CNVSTR2 signal is used to ini tiate conversions in low power tracking mode ADC2 tracks only when CNVSTR2 is low conversion begins on the rising edge of CNVSTR2 see Figure 7 3 Tracking can also be disabled shutdown when the device is in low power standby or
158. AL1 XTAL2 pins divided by 8 see Figure 24 14 When C Tn is set to logic 1 a high to low transition at the Tn input pin increments the counter timer register i e configured as a counter 24 2 1 Configuring Timer 2 3 and 4 to Count Down Timers 2 3 and 4 have the ability to count down When the timer s respective Decrement Enable Bit DCENn in the Timer Configuration Register See Figure 24 14 is set to 1 the timer can then count up or down When DCENn 1 the direction of the timer s count is controlled by the TnEX pin s logic level When TnEX 1 the counter timer will count up when 0 the counter timer will count down To use this feature must be enabled in the digital crossbar and configured as a digital input Note When DCENn 1 other functions of the TnEX input i e capture and auto reload are not available will only control the direction of the timer when DCENn 1 e Rev 1 2 295 SILICON LABS C8051F060 1 2 3 4 5 6 7 24 2 2 Capture Mode In Capture Mode Timer 2 3 and 4 will operate as a 16 bit counter timer with capture facility When the Timer External Enable bit found in the TMRnCN register is set to 1 a high to low transition on the TnEX input pin causes the 16 bit value in the associated timer THn TLn to be loaded into the capture registers RCAPnH RCAPnL If a capture is triggered in the counter timer the Timer External Flag TMRnCN 6 will be set
159. AO Data Address Beginning MSB Register SFR Page 3 SFR Address OxDA R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits 7 0 Address Beginning High Order Bits Figure 6 11 DMA0DAL Data Address Beginning LSB Register SFR Page 3 SFR Address 0xD9 R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits 7 0 Address Beginning Low Order Bits Figure 6 12 DMA0DSH Data Address Pointer MSB Register SFR Page 3 SFR Address 0xDG R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits 7 0 Address Pointer High Order Bits Figure 6 13 DMA0DSL Data Address Pointer LSB Register SFR Page 3 SFR Address 0xDB R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits 7 0 Address Pointer Low Order Bits 84 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 SFR Page 3 Figure 6 14 DMAO Repeat Counter Limit MSB Register SFR Address OxFA R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Bits 7 0 Repeat Counter Limit High Order Bits
160. ARTOEN 2 e e e e SPIOEN XBRO 1 e e e e NSS is not assigned to a port pin when the SPI is placed in 3 wire mode o o SMBOEN XBR0 0 ee e 1 XBR2 2 ee e e e e o XBRO 5 3 oo ooo e e 6 CPOE XBRO 7 1 1 1 0 2 6 6 6 0 06 CP2E XBR3 3 e e TOE XBR1 1 INTO INTOE XBR1 2 T1 1 1 3 INT1 6 XBR1 4 T2 2 1 5 2 e e 2 1 6 T3 e e XBR3 0 XBR3 1 o
161. ATL 0x04 Move the lower byte into data reg low byte Note CANOCN CANOSTA and CANOTST may be accessed either by using the index method or by direct access with the 51 SFRs is located at SFR location OxF8 SFR page 1 Figure 19 6 CANOTST at page 1 Figure 19 7 and CANOSTA at OxCO SFR page 1 Figure 19 8 19 2 6 CANOADR Autoincrement Feature For ease of programming message objects CANOADR features autoincrementing for the index ranges 0x08 to 0x12 Interface Registers 1 and 0x20 to 2 Interface Registers 2 When the CANOADR regis ter has an index in these ranges the CANOADR will autoincrement by 1 to point to the next CAN reg ister 16 bit word upon a read write of CANODATL This speeds programming of the frequently programmed interface registers when configuring message objects NOTE Table below supersedes Figure 5 in section 3 Programmer s Model of the Bosch CAN User s Guide Table 19 1 CAN Register Index and Reset Values Register name bead Notes 0x00 CAN Control Register 0x0001 Accessible CIP 51 SFR 0x01 Status Register 0 0000 Accessible in CIP 51 SFR Map 0x02 Error Register 0 0000 Read Only 0x03 Bit Timing Register 0 2301 Write Enabled by CCE Bit in CANOCN J Rev 1 2 229 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 19 1 CAN Register Index and Reset Values Continued
162. CAOMD register to be set to logic 1 0 Disabled 1 Enabled TOGn Toggle Function Enable This bit enables disables the toggle function for PCAO module n When enabled matches of the PCAO counter with a module s capture compare register cause the logic level on the CEXn pin to toggle If the PWMnh bit is also set to logic 1 the module operates in Frequency Output Mode 0 Disabled 1 Enabled PWMn Pulse Width Modulation Mode Enable This bit enables disables the PWM function for PCAO module n When enabled a pulse width modulated signal is output on the CEXn pin 8 bit PWM is used if PWM16n is logic 0 16 bit mode is used if PWM16n logic 1 If the TOGn bit is also set the module operates in Frequency Output Mode 0 Disabled 1 Enabled ECCFn Capture Compare Flag Interrupt Enable This bit sets the masking of the Capture Compare Flag CCFn interrupt 0 Disable CCFn interrupts 1 Enable a Capture Compare Flag interrupt request when CCFn is set 314 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 25 13 PCAUL PCAO Counter Timer Low Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0xF9 SFR Page 0 Bits 7 0 PCAOL Counter Timer Low Byte The PCAOL register holds the low byte LSB of the 16 bit PCAO Counter Timer Figure 25 14 PCAO Counter Timer High Byte
163. CF interrupt is enabled setting this bit causes the CPU to vector to the CCF interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software Bit3 PCAO Module 3 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF interrupt is enabled setting this bit causes the CPU to vector to the CCF interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software Bit2 CCF2 PCAO Module 2 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF interrupt is enabled setting this bit causes the CPU to vector to the CCF interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software Bit1 CCF1 Module 1 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF interrupt is enabled setting this bit causes the CPU to vector to the CCF interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software CCFO PCAO Module 0 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF interrupt is enabled setting this bit causes the CPU to vector to the CCF interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software 312 Rev 1 2 SILICON LABS C8051F060 1
164. CKCON 4 1 Counter Function Timer 1 incremented by high to low transitions on external input pin T1 55 4 1 1 1 0 Timer 1 Mode Select These bits select the Timer 1 operation mode T1M1 T1MO Mode 0 0 Mode 0 13 bit counter timer 0 1 Mode 1 16 bit counter timer 1 0 Mode 2 8 bit counter timer with auto reload 1 1 Mode 3 Timer 1 inactive Bit3 GATEO Timer 0 Gate Control 0 Timer 0 enabled when TRO 1 irrespective of INTO logic level 1 Timer 0 enabled only when TRO 1 AND INTO logic 1 Bit2 Counter Timer Select 0 Timer Function Timer 0 incremented by clock defined by TOM bit CKCON 3 1 Counter Function Timer 0 incremented by high to low transitions on external input pin TO 51 0 TOM1 TOMO Timer 0 Mode Select These bits select the Timer 0 operation mode TOM1 TOMO Mode 0 0 Mode 0 13 bit counter timer 0 1 Mode 1 16 bit counter timer 1 0 Mode 2 8 bit counter timer with auto reload 1 1 Mode 3 Two 8 bit counter timers 292 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 24 6 CKCON Clock Control Register R W R W R W R W R W R W Reset Value TOM SCAO 00000000 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0x8E SFR Page 0 UNUSED Read 000b Write don t care 1 Timer 1 Clock Select This select the clock source supplied to Timer 1 T1M is igno
165. CNVSTR Monitor reset Supply 09 Reset M 4 Timeout wired OR ceo D lt VDD Monitor Y mc Ies reset enable N D gt wired OR 0 enable Missing WDT Clock Detector one shot ad EN PRE se 58 58 Internal 25 25 26 Clock Generator Software Reset 51 xTAL2 DX e Microcontroller System Reset Core E Figure 1 6 On Board Clock and Reset Extended Interrupt Handler 26 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 1 2 On Chip Memory The CIP 51 has a standard 8051 program and data address configuration It includes 256 bytes of data RAM with the upper 128 bytes dual mapped Indirect addressing accesses the upper 128 bytes of general purpose RAM and direct addressing accesses the 128 byte SFR address space The CIP 51 SFR address space contains up to 256 SFR Pages In this way the CIP 51 MCU can accommodate the many SFRs required to control and configure the various peripherals featured on the device The lower 128 bytes of RAM are accessible via direct and indirect addressing The first 32 bytes are addressable as four banks of general purpose registers and the next 16 bytes can be byte addressable or bit addressable CIP 51 in the C8051 F060 1 2 3 4 5 6 7 MCUs additionally has an on chip 4 RAM block The on chip 4 kB block can be addressed over the entire 64 k external data memory address range ov
166. CON LABS C8051F060 1 2 3 4 5 6 7 Figure 16 2 C8051F066 7 Flash Program Memory Map and Security Bytes Readand Write Erase Security Bits SFLE 0 Bit7is MSB Memory Block Reserved NA NA 0x6000 0x7FFD 0x8000 0x4000 0x5FFF Read Lock Byte Ox7FFF 1 0x2000 0x3FFF Write EraseLockByte 0x7FFE 0x0000 0x1FFF Yd OX7 FFD FlashAccess Limit SFLE 1 0x007F 0x0000 0x0000 Program Data ScratchpadMemory Memory Space Dataonly Flash Read Lock Byte Bits7 0 Each bit locks a corresponding block of memory 0 Read operations are locked disabled for corresponding block across the JTAG interface 1 Read operations are unlocked enabled for corresponding block across the JTAG inter face Flash Write Erase Lock Byte Bits7 0 Each bit locks a corresponding block of memory 0 Write Erase operations are locked disabled for corresponding block across the JTAG interface 1 Write Erase operations are unlocked enabled for corresponding block across the JTAG interface NOTE When the block containing the security bytes is locked the security bytes may be written but not erased Flash Access Limit Register FLACL The Flash Access Limit is defined by the setting of the FLACL register as described in Figure 16 3 Firmware running at or above this address is prohibited from using the MOVX and MOVC instructions to read write or erase Flash locations below this address The Flash Access Limit security feature see
167. Compare Example Left Justified Differential Data ADC2H ADC2L ADC2H ADC2L Input Voltage Input Voltage 1 P1 y 1 P1 y VREF x 511 512 Ox7FCO ADEW INT AD2WINT 1 not affected 0x1040 0x1000 ADC2LTH ADC2LTL Ox1000 4 ADC2GTH ADC2GTL OxFCO AD2WINT AD2WINT 1 not affected 0x0000 OxFFCO OxFFCO ADC2GTH ADC2GTL ADC2LTH ADC2LTL OxFFE0 AD2WINT AD2WINT 1 not affected VREF 0x8000 100 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 7 1 ADC2 Electrical Characteristics VDD 3 0 V VREF 2 40 V REFSL 0 PGA Gain 1 40 C to 85 C unless otherwise specified Parameter Conditions Min Typ Max Units DC Accuracy Resolution 10 bits Integral Nonlinearity 0 5 1 LSB Differential Nonlinearity Guaranteed Monotonic 0 5 1 LSB Offset Error 12 1 2 LSB Full Scale Error Differential mode 15 5 5 LSB Offset Temperature Coefficient 3 6 ppm C DYNAMIC PERFORMANCE 10 kHz sine wave Differential inpu t 1 dB below Full Scale 200 ksps Signal to Noise Plus Distortion 53 55 5 dB Total Harmonic Distortion Up to the 5 harmonic 67 dB Spurious Free Dynamic Range 78 dB Conversion Rate SAR Conversion Clock 3 MHz Conversion Time in SAR Clocks 10 clocks Track Hold Acquisition Time 300 ns Throu
168. Convert Track B ADC Timing for Internal Trigger Sources SERIE SILICON LABS ADCnTM 1 Track Track Convert Track ADCnTM 0 Track Convert Track Figure 5 4 ADC Track and Conversion Example Timing Table 5 1 Conversion Timing ADnSC3 0 ADCnTM 0 ADCnTM 1 ADnSC3 0 ADCnTM 0 ADCnTM 1 0000 21 tsyscLK 38 tsyscLK 1000 171 tsvscik 315 0001 40 tsvsci k 72 tsyscLK 1001 189 349 0101 11 5 tsyscLK 211 ISYSCLK 1101 263 tevsci k 487 tevsci k Rev 1 2 55 C8051F060 1 2 3 4 5 6 7 5 3 3 Settling Time Requirements The ADC requires a minimum tracking time before an accurate conversion can be performed This tracking time is determined by the ADC input resistance the ADC sampling capacitance any external source resis tance and the accuracy required for the conversion Figure 5 5 shows the equivalent ADC input circuits for both Differential and Single ended modes Notice that the equivalent time constant for both input circuits is the same The required settling time for a given settling accuracy SA may be approximated by Equation 5 1 An absolute minimum tracking time of 280 ns is required prior to the start of a conversion n i 22 RroTALCsAMPLE Equation 5 1 ADCO Settling Time Requirements Where SA is the settling accuracy given as a fraction of
169. D VDD PORT OUTENABLE gt WEAK PORT X PAD PORT OUTPUT 7 Analog Select DGND Port 1 and 2 Only ANALOG INPUT gt lt gt lt PORT INPUT 1 Table 18 1 Port I O DC Electrical Characteristics VDD 2 7 to 3 6 V 40 to 85 unless otherwise specified Parameter Conditions Min Typ Max Units Output High Voltage 3 mA I O Push Pull VDD 0 7 V Vor 10 pA Port Push Pull VDD 0 1 Output Low Voltage lo 8 5 mA 0 6 V VoL lo 10 pA 0 1 Input High Voltage VIH 0 7 x VDD Input Low Voltage VIL 0 3 x VDD Input Leakage Current IDGND lt Port Pin lt VDD Pin Tri state Weak Pull up Off 1 Weak Pull up On 10 Input Capacitance 5 pF 1 2 203 SILICON LABS C8051F060 1 2 3 4 5 6 7 The C8051F06x family of devices have a wide array of digital resources which are available through the four lower I O Ports PO P1 P2 and on the C8051F060 2 4 6 Each of the pins on PO P1 P2 and can be defined as a General Purpose I O GPIO pin or can be controlled by a digital peripheral or function like UARTO or INT1 for example as shown in Figure 18 2 The system designer controls which digital functions are assigned pins limited only by the number of pins available This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder Note that the state of a Port I O pin can always be read from its associated Data register regardless of whet
170. D6 AV 11 P7 7 AD7m D7 CNVSTR1 12 VDD AVDD 13 C8051F060 F062 DGND AGND 14 P0 0 CNVSTRO 15 1 AV 16 2 AGND 17 AINO 18 P0 4 AINOG 19 P0 5 VRGNDO 20 6 21 P0 7 VBGAPO 22 P3 0 AGND 23 P3 1 AV 24 P3 2 DACO 25 P3 3 I fou St e S ISHS SHS SIS 9 8 N Z O i O m Q Fr ONZ c QN O F ON z z H sisi mW d mW d Z ce A o gt lt lt lt lt lt lt lt lt lt a ZNO DONES amp amp amp amp amp Figure 4 1 C8051F060 C8051F062 Pinout Diagram TQFP 100 Rev 1 2 45 SILICON LABS C8051F060 1 2 3 4 5 6 7 92 P4 6 RD P4 7 WR 90 VDD 89 DGND 5 7 15 80 P6 0 A8m A0 79 P6 1 A9m A1 RST 99 TDO 98 TDI 97 96 95 NC 94 NC 78 P6 2 A10m A2 77 6 11 76 P6 4 A12m A4 93 P4 5 ALE 88 5 0 8 87 P5 1 A9 86 P5 2 A10 85 5 11 84 P5 4 A12 83 P5 5 A13 82 P5 6 A14 91 81 NC 1 P6 5 A13m A5 NC 2 P6 6 A14m A6 NC 3 P6 7 A15m A7 VREF 4 P7 0 ADOm DO VBGAP1 5 P7 1 AD1m D1 VREF1 6 P7 2 AD2m D2 VRGND1 7 P7 3 AD3m D3 8 P7 4 AD4m D4 AIN1 9 P7 5 AD5m D5 AGND 10 P7 6 AD6m D6 AV 11 P7 7 AD7m D7 CNVSTR1 12 VDD AVDD 13 C8051F064 F066 DGND AGND 14 P0 0
171. DC Window Compare Example Right Justified Differential Data 100 Figure 7 18 ADC Window Compare Example Left Justified Differential Data 100 8 DACs 12 Bit Voltage Mode DACO and DAC1 C8051F060 1 2 3 103 Figure 8 1 DAC Functional Block Diagram one nante tuetur 103 Figure 8 2 DACOH DACO High Byte Register 105 Figure 8 3 DACO Low Byte Register 105 Figure 8 4 DACOCN DACO Control 106 Figure 8 5 DAC1H DAC1 High Byte Register 107 Figure 8 6 DAC1L DAC1 Low Byte Register 107 Figure 8 7 DACTCN DAC Control nna nra natn ntn 108 9 Voltage Reference 2 8051 060 2 4 2 2 1 2 2 111 Figure 9 1 Voltage Reference Functional Block Diagram 111 Figure 9 2 REF2CN Reference Control Register 2 112 10 Voltage Reference 2 8051 061 3 113 Figure 10 1 Voltage Reference Functional Block 113 Figure 10 2 REF2CN Reference Control Register 2
172. DC1 Conversion Complete Interrupt Flag This flag must be cleared by software 0 ADC1 has not completed a data conversion since the last time this flag was cleared 1 ADC1 has completed a data conversion Bit 4 AD1BUSY ADC1 Busy Bit Read 0 ADC1 Conversion is complete or a conversion is not currently in progress AD1INT is set to logic 1 on the falling edge of AD1BUSY 1 ADC1 Conversion is in progress Write 0 No Effect 1 Initiates ADC1 Conversion if AD1CM2 0 000b Bits 3 1 AD1CM2 0 ADC1 Start of Conversion Mode Select If AD1TM 0 000 ADC1 conversion initiated on every write of 1 to AD1BUSY 010 ADC1 conversion initiated on overflow of Timer 3 100 ADC1 conversion initiated on rising edge of external CNVSTR1 110 ADC1 conversion initiated on overflow of Timer 2 xx1 ADC1 conversion initiated on every write of 1 to ADOBUSY ADCOCN If AD1TM 1 000 Tracking starts with the write of 1 to AD1BUSY and is followed by the conversion 010 Tracking started by the overflow of Timer 3 and is followed by the conversion 100 ADC1 conversion starts on rising CNVSTR1 edge 110 Tracking started by the overflow of Timer 2 and is followed by the conversion xx1 Tracking starts with the write of 1 to ADOBUSY and is followed by the conversion See Figure 5 4 and Table 5 1 for conversion timing parameters Bit 0 RESERVED Write to Ob e Rev 1 2 61 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 5 11
173. DC1 Specification for complete description CNVSTRO 15 9 15 9 External Conversion Start Source for ADCO CNVSTR1 12 8 12 8 External Conversion Start Source for ADC1 CANTX 94 59 D Out Controller Area Network Transmit Output CANRX 95 60 D In Area Network Receive Input DACO 25 17 A Out Digital to Analog Converter 0 Voltage Output See DAC Specification for complete description DAC1 1 64 A Out Digital to Analog Converter 1 Voltage Output See DAC Specification for complete description P0 0 62 51 62 51 D Port 0 0 See Input Output section for complete description 1 61 50 61 50 D Port 0 1 See Port Input Output section for complete description P0 2 60 49 60 49 D Port 0 2 See Port Input Output section for complete description P0 3 59 48 59 48 D Port 0 3 See Port Input Output section for complete description P0 4 58 47 58 47 D Port 0 4 See Port Input Output section for complete description 40 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 4 1 Pin Definitions Continued Pin Numbers Name 060 F061 064 F065 Type Description F062 F063 F066 F067 0 5 57 46 57 46 D Port 0 5 Input Output section for complete description 6 56 45 56 45 D Port 0 6 Input Output section for complete description 7
174. DC2 operates in both Single ended and Differential modes and may be configured to mea sure any of the pins on Port 1 or the Temperature Sensor output The ADC2 subsystem is enabled only when the AD2EN bit in the ADC2 Control register ADC2CN is set to logic 1 The ADC2 subsystem is in low power shutdown when this bit is logic O Figure 7 1 ADC2 Functional Block Diagram ADC2GTH ADC2GTL ADC2LTH ADC2LTL 20 Comb Logic p AD2WINT AIN2 0 D lt AIN2 1 D lt SYSCLK AIN2 2 D lt AIN2 3 D lt AIN2 4 D lt AIN2 5 D lt AIN2 6 D lt AIN2 7 D lt 00 AD2BUSY W Start Conversion 01 Timer Overflow n ii E 10 CNVSTR2 lt o gt Oooo 11 Timer 2 Overflow sisi 25525550 ko t No ko o cp cp D 2 1656213 lt lt lt 5225 8888868868 z EEEE KK lt lt lt lt lt lt lt c lt lt lt lt lt 2 AMX2SL ADC2CF ADC2CN Q e Rev 1 2 87 SILICON LABS C8051F060 1 2 3 4 5 6 7 7 1 Analog Multiplexer The analog multiplexer AMUX2 selects the inputs to the ADC allowing any of the pins on Port 1 to be measured in single ended mode or as a differential pair Additionally the on chip te
175. Data Word MSB Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address OXBF SFR Page 0 Bits 7 0 ADCO Data Word High Order Bits Figure 5 14 ADCOL ADCO Data Word LSB Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address SFR Page 0 Bits 7 0 ADCO Data Word Low Order Bits Rev 1 2 63 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 5 15 ADCO Data Word Example 16 bit ADCO Data Word appears in the ADCO Data Word Registers as follows Example ADCO Data Word Conversion Map AINO Input in Single Ended Mode AMXOSL 0x00 AINO AINOG Volts ADCOH ADCOL VREF 65535 65536 OxFFFF VREF 2 0x8000 VREF 32767 65536 Ox7FFF 0 0x0000 Example ADCO Data Word Conversion Map AINO AIN1 Differential Input Pair AMXOSL 0x40 AINO AIN1 Volts ADCOH ADCOL VREF 32767 32768 Ox7FFF VREF 2 0x4000 VREF 1 32768 0x0001 0 0x0000 VREF 1 32768 OxFFFF VREF 2 0xC000 VREF 0x8000 Code Vinx X2 n 16 for Single Ended 15 for Differential VREF 64 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 5 16 ADC1H ADC1 Data Word MSB Register R W R W R W R W R W R W R W R W Reset Val
176. E 5 ADCO Data Overflow Warning DMAOCN 0 DMAODOO occurs when data from ADC1 becomes available and the DMA has not yet written the previous results to XRAM This inter rupt source can be enabled and disabled with the Data Overflow Warning Enable bit DMAOCN 2 DMAODOE 6 Repeat Counter Overflow DMAOCF 2 DMAOCI occurs when the Repeat Counter reaches the Repeat Counter Limit This interrupt source can be enabled and disabled with the Repeat Counter Overflow Interrupt Enable bit DMAOCF 3 DMAOCIE 7 End Of Operation DMAOCF 0 DMAOEO occurs when an End Of Operation instruction is reached in the Instruction Buffer This interrupt source can be enabled and disabled with the End Of Operation Interrupt Enable bit DMAOCF 1 DMAOEOE 6 7 Data Buffer Overflow Warnings and Errors The data paths from the ADCs to XRAM are double buffered when using the DMA interface When a con version is completed by the ADC it first enters the ADCs data register If the DMA s data buffer is empty the conversion results will immediately be written into the internal data buffer for that ADC Data in the DMA s internal data buffer is written to XRAM at the first available opportunity see Section 6 3 XRAM Addressing and Setup on page 76 Conversion results from the ADC s data registers are not copied into the data buffer until data in the buffer has been written to XRAM When a conversion is completed and the DMA s data buffer is not emp
177. Ec CNVSTR x Ctrl Latch DRV Eu 0 EMIF 5 AN A D Control Address Bus P5Latch gt P5 0 1 DMA Addi 15 8 DRV P 57 Interface 54 1 D F P6Latch F6 gt P6 0 DRV m 1 Addr 7 0 PE 567 P7Latch 27 0 amie Data Bus AV ds T CNVSTRL Figure 1 1 C8051F060 C8051F062 Block Diagram Rev 1 2 21 SILICON LABS C8051F060 1 2 3 4 5 6 7 VDD z VDD PO 04 20 0 VDD DigitalPower Drv e U 8 DGND Analog Power UART1 0 SFR Bus 1 0 SPIBus s P1 7 ms B JTAG y AIN2 7 B Logic Debug HW B gt E 22 0 mo B 1 Timers A s yest B Reset R MONEN VDDMonitor 2 64kbyte i FLASH xTaL2 Circuit System Clock 32X136 Trimmedinternal CANRAM Oscillator P2 7 1 2 Latches 59 VREF VREF EE 7 256 byte o HOG DACO 4kbyte RAM AVDD AGND AV AGND VREFO VRGNDO 5 External Data Memory Bus AINO AINOG EMIF Control DMA Interface AIN1G CNVSTRL Figure 1 2 C8051F061 C8051F063 Block Diagram 22 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 VDD P0 0 Digital Power PO UARTO DGND _ Drv z DGND Analog Power UARTI SFR Bus SMBus 1 4 1 0 i gp1 7 SPI Bus P2 0 Memory 1 2 3 4 JTAG Boundary
178. F C VDD KF 50 3 f KF 150 If a frequency of roughly 50 kHz is desired select the Factor from the table in Figure 15 5 as KF 7 7 f 7 7 150 0 051 MHz or 51 kHz Therefore the XFCN value to use in this example is 010 e Rev 1 2 175 SILICON LABS C8051F060 1 2 3 4 5 6 7 176 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 16 Flash Memory The C8051 F060 1 2 3 4 5 6 7 devices include on chip reprogrammable Flash memory for program code and non volatile data storage The C8051F060 1 2 3 4 5 include 64 k 128 bytes of Flash and the C8051F066 7 include 32 k 128 bytes of Flash The Flash memory can be programmed in system a sin gle byte at a time through the JTAG interface or by software using the MOVX write instructions Once cleared to logic 0 a Flash bit must be erased to set it back to logic 1 The bytes would typically be erased set to OxFF before being reprogrammed Flash write and erase operations are automatically timed by hardware for proper execution data polling to determine the end of the write erase operation is not required The CPU is stalled during write erase operations while the device peripherals remain active Interrupts that occur during Flash write erase operations are held and are then serviced in their priority order once the Flash operation has completed Refer to Table 16 1 for the electrical characteristics of the Flash memory 16 1 Programming The Flash Memory T
179. FFFF BYPASS Selects Bypass Data Register Selects FLASHCON Register to control how the interface logic responds to reads and writes to the FLASHDAT Register 0x0083 Flash Data Selects FLASHDAT Register for reads and writes to the Flash memory 0 0084 Flash Address Selects FLASHADR Register which holds the address of all Flash read write and erase operations Selects FLASHSCL Register which controls the Flash one shot timer and read always enable 0x0082 Flash Control 0 0085 Flash Scale e Rev 1 2 317 SILICON LABS C8051F060 1 2 3 4 5 6 7 26 1 Boundary Scan The DR in the Boundary Scan path is a 126 bit shift register for the C8051F060 2 4 6 and a 118 bit shift register for the C8051F061 3 5 7 The Boundary DR provides control and observability of all the device pins as well as the SFR bus and Weak Pullup feature via the EXTEST and SAMPLE commands Table 26 1 Boundary Data Register Bit Definitions C8051F060 2 4 6 EXTEST provides access to both capture and update actions while Sample only performs a capture Bit Action Target 0 Capture Reset Enable from MCU Update Reset Enable to RST 1 Capture Reset Input from RST pin Update Not used 2 Capture CAN RX Output Enable to pin Update RX Output Enable to 3 Capture CAN RX Input from
180. Figure 16 3 protects proprietary program code and data from being read by software running on the C8051F060 1 2 3 4 5 6 7 This feature provides support for OEMs that wish to program the MCU with proprietary value added firmware before distribution The value added firmware can be protected while allowing additional code to be programmed in remaining program memory space later The Flash Access Limit FAL is a 16 bit address that establishes two logical partitions in the program memory space The first is an upper partition consisting of all the program memory locations at or above the FAL address and the second is a lower partition consisting of all the program memory locations start e Rev 1 2 181 SILICON LABS C8051F060 1 2 3 4 5 6 7 ing at 0x0000 up to but excluding the FAL address Software in the upper partition can execute code in the lower partition but is prohibited from reading locations in the lower partition using the MOVC instruc tion Executing a MOVC instruction from the upper partition with a source address in the lower partition will always return a data value of 0x00 Software running in the lower partition can access locations in both the upper and lower partition without restriction The Value added firmware should be placed in the lower partition On reset control is passed to the value added firmware via the reset vector Once the value added firmware completes its initial execution it branches to a pred
181. L OxBB 2 ADC2 Analog Multiplexer Channel Select page 93 5 CANOADR OxDA 1 CANO Address page 23275 OxF8 1 CANO Control page 23075 CANODATH OxD9 1 CANO Data High page 2315 CANODATL OxD8 1 CANO Data Low page 231 75 0 0 1 Status page 233 5 CANOTST OxDB 1 CANO Test page 233 CKCON 0 8 0 Clock Control page 293 CLKSEL 0x97 F Oscillator Clock Selection Register page 173 CPTOCN 0x88 1 Comparator 0 Control page 120 CPTOMD 0x89 1 Comparator 0 Configuration page 121 0 88 2 Comparator 1 Control page 120 CPT1MD 0x89 2 Comparator 1 Configuration page 121 CPT2CN 0x88 3 Comparator 2 Control page 120 Rev 1 2 143 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 13 3 Special Function Registers Continued SFRs are listed in alphabetical order All undefined SFR locations are reserved Register Address SFR Page Description Page No CPT2MD 0x89 3 Comparator 2 Configuration page 121 DACOCN OxD4 0 DACO Control page 1065 DACOH 0xD3 0 High page 105 5 DACOL 0xD2 0 DAC0 Low page 105 DAC1CN 0xD4 1 DAC1 Control page 1085 DAC1H 0xD3 1 DAC1 High page 107 DAC1L 0xD2 1 DAC1 Low page 1075 OxFD 3 DMAO Instruction Boundary page 83 DMAOCF OxF8 3 DMAO Configuration page 81 DMAOCN OxD8 3 DMAO Control page 80 DMAOCSH OxFC 3 DMAO Repeat Co
182. Momentarily clearing the ENSMB flag and then resetting it to logic 1 will reset SMBusO communication However ENSMB should not be used to tempo rarily remove a device from the bus since the bus state information will be lost Instead the Assert Acknowledge AA flag should be used to temporarily remove the device from the bus see description of AA flag below Setting the Start flag STA SMBOCN 5 to logic 1 will put SMBusO in a master mode If the bus is free SMBus0 will generate START condition If the bus is not free SMBusO waits for a STOP condition to free the bus and then generates a START condition after a 5 us delay per the SMBOCR value In accordance with the SMBus protocol the SMBusO interface also considers the bus free if the bus is idle for 50 us and no STOP condition was recognized If STA is set to logic 1 while SMBusO is in master mode and one or more bytes have been transferred a repeated START condition will be generated When the Stop flag STO SMBOCN 4 is set to logic 1 while the SMBusO interface is in master mode the interface generates a STOP condition In a slave mode the STO flag may be used to recover from an error condition In this case a STOP condition is not generated on the bus but the SMBus hardware behaves as if a STOP condition has been received and enters the not addressed slave receiver mode Note that this simulated STOP will not cause the bus to appear free to SMBus0 The bus will remain occupied unt
183. N Controller Figure 19 2 Typical CAN Bus Configuration CAN Protocol Device CAN Protocol Device CAN CAN Transceiver Transceiver ation Buffer Optional ation Buffer Optional CAN Transceiver ation Buffer Optional Isol Isol Isol CAN L 226 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 19 1 Bosch CAN Controller Operation The CAN Controller featured in the C8051F060 1 2 3 devices is a full implementation of Bosch s full CAN module and fully complies with CAN specification 2 0B The function and use of the CAN Controller is detailed in the Bosch CAN User s Guide The User s Guide should be used as a reference to configure and use the CAN controller This Silicon Labs datasheet describes how to access the CAN controller The CAN Control Register CANOCN CAN Test Register CANOTST and CAN Status Register CANOSTA in the CAN controller can be accessed directly or indirectly via CIP 51 SFRs All other CAN registers must be accessed via an indirect indexing method See Using CANOADR CANODATH and CANDATL To Access CAN Registers on page 229 e Rev 1 2 227 SILICON LABS C8051F060 1 2 3 4 5 6 7 19 2 CAN Registers CAN registers are classified as follows 1 CAN Controller Protocol Registers CAN control interrupt error control bus status test modes 2 Message Object Interface Regist
184. N67IC AIN45IC AIN23IC 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Bits 7 4 UNUSED Read 0000b Write don t care Bit 3 AIN67IC AIN2 6 AIN2 7 Input Pair Configuration Bit 0 AIN2 6 and AIN2 7 are independent single ended inputs 1 AIN2 6 and AIN2 7 are a differential input pair Bit 2 AIN45IC AIN2 4 AIN2 5 Input Pair Configuration Bit 0 AIN2 4 and AIN2 5 are independent single ended inputs 1 AIN2 4 and AIN2 5 are a differential input pair Bit 1 2 AIN2 2 AIN2 3 Input Pair Configuration Bit 0 AIN2 2 and AIN2 3 are independent single ended inputs 1 AIN2 2 and AIN2 3 are a differential input pair Bit 0 AIN2 0 AIN2 1 Input Pair Configuration Bit 0 AIN2 0 and AIN2 1 are independent single ended inputs 1 AIN2 0 and AIN2 1 are a differential input pair NOTE ADC2 Data Word is in the 25 complement format for channels configured as differen tial The polarity of a differential measurement is determined by the AMX2SL setting See Figure 7 5 for more details on multiplexer channel selection 92 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 7 6 AMX2SL AMUX2 Channel Select Register SFR Page 2 SFR Address R W R W R W R W R W R W R W R W Reset Value AMX2AD3 AMX2AD2 AMX2AD1 AMX2ADO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Bits 7 4 UNUSED Read 0000b Write don t
185. OUT 3 to logic 1 All port pins default to open drain mode upon device reset 18 2 3 Configuring Port Pins as Digital Inputs A Port pin is configured as a digital input by setting its output mode to Open Drain and writing a logic 1 to the associated bit in the Port Data register For example P7 7 is configured as a digital input by setting P7MDOUT 7 to a logic 0 and P7 7 to a logic 1 18 2 4 Weak Pull ups By default each Port pin has an internal weak pull up device enabled which provides a resistive connec tion about 100 between the pin and VDD The weak pull up devices can be globally disabled by writ e Rev 1 2 219 SILICON LABS C8051F060 1 2 3 4 5 6 7 ing a logic 1 to the Weak Pull up Disable bit WEAKPUD XBR2 7 The weak pull up is automatically deactivated on any pin that is driving a logic 0 that is an output pin will not contend with its own pull up device 18 2 5 External Memory Interface If the External Memory Interface is enabled on the High ports and an off chip MOVX operation occurs the External Memory Interface will control the output states of the affected Port pins during the execution phase of the MOVX instruction regardless of the settings of the Port Data registers The output configura tion of the Port pins is not affected by the EMIF operation except that Read operations will explicitly dis able the output drivers on the Data Bus during the MOVX execution See Section 17 External
186. On receive the eight data bits are stored in SBUFO and the stop bit goes into RB80 SCONO 2 Data transmission begins when an instruction writes a data byte to the SBUFO register The TIO Transmit Interrupt Flag SCONO 1 is set at the end of the transmission the beginning of the stop bit time Data reception can begin any time after the RENO Receive Enable bit SCONO 4 is set to logic 1 After the stop bit is received the data byte will be loaded into the SBUFO receive register if the following conditions are met RIO must be logic 0 and if SM20 is logic 1 the stop bit must be logic 1 If these conditions are met the eight bits of data is stored in SBUFO the stop bit is stored in RB80 and the RIO flag is set If these conditions are not met SBUFO and RB80 will not be loaded and the RIO flag will not be set An interrupt will occur if enabled when either TIO or RIO are set Figure 22 4 UARTO Mode 1 Timing Diagram MARK START DO D1 D2 D3 04 05 06 D7 STOP SPACE BIT 5 T T 4 BITSAMPLING l Rev 1 2 267 SILICON LABS C8051F060 1 2 3 4 5 6 7 The baud rate generated in Mode 1 is a function of timer overflow UARTO can use Timer 1 operating in 8 Bit Auto Reload Mode or Timer 2 3 or 4 operating in Auto reload Mode to generate the baud rate note that the TX and RX clocks are selected separately On each timer overflow event a rollover f
187. PCA Interrupt Block Diagram PCAOMD P E C C M T P E F R C C C C C C MIOIP P T G M C S S S F ag pia 51413 21110 2110 Y Timer Overllow oe EPCAO EA PCA Module 0 ra d g e Interrupt e oo PCA Module 1 oo ECCF2 PCA Module 2 oon PCA Module 3 oe PCA Module 4 oe PCA Module 5 oe 1 2 305 SILICON LABS C8051F060 1 2 3 4 5 6 7 25 2 1 Edge triggered Capture Mode In this mode a valid transition on the CEXn pin causes PCAO to capture the value of the PCAO counter timer and load it into the corresponding module s 16 bit capture compare register PCAOCPLn and PCAOCPHn The and CAPNn bits in the PCAOCPMn register are used to select the type of transi tion that triggers the capture low to high transition positive edge high to low transition negative edge or either transition positive or negative edge When a capture occurs the Capture Compare Flag CCFn in PCAOCN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by software Figure 25 4 PCA Capture Mode Diagram PCA Interrupt
188. PIO master transfers data to a slave on the MOSI line the addressed SPI slave device simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full duplex operation Therefore the SPIF flag serves as both a transmit complete and receive data ready flag The data byte received from the slave is transferred MSB first into the master s shift register When a byte is fully shifted into the register it is moved to the receive buffer where it can be read by the processor by reading SPIODAT When configured as a master SPIO can operate in one of three different modes multi master mode 3 wire single master mode and 4 wire single master mode The default multi master mode is active when NSS MD1 SPIOCN 3 0 and NSSMDO SPIOCN 2 1 In this mode NSS is an input to the device and is used to disable the master SPIO when another master is accessing the bus When NSS is pulled low in this mode MSTEN SPIOCN 6 and SPIEN 0 are set to 0 to disable the SPI master device and a Mode Fault is generated MODF SPIOCN 5 1 Mode Fault will generate an interrupt if enabled SPIO must be manually re enabled in software under these circumstances In multi master systems devices will typically default to being slave devices while they are not acting as the system master device In multi mas ter mode slave devices can be addressed individually if needed using general purpose l O pins Figure 21 2 shows a c
189. R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xDA SFR Page 1 Bit7 0 CANOADR CAN Address Index Register The CANOADR Register is used to point the CANODATH CANODATL to a desired CAN Register The desired CAN Register s index number is moved into CANOADR The CANODAT Register can then read write to and from the CAN Register Note When the value of CANOADR is 0x08 0x12 and 0x20 2A IF1 and IF2 registers this register will autoincrement by 1 upon a write to CANODATL See Section 19 2 6 CANOADR Autoincrement Feature on page 229 All CAN registers functions definitions are listed and described in the Bosch CAN User s Guide Figure 19 6 CANOCN CAN Control Register R W R W R W R R W R W R W R W Reset Value CANIF Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0xF8 SFR Page 1 Bit 4 CANIF CAN Interrupt Flag Write don t care 0 CAN interrupt has not occured 1 CAN interrupt has occured and is active CANIF is controlled by the CAN controller and is cleared by hardware once all interrupt con ditions have been cleared in the CAN controller See section 3 4 1 in the Bosch CAN User s Guide page 24 for more information concerning CAN controller interrupts All CAN registers functions definitions are listed and described in the Bosch CAN User s Guide with the exception of the CANIF bit This register may be acces
190. SADENO 11000000 Broadcast Broadcast Broadcast Address 00111111 Address 11110111 Address 11110101 Where ZEROES in the Broadcast address are don t cares Note in the above examples 4 5 and 6 each slave would recognize as valid an address of OxFF as a broadcast address Also note that examples 4 5 and 6 uses the same SADDRO and SADENO register values as shown in the examples 1 2 and 3 respectively slaves 1 2 and 3 Thus a master could address each slave device individually using a masked address and also broadcast to all three slave devices For example if a Master were to send an address 11110101 only slave 1 would recognize the e Rev 1 2 271 SILICON LABS C8051F060 1 2 3 4 5 6 7 address as valid If a master were to then send an address of 11111111 all three slave devices would rec ognize the address as a valid broadcast address Figure 22 7 UART Multi Processor Mode Interconnect Diagram Slave Device Master Slave Slave Device Device Device OOO RX TX RX TX 22 3 Frame and Transmission Error Detection All Modes The Transmit Collision bit TXCOLO bit in register SCONO reads 1 if user software writes data to the SBUFO register while a transmit is in progress Note that the TXCOLO bit is also used as the SM20 bit when written by user software This bit does not generate an interrupt Modes 1 2 and 3 The Receive Overrun bit RXOVO in register SCONO reads
191. SFR Address RCAP2H 0xCB RCAP3H 0xCB RCAP4H 0xCB SFR Page RCAP2H page 0 RCAP3H page 1 RCAP4H page 2 Bits 7 0 RCAP2 3 and Timer 2 3 and 4 Capture Register High Byte The RCAP2 3 and register captures the high byte of Timer 2 3 and 4 when Timer 2 3 and 4 is configured in capture mode When Timer 2 3 and 4 is configured in auto reload mode it holds the high byte of the reload value Figure 24 17 TMRnL Timer 2 3 and 4 Low Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address TMR2L 0xCC TMR3L 0xCC TMR4L OxCC SFR Page 21 0 TMR3L 1 TMR4L page 2 Bits 7 0 TL2 and 4 Timer 2 4 Low Byte The TL2 3 and 4 register contains the low byte of the 16 bit Timer 2 3 and 4 e Rev 1 2 301 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 24 18 TMRnH Timer 2 3 and 4 High Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address TMR2H 0xCD TMR3H 0xCD TMR4H 0xCD SFR Page TMR2H page 0 TMR3H page 1 TMR4H page 2 Bits 7 0 2 3 and 4 Timer 2 3 and 4 High Byte 2 3 and 4 register contains the high byte of the 16 bit Timer 2 3 and 4 302 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 25 Programmable Counter Array The Pro
192. SFRLAST SFR Last Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0x86 SFR Page All Pages Bits7 0 SFR Page Stack Bits SFR page context is retained upon interrupts return from interrupts in a 3 byte SFR Page Stack SFRPAGE is the first entry SFRNEXT is the second and SFR LAST is the third entry The SFR stack bytes may be used to alter the context in the SFR Page Stack and will not cause the stack to push or pop Only interrupts and return from interrupt cause push and pop the SFR Page Stack Write Sets the SFR Page in the last entry of the SFR Stack This will cause the SFRNEXT SFR to have this SFR page value upon a return from interrupt Read Returns the value of the SFR page contained in the last entry of the SFR stack 140 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 13 2 Special Function Register SFR Memory Map A D D R 0 8 1 9 2 A 3 B 4 C 5 D 6 E E 5 5 SPIOCN PCAOL PCAOH 0 PCAOCPL1 CANOCN F8 DMAOCF DMAOCTL DMAOCTH DMAOCSL DMAOCSH DMAOBND DMAOISW P7 B FO ALL PAGES 2 2 PCAOCPL3 4 PCAOCPH4 RSTSRO 5
193. SILICON LABS SFRPAGE SFRNEXT SFRLAST SSS RA interrupt Automatically popped off of the stack on return from SFR Page 0x02 SFRNEXT popped to Figure 13 8 SFR Page Stack Upon Return From ADC2 Window Interrupt SFRPAGE On the execution of the RETI instruction in the ADC2 Window Comparator ISR the value in SFRPAGE register is overwritten with the contents of SFRNEXT The CIP 51 may now access the Port 5 SFR bits as it did prior to the interrupts occurring See Figure 13 8 below C8051F060 1 2 3 4 5 6 7 SILICON LABS Note that in the above example all three bytes in the SFR Page Stack are accessible via the SFRPAGE Rev 1 2 SFRNEXT and SFRLAST special function registers If the stack is altered while servicing an interrupt it is interrupt exit execution on the RETI instruction The automatic switching of the SFRPAGE and operation of the SFR Page Stack as described above can be disabled in software by clearing the SFR Automatic Page Enable Bit SFRPGEN in the SFR Page Control Register SFRPGON See Figure 13 9 access to the SFR Page stack can be useful to enable real time operating systems to control and manage Push operations on the SFR Page Stack only occur on interrupt service and pop operations only occur on possible to return to a different SFR Page upon interrupt exit than selected prior to the interrupt call Direct context switching between multiple ta
194. SILICON LABS C8051F060 1 2 3 4 5 6 7 8K ISP FLASH MCU Family Analog Peripherals Two 16 Bit SAR ADCs 16 bit resolution 0 75 LSB INL guaranteed missing codes Programmable throughput up to 1 Msps Operate as two single ended or one differential con verter Direct memory access data stored in RAM without software overhead Data dependent windowed interrupt generator 10 bit SAR ADC C8051F060 1 2 3 Programmable throughput up to 200 ksps 8 external inputs single ended or differential Built in temperature sensor Two 12 bit DACs C8051F060 1 2 3 Can synchronize outputs to timers for jitter free wave form generation Three Analog Comparators Programmable hysteresis response time Voltage Reference Precision VDD Monitor Brown Out Detector On Chip JTAG Debug amp Boundary Scan On chip debug circuitry facilitates full speed non intrusive in circuit in system debugging Provides breakpoints single stepping watchpoints stack monitor inspect modify memory and registers Superior performance to emulation systems using ICE chips target pods and sockets IEEE1149 1 compliant boundary scan Complete development kit High Speed 8051 uC Core Pipelined instruction architecture executes 70 of instruction set in 1 or 2 system clocks Upto 25 MIPS throughput with 25 MHz clock Flexible Interrupt sources Memory 4352 Bytes internal data RAM 4 256 64
195. T2E ADC2 External Convert Start Input Enable Bit 0 CNVST2 for unavailable at Port pin 1 CNVST2 for ADC2 routed to Port pin Bit1 Input Enable Bit 0 unavailable at Port pin 1 routed to Port pin Bito T3E T3 Input Enable Bit 0 T3 unavailable at Port pin 1 T3 routed to Port pin e Rev 1 2 213 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 18 9 0 Data Register R W R W R W R W R W R W R W R W Reset Value P0 7 P0 6 P0 5 P0 4 P0 3 P0 2 P0 1 P0 0 11111111 Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Addressable SFR Address 0x80 SFR Page All Pages Bits7 0 7 0 PortO Output Latch Bits Write Output appears on I O pins XBRO XBR1 XBR2 Registers 0 Logic Low Output 1 Logic High Output open if corresponding POMDOUT n bit 0 Read Regardless XBR2 and XBR3 Register settings 0 pin is logic low 1 PO n pin is logic high Figure 18 10 POMDOUT PortO Output Mode Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit SFR Address 4 SFR Page F Bits7 0 POMDOUT 7 0 PortO Output Mode Bits 0 Port Pin output mode is configured as Open Drain 1 Port Pin output mode is configured as Push Pull Note SDA SCL and RX0 when UAR
196. TO Chapter Updated and clarified baud rate equations Port I O Chapter Section 18 2 Added a note in text body that Port 4 7 registers are all on SFR Page F Comparators Chapter Updated Table 12 1 Comparator Electrical Characteristics e CIP51 Chapter Section 13 4 1 Added note regarding IDLE mode operation e ADC2 Chapter AD2LJST bit removed from ADC2CF register description AD2LJST is in the ADC2CN register e ADC2 Chapter Updated Table 7 1 ADC2 Electrical Characteristics and Figure 7 2 Temperature Sen sor Transfer Function with temperature sensor information e ADCO ADC1 Chapter Tracking Conversion timing when ADnTM 1 is shown in Figure 5 4 and Table 5 1 References to 18 or 16 SAR clocks of tracking were removed e DACs Chapter Table 8 1 DAC Electrical Characteristics Changed Gain Error to Full Scale Error e SMBus Chapter Figure 20 9 SMBOCR Changed 1 125 to 1 125 10 6 Chapter Figure 25 12 PCAOCPMn Bit 0 name changed to ECCFn from incorrect EECFn JTAG Chapter Figure 26 3 FLASHCON Bit 7 description corrected Bit 7 is SFLE allowing access to the Scratchpad memory area Chapter Added text The CAN controller s clock CAN CLK in the CAN User s Guide is equal to the 51 MCU s clock SYSCLK Table 4 1 Pin Descriptions MONEN Added text Recommended configuration is to connect directly to VDD e Timers Chapte
197. TO is in Mode 0 and RX1 when is in Mode 0 are always configured as Open Drain when they appear on Port pins 214 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 18 11 P1 Port Data Register R W R W R W R W R W R W R W R W Reset Value P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 11111111 Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Ad ressabl SFR Address 0x90 SFR Page All Pages Bits7 0 1 7 0 Porti Output Latch Bits Note R W Write Output appears pins XBRO XBR1 XBR2 and XBR3 Registers 0 Logic Low Output 1 Logic High Output open if corresponding P1MDOUT n bit 0 Read Regardless of XBRO XBR1 XBR2 and XBR3 Register settings 0 P1 n pin is logic low 1 P1 n pin is logic high On the C8051 F060 1 2 3 P1 7 0 can be configured as inputs to ADC2 as AIN2 7 0 in which case they are skipped by the Crossbar assignment process and their digital input paths are disabled depending on P1MDIN See Figure 18 12 Note that in analog mode the output mode of the pin is determined by the Port 1 latch and P1MDOUT Figure 18 13 See Section 7 10 Bit ADC2 8051 060 1 2 3 on page 87 for more information about ADC2 Figure 18 12 P1MDIN Porti Input Mode Register R W R W R W R W R W R W R W Reset Value 11111111 Bit7 Bits7 0 6 Bit5 Bit4 B
198. Value 0 0 BIASE REFBE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xD1 SFR Page 2 Bits7 4 UNUSED Read 0000b Write don t care Bits2 3 RESERVED Must Write to 00b Bit1 BIASE ADC DAC Bias Generator Enable Bit Must be 1 if using ADC2 or DACs 0 Internal Bias Generator Off 1 Internal Bias Generator On REFBE Internal Reference Buffer Enable Bit 0 Internal Reference Buffer Off 1 Internal Reference Buffer On Internal voltage reference is driven on the VREF pin Table 11 1 Voltage Reference Electrical Characteristics VDD 3 0 V AV 3 0 V 40 to 85 C unless otherwise specified Parameter Conditions Min Typ Max Units Internal Reference REFBE 1 Output Voltage 25 ambient 2 36 2 43 2 48 V VREF Power Supply Current 50 VREF Short Circuit Current 30 mA VREF Temperature Coefficient 15 ppm C Load Regulation Load 0 to 200 HA to AGND 0 5 VREF Turn on Time 1 4 7 uF tantalum 0 1 ceramic 2 ms bypass VREF Turn on Time 2 0 1 ceramic bypass 20 us VREF Turn on Time 3 no bypass cap 10 us 116 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 12 Comparators C8051F06x family of devices include three on chip programmable voltage comparators shown in Figure 12 1 Each comparator offers programmable response time and hysteresis When assigned to a Port pin the Comparator output
199. YN1 0 10 7 10 15 mV Negative Hysteresis 4 CPnHYN1 0 11 15 20 25 mV Inverting or Non Inverting 0 25 VDD V Input Voltage Range 0 25 Input Capacitance 7 pF Input Bias Current 5 0 001 5 Input Offset Voltage 5 5 mV Power Supply Power Supply Rejection 0 1 1 Power up Time 10 us Mode 0 7 6 Supply Current at DC ES Mode 2 1 3 Mode 3 0 4 122 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 13 51 Microcontroller The MCU system controller core is the CIP 51 microcontroller The CIP 51 is fully compatible with the MCS 51 instruction set standard 803x 805x assemblers and compilers can be used to develop soft ware The MCU family has a superset of all the peripherals included with a standard 8051 Included are five 16 bit counter timers see description in Section 24 two full duplex UARTs see description in Section 22 and Section 23 256 bytes of internal RAM 128 byte Special Function Register SFR address space see Section 13 2 6 and 59 24 General Purpose I O Pins see description in Section 18 The CIP 51 also includes on chip debug hardware see description in Section 26 and interfaces directly with the MCU s analog and digital subsystems providing a complete data acquisition or control system solution in a single integrated circuit Fully Compatible with MCS 51 Instruction Set Extended Interrupt Handler 25 MIPS Peak Throughput with 25 MHz Clock Reset In
200. a Byte A Data Byte AJP Received by SMBus S START m Interface P STOP A Transmitted by W WRITE SMBus Interface SLA Slave Address 20 3 2 Master Receiver Mode Serial data is received on SDA while the serial clock is output SCL The SMBusO interface generates START followed by the first data byte containing the address of the target slave and the data direction bit In this case the data direction bit R W will be logic 1 to indicate a READ operation The SMBusO inter face receives serial data from the slave and generates the clock on SCL After each byte is received SMBus0 generates NACK depending on the state of the AA bit in register SMBOCN SMBusO generates a STOP condition to indicate the end of the serial transfer Figure 20 5 Typical Master Receiver Sequence S SLA RJA Data Byte A Data Byte N P Received by SMBus S START Interface pe Transmitted by READ SMBus Interface SLA Slave Address 238 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 20 3 3 Slave Transmitter Mode Serial data is transmitted on SDA while the serial clock is received on SCL The SMBusO interface receives a START followed by data byte containing the slave address and direction bit If the received slave address matches the address held in register SMBOADR the SMBusO interface generates ACK SMBusO will also ACK if the general call address 0x00 is receive
201. a Chip MCUs with 59 digital pins C8051F060 2 4 6 or 24 digital I O pins C8051F061 3 5 7 and two integrated 16 bit 1 Msps ADCs Highlighted features are listed below refer to Table 1 1 for specific product feature selection High Speed pipelined 8051 compatible CIP 51 microcontroller core up to 25 MIPS Two 16 bit 1 Msps ADCs with a Direct Memory Access controller Controller Area Network CAN 2 0B Controller with 32 message objects each with its own indentifier mask C8051F060 1 2 3 In system full speed non intrusive debug interface on chip 10 bit 200 ksps ADC with PGA and 8 channel analog multiplexer C8051 F060 1 2 3 Two 12 bit DACs with programmable update scheduling C8051 F060 1 2 3 64 kB C8051F060 1 2 3 4 5 or 32 kB C8051F066 7 of in system programmable Flash memory 4352 4096 256 bytes of on chip RAM External Data Memory Interface with 64 kB direct address space C8051F060 2 4 6 SPI SMBus I2C and 2 UART serial interfaces implemented in hardware Five general purpose 16 bit Timers Programmable Counter Timer Array with six capture compare modules On chip Watchdog Timer VDD Monitor and Temperature Sensor With on chip VDD monitor Watchdog Timer and clock oscillator the C8051 FO6x family of devices are truly stand alone System on a Chip solutions All analog and digital peripherals are enabled disabled and con figured by user firmware The Flash memory can be reprogra
202. abilities for low power applications Perhaps the most unique enhancement is the Digital Crossbar This is a large digital switching network that allows mapping of internal digital system resources to Port I O pins on PO P1 P2 and P3 See Figure 1 9 Unlike microcontrollers with standard multiplexed digital I O ports all combinations of functions are supported with all package options offered The on chip counter timers serial buses HW interrupts comparator outputs and other digital signals in the controller can be configured to appear on the Port I O pins specified in the Crossbar Control registers This allows the user to select the exact mix of general purpose Port I O and digital resources needed for the particular application XBR1 XBR2 XBR3 P1MDIN P2MDIN P2MDOUT P3MDOUT Priority Registers Registers External Priority Decoder _ P0 0 Highest 3 10 H Priority Cells P0 7 T H H 2 Digital X Pio Crossba 5 r Cels 1 7 _ P2 P2 0 8 lt 10 Cells P2 7 Lowest Priority NVSTR2 8 0 vo Lowest Cells P3 7 Priority C8051F060 2 4 6 Only To ADC2 Input Port C8051F060 1 2 3 Latches To Comparators Figure 1 9 Digital Crossbar Diagra
203. age Range 1 00 V 0 3 Input Current 0 1 112 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 10 Voltage Reference 2 C8051F061 3 The internal voltage reference circuit consists of a 1 2 V temperature stable bandgap voltage reference generator and a gain of two output buffer amplifier The internal reference may be routed via the VREF pin to external system components or to the VREF2 input pin shown in Figure 10 1 The maximum load seen by the VREF pin must be less than 200 uA to AGND Bypass capacitors of 0 1 uF and 4 7 uF recom mended from the VREF pin to AGND as shown in Figure 10 1 The VREF2 pin provides a voltage reference input for ADC2 and the DACs ADC2 may also reference the analog power supply voltage via the VREF multiplexers shown in Figure 10 1 The Reference Control Register 2 REF2CN defined in Figure 10 2 enables disables the internal refer ence generator and selects the reference input for ADC2 The BIASE bit in REF2CN enables the on board reference generator while the REFBE bit enables the gain of two buffer amplifier which drives the VREF pin When disabled the supply current drawn by the bandgap and buffer amplifier falls to less than 1 typical and the output of the buffer amplifier enters a high impedance state If the internal bandgap is used as the reference voltage generator BIASE and REFBE must both be set to logic 1 If the internal ref erence is not used REFBE may be set to l
204. agram 297 Figure 24 13 TMRnCN Timer 2 and 4 Control Registers 299 Figure 24 14 TMRnCF Timer 2 and 4 Configuration Registers 300 Figure 24 15 RCAPnL Timer 2 and 4 Capture Register Low Byte 301 Figure 24 16 RCAPnH Timer 2 and 4 Capture Register High 301 Figure 24 17 TMRnL Timer 2 and 4 Low 301 Figure 24 18 TMRnH Timer 2 and 4 High 302 25 Programmable Counter Array eene nennen 303 Figure 25 1 Block Diagram re entia Rak rini a nd 303 Figure 25 2 PCA Counter Timer Block 304 Figure 25 3 PCA Interrupt Block Diagram unteren tenent tec etnies 305 Figure 25 4 PCA Capture Mode 306 Figure 25 5 PCA Software Timer Mode 307 Figure 25 6 High Speed Output Mode 308 Figure 25 7 PCA Frequency Output Mode 309 Figure 25 8 PCA 8 Bit PWM Mode 310 Figure
205. al Data will not be collected 1 Wait for differential data and store to XRAM ADC1EN Wait for data from ADC1 0 ADC1 Data will not be collected 1 Wait for ADC1 data and store to XRAM ADCOEN Wait for data from ADCO 0 ADCO Data will not be collected 1 Wait for ADCO data and store to XRAM If DIFFSEL is also 1 only the differential data will be stored Bits 3 0 RESERVED Write to 0000b Bit 6 Bit 5 Bit 4 For more details on DMA instruction words see Section 6 2 DMAO Instruction Format page 76 This register points to a dedicated RAM location and its reset value is indeterminate 82 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 6 8 DMAOBND Instruction Boundary Register SFR Page 3 SFR Address OxFD R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Biti Bito Bits 7 6 Unused Bits 5 0 instruction address to begin with when executing DMA instructions Figure 6 9 DMAOISW Instruction Status Register SFR Page 3 SFR Address OXFE R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito Bits 7 6 Unused Bits 5 0 Contains the address of the current Instruction to be executed e Rev 1 2 83 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 6 10 DMAQDAH DM
206. al Purpose I O GPIO pins by reading and writing the associated Port Data registers See Figure 18 19 Figure 18 21 Figure 18 23 Figure 18 25 a set of SFRs which are byte addressable Note that Port 4 has only three pins P4 5 P4 6 and P4 7 Note also that the Port 4 5 6 and 7 registers are located on SFR Page F The SFRPAGE reg ister must be set to OxOF to access these Port registers A Read of a Port Data register or Port bit will always return the logic state present at the pin itself regard less of whether the Crossbar has allocated the pin for peripheral use or not An exception to this occurs during the execution of a read modify write instruction ANL ORL XRL CPL INC DEC DJNZ JBC CLR SETB and the bitwise MOV write operation During the read cycle of the read modify write instruc tion it is the contents of the Port Data register not the state of the Port pins themselves which is read 18 2 1 Configuring Ports which are not Pinned Out Although P3 P4 P5 P6 and P7 are not brought out to pins on the C8051F061 3 5 7 devices the Port Data registers are still present and can be used by software Because the digital input paths also remain active it is recommended that these pins not be left in a floating state in order to avoid unnecessary power dissipation arising from the inputs floating to non valid logic levels This condition can be prevented by any of the following 1 Leave the weak pull up device
207. al Purpose Registers The lower 32 bytes of data memory locations 0x00 through 0x1F may be addressed as four banks of gen eral purpose registers Each bank consists of eight byte wide registers designated RO through R7 Only one of these banks may be enabled at a time Two bits in the program status word RSO PSW 3 and RS1 PSW 4 select the active register bank see description of the PSW in Figure 13 16 This allows fast con text switching when entering subroutines and interrupt service routines Indirect addressing modes use registers RO and R1 as index registers 13 2 4 Bit Addressable Locations In addition to direct access to data memory organized as bytes the sixteen data memory locations at 0x20 through Ox2F are also accessible as 128 individually addressable bits Each bit has a bit address from 0x00 to Ox7F Bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0x07 Bit 7 of the byte at Ox2F has bit address 0x7F A bit access is distinguished from a full byte access by the type of instruction used a bit source or destination operand as opposed to a byte source or destina tion The MCS 51 assembly language allows an alternate notation for bit addressing of the form XX B where XX is the byte address and B is the bit position within the byte For example the instruction MOV C 22 3h moves the Boolean value at 0x13 bit 3 of the byte at location 0x22 into the Carry flag 13 2 5 S
208. al START or STOP Set STO to reset SMBus OxF8 Idle State does not set SI SILICON LABS Rev 1 2 249 C8051F060 1 2 3 4 5 6 7 250 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 21 The Enhanced Serial Peripheral Interface SPIO provides access to a flexible full duplex synchronous serial bus SPIO can operate as a master or slave device in both 3 wire or 4 wire modes and supports mul tiple masters and slaves on a single SPI bus The slave select NSS signal can be configured as an input to select SPIO in slave mode or to disable Master Mode operation in a multi master environment avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers NSS can also be configured as a chip select output in master mode or disabled for 3 wire operation Additional gen eral purpose port I O pins can be used to select multiple slave devices in master mode Figure 21 1 SPI Block Diagram Enhanced Serial Peripheral Interface SPIO 2 SFR 2 SPIOCKR SPIOCFG SPIOCN gt z lt oa S 2 au z 000010000 012 955622
209. al interrupt enable settings Some interrupt pending flags are automatically cleared by the hardware when the CPU vectors to the ISR However most are not cleared by the hardware and must be cleared by software before returning from the ISR If an interrupt pending flag remains set after the CPU completes the return from interrupt RETI instruction a new interrupt request will be generated immediately and the CPU will re enter the ISR after the completion of the next instruction 13 3 1 MCU Interrupt Sources and Vectors The MCUs support 22 interrupt sources Software can simulate an interrupt event by setting any interrupt pending flag to logic 1 If interrupts are enabled for the flag an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt pending flag MCU interrupt sources associated vector addresses priority order and control bits are summarized in Table 13 4 Refer to the datasheet section associated with a particular on chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt pending flag s 13 3 2 External Interrupts The external interrupt sources INTO and INT1 are configurable as active low level sensitive or active low edge sensitive inputs depending on the setting of bits ITO 0 and IT1 TCON 2 IEO TCON 1 and IE1 TCON 3 serve as the interrupt pending flag for the INTO and INT1 external int
210. appear on any of the P1 P2 or I O pins as described Section 18 1 Ports 0 through 3 and the Priority Crossbar Decoder on page 205 Note that the Crossbar must be configured for the CNVSTR2 signal to be routed to the appropriate Port I O The Crossbar should be configured and enabled before the CNVRSEF is set CNVSTR2 cannot be used to start ADC2 conver sions when it is configured as a reset source When configured as a reset CNVSTR2 is active low and level sensitive After CNVSTR2 reset the CNVRSEF flag RSTSRC 6 will read 1 signifying CNVSTR2 as the reset source otherwise this bit reads 0 The state of the RST pin is unaffected by this reset 14 7 Watchdog Timer Reset The MCU includes a programmable Watchdog Timer WDT running off the system clock A WDT overflow will force the MCU into the reset state To prevent the reset the WDT must be restarted by application soft ware before overflow If the system experiences a software or hardware malfunction preventing the soft ware from restarting the WDT the WDT will overflow and cause a reset This should prevent the system from running out of control Following a reset the WDT is automatically enabled and running with the default maximum time interval If desired the WDT can be disabled by system software or locked on to prevent accidental disabling Once locked the WDT cannot be disabled until the next system reset The state of the RST pin is unaffected by
211. apture Module High Byte The PCAOCPHn register holds the high byte MSB of the 16 bit capture module n 316 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 26 JTAG IEEE 1149 1 Each MCU has an on chip JTAG interface and logic to support boundary scan for production and in sys tem testing Flash read write operations and non intrusive in circuit debug The JTAG interface is fully compliant with the IEEE 1149 1 specification Refer to this specification for detailed descriptions of the Test Interface and Boundary Scan Architecture Access of the JTAG Instruction Register IR and Data Regis ters DR are as described in the Test Access Port and Operation of the IEEE 1149 1 specification The JTAG interface is accessed via four dedicated pins on the MCU TCK TMS TDI and TDO Through the 16 bit JTAG Instruction Register IR any of the eight instructions shown in Figure 26 1 can be commanded There are three DR s associated with JTAG Boundary Scan and four associated with Flash read write operations on the MCU Figure 26 1 IR JTAG Instruction Register Reset Value 0x0000 Bit15 Bito Value Instruction Description 0x0000 EXTEST Selects the Boundary Data Register for control and observability of all device pins 0x0002 SAMPLE Selects the Boundary Data Register for observability and presetting the PRELOAD scan path latches 0x0004 IDCODE Selects device ID Register Ox
212. ator Frequencies for Standard Baud Rates 273 29 UART1 277 Table 23 1 Timer Settings for Standard Baud Rates Using the Internal Oscillator 284 Table 23 2 Timer Settings for Standard Baud Rates Using an External Oscillator 284 Table 23 3 Timer Settings for Standard Baud Rates Using an External Oscillator 285 Table 23 4 Timer Settings for Standard Baud Rates Using an External Oscillator 285 Table 23 5 Timer Settings for Standard Baud Rates Using an External Oscillator 286 Table 23 6 Timer Settings for Standard Baud Rates Using an External Oscillator 286 Nur 287 25 Programmable Counter Array u 303 Table 25 1 Timebase Input Options 304 Table 25 2 Register Settings for Capture Compare Modules 305 26 STAG IEEE 11481 317 Table 26 1 Boundary Data Register Bit Definitions C8051F060 2 4 6 318 Table 26 2 Boundary Data Register Bit Definitions C8051F061 3 5 7 320 27 DOCUMENT Change 327 18 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 1 System Overview The 8051 06 family of devices are fully integrated mixed signal System on
213. automatically cleared when the CPU vectors to the External Inter rupt 1 service routine if IT1 1 This flag is the inverse of the INT1 signal IT1 Interrupt 1 Type Select This bit selects whether the configured INT1 interrupt will be falling edge sensitive or active low 0 INT1 is level triggered active low 1 INT1 is edge triggered falling edge External Interrupt 0 This flag is set by hardware when edge level of type defined by ITO is detected It can be cleared by software but is automatically cleared when the CPU vectors to the External Inter rupt 0 service routine if ITO 1 This flag is the inverse of the INTO signal ITO Interrupt O Type Select This bit selects whether the configured INTO interrupt will be falling edge sensitive or active low 0 INTO is level triggered active logic low 1 INTO is edge triggered falling edge e Rev 1 2 291 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 24 5 TMOD Timer Mode Register R W R W R W R W R W R W R W R W Reset Value GATE1 C T1 T1M1 T1MO GATEO C TO TOM1 TOMO 00000000 Bit7 6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0x89 SFR Page 0 Bit7 GATE1 Timer 1 Gate Control 0 Timer 1 enabled when TH1 1 irrespective of INT1 logic level 1 Timer 1 enabled only when TR1 1 AND INT1 logic 1 Bit6 C T1 Counter Timer 1 Select 0 Timer Function Timer 1 incremented by clock defined by T1M bit
214. buffer is transferred to the SPI shift register this bit will be set to logic 1 indicating that it is safe to write a new byte to the transmit buffer Bit 0 SPIEN SPIO Enable This bit enables disables the SPI 0 SPI disabled 1 SPI enabled e Rev 1 2 259 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 21 10 SPIOCKR SPIO Clock Rate Register R W R W R W Reset Value SCR5 SCR4 SCRO 00000000 Bit5 Bit4 Bito SFR Address 0x9D SFR Page 0 Bits 7 0 SCR7 SCRO SPIO Clock Rate These bits determine the frequency of the SCK output when the SPIO module is configured for master mode operation The SCK clock frequency is a divided version of the system clock and is given in the following equation where SYSCLK is the system clock frequency and SPIOCKR is the 8 bit value held in the SPIOCKR register f SYSCLK SCK 2x SPIOCKR 1 for 0 lt SPIOCKR lt 255 Example If SYSCLK 2 MHz SPIOCKR 0x04 2000000 SCK 7 2x 4 1 200kHz 260 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 21 11 SPIODAT SPIO Data Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0x9B SFR Page 0 Bits 7 0 SPIODAT SPIO Transmit and Receive Data The SPIODAT register is used to transmit and receive SPIO data Writing data to SPIODAT places the data int
215. by any Port pin 100 mA Maximum output current sunk by any other I O pin 50 mA Maximum output current sourced by any Port pin 100 mA Maximum output current sourced by any other I O pin 50 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied Exposure to maximum rating conditions for extended periods may affect device reliability e Rev 1 2 37 SILICON LABS C8051F060 1 2 3 4 5 6 7 3 Global DC Electrical Characteristics Table 3 1 Global DC Electrical Characteristics 40 to 85 25 MHz System Clock unless otherwise specified ture Range Parameter Conditions Min Typ Max Units Analog Supply Voltage AV Note 1 2 7 3 0 3 6 V AVDD Digital Supply Voltage VDD 2 7 3 0 3 6 V Analog to Digital Supply Delta 0 5 V IVDD AVDD Supply Current from Analog Internal REF ADC DAC Com 14 mA Peripherals active parators all enabled Note 2 Supply Current from Analog Internal REF ADC DAC Com 0 2 Peripherals inactive parators all disabled oscillator disabled Supply Current from CPU VDD 2 7 V Clock 25 MHz 18 mA Digital Peripherals CPU active VDD 2 7 V C
216. cription P3 7 47 47 D Port 3 7 See Port Input Output section for complete description P4 5 ALE 93 93 D Port 4 5 See Port Input Output section for complete description ALE Strobe for External Memory Address Bus Mul tiplexed mode P4 6 RD 92 92 D I O 4 6 See Port Input Output section for complete description RD Strobe for External Memory Address Bus P4 7 WR 91 91 4 7 See Port Input Output section for complete description WR Strobe for External Memory Address Bus P5 0 A8 88 88 D Port 5 0 See Port Input Output section for complete description Bit 8 External Memory Address Bus Non multi plexed mode P5 1 A9 87 87 D Port 5 1 See Port Input Output section for complete description 42 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 4 1 Pin Definitions Continued Pin Numbers Name 060 F061 064 F065 Type Description F062 F063 F066 F067 P5 2 A10 86 86 D Port 5 2 See Port Input Output section for complete description P5 3 A11 85 85 D Port 5 3 See Port Input Output section for complete description P5 4 A12 84 84 D Port 5 4 See Port Input Output section for complete description P5 5 A13 83 83 D Port 5 5 See Port Input Output section for complete description P5 6 A14 82 82 D Port 5 6 See Port
217. ct bit 0 causes the CIP 51 to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes All internal registers and memory maintain their original data All analog and digital peripherals can remain active during Idle mode Idle mode is terminated when an enabled interrupt or RST is asserted The assertion of an enabled inter will cause the Idle Mode Selection bit 0 to be cleared and the CPU to resume operation The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt RETI will be the instruction immediately following the one that set the Idle Mode Select bit If Idle mode is terminated by an internal or external reset the CIP 51 performs a normal reset sequence and begins pro gram execution at address 0x0000 If enabled the WDT will eventually cause an internal watchdog reset and thereby terminate the Idle mode This feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCON register If this behavior is not desired the WDT may be disabled by software prior to entering the Idle mode if the WDT was initially configured to allow this operation This provides the oppor tunity for additional power savings allowing the system to remain in the Idle mode indefinitely waiting for an external stimulus to wake up the system Refer to Section 14 7 for more information on the use and confi
218. cycles 194 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 17 1 lists the AC parameters for the External Memory Interface and Figure 17 7 through Figure 17 12 show the timing diagrams for the different External Memory Interface modes and MOVX operations e Rev 1 2 195 SILICON LABS C8051F060 1 2 3 4 5 6 7 17 6 1 Non multiplexed Mode 17 6 1 1 16 bit MOVX EMIOCF 4 2 101 110 111 Figure 17 7 Non multiplexed 16 bit MOVX Timing Nonmuxed 16 bit WRITE ADDR 15 8 ADDR 7 0 DATA 7 0 ANR RD Nonmuxed 16 bit READ ADDR 15 8 ADDR 7 0 DATA 7 0 RD ANR 196 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 17 6 1 2 8 bit MOVX without Bank Select EMIOCF 4 2 101 or 111 Figure 17 8 Non multiplexed 8 bit MOVX without Bank Select Timing Nonmuxed 8 bit WRITE without Bank Select ADDR 15 8 P5 ADDR 7 0 DATA 7 0 ANR RD Nonmuxed 8 bit READ without Bank Select ADDR 15 8 P5 ADDR 7 0 DATA 7 0 RD ANR Rev 1 2 197 SILICON LABS C8051F060 1 2 3 4 5 6 7 17 6 1 3 8 bit MOVX with Bank Select EMIOCF 4 2 110 Figure 17 9 Non multiplexed 8 bit MOVX with Bank Select Timing Nonmuxed 8 bit WRITE with Bank Select ADDR 15 8 ADDR 7 0 DATA 7 0 ANR RD Nonmuxed 8 bit READ with Bank Select ADDR 15 8 ADDR 7 0 DATA 7 0 RD ANR
219. d and the General Call Address Enable bit is set to logic 1 In this case the data direction bit R W will be logic 1 to indicate a READ operation The SMBusO interface receives the clock on SCL and transmits or more bytes of serial data waiting for ACK from the master after each byte SMBusO exits slave mode after receiving a STOP condition from the master Figure 20 6 Typical Slave Transmitter Sequence S SLA Data Byte A Data Byte P Interrupt Received by SMBus S START Interface STOP R READ Transmitted SLA Slave Address SMBus Interface 20 3 4 Slave Receiver Mode Serial data is received on SDA while the serial clock is received on SCL The 0 interface receives a START followed by data byte containing the slave address and direction bit If the received slave address matches the address held in register SMBOADR the interface generates ACK 0 will also ACK if the general call address 0x00 is received and the General Call Address Enable bit is set to logic 1 In this case the data direction bit R W will be logic 0 to indicate a WRITE operation The SMBusO interface receives one or more bytes of serial data after each byte is received the interface transmits or NACK depending on the state of the AA bit in SMBOCN SMBus0 exits Slave Receiver e Rev 1 2 239 SILICON LABS C80
220. ddressable SFR Address 0xE8 SFR Page F Bits7 0 P6 7 0 Port6 Output Latch Bits Write Output appears I O pins 0 Logic Low Output 1 Logic High Output open if corresponding PeMDOUT bit 0 See Figure 18 24 Read Returns states of I O pins 0 P6 n pin is logic low 1 P6 n pin is logic high Note P6 7 0 can be driven by the External Data Memory Interface as Address 15 8 in Multi plexed mode or as Address 7 0 in Non multiplexed mode See Section 17 External Data Memory Interface and On Chip XRAM on page 187 for more information about the External Memory Interface Figure 18 24 PEMDOUT Port6 Output Mode Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit BitO SFR Address 9 SFR Page F Bits7 0 P6MDOUT 7 0 Port6 Output Mode Bits 0 Port Pin output mode is configured as Open Drain 1 Port Pin output mode is configured as Push Pull Rev 1 2 223 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 18 25 P7 Port7 Data Register R W R W R W R W R W R W R W R W Reset Value P7 7 P7 6 P7 5 P7 4 P7 3 P7 2 P7 1 P7 0 11111111 Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Ad ressabie SFR Address 0xF8 SFR Page F Bits7 0 P7 7 0 Port7 Output Latch Bits Write Output appears on pins 0 Logic Low Output 1 Logic High Output open if correspo
221. dress If the addresses match the slave should clear its MCE 1 bit to enable interrupts on the reception of the following data byte s Slaves that weren t addressed leave their MCE1 bits set and do not generate interrupts on the reception of the following data bytes thereby ignoring the data Once the entire message is received the addressed slave should reset its MCE1 bit to ignore all transmissions until it receives the next address byte Multiple addresses can be assigned to a single slave and or a single address can be assigned to multiple slaves thereby enabling broadcast transmissions to more than one slave simultaneously The master processor can be configured to receive all transmissions or a protocol can be implemented such that the master slave role is temporarily reversed to enable half duplex transmission between the original master and slave s Figure 23 6 UART Multi Processor Mode Interconnect Diagram Master Device RX TX Rev 1 2 281 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 23 7 SCON1 Serial Port 1 Control Register R W R W R W R W R W R W R W R W Reset Value S1MODE MCE1 REN1 TB81 RB81 TH 01000000 Bit Bit7 6 Bit5 Bit4 Bit3 Bit2 Bito Addressable SFR Address 0x98 SFR Page 1 Bit7 S1MODE Serial Port 1 Operation Mode This bit selects the UART1 Operation Mode 0 8 bit UART with Variable Baud Rate 1 9 bit UART with Variable Baud
222. dule 5 m m m m m m m gt gt gt gt N gt Crossbar TRO as el por mE e rl Portl O Rev 1 2 303 SILICON LABS C8051F060 1 2 3 4 5 6 7 25 1 PCA Counter Timer The 16 bit counter timer consists of two 8 bit SFRs PCAOL and PCAOH is the high byte MSB of the 16 bit counter timer and PCAOL is the low byte LSB Reading PCAOL automatically latches the value of PCAOH into a snapshot register the following PCAOH read accesses this snapshot register Reading the PCAOL Register first guarantees an accurate reading of the entire 16 bit PCAO counter Read ing PCAOH or PCAOL does not disturb the counter operation The CPS2 CPSO bits in the PCAOMD regis ter select the timebase for the counter timer as shown in Table 25 1 When the counter timer overflows from OxFFFF to 0x0000 the Counter Overflow Flag CF in PCAOMD is set to logic 1 and an interrupt request is generated if CF interrupts are enabled Setting the ECF bit in PCAOMD to logic 1 enables the CF flag to generate an interrupt request The CF bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by soft ware Note PCAO interrupts must be globally enabled before CF interrupts are recognized PCAO inter rupts are globally enabled b
223. e Available for Windows Mac and Linux loT Portfolio SW HW Quality Support and Community www silabs com loT www silabs com simplicity www silabs com quality community silabs com Disclaimer Silicon Laboratories intends to provide customers with the latest accurate and in depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products Characterization data available modules and peripherals memory sizes and memory addresses refer to each specific device and Typical parameters provided can and do vary in different applications Application examples described herein are for illustrative purposes only Silicon Laboratories reserves the right to make changes without further notice and limitation to product information specifications and descriptions herein and does not give warranties as to the accuracy or completeness of the included information Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories A Life Support System is any product or system intended to support or sustain life and or health which if it fails can be reasonably expected to result in sig
224. e R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x8B SFR Page 0 Bits 7 0 TL1 Timer 1 Low Byte The TL1 register is the low byte of the 16 bit Timer 1 Figure 24 9 THO Timer 0 High Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x8C SFR Page 0 Bits 7 0 THO Timer 0 High Byte The THO register is the high byte of the 16 bit Timer 0 Figure 24 10 TH1 Timer 1 High Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bite Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0x8D SFR Page 0 Bits 7 0 TH1 Timer 1 High Byte The TH1 register is the high byte of the 16 bit Timer 1 294 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 24 2 Timer 2 Timer 3 and Timer 4 Timers 2 3 and 4 are 16 bit counter timers each formed by two 8 bit SFRs TMRnL low byte and TMRnH high byte where n 2 3 and 4 for timers 2 3 and 4 respectively These timers feature reload capture and toggle output modes with the ability to count up or down Capture Mode and Auto reload mode are selected using bits in the Timer 2 3 and 4 Control registers TMRnCN Toggle output mode is selected using the Timer 2 3 and 4 Configuration registers TMRnCF These timers may also be used to generate a square wave at an external pin Timers 2 3 and 4 can use either the system clock divided by one two
225. e 1 11 CAN Controller Overview e Rev 1 2 31 SILICON LABS C8051F060 1 2 3 4 5 6 7 1 7 Serial Ports The C8051F06x MCU Family includes two Enhanced Full Duplex UARTs an enhanced SPI Bus and SMBus I2C Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP 51 s interrupts thus requiring very little intervention by the CPU The serial buses do not share resources such as timers interrupts or Port I O so any or all of the serial buses may be used together with any other 32 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 1 8 16 Analog to Digital Converters The C8051F060 1 2 3 4 5 6 7 devices have two on chip 16 bit SAR ADCs ADCO and ADC1 which can be used independently in single ended mode or together in differential mode ADCO and ADC1 can directly access on chip or external RAM using the DMA interface With a maximum throughput of 1 Msps the ADCs offer 16 bit performance with two available linearity grades ADCO and ADC1 each have the capability to use dedicated on chip voltage reference circuitry or an external voltage reference source The are under full control of the CIP 51 microcontroller via the associated Special Function Regis ters The system controller can also put the ADCs into shutdown mode to save power Conversions can be started in four ways a software command an overflow of Timer 2 an overflow of Timer 3 or an external signal input
226. e ADCO End of Conversion Interrupt 0 Disable ADCO Conversion Interrupt 1 Enable interrupt requests generated by the ADC1 Conversion Interrupt Bit6 CP2IE Enable Comparator CP2 Interrupt This bit sets the masking of the CP2 interrupt 0 Disable CP2 interrupts 1 Enable interrupt requests generated by the CP2IF flag Bit6 CP1IE Enable Comparator CP1 Interrupt This bit sets the masking of the CP1 interrupt 0 Disable CP1 interrupts 1 Enable interrupt requests generated by the CP1IF flag Bit6 CPOIE Enable Comparator CPO Interrupt This bit sets the masking of the CPO interrupt 0 Disable CPO interrupts 1 Enable interrupt requests generated by the CPOIF flag Bit3 EPCAO Enable Programmable Counter Array PCAO Interrupt This bit sets the masking of the PCAO interrupts 0 Disable all PCAO interrupts 1 Enable interrupt requests generated by PCAO Bit2 EWADCO Enable Window Comparison ADCO Interrupt This bit sets the masking of ADCO Window Comparison interrupt 0 Disable ADCO Window Comparison Interrupt 1 Enable Interrupt requests generated by ADCO Window Comparisons Bit1 ESMBO Enable System Management Bus 0 Interrupt This bit sets the masking of the SMBus interrupt 0 Disable all SMBus interrupts 1 Enable interrupt requests generated by the SI flag Bito ESPI0 Enable Serial Peripheral Interface SPIO Interrupt This bit sets the masking of SPIO interrupt 0 Disable all SPIO interrupts 1 Enab
227. e ADCO data word MSB and LSB registers ADCOH ADCOL When initiating conversions by writing a 1 to ADnBUSY the ADnINT bit should be polled to determine when a conversion has completed ADCn interrupts may also be used The recommended polling proce dure is shown below Step 1 Write a 0 to ADnINT Step 2 Write a 1 to ADnBUSY Step 3 Poll ADnINT for 1 Step 4 Process ADCn data When an external start of conversion source is required in differential mode the two pins CNVSTRO and CNVSTR1 should be tied together 5 3 2 Tracking Modes The ADnTM bit in register ADCnCN controls the ADCn track and hold mode When the ADC is enabled the ADC input is continuously tracked when a conversion is not in progress When the ADnTM bit is logic 1 each conversion is preceded by a tracking period after the start of conversion signal When the CNVSTRn signal is used to initiate conversions the ADC will track until a rising edge occurs on the CNVSTRn pin see Figure 5 4 and Table 5 1 for conversion timing parameters Setting ADnTM to 1 can be useful to ensure that settling time requirements are met when an external multiplexer is used on the analog input see Section 5 3 3 Settling Time Requirements on page 56 54 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Timer 2 Timer 3 Overflow Write 1 to ADnBUSY A ADC Timing for External Trigger Source t Conv CNVSTRn Track
228. e relevant TCON and TMOD bits just as with Timer 0 The input signal INT1 is used with Timer 1 Figure 24 1 TO Mode 0 Block Diagram CKCON TMOD Pre scaled Clock SYSCLK gt Interrupt GATEO TCON Crossbar 288 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 24 1 2 Mode 1 16 bit Counter Timer Mode 1 operation is the same as Mode 0 except that the counter timer registers use all 16 bits The counter timers are enabled and configured in Mode 1 in the same manner as for Mode 0 24 1 3 Mode 2 8 bit Counter Timer with Auto Reload Mode 2 configures Timer 0 or Timer 1 to operate as 8 bit counter timers with automatic reload of the start value TLO holds the count and THO holds the reload value When the counter in TLO overflows from OxFF to 0x00 the timer overflow flag TFO TCON 5 is set and the counter in TLO is reloaded from THO If Timer 0 interrupts are enabled an interrupt will occur when the TFO flag is set The reload value in THO is not changed TLO must be initialized to the desired value before enabling the timer for the first count to be cor rect When in Mode 2 Timer 1 operates identically to Timer 0 Both counter timers are enabled and configured in Mode 2 in the same manner as Mode 0 Setting the TRO bit TCON 4 enables the timer when either TMOD 3 is logic 0 or when the input signal INTO is low
229. ecially effective in an interrupt driven system saving code space and CPU bandwidth while delivering faster system response times The window detector interrupt flag ADOWINT in ADCOCN can also be used in polled mode The high and low bytes of the reference words are loaded into the ADCO Greater Than and ADCO Less Than registers ADCOGTH ADCOGTL ADCOLTH and ADCOLTL The Window Detector can be used in single ended or differential mode In signle ended mode the Window Detector compares the ADCOGTx and ADCOLTx registers to the output of ADCO In differential mode the combined output of ADCO and ADC1 contained in the ADCO data registers is used for the comparison Reference comparisons are shown starting on page 71 Notice that the window detector flag can be asserted when the measured data is inside or outside the user programmed limits depending on the programming of the ADCOGTx and ADCOLTx registers Figure 5 24 ADCOGTH ADCO Greater Than Data High Byte Register R W R W R W R W R W R W R W R W Reset Value 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xC5 SFR Page 0 Bits 7 0 High byte of ADCO Greater Than Data Word Figure 5 25 ADCOGTL ADCO Greater Than Data Low Byte Register R W R W R W R W R W R W R W R W Reset Value 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address SFR Page 0 Bits 7 0 Low byte of ADCO Greater Tha
230. ective address 16 bit MOVX operations use the contents of the 16 bit DPTR to determine the effective address 17 5 2 Split Mode without Bank Select When EMIOCF 3 2 are set to 01 the XRAM memory map is split into two areas on chip space and off chip space Effective addresses below the 4 kB boundary will access on chip XRAM space Effective addresses beyond the 4 kB boundary will access off chip space 8 bit MOVX operations use the contents of EMIOCN to determine whether the memory access is on chip or off chip However in the No Bank Select mode an 8 bit MOVX operation will not drive the upper 8 bits A 15 8 of the Address Bus during an off chip access This allows the user to manipulate the upper address bits at will by setting the Port state directly This behavior is in contrast with Split Mode with Bank Select described below The lower 8 bits of the Address Bus A 7 0 are driven deter mined by RO or R1 16 bit MOVX operations use the contents of DPTR to determine whether the memory access is on chip or off chip and unlike 8 bit MOVX operations the full 16 bits of the Address Bus A 15 0 are driven during the off chip transaction Figure 17 5 EMIF Operating Modes EMIOCF 3 2 00 EMIOCF 3 2 01 EMIOCF 3 2 10 EMIOCF 3 2 11 OxFFFF OxFFFF OxFFFF OxFFFF On Chip XRAM On Chip XRAM On Chip XRAM On Chip XRAM On Chip XRAM On Chip XRAM On Chip XRAM On Chip XRAM 0x0000 0x0000 0x
231. ed MOVX write operations target Flash memory e Rev 1 2 185 SILICON LABS C8051F060 1 2 3 4 5 6 7 186 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 17 External Data Memory Interface and On Chip XRAM The C8051F060 1 2 3 4 5 6 7 MCUs include 4 k bytes of on chip RAM mapped into the external data memory space XRAM In addition the C8051F060 2 4 6 include an External Data Memory Interface which can be used to access off chip memories and memory mapped devices connected to the GPIO ports The external memory space may be accessed using the external move instruction MOVX and the data pointer DPTR or using the MOVX indirect addressing mode using RO or R1 If the MOVX instruction is used with 8 bit address operand such as 1 then the high byte of the 16 bit address is provided by the External Memory Interface Control Register EMIOCN shown in Figure 17 1 Note the MOVX instruction can also be used for writing to the Flash memory See Section 16 Flash Memory on page 177 for details The MOVX instruction accesses XRAM by default 17 1 Accessing XRAM The XRAM memory space both internal and external is accessed using the MOVX instruction The MOVX instruction has two forms both of which use an indirect addressing method The first method uses the Data Pointer DPTR a 16 bit register which contains the effective address of the XRAM location to be read or written The second method uses RO or R1 in co
232. ementation is based solely on clock cycle timing All instruction timings are specified in terms of clock cycles Due to the pipelined architecture of the CIP 51 most instructions execute in the same number of clock cycles as there are program bytes in the instruction Conditional branch instructions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken Table 13 1 is the CIP 51 Instruction Set Summary which includes the mnemonic number of bytes and number of clock cycles for each instruction 13 1 2 MOVX Instruction and Program Memory In the CIP 51 the MOVX instruction serves three purposes accessing on chip XRAM accessing off chip XRAM and writing to on chip program Flash memory The Flash access feature provides a mechanism for user software to update program code and use the program memory space for non volatile data storage see Section 16 Flash Memory page 177 The External Memory Interface provides a fast access to off chip XRAM or memory mapped peripherals via the MOVX instruction Refer to Section 17 External Data Memory Interface and On Chip XRAM on page 187 for details Rev 1 2 125 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 13 1 CIP 51 Instruction Set Summary s Clock Mnemonic Descripti
233. enerator BIASE and REFBE must both be set to logic 1 If the internal reference is not used REFBE may be set to logic 0 Note that the BIASE bit must be set to logic 1 if ADC2 or either DAC is used regardless of the voltage reference used If neither ADC2 nor the DACs are being used both of these bits can be set to logic 0 to conserve power Bit AD2VRS selects between VREF2 and for the ADC2 voltage reference source The electrical specifications for the Voltage Reference are given in Table 9 1 Figure 9 1 Voltage Reference Functional Block Diagram REF2CN lo gt AD2VRS lt REFBE External Voltage Reference Circuit Bias to VREFD x 2 I VREF DACs lt Dx 1 2V s 7 04 Recommended Bypass Capacitors e Rev 1 2 111 SILICON LABS C8051F060 1 2 3 4 5 6 7 The temperature sensor connects to the highest order input of the ADC2 input multiplexer see Section 7 10 Bit ADC ADC2 8051 060 1 2 3 on page 87 The TEMPE bit within REF2CN enables and dis ables the temperature sensor While disabled the temperature sensor defaults to a high impedance state and any A D measurements performed on the sensor while disabled result in meaningless data Figure 9 2 REF2CN Reference Control Register 2 Bit
234. er device 3 wire slave mode is active when NSSMD1 SPIOCN 3 0 and NSSMDO SPIOCN 2 0 NSS is not used in this mode and is not mapped to an external port pin through the crossbar Since there is no way of uniquely addressing the device in 3 wire slave mode SPIO must be the only slave device present on the bus It is important to note that in 3 wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received The bit counter can only be reset by disabling and re enabling SPIO with the SPIEN bit Figure 21 3 shows a connection diagram between a slave device in 3 wire slave mode and a master device 21 4 SPIO Interrupt Sources When SPIO interrupts are enabled the following four flags will generate an interrupt when they are set to logic 1 Note that all of the following bits must be cleared by software 1 The SPI Interrupt Flag SPIF SPIOCN 7 is set to logic 1 at the end of each byte transfer This flag can occur in all SPIO modes 2 The Write Collision Flag WCOL SPIOCN 6 is set to logic 1 if a write to SPIODAT is attempted when the transmit buffer has not been emptied to the SPI shift register When this occurs the write to SPIODAT will be ignored and the transmit buffer will not be written This flag can occur in all SPIO modes 3 The Mode Fault Flag MODF SPIOCN 5 is set to logic 1 when SPIO is configured as a master and for multi master mode and the NSS pin is pu
235. eresis can be disabled In a similar way the amount of positive hysteresis is deter mined by the setting the CPnHYP bits 118 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Comparator interrupts can be generated on either rising edge and falling edge output transitions For Interrupt enable and priority control see Section 13 3 Interrupt Handler on page 151 The rising and or falling edge interrupts are enabled using the comparator s Rising Falling Edge Interrupt Enable Bits CPnRIE and CPnFIE in their respective Comparator Mode Selection Register CPTnMD shown in Figure 12 4 These bits allow the user to control which edge or both will cause a comparator interrupt However the comparator interrupt must also be enabled in the Extended Interrupt Enable Register EIE1 The CPnFIF flag is set to logic 1 upon a Comparator falling edge interrupt and the CPnRIF flag is set to logic 1 upon the Comparator rising edge interrupt Once set these bits remain set until cleared by soft ware The output state of a Comparator can be obtained at any time by reading the CPnOUT bit Com parator is enabled by setting its respective CPnEN bit to logic 1 and is disabled by clearing this bit to logic 0 Upon enabling a comparator the output of the comparator is not immediately valid Before using a com parator as an interrupt or reset source software should wait for a minimum of the specified Power up time as specified in Table 12
236. erface consists of four steps 1 Enable the EMIF on the High Ports P7 P6 P5 and P4 2 Configure the Output Modes of the port pins as either push pull or open drain push pull is most common 3 Configure Port latches to park the EMIF pins in a dormant state usually by setting them to logic 1 4 Select Multiplexed mode or Non multiplexed mode 5 Select the memory mode on chip only split mode without bank select split mode with bank select or off chip only 6 Setup timing to interface with off chip memory or peripherals Each of these four steps is explained in detail in the following sections The Port enable bit Multiplexed mode selection and Mode bits are located in the EMIOCF register shown in Figure 17 2 17 3 Port Selection and Configuration When enabled the External Memory Interface appears on Ports 7 6 5 and 4 in non multiplexed mode or Ports 7 6 and 4 in multiplexed mode The External Memory Interface claims the associated Port pins for memory operations ONLY during the execution of an off chip MOVX instruction Once the MOVX instruction has completed control of the Port pins reverts to the Port latches See Section 18 Port Input Output on page 203 for more information about the Port operation and configuration The Port latches should be explicitly configured to park the External Memory Interface pins in a dormant state when not in use most commonly by setting them to a logic 1 D
237. eriodic interrupt requests Timer 0 and Timer 1 are nearly identical and have four primary modes of operation Timers 2 3 and 4 are identi cal and offer not only 16 bit auto reload and capture but have the ability to produce a 50 duty cycle square wave toggle output at an external port pin Timer 0 and Timer 1 Modes Timer 2 3 and 4 Modes 13 bit counter timer 16 bit counter timer with auto reload 16 bit counter timer 16 bit counter timer with capture 8 bit counter timer with auto reload Toggle Output Two 8 bit counter timers Timer 0 only Timers 0 and 1 may be clocked by one of five sources determined by the Timer Mode Select bits T1M TOM and the Clock Scale bits SCA1 SCAO The Clock Scale bits define a pre scaled clock by which Timer 0 and or Timer 1 may be clocked See Figure 24 6 for pre scaled clock selection Timers 0 and 1 can be configured to use either the pre scaled clock signal or the system clock directly Timers 2 3 and 4 may be clocked by the system clock the system clock divided by 12 or the external oscillator clock source divided by 8 Timer 0 and Timer 1 may also be operated as counters When functioning as a counter a counter timer register is incremented on each high to low transition at the selected input pin Events with a frequency of up to one fourth the system clock s frequency can be counted The input signal need not be periodic but it should be held at a given logic level f
238. erlapping 4 boundaries The C8051F060 2 4 6 also have an external memory interface EMIF for accessing off chip data memory or memory mapped peripherals External data memory address space can be mapped to on chip memory only off chip memory only or a combination of the two addresses up to 4 k directed to on chip above 4 k directed to EMIF The EMIF is also configurable for multiplexed or non multiplexed address data lines The MCU s program memory consists of 64 C8051F060 1 2 3 4 5 or 32 k C8051F066 7 of Flash This memory may be reprogrammed in system in 512 byte sectors and requires no special off chip program ming voltage On the C8051F060 1 2 3 4 5 the 1024 bytes from addresses OxFCOO to OxFFFF are reserved There is also a single 128 byte Scratchpad Memory sector on all devices which may be used by firmware for non volatile data storage See Figure 1 7 for the MCU system memory map PROGRAM DATA MEMORY DATA MEMORY RAM FLASH C8051F060 1 2 3 4 5 OxFF INTERNAL DATA ADDRESS SPACE 0x1007F Scrachpad Memory Upper 128 RAM Special Function 0x10000 data only 0x80 Indirect Addressing Registers Ox7F Only Direct Addressing Only OxFFFF o RESERVED 0 00 0 30 Addressing Up To 2 FLASH Ox Lower 128 296 SFA Pages Direct and Indirect In System Addressing Programmable in 512 0x00 Byte Sector
239. ernal CMOS Clock Mode with divide by 2 stage External CMOS Clock input on XTAL1 pin 10x RC C Oscillator Mode with divide by 2 stage 110 Crystal Oscillator Mode 111 Crystal Oscillator Mode with divide by 2 stage Bit3 Unused Read 0 Write don t care Bits2 0 XFCN2 0 External Oscillator Frequency Control Bits 000 111 see table below XFCN Crystal XOSCMD 11x RC XOSCMD 10x C XOSCMD 10x 000 f lt 32 kHz f lt 25 kHz K Factor 0 87 001 32 kHz lt f lt 84 kHz 25 kHz f x 50 kHz Factor 2 6 010 84 kHz f x 225 kHz 50 kHz f 100 kHz Factor 7 7 011 225 kHz f lt 590 kHz 100 kHz f lt 200 kHz Factor 22 100 590 kHz f lt 1 5 MHz 200 kHz lt f lt 400 kHz Factor 65 101 1 5 MHz lt f lt 4 MHz 400 kHz lt 1 lt 800 kHz Factor 180 110 4 MHz lt f lt 10 MHz 800 kHz lt f 1 6 MHz K Factor 664 111 10 MHz f lt 30 MHz 1 6 MHz lt f lt 3 2 MHz K Factor 1590 CRYSTAL MODE Circuit from Figure 15 1 Option 1 XOSCMD 11x Choose XFCN value to match crystal frequency RC MODE Circuit from Figure 15 1 Option 2 XOSCMD 10x Choose XFCN value to match frequency range f 1 23 103 R C where f frequency of oscillation in MHz C capacitor value in pF R Pull up resistor value kQ C MODE Circuit from Figure 15 1 Option 3 XOSCMD 10x Choose K Factor KF for the oscillation frequency desired f KF
240. errupts respec tively If an INTO or INT1 external interrupt is configured as edge sensitive the corresponding interrupt pending flag is automatically cleared by the hardware when the CPU vectors to the ISR When configured as level sensitive the interrupt pending flag follows the state of the external interrupt s input pin The exter nal interrupt source must hold the input active until the interrupt request is recognized It must then deacti vate the interrupt request before execution of the ISR completes or another interrupt request will be generated e Rev 1 2 151 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 13 4 Interrupt Summary a Interrupt Priority o Enable Priority Interrupt Source Vector Order Pending Flag 5 Flag Control G G mo Reset 0x0000 Top None Mes Ways p Enabled Highest External Interrupt 0 INTO 0x0003 0 IE0 TCON 1 Y Y 0 PX0 IP 0 Timer 0 Overflow 0x000B 1 5 Y Y 1 IP 1 External Interrupt 1 INT1 0 0013 2 IE1 TCON 3 Y Y IE 2 1 IP 2 Timer 1 Overflow 0x001B 3 TF1 TCON 7 Y Y IE 3 IP 3 RIO SCONO 0 UARTO 0x0023 4 SCONO 1 Y ESO IE 4 PSO IP 4 Timer 2 0x002B 5 TF2 TMR2CN 7 Y ET2 IE 5 PT2 IP 5 SPIF SPIOCN 7 WCOL SPI0CN 6 ESPI0 PSPI0 Serial Per
241. ers Used to configure 32 Message Objects send and receive data to and from Message Objects The C8051 MCU accesses the CAN message RAM via the Message Object Interface Registers Upon writing a message object number to an IF1 or IF2 Command Request Register the contents of the associated Interface Registers IF1 or IF2 will be transferred to or from the message object in CAN RAM 3 Message Handler Registers These read only registers are used to provide information to the CIP 51 MCU about the message objects MSGVLD flags Transmission Request Pending New Data Flags and Interrupts Pending which Message Objects have caused an interrupt or status interrupt condition 4 8051 MCU Special Function Registers SFR Five registers located in the C8051 MCU memory map that allow direct access to certain CAN Controller Protocol Registers and Indexed indirect access to all CAN registers 19 2 1 CAN Controller Protocol Registers The CAN Control Protocol Registers are used to configure the CAN controller process interrupts monitor bus status and place the controller in test modes The CAN controller protocol registers are accessible using C8051 MCU SFRs by an indexed method and some can be accessed directly by addressing the SFRs in the C8051 SFR map for convenience The registers are CAN Control Register CANOCN CAN Status Register CANOSTA CAN Test Register CANOTST Error Counter Register Bit Timing Register and the Baud Rate Prescale
242. erter The C8051F060 1 2 3 devices have an on board 10 bit SAR ADC ADC2 with a 9 channel input multi plexer and programmable gain amplifier This ADC features a 200 ksps maximum throughput and true 10 bit performance with an INL of 1LSB Eight input pins are available for measurement and can be grammed as single ended or differential inputs Additionally the on chip temperature sensor can be used as an input to the ADC The ADC is under full control of the CIP 51 microcontroller via the Special Function Registers The ADC2 voltage reference is selected between the analog power supply AV and the exter nal VREF2 pin User software may put ADC2 into shutdown mode to save power A flexible conversion scheduling system allows ADC2 conversions to be initiated by software commands timer overflows or an external input signal Conversion completions are indicated by a status bit and an interrupt if enabled and the resulting 10 bit data word is latched into two SFR locations upon completion ADC2 also contains Window Compare registers which can be configured to interrupt the controller when ADC2 data is within or outside of a specified range ADC2 can monitor a key voltage continuously in back ground mode and not interrupt the controller unless the converted data is within the specified window Configuration and Control Registers AIN2 0 AIN2 1 DX AIN2 2 XX
243. es serial communication using the CAN protocol Silicon Labs CAN controller facilitates communication on a CAN network in accordance with the Bosch specification 2 0A basic CAN and 2 0B full CAN The CAN controller consists of a CAN Core Message RAM separate from the CIP 51 RAM a message handler state machine and control registers Silicon Labs CAN is a protocol controller and does not provide physi cal layer drivers i e transceivers Figure 19 2 shows an example typical configuration on a CAN bus Silicon Labs CAN operates at bit rates of up to 1 Mbit second though this can be limited by the physical layer chosen to transmit data on the CAN bus The CAN processor has 32 Message Objects that can be configured to transmit or receive data Incoming data message objects and their identifier masks are stored in the CAN message RAM All protocol functions for transmission of data and acceptance filtering is performed by the CAN controller and not by the CIP 51 MCU In this way minimal CPU bandwidth is needed to use CAN communication The CIP 51 configures the CAN controller accesses received data and passes data for transmission via Special Function Registers SFR in the CIP 51 The CAN control ler s clock fgyg or in the CAN User s Guide is equal to the CIP 51 clock SYSCLK e Rev 1 2 225 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 19 1 CAN Controller Diagram SAISIR oid C8051F060 1 2 3 CA
244. ess OxBF R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Bits7 0 ADC2 Data Word High Order Bits For AD2LJST 0 Bits 7 2 are the sign extension of Bit 1 Bits 1 0 are the upper 2 bits of the 10 bit ADC2 Data Word For AD2LJST 1 Bits 7 0 are the most significant bits of the 10 bit ADC2 Data Word Figure 7 9 ADC2L ADC2 Data Word LSB Register SFR Page 2 SFR Address OxBE R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Bits7 0 ADC2 Data Word Low Order Bits For AD2LJST 0 Bits 7 0 are the lower 8 bits of the 10 bit Data Word For AD2LJST 1 Bits 7 6 are the lower 2 bits of the 10 bit Data Word Bits 5 0 will always read 0 e Rev 1 2 95 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 7 10 ADC2CN ADC2 Control Register SFR Page 2 SFR Address OxE8 bit addressable R W R W R W R W R W R W R W R W Reset Value AD2EN AD2TM AD2INT AD2BUSY AD2CM1 AD2CMO AD2WINT AD2LJST 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Bit 7 AD2EN ADC2 Enable Bit 0 ADC2 Disabled ADC2 is in low power shutdown 1 ADC2 Enabled ADC2 is active and ready for data conversions Bit6 AD2TM ADC2 Track Mode Bit 0 Normal Track Mode When ADC2 is enabled tracking is continuous unless a conversion
245. ete It goes high when an operation is initiated and returns low when complete Read and Write commands are ignored while Busy is high In fact if poll ing for Busy to be low will be followed by another read or write operation JTAG writes of the next operation can be made while checking for Busy to be low They will be ignored until Busy is read low at which time the new operation will initiate This bit is placed at bit O to allow polling by single bit shifts When waiting for a Read to complete and Busy is 0 the following 18 bits can be shifted out to obtain the resulting data ReadData is always right justified This allows registers shorter than 18 bits to be read using a reduced number of shifts For example the results from a byte read requires 9 bit shifts Busy 8 bits 322 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 26 3 FLASHCON JTAG Flash Control Register Reset Value SFLE WRMD2 WRMD 1 WRMDO RDMD3 RDMD2 RDMD1 RDMDO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito This register determines how the Flash interface logic will respond to reads and writes to the FLASHDAT Register Bit7 SFLE Scratchpad Flash Memory Access Enable When this bit is set Flash reads and writes through the JTAG port are directed to the 128 byte Scratchpad Flash sector When SFLE is set to logic 1 Flash accesses out of the address range 0x00 0x7F should not be attempted Reads Writes out of this ra
246. etermined location in the upper partition If entry points are published software running in the upper partition may execute program code in the lower partition but it cannot read the contents of the lower partition Parameters may be passed to the program code running in the lower partition either through the typical method of placing them on the stack or in registers before the call or by placing them in prescribed memory locations in the upper partition The FAL address is specified using the contents of the Flash Access Limit Register The 16 bit FAL address is calculated as OXNNOO where NN is the contents of the FAL Security Register Thus the FAL can be located on 256 byte boundaries anywhere in program memory space However the 512 byte erase sector size essentially requires that 512 boundary be used The contents of a non initialized FAL security byte is 0x00 thereby setting the FAL address to 0x0000 and allowing read access to all locations in pro gram memory space by default Figure 16 3 FLACL Flash Access Limit R W R W R W R W R W R W R W Reset Value 00000000 SFR Address SFR Address 0xB7 SFR Page F Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Bits 7 0 FLACL Flash Access Limit This register holds the high byte of the 16 bit program memory read write erase limit address The entire 16 bit access limit address value is calculated as OXNNOO where is replaced by contents of FLACL A write to t
247. f a timer to count down When counting down the counter timer will set its overflow underflow flag TFn and cause an interrupt if enabled when the value in the timer TMRnH and TMRnL registers matches the 16 bit value in the Reload Capture Registers RCAPnH and RCAPnL This is considered an underflow event and will cause the timer to load the value OxFFFF The timer is automatically restarted when an underflow occurs Counter Timer with Auto Reload mode is selected by clearing the CP RLn bit Setting TRn to logic 1 enables and starts the timer In Auto Reload Mode the External Flag EXFn toggles upon every overflow or underflow and does not cause an interrupt The EXFn flag can be thought of as the most significant bit MSB of a 17 bit counter Figure 24 12 T2 3 and 4 Auto reload Mode Block Diagram TMRnCF njnjOjn C 110 N 5 y Toggle Logic 0 AN 2 gt OxFF OxFF 9 Port Pin SYSCLK 12 1 0 XTAL1 28 L s M uc TMRnL ovr TMRnH CP RIn Tn Crossbar 3 5 n z Tm Interrupt n Reload gt
248. f the Port Data registers and the PnMDOUT registers have no effect on the states of these pins 18 1 2 Configuring the Output Modes of the Port Pins The output drivers on Ports 0 through 3 remain disabled until the Crossbar is enabled by setting XBARE XBR2 4 to a logic 1 The output mode of each port pin can be configured to be either Open Drain or Push Pull In the Push Pull configuration writing a logic O to the associated bit in the Port Data register will cause the Port pin to be driven to GND and writing a logic 1 will cause the Port pin to be driven to VDD In the Open Drain configu ration writing a logic O to the associated bit in the Port Data register will cause the Port pin to be driven to GND and a logic 1 will cause the Port pin to assume a high impedance state The Open Drain configura tion is useful to prevent contention between devices in systems where the Port pin participates in a shared interconnection in which multiple outputs are connected to the same physical wire like the SDA signal on an SMBus connection The output modes of the Port pins on Ports 0 through 3 are determined by the bits in the associated PnMDOUT registers See Figure 18 10 Figure 18 13 Figure 18 16 and Figure 18 18 For example a logic 1 in 7 will configure the output mode of P3 7 to Push Pull a logic 0 in 7 will configure the output mode of P3 7 to Open Drain All Port pins default to Open Drain output 206 Rev
249. fset parameters be found in Table 7 1 88 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 7 2 Temperature Sensor Transfer Function Slope V deg C lt Offset V at 0 Celsius Voltage Slope x Temp Offset Tempe Vrgye Offset Slope 50 0 50 100 Temperature Celsius 7 2 Modes of Operation ADC2 has a maximum conversion speed of 200 ksps The ADC2 conversion clock is a divided version of the system clock determined by the AD2SC bits in the ADC2CF register system clock divided by AD2SC 1 for lt AD2SC lt 31 The ADC2 conversion clock should be no more than MHz 7 2 1 Starting a Conversion A conversion can be initiated in one of four ways depending on the programmed states of the ADC2 Start of Conversion Mode bits AD2CM1 0 in register ADC2CN Conversions may be initiated by one of the fol lowing Writing a 1 to the AD2BUSY bit of register ADC2CN A Timer 3 overflow i e timed continuous conversions A rising edge on the CNVSTR2 input signal Assigned by the crossbar 4 Timer 2 overflow T9 ie When CNVSTR2 is used as a conversion start source it must be enabled in the crossbar and the corre sponding pin must be set to open drain high impedance mode see Section 18 Port Input Output on page 203 for more details on Port I O configuration Writing a 1 to AD2BUSY provides software control of
250. ghput Rate 200 ksps Analog Inputs ADC Input Voltage Range Single Ended AIN AGND 0 VREF V Differential AIN AIN VREF VREF V SUME Pin Voltage with respect Single Ended or Differential 0 AV V Input Capacitance 5 pF Temperature Sensor Linearity 0 2 C Offset Temp 0 C 776 mV Offset Error Note 1 Temp 0 28 9 mV Slope 2 89 mV C Slope Error Note 1 63 uV C Power Specifications Power Supply Current VDD sup Operating Mode 200 ksps 400 900 plied to ADC2 Power Supply Rejection 0 3 mV A Note 1 Represents one standard deviation from the mean value Rev 1 2 101 SILICON LABS C8051F060 1 2 3 4 5 6 7 102 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 8 DACs 12 Bit Voltage Mode DACO and DAC1 C8051F060 1 2 3 The C8051F060 1 2 3 devices include two on chip 12 bit voltage mode Digital to Analog Converters DACs Each DAC has an output swing of 0 V to VREF 1LSB for a corresponding input code range of 0x000 to OxFFF The DACs may be enabled disabled via their corresponding control registers DACOCN and DAC1ON While disabled the DAC output is maintained in a high impedance state and the DAC sup ply current falls to 1 or less The voltage reference for each DAC is supplied at the VREFD C8051F060 2 devices or the VREF2 pin C8051F061 3 devices See Section 9 Voltage Reference 2 C8051F060 2 on page 111 or Section 10 Voltage Reference 2 C8051F061 3 on page 113 for mo
251. gic facilitates full speed in circuit debugging allowing the setting of hardware breakpoints and watch points starting stopping and single stepping through program execution including interrupt service routines examination of the program s call stack and reading writing the contents of reg isters and memory This method of on chip debug is completely non intrusive and non invasive requiring no RAM Stack timers or other on chip resources The CIP 51 is supported by development tools from Silicon Labs and third party vendors Silicon Labs pro vides an integrated development environment IDE which interfaces to the CIP 51 via its JTAG port to pro vide fast and efficient in system device programming and debugging Third party macro assemblers and C compilers are also available 13 1 Instruction Set The instruction set of the CIP 51 System Controller is fully compatible with the standard MCS 51 instruc tion set standard 8051 development tools can be used to develop software for the CIP 51 CIP 51 instructions are the binary and functional equivalent of their MCS 51 counterparts including opcodes addressing modes and effect on PSW flags However instruction timing is different than that of the stan dard 8051 13 1 1 Instruction and CPU Timing In many 8051 implementations a distinction is made between machine cycles and clock cycles with machine cycles varying from 2 to 12 clock cycles in length However the CIP 51 impl
252. gital Ground Must be tied to Ground 89 54 89 54 AV 11 16 7 10 11 16 7 10 Analog Supply Voltage Must be tied to 2 7 to 24 18 24 18 3 6 AVDD 13 23 13 23 Analog Supply Voltage Must be tied to 2 7 to 3 6 V AGND 110 14 6 11 110 14 6 11 Analog Ground Must be tied to Ground 17 23 19 22 17 23 19 22 96 52 96 52 JTAG Test Mode Select with internal pull up TCK 97 53 97 53 JTAG Test Clock with internal pull up TDI 98 56 98 56 DIn Test Data Input with internal pull up TDI is latched on the rising edge of TCK TDO 99 57 99 57 D Out JTAG Test Data Output with internal pull up Data is shifted out on TDO on the falling edge of TCK TDO output is a tri state driver RST 100 58 100 58 D I O Device Reset Open drain output of internal VDD monitor Is driven low when VDD is lt 2 7 V and MONEN is high An external source can initiate a system reset by driving this pin low XTAL1 26 20 26 20 Crystal Input This pin is the return for the internal oscillator circuit for a crystal or ceramic resonator For a precision internal clock connect a crystal or ceramic resonator from XTAL1 to XTAL2 If over driven by an external CMOS clock this becomes the system clock XTAL2 27 21 27 21 A Out Crystal Output This pin is the excitation driver for a crystal or ceramic resonator MONEN 28 63 28 63 D In VDD Monitor Enable When tied high this pin enables the internal VDD monitor
253. grammable Counter Array PCAO provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter timers PCAO consists of a dedicated 16 bit counter timer and six 16 bit capture compare modules Each capture compare module has its own associated line CEXn which is routed through the Crossbar to Port I O when enabled See Section 18 1 Ports 0 through 3 and the Priority Crossbar Decoder on page 205 The counter timer is driven by a programmable time base that can select between six inputs as its source system clock system clock divided by four system clock divided by twelve the external oscillator clock source divided by 8 Timer 0 overflow or an external clock signal on the ECI line Each capture compare module may be configured to operate independently in one of six modes Edge Triggered Capture Software Timer High Speed Output Frequency Output 8 Bit PWM or 16 Bit PWM each is described in Section 25 2 The PCA is configured and controlled through the system controller s Special Function Registers The basic PCA block diagram is shown in Figure 25 1 Figure 25 1 PCA Block Diagram SYSCLK 12 SYSCLK 4 Timer 0 Overflow SYSCLK External Clock 8 b 16 Bit Counter Timer Capture Compare Capture Compare Capture Compare Capture Compare Capture Compare Capture Compare Module 0 Module 1 Module 2 Module 3 Module 4 Mo
254. guration 188 17 4 Multiplexed and Non multiplexed 190 17 4 1 Multiplexed Configuration 190 17 4 2 Non multiplexed Configuration 191 17 5 Memory Mode 2202 2 200 4 200 192 17 5 T Intemal XRAM ONIY x sue rax 192 17 5 2 Split Mode without Bank 192 17 5 3 Split Mode with Bank Select 193 reg m 193 EM Acc Te 194 17 6 1 Non multiplexed Mode 196 17 6 1 1 16 bit MOVX EMIOCF 4 2 101 1110 or 111 196 17 6 1 2 8 bit MOVX without Bank Select EMIOCF 4 2 101 or 111 197 17 6 1 3 8 bit MOVX with Bank Select EMIOCF 4 2 110 198 17 6 2 Multiplexed Mode 199 17 6 2 1 16 bit MOVX EMIOCF 4 2 0017 010 0117 1 199 17 6 2 2 8 bit MOVX without Bank Select EMIOCF 4 2 001 or 011 200 17 6 2 3 8 bit MOVX with Bank Select EMIOCF 4 2 010 201 18 Port Inpu
255. guration Register R W R W R W R W R W R W R W R W Reset Value ADOSC3 ADOSC2 ADOSC1 ADOSCO ADOSCAL ADOGCAL ADOLCAL ADOOCAL 11110000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address OXBC SFR Page 0 Bits 7 4 ADOSC3 0 ADCO SAR Conversion Clock Period Bits SAR Conversion clock is divided down from the system clock according to the ADOSC bits ADOSC3 0 The number of system clocks used for each SAR conversion clock is equal to ADOSC 1 Note the ADCO Conversion Clock should be less than or equal to 25 MHz See Table 5 1 for conversion timing details ADOSCAL System Calibration Enable 0 Internal ground and reference voltage are used during offset and gain calibration 1 External voltages can be used during offset and gain calibration ADOGCAL Gain Calibration Read 0 Gain Calibration is completed or not yet started 1 Gain Calibration is in progress Write 0 No Effect 1 Initiates a gain calibration if ADCO is idle ADOLCAL Linearity Calibration Read 0 Linearity Calibration is completed or not yet started 1 Linearity Calibration is in progress Write 0 No Effect 1 Initiates a linearity calibration if ADCO is idle ADOOCAL Offset Calibration Read 0 Offset Calibration is completed or not yet started 1 Offset Calibration is in progress Write 0 No Effect 1 Initiates an offset calibration if ADCO is idle Bit 3 Bit 2 Bit 1
256. guration of the WDT Note Any instruction which sets the IDLE bit should be immediately followed by an instruction which has two or more opcode bytes For example ume PCON 0x01 Set IDLE bit PCON PCON Followed by a 3 cycle Dummy Instruction in assembly ORL PCON 016 Set IDLE bit MOV PCON PCON Followed by a 3 cycle Dummy Instruction If the instruction following the write to the IDLE bit is a single byte instruction and an interrupt occurs during the execution of the instruction of the instruction which sets the IDLE bit the CPU may not wake from IDLE mode when a future interrupt occurs 160 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 13 4 2 Stop Mode Setting the Stop Mode Select bit 1 causes the CIP 51 to enter Stop mode as soon as the instruc tion that sets the bit completes In Stop mode the CPU and internal oscillators are stopped effectively shutting down all digital peripherals Each analog peripheral must be shut down individually prior to enter ing Stop Mode Stop mode can only be terminated by an internal or external reset On reset the CIP 51 performs the normal reset sequence and begins program execution at address 0 0000 If enabled the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode The Missing Clock Detector should be disabled if the CPU is to be put to sleep for longer than the MCD timeout of 100 us Figure
257. gure 14 4 RSTSRC Reset Source Register R R W R W R W R R W R W R W Reset Value CNVRSEF CORSEF SWRSEF WDTRSF MCDRSF PORSF PINRSF 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO SFR Address OxEF SFR Page 0 Bit7 Reserved Bit6 CNVRSEF Convert Start Reset Source Enable and Flag Write 0 CNVSTR2 is not a reset source 1 CNVSTR2 is a reset source active low Read 0 Source of prior reset was not CNVSTR2 1 Source of prior reset was CNVSTR2 Bit5 CORSEF Reset Enable and Flag Write 0 Comparator0 is not a reset source 1 ComparatorO is a reset source active low Read 0 Source of last reset was not Comparator0 1 Source of last reset was Bit4 SWRSF Software Reset Force and Flag Write 0 No effect 1 Forces an internal reset RST pin is not effected Read 0 Source of last reset was not a write to the SWRSF bit 1 Source of last reset was a write to the SWRSF bit Bit3 WDTRSF Watchdog Timer Reset Flag 0 Source of last reset was not WDT timeout 1 Source of last reset was WDT timeout Bit2 MCDRSF Missing Clock Detector Flag Write 0 Missing Clock Detector disabled 1 Missing Clock Detector enabled triggers a reset if a missing clock condition is detected Read 0 Source of last reset was not a Missing Clock Detector timeout Source of last reset was a Missing Clock Detector timeout PORSF Power On Reset Flag Wri
258. he DMA interface works in conjunction with ADCO and ADC1 to write ADC outputs directly to a specified region of XRAM The interface is configured by software using the Special Function Registers shown in Figure 6 1 Up to 64 instructions can be programmed into the Instruction Buffer to designate a sequence of DMA operations The Instruction Buffer is accessed by the DMA Control Logic which gathers the appro priate data from the ADCs and controls writes to XRAM The DMA instructions tell the DMA Control Logic which ADC s to expect results from but do not initiate the actual conversions It is important to configure the ADCs for the desired start of conversion source voltage reference and SAR clock frequency prior to starting the DMA interface For information on setting up the ADCs refer to Section 5 16 Bit ADCs ADCO and ADC1 on page 51 Figure 6 1 DMAO Block Diagram DMAOCF DMAOCN i Address Instruction Data H gt uo gt E g 1610 5 5 DMAOIPT DMAOIDT als lt lt lt lt lt lt lt lt lt lt lt lt lt lt gt gt gt gt gt 2 2 2255 Y Y ala Write Logic T Current Address Y DMAOISW L Instruction Buffer Start Address 64 Bytes DMAOBND gt Address Bus Data Bus
259. he SFR Page Stack Software can now access the ADC2 SFRs Software may switch While CIP 51 executes in line code writing values to Port 5 in this example ADC2 Window Comparator to any SFR Page by writing a new value to the SFRPAGE register at any time during the ADC2 ISR to access SFRs that are not on SFR Page 0x02 See Figure 13 5 below its o 2 LLI O gt lt A Z 1 or z LL LL LL 8 5 8 8 3 cA Q lt S s 2 06 8 lt 558 m lt lt ep G s o 5 w ll ww Lu o 5 g Q agez T Low 5 gt SILICON LABS C8051F060 1 2 3 4 5 6 7 While in the ADC2 ISR a PCA interrupt occurs Recall the PCA interrupt is configured as a high priority interrupt while the ADC2 interrupt is configured as a low priority interrupt Thus the CIP 51 will now vector to the high priority PCA ISR Upon doing so the CIP 51 will automatically place the SFR page needed to access the PCA s special function registers into the SFRPAGE register SFR Page 0x00 The value that was in the SFRPAGE register before the PCA interrupt SFR Page 2 for ADC2 is pushed down the stack into SFRNEXT Likewise the value that was in the SFRNEXT register before the PCA interrupt in this case SFR Page for Port 5 is pushed d
260. he simplest means of programming the Flash memory is through the JTAG interface using programming tools provided by Silicon Labs or a third party vendor This is the only means for programming a non initial ized device For details on the JTAG commands to program Flash memory see Section 26 JTAG IEEE 1149 1 on page 317 The Flash memory can be programmed from software using the MOVX write instruction with the address and data byte to be programmed provided as normal operands Before writing to Flash memory using MOVX Flash write operations must be enabled by setting the PSWE Program Store Write Enable bit PSCTL 0 to logic 1 This directs the MOVX writes to Flash memory instead of to XRAM which is the default target The PSWE bit remains set until cleared by software To avoid errant Flash writes it is rec ommended that interrupts be disabled while the PSWE bit is logic 1 Flash memory is read using the MOVC instruction MOVX reads are always directed to XRAM regardless of the state of PSWE NOTE To ensure the integrity of Flash memory contents it is strongly recommended that the on chip VDD monitor be enabled by connecting the VDD monitor enable pin MONEN to VDD and set ting the PORSF bit in the RSTSRC register to 1 in any system that writes and or erases Flash memory from software See Reset Sources on page 163 for more information A write to Flash memory can clear bits but cannot set them only an erase operation can
261. her that pin has been assigned to a digital peripheral or behaves as GPIO The Port pins on Port 2 can be used as analog inputs to the ana log Voltage comparators On the C8051F060 1 2 8 the pins of Port 1 can be used as analog inputs for ADC2 The upper Ports available on C8051F060 2 4 6 can be byte accessed as GPIO pins or used as part of an External Memory Interface which is active during a MOVX instruction whose target address resides in off chip memory See Section 17 External Data Memory Interface and On Chip XRAM on page 187 for more information about the External Memory Interface Figure 18 2 Port Functional Block Diagram XBRO XBR1 XBR2 XBR3 P1MDIN Highest 2 POMDOUT P1MDOUT Priority ARTA P2MDOUT P3MDOUT Registers Registers Priority Pins Decoder 5 0 Highest g A 10 Priority S Cels si 2 Outputs Digital Y Crossbar 8 Pi ps Pe g lt hr 0 I TO T1 T2 2 Cells T3 8 i T4 T4EX i INTO Y INT1 2 PRO o SYSCLK Cells P27 Lowest Priority NVSTR2 m Y E P3 0 1 lt o Lowest Cells P3 7 Priority P0 0 P0 7 B ADC2 C8051F060 2 i Input Log cy To
262. heral Interface SPlIO 251 1 2 13 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 21 1 SPI Block Diagram 00 2 080000 251 Figure 21 2 Multiple Master Mode Connection 254 Figure 21 3 3 Wire Single Master and 3 Wire Single Slave Mode Connection Diagram 254 Figure 21 4 4 Wire Single Master Mode and 4 Wire Slave Mode Connection Diagram 254 Figure 21 5 Master Mode Data Clock 256 Figure 21 6 Slave Mode Data Clock Timing CKPHA 0 257 Figure 21 7 Slave Mode Data Clock Timing CKPHA 1 257 Figure 21 8 SPIOCFG SPIO Configuration Register 258 Figure 21 9 SPIOCN SPIO Control 4400 259 Figure 21 10 SPIOCKR SPIO Clock Rate Register 260 Figure 21 11 SPIODAT SPIO Data 261 Figure 21 12 SPI Master Timing CKPHA 0 262 Figure 21 13 SPI Master Timing CKPHA 1 262 Figure 21 14 SPI Slave Timing CKPHA 0 263 Figure 21 15 SPI Slave Timing 1
263. herals The CIP 51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub systems unique to the MCU This allows the addition of new functionality while retaining compatibility with the MCS 51 instruction set Table 13 2 lists the SFRs implemented in the CIP 51 System Controller The SFRs are accessed whenever the direct addressing mode is used to access memory locations from 0x80 to OxFF SFRs with addresses ending in OxO or 0x8 e g PO TCON P1 SCON IE etc are bit addressable as well as byte addressable All other SFRs are byte addressable only Unoccupied addresses in the SFR space are reserved for future use Accessing these areas will have an indeterminate effect and should be avoided Refer to the corresponding pages of the datasheet as indicated in Table 13 3 for a detailed description of each register 13 2 6 1 SFR Paging The CIP 51 features SFR paging allowing the device to map many SFRs into the 0x80 to OxFF memory address space The SFR memory space has 256 pages In this way each memory location from 0x80 to OxFF can access up to 256 SFRs The C8051F06x family of devices utilizes five SFR pages 0 1 2 3 and F SFR pages are selected using the Special Function Register Page Selection register SFRPAGE see Figure 13 10 The procedure for reading and writing an SFR is as follows 1 Select the appropriate SFR page number using the SFRPAGE reg
264. his register sets the Flash Access Limit This register can only be written once after any reset Any subsequent writes are ignored until the next reset To fully protect all addresses below this limit bit 0 of FLACL should be set to 0 to align the FAL on a 512 byte Flash page boundary 182 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 16 3 1 Summary of Flash Security Options There are three Flash access methods supported on the C8051F060 1 2 3 4 5 6 7 1 Accessing Flash through the JTAG debug interface 2 Accessing Flash from firmware residing below the Flash Access Limit and 3 Accessing Flash from firmware residing at or above the Flash Access Limit Accessing Flash through the JTAG debug interface 1 o P 8 The Read and Write Erase Lock bytes security bytes provide security for Flash access through the JTAG interface Any unlocked page may be read from written to or erased Locked pages cannot be read from written to or erased Reading the security bytes is always permitted Locking additional pages by writing to the security bytes is always permitted If the page containing the security bytes is unlocked it can be directly erased Doing so will reset the security bytes and unlock all pages of Flash If the page containing the security bytes is locked it cannot be directly erased To unlock the page containing the security bytes a full JTAG device erase is required A full JTAG
265. icant bits hold the 7 bit slave address The least significant bit is used to enable the recognition of the general call address 0x00 If BitO is set to logic 1 the general call address will be recog nized Otherwise the general call address is ignored The contents of this register are ignored when Rev 1 2 245 SILICON LABS C8051F060 1 2 3 4 5 6 7 SMBusO is operating in master mode Figure 20 11 SMBOADR SMBus0 Address Register R W R W R W R W R W R W R W R W Reset Value SLV6 SLV5 SLV4 SLV3 SLV2 SLV1 SLVO GC 00000000 Bit7 Bite Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xC3 SFR Page 0 Bits7 1 SLV6 SLV0 SMBusO Slave Address These bits are loaded with the 7 bit slave address to which SMBusO will respond when oper ating as a slave transmitter or slave receiver SLV6 is the most significant bit of the address and corresponds to the first bit of the address byte received BitO GC General Call Address Enable This bit is used to enable general call address 0x00 recognition 0 General call address is ignored 1 General call address is recognized 20 4 5 Status Register The SMBOSTA Status register holds 8 bit status code indicating the current state of the SMBusO inter face There 28 possible SMBusO states each with a corresponding unique status code The five most significant bits of the status code vary while the three least significant bits of a valid
266. ification by soft ware as well as prevent the viewing of proprietary program code and constants The Program Store Write Enable PSCTL 0 and the Program Store Erase Enable PSCTL 1 bits protect the Flash memory from accidental modification by software These bits must be explicitly set to logic 1 before software can write or erase the Flash memory Additional security features prevent proprietary program code and data constants from being read or altered across the JTAG interface or by software running on the system controller A set of security lock bytes protect the Flash program memory from being read or altered across the JTAG interface Each bit in a security lock byte protects one 8k byte block of memory Clearing a bit to logic O in a Read Lock Byte prevents the corresponding block of Flash memory from being read across the JTAG interface Clearing a bit in the Write Erase Lock Byte protects the block from JTAG erasures and or writes The Scratchpad area is read or write erase locked when all bits in the corresponding security byte are cleared to logic O On the C8051F060 1 2 3 4 5 the security lock bytes are located at OxFBFE Write Erase Lock and OxFBFF Read Lock as shown in Figure 16 1 On the C8051F066 7 the security lock bytes are located at Ox7FFE Write Erase Lock and Ox7FFF Read Lock as shown in Figure 16 2 The 512 byte sector con taining the lock bytes can be written to but not erased by software An attempted read of a read
267. ignificant Byte Rev 1 2 107 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 8 7 DAC1CN DAC1 Control Register R W R W R W R W R W R W R W R W Reset Value DAC1EN DAC1MD1 DAC1MDO DAC1DF2 DAC1DF1 DAC1DFO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xD4 SFR Page 1 Bit7 DAC1EN DAC1 Enable Bit 0 DAC1 Disabled DAC1 Output pin is disabled DAC1 is in low power shutdown mode 1 DAC1 Enabled DAC1 Output is active DAC1 is operational Bits6 5 UNUSED Read 00b Write don t care Bits4 3 DAC1MD1 0 DAC1 Mode Bits 00 DAC output updates occur on a write to DAC1H 01 DAC output updates occur on Timer 3 overflow 10 DAC output updates occur on Timer 4 overflow 11 DAC output updates occur on Timer 2 overflow Bits2 0 DAC1DF2 DAC1 Data Format Bits 000 most significant nibble of the DAC1 Data Word is in DAC1H 3 0 while the least significant byte is in DAC1L MSB LSB 001 The most significant 5 bits of the DAC1 Data Word is in DAC1H 4 0 while the least significant 7 bits are in DAC1L 7 1 MSB LSB 010 The most significant 6 bits of the DAC1 Data Word is in DAC1H 5 0 while the least significant 6 bits are in DAC1L 7 2 DAC1H DAC1L MSB LSB 011 MSB The most significant 7 bits of the DAC1 Data Word is in DAC1H 6 0 while the least significant 5 bits are in DAC1L 7 3 DAC1H DAC1L LSB 1 The m
268. il STOP appears on the bus or a Bus Free Timeout occurs Hardware automatically clears the STO flag to logic 0 when a STOP condition is detected on the bus The Serial Interrupt flag 51 SMBOCN 3 is set to logic 1 by hardware when the SMBusO interface enters one of 27 possible states If interrupts are enabled for the SMBusO interface an interrupt request is gener ated when the SI flag is set The SI flag must be cleared by software Important Note If SI is set to logic 1 while the SCL line is low the clock low period of the serial clock will be stretched and the serial transfer is suspended until SI is cleared to logic 0 A high level on SCL is not affected by the setting of the SI flag The Assert Acknowledge flag AA SMBOCN 2 is used to set the level of the SDA line during the acknowl edge clock cycle on the SCL line Setting the AA flag to logic 1 will cause an ACK low level on SDA to be sent during the acknowledge cycle if the device has been addressed Setting the AA flag to logic O will cause a NACK high level on SDA to be sent during acknowledge cycle After the transmission of a byte in slave mode the slave can be temporarily removed from the bus by clearing the AA flag The slave s own address and general call address will be ignored To resume operation on the bus the AA flag must be reset to logic 1 to allow the slave s address to be recognized e Rev 1 2 241 SILICON LABS C8051F060 1 2 3 4 5 6 7 Setting
269. interrupt disabled 1 Comparator rising edge interrupt enabled Bit 4 CPnFIE Comparator Falling Edge Interrupt Enable Bit 0 Comparator falling edge interrupt disabled 1 Comparator falling edge interrupt enabled Bits3 2 UNUSED Read 00b Write don t care Bits1 0 CPnMD1 CPnMDO Comparator Mode Select These bits select the response time for the Comparator Mode CPnMD1 CPnMDO Notes 0 0 0 Fastest Response Time 1 0 1 2 1 0 Lowest Power Consump 3 1 1 tion 1 2 121 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 12 1 Comparator Electrical Characteristics VDD 3 0 V 40 to 85 unless otherwise specified Parameter Conditions Min Typ Max Units Response Time CPn CPn 100 mV 100 ns Mode 0 CPn CPn 10 mV 250 ns Response Time CPn CPn 100 mV 175 ns Mode 1 CPn CPn 10 mV 500 ns Response Time CPn 100 mV 320 ns Mode 2 CPn CPn 10 mV 1100 ns Response Time CPn CPn 100 mV 1050 ns Mode 3 CPn CPn 10 mV 5200 ns Common Mode Rejection 1 5 4 mV V Ratio Positive Hysteresis 1 CPnHYP1 0 00 0 1 mV Positive Hysteresis 2 CPnHYP1 0 01 3 5 7 mV Positive Hysteresis 3 CPnHYP1 0 10 7 10 15 mV Positive Hysteresis 4 CPnHYP1 0 11 15 20 25 mV Negative Hysteresis 1 CPnHYN 1 0 00 0 1 mV Negative Hysteresis 2 CPnHYN1 0 01 3 5 7 mV Negative Hysteresis 3 CPnH
270. ion on interrupt exit Modifying registers in the SFR Page Stack does not cause a push or pop of the stack Only interrupt calls and returns will cause push pop operations on the SFR Page Stack 132 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 13 3 SFR Page Stack SFRPGCN Bit Interrupt Logic SFRPAGE Automatic hardware switching of the SFR Page on interrupts may be enabled or disabled as desired using the SFR Automatic Page Control Enable Bit located in the SFR Page Control Register SFRPGON This function defaults to enabled upon reset In this way the autoswitching function will be enabled unless dis abled in software summary of the SFR locations address and SFR page is provided in Table 13 2 in the form of an SFR memory map Each memory location in the map has an SFR page row denoting the page in which that SFR resides Note that certain SFRs are accessible from ALL SFR pages and are denoted by the ALL PAGES designation For example the Port I O registers PO P1 P2 and all have the ALL PAGES designation indicating these SFRs are accessible from all SFR pages regardless of the SFRPAGE register value Rev 1 2 133 SILICON LABS 1 Page OxOF device is also using the Programmable Counter Array PCA and the 10 bit ADC ADC2 window comparator to monitor a voltage The PCA is timing a critical control function in its inter
271. ipheral Interface 0x0033 6 SPI0CN 5 Y EIE1 0 EIP1 0 RXOVRN SPI0CN 4 ESMB0 PSMB0 SMBus Interface 0x003B 7 SI SMB0CN 3 Y EIE1 1 EIP1 1 ADC0 Window EWADCO PWADCO Comparator 0 0043 8 JADOWINT ADCOCN 1 Y EIEt 2 Programmable Counter 0x004B 9 CF 7 Y Array CCFn PCAOCN n EIE1 3 EIP1 3 CPOFIF CPORIF CPOIE PCPO 0 0053 10 PTOCN A 5 Li EIE1 4 1 4 CP1FIF CP1RIF CP1IE PCP1 0x005B 1 CPTICN 4 5 EIE1 5 EIP1 5 CP2FIF CP2RIF CP2IE PCP2 Comparator 0x0063 12 CPT2CN 4 5 Y EIE1 6 1 6 EADC0 PADC0 ADC0 End of Conversion 0x006B 13 ADCOINT ADC0CN 5 EIE1 7 EIP1 7 ET3 PT3 Timer 3 0x0073 14 7 Y EIE2 0 EIP2 0 EADC1 PADC1 ADC1 End of Conversion 0x007B 15 J ADC1INT ADC1CN 5 Y EIE2 1 EIP2 1 5 4 4 4 0 0083 16 TF4 TMR4CN 7 Y EIE2 2 EIP2 2 ADC2 Window EWADC2 PWADC2 Comparator 0x008B 17 AD2WINT ADC2CN 1 Y EIE2 3 EIP2 3 EADC2 PADC2 ADC2 End of Conversion 0x0093 18 AD2INT ADC2CN 5 Y EIE2 4 EIP2 4 ECANO PCANO CAN Interrupt 0x009B 19 CANOCN 7 Y EIE2 5 EIP2 5 SCON1 0 ES1 PS1 VARTI Ox00A3 20 T SCONI 1 EIP2 6 2 6 EDMAO PDMAO DMAO Interrupt 0x00AB 21 DMAOINT DMAOCN 6 Y EIE2 7 EIP2 7 152 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 13 3 3 Interrupt Priorities
272. is 0 and the processor core will have full access to off chip XRAM when this bit is 1 The DMAOHLT bit should be controlled in software when both the processor core and the DMA Interface require access to off chip XRAM data space Before setting DMAOHLT to 1 the software should check the DMAOXBY bit to ensure that the DMA is not currently accessing off chip XRAM The processor core can not access off chip XRAM while DMAOHLT is 0 The processor will continue as though it was able to per form the desired memory access but the data will not be written to or read from off chip XRAM When the processor core is finished accessing off chip XRAM DMAOHLT should be set back to O0 in software to return control to the Interface The Control Logic will wait until DMAOHLT is 0 before writing data to off chip XRAM If new data becomes available to the DMA Interface before the previous data has been written an overflow condition will occur and the new data word may be lost The Data Address Pointer Registers and DMAODSL contain the 16 bit XRAM address loca tion where the DMA interface will write data When the DMA is initially enabled the DMA Data Address 76 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Pointer Registers are initialized to the values contained in the DMA Data Address Beginning Registers DMAODAH and DMAODAL The Data Address Pointer Registers are automatically incremented b
273. is in progress 1 Low power Track Mode Tracking Defined by AD2CM2 0 bits see below Bit5 AD2INT ADC2 Conversion Complete Interrupt Flag 0 ADC2 has not completed a data conversion since the last time AD2INT was cleared 1 ADC2 has completed a data conversion Bit 4 AD2BUSY ADC2 Busy Bit Read 0 ADC2 conversion is complete or a conversion is not currently in progress AD2INT is set to logic 1 on the falling edge of AD2BUSY 1 ADC2 conversion is in progress Write 0 No 1 Initiates ADC2 Conversion if AD2CM2 0 000b Bits 3 2 AD2CM1 0 ADC2 Start of Conversion Mode Select When AD2TM 0 00 ADC2 conversion initiated on every write of 1 to AD2BUSY 01 ADC2 conversion initiated on overflow of Timer 3 10 ADC2 conversion initiated on rising edge of external CNVSTR2 pin 11 ADC2 conversion initiated on overflow of Timer 2 When AD2TM 1 00 Tracking initiated on write of 1 to AD2BUSY and lasts 3 SAR clocks followed by con version 01 Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks followed by conver sion 10 ADC2 tracks only when CNVSTR2 input is logic low conversion starts on rising CNVSTR2 edge 11 Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks followed by conversion Bit 1 AD2WINT ADC2 Window Compare Interrupt Flag 0 ADC2 Window Comparison Data match has not occurred since this flag was last cleared 1 ADC2 Window Comparison Data match has occurred Bit 0
274. ister 2 Use direct accessing mode to read or write the special function register MOV instruction 13 2 6 2 Interrupts and SFR Paging When an interrupt occurs the SFR Page Register will automatically switch to the SFR page containing the flag bit that caused the interrupt The automatic SFR Page switch function conveniently removes the bur den of switching SFR pages from the interrupt service routine Upon execution of the RETI instruction the SFR page is automatically restored to the SFR Page in use prior to the interrupt This is accomplished via a three byte SFR Page Stack The top byte of the stack is SFRPAGE the current SFR Page The second byte of the SFR Page Stack is SFRNEXT The third or bottom byte of the SFR Page Stack is SFRLAST On interrupt the current SFRPAGE value is pushed to the SFRNEXT byte and the value of SFRNEXT is pushed to SFRLAST Hardware then loads SFRPAGE with the SFR Page containing the flag bit associated with the interrupt On a return from interrupt the SFR Page Stack is popped resulting in the value of SFRNEXT returning to the SFRPAGE register thereby restoring the SFR page context without software intervention The value in SFRLAST 0x00 if there is no SFR Page value in the bottom of the stack of the stack is placed in SFRNEXT register If desired the values stored in SFRNEXT and SFRLAST may be modified during an interrupt enabling the CPU to return to a different SFR Page upon execution of the RETI instruct
275. isters SFRs associated with it in the CIP 51 system controller These registers are used to exchange data with a module and configure the module s mode of operation Table 25 2 summarizes the bit settings in the PCAOCPMn registers used to select the PCAO capture com pare module s operating modes Setting the ECCFn bit in a PCAOCPMn register enables the module s CCFn interrupt Note PCAO interrupts must be globally enabled before individual CCFn interrupts are rec ognized PCAO interrupts are globally enabled by setting the EA bit IE 7 and the EPCAO bit EIE1 3 to logic 1 See Figure 25 3 for details on the PCA interrupt configuration Table 25 2 PCAOCPM Register Settings for PCA Capture Compare Modules PWM16 ECOM PWM Operation Mode X X 1 0 0 0 0 X Capture triggered by positive edge on CEXn X X 0 1 0 0 0 X Capture triggered by negative edge on CEXn X X 1 1 0 0 0 X Capture triggered by transition on CEXn X 1 0 0 1 0 0 X Software Timer X 1 0 0 1 1 0 X High Speed Output X 1 0 0 0 1 1 X Frequency Output 0 1 0 0 0 0 1 0 8 Bit Pulse Width Modulator 1 1 0 0 0 0 1 0 16 Bit Pulse Width Modulator X Don t Care Figure 25 3
276. it3 Bit2 Bit1 Bito SFR Address 0xAD SFR Page F P1MDIN 7 0 Port 1 Input Mode Bits 0 Port Pin is configured in Analog Input mode The digital input path is disabled a read from the Port bit will always return 0 The weak pull up on the pin is disabled 1 Port Pin is configured in Digital Input mode A read from the Port bit will return the logic level at the Pin The state of the weak pull up is determined by the WEAKPUD bit XBR2 7 see Figure 18 7 e Rev 1 2 215 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 18 13 PIMDOUT Port1 Output Mode Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0xA5 SFR Page F Bits7 0 P1MDOUT 7 0 Porti Output Mode Bits 0 Port Pin output mode is configured as Open Drain 1 Port Pin output mode is configured as Push Pull Note SDA SCL and when UARTO is in Mode 0 and RX1 when is in Mode 0 always configured as Open Drain when they appear on Port pins Figure 18 14 P2 Port2 Data Register R W R W R W R W R W R W R W R W Reset Value P2 7 P2 6 P2 5 P2 4 P2 3 P2 2 P2 1 P2 0 11111111 Bit7 Bite Bits Bit4 Bit2 Bit B SFR Address 0 0 SFR Page All Pages Bits7 0 P2 7 0 Port2 Output Latch Bits Write Output appears on I O pins per XBRO XBR1 XBR2 and Registers
277. ive buffer It returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on SCK NOTE SRMT 1 when in Master Mode Bit 0 RXBMT Receive Buffer Empty Valid in Slave Mode read only This bit will be set to logic 1 when the receive buffer has been read and contains no new information If there is new information available in the receive buffer that has not been read this bit will return to logic O NOTE RXBMT 1 when in Master Mode TIn slave mode data on MOSI is sampled in the center of each data bit In master mode data on MISO is sampled one SYSCLK before the end of each data bit to provide maximum settling time for the slave device See Table 21 1 for timing parameters 258 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 21 9 SPIOCN SPIO Control Register R W R W R W R W R W R W R R W Reset Value SPIF WCOL MODF RXOVRN NSSMD1 NSSMDO TXBMT SPIEN 00000110 7 I Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address 0xF8 SFR Page 0 Bit 7 SPIF SPI0 Interrupt Flag This bit is set to logic 1 by hardware at the end of a data transfer If interrupts are enabled setting this bit causes the CPU to vector to the SPIO interrupt service routine This bit is not automatically cleared by hardware It must be cleared by software Bit 6 WCOL Write Collision Flag This bit is set to logic 1 b
278. kB C8051F060 1 2 3 4 5 32 C8051 F066 7 Flash In system programmable in 512 byte sectors External 64 kB data memory interface with multi plexed and non multiplexed modes C8051F060 2 4 6 Digital Peripherals 59 general purpose I O pins C8051F060 2 4 6 24 general purpose pins C8051F061 3 5 7 Bosch Controller Area Network CAN 2 0B C8051F060 1 2 3 Hardware SMBus 2 Compatible SPI and two UART serial ports available concurrently Programmable 16 bit counter timer array with 6 capture compare modules 5 general purpose 16 bit counter timers Dedicated watchdog timer bi directional reset Clock Sources Internal calibrated precision oscillator 24 5 MHz External oscillator Crystal RC C or clock Supply Voltage 2 7 to 3 6 V Multiple power saving sleep and shutdown modes 100 Pin and 64 Pin Packages Available Temperature Range 40 to 85 Interface 12 Bit 10 bit TEMP DAC lt DAC C8051F060 1 2 3Only 25MIPS ISP FLASH SRAM 22 DEBUG CLOCK SANITY 2 08 C8051F060 1 2 3 UARTO UART1 SMBus SPI Bus PCA Timer 0 CROSSBAR Timer 1 Timer 2 External Memory Interface Timer 3 Timer 4 Rev 1 2 12 03 Copyright 2003 Silicon Laboratories C8051F060 1 2 3 4 5 6 7 C8051F060 1 2
279. ks Track Hold Acquisition Time 280 ns Throughput Rate 1 Msps Aperture Delay External CNVST Signal 1 5 ns RMS Aperture Jitter External CNVST Signal 5 ps Analog Inputs Input Voltage Range Single Ended AINn AINnG 0 VREF V Differential AINO AIN1 VREF VREF V Input Capacitance 80 pF Rev 1 2 73 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 5 2 16 Bit ADCO and ADC1 Electrical Characteristics Continued VDD 3 0 V AV 3 0 V AVDD 3 0 V VREF 2 50 V 0 40 to 85 C unless otherwise specified Parameter Conditions Min Typ Max Units Operating Input Range AINO or AIN1 0 2 AV V AINOG or AIN1G DC Only 0 2 0 6 V Power Specifications Power Supply Current each Operating Mode 1 Msps ADC AV 4 0 mA AVDD 2 0 mA Shutdown Mode lt 1 uA Power Supply Rejection VDD 5 0 5 LSB Table 5 3 Voltage Reference 0 and 1 Electrical Characteristics VDD 3 0 V AV 3 0 V AVDD 3 0 V 40 to 85 C unless otherwise specified Parameter Conditions Min Typ Max Units Internal Reference Output Voltage 25 C ambient 2 36 2 43 2 48 V VREF Temperature Coefficient 15 ppm C Power Supply Current each 1 5 mA Voltage Reference External Reference Input Voltage Range 2 0 AV V Input Current ADC throughput 1 Msps 450 74 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 6 Direct Memory Access Interface DMAO T
280. le Interrupt requests generated by the SPIO flag 156 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 R W Figure 13 22 EIE2 Extended Interrupt Enable 2 R W R W R W R W R W R W R W Reset Value EDMAO ES1 ECANO EADC2 EWADC2 ET4 EADC1 ET3 00000000 Bit7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0xE7 SFR Page All Pages EDMAO Enable Interrupt This bit sets the masking of the Interrupt 0 Disable DMAO interrupt 1 Enable DMAO interrupt ES1 Enable UART1 Interrupt This bit sets the masking of the UART1 Interrupt 0 Disable UART1 interrupt 1 Enable UARTI interrupt ECANO Enable CAN Controller Interrupt This bit sets the masking of the CAN Controller Interrupt 0 Disable CAN Controller Interrupt 1 Enable interrupt requests generated by the CAN Controller EADC2 Enable ADC2 End Of Conversion Interrupt This bit sets the masking of the ADC2 End of Conversion interrupt 0 Disable ADC2 End of Conversion interrupt 1 Enable interrupt requests generated by the ADC2 End of Conversion Interrupt EWADC2 Enable Window Comparison ADC1 Interrupt This bit sets the masking of ADC2 Window Comparison interrupt 0 Disable ADC2 Window Comparison Interrupt 1 Enable Interrupt requests generated by ADC2 Window Comparisons ET4 Enable Timer 4 Interrupt This bit sets the
281. le to pin follows numbering scheme 57 59 61 63 65 Capture P3 n input from pin follows numbering scheme 67 69 71 Update P3 n output to pin follows PO n numbering scheme 72 74 76 Capture P4 5 P4 6 P4 7 respectively output enable from MCU Update 4 5 P4 6 P4 7 respectively output enable to pin 73 75 77 Capture P4 5 P4 6 4 7 respectively input from pin Update 4 5 P4 6 P4 7 respectively output to pin 78 80 82 84 86 Capture P5 n output enable from MCU follows PO n numbering scheme 88 90 92 Update 5 output enable to pin follows numbering scheme 318 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 26 1 Boundary Data Register Bit Definitions C8051F060 2 4 6 Continued EXTEST provides access to both capture and update actions while Sample only performs a capture Bit Action Target 79 81 83 85 87 89 91 93 Capture P5 n input from pin follows PO n numbering scheme Update P5 n output to pin follows PO n numbering scheme 94 96 98 100 102 104 106 108 Capture P6 n output enable from MCU follows PO n numbering scheme Update P6 n output enable to pin follows PO n numbering scheme 95 97 99 101 103 105 107 109 Capture P6 n input from pin follows PO n numbering scheme Update P6 n output to pin follows PO n numbering scheme 110 112 114 116 1
282. lled low When a Mode Fault occurs the MSTEN and SPIEN bits in SPIOCN are set to logic 0 to disable SPIO and allow another master device to access the bus 4 The Receive Overrun Flag RXOVRN SPIOCN 4 is set to logic 1 when configured as a slave and a transfer is completed and the receive buffer still holds an unread byte from a previous transfer The new byte is not transferred to the receive buffer allowing the previously received data byte to be read The data byte which caused the overrun is lost e Rev 1 2 255 SILICON LABS C8051F060 1 2 3 4 5 6 7 21 5 Serial Clock Timing Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPIO Configuration Register SPIOCFG The CKPHA bit SPIOCFG 5 selects one of two clock phases edge used to latch the data The CKPOL bit SPIOCFG 4 selects between an active high or active low clock Both master and slave devices must be configured to use the same clock phase and polarity SPIO should be disabled by clearing the SPIEN bit when changing the clock phase or polarity The clock and data line relationships for master mode are shown in Figure 21 5 For slave mode the clock and data relationships are shown in Figure 21 6 and Figure 21 7 Note that CKPHA must be set to 0 on both the master and slave SPI when communicating between two of the following devices C8051F04x C8051F06x C8051F12x C8051F31x C8051F32x and C8
283. location 0x0000 software can read the PORSF flag to determine if a power up was the cause of reset The contents of internal data memory should be assumed to be undefined after a power on reset Figure 14 2 Reset Timing 2 70 2 55 2 0 Logic HIGH Logic LOW Power On Reset VDD Monitor Reset 14 2 Power fail Reset When a power down transition or power irregularity causes VDD to drop below the power supply monitor will drive the RST pin low and return the CIP 51 to the reset state When VDD returns to a level above VRST the CIP 51 will leave the reset state in the same manner as that for the power on reset see Figure 14 2 Note that even though internal data memory contents are not altered by the power fail reset itis impossible to determine if VDD dropped below the level required for data retention If the PORSF flag is set to logic 1 the data may no longer be valid 14 3 External Reset The external RST pin provides a means for external circuitry to force the MCU into a reset state Asserting the RST pin low will cause the MCU to enter the reset state It may be desirable to provide an external pull up and or decoupling of the RST pin to avoid erroneous noise induced resets The MCU will remain in 164 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 reset until at least 12 clock cycles after the active low RST signal is removed The PINRSF flag RSTSRC 0 is set on exit from an external reset
284. lock 1 MHz 0 7 mA Note 3 VDD 2 7 V Clock 32 kHz 30 VDD 3 0 V Clock 25 MHz 20 mA VDD 3 0 V Clock 1 MHz 1 0 mA VDD 3 0 V Clock 32 kHz 35 Supply Current from CPU VDD 2 7 V 25 MHz 13 mA Digital Peripherals CPU inac VDD 2 7 V Clock 1 MHz 0 5 mA tive not accessing Flash VDD 2 7 V Clock 32 kHz 20 3 VDD 3 0 Clock 25 MHz 16 mA VDD 3 0 V Clock 1 MHz 0 8 mA VDD 3 0 V Clock 32 kHz 23 Supply Current with all systems Oscillator not running 0 2 shut down VDD Supply RAM Data Reten 1 5 V tion Voltage SYSCLK System Clock Note 4 0 25 MHz Specified Operating Tempera 40 85 C Note 1 Analog Supply AV must be greater than 1 V for VDD monitor to operate Note 2 Internal Oscillator and VDD Monitor current not included Individual supply current contributions for each peripheral are listed in the chapter Note 3 Current increases linearly with supply Voltage Note 4 SYSCLK must be at least 32 kHz to enable debugging 38 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 4 Pinout and Package Definitions Table 4 1 Pin Definitions Pin Numbers Name F060 F061 F064 F065 Type Description F062 F063 F066 F067 VDD 37 64 26 40 37 64 26 40 Digital Supply Voltage Must be tied to 2 7 to 90 55 90 55 3 6 V 138 63 27 39 38 63 27 39 Di
285. locks will meet the minimum tracking time requirements Figure 7 4 shows the equivalent ADC2 input circuits for both Differential and Single ended modes Notice that the equivalent time constant for both input circuits is the same The required ADC2 settling time for a given settling accuracy SA may be approximated by Equation 7 1 When measuring the Temperature Sensor output reduces to See Table 7 1 for ADC2 minimum settling time requirements Equation 7 1 ADC2 Settling Time Requirements n t 22 RroTALCSAMPLE Where SA is the settling accuracy given as a fraction of an LSB for example 0 25 to settle within 1 4 LSB tis the required settling time in seconds is the sum of the AMUX2 resistance and any external source resistance nis the ADC resolution in bits 10 Figure 7 4 ADC2 Equivalent Input Circuits Differential Mode Single Ended Mode MUX Select MUX Select Pix o e Pix 5k Ryux L saung SPF CSsampre R Cpu Ruux T1 R Csampre SPF 1 6 P Ruux 5k MUX Select Rev 1 2 91 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 7 5 AMX2CF AMUX2 Configuration Register SFR Page 2 SFR Address OxBA R W R W R W R W R W R W R W R W Reset Value AI
286. logic 1 e Rev 1 2 247 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 20 1 SMBOSTA Status Codes and States 0x08 START condition transmitted Load SMBODAT with Slave Address R W Clear STA 0x10 Repeated START condition transmitted Load SMBODAT with Slave Address R W Clear STA 0x18 Slave Address W transmitted Load SMBODAT with data to be transmit received ted 0x20 Slave Address W transmitted NACK Acknowledge poll to retry Set STO received STA 1 Load SMBODAT with next byte OR 0x28 Data byte transmitted ACK received 2 Set STO OR 3 Clear STO then set STA for repeated START 0x30 Data byte transmitted NACK received 1 Retry transfer OR 2 Set STO 0x38 Arbitration Lost Save current data 0x40 Slave Address R transmitted ACK received If only receiving one byte clear AA send NACK after received byte Wait for received data 0x48 Slave Address R transmitted NACK Acknowledge poll to retry Set STO received STA 0x50 Data byte received ACK transmitted Read SMBODAT Wait for next byte If next byte is last byte clear AA 0x58 Data byte received NACK transmitted Set STO 248 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 20 1 SMBOSTA Status Codes and States 0x60 Own slave address W received ACK trans mitted Wait for data 0x68 Arbitration lost in sending SLA R W as mas ter Own addre
287. ly switch to the SFR Page that contains the SFRs of the corresponding peripheral function that caused the interrupt and return to the previous SFR page upon return from interrupt unless SFR Stack was altered before a returning from the interrupt SFRPAGE is the top byte of the SFR Page Stack and push pop events of this stack are caused by interrupts and not by reading writing to the SFRPAGE register e Rev 1 2 139 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 13 11 SFRNEXT SFR Next Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bit0 SFR Address 0x85 SFR Page All Pages Bits7 0 SFR Page Stack Bits SFR page context is retained upon interrupts return from interrupts a 3 byte SFR Page Stack SFRPAGE is the first entry SFRNEXT is the second and SFR LAST is the third entry The SFR stack bytes may be used to alter the context in the SFR Page Stack and will not cause the stack to push or pop Only interrupts and return from interrupt cause push and pop the SFR Page Stack Write Sets the SFR Page contained in the second byte of the SFR Stack This will cause the SFRPAGE SFR to have this SFR page value upon a return from interrupt Read Returns the value of the SFR page contained in the second byte of the SFR stack This is the value that will go to the SFR Page register upon a return from interrupt Figure 13 12
288. m Rev 1 2 29 SILICON LABS C8051F060 1 2 3 4 5 6 7 1 5 Programmable Counter Array The C8051F06x MCU family includes an on board Programmable Counter Timer Array PCA in addition to the five 16 bit general purpose counter timers The PCA consists of a dedicated 16 bit counter timer time base with 6 programmable capture compare modules The timebase is clocked from one of six sources the system clock divided by 12 the system clock divided by 4 Timer 0 overflow an External Clock Input ECI pin the system clock or the external oscillator source divided by 8 Each capture compare module can be configured to operate in one of six modes Edge Triggered Capture Software Timer High Speed Output Frequency Output 8 Bit Pulse Width Modulator or 16 Bit Pulse Width Modulator The Capture Compare Module I O and External Clock Input are routed to the MCU Port O via the Digital Crossbar SYSCLK 12 SYSCLK 4 Timer 0 Overflow b 16 Bit Counter Timer SYSCLK External Clock 8 Capture Compare Capture Compare Capture Compare Capture Compare Capture Compare Capture Compare Module 0 Module 1 Module 2 Module 3 Module 4 Module 5 m m m m x gt gt Az e ever tope na
289. m clock The Crystal Valid Flag XTLVLD in register OSCXCN is set to 1 by hardware when the external oscillator is settled To avoid reading a false XTLVLD in crystal mode software should delay at least 1 ms between enabling the external oscillator and checking XTLVLD RC and C modes typically require no startup time Figure 15 4 CLKSEL Oscillator Clock Selection Register R W R W R W R W R W R W R W R W Reset Value CLKSL 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO SFR Address 0x97 SFR Page F Bits7 1 Reserved CLKSL System Clock Source Select Bit 0 SYSCLK derived from the Internal Oscillator and scaled as per the IFCN bits in OSCICN 1 SYSCLK derived from the External Oscillator circuit e Rev 1 2 173 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 15 5 OSCXCN External Oscillator Control Register R R W R W R W R R W R W R W Reset Value XTLVLD XOSCMD2 XOSCMD1 XOSCMDO XFCN2 XFCN1 XFCNO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0 8 SFR Page F Bit7 XTLVLD Crystal Oscillator Valid Flag Valid only when XOSCMD 11 0 Crystal Oscillator is unused or not yet stable 1 Crystal Oscillator is running and stable Bits6 4 XOSCMD2 0 External Oscillator Mode Bits 00x External Oscillator circuit off 010 External CMOS Clock Mode External CMOS Clock input on XTAL1 pin 011 Ext
290. mation on formatting the 12 bit DAC data word within the 16 bit SFR space 8 1 2 Update Output Based on Timer Overflow Similar to the ADC operation in which an ADC conversion can be initiated by a timer overflow inde pendently of the processor the DAC outputs can use a Timer overflow to schedule an output update event This feature is useful in systems where the DAC is used to generate a waveform of a defined sampling rate by eliminating the effects of variable interrupt latency and instruction execution on the timing of the DAC output When the DACOMD bits DACOCN 4 3 are set to 01 10 or 11 writes to both DAC data regis ters DACOL and DACOH are held until an associated Timer overflow event Timer 3 Timer 4 or Timer 2 respectively occurs at which time the DACOH DACOL contents are copied to the DAC input latches allow ing the DAC output to change to the new value 8 2 DAC Output Scaling Justification In some instances input data should be shifted prior to a DACO write operation to properly justify data within the DAC input registers This action would typically require one or more load and shift operations adding software overhead and slowing DAC throughput To alleviate this problem the data formatting fea ture provides a means for the user to program the orientation of the DACO data word within data registers DACOH and DACOL The three DACODF bits DACOCN 2 0 allow the user to specify one of five data word
291. may be configured as open drain or push pull and Comparator inputs should be configured as analog inputs see Section 18 1 5 Configuring Port 1 and 2 pins as Analog Inputs on 207 The Comparator may also be used as a reset source see Section 14 5 ComparatorO Reset on page 165 The output of a Comparator can be polled by software used as an interrupt source used as a reset source and or routed to a Port pin Each comparator can be individually enabled and disabled shutdown When disabled the Comparator output if assigned to a Port I O pin via the Crossbar defaults to the logic low state and its supply current falls to less than 1 uA See Section 18 1 1 Crossbar Pin Assignment and Allocation on page 205 for details on configuring the Comparator output via the digital Crossbar The Comparator inputs can be externally driven from 0 25 V to VDD 0 25 V without damage or upset The Figure 12 1 Comparator Functional Block Diagram CPnEN CPnRIF Q cPnFIF Interrupt CPnHYP1 CPnHYN1 CPnHYNO Rising edge Falling edge Comparator Pin Assignments Interrupt Flag Interrupt Flag CP0 P2 6 L pam 2 7 r Tnterr pt CP1 P22 oie CP1 P2 3 CPn 2 2 4 2 2 5 CPn Crossbar SYNCHRONIZER GND Reset Decision Tree ae 2
292. mbination with the EMIOCN register to generate the effective XRAM address Examples of both of these methods are given below 17 1 1 16 Bit MOVX Example The 16 bit form of the MOVX instruction accesses the memory location pointed to by the contents of the DPTR register The following series of instructions reads the value of the byte at address 0x1234 into the accumulator A MOV DPTR 41234h load DPTR with 16 bit address to read 0x1234 MOVX DPTR load contents of 0x1234 into accumulator The above example uses the 16 bit immediate MOV instruction to set the contents of DPTR Alternately the DPTR can be accessed through the SFR registers DPH which contains the upper 8 bits of DPTR and DPL which contains the lower 8 bits of DPTR 17 1 2 8 Bit MOVX Example The 8 bit form of the MOVX instruction uses the contents of the EMIOCN SFR to determine the upper 8 bits of the effective address to be accessed and the contents of RO or R1 to determine the lower 8 bits of the effective address to be accessed The following series of instructions read the contents of the byte at address 0x1234 into the accumulator A MOV EMIOCN 12h load high byte of address into EMIOCN MOV RO 34h load low byte of address into RO or R1 MOVX a RO load contents of 0x1234 into accumulator A Rev 1 2 187 SILICON LABS C8051F060 1 2 3 4 5 6 7 17 2 Configuring the External Memory Interface Configuring the External Memory Int
293. mer 2 interrupt set to high priority level PS0 UARTO Interrupt Priority Control This bit sets the priority of the UARTO interrupt 0 UARTO interrupt set to low priority level 1 UARTO interrupt set to high priority level PT1 Timer 1 Interrupt Priority Control This bit sets the priority of the Timer 1 interrupt 0 Timer 1 interrupt set to low priority level 1 Timer 1 interrupt set to high priority level PX1 External Interrupt 1 Priority Control This bit sets the priority of the External Interrupt 1 interrupt 0 External Interrupt 1 set to low priority level 1 External Interrupt 1 set to high priority level PTO Timer 0 Interrupt Priority Control This bit sets the priority of the Timer 0 interrupt 0 Timer 0 interrupt set to low priority level 1 Timer 0 interrupt set to high priority level PXO External Interrupt 0 Priority Control This bit sets the priority of the External Interrupt 0 interrupt 0 External Interrupt 0 set to low priority level 1 External Interrupt 0 set to high priority level e Rev 1 2 155 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 13 21 EIE1 Extended Interrupt Enable 1 R W R W R W R W R W R W R W R W Reset Value EADCO CP2IE CP1IE CPOIE EPCAO EWADCO ESMBO ESPIO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0xE6 SFR Page All Pages Bit7 EADCO Enable ADCO End of Conversion Interrupt This bit sets the masking of th
294. mmed even in circuit providing non volatile data storage and also allowing field upgrades of the 8051 firmware On board JTAG debug circuitry allows non intrusive uses no on chip resources full speed in circuit debugging using the production MCU installed in the final application This debug system supports inspec tion and modification of memory and registers setting breakpoints watchpoints single stepping Run and Halt commands All analog and digital peripherals are fully functional while debugging using JTAG Each MCU is specified for 2 7 to 3 6 V operation over the industrial temperature range 45 to 85 The C8051F060 2 4 6 are available in a 100 pin TQFP package and the C8051F061 3 5 7 are available in a 64 pin TQFP package see block diagrams in Figure 1 1 Figure 1 2 Figure 1 3 and Figure 1 4 e Rev 1 2 19 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 1 1 Product Selection Guide T m 2 Z A 9 v 2 a o 5 gt els 60 5 8 o S e oe 5 2 15121351 9 gt ol o 5 Oo Ds gt gt o oS S lt S S I 6 5 5 5 lt ic L tc gt 2 lt A C8051F060 25 64k 4352 v v v 2 5 7 59120 75 8 v x 12 2 3 100
295. mperature sensor may be selected as a single ended input The ADC2 input channels are configured and selected in the AMX 2CF and AMX2SL registers as described in Figure 7 5 and Figure 7 6 respectively In Single ended Mode the selected pin is measured with respect to AGND In Differential Mode the selected differential pair is measured with respect to one another The polarity of the differential measurement depends on the setting of the AMX2AD3 0 bits in the AMX2SL register For example if pins AIN2 0 and AIN2 1 are configured for differential measurement AINO1IC 1 and AMX2AD3 0 0000b the ADC will measure the voltage AIN2 0 AIN2 1 If AMX2AD3 0 is changed to 0001b the ADC will measure the same voltage with oppo site polarity AIN2 1 AIN2 0 The conversion code format differs between Single ended and Differential modes The registers ADC2H and ADC2L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion Data can be right justified or left justified depending on the setting of the AD2LJST bit ADC2CN 0 When in Single ended Mode conversion codes are represented as 10 bit unsigned integers Inputs are measured from 0 to VREF 1023 1024 Example codes are shown below for both right justified and left justified data Unused bits in the ADC2H and ADC2L registers are set to 0 Input Voltage Right Justified ADC2H ADC2L Left Justified ADC2H ADC2L AD2LJST
296. mrs ace bx Pas cien chiama cs tenues 78 Figure 6 4 DMAOCN DMAO Control Register 80 Figure 6 5 DMAOCF DMAO Configuration Register 81 Figure 6 6 DMAOIPT DMAO Instruction Write Address Register 82 Figure 6 7 DMAOIDT DMAO Instruction Write Data Register 82 Figure 6 8 DMAOBND DMAO Instruction Boundary Register 83 Figure 6 9 DMAOISW DMAO Instruction Status Register 83 Figure 6 10 DMAODAH DMAO Data Address Beginning MSB Register 84 Figure 6 11 DMAODAL DMAO Data Address Beginning LSB Register 84 Figure 6 12 DMAODSH DMAO Data Address Pointer MSB Register 84 Figure 6 13 DMAODSL DMAO Data Address Pointer LSB Register 84 Figure 6 14 DMAOCTH DMAO Repeat Counter Limit MSB Register 85 Figure 6 15 DMAOCTL DMAO Repeat Counter Limit LSB Register 85 Figure 6 16 DMAOCSH DMAO Repeat Counter MSB Register 85 Figure 6 17 DMAOCSL DMAO Repeat Counter LSB Register 85 7 10 Bit ADC ADC2 C8051F060 1 2 9 J 87 Figure 7 1 ADC2 Functional Block
297. n Timer 2 3 and 4 External Flag Set by hardware when either a capture or reload is caused by a high to low transition on the TnEX input pin and EXENn is logic 1 When the Timer interrupt is enabled setting this bit causes the CPU to vector to the Timer Interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software Reserved EXENn Timer 2 3 and 4 External Enable Enables high to low transitions on TnEX to trigger captures reloads and control the direc tion of the timer counter up or down count If DCENn 1 TnEX will determine if the timer counts up or down when in Auto reload Mode If EXENn 1 should be configured as a digital input 0 Transitions on the TnEX pin are ignored 1 Transitions on the pin cause capture reload or control the direction of timer count up or down as follows Capture Mode 1 to 0 Transition on pin causes RCAPnH RCAPnL to capture timer value Auto Reload Mode DCENn 0 1 to 0 transition causes reload of timer and sets the EXFn Flag DCENn 1 TnEX logic level controls direction of timer up or down TRn Timer 2 3 and 4 Run Control This bit enables disables the respective Timer 0 Timer disabled 1 Timer enabled and running counting C Tn Counter Timer Select 0 Timer Function Timer incremented by clock defined by TnM1 TnMO TMRnCF 4 TMRnCF 3 1 Counter Function Timer incremented by high to low
298. n Data Word e Rev 1 2 69 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 5 26 ADCOLTH ADCO Less Than Data High Byte Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xC7 SFR Page 0 Bits 7 0 High byte of ADCO Less Than Data Word Figure 5 27 ADCOLTL ADCO Less Than Data Low Byte Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xC6 SFR Page 0 Bits 7 0 Low byte of ADCO Less Than Data Word 70 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 5 28 16 Bit ADCO Window Interrupt Example Single Ended Data Input Voltage ADCO Data AINO AINOG Word REF x 65535 65536 OxFFFF ADOWINT not affected 0x2001 0x2000 ADCOLTH ADCOLTL ADOWINT 1 REF 4096 65536 0x1000 ADCOGTH ADCOGTL OxOFFF ADOWINT not affected 0x0000 Given AMXOSL 0x00 ADCOLTH ADCOLTL 0x2000 ADCOGTH ADCOGTL 0x1000 An ADCO End of Conversion will cause an ADCO Window Compare Interrupt ADOWINT 1 if the resulting ADCO Data Word is lt 0x2000 and gt 0x1000 Input Voltage ADCO Data AINO AINOG REF x 65535 65536 ADOWINT 1 REF x 8192 65536 0x2000 ADCOGTH ADCOGTL OLERE ADOWINT not affected POO AE E ERETI 0x1001
299. n Execution in Mode T i nennt ett end rne ero 78 6 6 elio NN m 79 6 7 Data Buffer Overflow Warnings and 79 7 10 Bit ADC ADC2 C8051F060 1 2 3 J 87 7 1 Analog Multiplexer enn 88 7 2 Modes of Operation 89 7 2 1 Starting a 89 oS MEI CO qe 90 7 2 3 Settling Time Requirements 91 Rev 1 2 3 SILICON LABS C8051F060 1 2 3 4 5 6 7 7 3 Programmable Window Detector sse 97 7 3 1 Window Detector In Single Ended Mode 99 7 3 2 Window Detector In Differential Mode 100 8 DACs 12 Bit Voltage Mode DACO and DAC1 C8051F060 1 2 3 103 DAC Output SOMe QUIN 104 8 1 1 Update Output 104 8 1 2 Update Output Based on Timer Overflow 104 8 2 DAC Output 104 9 Voltage Reference 2 8051 060 2 4 111 10 Voltage Reference 2 8051 061 3 2 2 2 2
300. n is transmitted if the bus is free If the bus is not free the START is transmitted after a STOP is received If STA is set after one or more bytes have been transmitted or received and before a STOP is received a repeated START condition is transmitted Bit4 STO SMBus Stop Flag 0 No STOP condition is transmitted 1 Setting STO to logic 1 causes a STOP condition to be transmitted When a STOP condi tion is received hardware clears STO to logic 0 If both STA and STO are set a STOP con dition is transmitted followed by a START condition In slave mode setting the STO flag causes SMBus to behave as if a STOP condition was received Sl SMBus Serial Interrupt Flag This bit is set by hardware when one of 27 possible 0 states is entered Status code OxF8 does not cause SI to be set When the SI interrupt is enabled setting this bit causes the CPU to vector to the SMBus interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software Bit2 AA SMBus Assert Acknowledge Flag This bit defines the type of acknowledge returned during the acknowledge cycle on the SCL line 0 A not acknowledge high level on SDA is returned during the acknowledge cycle 1 An acknowledge low level on SDA is returned during the acknowledge cycle Bit1 FTE SMBus Free Timer Enable Bit 0 No timeout when SCL is high 1 Timeout when SCL high time exceeds limit specified by the SMBOCR value
301. nd 4 295 24 2 1 Configuring Timer 2 and 4 to Count 295 24 22 Capt re Mode Nm 296 24 2 3 Auto Reload a 297 24 2 4 Toggle Output Mode rin REL tse o ee D pc Ee DR Reo UE 298 25 Programmable Counter Array eene nanus xata ann ta nuu ran an ERE u u 303 25 1 Counter Timer 304 25 2 Capture Compare 305 25 2 1 Edge triggered Capture Mode 306 25 2 2 Software Timer Compare 307 25 2 3 High Speed Output 308 25 2 4 Frequency Output 309 25 2 5 8 Bit Pulse Width Modulator 310 25 2 6 16 Bit Pulse Width Modulator Mode 311 25 3 Register Descriptions Tor PCA0 312 26 JTAG IEEE 11491 RIZR MEE E 317 26 1 Bo ndary tm m 318 Zi EP TEST p ele PRETI UU C TS 321 26 1 2 SAMPLE Instruction aub de plua e deus 321 26 1 3 BYPASS Instruction
302. nd DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12 to 24 MHz By contrast the CIP 51 core exe cutes 70 of its instructions in one or two system clock cycles with only four instructions taking more than four system clock cycles The CIP 51 has a total of 109 instructions The table below shows the total number of instructions that require each execution time Clocks to Execute 1 2 2 3 3 3 4 4 4 5 5 8 Number of Instructions 26 50 5 14 7 3 1 2 1 With the CIP 51 s maximum system clock at 25 MHz it has a peak throughput of 25 MIPS Figure 1 5 shows a comparison of peak throughputs of various 8 bit microcontroller cores with their maximum system clocks 25 20 Silicon Labs Microchip Philips ADuC812 CIP 51 PIC17C75x 80C51 8051 25 MHz clk 33 MHz 33 MHz clk 16 MHz clk Figure 1 5 Comparison of Peak MCU Execution Speeds e Rev 1 2 25 SILICON LABS C8051F060 1 2 3 4 5 6 7 1 1 3 Additional Features The C8051F06x MCU family includes several key enhancements to the CIP 51 core and peripherals to improve overall performance and ease of use in end applications The extended interrupt handler provides 22 interrupt sources into the CIP 51 allowing the numerous ana log and digital peripherals to interrupt the controller An interrupt driven system requires less intervention by the MCU giving it more effective throughput The extra in
303. nding P7MDOUT bit 0 See Figure 18 26 Read Returns states of I O pins 0 P7 n pin is logic low 1 P7 n pin is logic high Note P7 7 0 can be driven by the External Data Memory Interface as AD 7 0 in Multiplexed mode or as D 7 0 in Non multiplexed mode See Section 17 External Data Memory Inter face and On Chip XRAM on page 187 for more information about the External Memory Interface Figure 18 26 P7MDOUT Port7 Output Mode Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0x9F SFR Page F Bits7 0 P7MDOUT 7 0 Port7 Output Mode Bits 0 Port Pin output mode is configured as Open Drain 1 Port Pin output mode is configured as Push Pull 224 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 19 Controller Area Network CANO C8051F060 1 2 3 IMPORTANT DOCUMENTATION NOTE The Bosch CAN Controller is integrated in the C8051F060 1 2 3 devices This section of the data sheet gives a description of the CAN controller as an overview and offers a description of how the Silicon Labs CIP 51 MCU interfaces with the on chip Bosch CAN controller In order to use the CAN controller please refer to Bosch s C CAN User s Manual revision 1 2 as an accom panying manual to Silicon Labs C8051F060 1 2 3 4 5 6 7 Data sheet The C8051F060 1 2 3 family of devices feature a Control Area Network CAN controller that enabl
304. ng Interrupt Enable 0 Disable Data Overflow Warning interrupts 1 Enable Data Overflow Warning interrups Bit 1 DMAODO1 ADC1 Data Overflow Warning Flag 0 No ADC1 Data Buffer Warnings have been issued 1 ADC1 Data Buffer is and the DMA has not written previous data to XRAM This bit must be cleared by software Bit 0 DMAODOO ADCO Data Overflow Warning Flag 0 No ADCO Data Buffer Warnings have been issued 1 ADCO Data Buffer is full and the DMA has not written previous data to XRAM This bit must be cleared by software 80 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 6 5 DMAOCF DMAO Configuration Register SFR Page 3 SFR Address OxF8 bit addressable R W R R W R W R W R W R W R W Reset Value DMAOHLT DMAOXBY DMAOCIE DMAOCI DMAOEOE DMAOEO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Bit 7 DMAOHLT Halt DMAO Off Chip XRAM Access C8051F060 2 4 6 Only 0 has complete access to off chip XRAM 1 Processor core has complete access to off chip XRAM DMAO will wait until this bit is 0 before writing to off chip XRAM locations Bit 6 DMAOXBY Off chip XRAM Busy Flag C8051F060 2 4 6 Only 0 is not accessing off chip XRAM 1 DMAO is accessing off chip XRAM Bits 5 4 RESERVED Write to 00b Bit 3 DMAOCIE Repeat Counter Overflow Interrupt Enable 0 Disable Repeat Counter Overflow Interrupt 1 Enable Repeat Counter Overfl
305. ng to the following table IndOpCode Operation Ox Poll 10 Read 11 Write The Poll operation is used to check the Busy bit as described below Although a Capture DR is performed no Update DR is allowed for the Poll operation Since updates are disabled polling can be accomplished by shifting in out a single bit The Read operation initiates a read from the register addressed by the DRAddress Reads can be initiated by shifting only 2 bits into the indirect register After the read operation is initiated polling of the Busy bit must be performed to determine when the operation is complete The write operation initiates a write of WriteData to the register addressed by DRAddress Registers of any width up to 18 bits can be written If the register to be written contains fewer than 18 bits the data in Write Data should be left justified i e its MSB should occupy bit 17 above This allows shorter registers to be written in fewer JTAG clock cycles For example an 8 bit register could be written by shifting only 10 bits After a Write is initiated the Busy bit should be polled to determine when the next operation can be initi ated The contents of the Instruction Register should not be altered while either a read or write operation is busy Outgoing data from the indirect Data Register has the following format 19 18 1 0 0 ReadData Busy The Busy bit indicates that the current operation is not compl
306. nge will yield undefined results 0 Flash access from JTAG directed to the Program Data Flash sector 1 Flash access from JTAG directed to the Scratchpad sector Bits6 4 WRMD2 0 Write Mode Select Bits The Write Mode Select Bits control how the interface logic responds to writes to the FLASH DAT Register per the following values 000 AFLASHDAT write replaces the data in the FLASHDAT register but is otherwise ignored 001 FLASHDAT write initiates a write of FLASHDAT into the memory address by the FLASHADR register FLASHADR is incremented by one when complete 010 FLASHDAT write initiates an erasure sets all bytes to OxFF of the Flash page containing the address FLASHADR The data written must be 0xA5 for the erase to occur FLASHADR is not affected If FLASHADR 0x7BFE 0x7BFF the entire user space will be erased i e entire Flash memory except for Reserved area 0 7 00 Ox7FFF All other values for WRMD2 0 are reserved Bits3 0 RDMD3 0 Read Mode Select Bits The Read Mode Select Bits control how the interface logic responds to reads to the FLASH DAT Register per the following values 0000 AFLASHDAT read provides the data in the FLASHDAT register but is otherwise ignored 0001 AFLASHDAT read initiates a read of the byte addressed by the FLASHADR register if no operation is currently active This mode is used for block reads 0010 FLASHDAT read initiates a read of the byte addressed by FLASHADR only if ope
307. nificant personal injury or death Silicon Laboratories products are generally not intended for military applications Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including but not limited to nuclear biological or chemical weapons or missiles capable of delivering such weapons Trademark Information Silicon Laboratories Inc Silicon Laboratories Silicon Labs SiLabs and the Silicon Labs logo CMEMS EFM EFM32 EFR Energy Micro Energy Micro logo and combinations thereof the world s most energy friendly microcontrollers Ember EZLink amp EZMac EZRadio amp EZRadioPRO DSPLL ISOmodem 6 Precision328 ProSLIC SIPHY USBXpress and others are trademarks or registered trademarks of Silicon Laboratories Inc ARM CORTEX Cortex M3 and THUMB are trademarks or registered trademarks of ARM Holdings Keil is a registered trademark of ARM Limited All other products or brand names mentioned herein are trademarks of their respective holders Silicon Laboratories Inc 400 West Cesar Chavez Austin TX 78701 USA SILICON LABS
308. nly e Rev 1 2 147 SILICON LABS C8051F060 1 2 3 4 5 6 7 13 2 7 Register Descriptions Following are descriptions of SFRs related to the operation of the CIP 51 System Controller Reserved bits should not be set to logic Future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0 selecting the feature s default state Detailed descriptions of the remaining SFRs are included in the sections of the datasheet associated with their corresponding sys tem function Figure 13 13 SP Stack Pointer R W R W R W R W R W R W R W R W Reset Value 00000111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0x81 SFR Page All Pages Bits7 0 SP Stack Pointer The Stack Pointer holds the location of the top of the stack The stack pointer is incremented before every PUSH operation The SP register defaults to 0x07 after reset Figure 13 14 DPL Data Pointer Low Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0x82 SFR Page All Pages Bits7 0 DPL Data Pointer Low The DPL register is the low byte of the 16 bit DPTR DPTR is used to access indirectly addressed XRAM and Flash memory Figure 13 15 DPH Data Pointer High Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5
309. nterrupt is generated by these conditions e Rev 1 2 275 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 22 10 SBUFO UARTO Data Buffer Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bite Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0x99 SFR Page 0 Bits7 0 SBUFO 7 0 UARTO Buffer Bits 7 0 MSB LSB This is actually two registers a transmit and a receive buffer register When data is moved to SBUFO it goes to the transmit buffer and is held for serial transmission Moving a byte to SBUFO is what initiates the transmission When data is moved from SBUFO it comes from the receive buffer Figure 22 11 SADDRO UARTO Slave Address Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xA9 SFR Page 0 Bits7 0 SADDRO 7 0 UARTO Slave Address The contents of this register are used to define the UARTO slave address Register SADENO is a bit mask to determine which bits of SADDRO are checked against a received address corresponding bits set to logic 1 in SADENO are checked corresponding bits set to logic 0 are don t cares Figure 22 12 SADENO UARTO Slave Address Enable Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0xB9 SFR Page 0 Bits7 0 SADENO 7 0 UARTO Slave
310. nterrupt sources with two prior ity levels The allocation of interrupt sources between on chip peripherals and external inputs pins varies according to the specific version of the device Each interrupt source has one or more associated interrupt pending flag s located in an SFR When a peripheral or external source meets a valid interrupt condition the associated interrupt pending flag is set to logic 1 If interrupts are enabled for the source an interrupt request is generated when the interrupt pending flag is set As soon as execution of the current instruction is complete the CPU generates an LCALL to a prede termined address to begin execution of an interrupt service routine ISR Each ISR must end with an instruction which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred If interrupts are not enabled the interrupt pending flag is ignored by the hardware and program execution continues as normal The interrupt pending flag is set to logic 1 regard less of the interrupt s enable disable state Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an SFR IE EIE2 However interrupts must first be globally enabled by setting the EA bit IE 7 to logic 1 before the individual interrupt enables are recognized Setting the EA bit to logic 0 disables all interrupt sources regardless of the individu
311. o the transmit buffer and initiates a transfer when in Master Mode A read of SPIODAT returns the contents of the receive buffer Rev 1 2 261 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 21 12 SPI Master Timing 0 EE SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 MISO Figure 21 13 SPI Master Timing 1 N TuckH x MIS MIH is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 262 Rev 1 2 g SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 21 14 SPI Slave Timing CKPHA 0 lt SE 7 T MOSI M SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 Figure 21 15 SPI Slave Timing CKPHA 1 MOSI SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 Rev 1 2 263 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 21 1 SPI Slave Timing Parameters Parameter Description Min Max Units Master Mode Timing See Figure 21 12 and Figure 21 13 SCK High Time 1 5 SCK Low Time 1 5 Tus MISO Valid to SCK Shift Edge k ns SCK Shift Edge to MISO Change 0 n
312. ock cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR If the CPU is executing an ISR for an interrupt with equal or higher priority the new interrupt will not be serviced until the current ISR completes including the RETI and following instruction e Rev 1 2 153 SILICON LABS C8051F060 1 2 3 4 5 6 7 13 3 5 Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below Refer to the datasheet section associated with a particular on chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt pending flag s Figure 13 19 IE Interrupt Enable R W R W R W R W R W R W R W R W Reset Value EA IEGFO ET2 ESO ET1 EX1 ETO EXO 00000000 Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Addressable SFR Address 0xA8 SFR Page All Pages Bit7 EA Enable All Interrupts This bit globally enables disables all interrupts It overrides the individual interrupt mask set tings 0 Disable all interrupt sources 1 Enable each interrupt according to its individual mask setting Bit6 IEGFO General Purpose Flag 0 This is a general purpose flag for use under software control Bit5 ET2 Enabler Timer 2 Interrupt This bit sets the masking of the Timer 2 interrupt 0 Disable Timer 2 interrupt 1 Enable interrupt requests generated b
313. ogic 0 Note that the BIASE bit must be set to logic 1 if ADC2 or either DAC is used regardless of the voltage reference used If neither ADC2 nor the DACs are being used both of these bits can be set to logic 0 to conserve power Bit AD2VRS selects between VREF2 and AV 4 for the ADC2 voltage reference source The electrical specifications for the Voltage Reference are given in Table 10 1 Figure 10 1 Voltage Reference Functional Block Diagram m gt VREF2 XI A vob External Voltage Reference E Circuit EN 10 EN ADC2 VREF DACs i X 1 2V REFBE 57 Recommended Bypass Capacitors Rev 1 2 113 SILICON LABS C8051F060 1 2 3 4 5 6 7 The temperature sensor connects to the highest order input of the ADC2 input multiplexer see Section 7 10 Bit ADC ADC2 8051 060 1 2 3 on page 87 The TEMPE bit within REF2CN enables and dis ables the temperature sensor While disabled the temperature sensor defaults to a high impedance state and any A D measurements performed on the sensor while disabled result in meaningless data Figure 10 2 REF2CN Reference Control Register 2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Page 2 Bits7 4 UNUSED Read 00006 Write don t care Bit3 AD2VRS ADC2 Voltage Reference Select 0 ADC2 v
314. oltage reference from VREF2 pin 1 ADC2 voltage reference from AV Bit2 TEMPE Temperature Sensor Enable Bit 0 Internal Temperature Sensor Off 1 Internal Temperature Sensor On Bit1 BIASE ADC DAC Bias Generator Enable Bit Must be 1 if using ADC2 or DACs 0 Internal Bias Generator Off 1 Internal Bias Generator On REFBE Internal Reference Buffer Enable Bit 0 Internal Reference Buffer Off Table 10 1 Voltage Reference Electrical Characteristics VDD 3 0 V AV 3 0 V 40 to 85 C unless otherwise specified R W R W R W R W R W R W R W R W Reset Value AD2VRS TEMPE BIASE REFBE 00000000 SFR Address 0xD1 1 Internal Reference Buffer On Internal voltage reference is driven on the VREF pin Parameter Conditions Min Typ Max Units Internal Reference REFBE 1 Output Voltage 25 ambient 2 36 2 43 2 48 V VREF Power Supply Current 50 VREF Short Circuit Current 30 mA VREF Temperature Coefficient 15 Load Regulation Load 0 to 200 HA to AGND 0 5 VREF Turn on Time 1 4 7 uF tantalum 0 1 uF ceramic 2 ms bypass VREF Turn on Time 2 0 1 HF ceramic bypass 20 us VREF Turn on Time 3 no bypass cap 10 us External Reference REFBE 0 Input Voltage Range 1 00 V 0 3 Input Current 0 1 114 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 11 Voltage Reference 2 C8051F064 5 6
315. on Figure 17 3 Multiplexed Configuration Example A 15 8 P6 ALE P4 5 AD 7 0 P7 190 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 17 4 2 Non multiplexed Configuration In Non multiplexed mode the Data Bus and the Address Bus pins are not shared An example of a Non multiplexed Configuration is shown in Figure 17 4 See Section 17 6 1 Non multiplexed Mode on page 196 for more information about Non multiplexed operation Figure 17 4 Non multiplexed Configuration Example A 15 0 P5 and P6 D 7 0 RD P4 6 MR P4 7 Rev 1 2 191 SILICON LABS C8051F060 1 2 3 4 5 6 7 17 5 Memory Mode Selection The external data memory space can be configured in one of four modes shown in Figure 17 5 based on the EMIF Mode bits in the EMIOCF register Figure 17 2 These modes are summarized below More infor mation about the different modes can be found in Section 17 6 Timing on page 194 17 5 1 Internal XRAM Only When 2 are set to 00 all MOVX instructions will target the internal XRAM space on the device Memory accesses to addresses beyond the populated space will wrap on 4 k byte boundaries As an example the addresses 0x1000 and 0x2000 both evaluate to address 0x0000 in on chip XRAM space 8 bit MOVX operations use the contents of EMIOCN to determine the high byte of the effective address and RO or R1 to determine the low byte of the eff
316. on gt 0 d gt 1 Programmable g NUN 22762 Internal Clock Generator SYSCLK Option 2 oes Option 1 k VDD M XTAL1 7 XI t kl 1 _ d Circuit 989 TALI L7 L m 1 IN allalla OSCXCN 15 1 Programmable Internal Oscillator All C8051 F060 1 2 3 4 5 6 7 devices include a programmable internal oscillator that defaults as the system clock after a system reset The internal oscillator period can be adjusted via the OSCICL register as defined by Figure 15 2 OSCICL is factory calibrated to obtain 24 5 MHz base frequency fpAsp Electrical specifications for the precision internal oscillator are given in Table 15 1 The programmed inter nal oscillator frequency must not exceed 25 MHz Note that the system clock may be derived from the pro grammed internal oscillator divided by 1 2 4 or 8 as defined by the IFCN bits in register OSCICN Rev 1 2 171 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 15 2 OSCICL Internal Oscillator Calibration Register R W R W R W R W R W R W R W R W Reset Value Variable Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0x8B SFR Page F Bits 7 0 OSCICL Internal Oscillator Calibration Regi
317. on Bytes Cycles Arithmetic Operations ADD A Rn Add register to A 1 1 ADD direct Add direct byte to 2 2 ADD A Ri Add indirect RAM to A 1 2 ADD A data Add immediate to A 2 2 ADDC A Rn Add register to A with carry 1 1 ADDC A direct Add direct byte to A with carry 2 2 ADDC A Ri Add indirect RAM to A with carry 1 2 ADDC A data Add immediate to A with carry 2 2 SUBB A Rn Subtract register from A with borrow 1 1 SUBB A direct Subtract direct byte from A with borrow 2 2 SUBB A Ri Subtract indirect RAM from A with borrow 1 2 SUBB A data Subtract immediate from A with borrow 2 2 INCA Increment A 1 1 INC Rn Increment register 1 1 INC direct Increment direct byte 2 2 INC Ri Increment indirect RAM 1 2 DECA Decrement A 1 1 DEC Rn Decrement register 1 1 DEC direct Decrement direct byte 2 2 DEC Decrement indirect RAM 1 2 INC DPTR Increment Data Pointer 1 1 MUL AB Multiply A and B 1 4 DIV AB Divide A by B 1 8 DAA Decimal adjust A 1 1 Logical Operations ANL A Rn AND Register to A 1 1 ANL A direct AND direct byte to A 2 2 ANL A Ri AND indirect RAM to A 1 2 ANL A data AND immediate to A 2 2 ANL direct A AND A to direct byte 2 2 ANL direct data AND immediate to direct byte 3 3 ORL A Rn OR Register to A 1 1 ORL A direct OR direct byte to A 2 2 ORL A Ri OR indirect RAM to A 1 2 ORL A data OR immediate to A 2 2 ORL direct A OR A to direct byte 2 2 ORL direct data OR immediate to direct byte 3 3 XRL A Rn Exclu
318. on instructions Table 6 1 details all of the valid DMA instructions Instructions not listed in the table are not valid DMA instructions and should not be used Note that the ADCs can be independently controlled by the microcontroller when their outputs are not requested by the DMA Table 6 1 DMAO Instruction Set Second Data Instruction sss First Data Written f Word Description to XRAM 2 bytes Written to XRAM 2 bytes 00000000b End Of Operation none none 10000000b End Of Operation with Continuous Conversion none none x0010000b Retrieve ADCO Data ADCOH ADCOL none x0100000b Retrieve ADC1 Data ADC1H ADC1L none x0110000b Retrieve ADCO and ADC1 Data ADCOH ADCOL ADC1H ADC1L ADCOH ADCOL x10x0000b Retrieve Differential Data differential result none from both ADCs ADCOH ADCOL x11x0000b Retrieve Differential and ADC1 Data differential result ADC1H ADC1L from both ADCs 6 3 Addressing and Setup The DMA Interface can be configured to access either on chip or off chip XRAM Any writes to on chip XRAM by the DMA Control Logic occur when the processor core is not accessing the on chip XRAM This ensures that the DMA will not interfere with processor instruction timing Off chip XRAM access only available on the C8051F060 2 4 6 is controlled by the DMAOHLT bit in DMAOCF DMA Configuration Register Figure 6 5 The DMA will have full access to off chip XRAM when this bit
319. onnection diagram between two master devices in multiple master mode 3 wire single master mode is active when NSSMD1 SPIOCN 3 0 and NSSMDO SPIOCN 2 0 In this mode NSS is not used and is not mapped to an external port pin through the crossbar Any slave devices that must be addressed in this mode should be selected using general purpose I O pins Figure 21 3 shows a connection diagram between a master device in 3 wire master mode and a slave device 4 wire single master mode is active when NSSMD1 SPIOCN 3 1 In this mode NSS is configured as an output pin and can be used as a slave select signal for a single SPI device In this mode the output value of NSS is controlled in software with the bit NSSMDO SPIOCN 2 Additional slave devices can be addressed using general purpose pins Figure 21 4 shows a connection diagram for a master device in 4 wire master mode and two slave devices e Rev 1 2 253 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 21 2 Multiple Master Mode Connection Diagram Figure 21 3 3 Wire Single Master and 3 Wire Single Slave Mode Connection Diagram Figure 21 4 4 Wire Single Master Mode and 4 Wire Slave Mode Connection Diagram 254 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 21 3 SPIO Slave Mode Operation When SPIO is enabled and not configured as a master it will operate as a SPI slave As a slave bytes are shifted in through the MOSI pin and
320. oococcooooco i SILICON LABS Rev 1 2 285 C8051F060 1 2 3 4 5 6 7 230400 SYSCLK 115200 SYSCLK 57600 SYSCLK 28800 SYSCLK 14400 SYSCLK 12 9600 SYSCLK 12 2400 SYSCLK 12 SYSCLK 48 115200 EXTCLK 8 57600 EXTCLK 8 28800 EXTCLK 8 14400 EXTCLK 8 9600 230400 Don t 8 TSCA1 SCAO and T1M bit definitions can be found in Section 24 1 Table 23 6 Timer Settings for Standard Baud Rates Using an External Oscillator 115200 SYSCLK 57600 SYSCLK 28800 SYSCLK 14400 SYSCLK 9600 SYSCLK 2400 SYSCLK 12 1200 230400 SYSCLK 12 115200 EXTCLK 8 57600 EXTCLK 8 28800 EXTCLK 8 14400 EXTCLK 8 9600 Dont 8 TSCA1 SCAO bit definitions can be found in Section 24 1 286 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 24 Timers Each MCU includes 5 counter timers Timer 0 and Timer 1 are 16 bit counter timers compatible with those found in the standard 8051 Timer 2 Timer 3 and Timer 4 are 16 bit auto reload and capture counter tim ers for use with the ADC s DAC s square wave generation or for general purpose use These timers can be used to measure time intervals count external events and generate p
321. or at least two full system clock cycles to ensure the level is properly sampled 24 1 Timer 0 and Timer 1 Each timer is implemented as a 16 bit register accessed as two separate 8 bit SFRs a low byte TLO or TL1 and a high byte THO or TH1 The Counter Timer Control register TCON is used to enable Timer 0 and Timer 1 as well as indicate their status Timer 0 interrupts can be enabled by setting the bit in the IE register Section 13 3 5 Interrupt Register Descriptions on page 154 Timer 1 interrupts can be enabled by setting the ET1 bit in the IE register Section 13 3 5 Both counter timers operate in one of four primary modes selected by setting the Mode Select bits T1M1 TOMO in the Counter Timer Mode register TMOD Both timers can be configured independently 24 1 1 Mode O0 13 bit Counter Timer Timer 0 and Timer 1 operate as 13 bit counter timers in Mode 0 The following describes the configuration and operation of Timer 0 However both timers operate identically and Timer 1 is configured in the same manner as described for Timer 0 The THO register holds the eight MSBs of the 13 bit counter timer TLO holds the five LSBs in bit positions TLO 4 TLO 0 The three upper bits of TLO TLO 7 TLO 5 are indeterminate and should be masked out or ignored when reading the TLO register As the 13 bit timer register increments and overflows from 0x1FFF all ones to 0x0000 the timer overflow TCON 5 is set and an inte
322. ority level 1 CP1 interrupt set to high priority level Bit4 Interrupt Priority Control This bit sets the priority of the CPO interrupt 0 CPO interrupt set to low priority level 1 CPO interrupt set to high priority level Bit3 PPCAO Programmable Counter Array PCAO Interrupt Priority Control This bit sets the priority of the PCAO interrupt 0 PCAO interrupt set to low priority level 1 PCAO interrupt set to high priority level Bit2 PWADCO ADCO Window Comparator Interrupt Priority Control This bit sets the priority of the ADCO Window interrupt 0 ADCO Window interrupt set to low priority level 1 ADCO Window interrupt set to high priority level Bit1 PSMBO System Management Bus SMBusO Interrupt Priority Control This bit sets the priority of the SMBusO interrupt 0 SMBus interrupt set to low priority level 1 SMBus interrupt set to high priority level Bito PSPIO Serial Peripheral Interface SPIO Interrupt Priority Control This bit sets the priority of the SPIO interrupt 0 SPIO interrupt set to low priority level 1 SPIO interrupt set to high priority level 158 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 R W Figure 13 24 EIP2 Extended Interrupt Priority 2 R W R W R W R W R W R W R W Reset Value PDMAO PS1 PCANO PADC2 PWADC2 4 PADC1 PT3 00000000 Bit7 Bit7 Bit6 Bit5 Bit4 Bit3 Bi
323. ost significant 8 bits of the DAC1 Data Word is in DAC1H 7 0 while the least significant 4 bits are DAC1L 7 4 DACIL MSB LSB 108 Rev 1 2 5 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 8 1 DAC Electrical Characteristics VDD 3 0 V AV 3 0 V VREF 2 40 V REFBE 0 No Output Load unless otherwise specified Parameter Conditions Min Typ Max Units Static Performance Resolution 12 bits Integral Nonlinearity 1 5 LSB Differential Nonlinearity 1 LSB Output Noise No Output Filter 250 pu Vrms 100 kHz Output Filter 128 10 kHz Output Filter 41 Offset Error Data Word 0x014 3 30 Offset Tempco 6 ppm C Full Scale Error 20 60 Full Scale Error Tempco 10 ppm C VDD Power Supply Rejection 60 dB Ratio Output Impedance in Shutdown DACnEN 0 100 Output Sink Current 300 Output Short Circuit Current Data Word OxFFF 15 mA Dynamic Performance Voltage Output Slew Rate Load 40pF 0 44 V us Output Settling Time to 1 2 LSB Load 40pF Output swing from 10 us code 0xFFF to 0x014 Output Voltage Swing 0 VREF V 115 Startup Time 10 us Analog Outputs Load Regulation 0 01mA to 0 3mA at code 60 ppm OxFFF Power Consumption each DAC Power Supply Current AV Data Word Ox7FF 300 500 supplied to DAC Rev 1 2 109 SILICON LABS C8051F060 1 2 3 4 5 6 7
324. overflow of Timer 3 10 ADCO conversion initiated on rising edge of external CNVSTRO 11 ADCO conversion initiated on overflow of Timer 2 If ADOTM 1 00 Tracking starts with the write of 1 to ADOBUSY and is followed by the conversion 01 Tracking started by the overflow of Timer 3 and is followed by the conversion 10 ADCO conversion starts on rising CNVSTRO edge 11 Tracking started by the overflow of Timer 2 and is followed by the conversion See Figure 5 4 and Table 5 1 for conversion timing parameters Bit 1 ADOWINT ADCO Window Compare Interrupt Flag This bit must be cleared by software 0 ADCO Window Comparison Data match has not occurred since this flag was last cleared 1 ADCO Window Comparison Data match has occurred Bit 0 RESERVED Write to Ob 60 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 5 10 ADC1CN ADC1 Control Register R W R W R W R W R W R W R W R W Reset Value AD1EN AD1TM AD1INT AD1BUSY AD1CM2 AD1CM1 AD1CMO E 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Bit Addressable SFR Address OxE8 SFR Page 1 Bit 7 AD1EN ADC1 Enable Bit 0 ADC1 Disabled ADC1 is in low power shutdown 1 ADC1 Enabled ADC1 is active and ready for data conversions or calibrations Bit 6 AD1TM ADC Track Mode Bit 0 When the ADC is enabled tracking is continuous unless a conversion is in process 1 Tracking Defined by AD1CM2 0 bits Bit 5 AD1INT A
325. ow SYSCLK 100 CNVSTR1 110 Timer 2 Overflow xx1 ADOBUSY W 1 1 gt lt lt lt lt E 29099028965 286665 5555565656 65556566 lt lt lt lt lt lt lt lt lt lt lt lt lt lt ADC1CF ADC1CN Figure 5 1 16 Bit ADCO and ADC1 Control Path Diagram Rev 1 2 51 SILICON LABS C8051F060 1 2 3 4 5 6 7 AMXOSL AINO AINOG Single Ended AINT Differential AIN1G ADC1L ADCOH ADCOL 16 16 l gt ADOWINT 32 ADCOGTH ADCOGTL ADCOLTH ADCOLTL Figure 5 2 16 bit ADCO and ADC1 Data Path Diagram 5 1 Single Ended or Differential Operation ADCO and ADC1 can be programmed to operate independently as single ended ADCs or together to accept a differential input In single ended mode the ADCs can be configured to sample simultaneously or to use different conversion speeds In differential mode ADC1 is a slave to ADCO and its configuration is based on ADCO settings except during offset or gain calibrations The DIFFSEL bit in the Channel Select Register AMXOSL Figure 5 6 selects between single ended and differential mode 5 1 1 Pseudo Differential Inputs The inputs to the ADCs are pseudo differential The actual voltage measured by each ADC is equal to the voltage between the
326. ow Interrupt Bit 2 DMAOCI Repeat Counter Overflow Flag 0 Repeat Counter Overflow has not occured 1 Repeat Counter Overflow has occured This bit must be cleared by software Bit 1 DMAOEOE End Of Operation Interrupt Enable 0 Disable End Of Operation Interrupt 1 Enable End Of Operation Interrupt Bit 0 DMAOEO End Of Operation Flag 0 End Of Operation Instruction has not been received 1 End Of Operation Instruction has been received This bit must be cleared by software e Rev 1 2 81 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 6 6 DMAOIPT DMAO Instruction Write Address Register SFR Page 3 SFR Address OxDD R R R W R W R W R W R W R W Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Reset Value 00000000 Bits 7 6 Unused Bits 5 0 DMAO instruction address to write or read When DMAOIDT is written or read this register will be incremented to point to the next instruction address Figure 6 7 DMAOIDT DMAO Instruction Write Data Register SFR Page 3 SFR Address R W R W R W R W R W R W R W R W Reset Valuet CCNV DIFFSEL ADC1EN ADCOEN XXXXXXXX Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit 7 CCNV Continuous Conversion 0 Disable Continuous Conversion 1 Enable Continuous Conversion Repeat Counter value is ignored and conversions will continue DIFFSEL Wait for data in differential mode 0 Differenti
327. own to the SFRLAST register the bottom of the stack Note that a value stored in SFRLAST via a previous software write to the SFRLAST register will be overwritten See Figure 13 6 below Figure 13 6 SFR Page Stack Upon Interrupt Occurring During an ADC2 ISR SFR Page 0x00 Automatically pushed on stack in SFRPAGE on PCA interrupt SFRPAGE SFRPAGE pushed to SFRNEXT SFRNEXT SFRNEXT pushed to SFRLAST SFRLAST 136 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 On exit from the PCA interrupt service routine the CIP 51 will return to the ADC2 Window Comparator ISR On execution of the RETI instruction SFR Page 0x00 used to access the PCA registers will be auto SFR Page value 0x0F being used to access Port 5 before the ADC2 interrupt occurred See Figure 13 7 interrupt Likewise the contents of SFRLAST are moved to the SFRNEXT register Recall this was the below matically popped off of the SFR Page Stack and the contents of the SFRNEXT register will be moved to the SFRPAGE register Software in the ADC2 ISR can continue to access SFRs as it did prior to the PCA Figure 13 7 SFR Page Stack Upon Return From PCA Interrupt SFR Page 0x00 gt 9 9 HS 28 lt stack on return from interrupt SFRPAGE SFRNEXT popped to SFRPAGE SFRNEXT SFRLAST REE RSS __AAAAY Kok gt lt 92 etr nan 137 Rev 1 2
328. ows a receive to begin any time a START is detected independent of the TX Timer state Figure 23 2 UART1 Baud Rate Logic DENEN PN rc NN TL1 Overflow 9 p Clock 4 1 Detected I RX Timer 2 RX Clock Timer 1 should be configured for Mode 2 8 bit auto reload see Section 24 1 3 Mode 2 8 bit Counter Timer with Auto Reload on page 289 The Timer 1 reload value should be set so that overflows will occur at two times the desired baud rate Note that Timer 1 may be clocked by one of five sources SYSCLK SYSCLK 4 SYSCLK 12 SYSCLK 48 or the external oscillator clock 8 For any given Timer 1 clock source the UART1 baud rate is determined by Equation 23 1 Equation 23 1 UART1 Baud Rate 1 R V x UartbaudRate Q56 TI 2 Where is the frequency of the clock supplied to Timer 1 and T1H is the high byte of Timer 1 reload value Timer 1 clock frequency is selected as described in Section 24 1 Timer 0 and Timer 1 page 287 A quick reference for typical baud rates and system clock frequencies is given in Table 23 1 through Table 23 6 Note that the internal oscillator may still generate the system clock when the external oscillator is driving Timer 1 see Section 24 1 Timer 0 and Timer 1 on page 287 for more details 278 Rev 1 2 SILICON LABS C8051F060 1 2 3 4
329. p device can also be explicitly disabled on a Port 1 pin by configuring the pin as an Analog Input as described below 18 1 5 Configuring Port 1 and 2 pins as Analog Inputs The pins on Port 1 can serve as analog inputs to the ADC2 analog C8051F060 1 2 3 only and the pins on Port 2 can serve as analog inputs to the Comparators all devices A Port pin is configured as an Analog Input by writing a logic O to the associated bit in the PnMDIN registers All Port pins default to a Digital Input mode Configuring a Port pin as an analog input 1 Disables the digital input path from the pin This prevents additional power supply current from being drawn when the voltage at the pin is near VDD 2 A read of the Port Data bit will return a logic 0 regardless of the voltage at the Port pin 2 Disables the weak pull up device on the pin 3 Causes the Crossbar to skip over the pin when allocating Port pins for digital peripherals Note that the output drivers on a pin configured as an Analog Input are not explicitly disabled Therefore the associated PnMDOUT bits of pins configured as Analog Inputs should explicitly be set to logic 0 Open Drain output mode and the associated Port Data bits should be set to logic 1 high impedance Also note that it is not required to configure a Port pin as an Analog Input in order to use it as an input to ADC2 or the Comparators however it is strongly recommended See the analog peripheral s correspond
330. plement of direct bit to Carry 2 2 MOV C bit Move direct bit to Carry 2 2 MOV bit C Move Carry to direct bit 2 2 JC rel Jump if Carry is set 2 2 3 JNC rel Jump if Carry is not set 2 2 3 JB bit rel Jump if direct bit is set 3 3 4 JNB bit rel Jump if direct bit is not set 3 3 4 JBC bit rel Jump if direct bit is set and clear bit 3 3 4 Program Branching addr11 Absolute subroutine call 2 3 LCALL addr16 Long subroutine call 3 4 RET Return from subroutine 1 5 RETI Return from interrupt 1 5 AJMP 11 Absolute jump 2 3 LUMP addr16 Long jump 3 4 SJMP rel Short jump relative address 2 3 JMP A DPTR Jump indirect relative to DPTR 1 3 JZ rel Jump if A equals zero 2 2 3 JNZ rel Jump if A does not equal zero 2 2 3 CJNE A direct rel Compare direct byte to A and jump if not equal 3 3 4 CJNE A data rel Compare immediate to A and jump if not equal 3 3 4 CJNE Rn data rel o immediate to Register and jump if not 3 3 4 CJNE Ghi data rel 227 immediate to indirect and jump if not 3 4 5 DJNZ Rn rel Decrement Register and jump if not zero 2 2 3 DJNZ direct rel Decrement direct byte and jump if not zero 3 3 4 NOP No operation 1 1 128 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Notes on Registers Operands and Addressing Modes Rn Register RO R7 of the currently selected register bank Ri Data RAM location addressed indirectly through RO or R1 rel 8 bit signed two s complement offset relative to the first by
331. put 01025 MHz Clock Frequency Power Management Modes 256 Bytes of Internal RAM On chip Debug Logic 59 24 General Purpose I O Pins Program and Data Memory Security Rev 1 2 123 SILICON LABS C8051F060 1 2 3 4 5 6 7 The CIP 51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability see Figure 13 1 for a block diagram The CIP 51 includes the following features Performance The CIP 51 employs a pipelined architecture that greatly increases its instruction throughput over the stan dard 8051 architecture In a standard 8051 all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute and usually have a maximum system clock of 12 MHz By contrast the CIP 51 core executes 70 of its instructions in one or two system clock cycles with no instructions taking more than eight system clock cycles With the CIP 51 s maximum system clock at 25 MHz it has a peak throughput of 25 MIPS The CIP 51 has a total of 109 instructions The table below shows the total number of instructions that require each execu tion time Clocks to Execute 1 2 2 3 3 3 4 4 4 5 5 8 Number of Instructions 26 50 5 14 7 3 1 2 1 Figure 13 1 CIP 51 Block Diagram
332. r All references to DCEN and DECEN corrected to DCENn e Timers Chapter Equation 24 1 Equation was corrected to Fsq Ftclk 2 65536 RCAPn This equation is valid for a timer counting up or down Timers Chapter Figure 24 14 TMRnCF Corrected Bit 1 description For square wave output CP RLn 0 C Tn 0 TnOE 1 e VREF Chapters Added VREF Power Supply Current to VREF Electrical Characteristics Tables Chapter Added Note about writing PCAOCPLn to sections for SW Timer Mode High Speed Output Mode Frequency Output Mode 8 bit PWM Mode and 16 bit PWM Mode Oscillators Chapter Table 15 1 Internal Oscillator Electrical Characteristics Updated typical supply current Table 3 1 Global DC Electrical Characteristics Updated supply current numbers with additional char acterization data e ADCO ADC1 Chapter Table 5 2 ADCO and ADC1 Electrical Characteristics Updated supply current numbers with additional characterization data e ADCO ADC1 Chapter Table 5 3 Voltage Reference 0 1 Electrical Characteristics Updated Out put Voltage numbers with characterization data Figure 4 3 TQFP 100 Package Drawing Added L Dimension Figure 4 6 TQFP 64 Package Drawing Added L Dimension e Rev 1 2 327 SILICON LABS Simplicity Studio One click access to MCU and wireless tools documentation software source code libraries amp mor
333. r BRP Extension Register CANOSTA CANOCN and CANOTST can be accessed via C8051 MCU SFRs All others are accessed indirectly using the CAN address indexed method via CANOADR CANODATH and CANODATL Please refer to the Bosch CAN User s Guide for information on the function and use of the CAN Control Protocol Registers 19 2 2 Message Object Interface Registers There are two sets of Message Object Interface Registers used to configure the 32 Message Objects that transmit and receive data to and from the CAN bus Message objects can be configured for transmit or receive and are assigned arbitration message identifiers for acceptance filtering by all CAN nodes Message Objects are stored in Message RAM and are accessed and configured using the Message Object Interface Registers These registers are accessed via the C8051 s CANOADR and CANODAT regis ters using the indirect indexed address method Please refer to the Bosch CAN User s Guide for information on the function and use of the Mes sage Object Interface Registers 19 2 3 Message Handler Registers The Message Handler Registers are read only registers Their flags can be read via the indexed access method with CANOADR CANODATH and CANODATL The message handler registers provide interrupt error transmit receive requests and new data information 228 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Please refer to the Bosch CAN User s Guide for information on the func
334. r since the stack pointer SFR is reset the stack is effectively lost even though the data on the stack are not altered The I O port latches are reset to OxFF all logic 1 s activating internal weak pull ups which take the exter nal I O pins to a high state The external I O pins do not go high immediately but will go high within four system clock cycles after entering the reset state This allows power to be conserved while the part is held in reset For VDD Monitor resets the RST pin is driven low until the end of the VDD reset timeout On exit from the reset state the program counter PC is reset and the system clock defaults to the inter nal oscillator running at its lowest frequency Refer to Section 15 Oscillators on page 171 for information on selecting and configuring the system clock source The Watchdog Timer is enabled using its longest timeout interval see Section 14 7 Watchdog Timer Reset page 165 Once the system clock source is stable program execution begins at location 0 0000 There are seven sources for putting the MCU into the reset state power on power fail external RST pin external CNVSTR2 signal software command Comparator0 Missing Clock Detector and Watchdog Timer Each reset source is described in the following sections Figure 14 1 Reset Sources VDD Crossbar LL o Supply iced CNVSTR Monitor Port 1 0 Supply Reset RST Timeout
335. rate for Timer 2 3 or 4 is determined by the clock source for the timer and the 16 bit reload value stored in the RCAPn register n 2 3 or 4 as shown in Equation 22 4 Equation 22 4 Timer 2 3 or 4 Overflow Rate Timer234 OverflowRate TnCLK 65536 RCAPn 268 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 22 1 3 Mode 2 9 Bit UART Fixed Baud Rate Mode 2 provides asynchronous full duplex communication using a total of eleven bits per data byte a start bit 8 data bits LSB first a programmable ninth data bit and a stop bit Mode 2 supports multiprocessor communications and hardware address recognition see Section 22 2 On transmit the ninth data bit is determined by the value TB80 SCONO 3 It can be assigned the value of the parity flag P in the PSW or used in multiprocessor communications On receive the ninth data bit goes into RB80 SCONO 2 and the stop bit is ignored Data transmission begins when an instruction writes a data byte to the SBUFO register The TIO Transmit Interrupt Flag SCONO 1 is set at the end of the transmission the beginning of the stop bit time Data reception can begin any time after the RENO Receive Enable bit SCONO 4 is set to logic 1 After the stop bit is received the data byte will be loaded into the SBUFO receive register if RIO is logic 0 and one of the following requirements are met 1 5 20 is logic 0 2 5 20 is logic 1 the received 9th bit is logic
336. ration is active and any data from a previous read has already been read from FLASH DAT This mode allows single bytes to be read or the last byte of a block without initiating an extra read All other values for RDMD3 0 are reserved e Rev 1 2 323 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 26 5 FLASHADR JTAG Flash Address Register Reset Value 0 0000 Bit15 Bito This register holds the address for all JTAG Flash read write and erase operations This register auto increments after each read or write regardless of whether the operation succeeded or failed Bits15 0 Flash Operation 16 bit Address Figure 26 4 FLASHDAT JTAG Flash Data Register Reset Value 0000000000 Bit9 Bito This register is used to read or write data to the Flash memory across the JTAG interface Bits9 2 DATA7 0 Flash Data Byte Bit1 FAIL Flash Fail Bit 0 Previous Flash memory operation was successful 1 Previous Flash memory operation failed Usually indicates the associated memory loca tion was locked Bito BUSY Flash Busy Bit 0 Flash interface logic is not busy 1 Flash interface logic is processing a request Reads or writes while BUSY 1 will not ini tiate another operation 324 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 26 3 Debug Support Each MCU has on chip JTAG and debug logic that provides non intrusive f
337. rbitration scheme is employed to force one master to give up the bus The master devices continue transmitting until one attempts a HIGH while the other transmits a LOW Since the bus is open drain the bus will be pulled LOW The master attempting the HIGH will detect a LOW SDA and give up the bus The winning master continues its transmission without interruption the losing master becomes a slave and receives the rest of the transfer This arbitration scheme is non destructive one device always wins and no data is lost 20 2 2 Clock Low Extension SMBus provides a clock synchronization mechanism similar to 12C which allows devices with different speed capabilities to coexist on the bus A clock low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters The slave may temporarily hold the SCL line LOW to extend the clock low period effectively decreasing the serial clock frequency 20 2 3 SCL Low Timeout If the SCL line is held low by a slave device on the bus no further communication is possible Furthermore the master cannot force the SCL line high to correct the error condition To solve this problem the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a timeout condition Devices that have detected the timeout condition must reset the communi cation no later than 10 ms after detecting the timeout condition
338. re information on configuring the voltage reference for the DACs Note that the BIASE bit described in the voltage reference sections must be set to 1 to use the DACs Figure 8 1 DAC Functional Block Diagram DAC0DF2 REF DAC0DF1 REF Rev 1 2 103 SILICON LABS C8051F060 1 2 3 4 5 6 7 8 1 DAC Output Scheduling Each DAC features a flexible output update mechanism which allows for seamless full scale changes and supports jitter free updates for waveform generation The following examples are written in terms of DACO but operation is identical 8 1 1 Update Output On Demand In its default mode DACOCN 4 3 007 the DACO output is updated on demand on a write to the high byte of the DACO data register DACOH It is important to note that writes to DACOL are held and have no effect on the DACO output until a write to DACOH takes place If writing a full 12 bit word to the DAC data registers the 12 bit data word is written to the low byte DACOL and high byte DACOH data registers Data is latched into DACO after a write to the corresponding DACOH register so the write sequence should be DACOL followed by DACOH if the full 12 bit resolution is required The DAC can be used in 8 bit mode by initializing DACOL to the desired value typically 0x00 and writing data to only DACOH also see Section 8 2 for infor
339. re 18 21 P5 Port5 Data Register R W R W R W R W R W R W R W R W Reset Value P5 7 P5 6 P5 5 P5 4 P5 3 P5 2 P5 1 P5 0 11111111 Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Addressable SFR Address 0xD8 SFR Page F Bits7 0 P5 7 0 Port5 Output Latch Bits Write Output appears on pins 0 Logic Low Output 1 Logic High Output open if corresponding PSMDOUT bit 0 See Figure 18 22 Read Returns states of I O pins 0 P5 n pin is logic low 1 P5 n pin is logic high Note P5 7 0 can be driven by the External Data Memory Interface as Address 15 8 in Non mul tiplexed mode See Section 17 External Data Memory Interface and On Chip XRAM on page 187 for more information about the External Memory Interface Figure 18 22 PSMDOUT Port5 Output Mode Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SFR Address 0x9D SFR Page F Bits7 0 P5MDOUT 7 0 Port5 Output Mode Bits 0 Port Pin output mode is configured as Open Drain 1 Port Pin output mode is configured as Push Pull 222 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 18 23 P6 Port6 Data Register R W R W R W R W R W R W R W R W Reset Value P6 7 P6 6 P6 5 P6 4 P6 3 P6 2 P6 1 P6 0 11111111 Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito A
340. re 23 1 UART1 Block Diagram 2 2 Write to SBUFT gt TB81 7 SBUF1 TX Shift Loc TX gt Crossbar L Zero Detector i Tx Control Stop Bit Shift Data Start SCONM Y eth UART1 Baud Rate Generator Serial Port I O Port Interrupt 81 TH tc Rx Control S1MODE 4 MCEI Rx IRQ E Clock Load start X Shift OxtFF RB81 SBUF1 nput Shift Register 9 bits Load SBUF1 SBUF1 RX Latch Read EPA SBUF1 2 SFR Bus Crossbar e Rev 1 2 277 SILICON LABS C8051F060 1 2 3 4 5 6 7 23 1 Enhanced Baud Rate Generation The UART1 baud rate is generated by Timer 1 in 8 bit auto reload mode The TX clock is generated by TL1 the RX clock is generated by a copy of TL1 shown as RX Timer in Figure 23 2 which is not user accessible Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates The RX Timer runs when Timer 1 is enabled and uses the same reload value TH1 However an RX Timer reload is forced when a START condition is detected on the RX pin This all
341. re 5 12 is the Reference Control Register for ADC1 The REFnCN registers are used to enable disable the internal reference and bias generator circuitry for each ADC independently The BIASEn bits enable the on board bias generators for each ADC while the REFBEn bits enable the 2x buffer amplifiers which drive the VREFn pins When disabled the supply current drawn by the bandgap and buffer amplifier falls to less than 1 typical and the output of the buffer amplifier enters high impedance state approximately 25 k Ohms If the internal voltage reference for an ADC is used the BIASEn and REFBEn bits for that ADC must both be set to logic 1 If an external reference is used the REFBEn bit should be set to logic 0 Note that the BIASEn bit for an ADC must be set to logic 1 to enable that ADC regardless of the voltage refer ence that is used If an ADC is not being used the BIASEn bit can be set to logic 0 to conserve power The electrical specifications for the Voltage References are given in Table 5 3 External Voltage Reference 1 25V Band Gap REFnCN BIASEn REFBEn Recommended Bypass Capacitors Figure 5 3 Voltage Reference Block Diagram e Rev 1 2 53 SILICON LABS C8051F060 1 2 3 4 5 6 7 5 3 Modes of Operation ADCO and ADC1 have a maximum conversion speed of 1 Msps The conversion clocks for the ADCs are derived from the system clock The ADCnSC bits in the ADCnCF register determine ho
342. re supported as described in Section 22 2 270 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 22 2 Multiprocessor Communications Modes 2 and 3 support multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit and the built in UARTO address recognition hardware When a master processor wants to transmit to one or more slaves it first sends an address byte to select the tar get s An address byte differs from a data byte in that its ninth bit is logic 1 in a data byte the ninth bit is always set to logic 0 UARTO will recognize as valid i e capable of causing an interrupt two types of addresses 1 a masked address and 2 a broadcast address at any given time Both are described below 22 2 1 Configuration of a Masked Address The UARTO address is configured via two SFRs SADDRO Serial Address and SADENO Serial Address Enable SADENO sets the bit mask for the address held SADDRO bits set to logic 1 in SADENO corre spond to bits in SADDRO that are checked against the received address byte bits set to logic 0 in SADENO correspond to don t care bits in SADDRO Example 1 SLAVE 1 Example 2 SLAVE 2 Example 3 SLAVE 3 SADDRO 00110101 SADDRO 00110101 SADDRO 00110101 SADENO 00001111 SADENO 11110011 SADENO 11000000 UARTO Address xxxx0101 UARTO Address 0011xx01 UARTO Address 00 Setting the SM20 bit SCONO
343. red when 1 is set to logic 1 0 Timer 1 uses the clock defined by the prescale bits 1 5 1 Timer 1 uses the system clock TOM Timer 0 Clock Select This bit selects the clock source supplied to Timer 0 TOM is ignored when 1 set to logic 1 0 Counter Timer 0 uses the clock defined by the prescale bits SCA1 SCAO 1 Counter Timer 0 uses the system clock UNUSED Read 0b Write don t care SCA1 SCAO Timer 0 1 Prescale Bits These bits control the division of the clock supplied to Timer 0 and or Timer 1 if configured to use prescaled clock inputs SCA1 5 0 Prescaled Clock 0 0 System clock divided by 12 0 1 System clock divided by 4 1 0 System clock divided by 48 1 1 External clock divided by 81 External clock divided by 8 is synchronized with the system clock and external clock must be less than or equal to the system clock frequency to operate the timer in this mode Rev 1 2 293 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 24 7 TLO Timer 0 Low Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address SFR Page 0 Bits 7 0 TLO Timer 0 Low Byte The TLO register is the low byte of the 16 bit Timer 0 Figure 24 8 TL1 Timer 1 Low Byt
344. rogress Write 0 No Effect 1 Initiates an offset calibration if ADC1 is idle Bit 3 Bit 2 Bit 1 Bit 0 e Rev 1 2 59 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 5 9 ADCOCN ADCO Control Register R W R W R W R W R W R W R W R W Reset Value ADOEN ADOTM ADOINT ADOBUSY ADOCM1 ADOCMO ADOWINT 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Bit Addressable SFR Address OxE8 SFR Page 0 Bit 7 ADOEN ADCO Enable Bit 0 ADCO Disabled ADCO is in low power shutdown 1 ADCO Enabled ADCO is active and ready for data conversions or calibrations Bit 6 ADOTM ADC Track Mode Bit 0 When the ADC is enabled tracking is continuous unless a conversion is in process 1 Tracking Defined by ADOCM1 0 bits Bit 5 ADOINT ADCO Conversion Complete Interrupt Flag This flag must be cleared by software 0 ADCO has not completed a data conversion since the last time this flag was cleared 1 ADCO has completed a data conversion Bit 4 ADOBUSY ADCO Busy Bit Read 0 ADCO Conversion is complete or a conversion is not currently in progress ADOINT is set to logic 1 on the falling edge of ADOBUSY 1 ADCO Conversion is in progress Write 0 No Effect 1 Initiates ADCO Conversion if ADOCM1 0 00b Bits 3 2 ADOCM1 0 ADCO Start of Conversion Mode Select If ADOTM 0 00 ADCO conversion initiated on every write of 1 to ADOBUSY 01 ADCO conversion initiated on
345. rom all ones OXFF for Timer 1 OXFFFF for Timer 2 3 or 4 to zero a clock is sent to the baud rate logic Timers 1 2 3 or 4 are selected as the baud rate source with bits in the SSTAO register see Figure 22 9 The transmit baud rate clock is selected using the SOTCLK1 and SOTCLKO bits and the receive baud rate clock is selected using the SORCLK1 and SORCLKO bits When Timer 1 is selected as a baud rate source the SMODO bit SSTAO 4 selects whether or not to divide the Timer 1 overflow rate by two On reset the SMODO bit is logic 0 thus selecting the lower speed baud rate by default The SMODO bit affects the baud rate generated by Timer 1 as shown in Equation 22 1 Equation 22 1 Mode 1 Baud Rate using Timer 1 When SMODO 0 Model BaudRate 1 32 OverflowRate When SMODO 1 Model BaudRate 1 16 OverflowRate The Timer 1 overflow rate is determined by the Timer 1 clock source T1CLK and reload value TH1 The frequency of T1CLK is selected as described in Section 24 1 Timer 0 and Timer 1 on page 287 The Timer 1 overflow rate is calculated as shown in Equation 22 2 Equation 22 2 Timer 1 Overflow Rate OverflowRate TICLK 256 When Timers 2 3 or 4 are selected as a baud rate source the baud rate is generated as shown in Equation 22 3 Equation 22 3 Mode 1 Baud Rate using Timer 2 3 or 4 BaudRate 1 16 Timer234 OverflowRate The overflow
346. rrupt will occur if Timer O inter rupts are enabled e Rev 1 2 287 SILICON LABS C8051F060 1 2 3 4 5 6 7 The C TO bit TMOD 2 selects the counter timer s clock source When C TO is set to logic 1 high to low transitions at the selected Timer 0 input pin TO increment the timer register Refer to Section 18 1 Ports 0 through and the Priority Crossbar Decoder on page 205 for information on selecting and configuring external I O pins Clearing C T selects the clock defined by the TOM bit CKCON 3 When TOM is set Timer 0 is clocked by the system clock When TOM is cleared Timer 0 is clocked by the source selected by the Clock Scale bits in CKCON see Figure 24 6 Setting the TRO bit TCON 4 enables the timer when either GATEO TMOD 3 is logic 0 or the input signal INTO is logic level 1 Setting GATEO to 1 allows the timer to be controlled by the external input signal INTO see Section 13 3 5 Interrupt Register Descriptions on page 154 facilitating pulse width measure ments TRO GATEO INTO Counter Timer 0 X X Disabled 1 0 X Enabled 1 1 0 Disabled 1 1 1 Enabled X Don t Care Setting TRO does not force the timer to reset The timer registers should be loaded with the desired initial value before the timer is enabled TL1 and TH1 form the 13 bit register for Timer 1 in the same manner as described above for TLO and THO Timer 1 is configured and controlled using th
347. rs Reading SCONO accesses the Receive register and writing SCONO accesses the Transmit register UARTO may be operated in polled or interrupt mode UARTO has two sources of interrupts a Transmit Interrupt flag TIO SCONO 1 set when transmission of a data byte is complete and a Receive Interrupt flag RIO SCONO 0 set when reception of a data byte is complete UARTO interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine they must be cleared manually by soft ware This allows software to determine the cause of the UARTO interrupt transmit complete or receive complete Figure 22 1 UARTO Block Diagram 2 SFR Bus Write to SBUF0 D SBUF0 pho os SSTAO a U Crossbar 5 515189 1 scc Zero Detector O LIO LIL L L 0 MENEAR Stop Bit Shift mee Start Tx Control r T Clock SCONO UARTO L Serial Baud Rate Generation IB B I a Interrupt Logic 0 1 2 8 8 0 0 7 RIO Rx Clock EN Load oai
348. rst see the timing diagram in Figure 22 2 and the TIO Transmit Interrupt Flag SCONO 1 is set at the end of the eighth bit time Data reception begins when the RENO Receive Enable bit SCONO 4 is set to logic 1 and the RIO Receive Interrupt Flag SCONO 0 is cleared One cycle after the eighth bit is shifted in the RIO flag is set and reception stops until software clears the RIO bit An inter rupt will occur if enabled when either TIO or RIO are set 266 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 The Mode 0 baud rate is SYSCLK 12 is forced to open drain in Mode 0 and an external pull up will typically be required Figure 22 2 UARTO Mode 0 Timing Diagram MODE 0 TRANSMIT RX data out 00 D1 D2 D3 Y D4 05 06 D7 TX clk out 1 MODE 0 RECEIVE RX data in Do D1 D2 D3 D4 D5 D6 D7 TX clk out Figure 22 3 UART0 Mode 0 Interconnect TX CLK Shift Heg 8 Extra Outputs C8051F xxx 22 1 2 Mode 1 8 Bit UART Variable Baud Rate Mode 1 provides standard asynchronous full duplex communication using a total of 10 bits per data byte one start bit eight data bits LSB first and one stop bit Data are transmitted from the TXO pin and received at the RXO pin
349. rt 0 Output Mode Configuration page 214 1 0 90 All Pages Port 1 Latch page 215 P1MDIN OxAD F Port 1 Input Mode page 215 P1MDOUT OxA5 F Port 1 Output Mode Configuration page 216 P2 0 0 All Pages Port 2 Latch page 216 144 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 13 3 Special Function Registers Continued SFRs are listed in alphabetical order All undefined SFR locations are reserved Register Address SFR Page Description Page No P2MDIN OxAE F Port 2 Input Mode page 217 P2MDOUT OxA6 F Port 2 Output Mode Configuration page 217 P3 0 0 All Pages Port 3 Latch page 218 P3MDOUT OxA7 F Port 3 Output Mode Configuration page 218 P4 0xC8 F Port 4 Latch page 221 PAMDOUT Ox9C F Port 4 Output Mode Configuration page 221 P5 OxD8 F Port 5 Latch page 222 P5MDOUT Ox9D F Port 5 Output Mode Configuration page 22271 P6 OxE8 F Port 6 Latch page 2231 P6MDOUT Ox9E F Port 6 Output Mode Configuration page 2237 P7 OxF8 F Port 7 Latch page 2241 P7MDOUT Ox9F F Port 7 Output Mode Configuration page 2247 PCAOCN OxD8 0 PCA Control page 312 PCAOCPHO OxFC 0 PCA Capture 0 High page 316 PCAOCPH 1 OxFE 0 PCA Capture 1 High page 316 2 0 PCA Capture 2 High page 316 PCAOCPH3 OxEC 0 PCA Capture 3 High page 316 OxEE 0 PCA Capture 4 High page 316
350. rupt service routine ISR so its interrupt is enabled and is set to high priority The ADC2 is monitoring a voltage that is less important but to minimize the software overhead its window comparator is being used with an associ ated ISR that is set to low priority At this point the SFR page is set to access the Port 5 SFR SFRPAGE In this example the SFR Page Control is left in the default enabled state i e SFRPGEN OxOF See Figure 13 4 below CIP 51 is executing in line code that is writing values to Port 5 SFR P5 located at address OxD8 on SFR C8051F060 1 2 3 4 5 6 7 13 2 6 3 SFR Page Stack Example The following is an example that shows the operation of the SFR Page Stack during interrupts o W or O gt lt U 25 lt lt id A Z oc Lo 9 LL 40 Qo CCa a 5v k g g lCry 3 ky l ycYI NWNWII I I I YII lt O ES II IIIIIII I IIKUHUONI I K IO I IK II I IO NI Figure 13 4 SFR Page Stack While Using SFR Page 0x0F To Access Port 5 SILICON LABS Rev 1 2 134 C8051F060 1 2 3 4 5 6 7 Interrupt occurs The CIP 51 vectors to the ADC2 Window Comparator ISR and pushes the current SFR Page value SFR Page Ox0F into SFRNEXT in the SFR Page Stack The SFR page needed to access ADC2 s SFRs is then automatically placed in the SFRPAGE register SFR Page 0x02 SFRPAGE is con sidered the top of t
351. s 0x0000 C8051F066 7 EXTERNAL DATA ADDRESS SPACE 0x1007F Memory OxFFFF 0x10000 data only OxFFFF RESERVED 0x8000 Ox7FFF FLASH 0x1000 In System OxOFFF Programmable in 512 XRAM 4096 Bytes Byte Sectors accessable using MOVX 0x0000 0x0000 instruction Figure 1 7 On Chip Memory Map e Rev 1 2 27 SILICON LABS C8051F060 1 2 3 4 5 6 7 1 3 JTAG Debug and Boundary Scan The 8051 06 family has on chip JTAG boundary scan and debug circuitry that provides non intrusive full speed in circuit debugging using the production part installed in the end application via the four pin JTAG interface The JTAG port is fully compliant to IEEE 1149 1 providing full boundary scan for test and manufacturing purposes Silicon Laboratories debugging system supports inspection and modification of memory and registers breakpoints watchpoints a stack monitor and single stepping No additional target RAM program mem ory timers or communications channels are required All the digital and analog peripherals are functional and work correctly while debugging All the peripherals except for the ADCs and SMBus are stalled when the MCU is halted during single stepping or at a breakpoint in order to keep them synchronized with instruction execution The C8051F060DK development kit provides all the hardware and software necessary to develop applica tion code and perform in circuit debugging with the C8051F06x MCUs The kit
352. s Slave Mode Timing See Figure 21 14 and Figure 21 15 Tse NSS Falling to First SCK Edge 2 Tsyscik ns Tsp Last SCK Edge to NSS Rising 2 TSYSCLK ns Tsez NSS Falling to MISO Valid 4 Tsyscik ns Tspz NSS Rising to MISO High Z 4 ns SCK High Time 9 Tsvscik ns TckL SCK Low Time S T SYSCLK ns Tsis MOSI Valid to SCK Sample Edge 2 5 SCK Sample Edge to MOSI Change 2 TSYSCLK ns Tsou SCK Shift Edge to MISO Change 4 ns TOR Last SCK Edge to MISO Change 1 8 ns ONLY TT syscik is equal to one period of the device system clock SYSCLK 264 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 22 UARTO UARTO is an enhanced serial port with frame error detection and address recognition hardware UARTO may operate in full duplex asynchronous or half duplex synchronous modes and mutiproccessor commu nication is fully supported Receive data is buffered a holding register allowing UARTO to start reception of a second incoming data byte before software has finished reading the previous data byte A Receive Overrun bit indicates when new received data is latched into the receive buffer before the previously received byte has been read UARTO is accessed via its associated SFRs Serial Control SCONO and Serial Data Buffer SBUFO The single SBUFO location provides access to both transmit and receive registe
353. s enabled by setting WEAKPUD XBR2 7 to a logic 0 2 Configure the output modes of P3 P4 P5 P6 and P7 to Push Pull by writing OxFF to the associated output mode register PRMDOUT 3 Force the output states of P3 P4 P5 P6 and P7 to logic 0 by writing zeros to the Port Data registers P3 0x00 P4 0x00 P5 0x00 P6 0x00 P7 0x00 18 2 2 Configuring the Output Modes of the Port Pins The output mode of each port pin can be configured to be either Open Drain or Push Pull In the Push Pull configuration a logic 0 in the associated bit in the Port Data register will cause the Port pin to be driven to GND and a logic 1 will cause the Port pin to be driven to VDD In the Open Drain configuration a logic 0 in the associated bit in the Port Data register will cause the Port pin to be driven to GND and a logic 1 will cause the Port pin to assume a high impedance state The Open Drain configuration is useful to prevent contention between devices in systems where the Port pin participates in a shared interconnection in which multiple outputs are connected to the same physical wire The output modes of the Port pins on Ports 4 through 7 are determined by the bits in their respective PnMDOUT Output Mode Registers Each bit in PhMDOUT controls the output mode of its corresponding port pin see Figure 18 20 Figure 18 22 Figure 18 24 and Figure 18 26 For example to place Port pin 5 3 in push pull mode digital output set PSMD
354. se Cycle Time 10 12 14 ms Write Cycle Time 40 50 60 us Includes 128 byte Scratch Pad Area T 1024 Bytes at location OXFCOO to OxFFFF are reserved 16 2 Non volatile Data Storage The Flash memory can be used for non volatile data storage as well as program code This allows data such as calibration coefficients to be calculated and stored at run time Data is written using the MOVX write instruction as described in the previous section and read using the MOVC instruction An additional 128 byte sector of Flash memory is included for non volatile data storage Its smaller sector size makes it particularly well suited as general purpose non volatile scratchpad memory Even though Flash memory can be written a single byte at a time an entire sector must be erased first In order to change a single byte of a multi byte data set the data must be moved to temporary storage The 128 byte sector size facilitates updating data without wasting program memory or RAM space The 128 byte sector is double mapped over the normal Flash memory area its address ranges from 0 00 to Ox7F see Figure 16 1 and Figure 16 2 To access this 128 byte sector the SFLE bit in PSCTL must be set to logic 1 Code execution from this 128 byte scratchpad sector is not supported 178 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 16 3 Security Options The CIP 51 provides security options to protect the Flash memory from inadvertent mod
355. sed directly in the CIP 51 SFR register space or through the indi rect index method See Section 19 2 5 Using CANOADR CANODATH and CANDATL To Access CAN Registers on page 229 232 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 19 7 CANOTST CAN Test Register R W R W R W R W R W R W R W R W Reset Value Please see the Bosch CAN User s Guide for a complete definition of this register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xDB SFR Page 1 All CAN registers functions definitions are listed and described in the Bosch CAN User s Guide This register may be accessed directly in the CIP 51 SFR register space or through the indi rect index method See Section 19 2 5 Using CANOADR CANODATH and CANDATL To Access CAN Registers on page 229 Figure 19 8 CANOSTA CAN Status Register R W R W R W R W R W R W R W R W Reset Value Please see the Bosch CAN User s Guide for a complete definition of this register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0xC0 SFR Page 1 All CAN registers functions definitions are listed and described in the Bosch CAN User s Guide This register may be accessed directly in the CIP 51 SFR register space or through the indi rect index method See Section 19 2 5 Using CANOADR CANODATH and CANDATL To Access CAN Registers on page 229 Rev 1 2 233 SILICON LABS C8051F060 1
356. served Register Address SFR Page Description Page No REFOCN OxD1 0 Voltage Reference Control 0 page 62 REF1CN OxD1 1 Voltage Reference Control 1 page 62 page 11272 REF2CN OxD1 2 Voltage Reference Control 2 page 114 3 page 1165 RSTSRC OxEF 0 Reset Source page 168 SADDRO 0 0 UART 0 Slave Address page 276 SADENO 0 9 0 UART 0 Slave Address Enable page 276 SBUFO 0x99 0 UART 0 Data Buffer page 276 SBUF 1 0x99 1 UART 1 Data Buffer page 283 SCONO 0x98 0 UART 0 Control page 274 SCON1 0x98 1 UART 1 Control page 282 SFRLAST 0x86 All Pages SFR Page Stack Access Register page 140 SFRNEXT 0x85 Pages SFR Page Register page 140 SFRPAGE 0x84 All Pages SFR Page Register page 139 SFRPGCN 0x96 F SFR Page Control Register page 139 SMBOADR 0xC3 0 SMBus Slave Address page 246 SMBOCN 0xCO 0 SMBus Control page 243 SMBOCR OxCF 0 SMBus Clock Rate page 244 SMBODAT 0 2 0 SMBus Data page 245 SMBOSTA OxC1 0 SMBus Status page 247 SP 0 81 All Pages Stack Pointer page 148 SPIOCFG 0x9A 0 SPI Configuration page 258 SPIOCKR 0 9 0 SPI Clock Rate Control page 260 SPIOCN OxF8 0 SPI Control page 259 SPIODAT Ox9B 0 SPI Data page 261 SSTAO 0x91 0 UART 0 Status page 275 TCON 0x88 0 Timer Counter Control page 291 THO 0x8C 0 Timer Counter 0 High page 294 TH1 0x8D 0 Timer Counter 1 High page 294 TLO Ox8A 0
357. set bits in Flash A byte location to be programmed must be erased before a new value can be written The Flash memory is organized in 512 byte pages The erase operation applies to an entire page setting all bytes in the page to OxFF The following steps illustrate the algorithm for programming Flash from user software Step 1 Disable interrupts Step 2 Set FL WE FLSCL 0 to enable Flash writes erases via user software Step 3 Set PSEE PSCTL 1 to enable Flash erases Step 4 Set PSWE PSCTL 0 to redirect MOVX commands to write to Flash Step 5 Use the MOVX command to write a data byte to any location within the 512 byte page to be erased Step 6 Clear PSEE to disable Flash erases Step 7 Use the MOVX command to write a data byte to the desired byte location within the erased 512 byte page Repeat this step until all desired bytes are written within the target page e Rev 1 2 177 SILICON LABS C8051F060 1 2 3 4 5 6 7 Step 8 Clear the PSWE bit to redirect MOVX write commands to the XRAM data space Step 9 Re enable interrupts Write Erase timing is automatically controlled by hardware Note that code execution in the 8051 is stalled while the Flash is being programmed or erased Table 16 1 Flash Electrical Characteristics Parameter Conditions Min Typ Max Units Flash Size C8051F060 1 2 3 4 5 65664 t Bytes Flash Size 8051 066 7 32896 Bytes Endurance 20 k 100 k Erase Write Era
358. set to logic 1 software should not attempt to access the SMBODAT register when the SMBus is enabled and the SI flag reads logic 0 since the hardware may be in the process of shifting a byte of data in or out of the register Data in SMBODAT is always shifted out MSB first After a byte has been received the first bit of received data is located at the MSB of SMBODAT While data is being shifted out data on the bus is simultaneously being shifted in Therefore SMBODAT always contains the last data byte present on the bus In the event of lost arbitration the transition from master transmitter to slave receiver is made with the correct data in SMBODAT Figure 20 10 SMBODAT 5 0 Data Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xC2 SFR Page 0 Bits7 0 SMBODAT SMBus0O Data SMBODAT register contains a byte of data to be transmitted on the SMBusO serial inter face or a byte that has just been received on the SMBusO serial interface The CPU can read from or write to this register whenever the SI serial interrupt flag SMBOCN 3 is set to logic 1 When the SI flag is not set the system may be in the process of shifting data and the CPU should not attempt to access this register 20 4 4 Address Register The SMBOADR Address register holds the slave address for the SMBusO interface In slave mode the seven most signif
359. shed the ADCnOCAL bit will be set to 0 by the hardware Offset calibration can compensate for offset errors of approximately 3 125 of full scale The offset value is added to the AINnG input prior to digitization by the ADC Gain calibration is initiated by setting the ADCnGCAL bit to 1 When the calibration is finished the ADCnGCAL bit will be set to 0 by the hardware Gain calibration can compensate for slope errors of approximately 3 125 The gain value is added to the ADC s VREF path to change the slope of the converter s transfer function Figure 5 21 shows how the offset and gain values affect the analog signals used by the ADC 66 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 5 20 Offset and Gain Register Mapping The offset register value affects the offset at the analog input as follows Offset Register 14 Bits Ox3FFF Approximate Offset Change V 3 125 VREF 0x2000 0 0x0000 3 125 VREF Offset Change 0x2000 Offset Register x 3 125 x VREF 8192 The gain register value affects the slope of the ADC transfer function as follows Gain Register 13 Bits Approximate Slope Change 0x1 FFF 3 125 0x1000 0 0x0000 3 125 Gain Register 0x 1000 07 4096 x 3 125 Slope Change Figure 5 21 Offset and Gain Calibration Block Diagram VREF Gain Offset AINn 16 ADCn Data AINnG x
360. sive OR Register to A 1 1 XRL A direct Exclusive OR direct byte to A 2 2 XRL A Ri Exclusive OR indirect RAM to A 1 2 XRL A data Exclusive OR immediate to A 2 2 XRL direct A Exclusive OR A to direct byte 2 2 126 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 13 1 CIP 51 Instruction Set Summary Continued E Clock Mnemonic Description Bytes Cycles XRL direct data Exclusive OR immediate to direct byte 3 3 CLRA Clear A 1 1 CPLA Complement A 1 1 RLA Rotate A left 1 1 RLC Rotate left through Carry 1 1 RRA Rotate A right 1 1 RRC A Rotate A right through Carry 1 1 SWAP A Swap nibbles of A 1 1 Data Transfer MOV A Rn Move Register to A MOV A direct Move direct byte to A MOV A Ri Move indirect RAM to A MOV A data Move immediate to A MOV Rn A Move A to Register MOV direct Move direct byte to Register MOV Rn data Move immediate to Register MOV direct A Move A to direct byte MOV direct Rn Move Register to direct byte MOV direct direct Move direct byte to direct byte MOV direct Ri Move indirect RAM to direct byte MOV direct data Move immediate to direct byte MOV Ri A Move A to indirect RAM MOV direct Move direct byte to indirect RAM MOV data Move immediate to indirect RAM MOV DPTR 16 Load DPTR with 16 bit constant MOVC A
361. sks 138 C8051F060 1 2 3 4 5 6 7 Figure 13 9 SFRPGCN SFR Page Conirol Register R W R W R W R W R W R W R W R W Reset Value SFRPGEN 00000001 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0x96 SFR Page F Bits7 1 Reserved Bito SFRPGEN SFR Automatic Page Control Enable Upon interrupt the C8051 Core will vector to the specified interrupt service routine and automatically switch the SFR page to the corresponding peripheral or function s SFR page This bit is used to control this autopaging function 0 SFR Automatic Paging disabled C8051 core will not automatically change to the appro priate SFR page i e the SFR page that contains the SFRs for the peripheral function that was the source of the interrupt 1 SFR Automatic Paging enabled Upon interrupt the C8051 will switch the SFR page to the page that contains the SFRs for the peripheral or function that is the source of the inter rupt Figure 13 10 SFRPAGE SFR Page Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bite Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0x84 SFR Page All Pages Bits7 0 SFR Page Bits Byte Represents the SFR Page the C8051 MCU uses when reading or modifying SFRs Write Sets the SFR Page Read Byte is the SFR page the C8051 MCU is using When enabled in the SFR Page Control Register SFRPGCN the C8051 will automatical
362. ss W received transmit ted Save current data for retry when bus is free Wait for data 0x70 General call address received ACK transmit ted Wait for data 0x78 Arbitration lost in sending SLA R W as mas ter General call address received ACK trans mitted Save current data for retry when bus is free 0x80 Data byte received ACK transmitted Read SMBODAT Wait for next byte or STOP 0x88 Data byte received NACK transmitted Set STO to reset SMBus 0x90 Data byte received after general call address ACK transmitted Read SMBODAT Wait for next byte or STOP 0x98 Data byte received after general call address NACK transmitted Set STO to reset SMBus OxAO STOP or repeated START received No action necessary OxA8 Own address R received ACK transmitted Load SMBODAT with data to transmit 0 0 Arbitration lost in transmitting SLA R W as master Own address R received ACK transmitted Save current data for retry when bus is free Load SMBODAT with data to trans mit 0 8 Data byte transmitted ACK received Load SMBODAT with data to transmit 0xC0 Data byte transmitted NACK received Wait for STOP 0xC8 Last data byte transmitted AA 0 ACK received Set STO to reset SMBus 0xD0 SCL Clock High Timer per SMB0CR timed out Set STO to reset SMBus 0x00 Bus Error illeg
363. status code are fixed at zero when SI 1 Therefore all possible status codes are multiples of eight This facilitates the use of sta tus codes in software as an index used to branch to appropriate service routines allowing 8 bytes of code to service the state or jump to a more extensive service routine For the purposes of user software the contents of the SMBOSTA register is only defined when the SI flag is logic 1 Software should never write to the SMBOSTA register doing so will yield indeterminate results The 246 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 28 SMBusO states along with their corresponding status codes are given in Table 1 1 Figure 20 12 SMBOSTA SMBus0 Status Register R W R W R W R W R W R W R W R W Reset Value STA7 STA6 STA5 STA4 5 STA2 STA1 STAO 11111000 Bit7 Bit Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xC1 SFR Page 0 Bits7 3 5 7 5 5 50 Status Code These bits contain the SMBus0 Status Code There are 28 possible status codes each sta tus code corresponds to a single SMBus state A valid status code is present in SMBOSTA when the SI SMBOCN 3 is set to logic 1 The content of SMBOSTA is not defined when the SI flag is logic 0 Writing to the SMBOSTA register at any time will yield indeterminate results Bits2 0 5 2 5 0 The three least significant bits of SMBOSTA are always read as logic 0 when the SI flag is
364. ster This register calibrates the internal oscillator period The reset value for OSCICL defines the internal oscillator base frequency The reset value is factory calibrated to generate an inter nal oscillator frequency of 24 5 MHZ Figure 15 3 OSCICN Internal Oscillator Control Register R W R W R R W R W R W R W Reset Value IOSCEN IFRDY IFCN1 IFCNO 11000000 Bit7 Bit7 Bit6 Bits5 2 Bits1 0 Bit6 Bit5 Bit4 Bit2 Bit Bito SFR Address 0x8A SFR Page F IOSCEN Internal Oscillator Enable Bit 0 Internal Oscillator Disabled 1 Internal Oscillator Enabled IFRDY Internal Oscillator Frequency Ready Flag 0 Internal Oscillator not running at programmed frequency 1 Internal Oscillator running at programmed frequency Reserved IFCN1 0 Internal Oscillator Frequency Control Bits 00 SYSCLK derived from Internal Oscillator divided by 8 01 SYSCLK derived from Internal Oscillator divided by 4 10 SYSCLK derived from Internal Oscillator divided by 2 11 SYSCLK derived from Internal Oscillator divided by 1 172 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 15 1 Internal Oscillator Electrical Characteristics 40 C to 85 C unles otherwise specified Parameter Conditions Min Typ Max Units Calibrated Internal Oscillator 24 245 25 MHz Frequency Internal Oscillator Supply n Current
365. t OUTPUT uuu uu 203 18 1 Ports 0 through and the Priority Crossbar Decoder 205 18 1 1 Crossbar Pin Assignment and Allocation 205 18 1 2 Configuring the Output Modes of the Port Pins 206 18 1 3 Configuring Port Pins as Digital Inputs 207 18 1 4 Weak quio m 207 Rev 1 2 5 SILICON LABS C8051F060 1 2 3 4 5 6 7 18 1 5 Configuring Port 1 and 2 pins as Analog Inputs 207 18 1 6 Crossbar Pin Assignment 208 18 2 Ports 4 through 7 58051F060 2 4 8 only 219 18 2 1 Configuring Ports which are not Pinned 219 18 2 2 Configuring the Output Modes of the Port 219 18 2 3 Configuring Port Pins as Digital Inputs 219 18 2 4 Weak Pull UpS C centering 219 18 2 5 External Memory 100 220 19 Controller Area Network CANO 8051 060 1 2 3 225 19 1 Bosch CAN Controller Operation
366. t care Bit5 PRTSEL EMIF Port Select 0 EMIF not mapped to port pins 1 EMIF active on P4 P7 Bit4 EMD2 EMIF Multiplex Mode Select 0 EMIF operates in multiplexed address data mode 1 EMIF operates in non multiplexed mode separate address and data pins Bits3 2 EMD1 0 EMIF Operating Mode Select These bits control the operating mode of the External Memory Interface 00 Internal Only MOVX accesses on chip XRAM only All effective addresses alias to on chip memory space 01 Split Mode without Bank Select Accesses below the 4 kB boundary are directed on chip Accesses above the 4 kB boundary are directed off chip 8 bit off chip MOVX operations use the current contents of the Address High port latches to resolve upper address byte Note that in order to access off chip space EMIOCN must be set to a page that is not contained in the on chip address space 10 Split Mode with Bank Select Accesses below the 4 kB boundary are directed on chip Accesses above the 4 kB boundary are directed off chip 8 bit off chip MOVX operations use the contents of EMIOCN to determine the high byte of the address 11 External Only MOVX accesses off chip XRAM only On chip XRAM is not visible to the CPU Bits1 0 0 ALE Pulse Width Select Bits only has effect when 0 00 ALE high and ALE low pulse width 1 SYSCLK cycle 01 ALE high and ALE low pulse width 2 SYSCLK cycles 10 ALE high and ALE low pulse width 3 SYSCLK cycles
367. t is not used in Modes 0 and 1 Set or cleared by software as required Bit2 RB80 Ninth Receive Bit The bit is assigned the logic level of the ninth bit received in Modes 2 and 3 In Mode 1 if SM20 is logic 0 RB80 is assigned the logic level of the received stop bit RB8 is not used in Mode 0 Bit1 TIO Transmit Interrupt Flag Set by hardware when a byte of data has been transmitted by UARTO after the 8th bit in Mode 0 or at the beginning of the stop bit in other modes When the UARTO interrupt is enabled setting this bit causes the CPU to vector to the UARTO interrupt service routine This bit must be cleared manually by software RIO Receive Interrupt Flag Set by hardware when a byte of data has been received by UARTO as selected by the 5 20 bit When the UARTO interrupt is enabled setting this bit causes the CPU to vector to the UARTO interrupt service routine This bit must be cleared manually by software 274 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 22 9 SSTAO UARTO Status and Clock Selection Register R W R W R W R W R W R W R W R W Reset Value FEO RXOVO TXCOLO SMODO SOTCLK1 SOTCLKO SORCLK1 SORCLKO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address 0x91 SFR Page 0 Bit7 FE0 Frame Error Flag t This flag indicates if an invalid low STOP bit is detected 0 Frame Error has not been detected
368. t2 Bit1 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SFR Address 7 SFR Page All Pages PDMAO DMAO Interrupt Priority Control This bit sets the priority of the DMAO interrupt 0 DMAO interrupt set to low priority 1 DMAO interrupt set to high priority PS1 UART1 Interrupt Priority Control This bit sets the priority of the UART1 interrupt 0 UART1 interrupt set to low priority 1 UARTI interrupt set to high priority PCANO CAN Interrupt Priority Control This bit sets the priority of the CAN Interrupt 0 CAN Interrupt set to low priority level 1 CAN Interrupt set to high priority level PADC2 ADC2 End Of Conversion Interrupt Priority Control This bit sets the priority of the ADC2 End of Conversion interrupt 0 ADC2 End of Conversion interrupt set to low priority 1 ADC2 End of Conversion interrupt set to high priority PWADC2 ADC2 Window Comparator Interrupt Priority Control 0 ADC2 Window interrupt set to low priority 1 ADC2 Window interrupt set to high priority 4 Timer 4 Interrupt Priority Control This bit sets the priority of the Timer 4 interrupt 0 Timer 4 interrupt set to low priority 1 Timer 4 interrupt set to high priority PADC1 ADC End of Conversion Interrupt Priority Control This bit sets the priority of the ADC1 End of Conversion Interrupt 0 ADC1 End of Conversion interrupt set to low priority level 1 ADC1 End of Conversion interrupt set to high priority level
369. ta Access Register High Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xD9 SFR Page 1 Bit7 0 CANODATH CAN Data Access Register High Byte The CANODAT Registers are used to read write register values and data to and from the CAN Registers pointed to with the index number in the CANOADR Register The CANOADR Register is used to point the CANODATH CANODATL to a desired CAN Register The desired CAN Register s index number is moved into CANOADR The CANODAT Register can then read write to and from the CAN Register Figure 19 4 CANODATL CAN Data Access Register Low Byte R W R W R W R W R W R W R W R W Reset Value 00000001 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0xD8 SFR Page 1 Bit7 0 CANODATL CAN Data Access Register Low Byte The CANODAT Registers are used to read write register values and data to and from the CAN Registers pointed to with the index number in the CANOADR Register CANOADR Register is used to point the CANODATH CANODATL to a desired Register The desired CAN Register s index number is moved into CANOADR The CANODAT Register can then read write to and from the CAN Register e Rev 1 2 231 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 19 5 CANOADR CAN Address Index Register R W R W R W R W R W
370. tack A programmer s stack can be located anywhere in the 256 byte data memory The stack area is designated using the Stack Pointer SP address 0x81 SFR The SP will point to the last location used The next value pushed on the stack is placed at SP 1 and then SP is incremented A reset initializes the stack pointer to location 0x07 therefore the first value pushed on the stack is placed at location 0x08 which is also the first register RO of register bank 1 Thus if more than one register bank is to be used the SP should be initialized to a location in the data memory not being used for data storage The stack depth can extend up to 256 bytes The MCUs also have built in hardware for a stack record which is accessed by the debug logic The stack record is a 32 bit shift register where each PUSH or increment SP pushes one record bit onto the register Rev 1 2 131 SILICON LABS C8051F060 1 2 3 4 5 6 7 and each CALL pushes two record bits onto the register A POP or decrement SP pops one record bit and a RET pops two record bits also The stack record circuitry can also detect an overflow or underflow on the 32 bit shift register and can notify the debug software even with the MCU running at speed 13 2 6 Special Function Registers The direct access data memory locations from 0x80 to OxFF constitute the Special Function Registers SFRs The SFRs provide control and data exchange with the CIP 51 s resources and perip
371. te If the VDD monitor circuitry is enabled by tying the MONEN pin to a logic high state this bit can be written to select or de select the VDD monitor as a reset source 0 De select the VDD monitor as a reset source 1 Select the VDD monitor as a reset source Important At power on the VDD monitor is enabled disabled using the external VDD monitor enable pin MONEN The PORSF bit does not disable or enable the VDD monitor circuit It simply selects the VDD monitor as a reset source Read This bit is set whenever a power on reset occurs This may be due to a true power on reset VDD monitor reset In either case data memory should be considered indeterminate following the reset 0 Source of last reset was not a power on or VDD monitor reset 1 Source of last reset was a power on or VDD monitor reset Note When this flag is read as 1 all other reset flags are indeterminate Bito PINRSF HW Pin Reset Flag Write 0 No effect 1 Forces a Power On Reset RST is driven low Read 0 Source of prior reset was not RST pin 1 Source of prior reset was RST pin 168 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 14 1 Reset Electrical Characteristics 40 to 85 C unless otherwise specified Parameter Conditions Min Typ Max Units RST Output Low Voltage lo 8 5 mA VDD 2 7 V to 3 6 V 0 6 V 0 7 RST Input High Voltage VDD V
372. te of the following instruction Used by SJMP and all conditional jumps direct 8 bit internal data location s address This could be a direct access Data RAM location 0x00 Ox7F or an SFR 0 80 0 data 8 bit constant data16 16 bit constant bit Direct accessed bit in Data RAM or SFR addr11 11 bit destination address used by ACALL and AJMP The destination must be within the same 2K byte page of program memory as the first byte of the following instruction addr16 16 bit destination address used by LCALL and LJMP The destination may be anywhere within the 64K byte program memory space There is one unused opcode 0xA5 that performs the same function as NOP All mnemonics copyrighted Intel Corporation 1980 e Rev 1 2 129 SILICON LABS C8051F060 1 2 3 4 5 6 7 13 2 Memory Organization The memory organization of the CIP 51 System Controller is similar to that of a standard 8051 There are two separate memory spaces program memory and data memory Program and data memory share the same address space but are accessed via different instruction types There are 256 bytes of internal data memory and 64 k bytes C8051F060 1 2 3 4 5 or 32 bytes C8051F066 7 of internal program memory address space implemented within the CIP 51 The CIP 51 memory organization is shown in Figure 13 2 Figure 13 2 Memory Map PROGRAM DATA MEMORY DATA MEMORY RAM FLASH OxFF INTERNAL DATA ADDRESS SPACE 0
373. ter 2 R W R W R W R W R W R W R W Reset Value WEAKPUD XBARE T4EXE T4E UART1E 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bits 1 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xE3 SFR Page F WEAKPUD Weak Pull Up Disable Bit 0 Weak pull ups globally enabled 1 Weak pull ups globally disabled XBARE Crossbar Enable Bit 0 Crossbar disabled All pins on Ports 0 1 2 and 3 are forced to Input mode 1 Crossbar enabled UNUSED Read 0 Write don t care T4EXE T4EX Input Enable Bit 0 T4EX unavailable at Port pin 1 T4EX routed to Port pin T4E T4 Input Enable Bit 0 T4 unavailable at Port pin 1 T4 routed to Port pin UART1E UART1 I O Enable Bit 0 UART1 I O unavailable at Port pins 1 UART1 TX and RX routed to 2 Port pins Reserved 212 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 18 8 XBR3 Port Crossbar Register 3 R R R R W R W R W R W R W Reset Value CTXOUT E CP2E CNVST2E 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0 4 SFR Page F Bit7 CTXOUT CAN Transmit Pin CTX Output Mode 0 CTX pin output mode is configured as open drain 1 CTX pin output mode is configured as push pull Bit6 4 Reserved Bit3 CP2E CP2 Output Enable Bit 0 CP2 unavailable at Port pin 1 CP2 routed to Port pin Bit2 CNVS
374. terrupt sources are very useful when building multi tasking real time systems There are up to seven reset sources for the MCU an on board VDD monitor a Watchdog Timer a missing clock detector a voltage level detection from Comparator0 a forced software reset the CNVSTR2 input pin and the RST pin The RST pin is bi directional accommodating an external reset or allowing the internally generated POR to be output on the RST pin Each reset source except for the VDD monitor and Reset Input pin may be disabled by the user in software the VDD monitor is enabled disabled via the MONEN pin The Watchdog Timer may be permanently enabled in software after a power on reset during MCU initialization The MCU has an internal stand alone clock generator which is used by default as the system clock after any reset If desired the clock source may be switched on the fly to the external oscillator which can use a crystal ceramic resonator capacitor RC or external clock source to generate the system clock This can be extremely useful in low power applications allowing the MCU to run from a slow power saving exter nal crystal source while periodically switching to the fast up to 25 MHz internal oscillator as needed Port CNVSTR2 4 Supply 1 0 4 ccc
375. the SMBusO Free Timer Enable bit FTE SMBOCN 1 to logic 1 enables the timer in SMBOCR When SCL goes high the timer in SMBOCR counts up A timer overflow indicates a free bus timeout if SMBus0 is waiting to generate a START it will do so after this timeout The bus free period should be less than 50 us see Figure 20 9 SMBusO Clock Rate Register When the TOE bit in SMBOCN is set to logic 1 Timer 4 is used to detect SCL low timeouts If Timer 4 is enabled see Section 24 2 Timer 2 Timer 3 and Timer 4 on page 295 Timer 4 is forced to reload when SCL is high and forced to count when SCL is low With Timer 4 enabled and configured to overflow after 242 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 25 ms and TOE set a Timer 4 overflow indicates a SCL low timeout the Timer 4 interrupt service routine can then be used to reset SMBus0 communication in the event of an SCL low timeout Figure 20 8 SMBOCN SMBus0 Control Register R R W R W R W R W R W R W R W Reset Value BUSY ENSMB STA STO SI AA FTE TOE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Ad PM SFR Address 0xCO SFR Page 0 Bit7 BUSY Busy Status Flag 0 SMBusO is free 1 SMBusO is busy Bit6 ENSMB SMBus Enable This bit enables disables the SMBus serial interface 0 SMBusO disabled 1 SMBusO enabled Bit5 STA SMBus Start Flag 0 No START condition is transmitted 1 When operating as a master a START conditio
376. tial data with ADC2LTH ADC2LTL 0x0040 644 and ADC2GTH ADC2GTH OxFFFF 19 In differential mode the measurable voltage between the input pins is between VREF and VREF 511 512 Output codes are rep resented as 10 bit 2 s complement signed integers In the left example an AD2WINT interrupt will be gen erated if the ADC2 conversion word ADC2H ADC2L is within the range defined by ADC2GTH ADC2GTL and ADC2LTH ADC2LTL if OXFFFF 1d lt ADC2H ADC2L lt 0x0040 64d In the right example an AD2WINT interrupt will be generated if the ADC2 conversion word is outside of the range defined by the ADC2GT and ADC2LT registers if ADC2H ADC2L lt OxFFFF 1d or ADC2H ADC2L gt 0x0040 64d Figure 7 18 shows an example using left justified data with the same comparison values Figure 7 17 ADC Window Compare Example Right Justified Differential Data ADC2H ADC2L ADC2H ADC2L Input Voltage Input Voltage P1 x P1 y P1 x P1 y VREF x 511 512 0x01FF VREF x 511 512 AD2WINT not affected AD2WINT I 0x0041 VREF x 64 512 0x0040 I ADC2LTH ADC2LTL VREF x 64 512 0x0040 4 ADC2GTH ADC2GTL 0 00 AD2WINT 1 AD2WINT 0x0000 not affected VREF x 1 512 OxFFFF ADC2GTH ADC2GTL OxFFFF I ADC2LTH ADC2LTL OxFFFE AD2WINT AD2WINT 1 not affected VREF 0x0200 Figure 7 18 ADC Window
377. time When the UARTI interrupt is enabled setting this bit to 1 causes the CPU to vector to the interrupt service routine This bit must be cleared manually by soft ware 282 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 23 8 SBUF1 Serial UART1 Port Data Buffer Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit2 Bit1 Bito SFR Address 0x99 SFR Page 1 Bits7 0 SBUF1 7 0 Serial Data Buffer Bits 7 0 MSB LSB This SFR accesses two registers a transmit shift register and a receive latch register When data is written to SBUF1 it goes to the transmit shift register and is held for serial transmis sion Writing a byte to SBUF1 is what initiates the transmission A read SBUF1 returns the contents of the receive latch 3 Rev 1 2 283 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 23 1 Timer Settings for Standard Baud Rates Using the Internal Oscillator 230400 SYSCLK 115200 SYSCLK 57600 A SYSCLK 28800 SYSCLK 4 14400 SYSCLK 12 9600 SYSCLK 12 2400 5 SYSCLK 48 1200 SYSCLK 48 Dont care O O O O O TSCA1 SCAO and bit definitions can be found in Section 24 1 Table 23 2 Timer Settings for Standard Baud Rates Using an External Oscillator 230400 115200 SYSCLK 57600 SYSCLK 28800 s SYSCLK 4 14400
378. tion and use of the Mes sage Handler Registers 19 2 4 CIP 51 MCU Special Function Registers C8051F060 1 2 3 peripherals are modified monitored and controlled using Special Function Registers SFRs Most of the CAN Controller registers cannot be accessed directly using the SFRs Three of the CAN Controller s registers may be accessed directly with SFRs All other CAN Controller registers are accessed indirectly using three CIP 51 MCU SFRs the CAN Data Registers CANODATH and CANO DATL and CAN Address Register CANOADR In this way there are a total of five CAN registers used to configure and run the CAN Controller 19 2 5 Using CANOADR CANODATH and CANDATL To Access CAN Registers Each CAN Controller Register has an index number see Table below The CAN register address space is 128 words 256 bytes A CAN register is accessed via the CAN Data Registers CANODATH and CANO DATL when a CAN register s index number is placed into the CAN Address Register CANOADR For example if the Bit Timing Register is to be configured with a new value CANOADR is loaded with 0x03 The low byte of the desired value is accessed using CANODATL and the high byte of the bit timing register is accessed using CANODATH CANODATL is bit addressable for convenience To load the value 0x2304 into the Bit Timing Register CANOADR 0x03 Load Bit Timing Register s index Table 18 1 CANODATH 0x23 Move the upper byte into data reg high byte CANOD
379. transitions on external input pin CP RLn Capture Reload Select This bit selects whether the Timer functions in capture or auto reload mode 0 Timer is in Auto Reload Mode 1 Timer is in Capture Mode e Rev 1 2 299 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 24 14 TMRnCF Timer 2 3 and 4 Configuration Registers R W R W R W R W R W Reset Value TnM1 TnMO TOGn DCENn 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address TMR2CF 0 9 TMR3CF 0 9 TMR4CF 0 9 SFR Page TMR2CF page 0 TMR3CF page 1 TMR4CF page 2 Bit7 5 Reserved Bit4 3 TnM1 and 0 Timer Clock Mode Select Bits Bits used to select the Timer clock source The sources can be the System Clock SYSCLK SYSCLK divided by 2 or 12 or an external clock signal routed to Tn port pin divided by 8 Clock source is selected as follows 00 SYSCLK 12 01 SYSCLK 10 EXTERNAL CLOCK 8 11 SYSCLK 2 Bit2 TOGn Toggle output state bit When timer is used to toggle a port pin this bit can be used to read the state of the output or can be written to in order to force the state of the output TnOE Timer output enable bit This bit enables the timer to output a 50 duty cycle output to the timer s assigned external port pin NOTE A timer is configured for Square Wave Output as follows CP RLn 0 C In 0 1 Load RCAPnH RCAPnL See Toggle Mode Square Wave Frequenc
380. transmitting device will read a not acknowledge NACK which is a high SDA during a high SCL 236 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 The direction bit R W occupies the least significant bit position of the address The direction bit is set to logic 1 to indicate a READ operation and cleared to logic 0 to indicate a WRITE operation All transactions are initiated by a master with one or more addressed slave devices as the target The master generates the START condition and then transmits the slave address and direction bit If the trans action is a WRITE operation from the master to the slave the master transmits the data a byte at a time waiting for an ACK from the slave at the end of each byte For READ operations the slave transmits the data waiting for an ACK from the master at the end of each byte At the end of the data transfer the master generates a STOP condition to terminate the transaction and free the bus Figure 20 3 illustrates a typical SMBus transaction Figure 20 3 SMBus Transaction SDA SLA6 51 5 0 R W D7 06 0 START Slave Address R W ACK Data Byte NACK STOP 20 2 1 Arbitration A master may start a transfer only if the bus is free The bus is free after a STOP condition or after the SCL and SDA lines remain high for a specified time See Section 20 2 4 In the event that two or more devices attempt to begin a transfer at the same time an a
381. ty an overflow warning flag is generated If a second conversion data word becomes available before the DMA s data buffer is written to XRAM the data in the ADC s data regis ters is over written with the new data word and a data overflow error flag is generated Rev 1 2 79 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 6 4 DMAOCN DMAO Control Register SFR Page 3 SFR Address 0 08 bit addressable R W R W R W R W R W R W R W R W Reset Value DMAOEN DMAOINT DMAOMD DMAODE1 DMAODEO DMAODOE DMA0DO1 DMAODOO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Bit 7 Enable Write 0 Stop DMAO Operations 1 Begin DMAO Operations Read 0 DMAO is ldle 1 DMAO Operation is in Progress Bit 6 DMAOINT DMAO Operations Complete Flag 0 DMAO has not completed all operations 1 DMAO operations are complete This bit must be cleared by software Bit 5 DMAOMD DMAO Mode Select 0 DMAO will operate in Mode O 1 DMAO will operate in Mode 1 Bit 4 DMAODE1 ADC1 Data Overflow Error Flag 0 ADC1 Data Overflow has not occured 1 ADC1 Data Overflow has occured data from ADC1 has been lost This bit must be cleared by software Bit 3 DMAODEO ADCO Data Overflow Error Flag 0 ADCO Data Overflow has not occured 1 ADCO Data Overflow has occured and data from ADCO has been lost This bit must be cleared by software Bit 2 DMAODOE Data Overflow Warni
382. uction The SAMPLE instruction is accessed via the IR The Boundary DR provides observability and presetting of the scan path latches 26 1 3 BYPASS Instruction The BYPASS instruction is accessed via the IR It provides access to the standard JTAG Bypass data reg ister 26 1 4 IDCODE Instruction The IDCODE instruction is accessed via the IR It provides access to the 32 bit Device ID register Figure 26 2 DEVICEID JTAG Device ID Register Reset Value Version Part Number Manufacturer ID 1 0xn0006243 Bit31 Bit28 Bit27 Bit12 Bit11 Bit1 Bito Version 0000b Part Number 0000 0000 0000 0110b C8051F060 1 2 3 4 5 6 7 Manufacturer ID 0010 0100 001b Silicon Labs 5 1 2 321 SILICON LABS C8051F060 1 2 3 4 5 6 7 26 2 Flash Programming Commands The Flash memory can be programmed directly over the JTAG interface using the Flash Control Flash Data Flash Address and Flash Scale registers These Indirect Data Registers are accessed via the JTAG Instruction Register Read and write operations on indirect data registers are performed by first setting the appropriate DR address in the IR register Each read or write is then initiated by writing the appropriate Indirect Operation Code IndOpCode to the selected data register Incoming commands to this register have the following format 19 18 17 0 IndOpCode WriteData IndOpCode These bit set the operation to perform accordi
383. ue 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address OXBF SFR Page 1 Bits 7 0 ADC1 Data Word High Order Bits Figure 5 17 ADC1L ADC1 Data Word LSB Register R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address OXBE SFR Page 1 Bits 7 0 ADC1 Data Word Low Order Bits Figure 5 18 ADC1 Data Word Example 16 bit ADC1 Data Word appears in the ADC1 Data Word Registers as follows Example ADC1 Data Word Conversion Map AIN1 Input in Single Ended Mode AMX1SL 0x00 AINT AINTG Volts VREF 65535 65536 OxFFFF VREF 2 0 8000 VREF 32767 65536 Ox7FFF 0 0x0000 Gain Vinx GREF n 16 For differential mode the differential data word appears ADCOH ADCOL The single ended ADC1 results are always present in ADC1H ADC1L regardless of the operating mode e Rev 1 2 65 SILICON LABS C8051F060 1 2 3 4 5 6 7 5 4 Calibration The ADCs are calibrated for linearity offset and gain in production ADCO and ADC1 can also be inde pendently calibrated for each of these parameters in system Calibrations are initiated using bits in the ADCO or ADC1 Configuration Register The calibration coefficients can be accessed using the ADC Cali bration Pointer Register ADCOCPT Figure 5 22 and the ADC Calibration Coefficient Register
384. ull speed in circuit debug sup port using the production part installed in the end application via the four pin JTAG I F Silicon Labs debug system supports inspection and modification of memory and registers breakpoints and single stepping No additional target RAM program memory or communications channels are required All the digital and analog peripherals are functional and work correctly remain synchronized while debugging The Watch dog Timer WDT is disabled when the MCU is halted during single stepping or at a breakpoint The C8051F060DK is a development kit with all the hardware and software necessary to develop applica tion code and perform in circuit debug with each MCU the C8051F06x family Each kit includes develop ment software for the PC a Serial Adapter for connection to JTAG and a target application board with a C8051F060 installed Serial cables and wall mount power supply are also included e Rev 1 2 325 SILICON LABS C8051F060 1 2 3 4 5 6 7 326 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Document Change List Revision 1 1 to Revision 1 2 Added four part numbers C8051F064 C8051F065 C8051F066 and C8051F067 Modified all sections to describe functionality of the four new parts e Revised and expanded Flash Chapter with clearer descriptions of Flash security features e UARTO Chapter Section 22 3 FEO in register SCONO changed to FEO in register SSTAO e UAR
385. unter Status High Byte page 85 DMAOCSL OxFB 3 DMAO Repeat Counter Status Low Byte page 85 DMAOCTH OxFA 3 DMAO Repeat Counter Limit High Byte page 85 DMAOCTL OxF9 3 DMAO Repeat Counter Limit Low Byte page 85 DMAODAH OxDA 3 DMAO Data Address Beginning High Byte page 84 DMAODAL 0 09 3 Data Address Beginning Low Byte page 84 DMAODSH OxDC 3 DMAO Data Address Pointer High Byte page 84 DMAODSL OxDB 3 DMAO Data Address Pointer Low Byte page 84 DMAOIDT OxDE 3 Instruction Write Data page 82 DMAOIPT OxDD 3 Instruction Write Address page 82 DMAOISW OxFE 3 DMAO Instruction Status page 83 DPH 0x83 All Pages Data Pointer High page 148 DPL 0x82 All Pages Data Pointer Low page 148 EIE1 OxE6 All Pages Extended Interrupt Enable 1 page 156 EIE2 OxE7 All Pages Extended Interrupt Enable 2 page 157 EIP1 OxF6 All Pages Extended Interrupt Priority 1 page 158 EIP2 OxF7 All Pages Extended Interrupt Priority 2 page 159 EMIOCF OxA3 0 EMIF Configuration page 189 EMIOCN 2 0 Control page 189 EMIOTC OxA1 0 EMIF Timing Control page 1947 FLACL 0 7 Flash Access Limit page 182 FLSCL 0 7 0 Flash Scale page 184 IE OxA8 All Pages Interrupt Enable page 154 IP OxB8 All Pages Interrupt Priority page 155 OSCICL 0x8B F Internal Oscillator Calibration page 172 OSCICN 0x8A F Internal Oscillator Control page 172 OSCXCN 0 8 External Oscillator Control page 174 PO 0x80 All Pages Port 0 Latch page 214 POMDOUT 0 4 Po
386. uring the execution of the MOVX instruction the External Memory Interface will explicitly disable the driv ers on all Port pins that are acting as Inputs Data 7 0 during a READ operation for example The Output mode of the Port pins whether the pin is configured as Open Drain or Push Pull is unaffected by the External Memory Interface operation and remains controlled by the PnMDOUT registers See Section 18 Port Input Output on page 203 for more information about Port output mode configuration 188 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 17 1 EMIOCN External Memory Interface Control R W R W R W R W R W R W R W R W Reset Value PGSEL7 PGSEL6 PGSEL5 PGSEL4 PGSEL3 PGSEL2 PGSEL1 PGSELO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xA2 SFR Page 0 Bits7 0 PGSEL 7 0 XRAM Page Select Bits The XRAM Page Select Bits provide the high byte of the 16 bit external data memory address when using an 8 bit MOVX command effectively selecting a 256 byte page of RAM 0x00 0x0000 to 0x00FF 0x01 0x0100 to 0x01 FF OxFE OxFEOO to OxFEFF OxFF OxFFOO to OxFFFF Figure 17 2 EMIOCF External Memory Configuration R W R W R W R W R W R W R W R W Reset Value PRTSEL EMD2 EMD1 EMDO EALE1 EALEO 00000011 Bit7 Bit6 5 Bit4 Bit3 Bit2 Bit0 SFR Address 0xA3 SFR 0 Bits7 6 Unused Read 00b Write don
387. utoincrement upon write to CANODATL 0x24 IF2 Arbitration 1 0x0000 CANOADR autoincrement upon write to CANODATL 0x25 IF2 Arbitration 2 0x0000 CANOADR autoincrement upon write to CANODATL 0x26 IF2 Message Control 0x0000 CANOADR autoincrement upon write to CANODATL 0x27 IF2 Data A1 0x0000 CANOADR autoincrement upon write to CANODATL 0x28 IF2 Data A2 0x0000 CANOADR autoincrement upon write to CANODATL 0x29 IF2 Data B1 0x0000 CANOADR autoincrement upon write to CANODATL 2 IF2 Data B2 0x0000 CANOADR autoincrement upon write to CANODATL 0x40 Transmission Request 1 0x0000 Transmission request flags for message objects read only 0x41 Transmission Request 2 0x0000 Transmission request flags for message objects read only 0x48 New Data 1 0x0000 New Data flags for message objects read only 0x49 New Data 2 0x0000 New Data flags for message objects read only 0x50 Interrupt Pending 1 0x0000 Interrupt pending flags for message objects read only 0x51 Interrupt Pending 2 0x0000 Interrupt pending flags for message objects read only 0x58 Message Valid 1 0x0000 Message valid flags for message objects read only 230 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Table 19 1 CAN Register Index and Reset Values Continued CAN Register Reset I dex Register name Value Notes 0x59 Message Valid 2 0x0000 Message valid flags for message objects read only Figure 19 3 CANODATH CAN Da
388. w many system clocks from 1 to 16 are used for each conversion clock 5 3 1 Starting a Conversion For ADCO conversions can be initiated in one of four ways depending on the programmed states of the ADCO Start of Conversion Mode bits ADOCM1 ADOCMO in ADCOCN For ADCO conversions may be ini tiated by Writing a 1 to the ADOBUSY bit of ADCOCN A Timer 3 overflow i e timed continuous conversions A rising edge detected on the external ADC convert start signal CNVSTRO 4 A Timer 2 overflow i e timed continuous conversions ADC1 conversions be initiated five different ways according to the ADC1 Start of Conversion Mode bits AD1CM2 AD1CMO in ADC1CN For ADC1 conversions may be initiated by Writing a 1 to the AD1BUSY bit of ADC1CN A Timer 3 overflow i e timed continuous conversions A rising edge detected on the external ADC convert start signal CNVSTR1 A Timer 2 overflow i e timed continuous conversions Writing a 1 to the ADOBUSY bit of ADCOCN OF Nr The ADnBUSY bit is set to logic 1 during conversion and restored to logic 0 when conversion is complete The falling edge of ADnBUSY triggers an interrupt when enabled and sets the ADnINT interrupt flag ADCnCN 5 In single ended mode the converted data for ADCn is available in the ADCn data word MSB and LSB registers ADCnH ADCnL In differential mode the converted data combined from ADCO and ADC1 is available in th
389. when the SPI operates in 4 wire mode as a slave that is not selected When acting as a slave in 3 wire mode MISO is always driven by the MSB of the shift register 21 1 3 Serial Clock SCK The serial clock SCK signal is an output from the master device and an input to slave devices It is used to synchronize the transfer of data between the master and slave on the MOSI and MISO lines SPIO gen erates this signal when operating as a master The SCK signal is ignored by a SPI slave when the slave is not selected NSS 1 in 4 wire slave mode 21 1 4 Slave Select NSS The function of the slave select NSS signal is dependent on the setting of the NSSMD1 and NSSMDO bits in the SPIOCN register There are three possible modes that can be selected with these bits 1 NSSMDf 1 0 00 3 Wire Master or 3 Wire Slave Mode SPIO operates in 3 wire mode and NSS is disabled When operating as a slave device SPIO is always selected in 3 wire mode Since no select signal is present SPIO must be the only slave on the bus in 3 wire mode This is intended for point to point communication between a master and one slave 2 NSSMD 1 0 01 4 Wire Slave or Multi Master Mode SPIO operates in 4 wire mode and NSS is enabled as an input When operating as a slave NSS selects the SPIO device When operating as a master a 1 to 0 transition of the NSS signal disables the master function of SPIO so that multiple master devices can be used on the same SPI bus
390. while Timer 0 is in Mode 3 set the Timer 1 Mode as 0 1 or 2 To disable Timer 1 configure it for Mode 3 Figure 24 3 TO Mode 3 Block Diagram Pre scaled Clock THO Interrupt 8 bits Interrupt SYSCLK Tom TLO 8 bits TRO Crossbar GATE0 m INTO w EI amp 290 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 24 4 TCON Timer Control Register R W Reset Value ITO 00000000 Bit Addressable SFR Address 0x88 SFR Page 0 Bito TF1 Timer 1 Overflow Flag Set by hardware when Timer 1 overflows This flag can be cleared by software but is auto matically cleared when the CPU vectors to the Timer 1 interrupt service routine 0 No Timer 1 overflow detected 1 Timer 1 has overflowed TR1 Timer 1 Run Control 0 Timer 1 disabled 1 Timer 1 enabled Timer 0 Overflow Flag Set by hardware when Timer 0 overflows This flag can be cleared by software but is auto matically cleared when the CPU vectors to the Timer 0 interrupt service routine 0 No Timer 0 overflow detected 1 Timer 0 has overflowed TRO Timer 0 Run Control 0 Timer 0 disabled 1 Timer 0 enabled IE1 External Interrupt 1 This flag is set by hardware when an edge level of type defined by IT1 is detected It can be cleared by software but is
391. x1007F Scrachpad Memory Upper 128 RAM Special Function 0 10000 data only 0x80 indirect Addressing Only 62081818 OxFFFF 0 7 Direct Addressing Only 4 OxFCOO Direct and Indirect 0x30 Addressing Up To Ox2F 256 SFR Pages OxFBFF Lower 128 RAM FLASH UE Direct and Indirect In System Programmable 0x00 Addressing in 512 Byte Sectors 0 0000 8051 066 7 EXTERNAL DATA ADDRESS SPACE 0 1007 Scrachpad Memory OxFFFF 0 10000 data only OxFFFF RESERVED 0x8000 Ox7FFF FLASH 0 1000 In System Programmable Bytes in 512 Byte Sectors accessableusingMOVX 0x0000 0x0000 instruction 13 2 1 Program Memory The CIP 51 has a 64 k byte program memory space The C8051F060 1 2 3 4 5 devices implement 64 k bytes of this program memory space as in system re programmable Flash memory organized in a contig uous block from addresses 0 0000 to 0xFFFF Note 1024 bytes 0xFC00 to OxFFFF of this memory are reserved and are not available for user program storage The C8051F066 7 implement 32 k bytes of this program memory space as in system re programmable Flash memory organized in a contiguous block from addresses 0x0000 to 0x7FFF Program memory is normally assumed to be read only using the MOVC instruction However the CIP 51 can write to program memory by enabling Flash writes and using the MOVX instruction This feature pro vides a mechanism for the CIP 51
392. y on page 298 Configure Port Pin to output squarewave See Section 18 Port Input Output on page 203 0 Output of toggle mode not available at Timers s assigned port pin 1 Output of toggle mode available at Timers s assigned port pin Decrement Enable Bit This bit enables the timer to count up or down as determined by the state of 0 Timer will count up regardless of the state of TnEX 1 Timer will count up or down depending on the state of as follows if TnEX 0 the timer counts DOWN if TREX 1 the timer counts UP 300 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 Figure 24 15 RCAPnL Timer 2 3 and 4 Capture Register Low Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address RCAP2L 0xCA RCAP3L 0xCA RCAP4L SFR Page RCAP2L page 0 RCAP3L page 1 RCAP4L page 2 Bits 7 0 RCAP2 3 and 4L Timer 2 3 and 4 Capture Register Low Byte The RCAP2 3 and 4L register captures the low byte of Timer 2 3 and 4 when Timer 2 3 and 4 is configured in capture mode When Timer 2 3 and 4 is configured in auto reload mode it holds the low byte of the reload value Figure 24 16 RCAPnH Timer 2 3 and 4 Capture Register High Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito
393. y 2 or 4 after each data write by the DMA interface 6 4 Instruction Execution in Mode 0 When the DMA interface begins an operation cycle the DMA Instruction Status Register DMAOISW Figure 6 9 is loaded with the address contained in the DMA Instruction Boundary Register DMAOBND Figure 6 8 The instruction is fetched from the Instruction Buffer and the DMA Control Logic waits for data from the appropriate ADC s The DMA will execute each instruction once and then increment DMAOISW to the next instruction address When the current DMA instruction is an End of Operation instruction the Instruction Status Register is reset to the Instruction Boundary Register If the Continuous Conversion bit bit 7 CCNV in the End of Operation instruction word is set to 1 the Repeat Counter is ignored and the will continue to execute instructions indefinitely When is set to 0 the Repeat Counter regis ters DMAOCSH and DMAOCSL is decremented and the DMA will continue to execute instructions until the Repeat Counter reaches 0x0000 The Repeat Counter is initialized with the Repeat Counter Limit value registers DMAOCTH and DMAOCTL at the beginning of the DMA operation An example of Mode 0 operation is shown in Figure 6 2 Figure 6 2 DMA Mode 0 Operation XRAM INSTRUCTION DMAOCSH L 0x0000 BUFFER 64 Bytes DMAOCSH L DMAOCTH L 1 Ox3F 0x03 00000000 0x02 0x01 DMAOBND 0x00 DMAOCSH L
394. y hardware and generates a SPIO interrupt to indicate a write to the SPIO data register was attempted while a data transfer was in progress It must be cleared by software Bit 5 MODF Mode Fault Flag This bit is set to logic 1 by hardware and generates a SPIO interrupt when a master mode collision is detected NSS is low MSTEN 1 and NSSMD 1 0 01 This bit is not auto matically cleared by hardware It must be cleared by software Bit 4 RXOVRN Receive Overrun Flag Slave Mode only This bit is set to logic 1 by hardware and generates a SPIO interrupt when the receive buf fer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPIO shift register This bit is not automatically cleared by hardware It must be cleared by software Bits 3 2 NSSMD1 NSSMDO Slave Select Mode Selects between the following NSS operation modes See Section 21 2 SPIO Master Mode Operation on page 253 and Section 21 3 SPIO Slave Mode Operation on page 255 00 3 Wire Slave or 3 wire Master Mode NSS signal is not routed to a port pin 01 4 Wire Slave or Multi Master Mode Default NSS is always an input to the device 1x 4 Wire Single Master Mode NSS signal is mapped as an output from the device and will assume the value of NSSMDO Bit 1 TXBMT Transmit Buffer Empty This bit will be set to logic 0 when new data has been written to the transmit buffer When data in the transmit
395. y setting the EA bit IE 7 and the EPCAO bit in EIE1 to logic 1 Clearing the CIDL bit in the PCAOMD register allows the PCA to continue normal operation while the CPU is in Idle mode Table 25 1 PCA Timebase Input Options CPS2 CPS1 CPSO Timebase 0 0 0 System clock divided by 12 0 0 1 System clock divided by 4 0 1 0 Timer 0 overflow 0 1 1 High to low transitions max rate system clock divided by 4 1 0 0 System clock 1 0 1 External oscillator source divided by 8 synchronized with sys tem clock Figure 25 2 PCA Counter Timer Block Diagram IDLE PCAOMD PCAOCN C C C C C C C SISISIF F F F F F F L E C 211 0 5 4 312 1 0 rosFR Bus K PCA0L mum read Snapshot Register SYSCLK 12 SYSCLK 4 Timer 0 Overflow 0 o e PCAOH PCAOL Overflow PCA Interrupt System SYSCLK CF External Clock 8 gt To PCA Modules 304 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 25 2 Capture Compare Modules Each module can be configured to operate independently in one of six operation modes Edge triggered Capture Software Timer High Speed Output Frequency Output 8 Bit Pulse Width Modulator or 16 Bit Pulse Width Modulator Each module has Special Function Reg
396. y the TF2 flag Bit4 ESO Enable UARTO Interrupt This bit sets the masking of the UARTO interrupt 0 Disable UARTO interrupt 1 Enable UARTO interrupt Bit3 ET1 Enable Timer 1 Interrupt This bit sets the masking of the Timer 1 interrupt 0 Disable all Timer 1 interrupt 1 Enable interrupt requests generated by the TF1 flag Bit2 EX1 Enable External Interrupt 1 This bit sets the masking of external interrupt 1 0 Disable external interrupt 1 1 Enable interrupt requests generated by the INT1 pin Bit1 ETO Enable Timer 0 Interrupt This bit sets the masking of the Timer 0 interrupt 0 Disable all Timer 0 interrupt 1 Enable interrupt requests generated by the TFO flag Bito Enable External Interrupt 0 This bit sets the masking of external interrupt 0 0 Disable external interrupt 0 1 Enable interrupt requests generated by the INTO pin 154 Rev 1 2 SILICON LABS C8051F060 1 2 3 4 5 6 7 R W Figure 13 20 IP Interrupt Priority R W R W R W R W R W R W R W Reset Value PT2 PSO PT1 1 PX0 11000000 Bit7 Bits7 6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit Addressable SFR Address 0xB8 SFR Page All Pages Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito UNUSED Read 11b Write don t care PT2 Timer 2 Interrupt Priority Control This bit sets the priority of the Timer 2 interrupt 0 Timer 2 interrupt set to low priority level 1 Ti

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