USBS6 is a low-cost multilayer PCB with SPARTAN
Contents
1. i T 00000000000 st CA poo L s N Ooo ml EJ alo x 4 0000 000000 10000 10000 1 16 44 PR 1 5 55 94 45 100 Figure 21 USBS6 mechanical dimensions in mm UG107 v1 1 April 07 2014 www cesys com 67 CESYS Copyright Notice Copyright Notice This file contains confidential and proprietary information of Cesys GmbH and is protected under international copyright and other intellectual property laws Disclaimer This disclaimer is not a license and does not grant any rights to the materials distributed herewith Except as otherwise provided in a valid license issued to you by Cesys and to the maximum extent permitted by applicable law 1 THESE MATERIALS ARE MADE AVAILABLE AS IS AND WITH ALL FAULTS AND CESYS HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS EXPRESS IMPLIED OR STATUTORY INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY NON INFRINGEMENT OR FITNESS FOR ANY PARTICULAR PURPOSE and 2 Cesys shall not be liable whether in contract or tort including negligence or under any other2. 00200000 99 55 66 Banki gt 0 00100004 00200008 30 00 80 01 00 00 00 07 00200010 30 01 60 01 00 00 00 60 00000000 00200018 30 01 20 01 00 00 31 5 00200020 30 01 cO 01 01 c2 20 93 00200028 30 00 0 01 00 00 00 00 wwe 00200030 30 00 80 01 00 00 00 09 00200038 30 00 20 01 00 00 00 00 Lo 00200040 30 00 80 01 00 00 00 01 00200048 30 00 40 00 50 01 14 9a Command gt 0x00280000 00000000 Dec Lo g HHAH 3 0668 8 HHAH 8 88 5 Figure 18 Content panel Register entry A register entry can be used to communicate with a 32 bit register inside the FPGA In UDKLab a register consists of the following values Address Info text The visual representation of one register can be seen in the following image UG107 v1 1 April 07 2014 www cesys com 57 CESYS Software GPIO BankO gt 00100000 Hex 00000000 Dec 0 4 gl Red write Auto Figure 19 Register panel Th
3. 17 11 FPGA Suspend COD le CtOF a ened 17 2 aun Cutan 17 EPGA 18 Cypress 2 LP and USB 4 2 44 sea sea 18 Clocking FPGA 19 EX 2 EPGA Slave FIFO COnDfFieCcbiOri D DUO UA E ETUR OC 19 Introduction to Example FPGA designs see era 20 FPGA source code copyright inforrnatlori rr e X e X Y ve XR 22 FPGA Source code Sont RES 22 Disclaimer of Warranty PAGE Ea 22 DESIGN USHSO SOC suspans vais 23 Software Pseudo Code Example ka oe Re Cea LAUR ER RUNE 27 85 25 5 un e FE Vau e REN UEM Rd a DER NENNEN 27 Design 05566
4. MP 29 30 Changes previous c eoi Sede 30 06107 v1 1 April 07 2014 www cesys com 70 CESYS Table of contents lv aw been a E PUR 31 Mis IRIURE 31 TELE TT 31 Build dem 31 33 5 iem ds ra nea D ahaa M E PUDE DIA 33 Driver 33 Build 36 USE ARIS AE EEE 37 T 37 PT 37 Ade quada NES 38 APL FUNCUONS IN Aeta nnb d 38 Error handling ERA pA Sx UI Dan EP Rai S 38
5. 00000030 00 00 00 00 00 00 00 00 00000038 00 00 00 00 00 00 00 00 cy 00000040 00 00 00 00 00 00 00 00 lo A 00000048 00 00 00 00 00 00 00 00 GPIO Bank1 gt 0x0010000c EU Flash Contents gt 0x00200000 Hex 00000000 Dec 0 Address Range 0x00200000 0x0027ffff D Read Write 512 0 MB Alignment 4 byte gn Eee SY qo E xw 00200000 ff ff aa 99 55 66 00200008 30 00 80 01 00 00 00 07 GPIO Bank1 gt 0 00100004 00200010 30 01 60 01 00 00 00 60 a Hex Dec 15728640 00200018 30 01 20 01 00 00 31 5 00200020 30 01 0 01 01 2 20 93 00200028 30 00 01 00 00 00 00 Write 00200030 30 00 80 01 00 00 00 09 lr I 11 v V Y F 00200038 30 00 20 01 00 00 00 00 jis ili 17 00200040 30 00 80 01 00 00 00 01 24 00200048 30 00 40 00 50 01 14 Flash Command gt 0x00280000 00000000 Dec 0 t3 Hi DAL Lo AE rj Figure 12 UDKLab Main Screen Using UDKLab After starting UDKLab most of the UI components are disabled They will be enabled at the point they make sense A
6. ge B oe 2 _ H m a5 a USB2 0 Pm m AA mi Bm Tee m 4 desig ee TMS 9r Figure 2 USBS6 Top View UG107 v1 1 April 07 2014 www cesys com 5 CESYS Powering Powering USBS6 can be used bus powered see SW2 below without the need of any external power supply other than USB In this mode 3 sourcing capability is limited due to the fact that USB power supply current is limited depending on which system is used as host In bus powered mode at first only FX2 is enabled After successful connection to the operating system the further power on sequencing behavior depends on UDK configuration Until the release of UDK2 0 only the API could enable power on sequencing therefore after plugging an USB cable it also was necessary to start an application like cesys Monitor before the FPGA and other devices turned on With v2 0 and upcoming releases of UDK framework the user can decide which power on behavior fits best Power on sequencing through API or as soon as USB cable is plugged in Default mode is API controlled Self powered Connect 5V power supply to VG 96pin 3 3V 2A external expansion connector J3 PINS 1 B1 und C1 Minimum required supply current 400mA
7. FX2_FDO Ril 16 Bit bidirectional FIFO data bus FD 0 15 FX2_FD1 114 FX2_FD2 14 FX2_FD3 U5 FX2_FD4 V5 FX2_FD5 R3 FX2_FD6 T3 FX2_FD7 R5 FX2_FD8 5 FX2_FD9 P6 FX2_FD10 12 FX2_FD11 U13 FX2_FD12 V13 FX2 FD13 U10 FX2_FD14 R8 FX2 FD15 T8 External memory USBS6 offers the opportunity to use various external memory architectures in one s FPGA design With Micron Technology MT46H64M16LFCK 5 up to 1Gbit of high speed low power DDR SDRAM is available The integrated memory controller of Spartan 6 devices enables system designers to implement state of the art memory interfaces without the need to develop a whole memory controller Soft IP all on their own Some examples how to implement LPDDR with Spartan 6 are available in FPGA design UG107 v1 1 April 07 2014 www cesys com 9 CESYS Powering Signal Name FPGA IO Comment 1 8 12 1 9 G13 MCB1 A10 E16 MCB1 A11 G14 MCB1 A12 D18 MCB1 A13 C17 1 BAO H13 Bank address inputs BAO and BA1 define to which bank an ACTIVE READ WRITE or PRECHARGE command is being applied BAO and BA1 also determine which mode register is loaded during a LOAD MODE MEBI E REGISTER command MCB1 RAS n K15 Command inputs RAS CAS and WE along with CS define the CAS n K16 command being entered WE n K12 1 CS n 1 17 Clock enable HIGH activates LOW deactivates
8. If USBS6 is used self powered see SW2 above an external 5V power supply must be connected to J3 A1 B1 C1 In this mode all onboard voltages are enabled as soon as an external power supply is applied IO on J3 and J4 are powered through VCCO on As default VCCO is connected to VCCO VCCAUX regulator to enable 3 3V signaling levels on external expansion connectors J3 and J4 In self powered mode maximum current available for powering external hardware on J3 A3 B3 C3 mainly depends on the external power supply but a maximum of 2A should not UG107 v1 1 April 07 2014 WWW Cesys com 6 CESYS Powering be exceeded If other signaling levels or higher current output are needed an additional synchronous buck regulator can be populated to independently supply 10 is strongly recommended to check XILINX UG381 about Spartan 6 FPGA SelectlO Signal Standards on XILINX website Configuration Configuration of USBS6 can be accomplished in several ways JTAG SPI Flash or USB The default configuration mode is booting from SPI Flash After powering on the FPGA USBS6 always tries to configure itself from the attached Flash using Master mode If no valid design is stored in the SPI Flash the FPGA has to be configured via JTAG or USB JTAG configuration is supported at any time after the FPGA is properly powered on For downloading designs via ISE WebPACK from XILINX
9. 17 VG96 IO39 B17 K3 VG96 IO40 C17 L6 VG96 IO41 15 L5 VG96 IO33 B15 K5 VG96 1034 C15 E3 VG96 IO35 A13 C2 VG96 IO27 B13 Ci VG96 IO28 C13 G3 VG96 IO29 Aii F2 VG96 IO21 B11 Fi VG96 IO22 C11 VG96_1023 AQ K2 VG96 IO15 B9 K1 VG96 IO16 C9 M3 VG96 IO17 A7 N2 VG96 109 B7 1 VG96 1010 C7 N4 VG96 1011 5 T2 VG96 IO3 B5 Ti VG96 104 C5 P4 VG96 IO5 A3 B3 es VCCO IO VCCO_IO Al 5 0 EXT 1 5 0V_EXT 5 0 EXT 24 IDC 2x25 Pin external expansion connector Figure 6 IDC 2x25 Pin external expansion connector J4 UG107 v1 1 April 07 2014 www cesys com 15 CESYS Powering ADD 100 i ADD IO1 7 GND 8 GND 11 B3 ADD 106 12 ADD 107 15 6 ADD 1010 16 ADD 1011 19 B8 ADD_1012 20 ADD 1013 GND 724 GND 27 12 ADD 1018 28 12 ADD 1019 31 16 ADD 1022 32 16 ADD 1023 35 10 ADD IO24 36 A10 ADD 1025 39 GND 40 GND 43 D14 ADD IO30 44 14 ADD 1031 47 04 HSWAPEN 48 GND GCLK It is strongly recommended to check the appropriate data sheets of SPARTAN 6 devices about special functionality IO like GCLK HSWAPEN UG107 v1 1 April 07 2014 www cesys com 16 CESYS Powering Suspend and Awake SPARTAN 6 FPGA devices support an advanced static power management feature which reduces power consumption while retaining the FPGA s configuration data and maintaining the des
10. USBAVF devices one of two areas can be chosen Write to flash Stage Figure 15 Flash design to device Projects Device communication is placed into a small project management This reduces the actions from session to session and can be used for simple service tasks too A projects stores the following information Device type it is intended to Initializing sequence Register list Data area list Projects are handled like files in usual applications they can be loaded saved new projects can be created Only one project can be active in one session UG107 v1 1 April 07 2014 www cesys com 54 CESYS Software Initializing sequence The initializing sequence is a list of actions that must be executed in order to work with the FPGA on the device The image shows an example initializing list of an EFMO1 loading our example design and let the LED blink for some seconds Sequence contents UDKLab supports the following content for initialization FPGA programming FPGA reset Register write Sleep Without a design an FPGA does nothing so it must be loaded before usage This can be ensured in two ways Download design from host Load design from flash supported on EFMO1 USBV4F and USBS6 So the first entry in the initialize list must be a program entry or if loaded from flash a reset entry To sync communication to the host side Subsequent to this a mix of register write and s
11. Build drivers cd PlxSdk Linux Driver PLX SDK buildalldrivers Loading the driver manually requires a successful build it is done using the following commands cd udkapi2 0 drivers linux PlxSdk sudo PLX SDK DIR pwd Bin Plx load Svc PCI based boards like the PCIS3Base require the following driver sudo PLX SDK DIR pwd Bin Plx load 9056 PCle based boards like the PCleV4Base require the following sudo PLX SDK DIR pwd Bin Plx load 8311 Automation of this load process is out of the scope of this document UG107 v1 1 April 07 2014 www cesys com 36 CESYS Software Build UDK Prerequisites The whole UDK will be build using CMake a free cross platform build tool It creates dynamic Makefiles on unix compatible platforms The first thing should be editing the little configuration inux cmake inside the installation root of the UDK It contains the following options BUILD UI TOOLS If 0 UDKLab isn t build if 7 UDKLab is part of the build but requires a compatible wxWidgets installation CMAKE_BUILD_TYPE Select build type can be one of Debug Release RelWithDeblnfo MinSizeRel If there should be at least 2 builds in parallel remove this line and specify the type using command line option DCMAKE BUILD Makefile creation and build Best usage is to create an empty build directory and run cmake inside of it cd udkapi2
12. can be called to initiate a pulse on RESET at a user given time The following sections will give you a brief introduction about the data transfer from and to the FPGA over the Cypress FX 2 USB peripheral controller s slave FIFO interface the WISHBONE interconnection architecture and the provided peripheral controllers CESYS USB cards use only slave FIFO mode for transferring data For further information about the FX 2 slave FIFO mode see Cypress FX 2 user manual and datasheet and about the WISHBONE architecture see specification B 3 wbspec b3 pdf UG107 v1 1 April 07 2014 WWW Cesys com 21 CESYS FPGA design FPGA source code copyright information This source code is copyrighted by CESYS GmbH GERMANY unless otherwise noted FPGA source code license THIS SOURCECODE 1 NOT FREE IT 1 FOR USE TOGETHER WITH THE CESYS PRODUCTS ONLY YOU ARE NOT ALLOWED TO MODIFY AND DISTRIBUTE OR USE IT WITH ANY OTHER HARDWARE SOFTWARE OR ANY OTHER KIND OF ASIC OR PROGRAMMABLE LOGIC DESIGN WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT HOLDER Disclaimer of warranty THIS SOURCECODE 15 DISTRIBUTED IN THE HOPE THAT IT WILL BE USEFUL BUT THERE IS NO WARRANTY OR SUPPORT FOR THIS SOURCECODE THE COPYRIGHT HOLDER PROVIDES THIS SOURCECODE AS IS WITHOUT WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FORA PARTICULAR PURPOSE THE ENTIRE RISK AS TO
13. 67 eines 67 Revision 68 06107 v1 1 April 07 2014 www cesys com 71
14. is recommended The tool can be downloaded from XILINX web page free of charge As JTAG connector USBS6 implements a standard 2x7 Pin header with 2mm pitch which is compatible to recent XILINX platform cables mE Is Figure 3 JTAG connector J2 UG107 v1 1 April 07 2014 WWW Cesys com 7 CESYS Powering JTAG connector J2 Ground signal Test Mode Select Ground signal Test Data Out Ground signal No connection For further information on the different configuration solutions for XILINX SPARTAN 6 FPGA the reader is encouraged to take a look at the user guide UG380 on XILINX web page USB2 0 controller CYPRESS FX2LP CY7C68013A is a highly integrated low power USB2 0 microcontroller that integrates USB2 0 transceiver serial interface engine SIE enhanced 8051 micro controller and a programmable peripheral interface More information on usage of FX2LP in conjunction with Spartan 6 can be found in chapter FPGA design FX2_SLWR U8 FX2 input FIFO write strobe FX2_SLOE 11 FX2 input output enable activates FX2 data bus FX2_FIFOADRO R10 FX2 input endpoint buffer addresses only two endpoints are used SG HIDE U3 EP2 OUT ADR 1 0 b 00 EP6 IN ADR 1 0 10 FX2_FLAGB FX2 output EP2 almost empty flag UG107 v1 1 April 07 2014 www cesys com 8 CESYS Powering
15. v1 1 April 07 2014 www cesys com 23 CES 5 FPGA design Files and modules Comment src wishbone_pkg vhd A package containing datatypes constants and components needed for the WISHBONE system There are VHDL subroutines for a WISHBONE master bus functional model BFM too These can be used for behavioral simulation purposes src usbs6 soc top vhd This is the top level entity of the design The WISHBONE components instantiated here src wb intercon vhd WISHBONE devices are connected to this shared bus interconnection logic Some MSBs of the address are used to select the appropriate slave src wb fx2 vhd This is the entity of the WISHBONE master which converts the CESYS USB protocol into one or more 32 Bit single read write WISHBONE cycles The low level FX 2 slave FIFO controller fx2 slfifo ctrl vhd is used and 16 32 bit data width conversion is done by using special FIFOs sfifo hd a1Kx18b0K5x36 vhd src wb sl bram vhd A internal BlockRAM is instantiated here and simply connected to the WISHBONE architecture It can be used for testing address oriented data transactions over USB src wb_sl_gpio vhd This entity provides up to 256 general purpose I Os to set and monitor non timing critical internal and external FPGA signals The I Os can be accessed as eight ports with 32 bits each Every single I O can be configured as an in or output I O signals of VG96 connector VG96_IO 80 0 are at 0 por
16. v1 1 April 07 2014 www cesys com 50 CESYS Software The right side contains elements for communication with the FPGA design Register read and write either by value or bit wise using checkboxes Live update of register values Data areas like RAM or Flash can be filled from file or read out to file Live view of data areas More on these areas below um 01 r Device Project Tools Info CLIE GPIO OE Bank0 gt 0 00100008 Block RAM gt 0 00000000 Prog C devel projects cesys udk trunk efm0 1_top bin 32 2 og C devel projects cesys udk trunk efm01_top bin C c mI 1073741824 Address Range 0 00000000 0x000007fF 73 4 2 kByte 0 MB Alignment 4 byte Read write Auto w Device To File File To Device itive view Lor 00000000 00 00 00 00 00 00 00 00 00000008 00 00 00 00 00 00 00 00 Ei GPIO gt 0x00100000 00000010 00 00 00 00 00 00 00 00 00000018 00 00 00 00 00 00 00 00 Hex 40000000 1073741824 00000020 00 00 00 00 00 00 00 00 00000028 00 00 00 00 00 00 00 00 Read Write
17. 1 April 07 2014 www cesys com 31 CESYS Software Windows Requirements To use the UDK in own projects the following is required Installed drivers Microsoft Visual Studio 2005 or 2008 2010 is experimental CMake 2 6 or higher http www cmake org wxWidgets 2 8 10 or higher must be build separately http www wxwidgets org optionally only if UDKLab should be build Driver installation The driver installation is part of the UDK installation but can run standalone on final customer machines without the need to install the UDK itself During installation a choice of drivers to install can be made so it is not necessary to install i e PCI drivers on machines that should run USB devices only or vice versa If USB drivers get installed on a machine that has pre 2 0 driver installation we prefer the option for USB driver cleanup offered by the installer this cleanly removes all dependencies of the old driver installation Note There are separate installers for 32 and 64 bit systems Important At least one device should be present when installing the drivers Build UDK Prerequisites The most components of the UDK are part of one large CMake project There are some options that need to be fixed in msvc cmake inside the UDK installation root BUILD UI TOOLS If 0 UDKLab will not be part of the subsequent build procedure if 1 it will This requires an installation of an already built wxWidgets WX WIDGETS
18. example design requirements The upper waveform demonstrates the behavior of app fifo wr full o and UG107 v1 1 April 07 2014 www cesys com 25 CESYS FPGA design app fifo wr count o when there is no transaction on the slave FIFO controller side of the FIFO During simultaneous FIFO read and FIFO write transactions the signals do not change The signal app fifo wr full o cleared and app fifo wr count o Will decrease if there are read transactions at the slave FIFO controller side but no write transactions at the application side The lower waveform demonstrates the behavior of app fifo rd empty o and app fifo rd count o when there is no transaction at the slave FIFO controller side of the FIFO During simultaneous FIFO read and FIFO write transactions the signals do not change The signal app fifo rd empty o Will be cleared and app fifo rd count o will increase if there are write transactions on the slave FIFO controller side but no read transactions at the application side Please note the one clock cycle delay between app fifo rd iandapp fifo rd data The signals app usb h2p pktcount o 7 0 and app usb p2h pktcount o 7 0 notshown in figure 9 are useful to fit the 512 byte USB bulk packet alignment They are automatically incremented if the appropriate read app fifo rd i orwrite strobe app fifo wr i is asserted These signals count 16 bit data words not data bytes 512 byte alig
19. external IO pins as described in the following chart SPI Flash Direct Programming necessary connections to JTAG cable Q DIN TDO C CCLK TCK GND GND GND Make sure that VCCO is configured for 3 3V signaling levels Do not forget to also enable FPGA power up With XILINX parallel cable IV the led lights green if FPGA is powered on Before starting to download a design to SPI Flash with iMPACT programming software it is necessary to prepare the required mcs SPI PROM file With xapp951 XILINX provides an application note how to accomplish that using iMPACT or PROMGen software tools Select 16M SPI PROM Density when asked Now programming of the SPI Flash can be started by clicking Direct SPI Configuration from within iMPACT Follow the manual provided by XILINX in xapp951 Select M25P16 SPI Flash PROM Type when asked UG107 v1 1 April 07 2014 www cesys com CESYS Additional information pairing and etch length report J3 VG 96 pin connector Differential pairs 28 IN 12 IN OUT B4 696 101 01 BANK 3 62 368 5 VG96 IO4 Ti BANK 3 60 664 C4 VG96 IO2 P3 BANK 3 57 362 B6 VG96 IO7 P1 BANK 3 59 394 B7 VG96 IO10 1 3 597129 C6 VG96 108 N3 BANK 3 59 232 2 2 27 2 2 2 2 2 B8 VG96 IO13 11 58 299 9 VG96 1016 K1 N IN BANK 3 58 236 C8 VG96 IO14 Mi N IN BANK 3 59 761 B10 VG96 1019 H
20. kByte 0 MB Alignment 4 byte t3 Device To File File To Device Live View Figure 20 Data area panel Similar to the register visualization the buttons on the right side can be used to add move and remove data area panels The header shows the name and the address followed by the data area details Below are these buttons Device To File The complete area is read and stored to the file which is defined in the file dialog opening after clicking the button File To Device This reads the file selected in the upcoming file dialog and stores the contents in the data area limited by the file size or data area size This button is not shown if the Read only flag is set Live View If this button is active the text view below shows the contents of the area updated every 100 ms the view can be scrolled so every piece can be visited UG107 v1 1 April 07 2014 www cesys com 59 CESYS Additional information Additional information Using SPI Flash for configuration How to store configuration data in SPI Flash To allow configuration of the FPGA via onboard SPI Flash on power up first an appropriate configuration file has to be stored in the SPI Flash There are several ways to accomplish this Loading SPI Flash via USB The easiest way to get data into SPI Flash surely is to use CESYS software UDK Lab With the help of this easy to use tiny tool binary FPGA configuration bitstreams bin can be downloaded to
21. loaded by calling one of the calls These call internally reset the FPGA after design download From now on data can be transferred Important All data transfer is based on a 32 bit bus system which must be implemented inside the FPGA design PCI devices support this natively while USB devices use a protocol which is implemented by Cesys and sits on top of a stable bulk transfer implementation UG107 v1 1 April 07 2014 www cesys com 45 CESYS Software Methods Functions Open CE_RESULT Open CE_DEVICE_HANDLE Handle Gain access to the specific device Calling one of the other functions in this section require a successful call to Open Notice If two or more applications try to open one device PCI and USB devices behave a bit different For USB devices Open causes an error if the device is already in use PCI allows opening one device from multiple processes As PCI drivers are not developed by Cesys it s not possible to us to prevent this as we see this as strange behavior The best way to share communication of more than one application with devices would be a client server approach Close CE_RESULT Close CE_DEVICE_HANDLE Handle Finish working with the given device ReadRegister CE_RESULT ReadRegister CE_DEVICE_HANDLE Handle unsigned int uiRegister unsigned int puiValue Read 32 bit value from FPGA design address space internally just calling ReadBlock U
22. the buffer were the value is stored to it must be at least of size uiDestSize GetDeviceName CE RESULT GetDeviceName CE DEVICE HANDLE Handle char pszDest unsigned int uiDestSize Return device type name of given device pointer or handle Notice C API pszDest is the buffer were the value is stored to it must be at least of size uiDestSize GetBusType CE_RESULT GetBusType CE_DEVICE_HANDLE Handle unsigned int puiBusType UG107 v1 1 April 07 2014 www cesys com 44 CESYS Software Return type of bus a device is bound to can be any of the following ceBT_USB USB bus GetMaxTransferSize CE_RESULT GetMaxTransferSize CE_DEVICE_HANDLE Handle unsigned int puiMaxTransferSize Return count of bytes that represents the maximum in one transaction larger transfers must be split by the API user Using devices After getting a device pointer or handle devices can be used Before transferring data to or from devices or catching interrupts PCI devices must be accessed which is done by calling Open All calls in this section require an open device which must be freed by calling Close after usage Either way after calling Open the device is ready for communication As of the fact that Cesys devices usually have an FPGA on the device side of the bus the FPGA must be made ready for usage If this isn t done by loading contents from the on board flash not all devices have one a design must be
23. their own applications FX 2 endpoints are realized as 2 kB buffers These buffers can be accessed over a FIFO like interface with a 16 bit tristate data bus by external hardware External hardware acts as a master polling FIFO flags applying read and write strobes and transferring data Therefore this FX 2 data transfer mechanism is called slave FIFO mode As already mentioned all data is transferred in multiples of 512 bytes External hardware has to ensure that the data written to IN endpoint is aligned to this value so that data will be transmitted from endpoint buffer to host The 512 byte alignment normally causes no restrictions in data streaming applications with endless data transfers Maybe it is necessary to fill up endpoint buffer with dummy data if some kind of host timeout condition has to be met Another FX 2 data transfer mechanism is called GPIF General Programmable InterFace mode The GPIF engine inside the FX 2 acts as a master to endpoint buffers transferring data and presenting configurable handshake waveforms to external hardware CESYS USB card supports slave FIFO mode for data communication only GPIF mode is exclusively used for downloading configuration bitstreams to FPGA UG107 v1 1 April 07 2014 WWW Cesys com 18 CESYS FPGA design Clocking FPGA designs The 48 MHz SYSCLK oscillator is an onboard clock source for the FPGA It is used as interface clock IFCLK between FX 2 slave FIFO bus and F
24. theory of liability for any loss or damage of any kind or nature related to arising under or in connection with these materials including for any direct or any indirect special incidental or consequential loss or damage including loss of data profits goodwill or any type of loss or damage suffered as a result of any action brought by a third party even if such damage or loss was reasonably foreseeable or Cesys had been advised of the possibility of the same CRITICAL APPLICATIONS CESYS products are not designed or intended to be fail safe or for use in any application requiring fail safe performance such as life support or safety devices or systems Class medical devices nuclear facilities applications related to the deployment of airbags or any other applications that could lead to death personal injury or severe property or environmental damage individually and collectively Critical Applications Customer assumes the sole risk and liability of any use of Cesys products in Critical Applications subject only to applicable laws and regulations governing limitations on product liability THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES CESYS Gesellschaft fur angewandte Mikroelektronik mbH Zeppelinstrasse 6a D 91074 Herzogenaurach Germany UG107 v1 1 April 07 2014 www cesys com 68 CESYS Revision history Revision history v1 0 Initial release V1 01 Impro
25. to give device nodes the correct access rights 0666 etc udev rules d 99 ceusbuni rules Install module configuration file etc dev modprobe d ceusbuni conf Start module If things work as intended there must be an entry proc ceusbuni after this procedure The following code will completely revert the above installation called in same directory sudo make remove The configuration file etc modprobe d ceusbuni conf offers two simple options Read the comments in the file Enable kernel module debugging Choose between firmware which automatically powers board peripherals or not Changing these options require a module reload to take affect PCI The PCI drivers are not created or maintained by Cesys they are offered by the manufacturer of the PCI bridges that were used on Cesys PCl e boards So problems UG107 v1 1 April 07 2014 www cesys com 35 CESYS Software regarding them can t be handled or supported by us Important If building PlxSdk components generate the following error warning bin sh not found Here s a workaround The problem is Ubuntu s default usage of dash as sh which can t handle command Replacing dash with bash is accomplished by the following commands that must be done as root sudo rm bin sh sudo ln s bin bash bin sh Installation explained in detail PIxSdk decompression cd udkapi2 0 drivers linux tar xvf PlxSdk tar
26. 0 mkdir build cd build cmake If all external dependencies are met this will finish creating a Makefile To build the UDK just invoke make make Important The UDK C API must be build with the same toolchain and build flags like the application that uses it Otherwise unwanted side effects in exception handling will occur See example in project to UDK build UG107 v1 1 April 07 2014 WWW Cesys com 37 CESYS Software Use APIs in own projects C API Include file udkapi h Library file Windows udkapi_vc ver _ arch lib ver is 8 9 10 arch is x86 or amd64 resides in ib build Linux libusbapi so resides in ib Namespace ceUDK As this uses exceptions for error handling it is really important to use the same compiler and build settings which are used to build the API itself Otherwise exception based stack unwinding may cause undefined side effects which are really hard to fix Add project to UDK build A simple example would be the following Let s assume there s a source file mytest mytest cpp inside UDK s root installation To build a mytestexe executable with UDK components those lines must be appended add executable mytestexe mytest mytest cpp target link libraries mytestexe UDKAPI LIBNAME Rebuilding the UDK with these entries in Visual Studio will create a new project inside the solution and request a solution reload On Linux callin
27. 9 246 B29 VG96 1073 Gi N IN OUT BANK 0 72 379 B30 96 1076 12 IN OUT BANK 0 74 253 m 2 29 696 1074 IN OUT BANK 0 68 755 B31 VG96 IO79 E13 N IN OUT BANK 74 871 J4 IDC 50 pin connector Differential pairs 17 IN OUT 4 ADD IO A5 N IN OUT BANK 0 30 458 6 ADD IO A7 N IN OUT BANK 0 28 005 10 ADD IO A2 N IN OUT BANK 18 461 12 ADD IO A3 N IN OUT BANK 19 021 14 ADD IO 4 IN OUT BANK 0 19 743 UG107 v1 1 April 07 2014 www cesys com 5 CESYS Additional information 16 ADD_IO A6 N IN OUT BANK 0 20 131 20 ADD_IO 8 IN OUT BANK 20 394 22 ADD_IO 9 IN OUT BANK 0 21 497 26 ADD IO A11 N IN OUT BANK 24 354 28 ADD IO A12 N IN OUT BANK 0 25 137 30 ADD IO A m A IN OUT BANK 25 137 32 ADD IO A IN OUT BANK 0 25 980 36 ADD_IO A IN OUT BANK 0 40 669 38 ADD IO N IN OUT BANK 0 40 865 42 ADD_IO 13 IN OUT BANK 0 43 527 44 ADD_IO 14 IN OUT BANK 0 42 990 46 ADD_IO 15 IN OUT BANK 0 43 551 UG107 v1 1 April 07 2014 www cesys com o o CESYS Additional information Mechanical dimensions
28. BASE PATH Path to wxWidgets build root only needed if BUILD UI TOOLS is not 0 USE STATIC RTL all projects are build against the dynamic runtime libraries This requires the installation of the appropriate Visual Studio redistributable pack on every machine the UDK is used on Using a static build does not create such dependencies but will conflict with the standard wxWidgets build configuration UG107 v1 1 April 07 2014 WWW Cesys com 32 CESYS Software Solution creation and build The preferred way is to open a command prompt inside the installation root of the UDK lets assume to use udkapi CMake allows the build directory separated to the source directory so it s a good idea to do it inside an empty sub directory mkdir build cd build The following code requires an installation of CMake and at least one supported Visual Studio version If CMake isn t included into the PATH environment variable the path must be specified as well cmake This searches the preferred Visual Studio installation and creates projects for it Visual Studio Express users may need to use the command prompt offered by their installation If multiple Visual Studio versions are installed CMake s command parameter G can be used to specify a special one see CMake s documentation in this case This process creates the solution files inside c udkapi build All subsequent tasks can
29. CESYS USBS6 USBS6 is a low cost multilayer PCB with SPARTAN 6 FPGA and USB 2 0 Interface 34 I O balls of the FPGA are available on standard 2 54mm headers 81 I O balls can be reached through a industry standard VG 96 pin connector It offers multiple configuration options including USB and onboard SPI Flash and can also be used standalone without the need of a USB interface UG107 v1 1 April 07 2014 www cesys com CESYS Features Features XILINX SPARTAN 6 XC6SLX16 2CSG324C FPGA Configuration Using USB2 0 JTAG or SPI Flash Peripherals USB to serial UART FTDI FT232R HEX rotary DIP switch 3 status 5 user LEDs Clock Onboard 48 MHz clock signal up to two optional onboard clocks external clock sources possible Included in delivery The standard delivery includes One USBS6 One USB cable 1 5m User s manual English drivers and source code of sample applications at our download section at www cesys com All party are ROHS compliant UG107 v1 1 April 07 2014 www cesys com 2 CESYS Hardware description Hardware description Block Diagram SPI Flash FPGA configuration 16 Mb Oscillator FPGA 24 MHz USB 2 0 Controller 16 2 32 XC6SLX25 2CSG324C XC6SLX45 2C8G324C Oscillator 48 MHz Expansion connector VG96 81 signals Expansion connector strip header 34 signals Peripherals UART USB ro
30. E 40 Information R RR 42 COVICES iis 44 ATE 49 Th MAIN 49 USING Eo 50 Additional information Nb 59 Using SPI Flash kr netur ex pnta ene ek exon ke 59 How to store configuration data 5 1 59 Loading SPIcFlash via USB Ia Eten ta Prou pe a a 59 SPI Flash Indirect Programming Using FPGA JTAG 59 SPI Flash Direct Programming using 2 4 44 4 1 11 14 1 44 4 1 ene nennen 60 paing and etehi length report uisi toe eie eoa EUR aera ber ver e aw VENE X 61 23 VG 96 pin connector Differential pairs 28 IN 12 IN OUT 61 IDC 50 pin connector Differential pairs 17 685 eee eae 64 Mechanical dimensions Rer doe ed Ta caa Cees Ru gba RR 66 Copyright
31. G107 v1 1 April 07 2014 www cesys com 46 CESYS Software with size 4 WriteRegister CE_RESULT WriteRegister CE_DEVICE_HANDLE Handle unsigned int uiRegister unsigned int uiValue Write 32 bit value to FPGA design address space internally just calling WriteBlock with size 4 ReadBlock CE_RESULT ReadBlock CE_DEVICE_HANDLE Handle unsigned int uiAddress unsigned char pucData unsigned int uiSize unsigned int uiIncAddress Read a block of data to the host buffer which must be large enough to hold it The size should never exceed the value retrieved by GetMaxTransferSize for the specific device bIncAddress is at the moment available for USB devices only It flags to read all data from the same address instead of starting at it WriteBlock CE RESULT WriteBlock CE DEVICE HANDLE Handle unsigned int uiAddress unsigned char pucData unsigned int uiSize unsigned int uiIncAddress Transfer a given block of data to the 32 bit bus system address uiAddress The size should never exceed the value retrieved by GetMaxTransferSize for the specific UG107 v1 1 April 07 2014 WWW Cesys com 47 CESYS Software device bIncAddress is at the moment available for USB devices only It flags to write all data to the same address instead of starting at it WaitForlnterrupt CE RESULT WaitForInterrupt CE DEVICE HANDLE Handle unsigned int uiTimeOutMS unsigned int puiRaised PCI only Check if the inte
32. IGH along with that input data during a 1 UD UDM WRITE access is sampled both edges of 005 MCB1 1005 15 Data strobe for Upper Byte Data bus Output with read data input with write data DQS is edge aligned with read data center aligned in write data It is used to capture data It is strongly recommended to check XILINX user guide UG388 about Spartan 6 FPGA Memory Controller on XILINX website It is strongly recommended to check XILINX user guide UG416 about Spartan 6 FPGA Memory Interface Solutions on XILINX website User specific data can be stored in up to 128Mb of non volatile Flash memory The SPI compliant interface guarantees ease of use and when speed matters MX25L12845EMI 10G supports Q SPI with data rates up to 50 MByte s in fast read double transfer rate mode Some examples on how to implement a SPI compliant interface with Spartan 6 are available in chapter FPGA design MX SCLK Clock Input 6101 T4 Serial Data Output SPI Serial Data IO Dual or Q SPI MX SIO3 V7 Not connect pin SPI Serial Data IO Dual or Q SPI UG107 v1 1 April 07 2014 WWW Cesys com 11 CESYS Powering Peripherals 05856 integrates several peripheral devices Three system and five user configurable LEDs one HEX rotary DIP switch and one USB to SERIAL UART are available Power supply status and FPGA configuration are observable through
33. PGA I Os So this clock source must be used for data transfers to and from FPGA over USB Appropriate timing constraints can be found in ucf files of design examples included in delivery It is strictly recommended to use a single clock domain whenever possible Using a fully synchronous system architecture often results in smaller less complex and more performant FPGA designs compare Xilinx white paper WP331 Timing Closure Coding Guidelines In FPGA designs with multiple clock domains asynchronous FIFOs have to be used for transferring data from one clock domain to the other and comprehensive control signals have to be resynchronized Other clock sources can be added internally by using Spartan 6 onchip digital clock managers DCMs or PLLs or externally by connecting clock sources to other FPGA global clock inputs A wide range of clock frequencies can be synthesized with DCMs and PLLs For further details on DCMs PLLs please see Spartan 6 FPGA Clocking Resources User Guide UG382 FX 2 FPGA slave FIFO connection Only the logical behavior of slave FIFO interface is discussed here For information about the timing behavior like setup and hold times please see FX 2 datasheet All flags and control signals are active low postfix 78 The whole interface is synchronous to IFCLK The asynchronous FIFO transfer mode is not supported FX 2 input FIFO read strobe PKTEND FX 2 input packet end control signal causes FX 2 to sen
34. THE QUALITY AND PERFORMANCE OF THIS SOURCECODE 15 WITH YOU SHOULD THIS SOURCECODE PROVE DEFECTIVE YOU ASSUME THE COST OF ALL NECESSARY SERVICING REPAIR OR CORRECTION IN NO EVENT WILL THE COPYRIGHT HOLDER BE LIABLE TO YOU FOR DAMAGES INCLUDING ANY GENERAL SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THIS SOURCECODE INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES ORA FAILURE OF THIS SOURCECODE TO OPERATE WITH ANY OTHER SOFTWARE PROGRAMS HARDWARE CIRCUITS OR ANY OTHER KIND OF ASIC OR PROGRAMMABLE LOGIC DESIGN EVEN IF THE COPYRIGHT HOLDER HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES UG107 v1 1 April 07 2014 www cesys com 22 CESYS FPGA design Design usbs6_soc An on chip bus system is implemented in this design The VHDL source code shows you how to build a 32 Bit WISHBONE based shared bus architecture All devices of the WISHBONE system support only SINGLE READ WRITE Cycles Files and modules having something to do with the WISHBONE system are labeled with the prefix wb_ The WISHBONE master is labeled with the additional prefix ma_ and the slaves are labeled with 5 There is a package for each module with the additional postfix _ pkg It contains the appropriate VHDL component declaration interface description as well as public constants like register address offsets UG107
35. ally work The best way is to extract it to the home directory tar xzvf UDKAPI x x tgz This creates a directory home userj udkapi version which is subsequently called udkroot The following examples assume an installation root in udkapi2 0 Important Commands sometimes contain a symbol have attention to use the right one refer to command substitution if not familiar with Driver installation The driver installation on Linux systems is a bit more complicated than on Windows systems The drivers must be build against the installed kernel version Updating the kernel requires a rebuild UG107 v1 1 April 07 2014 WWW Cesys com 34 CESYS Software USB As the USB driver is written by Cesys the installation procedure is designed to be as simple and automated as possible The sources and support files reside in directory lt udkroot gt drivers linux usb Just go there and invoke make cd udkapi2 0 drivers linux usb make If all external dependencies are met the build procedure should finish without errors Newer kernel releases may change things which prevent success but it is out of the scope of our possibilities to be always up to date with latest kernels To install the driver the following command has to be done sudo make install This will do the following things Install the kernel module inside the module library path update module dependencies Install a new udev rule
36. be done in Visual Studio with the created solution another invocation of CMake isn t necessary under normal circumstances Important The UDK C API must be build with the same toolchain and build flags like the application that uses it Otherwise unwanted side effects in exception handling will occur See example in Add project to UDK build Info It is easy to create different builds with different Visual Studio versions by creating different build directories and invoke CMake with different G options inside them udkapi mkdir build2005 cd build2005 UG107 v1 1 April 07 2014 www cesys com 33 CESYS Software cmake G Visual Studio 8 2005 cd mkdir build2008 cd build2008 cmake G Visual Studio 9 2008 Linux There are too many distributions and releases to offer a unique way to the UDK installation We ve chosen to work with the most recent Ubuntu release 9 10 at the moment All commands are tested on an up to date installation and may need some tweaking on other systems versions Requirements GNU C compiler toolchain zlib development libraries CMake 2 6 or higher http www cmake org wxWidgets 2 8 10 or higher http www wxwidgets org optionally only if UDKLab should be build sudo apt get install build essential cmake zliblg dev libwxbase2 8 dev libwxgtk2 8 dev The Linux UDK comes as gzip ed tar archive as the Windows installer won t usu
37. d data to host at once ignoring 512 byte alignment so called short packet UG107 v1 1 April 07 2014 www cesys com 19 CESYS FPGA design FIFOADR 1 0 FX 2 input endpoint buffer addresses CESYS USB cards use only two endpoints EP2 OUT ADR 1 0 b 00 and EP6 IN ADR 1 0 b 10 itchinc REL i direct FIFOADR 0 ha FLAG A B C FX 2 outputs A gt EP2 empty flag B gt EP2 almost empty flag meaning one 16 bit data word is available C gt EP6 almost full flag meaning one 16 bit data word can still be transmitted to EP6 there is no real full flag for EP6 almost full could be used instead Introduction to example FPGA designs The CESYS USBS6 Card is shipped with some demonstration FPGA designs to give you an easy starting point for own development projects The whole source code is written in VHDL Verilog and schematic entry design flows are not supported The design usbs6_soc demonstrates the implementation of a system on chip SoC with host software access to the peripherals like GPIOs external Flash Memory LPDDR Memory and internal BlockRAM over USB This design requires a protocol layer over the simple USB bulk transfer see CESYS application note Transfer Protocol for CESYS USB products for details which is already provided by CESYS software API The design usbs6 bram is a minimal example for data transfers fro
38. e left buttons are responsible for adding new entries move the entry up or down and removing the current entry all are self explanatory The header shows it s mapping name as well as the 32 bit address The question mark in the lower right will show a tooltip if the mouse is above it which is just a little help for users Both input fields can be used to write in a new value either hex or decimal or contain the values if they are read from FPGA design The checkboxes represent one bit of the current value Clicking the Read button will read the current value from FPGA and update both text boxes as well as the checkboxes which is automatically done every 100ms if the Auto button is active Setting register values inside the FPGA is done in a similar way clicking the Write button writes the current values to the device One thing needs a bit attention here Clicking on the checkboxes implicitly writes the value without the need to click on the Write button Data area entry A data area entry can be used to communicate with a data block inside the FPGA examples are RAM or flash areas Data can be transfered from and to files as well as displayed in a live view An entry constits of the following data Address Name Data alignment Size Read only flag The visual representation is shown below UG107 v1 1 April 07 2014 www cesys com 58 CESYS Software Block RAM gt 0x00000000 Address Range 0x00000000 0x000007ff 2
39. e whole flash before The read access is as simple as reading from any other WISHBONE device Please see the SPI FLASH data sheet for details on programming and erasing There are two instances of this module One is used for programming FPGA configuration bitstream to SPI FLASH and the other accesses QUAD SPI FLASH for storing nonvolatile application data src wb sl mcb vhd WISHBONE adapter for one port of Spartan 6 build in multiport memory controller block MCB UG107 v1 1 April 07 2014 www cesys com 24 CESYS FPGA design src wb_sl_uart vhd This entity is a simple UART transceiver with 16 byte buffer for each direction connected to USB2UART interface UART transceiver macros are used as physical layer Baudrate is adjustable up to 230400 default 9600 by writing appropriate timer prescaling values to the status and configuration register This register contains buffer level flags FULL and HALFFULL for each direction too Data format is fixed at 8 N 1 Reading from UART pipe is always non blocking A data present flag provided along with received bytes indicates if current RX value is valid Writing to UART pipe is blocking if TX buffer gets full So that loss of transmitted data can easily be avoided src xil_mcb_mig This directory contains VHDL source code files generated by Xilinx memory interface generator tool to build the frontend for MCB File memci infrastructure vhd has been modified to fit
40. eft part contains the registers and the right part all data area block entries UG107 v1 1 April 07 2014 www cesys com 56 CESYS Software GPIO OE Bank0 gt 0 00100008 Block RAM gt 0 00000000 Hex 40000000 Dec 1073741824 Address Range 0 00000000 0x000007fF 2 kByte 0 MB Alignment 4byte Um peviceToFie Fie To Device 00000000 00 00 00 00 00 00 00 00 00000008 00 00 00 00 00 00 00 00 3 Bank gt 0 00100000 00000010 00 00 00 00 00 00 00 00 00000018 00 00 00 00 00 00 00 00 40000000 1073741824 00000020 00 00 00 00 00 00 00 00 00000028 00 00 00 00 00 00 00 00 Read Write 00000030 00 00 00 00 00 00 00 00 z 00000038 00 00 00 00 00 00 00 00 00000040 00 00 00 00 00 00 00 00 Lo 00000048 00 00 00 00 00 00 00 00 OE Bank1 gt 0x0010000c Flash Contents gt 0x00200000 Hex 00000000 Dec Address Range 0 00200000 0x0027ffff Write 512 kByte 0 Alignment 4 byte Hi JBE X Device Toric itive ews Lo
41. evice list but invalidates all previous created device pointers and handles To identify devices in a unique way each device gets a UID which is a combination of device type name and connection point so even after a complete cleanup and new enumeration devices can be exactly identified by this value Methods Functions Init Prepare internal structures must be the first call to the UDK API Can be called after invoking Delnit again see top of this section Delnit CE RESULT Delnit UG107 v1 1 April 07 2014 WWW Cesys com 41 CESYS Software Free up all internal allocated data there must no subsequent call to the UDK API after this call except Init is called again All retrieved device pointers and handles are invalid after this point Enumerate CE_RESULT Enumerate unsigned int DeviceType Search for newly plugged devices of the given type and add them to the internal list Access to this list is given by GetDeviceCount GetDevice DeviceType can be one of the following ceDT_PCI_ALL All UDK supported devices on PCI bus ceDT_PCI_ ceDT_PCI_DOB DOB _PCI_ ceDT_PCI_RTC RTC cel ceDT_PCI_DEFLECTOR Deflector ceDT_USB_USBV4F Cesys USBV4F ceDT_USB_MISS2 MISS2 ceDT_USB_USBS6 Cesys USBS6 Customer specific devices UG107 v1 1 April 07 2014 www cesys com 42 CESYS Software GetDeviceCount CE_RESULT GetDeviceCount unsigned int
42. g make will just include mytestexe into the build process C API Include file udkapic h Library file Windows udkapic_vc ver _ arch lib ver is 8 9 10 arch is x86 or amd64 resides in ib build Linux libusbapic so resides in ib Namespace Not applicable The C offers all functions from a dynamic link library Windows dll Linux so and uses standardized data types only so it is usable in a wide range of environments UG107 v1 1 April 07 2014 WWW Cesys com 38 CESYS Software Adding it to the UDK build process is nearly identical to the C API description except that UDKAPIC_LIBNAME must be used API Include file Library file udkapinet dll resided bin build Namespace cesys ceUDK The NET API as well as it example application is separated from the normal UDK build First of all CMake doesn t have native support NET as well as it is working on Windows systems only Building it has no dependency to the standard all required sources are part of the API project The Visual Studio solution is located in directory dotnet inside the UDK installation root It is a Visual Studio 8 2005 solution and should be convertible to newer releases The solution is split into two parts the NET API in mixed native managed C and an example written in C To use the NET API in own projects it s just needed to add the generated DLL udkapinet dll to the projects
43. i N IN BANK 3 55 680 o UG107 v1 1 April 07 2014 www cesys com 2 CESYS Additional information B11 VG96_IO22 F1 N IN BANK 3 52 504 96 1020 Ji N IN BANK 3 60 972 B12 VG96_1025 D1 N IN BANK 3 50 221 B13 VG96 IO28 3 48 315 12 96 1026 G1 N IN BANK 3 62 840 14 47696 1031 L3 N IN BANK 3 61 456 15 47696 1034 5 3 62 210 14 696 1032 1 z BANK 3 65 008 Bi6 gt VG96 1037 K6 BANK 3 63 853 2 B17 VG96 1040 3 67 031 C16 gt VG96 1038 5 3 62 926 18 VG96 1043 5 3 63 426 06107 v1 1 April 07 2014 www cesys com o CESYS Additional information 18 696 1046 16 3 64 144 20 96 1044 G6 N IN BANK 3 63 609 B21 VG96 1049 D3 N IN BANK 3 60 885 C20 VG96 1052 F3 N IN BANK 3 55 884 B23 VG96 1050 3 64 134 24 VG96 1058 C6 N IN OUT BANK 0 63 540 23 96 1056 6 IN OUT BANK 0 60 128 B25 VG96_1061 E8 IN OUT BANK 0 71 637 B26 VG96 1064 C9 IN OUT BANK 0 69 497 C25 696 1062 C8 IN OUT BANK 0 63 051 27 gt VG96 1067 9 IN OUT BANK 74 696 B28 VG96 IO70 F10 N IN OUT BANK 0 73 594 UG107 v1 1 April 07 2014 www cesys com o 4 CESYS Additional information 27 696 IO68 F8 N IN OUT BANK 0 6
44. ign on E Figure 7 Awake LED and Suspend Connector J1 1 FPGA Suspend connector VCCAUX 3 3V auxiliary supply Awake LED For details of the Suspend feature of SPARTAN 6 devices please visit XILINX homepage and check User Guide Spartan 6 FPGA Power Management UG107 v1 1 April 07 2014 WWW Cesys com 17 CESYS FPGA design FPGA design Cypress FX 2 LP and USB basics Several data transfer types are defined in USB 2 0 specification High speed bulk transfer is the one and only mode of interest to end users USB transfers are packet oriented and have a time framing scheme USB packets consist of USB protocol and user payload data Payload could have a variable length of up to 512 bytes per packet Packet size is fixed to the maximum value of 512 bytes for data communication with CESYS USB cards to achieve highest possible data throughput USB peripherals could have several logical channels to the host The data source sink for each channel inside the USB peripheral is called the USB endpoint Each endpoint can be configured as IN channel direction peripheral gt host or OUT endpoint channel direction host gt peripheral from host side perspective CESYS USB cards support two endpoints one for each direction FX 2 has an integrated USB SIE Serial Interface Engine handling USB protocol and transferring user payload data to the appropriate endpoint So end users do not have to care about USB protocol in
45. leep commands can be placed which totally depends on the underlying FPGA design This can be a sequence of commands sent to a peripheral component or to fill data structures with predefined values If things get complexer i e return values must be checked this goes beyond the scope of the current UDKLab implementation and must be solved by a host process i Prog C devel projects cesys udk trunk efm0 1_top bin Write GPIO OE 8 5 8E Ez 55 CESYS Software Choose option to add Program design to FPGA e Reset FPGA Write register value Sleep Figure 17 Add new initializing task One of the four possible entries must be selected using the radio button in front of it Depending on the option one or two parameters must be set OK adds the new action to initializer list Sequence start The button sitting below the list runs all actions from top to bottom In addition to this the remaining components the content panel will be enabled as UDKLab expects working communication at this point The sequence can be modified an started as often as wished Content panel The content panel can be a visual representation of the FPGA design loaded during initialization It consists of a list of registers and data areas which can be visit and modified using UDKLab The view is split into two columns while the l
46. m and to the FPGA over USB and can be used to get for familiar with UDK hardware software interface The Spartan 6 XC6SLX16 Device is supported by the free Xilinx ISE Webpack development software You will have to change some options of the project properties for own applications A bitstream in the bin format is needed if you want to download your FPGA design with the CESYS software API functions LoadBIN and ProgramFPGA The generation of this file is disabled by default in the Xilinx ISE development environment Check create binary configuration file at right click generate programming file gt properties gt general options UG107 v1 1 April 07 2014 www cesys com 20 CESYS FPGA design ES Process Properties Category General Options Configuration Options Startup Options Readback Options Property Name Value Run Design Rules Checker Create Bit File Create ASCII Configuration File Create IEEE 1532 Configuration File Enable BitStream Compression Enable Debugging of Serial Mode BitStream Enable Cyclic Redundancy Checking Property display level Standard After ProgramFPGA is called and the FPGA design is completely downloaded the pin RESET note the prefix means that the signal is active low is automatically pulsed HIGH LOW HIGH This signal can be used for resetting the FPGA design The API function Reset FPGA
47. n be incremented automatically in block transfers You can find details on enabling disabling the burst mode and address auto increment mode in the CESYS application note Transfer Protocol for CESYS USB products and software documentation CESYS USB transfer protocol is converted into one or more WISHBONE data transaction cycles So the FX 2 becomes a master device in the internal WISHBONE architecture Input signals for the WISHBONE master are labeled with the postfix output signals with O WE O write enable indicates if a write or read cycle is in progress O 31 0 32 Bit data out bus for data transportation from master to slaves UG107 v1 1 April 07 2014 WWW Cesys com 27 CESYS FPGA design ACK_I handshake signal slave devices indicate a successful data transfer for writing and valid data on bus for reading by asserting this signal slaves can insert wait states by delaying this signal it is possible to assert ACK_I in first clock cycle of STB_O assertion using a combinatorial handshake to transfer data in one clock cycle recommendation registered feedback handshake should be used in applications where maximum data throughput is not needed because timing specs are easier to meet UG107 v1 1 April 07 2014 www cesys com 28 CESYS FPGA design Figure 11 WISHBONE transactions with WriteRegister WriteBlock ReadRegister ReadBlock The WISHBONE signals in these illustration
48. nents into one single C project and offers interfaces to C C and for Windows only The API has functions to mask able enumeration unique device identification runtime FPGA programming and 32bit bus based data communication devices have additional support for interrupts Changes to previous versions Beginning with release 2 0 the UDK API is a truly combined interface to Cesys s USB and PCI devices The class interface from the former USBUni and API s was saved at a large extend so porting applications from previous UDK releases can be done without much work Here are some notes about additional changes Complete rewrite Build system cleanup all UDK parts except NET are now part of one large project 64 bit operating system support UDK tools combined into one application UDKLab Updated to latest PLX SDK 6 31 Identical C C and NET API interface NET Windows only Different versions of components collapsed to one UDK version Windows only Microsoft Windows Vista Seven 7 support PCI drivers are not released for Seven at the moment Driver installation update is done by an installer now Switched to Microsoft s generic USB driver WinUSB Support moved to Visual Studio 2005 2008 and 2010 experimental older Visual Studio versions are not supported anymore Linux only Revisited USB driver tested on latest Ubuntu distributions 32 64 Simpler USB driver installation UG107 v1
49. ng internal processing of anything CeE_INCOMPATIBLE supported by this device ceE_OUTOFMEMORY Failure allocating enough memory GetLastErrorText const char GetLastErrorText Returns a text which describes the error readable by the user Most of the errors contain problems meant for the developer using the UDK and are rarely usable by end users In most cases unexpected behavior of the underlying operation system or in data transfer is reported All texts are in english UG107 v1 1 April 07 2014 www cesys com 40 CESYS Software Device enumeration The complete device handling is done by the API internally It manages the resources of all enumerated devices and offers either a device pointer or handle to API users Calling Init prepares the API itself while Delnit does a complete cleanup and invalidates all device pointers and handles To find supported devices and work with them Enumerate must be called after Init Enumerate can be called multiple times for either finding devices of different types or to find newly plugged devices primary USB at the moment One important thing is the following Enumerate does never remove a device from the internal device list and so invalidate any pointer it just add new ones or does nothing even if a USB device is removed For a clean detection of a device removal calling Delnit Init and Enumerate in exactly that order will build a new clean d
50. nment is turned into a 256 16 bit word alignment at this interface Please note that using raw USB bulk transfers and slave FIFO transactions directly is not recommended It is just for background information Use protocol based WISHBONE interface instead src sfifo hd a1Kx18bOK5x36 vhd This entity is a general purpose synchronous FIFO buffer with mismatched port widths It is build of a FPGA BlockRAM usbs6 soc xise Project file for Xilinx 15 usbs6 soc fpga consts h C header file extracted from VHDL packages It contains address flag bitfield and value definitions for FPGA design access integration into host software application UG107 v1 1 April 07 2014 www cesys com 26 CESYS FPGA design Software Pseudo Code Example include usbs6 soc fpga consts h address of UART status and configuration register uint32 t uiRegAddr UART BASEADR UART STACFG OFFSET read modify write register value for 9600 baud uint32 t uiRegVal ReadRegister uiRegAddr amp UART STACFG BDR FIELD uiRegVal STACFG BDR FIELD amp UART STACFG BDR VAL 9600 UART STACFG BDR FIELD POS setting UART baud rate WriteRegister uiRegAddr uiRegVal WISHBONE transactions The software API functions ReadRegister WriteRegister lead to one and ReadBlock WriteBlock to several consecutive WISHBONE single cycles Bursting is not allowed in the WISHBONE demo application The address ca
51. onboard SPI Flash via USB SPI Flash Indirect Programming Using FPGA JTAG Chain Since XILINX ISE WebPACK version 10 1 it is possible to configure SPI Flashes attached to the FPGA JTAG interface Before starting to download a design to SPI Flash with iMPACT programming software it is necessary to prepare the required mcs SPI PROM file With xapp951 XILINX provides an application note how to accomplish that using or PROMGen software tools Select 16M SPI PROM Density when asked Thereafter connect JTAG adapter and power up USBS6 either by connecting USB cable or via external 5V power supply With XILINX parallel cable IV the led lights green if FPGA is powered on Now start XILINX iMPACT select Boundary Scan mode and follow the manual provided by XILINX in xapp951 Select M25P16 SPI Flash PROM Type when asked SPI Flash MISO R13 Input Master SPI Serial Data Input CCLK R15 Output Configuration Clock UG107 v1 1 April 07 2014 www cesys com 60 CESYS Additional information HOLD HOLD Externally pulled HIGH 4 7kOhm resistor SPI Flash Direct Programming using iMPACT Out of the box Direct SPI Programming via XILINX download cable and iMPACT programming software is not supported But with the help of some tiny FPGA design which only has to bypass SPI signals to external pins on connectors J3 or J4 it is possible to access all needed SPI Flash pins Connect JTAG adapter to
52. or 3 3V signaling level per default Differential IO standards as for example LVDS are supported too Detail information about IO pairing is available in paragraph pairing and etch length report of chapter Additional information on connectors J3 and J4 are directly connected to FPGA IO and therefore are only 3 3 Volt tolerant NEVER apply voltages outside the interval 0 95V 4 1V as this may lead to severe damage of FPGA and attached components For more information regarding DC and switching characteristics of Spartan 6 FPGA please consult documentation 05160 on XILINX website J3 VG96 pin external expansion connector 05 oe 1 B H Figure 5 VG 96 pin external expansion connector J3 A31 F13 VG96 IO78 B31 E13 VG96 IO79 C31 C4 VG96 1080 A29 011 VG96 IO72 B29 C11 VG96 IO73 C29 E11 VG96 IO74 A27 G9 VG96 IO66 B27 F9 VG96 IO67 C27 F8 VG96 IO68 A25 E7 VG96 IO60 B25 E8 VG96 IO61 C25 C8 VG96 IO62 A23 F6 VG96 IO54 B23 F5 VG96 IO55 C23 E6 VG96 IO56 A21 E4 VG96 IO51 B21 D3 VG96 IO52 C21 F4 VG96 IO53 UG107 v1 1 April 07 2014 WWW Cesys com 14 CESYS Powering A19 H4 VG96 IO45 B19 H3 VG96 IO46 C19 27 VG96_1047
53. puiCount Return count of devices enumerated up to this point May be larger if rechecked after calling Enumerate in between GetDevice CE RESULT GetDevice unsigned int CE DEVICE HANDLE pHandle Get device pointer or handle to the device with the given index which must be smaller than the device count returned by GetDeviceCount This pointer or handle is valid up to the point Delnit is called Information gathering The functions in this chapter return valuable information All except GetUDKVersionString are bound to devices and can be used after getting a device pointer or handle from GetDevice only Methods Functions GetUDKVersionString const char GetUDKVersionString Return string which contains the UDK version in printable format UG107 v1 1 April 07 2014 www cesys com 43 CESYS Software GetDeviceUID CE RESULT GetDeviceUID CE DEVICE HANDLE Handle char pszDest unsigned int uiDestSize Return string formatted unique device identifier This identifier is in the form of type location while type is the type of the device i e EFMO1 and location is the position the device is plugged to For PCI devices this is a combination of bus slot and function PCI bus related values and for USB devices a path from device to root hub containing the port of all used hubs So after re enumeration or reboot devices on the same machine can be identified exactly Notice C API pszDest is
54. references API Functions in detail Notice To prevent overhead in most usual scenarios the API does not serialize calls in any way so the API user is responsible to serialize call if used in a multi threaded context Notice The examples for NET in the following chapter are in C coding style API Error handling Error handling is offered very different While both C and NET API use exception handling the C API uses a classical return code error inquiry scheme C and NET API UDK API code should be embedded inside a try branch and exceptions of type ceException must be caught If an exception is raised the generated exception object offers methods to get detailed information about the error C API All UDK API functions return either SUCCESS or CE FAILED If the latter is returned the functions below should be invoked to get the details of the error UG107 v1 1 April 07 2014 WWW Cesys com 39 CESYS Software Methods Functions GetLastErrorCode unsigned int GetLastErrorCode Returns an error code which is intended to group the error into different kinds It can be one of the following constants ceE IO ERROR IO errors of any kind file hardware etc ceE PARAM Errors related to wrong call parameters NULL pointers ceE API Undefined behavior of underlying API Wrong order calling group of code i e ceE_PROCESSING Occurred duri
55. rrupt is raised by the FPGA design If this is done in the time specified by the timeout the function returns immediately flagging the interrupt is raised return code puiRaised Otherwise the function returns after the timeout without signaling Important If an interrupt is caught Enablelnterrupt must be called again before checking for the next Besides that the FPGA must be informed to lower the interrupt line in any way Enablelnterrupt CE RESULT EnableInterrupt CE DEVICE HANDLE Handle PCI only Must be called in front of calling WaitForlnterrupt and every time an interrupt is caught and should be checked again ResetFPGA CE RESULT ResetFPGA CE DEVICE HANDLE Handle Pulses the FPGA reset line for a short time This should be used to sync the FPGA UG107 v1 1 April 07 2014 www cesys com 48 CESYS Software design with the host side peripherals ProgramFPGAFromBIN Program the FPGA with the Xilinx tools bin file indicated by the filename parameter Calls ResetFPGA subsequently ProgramFPGAFromMemory CE_RESULT ProgramFPGAFromMemory CE_DEVICE_HANDLE Handle const unsigned char pszData unsigned int uiSize Program FPGA with a given array created with UDKLab This was previously done using fpgaconv ProgramFPGAFromMemoryZ CE_RESULT ProgramFPGAFromMemoryZ CE_DEVICE_HANDLE Handle const unsigned char pszData unsigned int uiSize Same as ProgramFPGAFromMemory except the de
56. s and explanations are shown as simple bit types or bit vector types but in the VHDL code these signals could be encapsulated in extended data types like arrays or records UG107 v1 1 April 07 2014 WWW Cesys com 29 CESYS FPGA design Example port map I gt intercon masters slave 2 ack Port 1 is connected to signal ack of element 2 of array slave of record masters of record intercon Design usbs6_bram This design is intended to demonstrate behavior of UDK software API resulting in WISHBONE cycles It is a reduced version of usbs6_soc example implementing a single slave src usbs6 bram top vhd This is the top level module It instantiates FX 2 module as a WISHBONE master device wb fx2 vhd and BlockRAM as a WISHBONE slave device wb sl bram vhd src wb sl bram vhd See chapter Design usbs6 soc src fx2_slfifo_ctrl vhd See chapter Design usbs6_soc usbs6 bram xise Project file for Xilinx ISE wb_sl_bram_tb do ModelSim command macro file for BFM BlockRAM testbench wb sl bram tb vhd UG107 v1 1 April 07 2014 www cesys com 30 CESYS Software Software The UDK Unified Development Kit is used to allow developers to communicate with Cesys s USB and PCl e devices Older releases were just a release of USB and drivers plus API combined with some shared code components The latest UDK combines all compo
57. s no device is selected only device independent functions are available FPGA design array creator option to define USB Power On behavior Info menu contents UG107 v1 1 April 07 2014 www cesys com 51 CESYS Software All other actions require a device which can be chosen via the device selector which pops up as separate window Choose device selector E Select device to work with 2 Confirm selection same as double click 2 Re Trigger device enumeration i e after device un plug Select device USBV4F roothubp 1 EFM01 roothubpo Figure 13 Device selection flow If the device list is not up to date clicking Re Enum will search again A device can be selected by either double clicking on it or choosing OK Important Opening the device selector again will internally re initialize the underlying API so active communication is stopped and the right panel is disabled again more on the state of this panel below After a device has been selected most UI components are available FPGA configuration FPGA design flashing if device has support Project controls Initializer controls Related to projects UG107 v1 1 April 07 2014 www cesys com 52 CESYS Software The last disabled component at this point is the content panel It is enabled if the initialization sequence has been run The complete flow to enable all Ul elements can be
58. seen below x Block RAM Select device og C devel projects cesys Yudk y fm0 1_top bin Ey of e Load project modify initialize sequence t Run the initialization sequence gt After completion this panel will be enabled 0x00000 100 gt uxduuud 100 00000000 4 GPIO OE 0 gt 0x00100008 Flash Contents gt 0x00200000 GPIO Bank0 gt 0 00100000 00000000 t 4 GPIO Bank1 gt 0 0010000 2 GPIO Bank1 gt 0 00100004 Figure 14 Prepare to work with device FPGA configuration Choosing this will pop up a file selection dialog allowing to choose the design for download If the file choosing isn t canceled the design will be downloaded subsequent to closing the dialog FPGA design flashing This option stores a design into the flash component on devices that have support for it The design is loaded to the FPGA after device power on without host intervention How and under which circumstances this is done can be found in the hardware description of the corresponding device The following screen shows the required actions for flashing UG107 v1 1 April 07 2014 www cesys com 53 CESYS Software Choose device Select flash device Choose FPGA design for flashing Close dialog after flashing has finished Alternatively the flash can be erased
59. sign data is compressed UG107 v1 1 April 07 2014 www cesys com 49 CESYS Software SetTimeOut CE_RESULT SetTimeOut CE_DEVICE_HANDLE Handle unsigned int uiTimeOutMS Set the timeout in milliseconds for data transfers If a transfer is not completed inside this timeframe the API generates a timeout error EnableBurst CE_RESULT EnableBurst CE_DEVICE_HANDLE Handle unsigned int uiEnable PCI only Enable bursting in transfer which frees the shared address data bus between PCl e chip and FPGA by putting addresses on the bus frequently only UDKLab UDKLab is a replacement of the former cesys Monitor as well as cesys Lab and fpgaconv It is primary targeted to support FPGA designers by offering the possibility to read and write values from and to an active design It can further be used to write designs onto the device s flash so FPGA designs can load without host intervention Additionally designs can be converted to C C and C arrays which allows design embedding into an application The main screen The following screen shows an active session with an EFM01 device The base view is intended to work with a device while additional functionality can be found in the tools menu The left part of the screen contains the device initialization details needed to prepare the FPGA with a design or just a reset if loaded from flash plus optional register writes for preparation of peripheral components UG107
60. t2 bits 80 0 I O signals of add on connector ADD IO 33 0 are at port4 bits 129 96 user LEDs are at port5 bits 163 160 and hex encoder is at port6 bits 195 192 Port7 is used for monitoring MCB status signals bit 224 2 READ ERROR bit 225 gt READ OVERFLOW bit 226 gt WRITE ERROR bit 227 gt WRITE UNDERRUN and bit 228 2 CALIBRATION DONE src wb sl gpio vhd This entity provides up to 256 general purpose I Os to set and monitor non timing critical internal and external FPGA signals The I Os can be accessed as eight ports with 32 bits each Every single I O can be configured as an in or output I O signals VG96 connector VG96_IO 80 0 are at portO port2 bits 80 0 I O signals of add on connector ADD IO 33 0 are at port3 port4 bits 129 96 user LEDs are at port5 bits 163 160 and hex encoder is at port6 bits 195 192 Port7 is used for monitoring MCB status signals bit 224 gt READ ERROR bit 225 gt READ OVERFLOW bit 226 gt WRITE ERROR bit 227 gt WRITE UNDERRUN and bit 228 gt CALIBRATION DONE src wb sl flash vhd The module encapsulates the low level FLASH controller flash ctrl vhd The integrated command register supports the BULK ERASE command which erases the whole memory by programming all bits to 1 In write cycles the bit values can only be changed from 1 to 0 That means that it is not allowed to have a write access to the same address twice without erasing th
61. tary hex switch user leds Figure 1 USBS6 Block Diagram Spartan 6 FPGA Configurable logic blocks Slices Flip Flops 2 278 18 224 DSP Slices USB 2 0 connector UG107 v1 1 April 07 2014 www cesys com CESYS Hardware description For details of the SPARTAN 6TM FPGA device please look at the data sheet at http www xilinx com support documentation data_sheets ds160 pdf UG107 v1 1 April 07 2014 www cesys com 4 CESYS Hardware description 020 e zm e 5 a O o m m m us m 618 K15 017 16 XILINX FPGA inte M14 SPARTAN LEDDR Wa L18 AS a 2 mu on 5 B ETE 8 8 8 8 5 mm E OOOO 8 B 8m 8 8 18 880801 2 z iTiiiiif E M AIO IO Tse UEM Magma nif
62. the internal clock signals input buffers and output drivers Taking CKE LOW enables PRECHARGE power down and SELF REFRESH operations all banks idle or ACTIVE power down row active in any bank CKE is synchronous for all functions except SELF REFRESH exit All input buffers except CKE are disabled during power down and self refresh modes MCB1 RZQ N14 Input termination calibration pin used with the soft calibration module External 100 Ohm resistor to GND 1 210 No connect signal used with the soft calibration module to calibrate the input termination value MCB1 CK G16 Clock CK is the system clock input and are differential clock inputs All address and control input signals are sampled on the crossing CK n G18 of the positive edge of CK and the negative edge of Input and output data is referenced to the crossing of CK both directions of the crossing MCB1 DQO M16 Data input output Lower Byte Data bus MCB1 001 M18 MCB1 DQ2 L17 MCB1 DQ3 L18 1 004 17 MCB1 005 18 MCB1 DQ6 216 1 007 218 1 1005 17 Data strobe for Lower Byte Data bus Output with read data input with write data DQS is edge aligned with read data center aligned in write data It is used to capture data UG107 v1 1 April 07 2014 www cesys com 10 CESYS Powering MCB1 LDM Input data mask DM is an input mask signal for write data Input data is masked when DM is sampled H
63. the system LEDs The user configurable LEDs allow to make internal monitoring status signals visible by driving the appropriate FPGA IO to a HIGH level Figure 4 USBS6 peripheral devices System LEDs User LEDs USB to Serial connector HEX rotary DIP switch USB2 0 connector LEDs SYS LED1 Power signal from onboard voltage regulator USER_LEDO 7 User configurable LED USER_LED2 P8 User configurable LED USER_LED4 R7 User configurable LED HEX rotary DIP switch The HEX rotary DIP switch is of binary coded type The four weighted terminals are externally pulled HIGH with 4 7 kOhm resistors the common terminals are connected to GND Therefore the four FPGA inputs behave like a complementary binary coded hexadecimal switch UG107 v1 1 April 07 2014 www cesys com 12 CESYS Powering USB to serial UART interface FT232R from FTDI is a USB to serial UART interface A short example how to implement a simple UART transceiver in FPGA designs can be found hdl usbs6 src wb_sl_uart vhd in UDKAPI2 O installation folder FTDI_RXD 15 Receiving asynchronous data input for FT232R FTDI_CTS_n M8 FPGA OUT Clear to send control input for FT232R UG107 v1 1 April 07 2014 www cesys com 13 CESYS Powering External expansion connectors On connectors J3 and up to 115 general purpose FPGA IO are accessible Bank 0 and Bank 3 of the FPGA are configured f
64. ved readability of tables V1 1 April 07 2014 Header added Footer Modified Layout modified jk UG107 v1 1 April 07 2014 www cesys com 69 CESYS Table of contents Table of contents 2111021 2 2 Hardware dqesceripEIOH ee 3 Bee ISO 3 Spartae TM 3 POWERING DIM DONDE REDE 6 A 7 USB2 0 controller 8 External AMMO RY E e RE x sca eU TER RES 9 P ripherals 12 12 HEX rotary DIP SWIECh secet Ke a xa eGo bas 12 USB to Serial VART 13 External expansion eese ae 14 23 VG96 pin external expansion 2 14 24 IDC 2x25 Pin external expansion 15 Suspend and AWake exe
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