Usage Notes on A/D Conversion Delaying Function of MTU2
Contents
1. UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Do not set bits 6 and 4 to 0 to 1 when complementary PWM mode is not selected Bit Symbol Bit Name Description R W bO ITB4VE TCIV4 Interrupt Skipping Link 0 TCI4V interrupt skipping is not linked R W Enable 1 TCI4V interrupt skipping is linked b1 ITB3AE TGIA3 Interrupt Skipping Link 0 TGI3A interrupt skipping is not linked R W Enable 1 TGI3A interrupt skipping is linked b2 ITA4VE TCIV4 Interrupt Skipping Link 0 TCI4V interrupt skipping is not linked R W Enable 1 TCI4V interrupt skipping is linked b3 ITASAE TGIA3 Interrupt Skipping Link 0 TGI3A interrupt skipping is not linked R W Enable 1 TGI3A interrupt skipping is linked b4 DT4BE Down Count TRG4BN Enable 0 A D converter start requests TRG4BN disabled R W during MTU4 TCNT down count operation A D converter start requests TRG4BN enabled during MTU4 TCNT down count operation b5 UT4BE Up Count TRG4BN Enable 0 A D converter start requests TRG4BN disabled R W during MTU4 TCNT up count operation 1 A D converter start requests TRG4BN enabled during MTU4 TCNT up count operation b6 DT4AE Down Count TRG4AN Enable 0 A D converter start requests TRG4AN disabled R W during MTU4 TCNT down count operation 1 A D converter start requests TRG4AN enabled during MTU4 TCNT down count operation b7 UT4AE Up Count TRG4AN Enable 0 A D converter star2. 4 10 Write 0 to MTU4 TADCOBRA MTU4 TCNT MTU4 TADCORA l MTU4 TADCOBRA i l l diik Request of starting A D conversion TRG4AN An A D converter start request is not issued during up counting immediately after buffer transfer trough Poe ea eae UT4AE DT4AE BF 1 0 Bits in TADCR DI4AE 0 BF 1 0 10b transferred at trough Note 1 An A D converter start request is issued when TCDR 11 MTU4 TADCOBRA TADCOBRB I 1 is written Figure 2 1 A D Converter Start Request When 0 is Written to MTU4 TADCOBRA Write the same value as Ki to MTU4 TADCOBRA tus TADCOBRA Request of starting A D conversion TRG4AN An A D converter start request is not issued during down counting immediately after buffer transfer crest Complementary PWM mode UT4AE 0 UT4AE DT4AE BF 1 0 Bits in TADCR DT4AE 1 BF 1 0 01b transferred at crest Note 1 An A D converter start request is issued when TCDR 11 MTU4 TADCOBRA TADCOBRB I 1 is written Figure 2 2 A D Converter Start Request When the Same Value as TCDR is Written to MTU4 TADCOBRA Re Page 2 of 11 lt ENESAS RENESAS TECHNICAL UPDATE TN RX A118A E Date March 11 2015 Corrections in the Manual 18 2 9 Timer A D Converter Start Request Control Register TADCR lt Before correction p 909 gt Address MTU4 TADCR 0008 8640h MTU10 TADCR 0008 8A40h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 bO BF 1 0 p f
3. Set bits 6 and 4 to 0 to 0 when not in complementary PWM mode Bit Symbol Bit Name Description R W bO ITB4VE TCIV4 Interrupt Skipping Link 0 TCI4V interrupt skipping is not linked R W Enable 1 TCI4V interrupt skipping is linked b1 ITB3AE TGIA3 Interrupt Skipping Link 0 TGI3A interrupt skipping is not linked R W Enable 1 TGI3A interrupt skipping is linked b2 ITA4VE TCIV4 Interrupt Skipping Link 0 TCI4V interrupt skipping is not linked R W Enable 1 TCI4V interrupt skipping is linked b3 ITA3AE TGIA3 Interrupt Skipping Link 0 TGI3A interrupt skipping is not linked R W Enable 1 TGI3A interrupt skipping is linked b4 DT4BE Down Count TRG4BN Enable 0 A D converter start requests TRG4BN disabled R W during MTU4 TCNT down count operation A D converter start requests TRG4BN enabled during MTU4 TCNT down count operation b5 UT4BE Up Count TRG4BN Enable 0 A D converter start requests TRG4BN disabled R W during MTU4 TCNT up count operation 1 A D converter start requests TRG4BN enabled during MTU4 TCNT up count operation b6 DT4AE Down Count TRG4AN Enable 0 A D converter start requests TRG4AN disabled R W during MTU4 TCNT down count operation 1 A D converter start requests TRG4AN enabled during MTU4 TCNT down count operation b7 UT4AE Up Count TRG4AN Enable 0 A D converter start requests TRG4AN disabled R W during MTU4 TCNT up count operation 1 A D converter up requests TRG4AN enabled during MTU4 TCNT d
4. cycle register register to cycle register MTU4 TADCORA MTU4 TCNT MTU4 TADCOBRA f ee m we oe om ow o op A D converter start request TRG4AN Complementary PWM mode Figure 18 75 Basic Example of A D Converter Start Request Signal TRG4AN Operation Unit 0 lt After correction gt Transfer from cycle buffer Transfer from cycle buffer Period in which A D _ Period in which A D register to cycle register register to cycle register converter start eanwarter atari requests are enabled requests are enabled DT4AE 1 UT4AE 1 oe MTU4 TADCORA MTU4 TADCOBRA A D converter start request TRG4AN Period in which A D converter start requests are enabled DT4AE 1 0 lt MTU4 TCNT lt TCDR 1 ompiementary PWM mode Period in which A D converter start requests are enabled UT4AE 1 TCDR gt MTU4 TCNT gt 1 UT4AE 0 DT4AE 1 BF 1 0 10b Figure 18 75 Basic Example of A D Converter Start Request Signal TRG4AN Operation Unit 0 Re Page 7 of 11 lt ENESAS RENESAS TECHNICAL UPDATE TN RX A118A E Date March 11 2015 lt Addition gt 3 Period in Which A D Converter Start Requests are Enabled When MTUn TCNT and MTUn TADCORA MTUn TADCORB match during the period enabled by the UT4AE DT4AE UT4BE or DT4BE bit in MTUn TADCR the corresponding A D converter start request TRG4AN or TRG4BN is generated If the UT4AE or UT4BE bit is set to 1 in complementary PWM mode A D converte
5. cycle set register MTUn TADCORA MTUn TADCORB Transfers data from the cycle set buffer register MTUn TADCOBRA MTUn TADCOBRB to the cycle set register MTUn TADCORA MTUn TADCORB at a compare match between MTUn TCNT and MTUn TGRA Setting prohibited Setting prohibited n 4 10 m 3 9 Reset Synchronous PWM Mode Does not transfer data from the cycle set buffer register MT Un TADCOBRA MT Un TADCOBRB to the cycle set register MTUn TADCORA MTUn TADCORB Transfers data from the cycle set buffer register MTUn TADCOBRA MT Un TADCOBRB to the cycle set register MTUn TADCORA MTUn TADCORB at a compare match between MTUm TCNT and MTUm TGRA Setting prohibited Setting prohibited Normal Mode Does not transfer data from the cycle set buffer register MT Un TADCOBRA MT Un TADCOBRB to the cycle set register MTUn TADCORA MTUn TADCORB Transfers data from the cycle set buffer register MTUn TADCOBRA MTUn TADCOBRB to the cycle set register MTUn TADCORA MTUn TADCORB at a compare match between MTUn TCNT and MTUn TGRA Setting prohibited Setting prohibited Page 5 of 11 tENESAS RENESAS TECHNICAL UPDATE TN RX A118A E Date March 11 2015 18 3 9 A D Converter Start Request Delaying Function 1 Example of Procedure for Specifying A D Converter Start Request Delaying Function lt Before correction p 1000 gt ma i 1 Set the cycle in the timer A D converter start request cycle buffer pe aa s
6. Date Mar 11 2015 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product MPU MCU Document TN RX A118A E Rev 1 00 Category No l Usage Notes on A D Conversion Delaying Information seas ae Title Function of MTU2 Category Technical Notification RX62N 621 Group Asiana RX63N 631 Group RX630 Group Beirencs Product RX210 Group RX220 Group See below RX21A Group RX111 Group Alllots Document RX113 Group Usage notes on the multi function timer pulse unit 2 MTU2 MTU2a for the products listed below are as follows According to this update relevant manuals are revised The details of the corrections are described as follows based on the users manual hardware of the RX62N group and RX621 group See the section of Applicable Products and Relevant Documents in the last section for the corrections of the manuals in other groups Notes 1 A D Converter Start Request Enabled Interval in A D Conversion Delaying Function lf the UT4AE or UT4BE bit in MTUn TADCR is set to 1 in complementary PWM mode A D converter start requests are enabled during the MTUn TCNT up counting period The A D converter start request enabled interval is 0 lt MTUn TCNT s TCDR 1 lf the DT4AE or DT4BE bit in MTUn TADCR is set to 1 in complementary PWM mode A D converter start requests are enabled during the MTUn TCNT down counting period The A D converter s
7. E and ITB4VE bits in the MTU4 TADCR register to 0 Note This function should be used in combination with interrupt skipping When interrupt skipping is disabled the T3AEN and T4VEN bits in the timer interrupt skipping set register TITCR are cleared to 0 or the skipping count set bits T3ACOR and T4VCOR in TITCR are cleared to 0 make sure that A D converter start requests are not linked with interrupt skipping clear the ITASAE ITA4VE ITB3AE and ITB4VE bits in the timer A D converter start request control register TADCR to 0 Note that TRG4ABN TRG4AN or TRG4BN is output as the A D converter start request signal in this case When this function is used MTUn TADCORA and MTUn TADCORB should be set with the value ranging 0002h to the value set in TCDRA minus 2 n 4 10 Re Page 9 of 11 lt ENESAS RENESAS TECHNICAL UPDATE TN RX A118A E Date March 11 2015 lt Addition gt 18 6 25 Usage Notes on A D Converter Delaying Function in Complementary PWM Mode When MTUn TADCOBRA MTUn TADCOBRB is set to 0 and the UT4AE or UT4BE bit in MTUn TADCR is set to 1 and the result is transfer to the buffer when counting by MTUn TCNT reaches its trough an A D converter start request is not generated during the up counting period immediately following the transfer Figure 18 125 When the same value as that of TCDR is set to MTUn TADCOBRA MTUn TADCOBRB and the DT4AE or DT4BE bit in TADCR is set to 1 and the result is transferred to the
8. buffer when counting by MTUn TCNT reaches its crest an A D converter start request is not generated during the down counting period immediately following the transfer Figure 18 126 When A D converter start requests are linked to the interrupt skipping function set TADCORA TADCORB to meet the condition 2 lt MTUn TADCORA MTUn TADCORB lt TCDR 2 n 4 10 Write 0 to MTU4 TADCOBRA MTU4 TCNT MTU4 TADCORB MTU4 TADCOBRA MTU4 TADCORB MTU4 TADCORA e Ji Request of starting A D conversion TRG4AN An A D converter start request is not issued during up counting immediately after buffer transfer trough Complementary PWM mode UT4AE 1 UT4AE DT4AE BF 1 0 Bits in TADCR DT4AE 0 BF 1 0 10b f h Note 1 An A D converter start request is issued when TCDR 1 TU4 TADCOBRA TADCOBRB I 1 1 0 ASTEA AER is written Figure 18 125 A D Converter Start Request When 0 is Written to MTU4 TADCOBRA Write the same value as T to MTU4 TADCOBRA mmus TADCOBRA MTU4 TADCORA MTU4 TADCORB Request of A A gt f A D conversion TRG4AN An A D converter start request is not issued during down counting Compl tarv PWM mod immediately after buffer transfer crest omplementary mode UT4AE 0 DT4AE 1 BF 1 0 01b transferred at crest UT4AE DT4AE BF 1 0 Bits in TADCR Note 1 An A D converter start request is issued when TCDR 11 MTU4 TADCOBRA TADCOBRB II 1 is written Figure 18 126 A D Conver
9. eries register MTU4 TADCOBRAVB and timer A D converter start sd a TUNCUAN request cycle register MTU4 TADCORA B The same initial value must be specified in the cycle buffer register and cycle register Set A D converter start request cycle l l Use bits BF 1 0 in the timer A D converter start request control register TADCR to specify the timing of transfer from the timer A D converter start request cycle buffer register to A D converter start request cycle register e Set the timing of transfer from cycle set buffer register e Set linkage with interrupt skipping e Enable A D converter start request delaying function e Specify whether to link with interrupt skipping through bits ITASAE ITA4VE ITB3AE and ITB4VE e Use bits TU4AE DT4AE UT4BE and DT4BE to enable A D conversion start requests TRG4AN or TRG4BN Note 1 Perform TADCR setting while MTU4 TCNT is stopped Note 2 Do not set BF 1 to 1 when complementary PWM mode is not delaying function DT4BE to 1 when complementary PWM mode is not selected selected AP converter start a Note 3 Do not set ITA3AE ITA4VE ITB3AE ITB4VE DT4AE or Figure 18 74 Example of Procedure for Specifying A D Converter Start Request Delaying Function lt After correction gt iv 1 Set the cycle in the timer A D converter start request cycle buffer ee register MTU4 TADCOBRAVB and timer A D converter start ray lng CHON request cycle register MTU4 TADCORA B The same in
10. g selected with the BF 1 0 bits in the timer A D converter start request control register MTUn TADCR n 4 or 10 There are notes on the timing for transferring data when using buffer transfer in complementary PWM mode For details see section 18 6 25 Notes on A D converter Delaying Function in Complementary PWM Mode In modes other than complementary PWM mode set the BF1 bit in the MTU4 TADCR register to 0 Re Page 8 of 11 lt ENESAS RENESAS TECHNICAL UPDATE TN RX A118A E Date March 11 2015 4 A D Converter Start Request Delaying Function Linked with Interrupt Skipping The title is changed to 5 A D Converter Start Request Delaying Function Linked with Interrupt Skipping lt Before correction p 1001 gt A D converter start requests TRG4AN and TRG4BN can be issued in coordination with interrupt skipping by the ITA3AE ITA4VE ITB3AE and ITB4VE bits in the timer A D converter start request control register TADCR Figure 18 76 shows an example of A D converter start request signal TRG4AN operation when TRG4AN output is enabled during MTUn TCNT up counting and down counting and A D converter start requests are linked with interrupt skipping Figure 18 77 shows another example of A D converter start request signal TRG4AN operation when TRG4AN output is enabled during MTUn TCNT up counting and A D converter start requests are linked with interrupt skipping n 4 or 10 Note This function should be used in combination
11. itial value must be specified in the cycle buffer register and cycle register Set A D converter start request cycle Use bits BF 1 0 in the timer A D converter start request control register TADCR to specify the timing of transfer from the timer A D converter start request cycle buffer register to A D converter start request cycle register a e Specify whether to link with interrupt skipping through bits P a In er aT ITASAE ITA4VE ITB3AE and ITB4VE A elle a ac Use bits TU4AE DT4AE UT4BE and DT4BE to enable A D e Set linkage with interrupt skipping e Enable A D converter start conversion start requests TRG4AN or TRG4BN ede aoe ey aginenen Note 1 Perform TADCR setting while MTU4 TCNT is stopped Note 2 Set bit BF 1 to 0 when not in complementary PWM mode Note 3 Set bits ITA3AE ITA4VE ITB3AE ITB4VE DT4AE and DT4BE to 0 when not in complementary PWM mode Note 4 Set bits ITAS3AE 4VE and ITB3AE 4VE to 0 while interrupt skipping is prohibited A D converter start request delaying function Figure 18 74 Example of Procedure for Specifying A D Converter Start Request Delaying Function Re Page 6 of 11 lt ENESAS RENESAS TECHNICAL UPDATE TN RX A118A E Date March 11 2015 2 Basic Example of A D Converter Start Request Delaying Function Operation lt Before correction p 1001 gt Transfer from cycle buffer Transfer from cycle buffer Transfer from cycle buffer register to cycle register register to
12. own count operation b13 to b8 Reserved These bits are always read as 0 The write value should be 0 R W b15 b14 BF 1 0 MTU4 TADCOBRA B Transfer See Table 18 31 for details R W Timing Select Note Since channels 4 and 10 have the same functionality the explanation here is only for unit O Note Access to TADCR in 8 bit units is prohibited Always access this register in 16 bit units Note 1 While interrupt skipping is prohibited i e while the T3AEN and T4VEN bits and the skipping count setting bits T3ACOR and T4VCOR in the timer interrupt skipping set register TITCR are set to 0 set this bit to O Note 2 Requests to start A D converter are not issued if the setting for interlocking with interrupt skipping is made while interrupt skipping is prohibited lt Before correction p 910 gt Table 18 31 Setting of Transfer Timing by BF 1 0 Bits Bit 15 Bit 14 BF 1 BF 0 Description 0 0 Does not transfer data from the cycle set buffer register to the cycle set register 0 1 Transfers data from the cycle set buffer register to the cycle set register at the crest of the MTUn TCNT count 1 0 Transfers data from the cycle set buffer register to the cycle set register at the trough of the MTUn TCNT count 2 1 1 Transfers data from the cycle set buffer register to the cycle set register at the crest and trough of the MTUn TCNT count 2 Legend n 4o0r10 m 30r9 Note 1 Data is transferred from the cycle set buffer registe
13. r start requests are enabled during the MTUn TCNT up counting period 0 lt MTUn TCNT lt TCDR 1 A D converter start requests are enabled during the MTUnTCNT down counting period TCDR 2 MTUn TCNT 2 1 if the DT4AE or DT4BE bit is set to 1 Figure 18 75 Clear the DT4AE and DT4BE bits to 0 when not in complementary PWM mode Setting the UT4AE or UT4BE bit to 1 causes an A D converter start request to be generated at a compare match between MTUn TCNT and MTUn TADCORA MTUn TADCORB regardless of whether MTUn TCNT is counting up or down n 4 10 3 Buffer Transfer The title is changed to 4 Buffer Transfer lt Before correction p 1001 gt The data in the timer A D converter start request cycle set registers MTUn TADCORA and MTUn TADCORB is updated by writing data to the timer A D converter start request cycle set buffer registers MTUn TADCOBRA and MTUn TADCOBRB Data is transferred from the buffer registers to the respective cycle set registers at the timing selected with the BF 1 0 bits in the timer A D converter start request control register MTUn TADCR n 4 or 10 lt After correction gt The data in the timer A D converter start request cycle set registers MTUn TADCORA and MTUn TADCORB is updated by writing data to the timer A D converter start request cycle set buffer registers MTUn TADCOBRA and MTUn TADCORB Data is transferred from the buffer registers to the respective cycle set registers at the timin
14. r to the cycle set register when the crest of the MTUn TCNT count is reached in complementary PWM mode when a compare match occurs between MTUm TCNT and MTUm TGRA in reset synchronized PWM mode or when a compare match occurs between MTUn TCNT and Re Page 4 of 11 sKLKENESAS RENESAS TECHNICAL UPDATE TN RX A118A E Note 2 lt After correction gt MTUn TGRA in PWM mode 1 or normal mode Date March 11 2015 These settings are prohibited when complementary PWM mode is not selected Table 18 31 Bit15 Bit 14 BF1 BFO 0 0 0 1 1 0 1 1 Bit15 Bit 14 BF1 BFO 0 0 0 1 1 0 1 1 Legend Setting of Transfer Timing by BF 1 0 Bits Description Complementary PWM Mode Does not transfer data from the cycle set buffer register MTUn TADCOBRA MTUn TADCOBRB to the cycle set register MTUn TADCORA MTUn TADCORB Transfers data from the cycle set buffer register MTUn TADCOBRA MTUn TADCOBRB to the cycle set register MTUn TADCORA MTUn TADCORB at the crest of MTUn TCNT Transfers data from the cycle set buffer register MTUn TADCOBRA MTUn TADCOBRB to the cycle set register MTUn TADCORA MTUn TADCORB at the trough of MTUn TCNT Transfers data from the cycle set buffer register MTUn TADCOBRA MTUn TADCOBRB to the cycle set register MTUn TADCORA MTUn TADCORB at the crest and trough of MTUn TCNT Description PWM Mode 1 Does not transfer data from the cycle set buffer register MTUn TADCOBRA MTUn TADCOBRB to the
15. t requests TRG4AN disabled R W during MTU4 TCNT up count operation 1 A D converter up requests TRG4AN enabled during MTU4 TCNT down count operation b13tob8 Reserved These bits are always read as 0 The write value should be 0 R W b15 b14 BF 1 0 MTU4 TADCOBRA B Transfer See Table 18 31 for details R W Timing Select Note 1 Since channels 4 and 10 have the same functionality the explanation here is only for unit 0 Note 2 Access to TADCR in eight bit units is prohibited Always access this register in 16 bit units Note 3 While interrupt skipping is prohibited i e while the T3AEN and T4VEN bits and the skipping count setting bits T3ACOR and T4VCOR in the timer interrupt skipping set register TITCR are set to 0 do not set up interlocking with interrupt skipping i e set the ITA3AE ITA4VE ITB3AE or ITB4VE bits in the timer A D converter start request register TADCR to 0 Note 4 Requests to start A D converter are not issued if the setting for interlocking with interrupt skipping is made while interrupt skipping is prohibited Re Page 3 of 11 lt ENESAS RENESAS TECHNICAL UPDATE TN RX A118A E Date March 11 2015 lt After correction gt Address MTU4 TADCR 0008 8640h MTU10 TADCR 0008 8A40h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b1 BF 1 0 p f f UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note
16. tart request enabled interval is TCDR 2 MTUn TCNT 2 1 Clear the DT4AE and DT4BE bits in MTUn TADCR to 0 when not in complementary PWM mode Setting the UT4AE or UT4BE bit in MTUn TADCR to 1 causes an A D converter start request to be generated at a compare match between MTUn TCNT and MTUn TADCORA MTUn TADCORB regardless of whether MTUn TCNT is counting up or down n 4 10 2 Notes on A D Converter Start Request Delaying Function in Complementary PWM Mode When MTUn TADCOBRA MTUn TADCOBRB is set to 0 and the UT4AE or UT4BE bit in MTUn TADCR is set to 1 and the result is transferred to the buffer when counting by MTUn TCNT reaches its trough an A D converter start request is not generated during the up counting period immediately following the transfer Figure 2 1 When the same value as that of TCDR is set to MTUn TADCOBRA MTUn TADCOBRB and the DT4AE or DT4BE bit in MTUn TADCR is set to 1 and the result is transferred to the buffer when counting by MTUn TCNT reaches its crest an A D converter start request is not generated during the down counting period immediately following the transfer Figure 2 2 c 2015 Renesas Electronics Corporation All rights reserved Page 1 of 11 stEN ESAS RENESAS TECHNICAL UPDATE TN AIE Date March 11 2015 When A D converter start requests are linked to the interrupt skipping function set MTUn TADCORA or MTUn TADCORB to meet the condition 2 lt MTUn TADCORA or MTUn TADCORB lt TCDR 2 n
17. ter Start Request When the Same Value as TCDR is Written to MTU4 TADCOBRA Re Page 10 of 11 sLKENESAS RENESAS TECHNICAL UPDATE TN RX A118A E Date March 11 2015 Applicable Products and Reference Documents Section No Reference Document i of MTU2 RX62N 621 RX62N RX621 Group User s R01UH0033EJ0140 18 Manual Hardware RX63N 631 RX63N RX631 Group User s 23 l R01UH0041EJ0180 Manual Hardware RX630 RX630 Group User s Manual l 22 R01UH0040EJ0160 Hardware RX200 RX210 RX210 Group User s Manual R01UH0037EJ0150 21 Hardware RX220 RX220 Group User s Manual R01UH0292EJ0110 21 Hardware RX21A Group User s Manual l R01UH0251EJ0110 Hardware RX100 RX111 Group User s Manual l R01UH0365EJ0110 Hardware RX113 Group User s Manual R01UH0448EJ0102 Hardware Re Page 11 of 11 lt ENESAS
18. with interrupt skipping When interrupt skipping is disabled the T3AEN and T4VEN bits in the timer interrupt skipping set register TITCR are cleared to 0 or the skipping count set bits T3ACOR and T4VCOR in TITCR are cleared to 0 make sure that A D converter start requests are not linked with interrupt skipping clear the ITASAE ITA4VE ITB3AE and ITB4VE bits in the timer A D converter start request control register TADCR to 0 Note that TRG4ABN TRG4AN or TRG4BN is output as the A D converter start request signal in this case lt After correction gt In complementary PWM mode A D converter start requests TRG4AN and TRG4BN can be issued in coordination with interrupt skipping by making settings the ITA3AE ITA4VE ITB3AE and ITB4VE bits in the timer A D converter start request control register TADCR Figure 18 76 shows an example of A D converter start request signal TRG4AN operation when TRG4AN output is enabled during MTUn TCNT up counting and down counting and A D converter start requests are linked with interrupt skipping Figure 18 77 shows another example of A D converter start request signal TRG4AN operation when TRG4AN output is enabled during MTUn TCNT up counting and A D converter start requests are linked with interrupt skipping n 4 or 10 In modes other than complementary PWM mode do not use the A D converter start request delaying function linked with the interrupt skipping function Set the ITA3AE ITA4VE ITB3A
Download Pdf Manuals
Related Search