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Design and development of Mnemosine MK IV

1. A POLITECNI GER SEG MNEMOSINE MKIV FLIGHT TEST en ISTRUMENTATION M_FTI_SRS rev A QUO Software Requirements Specification SRS pag 25 27 ENG_HAL_FUN_004 The OPSW shall setting up static ICUConfig icucfg ICU_INPUT ACTIVE HIGH 100000 100kHz ICU clock frequency x10usec icuwidthcb icuperiodcb icuoverflowcb ICU_CHANNEL 2 ENG_HAL_FUN_005 The OPSW shall setting up palSetPadMode GPIOE 0 PAL MODE ALTERNATE 1 icuStart amp ICUD4 amp icucfg palSetPadMode GPIOD 13 PAL MODE ALTERNATE 2 ENG_COM _FUN_001 The OPSW shall the thread enters in a wait state until it receives a start on its mailbox result chMBFetch mbox amp fileBufferP WAIT TIME result could be RDY OK if a message has been correctly fetched RDY RESET if the mailbox has been reset while waiting RDY_ TIMEOUT if the operation has timed out ENG COM FUN 002 The OPSW shall if result RDY OK the thread entry in acquisition mode icuEnable amp ICUD4 ENG _EXP_FUN_001 The OPSW shall Fill the ENG _data_struct with new last period amp last_overflow MNEMOSINE MKIV FLIGHT TEST ISTRUMENTATION Software Requirements Specification SRS M_FTI_SRS rev A BLANK pag 26 27 AOE NE A MNEMOSINE MKIV FLIGHT TEST ISTRUMENTATION M_FTI_SRS rev A 8 ee A Software Requirements Specification SRS
2. ted to the group lback function associated to the MNEMOSINE MKIV FLIGHT TEST ISTRUMENTATION M_FTI_SRS rev A Software Requirements Specification SRS pag 19 27 CSP_HAL_FUN_001 The OPSW shall Create a static void adccallback CSP ADCDriver adcp adcsample_t buffer size t n CSP_HAL_FUN_002 The OPSW shall Create a static void adcerrcallback_CSP ADCDriver adcp adcerror_t err and post a error message to error thread CSP_HAL_FUN_004 The OPSW shall Setting up static const ADCConversionGroup adcgrpcfg TRUE ADC_GRP_NUM_CHANNELS adccallback adcerrorcallback 0 CR1 ADC_CR2_SWSTART CR2 ADC_SMPR2_SMP_AN9 ADC_ SAMPLE 56 ADC_SMPR1_SMP_AN14 ADC_SAMPLE_56 ADC_SMPR1_SMP_AN15 ADC_SAMPLE 56 ADC_SMPR2_SMP_AN4 ADC_SAMPLE 56 ADC_SMPR2_SMP_AN5 ADC_ SAMPLE 56 ADC_SMPR2_SMP_AN6 ADC_SAMPLE 56 ADC_SMPR2_SMP_AN7 ADC_SAMPLE 56 ADC_SMPR2_SMP_AN8 ADC_SAMPLE 56 0 SMPR2 ADC_SQR1_NUM_CH ADC_GRP_NUM_CHANNELS ADC_SOR2 SQ8_N ADC CHANNEL _IN8 ADC_SQR2_SQ7_N ADC_CHANNEL_IN7 ADC_SOR3_SQ6_N ADC_CHANNEL_IN6 ADC_SQR3_SQ5 _N ADC_CHANNEL_IN5 ADC_SOR3 SQ4_N ADC_CHANNEL_IN4 ADC_SQR3 SQ3 N ADC_ CHANNEL IN15 ADC_SQR3 SQ2 N ADC CHANNEL IN14 ADC_SQR3 SQl_N ADC_CHANNEL INQ SES l N 4 N S MNEMOSINE MKIV FLIGHT TEST Rn ISTRUMENTATION M_FTI_SRS rev A ran Software Requirements Specification SRS ii pag
3. 6 7 8 9 MNEMOSINE A FEDERATED FLIGHT TEST INSTRUMENTATION SYSTEM FOR SPORT AVIATION AIRCRAFT C Cardani A Folchini A Rolando 19th AIDAA Na tional Congress Forli Italy September 17 20 2007 R B GmbH CAN Specification Version 2 b M S F Systems CANAerospace Interface specification for airborne CAN applications V 1 7 C Technologies AHRS400 Series User s Manual F Semiconductor MPXV5004G SERIES Integrated Silicon Pressure Sensor On Chip Signal Conditioned Temperature Compensated and Calibrated Technical data 2007 F Semiconductor MPX5100 MPXV5100 SERIES Integrated Silicon Pressure Sensor On Chip Signal Conditioned Temperature Compensated and Calibrated Technical data 2005 nenn Apri 4 2013 http www designspark com April 4 2013 Olimex ltd STM32 E407 development board User Manual 10 http www freertos org April 4 2013 11 fxttp wwr chibios org dokwwik doku php April 4 2013 12 http gplv3 sf org April 4 2013 13 STMicroelectronics STM32F407xx Reference Manual 14 http dunkels com adam April 4 2013 15 http savannah nongnu org projects Iwip April 4 2013 16 ttp elm chan org fsw 00index_e html April 4 2013 17 http www okpedia it epu motorola 68000 April 4 2013 18 http gcc gnu org April 4 2013 19 http www gnu org software emacs April 4 2013 20 http www linux org April 4 2013 61 BIBLIOG
4. 00000000000 pag 23 27 SD_CAL_FUN_002 The OPSW shall if result RDY_OK the thread shall decode the message and entry in acquisition mode In this mode the thread collects and writes all the data struct in a new file every seconds SD_CAL_FUN_003 The OPSW shall keep track of byte written and update the mission record file where all error messages are stored SD_COM_FUN_002 The OPSW shall if the thread receive a FALLING message it must perform the following instruction mount 0 NULL unmount file system sdcDisconnect amp SDCD1 disconnect SDC driver in order to not corrupt the file system AOC POLITECNICO RN MNEMOSINE MKIV FLIGHT TEST IM Pa D db ISTRUMENTATION M_FTI_SRS rev A AAA gl io Software Requirements Specification SRS pag 24 27 2 6 Engine Thread Name Eng_com_thread Thread Acronym ENG Thread Priority NORMAL_PRIO 10 Pointer Input argument struct Output argument struct ENG_Data_Struct HAL reference TIM4 ETR CH2 ENG_HAL_DEF_001 The OPSW shall Define the following object uint8 t last_overflow icucnt_t last_width last_period ENG _HAL_FUN_001 The OPSW shall setting up static void icuwidthcb ICUDriver icup ENG _HAL_FUN_002 The OPSW shall setting up static void icuperiodcb ICUDriver icup ENG _HAL_FUN_003 The OPSW shall setting up static void icuoverflowcb ICUDriver icup
5. CSP 101 chThdSleepMilliseconds FLAG_CSP 10 102 sdWrite amp SD3 CSP THREAD r n sizeof CSP THREAD r n 103 103 104 105 106 107 108 109 110 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 Appendix B SVC INFINITE LOOP while TRUE result chMBFetch mbox amp fileBufferP TIME_INFINITE if fileBufferP gt t flag FLAG_CSP out csp count C end infinite loop return 0 y end thread Hah AHRS THREAD WORKING_AREA wa_ahrs 128 msg_t ahrs_com_thread void x arg GLOBAL OBJECT Mailboxx mbox Mailbox x arg msg_t result filebuffer_t fileBufferP LOCAL OBJECT INIT chRegSetThreadName AHRS chThdSleepMilliseconds FLAG_AHRS 10 sdWrite amp SD3 AHRS THREAD r n sizeof AHRS THREAD r n INFINITE LOOP while TRUE result chMBFetch mbox amp fileBufferP TIME_INFINITE if fileBufferP gt t flag FLAG_AHRS out ahrs count A end infinite loop return 0 y end thread hy CDU THREAD WORKING_AREA wa_cdu 128 msg_t cdu_com_thread void arg GLOBAL OBJECT Mailboxx mbox Mailbox x arg msg_t result filebuffer_t fileBufferP LOCAL OBJECT INIT chRegSetThreadName CDU
6. ch ThdSleepMilliseconds FLAG_CDU 10 sdWrite amp SD3 CDU THREAD r n sizeof CDU THREAD r n INFINITE LOOP while TRUE result chMBFetch mbox amp fileBufferP TIME_INFINITE if fileBufferP gt t flag FLAG_CDU out cdu count U y end infinite loop return 0 y end thread 104 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 Time Scheduler source code if WORKING_AREA wa_sd 128 SD THREAD msg_t sd_save_thread void x arg GLOBAL OBJECT Mailboxx mbox Mailbox x arg msg_t result filebuffer_t xfileBufferP A 7 LOCAL OBJECT uint8_t i SETUP chRegSetThreadName SD ch ThdSleepMilliseconds FLAG_SD 10 sdWrite amp SD3 INFINITE LOOP while TRUE SD THREAD rAn sizeof SD THREAD r n result chMBFetch mbox amp fileBufferP TIME_INFINITE if fileBufferP t sdWrite amp SD3 sdWrite amp SD3 sdWrite amp SD3 sdWrite amp SD3 sdWrite amp SD3 sdWrite amp SD3 sdWrite amp SD3 sdWrite amp SD3 sdWrite amp SD3 sdWrite amp SD3 sdWrite amp SD3 sdWrite amp SD3 sdWrite amp SD3 flag FLAG_SD r nAHRS sizeof r nAHRS out ahrs sizeof out ahrs t nCSP gt sizeot r nOSP out csp sizeo
7. extern WORKING_AREA wa_air 128 msg_t air_com_thread void x arg 101 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 OCOAN DTK Wn m FE WWWwWwWwWwwWwWwWwWwowWwNnn nN NNN NNNMNN HP FP RP BP RP RP PR PP kK FOO AN DT KR WNrF TDHO AN DAK WNrF TKO AN De K WN Hm oO Appendix B SVC extern WORKING_AREA wa_sf 128 msg_t sf_com_thread void xarg extern WORKING_AREA wa_csp 128 msg_t csp_adc_thread void x arg extern WORKING_AREA wa_ahrs 128 msg_t ahrs_com_thread void x arg extern WORKING_AREA wa_cdu 128 msg_t cdu_com_thread void xarg extern WORKING_AREA wa_sd 128 msg_t sd_save_thread void x arg endif GLOBAL H_ x global c include ch h include hal h include global h include chsprintf h i GPS THREAD WORKING_AREA wa_gps 128 msg_t gps_com_thread void x arg GLOBAL OBJECT Mailboxx mbox Mailbox x arg msg_t result filebuffer_t fileBufferP LOCAL OBJECT INIT chRegSetThreadName GPS ch ThdSleepMilliseconds FLAG_GPSx10 sdWrite 85D3 GPS THREAD r n sizeof GPS THREAD r n INFINITE LOOP while TRUE result chMBFetch mbox amp fileBufferP TIME_INFINITE if fileBufferP gt t flag FLAG_GPS out gps count G end infinite loop return 0 y end thread m AIR THREAD WORKING_AREA wa_air 128 msg_t air_com_thread void x arg GLOBAL OBJECT Mailboxx mbox
8. 000 120000000 pag 27 27 3 ACRONYM LIST GPS Global Positioning System OAT Outer Air Temperature AOA Angle Of Attack AOS Angle Of Side sleep ECEF Earth Centered Earth Fixed RPM Rotation Per Minute EGT Exhaust Gas Temperature SD Secure Digital Card ETH Ethernet CAN Controller Area Network 12 Inter Integrated Circuit USB Universal Serial Bus RDY Ready Appendix B SVC Serial Driver source code include ch h include hal h Application entry point int main void Oo oND AUNE DNDNDNDNDNDwHHLOOEH HR HR HH en HH 000 1900 PR WN Ho hallnit chSysInit Activates the serial driver 3 using the driver default configuration PD8 TX and PD9 RX are routed to USART3 7 sdStart amp SD3 NULL palSetPadMode GPIOD 8 PAL_MODE_ALTERNATE 7 palSetPadMode GPIOD 9 PAL_MODE_ALTERNATE 7 while TRUE sdWrite amp SD3 hello world r n sizeof hello world r n palTogglePad GPIOC GPIOC_LED chThdSleepMilliseconds 1000 91 O oND KF Wn a a aaa AA A br BP BKK SBP WWW WWWWWwWwWwWNnNn nD NNN NNNN HP PRP KP PRP RP RP PrP hI Dd MNMRA4AONAIOCDOO Sao aa oO NAOODoOoOO I OUT AOUN HT OO OO I OS UT AOUN HM OO OO Sao aa wNnNrono Appendix B SVC USART UART Driver source code Zinehide ch a HAinclude hal h static VirtualTimer vti vt2 static void restart void xp void p chSysLockFrom
9. 20 27 CSP_HAL_FUN_004 The OPSW shall Setting up palSetGroupMode GPIOF PAL PORT _BIT 3 PAL _PORT_BIT 4 PAL PORT_BIT 5 PAL PORT BIT 6 PAL PORT _BIT 7 PAL PORT BIT 8 PAL PORT BIT 9 PAL PORT BIT 10 0 PAL _MODE_INPUT_ANALOG CSP_HAL_FUN_004 The OPSW shall Setting up ADC driver adcStart amp ADCD1 NULL CSP_COM FUN_001 The OPSW shall the thread enters in a wait state until it receives a start on its mailbox result chMBFetch mbox amp fileBufferP WAIT_TIME result could be RDY OK if a message has been correctly fetched RDY RESET if the mailbox has been reset while waiting RDY_ TIMEOUT if the operation has timed out CSP_COM_FUN_002 The OPSW shall if result RDY OK the thread shall decode the message and entry in acquisition mode adcStartConversion amp ADCD1 amp adcgrpcfg CSP CSP_samples ADC_CSP_GRP_BUF_DEPTH CSP_EXP_FUN_001 The OPSW shall Fill the CSP_data_struct with new CSP_samples EN POLITECNICO Ra DI MILANO MNEMOSINE MKIV FLIGHT TEST ue 52 N ISTRUMENTATION SS Software Requirements Specification SRS 2 5 Secure Digital M_FTI_SRS rev A pag 21 27 Thread Name sd_save thread Thread Acronym SD Thread Priority NORMAL_PRIO 10 Pointer Input argument struct Output argument struct SD _Data_Struct HAL reference MMC_SDIO SD_HAL_DEF_001 The OPSW
10. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Appendix B SVC 12C Driver source code include ch h include hal h include chprinti h 1DG3205 3D rate gyro define GYRO RX DEPTH 6 define GYRO TX DEPTH 2 define GYRO_ON 0x53 define GYRO ZERO 0x52 define GYRO REC 0x52 define steps per_deg_ slow 40 define steps per deg fast 4 msg_t status RDY_OK systime_t tmo MS2ST 20 int16_t yaw pitch roll int16_t yaw0 0 pitch0 0 rol10 0 void wmpOn void send 0x04 to address OxFE to activate IDG3205 uint8_t txbuf GYRO_TX_DEPTH uint8_t rxbuf GYRO_RX_DEPTH txbuf 0 OxFE txbuf 1 0x04 i2cAcquireBus amp 12CD2 status i2cMasterTransmitTimeout amp 12CD2 GYRO_ON txbuf GYRO_TX_DEPTH rxbuf 0 tmo i2cReleaseBus amp 12CD2 void receiveData void uint8_t rxbuf GYRO_RX_DEPTH three axes calibration zeroes register address send zero before each request request the six bytes from IDG3205 i2cAcquireBus amp I12CD2 status i2cMasterTransmitTimeout amp 1I2CD2 GYRO_REC 0x00 i2cReleaseBus amp 12CD2 te Crxbut Aa steps_per_deg_slow 1 rxbuf 6 tmo 1 yau rxbuf 3 gt gt 2 lt lt 8 rxbuf 0 yaw0 else yaw rxbuf 3 gt gt 2 lt lt 8 rxbuf 0 yaw0 steps_per_deg_fast if rxbuf 3 1 lt lt 0 1 piteh rxbuf 4 gt gt 2 lt lt 8 rxbu
11. 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 ADC Driver source code sdStart amp SD3 NULL palSetPadMode GPIOD 8 PAL_MODE_ALTERNATE 7 palSetPadMode GPIOD 9 PAL_MODE_ALTERNATE 7 Setting up analog inputs used by the demo palSetGroupMode GPIOF PAL_PORT_BIT 3 PAL_PORT_BIT PAL_PORT_BIT 5 PAL_PORT_BIT PAL_PORT_BIT 7 PAL_PORT_BIT PAL_PORT_BIT 9 PAL_PORT_BIT Activates the ADC3 driver and the thermal sensor x adcStart amp ADCD3 NULL Starts an ADC continuous conversion adcStartConversion amp ADCD3 amp adcegrpcfg samples ADC_GRP_BUF_DEPTH N W 0 4 6 8 10 0 PAL_MODE_INPUT_ANALOG NNN while TRUE uint8_t i j char val 7 for i 0 i lt 16 i for j 0 j lt sizeof val j val j J chsprintf amp val 0 Xd samples i sdWrite amp SD3 val sizeof val sdWrite amp SD3 r n 2 palTogglePad GPIOC GPIOC_LED chThdSleepMilliseconds 1000 95 O oND AUNE a a AAA A BP qe qe e SR WwWWWWwWwWwwWwwWnNn nN NNN NNNN HP o ppp DO PVONDHMOVO Oo I oDarWwNrFoUdAnN Dour wWwNnNrFodoUDdoAOANoaa 4rkWwWwnNrdoevVueweanoaunrwNnNro Appendix B SVC SDIO Driver source code inehide ch h HAinclude hal h include chprintf h Zinchrde tf h FatFs related Qbrief FS object x static FATFS SDC_FS FS mounted and ready x static bool_t fs_ready
12. buffer size_t n void adcp ADC error callback do nothing x static void adcerrorcallback ADCDriver x adcp adcerror_t err void adcp void err ADC conversion group Mode Continuous 16 samples of 8 channels SW triggered Channels INQ IN14 IN15 IN4 IN5 IN6 INT INS x ADC3 IN9 PF3 ADC3_IN14 PF4 ADC3_IN15 PF5 ADC3_IN4 PF6 ADCS INE PEF ADC3_IN6 PF8 ADC3 IN7 PF9 ADC3_IN8 PF10x static const ADCConversionGroup adcgrpc g TRUE ADC_GRP_NUM_CHANNELS adccallback adcerrorcallback 0 CRI w ADC_CR2_SWSTART OR2 ADC_SMPR2_SMP_AN9 ADC_SAMPLE_56 ADC_SMPR1_SMP_AN14 ADC_SAMPLE_56 ADC_SMPR1_SMP_AN15 ADC_SAMPLE_56 ADC_SMPR2_SMP_AN4 ADC_SAMPLE_56 ADC_SMPR2_SMP_AN5 ADC_SAMPLE_56 ADC_SMPR2_SMP_AN6 ADC_SAMPLE_56 ADC_SMPR2_SMP_AN7 ADC_SAMPLE_56 ADC_SMPR2_SMP_AN8 ADC_SAMPLE_56 0 SMPR2 x ADC_SQR1_NUM_CH ADC_GRP_NUM_CHANNELS ADC_SQR2_SQ8_N ADC_CHANNEL_IN8 ADC_SQR2_SQ7_N ADC_CHANNEL_IN7 ADC_SQR3_SQ6_N ADC_CHANNEL_ING ADC_SQR3_SQ5_N ADC_CHANNEL_IN5 ADC_SQR3_SQ4_N ADC_CHANNEL_IN4 ADC_SQR3_SQ3_N ADC_CHANNEL_IN15 ADC_SQR3_SQ2_N ADC_CHANNEL_IN14 ADC_SQR3_SQ1_N ADC_CHANNEL_IN9 Application entry point int main void hallnit chSysInit Activates the serial driver 3 using the driver default configuration x PD8 TX and PD9 RX are routed to USART3 94 57 58 59 60 61 62 63 64 65 66 67
13. received The second Secure Digital Input Output is an advanced standard for this type of memories which uses several communication lines in order to improve the speed of reading or writing procedures In an attempt to evaluate whether increased complications in the communication protocol were acceptable different comparison tests were made using the same hardware and high level software oS SDIO 4 gt lt PI 1407 1207 1007 Time ms 80 60 407 20 r A r ng r ma 51 Byte Figure 2 10 SPI vs SDIO As expected communication through SDIO interface is much more efficient than the sp Graph obtained using Scilab http www scilab org April 4 2013 25 2 Hardware Realization 2 6 Air Data Computer It is the only external module of system Mnemosine MK IV indeed to avoid a long linkage pipe for the weak pressures detected by taps It was decided to maintain it as unique external module in order to facilitate as much as possible the phase of integration on the aircraft It uses the same Urania sensors Mnemosine MK III and communicates via I C with the main board e As differential pressure transducer to measure the dynamic pressure it is used the HCLA0050EU 5 made by Sensor Technics Its main features are Range 0 to 50 hPa Max pressure 1200 hPa Temperature range 25 C to 80 C Sensitivity 80 mV hPa e As total pressure transducer to measure
14. use the Olimex STM32 development board E407 equipped with STM32F407ZG 9 This choice is justified by the presence of connectors for devices including also the slot for SD card and Ethernet interface the presence of hardware abstraction layer HAL for ChibiOS RT Its main features are e Joint Test Action Group JTAG connector with ARM 2x10 pin layout for program ming debugging e Ethernet 100Mbit UEXT connector e USB host USB On The Go OTG e SD card Input e DC DC power supply which allows operation from 6 V to 16 V source Power and User LEDs e Reset and User buttons e 4 full 20 pin Ports with the external memory bus e Dimensions 101 6 x 86 mm 16 2 2 Power Supply Section 2 2 Power Supply Section The power supply circuit must ensure an adequate stabilized voltage during all phases of flight tests Especially during the critical phase of engine startup To meet this requirement it s necessary to provide a separate power supply that can be replaced by the voltage coming from the aircraft during the flight The circuit must also ensure a minimum period of time which provides energy to Mnemosine MK IV even if the power fails If this happens the board shall immediately notify to the microcontroller in order to follow the emergency power falling procedure Controlled Power Supply Lines MCU External Battery Rotary Switch light Indicators from CDU to CDU Figure 2 4 Power Supply Diagram 17 2 Hardw
15. 5T features a Time Mode function whereby the GPS receiver assumes a stationary 3D position either manually programmed or determined by an initial self survey Stationary operation enables GPS timing with only one visible satellite and eliminates timing errors which otherwise would result in positioning errors The accuracy of the time pulse is as good as 30 ns synchronized to GPS or UTC time An accuracy of 15 ns is achievable by using the quantization error information to compensate the granularity of the time pulse A built in time mark and counter unit provides precise time measurement of an external signal EXTINTO input Main features e 50 channel U Blox 5 engine with over 1 million effective correlators e Hybrid GPS GALILEO and Satellite Based Augmentation System SBAS engines like WAAS EGNOS MSAS GAGAN e lt 1 second Time To First Fix for hot and aided starts e Stationary mode for GPS timing operation e Super sense indoor GPS with best in class acquisition and tracking sensitivity e Output time pulse with at least one satellite in view Figure 2 16 U Blox LEA XT 30 2 11 CDU Command and Display Unit 2 11 CDU Command and Display Unit Inside the aircraft the operator has two CDUs The first controls the power supply circuits of Mnemosine MK IV and contains the recording switch Figure 2 17 CDU Rendering In order to facilitate the integration of CDU it was decided to design it into a classical 3
16. 80 C 2 4 1 Noise Filter Figure 2 6 Noise Filter schematic Before the signals are acquired by the DAC Digital to Analog Converter site internally in the microcontroller it s necessary to filter those that are obviously the more noisy signals within the system Mnemosine The Sallen Key filter is used with cutoff frequency less than or equal to half of the frequency sampling For this type of active filter is provided an algebraic formula to calculate the cut off frequency 1 Fe 2r VC1C2R1 Ra By suitably choosing the values of capacitance and resistance it is obtained C1 Ca 100 nF R Ra 180 KQ Fe 9 Hz 21 2 Hardware Realization 2 4 2 Schematics of Analog Signal Conditioning Module To ensure electrical isolation between potentiometer and microcontroller it has been studied the use of analog photocoupler This device costs of a high brightness light emitting diode and two photodiodes tightly cou pled from the logical point of view the input signal a voltage allows the passage of current through the photoemitter that thanks to a simple feedback circuit emits a signal bright directly proportional to the signal itself At this point the second photodiode transposes the same light signal and reconverted it into a current signal that can be reconstructed from the last operational that actually remains isolated from the first This component is produced by Avago with code HCNR20x whose performances are 27
17. CABLE Figure 2 13 Futek MU300 27 2 Hardware Realization This subsystem is composed of a load cell produced by Futek and load cell embedded digitiser also called DSC produced by Mantracourtp The load cell gathers the stick forces in both directions while the DSC allows complete processing of the signals coming from the strain gauges 1t also transmits data already engineered via serial protocol to Mnemosine MK IV DSCHMCANo 208626 MANTRACOURT ELECTRONICS LIMITED www mantracourt co uk Manufactured in the UK CE Figure 2 14 Mantracourt DSC Load Cell Embedded Digitiser http www futek com April 4 2013 http www mantraconrt com April 4 2013 28 2 9 2 9 Inertial Data Inertial Data To capture the inertial flight data it is necessary to use an AHRS It was choosed the MTi Xsens 31 The MTi is a miniature gyro enhanced Attitude and Heading Reference System Its internal low power signal processor provides drift free 3D orientation as well as calibrated 3D acceleration 3D rate of turn and 3D earth magnetic field data The MTi is an excellent measurement unit IMU for stabilization and control of cameras robots vehicles and other un manned equipment The main features of MTI are Real time computed attitude heading and inertial dynamic data 360 orientation refer enced by gravity and Earth Magnetic Field Integrated 3D gyroscopes accelerometers and magnetometers On boar
18. FALSE Generic large buffer static uint8_t fbuff 1024 FRESULT err rc uvint32_t clusters FATFS fsp FIL Fil char fold char path UINT bw MISSIONOO MISSIONO0 LOGOO dat Application entry point int main void BaseSequentialStream xchp uint8_t j hallnit chSysInit Activates the serial driver 3 sdStart amp SD3 NULL palSetPadMode GPIOD 8 PAL_MODE_ALTERNATE 7 palSetPadMode GPIOD 9 PAL_MODE_ALTERNATE 7 chp amp SD3 xand SDC driver 1 using default configuration x sdcStart amp SDCD1 NULL while TRUE palTogglePad GPIOC GPIOC_LED chThdSleepMilliseconds 500 SDIO TEST if palReadPad GPIOA GPIOA_BUTTON_WKUP mount filesystem sdcConnect amp SDCD1 f_mount 0 amp SDC_FS info about SDC err f_getfree amp clusters amp fsp if err FR_OK chprintf chp FS f getfree failed r n return 0 96 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 SDIO Driver source code chprintf chp FS lu free clusters lu sectors per cluster lu bytes free r n clusters uint32_t SDC_FS csize clusters uint32_t SDC_FS csize uint32_t MMCSD_BLOCK_SIZE Create a new folder for j 0 j lt 100 j fold 7 j 10 0 fold 8 j 10 0 rc f_mkdir fold if re FR OR A path 7 j 10 0 path 8 j 10 0
19. Mailbox x arg msg_t result 102 Time Scheduler source code 42 filebuffer_t fileBufferP 43 44 LOCAL OBJECT 45 46 INIT 47 chRegSetThreadName AIR 48 chThdSleepMilliseconds FLAG_AIR 10 49 sdWrite amp SD3 AIR THREAD r n sizeof AIR THREAD r n 50 51 INFINITE LOOP 52 while TRUE 53 result chMBFetch mbox amp fileBufferP TIME_INFINITE 54 if fileBufferP gt t flag FLAG_AIR out air count R 55 end infinite loop 56 return 0 57 Y end thread 58 59 60 6l SF THREAD 62 WORKING_AREA wa_sf 128 63 msg_t sf_com_thread void arg 64 65 66 GLOBAL OBJECT 67 Mailboxx mbox Mailbox arg 68 msg_t result 69 filebuffer_t fileBufferP 70 71 LOCAL OBJECT 72 73 INIT 74 chRegSetThreadName SF 75 chThdSleepMilliseconds FLAG_SF 10 76 sdWrite amp SD3 SF THREAD r n sizeof SF THREAD r n 77 78 INFINITE LOOP 79 while TRUE 80 result chMBFetch mbox amp fileBufferP TIME_INFINITE 81 if fileBufferP gt t flag FLAG_SF out sf count S 82 end infinite loop 83 return 0 84 Y end thread 85 86 87 88 CSP THREAD 89 WORKING_AREA wa_csp 128 90 msg_t csp_adc_thread void x arg 91 92 GLOBAL OBJECT 93 Mailboxx mbox Mailbox arg 94 msg_t result 95 filebuffer_t fileBufferP 96 97 LOCAL OBJECT 98 99 INIT 100 chRegSetThreadName
20. Peake A A gages 13 Oh ie ee ie Ge es a ow hh as wo E 14 2 3 STM32E407 Layout 2 ee 16 E ee ee a bee a ee ae 17 agas Ena 19 2 6 Noise Filter schematic ee 21 2 7 Schematics of Analog Signal Conditioning Module 22 Bie ian Sete eee ne 23 2 9 3D PCB of Analog Signal Conditioning Module 23 Cd Dhak aw Ada hae oS ee Do eh doe ee eh ee ed 25 2 11 HCLA Pressure Sensors Family aoaaa aa 26 NE ee 27 2 13 Fatek MU300 00000 a a a Ea ee 27 pipes ote en 28 2 15 Xsens MII oe 34 ate Sl ad Ben ee we e e EA a A ee a 29 Soe get dh Bao ee en de Be di et a i Sh Brit a el 30 ato Bk See a Se eh oy dow ed Wade eee ee a a 31 3 1 ChibiStudio screen shot o 36 SW EER A EEE re re ed Ee A ee eS 39 ed WEE aaa A ey ae ws ane AE ah She de Bo 41 BA SD driver z sears 20000 osa ewe a ds na 41 3 5 VART driver 4 a o a ae a a A a a a AS 42 Seige a My hoe A A tas 42 A Ge Bs ott te A dies Ps ne A die A tent 42 8 8 ADC AHVEN oa a 44 8 a a a RE Re oe A E Ee Ew h 43 39 TPO driver AE 44 3 10 Overall Software Configuration Flowchart aooo aaa a 45 a eect BRE gre he aos geeks weal aha ks 48 be ha a Suet Godot Ge Beet ee cada E 49 4 3 ADC Driver SVC Flowchart 222222 2 oo non nn 51 4 4 SDIO Driver SVC Flowchart 2 0 0 0 000000000 a 52 LIST OF FIGURES 4 5 Time Scheduler SVC Flowchart 2 0 es 53 4 6 Input Capture SVC Flowchartl 2 222 22 Coon on nn 55 4 7 CAN Driver SVC
21. RA R SF Shey tea er SI es SI E SAN E A SIA IS S GPS AG fee ay SA by Ra om C a E E Ce Ee as a ee G CDU U U U U As it s visible from the results ChibiOS proves to be able to fully meet the time scheduling requirements 54 4 6 Input Capture SVC 4 6 Input Capture SVC The purpose of this demo is to verify the functionality of the ChibiOS RT ICU Driver with the board STM32E407 in order to simulate the capture of enigine s RPM While the demo is running after connecting a USB TTL converter from PC to PD11 TX data and applying a square wave to PD pin 16 the thread every 200 ms shows on the terminal the period of wave and in case of timer overflow it displays overflow 1 It should be noted once again that all timer interrupts are hardware interrupts so the CPU is completely free HAL Init ChibiOS Init Start Serial Driver 3 Start ICU Driver 4 Capture Period Width Update Sampe Data Write Samples Sleep 200 ms Figure 4 6 Input Capture SVC Flowchart After having extensively tested the software the ICU operational requirements are deemed satisfied 55 4 Hardware amp Software Suitability Validation Code 4 7 CAN SVC The purpose of this demo is to verify the functionality of the ChibiOS RT CAN Driver with the board STM32E407 The demo uses two different threads the transmitter and the receiver Every half a second transmitter sends
22. Realization 2 1 Development board 2 1 1 SIM32F407 sa E ae ee ee ee nee 2 3 Multi Mode Serial Peripheral Interface 2 22 2m ann nenn te ler dl ad ide de Oe 6 24AT Noise Filter u 22 02 2 Kaeo arras e Rad 2 4 2 Schematics of Analog Signal Conditioning Module ik PEGE Sew ee Ghee a ee eee ee oa a 2 5 Secure Digital Card 2 6 2 5 1 SPI vs SDIO Air Data Computer xi xiii O 0 0 Ny OF OF oOo A UOV Nhe me MH Rh 13 15 15 17 18 21 21 22 22 24 25 26 CONTENTS 2 0 Engine Data ea oa 2440 4 iruri dgan kada tko Eee ann 2 8 Stick Force Data ak a asa aon Ha Da ee Bw a a be el ela oes 2 9 Inertial Data coc osanna keha kA e a e a a e a a art 2 10 GPS Data 2 11 CDU Command and Display Unity 24 64 vu ear A 3 Software Realization 3 1 Real Time Operating System 2 222222 on nn nn 3 1 1 Choosing the RTOS 2 2 2 2 2 2 nn n onen 3 2 Development Environment 22222 2 nn nn 3 3 Thread definitions High Level Software Requirements 33 MALO ack a a Bow Ge ee eae we ew OR a PO ed 33 2 lime scheduler corporate ee a ee 333 SD thread Varas Rh ARE Ra Ree eR ew 3 3 4 Ethernet thread 2 222 nn nn nn 33 9 CAN thread e s 244 4 2 au au a RRA E wa era 330 GPS thre dl scp a a e Bae OU ew a a 3 3 7 Stick force thread 2 2 ee 3 3 8 AHRS thread 2 san 4a a Pea he eRe A 3 3 9 CDU thread 3 4 0 0 Gag ee 28 SH an a Dh ae 3 3 10 C
23. a message on the CAN bus configured in loopback mode the message is transposed by receiver that flashes the LED HAL Init ChibiOS Init Y Start CAN Driver 1 Create CAN RX Thread Create CAN TX Thread CAN RX Thread Init CAN TX Thread Init TRUE Sleep 500 ms Y Y RX message meer TX message l l l l 4 CAN Driver amp Y Toggle Led Sleep 500 ms Figure 4 7 CAN Driver SVC Flowchart After having extensively tested the software the CAN operational requirement is deemed satisfied 56 4 8 PC SVC 4 8 I C SVC The purpose of this demo is to verify the functionality of the ChibiOS RT P C Driver with the board STM32E407 in order to acquire the three angle rates provided by IDG600 3D mems rate gyro While the demo is running after connecting a USB TTL converter from PC to PD11 TX data and PD12 RX data and the gyro to the 12C2 driver PFpin3 amp 4 the thread shows on the terminal every 50 ms the yaw pitch and roll rates HAL Init Start Serial Driver 3 Setting MCU Pad Setting MCU Pad 12C Mode Serial Mode Activate IDG600 ChibiOS Init Start I2C Driver 2 Calibrate Zeros Receive Gyro Information Write Gyro Message Sleep 50 ms Figure 4 8 PC Driver SVC Flowchart After having extensively tested the software the I C operational requirement i
24. break write data rc f_open amp Fil path FA_OPEN_ALWAYS FA_WRITE re f_write amp Fil FTI data r n sizeof FTI data r n amp bw re f_close amp Fil unmount filesystem f_mount 0 NULL sdcDisconnect amp SDCD1 97 O oND KF WN HH a a aAa aAA A fF BP BPSK SBP WWW WWW WWW DD NNN NNNN HP KP RP KP RP RP RP RP hI O vokrwnNnrFoeUnuoaAnNnNt O9 UV AOUN HMO VO OD I VG AOUN HT ODO Oo UT PWDND HM OVO OO I OO a oyNR A Oo Appendix B SVC Time Scheduler source code main c Zinchide ch hb include hal h include global h Mailbox mbox_AHRS msg_t mbox_buf_AHRS 1 Mailbox mbox_CSP msg_t mbox_buf_CSP 1 Mailbox mbox_AIR msg_t mbox_buf_AIR 1 Mailbox mbox_SF msg_t mbox_buf_SF 1 Mailbox mbox_GPS msg_t mbox_buf_GPS 1 Mailbox mbox_CDU msg_t mbox_buf_CDU 1 Mailbox mbox_SD msg_t mbox_buf_SD 1 Global Object int16_t count output_t out msg_t time_dispenser void Triggered when the WakeUP button is pressed static void extcb1 EXTDriver extp expchannel void extp void channel count 0 gptStartOneShotI amp GPTD2 TIMER_PRE time_dispenser static const EXTConfig extcfg 98 EXT_CH_MODE_RISING_EDGE EXT_CH_MODE_AUTOSTART EXT_CH_MODE_DISABLED EXT_CH_MODE_DISABLED EXT_CH_MODE_DISABLED EXT_CH_MODE_DISABLED EXT_CH_MODE_DISABLED EXT_CH_MODE_DISABLED EXT_CH_MODE_DISABLED EXT_CH_MODE_DISABLED EXT_CH
25. el 0 while chThdShouldTerminate if chEvtWaitAnyTimeout ALL_EVENTS MS2ST 100 0 continue while canReceive amp CAND1 amp rxmsg TIME_IMMEDIATE RDY_OK Process message palTogglePad GPIOC GPIOC_LED chEvtUnregister amp CAND1 rxfull_event amp el return 0 Transmitter thread x static WORKING_AREA can_tx_wa 256 static msg_t can_tx void p CANTxFrame txmsg void p chRegSetThreadName transmitter txmsg IDE CAN_IDE_EXT txmsg EID 0x01234567 txmsg RTR CAN_RTR_DATA txmsg DLC 8 txmsg data32 0 Ox55AA55AA txmsg data32 1 Ox0O0FFOOFF while chThdShouldTerminate canTransmit amp CAND1 amp txmsg MS2ST 100 chThdSleepMilliseconds 500 return 0 108 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 CAN Driver source code Application entry point int main void hallnit chSysInit Activates the CAN driver 1 x canStart amp CAND1 amp cancfg Starting the transmitter and receiver threads chThdCreateStatic can_rx_wa sizeof can_rx_wa NORMALPRIO 7 can_rx NULL chThdCreateStatic can_tx_wa sizeof can_tx_wa NORMALPRIO 7 can_tx NULL Normal main thread activity in this demo it does nothing while TRUE chThdSleepMilliseconds 500 return 0 109 O oND AUNE N NN NYNNNNNKRP RRP BP BP RPP HH HH NO TOR WNrF OKO AN DAF WHF OC 28
26. from airplane to ground 3 3 5 CAN thread The CAN thread should configure hardware abstraction layer and ChibiOS s CAN module The CAN driver implements a state machine internally not all the driver functionalities can be used in any moment any transition not explicitly shown in the following diagram has to be considered an error http savannah nongnu org projects lwip April 4 2013 40 3 3 Thread definitions High Level Software Requirements canStart other thread se tae canStart initialization compkte i canReceive all threads P canTransmit Initializing canStart canSkep slow implementation canStop canSkep hardware wakeup event CAN_SLEEP Low Power canStart fast implementation CAN_READY Clock Enabled CAN_STOP Figure 3 3 CAN diagram 3 3 6 GPS thread The GPS thread should configure hardware abstraction layer and ChibiOS s SD Serial Driver module The thread is generally divided into 2 parts the initialization should perform a commu nication test that checks the GPS operation while the infinite loop is freed from time scheduler every 200 ms 5 Hz it requires GPS data and check its integrity Any I O operation sdStart sdStop SD_READY sdInit SD_STOP sdStart Clock Enabled Low Power sdStop Figure 3 4 SD driver 3 3 7 Stick force thread The stick force thread should confi
27. kg for snow configuration and 650 kg for amphibious operations Stall speed V so must not exceed 65 km h Calibrated Air Speed CAS VHF radio with A or C mode Transponder and ELT They aren t subject to altitude limits imposed on the ULM being able to take full advantage of all air navigation services in the same mode and the same obligations as other aircraft although they should conduct their flights outside the controlled airspace by the airport traffic areas at a safe distance from obstacles and with not less than 5 km of distance from the airport Therefore registered advanced ULM can fly in uncontrolled air space with Visual Flight rules VFR equivalent to those of general aviation few times night VFR Both ULM and Advanced ULM may be certified according to CS LSA or CS VLA although in Italy as in other countries of Europe is not formally required This helps in keeping the overall cost of these planes very low allowing a large diffusion of these aircrafts For this reason normally no systematic flight test activity is planned by the manufacturing companies as a part of the design development and production process but it is an activity that is mandatory if the company wants to certify the aircraft in compliance with EASA or DPR 133 2010 Even when flight test is performed it is generally carried out adapting to the task some kind of general purpose PC based data acquisition system Such systems tend to be b
28. name C Documents and Settings Federico Desktop build ch bin File size 13 62 KB 13948 bytes Status 13 62 KB 13948 bytes of 13 62 KB 13948 bytes Time 00 00 04 Download operation finished successfully Back Cancel Close Figure 5 6 Flash Loader Demonstrator 5 120
29. non linearity under 0 01 as ratio between the current input and output with 5 of transfer gain wide bandwidth from DC up to 1 MHz and worldwide safety approval UL 1577 recognized minimum isolation guaranteed of 5 kV rms for 1 min 2 4 3 PCB Using Design Spark PCB 8 it is possible to draw both the schematics and PCB also in 3d view fonda iggd pin cann Pon aH Foc 5 2 od 4 Syne rane KERERE Figure 2 7 Schematics of Analog Signal Conditioning Module 22 2 4 Analog Signal Conditioning Module RO poo 000 o 0000 TTE OOO FOO O ONIN de re 90 olostolo o o ozaelo o 00 ollo OJO Ola 5 O O O 0000000000000 Figure 2 9 3D PCB of Analog Signal Conditioning Module 23 2 Hardware Realization 2 5 Secure Digital Card This is the real physical memory of Mnemosine MK IV that takes its name from its characteristic to allow the protection of data stored in it This feature is also called key revocation and allows reading only by specific readers Specially developed to store information very quickly it is currently the digital memory of smallest size The main characteristics of a typical uSD on the market are e Dimension 15 mm x 11 mmx 1 mm e Default mode 0 25 MHz up to 12 5 MB s interface speed e High speed mode 0 50 MHz up to 25 MB s interface speed e Temperature range 25 C a 85 C e Free fall 1 5 m e MTBF gt 170007000 h e Voltage supply 2 7 V a 3
30. of the received data GPS_COM_FUN_001 The OPSW shall the thread enters in a wait state until it receives a start on its mailbox result chMBFetch mbox amp fileBufferP WAIT TIME result could be RDY OK if a message has been correctly fetched RDY RESET if the mailbox has been reset while waiting RDY_ TIMEOUT if the operation has timed out GPS_COM_FUN_002 The OPSW shall if result RDY OK the thread shall decode the message and entry in acquisition mode uartStartReceive amp GPS USART_DRIVER size_t n void GPS_rxbuf GPS_CAL_FUN_001 The OPSW shall Convert GPS_rxbuf in to GPS data and check its integrity GPS_EXP_FUN_001 The OPSW shall Fill the GPS Data_ Struct with new GPS_data O POLITECNICO GER MNEMOSINE MKIV FLIGHT TEST ie D ecc ISTRUMENTATION M_FTI_SRS rev A SS Software Requirements Specification SRS pag 14 27 2 3 Stick Force data Thread Name sf_com_thread Thread Acronym SF Thread Priority NORMAL_PRIO 10 Pointer Input argument struct Output argument struct SF_Data_Struct HAL reference USART 6 SF_HAL_DEF_001 The OPSW shall Define the following object GPIO_BASE_SF GPIO_RX SF GPIO_TX SF GPIO BASE PIN A SF GPIO_A GPIO BASE PIN B SF GPIO_B GPIO BASE PIN C SF GPIO_C GPIO BASE PIN D SF GPIO_D GPIO BASE PIN OUT_SF GPIO_OUT GPIO BASE PIN IN SF GPIO_IN SF_USART_DRIVER SF_USART_SPEED SF_USART_CR
31. of this demo is to verify the functionality of the ChibiOS RT EXT and GPT Drivers with the board STM32E407 in order to simulate the Time Scheduler thread While the demo is running after connecting a USB TTL converter from PC to PD11 TX data and PD12 RX data the Time Scheduler test is performed if WakeUP button is pushed All timer interrupts are hardware interrupts so the CPU is free to execute threads instructions during the message post All the threads do nothing but write their own identifier character in the output structure shown on the terminal at the end of execution HAL Init Write A Time Dispenser Fuction Mail Box Fetch ChibiOS Init Start Serial Driver 3 Figure 4 5 Time Scheduler SVC Flowchart Write C Write R Write S Write G Setting MCU Pad Serial Mode Start Timer 2 Start EXT Interrupt Sleep 1000 ms 53 OMAN Do K WN Pee PP Pe aow r wn rer O 4 Hardware amp Software Suitability Validation Code Serial dev ttyUSBO 38400 8 1 None None CONNECTED AHRS THREAD CSP THREAD AIR THREAD SF THREAD GPS THREAD CDU THREAD SD THREAD AHROWA SAS RSS ASA ASAS SWEET RSS IIND AACA SAC DEN CASA A ASA AMAA SAN hae AS AA AER COEM Game tate CASO CS CSC CASO CO RC CIO Senet Ss IS O ES O ACR aR ey tee eee RARE RAS REA RECAM RARAS RAREZAS
32. sleep 200 monitor flash write_image erase project_loc build ch bin 0x08000000 bin monitor sleep 200 monitor reset init JTAG e Load image no image e load symbols use project binary build ch elf e Apply and Close After setup the hardware it s possible to switch Eclipse in Debug Mode Run External Config uration and select OpenOCD 0 6 on Olimex Arm Usb Tiny H prompts for cfg target configu ration Debug and select OLIMEX STM32E407 demo_0 OpenOCD Flash and Run Now the project is loaded in the microcontroller This procedure is considered to be well founded therefore will be omitted from future demos 117 Appendix D Software Upgrade Procedures UART Once Mnemosine MK IV is complete it is necessary the capability to update the software without accessing to the inner debugging pins This is done by using the USART port 3 that is normally connected to the CDU Below is minutely described the procedure to accomplish this task Hardware required OLIMEX STM32E407 any USB TTL cable converter Hardware required binary file ex ch bin STMicroelecttronics Flash Loader Demonstrator 1 Setting up the board for system memory boot BOOT0 1 amp BOOT1 0 Plit is foreseen that there is an explicit protected switch outside the Mnemosine s case 2 Connect the USB TTL converter to the computer and to the port of Mnemosine s CDU 3 Run Flash Loader Demonstrator and follow the images Pl ale va Sel
33. the ToolChain and the JTAG debugger After checking that the devices are properly recognized by the operating system it s possible to create a new project Procedure 1 2 Copy an existing demo for STM32E407 to workspace and rename the folder es demo_ 0 In ChibiStudio File gt New Makefile Project with Existing Code Browse select demo_ 0 folder Now the folder is shown in the Project Explorer Right click on the folder Clean Project Open Makefile and verify the statement Imported source files and paths CHIBIOS Chibios Link ChibiOS folder to the project File gt new folder gt Advanced Link to alternate location Linked Folder Browse gt ChibiStudio ChibiOS os gt OK Link board folder to the project File gt new folder gt Advanced Link to alternate location Linked Folder Browse gt ChibiStudio Chibi0S boards gt OK Properly set the Eclipse indexer Project Properties gt C C Build Discovery Option select Automate discovery of path and symbols select GCC per project scanner info profile This first demo has the aim of verifying the hardware so a simple blinking thread is fit for purpose include ch h include hal h Application entry point int main void hallnit chSysInit while TRUE palTogglePad GPIOC GPIOC_LED chThdSleepMilliseconds 1000 115 Appendi
34. the same space on the tape Moreover it facilitated the direct interfacing with the digital data processing computer However FM techniques are still being used at some flight test facilities for high frequency recording In this period the use of telemetry became more widespread It had the big advantage of providing real time results which could reduce the time needed to complete a flight test program In the sixties the combination of digital techniques and the micro miniaturization of electronic components triggered the development of high capacity data acquisition telemetry and data processing systems These were necessary as the number of parameters to be recorded and analyzed during flight tests increased sharply from a few tens just after WWII to some tens of thousands for the flight testing of present day aircraft Not only the total number of parameters increased enormously during this period but also the number of parameters with a high sampling rate for high frequency signals resulting in enormous figures for the total system sampling rate 1 1 A bit of FTI history Nowadays data systems which can cope with several millions of measurement values per second are not uncommon This increase in capacity of flight test data systems has only been made possible by the great advances in electronic technology during the past few decades 1 1 2 Data Processing and Analysis Methods The first tools that were used to reduce flight test dat
35. the total pressure it is used the HCA0611ARH8 6 also made by Sensor Technics Its main features are Range 600 to 1100 hPa Max pressure 3000 hPa Temperature range 0 C to 85 C Sensitivity 8 mV hPa Accuracy 1 0 ES Response time 2 ms Regarding the sensors for angle of attack and sideslip given the difficulty of installation of a nose boom in ULM aircraft sometimes they were omitted However the use of classical flag sensors is always possible Figure 2 11 HCLA Pressure Sensors Family 26 2 7 Engine Data 2 7 Engine Data By exploiting a hall effect sensor installed near the propeller it is possible to detect the number of turns of the same In order to detect the fuel consumption a fuel flow sensor may be installed inner the engine cowl and a thermocouple allows detection of EGT This thermocouple must be of type J given the high temperature of the engine and must necessarily be mounted at the critical point i e the less cooled part Figure 2 12 Typical Hall effect sensor and type J thermocouple 2 8 Stick Force Data Using a small 3D load cell originally built for automotive application and its acquisition board that is connected with Mnemosine MK IV via UART port it is possible to record stick force during the flight test FX m al FY OUTPUT OUTPUT COMPRESSION TENSION FY FX OUTPUT OUTPUT COMPRESSION TENSION Y AXIS X AXIS nn MARKER FY CABLE N Pa FX
36. 1 SF_USART_CR2 SF_USART_CR3 systime_t WAIT_TIME Psion 40 N A MNEMOSINE MKIV FLIGHT TEST eee ISTRUMENTATION M_FTI_SRS rev A SS Software Requirements Specification SRS pag 15 27 SF_HAL STP_001 The OPSW shall Setting up static UARTConfig uart_cfg SF as follows Callback that is invoked when a transmission buffer has been completely read by the driver SF_txendl Callbac N that is invoked when a transmission has physically completed SF_txend2 Callback that is invoked when a receive buffer has been completely written SF_rxend callback is invoked when a character is received but the application was not ready to receive it SF_rxchar Callback that is invoked on a receive error the errors mask is passed as parameter SF rxerr SF_USART_SPEED SF_USART_CR1 SF_USART_CR2 SF_USART_CR3 SF_HAL_FUN_001 The OPSW shall Create a static void SF _txendl UARTDriver uartp SF_HAL_FUN_002 The OPSW shall Create a static void SF_txend2 UARTDriver uartp SF_HAL_FUN_003 The OPSW shall Create a static void SF_rxchar UARTDriver uartp uintl6_t c SF_HAL_ FUN _004 The OPSW shall Create a static void rxerr UARTDriver uartp uartflags_t e MNEMOSINE MKIV FLIGHT TEST ISTRUMENTATION M_FTI_SRS rev A Software Requirements Specification SRS pag 16 27 SF_HAL_FUN_005 The OPSW shall Setting up uartStart amp SF_USART DRIVER
37. 5 aircraft instrument case this CDU is splitted into three main parts the rotary power switch the recording switch and the light indicators Its minimalist design ensures the minor probability to cause confusion although the operator retains full situation awareness The four lights identify e Orange external power supply in use e Green 1 aircraft power supply in use e Green 2 GPS fix e Red Recording The second currently under development is a multifunction touchscreen that makes possible to upload the test card or other documents It communicates with Mnemosine MK IV through a bluetooth module 31 3 Software Realization Once defined the physical structure of the system it is now possible focus on the software In this chapter all the choices that have been carried out for the operating system and application software will be introduced and motivated 3 1 Real Time Operating System From first instant it was clear that in order to meet the requirements the presence of a real time operating system had to be considered imperative Mnemosine MK IV like other real time systems are characterized by the severe consequences that result if logical as well as timing correctness properties of the system are not met Two types of real time systems exist soft and hard In a soft real time system task are performed by the system as fast as possible but the task don t have to finish by specific times In hard real time system
38. 6 V e Standby current 0 3 mA e Read Write current 15 mA Pad Number Name Type Description Name Type Description SDIO mode SPI mode 1 DAT2 T O PP data line bit2 2 CD DAT3 I O PP data line bit3 CS I chip select 3 CMD PP command response DI I data input 4 Vpp S supply voltage Vpp S supply voltage 5 CLK I clock SCLK I clock 6 Vss S supply voltage ground Vss S supply voltage ground 7 DATO I O PP data line bitO DO 0 data output 8 DAT1 T O PP data line bit1 24 Table 2 3 pad assignment 2 5 Secure Digital Card 2 5 1 SPI vs SDIO This memory supports two types of communication bus called SPI and SDIO The first which stands for Serial Peripheral Interface is a full duplex synchronous serial It is defined to use only 4 wires and is now widely used in communication between microprocessors and sensors of all types The data transmission on the SPI bus is based on the operation of the shift registers Each device master and slave is equipped with an internal shift register whose bits are output and simultaneously enter via the output SDO MOSI and the input SDI MISO The shift register 8 bits is a complete interface through which commands are given and transmitted as a serial stream even if they are taken internally in parallel At each clock pulse the devices that are communicating on the bus lines send a bit from their internal register replacing it with a bit
39. ASTERS i 2c_lld c STM32F407_Mnen line 143 C C Task gt sd_task h Topo globalc STM32F407_Mneni line 35 C Task gt time_task c ToDo global c STM32F407_Mnen line 67 C C Task gt fi time task h Topo global STM32F407_Mnen line 100 C C Task T Makefile le nn E ps Figure 3 1 ChibiStudio screen shot See Appendix C for the complete ChibiStudio software components Dipartimento di Elettronica E Informazione del Politecnico di Milano 36 3 3 Thread definitions High Level Software Requirements 3 3 Thread definitions High Level Software Requirements The software is mainly divided into threads each thread manages its own work The purpose of the threads is to support the following capabilities e Data acquisition of the following parameters Air data static pressure P_ STAT dynamic pressure P_ DIN OAT AOA AOS GPS data 3D ECEF position 3D ECEF velocity Stick force Control Surface positions elevator ELE POS rudder RUD_ POS aileron AIL_ POS flaps FLP_ POS Engine data RPM EGT Fuel Flow Data saving on secure digital SD e ETH port communication e CAN port communication e I C port communication e Software maintenance via UART port e Ensure data synchronization The following notation has been used in order to guarantee a project unique identifier for each operational software OPSW requirement THD _xxx_ yyy zzz The characters xxx denote th
40. E result could be RDY OK if a message has been correctly fetched RDY RESET if the mailbox has been reset while waiting RDY_ TIMEOUT if the operation has timed out AIR_COM_FUN_002 The OPSW shall if result RDY OK the thread shall decode the message and entry in acquisition mode In this mode it shall 1 Acquire the bus i2cAcquireBus amp I2CD2 2 Request data i2cMasterTransmitTimeout 3 Receive data i2cMasterReceiveTimeout 4 Release the bus i2cReleaseBus 12CD2 POLITECNICO y DI MILANO AIR_CAL_FUN_001 The OPSW shall MNEMOSINE MKIV FLIGHT TEST ISTRUMENTATION Software Requirements Specification SRS M_FTI_SRS rev A Convert AIR _rxbuf in to AIR data and check its integrity AIR_EXP_FUN_001 The OPSW shall Fill the AIR data AIR_Data_Struct with new AIR data pag 9 27 ATI POLITECNICO SERA DI MILANO lt a y Software Requirements Specification SRS ooo MNEMOSINE MKIV FLIGHT TEST ISTRUMENTATION M_FTI_SRS rev A 2 2 GPS data pag 10 27 Thread Name gps_com_thread Thread Acronym GPS Thread Priority NORMAL_PRIO 10 Pointer Input argument struct Output argument struct Gps Data_Struct HAL reference USART1 GPS_HAL_DEF_001 The OPSW shall Define the following object GPIO_BASE_GPS GPIO_BASE_PIN_A_GPS GPIO_ BASE PIN B GPS GPIO BASE PIN C
41. F O0index_e html April 4 2013 39 3 Software Realization e Windows compatible FAT file system e Platform independent and easy to port e Very small footprint for code and work area e Various configuration options Multiple volumes physical drives and partitions e Long file name support in ANSI OEM or Unicode e RTOS support e Multiple sector size support e Read only minimized API I O buffer 3 3 4 Ethernet thread This thread uses light weight Internet Protocol lwIP that is a small independent implemen tation of the transmission control protocol for Internet Protocol TCP IP suite that has been initially developed by Adam Dunkeld The focus of the lwIP TCP IP implementation is to reduce resource usage while still having a full scale TCP This makes lwIP suitable for use in embedded systems with tens of kilobytes of free RAM and around 40 kilobytes of code read only memory ROM Main features include Internet Control Message Protocol ICMP Point to Point Protocol Over Ethernet PPPoE Other extended features IP forwarding over multiple network in terfaces TCP congestion control round trip time RTT estimation and fast recovery fast re transmit are also includes addon applications like Hypertext Transfer Protocol HTTP server Network Basic Input Output System NetBIOS nameserver The Ethernet port will ensure proper delivery of data stream to ground stations The data transmission is unidirectional
42. Flowchart 22222 2 oo En 56 4 8 PC Driver SVC Flowchart 222 2 2 oo non nn 57 5 1 Boards Arrangement aaao 60 5 2 Flash Loader Demonstrator I 2 2 mo nn 118 5 3 Flash Loader Demonstrator 2 222 2 2 2 2 m on 119 5 4 Flash Loader Demonstrator Al 119 5 5 Flash Loader Demonstrator Al 222 ss srst onen 120 5 6 Flash Loader Demonstrator 5 2 2 2 a 120 List of Tables 2 1 Pin configuration of multi mode serial peripheral interface 19 2 2 Pin configuration of multi mode serial peripheral interface 20 23 pad assignment 24 au sr Po ee ead be Ee SA Re eee ees 24 4 1 ADC board pin configuration 22 22 2 cn Eon 50 Xi List of Acronyms ADC ADC AHRS AOA AOS API ATZ CAFFE CAN CAS CCM CDU CPU CS LSA CS VLA DAC DMA DPR DSP EASA EFIS EFIS EGT EICAS Air Data Computer Analog To Digital Converter Attitude Heading Reference System Angle Of Attack Angle Of Sidesleep Application Program Interface Air Traffic Zone CAN for Flight test Equipment Controller Area Network Calibrated Air Speed Core Coupled Memory Command and Display Unit Central Processing Unit Certification Specification Light Sport Aircraft Certification Specification Very Light Aircraft Digital Converter To Analog Direct Memory Access Decreto Presidente della Repubblica Digital Signal Processor European Aviation Safety Agency Electronic Flight
43. GHT TEST E AN ISTRUMENTATION M_FTI_SRS rev A un Software Requirements Specification SRS pag 12 27 GPS HAL _FUN_004 The OPSW shall Create a static void rxerr UARTDriver uartp uartflags t e GPS _HAL_FUN_005 The OPSW shall Setting up uartStart GPS_USART DRIVER amp uart_cfg GPS GPS _HAL_FUN_006 The OPSW shall Setting up palSetPadMode GPIO BASE GPS GPIO RX GPS PAL MODE ALTERNATE 7 palSetPadMode GPIO_BASE_GPS GPIO_TX GPS PAL MODE ALTERNATE 7 GPS HAL _FUN_007 The OPSW shall Setting up palSetPadMode GPIO_BASE_PIN_A GPS GPIO_A GPS PAL MODE OUTPUT_PUSHPULL palSetPadMode GPIO_BASE_PIN B GPS GPIO _B GPS PAL MODE _OUTPUT_PUSHPULL palSetPadMode GPIO BASE PIN C GPS GPIO_C GPS PAL MODE OUTPUT _PUSHPULL palSetPadMode GPIO BASE PIN _D_ GPS GPIO_D GPS PAL MODE _OUTPUT_PUSHPULL palSetPadMode GPIO_ BASE PIN OUT_GPS GPIO_OUT_GPS PAL MODE OUTPUT _PUSHPULL palSetPadMode GPIO BASE PIN_IN GPS GPIO_IN GPS PAL_MODE_INPUT_PULLDOWN ASE NE A MNEMOSINE MKIV FLIGHT TEST ISTRUMENTATION M_FTI_SRS rev A MILANO 7 Software Requirements Specification SRS 000 120000000 pag 13 27 GPS_COM_TST_001 The OPSW shall perform a communication test with GPS module in order to ensure th effectiveness both receiver and transmitter state GPS_COM_TST_002 The OPSW shall once assured proper communication the thread must check the consistency
44. GPS GPIO BASE PIN D GPS GPIO BASE PIN _OUT GPS GPIO BASE PIN IN GPS GPS_USART_DRIVER GPS_USART_SPEED GPS_USART_CR1 GPS_USART_CR2 GPS_USART_CR3 systime_t WAIT TIME GPIO_RX_GPS GPIO A GPIO B GPIO_C GPIO D GPIO_ OUT GPIO_IN GPIO_TX GPS A POLITECNI GER SEG MNEMOSINE MKIV FLIGHT TEST el y ISTRUMENTATION k SN y J SS Software Requirements Specification SRS M_FTI_SRS rev A GPS_HAL_STP_001 The OPSW shall Setting up static UARTConfig uart_cfg_GPS as follows pag 11 27 Callback that is invoked when a transmission buffer has been completely read by the driver GPS_txendl Callback that is invoked when a transmission has physically completed GPS_txend2 Callback that is invoked when a receive buffer has been completel GPS_rxend callback is invoked when a character is received but the appl ready to receive it GPS_rxchar y written lication was not Callback that is invoked on a receive error the errors mask is passed as parameter GPS_rxerr GPS_USART_SPEED GPS_USART_CR1 GPS_USART_CR2 GPS_USART_CR3 GPS HAL _FUN_001 The OPSW shall Create a static void GPS_txendl UARTDriver uartp GPS HAL _FUN_002 The OPSW shall Create a static void GPS_txend2 UARTDriver uartp GPS_HAL FUN _003 The OPSW shall Create a static void GPS_rxchar UARTDriver uartp uintl6_t c ATI POLITECNICO AED DI MILANO MNEMOSINE MKIV FLI
45. Instrument System Electronic Flight Instruments System Exhaust Gas Temperature Engine Indicating and Crew Alerting System xiii List of Acronyms ELT FM FPU FTE FTI GPIO GPS HAL HTTP PC PS ICMP IDE ISR JTAG lwIP MCU MPU MTOW NetBIOS OPSW OTG PCM PLL PPPoE PWM RISC RMS XIV Emergency Locator Transmitter Frequency Modulation Floating Point Unit Flight Test Engineer Flight Test Instrumentation General Purpose Input Output Global Positioning System Hardware Abstraction Layer Hypertext Transfer Protocol Inter Integrated Circuit Inter IC Sound Internet Control Message Protocol Integrated Development Environment Interrupt service routine Joint Test Action Group light weight Internet Protocol Microcontroller Unit Memory Protection Unit Maximum Take off Weight Network Basic Input Output System Operational Software On The Go USB Peripheral Pulse Code Modulation Phase Locked Loop Point to Point Protocol Over Ethernet Pulse Width Modulation Reduced Instruction Set Code Rate Monotonic Scheduling ROM RPM RTOS RTT SBAS SDC SDIO SRAM SRS SVC TCP IP UART ULM USART VFR List of Acronyms Read Only Memory Revolutions Per Minute Real Time Operating System Round Trip Time Satellite Based Augmentation System Secure Digital Card Secure Digital Input Output Static Random Access Memory Software Requirement Specification Suitability Validation Cod
46. MEOUT if the operation has timed out SF_COM_FUN_002 The OPSW shall if result RDY OK the thread shall decode the message and entry in acquisition mode uartStartReceive amp SF_USART_ DRIVER size_t n void SF_rxbuf SF_CAL_FUN_001 The OPSW shall Convert SF_rxbuf in to SF_data and check its integrity SF_EXP_FUN_001 The OPSW shall Fill the SF_Data_Struct with new SF data AN POLITECNICO 201 DI MILANO Ce 000 00000000 MNEMOSINE MKIV FLIGHT TEST ISTRUMENTATION Software Requirements Specification SRS M_FTI_SRS rev A 2 4 Control Surface Position data pag 18 27 Thread Name csp_com_thread Thread Acronym CSP Thread Priority NORMAL_ PRIO 10 Pointer Input argument struct Output argument struct CSP_Data_Struct HAL reference ADC3 CSP_HAL_DEF_001 The OPSW shall Define the following object GPIO_CSP ADC_CSP_GRP_BUF_DEPTH ADC_CSP_GRP_NUM_CHANNELS adcsample _t CSP_samples ADC_CSP_ GRP NUM _ CHANNELS ADC _CSP_GRP_ BUF DEPTH CSP_HAL_STP_001 The OPSW shall Set Enables the circular buffer Set Set Set group ting up adcerrcallback_CSP as error call mode for the group ting up the number of the analog channels belonging ting up adccallback_CSP as callback function associat ting up static const ADCConversionGroup adcgrpcfg CSP as follows to the conversion group
47. P RP RP Hm e COON DTKFRWNYNRrF TKO AN DAK WNrF DOAN DTK WNKrFTWTMO AN DBA KFWNrF THO oO I DAK WN Hm IO Time Scheduler source code global h ifndef GLOBAL H_ define define define define define define define define define define define define define define define define define define define define define define define define define GLOBAL H MAX PRIO 30 AHRS _ PRIO MAX PRIO CSP_PRIO MAX PRIO 1 AIR PRIO MAX PRIO 2 SF_PRIO MAX_PRIO 3 GPS PRIO MAX PRIO 4 CDU PRIO MAX PRIO 5 SD_PRIO MAX_PRIO 6 TIMER_FREQ 10000 10kHz timer clock gt 100 ns TIMER PRE 100 TIMER FREQ TIMER PRE Hz 100hz AHRS COUNT FREQ TIMER FREQ TIMER PRE 50 CSP_COUNT FREQ TIMER FREQ TIMER PRE 20 AIR_COUNT FREQ TIMER FREQ TIMER PRE 10 SF_COUNT FREQ TIMER FREQ TIMER PRE 10 GPS_COUNT FREQ TIMER FREQ TIMER PRE 5 CDU COUNT FREQ TIMER FREQ TIMER PRE 4 FLAG_AHRS FLAG_CSP FLAG_AIR FLAG SF FLAG GPS FLAG CDU FLAG SD NO TB WN m BYTE NUMBER 32 typedef struct uint32_t flag uint32_t message BYTE_NUMBER 4 test_t typedef union test_t t char c sizeof test_t filebuffer_t typedef struct uint8_t ahrs 102 uint8_t csp 102 uint8_t air 102 uint8_t sf 102 uint8_t gps 102 uint8_t cdu 102 output_t extern inti16_t count extern output_t out extern WORKING_AREA wa_gps 128 msg_t gps_com_thread void xarg
48. POLITECNICO DI MILANO Scuola di Ingegneria Industriale Corso di Laurea Magistrale in Ingegneria Aeronautica Design and development of the new generation of the Mnemosine FTI system for light aircraft Relatore prof Alberto ROLANDO Tesi di Laurea di Federico ROSSI Matr 763665 Anno Accademico 2011 2012 Sommario Questa tesi nasce per rispondere alla richiesta di una nuova generazione di strumentazione per prove di volo per velivoli ultraleggeri sviluppata dal Dipartimento di Scienze e Tecnolo gie Aerospaziali del Politecnico di Milano Tale strumentazione andra a sostituire la precedente versione chiamata Mnemosine MK III che essenzialmente si compone di pit case metallici con tenenti i nodi ognuno con le proprie caratteristiche che comunicano fra loro tramite protocollo Controller Area Network CAN data bus appositamente sviluppato Quanto segue il risultato di diverse analisi volte allo sviluppo del nuovo sistema flight test instrumentation FTI chiamato Mnemosine MK IV Capitalizzando i progressi dell industria dei semiconduttori questa nuova versione introduce l integrazione di pi nodi in un unica unit centrale le cui funzioni sono governate da un sistema operativo real time Fin da subito si espone la volonta di utilizzare il pit possibile software e codici sorgenti Open Source Il lavoro qui presentato composto da una parte introduttiva dove si riporta brevemente la storia dell evoluzione di Mne
49. PRICE i2cStart amp I2CD2 amp i2cfgi palSetPadMode GPIOF 0 PAL_MODE_ALTERNATE 4 PAL_STM32_OTYPE_OPENDRAIN vel palSetPadMode GPIOF 1 PAL_MODE_ALTERNATE 4 PAL_STM32_OTYPE_OPENDRAIN el chThdSleepMilliseconds 100 wmpOn chThdSleepMilliseconds 2000 calibration calibrateZeroes chprintf chp n n n r d d d r n yawO pitch0 roll0 while TRUE receiveData chprintf chp d d X d r n yaw pitch roll ch ThdSleepMilliseconds 50 return 0 SDA SCL gt 111 Appendix C ChibiStudio ChibiStudio components are e Eclipse Juno 4 2 classic http www eclipse org with the following optional components installed Eclipse CDT 8 1 0 C C GDB Hardware Debugging 7 0 0 Eclipse XML Editors and Tools 3 4 0 Target Management Terminal 3 3 0 Serial Connector plugin http rxtx qbang org eclipse ChibiOS RT debug plugin 1 0 8 ChibiOS RT configuration plugin 1 1 0 Embedded Systems Register View plugin 0 2 1 90 http sourceforge net projects embsysregview GCC ARM toolchain gcc arm none eabi 4__6 2012q2 20120614 https launchpad net gcc arm embedded OpenOCD 0 6 0 http openocd sourceforge net ChibiOS RT 2 5 0 113 o N na oFr WN FH Appendix D Software Upgrade Procedures JTAG The first step towards the realization of a project involving the use of a microcontroller requires the setup of
50. Power sdcStart sdcDisconnect sdcRead sdcConnect connection successful SDC_READING Reading read finished read error connection failed sdcStart SDC_READY Clock Enabled SDC_ACTIVE sdcConnect Card Ready sdcWrite disconnection finished sdcDisconnect SDC_WRITING Writing Disconnecting write finished write error Figure 3 2 SDC diagram In agreement with the above diagram the thread must initialize the driver from left to right After the initialization phase the thread enters a phase of waiting until it is released by the time scheduler The software should guarantee the following functions create a new mission folder in the SD card create e close a new file each second where writes all acquired measurements in that time period start stop recording communicates its state and errors keeping track of all written bytes keeping track of all free bytes in the SD card mount unmount card secure power falling procedure without loss of information In order to use SD card a file system is needed ChibiOS uses FatF 9 FatFs is a generic FAT file system module for small embedded systems The FatFs is written in compliance with ANSI C and completely separated from the disk I O layer Therefore it is independent of hardware architecture its features are http elm chan org fsw f
51. RAPHY 21 attp www st com internet com home home jsp April 4 2013 23 http www arm com April 4 2013 24 fntep wwww seneca it prodotti php id_c 4 April 4 2013 25 http www altheris com products displacement sensors draw wire sensors htm April 4 2013 26 http www linear com designtools software LTSpice April 4 2013 27 http www avagotech com April 4 2013 28 http en wikipedia org wiki Ultralight aviation April 4 2013 29 EASA CS VLA amdt1 30 http www chibios org dokuwiki doku php id chibios documents introduction April 4 2013 31 http www xsens com en general mti April 4 2013 32 http www u blox com en lea 5t html April 4 2013 33 EASA CS LSA Initial Issue 34 AGARDograph 300 volume 14 Chapter 2 HISTORICAL PERSPECTIVE ONE HUN DRED YEARS OF FLIGHT TESTING Robert L van der Velde 35 MicroC OS II The Real Time Kernel second edition Jean J Lambrosse 62 Appendix A SRS Oy POLITECNICO DI MILANO MNEMOSINE MK IV FLIGHT TEST ISTRUMENTATION Software Requirements Specification SRS Document ID M_FTI_SRS rev A Compiled by Federico Rossi Project Leader Alberto Rolando Authorization EN Ta POLITECNICO BON MNEMOSINE MKIV FLIGHT TEST N PERN S ISTRUMENTATION M_FTI_SRS rev A AO i Software Requirements Specification SRS pag 2 27 REVISION HISTORY ISSUE CHANGE DESCRIPTION I
52. SSUE DATE A First Issue 13 02 2013 site i GER DE TECNICO MNEMOSINE MKIV FLIGHT TEST ISTRUMENTATION M_FTI_SRS rev A SS Software Requirements Specification SRS pag 3 27 TABLE OF CONTENTS NCS COUR a aie O 5 USI i Ba ol dF y s CO ahs ea a a A O ne A PA 5 152 SYS dole AB Ny EET Val GV ec E A A A N 5 AOO CUM N OVP RV A BIN 6 1 4 OPERATIVE SOFTWARE REQUIREMENTS NOTATION cccccccssscessccssecesseessecesseeeess 6 PSCAPABIMIASREOQUIREMEN DS E E tse ne ca O UI ane are es 1 DMAA a I E E EN SA E NS TEE ETE S E TE E TERA A TN 7 DENG SHA aa ee E eke ogee rac Noa ag cdo ee T ek ag oc Aha OY ate E Oe en te 10 IS HEISE A sarod co DI UNE MINE 14 PA antro Surface Fostiomdatar Sasse Ne Re 18 A RR ee ee 21 A Re ee een meets 24 BZACRONY MES sera LISA ER RE 2 MNEMOSINE MKIV FLIGHT TEST ISTRUMENTATION Software Requirements Specification SRS M_FTI_SRS rev A BLANK pag 4 27 Psion 7 NON MULAS MNEMOSINE MKIV FLIGHT TEST US A ISTRUMENTATION M_FTI_SRS rev A RAN SS Software Requirements Specification SRS pag 5 27 1 SCOPE 1 1 IDENTIFICATION This software requirements specification applies to MNEMOSINE MK IV FLIGHT TEST ISTRUMENTATION abbreviated as MFTI This document details and defines the software specification of MFTI MK IV thread s 1 2 SYSTEM OVERVIEW The purpose of the threads are to support the fol
53. Signal Processor DSP by Microchip Technology Inc CAN line driver integrated circuit IC MCP2551 by Microchip Technology Inc The used board appears to be divided into two parts one part common to all modules that implements the basic functionality and another ad hoc that allows to characterize each node to its purpose 1 5 History of Mnemosine FTI 1 5 2 Actual state Mnemosine MK Ill Mnemosine MK III is made up of the following nodes Terpsicore Urania Melete Polimnia Eutherpe and Talia CALLIOPE FC FORCE cuo DATA LOGGING POLYHYMNIA GPS TERPSICHORE INERTIAL MEAS MELPOMENE COMMAND amp DISPLAY Figure 1 1 Block diagram of Mnemosine MK III EUTERPE FLIGHT CONTROLS MELETE POWER SUPPLY THALIA ENGINE DATA URANIA AIR DATA POWER DISTRIBUTION D BUS T BUS Clio performs data logging on Secure Digital card SDC using a specific CAN data logger Calliope receives the signal from the Load Cell Embedded Digitiser and creates the message to be sent on the bus Eutherpe through the use of potentiometers allows the monitoring of the positions of equilibrator ailerons flaps and pedals Melete is the power unit Melpomene communicates with the command and display unit CDU Polyhymnia via GPS module it transmits speed position and satellites in view with a frequency of 4 Hz on the data bus Talia engine data through a Hall effect sensor calculates the spee
54. Y Clock Enabled callback return adcStartConversion then callback return ADC_ERROR Error callback return Figure 3 8 ADC driver The ADC Conversion Group is the object that specifies a physical conversion operation This structure contains some standard fields and several implementation dependent fields The stan dard fields define the conversion group mode the number of channels belonging to the conversion group and the optional callbacks The implementation dependent fields specify the physical ADC operation mode the analog channels belonging to the group and any other implementation spe cific setting Usually the extra fields just mirror the physical ADC registers The driver supports three conversion modes e One Shot the driver performs a single group conversion then stops e Linear Buffer the driver performs a series of group conversions then stops This mode is like a one shot conversion repeated N times the buffer pointer increases after each 43 3 Software Realization conversion The buffer is organized as an S CG N samples matrix when S CG is the conversion group size number of channels and N is the buffer depth number of repeated conversions e Circular Buffer much like the linear mode but the operation does not stop when the buffer is filled it is automatically restarted with the buffer pointer wrapping back to the buffer base The driver is able to invoke callbac
55. _MODE_DISABLED EXT_CH_MODE_DISABLED EXT_CH_MODE_DISABLED EXT_CH_MODE_DISABLED EXT_CH_MODE_DISABLED EXT_CH_MODE_DISABLED EXT_CH_MODE_DISABLED EXT_CH_MODE_DISABLED EXT_CH_MODE_DISABLED EXT_CH_MODE_DISABLED EXT_CH_MODE_DISABLED NULL NULL NULL NULL NULL NULL NULL NULL NULL NULL NULL NULL NULL NULL NULL NULL NULL NULL NULL _t channel EXT_MODE_GPIOA extcb1 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 112 113 114 115 116 117 Time Scheduler source code EXT_CH_MODE_DISABLED NULL EXT_CH_MODE_DISABLED NULL EXT_CH_MODE_DISABLED NULL GPT callback static void gpt2cb GPTDriver xgptp void gptp if count lt 99 count gptStartOneShotI amp GPTD2 TIMER_PRE time_dispenser GPT2 configuration static const GPTConfig gpt2cfg TIMER_FREQ gpt2cb Timer callback x E msg_t time_dispenser void filebuffer_t FileBuffer filebuffer_t FileBufferP FileBufferP amp FileBuffer if O count AHRS_COUNT_FREQ FileBufferP gt t flag FLAG_AHRS chMBPost amp mbox_AHRS msg_t FileBufferP TIME_IMMEDIATE if 0 count CSP_COUNT_FREQ FileBufferP gt t flag FLAG_CSP chMBPost amp mbox_CSP ms
56. a to standard conditions and other calcu lations were the hand cranked mechanical calculator and the slide rule Data reduction was a tedious process involving a lot of manpower and time The error rate was high and equations had to be simplified to avoid complex time consuming calculations Starting from late fifties the situation improved The rapidly increasing capabilities of the digital computer were easily absorbed by the now growing demand for computing power generated by the new PCM data acquisition systems The computer also became an invaluable tool for the storage of flight test data results of calculations administrative data aircraft and data system configuration data and calibration data Large relational data base management systems were introduced for the storage and retrieval of such data The main advantage coming from that was the capability of an orderly known fashion storage which is also accessible to many users of various disciplines Computer networks and commercial data transmission facilities enabled users to transmit their flight test data from and to virtually any place in the world and provided access to their data bases from wherever they choose to do their flight tests 1 Introduction 1 2 ULM Ultra Light Machine Ultra Light Machines ULM are lightweight aircraft with one or two seat Nowadays different types ULM are product including 28 Weight shift control trike while the first generation of ultrali
57. apter Obviously it was an iterative process with the aim of finding the best fit of the requirements EGT Propeller PickOff Q Ground Station Link ANALOG 0 Ny OU A U NE URANIA STICK FORCE FTE Software Upgrade Bluetooth Display Figure 2 1 Mnemosine MK IV 13 2 Hardware Realization Figure 2 1 allows to observe all the hardware subsystems that compose MK IV comparing it with the diagram of MK III it is immediately note the absence of a data bus in favor of an integrated architecture The only external module is Urania air data that communicates with the main board using I C protocol The entire system is enclosed in a metal case that will protect the delicate circuits during the flight test It should be noted the ability to update the software externally without changing the boarded configuration this skill ensures a high degree of software maintainability Figure 2 2 Mnemosine MK IV Rendering The new hardware architecture allows to assemble the most part of the system inside one single metal case 14 2 1 Development board 2 1 Development board As previously mentioned Mnemosine MK IV is constituted by a single central core the mi crocontroller Currently there are hundreds if not thousands of models all different from each other each one having its own features By conducting research in the automotive and industrial automation it has been possible to draw up a list of prod
58. are Realization 2 3 Multi Mode Serial Peripheral Interface As expressly indicated by the requirement the system uses a number of sensors that transmit data by serial interface directly to the doors USART or UART of the microcontroller By the way in the world of aviation and automation in general there are several serial communication protocols including 24 RS232 EIA RS 232 is a standard EIA equivalent to the European standard CCITT V21 V24 It defines a low speed serial interface for the data exchange between digital devices Stretch ing a physical cable between two electronic devices equipped with a RS 232 port is possible to realize a communication between them EIA standard RS 232 was born in the early sixties by the work of the Electronic Industries Association and was oriented to the com munication between the mainframe and terminals Data Terminal Equipment through the telephone line using a modem Data Communication Equipment Over the years changes have been made to obtain different standards such as RS 232c widely used in the industrial field Viewing from the electrical point three logical levels are defined mark between 3 V and 15 V space between 3 V and 15 V and uncertainty between 3 V and 3 V RS 422 EIA RS 422 is a standard EIA or CCITT V11 in European legislation It is a protocol for serial data communication that involves the use of two wires with multi point differential line balanced different
59. are routed to USART3 sdStart amp SD3 NULL palSetPadMode GPIOD 8 PAL_MODE_ALTERNATE 7 palSetPadMode GPIOD 9 PAL_MODE_ALTERNATE 7 chp amp SD3 Initializes ICU driver 4 TIM4 ETR GPIOEO TIM4 CH2 GPIOD13 is the ICU input pin D16 Enables ICU palSetPadMode GPIOE 0 PAL_MODE_ALTERNATE 1 icuStart amp ICUD4 amp icucfg palSetPadMode GPIOD 13 PAL_MODE_ALTERNATE 2 icuEnable amp ICUD4 while TRUE chprintf chp period d usec overflow d r n last_period 10 last_overflow chThdSleepMilliseconds 200 106 IC Driver source code 57 58 return 0 59 107 O oND AUNE a a U U Ver FBP BKK SBP WWW WWwWwWwWwWwWwWNnNn nD NNN NNNN HP o ppp Ott PN HMTOVO Oo I DarWwNrFoUdAN Doar yoNRAODO Io UV PD HM OO OO II OO VD rRrWN Hm oO Appendix B SVC CAN Driver source code include ch h include hal h Internal loopback mode 500KBaud automatic wakeup automatic recover from abort mode See section 22 7 7 on the STM32 reference manual static const CANConfig cancfg F CAN_MCR_ABOM CAN_MCR_AWUM CAN_BTR_LBKM CAN_BTR_SJW 0 CAN_BTR_TS1 8 CAN_BTR_BRP 0 NULL CAN_MCR_TXFP CAN_BTR_TS2 1 6 gt Receiver thread x static WORKING_AREA can_rx_wa 256 static msg_t can_rx void xp EventListener el CANRxFrame rxmsg void p chRegSetThreadName receiver chEvtRegister amp CAND1 rxfull_event amp
60. box_CDU mbox_buf_CDU chMBInit amp mbox_SD mbox_buf_SD halInit chSysInit Init Threads chThdCreateStatic wa_ahrs mbox_AHRS chThdCreateStatic wa_csp mbox_CSP chThdCreateStatic wa_air mbox_AIR chThdCreateStatic wa_sf mbox_SF chThdCreateStatic wa_gps mbox_GPS chThdCreateStatic wa_cdu mbox_CDU chThdCreateStatic wa_sd mbox_SD Activates the serial sizeof sizeof sizeof sizeof sizeof sizeof sizeof TE 1 1 1 1 1 wa_ahrs AHRS_PRIO ahrs_com_thread wa_csp CSP_PRIO csp_adc_thread wa_air AIR_PRIO air_com_thread wa_sf SF_PRIO sf_com_thread wa_gps GPS_PRIO gps_com_thread wa_cdu CDU_PRIO cdu_com_thread wa_sd SD_PRIO sd_save_thread driver 3 using the driver default configuration x PD8 TX and PD9 RX are routed to USARTS sdStart amp SD3 NULL palSetPadMode GPIOD 8 PAL_MODE_ALTERNATE 7 palSetPadMode GPIOD 9 PAL_MODE_ALTERNATE 7 Initializes the GPT drivers 2 gptStart amp GPTD2 amp gpt2cfg Activates the EXT driver 1 extStart amp EXTD1 amp extcfg 1 extChannelEnable amp EXTD1 while TRUE chThdSleepMilliseconds 5000 end infinite loop y end main void void void void void void void 100 OmoAN Do KR WN OO TUT UT UT UT UT A Fe Pe KP BK BK WwWwWwWWWWwWwWwWwWwWwWn nN NNN NYN NNN N HP KP RP BP RP R
61. d DSP running sensor fusion algorithm Gyroscopes enable high frequency orientation tracking High update rate 120 Hz inertial data processing at max 512 Hz Individually calibrated for temperature 3D misalignment and sensor cross sensitivity Accepts and generates synchronization pulses This last point is prime for Mnemosine MK IV that is a synchronous real time system and allows the essential command response from the board and the MTi The MTi returns and technical specifications are 3D Orientation 360 3D acceleration 3D rate of turn 3D magnetic field Static accuracy roll pitch lt 0 5 Digital interface RS 232 RS 485 RS 422 Dynamic accuracy 2 RMS Static accuracy heading lt 1 Operating voltage 4 5 30 V Angular resolution 0 05 Figure 2 15 Xsens MTi 29 2 Hardware Realization 2 10 GPS Data The GPS module for Mnemosine MK IV is not just a simple position sensor but it is the main source of the entire time system this means that it is probably one of the major critical points of the whole project As previously mentioned Mnemosine MK IV allows to acquire measurements synchronously to obtain this the system receives in input a pulse every second that gives start to a default sequence of operations Thus the source of time is the external time pulse of GPS Following a brief marketing research the LEA 5T made by U Blox 32 has been chosen as Mnemosine GPS module The LEA
62. d rotation of the propeller Terpsichore communicates serially with AHRS 400CC 200 4 with a frequency of 58 Hz providing speed and angles of roll pitch and yaw as well as accelerations along the three axes XYZ Urania in effect an air date computer uses a differential pressure sensor MPXV5004G 5 and a absolute pressure MPX5100 6 1t allows to obtain information on static pressure dynamic pressure temperature and angles of attack and sideslip 1 Introduction 1 6 Operating limits After using the system for few years some critical aspects have been found first of all the decentralized nature in multiple nodes leads to an increase of the space occupied by the system data was asynchronous and affected by presence of short random data delay As a matter of fact it has been noted that it needs a new on board user interface Figure 1 2 Mnemosine MK III installed on board 10 1 7 Upgrade requirements 1 7 Upgrade requirements At first glance it is immediately apparent the need for a deep change in the configuration the integrated architecture makes it possible to obtain smaller volumes and in this case it s the highest grade of efficiency In order to face the undesired presence of asynchronism it will be used a deterministic software while as far as it concerns the last issue it is necessary to design a new user interface Collecting all the ideas it s possible to write the new high level requirements and the new M
63. e Transmission Control Protocol Internet Protocol Universal Asynchronous Receiver Transmitter Ultra Light Machine Universal Synchronous Asynchronous Receiver Transmitter Visual Flight Rules XV 1 Introduction 1 1 A bit of FTI history In less than a century the airplane has undergone a spectacular evolution 34 This evolution was marked by recurring cycles of research ground testing production flight testing improved products and it stemmed from man s constant striving for better more capable more effective more economical airplanes The early pioneers in aviation combined many disciplines they were aerodynamicist materials specialist researcher designer airframe manufacturer and sometimes like the Wright brothers engine manufacturer too They were also test pilot flight test engineer and data analyst all in one person As time progressed technology advanced and the com plexity of airplanes increased it was no longer possible for one person to remain ahead of the developments in all fields Specialist disciplines started to develop and the former one man job eased in many specialist functions The function of Flight Test Engineer FTE was one of those specialist functions In itself the profession of FTE has changed quite a bit over the years as a consequence of further specialization At first gradually but from the beginning of the seventies at an ever increasing rate electronics started to fulfil
64. e RS 485 only specifies the electrical characteristics of the transmitter and the receiver It does not indicate or recommend any protocol for data transmission EIA RS 485 allows the configuration of a low cost local area networks or multi point data communications It permits a very high speed transmission 35 Mbit s up to 10 m and 100 kbps to 1 200 m Since it uses a signaling system with a non negligible voltage with a balanced line through the use of a pair of twisted cable as is the case in the EIA RS 422 you can reach far distances up to 1 200 m Compared to the EIA RS 422 which has a 2 3 Multi Mode Serial Peripheral Interface single driver circuit which must not be turned off the transmitter for the EIA 485 is placed in transmission mode explicitly by applying a signal EIA RS 485 such as EIA RS 422 can be made using four wire full duplex two pairs but since EIA 485 is a specific type of multi point this is not strictly necessary As it is differential it resists to interferences of electromagnetic nature From conceptual point of view in order to choose which standard to use to communicate between the device and the microcontroller it becomes necessary the realization of a line driver that brings the signal by the above listed protocols to TTL logic level useful for the MCU TXD RXD Figure 2 5 Conceptual diagram of multi mode serial peripheral interface Referring to Figure 2 1 it s possible to fill the foll
65. e desire to use as much as possible Open Source software and source code This work consists of an introduction where is given a brief history of general flight test activity and the evolution of Mnemosine the formal research of new requirements gathered during the flight test campaigns both in academic and in business through to the project Poli XFlight Follows the hardware preliminary design that in some cases goes into detail according to the functional requirements Then the description of the software philosophy until the preparation of the requirements specification and the presentation of the demo made with the purpose of verifying the actual feasibility of entire project 111 Contents t ontents gt eg iw ic v o List of Figures ist of Tables m ist of Acronyms 1 Introduction LI A bit ot FI History Je es a d aed a aa Oe ew nahe 1 1 1 Data Acquisition Methods o aoa aaa aa a a Be a o a aw ooh e ge e eo dH Ge ok wo Mh aa eRe a Ake A a Gea doe Gale Eh ee eh ah ae tle ie red LS OS VIDAL e ak od ea BREA ne er oe eat Sig hot Waca ow wh ee ee bw hoe RN 1 4 ULM Regulation in Italy 2 o o o e 1 5 History of Mnemosine FTI o e a 1 5 1 Initial requirements ee 15 2 Actual state Mnemosine MK Ill o o e 1 6 Operating limits o o e e 1 7 Upgrade requirements 22222222 non nn 2 Hardware
66. e type the requirement belongs to among the following HAL hardware abstraction layer COM peripheral communication CAL calculate compute do something SAV save UPT update EXP export data The characters yyy denote the type the requirement belongs to among the following DEF definition STP setup structure FUN function and zzz denote a serial number useful for identification As mentioned ChibiOS RT is written entirely in ANSI C for this reason all the code that will be proposed is intended written in this language hereinafter will displays all the expected threads with their general characteristics 37 3 Software Realization 3 3 1 Main The main has the task to initialize the operating system according to the operating parameters of the board OLIMEX STM32E407 9 allow the creation of all threads and their respective mail boxes Substantially the work of the script main ends with the initialization phase where the thread scheduler thanks to the operating system takes control of the entire software common aspect of all embedded real time operating systems 3 3 2 Time scheduler The time scheduler is not just a simple thread but a set functions independently managed through the use of hardware and software interrupts It receives a pulse every second from GPS time pulse starting from here and knowing the sampling frequencies of all desired measures a timer starts and sends a startup message that allows the executio
67. eceive buffer has been completely written x 70 static void rxend UARTDriver xuartp 71 72 void uartp 73 74 75 x UART driver configuration structure x 76 static UARTConfig uart_cfg_3 77 txendl 78 txend2 79 rxend 80 rxchar 81 rxerr 82 38400 83 0 84 USART_CR2_LINEN 85 0 86 y 87 88 Application entry point x 89 int main void 90 91 hallnit 92 chSysInit 93 94 Activates the UART driver 3 PD8 TX and PD9 RX are routed to USARTS 95 96 uartStart amp UARTD3 amp uart_cfg_3 97 palSetPadMode GPIOD 8 PAL_MODE_ALTERNATE 7 98 palSetPadMode GPI0OD 9 PAL_MODE_ALTERNATE 7 99 100 Starts the transmission it will be handled entirely in background x 101 uartStartSend amp UARTD3 sizeof Starting r n Starting r n 102 103 while TRUE 104 chThdSleepMilliseconds 500 15 106 93 O oND A WN OT a nm ner re rer rer BD WW DD WWW WWW N DD DD DD NDDNDIDDNDHTHHE RP RP RP KR ee oR WwW NF OU AN OD OCT PM HH OO SI DA PO ND HT THAN OD VOGT PO DND HH ODO ID OUT PP WM MH O 56 Appendix B SVC ADC Driver source code include ch h include hal h define COUNT2VOLT 0 000805861 3v3V 4095count define ADC GRP NUM CHANNEIS 8 define ADC GRP BUF DEPTH 2 static adcsample_t samples ADC_GRP_NUM_CHANNELS ADC_GRP_BUF_DEPTH ADC streaming callback do nothing x static void adccallback ADCDriver x adcp adcsample_t
68. ect the communication port and set settings then click next to open connection Common for all families UART Port Name COM5 v Parity Even BaudRate 115200 v Echo Disabled v Data Bits Timeoutfs 10 Flow Control oF y zem y If Flow control is active By default DTR amp RTS are ON Figure 5 2 Flash Loader Demonstrator 1 Mirror copy available here http code google com p afrodevices downloads detail name stm32 stm8 flash _loader_demo zip amp can 2 amp q April 4 2013 118 Remove prot Figure 5 3 Flash Loader Demonstrator 2 0x4000 16K 0x4000 16K 0x4000 16K 0x1 0000 64 0x20000 12 0x20000 12 0x20000 12 Figure 5 4 Flash Loader Demonstrator 3 UART 119 Appendix D Software Upgrade Procedures Y als ut C Erase E Ail C Selection Bj Download to device r Download from file C Documents and Settings Federico Desktop build ch bin El Erase necessary pages NoErase Global Erase thi 8000000 y Jump to the user program I Optimize Remove some FFs IV Verify after download Apply option bytes Upload from device Upload to file E Hi ENABLE y READ PROTECTION Y Back Next Cancel Close Figure 5 5 Flash Loader Demonstrator 4 Vl als va Target STM32F4_512K Map file STM32F4_512K 5Tmap Operation DOWNLOAD File
69. ecture is static everything is statically allocated at compile time nevertheless dynamic extensions and objects are supported by an optional layer built on top of the static core There is an entire set of primitives threads vir tual timers semaphores mutexes condition variables messages mailboxes event flags queues It support priority inheritance algorithm on mutexes HAL component supporting a many if not all abstract device drivers also supporting external components like uIP lwIP and FatFs essential for the proper functioning of the SD card 34 3 1 Real Time Operating System The ChibiOS s father is Giovanni Di Sirio in the eighties he developed an ancestor that was an Operating System for Motorola 68000 17 In 1989 it supported GCC ran EMACS was preemptive and real time but in 1991 Linus Torvalds began the development of Linux and the project changed course The original full featured OS turned in a minimalistic efficient RTOS ChibiOS RT s father In 2007 15 years later it turned to ChibiOS RT an open source RTOS project targeted to embedded systems Currently the project is led and mainly developed by Giovanni Di Sirio and in the last years ChibiOS RT started growing in features ports and users Now it is a real software community As underlined ChibiOS RT is meant to be a whole operating system not just a scheduler The kernel has no internal tables there is nothing that must be configured at compile time or tha
70. ediately appeared that the most suitable architecture to satisfy the above requirements was the federate one in which the system is divided in a number of autonomous nodes Every single node can operate independently from the others and is specialized for specific task it has processing power memory power supply and all the signal conditioning interface resources required to manage the particular sensor device it manages All the data generated by the modules are then shared by means of a common communications line a digital data bus Among the advantages of such an architecture the possibility to distribute the units across the aircraft permits to place every module as close to the sensor it manages as it is possible avoiding to lay down long noise sensible analog signal lines since information is immediately converted to a digital format processed and transmitted over a robust medium The nodes communicate with each other using a special version of CAN Aerospace protocol 3 that is an extremely lightweight protocol data format definition which was designed for the highly reliable communication of microcomputer based systems in airborne applications via CAN 2 with built in data time stamping capability The entire communication protocol is called CAN for Flight test Equipment CAFFE The choice hardware for the single module fell on a single multipurpose board whose primary functions were carried out by dsPIC30F4011 16 bit fixed point Digital
71. est priority task ready to run is always given control of CPU It is used when system responsiveness is important therefore this feature is explicitly required When a task makes a higher priority task ready to run the current task is preempted suspended and higher priority task is immediately given control of the CPU If an ISR makes a higher priority task ready when the ISR completes the interrupted task is suspended and the new higher priority task is resumed 3 3 1 1 Choosing the RTOS Using a survey in the RTOS world and excluding all operating systems with proprietary license substantially two products are emerged FreeRTOS 10 and ChibiOS RT 11 Remembering that both FreeRTOS and ChibiOS RT are distributed under GPL3 license 12 this means that it can be used the code or part of code for a commercial product The reasons that led to the choice of ChibiOS compared to FreeRTOS can be summarized as ChibiOS RT is designed for deeply embedded real time applications where execution efficiency and compact code are important requirements This RTOS is characterized by its high portability compact size and mainly by its architecture optimized for extremely efficient context switching ChibiOS RT has an efficient and portable preemptive kernel best in class context switch performance i e withARMCM3 STM32F4xx 168 GCC4 6 2 the context switch time is 0 4045 with a kernel size of 6172 byte all the non debug subsystems enabled The archit
72. eturn uartStartReceivel then callback return Figure 3 7 UART driver receiver diagram 42 3 3 Thread definitions High Level Software Requirements 3 3 9 CDU thread The CDU thread should configure hardware abstraction layer and ChibiOS s UART module in order to use the multifunction touchscreen and other GPIO peripheral for the CDU Since the rotary supply selector switch is fully connected to Mnemosine with hardware cables no software code is needed Only the recording switch is monitored by the thread The multifunction touchscreen is linked with bluetooth module that is actually a normal UART module and doesn t need a specific abstraction layer 3 3 10 Control surface position thread The CDU thread should configure hardware abstraction layer and ChibiOS s ADC module The driver implements a state machine internally not all the driver functionalities can be used in any moment any transition not explicitly shown in the following diagram has to be considered an error adcStartConversion then async callback half buffer callback return async callback full buffer circular gt acg_endcb lt async callback full buffer adcStartConversion async send cb lt adeStart adcConvert sync ADC_ACTIVE adcStop adcStopConversion Converting async callback error gt error_cb lt adcStopConversion sync return ADC_STOP Low Power adcStart ADC_READ
73. f 1 pitcho steps_per_deg_slow else pitch rxbuf 4 gt gt 2 lt lt 8 rxbuf 1 pitch0 steps_per_deg_fast if rxbut 4 1 lt lt 1 gt gt 1 1 roll rxbuf 5 gt gt 2 lt lt 8 rxbuf 2 ro110 steps_per_deg_slow else ro11 rxbuf 5 gt gt 2 lt lt 8 rxbuf 2 ro110 steps_per_deg_fast void calibrateZeroes void ulate_t i uint8_t data GYRO_RX_DEPTH for i 0 i lt 10 i 110 i2cAcquireBus amp 12CD2 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 I C Driver source code status i2cMasterTransmitTimeout amp 12CD2 GYRO_REC 0x00 1 data 6 tmo i2cReleaseBus amp 12CD2 yaw0 data 3 gt gt 2 lt lt 8 data 0 10 average 10 readings for each zero pitch0 data 4 gt gt 2 lt lt 8 data 1 10 ro1104 data 5 gt gt 2 lt lt 8 data 2 10 chThdSleepMilliseconds 5 static const I2CConfig i2cfgi OPMODE_I2C 400000 FAST_DUTY_CYCLE_2 int main void BaseSequentialStream chp hallnit chSysInit Activates the serial driver 3 using the driver default configuration x PD8 TX and PD9 RX are routed to USART3 sdStart amp SD3 NULL palSetPadMode GPIOD 8 PAL_MODE_ALTERNATE 7 palSetPadMode GPIOD 9 PAL_MODE_ALTERNATE 7 chp amp SD3 Starts I2C2 PF0 SDA
74. f out csp r nAIR sizeof r nAIR out air sizeof out air r nSF sizeof r nSF out sf sizeof out sf IN EINGES N sizeok r nGPs out gps sizeof out gps NN E nEDU 5 sizeot r nCDU out cdu sizeof out cdu r nEND r n sizeof r nEND r n for i 0 i lt 101 i out ahrs i J _ out air i out cdu i J out csp il out gps i J outiast il N end infinite loop return 0 y end thread gt gt 3 105 O oND KF WN WO ND DD NY NYNYNNNNHPHEP HH eee FOOMONATKEWONHF CHM ANDAR No 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Appendix B SVC IC Driver source code include ch h include hal h uint8_t last_overflow 0 icucnt_t last_width last_period static void icuwidthcb ICUDriver x icup last_width icuGetWidth icup static void icuperiodcb ICUDriver xicup last_period icuGetPeriod icup last_overflow 0 static void icuoverflowcb ICUDriver xicup last_overflow 1 static ICUConfig icucfg J ICU_INPUT_ACTIVE_HIGH 100000 100kHz ICU clock frequency x10usec icuwidthcb icuperiodcb icuoverflowcb ICU_CHANNEL_2 Application entry point int main void BaseSequentialStream chp hallnit chSysInit ti a Activates the serial driver 3 using the driver default configuration x PD8 TX and PD9 RX
75. g_t FileBufferP TIME_IMMEDIATE if O count AIR_COUNT_FREQ FileBufferP gt t flag FLAG_AIR chMBPost amp mbox_AIR msg_t FileBufferP TIME_IMMEDIATE if O count SF_COUNT_FREQ FileBufferP gt t flag FLAG_SF chMBPost amp mbox_SF msg_t FileBufferP TIME_IMMEDIATE if O count GPS_COUNT_FREQ FileBufferP gt t flag FLAG_GPS chMBPost amp mbox_GPS msg_t FileBufferP TIME_IMMEDIATE if O count CDU_COUNT_FREQ FileBufferP gt t flag FLAG_CDU chMBPost amp mbox_CDU msg_t FileBufferP TIME_IMMEDIATE if 98 count FileBufferP gt t flag FLAG_SD chMBPost amp mbox_SD msg_t FileBufferP TIME_IMMEDIATE FileBufferP gt t flag 0 idle state return 0 end time dispenser 99 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 Appendix B SVC int main void vint8_t i for i 0 i lt 101 i out ahrs iJ out airji j out cdu i J outcsp ij _ s out gps i J outs ij Init Mailboxes chMBInit amp mbox_AHRS mbox_buf_AHRS 1 chMBInit amp mbox_CSP mbox_buf_CSP chMBInit amp mbox_AIR mbox_buf_AIR chMBInit amp mbox_SF mbox_buf_SF chMBInit amp mbox_GPS mbox_buf_GPS chMBInit amp m
76. ghts were also controlled by weight shift most of the current weight shift ultralights use a hang glider style wing below which is suspended a three wheeled carriage which carries the engine and aviators These aircraft are controlled by pushing against a horizontal control bar in roughly the same way as a hang glider pilot flies Trikes generally have impressive climb rates and are ideal for rough field operation but are slower than other types of fixed wing ultralights Powered parachutes cart mounted engines with parafoil wings which are wheeled aircraft Powered paragliding backpack engines with para foil wings which are foot launched Pow ered hang glider motorized foot launched hang glider harness Autogyro rotary wing with cart mounted engine Gyrocopter is different from a helicopter since the rotating wing is not powered the engine provides forward thrust and the airflow through the rotary blades causes them to autorotate or spin up to create lift Helicopter there are a number of single seat and two place helicopters that are included in the microlight categories in many countries such as New Zealand However few helicopter s design are included in the more restrictive FAA ultralight category Hot air balloon there are numerous ultralight hot air balloons in the USA and several more have been built and flown in France and Australia in recent years Some ultralight hot air balloons are hopper balloons while others a
77. gure hardware abstraction layer and ChibiOS s UART module After the initialization phase the thread must perform a communication test in case of errors will have to report it in an appropriate way Every 100 ms 10 Hz the time scheduler will ensure the enforceability of the loop using the traditional command response method with the stick force conversion board sited near the cloche 41 3 Software Realization 3 3 8 AHRS thread It is the thread that runs at higher frequency 50 Hz or 20 ms The AHRS thread should configure hardware abstraction layer and ChibiOS s UART module After the initialization phase the thread must perform a communication test in case of errors must report it in an appropriate way Once entered the stage of loop it should require the latest data to the AHRS receive and store it uartStop uartStart uartinit UART_STOP uartStart UART_READY Low Power Clock Enabled uartStop Figure 3 5 UART driver uartStopSend gt uc_txend2 lt uartStartSend uartStopSend uartStartSend buffer transmitted gt uc_txend1 lt uartStartSendl then callback return callback return Figure 3 6 UART driver transmission diagram receive error uartStartReceive gt uc_rxerr lt Fatal Error uartStopReceive gt uc_rxchar lt gt Uc_rxerr lt buffer filled gt uc_rxend lt uartStartReceive uartStopReceive callback r
78. ial By using two pairs of wires and of course with two similar circuits it is possible to obtain the full duplex connection Unlike EIA RS 485 from which it differs only for the ability to be on line in the high impedance if not selected the EIA 422 does not allow multiple transmitters but only multiple receivers Unlike the standard EIA RS 232 is designed to directly connect two devices either DTE or DCE with high noise immunity even at considerable distances typically up to 1550 m and at considerable speed Since the change of state of the data is determined by the difference of the voltages on the two wires in a balanced mode 0 to 5 V and 5 V on the two conductors respectively and since the wire is a twisted pair this standard is resistant to the electrical noise and jamming disturbance high noise immunity The maximum length of cable is 1550 m for speeds up to 1 Mbit s RS485 EIA RS 485 equivalent to the European standard CCITT V11 is a specific OSI Model 18 Physical Layer of a two wire half duplex and multi point serial interface The standard specifies a management system of the signal in differential form the difference between the voltage present on the two wires constitutes the data in transit A polarity indicates a logic level 1 and the null state the logic level 0 The potential difference should be at least 0 2 V for a valid operation but any voltage between 12 V and 7 V allows the correct operation of the receiver Th
79. ital to analog converters DAC There are 16 stream direct memory access DMA that can be used to direct transfer of data from or to memory to minimize the interruptions caused by program controlled data transfers The STM32F407 contains twelve 16 bit and two 32 bit timers up to 168 MHz each with up to 4 input capture output compare or pulse width modulation PWM Up to 15 communication interfaces are present which include three I C interfaces 4 universal synchronous asynchronous receiver transmitter USART and two UART 10 5 Mbit s ISO 7816 interface three SPI 37 5 Mbits s two of which capable of muxed full duplex inter IC sound IT S to achieve audio class accuracy via internal audio phase locked loop PLL or external clock Last two communication interfaces are essential for Mnemosine the two CAN interfaces and Secure Digital Input Output interface SDIO which allows saving all flight data 15 2 Hardware Realization Arduino Duino Maple platform GPIO ports PE and PD connectors WKUP button TIT LED ps pea Mount hole SD card Ethernet SWD JTAG USB OTG 2 GND pinhole USB OTG 1 UEXT Battery connector Boot jumpers PWR LED Reset button GPIO ports PF and PG Arduino Duino Maple platform connectors Figure 2 3 STM32E407 Layout This microprocessor is used by several development board manufacturers with the effort to meet as many as possible requirements with a single board In this project it was decided to
80. ks during the conversion process A callback is invoked when the operation has been completed or in circular mode when the buffer has been filled and the operation is restarted In linear and circular modes a callback is also invoked when the buffer is half filled The half filled and filled callbacks in circular mode allow to implement streaming processing of the sampled data while the driver is busy filling one half of the buffer the application can process the other half this allows for continuous interleaved operations Said this more than one choice is possible it is currently foreseen the use of a circular buffer to obtain a filtered measure for each channel 3 3 11 Air thread The AIR thread should configure hardware abstraction layer and ChibiOS s IPC Inter Integrated Circuit module The driver implements a state machine internally not all the driver function alities can be used in any moment any transition not explicitly shown in the following diagram has to be considered an error 2C_ACTIVE_T Bus TX Active cMasterTransmit RDY_TIMEOUT ecStart completed ecStop 2C_ACTIVE_R Bus RX Active cMasterReceive l2C_READY Clock Enabled RDY_TIMEOUT cStart completed l2C_LOCKED Bus Locked l2C_STOP Low Power Figure 3 9 IPC driver As for the other thread after an initialization phase the algorithm must test comm
81. l functions previously unheard of or previously performed by electro mechanical pneumatic or hydraulic devices Each new generation of aircraft had more on board electron ics for communication navigation and other functions Weather radar was introduced The cockpit instruments that in the thirties had become full of electro mechanical instruments were replaced by an Electronic Flight Instruments System EFIS and an Engine Indicating and Crew Alerting System EICAS The vacuum tube electronics became transistor electronics the transistor was soon replaced by integrated circuits The birth of digital electronics and the asso ciated digital computer marked the beginning of a new era in aviation in which we experienced an increased growth in aircraft system capabilities The rapid development of electronics and software intensive systems contributed considerably to the development of aviation The minia turization of the electronic modules enabled more functions to be installed in less space with less weight and consuming less electrical power Automatic Flight Control systems took over the classical autopilot functions but they were also put to work for automatic landings and stability augmentation or even to provide artificial stability in aircraft with inherent instability The hydro mechanical method of control surface actuation was in some modern aircraft replaced by a new method These aircraft such as the civil Airbus 320 passenger trans
82. lication for each peripheral of the system these application program are easier to design and to maintain in comparison to a single background software Currently there are many types of operating systems each of them with their own particu larities and peculiarities Below it will be exposed the motivations that led to the choice of the RTOS 33 3 Software Realization Task also called thread is a simple program that thinks it has the CPU all to itself The design process for our real time application involves splitting the work to be done into tasks responsible for a portion of the problem To each task is assigned a priority its own set of CPU registers and its own stack area Kernel is the part of multitasking system responsible for management of task i e for man aging the CPU s time and communication between tasks A kernel adds overhead to the system because the services provided by the kernel requires execution time The amount of overhead depends on how often these services are invoked and naturally how the kernel is made One of the major performance index for kernel is the Context Switch When a multitasking kernel decides to run a different task it saves the current task s context CPU registers in the current task s context storage area After this operation is performed the new task s context is restored from its storage area and then resumes execution of the new task s code Preemptive kernel means that the high
83. lowing capabilities Data acquisition of the following parameters Air data static pressure P_STAT dynamic pressure P_DIN OAT AOA AOS GPS data 3D ECEF position 3D ECEF velocity Stick force Control Surface positions elevator ELE POS rudder RUD_POS aileron AIL_POS flaps FLP_POS Engine data RPM EGT Fuel Flow Data saving on secure digital SD ETH port communication CAN port communication IC port communication Software maintenance via USB port Ensure data synchronization TZ POLITECNI BA A MNEMOSINE MKIV FLIGHT TEST US Y ISTRUMENTATION M_FTI_SRS rev A AN SS Software Requirements Specification SRS pag 6 27 1 3 DOCUMENT OVERVIEW This document is organized in the following chapters chapter 1 defines MNEMOSINE FLIGHT TEST ISTRUMENTATION contents and system summary chapter 2 contains all the functional requirements chapter 3 contains the Acronym List 1 4 OPERATIVE SOFTWARE REQUIREMENTS NOTATION The following notation has been used in order to guarantee a project unique identifier for each OPSW requirement THD_xxx_yyy_zzz The characters xxx denote the type the requirement belongs to among the following HAL hardware abstraction layer COM peripheral communication CAL calculate compute do something SAV save UPT update EXP export data The characters yyy denote the type the requirement bel
84. lsr uartStartSendI amp UARTD3 14 Hello World r n chSysUnlockFromlsr static void ledoff void xp void p palClearPad GPIOC GPIOC_LED This callback is invoked when a transmission buffer has been completely x read by the driver static void txendi UARTDriver x uartp void uartp palSetPad GPI0C GPIOC_LED This callback is invoked when a transmission has physically completed static void txend2 UARTDriver x uartp void uartp palClearPad GPIOC GPIOC_LED chSysLockFromlsr if chVTIsArmedI amp vt1 chV TResetI amp vt1 chVTSetI amp vti MS2ST 5000 restart NULL chSysUnlockFromlsr This callback is invoked on a receive error the errors mask is passed as parameter static void rxerr UARTDriver xuartp uart lags_t e void uartp void e This callback is invoked when a character is received but the application was not ready to receive it the character is passed as parameter static void rxchar UARTDriver x uartp uint16_t c 92 USART UART Driver source code 57 58 void uartp 59 void c 60 Flashing the LED each time a character is received x 61 palSetPad GPIOC GPIOC_LED 62 chSysLockFromlsr 63 if chVTIsArmedI amp vt2 64 chV TResetI amp vt2 65 chVTSetI amp vt2 MS28T 200 ledoff NULL 66 chSysUnlockFromlsr 67 y 68 69 This callback is invoked when a r
85. mosine con una parentesi rivolta al mondo dell aviazione la ricerca formale dei nuovi requisiti raccolti durante le campagne di flight test sia in ambito accademico sia in ambito aziendale grazie al progetto Poli XFlight Segue il progetto di massima dell hardware che in alcuni casi si spinger pit in dettaglio secondo le esigenze funzionali e la descrizione della filosofia software fino alla redazione della specifica dei requisiti e la presentazione dei codici di validazione realizzati con lo scopo di verificare l effettiva fattibilit dell intero progetto Abstract This thesis was created to meet the demand for a new generation of flight test instrumentation for ultra light aircraft developed by the Dipartimento di Scienze e Tecnologie Aerospaziali of Politecnico di Milano This instrumentation will replace the previous version called Mnemosine MK II which essentially consists of several metal cases containing nodes each one with its own characteristics which communicate with each other through a specially developed protocol based on Controller Area Network CAN What follows is the result of several analysis aimed at developing the new flight test instru mentation FTI system called Mnemosine MK IV Thanks to the progress of the semiconductor industry this new version introduces the integration of multiple nodes in a single central unit whose operations are governed by a real time operating system Right from the start it exposes th
86. n of the task To give a fair priority execution to each thread it is set at the creation time in the main The priority policy is based on the need of time of each task Assigning task priorities is not a trivial undertaking because of the complex nature of real time system An interesting technique called rate monotonic scheduling RMS has been established to assign task priorities based on how often tasks execute Simply put tasks with the highest rate of execution are given the highest priority Given a set of n task that are assigned RMS priorities the basic RMS theorem states that all task hard real time deadlines are always met if the inequality in the following equation is verified Ei 1 Dag nl re Where E corresponds to the maximum execution time of task i and T corresponds to the E execution period of task i In other words a corresponds to the fraction of CPU time required to i execute task 35 It is likely that Mnemosine MK IV can not be run entirely by this philosophy but RMS is a good starting point 38 3 3 Thread definitions High Level Software Requirements 3 3 3 SD thread The SD thread should configure hardware abstraction layer and ChibiOS s SDC module The SDC driver implements a state machine internally not all the driver functionalities can be used in any moment any transition not explicitly shown in the following diagram has to be considered an error sdcStop SDC_STOP Low
87. nemosine MK IV will be made up by a microcontroller unit MCU mounted on the mother board which also provides all inputs for external sensors all power supply components and of course all plug connectors for external module Mnemosine MK IV will be equipped with sensors able to acquire e air data total air pressure static air pressure angle of attack AOA angle of sidesleep AOS e engine data propeller revolutions per minute RPM fuel flow exhaust gas temperature EGT e control surface positions aileron equilibrator rudder flap e stick forces e 3D inertial data accelerations Eulerian angle rates Eulerian angles e GPS data The lower level requirements of Mnemosine MK IV must ensure e the use of a standard development board e communication with GPS module with time pulse over UART port attitude heading reference system AHRS platform over multi mode serial peripheral interface RS232 RS485 RS422 embedded stick force acquisition system over multi mode serial peripheral interface RS232 RS485 RS422 SD card CDU also through bluetooth module Ethernet port CAN port air data computer ADC over Inter Integrated Circuit port I C e possibility of software upgrade through universal asynchronous receiver transmitter port UART 11 2 Hardware Realization All the choices that led to the final hardware configuration of the system Mnemosine MK IV will be motivated in this ch
88. noted that the following demos require the use of e ChibiStudio v2 5 or later e OLIMEX STM32E407 development board P e OLIMEX ARM USB TINY HB All source code are presented in Appendix B while Appendix C shows how to load and update the software using the two supported systems UART and JTAG April 4 2013 Ma DIE NL TERM Bea E A o ridic sourceforge net proj jects chibios files Ce tudio 47 4 Hardware amp Software Suitability Validation Code 4 1 Serial Driver SVC The purpose of this SVC is to verify the functionality of the ChibiOS RT Serial Driver with the board STM32E407 While the code is running the green led blinks every second and connecting a USB TTL converter from PC to PD11 TX data and PD12 RX data with a serial virtual terminal the hello world message is shown HAL Init ChibiOS Init Start Serial Driver 3 Setting MCU Pad Serial Mode Toggle Led Sleep 1000 ms Figure 4 1 Serial Driver SVC Flowchart After having extensively tested the software the serial port communication requirement is deemed satisfied 48 4 2 USART UART SVC 4 2 USART UART SVC The purpose of this SVC is to verify the functionality of the ChibiOS RT UART Driver with the board STM32E407 While the demo is running after connecting a USB TTL converter from PC to PD11 TX data and PD12 RX data the green led blinks every time a character is received or the hello wo
89. of the fast developing aviation sector In a few years the Agency will also be responsible for safety regulations regarding airports and air traffic management systems 1 3 1 CS VLA This Certification Specification was born in 2003 called Certification Specification Very Light Aircraft or CS VLA This airworthiness code is applicable to aeroplanes with a single engine spark or compression ignition having not more than two seats with a Maximum Certificated Take off Weight of not more than 750 kg and a stalling speed in the landing configuration of not more than 83 km h CAS to be approved for day VFR only This CS VLA applies to aeroplanes intended for non aerobatic operation only Non aerobatic operation includes any manoeuvre incident to normal flying stalls except whip stalls and lazy eights chandelles and steep turns in which the angle of bank is not more than 60 29 1 3 2 CS LSA Since 2011 the EASA issued a new type certificate called Certification Specification Light Sport Aircraft CS LSA that is applicable to Light Sport Aeroplanes to be approved for day VFR only that meet all of the following criteria e Maximum Take Off Mass of not more than 600 kg for aeroplanes not intended to be oper ative on water or 650 kg for aeroplanes intended to be operative on water e Maximum stalling speed in the landing configuration of not more than 83 km h CAS at the aircraft s maximum certificated Take Off Mass and mo
90. ongs to among the following DEF definition STP setup structure FUN function TST test and zzz denote a serial number useful for identification TZ POLITECNI ER MULAS MNEMOSINE MKIV FLIGHT TEST m N ISTRUMENTATION M_FTI_SRS rev A AEN SS Software Requirements Specification SRS pag 7 27 2 CAPABILITY REQUIREMENTS 2 1 Air data Thread Name air_com_thread Thread Acronym AIR Thread Priority NORMAL_PRIO 10 Pointer Input argument struct Output argument struct Air_Data_Struct HAL reference I2C2 AIR_HAL_DEF_001 The OPSW shall Define the following object systime_t WAIT TIME AIR_HAL_STP_001 The OPSW shall Setting up static const I2CConfig i2c_air_ fg in compliance with I2C communication protocol of URANIA AIR_HAL_FUN_001 The OPSW shall setting up i2cStart amp I2CD2 amp i2c air fg TZ POLITECNICO No Software Requirements Specification SRS pag 8 27 AIR_COM_TST_001 The OPSW shall perform a communication test with URANIA in order to ensure the effectiveness both in receiver and transmitter state AIR_COM_TST_002 The OPSW shall once assured proper communication the thread must check the consistency of the received data AIR_COM_FUN_001 The OPSW shall the thread enters in a wait state until it receives a start on its mailbox result chMBFetch mbox amp fileBufferP WAIT_TIM
91. ontrol surface position thread 22 222 2 nn nn nn 9 311 Air thread covers eae ae a ROP ae ee 3 4 Software Requirements Specification SRS oo 4 Hardware amp Software Suitability Validation Code AT Serial Driver VOL e pas ne srr dg rag AA a Bae ad 4 2 USART UART SVG 2 090 8 end bt a u Re OSH HR Sawa ae 4 3 Analog to Digital Converter SVO 22 2222 a 44 SD SDIO Mode SVC 2 0 aoa a a p a aa a a a e a a a 4 5 Time Scheduler SVC aasa erarnan ee 4 6 Input Capture SVC serwa ac 3 Be ee ee re 4 7 CAN SVC 48 T C SVC 5 Conclusion and Future Developments 5 1 Prototyping sa sa saa doe ae ER einer Ee Re ee A 5 2 Conclusion Bibliography Appendix A SRS 33 33 34 36 37 38 38 39 40 40 41 41 42 43 43 44 45 47 48 49 50 52 53 55 56 57 59 59 59 61 63 CONTENTS Appendix B SVC 91 Serial Driver source codel nam na n 91 ce E ews spa 92 A BS RO eh Ge ae ar 94 SDIO Driver source code 222 22 2 anna 96 A hot wae ee are a es 98 IC Driver source COJO sos u sos ar ace he ee ha BAe awe Ow wa ee 8 106 CAN Driver source codel saos 22 2 2 mm p nern 108 IC Driver source Code 110 Appendix C ChibiStudio 113 Appendix D Software Upgrade Procedures 115 JTAG cria ER ee a he os 115 ee O A AN A A ee AA ee oe 118 vii List of Figures 1 1 Block diagram of Mnemosine MK II 2 00 4 9 air we en a eee a 10 Wad grat
92. owing table mode a Bl y 0 off off off off off off 232 on off off off off 422 off on off off on 485 TX off on off off off 485 RX off off on off off Table 2 1 Pin configuration of multi mode serial peripheral interface 19 2 Hardware Realization It turns out that the Transmission Enable 6 of the second driver 485 will be permanently disabled To conclude other 4 general purpose input output GPIO are needed for the following functions GPIO Function 12 enable n digital out Y 5 enable L event in Table 2 2 Pin configuration of multi mode serial peripheral interface 20 2 4 Analog Signal Conditioning Module 2 4 Analog Signal Conditioning Module For the position detection of the control surfaces as for the old version of the Mnemosine FTI potentiometric sensors will be used This easy integration type of sensor guarantees the per formance of a common linear rigid rod potentiometer but at the same time allows an adequate safety from the moment in which a malfunction of the same thanks to the wire behaving like a programmed fracture allows however the government of the surface The potentiometer FMDK46 1000 produced by Atheris 25 is the smallest design in this sensor class with measur ing range of 1000 mm resolution 0 3 mm and it is able to work within temperature range of 20 C to
93. port feature Fly By Wire technology The command inputs from the pilot are no longer mechanically transferred to the control servos but electrically by a simple pair of electrical wires In the future these wires will be replaced by fibre optic data links i e the Fly By Light concept In the late eighties the Global Positioning System GPS 1 Introduction was introduced allowing very accurate navigation worldwide Modern electronics are required to perform many complex functions in a very short or near real time To achieve this present day electronic circuitry has to work with very low energy levels which makes it sensitive to interference from outside sources generating electrical or electromagnetic fields Today s modern aircraft have numerous electronic systems for numerous functions all of which have to be tested in flight It is no wonder that the job of the FTE has changed considerably over the years Flight test engineering can be summarized as the engineering associated with the testing in flight of an aircraft or item s of aircraft equipment The aims of that testing can be very different investigate new concepts provide empirical data to substantiate design assumptions or demonstrate that an aircraft and or its equipment achieve specified levels of performance etc Thus flight testing covers a broad spectrum of topics all demonstrating that there is a degree of novelty in the aircraft its equipment or its intended usage
94. ration of the system initially within flight case and then on board of an ULM the occasion could probably occur during the flight tests performed during the course of Sperimentazione in Volo which is discussed in advance Considering a work team consisting of one person a project manager and one aircraft s specialist it is expected that the final integration phase until the first flight test should last about three more weeks However considering strong innovation in the project it is reasonable to expect at least a week of delay for each phase 5 2 Conclusion The aim of the present work was to verify the feasibility of the project coming to the preliminary design of both hardware and software of the new data acquisition system for flight test of ULM The work started from requirements analysis while to choose the sensors performance and their measurement range it has been taken for granted the past experience Mnemosine MK III In accordance with the mission requirements the sensors that are currently been identi fied as the best possible choice are Olimex STM32E407 development board Sensors Technics HCLA0050EU and HCA0611ARHB8 pressure sensors Xsens MTi AHRS U Blox LEA 5T GPS module 59 5 Conclusion and Future Developments In the last days before the end of the thesis two other requirements have been added Today it is increasingly common to use EFIS Electronic Flight Instrument System specialized for light aircraf
95. re regular hot air balloons that carry passengers in a basket Advanced ULM is a ULM that responds to the technical specification reported in the Decreto Presidente della Repubblica 9 10 2010 n 133 also called DPR 133 2010 These types of advanced ULM are equipped with radio A or C mode transponder and Emergency Locator Transmitter ELT registered at the AeCI Aeroclub d Italia as advanced ULM In most countries microlights or ultralight aircraft now account for a significant percentage of the global civilian owned aircraft The increasing cost of fuel the current crisis and the research of a low cost way to fly are indexes of expansion of the ULM market 1 3 EASA 1 3 EASA The European Aviation Safety Agency EASA promotes the highest common standards of safety and environmental protection in civil aviation in Europe and worldwide Its first aim is to provide an unique regulatory system for the entire European aviation market The agency s responsibilities include e Expert advice to the EU for drafting new legislation e Implementing and monitoring safety rules including inspections in the Member States e Type certification of aircraft and components as well as the approval of organizations involved in the design manufacture and maintenance of aeronautical products e Authorization of third country non EU operators e Safety analysis and research The agency s responsibilities are growing to meet the challenges
96. rld message is shown The driver restarts every five seconds HAL Init ChibiOS Init Start UART Driver 3 UART Send Message Toggle Led Wait 200 Sleep 5000 ms Sleep 500 ms sien 5000s Figure 4 2 USART UART Driver SVC Flowchart After having extensively tested the software the UART port communication requirement is deemed satisfied 49 4 Hardware amp Software Suitability Validation Code 4 3 Analog to Digital Converter SVC The purpose of this demo is to verify the functionality of the ChibiOS RT ADC Driver with the board STM32E407 While the demo is running after connecting a USB TTL converter from PC to PD11 TX data and PD12 RX data the green led blinks every time a string that contains the eight measure repeated twice is shown The conversions are done automatically and continuously every 56 system ticks Please note that the conversion is valid for a signal between OV 3 3V and 3 3V is the maximum voltage rating The eight values come from ADC3 Channel STM32 Pad External Connector Pin INO PF3 PF pin 6 IN14 PF4 PF pin 7 IN15 PF5 PF pin 8 IN4 PF6 PF pin 9 IN5 PF7 PF pin 10 IN6 PF8 PF pin 11 IN7 PF9 PF pin 12 IN8 PF10 PF pin 13 Table 4 1 ADC board pin configuration 50 4 3 Analog to Digital Converter SVC HAL Init ChibiOS Init Start Serial Driver 3 Start ADC Driver 3 Capture samples Wait 56
97. s task have to be performed not only correctly but on time Mnemosine MK IV like most real time systems have a combination of soft and hard requirements This systems are called foreground background systems or super loops An application consists of an infinite loop that calls modules i e function to perform the de sired operation background or task level Interrupt service routine ISR handles asynchronous events foreground that is also called interrupt level Critical operations must be performed by ISRs to ensure that they are dealt with in timely fashion Because of this ISRs have the tendency to take longer than they should Also informa tion for background module that an ISR makes available is not processed until the background routine gets its turn to execute which is called the task level response During the operation of the software the Real Time Operating System RTOS inside Mnemo sine MK IV must guarantee the determinism of events for this reason all task and functions have a specific timeout Shared Resource can be used by more than one task Each task should gain exclusive access to shared resource to prevent data corruption This process is called mutual exclusion and of course this feature must be present in the chosen RTOS Multitasking is the process of scheduling and switching the central processing unit CPU between several tasks Multitasking allow to have more backgrounds this helps to design a specific app
98. s deemed satis fied http invensense com mems gyro itg3200 html April 4 2013 97 5 Conclusion and Future Developments 5 1 Prototyping Now that the hardware and software configuration until the test demos has been fully described it s time to create the first prototype First it is necessary to integrate the wiring diagrams to realize the motherboard which will be assembled on the microcontroller and other peripheral cards including GPS module Considering a work team consisting of one person and a project manager it is expected that the hardware integration phase including also the physical realization of the board should last about two months The second step is to write the definitive source code which can be then tested in its entirety and decide the size of the individual threads i e the physical division of the RAM that at this design stage couldn t be determined At the beginning the task priority will be assigned according to the rate monotonic scheduling philosophy where basically high speed thread has priority on low speed thread After having extensively tested the software and according to their results it will be obviously clear the good task priority policy Considering a work team consisting of one person and a project manager it is expected that the software integration phase including the debugging of the source codes should last about two more months The third phase will involve the final integ
99. s platform and unofficially for Linus LyX Documenti TESI Tes M Te cpu mem_swap Ogiomi y C C STM32F407_Mnemosine_Test_v4 main c Eclipse SDK x File Edit Source Refactor Navigate Search Projet Run Window Help Hr Br Qe rr er Sr Br Or Qr GS ay la Acce BE Ea debug Project Explorer 5 aS vro r del main c amp g a wu MDL MEME eave HERA a I STM32F407_Mnemosine_Test_v3 include hal h Y G STM32F407_Mnemosine_Test_v4 include global h Be gt Dindud include time_task h ema include sd_task h gt Ga boards include data_struct h gt build include ff h gt Ga fat s 1 global var gt Gaos int16_t count gt chconf h GLOBAL OBJECT gt 2 csp_task c gt csp_task h FRESULT rc FIL Fil gt 3 data struct c amp El Fil B data amp UINTI bw gt data struct h de FATFS MMC_FS FS object gt 2 engine task c MMCDriver MMCD1 MMC driver instance Sen bool_t fs_ready FALSE FS mounted and ready er Maximum speed SPI configuration 18MHz CPHA 0 CPOL 0 MSb first gt ffconf h SPIConfig hs_spicfg NULL GPIOB GPIOB_PIN12 0 gt 2 global c Low speed SPI configuration 281 250kHz CPHA 0 CPOL 0 MSb first gt global h gt A halconf h EJ Console Problems Tasks X E Properties Raa cl gt td 54 items gt mcuconf h Y Description Resource Path Location Type gt 2 sd task c FIXME only gets here if there are other M
100. shall Define the following object static FATFS SDC_FS static bool_t fs ready FRESULT err rc FATFS fsp FIL Fil UINT bw char fold SD_HAL_FUN_001 The OPSW shall setting up sdcStart amp SDCD1 NULL uint32_t clusters O POLITECNICO un Software Requirements Specification SRS pag 22 27 SD_COM_TST_001 The OPSW shall perform a communication test with SD card in order to ensure th ffectiveness both receiver and transmitter state SD_COM_TST_002 The OPSW shall once assured proper communication the thread must check the card f getfree amp clusters amp fsp free clusters clusters sectors per cluster uint32_t SDC_FS csize bytes free clusters uint32_t SDC_FS csize uint32_t MMCSD_BLOCK_ SIZE SD_CAL_FUN_001 The OPSW shall Create a new mission folder with sequential identification number Copy the path to the new folder into fold variable SD_COM_FUN_001 The OPSW shall the thread enters in a wait state until it receives a start on its mailbox result chMBFetch mbox amp fileBufferP WAIT TIME result could be RDY OK if a message has been correctly fetched RDY RESET if the mailbox has been reset while waiting RDY_ TIMEOUT if the operation has timed out AOE EN A MNEMOSINE MKIV FLIGHT TEST ISTRUMENTATION M_FTI_SRS rev A 8 ee A Software Requirements Specification SRS
101. st critical centre of gravity e Maximum seating capacity of no more than two persons including the pilot e Single non turbine engine fitted with a propeller and non pressurized cabin https www easa europa eu what we do php April 4 2013 1 Introduction The CS LSA is applicable to aeroplanes that are by definition engine driven by design and there fore CS LSA is not applicable to powered sailplanes that are designed for sailplane characteristics when the engine is inoperative 33 1 4 ULM Regulation in Italy 1 4 ULM Regulation in Italy Currently in Italy there are two types of ultra light categories e Ultralight or Ultraleggero is an aircraft totally not certified with the following main fea tures Maximum weight requirements excluding seat belts parachute and instruments Single seat maximum weight of 300 kg and 330 kg for amphibious stall speed must not exceed 65 km h Two seat maximum weight of 450 kg and 500 kg for amphibious Must remain within the territory of the state From 30 min before dawn till 30 min after sunset flight must be below 500 ft 152 m on Saturday and holidays flight must be below 305 m with 5 km separation from airports not located within Air Traffic Zone ATZ e Advanced ULM or Ultraleggero Avanzato must comply with the law DPR 133 2010 and its main features are Land version Maximum Take off Weight MTOW must not exceed 600 kg that be come 630
102. t can overflow at run time no upper bounds the internal structures are all dynamic even if all the objects are statically allocated System application program interface API has no error conditions all the previous points are finalized to this objective The APIs are not slowed down by parameter checks they do exist but only are activated when the related debug switches All the static core APIs always succeed if correct parameters are passed Exception to this rule are the optional dynamic APIs that of course can report memory exhausted e Note first fast then compact the focus is on speed and execution efficiency and then on code size This does not mean that the OS is large the kernel size with all the subsystems activated weighs around 5 5KiB STM32 Cortex M3 Test results on all the supported platforms and performance metrics are included in each ChibiOS RT release The test code is released as well all the included demos are capable of executing the test suite and the OS benchmarks 30 35 3 Software Realization 3 2 Development Environment The development environment chosen for the realization of the software is ChibiStudio It is an Integrated Development Environment IDE composed by freely distributed softwares grouped in a handy suite It is essentially composed by Eclipse Juno 4 2 classic configured for execution of embedded applications Today is officially distributed and free of chargd for Window
103. t and it is requested the ability to interface this device with Mnemosine The second request is the ability to record cockpit voice directly with MK IV to get a synchronous audio track with other aircraft data The choice of how to arrange the boards inside the hardware case has not been decided yet Preserving the schematics more than one configuration is possible and during the prototyping phase will be identified the best choice The most suitable solution now consists of a horizontal motherboard where the MCU is also housed horizontally while the serial adapter boards and the analog conditioning boards are arranged vertically hence connected by side It is expected that this arrangement minimizes the volume used GPS Module Figure 5 1 Boards Arrangement Using all Open Source SW helped to keep down the overall budget It was possible to test all the features of the system by purchasing only the development board and the debugger for about a hundred euros Currently it is expected a final expenditure in line with the budget estimated in the preliminary phase for about a few thousand euros The strong push by the authorities for a safer aviation will force the aviation industry to perform more systematic flight test campaign and we are confident that Mnemosine MK IV will be the reference point for the Design and Development of each Flight Test Instrumentation System for Light Aircraft 60 Bibliography 1 2 3 4 5
104. ticks Write Samples Sleep 1000 ms Figure 4 3 ADC Driver SVC Flowchart After having extensively tested the software the analog to digital converter requirements are deemed satisfied 51 4 Hardware amp Software Suitability Validation Code 4 4 SD SDIO Mode SVC The purpose of this demo is to verify the functionality of the ChibiOS RT SDIO Driver with the board STM32E407 While the demo is running after connecting a USB TTL converter from PC to PD11 TX data and PD12 RX data the green led blinks every half second If WakeUP button is pushed the SDIO s test is performed The task reads information about the SD card inserted and displays the results on the serial terminal emulator a new mission folder is created and inside the directory is written a generic log00 dat file Startup HAL Init ChibiOS Init Setting MCU Pad Serial Mode Start SD Card Driver 1 Start Serial Driver 3 Read Push Button Yes No Connecting to SD Card Mount File System Procedure Fail Yes Write Error Message Create New Folder Write FTI data into SD Card Unmount File System Disconnecting from SD Card Sleep 1000 ms Figure 4 4 SDIO Driver SVC Flowchart After having extensively tested the software the SDIO operational requirements are deemed satisfied 52 4 5 Time Scheduler SVC 4 5 Time Scheduler SVC The purpose
105. uart_cfg SF SF_HAL_FUN_006 The OPSW shall Setting up palSetPadMode GPIO_BASE SF GPIO_RX SF PAL MODE ALTERNATE 7 palSetPadMode GPIO_BASE_SF GPIO_TX_SF PAL MODE ALTERNATE 7 SF_HAL_FUN_007 The OPSW shall Setting up palSetPadMode GPIO BASE PIN A SF GPIO A SF PAL MODE OUTPUT_PUSHPULL palSetPadMode GPIO BASE PIN B SF GPIO B SF PAL MODE OUTPUT_PUSHPULL palSetPadMode GPIO_BASE PIN C SF GPIO C SF PAL MODE OUTPUT _PUSHPULL palSetPadMode GPIO BASE PIN D SF GPIO D SF PAL MODE OUTPUT_PUSHPULL palSetPadMode GPIO BASE PIN OUT_SF GPIO_OUT_SF PAL MODE OUTPUT_PUSHPULL palSetPadMode GPIO_BASE PIN IN SF GPIO_IN SF PAL MODE _INPUT_PULLDOWN SF_COM_TST_001 The OPSW shall perform a communication test with SF module in order to ensure th ffectiveness both receiver and transmitter state SF_COM_TST_002 The OPSW shall once assured proper communication the thread must check the consistency of the received data ASE NE A MNEMOSINE MKIV FLIGHT TEST ISTRUMENTATION M_FTI_SRS rev A MILANO 7 Software Requirements Specification SRS 000 120000000 pag 17 27 SF_COM_FUN_001 The OPSW shall the thread enters in a wait state until it receives a start on its mailbox result chMBFetch mbox amp fileBufferP WAIT TIME result could be RDY OK if a message has been correctly fetched RDY RESET if the mailbox has been reset while waiting RDY_ TI
106. ucts Through a simple comparison it emerged that the more suitable microcontroller for our purposes is produced by STMicroelec tronics 21 and it s called STM32F407 2 1 1 STM32F407 STM32F407 is in fact not a single chip but identifies a whole family of controllers based on ARM CORTEX M4 32 bit with reduced instruction set code RISC 23 capable of operating up to 168 MHz clock frequency The CORTEX M4 is equipped with a single precision floating point unit FPU and is therefore able to work with all types of data and instructions An other peculiarity is the presence of a digital signal processor DSP and memory protection unit MPU that improves the security of the application code 13 The memory of the microprocessor is composed by up to 1 Mbyte of flash memory and up to 192 4 Kbytes of static random access memory SRAM including 64 Kbyte of core coupled memory CCM that certainly guarantees an adequate memory space for the full application of Mnemosine MK IV The timing source is composed by a factory trimmed 1 accuracy 16 MHz crystal oscillator and a 32 kHz os cillator for the real time clock separately powered which can rely on 4 KBytes of SRAM The microcontroller shall be supplied from 1 8 V to 3 6 V It s possible to obtain a maximum of three 12 bit 2 4 MSPS analog to digital converters ADC with up to 24 channels and 7 2 MSPS in triple interleaved mode In opposite direction are also being offered two 12 bit dig
107. ulky highly intrusive especially considering the lack of real estate available in a 450 Kg Maximum Take Off Weight MTOW aircraft and very little flexible Keeping in mind the particular requirements of ULM aircraft and with the aim to realize a Flying Laboratory capable of fulfilling the necessities and requirements of both research and didactic activities the Dipartimento di Scienze e Tecnologie Aerospaziali of the Politecnico di Milano since 2007 it has launched the Mnemosine project to design make and exploit a low cost federated FTI system DPR 133 2010 1 2 see allegato legge 106 85 1 Introduction 1 5 History of Mnemosine FTI 1 5 1 Initial requirements The system requirements are deeply influenced by the academic nature of the project Apart the unavoidable low budget constraints in fact the highly dynamic nature of the project called for a system capable of being upgraded or maintained in one or more components without affecting the operational capability of the remaining parts In addition it was clear that it was necessary to provide a huge growth potential because of the predictable expansion of the system as new inputs from the research activities will arise To summarize the initial requirements identify the system as a low cost reliable and flexible FTI which must be capable to assure a considerable growth potential open Other essential features of the system are non intrusive easy to manage and maintain It imm
108. unication with the air data computer Urania if positive with an interval of 100 ms 10 Hz the time scheduler require its execution 44 3 4 Software Requirements Specification SRS 3 4 Software Requirements Specification SRS A Software Requirements Specification SRS is a complete description of the behavior of a system to be developed In order to align a well established practice in the aviation world it is decided to draw up a formal SRS document that permits to verify the satisfaction of the requirements set forth above and allows to write a faster and more efficient source code The f y Time Pulse ChibiOS Init E x y CDU Management HW SW Interrupt A i __ Time Management lt i gt Sleep l I 1 AHRS Management document is entirely given in Appendix A Y IwIP Management y e m Figure 3 10 Overall Software Configuration Flowchart The diagram in Figure 3 10 shows the complete software architecture which summarizes all the individual threads previously seen 45 4 Hardware amp Software Suitability Validation Code The purpose of the following suitability validation code SVC is to show that the characteristics expressed by the requirements are fully met by the union of the chosen hardware and software It should be
109. which requires assessment in flight 1 1 1 Data Acquisition Methods At the beginning of flight testing the main source of flight test information was the flight test pilot s subjective judgment At best the pilot had some basic instruments the readings of which he could jot down on his kneepad if the maneuver permitted that NACA in 1930 was probably the first to use special flight instruments to record measurands of interest during flight tests for the determination of aircraft handling qualities At a later stage cameras were used to photograph or film the pilot s instrument panel or other panels specially installed in the test aircraft for the purpose of the flight test and provided with special instruments and warning or indicator lights These were the so called Automatic Observers or Photo Panel Recorders After WWII special flight test instruments became available in which a small mirror could be deflected under the influence of an electrical current an air pressure an acceleration or another physical phenomenon By reflecting a sharp light beam onto photo sensitive paper signals could be recorded From the early fifties Frequency Modulation FM techniques were used for recording these electrical signals on magnetic tape Later in the sixties Pulse Code Modulation PCM became the major recording standard This digital technique had the advantage of a better accuracy a bigger dynamic range so more data could be packed into
110. x D Software Upgrade Procedures a ae 15 Press Ctrl b to build the project if all has gone well in the Console a Done message will shown Procedure to create a new External Toll Configuration 1 2 Run External Toll External Tool Configuration gt New launch configuration In the Main window e Name OpenOCD 0 6 on Olimex Arm Usb Tiny H prompts for cfg target configu ration e Location eclipse_home tools openocd bin openocd e Working Directory workspace_loc ARMCM4 STM32F407 LWIP FATFS USB e Arguments c telnet_ port 4444 f interface olimex arm usb tiny h cfg f file_ prompt Select target configuration file workspace_loc tools openocd openocd scripts target stm32f4x cfg e Apply and Close Procedure to create a new Debug Configuration 1 2 o N no WN HH 116 Run Debug Configurations GDB Hardware debugging New launch configuration In the Main window e Name OLIMEX STM32E407_demo_0 OpenOCD Flash and Run e C C Application build ch elf e Project demo 0 browse e Built configuration default In the Debugger window e GDB command arm none eabi gdb e Remote target Use remote target JTAG device generic TCP IP localhost 3333 In the Startup window e Reset and delay second 1 e Halt no halt e Script set remote timeout 20 monitor reset init monitor sleep 200 monitor halt 2000 monitor

Design and development of Mnemosine MK IV

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