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187 - National Radio Astronomy Observatory

1. O eecht MEIN NN S ASV t3 IN Nn 8 8300101 TWIT 90 edd H v4 Hut 21001192103580 000015 010 9 TNO W3000N3 33 DL ANANI vm A NOT le VAVO 3002 INIL 1 7 001 Jdvi 1 811001121801 15 1003 028 IHi NI 18 Lem SindNI 1 80011 3 VIV f 000 9 Wl dee UNV 100 99 10 011 031 Dives HOS ole St 1 8 1 75 3492 3dunos 22 70 UU SOTUONMH SAVA 2 01 su31 Sava sava QI TeNINa3L TD Ely Zz 01 8 tly ato g d e D 01 be 5431 06 o 101 23002 5 x SLINA 0 20 0 Do fo 0 zo x ef et 0 UON tO 100 10 SHINN savo 02 001 x QT IUNIMAAL 2 p 3do 324noS ct s 35s sa1uoNrH sava NI 0 390 35un0S 29 475 NOI LINN JA 1087 8 0 VI TUR EEN wi 54 0 e 521000 w o Z MIVYA 010169 03 MAN euo live 2 ut 3408 TTT CI 0 4 f 1 7 2 warding 6 3YN9I Zuyad 2X3 3 A AN A E TEA Zu Rail q INT SIN gt 2 Xom sraqRhaoz nims ZIS ya 12 22 aal At az hz ee 2 gt If ot a 7 0 OHTOL XTP d q sw 08hoz Spa ozele ON SA aang SAIAD ina 3uvail 533528629 AZO 4C PEI qh SW ATA SHY 9604 Y 3 SH
2. 24 25 26 27 5 ASLA ASRL ASLL ADSLA ADSLL ADSRA ADSRL AFSUB AFADD AFMUL AFDIV FSCAL AMOVE ANORM AFN1 AFMTH LCARG LSARG LBARG Arithmetically left shifts RO by amount following call Logically right shifts RO by amount following call Logically left shifts RO by amount following call Arithmetically shifts left the contents of the double precision value as addressed by the next location Logical left shift version Arithmetic right version Logical right shift version Double precision subtract of next address from next plus one 11 overflow return is with carry set Double precision add Single precision multiply with double precision result Address following call is multiplied by address following that DP product is placed in following address A double precision dividend is divided by a single precision divisor resulting in a single precision quotient Divisor follows call then dividend then quotient Quotient l contains remainder Return is with carry set if overflow Arithmetically shifts right the value in RO The result is rounded rather than truncated Accepts positive or negative numbers Moves one or more contiguous words from one location to another FROM address follows call then TO address then N words to move N is octal Normalizes a binary fraction with contiguous exponent Address of fraction exponent follows call Calls MFFT routines Funct
3. FIGURE 4 8 CORRELATOR ORGANIZATION The correlator card is designed straight forward using low cost 7400 series logic It contains 8 exclusive or gate multipliers one 8 bit shift register for lag one 4 bit prescaler per channel and one 16 bit counter per channel for integration Two 8 bit shift registers are used to read out all channels one at a time When the correlator is correlating undelayed data coming from the fringe rotator are applied on B Delayed data are applied at AIN and come out at AOUT from where they go to the input of the next card CS is the shift clock which is continuously clocking the A shift register CS changes frequency proportional to bandwidth and is 4 MHz at BW 2 MHz Multiplier clock CM is a 4 MHz clock which clocks the synchronous prescalers 74161 If a high is on the output of the exclusive or gate bits A and B are the same when CM goes negative the counters are incremented If there is anti correlation the counters are not incremented CM is always a 4 MHz clock independent of bandwidth however CM is being turned off during correlator blanking This can happen several ways The correlator is blanked by the fringe rotator during 1 4 of each fringe cycle It is blanked during frame gap bad frames and bad data as detected by DATAOK and it is blanked under program control during read out The carry outputs are then counted in ripple thru 16 bit counters 74177 normally for a period of 200 ms After ev
4. B54 B67 B69 4040 WW PIN 134A 98A 104 134 135 136A 125 136 VARIAN CD EDGE 1 39 1 39 1 37 1 38 1 36 1 35 2 34 2 35 2 36 2 35 2 37 2 38 2 39 2 38 2 40 2 38 2 42 2 41 2 31 2 29 2 33 2 32 N N N l l oo ooN UO OP NW NE O NN NN N N NN NN N COLOR WH BL OR BL BN WH BK BN GN BN BK BN OR BN WH BN YE BN BL GN YE GN OR 9 8 2 GN GN WH BK WH BK BK OR BK PADDLE BD 4 33 23 24 25 26 27 28 29 30 31 32 33 34 35 36 317 38 39 40 41 NOVA BACKPLANE A86 A85 A88 A87 A89 A90 B6 Bll B13 B15 B19 B23 B25 B27 B31 B34 B36 B38 B40 4040 WW PIN 3 68 69 70A 4A 71 72A 72 76 83 84A 89 93 82 131 132A 132 133 CHAPTER 5 A ADV ADVANCE AICHK ALERT ALERT ENA ALERT OFF ASTRODATA AUD 2 AUDIO B BCCOS B COS BCSIN BI BICHK BLKCOR BOF BOFFLT BSIN BTEN BUFFLT BUFFRAME BW BWSTR CCOS CD CH CHB CHK Mnemonics Index Correlator input data from recorder A Advance flip flop Control pulse from Varian advances recorder 0 25 ys A input of checkboard Control pulse from Varian to ring beeper Control pulse from Varian to enable beeper Control pul
5. re 2 oU In Oly SLINN 4 e fy 0 2 10y SLINN NAd b 0 00 oU N x S431 SunoH SONDA dai SN31 SUNOH MOlishn4 104 15 NOTIN 2 0 LEAL CCS OP AN NOUIS V WAQUISV_NIISH 490 SES iuvd Uu z 01 0 a pez z ol 029 EMT 0 801 vig t T OM 0 t Ol Ota o 2 ot 0 8 01 Z00 2 o 0 CT 0 ji 00 af pol 0 FINI Ely 8 0 Uy 199 TM 011 NITE WIEN 1447 wi ASS IN JA M A LO SLINN SunoH SN31 SILNNIM 0N3931 5031 1 SN31 SunoH SLINN SunoH SN31 SILNNIM SAINN S31nNIM SLINN 04 IDWAL Qiany MAN L 3 91 y daa De Y om D a o aos OO d Ca Vu Vil Sap as o A Wall NM E E Mim Joha Uj freit Mhel el 3002N3 040334 31 1 SN31 SQNO23 SN31 5 SONOIIS SLINN SONOIIS 6S OJ1NNOI 1 65 0 ANNO INA o jo o PO Posto pos APA PIA Aa Fui Pi pa Sz opcre ep ipii 2vuL alany JuuuOd M3N dl a V GO ons 1 Leg 038 JHL NI 18 ASNH SININI 11113 000 99 04 Wa UNY 00 99 10 3 IVE YOS ulu St 1 8 JUV SLMNE e 12511 T 12 GIN ig aungaa y e ww e E Rn 4
6. type signed octal Types out in signed decimal fraction location 20000 Will jump to location 2040 N locations of core may be set to a constant value including zero by assembling the constant into the first location of the array then moving N 1 values from the first location to the second location EX A 1000 Enter constant into location 1000 M 1000 1001 077 Will propagate the constant from 1001 through 1077 All instruction to the EDIT programs are terminated by a carriage return NOVAEDIT restricts mnemonics to three characters Changes from cross assembler follow ORIGINAL NOVAEDIT INTEN INE INTDS IND SKPBN SBN SKPBZ SB2 SKPDN SDN SKPDZ SDZ READS RDS INTA INA MSKO MKO IORST IOR HALT HLT Nova Subroutines l AGET Accepts a character from input device 2 APUT Outputs a character on the output device 3 ATYPE Types the value in RO in 2 s complement octal 4 TNCR Types message in address following call Entry ATNCR No LF CR Entry ATLCR LF CR before typing Entry ATFCR LF CR after typing 5 AWLIM Compares value of RO with limits directly following call Lower limit is first then upper Return is to next location if outside limits and to the next one if within limits 6 ASHFT Logically left shifts RO by amount following call 7 ASRA Arithmetically right shifts RO amount following call Nova Subroutines cont 8 9s 10 11 12 135 14 tox 16 17 18 19 20 21 22 23
7. 10 Buffer fault on recorder C 11 Buffer fault on recorder B 12 Buffer fault on recorder B 30 Program interrupted itself 11 in 3 station 6 and addresses typed after CC are identical probably a parity error occurred on 9 track tape and there was not time to correct it If switch 1 is up certain parameters may be entered from the teletype These are B DELAY DDD CR ACTUAL CHARACTERS DECODED BD C DELAY DDD CR DDD gt DECIMAL DIGITS CD A CLOCK DDD CR CR gt CARRIAGE RETURN AC B CLOCK DDD CR BC C CLOCK DDD CR 00 B LO DDD CR BL C LO DDD CR CL NOTE MESSAGE CR NO EOF CR EO FIRST SCAN CR FI ENABLE CHECKING CR EN DISABLE CHECKING CR DI DATA END CR DA SKIP SCAN CR SK READ PREPTAPE CR RE TYPE SCAN NUMBER CR TY START STOP TYPE CR ST WAKE UP ALERT CR WA 2 10 The current value of setable parameters may be displayed by typing a in place of the or immediately following the The computer s attention must be gotten by typing an X before the commands to accept or display a value For example X WAKE UP CR OR JUST X WA CR CR gt CARRIAGE RETURN X A CLOCK X B LO X AC 1 CR Only the first two non blanks following the X will be decoded Loading the System Both the Nova and Varian object codes reside on the same system tape The system tape is placed on the tape unit and the load button pushed After the tape reaches the load point both the Nova and Varian may be loaded or the Varian only may be loaded I
8. AQ MIAH i YA 22 AQ beten 3 Gel 1 Soe CPU E h n 1 1 A oo 0 n go h hI mms t h Al m n h 6 27 mars zi n e Na UG a 8 Za mais n 3 au O NIH A 401 mas Ql h L MQ S 2dH 0 WISH XO 9 AD 5 I GN 9 S h n 5 T 5 CNIS SY 5 l 8 n S s yi nu H 2 T 7 z CH M355 f S h t T N m Ig mans 4 h Y 24H V 24H WIAH d ga mas lt Awad 2 49 AMWANAINEI NWA 3 10 ANO UMd ida 4 3539 Ja E LWLS AQ ADI auai AITO NOAINGO 1 403 AID Wd 71 6 L 9 3 E 9 LVLs ano 2 1515 13S LVYLS Las Ada 20 AA 0 ADVI 10341402 Inding YA wid L9 32 1117 d 6 8 L 9 e d 3511 Check bits 0 5 are six control lines which set a multiplexer to select the position of the checkboard Their assignments are given below CHB BOARD CHB BOARD 0 00 30 40 1 01 31 41 2 02 32 42 3 03 33 43 4 04 34 44 5 05 35 45 6 06 36 46 7 07 37 47 10 10 40 50 11 11 41 51 12 12 42 52 13 13 43 53 14 20 44 15 21 E No check 16 58 67 Turns on panel indicator 17 23 70 TCA TCB 20 30 71 TCC TCC 2l 3l 72 TCBC TCBS 22 32 73 TCCC TCCS 23 33 74 TCCBC TCCBS 24 34 75 25 35 1 No check e ya 25 Turns on panel indicator 27 37 Figure 3 7 Check Channel Assignments Chapter 4 Circuit Description All N
9. HFCOK HIFR HZ IACK ICRDY IDRDY INTRPT ENABLE INTRPT DISABLE IVC IUAX IUJX IUCX IURX LED LDUP LP End of frame External control control pulse from Varian Undelayed data B Undelayed data C Delayed frame signal Sense line to Varian true when Nova is reset Sense line to Varian true when Nova power is on Frame lenght error turns on dropout light Fringe phase Varian output lines for fringe phase B Varian output lines for fringe phase C Varian output lines for fringe rate Frame signal as decoded off the tape Frame signal delayed by buffer Input to Varian hundred days DC signal to control phase of recorder head drum servo 30 Hz signal from recorder tachometer Input line to Varian helical frame count Input line to Varian true when helical frame count parity is decoded properly Line for fringe rate display true if rate gt 62 Hz Hertz cycles per second Control pulse from Varian to Nova after Varian has accepted data from Nova Varian sense line true when Nova has sent a control word Varian sense line true when Nova has sent a data word Control pulse from Varian to enable interrupt logic Control pulse from Varian to disable interrupt logic International Video Corp Varian I O bus line interrupt acknowledge Varian I O bus line interrupt jump Varian I O bus line interrupt clock Varian I O bus line interrupt request Light emitting diode Load unload pointer Load pointer MCA MCB
10. Then when the address has reached 81 920 memory is looped around and location O is addressed The BOF for the third frame is written at location 49 152 At the beginning of the 6th cycle we start again with writing into location 0 Figure 4 6 shows the memory map and timing Similar to Buffer A we have a load pointer LP and an unload pointer UP but in addition we have a reference unload pointer REFUP REFUP lags behind LP from 512 to 1024 us UP lags REFUP by a delay as given by the Varian computer If that delay is zero then lst DATA LAST DATA FRAME DELCT SE 0 34 UP and REFUP are identical 0 5 65 535 4 1 65 536 0 49 151 3 eee 2 49 152 49 186 32 767 2 3 32 768 2 16 383 1 4 16 384 16 418 81 919 0 1 2 3 4 28 29 30 3p 32 33 34 36 37 38 39 40 2kb 2kb 2kb 2kb _ _ _ L 2kb 2kb 2kb 2kb 2kb 2kb _ _ L 2kb 2kb 22 2kb UPA REFUP LP 512 1024 us EID s 20460 Ua EE Se AAA lt NEXT FRAME w Figure 4 6 Buffer B C Timing and Map UP and REFUP are counters that run normally independent from each other clocked by the same clock Only during delay update UP is set to a new value 5 new value is calculated from the present REFUP and a delay given by the Varian computer Load Control B C The load control board contains all write logic to write into a 10240 word 8 bit word Monostore III memory One 8 bit word is written every 2 ys as addre
11. VINO 41 TVS 30N3AV A3NOD HIHON U 05 06 o MONTT ON ONIAJILN 301 001334 NOI1V2131234S 71v1431VN 001115530 YO 9350 FAR pe proa wm ln e un SN31 Sunou DN lu swan 5 SOJYANNH SAVA 2 0l ttg SN31 SunoH AMT Oly Kat de SLINA Sunon FINT 0 SOJYONNH SAVO 02 Ol io sN31 SONOS 2 01 ats SN31 SAVO g 91 lg SLINn SONOIIS 048 AMyIlIXV ZN Sie 0 tlg SLINA SYNOH 8 NW cly LINT Te SN31 SILNNIM 01 ely CW y SN31 SAV 019 SLINA 5080335 HM Oly SLINA SAV E0 65 0 1Nn02 3 1 gU ge Oq SN31 S3LONIW dw 20y LINT 0 SLINN SILNNIH ON SLINA SAVO 000 Sinani AY N 99 SN31 SunoH E Ely sa3uQNmH sava io SN31 SunoH SLINN SIANNIM 65 0 1NNO 3 MOL DM 1388 308818 31137 ont ud UBF QN3931 2 vi TUNDA 0 m 71 I ADYAUL alany J vua03 08 G3 oW dv ue NOI1dIU2S30 ur 27 0 1 1 Z 19796 OM 1N10 723 01 1580 AHONOMISV 0 0 8 01 LUN viva 3003 141 1 01 10 1 1 NL II 7 JINMIAV NOISIAIQ 3 AJNOJ HIVON M NOIIVHOdUOD H 3131 or wouvor anne gien NOILdIM2S3O WO 34n1V19N3 O0N awa gt aan e A o es 91 AMA SOIVONMH 1 SN31 4 LWHY0d MAN UC f 8 Wied ON O 2D QU x SNL 4
12. and checks parity DAT A B or C areshifted into a shift register and when BUFFRAME goes high the frame count is latched into an 8 bit latch Frame count A is directly presented to the CPU thru a multiplexer Frame count B and C may occur either before or after A and therefore must be latched a second time at the beginning of BUFFRAMEA With EXC364 464 or 564 the computer may select HFC A B A C or B C Two slew circuits one for B and one for C are located on this card too During slewing B or C is advanced or retarded by an integer amount of frames under computer control The computer may command slewing from O to 32 or 31 frames by placing an appropriate binary number on SLEW 0 5 Following that with a RUNSTR pulse starts the slewing process The hardware goes busy SLEWBSY till it is done NOTE that slewing may be stopped by the program by setting slew O frames before slewing is completed The first and last frames are slewed slowly 2 sec per frame and if there are more than two frames they are slewed faster 1 sec per frame Thenumber of frames to be slewed is loaded into up down counters 5A 5B Gate 1G3 senses whether there is something to be slewed gate 2E6 and FF7D6 senses whether to slew slow or fast Circuits 3C6 2G5 2G9 3A 3B and 2F1 4 create either a count up pulse or a count down pulse every time one frame has been slewed This process continues until a count of O has been slewed The slewing is accomplished by changing
13. increments DELCT This prepares DELCT to detect the next EOF Every 2 ys a read cycle is executed to read one 8 bit word from the Monostore memory 11 is initialized by SRDREQ if there is no DELCYC If there is a true FRM and no RDFAIL then 6A is set which in turn sets RDREQ flip flop if no read is pending 6A is now cleared If there is no WRREQ then read flip flop 4E 5A is set which inhibits any new write requests VALMA becomes true and UP 3 16 is placed on the memory address bus for 150 ns A 150 ns memory read command MRC is issued After a read cycle is completed the memory returns with MCC which resets RDREQ It should be noted that at the end of a write cycle MCC also gets true but then 6B latches the RDREQ flip flop so that it does not get reset Now after RDREQ gets cleared by MCC the new data is on MDO and gets latched into 7B 7C 1100 changes value as soon as the next write cycle is started When the next SDREQ is issued data is strobed into shift register 1D and one bit later the first data bit appears on DATB C At UP 35 BUFFRAMES becomes true which is one bit before FO appears on DATB C At UP 43 BUFFRAME and DATOK becomes true and the correlator is unblanked The first data bit Dl is now on DATB C BUFFRAME goes false at UP 65536 and blanks the correlator The sync memory is a 40 bit static write read memory at 9E 9D 9C Normally it is in a read mode with WSAD low and UP ll 16 provides SYNCAD The current data is continuou
14. particular correlator channel or in the check channel Note that this works independently of correlator mode and it works while real data is correlated Six control bits CHKBO 5 set the multiplexer Octal 00 to 43 select board 00 to 53 as shown in Table 3 7 One additional multiplexer 8A is used so that the check card can also duplicate all total counts This happens for check bits 70 to 74 A low level is applied at AICHK by gates 8F and 2G and at BICHK by multiplexer 3F and all check channels count clock pulses All check channels should have the same count and be equal to the total count TC Counter This board contains nine 20 bit counters which count the total number of bits correlated for all modes 3 autocorrelations and 3 complex cross correlations The 16 most significant bits are available to the computer in similar fashion as for the correlator This board also contains the circuitry for correlator clear and recovery which was described earlier Fringe Rotators There are three three level fringe rotators of the same type as described in Report 118 Each has one data input from the deskewing buffer and two data outputs in quadrature phase These outputs go to the undelayed data inputs B of the correlator Two additional MC outputs are multiplier enable lines for the cosine and sine correlators Fringe rotator B and C is driven by independent fringe rate synthesizers which are under program control Fringe rotator B C simply takes t
15. sL zac s e8c H ZEN II ze NS 3 AZ x fj i40 5 LOW JYO 3A1123 443 a aA NL 934015 7 999 i av9 3 303447 Mai 2664 86 S C8 ET dos Viva eum m HRH 70359 23119 o 312 D whee Aa Wee ARA SA h8g v0 E sw SSI SE em Po kapa SAGGLEQL SWZ Ek Specification of Correlator A block diagram of the correlator is shown in Figure 1 10 There is one cable to the buffer and a description of the signals is given above There are four cables interfacing to the computers thru four general purpose interfaces Their description is given in Chapter 3 One additional cable connects to the computer I O bus to handle the 60 Hz interrupt The correlator has a total of 576 channels which are arranged in one of 8 modes as shown in Figure 1 11 In addition to those channels there are 9 total count channels plus 16 channels which may be placed in parallel with any of the others under program control MODE CORRELATOR 96 CH AUTO A 96 CH AUTO B 192 CH CROSS A B 288 CH AUTO A 288 CH AUTO B 576 CH AUTO A 192 CH AUTO A 192 CH AUTO B 192 CH AUTO C 288 CH CROSS A B 128 CH AUTO A 128 CH AUTO B 128 CH CROSS A B 96 CH CROSS A B 96 CH CROSS A C 96 CH CROSS B C 64 CH AUTO A 64 CH AUTO B 64 CH AUTO C 64 CH CROSS A B 64 CH CROSS A C
16. signal is the master 60 Hz It also provides a 60 Hz squarewave with circuit 2E etc reference which controls the entire system including channels B and C and the Since there are 66 666 2 3 bits per 60 Hz cycle there are Divide by Varian interrupt two long frames of 66 667 bits per 1 short frame of 66 666 bits three counter 2E keeps track of long and short frames and is initialized by detected 0 frame At UP count 66 665 or 66 666 SETUP becomes true and UP is set to zero at the next clock At UP 43 BUFFRAMEA becomes true when BOF is detected VFME is true At UP 65 536 BUFFRAMEA becomes false BUFFRAME is the signal that blanks the correlator during head gap Bit 24 33 34 35 36 DAT A il ol ol Fo F1 r2 3 sai sel P p p p p UP 41 42 43 44 45 BUFFRAMEA FCT Figure 4 4 BUFFRAMEA Timing Another signal DATOKA can also blank the correlator Every 512 us flag 1G is read and clocked into FF1B Since there is a time delay of gt 512 ys between LP and UP we can now read the flag at the beginning of each 512 ys and therefore know whether the following 2048 bits are good or not If the flag shows that there is an error the correlator is blanked during an entire 512 us period by DATOK FLERR A is similar to DATOK and is used by the correlator to set indicator DROPOUT For MK 11 C timing of the LP is not changed however 60 Hz and BUFFRAME is different The negative transition of 60 Hz REFA is delayed and occur
17. upset by the 2 66 MHz BOF Data is decoded by a fast sampler decoder whose phase is given by the phase of the PLL and propagation thru several gates Adjusting capacitor 8811 effects the phase of the sampler and should be adjusted for best decoding with the front panel trimpot on half scale This 2004 front panel trimpot is a fine adjustment for the PLL The operator should use it to compensate for variations in tapes and recorder performance Detection of BOF is done with a separate circuit At every transition of HEADSW a 45 us 1 shot is fired This is needed to let the video signal settle from the head switch signal After 45 us gate 6C6 is enabled by BOFWDW and at the beginning of the 2 3 clock 6C6 is made and counter 6D 6E is started 24 clock pulses later GATE becomes true thru 5C5 When a 100 pattern is detected in 10D8 BOF becomes true for 100 ns BOF resets counter 6D 6E and closes GATE TOP VIEW I D SISSWHD UNO 2 gt 03 Hi Taw AHI HITE d E Sh S8 77 g ZC AS HITE g AY 219 98 49 201 35 8 EI TO NDI 2 A Y 045 7 134 Aa Y AV ATI WALSH 2 9 1034 3745 205 1 3 32 16 Y WL IwoWh 2 mom 9 ALI 7 4300320 312 2040732 1232 343040742 a 21121 5 3 MULI l YUI 37 e 460 9 dant 13007301 5 LAYOUT CHASSIS FIGURE t l If no 100 i
18. word on BI Gets reset by IACK NOVA IORST NOVA CLEAR SEN 3 STAT3 Spare status bit Gets reset by CLRSTAT NOVA IORST NOVA CLEAR Gets set by NOVA IOPULSE SEN 6 FFTRESET Set during Nova power turn on and during NOVA IDRST instruction and during Nova console reset Cleared by CLRSTAT SEN 7 FFTPWRON Set when power is applied to Nova SYRT Sets VARSYRT status flip flop when Varian console master reset is depressed VARSYRT is cleared by DATINC NOVA IORST NOVA CLEAR Description of Nova Interface Device Address 04 Device Code 04 Interrupt Mask Bit 4 Output data and output command use the same output lines and therefore only one may occur at a time DOA sets status flip flop IDRDY for transfer of data DOB sets status flip flop ICRDY for transfer of command Register C is not implemented IDRDY and ICRDY are reset by Varian IACK IORST CLEAR Status 3 not assigned yet is set by the pulse output P 11 bit 8 9 of control function F Status 3 is reset by IORST or clear command code C in F Status bit FFTWRON is set whenever power is applied to the Nova Status bit FFTRESET is set by NOva IORST and is cleared by Varian CLRSTAT Input data and input command use the same input lines and therefore only one may occur at a time DIA read a data word in and resets IDRDY status flip flop DIB reads a command word in and resets ICRDY status flip flop DIC reads a 5 bit status word in status word format BIT
19. 081 dv9 ALIAWA N3A3 x SLIQ Hz Lang 3 Mai afta a s a 0 o _ 2 9472 WON Ee SE AS t ez ME amp Z 12 92 S NL RO HLIS 4 052 T132103 SIOHh 4 ZHN Q LHYyh E c 3007 MAYH ASKHA IQ manaa a Lao 031 OI H 5 35 SLISI ROLE t979 dv9 SLA 08 Va3liValS3L 29929 59929 SU ghoz 2 4 541 EN ASOH SIOZ VA Ar 900 0 dot i h wiwa 001 e 79 Alla Vd N34 3 SLIT h 1na 0 4 1014 sa 4 542 1 0 0 8 l i 0 01 ite ajali 3i AEE CZ L GE ot Be e q2 Ad Et Cz Qt H E L1 Mon ed la d L9 S gt gt 2 lt HELIS SUOST 7321198 5 8W4 ALVA 6 ZHUT d ZHU 300 AAW 35vdd Id 0 oval olang aio 19 t 743 o y s t AP God NS CIA To 40V i1 NO 1VJI atv lo ww So oneness hag NO USN ASS sd y UR MA TE LEON WAONddY NDIS T SINIT A ON AQ ON 1N30 3009 WAOUddY 41 dJuuuN1 UYOI JA Ob budhi Gl vel af M ol Cl AMOLVAu3SgO AHONOWUISV 010 8 0 9190 3007 iWli 1 031 33 1 1 43003N3 040334 31 1NANI cds V SI ax 17 ve 1 02H JHL NI 39 Lem 5104 9 1 8031 3 Tv E 000 99 YOJ 404 UNV 00 99 JO H1U9NJ1 3HVHJ 803 ata SI 119 a VIVO JYV SINANI llv
20. 64 CH CROSS B C Figure 1 11 Correlator Modes There are three 3 level fringe rotators similar to the one described in EDIR 118 Fringe rotator A B and A C are independently controlled by the program whereas fringe rotator B C takes the phase difference of A C minus A B Sample rates are controlled by the program and correspond to the bandwidths 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62 5 kHz 31 25 kHz and 15 625 kHz O dd y m 7d 3 2 2 Hoa 313 Y ony 1029 0 Basins HONE 2 2 wld 7 45 Aad 3 Jard MAA A 3 30 AANA 5 23 45 1 juifs didus Jany H033 8 dd 343 9 14 3 HA 010 D 0 30 9103 Y 4 IINA 39 FS AE 239 0 7 i 1029 3 13537 1029 01 1 2 H I og D a M Janaus je A Mugs fe TE aaa CITI LE 0 5 94 Wd NS AOA 1 7 9 SIH m 4 Su Voy X CHEN 209 XINGALNAL SE 1 i 2 gebr 9 0 50 0 ag Du jo NM WM ia i 18 1 1 oat 2340011 eta zadany 211111111112222 AD WW Y S2 2 09 1Nno 313 NYH ANISO ol elQiyi32302 13NNvY42 RAIZ 2 2Hhoz 432012 SS 921544 Mg Hoat lo29 HOA JVINAVH MIS nods Specification of FFT Processor The FFT consists of a Nov
21. 7 b 3 L 9 5 h 19 350295181 NYAYA 3 7 Kee Q HL iG S TIS d n hi d TUL 0 DEIS a IH n Zi 5 N gun 1 222 25 IV Hun i pl L n TWN n 6 AZIS T Iun it 3 195 n 81 il L 205 u RSL 0 9 1195 h CSL T 5 1 195 1 T h EMIS n 55 T 3 26 0 HSN 1 X IANS u 25 T 90895 TAIL ISN IL E E ES ZAN9IA Sud lt 3513 ma MA 4 gt Aya gt 07 9 dauviay J ANCA vu dai i35 LS XW3102 ALS MI hg 482 MHD 3 H2 38 MHD DIA 207413 9 42 CC Ad 3 4 AT ua bl ua 02 31 ue XW 402 Li yal AMI Kwao ai Zo 32V3341L NL NV S 74 451 DA 31 5 4 0 D 83 Q dsd ASUS OWAN 59 1 OHAW 4 t4 la DA NOV hee 39914 H19NA7 25754 ANY 9 230VAuALNIT 133533 6 TONIH lonau nta IN OWA v10 ONAN elis COHAN ALS OMA Lona JOWAN XOWAN SB aqmthorB NmMsthvor X OWA LO 6 amp L 9 5 4 2 E 2 379 S S JlAn9la 319 Mina L MIX UN S17 89 1 157 2 yai 135 St v Adans 5 29g DAH NAS Smg 911 230 Y h Y DAH NAS 91 g 112408 gvo2du13 991 20 2 5 ASI MAIS GF 2106 dols g 315 NNA DES swz lt 451d 2210 ix ida
22. A OLYA gt AA AAA aa AAA 2 135 e rm 4 29 OUT PUT PATA BI 67 gl EE la PS la Msp ODATA DATA INPUT gt Qo ki 0 8 61 FIGURE 4 12 BI 9 Ret BI 10 BI 11 Ret BI 12 Ret VARIAN CD 1 1 1 2 1 10 1 11 1 10 1 12 1 10 1213 1 14 1 15 1 14 1 16 1 17 1 18 1 17 1 9 1 20 1 21 1 20 1 22 1 23 1 24 1 23 1 25 1 26 i27 1 26 1 8 1 9 1 30 1 29 1 31 1 32 EDGE COLOR BK GY OR GY BN GY YE GY GN GY BL BY PU GY WH GY BK PU RD GY YE PU OR PU BL PU BN PU WH PU RD PU GN PU PU WH BK YE WH BK OR WH BK YE WH BK PADDLE BD 4 31 VARIAN NOVA INTERFACE CABLE 2 10 11 12 13 14 15 16 17 18 19 20 21 22 NOVA BACKPLANE A92 A91 A78 A77 A76 A75 A73 A71 A69 A67 A65 A63 A61 A59 A57 A47 A49 A79 A81 A84 A83 4040 WW PIN 5 70 49A 49 48 6A 41 29 34A 8A 10 57 67 2A 68A 2 13 2 14 2 Lo 2 14 2 16 2 17 2 18 2 17 2 19 2 20 2 27 2 26 2225 2 26 2 24 223 VARIAN NOVA INTERFACE CABLE VARIAN CD EDGE COLOR WH BK YE BK BL BK BL GN 87 WH BK 68 68 6 PADDLE BD 42 43 44 45 46 47 48 49 NOVA BACKPLANE B48 B49 B51 B52 B53
23. BAM cos and sin of total counts are divided by PI normalized and the reciprocal taken The data to be transformed are checked to determine the largest absolute value All data are shifted left by the amount needed to normalize this value This insures maximum precision All odd numbered values cosines are multiplied by the reciprocal of the cosine of total counts and all even numbered values sines are multiplied by the reciprocal of the sine of total counts Exact count is kept of all scaling The sign on the transform is determined by which sideband is called for As a note the Nova s inverse FFT corresponds to the subroutine Fourg s forward FFT The call to the Nova s FFT is straight forward Some addresses must be inititalized the number of points must be set then a standard subroutine jump is used The transform is done in place that is the spectrum occupies the area where the correlation function once resided A check is now made on whether to do the FBS correction If it is to be done much use is made of the Elystec s array arithmetic capability This uses a greater amount of core but is much faster In fact without using arrays the FBS takes too long and the task cannot be completed within the allotted time Cos and sin of delta are calculated then a table of cos P Sin P is generated The product arrays cos P RE sin P RE cos P IM and sin P RE are computed 128 at a time Then the real and imaginary parts are updated in
24. ELTA DELTA 45 FBS TRUNC DELAY TRUE DELAY BAND WIDTH 2000 N N SAMPLING INTERVAL 0 25 micro seconds Only the first 128 complex points of the spectrum are kept The remainder are set to zero The actual beginning of the program is at entry DWAIT The first thing there is to disable the interrupts DLOOP busy switch is setnot busy the interrupts are enabled and the computer stays in a jump to itself instruction When an interrupt occurs DSERV routine is reached Here all registers and the status of the carry bit are saved If the Varian interrupted with code 0 DINIT routine is called If this entry is the first since the program was loaded a cosine table for the FFT is calculated Several counters are zeroed and a table of cosines is calculated for possible Hanning weighting The program then returns to DWAIT If the Varian interrupts with code 2 DSEND routine is called This is the routine which sends the computed spectrum to the Varian The spectrum has been placed in a buffer array and is safe from other routines The data are sent one word at a time to the Varian The Nova sends a word then repeatedly asks if the Varian has received it 11 more than a predetermined number of ASKS occurs the Nova gives up and goes back to DWAIT This probably means the Varian got into trouble and interrupted itself and had to resync If the Nova successfully sends the complete spectrum to the Varian it calls DOVE
25. H later than A 96 CH CROSS A B 96 CH CROSS A C 96 CH CROSS B C B BCCOS A BSIN BL 04 48CHI BL 10 MCCBC MCBS 64 CH AUTO A 64 CH AUTO B 64 CH AUTO C 64 CH CROSS A B 64 CH CROSS A C 64 CH CROSS B C Mode 7 A BCOS 64 CH 32CH BL 00 pn 8B MCBC CCOS 64 CH BL Ol 02 8B MCCC MCA B 32 CH later than A C 64 CH later than A BCOS A BSIN 64 CH 32CH BL 10 8B MCCBC MCBS MCB MCC 3 5 CSIN MCCS MCCBS CSIN B BCSIN 64 CH 64 CH BL 11 BL 13 12 8B 8B MCCS MCCBS DOLAR DANS ri deg ao 50 0 141 1 2 17 604 2 46 9 Y Lnodoud Xi Lhnoa0 al is h 21 EI zi d el H l pl A ql E o d d 4 i 9 A G 3 h S gt 0 c n o i D LNOAO Ta x pe 2 797 Kee 3 729510 LdelL r 319 13 1 NI MJ YAL LYA Adu 0 alaa 13530 Gum LX Yoo A 3 7 2 sw I 09 2ADVAAALNT A Via NA X S gon mm H AMF AGE S Fangs laaa VN3 1 430 LIA 233133 wa las Y Q24113S g 921435 225 330 194274 Hi 9047 3574 ANY SOL Ld AQL 9d TAL Sd las hd d han td Tan id an Dd esos 8HL cS 2S HHI IS 25 ZHL OS 35 Hi HIS CHh THIS un HIS oh2S TUL Hn 11
26. LK REFUP RESET ERROR RETARD RDFAIL RDREQ RTD RUN RUNSTR SC SELHFC SELTCD SEN SETFP SETFR SETSTAT1 2 SETWRREQ SETXFER SHCLK SHCLKQT SHF SKPFRM SLEW SLEWBSY SRDREQ SREFUPST SRINPUT SROUTPUT STAT3 STOP SW SYNCADD Diagnostic program 4 MHz reference clock to buffer Reference unload pointer Control pulse from Varian resets dropout Control pulse from Varian retards recorder by 250 nsec Read fail line set when a hardware read error is detected Read request line Retard flip flop Varian output line turns on recorder Control pulse from Varian strobes RUN into hardware Shift clcok see page 4 20 Control pulse from Varian sets HFC multiplexer Control pulse from Varian sets TCD multiplexer Varian sense lines Control pulse from Varian strobes FP into hardware Control pulse from Varian strobes FR into hardware Control pulse from Varian sets status flip flop in Nova Set write request line Control pulse from Varian sets correlator into transfer mode 4 MHz shift clock for readout of correlator l MHz clock for TC counter board Short frame signal Skip frame Varian output lines to slew recorders Varian sense line true when recorders are slewing Set read request Set reference unload pointer in start mode Shift input of correlator to read out correlator Shift output of correlator to read out correlator Varian sense line senses Nova status 3 flip flop Varian sense line for stop button
27. MCBC MCBS MCC MCCBC MCCBS MCCC MCCS MCLK MDO ME MOBSY MEMOCLR MEMOSTR MEMOX Y MKIIC MODE 2 MRC MSB MWC NEGFR NOOP NEXTWRD OACK OCRDY ODRDY OVFLO OTB 7 PLL Monostore address lines Multiplier clock for autocorrelator A Multiplier clock for autocorrelator B Multiplier clock for A B cosine baseline Multiplier clock for A B sine baseline Multiplier clock for autocorrelator C Multiplier clock for C B cosine baseline Multiplier clock for C B sine baseline Multiplier clock for A C cosine baseline Multiplier clock for A C sine baseline Master clock Monostore data out Sense line to Varian true when Memoscope is busy Control pulse from Varian erases screen of Memoscope Control pulse from Varian turns on Memoscope beam to plot a point Varian output lines to set Memoscope beam Input line to Varian set when IVC tapes are played Correlator mode 2 line Monostore read command Most significant bit Monostore write command Varian output line for negative fringe rate No operation Control pulse from Varian places the next word from correlator on COROUT lines Sense line to Varian set after Nova has accepted a word from Varian Control pulse from Varian tells Nova that Varian has sent a control word Control pulse from Varian tells Nova that Varian has sent a data word Overflow flip flop of adder Varian output bit Most significant bit of fringe phase Phase lock loop READOUT REF C
28. NA FRACTIONAL FRACTION TYPE OUT I TSD INTEGER DECIMAL TYPE OUT O TSO INTEGER OCTAL TYPE OUT T TUO TYPE OUT 2 S COMPLEMENT OCTAL NA TUD TYPE OUT UNSIGNED DECIMAL 16 BITS JMP JUMP TO BEGIN EXECUTING M MOV MOVE CONTENTS OF SELECTED LOCATIONS 7 ZBR ZAP BREAK POINT CBP NO ADDRESS RESTORATION The assembler mimics the cross assemblers but does not permit the use of The instructions A 1000 1020 T 12345 or TUO 12345 I 15 20 or TSD 15 20 F 17000 M 100 200 20 or MOV 100 200 20 B 1025 or SBP 1025 C 1025 or CBP 1025 Z 1025 or ZBP 1025 O 1777 2001 or TSO 1777 2001 D 20000 J 2040 or JMP 2040 and in the All addresses must be relative to the P register or must be absolute to the EDIT programs are in the form of function Address 1l case of MOVE N Some examples follow Assemble from locations 1000 through 1020 Types out in 2 s complement octal location 12345 Type unsigned octal Types out in integer decimal locations 15 through 20 Type signed decimal Accepts fractional decimal in the form or DDDDD where DDDDD refers to decimal digits Will move locations 100 through 117 to locations 200 through 217 Will set a break point at location 1025 Location 1026 will be used also Will restore locations 1025 and 1026 to original values Will clear the break point switch without restoring locations 1025 and 1026 Types out in signed octal locations 1777 through 2001
29. NATIONAL RADIO ASTRONOMY OBSERVATORY CHARLOTTESVILLE VIRGINIA ELECTRONICS DIVISION INTERNAL REPORT No 7 THE NRAO VLBI MARK II PROCESSOR B MEREDITH AND B RAYHRER JUNE 1978 NUMBER or Copies 150 CHAPTER 1 CHAPTER 2 CHAPTER 3 CHAPTER 4 CHAPTER 5 Introduction Software System Interconnection and Computer I O s Photograph of the Processor Block Diagram of Control CPU and FFT Processor INDEX Specification of Buffer Specification of Correlator Specitication of FFT ici Circuit Description ee e e 99 e e e e ee e e e e G e e ee e Decoder e w e e e e oe e e e P ller A asa Buffer B C Load Control B C Unload Control B C Recorder Control 1 Recorder Control 2 Correlator and Correlator Card TC Counters Fringe Rotators Buffer Interface e e e e e e e e e e e e e e e e e Delay of Fringe Rate Display TCD Display Memoscope Alert Masterclock Diagnostics and Failures FFT Interface Mnemonics Index PAGE i 3 1 4 1 13 125 THE NRAO VLBI MARK 11 PROCESSOR CHAPTER 1 Introduction This report describes the hardware developments of the Mark 11 VLBI processor during the past four years The reader is referred to NRAO Electronics Division Internal Rep
30. R routine Here the registers and carry bit are restored to values they contained before interruption then return is back to location where the interrupt occurred Code 1 interrupt is where the real work is done This is when the Varian wants to send a correlation function to be transformed The Nova reads each word tells the Varian it has read the word then waits for the next word The Nova s interrupts are disabled during this time but each word is checked for a command word so if the varian has gotten itself lost and has to restart the Nova will be prepared for it Following successful data transfer the Nova re enables its interrupts then enters DLOOP routine A busy switch is checked to see if the Nova had been interrupted out of this routine This is a catastropic Situation if it happens so the Nova just stops Operator intervention is necessary to restart the system Normally DLOOP will not be busy and processing will continue The first 53 words are moved from the input array to the working array for safekeeping These are not the correlation function but are parameters necessary to the Nova and the post processing programs The busy switch is set busy The correlation function is moved to the working array divided in half and the middle zeroed or portions ignored depending on mode Several switches are set or reset depending on sideband Hanning weighting and FBS correction Delta is computed in binary angle measurement
31. RAO designed circuits are built on NRAO digital circuit boards and mounted in NRAO digital chassis Figure 4 1 shows chassis layouts All circuits are built on wire wrap cards with the exception of the correlator cards which have a two sided printed circuit card The following sections describe function and timing of the circuits whereby the reader is referred to NRAO drawings D2 519 Decoder All three decoders are identical and interchangeable They contain decoding circuits and BOF detector for video data and decoding circuits for audio data Video data are first amplified and phase compensated in the recorder preamplifier and then clipped within the video recorder This clipped video data the Astrodata is the input to the decoder Astrodata is first edge detected by a double edge detector which results in 20 ns wide pulses at 8 MHz or 4 MHz depending whether a 1 or a 0 has been recorded A phase locked loop running at 8 MHz with a time constant of 15 ys locks to these pulses 8 MHz is necessary because of an unfortunate choice for the video code During the head gap a 4 MHz signal is recorded without polarity information A 4 MHz PLL would lock with an ambiguity of 1 2 cycle At the first 0 in the data stream this ambiguity is resolved however the PLL cannot respond fast enough and BOF would not be decoded properly Another unfortunate choice is the 2 66 MHz for BOF and EOF The PLL has a narrow capture range of 10 so that it is not
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33. Switch Address lines for dropout sync SYRT S1 8 TAPE TC TCAUTO TCCROSS TCD TCD BLK TCD CLK TCD DAT TD TH TM TOTEMPOLE TPIX TPOX TS TTY UCLK UD UH UM UP US UT VALMA VALFR VALSYNC VR Wu L WRFAIL WRREQ WSAD system reset 8 states during which new delay is strobed into hardware Diagnostic program Total count Total count of autocorrelator Total count of cross correlator Time coded decimal Time code blank to blank display Time code clock Time code data Input to Varian ten day Input to Varian ten hour Input to Varian ten minutes Push pull output stage Varian I O bus line trap input Varian I O bus line trap output Input to Varian ten second Teletype Unload clock Input to Varian unit day Input to Varian unit hour Input to Varian unit minutes Input to Varian unit total power Input to Varian unit seconds Input to Varian unit terminal I D Valid monostore memory address Valid frame Valid dropout sync Video recorder Data to be written into sync memory Write fail line set when a hardware write error is detected Write request Write sync at this address X Analog signal to Memoscope for x deflection XFER Sense line to Varian transfer Y Analog signal to Memoscope for Y deflection ZMEM Signal to Memoscope to turn on beam lMHZ l MHz squareware for delay display 60 HZ REFERENCE Reference signal to video recorders 60 HZ REF Internal 60 Hz signal 60 HZ Intern
34. VAR SYRT IDRDY ICRDY SPAREl or 2 VAR SYRT IDRDY ICRDY SPAREl SPARE2 11 12 13 14 15 Is set when Varian console master reset is depressed and is reset by DIC instruction Is set by Varian ODRDY POT67 1 and reset by DIA or Varian CLRSTAT POT67 5 or Nova CLR instruction or Nova IORST Is set by Varian OCRDY POT67 2 and reset by DIB or Varian CLRSTAT POT67 5 or Nova CLR instruction or Nova IORST Is set by Varian SPAREl or 2 POT67 3 or 4 and is reset by CLRSTAT POT67 5 or Nova CLR instruction or Nova IORST 6 4 Aana vs wei Uv MN m m x 3 lt K i Sch J I f o 8 ii Em L 3 o E n a E e 9 a al 38 N sn 7 OORL 001 1 0A4L CN CNS Am 7 S a Ra 3 S d gt A m A0ALNO ANdANGQ ON OH 4 27 On RLY L5 el z a q Ton dua S 75 lon aS 4 19 Lod 013 24 z 3 oe a 3 od gt p T UJ LA 0 31 Kad e v e o 1 x an E an E OLA 4 m SH Ti 3 di 5 han CAL h Son hone dz SP l 4S PA A02 2T un m red Ag N L anan YNI Laag san hohl K KS S Ob 011 E AVAIL Za A AO lich Sandie YW Lo z z om Gu U J 1 I El ka i A E 2 g ot lt 4 Aum D lan Y ZOhL N WA LSnL a du SL EI MCL EJ 5 El
35. a 820 CPU an Elsytec 306 MFFT plug in array processor and a program library supplied by Elsytec It is a medium speed FFT processor with the following basic specification 32 64 128 256 512 1024 2048 4098 8192 4 8 8 14 5 23 39 75 139 280 600 1300 58 114 226 450 898 1794 3586 7170 14338 28674 These times are without I O transfers and without set up by a master program No Real Points Time ms No Core Locations Used by NRAO NRAO has added fractional bit shift corrections to the master program For further details see Chapter 2 1 15 CHAPTER 2 Software Introduction The present configuration for VLBI processing consists of a Varian 620 I minicomputer and a Data General Nova 820 minicomputer The Nova contains an Elsytec array processor hardware board which permits it to fast Fourier transform the cross correlation function sent by the Varian and to return the resultant spectrum back to the Varian where it is written on 9 track magnetic tape The Varian is in general the same software which has been around since the processor has been in operation There have been extensive modifications however These modifications add to rather than alter the original philosophy The first task for the Varian program is to read into memory the PREPTAPE information This consists of up to 20 scans The video tapes should be positioned to within one second of time relative to each other Whe
36. al 60 Hz signal LFL T Adder fault set when hardware does not work properly during DELCYC
37. ame frame Get no carry if result 1 means skip to next previous frame Next CLK1 Clock UP if SKPFRM1 load result into UP Set SKPFRM2 if no carry Set 83 Comment UP 4 66666 is calculated to make O UP 66666 for long frames For short frames one has to calculate UP 66667 NOOP if no SKPFRM2 If SKPFRM2 Decrement DELCT with CD Set multiplexers to do UP 66666 1 for SHF2 Get carry if result lt 1 means same frame Get no carry if result 1 skip another frame Next CLK1 Clock UP if SKPFRM2 load result into UP Set FLT if no carry Set S4 Comment 3 is very similar to S2 Since DEL cannot be larger than 19965 75 us we can never skip more than two frames Therefore if we don t get a carry now the hardware has not worked properly and fault flip flop is set This is a fatal error and processing should be stopped 4 9 dati MAWA AL AUN REI Ha Qai 22130 229 17 04 916017 37 7 040 SHIN ZEIEN 999 99 Longo Ch 0 4491 Z401 4 taal Ixnu SHI 247 JG Ad MOOV 3413 91 Amor 3 4 Ca 555200 dn woud 114 Zi di14MS 3 S4 Set multiplexers to do UP DELCT Get carry if result gt 81920 Next CLK1 Clock UP load result into UP Set OVFLO if carry Set 5 Comment During S1 S3 we have updated DELCT as we skipped frames Now we add DELCT to UP to place UP the read address at right location wi
38. and 1 Control pulse from Varian to turn off Computer off light Sense line to Varian goes true after CORCLR and CORRECOVERY command Control pulse from Varian to clear correlator Control lines from Varian to set correlator mode Control pulse from Varian which strobes correlator mode on CORMX lines into hardware 16 parallel output lines from correlator to Varian Control pulse from Varian to recover correlator for next correlation after all channels are read Diagnostic correlator test program Central Processor Unit Cathode ray tube Shift clock Shift clock to chassis H or 1 Correlator input data for A C sine baseline Counter clear input of correlator card Count up 16 bit correlator output data Correlator input flag true when data has no errors Varian output lines to set Monostore delay Control pulse from Varian to clear Computer off light Hardware counter to keep track of frame cycle 0 1 2 3 4 0 Hardware delay cycle flip flop is set during time when new delay is set Control pulse from Varian to strobe a new DEL into the hardware Signal to Memoscope to dim the screen Control pulse from Varian to dim Memoscopes Control pulse from Varian to brighten Memoscope Direct memory access Sense line to Varian set when error in data has occurred Input line to Varian panel time constant switch EOF EXC FB PC FCT FFTRESET FFTPWRON FLERR FP FPB FPC FR FRAME FRM HD HEADDRUM HEADSWITCH HFC
39. are 320 ns 20 ns so that 2 cycles can be executed within 1 us Write and read addresses are given by two counters load pointer LP and unload pointer UP They start addressing location O first then step thru all locations to 1023 The next location is location O again 4095 0 MEMORy AYOW AWN 2048 0 1 2 3 4 230 31 32 1 2 ES 2kb 2kb 2kb 2kb 2kb 2kb 2kb m 4 BUFA 4kb EE ki FRAME 16 BUFF CYCLES 32 SYNC CYCLES 1130 1131b not stored Figure 4 3 Buffer A Timing and Map At BOF the LP is preset to 24 as it should be from Figure 4 2 BOF also sets VALFR which enables the write control circuit LP now increments till it reaches 65536 at which time the write circuit is disabled LP keeps counting until the next BOF When a BOF is not detected LP is preset to 24 by BOFWDW however the write circuit stays disabled and no data is written into memory Every 512 us an 8 bit sync pattern is recorded on tape which is decoded in circuit 10B etc The circuit searches for this pattern within a window of 7 bits If no sync is detected a flag is set to indicate that an error has If a sync is detected at the wrong time the flag is set as well and LP 0 10 Occurred it is assumed that a bit slip has occurred within the preceding 512yus is then set to zero for resync 11 a sync is detected at proper time no action is taken The UP provides the read address for the buffer memory This 60 Hz
40. ator FB and FC are data outputs to the fringe rotators and DATA DATB and DATC are outputs to a frame count detection circuit on delay display board This board also contains an unblanking delay circuit As soon as data coming from deskewing buffers is good DATOK becomes true However there still are invalid data bits in the correlator shift registers The correlator has to stay blanked until they are cleared out The time required is a function of the mode Blanking outputs X Y and Z are delayed according to the table on the blueprint Delay and Fringe Rate Display The fringe rate is displayed with a five digit LED panel display When the fringe rate is gt 63 5 Hz then HIFR is high and PH7 is counted which is the MSB of fringe phase over a period of 1 second The display is in Hz If the fringe rate is lt 63 5 Hz then BTEN is counted which is 10 bits less down in the fringe phase register The decimal point is moved three decimals left It should be noted that an approximation is made here 1024 1000 and at very low fringe rates it is possible to rotate the fringe rotator by updating the phase only the fringe rate register may well be 0 The display then may show 0 where in fact the rotator is rotating slowly The delay is measured and displayed as difference of O frame A and O frame Bor C Zero frame pulses are one pps pulses derived from decoded helical frame count O If data are poor O frame may be decoded improperly and the d
41. d of frame to reset VALFR VALFR is set by BOF and therefore stays low when no BOF is detected Another frame signal is created by 10108 which is true even when no BOF is detected This signal inhibits clock carries into 1 during frame gap One other circuit the write logic for a sync memory is located on the load control board Its function is described later with the unload circuit Unload Control B C The unload control circuit is located on two boards Unload Control 1 and Unload Control 2 These boards contain all necessary circuits to read the Monostore III memory Some of the circuits are similar to Buffer A and it is necessary to know how Buffer A works in order to understand unload control B amp C The differences are UP is replaced by two counters REFUP and UP An adder multiplexing circuit is added to strobe a delay into UP under program control The 4 bit parallel data word is replaced by an 8 bit word The 2 bit sync memory is replaced by a 40 bit memory A circuit similar to load control for keeping track of the 5 frame cycle is added Instead of one circuit for long and short frames there are two one for REFUP and one for UP The REFUP is almost identical to UP of Buffer A It lags behind LP by 512 to 1024 us It is not affected by DELAY from the Varian CPU It derives a 60 Hz reference for the video recorder In STOP mode it is initialized by Buffer A thru SREFUPST When the processor is in XFER mode REFUP is c
42. e shifted left until the most significant bit MSB is set since they are all positive Actually they are both shifted the same number of bits the greater 2 5 of them making the decision of how many bits to shift This assures no over flow during the normalization divide step there being no overflow indication on the Nova The data arrangement consists mainly of dividing the input array down the middle moving the firsthalf to the latter half of the array to be trans formed and likewise moving the latter half of the original array to the first half of the array to be transformed In mode zero zeros are inserted into the middle of the new array and in mode four the last 64 points of the original array do not participate in any portion of the task The third task is simply the forward or inverse fast Fourier transform of the data The Elystec FFT subroutine is called and the resulting spectrum occupies the space where the cross correlation function originally was stored The complex spectrum can be written as S K SR K I SI K where SR is the real and SI the imaginary parts The FBS correction transforms S K into S K S K SR K 1I SI K cos P K I sin P K or S K SR K cos P K SI K sin P K 1 SI K cos P K SR K sin P K cos P K and sin P K are generated recursively as cos P 1 1 sin P 1 O cos P K cos P K 1 cos DELTA sin P K 1 sin DELTA sin P K sin P K 1 cos DELTA cos P K 1 sin D
43. e test and transfer mode The Nova 820 may also be operated in the interrupt mode No data channels are provided Data transfer occurs in parallel over two independent 16 bit data lines Transfer may occur simulataneously in both directions Over the same lines 16 bit command words are transmitted Handshaking is done on the ready acknowledge principle Five status bits are used by the Varian to transfer status information to the Nova of which two are not assigned yet Six additional status bits are used by the Nova to indicate status to the Varian of which one is not assigned yet Description of Varian Interface Device Address 67 OTB O to 15 Output of 16 bit parallel data or control data BI O to 15 Input of 16 bit parallel data or control data POT O IACK To be set after either a data or control word has been read by Varian POT 1 ODRDY To be set after output data has been placed on OTB lines POT 2 OCRDY To be set after output command has been placed on OTB lines POT 3 STAT 1 Sets spare status bit POT 4 STAT 2 Sets spare status bit POT 5 CLRSTAT Clears status bit 1 and 2 FFT RESET ODRDY OCRDY does not clear VARSYRT 4 24 SEN O OACK Set after Nova has accepted either a data or control word Gets reset after either ODRDY or OCRDY SEN 1 IDRDY Set after Nova has place a data word on Bl Gets reset by IACK NOVA IORST NOVA CLR SEN 2 ICRDY Set after Nova has placed a command
44. e unload clock MODE 2 correlator mode 2 ALERT OFF Disables audible error buzzer Outputs to correlator control DAT A B C 4 Mb NRZ data FRAME A B C TCD DAT A B C audio NRZ data TCD CLK A B C audio clock FLERR A B C error count DATOK A B C True when data is decoded properly XFER True when processor is ready to correlate Computer I O to 1 general purpose Varian interface as assigned in Chapter 3 Block diagram Figure 1 3 shows the buffer The buffer is designed to decode MK II VR 660 as well as MK II C IVC 825A formats shown in Figures 1 4 1 5 1 6 1 7 and 1 8 Buffer A has a small 4 096 bit memory half of which is used to correct for time displacements jitter of the tape recorders and the other half is used to keep track of bad 512 us sync patterns At the end of every 2 048 bits a 8 bit sync pattern is decoded If this pattern does not appear or if it is decoded at the wrong time an error in the pattern or a bit slip has occurred during the last 512 microseconds When this data is shifted thru the correlator the correlator is blanked by DATOK going false Buffer B and C each have a 81 920 bit memory of which 4 096 bits perform the same function as Buffer A and 77 824 bits are used for delay of 0 to 19 456 us This delay is under program control and may be changed rapidly Timing and address relations for Buffer A B and C are shown in Figure 1 9 l 0 4 OL 71 010 ve s as Does
45. e 15 usec for full scale deflection before Z may be turned on After Z pulse is executed it takes 30 usec for a point to print on the screen During that time X and Y should not be changed and no other EXC 63 should be executed All other outputs are not critical for timing The correlator is read out per block and card in a fixed sequence TC AUTO A TC AUTO B TC AUTO C TC CROSS A B COS TC CROSS A B SIN TC CROSS A C COS TC CROSS A C SIN TC CROSS B C COS TC CROSS B C SIN BLOCK 00 64 CH BLOCK Ol 32 BLOCK 02 32 E BLOCK 03 64 CH BLOCK 04 64 BLOCK 05 32 m BLOCK 10 64 BLOCK 11 32 BLOCK 12 32 BLOCK 13 64 BLOCK 14 64 BLOCK 15 32 CHK 0 8 CH CHK 1 8 CH TERMINATOR CH CH CH CH CH CH Depending upon the mode selected the blocks are arranged in the followings ways Mode 0 96 CH Auto A 96 CH Auto B 192 CH Cross A B A A 56 A 7 FT B 96 CH later than A MCBC MCBS MCA MCB Mode 1 288 CH Auto A 288 CH Auto B MCA MCB Mode 2 576 CH Auto A A ws 576 CH BL 00 10 01 11 02 12 03 13 728 04 14 05 15 MCA Mode 3 192 CH AUTO 192 CH AUTO B 192 CH AUTO C MCA MCB MCC Mode 4 288 CH CROSS A B A BCOS A BSIN B 144 CH later than A MCBC MCBS Mode 5 128 CH AUTO A 128 CH AUTO B 128 CH CROSS A B A BCOS A BSIN B 64 CH later than A MCBC MCBS MCA MCB Mode 6 A BCOS 48CH BL 00 MCBC CCOS MCCC B 48 CH later than A C 96 C
46. en us numerous problems Some of the gaskets of the vacuum system have failed causing the vacuum to be unstable to the extent that tapes could not be loaded We have had a sizable number of failures with the Molex connectors which interconnect all boards According to Molex these connectors are not made for low voltage low current applications as in this tape unit Another failure we have had was in the controller timing circuit which sets record gap length A diagnostic program TAPE checks for proper record gap length as well as proper recording Another diagnostic program MEMO is used to test the performance of both D A converters and to check alignment of the memoscopes MEMO displays three different patterns on the screen A crossed rectangle makes visible any faulty bit of either one of the D A converters A checkerboard pattern checks for geometric distortion The third pattern plots a point everywhere on the screen Distortions in the floodgun become visible as well as burned out spot in the phosphor 4 23 FFT Interface Interface FFT NOVA 820 to Varian 620 Two general purpose controllers are used to interface the Nova 820 to the Varian 6207 computer The Varian uses a buffered I O controller mode DM 373B with device address 67 The Nova uses a general purpose interface mode 4040 and data registers mode 4041 with device address code 04 and interrupt mask bit 4 Each CPU looks to the other as a peripheral Data transfers are in th
47. ery 200 ms the correlator is blanked and is now ready for read out The first channel is immediately available on the parallel output After the computer has read the first channel a 250 ns negative pulse is applied at SRINPUT After the next SHIFTCLOCK this low level is applied to the strobe input of the 16 bit counter of the first channel This causes channel 2 to be loaded into channel 1 and now channel 2 is available on the output lines At every subsequent SHIFTCLOCK this low level propagates thru the two 8 bit shift registers at a rate of 4 Mbits s and shifts each channel up one counter The output SROUTPUT is connected to the next card etc It takes 4 us to propagate thru one card and 300 5 us to propagate thru the entire correlator The program does not have to wait 300 us for reading the second channel the second channel is available in less than a CPU cycle e g there may be several low bits propagating thru the correlator shift registers at one time At the end of the correlator e g the data input of the ast correlator card a terminator is connected which grounds all input lines As the correlator is read out 0 s are therefore shifted gradually into all counters and when all channels have been read the entire correlator is cleared except the first channel One more NXTWRD command has to be executed to clear the first channel too After this there still are several low bits propagating thru the shift registers for 300 us and the co
48. f both computers are to be loaded switch 13 and only switch 13 on the Nova must be in the up position Stop reset and load are pushed in that order The Varian must be in step mode The U register must be clear and the key in loader executed at location 27765 The Nova will be loaded first with an appropriate message typed on the TTY Then the Varian will be loaded with its message If the Varian only is to be loaded the Nova step is skipped A message saying the Nova was not loaded will be output on the TTY then the Varian will load itself CHAPTER 3 System Interconnection and Computer I O s This chapter describes the interface between the correlator and the Varian computer Organization of the correlator is described as seen by the computer The 8 correlator modes are shown including the sequence in which data is presented to the computer All I O control and monitor lines are shown in 3 1 to 3 6 Also all critical timing that has to be considered by the program are detailed All cables that interconnect all chassis computer and tape recorder are listed in detail in the blueprints There are six general purpose I O connections to the computer which have fixed assignments They are shown in Figures 3 1 to 3 6 Timing the decoded audio is important for the program It takes up to 34 msec for new data to be ready after a select command Also timing for memo X Y and 2 needs to be considered by the programmer X and Y need to settl
49. he difference of phase C phase B Fringe rotator B and C are built on two identical boards and rotator B C is located on the master clock board The fringe rate synthesizer is different from the design in report 118 The phase is an eight bit binary number which the program sets on the FP lines Then SETFP is executed and at the next 60 Hz interrupt precisely FP is strobed into phase registers 6F and 4B All less significant bits of phase registers 4C to AF are cleared Fringe rate registers 2C to 2G contain the current fringe rate This fringe rate is added to the current fringe phase by adders 3B to 3F and the resulting new fringe phase is latched into the phase register every usec Every 1 us the fringe phase is incremented by the amount of the fringe rate Fringe rate register is set by 20 FR lines at the time when SETFR is executed FR is the fringe rate in cycles per microseconds a binary number with the binary point four places left Maximum fringe rate is 62 5 kHz minimum fringe rate is O smallest step is 62 mHz Negative fringe rate is implemented by reversing direction of counter 6F 6F counts down instead of up which results in a 180 phase reversal of sine channel phase PHASES and does not effect the cosine phase Buffer Interface This board has most of the receiver driver circuit to and from the buffer Note that CS is the correlator shift clock which changes frequency with bandwidth A B and C are data outputs to the correl
50. ic tape At each 60 Hz interrupt VLOOP runs the assured clock on the frame count This assures the program that the frame count difference between A B and A C will not be affected by bad frame counts that occur only rarely A series of bad frame counts will throw the program back into re sync condition Audio I is read for one recorder at each 60 Hz interrupt Every six 60 Hz interrupts 100 milliseconds delays and rates are computed If the Nova is to be used to transform data at one of these 100 millisecond intervals data are sent to the Nova and at the next interval the previous data are read from the Nova The assured clock is run for complete time rather than frame counts as in the 60 Hz loop If the Varian finds it necessary to re sync it types out a condition code which describes the reason CONDITION CODE REASON 01 A B frame count difference too great 05 A B frame count difference too great 02 A C frame count difference too great 03 A C frame count difference too great 25 Fringe rate too large 13 Correlator stop button pushed 26 End of scan 24 Correlator stop button pushed 50 EOF on 9 track tape 42 Read PREPTAPE 23 Stop during 9 track tape write 40 Restart same scan 44 Skip one scan 46 Restart first scan 52 Position 9 track tape at EOF 54 Backspace one record CONDITION CODE REASON 56 Type current scan number and time 17 Position 9 track tape at end of data 62 Enable channel checking 64 Disable channel checking
51. interrupt from the Varian There are three expected commands from the Varian The first is an initialization command which is generated by the Varian at Varian set up time This occurs when the Varian is syncing the tapes as during scan changes The cosine table for the FFT is computed at this time and some minor initialization is done The other two expected interrupts are when the Varian is ready to send data and receive data When data transfer occurs it is done one word at a time One computer sends a word to the other then waits until the other has received it before another word is sent When the Varian is sending it is in interrupt enable state and will be interrupted out of this SEND mode before all data have been sent This is no problem except the actual time required to send data is somewhat greater than if the Varian could devote its undivided attention to the task As soon as the Nova has received all the data it immediately begins to work on it There are four tasks to be performed l Normalize the data by total counts and scale them 2 Arrange the data in the proper mode including inserting zeros or discarding data as necessary 3 Perform the FFT 4 Perform the fractional bit shift FBS correction The cosine and sine total counts are divided by PI then all cosine values are divided by cosine TC PI and sine values are divided by sine TC PI Prior to this division cos TC PI and sin TC PI are normalized that is they ar
52. ion to do follows call then PSI 1 then PSI 2 then PSI 3 MWDCT page zero must contain the negative number of elements to do Before call RO contains address of operator Rl contains address of operatee R2 contains address of result Calls meet arithmetic routines Following call the address contains the function code next is address of operand 1 next is address of operand 2 then address of result Operand 1 is performed on operand 2 Computes cosine of value in R2 expressed in binary angle measurement BAM Upon return RO contains result Computes sine of value in R2 Computes sine and cosine of value in R2 For more subroutines see the Elystec MFFT User s Guide Nova Program The Nova s sole purpose is to transform the cross correlation functions into complex spectra The Varian reads the correlators every 200 msec and sends the correlation functions to the Nova following each read Modes zero and four are the only modes available to the spectral line user Mode zero has 192 channels of A X B or a total of 384 sines and cosines Mode four has 288 channels of A X B or a total of 576 sines and cosines A 512 real point transform is taken so in Mode 4 64 points are ignored and in Mode O 128 points are cleared to zero before the FFT The Nova is a complete slave to the Varian that is all tasks are initiated by the Varian During idle moments the Nova is in a tight wait loop with its interrupts enabled waiting on an
53. is held low so that request flip flop 3G5 will not be cleared This is necessary because an acknowledge to DMA request appears on IUAX After DMA is serviced a waiting interrupt may then be executed at the next IUCK Interrupts may be enabled and disabled under program control Interrupt enable flip flop is cleared by IUJX after each interrupt so that no interrupt is executed twice The program needs to enable interrupts after each interrupt When the computer is halted interrupt enable flip flop is also cleared by SYRT when system reset is depressed A pulse delay circuit controls delay between tapes A B and B C Every time RTD or ADV is pulsed by the program a clock pulse is deleted or inserted at UCLK The unload counters in the buffers B and C are therefore retarded by 250 ns per pulse with respect to A Since 60 Hz reference is derived from the unload pointer this will actually displace recorder B or C respectively Although the advance and retard pulse are executed instantaneously in the buffer there is a limit how fast the video recorders can be slewed before head drum servo gets out of lock Diagnostic and Typical Failures In our experience during the last two years problems and failures have mostly occurred in the correlator the decoders video tape recorders and computer 9 track tape drive Correlator failures are typically in the counters If a counter counts improperly then there is a difference between that channel and the corres
54. isplay will not be stable It typically jumps around in multiples of 16 6 ms or it may not change at all One should recognize that the display shows the actual delay between the two data streams and not the delay which the computer has calculated and thinks it has put into the hardware TCD Display and Memoscope Alert Decoded audio data are converted into parallel format by a 64 bit shift register At the right time when a sync pattern of 111111110000 is recognized parallel data are latched in a 52 bit latch where they are held for display and for input to the computer Every frame the latch is updated The circuit displays only one audio channel at a time With multiplexer 1F any of three recorders A B or C may be selected either under computer control when in XFER mode or by panel switches when in STOP mode When in XFER mode and the multiplexer is changed from one recorder to another it will take between 16 6 to 33 2 ms for new data to be ready During that time the display is blanked by TCDBIK As data is processed and the computer scans thru the recorders rapidly one cannot read each recorder individually on the display If one depresses one of the three select buttons for example SWA then during B and C the display is blanked and A may be read The display will be dim and will flash because for over 2 3 of the time it is turned off A retriggerable one shot circuit 10B detects if any of the 16 ms sync s are missing and turns on TCD err
55. n the start button is pushed on the correlator chassis the program starts the video tape players either 2 or 3 insists on 30 consecutive good frames then aligns the tapes to the same frame number The delay between station A and 8 is calculated and strobed in If there is a third station the A C delay is calculated and strobed in A built in delay of 5 seconds must elapse before data are recorded on 9 track tape If mode 0 or 4 is in effect the correlator data are sent to the Nova computer to be transformed then sent back to the Varian to be written on tape A CRT display of fringe amplitude for 12 channels of A B data and 12 channels of A C data is created by the Varian In case of two station processing 24 channels of A B data are displayed The source statements for both the Varian and Nova computers contain many comments which make the programs self documenting NOVAEDIT and VAREDIT As an on line aid to debugging simple editing programs have been written for the Varian and Nova computers These are very similar in use They allow a programmer to assemble set and clear break points type out in various formats selected portions of core move selected portions of core and to begin executing a program at a given location The editing instructions are slightly different for the two systems labels Address 2 NOVA VARIAN A A ASSEMBLE B SBP SET BREAK POINT C CBP CLEAR BREAK POINT D NA DECIMAL FRACTION TYPE OUT F
56. nt of the trimpot capacitor for center frequency of the PLL is very critical and the circuit is somewhat temperature dependent A front panel potentiometer is a fine control for the center frequency 4 22 Failures of the video recorders are mostly not clear cut Sometimes tape may work better on one tape recorder than on another The difference may be in the video heads or the mechanical alignment or in the response of the preamplifier These differences between recorders become less obvious when a good quality tape with good recording is played back Head drum servo and capstan servo are not too well designed They are not critically damped Head drum servo has significant temperature drift In general however their performance is good enough for processing tapes properly Since report 118 was written major improvements were made in the stability of the capstan servo and the head drum servo by cleaning up control track amplifier clipper and by closing the head drum servo loop which eliminates problems due to temperature drift and by replacing the 12 internal supply with a well regulated external supply Dramatic failures due to broken video heads faulty components in the servos bad switches or relays are easily spotted and repaired by replacement of a card or component Excessive play in worn bearings etc can be spotted very easily and needs to be attended to by an experienced service technician The nine track 1 2 tape drive has giv
57. or indicator The circuit for ALERT is simple and needs no further explanation On the same board is the circuit to drive the memoscopes Two D A converters drive X and Y respectively of the Tektronix model 603 memoscopes ZMEM1 and ZMEM2 turn on the beam currents to plot a point on the screen Timing is important and needs to be considered for programming It takes 15 us for X and Y to settle for full scale deflection and it takes 30 us for Z to plot a point Erasing a screen takes 250 ms during which time the scope goes busy Another control is DIM which reduces the brightness of the stored image so that it may be viewed up to 1 hour and life of the CRT is extended This function is active only when the brightness control on the front panel is completely counter clockwise Note that the scopes are forced dim when the computer is halted or when it goes into an unusual mode COMPRDY and DLYTRK are both missing then and flip flops 3G 3F are cleared Masterclock This board contains 6 circuits Masterclock correlator bandwidth registers NXTWRD shaper 60 Hz interrupt pulsed delay and fringe rotator B C The masterclock consists of a 20 MHz crystal oscillator a divider multiplexer and driver circuits The outputs are MCLK Masterclock 4 MHz squarewave for control circuits within correlator control chassis SHCLK Shift clock 4 MHz squarewave for correlator read out shift registers of correlator O and 1 respectively SHCLK QT 1 MHz square
58. ort 118 in which the principle of the Mark II system is described The processor control program is described in NRAO User s Manual 26 We will limit this report to the processor and describe in detail all needed features Summary of changed and added hardware features see Figures 1 2 1 3 1 10 The old 190 channel correlator was replaced by a larger 576 channel correlator The new correlator works with eith 1 2 or 3 stations and processes autocorrelation cross correlation or a combination thereof in any one of 8 modes A self checking feature was added to the correlator which insures that the correlator circuitry is working properly Nine extra channels for total counts were added in addition to the correlator channels The fringe rotator was redesigned The two station Leach buffer was replaced by a three station buffer Buffers B and C were enlarged to 81 920 bits One may add a delay from O to 19 456 us under program control for source switching experiments The previously open head drum servo loop was closed The audio decoder was redesigned The video decoder was redesigned and accepts MK II or MK II C format The buffer was designed so that VR 660 or IVC 825 video recorders may be connected on any of the inputs The buffer was designed so that when an error is detected for the 512 us sync word the correlator is blanked during the previous 512 us of data A blanking circuit was added that insures that invalid data is shif
59. ounting independently of Buffer A The unload pointer UP is a 16 bit counter which provides read address to the Monostore III memory It is clocked by the same 4 MHz clock as REFUP but otherwise is independent except when a new delay cycle is executed Then starting with the current value of REFUP and a new delay a new value for UP is calculated This sequence is described here in detail See Figure 4 7 First the Varian places a new delay value DEL 3 16 on I O lines OTB64 0 13 Then under program control a strobe DELSTR is issued If the processor is not in STOP mode a delay cycle is initialized by placing a low level on 3Al A sequence of 8 states Sl to S8 is now started each state lasting 0 5 us 4 8 Sl S24 S3 Set DELCYC clear 3Al load DELCT from LP circuit Clear DATOK disable FLERR Set multiplexers to do DEL REFUP 1 REFUP DEL Get carry if result gt O means same frame Get no carry if result lt O means skip to previous frame or frames Next CLK1 Clock up Load result into UP Set SKPFRM if no carry Set S2 Comments If DEL 0 then we always stay within the same frame If DEL is small then we may have to go to the previous frame depending upon the present REFUP If DEL gt 16 6 ms then we may have to go two frames back SKPFRM 1 amp 2 keep track of this NOOP if no SKPFRMI If SKPFRMl Decrement DELCT with CD Set multiplexers to do UP 66666 1 for SHF1 Get carry if result gt l means s
60. place Finally unused words in the array are set to zero This happens even if the FBS correction is not being done The DLOOP busy switch is cleared and the program switches back to DWAIT and loops there until the next interrupt occurs Varian Program The Varian program types out a message informing the user of the current system date then halts When the computer run button is pushed the Varian reads PREPTAPE information into core then waits for the correlator start button to be pushed The video tapes should be aligned to the same second of time and be in remote control When the correlator start button is pushed the VArian starts the video tapes waits for 30 good frame counts to come in then synchronizes the tpaes to the same frame count Delays are computed strobed into the correlator and correlation begins The Varian enables its interrupts then waits in a tight loop for an interrupt to come in Interrupts occur 60 times per second or ata 16 66666667 millisecond rate This is the innermost loop of the program Other loops are at 100 millisecond and 200 millisecond intervals At the 100 millisecond interval delays and rates are computed for the next 100 millisecond interval The values for the 60 Hz interrupts are derived by linearly interpolating between the values computed for 100 millisecond intervals At the 200 millisecond interval data are either passed to the Nova for transforming or written directly on 9 track magnet
61. ponding check channel The program can correctly analyze and find the failing channel If a counter fails in a way that parallel loading function of the chip malfunctions then other channels than the failing channel are affected The program will indicate failure at random channels or will indicate that the terminator is not zero Often this happens when a totempole output is damaged so that the output voltage is between proper TIL levels This typically causes a high being shifted into the next counter instead of a low Note that since clearing the correlator is done by shifting in all low bits the correlator cannot be cleared A diagnostic program READOUT tests whether the correlator shifts properly Program CORTEST actually correlates data and compares correlator channels with check channel and detects errors by halting at particular error locations Comments at those locations in the listing help analyze the problems The same checking occurs while actual data is correlated by the on line program system An error will be indicated by a TTY message if the difference is larger than two counts Failures of the decoder are indicated by various error lights and data cannot be decoded properly This happens usually when the phase lock loop is maladjusted which retrieves the lock from the BI data Not only must the phase lock loop lock to the input data but the phase must be so that the decoder is able to sample in the middle of a bit cell The adjustme
62. rd and do not need much explanation In the STOP mode recorders are halted and XFER is cleared 60 Hz B and C are locked to 60 Hz A The computer waits in an idle loop which is interrupted every 16 ms to reset the drop out error lights When the START button is pressed the CPU can start 1 2 or 3 recorders and wait till they are at normal speed and BOF errors BUFFLT are off and helical frame count does increment every frame Then the recorders B and C are slewed to line up the frames properly The computer sets XFER 60 Hz B and C are now independent of 60 Hz A the CPU sets delay and the hardware is ready for data reduction Three identical circuits that control the head drum circuit of each recorder are located on this board The circuits are the equivalent of the Hallman circuit for Mark II record terminals With a timing circuit ramp and sample hold an error Signal HEADDRUM is produced proportional to timing difference between BOF and 60 Hz 60 Hz should be behind BOF by 750 us 250 us If it is not within these limits capacity of the buffer memory is exceeded and data is not properly correlated HEADDRUM is connected to the head drum servo amplifier within recorders biases the servo phase detector and therefore moves BOF to proper relation with respect to 60 Hz HEADDRUM does now what trimpot R7 used to do with the old two station Leach hardware 4 13 Recorder Control 2 This card contains the circuit that detects the frame counter
63. rrelator could not correlate during that time This can be reduced to 4 us with a COR RECOVERY command which applies a low signal at SRSET of all correlator cards in parallel It should be noted that while the correlator is read and cleared the prescalers are not affected The four least significant bits are not erased they are included in the counts during the next 200 ms integration The counts of the correlator channels and check channels may differ by one bit If a difference of three counts occurs the on line program causes a message to be typed and turns off the correlator An independent command CORCLR applies a high level at CTRCLR input of the correlator cards in parallel which clears all counters and prescalers It takes 31 us to execute CORCLR which is followed by correlator recovery automatically Correlator mode multiplexers located on the correlator control board select A input B input and multiplier clock of all six blocks and set the correlator into any one of 8 modes as shown in Figure 1 11 A second set of multipliers IF lE 1D 1C 1B 3F and 3E control the extra check board with 8 check channels The check board can be placed in parallel to any other card in the same chassis under program control The check board duplicates exactly all of those 8 channels of correlation and independently of the type of data correlated should show identical counts If a channel is not identical a hardware failure has occurred either in the
64. s now at UP 59 648 This is the transition that the IVC 825 recorder uses to lock its head drum to The circuits internal to the IVC recorders require this timing Je 8 2 ms gt MKII _ lt 16 4 ms gt BUFFRAME 6OHZREF _ TT 14 9 ms 15 3 ms 16 7 ms Figure 4 5 MKIIC Timing A MKIIC furthermore has a shorter frame BUFFRAME goes false at UP 61 440 Since the frame is shorter for MKIIC format the correlator total count will be slightly smaller UP has to trail LP by 512 1024 us This timing is a function of the head drum servo amplifier If phasing is adjusted incorrectly then the buffer is not working properly Fault circuit 185 detects improper phasing timing and sets BFLTA Buffer B C Buffer B and C are identical Each consists of a load control circuit a memory an unload control circuit 1 and an unload control circuit 2 Buffers B and C have a memory of 81 920 bits 20 48 ms which handles the same deskewing task as Buffer A plus a delay of up to 79 864 bits 19 97 ms which may be added under program control This makes it possible to change delay rapidly 4 us and source switching experiments may be processed in one pass instead of two Since 20 ms is longer than one frame the buffer contains a cycle of five frames The write sequence is as follows The BOF for the first frame frame O is loaded at location 0 BOF of the next frame is written at location 65 536
65. s detected GATE closes after 4 bits EOF is not detected MK II C format is chosen to eliminate the problem described above and therefore the BOF circuit works differently The negative transition of 60 Hz triggers the 45 us 1 shot After 45 us gate 10El is enabled to detect BOF Circuit 10E6 9F 9E 10E8 looks for six sequences of 0011 and opens GATE for 250 ns During that time 10D8 should detect the 100 and BOF becomes true for 100 ns clears 5D and disables 10El and closes GATE If BOF is not detected after 1 3 ms BOFWDW is closed BOF timing is shown in Figure 4 2 Bit 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 NRZO 2 3 CLK 1 o olFo Fi r2 r3 F4 F5 P p p oi p BOF _ Figure 4 2 BOF Timing Audio 1 and Audio 2 are decoded in the same decoder circuit A multiplexer selects either one Audio 1 or 2 of all three decoders A B C is selected simultaneously The diphase decoder is straight forward with no critical timing circuit and experience has shown that it works without any trouble Buffer A The buffer contains a 1024 word by four bit memory that works as a silo type first in first out storage Data is written into sequential locations at the rate at which it is decoded from the tape After a time delay of 5512 us and 1024 us the same data is read out at the rate of the reference clock The timing circuit that controls read and write cycle works completely asynchronous with proper interlocks Read and write cycle
66. se from Varian to disable beeper also sense bit to Varian BI coded data from recorders Control bit from Varian to select audio track 2 BI phase coded time data from audio tracks Correlator input data from recorder B Correlator input data for B C cosine baseline Correlator input data for A B cosine baseline Correlator input data for B C sine baseline l6 bit binary input lines to Varian B input of checkboard Control bit from Varian to blank the correlator Beginning of frame Sense bit to Varian when beginning of frame is not detected T 16 6 msec Correlator input data for A B baseline Bit 10 of fringe rotator Sense line to Varian when data is not transferred properly thru deskewing buffer Frame signal after deskewing buffer Bandwidth Bandwidth strobe pulse which strobes bandwidth on BW lines into hardware Correlator input data from recorder C Correlator input data for A C cosine baseline Count down signal Chassis Varian output lines to set checkboard multiplexer Check CLRSTAT CLRXFER CM CMY 1 COMP RDY CORBSY CORCLR CORMX CORMXSTR COROUT CORRECOVE RY CORTEST CPU CRT CS 1 CS IN CTRCLR CU DAT DATOK DELAY DELAYTRACK DELCT DELCYC DELSTR DIM DIMMEMO DIMRESET DMA DROPOUT DSPTC Control pulse from Varian to clear Nova status flip flops Control pulse from Varian to clear transfer flip flop 4 MHz multiplier clock for TC counters 4 MHz multiplier clock to chassis
67. sly avaliable at 10E14 At UP 9 2057 4105 etc 10E is clocked and DATOK is set to the value read from memory 101 is also clocked at the end of each DELCYC by RSREQ When the Load Control requests a write cycle it raises WSAD and puts LP 11 16 on the SYNCAD lines WO and Wl now write a 0 or a 1 depending upon VALSYNC If at that time the Unload Control attempts to clock 10E it is delayed by 9B12 which retriggers 8B and causes a 170 ns delay When MK II C tapes are processed 60 Hz REF is modified by REFUP 59648 At REFUP 0 60 Hz goes high and at 59648 60 Hz goes low The negative transition is used for sync by the IVC recorder Since frame length is shorter for MK 11 C BUFFRAME is shortened by ZDFRM This happens at UP 61440 45056 28672 12288 77824 respectively A buffer fault condition can occur several ways If the value DEL from the CPU exceeds the capacity of the buffer memory gt 79864 then DELFLT becomes true If FLT flip flop gets set the hardware attempts to skip three frames A hardware malfunction has occurred in the delay cycle adder or multiplexers If the Monostore memory has not executed a read or write cycle in time WRFAIL or RDFAIL is set If delay between load pointer and ref unload pointer is not within 512 and 1024 us BFLT is set Any of these errors are fatal and bad data is correlated Recorder Control 1 This board has all circuits to control motion of the video recorders The circuits are straight forwa
68. ssed by LP Memory address bus is time shared between LP and UP Notice that MAI 12 and 13 are low true all others are high true an unfortunate feature of the Monostore III Write control logic works asynchronously with read logic and is interlocked by WRREQ and RD signals Every 2 ys a new 8 bit data word is latched into 2A 2B 2C 2D At the same time SETWRREQ flip flop is set If due to a timing fault either of the Monostore III or of the write logic a request is made when SETWRREO flip flop is still set from a previous request WRFAIL is set indicating that data is not properly written into memory SETWRREQ sets WRREQ flip flop if and when the previous cycle is complete and WRREQ is clear If there is no read RD not true in progress a MWC pulse of 120 ns to the Monostore III is created and simultaneously VALMA becomes true placing LP on the address bus Monostore III now executes a write cycle and after 650 ns when it is finished acknowledges with a 50 ns MCC pulse MCC now clears WRREQ flip flop LP and sync detect resync circuit are the same as for Buffer A A divide by 5 counter 8G keeps track of the 5 frame cycle described earlier It is initialized into proper sequence by OFRAME OFRAME is a 1 per second pulse when frame count 0 is decoded The output of counter 8G is used several ways First it is used to set delay counter DELCT which function is described later The it is also used by a decoding network 7C 7D 7E 7F to decode en
69. ted out of the correlator before the correlator is unblanked A special FFT processor was added to the system to calculate spectra and correct for fractional bit shift Block diagram Figure 1 2 shows the overall system Ma KA A SE ve Fe ET men MG Ka 7 masmapi s HOFS 3 lt 0 lt 133 f INV 23LN3 Ug lt 021 C 39n914 2907 391 029 3 N 4X4 53101214 3901 2 lo 553200 2220007 0 aang 77433 W3ddn Ald lind 10d 1 lddH 723 JAN 99 ANN Eg aog VAN 0 L9 9 pavo ol B I 079 NYIJYA T3 sichs 2034 144 231n440 ANN NO Q9 issauday Al 67 yuq 1933 0 Id nasan MOYA vo 2UYHOLNY SIT SL 31711440 WI Walt 009 Ad SLZ 099NVIN 3 190 31 1 1 3 Specification of Buffer Inputs from each of three video recorders ASTRODATA clipped diphase video signal at 4 Mb s 0 3 15 into 752 HEADSWITCH 0 Hz square wave 7 Mor none for MK II C AUDIO 1 diphase time code at 3 84 Kb s 0 5 20 AUDIO 2 diphase ID code at 3 84 Kb s 0 5 20 Ms Outputs to each of three video recorders RUN Relay contact to start stop recorders 60 Hz REFERENCE 60 Hz TTL square wave to which the recorder motors lock HEAD DRUM Analog signal 7V with TC 5 seconds to control phase of head drum servo Not used for MK II C Inputs from Correlator Control REFCLK 4 MHz square wave master reference UCLK B C 4 MHz square wav
70. the frequency of the 60 Hz reference Gate 3E8 normally creates a reset pulse at REFUP 66680 If this reset pulse happens earlier or later the 60 Hz reference is changed accordingly and the recorders slew Four gates 4A and 4B modify this reset pulse according to slow fast and positive negative slew The circuit for slew C is identical to B The Correlator and Correlator Card The correlator is located in two chassis Chassis O contains all cosine channels and chassis 1 all sine channels Each chassis has 36 correlator cards with 8 channels each and is organized in 6 blocks as shown in Figure 4 8 Each chassis has one additional card with 8 correlator channels which can be placed in parallel to any of the other cards by multiplexers under program control An additional control card contains those multiplexers multiplexers to select correlator modes as shown in Figure l ll and circuits to fan out clock signals The correlator is read out under program control in a fixed sequence as shown in Chapter 3 AX BOO ALIQ Bip BLOCK BLOCK 50032 64 CHOG A0132 b CHIP AOV DR Ao 142 ep Aoc A01 Aij BY ATI BII BLOCK 64 Chi UB AO OI AO LI M02 02 Aim 2 BLOCK 2 BLOCK 2 32 2 32 CHI2 UB 2002 2 Arpa 3 3 3 BLOCk 3 S 0 4 b4 3 yA 3 7 SB 0 A003 Aigpe Any GV e BLOCK 4 64 CHOY bY CM 88 00 AO ATOS BOS ATIS BIS BLOCKS 32 CHS 48 Loos
71. thin the sequence of 5 frames The result may be larger than the size of the memory and overflow is set S5 is to be executed S5 NOOP if no OVFLO If OVFLO Set multiplexers to do UP 49152 UP 81920 Next CIK1 Clock UP if OVFLO load result into UP Set 6 Comment 49152 is the same as 81920 We have now the final UP S6 Increment DELCT with CU Next CLK Set S7 Comment DELCT still had the value for the previous frame Now it needs to be incremented so that end of current frame can be detected properly S7 NOOP Next CLK1 Set S8 S8 NOOP Next CLK1 Reset DELCYC Enable UP clocking Comment During each delay cycle DELCYC normal 4 MHz clocking of UP is inhibited At the end of DELCYC clocking is re enabled At next UPO UPl UP2 0 set SRDREQ and RSREQ Eight bits later the first good data bit appears on DATB C and DATOK B C becomes true DELCT is a three bit divide by five counter which keeps track of the five frame sequence DELCT 14 16 together with UP 14 16 resets FRM flip flop 1A 2B at UP 65536 49152 32768 16384 O respectively This is the end of frame at which time the correlator is blanked and memory read cycles are inhibited UP keeps running till it reaches 1129 or 1130 depending upon SHFO Now FRM goes true 1D is set and LDUP goes true At the next clock UP is set to DELCT at 65536 49152 32768 16384 O respectively LDUP also starts circuit 4E 4F which creates a double pulse CU which in turn
72. wave for TC counters board l MHz Squarewave for delay display CM Multiplier clock 50 ns wide pulse 4 MHz for TC counters CMO 1 50 ns 4 MHz pulse for correlator multipliers CSO l1 Shift clock 50 ns wide for correlator shift registers Frequency 4 MHz to 31 25 depending on bandwidth Multiplier lines CMO CMl and shift clock lines CSO and 051 are long twisted pair lines terminated on both ends by 6892 This avoids overshoot and controls transition times accurately throughout the correlator These lines are driven by open emitter line driver 8T13 Next word shaper is a simple circuit which transforms the transmission of NXTWRD into a 250 ns wide pulse with precise time relation to CM 60 Hz interrupt circuit has the necessary circuit to interrupt the CPU and interlock interrupts with DMA transfers It connects to the computer via the I O bus This 60 Hz interrupt is the only interrupt of the CPU Interrupt location is O since nothing is connected to the interrupt address select lines 60 Hz from buffer sets request flip flop 3G if interrupt enable flip flops 2F8 2F6 are set At the next interrupt clock IUCK interrupt flip flop 3G sets and the CPU gets interrupted by IURX After this interrupt is accepted by the CPU IUAX comes back and clears interrupt request flip flop If a DMA request is pending either TPIX or TPOX is low and interrupt flip flop is held in the clear state by 3G13 At the next IUCK clock 3G9 will not be set Furthermore 8E5

187 - National Radio Astronomy Observatory

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