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SH7786 Group SH7786 PCI Express Controller (PCIEC)

1. E g CE a AP SH4AD 0A configured Es a as PCI Express endpoint Li gt E INDDODODILIODUDIPIDOD 10000000000 Insert PCI Express endpoint PCI Express card edge into PCI Express root port connector CN6 3 L AP SH4AD 0A configured as PCI Express root port G E B bh m um PC USB 02A TTL lt USB board E Console PC Figure 4 1 System Configuration R01AN0557EJ0100 Rev 1 00 Page 29 of 84 Jul 15 2011 3 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 4 2 2 Specifications of Sample Program e Serial console initial settings e PCIEC initial settings PCI Express root port mode or PCI Express endpoint mode settings e Display of PCI Express endpoint Vendor ID and Device ID e Data transfer transmit receive to PCI Express endpoint memory area or IO area e Data transfer transmit receive to PCI Express endpoint memory area by using the on chip DMA e The following operations are not supported by the sample program Stride transfer and command chain operation by using the on chip DMA Message transmit receive INTx or MSI interrupts Link power control function LO LOs L1 and L3 states RO1AN0557EJ0100 Rev 1 00 Page 30 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 4 2 3 Sample Program Flowcharts 1 Flowchart of main Func
2. Start lt pcie config init gt Y Read configuration register config read gt Obtain header and product ID from PCI Express configuration register lt CRS received CRS 1 in PIO control register PCIEPCTLR CRS 1 Device ID 0 confirm device ID DevicelD 0 DevicelD 0 Read configuration register lt config read gt Obtain Max Payload Size Supported MPSS of connected device CAPID 0x10 CAP ID 0x10 CAP ID 0x10 Read configuration register Obtain PCI Express capability structure from PCI Express configuration lt config read gt register Compare Max Payload Size MPS in obtained PCI express capability Obtain MPS structure with MPS in PCIE capability register 1 PCIEEXPCAP1 and use smaller value as MPS Read configuration register Obtain PCI Express capability structure from PCI Express configuration config read register Write to configuration register Set MPS to MPS value of PCI Express capability structure from PCI config write gt Express configuration register v Set PCIE capability register 2 PCIEEXPCAP2 Set obtained MPS in PCIE capability register 2 PCIEEXPCAP2 v Write to configuration register config write gt Y Read configuration register Obtain value of base address register O PCI Express configuration con
3. ORER Clear dif defined CONFIG SCIF CLK EXTERNAL SCIF SCSCR BIT CKE 2 Clock source SCK elif defined CONFIG SCIF CLK PCLK SCIF SCSCR BIT CKE 0 Clock source PCLK t SCBRR VALUE CONFIG BPS CONFIG SCIF CLK PCLK endif CONFIG SCIF CLK RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 3 NE SAS ated Page 76 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 112 113 LE E gt 0 d 114 while t gt 256 HLS ent 116 G gt 24 117 118 if cnt gt 3 19 return 1 120 121 SCIF SCSMR BIT CKS cnt 122 SCIF SCBRR t 123 124 delay 1000 125 126 SCIF SCFCR BIT RTRG 0 127 SCIF SCFCR BI RG 0 128 SCIF SCFCR BIT TFCL 1 Tx FIFO Clear 129 SCIF SCFCR BIT RFCL 1 Rx FIFO Clear 130 131 SCIF SCFCR BI FCL 0 Tx FIFO Not Clear 132 SCIF SCFCR BIT RFCL 0 Rx FIFO Not Clear 133 SCIF SCSCR BIT TE 1 134 SCIF SCSCR BIT RE 1 135 return 0 136 137 138 FUNC COMMENT X X X kk A kk KA KA X KA KA KA K AX KA KA kA k AA kA kk kk kk kk kk A ck 139 ID 140 Outline Sample Program Main 141 142 Include 143 Declaration void scif transmit data char Data 144 Description A transmission of two or more byte data of SCIF 145 14
4. 188 189 while SCIF SCFSR BIT TDFE Weight is carried out until the write of a send data will be in an authorized state 190 SCIF SCFTDR Data A set of a send data 191 while SCIF SCFSR BIT TEND Waiting for the quit of transmitting 192 SCIF SCFSR BI DFE 0 193 SCIF SCFSR BI END 0 194 195 196 197 FUNC COMMENT V X X kc kk Ck kk kk kk KA kk X KA kk Kk Kk kk KA KA X AA KA kA A ck ck A A ck 198 ID 199 Outline Sample Program Main 200 PCIe 201 Include 202 Declaration void sci printf char str 203 Description A text with a format is outputted 204 205 206 ZV 3k 208 209 Limitation 210 211 Argument Data A send data is stored 212 Return Value none 213 Calling Functions 244 PFUNC COMMENT END V V RR ke ke ke e ke X e x x 215 RK IK ok ok kok ok k kk ok kk kc ke kk kk ko ke kk ke ke ke ke e e 216 A text with a format is outputted Ef 2 RK kok ok ok ok kok k oko ok oko oko kok ok kok ok ke ke ke ke e e e x f 218 define PRINTF SIZE 1024 219 static char printf str PRINTF SIZE 220 221 void scif printf char str 222 223 va list args 224 size t size 225 R01AN0557EJ0100 Rev 1 00 Page 78 of 84 Jul 15 2011 RENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 226 Zd 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245
5. bus in order to generate PCI Express packets 1 Overview In a PI O transfer a unit such as the CPU accesses the PCIEC memory space via the SuperHyway bus in order to generate PCI Express packets that are then transmitted PI O transfers can be used to perform memory read write and I O read write access to external PCI Express devices PI O transfers make it possible easily to generate PCI Express packets by accessing the PCI memory space PCI Express read packets are generated by read access and PCI Express write packets are generated by write access In a typical PI O transfer one PCI Express packet is generated per access to the PCI memory space The data length of the generated PCI Express packet is equal to the access size to the PCI memory space For this reason only short PCI Express packets with a data length of 4 bytes can be generated by 4 byte accesses by the CPU so the data transfer efficiency is poor when large amounts of data are transferred To transfer large quantities of data the packet connection function or the DMAC incorporated into the PCIEC should be used Note that the sample program does not support the packet connection function 2 Address Map SuperHyway Space Table 2 5 shows the address map of the SuperHyway space The PCIEC has three address areas consisting of eight physical types the PCI memory area six types the control register area and the configuration register area PCI Express packet
6. if Data n An obtaining data is CR break A processing is completed RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 3 NE SAS Page 79 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 283 if Data 0x0d An obtaining data is CR 284 285 break A processing is completed 286 287 Data The following set of the one plus one address which the data acquired 288 if i 289 290 ret cd 1 291 292 293 if ret cd 1 294 295 break 296 297 298 return ret cd 299 300 301 FUNC COMMENT V X XX kk kk kk kk kk KA kk X KA KA KA K AX KA KA KA X kk KA kk kA ck kk kk kk ck 302 ID 303 Outline Sample Program Main 304 305 Include 306 Declaration char scif recive data byte char Data 307 Description A data reception of SCIF 308 309 310 311 312 313 Limitation 314 315 Argument Data A receive data is stored 316 Return Value 1 A receive data error 317 Calling Functions 318 PFUNC COMMENT END kk kk kk kk kk kk kk kk Ck AAA AA AA 319 char scif recive data byte char Data 320 321 unsigned char ReadData i 0 322 char ret_cd 0 323 324 For ri 325 326 if SCIF SCFSR BIT ER 327 SCIF SCFSR BIT BRK 328 SCIF SCFSR BIT DR An error occurs 329
7. 043 045 History 035 Tool Chain 038 H W Platform 039 Description 041 Operation 042 Limitation 022 Renesas reserves the right without notice to make changes to this 023 software and to discontinue the availability of this software 024 By using this software you agree to the additional terms and 025 conditions found by accessing the following link 026 http www renesas com disclaimer 027 FER CK Ck kk kk kk kk kk kk kk kk kk kk k kk kk kk kk AAA ck ck ck kk ke 028 Copyright C COMMENT 030 System Name 031 File Name 032 Abstract 2010 Renesas Electronics Corporation All Rights Reserved WN ck ck ck ck ck ck ck KKK Technical reference data kckckckckckckckckckck ck ck kc kk SH7786 Sample Program scif c The example of a set of SCIF Sample Program Ver 1 00 SH7786 High performance Embedded Workshop Version 4 07 00 007 C C Compiler Package for SuperH Family V 9 3 2 0 None SH 4A Board P N AP SH4AD 3A Manufacturer ALPHA PROJECT It is an example program of the example of a SH7786 SCIF set 044 KKK KKK KK KKK KKK KK RK RK KK KK 01 Sep 2010 Ver 1 00 First Release 046 FILE COMMENT END NW RR AAA AA 047 048 049 include 050 052 ID 053 Outline 054 scif h 051 FUNC COMMENT WV kk ck kk C Ck Ck Ck ck AA A Ck A ck ck KKK RARA kc KKK Sample Program Main RO1AN0557EJ0100 Rev 1 00 Page 75 of 8
8. 330 ReadData SCIF SCFRDR Read of a data dummy 331 ret cd 1 A set of a reception error 332 SCIF SCFSR WORD amp 0x0000 A clear of an error 333 SCIF SCLSR WORD amp 0x0000 334 335 else if SCIF SCFSR BIT RDF data was received 336 337 Data SCIF SCFRDR data is acquired 338 SCIF SCFSR BIT RDF 0 Clear of a receive data sign 339 SCIF SCFSR BIT DR 0 Clear of a receive data sign RO1AN0557EJ0100 Rev 1 00 Page 80 of 84 Jul 15 2011 RENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 340 scif_transmit_data_byte Data 341 break A processing is completed 342 343 344 return ret cd 345 3 346 RO1AN0557EJ0100 Rev 1 00 Page 81 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 6 scif h This is a header file used by the SCIFO initial settings and serial driver function 01 02 ifndef _SCIF_H 03 define _SCIF_H 04 05 include config h 06 07 if defined CONFIG SCIFO 08 define SCIF volatile struct st scif OxFFEAO000 SCIFO Address 09 elif defined CONFIG SCIF1 10 define SCIF volatile struct st scif OxFFEBOO00 SCIF1 Address 11 elif defined CONFIG SCIF2 12 define SCIF volatile struct st scif
9. Table 4 2 Serial Console Settings Item Specification SCIFO Asynchronous mode Baud rate 115 200 bps Data 8 bits Parity bit None Stop bit 1 bit Flow control None RO1AN0557EJ0100 Rev 1 00 Page 28 of 84 Jul 15 2011 RENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 4 2 Description of Sample Program The sample program presented in this application note uses two AP SH4AD 0A boards one operating as a PCI Express root port and one as a PCI Express endpoint The description that follows covers the basic method whereby after initial PCIEC settings the PCI Express root port displays on the serial console information from the configuration registers of the PCI Express endpoint 4 2 1 System Configuration for Sample Program Two AP SH4AD 0A boards once set as a PCI Express root port and one as a PCI Express endpoint are connected as shown below and the PC USB 024 serial console is used to display settings Vendor ID Device ID etc from the configuration registers of the PCI Express endpoint on the console PC don oowh 2000000
10. 0 Normal Calling Functions unsigned long addr unsigned long pcie_addr short wdata char bdata unsigned long data unsigned unsigned Validation of an I O transmission pcie_enable_io_transfer sel From an I O field to read PCIE_AREA_IO_ADDR addr switch size pcie_addr case 1 bdata data break PCIE READB pcie_addr bdata unsigned long case 2 wdata PCIE READW pcie addr data unsigned long wdata break case 4 data PCIE READL pcie addr break default data break return data RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 34 NE SAS ENT UM oko ok CK Ok Ok Sk Ck kA AAA ck ck ckckckckck ck ckck ck KA k k k ok ko k long pcie io read int sel unsigned long addr unsigned long data unsigned long size END kk kk kk kk kk kk kk kk k k k CK kk kk kk kk kk kk AA AA unsigned long size ENT kk ok CK Ok Ok Sk Ck kA kA XXX KA KA KA Kk kk k Page 57 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 339 ID 340 Outline Sample Program Main 341 PCI Express 342 Include 343 Declaration static int phyreg_write int sel int addr int lane unsigned long data 344 Description The write
11. H 0000 0000 H 1000 0000 H 2000 0000 H 3000 0000 H 8000 0000 H A000 0000 H C000 0000 H FC80 0000 H FCCO 0000 H FCDO 0000 H FD00 0000 H FD80 0000 H FEO0 0000 H FE10 0000 H FE20 0000 H FE30 0000 PCIECO area 2 64 MB PCIEC2 area 2 256 MB PCIEC1 area 2 256 MB PCIEC2 area 1 512 MB PCIEC1 area 1 512 MB PCIECO area 1 512 MB PCIEC2 area 0 4 MB PCIEC2 register reserved 1 MB PCIEC2 area 3 1 MB PCIECO area 0 8 MB PCIEC1 area 0 8 MB PCIECO register reserved 1 MB PCIECO area 3 1 MB PCIEC1 register reserved 1 MB PCIEC1 area 3 1 MB PCIECO memory space PCIECO area 2 64 MB PCIECO I O space PCIECO area 3 1 MB PCIECO area 1 512 MB PCIEC1 memory space PCIEC1 I O space PCIEC1 rea 2 256 MB PCIEC1 area 3 1 MB p area 1 512 MB s b PCIEC2 memory space PCIEC2 I O space wx i E V PCIEC2 area 2 256 MB PCIEC2 area 3 1 MB PES PCIEC2 area 1 512 MB Figure 2 1 Mapping of SuperHyway Address Space to PCI Address Spaces RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 ztENESAS Page 17 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 4 Register Settings for PI O Transfers Table 2 6 lists the t
12. PMCAPI is used to change the power state When a normal configuration write is received the PCIEC reads the bus number and device number in the received packet and writes them to the BusNumber bits 31 to 24 DeviceNumber bits 23 to 19 and FunctionNumber bits 18 to 16 fields in TLCTLR These values are used as requester IDs for the packets generated by the PCIEC RO1AN0557EJ0100 Rev 1 00 Page 12 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 3 Setting Details To use the PCIEC as a root port issue a configuration request and specify settings listed below to initialize the PCI Express These settings are made by the root port to both the root port and endpoint registers The description below applies to the use of a single PCI Express device as the connection target Additional settings are necessary when the connection target is a switch or a bridge a Max Payload Size MPS Setting Examine the Max Payload Size Supported MPSS values in the configuration registers of all the PCI Express devices in the PCI Express system including both root ports and endpoints and use the smallest value as the system MPS Set the MPS value in the configuration registers of all devices both root ports and endpoints b Max Read Request Size MRRS Setting For the PCIEC the MRRS value should be the same as the MPS value Set a value equal to MPS in the configuration re
13. Set PH1 and PHO to SCIFO Figure 4 4 Flowchart of Pin Function Settings RO1AN0557EJ0100 Rev 1 00 Page 33 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 3 Flowchart of SCIFO Initial Settings This flowchart shows the processing sequence for making SCIFO initial settings for use as a serial console Start lt scif_init gt v Set serial control register 0 SCSCRO Clear TIE RIE TE and RE to 0 v Set FIFO control register 0 SCFCRO Y Set serial status register 0 SCFSRO Y Set line status register 0 Clear TX and RX FIFOs Clear BRK DR and TR to O SCLSRO Clear ORER to 0 EXT SCK input Select the source clock to determine the baud rate INI P EXT SCK external input Select source clock Set serial control register 0 Set Pd as source Set serial control register 0 Set SCK external SCSCRO SCSCRO input as source clock Set bit rate register O SCBRRO Set to 115 200 bps Wait in software Wait in software for 1 bit period Set FIFO control register 0 Receive FIFO data count trigger Set to 1 SCFCRO Transmit FIFO data count trigger Set to 32 Set to not clear TX and RX FIFOs Transmit enable Set to 1 Receive enable Set to 1 End Figure 4 5 Flowchart of SCIFO Initial Settings RO1AN0557EJ0100 Rev 1 00 Pa
14. 0x20040 045 define MSIFR 0x20044 046 define PWRCTLR 0x20100 047 define PCCTLR 0x20180 048 define LARO 0x20200 049 define LAMRO 0x20208 050 define LAR 0x20220 051 define LAMR1 0x20228 052 define LAR2 0x20240 053 define LAMR2 0x20248 R01AN0557EJ0100 Rev 1 00 Page 69 of 84 Jul 15 2011 ENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 054 055 056 057 058 059 060 061 062 063 064 065 066 067 068 069 070 071 072 073 074 075 076 077 078 079 080 081 082 083 084 085 086 087 088 089 090 091 092 093 094 095 096 097 098 099 F O O Oo o o oo o o o COO O VN a U M UN F o RO1AN0557EJ0100 Rev 1 00 define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define define Jul 15 2011 LAR3 LAMR3 LAR4 LAMR4 LAR5 LAMR5 PALRO PAHRO PAMRO PTC PALR1 PAHR1 PAMR1 PTCTLR1 PALR2 PAHR2 PAMR2 PTCTLR2 PALR3 D o N E SAL TLRO LR3 LRO RO RO BCNTRO SBC STR CCA CHC CHS PAL PAH SAL TRO RO
15. 0xFFEC0000 SCIF2 Address 13 elif defined CONFIG SCIF3 14 define SCIF volatile struct st scif OxFFEDOOO0 SCIF3 Address 15 elif defined CONFIG SCIF4 16 define SCIF volatile struct st scif OxFFEEOO00 SCIF4 Address 17 elif defined CONFIG SCIF5 18 define SCIF volatile struct st scif OxFFEF0000 SCIF5 Address 19 endif CONFIG SCIFn 20 21 define SCBRR VALUE bps clk clk 16 bps 16 bps 1 22 define SCBRR VALUE bps clk clk 32 bps 1 23 24 SCFCR 25 defineRTRG1 0 26 defineRTRG16 1 27 defineRTRG32 2 28 defineRTRG48 3 29 defineTTRG32 0 30 defineTTRG16 1 31 defineTTRG2 2 32 defineTTRGO 3 33 34 35 36 endif _SCIF_H R01AN0557EJ0100 Rev 1 00 Page 82 of 84 Jul 15 2011 34 NE SAS SH7786 Group 5 Reference Documents Software Manual SH4 A Software Manual REJ09B0003 The latest version can be downloaded from the Renesas Electronics Web site Hardware Manual SH7786 Group User s Manual Hardware REJO9B0501 The latest version can be downloaded from the Renesas Electronics Web site Evaluation Board Manual AP SH4AD 0A SH 4A Multi SH7786 CPU Board Hardware Manual The latest version can be downloaded from the Alpha Project Web site SH7786 PCI Express Controller PCIEC Initialization Sample Program RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 34 NE SAS Page 83 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization S
16. 157 define 158 define 159 define 160 define 161 define 62 define 163 define 164 define 165 define 166 define 167 define RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 DMCHCR3 DMCHSR3 PCICONFO PCICONF1 PCICONF2 PCICONF3 PCICONF4 PCICONF5 PCICONF 6 PCICONF7 PCICONF8 PCICONF9 PCICONF10 PCICONF11 PCICONF12 PCICONF13 PCICONF14 PCICONF15 PMCAPO PMCAP1 SICAPO SICAP1 SICAP2 SICAP3 SICAP4 SICAP5 EXPCAPO EXPCAP1 EXPCAP2 EXPCAP3 EXPCAP 4 EXPCAP5 EXPCAP 6 EXPCAP7 EXPCAP8 VCCAPO VCCAP1 VCCAP2 VCCAP3 VCCAP4 VCCAP5 VCCAP 6 VCCAP7 VCCAP8 VCCAP 9 NUMCAP 0 NUMCAP1 NUMCAP2 IDSETR1 IDSETR2 DSERSETRO DSERSETRI TLSR LCTLR DLS DLCTLR ACSR d Ox211E8 Ox211EC 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x4 0x41 0x41 0x41 0x41 0x41 0x41 0x41 0x41 0x41 CX O SC C CO C OS OQ C COO O C Oe O O OQ CO 000 004 008 00C 010 014 018 01C 020 024 028 02C 030 034 038 03C 040 044 050 054 058 05C 060 064 070 074 078 O7C 080 084 088 08C 090 100 104 108 10C 110 114 118 IIC 120 124 1B0 1B4 1B8 004 024 02C 03
17. AA ke ee eek 201 volatile void BuffClear char pBuff int size 202 203 int i 204 for i 0 i lt size i A clear of a serial data receiving workpiece 205 206 pBuff i 0 207 208 209 210 FUNC COMMENT X XX kk A kk kk kk X KA KA Kk X AX Ck A A ck ck ck kk ck ck ck 204 9 TD 212 Outline Sample program main 213 PCI Express 214 Include 215 Declaration volatile void SdramDataInit int cnt 216 Description A initialization of the data for sdram 2177 218 2X9 220 221 222 Limitation 223 224 Argument none R01AN0557EJ0100 Rev 1 00 Page 49 of 84 Jul 15 2011 3 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 Return Value none Calling Functions PFUNC COMMENT END x a a a ARA k k k k AAA AAA AAA ee eek volatile void SdramDataInit int cnt int i int sdram add 0xA0000000 sdram data area for i 0 i lt cnt 4 i SDRAM Data Initialize cnt 4 byte unsigned long sdram_add i sdram_add 4 ifdef _ cplusplus void abort void endif RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 34 NE SAS Page 50 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 2 config h This is
18. CK kk kk AAA ck k kc kck ck ck k ck ck A ID Outline Sample program main o a a NF O PCI Express Include Declaration void pfe init void oV a a ow Ww Description A set of a pin function o o ov J RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 3 NE SAS ret pcie start dma CONFIG PCIE ROOT PCIE AREA ADDR sdram data area 0x1000 PCIE READ TransByte printf Xn r SH7786 PCI Express DEMO Sample END Point NnNr Page 48 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 168 169 DOs 171 Limitation 172 173 Argument none 174 Return Value none 175 Calling Functions 176 PFUNC COMMENT END V RR ke 177 void pfc init void 178 179 SOIEQ 180 GPIOR PHCR WORD OxFC30 181 182 183 FUNC COMMENT X XX kk kk kk kk kk kk Kk X KA kk Kk KK Ck KA Kk Kk Ck KA kA kA ck kk kk A ck 184 ID 185 Outline Sample program main 186 PCI Express 187 Include 188 Declaration void BuffClear char pBuff int size 189 Description A initialization of the buffer for serial receive datas LEO 191 192 1 93 194 195 Limitation 196 197 Argument pBuff Buffer size Buffer siz 198 Return Value none 199 Calling Functions 200 PFUNC COMMENT END MARAR a k k k k k k k k k k k AAA
19. Functions 393 PFUNC COMMENT END V V RR ke ke kk ke e ke e ke e x 394 static int phyreg read int sel int addr int lane unsigned long data 395 R01AN0557EJ0100 Rev 1 00 Page 58 of 84 Jul 15 2011 RENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 396 unsigned long wdata 397 398 Read of a physical layer control register 399 wdata 0x00020000 lane amp Oxf lt lt 8 addr amp Oxff 400 PCIE_REG sel PHYCTLR 0x00000001 clock enable 401 PCIE_REG sel PHYADRR wdata A set of a command address 402 while PCIE REG sel PHYADRR amp 0x01000000 0 403 404 Waiting for ACK 405 data PCIE REG sel PHYDINR Read data 406 PCIE REG sel PHYADRR 0x00000000 Command clear 407 while PCIE REG sel PHYADRR amp 0x01000000 0 408 409 PCIE REG sel PHYCTLR 0x00000000 Clock disabling 410 411 return 0 412 413 414 FUNC COMMENT V X XX kk kk kk kk kk KA KA X KA kk KA Kk CK kk AA A ck kk kk kk ck 415 ID 416 Outline Sample Program Main 417 PCI Express 418 Include 419 Declaration static int config read int sel int bus int dev int func int regno unsigned long data 420 Description Read of a configuration register 421 422 4
20. PCI DMAC SuperHyway address lower register 0 PCIEDMSALRO Set SDRAM address in PCI DMAC SuperHyway address lower register 0 y Set PCI DMAC byte count register O PCIEDMBCNTRO Set DMA transfer byte count in PCI DMAC byte count register 0 No Ready for DMA transfer Check PE SE and TE flags in PCI DMAC channel status register 0 Set PCI DMAC channel control Set CHE to 1 in PCI DMAC channel control register 0 to set transfer direction register 0 PCIEDMCHCRO to DIR DMA manster finished Check TE flag in PCI DMAC channel status register 0 Set PCI DMAC channel control register 0 PCIEDMCHCRO Clear CHE to 0 in PCI DMAC channel control register 0 Y Set PCI DMAC channel control register 0 PCIEDMCHCRO Y Set TE to 1 in PCI DMAC channel status register O to clear the flag Figure 4 20 Flowchart of PCIEC Internal DMAC Transfer RO1AN0557EJ0100 Rev 1 00 Page 45 of 84 Jul 15 2011 3 NE SAS SH7786 Group 4 2 4 Sample Program 1 PCIe DemoSample c This is a program listing of the main function SH7786 PCI Express Controller PCIEC Initialization Sample Program CO XO OC O O O CO O oc O c o U O U M UN E O o me 10 U MD UN r J KCKCKCKCk kok ok k ok k ok k k kk oko oko oko oko ok oko ok ok kok kok kok kok kok kok kok kok kok kok k kok k kok k kok kk kok pe FIL
21. Sample Program 4 pcie h This is a header file used by the main function PCIEC initialization function PCI Express control function and DMAC control function 001 ifndef PCIE H 002 define PCIE H 003 004 include config h 005 006 define PCIE BASE 0xFE000000 007 define PCIE REG p x volatile unsigned long PCIE BASE p lt lt 21 x 008 009 define ENBLR 0x00008 010 define ECR 0x0000C 011 define PAR 0x00010 012 define PCTLR 0x00018 013 define PDR 0x00020 014 define MSGALR 0x00030 015 define MSGAHR 0x00034 016 define MSGCTLR 0x00038 017 define UNLOCKCR 0x00048 018 define IDR 0x00060 019 define DBGCTLR 0x00100 020 define INTXR 0x04000 021 define RMSGR 0x04010 022 define RMSGIER 0x04040 023 define RSTRO 0x08000 024 define RSTR1 0x08004 025 define RSTR2 0x08008 026 define RSTR3 0x0800C 027 define SRSTR 0x08040 028 define PHYCTLR 0x10000 029 define PHYADRR 0x10004 030 define PHYDINR 0x10008 031 define PHYDOUTR 0x1000C 032 define PHYSR 0x10010 033 define TCTLR 0x20000 034 define TSTR 0x20004 035 define INTR 0x20008 036 define INTER 0x2000C 037 define EHOR 0x20010 038 define EHIR 0x20014 039 define EH2R 0x20018 040 define EH3R 0x2001C 041 define ERRFR 0x20020 042 define ERRFER 0x20024 043 define ERRFR2 0x20028 044 define MSIR
22. U O1 U SG O E So 6 KO O0 JO U BM UN F o Description Limitation Argument Return Value Write of a configuration register none Calling Functions PFUNC COMMENT END V RR kk ke e ke e ke static int config write int sel int bus int dev int func int regno unsigned unsigned long wdata PCIE_REG sel PCTLR 0x80000000 An issue Clearance of a configuration wdata bus lt lt 24 dev lt lt 19 func lt lt 16 regno PCIE_REG sel PAR wdata Set of addr bus dev func PCIE_REG sel PDR data Issue of configuration read PCIE_REG sel PCTLR 0x00000000 Issue of a configuration request is f return 0 FUNC COMMI ENTENDA XXX KX KA KA X ck ckck ck ckck ck ckckckckckck ck k ck ko kk k ID Outline Include Declaration Description Limitation Argument Return Value Sample Program Main PCI Express static void pcie soft reset int sel Software reset of a PCIE controller none none Calling Functions FUNC COMM ENT END V V RR kk ke ke e x x static void pcie soft reset int sel A run of software reset PCIE_REG sel SRSTR 0x00000001 A reset of a PCIE internal register PCIE_REG sel TCTLR 0x00000000 A reset of software reset PCIE_RE
23. a PCI space One set of target transfer registers allocate one PCI space when a 32 bit space is used and two sets of transfer registers allocate one PCI space when a 64 bit space is used Table 2 7 Transfer Control Registers for Target Transfers PCIELARLn Start address of the local bus SuperHyway space to which PCI area n will be mapped PCIELAMRn Specifies size of PCI area n Note The value of n is 0 or 1 for a root port and 0 to 5 for an endpoint PCIELARLn specifies the address on the SuperHyway bus to which area BARn is mapped The value of n can be 0 or 1 for a root port and 0 to 5 for an endpoint PCIELAMRn specifies the size and type memory space I O space etc of the PCI area allocated in the PCI space and whether the area is enabled or disabled The area cannot be allocated in the PCI space if it is not enabled in PCIELAMRn and no transfers will be performed to the internal bus The initial setting after a reset is disabled for all areas RO1AN0557EJ0100 Rev 1 00 Page 21 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 4 Conversion from PCI Address to SuperHyway Bus Address Figure 2 4 illustrates decoding of PCI space addresses and figure 2 5 illustrates conversion of PCI addresses to SuperHyway addresses When a PCI Express packet is received first its address is decoded The address decoding differs depending on whether the address widt
24. a header file used by the main function 01 ifndef _CONFIG_H_ 02 define _CONFIG_H_ 03 04 include lt stdarg h gt 05 include lt stdio h gt 06 include lt stdlib h gt 07 include iodefine h 08 09 defineLong 4 defineWord 2 defineByte Ak o SCIF define CONFIG PCLK 44400000 define CONFIG SCIFO define CONFIG SCIF1 define CONFIG SCIF2 define CONFIG SCIF3 define CONFIG SCIF4 define CONFIG SCIF5 define CONFIG SCIF CLK EXTERNAL define CONFIG_SCIF_CLK_PCLKCONFIG_PCLK define CONFIG BPS115200 o IS U BK WN r DO o N mn N N V NM N M oV UMa U define CONFIG PCIE ROOT 0 define CONFIG PCIE END 1 N N N to CO undef printf Co e define printf scif_printf W w NF SCIF extern void delay int cnt 99 U 34 extern int scif init void 35 extern char scif recive data char Data 36 extern char scif recive data byte char Data 37 extern void scif transmit data char Data 38 extern void scif transmit data byte char Data 39 extern void scif printf char str 40 41 PCIe od N extern void pcie_init int sel ws U extern void pcie check int sel D Bs extern void pcie enable mem transfer int sel 45 extern long pcie mem write int sel unsigned long addr unsigned long data unsigned long size 46 extern unsigned long pcie mem read
25. dev ctrl amp OxFFFFFFIF mps lt lt 5 bit7 5 is substituted for MPS PCIE REG sel EXPCAP1 dev ctrl A set of a command and a register config write sel 0 1 0 PCIE CONF COMMAND 0x00000007 External Set of BAR Splicing place device config read sel 0 1 0 PCIE CONF BASE ADDRESS 0 amp dev bar dev type dev bar amp 0x06 if dev type 0x00 32 bit space device config_write sel 0 1 0 PCIE_CONF_BASE_ADDRESS_0 PCIE_AREA_ADDR config write sel 0 1 0 PCIE CONF BASE ADDRESS 2 PCIE AREA IO ADDR else if dev type 0x04 64 bit space config write sel 0 1 0 PCIE CONF BASE ADDRESS 0 PCIE AREA ADDR config write sel 0 1 0 PCIE CONF BASE ADDRESS 1 0x00000000 An obtaining of all the configuration registers of an external device for regno 0 regno lt PCIE MAX CONFREG SIZE 4 regno config read sel 0 1 0 regno 4 amp data config data regno data RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 3 NE SAS Page 64 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 738 739 740 741 742 743 744 745 746 747 748 749 750 TIL 752 733 754 795 756 To 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 719 780 781 7
26. in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal
27. int sel unsigned long addr unsigned long size 47 extern void pcie enable io transfer int sel 48 extern long pcie io write int sel unsigned long addr unsigned long data unsigned long size 49 extern unsigned long pcie io read int sel unsigned long addr unsigned long size 50 51 endif CONFIG H RO1AN0557EJ0100 Rev 1 00 Page 51 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 3 pcie c This is a program listing of the PCIEC initialization function PCI Express control function and DMAC control function oOo C Q O O oo Oo O O C o U o U M UN FE O o em VJ a U AM UN r 025 026 030 031 032 033 043 045 049 include DISCLAIMER 3 RK HK ok ok RR kk kk kk kk kk kk kk Ck kk kk kk kk kk kk ke kk kk kk kk kk kk kk kk RR kk k k k k his software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products No other uses are authorized his software is owned by Renesas Electronics Corporation and is protected under all applicable laws including copyright laws HIS SOFTWA REGARDING T INCLUDING B PARTICULAR DISCLAIMED TO THE MAXI ELECTRONICS FOR ANY DIRI RE IS PROVIDED AS IS AND RENESAS MAKES NO WARRANTII HIS SOFTWARE WHETHER EXPRESS IMPLIED OR STATUTO
28. phyreg write sel 0x65 Oxf 0x09070907 545 phyreg write sel 0x66 Oxf 0x00000010 546 phyreg write sel 0x74 Oxf 0x0007001C 547 phyreg write sel 0x79 Oxf 0x01FC000D 548 phyreg write sel OxBO Oxf 0x00000610 549 550 A boot of a physical layer 551 phyreg_write sel 0x67 0x1 0x00000400 552 553 if sel 554 phyreg_read sel 0x67 Oxl amp data 555 556 The clock of a physical layer register space accessing is suspended 557 PCIE REG sel PHYCTLR 0x00000000 558 559 Waiting for set a physical module 560 stime 1000 561 while stime 562 It waits until a physical module will be in a ready state 563 if PCIE REG sel PHYSR amp 0x00000001 0 564 break 565 566 delay 1000 Page 61 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 567 568 if stime 569 return 1 570 571 printf Finish n r 572 573 return 0 574 575 576 FUNC COMMENT X XX kk kk kk kk kk KA Kk X KA KA KA X AX AXA kk k AA KA kA kA A k AH A ck od ID 578 Outline Sample Program Main 57 9 PCI Express 580 Include 581 Declaration static int pcie trans cont init int sel 582 Description The initialization of a PCIE controller transfer control register 583 584 285 586
29. the DIP switches as indicated below For a detailed description of the DIP switches see section 2 Functions in AP SH4AD 0A Hardware Manual e PCI Express mode setting SW2 2 MODE11 PCI Express Mode ON Root port mode e PCI Express PHY mode setting SW2 3 MODE12 PCI Express PHY Mode ON 4 lane 1 lane 4 1 3 Settings for PCI Express Endpoint Mode To set the AP SH4AD 0A to operate in PCI Express endpoint mode set the DIP switches as indicated below For a detailed description of the DIP switches see section 2 Functions in AP SH4AD 0A Hardware Manual e PCI Express mode setting SW2 2 MODE11 PCI Express Mode OFF Endpoint mode e PCI Express PHY mode setting SW2 3 MODE12 PCI Express PHY Mode ON 4 lane 1 lane Note To operate the AP SH4AD 0A in PCI Express endpoint mode while supplying power from the PCI Express card edge use a soldering iron to open solder junction JP1 on the board For a detailed description of power supply configuration see section 3 7 1 Power Supply Examples in AP SH4AD 0A Hardware Manual 4 1 4 Serial Console Settings The sample program uses SCIFO as the serial interface of the AP SH4AD 0A and the relevant settings are described below The PC USB 02A is used as the serial console The PC USB 02A converts the TTL serial level of SCIFO into a USB signal allowing communication with a PC For details of the serial interface and console see 3 7 Serial Interface in AP SH4AD 0A Hardware Manual
30. the system receiving error messages recovering from errors etc The root port also transmits request packets returns completion packets and transmits and receives messages PCI Express endpoint PCI Express endpoints are ports that perform data communication under the control of a root port A PCI Express system can have multiple endpoints After an endpoint is initialized in the configuration cycle it performs error detection sends notifications to the root port etc Endpoints also transmit request packets return completion packets and transmit and receive messages I O address space The I O address space is PCI bus compatible Memory address space The memory address space is PCI bus compatible Configuration register space The configuration register space is PCI bus compatible The total configuration register space comprises 4 096 bytes of which the lower 256 bytes compose an area that is compatible with the earlier PCI bus standard The upper 3 840 bytes compose an area used by PCI Express that is called the PCI Express extended configuration space 1 5 Scope of the Sample Program The sample program introduced in this application note does not support all the functions of the PCI Express controller PCIEC The application note describes basic usage scenarios in which after initialization the PCI Express controller PCIEC operates either as a PCI Express root port or endpoint When operating as a PCI Express root port it dis
31. to a physical layer control register 345 346 347 348 349 350 Limitation 351 352 Argument none 353 Return Value 0 354 Calling Functions 355 PFUNC COMMENT END kk kk kk kk kk kk kk Ck AAA AA AA 356 static int phyreg write int sel int addr int lane unsigned long data 357 1 358 unsigned long wdata 359 360 The write to a physical layer control register 361 wdata 0x00010000 lane amp Oxf lt lt 8 addr amp Oxff 362 PCIE_REG sel PHYCTLR 0x00000001 clock enable 363 PCIE_REG sel PHYDOUTR data A set of a writed data 364 PCIE_REG sel PHYADRR wdata A set of a command address 365 while PCIE REG sel PHYADRR amp 0x01000000 0 366 367 Waiting for ACK 368 PCIE REG sel PHYADRR 0x00000000 Command clear 369 while PCIE REG sel PHYADRR amp 0x01000000 0 370 371 PCIE REG sel PHYCTLR 0x00000000 Clock disabling 372 373 return 0 374 375 376 FUNC COMMENT Ma X XX kk kk kk kk kk kk KA Kk Ck kk KA Kk Ck KA KA X AA KA kA kA ck A A kk ck 377 ID 378 Outline Sample Program Main 379 PCI Express 380 Include 381 Declaration static int phyreg read int sel int addr int lane unsigned long data 382 Description Read of a physical layer control register 383 384 385 386 387 388 Limitation 389 390 Argument none 391 Return Value 0 392 Calling
32. 0 044 048 04C 050 054 3 NE SAS Page 71 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 168 define MACCTLR 0x41058 169 define PMSR 0x4105C 170 define PMCTLR 0x41060 171 define TLINTENR 0x41064 172 define DLINTENR 0x41068 173 define MACINTENR 0x4106C 174 define PMINTENR 0x41070 175 define TXSR 0x44028 176 define TXVCOSR 0x44108 177 178 LYD 180 PCIE DMAC 181 182 DMAOR 183 define DMAE 1 lt lt 31 184 185 CHCR 186 define CHE 1 lt lt 31 187 define DIR x x lt lt 30 188 189 define PCIE_WRITE 1 190 define PCIE READ 0 191 192 CHSR 193 define PE 1 lt lt 11 194 define SE 1 lt lt 195 define TE 1 lt lt 0 196 197 198 199 PCI area 200 201 ifdef CONFIG_PCIE_ROOT 202 define PCIE AREA ADDR OxFD000000 PCI area 0 address 203 define PCIE AREA IO ADDR OxFE100000 PCI area 3 address 204 else 205 define PCIE AREA ADDR 0xFD800000 PCI area 0 address 206 define PCIE AREA IO ADDR OxFE300000 PCI area 3 address 207 endif 208 209 k 210 SDRAM DATA area 2 X 212 define sdram data area 0x0C000000 SDRAM DATA AREA 213 214 215 PCIE data macroinstr
33. 00 Page 54 of 84 Jul 15 2011 34 NESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 unsigned long addr 3 NE SAS long pcie mem read unsigned long addr unsigned long data unsigned long size END V RR AAA AA unsigned long size 168 PCI Express 169 Include 170 Declaration 171 Description Read of a memory space 172 173 174 175 176 177 Limitation 178 179 Argument none 180 Return Value 1 size error 0 Normal 181 Calling Functions 182 FUNC COMMENT 183 unsigned long pcie mem read int sel 184 185 unsigned long pcie addr 186 unsigned short wdata 187 unsigned char bdata 188 unsigned long data 189 190 Memory transfer is validated 191 pcie enable mem transfer sel 192 193 From a memory space to read 194 pcie addr PCIE AREA ADDR addr 195 switch size 196 case 1 197 bdata PCIE READB pcie addr 198 data unsigned long bdata 199 break 200 case 2 201 wdata PCIE READW pcie addr 202 data unsigned long wdata 203 break 204 case 4 205 data PCIE READL pcie addr 206 break 207 default 208 data 0 209 break 210 211 return data 212 213 214 215 FUNC COMMENT X X kk kk kk kk kk kk Ck X KA KA KA
34. 116 break 117 default 118 return 1 119 120 121 return 0 122 123 124 FUNC COMMENT V X XX kk kk Ck Ck kk kk kk KA X KA KA Kk Kk Ck Ck KA kA Kk Ck kA kk kk ck ck ck ck kk kk ck 125 ID 126 Outline Sample Program Main 127 PCI Express 128 Include 129 peciaration long pcie endpoint mem burst write int sel unsigned long addr unsigned long data unsigned long size 130 Description It is a burst write to a memory space 131 132 ISS ue 134 T35 x 136 Limitation T37 3 138 Argument none 139 Return Value l size error 0 Normal 140 Calling Functions 141 PFUNC COMMENT END kk kk kk kk kk kk kk kk kk k k AAA AA 142 long pcie mem burst write int sel unsigned long addr unsigned long data unsigned long size 143 144 unsigned long pcie_addr 145 int i 146 147 Memory transfer is validated 148 pcie_enable_mem_transfer sel 149 150 Validation of a packet joining MAX 4096 byte 151 PCIE REG sel PTCTLRO 0x9B000000 152 153 The 16byte write to a memory space 154 pcie addr PCIE AREA ADDR addr 155 156 for i 0 i lt size 4 i 157 PCIE WRITEL pcie addr i 4 data i 158 159 160 A run of a packet joining 161 PCIE REG sel PCCTLR 0x00000001 162 163 return 0 164 165 FUNC COMMENT X X A Ck kk KA KA X KA KA Kk KX AX Ck Ck kk k AA KA kA kA ck kk kk kk ck 166 ID 167 Outline Sample Program Main R01AN0557EJ0100 Rev 1
35. 18 17 0 PCIEPALRn A 0 312928 18 17 0 1 Selected for each bit according to the V corresponding bit in PCIEPAMRn SuperHyway address ZZ 312928 18 17 0 PCIEPAMRn Figure 2 2 Address Conversion to PCI Space RO1AN0557EJ0100 Rev 1 00 Page 19 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 2 6 Target Transfers Data Transfer from External Device to PCIEC Target transfers are described below As used here target transfer refers to the reception of a PCI Express packet from an external device by the PCIEC and to the transfer of data to another module in the SH7786 via the SuperHyway bus 1 Overview In a target transfer an external device accesses the PCIEC by using a PCI Express packet a request to the SuperHyway bus is generated and data is transferred to another module Target transfers enable an external device to perform read write access to another module in the SH7786 or to external memory connected to it such as DRAM by transmitting memory read write or I O read write packets In a target transfer the PCIEC can receive packets of any data length less than or equal to the specified Max Payload Size MPS When a transfer using a size greater than that supported by the SuperHyway bus is specified the PCIEC splits the packet and generates multiple internal bus requests 2 Address Map PCI Express Space Figure 2 3 illustrates mapping of the PCI space to the
36. 2 85 k 256 Argument none 257 Return Value l size error 0 Normal 258 Calling Functions 259 PFUNC COMMENT END kk kk kk kk kk kk kk AAA AAA AA 260 long pcie io write int sel unsigned long addr unsigned long data unsigned long size 261 1 262 unsigned long pcie addr 263 264 Validation of an I O transmission 265 pcie enable io transfer sel 266 267 The write to an I O field 268 pcie addr PCIE AREA IO ADDR addr 269 switch size 270 case 1 271 PCIE WRITEB pcie addr data 272 break 213 case 2 274 PCIE WRITEW pcie addr data 275 break 276 case 4 2171 PCIE WRITEL pcie addr data 278 break 279 default 280 return 1 281 RO1AN0557EJ0100 Rev 1 00 Page 56 of 84 Jul 15 2011 3 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 282 283 284 285 286 287 288 209 290 291 K 292 203 294 295 296 297 298 209 WWWWWW WWW C0 C0 C0 C0 C0 C0 ww Ww Ww O0 U o U M UN FE O o CO VJ o UO A UN r o Ww oO 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 FUNC COMM FUNC COMMENT unsigned long pcie_io_read int sel NEUNC COMM return 0 ID Outline Sample Program Main PCI Express Include Declaration Description Read of an input output field Limitation Argument none Return Value 1 size error
37. 23 424 425 426 Limitation 427 428 Argument none 429 Return Value Q 430 Calling Functions 431 PFUNC COMMENT END V V RR kk ke ke e 432 static int config read int sel int bus int dev int func int regno unsigned long data 433 434 unsigned long wdata 435 436 PCIE REG sel PCTLR 0x80000000 An issue Clearance of a configuration request 437 wdata bus lt lt 24 dev lt lt 19 func lt lt 16 regno 438 PCIE_REG sel PAR wdata 439 440 Set of addr bus dev func 441 data PCIE_REG sel PDR Issue of configuration read 442 PCIE_REG sel PCTLR 0x00000000 Issue of a configuration request is forbidden 443 444 return 0 445 446 447 FUNC COMMENT X X ckck kk kk Ck Ck Ck kk KA X KA KA Kk K AX kk Ck Kk X AA Ck kc kc kA k k A A ck 448 ID 449 Outline Sample Program Main 450 PCI Express 45 Include 452 Declaration static int config write int sel int bus int dev int func int regno unsigned long data RO1AN0557EJ0100 Rev 1 00 Page 59 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 U U U UG U U U
38. 246 247 248 249 250 251 252 293 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 219 280 281 282 FUNC COMMI FUNC COMM size strlen str if size gt PRINTF SIZE return va start args str vsprintf printf str str args va end args scif transmit data printf str ENTERRADA AAA ck ck ck KX k k k ck ko kk k received ID Outline Sample Program Main Include Declaration char scif recive data char Data Description The data of SCIF is Limitation Argument Data A receive data is stored Return Value 1 A receive data Calling Functions rror ENT END kk kk kk kk kk kk kk kk k AAA AAA char scif_recive_data char Data unsigned char ReadData i 0 char ret_cd 0 for if SCIF SCFSR BIT ER SCIF SCFSR BIT BRK SCIF SCFSR BIT DR An error occurs ReadData SCIF SCFRDR Read of a data dummy ret cd 1 A set of a reception error SCIF SCFSR WORD amp 0x0000 A clear of an error SCIF SCLSR WORD amp 0x0000 else if SCIF SCFSR BIT RDF A data was received Data SCIF SCFRDR A data is acquired SCIF SCFSR BIT RDF 0 A clear of a receive data sign SCIF SCFSR BIT DR 0 A clear of a reception sign scif transmit data byte Data
39. 4 Jul 15 2011 3 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 055 056 057 058 059 060 061 062 063 064 065 066 067 068 069 070 071 072 073 074 075 076 077 078 079 080 081 082 083 084 085 086 087 088 089 090 091 092 093 094 095 096 097 098 099 0 L1 1 Include Declaration int delay int cnt Description Software weight A part for the count of cnt and a for are repe Limitation Argument cnt Return Value none Calling Functions FUNC COMMENT END V V xk kk kk kk kk kk kk kk k Ck kk kk kk kk kk kk kk kk ke ke kk ke o ke e ke e x x void delay int cnt int i for i 0 i lt cnt i FUNC COMMENT x oko kk Kk AAA AAA AAA ck ck ck A ID Outline Sample Program Main Include Declaration int scif init void Description The initialization of SCIF Limitation Argument none Return Value 1 Baud rate clock count error Calling Functions PFUNC COMMENT END V AAA ke ke e ke e x int scif init void unsigned short data int t 1 cnt 0 SCIF SCSCR WORD 0x0000 TIE RIE TE RE Clear SCIF SCFCR BIT TFCL 1 Tx FIFO Clear SCIF SCFCR BIT RFCL 1 Rx FIFO Clear SCIF SCFSR WORD 0x0000 BRK DR TR Clear SCIF SCLSR BIT ORER 0
40. 434 NE SAS APPLICATION NOTE SH7786 Group SH7786 PCI Express Controller PCIEC Initialization MMC oO Sample Program Jul 15 2011 Introduction This application note presents a sample program for making the initial settings required by the PCI Express controller of the SH7786 Target Device SH7786 Contents JEn mL E eia 2 2 PCI Express Controller PCIEC erre eren KKK nnn nnns 6 3 Serial Communication Interface SCIFO eee nennen nennen nnns 27 4 Application Example ct nt d aae Renten the dadas pasa de URCA E Aa hovada das nd aaa dra Eaa 27 5 Reference DOCUMENTS azar iere eet ee eeu ret dentata qe sed MAIAS Ad eder a AE 83 RO1AN0557EJ0100 Rev 1 00 Page 1 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 1 Introduction 1 1 Specifications The PCI Express controller PCIEC initialization sample program presented in this application note makes initial settings to the local bus state controller LBSC DDR3 SDRAM interface DBSC3 and PCI Express controller PCIEC after the power on reset is cleared After initialization the PCI Express controller PCIEC operates either as a PCI Express root port or endpoint When operating as a PCI Express root port it displays on the serial console information such as the vendor ID and device ID of PCI Express endpoint devices and executes simple D
41. 587 588 Limitation 589 590 Argument none 591 Return Value 1 Time out O0 Normal 592 Calling Functions 593 PFUNC COMMENT END kk kk kk kk kk kk kk kk k Ck kk AA AA 594 static int pcie trans cont init int sel 595 1 596 unsigned long stime 597 598 printf PCI Express Controller During Initialization 599 600 A set of a bridge facility 601 PCIE REG sel LARO 0x0C000000 A local address 0 is specified 602 PCIE REG sel LAR2 0x0D000000 A local address 1 is specified 603 604 PCIE REG sel LAMRO 0x000FFFO1 Local SHwy space register 0 605 1MB 606 A memory is secured in 32 bit address space 607 Local address enabling is specified 608 PCIE REG sel LAMR2 Ox000FFF11 Local SHwy space register 1 609 1MB 610 A memory is secured in 32 bit address space 611 Local address enabling is specified 612 613 A set of a configuration register 614 if sel 615 PCIE REG sel IDSETR1 0x01234567 616 PCIE REG sel IDSETR2 0x89ABCDEF 617 618 619 PCIE_REG sel PCICONF1 0x00000007 620 621 A wake up of LTSSM A settlement of a connection is started 622 PCIE_REG sel TCTLR 0x00000001 623 R01AN0557EJ0100 Rev 1 00 Page 62 of 84 Jul 15 2011 3 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 624 A connection s settlement waiting 625 stime 10000 626 while
42. 6 147 148 149 150 Limitation SA 152 Argument Data A send data is stored 153 Return Value none 154 Calling Functions 155 PFUNC COMMENT END kk kk kk kk kk kk kk kk k AA AA 156 void scif transmit data char Data 153 4 158 while Data 159 160 while SCIF SCFSR BIT TDFE Weight is carried out until the write of a send data will be in an authorized state 161 SCIF SCFTDR Data A set of a send data 162 Datat 163 while SCIF SCFSR BIT TEND Waiting for the quit of transmitting 164 SCIF SCFSR BI DFE 0 165 SCIF SCFSR BI END 0 166 167 168 R01AN0557EJ0100 Rev 1 00 Page 77 of 84 Jul 15 2011 RENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 169 FUNC COMMENT V X X X kc k kk kk Ck Ck kk KA KA Kk Ck kk Kk Kk Kk KA Kk A KK ck ck ck kk A ck 170 ID 171 Outline Sample Program Main 172 PCIe 173 Include 174 Declaration void scif transmit byte data char Data 175 Description A transmission of the single byte data of SCIF 176 177 178 179 180 181 Limitation 182 183 Argument Data A send data is stored 184 Return Value none 185 Calling Functions 186 PFUNC COMMENT END kk kk kk kk kk kk kk kk k AAA ke o ke e ke e x x 187 void scif transmit data byte char Data
43. 7786 PCI Express Controller PCIEC Initialization Sample Program 15 Flowchart of PCI Express Physical Layer Control Register Write This flowchart shows the processing sequence for writing to the PCI Express physical layer control register Start lt phyreg_write gt v Set physical layer control register PCIEPHYCTLR v Set write data in physical layer data out register PCIEPHYDOUTR Y Write to physical layer address register PCIEPHYADRR Write to physical layer address register PCIEPHYADRR Set physical layer control register PCIEPHYCTLR End Set PHYCKE to 1 to supply clock for accessing physical layer register space Set write data in physical layer data out register PCIEPHYDOUTR Set write command and address in physical layer address register PCIEPHYADRR Determine response form PHY control bus ACK 1 indicates access end Clear physical layer address register PCIEPHYADRR Determine response form PHY control bus ACK 0 indicates idle state Stop clock for accessing physical layer register space by clearing PHYCKE to 0 Figure 4 17 Flowchart of PCI Express Physical Layer Control Register Write RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 Page 43 of 84 ztENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 16 Flowchart of PCI Express Configurat
44. 7EJ0100 Rev 1 00 Jul 15 2011 3 NE SAS Page 63 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 S e a a a a S l a o U O U M UN FE O ao CO VJ o U AM UN IL o if dev id 0x00000000 return 1 Max Payload Size Supported of a splicing place device is acauired config read sel 0 1 0 PCIE CONF CAP PTR amp data j next ptr data amp Oxff cap id Oxff while 1 if cap_id 0x10 PCI Express Capability Structure x config read sel 0 1 0 unsigned long cap ptr 0x04 sdev cap mpssl dev cap amp 0x07 break else other capability list cap ptr next ptr config read sel 0 1 0 unsigned long cap ptr amp data cap id data amp Oxff next ptr data gt gt 8 amp Oxff MPSS of a self device mpss2 PCIE REG sel EXPCAP1 amp 0x07 mps mpssl lt mpss2 mpssl mpss2 Both smallest value is taken Set of MPS Splicing place device config read sel 0 1 0 unsigned long cap ptr 0x08 amp dev ctrl dev ctrl dev ctrl amp OxFFFFFFIF mps lt lt 5 bit7 5 is substituted for MPS config write sel 0 1 0 unsigned long cap ptr 0x08 dev ctrl Set of MPS self device dev ctrl PCIE REG sel EXPCAP2 dev ctrl
45. 82 783 784 785 786 787 788 789 790 791 792 793 794 memcpy return 0 NEUNC COMM amp conf_data PCIE CONF DATA config data sizeof i E NUT UM oko oko CK AAA AAA AAA AAA ck k ok ko kk k ID Outline Sample Program Main x PCI Express Include Declaration static unsigned long pcie_link_lane void Description An obtaining of an effective lan Limitation Argument none Return Value Calling Functions FUNC COMM ENT An obtaining of a link data END V RR AA AA static unsigned long pcie link lane int sel unsigned 1 long data The read of a link status data PCIE REG sel data gt gt 20 data amp Ox3f return data NEUNC COMM EXPCAP4 ENT UM oko o CK Ck Ok Sk Ck kA AAA AA Kk kk k ID Outline Sample Program Main E PCI Express Include Declaration void pcie init int sel Description The initialization of a PCIE controller Limitation Argument none Return Value none Calling Functions PFUNC COMMENT END kk kk kk kk kk kk kk kk k AAA AAA void pcie in it int sel The initializatio RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 n of a PCIE configuration data 34 NE SAS Page 65 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Ini
46. Address char CAP PTR char reserve0 3 long reservel char InttreuptLine char InttreuptPin char Min Gnt char Max Lat PCIE CONF DATA 337 endif PCIE H RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 3 NE SAS Subsystem ID Subsystem Vender ID Expantion ROM base Address Reserve New facility pointer Reserve MAX latency MIN Grant PCI Inttreupt pin Interrupt line Vender ID Device ID Device Control Device Status Revision ID Programming Interface Sub Class Base Class Cach Line Size Master latency timer Header Type BIST Base Address Registers space Card Bus CIS pointer Subsystem Vender ID Subsystem ID Expantion ROM base Address New facility pointer Reserve Reserve Interrupt line PCI Inttreupt pin MIN Grant MAX latency Page 74 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 5 scif c This is a program listing of the SCIFO initial settings and serial driver function REGARDI INCLUDI DISCLAI TO THE ELECTRO FOR ANY FOR ANY O C QC Q O O O C OO O O C c o 10 U M UN FE O o m V o U 4 UN
47. BL IntPRG 0800 PResetPRG 01000 P C C BSEC C DSEC D 02000 RSTHandler PnonCACHE 0A0000000 B R 0ADF00000 S OADFFO0000 nologo For detailed information on using the AP SH4AD 0A refer to AP SH4AD 0A Hardware Manual For detailed information on using the PC USB 02A refer to AP SH4AD 0A Hardware Manual To operate the PCI Express controller PCIEC as a PCI Express root port specify CONFIG PCIE ROOT 0 in the macro definitions To operate the PCI Express controller PCIEC as a PCI Express endpoint specify CONFIG PCIE END 1 in the macro definitions Page 3 of 84 ztENESAS SH7786 Group Table 1 2 lists the section allocations used in the sample program Table 1 2 Section Allocations SH7786 PCI Express Controller PCIEC Initialization Sample Program Section Section Usage Area Allocation Address Virtual Address INTHandler Exception interrupt handler ROM 0x00000800 PO area VECTTBL Reset vector table ROM Can be cached Interrupt vector table MMU address INTTBL Interrupt mask table ROM conversion not IntPRG Interrupt function ROM possible PResetPRG Reset program ROM 0x00001000 P Program area ROM 0x00002000 C Constant area ROM C BSEC Uninitialized data area address structure ROM C DSEC Initialized data area address structure ROM D Initialized data ROM RSTHandler Reset handler ROM 0xA0000000 P2 area PnonCACHE Program area Cache invalid access ROM Can not be cached B Uninitialize
48. E PCIe DemoSample c DATE Wed Nov 17 2010 hu DESCRIPTION Main Program x CPU TYPE Other gt This file is generated by Renesas Project Generator Ver 4 16 R K RK HK IK kk ok kok RR I kk I I I kk kk kk I I I I I k kok k kk kk kk kok ck ck ck ko ke xe include typedefine h include config h include pcie h ifdef cplusplus include ios SINT ios base Init init cnt endif void main void ifdef cplusplus extern C void abort void endif Variable declaration Remove the comment when you use ios Remove the A extern static PCIE CONF DATA conf data define BUFF_MAX 7 define TransByte 64 Function declaration volatile void BuffClear char pBuff und volatile void SdramDataInit int cnt void pfc init void int size comment when you use ios FUNC COMMENT Mx ook kk CK AAA AAA AAA A ID Outline Sample program main Include Declaration void main void Description Main program RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 34 NESAS Page 46 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 ENESAS 054 Limitation 055 056 Argument none 057 Return Value none 058 Ca
49. G sel SRSTR 0x00000000 A clear of a VCO transmitter buffer RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 34 NESAS long data request orbidden Page 60 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 3 NE SAS 510 PCIE REG sel TXVCOSR 0x80000000 511 512 533 jx FUNC COMMENT Ml ck Ck ck ck 0k ck 0k RR RR A 514 ID 515 Outline Sample Program Main LG PCI Express 517 Include 518 Declaration static int pcie phy init int sel 519 Description The initialization of a PCIE controller transfer control register DZ k bal b22 523 524 525 Limitation 526 527 Argument none 528 Return Value 1 Time out O0 Normal 529 Calling Functions 530 PFUNC COMMENT END V V RR ke ke kk ke ke e ke 531 static int pcie phy init int sel 532 533 unsigned long stime 534 static unsigned long data 535 536 printf PCI Express PHY During Initialization 537 A clock supply of a physical layer register space accessing 538 PCIE REG sel PHYCTLR 0x00000001 539 540 A physical layer s initialization BAT phyreg write sel 0x60 Oxf 0x004B008B 542 phyreg write sel 0x61 Oxf 0x00007B41 543 phyreg write sel 0x64 Oxf 0x00FF4F00 544
50. H7786 High performance Embedded Workshop Version 4 07 00 007 C C Compiler Package for SuperH Family V 9 3 2 0 None H W Platform SH 4A Board P N AP SH4AD 3A Manufacturer ALPHA PROJECT It is an example program of the example of a SH7786 PCI Express set 044 KKK KKK KKK KK KK AAA KK KK 01 Sep 2010 Ver 1 00 First Release E 053 FUNC COMM 046 FILE COMMENT END V MALA AAA AAA pcie h 051 static PCIE CONF DATA conf data ENT oko ok CK Ck ee kA kA XXX KX KA KA X XX KA Kk kk k RO1AN0557EJ0100 Rev 1 00 Page 52 of 84 Jul 15 2011 32 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 054 ID 055 Outline Sample Program Main 056 PCI Express 057 Include 058 Declaration void pcie_enable_mem_transfer int sel 059 Description Memory transfer significance 060 061 062 063 064 065 Limitation 066 067 Argument none 068 Return Value none 069 Calling Functions 070 x FUNC COMMENT END Ik A A A RR RA A k k k k k k k k ck k k k k ke ke e 071 void pcie_enable_mem_transfer int sel 072 073 A set of a register A set of a window 074 PCIE_REG sel PAHRO 0x00000000 32bit of a upper address 075 PCIE_REG sel PALRO PCIE_AREA_ADDR 32 bits of a lower address 076 PCIE_REG s
51. I Express memory transfer write Start lt pcie mem write gt Enable memory transfer lt pcie enable mem transfer gt Enable PCI Express memory transfer Y Write data to PCI Express memory area Write data to PCI Express memory area PCI area address 0 End Figure 4 11 Flowchart of PCI Express Memory Transfer Write RO1AN0557EJ0100 Rev 1 00 Page 39 of 84 Jul 15 2011 ztENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 10 Flowchart of PCI Express Memory Transfer Read This flowchart shows the processing sequence for performing a PCI Express memory transfer read Start pcie mem read gt Y Enable memory transfer pcie enable mem transfer gt Enable PCI Express memory transfer Y Read data from PCI Express memory area Read data from PCI Express memory area PCI area address 0 End Figure 4 12 Flowchart of PCI Express Memory Transfer Read 11 Flowchart of PCI Express Memory Transfer Enable Settings This flowchart shows the processing sequence for making PCI Express memory transfer enable settings Start lt pcie enable mem transfer gt Y Set PCI address upper register 0 Set PCI address upper register 0 PCIEPAHRO to 0x00000000 PCIEPAHRO 32 bit space v Set PCI address lower register 0 Set PCI
52. KK AKA kk k AA KA kA kA k k kk ck 216 ID 217 Outline Sample Program Main 218 PCI Express 219 Include 220 Declaration void pcie enable io transfer int sel 221 Description An I O transmission is validated 222 223 224 Page 55 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 225 226 227 Limitation 228 229 Argument none 230 Return Value none 231 Calling Functions 232 PFUNC COMMENT END kk kk kk kk kk kk kk kk kk k k k AA AA 233 void pcie enable io transfer int sel 234 1 235 A set of a register A set of a window 236 PCIE_REG sel PAHR3 0x00000000 32 bits of a upper address 237 PCIE REG sel PALR3 PCIE AREA IO ADDR 32 bits of a lower address 238 PCIE REG sel PAMR3 0x000C0000 A window size is specified 1M 239 PCIE REG sel PTCTLR3 0x80000100 A transmitting packet property is specified 240 241 2012 FUNC COMMENT X XX kk kk Ck Ck kk kk kk Kk X KA KA Kk Kk A Kk X AA ke kc kk A ck kk kk kk ck 243 ID 244 Outline Sample Program Main 245 PCI Express 246 Include 247 Declaration long pcie io write unsigned long addr unsigned long data unsigned long size 248 Description It writes in an I O field 249 250 253 252 253 254 Limitation
53. Little endian MD8 high Addressing mode 29 bit addressing mode MD10 low Area 0 bus width 16 bits MD4 low MD5 High MD6 low Memory NOR flash memory 16 MB area 0 Spansion S29GL128P90TFIRI DDR3 SDRAM 256 MB areas 2 to 5 Micron MT41J64M16LA 187E 2 chips PCI Express Serial interface SH7786 on chip PCI Express controller PCIEC Support for PCI Express Base Specification revision 1 1 PCI Express Generation 1 Bus frequency 2 5 GHz Root port PCI Express x4 card slot 1 channel Endpoint PCI Express x1 card edge 1 channel SH7786 on chip SCIF channel 0 115 200 bps PC USB 02A Alpha Project Serial console TTL serial USB converter Super H RISC engine Standard Toolchain Version 9 3 2 0 Compiler options cpu sh4a endian little include PROJDIR inc PROJDIR inc drv define CONFIG_PCIE_ROOT 0 object CONFIGDIR FILELEAF obj debug gbr auto chgincpath errorpath global volatile 0 opt range all infinite_loop 0 del vacant loop 0 struct alloc 1 nologo Assembler options cpu sh4a endian little round zero denormalize off include PROJDIR inc debug object CONFIGDIR FILELEAF obj literal pool branch jump return nolist nologo chgincpath errorpath Linker options RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 noprelink rom D R nomessage list CONFIGDIR PROJECTNAME map optimize safe start INTHandler VECTTBL INTT
54. M BASE 0x30 define PCIE CONF CAP PTR 0x34 define PCIE CONF MAX LAT 0x3C define PCIE CONF MIN GNT 0x3C define PCIE CONF INTERRUPT PIN 0x3C define PCIE CONF INTERRUPT LINE 0x3C Register accessing define PCIE_WRITEL addr data volatile unsigned long addr unsigned long data define PCIE_READL addr volatile unsigned long addr define PCIE_WRITEW addr data volatile unsigned short addr unsigned short data define PCIE READW addr volatile unsigned short addr define PCIE_WRITEB addr data volatile unsigned char addr unsigned char data define PCIE READB addr volatile unsigned char addr A configuration space register s structure YF Header Type 0 typedef struct PCIE CONF DATA if defined BIG unsigned short DeviceID Device ID unsigned short VenderID Vender ID unsigned short Status Device Status unsigned short Command Device Control unsigned char BaseClass Base Class unsigned char SubClass Sub Class unsigned char ProgrammingInterface Programming Interface unsigned char RevisionID Revision ID unsigned char BIST BIST unsigned char HeaderType Header Type unsigned char LatencyTimer Master latency timer unsigned char CachLineSize Cach Line Size unsigned long BaseAddressRegisters 6 Base Address Registers space unsigned long CardbusCISpointe
55. MA transfers When operating as a PCI Express endpoint it specifies setting items such as vendor ID and device ID in the PCI Express controller PCIEC 1 2 Functions Used e Local bus state controller LBSC e DDR3 SDRAM interface DBSC3 e PCI Express controller PCIEC e Serial communication interface SCIFO Initial settings for the local bus state controller LBSC and DDR3 SDRAM interface DBSC3 are described in SH7786 Group Application Note SH7786 Initial Settings Sample Program ROL ANO519EJ0101 Refer to that document in conjunction with this application note Note that descriptions of the initial settings to the local bus state controller LBSC and DDR3 SDRAM interface DBSC3 are omitted from this application note as the relevant operations are verified in SH7786 Group Application Note SH7786 Initial Settings Sample Program RO1AN0519EJ0101 RO1AN0557EJ0100 Rev 1 00 Page 2 of 84 Jul 15 2011 34 NE SAS SH7786 Group 1 3 Applicable Conditions Table 1 1 Applicable Conditions SH7786 PCI Express Controller PCIEC Initialization Sample Program AP AH4AD 0A Alpha Project Evaluation board Toolchain Notes 1 2 3 CPU SH7786 Operating frequencies Internal clock 533 MHz SuperHyway clock 267 MHz Peripheral clock 44 MHz DDR3 clock 533 MHz External bus clock 89 MHz Clock operating mode Clock mode 3 MDO high MD1 high MD2 low MD3 low Endian mode
56. RO RO RO R1 R1 R1 BCNTR1 SBC STR CCA CHC CHS PAL PAH SAL TR1 R1 R1 R1 R1 R2 R2 R2 BCNTR2 SBC STR CCA CHC CHS PAL PAH SAL TR2 R2 R2 R2 R2 R3 R3 R3 BCNTR3 SBC STR CCA TR3 R3 R3 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x21 CO CX CQ O OC O O C CO Oo Oo SC O aS 260 268 280 288 2A0 2A8 400 404 408 40C 420 424 428 42C 440 444 448 44C 460 464 468 3 NE SAS Page 70 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 111 define 112 define 113 define 114 define 115 define 116 define 117 define 118 define 19 define 120 define 121 define 122 define 123 define 124 define 125 define 126 define 127 define 128 define 129 define 130 define 131 define 132 define 133 define 134 define 135 define 136 define 137 define 138 define 139 define 140 define 141 define 42 define 143 define 144 define 45 define 146 define 147 define 48 define 149 define 150 define 151 define 152 define 153 define 154 define 155 define 156 define
57. RY U P Fi a T NOT LIMITED TO WARRANTIES OF MERCHANTABILITY FITNESS FOR A PURPOSE AND NON INFRINGEMENT ALL SUCH WARRANTIES ARE EXPRESSLY UM EXTENT PERMITTED NOT PROHIBITED BY LAW NEITHER RENESAS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE ECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THE THIS SOFTWARE EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Renesas res rves the right without notice to make changes to this software and to discontinue the availability of this software By using this software you agree to the additional terms and conditions found by accessing the following link http www renesas com disclaimer 027 FR kk kok k kk k k kk kk kk A AA AA AA OK 028 Copyright C 2010 Renesas Electronics Corporation All Rights Reserved 029 FILE COMM ENT Technical reference data System Name File Name Abstract Version Device Tool Chain OS Description Operation Limitation History SH7786 Sample Program scif c The example of a set of PCI Express Sample Program Ver 1 00 S
58. SuperHyway space The assignment of addresses in the PCI Express space is dynamically determined by the root port during the configuration cycle based on the register settings at initialization The register settings at initialization specify the size and type memory space or I O space etc of each area to be allocated When initialization is completed by setting CFINIT to 1 the initialization details are reflected in the value of Base Address Register n BARn or the R W attributes in the configuration registers Here n represents the BAR register number n O to 1 for a root port and n 0 to 5 for an endpoint The root port references these settings during subsequent configuration cycles determines the address mapping and sets the result for each device in BARn in the corresponding configuration register The address pointed to by BARn serves as the start address assigned to the individual device in the PCI Express space The PCIEC supports either a 64 bit or a 32 bit PCI address space the first 4G area of the 64 bit space as the area in which memory space is allocated One BARn register is used to allocate an area in a 32 bit address space and two contiguous BARn registers BARn 1 BARn are used to allocate an area in a 64 bit address space For this reason a maximum of one 64 bit address space area can be allocated for a root port and a maximum of three 64 bit address space areas for an endpoint In I O spaces areas are allocated usin
59. ample Program Website and Support Renesas Electronics Website http www renesas com Inquiries http www renesas com inquiry PCIe is a registered trademark of PCI SIG All trademarks and registered trademarks are the property of their respective owners RO1AN0557EJ0100 Rev 1 00 Page 84 of 84 Jul 15 2011 34 NE SAS Revision Record Description Rev Date Page Summary 1 00 Jul 15 11 First edition issued General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of MPU MCU Products and in the body of the manual differ from each other the description in the body of the manual takes precedence 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins
60. ansferred To use stride transfer set a stride interval stride counter in PCIEDMSBCNTRn and a stride width in PCIEDMSTRRn when specifying transfer settings To use stride transfer on the PCI side or SuperHyway side only set the stride width SS or PS field in PCIEDMSTRRn to 0 for the non stride transfer side To start the DMAC set the SARE bit bit 24 or PARE bit bit 25 in PCIEDMCHCRRn to 1 The other settings are the same as those for normal mode transfer 7 Command Chain The command chain function enables the consecutive execution of multiple DMAC commands Here DMAC command refers to a set of information that specifies a PCIEC DMAC transfer that is the information specified in PCIEDMPALRn PCIEDMSALRn PCIEDMBCNTRn PCIEDMSBCNTRn PCIEDMSTRRn PCIEDMCCARn and PCIEDMCHCRRn This information can be set in the PCIE DMAC control registers and also in the memory in the format shown in figure 2 6 The upper 32 bits of the address on the PCI side cannot be specified by a DMAC command The address specified in the PCIEC DMAC control registers is always used The command chain function enables the PCIEC DMAC to read the next DMAC command from memory after execution of a DMAC command to write the DMAC command contents to the PCIEC DMAC control registers and to execute the DMAC command By specifying the next DMAC command in each DMAC command that is read a DMAC command chain can be built and consecutive transfers performed When a c
61. area 0 address in PCI address lower register 0 PCIEPALRO PCIEPALRO to OxXFD000000 32 bit space v Set PCI address mask register 0 Set PCI address mask register O PCIEPAMRO to 0x007C0000 to specify PCIEPAMRO 8 MB window size Set PCI conversion control register 0 PCIEPTCTLRO to 0x80000000 Set PCI conversion control to specify maximum packet size of 4 bytes no lock memory area as register 0 PCIEPTCTLRO nam transfer destination and transmit packet attribute no snoop End Figure 4 13 Flowchart of PCI Express Memory Transfer Enable Settings RO1AN0557EJ0100 Rev 1 00 Page 40 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 12 Flowchart of PCI Express IO Transfer Write This flowchart shows the processing sequence for performing a PCI Express IO transfer write Start lt pcie io write gt v Enable IO transfer pcie enable io transfer gt Enable PCI Express IO transfer v Write data to PCI Express IO space Write data to PCI Express IO space PCI area address 3 End Figure 4 14 Flowchart of PCI Express IO Transfer Write 13 Flowchart of PCI Express IO Transfer Read This flowchart shows the processing sequence for performing a PCI Express IO transfer read Start lt pcie io read gt Enable IO transfer lt pcie enable io t
62. ave any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Because the evaluation of microcomputer software alone is very difficult 434 N SAS SALES OFFICES Renesas Electronics Corporation http www renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2880 Scott Boulevard Santa Clara CA 95050 2554 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario L3Y 9C3 Canada Tel 1 905 898 5441 Fax 1 905 898 3220 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 585 100 Fax 44 1628 585 900 Renesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 49 211 65030 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd 7th Floor Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100083 P R China Tel 86 10 8235 1155 Fax 86 10 8235 7679 Renesas Electronics Shanghai Co Ltd Unit 204 205 AZIA Center No 1233 Lujiazui Ring Rd Pudong District Shanghai 200120 China Tel 86 21 5877 1818 Fax 86 21 6887 7858 7898 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowl
63. d Not Supported o Start Address H 040 MSI H 050 PCI Express H 070 Advanced error reporting Virtual channel O xXx 0 0 H 100 Device serial number H 1B0 PCI Express link complex declaration PCI Express root complex internal link control Power budgeting PCI Express root complex event collector endpoint association Multi function virtual channel Vendor specific RCRB header Legend o Supported by hardware x Not supported by the PCIEC X X X X x x x The PCIEC implements the device serial number capability structure but no serial number is specified by the hardware To use the device serial number capability structure set the serial number by software The device serial number capability structure is not included in the capability list chain in the initial state To use the structure add it to the capability list chain R01AN0557EJ0100 Rev 1 00 Jul 15 2011 34 NE SAS Page 9 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 2 2 Pin Assignments The PCIEC operates as either a root port or an endpoint as defined by the PCI Express standard The operating mode is specified by the mode pins Mode pin settings for the sample program are specified by using the DIP switches on the evaluation board For details of the DIP switches see 4 1 AP SH4AD 0A SH7786 Evaluation Board The PCIEC does not support the legacy endp
64. d 2 establish a connection between the PCI Express bus and the PCIEC 1 Bridge Function Settings to Link PCI Express Bus and SuperHyway Bus Making settings for the bridge function to link the PCI Express bus and the SuperHyway bus involves setting transfer information in the registers listed below For details on the transfer information to be set see 2 6 Target Transfers e PCIELARO to PCIELARS e PCIELAMRO to PCIELAMR5 2 Establishing Connection between PCI Express Bus and PCIEC After specifying the transfer information in the above transfer control registers set the CFINIT bit bit 0 in PCIETCTLR to 1 to indicate the start of connection establishment The values of the above transfer control registers cannot be changed after CFINIT is set to 1 Setting the CFINIT bit bit 0 in PCIETCTLR to 1 starts the initialization of the data link layer to prepare for communication with the connection target PCI Express device When initialization of the data link layer completes the DL_Active state is entered making the system ready for communication by VCO Initialization is completed when the DL Active state is confirmed by any of the following methods Establishment of communication by VCO e DLLACT bit 0 in PCIETSTR is set to 1 e VC NeGotiation PenDing bit 17 in VCCAP6 is set to 1 e A INTDL interrupt indicating DL Active is generated The following settings must be performed in advance in order to generate an INTDL interrupt b
65. d data area RAM OxADFO00000 MMU address R Initialized data area RAM conversion not S Stack area RAM OxADFFO000 Possible RO1AN0557EJ0100 Rev 1 00 Page 4 of 84 Jul 15 2011 RENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 1 4 Descriptions of Terms Used in the Application Note PCI Express PCI Express is a serial transfer interface standard established by PCI SIG that is intended as a replacement for the PCI bus standard It is not compatible with the physical layer of the PCI bus which has a 32 bit parallel interface but it allows continued use of existing software resources because it uses common communication protocols Each of the lanes used by PCI Express to transfer data consists of a differential pair transmit and receive to enable bidirectional communication dual simplex Revision 1 1 of the PCI Express Base Specification commonly referred to as Genl supports a maximum unidirectional transfer rate of 2 5 Gbps per lane and a maximum bidirectional rate of 5 0 Gbps per lane The data bandwidth can be increased by combining multiple lanes using two lanes to double the transfer rate four lanes to quadruple it and so on PCI Express root port A PCI Express root port performs overall control of the PCI Express system Each PCI Express system must have at least one root port When a configuration cycle commences the PCI Express root port controls the PCI Express system overall initializing
66. dress mask register 2 PCIELAMR2 Set local SuperHyway address mask register 2 to OxOOOFFF11 This sets LAMR2 to 1 MB and SPCSEL to secure a 32 bit address space in I O and sets LARE to local address enabled v Set ID setting register 1 PCIEIDSETR1 Set ID setting register 1 PCIEIDSETR1 to 0x01234567 v Set ID setting register 2 PCIEIDSETR2 Y Set PCI configuration register 1 Set PCI configuration register 1 PCIEPCICONF 1 to 0x00000007 PCIEPCICONF1 This enables memory lO requests enables memory space access and i enables IO space access Set transfer control register Set transfer control register PCIETCTLR to 0x00000001 PCIETCTLR This activates LTSSM connection establishment start Set ID setting register 2 PCIEIDSETR2 to Ox89ABCDEF DLLACT 0 Data link layer inactive state DLLACT 1 in transfer status register PCIETSTR DLLACT 1 Console display 2 Console display 2 Display PCle Controller During Initialization Finish End Figure 4 9 Flowchart of PCIEC Initialization RO1AN0557EJ0100 Rev 1 00 Page 37 of 84 Jul 15 2011 ztENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 8 Flowchart of PCI Express Configuration Register Initial Settings This flowchart shows the processing sequence for making PCI Express configuration register initial settings
67. e SuperHyway address space are mapped to either a PCI address space or a PCI I O space The PI O transfer control registers described below specify the space to which the mapping is to be performed or an address in a specific space where the mapping is to be performed Access to a PCI memory space or a PCI I O space can be performed by accessing the space PCI area on the SuperHyway that is mapped to the PCI space A read access to a PCI area generates a read packet for a PCI memory space or PCI I O space and a write access to a PCI area generates a write packet for a PCI memory space or PCI I O space When a PCI memory space is accessed the packet length is determined according to the access size to the PCI area In other words if the PCI area is accessed by 4 byte access read write packets of 4 bytes 1 DW are generated in the PCI memory space Only 4 byte 1 DW access to a PCI I O space is allowed When a PCI area is mapped to a PCI I O space access to the PCI area should be made with an access size of 4 bytes The PIO transfer control registers specify the transfer destination space selection of PCI memory or I O space the start address in each space the size of transfer destination space and the attributes of the transfer packets RO1AN0557EJ0100 Rev 1 00 Page 16 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program SuperHyway address space 32 bits
68. el DMSTRRO 0x00000000 903 PCIE REG sel DMCCARO 0x00000000 No DMAC Command chain Transfer 904 905 PCIE REG sel DMPALRO pciadd 32bit of a lower address for PCI 906 PCIE REG sel DMPAHRO 0x00000000 32bit of a upper address for PCI 907 908 PCIE REG sel DMSALRO shadd 32bit of a address for SuperHyway RO1AN0557EJ0100 Rev 1 00 Page 67 of 84 Jul 15 2011 RENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 909 910 PCIE_REG sel DMBCNTRO cnt Transfer Count 911 912 DMA Transfer Raedy settlement waiting 913 stime 10000 914 while stime 915 Channel Status PE amp SE amp TE 0 916 status PCIE REG sel DMCHSRO 917 if status amp PE PE 918 status amp SE SE 919 status amp TE TE 920 break 921 922 delay 1000 923 924 if stime 925 return 1 926 927 PCIE_REG sel DMCHCRO CHE DIR dir Transfer Start Direction 928 929 while PCIE REG sel DMCHSRO amp TE TE Transfer End Wait 930 PCIE REG sel DMCHCRO amp CHE Transfer Disable 931 PCIE REG sel DMCHSRO TE 932 933 R01AN0557EJ0100 Rev 1 00 Page 68 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization
69. el PAMRO 0x007C0000 A window size is specified 8M 077 PCIE REG sel PTCTLRO 0x80000000 A transmitting packet property is specified 078 079 080 fx FUNC COMMENT x AAA AAA AAA KK 081 ID 082 Outline Sample Program Main 083 PCI Express 084 Include 085 Declaration long pcie_mem write int sel unsigned long addr unsigned long data unsigned long size 086 Description It writes in a memory space 087 088 089 090 091 092 Limitation 093 094 Argument none 095 Return Value l size error 0 Normal 096 Calling Functions 097 PFUNC COMMENT END V V RR AA AA 098 long pcie mem write int sel unsigned long addr unsigned long data unsigned long size 099 LOO unsigned long pcie_addr 101 102 Memory transfer significance 103 pcie enable mem transfer sel 104 105 The write to a memory space 106 pcie addr PCIE AREA ADDR addr 107 switch size 108 case 1 109 PCIE WRITEB pcie addr data 110 break R01AN0557EJ0100 Rev 1 00 Page 53 of 84 Jul 15 2011 ENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program L11 case 2 112 PCIE WRITEW pcie addr data 113 break 114 case 4 EES PCIE_WRITEL pcie_addr data
70. emVenderID 04xWNnNr conf data SubsystemVenderID 864 Scif printf SubsystemID 04x n r conf data SubsystemID 865 Scif printf ExpantionROMbaseAddress 08x n r conf data ExpantionROMbaseAddress 866 scif printf CAP PTR 02xNXnNr conf data CAP PTR 867 scif_printf Int Line 02xNnNr conf data InttreuptLine 868 scif_printf Int Pin 02x n r conf data InttreuptPin 869 scif printf Min Gnt 02x n r conf data Min Gnt 870 Scif printf Max Lat 02xNnNr conf data Max Lat 871 else 872 no device 873 Scif printf Device not detected on PCI Bus r n 874 875 876 877 FUNC COMMENT X X X kk kk kk kk kk KA KA X KA kk Kk Kk Ck KA KA Kk k AA kA kA kA ck ck AH A 878 ID 879 Outline Sample Program Main 880 PCI Express 881 Include 882 Declaration int pcie start dma int sel int pciadd int shadd int dir int cnt 883 Description PCIEC DMAC Setting and start 884 885 886 887 888 889 Limitation 890 891 Argument none 892 Return Value none 893 Calling Functions 894 FUNC COMMENT END Y X Xo ok kk kk k KK eK KK CK KK kk ke kk kk ko kk Kok ko kk IA AO IK I ke 895 int pcie start dma int sel int pciadd int shadd int dir int cnt 896 897 int stime status 898 DMA Nomal Transfer 899 PCIE REG sel DMAOR DMAE DMAC Enable 900 901 PCIE REG sel DMSBCNTRO 0x00000000 No Stride Transfer 902 PCIE REG s
71. en an error occurs 3 DMAC Transfer Requests The PCIEC DMAC supports auto request mode The PCIEC DMAC is activated by writing to its registers by the CPU or other unit RO1AN0557EJ0100 Rev 1 00 Page 23 of 84 Jul 15 2011 ztENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 4 Channel Priority When receiving simultaneous transfer requests with respect to multiple channels the PCIEC DMAC performs transfers according to the specified priority The priority of channels can be selected from two modes fixed and round robin The mode is selected by the ABT bit in the PCIEDMAOR register To improve transfer efficiency the PCIEC DMAC uses the largest possible PCI Express packets for transfer Once transmission or reception processing starts it is not interrupted until transfer processing for the packet is completed For this reason even if a transfer request with a higher priority becomes executable no channel switching occurs until the current packet transmission at that stage completes Channel switching cannot occur until a transfer of up to 4 KB finishes Channel switching occurs when a data transfer set in the active channel completes Here transfer set completion means the point in time when the transfers for both the SuperHyway bus and PCI Express have completed a Fixed Mode In fixed mode the channel priority does not change The priority is fixed as follows CHO gt CHI gt CH2 g
72. fig read gt register Set command register PCI Express configuration register to 0x00000007 Figure 4 10 Flowchart of PCI Express Configuration Register Initial Settings 1 RO1AN0557EJ0100 Rev 1 00 Page 38 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program Determine address space from value obtained from base address register 64 bit space 0 PCI Express configuration register Device Address Type 32 bit space Write to configuration register A Write to configuration register B lt config write gt lt config write gt Read configuration register Obtain values of all external device configuration registers lt config_read gt Y memcpy Store values in all external device configuration registers A Set PCI area address 0 to OxFD000000 base address register O PCI End Express configuration register and PCI area address 2 to OxFE100000 in base address register 2 B Set PCI area address 0 to OxFD000000 base address register O PCI Express configuration register and PCI area address 1 to 0x00000000 in base address register 1 Figure 4 10 Flowchart of PCI Express Configuration Register Initial Settings 2 9 Flowchart of PCI Express Memory Transfer Write This flowchart shows the processing sequence for performing a PC
73. g one BAR register Accesses to BARn by the PCI Express are received by the PCIEC which converts them into accesses to the SuperHyway bus The conversion destination address is specified by PCIELARn RO1AN0557EJ0100 Rev 1 00 Page 20 of 84 Jul 15 2011 ztENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program PCIEC memory space 64 bits SuperHyway space 32 bits H 0000_0000_0000_0000 PCIEC area 0 H 0000 0000 BARO memory 32 bits PCIELARO Local area 0 BAR1 PCIEC area 1 memory 32 bits PCIELAR1 H 0000 0000 FFFF FFFF n PCIELAR3 PCIEC area 3 Local area 3 PCIELARA is not used memory 64 bits Local area 2 PCIELAR2 H FFFF_FFFF_FFFF_FFFF H FFFF_FFFF PCIEC I O space 64 bits BAR2 PCIEC area 2 I O Figure 2 3 Mapping of PCI Spaces to SuperHyway Space 3 Register Settings for Target Transfers Table 2 7 lists the transfer control registers for target transfers These registers control access to areas allocated in the PCI spaces and access to the internal bus from the allocated areas The PCIEC has six sets of target transfer registers The PCIEC can allocate a maximum of two PCI areas in a PCI space when used as a root port and a maximum of six PCI areas in a PCI space when used as an endpoint The PCIEC supports allocation of 64 bit or 32 bit spaces as memory space that can be allocated in
74. ge 34 of 84 Jul 15 2011 ztENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 4 Flowchart of PCI Express Bus Initial Settings This flowchart shows the processing sequence for making PCI Express bus initial settings Start lt pcie init gt v memset Initialize PCIEC configuration data v PCIEC software reset lt pcie soft reset gt Y Initialize PCI Express physical layer Initialize PCI Express physical layer lt pcie phy init gt Y Initialize PCI Express lt pcie trans cont init gt Y Initialize PCI Express configuration Make PCI Express configuration settings lt pcie config init gt Perform PCIEC software reset Initialize PCI Express start connection End Figure 4 6 Flowchart of PCI Express Bus Initial Settings 5 Flowchart of PCIEC Software Reset This flowchart shows the processing sequence for performing a PCIEC software reset Start lt pcie soft reset gt v Set software reset control register PCIESRSTR Execute software reset Set SRST to 1 v Set transfer control register PCIETCTLR Initialize PCIEC internal registers Clear CFINIT to 0 v Set software reset control register PCIESRSTR Y Set transmit VCO status register PCIETXVCOSR Cancel software reset Clear SRST to 0 Clear VCO transmit b
75. gisters of all the PCI Express devices both root ports and endpoints c PCI Address Space Setting BAR Setting Allocate PCI address space for each device Allocate address space according to the PCI Express standard then set the BAR for each device to match d Operating Mode Setting Set values in the configuration registers listed below to define the PCI Express operating mode No setting needs to be made if the initial value is used Do not change the values of these registers after the configuration cycle completes For a detailed description of each register see 13 4 5 Configuration Registers in SH7786 Group User s Manual Hardware PCICONFI 10 Interrupt Disable PCICONF1 8 SERR Enable PCICONFI 6 Parity Error Response PCICONF15 17 SERR Enable root port only PCICONF15 15 8 Interrupt Pin endpoint only PCICONF15 7 0 Interrupt Line root port only EXPCAP2 11 Enable No Snoop EXPCAP2 4 Enable Relaxed Ordering EXPCAP2 3 Unsupported Request Reporting Enable EXPCAP2 2 Fatal Error Reporting Enable l EXPCAP2 2 Non Fatal Error Reporting Enable EXPCAP2 2 Correctable Error Reporting Enable EXPCAP3 20 Data Link Layer Active Reporting Capable root port only EXPCAP7 4 CRS Software Visibility Enable EXPCAP7 3 PME Interrupt Enable EXPCAP7 2 System Error on Fatal Error Enable EXPCAP7 1 System Error on Non Fatal Error Enable 0 EXPCAP7 0 System Error on Correctable Error Enable e INTx MSI Interr
76. h of the received packet is 32 or 64 bits If the address width is 32 bits the address in the received packed is compared with BARn to determine the matching n value Then the corresponding PCIELARn and PCIELAMRn are used to convert the address into a SuperHyway bus address If the address width of the received packet is 64 bits the 64 bit address in the received packet is compared the 64 bit address obtained by combining BARn 1 and BARn to determine the matching n value Then the corresponding PCIELARn and PCIELAMRn are used to convert the address into a SuperHyway bus address The registers PCIELARn 1 and PCIELAMRn 1 are not used in this process The lower bits bits 17 to 0 of the SuperHyway bus address after conversion are generated from the lower bits of the received PCI packet For the middle bits bits 28 to 18 the corresponding bits of the received packet address or PCIELARn are used according to the PCIELAMRn bit values For the upper bits bits 31 to 29 bits 31 to 29 in PCIELARn are used without modification BARn Bits 31 to n are compared according to PCIEIAMRn n 28 to 18 Comparison 0 PCI address ZA 32 bits a 32 bit address comparison BARn 1 BARn BAR 63 3231 0 64 bits Bits 31 to n are compared according to C A PCIEIAMRn n 28 to 18 ompar
77. h transfer capacity of the PCI Express Note Max Payload Size defines the maximum length of the packet data issued to the PCI Express The PCIEC DMAC supports stride transfers for the transfer of data from non contiguous areas and command chains as a function for executing multiple transfer commands The stride transfer function enables transfers in which non contiguous areas serve as the transfer source or destination by adding an offset to the transfer source or destination address after performing a fixed number of transfers The command chain function treats a set of DMAC settings such as transfer source and destination addresses and transfer sizes as a command By providing a function that sequentially reads and executes commands that are stored in memory the PCIEC DMAC supports the continuous execution of multiple transfers without CPU intervention 2 Features e Number of channels 4 e Address space PCI Express 64 bits SuperHyway bus 32 bits e Transfer data length PCI Express 4 bytes to 1 KB SuperHyway bus 4 to 32 bytes e Maximum transfer count 536 870 912 2 e Addressing mode Dual mode e Transfer requests Auto request started by register control e Data transfer Normal mode continuous transfer stride transfer command chain e Priority Selectable between channel priority fixed mode and round robin mode e Interrupt requests Interrupt requests can be issued to the INTC when a data transfer completes or wh
78. he bus number device number function number and extension register number of the access destination when a configuration cycle is generated Write configuration data to PI O data register PCIEPDR Clear CCIE to 0 in PI O control register PCIEPCTLR to disable issuing of configuration requests Figure 4 19 Flowchart of PCI Express Configuration Register Write RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 Page 44 of 84 ztENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 18 Flowchart of PCIEC DMA Transfer This flowchart shows the processing sequence for performing a PCIEC internal DMAC transfer Start lt pcie_start_dma gt Y Set PCI DMAC DMA operation register PCIEDMAOR Y Set PCI DMAC stride count register 0 PCIEDMSBCNTRO Y Set PCI DMAC stride register 0 PCIEDMSTRRO Y Set PCI DMAC command chain address register 0 Set PCI DMAC command chain address register O to 0x00000000 PCIEDMCCARO Set DMA enable bit DMAE to 1 in PCI DMAC DMA operation register Set PCI DMAC stride count register O to 0x00000000 Set PCI DMAC stride register O to 0x00000000 y Set PCI DMAC PCI address lower register 0 PCIEDMPALRO Set PCI DMAC PCI address lower register O to OxFD000000 y Set PCI DMAC PCI address upper register 0 PCIEDMPAHRO Set PCI DMAC PCI address upper register 0 to 0xx0000000 y Set
79. ibutes settings must be made to PCIEPTCTLRn before accessing the PCI area RO1AN0557EJ0100 Rev 1 00 Page 18 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 5 Address Conversion from SuperHyway Bus to PCI The address used when accessing a PCI space by means of accessing a PCI area is determined by the address of the PCI area accessed and by the settings of the associated transfer control register The address conversion details are described below and illustrated in figure 2 2 Address Conversion to PCI Space In the figure and description below the number n represents a value of 0 to 3 which corresponds to a PCI areas from 0 to 3 The lower 16 bits of the PCI address bits 17 to 2 are generated from the lower bits of the SuperHyway address The middle 11 bits of the PCI address bits 28 to 18 are selected from the corresponding bits of the SuperHyway address or PCIEPALRn depending on the value of the transfer control register PCIEPAMRn The SuperHyway address is used if the value of the corresponding bit in PCIEPAMRn is 1 and PCIEPALRn is used if it is 0 The contents of PCIEPAHRn and the upper 3 bits of PCIEPALRn are used as the upper 35 bits bits 63 to 29 of the PCI address 63 3231 29 28 18 17 0 PCI address A Z A A 31 0 PCIEPAHRn 31 29 28
80. ill not be used clear PCIEDMCCARn to 0 c Activating the DMAC In PCIEDMCHCRn specify the direction of transfer and at the same time initiate the transfer process by enabling the channel If the stride transfer function will not be used clear the SARE bit bit 24 and PARE bit bit 25 in PCIEDMCHCRn to 0 If the command chain function will not be used clear the CCRE bit bit 29 in PCIEDMCHCRRn to 0 d Waiting for Transfer End The end of the transfer can be determined by confirming that the TE bit bit 0 in PCIEDMCHSRn is set to 1 or by detecting a transfer end interrupt RO1AN0557EJ0100 Rev 1 00 Page 24 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program e End Processing Complete the transfer by clearing the CHE bit in bit 31 in PCIEDMCHCRn to 0 Also write 1 to the TE bit bit 0 in PCIEDMCHSRn to clear it to 0 The next DMA transfer cannot be started unless end processing is performed 6 Stride Transfer In a stride transfer a procedure called striding is used in which an offset is added to the source or destination address after the transfer of a specific number of bytes By applying striding to the destination address scatter transfer can be performed Similarly by applying striding to the source address gather transfer can be performed By applying striding to both the source and destination addresses non contiguous regions can be tr
81. ion Register Read This flowchart shows the processing sequence for reading the PCI Express configuration register Start lt config read gt Y Set PI O control register PCIEPCTLR Y Set PI O address register PCIEPAR Y Read PI O data register PCIEPDR Y Set PI O control register PCIEPCTLR End Set CCIE to 1 in PI O control register PCIEPCTLR to enable issuing of configuration requests In the PI O address register PCIEPAR set the bus number device number function number and extension register number of the access destination when a configuration cycle is generated Read configuration data from PI O data register PCIEPDR Clear CCIE to O in PI O control register PCIEPCTLR to disable issuing of configuration requests Figure 4 18 Flowchart of PCI Express Configuration Register Read 17 Flowchart of PCI Express Configuration Register Write This flowchart shows the processing sequence for writing to the PCI Express configuration register Start config write gt Y Set PI O control register PCIEPCTLR Y Set PI O address register PCIEPAR Y Write to PI O data register PCIEPDR y Set PI O control register PCIEPCTLR End Set CCIE to 1 in PI O control register PCIEPCTLR to enable issuing of configuration requests In the PI O address register PCIEPAR set t
82. ison PCI address 64 bits b 64 bit address comparison Figure 2 4 PCI Space Address Decoding 312928 18 17 o SuperHyway address SN FZ A 31 2928 18 17 o PCIEPALRn Y N 312928 18 47 0 Selected for each bit according PCI address V to the corresponding bit in lower 32 bits LLL PCIELAMRn 312928 18 17 o PCIELAMRn Figure 2 5 Conversion from PCI Address to SuperHyway Address RO1AN0557EJ0100 Rev 1 00 Page 22 of 84 Jul 15 2011 3 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 5 Accessing the SuperHyway Bus from the PCI Express The internal bus spaces that can be accessed by the PCI Express via the PCIEC are CS2 CS3 the DBSC space and other PCIEC modules Here the other PCIEC modules that can be specified as transfer destinations are PCIEC1 and PCIEC2 when access is made from PCIECO PCIECO and PCIEC2 when access is made from PCIEC1 and PCIECO and PCIEC1 when access is made from PCIEC2 2 7 DMA Transfer DMA transfer using the DMAC incorporated in the PCIEC PCIEC DMAC is described below 1 Overview The PCIEC DMAC enables efficient data transfer between the PCI Express and other modules or external memory devices that are connected via the SuperHyway bus The PCIEC DMAC is designed so that it can issue packets with a maximum data length of 1 024 bytes to the PCI Express making possible high speed data transfers that fully exploit the hig
83. lling Functions 059 PFUNC COMMENT END V V RR kk ke ke e x 060 void main void 061 062 volatile static int ret 0 063 int i j 064 char KeyBuff BUFF MAX 065 unsigned long data 066 int startadd 067 068 pfc init 069 ret scif init 070 071 ifdef CONFIG PCIE ROOT 072 if ret 073 printf Xn r SH7786 PCI Express DEMO Sample ROOT Port NnNr 074 BuffClear KeyBuff BUFF MAX Buffer clear 075 printf Target Device Check Y N n r 076 while scif recive data KeyBuff 0 077 switch KeyBuff 0 078 case Y 079 pcie init CONFIG PCIE ROOT 080 pcie check CONFIG PCIE ROOT 081 break 082 case N 083 printf Not Check Device n r 084 break 085 default 086 break 087 088 delay 1000 089 BuffClear KeyBuff BUFF MAX Buffer clear 090 printf Transmit Data Start Y N n r 091 while scif recive data KeyBuff 0 092 switch KeyBuff 0 093 case Y 094 printf Transmit Start n r 095 for i 0 i lt 4 i 096 pcie io write CONFIG PCIE ROOT i 4 i 1 Long 097 data pcie io read CONFIG PCIE ROOT i 4 Long 098 printf Addr 08x Data 08x n r OxFE100000 i 4 data 099 pcie mem write CONFIG PCIE ROOT i 4 i 2 Long LOO data pcie_mem_read CONFIG_PCIE_ROOT i 4 Long 101 printf Addr 08x Data 08x n r OxFD000000 i 4 data 102 103 DMA Transfer Test 104 SdramDataInit TransByte 64B
84. lock synchronous serial communication Note that SCIFO is used as an asynchronous serial console by the sample program For a detailed description of SCIFO see section 24 Serial Communication Interface with FIFO SCIF in SH7786 Group User s Manual Hardware REJ09B0501 4 Application Example 4 1 AP SHAAD 0A SH7786 Evaluation Board The sample program presented in this application note uses two AP SHAAD 0A SH7786 evaluation boards manufactured by Alpha Project and operates the PCIEC on one of them as a PCI Express root port and the other as a PCI Express endpoint For details of the AP SH4AD 0A see AP SH4AD 0A Hardware Manual 4 1 1 Memory Map Table 4 1 shows a memory map of the AP SHAAD 0A Table 4 1 AP SHAAD 0A Memory Map Area Address Connected Device Bus Width 0 H 0000 0000 to S29GL128P90TFIR20 16 MB 16 bits H OOFF FFFF H 0100 0000 to Shadow H O3FF FFFF 1 H 0400 0000 to LAN9221 512 B 16 bits H 0400 OFFF H 0400 1000 to Shadow H O7FF FFFF 2 H 0800 0000 to MT41J64M16LA 187E 256 MB 32 bits H OBFF FFFF 3 H 0COO 0000 to H OFFF FFFF 4 H 1000 0000 to H 13FF_FFFF 5 H 1400 0000 to H 17FF_FFFF 6 H 1800 0000 to Left open by user 32 bits H 1BFF FFFF R01AN0557EJ0100 Rev 1 00 Page 27 of 84 Jul 15 2011 ENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 4 1 2 Settings for PCI Express Root Port Mode To set the AP SH4AD 0A to operate in PCI Express root port mode set
85. mory base PCICONF8 15 0 x Memory limit PCICONF8 31 16 x Base address register 5 PCICONF9 31 0 o Prefetchable memory base PCICONF9 15 0 x Prefetchable memory limit PCICONF9 31 16 x Card bus CIS pointer PCICONF10 31 0 x Prefetchable base upper 32 bits PCICONF10 31 0 x Subsystem ID register PCICONF 11 31 0 o Prefetchable limit upper 32 bits PCICONF 11 31 0 x Subsystem vendor ID register PCICONF 12 31 0 o I O base register upper 16 bits PCICONF 12 15 0 x I O limit register lower 16 bits PCICONF12 31 16 x Capability pointer PCICONF13 31 0 o o Expansion ROM base address register PCICONF14 31 16 x Interrupt line PCICONF15 7 0 o o Interrupt pin PCICONF15 15 8 o Minimum grant PCICONF15 23 16 Maximum latency PCICONF 15 31 24 Bridge control register PCICONF15 31 16 o Legend o Supported by the PCIEC Use by PCI Express prohibited by the standard x Not supported by the PCIEC RO1AN0557EJ0100 Rev 1 00 Page 8 of 84 Jul 15 2011 RENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 4 Capability Structures Table 2 4 lists the supported PCI Express capability structures The PCIEC supports the capability structures listed Note that the sample program does not support PCI Express capability structures Table 2 4 Supported PCI Express Capability Structures Capability Structure PCI power management Supporte
86. ng as a result of your noncompliance with applicable laws and regulations Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life 8 You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising ou
87. nsfer test data 64 bytes into SDRAM Console display 7 Display DMA Start WRITE SuperHyway gt PCI Perform DMA transfer of 64 bytes of test data from SDRAM to memory space of target device Console display 8 Display Transfer Data transfer source SDRAM address and 64 bytes of test data Console display 9 Display READ PCI gt SuperHyway Perform DMA transfer of 64 bytes of test data from same memory space of target device to SDRAM Console display 10 Display Transfer Data transfer destination SDRAM address and 64 bytes of test data Console display 11 Display PCI Express Demo Sample End Figure 4 2 Flowchart of main PCI Express Root Port 2 RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 Page 32 of 84 3 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program Console display 1 Console display 1 Display SH7786 PCI Express DEMO Sample Endpoint Y PCI Express initial settings lt pcie init gt Make PCIEC endpoint initial settings v Console display 2 Console display 2 Display PCI Express Demo Sample End End Figure 4 3 Flowchart of main PCI Express Endpoint 2 Flowchart of Pin Function Settings This flowchart shows the processing sequence for making pin function settings Start lt pfc init gt Set port H control register PHCR
88. o o o VO read o o o VO write o o o Lock o EE EE Configuration read o o Configuration write o o o Message o o o o Legend o Supported by the PCIEC Use by PCI Express prohibited by the standard Supported by the PCIEC but not supported by the application program RO1AN0557EJ0100 Rev 1 00 Page 6 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 2 Message Transmission Reception Table 2 2 lists the supported PCI Express messages The PCIEC does not support vendor defined messages Note that the sample program does not support message transmission or reception Table 2 2 Supported PCI Express Messages Root Port Endpoint Packet Type Transmission Reception Transmission Reception Assert_INTA m Assert INTB Assert INTC us Assert INTD Deassert INTA Deassert INTB Deassert INTC ololo o olo o o ololo o olo o o Deassert INTD PME Active State Nak PM PME PME Tum Off gt pues pe PME To Ack ERR COR ERR_NONFATAL ojo o D P Ojo fo P ERR_FATAL Unlock Set Slot Power Limit Vender Define TypeO x x 0 0 x X o o Vender Define Type1 Legend o Supported by the PCIEC A Transmission reception possible but control by software is required Use by PCI Express prohibited by the standard x Not sup
89. o store the chain of DMAC commands in a memory location accessible from the SuperHyway bus DDR3 SDRAM LBSC IL memory OL memory or shared memory specified in L2CR and to specify the address of the first command in PCIEDMCCARn Each DMAC command stored in memory must satisfy the conditions listed below The DMAC commands should be located in a shared memory location such as DDR LBSC or LRMA e CHE field This must always be set to 1 e ATTR field Set the ATTR field of the DMAC command in memory to the same value as that specified in the ATTR field in the PCIEC DMAC control register The value of the ATTR field cannot be modified by loading a command e TC field Set the traffic class TC field of the DMAC command in memory to specify the same virtual channel VCO as that specified by the TC field in the PCIEC DMAC control register e RESERVED field This must always be set to 8 e CCA field The value of the CCA field of the final command executed must be 0 8 PCIE DMAC Interrupt Sources The PCIEC DMAC generates an interrupt for each channel at transfer end as well as an interrupt at error termination on a common basis for all channels RO1AN0557EJ0100 Rev 1 00 Page 26 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 3 Serial Communication Interface SCIFO The serial communication interface SCIFO incorporates FIFO buffers and supports both asynchronous and c
90. o the SuperHyway bus address space a PCIEPAR Settings Specify the access destination configuration register number extension register number and access destination device bus device and function numbers in PCIEPAR b PCIEPCTLR Settings Specify the type of configuration access to be initiated and set the access enable bit in PCIEPCTLR c PCIEPDR Settings Generate a configuration read by read accessing PCIEPDR and generate a configuration write by write accessing PCIEPDR Reading PCIEPDR returns the result of the configuration read d Checking PCIEPCTLR Check the CRS bit bit 16 in PCIEPCTLR to verify whether the configuration request retry status CRS has been returned A CRS value of 1 indicates that a correct response to the configuration request has not been made because the connection target device has not been activated If CRS is set to 1 write 1 to CRS to clear it and resume processing from step c above It is not necessary to recheck the CRS bit again once configuration access to a device is successful 2 Receiving Configuration Access When the PCIEC is used as an endpoint it receives configuration accesses from root ports and accepts initialization processing Reception of a configuration access by the PCIEC is handled automatically in hardware and no software control is necessary Software processing is required however when a configuration write access to the PowerState field bits 1 and 0 in
91. oint root complex integrated endpoint switch and root complex invent controller operation modes defined in the PCI Express standard 1 Root Port A root port performs overall control of the PCI Express system Each PCI Express system must have at least one root port The PCIEC can operate as a root port for which the SH processor acts as a host processor When a configuration cycle commences the root port controls the PCI Express system overall initializing the system receiving error messages recovering from errors etc The root port also transmits request packets returns completion packets and transmits and receives messages 2 Endpoint An endpoint is a port that performs data communication under the control of a root port A PCI Express system can have multiple endpoints The PCIEC can operate as an endpoint After an endpoint is initialized in the configuration cycle it performs error detection sends notifications to the root port etc Endpoints also transmit request packets return completion packets and transmit and receive messages RO1AN0557EJ0100 Rev 1 00 Page 10 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 2 3 PCIEC Module Initialization To enable PCI Express packet communication by using the PCIEC it is necessary to 1 make settings for the bridge function to link the PCI Express bus and the internal bus of the SH7786 SuperHyway bus an
92. ommand chain is used the PCIEC DMAC first executes the DMAC command specified in the PCIEC DMAC control registers for each channel After execution of this DMAC command the PCIEC DMAC reads the next DMAC command from the address specified in PCIEDMCCARn writes the command contents to the PCIEC DMAC control registers for the corresponding channel and executes it If the value of the CCRE bit in the newly read DMAC command is 1 the PCIEC DMAC reads the next command again from the memory and executes it after completion of that command If the value of the CCRE bit in the read DMAC command is 0 execution of the series of commands in the chain ends upon completion of that command Offset Coresponding 44 30 29 27 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 44 10 9 8 7 6 5 4 3 2 1 O register CH cc PAS SAS 0 DMCHR E RE RE RE DIR ATTR TC Burst Burst Length 4 RESERVED RESERVED RESERVED 8 DMSALR SADR 12 DMPALR PADR 16 DMCCAR CCA 20 DMBCNTR BCNT 24 DMSTRR SS PS 28 DMSCNTR SBCINI SBCNT Figure 2 6 PCIEC DMAC Command Format RO1AN0557EJ0100 Rev 1 00 Page 25 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program Command chain execution starts when a channel is enabled while the CCRE bit bit 29 in PCIEDMCHCRn is set to 1 Before starting a command chain it is necessary first t
93. onf data Command scif printf Status S04x n r conf data Status E scif_printf Revision ID 02xNnNr conf data RevisionID scif_printf ProgrammingInterface 02x n r conf data ProgrammingInterface Scif printf SubClass 02x n r conf data SubClass Scif printf BaseClass 02x n r conf data BaseClass RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 34 NE SAS Page 66 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 852 scif printf CachLineSize 02x n r conf data CachLineSize 853 Scif printf LatencyTimer 02x n r conf data LatencyTimer 854 scif printf HeaderType 02xWNnNr conf data HeaderType 855 scif printf BIST 02x n r conf data BIST 856 scif_printf BaseAdrsREG 08x n r conf data BaseAddressRegisters 0 857 Scif printf BaseAdrsREG 08x n r conf data BaseAddressRegisters 1 858 scif printf BaseAdrsREG 08x n r conf data BaseAddressRegisters 2 859 scif_printf BaseAdrsREG 08x n r conf data BaseAddressRegisters 3 860 scif_printf BaseAdrsREG 08x n r conf data BaseAddressRegisters 4 861 Scif printf BaseAdrsREG 08x n r conf data BaseAddressRegisters 5 862 scif printf CardbusCISpointer 08xWNnNr conf data CardbusCISpointer 863 scif printf Subsyst
94. ontrol register address OxBO to 0x0000 0610 9 Set physical layer control register address 0x67 to 0x0000 0400 PCIEC Root port CONFIG PCIE ROOT 2 0 Set physical layer control register PCIEPHYCTLR Y Console display 2 End Stop physical layer register space access clock Clear PHYCKE to 0 Console display 2 Display PCle PHY During Initialization Finish Figure 4 8 Flowchart of PCIEC Physical Layer Initialization RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 Page 36 of 84 ztENESAS Read data from physical layer control register address 0x67 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 7 Flowchart of PCIEC Initialization This flowchart shows the processing sequence for PCIEC initialization Start lt pcie trans cont init gt v Console display 1 Console display 1 Display PCle Controller During Initialization v Set local address register 0 PCIELARO Set local SuperHyway address register 0 to 0x0C000000 Y Set local address register 2 PCIELAR2 Y Set local address mask register 0 PCIELAMRO Set local SuperHyway address register 2 to 0x0D000000 Set local SuperHyway address mask register O to OxOOOFFFO01 This sets LAMRO to 1 MB and SPCSEL to secure a 32 bit address space in memory and sets LARE to local address enabled v Set local ad
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96. plays on the serial console information such as the vendor ID and device ID of PCI Express endpoint devices and executes simple DMA transfers When operating as a PCI Express endpoint it specifies setting items such as vendor ID and device ID in the PCI Express controller PCIEC The descriptions in this application note do not cover the following functions of the PCI Express controller PCIEC Message transmission and reception INTx MSI interrupts Link power control function LO LOs L1 and L3 states RO1AN0557EJ0100 Rev 1 00 Page 5 of 84 Jul 15 2011 ztENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 2 PCI Express Controller PCIEC The PCI Express controller PCIEC performs PCI Express control and transfers data between the internal bus SuperHyway bus of the SH7786 and PCI devices connected to the PCI Express interface This section describes the PCIEC functions supported by the sample program For a detailed description of the PCIEC see section 13 PCI Express Controller PCIEC in SH7786 Group User s Manual Hardware REJ09B0501 2 1 Supported Functions 1 Packet Transmission Reception Table 2 1 lists the supported PCI Express packets The PCIEC supports packets that are not prohibited by the standard Table 2 1 Supported PCI Express Packets Root Port Endpoint Packet Type Transmission Reception Transmission Reception Memory read o o o o Memory write o
97. ported by the PCIEC RO1AN0557EJ0100 Rev 1 00 Page 7 of 84 Jul 15 2011 RENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 3 Configuration Registers Table 2 3 lists the supported PCI Express configuration registers The PCIEC does not support registers related to the built in self test BIST function switches and expansion ROM Table 2 3 Supported PCI Express Configuration Registers Configuration Register PCIEC Register Root Port Endpoint Vendor ID register PCICONFO 15 0 o o Device ID register PCICONFO 31 16 o o Command register PCICONF1 15 0 o o Status register PCICONF1 31 16 o o Revision ID register PCICONF2 7 0 o o Class code register PCICONF2 31 8 o o Cache line size PCICONF3 7 0 Master latency timer PCICONF3 15 8 Header type register PCICONF3 23 16 o o BIST register PCICONF3 31 24 x x Base address register O PCICONF4 31 0 o o Base address register 1 PCICONF5 31 0 o o Base address register 2 PCICONF6 31 0 o Primary bus number PCICONF6 7 0 o Secondary bus number PCICONF6 15 8 o Subordinate bus number PCICONF6 23 16 Secondary latency timer PCICONF6 31 24 Base address register 3 PCICONF7 31 0 o I O base register PCICONF7 7 0 x I O limit register PCICONF7 15 8 x Secondary status register PCICONF7 31 16 o Base address register 4 PCICONF8 31 0 o Me
98. produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 5 Differences between Products Before changing from one product to another i e to one with a different type number confirm that the change will not lead to problems The characteristics of MPU MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern When changing to products of different type numbers implement a system evaluation test for each of the products Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or othe
99. r o to HIS SOFTWA PARTICULAR F m RK HK ok ok kok oko kk kk kk kk kk kk kk Ck kk kk kk kk kk kk kk kk kk kk ke kk kk kk Sk kk kk kk ke kc ke kk kk kk kk ke ke kk k e k k DISCLAIMER This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products No other uses are authorized This software is owned by Renesas Electronics Corporation and is protected under all applicable laws including copyright laws IS PROVIDED AS IS AND RENESAS MAKES NO WARRANTII Ei n SOFTWARE WHETHER EXPRESS IMPLIED OR STATUTORY R G THIS G BU P PUR ED AXIMU ICS CO DIRECT T NOT LIMITED TO WARRANTIES OF MERCHANTABILITY FITNESS FOR A POSE AND NON INFRINGEMENT ALL SUCH WARRANTIES ARE EXPRESSLY EXTENT PERMITTED NOT PROHIBITED BY LAW NEITHER RENESAS RPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES REASO RELATED TO THE THIS SOFTWARE EVEN IF RENESAS OR ITS 020 AFFILIATES HAV E BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES 021 029 FILE 033 Version 034 Device 036 037 OS 040
100. r Card Bus CIS pointer RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 34 NE SAS Page 73 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 C CO C0 U CO C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 ww WwW C2 O0 U 0 U M UN FE O a CO VJ o UG A UN r o Ww ko 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned else unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned endif short SubsystemID short SubsystemVenderID long ExpantionROMbaseAddress char reserve0 3 char CAP PTR long reservel har Max Lat har Min Gnt har InttreuptPin har InttreuptLine VenderID DeviceID hort n hort o Command Status hort o short har RevisionID har ProgrammingInterface har SubClass a a a a har BaseClass har CachLineSize har LatencyTimer har HeaderType har BIST long BaseAddressRegisters 6 long CardbusCISpointer short SubsystemVenderID short SubsystemID long ExpantionROMbase
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102. ransfer gt Enable PCI Express IO transfer Y Read data from PCI Express IO space Read data from PCI Express IO space PCI area address 3 End Figure 4 15 Flowchart of PCI Express IO Transfer Read RO1AN0557EJ0100 Rev 1 00 Page 41 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 14 Flowchart of PCI Express IO Transfer Enable Settings This flowchart shows the processing sequence for making PCI Express IO transfer enable settings Start lt pcie enable mem transfer gt v Set PCI address upper register 3 Set PCI address upper register 3 PCIEPAHR3 to 0x00000000 PCIEPAHR3 32 bit space v Set PCI address lower register 3 Set PCI area 0 address in PCI address lower register 3 PCIEPALR3 PCIEPALR3 to OxFE100000 32 bit space Set PCI address mask register 3 Set PCI address mask register 3 PCIEPAMR3 to 0x007C0000 to specify PCIEPAMR3 1 MB window size Set PCI conversion control Set PCI conversion control register 3 PCIEPTCTLR3 to 0x80000100 to specify maximum packet size of 4 bytes no lock IO space as register 3 PCIEPTCTLR3 am transfer destination and transmit packet attribute no snoop End Figure 4 16 Flowchart of PCI Express IO Transfer Enable Settings RO1AN0557EJ0100 Rev 1 00 Page 42 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH
103. ransfer control registers used for PI O transfers Accesses to PCI areas 0 to 3 are mapped to the PCI memory or I O spaces according to these register settings The functions of these registers are listed in table 2 6 Table 2 6 Transfer Control Registers for PI O Transfers PCIEPALRO to Start addresses of the PCI address spaces to which PCI areas 0 to 3 are mapped PCIEPALR3 lower 32 bits PCIEPAHRO to Start addresses of the PCI address spaces to which PCI areas 0 to 3 are mapped PCIEPAHR3 upper 32 bits PCIEPAMRO to Specifies the sizes of data in PCI areas 0 to 3 mapped to the PCI address spaces PCIEPAMR3 PCIEPTCTLRO to Enables disables PCI areas 0 to 3 PCIEPTCTLR3 Specifies the transfer destination space PCI memory space or PCI I O space Specifies attributes Lock EP No Snoop Relax Ordering for conversion PCIEPALRn and PCIEPAHRn n 0 to 3 specify an address in the PCI Express space to which PCI area n is mapped PCIEPAMRn specifies the size of the PCI area It is not possible to specify a size larger than the size of the PCI area as listed in table 2 5 SuperHyway Space Address Map PCIEPTCTLRn specifies whether a given area is enabled or disabled the transfer destination space and the attributes of packets during the transfer process Unless it is specified in PCIEPTCTLRn that PCI area n is enabled default disabled any access to the corresponding PCI area is invalid To perform a lock transfer or specify other attr
104. s are generated by accessing the PCI memory area The mapping between the PCI memory area and the PCI Express address space is described below Table 2 5 SuperHyway Space Address Map Physical Memory Area PCIECO PCIEC1 PCIEC2 Address Size PCI are 0 H FDOO 0000 H FD80 0000 H FC80 0000 PCIECO 1 8 MB to to to PCIEC2 4 MB H FD7F FFFF H FDFF FFFF H FCBF FFFF PCI are 1 Not available Not available Not available 512 MB PCI are 2 H 1000 0000 Not available Not available 64 MB to H 13FF FFFF only for memory space setting 1 2 5 or 6 PCI are 3 H FE10 0000 H FE30 0000 H FCDO 0000 1 MB to to to H FE1F_FFFF H FE3F_FFFF H FCDF_FFFF Control register H FEOO_0000 H FE20_0000 H FCCO 0000 256 kB area 1 to to to H FEO3 FFFF H FE23 FFFF H FCC3 FFFF Configuration H FEO4 0000 H FE24 0000 H FCC4 0000 4 kB register to to to H FEO4 OFFF H FE24 OFFF H FCC4_OFFF Control register H FE04 1000 H FE24 1000 H FCC4_1000 252 kB area 2 to to to H FEO7 FFFF H FE27 FFFF H FCC7 FFFF Notes 1 The above address map is for the 29 bit address mode 2 The sample program uses areas PCIECO and PCIEC1 RO1AN0557EJ0100 Rev 1 00 Jul 15 2011 34 NE SAS Page 15 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 3 Accessing PCI Memory Space and PCI I O Space Figure 2 1 illustrates the mapping of the SuperHyway address space to the PCI address spaces As shown in figure 2 1 accesses to the PCI area in th
105. stime 627 Data Link Layer Active check 628 if PCIE REG sel TSTR 0 629 break 630 631 delay 1000 632 633 if stime 634 return 1 635 printf FinishWMnNr 636 return 0 637 638 639 FUNC COMMENT ook kk CK kk Ck AAA AAA ck ck ck A 640 ID 641 Outline Sample Program Main 642 PCI Express 643 Include 644 Declaration static int pcie config init void 645 Description A set of the configuration of a PCIE controller 646 647 648 649 650 651 Limitation 652 653 Argument none 654 Return Value 1 Inaccurate ID 0 Normal 655 Calling Functions 656 PFUNC COMMENT END V OR AA AA 657 static int pcie config init int sel 658 659 unsigned long config data PCIE MAX CONFREG SIZE 4 660 unsigned long regno 661 unsigned long data 662 unsigned long dev id 663 unsigned long dev cap 664 unsigned long dev ctrl 665 unsigned long dev bar 666 unsigned long dev type 667 unsigned char cap ptr next ptr cap id mpssl mpss2 mps 668 int stime 1000 669 670 A confirm of a vender and product ID 671 while stime 672 config read sel 0 1 0 PCIE CONF DEVICE ID amp data 673 if PCIE REG sel PCTLR amp 0x00010000 674 break 675 delay 1000 676 677 if stime 678 return 1 679 680 dev id data RO1AN055
106. t CH3 b Round Robin Mode In round robin mode when a transfer set has completed in one channel the channel priority changes so that the completed channel has the lowest priority 5 Transfer in Normal Mode In a normal mode transfer data is transferred from a specified source address to a specified destination address Either of the following transfer directions can be selected PCI to SuperHyway bus or SuperHyway bus to PCI The procedure for performing normal mode transfers with the PCIEC DMAC is described below For detailed specifications of the individual registers see 13 4 4 PCIEC DMAC Control Registers in H7786 Group User s Manual Hardware REJO9B0501 a General PCIEC DMAC Settings Make settings in the PCIEDMAOR register to enable DMA and select the arbitration type b Transfer Settings Specify the PCI and SuperHyway addresses and byte count and the transfer termination interrupt Specify the source and destination addresses in the registers PCIEDMPALRn and PCIEDMPAHRn PCIEDMSALRn and PCIEDMBCNTRn where n denotes the channel number 0 to 3 Regardless of the direction of transfer specify the PCI address in PCIEDMPALRn and PCIEDMPAHRn and the SuperHyway bus address in PCIEDMSALRn To generate an interrupt when a transfer is completed specify an interrupt setting in the PCIEDMCHSRn register If the stride transfer function will not be used clear PCIEDMSBCNTRn and PCIEDMSTRRn to 0 If the command chain function w
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108. tialization Sample Program 795 796 797 798 799 oo gt o OO CO CO CO CO CO CO CO U Oo U M UN FE O oa CO VJ o UG A UN r o memset amp conf data OxFF sizeof PCIE CONF DATA Software reset pcie soft reset sel A physical layer s initialization if pcie phy init sel lt 0 return A connection start The initialization of PCIE lt 0 if pcie trans cont init sel return A set of a configuration if pcie config init sel 0 return fx FUNC COMMENT U HAHAHAHAHAHA AAA AAA AA AA A ox F F F xo F ID Outline Sample Program Main PCI Express Include Declaration void pcie check int sel Description The check of a PCIE controller device Limitation Argument none Return Value none Calling Functions FUNC COMMENT END M VOKCKCKCKCKCKCKCKCkCkCkCKCkCkCkCKCkCkCkCkCkCkCkCk k k k k k k k k kk SR e void pcie check int sel unsigned long lane A view of a configuration register if conf data VenderID OxFFFF amp amp conf data DeviceID OxFFFF Scif printf Enable lane d LANE n r pcie link lane sel scif_printf n r EE Scif printf Vender ID 04xNnNr conf data VenderID Scif printf Device ID 04xNnNr conf data DeviceID scif printf Command 04xNnNr c
109. tion This flowchart shows the processing sequence from the start of the main function which occurs after initial settings to LBSC and DBSC3 following a power on reset Pin function settings A lt pfc init gt Make pin function settings v SCIFO settings lt scif_init gt Set SCIFO to 115 200 bps 8 bits PCIEC Endpoint CONFIG PCIE END 1 PCIEC ROOT port or END point PCIEC Root port CONFIG PCIE ROOT 0 Console display 1 i ii Console display 1 Display SH7786 PCI Express DEMO Sample root port 8 PCIEC endpoint initial settings Target Device Check Y N appears on the console display prompting the user No to enter Y to check or N not to check the target device Check target device Console display 2 Display No Check Device Pel B 9 Make PCIEC root port initial settings Console display 2 v Read PCI Express configuration Read the configuration space of the target End space device v i Console display 3 Display the Vendor ID and Device ID of the target device Console display 3 If the value of VID DID is OxFF display Device not detected on PCI Bus Transmit Data Start Y N appears on the console display prompting the user to enter No Y to transmit receive data to from the target device or N not to transmit receive data Start data
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111. transmit Console display 4 Display Transmit Not Start v Console display 4 End Figure 4 2 Flowchart of main PCI Express Root Port 1 RO1AN0557EJ0100 Rev 1 00 Page 31 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program v for i 0 i lt 4 i Vv Write to IO space lt pcie io write gt v Read IO space lt pcie io read gt v Console display 5 v Write to memory space lt pcie mem write gt Vv Read memory space lt pcie mem read gt v Console display 6 v v Initialize transmit data v Console display 7 v DMA transfer write to memory space lt pcie start dma gt v Console display 8 v Console display 9 v DMA transfer read from memory space lt pcie start dma gt v Console display 10 v Console display 11 End Write test data to IO space of target device Read test data from IO space of target device Console display 5 Display address and test data read from IO space Write test data to memory space of target device Read test data from memory space of target device Console display 6 Display address and test data read from memory space Load DMA tra
112. uction 216 217 define PCIE MAX CONFREG SIZE 0x1000 Configuration register size 256 byte 218 2I9 k 220 PCIE Configuration register 221 222 tdefine PCIE CONF DEVICE ID 0x00 223 define PCIE CONF VENDER ID 0x00 224 define PCIE CONF STATUS 0x04 R01AN0557EJ0100 Rev 1 00 Page 72 of 84 Jul 15 2011 RENESAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 212 273 274 275 276 Did 278 279 280 281 define PCIE CONF COMMAND 0x04 define PCIE CONF CLASS CODE 0x08 define PCIE CONF REVISION ID 0x08 define PCIE CONF BIST 0x0C define PCIE CONF HEADER TYPE 0x0C define PCIE CONF LATENCY TIME 0x0C define PCIE CONF CACHE LINE SIZE 0x0C define PCIE CONF BASE ADDRESS 0 0x10 define PCIE CONF BASE ADDRESS 1 0x14 define PCIE CONF BASE ADDRESS 2 0x18 define PCIE CONF BASE ADDRESS 3 0x1C define PCIE CONF BASE ADDRESS 4 0x20 define PCIE CONF BASE ADDRESS 5 0x24 define PCIE CONF SUB SYSTEM ID 0x2C define PCIE CONF SUB VENDER ID 0x2C define PCIE CONF EXP RO
113. uffer Set TXBUFCLR to 1 End Figure 4 7 Flowchart of PCIEC Software Reset RO1AN0557EJ0100 Rev 1 00 Page 35 of 84 Jul 15 2011 3 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 6 Flowchart of PCIEC Physical Layer Initialization This flowchart shows the processing sequence for initializing the PCIEC physical layer Start lt pcie phy init gt v Console display 1 v Set physical layer control register PCIEPHYCTLR Y Initialize physical layer control register phyreg_write gt PCIEC root port or endpoint PCIEC Endpoint CONFIG PCIE END 1 Read physical layer control register lt phyreg read gt Console display 1 Display PCle PHY During Initialization Supply physical layer register space access clock Set PHYCKE to 1 Initialization sequence 1 Set physical layer control register address 0x60 to 0x004B_008B 2 Set physical layer control register address 0x61 to 0x0000 7B41 3 Set physical layer control register address 0x64 to 0x00FF 4F00 4 Set physical layer control register address 0x65 to 0x0907 0907 5 Set physical layer control register address 0x66 to 0x0000 0010 6 Set physical layer control register address 0x74 to 0x0007_001C 7 Set physical layer control register address 0x79 to 0x01FC 000D 8 Set physical layer c
114. upt Setting Determine the type of interrupt to be used by the system INTx or MSI and make the corresponding setting for each device RO1AN0557EJ0100 Rev 1 00 Page 13 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program f Master Enable Setting Set the Bus Master Enable bit bit 2 Memory Space Enable bit bit 1 and I O Space Enable bit bit 0 in PCICONFI to match the transfer to be performed following initialization When the root port receives a request from an endpoint first set the Bus Master Enable bit of the root port to 1 At the same time set Memory Space Enable to 1 if memory access is to be accepted or set I O Space Enable to 1 if I O access is to be accepted Without these settings the root port will not accept requests Next set the Bus Master Enable bit of the endpoint to 1 Without this setting the endpoint cannot issue requests To enable memory access or I O access to the endpoint set the Memory Space Enable or I O Space Enable bit of the endpoint to 1 Without this setting the endpoint will not receive requests RO1AN0557EJ0100 Rev 1 00 Page 14 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 2 5 PI O Transfers Data Transfer from PCIEC to External Device As used here PI O transfer refers to a data transfer performed by accessing the PCIEC memory space via the internal
115. y DL Active e Set INTDLE bit 14 in PCIEINTER to 1 e Set Data Link Layer ACTive Enable bit 31 in DLINTENR to 1 The PCIEC does not support more than one virtual channel VC Only one virtual channel VCO can be used for communication RO1AN0557EJ0100 Rev 1 00 Page 11 of 84 Jul 15 2011 34 NE SAS SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program 2 4 Configuration Cycle PCI Express Initialization When the PCIEC is used as a root port a configuration cycle must be initiated to configure the connection target device In the configuration cycle configuration access is performed to confirm the status of the configuration registers of the connection target endpoints and based on the result values are assigned to the configuration registers of the root port itself and of the endpoints The root port typically accesses its own configuration registers via the SuperHyway bus 1 Initiating Configuration Access When the PCIEC is used as a root port the configuration is accessed to start the configuration cycle in which a variety of initial settings are made The procedure described below is used to access the configuration registers of external devices by means of configuration access by PCIEC The procedure described below should not be used by the PCIEC when operating as a root port to access its own configuration registers Instead perform access via the SuperHyway bus to registers mapped t
116. yte data set 105 printf r nDMA Start 106 L07 printf n rWRTITE SuperHyway gt PCI An 108 ret pcie start dma CONFIG PCIE ROOT PCIE AREA ADDR sdram data area PCIE WRITE TransByte 109 if ret 110 printf inNrPCIE DMA Error n Page 47 of 84 SH7786 Group SH7786 PCI Express Controller PCIEC Initialization Sample Program break startadd 0xA0000000 sdram_data_area printf r nTransfer Data n r for 1 0 i lt TransByte 16 it for j 0 j 4 j printf 08x unsigned long startadd startadd 4 printf n r o U o U M WN S N N PROP PM PM or as U NF O to printf r nREAD PCI gt SuperHyway Nn N N Jo if ret printf XnNrPCIE DMA Error n break N oo WwW N C startadd 0xA0001000 sdram_data_area printf r nTransfer Data n r for i 0 i lt TransByte 16 i t for j 0 j 4 j printf 08x unsigned long startadd startadd 4 WWW WWW Ww Yo oF UN FE printf n r A AeA U W FO io o break Ds N case N printf Transmit Not Start n r Bam dy U break default break Bs C BBA A wo 0 1 a else if ret 91 o Cc Fr pcie init CONFIG PCIE END C N C ul Ae U endif printf PCI Express Demo Sample End n r on 91 ow U U o 0 1 a FUNC COMMEN T TH ook kk

SH7786 Group SH7786 PCI Express Controller (PCIEC)

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