EECS 373 Winter 2004 Lab 3: Bus Interfacing for I/O Devices
Contents
1. like that found on page 13 13 of the white book Exclude BR BG BB TSIZ 0 1 and BURST Include in the sketch where you think the enable and latch clock signals should occur for the LED switch regis ter Reference the signals to the bus clock 2 points In Lab Procedure Part Debugging your hardware Step 1 Basic functionality Implement the interface circuitry in a macro and test the macro using the simulator Although this is not a prelab requirement your time in lab will be better utilized if you simulate your design before coming to lab Since it is difficult to completely simulate MPC read and write cycles just focus on address decode correctness and TA generation Remember when using buses to always label them Configure the logic analyzer with the configuration file first A This configuration maps the MPC external address bus data bus control bus and 8 testpoints for observation The MPC external bus signals are physically connected to the logic analyzer via the ribbon cables connected to the MPC processor board The configuration also sets the trigger to capture on an active low TS transition Triggering on transfer start captures a complete read or write cycle In addition to the MPC external bus signals it will also be very helpful to observe the con trol signals associated with reading the switches and writing the LEDs For now connect the switches tri state buffer enable signal the LED register latch cloc2. EECS 373 Winter 2004 Lab 3 Bus Interfacing for I O Devices Requirements Pre lab Individual answers to pre lab questions are due at the beginning of your lab sec tion during the week of January 19 2004 Your group must also have initial hardware and software designs completed and entered into Xilinx and Sing leStep respectively In lab In lab demo sheet due by Friday at 5 30 PM January 30 2004 This is a two week lab Post lab Answers to post lab questions are due at the beginning of your lab section dur ing the week of February 2 2004 This is a two week lab Value This lab is worth 7 of your total grade Objectives The purpose of this lab is to 1 Introduce you to the basic logic required to interface a device to the MPC823 bus 2 Observe the interaction of hardware and software in a very simple environment 3 Gain very basic experience with system design involving hardware software and integration Overview Interfacing hardware I O devices to a microprocessor is a simple matter of observing the processor s bus signals and responding accordingly Once done the hardware device can be controlled by software running on the processor In this lab you will interface the switches and LEDs on the expansion board which you used in Lab 1 to the MPC823 bus You will also write a simple assembly language program to read the state of the switches and update the LED display accordingly Design Specifications
3. Your hardware design will consist of two I O device registers an input pathway to read the state of the switches and an output register to control the state of the LED displays Specifically e Create a 32 bit input pathway at address 0x03 100000 that returns the state of the eight DIP switches in bits 24 31 and the toggle and pushbutton switches in bits 20 23 Bits 0 19 are unused and should return zeros to the CPU e Create at 32 bit output register at address 0x03 100004 that sets the pattern displayed on the LEDs After writing to this register the seven segment display must show the hexadecimal value contained in bits 24 31 of the value written and the bar graph dis play should show the binary value contained in bits 16 23 0 off 1 on Bits 0 15 are unused and should be ignored The software component consists of an assembly language program that continuously reads the state of the switches and sets the LED displays accordingly Your program should have the following features e When pushbutton S1 is pressed the seven segment display should be updated to show the binary value entered on the DIP switches When pushbutton S2 is pressed the bar graph display should be updated to show the binary value entered on the DIP switches The state or position of toggle switch S3 determines how values are to be displayed on the bar graph LED and seven segment display when S1 or S2 are depressed If switch S3 is in the normal positi
4. h clearer and as long as all the operands are constants the assem bler will evaluate these expressions for you eliminating potential calculation errors For example a 32 bit value with a single 1 bit in bit position 21 can be written as 1 lt lt 31 21 The 31 x is required because in the PowerPC world bit position 0 is the most significant bit Your intent is much clearer and errors are much less likely than if you did the calculation in your head and just used the equivalent constant value e g 0x400 14 points 2 points each a Set bit 29 b Set bit 18 c Set bit 4 d Toggle complement bit 15 e Toggle bit 6 f Clear bit 21 g Set the bit indicated by the value in r6 Assume that r6 holds a value between 0 and 31 Give an instruction sequence that will execute the Iwz in the code fragment below if and only if bit 21 of r4 is 1 4 points your code goes here lwz r5 O r6 skipload more code Why is the LED register at 0x03100004 and not 0x03100001 4 points Since you are only checking a subset of the external address bits your registers will respond to a number of different addresses This practice of partially decoding addresses is very common Partial decoding is OK if there are no other devices 3 located in that part of the address space The additional addresses are referred to as shost or shadow locations For example consider a hypothetical processor with a
5. inside the PROC macro will act as the tristates which allow your device to return read data to the CPU Low true signals are denoted in Xilinx by a _ BAR suffix e g TA is TA_BAR The open collector wired OR Xilinx output signals TA_BAR TEA BAR IRQI_ BAR and IRQ7_ BAR use a special output circuit that only drives the output pin low when the input signal is low and leaves it tri stated floating otherwise You should make sure to drive all unused Xilinx output signals i e for this lab tie TEA BAR IRQI BAR and IRQ7 BAR to VCC The MPC823 will sample its input signals TA_BAR and on a read the data bus on each rising edge of the clock You need to provide non zero setup and hold times for these inputs relative to the clock edge An easy way to do this is to drive the signals from one falling clock edge to the next providing roughly one half of a clock cycle of setup and hold each To save on address decoding logic you should check only the upper six external address lines A 6 11 recall that A 0 5 are not available off the processor chip to determine whether your registers are being accessed and one low order address line which one to determine which of your two registers is being accessed The remain ing address bits are don t cares TA must be asserted for exactly one rising edge of the bus clock There is a macro in the EECS 373 library Dual7sdsp that takes an 8 bit binary input converts it to the appr
6. ive to the led register latch clock sig nal Demonstration 1 2 Show your captured write transaction to the lab instructor and indi cate that you can measure the respective setup and hold times Step 3 Experiment with access size Access your I O registers using byte rather than word operations You can do this from the SingleStep command line by using b instead of I i e read rbx and write b Record what happens for questions 7 and 8 of the post lab Part Il Debugging your software Thoroughly test your program using the SingleStep simulator The simulator will assume that 0x03 100000 and 0x03100004 are regular memory locations You can emulate the effects of changing the switches by changing the contents of location 0x03100000 in the memory window You can observe changes to LEDS by checking the values written to location 0x03 100004 Part Ill Integration Once your hardware and software appear to work in isolation download your program to the processor and trace through it using the debugger Once you are satisfied that your pro gram works click the green go icon and let your program run Adjust the switches on the target board to test your system Demonstration 2 1 Demonstrate your system for the lab instructor Post Lab 1 Summarize the operation of your circuit and describe how you arrived at the design Include a printout of your final schematic including schematics of any macr
7. k and enable signal to test points It is also very useful to observe the PD_OUT_EN signal since it enables data onto the MPC823 data bus via PROC macro Make sure the appropriate test point wires from the logic analyzer are physically connected to the EECS373 IO board Power on the target board then start SingleStep In the initial SingleStep dialog box check Debug without a file then click OK This causes SingleStep to initialize the target board without downloading a program Remember you must initialize the target board using Sin gleStep before downloading your Xilinx design Download your design to the Xilinx board with the suggested test point signals connected Use the read and write commands in the SingleStep command window to test the I O device registers Specifically read rlx 0x03100000 will read your switches and write 1 0x03 100004 0x1234 will write the 32 bit value 0x00001234 to your LED reg ister The read and write arguments are lowercase Ls not ones Initiate a read and write cycle with the SingleStep read and write commands and observe the transactions with the Logic Analyzer e Verify that TA occurs at the correct time for both read and write cycles If it does not you must correct your design before going any further Do not expect to debug your logic by simply observing your schematic If you are suspicious about some facet of your circuits functionality connect te
8. on the displays show the actual binary value on the DIP switches If switch is S3 is in the other complemented position the value dis played on the bar graph must be the one s complement of the DIP switch value and the value displayed on the seven segment display must be the two s complement neg ative of the DIP switch value You may choose which S3 switch position is normal and which is complemented Toggle switch S4 is unused Design Notes and Hints e e e e e e Review pages 13 9 through 13 14 of the Motorola PowerPC MPC823 User s Manual The PROC macro from the EECS373 library represents the basic bus signal connec tions for the Xilinx chip on the expansion board Signals on the left side of the macro block are processor inputs Xilinx outputs while signals on the right side are proces sor outputs Xilinx inputs The data bus is handled specially although the pins are bi directional the Xilinx software requires splitting them up into two parts on the Xilinx chip PD_IN is the data bus input from the processor to the Xilinx while PD_OUT is the data bus output from the Xilinx to the processor The PD_OUT_EN signal enables the data bus drivers which will drive the value on the PD OUT bus onto the Xilinx pins Use the Hierarchy tool to open up the PROC macro and see how these two busses and the enable signal are connected to the physical data bus pins In this lab the tri state drivers
9. opriate hexadecimal seven segment on off patterns and multi plexes it onto the dual seven segment display You need only supply a clock i e gclock from the PROC macro e You will need to select a device to implement your LED register Consider a clocked device such as the FD8CE This is a macro consisting of 8 D flip flops in parallel Use the hierarchy key to examine the contents Pre lab assignment Note Pre lab questions must be done individually and handed in at the start of your lab section You must also with your partner design an initial version of your hardware and write an initial version of the required program before you come to your lab section You must bring a printed schematic and program listing file the lst file to your lab section to show the lab instructor or you will not be allowed to work in the lab Your hardware and program do not need to be completely debugged but obviously the more debugging you do on the CAEN simulator the less time you will spend in the lab For all the questions use the following constants 1 equ zero 0 equ one 1 Write an instruction or instruction sequence that will perform each of the following single bit operations on the value in register r4 All other bits in r4 should remain unchanged In this problem and in all your programs use the C arithmetic operators for example lt lt gt gt amp to derive the constant values you may need Your code will be muc
10. os you defined Itemize in a systematic fashion the different steps involved in your design Make sure that the schematic printouts are big enough that all the signals are legible 4 points Sketch the bus activity for a read of the switch register and a write of the LED regis ter Clearly indicate causality using arrows e g from clock edges or input control transitions to output transitions 4 points What are the setup and hold times you measured at the HP logic analyzer in Part I 3 points Include a well commented listing of your program Comments should include regis ter usage which values are kept in which registers descriptions of all symbols and explanations of all derived expressions 4 points Compare the complexity of your system hardware and software to Lab 1 What are the advantages and disadvantages of using a microprocessor instead of hard wired control logic 3 points What happens when you perform a read to your LED register If your circuit does not let the CPU read back the LED display value sketch the logic required to make it do so Briefly describe how your program might change if you did did not let the CPU read back the LED state whichever you didn t do for the lab 4 points How does your input register handle byte reads Describe what happened when you attempted to use byte reads in Part I What address would you use to have a byte read return the settings of the eight DIP switches 4
11. points How does your output register handle byte writes Describe what happened when you attempted to use byte writes in Part I What address would you use to have a sin gle byte write set the bar graph display value without affecting the seven segment display Sketch the additional logic needed to make this work 4 points Lab 3 Demonstration Sheet Print this page and present it to your lab instructor when demonstrating the various lab sections Turn this sheet in with your post lab or when your in lab demonstration is due You are required to turn in only one demonstration sheet per group List Partners Names Part I Debugging Your Hardware D1 1 Show your captured read transaction to the lab instructor and verify measurement of setup and hold times Lab instructors initials D1 2 Show your captured write transaction to the lab instructor and verify measurement of setup and hold times Lab instructors initials Part III Integration D2 1 Demonstrate your system for the lab instructor Lab instructors initials
12. st points to the signals and verify the operation with the logic analyzer e Verify that the enable control for the switches tri state buffer and PD_OUT_EN signal occurs at the correct time during a read cycle If they do not you must correct your design before going any further Again use the logic analyzer to observe and verify the operation of your interface logic e Verify that the enable and latching clock signal to the led register occur at the correct time for a write cycle If they do not you must correct your design before going any further Use the logic analyzer to verify your design assumptions The read command reads several adjacent locations in addition to the one you specify Do the values in the adjacent locations confirm or contradict your answer to pre lab ques tion 4 Try writing the LEDs via one of the shadow locations What happens Step 2 Measure setup amp hold times Capture a read transaction to your input register on the logic analyzer What are the setup and hold times of TA and the data bus relative to the clock edge Demonstration 1 1 Show your captured read transaction to the lab instructor and indicate that you can measure the respective setup and hold times Capture a write transaction to your output register on the logic analyzer What are the setup and hold times of TA relative to the clock edge What are the setup and hold times for the data bus and led register enable signal relat
13. very small address space from 0x00 to OxFF The address lines are labeled from AO to A7 with A7 being the least significant Lets say the processor only needs the address space from 0x00 to Ox7F for program execution The space from 0x80 to OxFF is available for IO mapping Lets also say we are only interested in providing an address for one register We could simply use address line AO to enable the IO register In other words its pri mary address would be at 0x80 However the rest of the address space from 0x81 to OxFF would also map to the register since AO is always logical high in this address range This is not a problem if this is the only IO address we are interested in decod ing in this range The shadow locations would range from 0x81 to OxFF and the number of shadow locations would be 0x7E Besides the address you designed your registers to be accessed from how many other word aligned addresses shadow locations will they respond to What are these addresses You can specify a range Remember the MPC823 external bus con sists of address lines A6 A31 so you can assume AO AS are zero 4 points 5 Sketch a read cycle with zero wait states like that found on page 13 10 of the white book Exclude BR BG BB TSIZ 0 1 and BURST Include in the sketch where you think the enable for the tri state buffer PD_OUT_EN should occur Reference the signals to the bus clock 2 points 6 Sketch a write cycle with zero wait states
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