Deep Dive on Kinetis E Series MCUs with 5 V I/O and High EMC
Contents
1. O Fault flag cleared Fault z freescale FlexTimer Dual Edge Capture One shot or continuous mode Pulse width measurement Period measurement fifa DECAPEN al UWhannalim TA CHITIE interrupt CHF j ELSin TB GinvHiL 15 Dual capture mode logic channel n1 CHinetIE interupt 2 counter 4 2 freescale aus ADC with 8 entry FIFO Linear Successive Approximation algorithm with 8 10 or 12 bit resolution Up to 16 external analog inputs external pin inputs and 5 internal analog inputs including internal bandgap temperature sensor and references oingle or Continuous Conversion automatic return to idle after single conversion Operation in wait or stop3 modes for lower noise operation Automatic compare with interrupt for less than or greater than or equal to programmable value 8 entry channel FIFO and result FIFO to minimize the CPU overhead Configurable FIFO depth from 2 to 8 entries as FIFO full condition When channel FIFO is full For software trigger mode Immediately start the first channel conversion after the previous conversion completes start the next conversion until the conversion of the last channel in FIFO depth completed set conversion complete COCO flag For hardware trigger mode When the first trigger occurs start the first2. N 00 tO tO a o o N gt B J Ul ev 3 3 3 3 3 3 3 3 gt gt gt gt gt gt gt gt gt 10 Module to Module Interconnection ADC BUS CLE 1 ADHWT BUSREF freescale External Use 43 Use case1 FTM2 sync ADC while generates fault to FTM2 ADO AD1 INITTRG MATCHTRG AD15 Gap FIM2 4 A 52 2 freescale uu Use case2 UARTO TXD modulation for Infrared UUL UARTO TX i 4 TXDME 4 2 freescale 45 Use case3 UARTO RX filter for Infrared demodulation UARTO RX RX UARTO RXDFE 4 Z freescale uu 46 Use case4 UARTO RX capture by FTMO ch1 x UARTO RX FIMO CH1 RXDCE 4 freescale External Use 47 Fast FlexTimer FTM e Optimized for motor control and power Dual edge capture conversion applications Immediate PWM registers load FIM clock as high as CPU clock up to 48 MHZ Invert control channel e Generation of independent complementary and asymmetric Fault input polarity contro Hardware dead time insertion Rich PWM synchronization scheme and fault Programmable TOF frequency Software output control Debug mode function The be set to protection still function when the debug mode is entered PWM output masking and polarity control
3. 5 5V 48MH 64 128KB 8 16KB 12 bit Operating Temp 40 to 105 C REC 3 Clock Management KE047128 48MHz 128KB 16KB J J 12 bit External OSC 4 20MHz 32KHz Internal OSC 32KHz 1KHz KE04Z64 48MHz 64KB 8KB J J 12 bit Analog Peripherals 12 Bit ADC KE04Z8 48MHz 8KB 1KB J 12 bit 20MHz 16 64KB 2 4KB 12 bit Analog Comparators Serial Interfaces SCI 40MHz SPI Timers Real Time Clock 16bit Flex timers 32bit Periodic Interrupt Timer 1 20MHz 40MHz for 02 N 4 Z freescale Kinetis 0 Series Master Block Diagram System Memories Clocks Key Features Core System ARM G Cortex MO up to 48MHz Memory upto 128KB Flash upto 16KB SRAM Communications 1x CAN Multiple serial ports UART 2 x SPI 2 x I2C Analog 16 12 bit ADC _ 2X ACMP Security and Analog Timers Communication Interfaces HMI Timers Integrity 1x6chFIM 2 x 20h FTM 1xPIT UID PIT aic RTC PWT Others Upto 71 I Os RTC 2 7 5 5V 40 to 1050 Packages 80 64 44 32 64QFP 24QFN 20SOIC 161 SSOP Pin compatible within KE freescale aus Kinetis E Series Selling Point Robust ns Better performance and system robust Robust Improved 5V 1 0 pad with digital filter the harness environment and easy for PCB layout Makes system more safer while reducin
4. 2 freescale semaus 62 Background Internal evaluation on EMC performance in board level and system Ievel Identify device capability in real application environments A simplify microwave oven reference design is developed as a test platform e Include all hardware firmware and mechanical design to provide stable controllable and precise environment for EMC measurement y 4 2 freescale lt Test Platform Application Home Product Microwave oven MCU MKE02Z64VLD2 64 LQFP Board KE02 Controller Board with Power Supply KEO2 Controller Board freescale 65 Test Results Board level IEC 61000 4 4 EFT 4 4kV e IEC 61000 4 2 ESD Indirect Contact Discharge 20kV e China Appliance local test on AC Power Relay 6 turns without Reset oystem level e IEC 61000 4 4 EFT 4 4kV e IEC 61000 4 2 ESD Contact Discharge at the case 20kV IEC 61000 4 2 ESD Air Discharge at the control panel 15kV Limited by the test equipment max output voltage 4 Z freescale uu 66 PCB Layout Recommendation Ground Plane Connection e Rotate the 02 package 45 degree for more easy routing on I O pins Fill up a ground plane underneath the MCU and connect all VSS pins together to ensure all VSS pins are kept at same potential level e The MCU ground plane can be further extended to the package corner points to achieve
5. Can sync with ADC via programmable delay Enhanced triggering functionality channel block match trigger and init trigger PWM 1 a PWM 2A PWM Signal Sync Pulse ADC trigger mese Conversion o Z freescale FlexTimer Complementary PWM Channel n controls first edge of PWM while lt n 1 gt controls 2nd PWM edge channel match FTM counter channel m match channel n output with ELSnB ELSnA 1 0 channel n 1 output with COMP 0 ce output E 4 2 freescale au 49 FlexTimer Deadtime insertion Deadtime insertion on either rising edge or falling edge Counter clock derived from 1 4 16 system clocks Count from 1 to 63 Dead time from 1 to 1008 system clocks 0 05 to 50 4us 20MHz channel r 1 match y M al da aaa NEN d counter Pun al channel m match 5 mn mmm T i l L i I channel nj output before deadtime Eo insertion ehannelf re T output before deadtime EE H insertion N channel output P after deadtime irc e eho ri channel n 1 output after deadime ine ertion gt o Z freescale 50 FlexTimer PWM synchronization Provide opportunity to force FTM counter to its initial value CNTINH L and the channel outputs are forced t
6. FREESCALE TECHNOLOGY FORUM 2014 Deep Dive on Kinetis E Series MCUS with 5 V 1 0 and High EMC Performance FTF IND F0471 Allen Lv Product Marketing William Jiang Dennis Lui Application MAY 2014 27 freescale E vaito Ls ren etg portare mens reveren ar gi rte terr er in eg den c Agenda US e Kinetis E MCU Overview by Marketing Deep Dive of Key Features e Real Case EMC Design Guideline Freedom and KEOx Peripheral Driver Lib Demo e Summary 4 2 freescale Kinetis E Overview freescale Market Needs 5 32b KE Appliance MCU TAM Key Segment Appliances B COLD Refrigeration B HOT Oven Hobs uWave BRAC Room Air Con WET Washer Dish Dryer Changing Product Mix in Appliance Electrolux LG Designed for the well Iived home 5 GRECE 4 Lu 1 inpesir D company Aides JAM Miele 2 gt Z freescale CR E 5 bit E 16 bit 32 bit 2010 2014 16 32 bit TAM Grows from 143M to 278M M Vm i e 9 0 E A ANE p u 797 aa s A I e d t M a T 4 7 Pe 4 x B O 5 4 5 CI 4 2 q 7 Ca bI Cw L EMC ESD design Kinetis technology ensure strong noise immunity Fret Tape Alpha performance p
7. C code for bit field insertion without BME gt C code for bit field insertion with BME Speed improved by 9 Code size improved by 33 4 2 freescale ernal Use 32 Bit band KE04 and 06 Support uninterruptible atomic read modify write operation on RAM U Two 32 MB aliased bit band regions associated with the two 1 MB bit band spaces functional on RAM U e Each 32 bit location in the 32 MB space maps to an individual bit in the bit band region A 32 bit write in the alias region has the same effect as a read modify write operation on the targeted bit in the bit band region A 32 bit write in the alias region returns either Writing a value with bit O set writes a 1 to the target bit a value with bit O clear writes O to the target it 32 bit read in the alias region returns either value of 0x0000 0000 to indicate the target bit is clear a value of 0x0000 0001 to indicate the target bit is set 4 2 freescale us FLASH Memory Controller FMC The FMC sits between the platform masters Core and the Flash accelerates access time with buffers which will provide 0 wait state access times when hit e Each access of the Flash pulls next 32 bits into the FMC cache buffer This way we move 2 instructions and can deliver full performance to the 48MHz bus from the 24Mhz Flash bus When flash cache enabled the
8. 2013 o Cortex M0 core up to Ti ar 48MHz and 40x more than 8 16 bit MCUs t p AE Optimized for cost sensitive mph Aug 2013 applications offering low pin count option Productio Prone freescale aus S Kinetis E Series Target Market DC fans 4 Timers System Core Complex Analog Sewing Machine ec MEME Co 0 o Elevator EL Les Je 22 Clocks e ES sm Offline UPS T E EE EE Metering G Memory HMI Security Serial B ker Interfaces Interfaces Surge Protection L t e DC DC y 4 Z freescale lt Kinetis E Series Kinetis E Series Product Roadmap 2 7 5 5V MCUs with high reliability and robustness Based on ARM Cortex M with best in class Enablement Concept KE1xF High Performance Mix Signal EN KE1xZ General Purpose ROM DMA KEOxZ Entry Level KE1xF Performance QT O Mix Signal Ki 2 2 KE1xZ Performance enhancement Feature optimization KEOxZ MO with base feature set 8KB 16KB 32KB 64KB 128KB 256KB 512KB Memory Density 4 Z freescale Kinetis E Series MCU Families Optional Features KeyFeatures KeyFeatures System LCD Timer Multiple power modes Clock Gating 2 7V
9. Kinetis E HARDWARE Development Platforms www freescale com FRDM KE02Z Freedom Platform FRDM KE022 The Freescale Freedom development platform is a set of software and hardware tools for evaluation and development It is ideal for rapid prototyping of microcontroller based applications The Freescale Freedom KE02Z hardware FRDM KE02Z is a simple yet sophisticated design featuring a Kinetis E Series microcontroller the industry s 5V microcontroller built on the ARM Cortex M0 core MKE02Z64VQH2 MCU 20MHz 64KB Flash 4KB SRAM 64QFP Capacitive touch slider MMA8451Q accelerometer Tri color LED Flexible power supply options USB external source Easy access to MCU I O OpenSDA IrDA transmitter and receiver Thermistor sensor to measuring temperature Form factor compatible with Arduino M R3 pin layout OpenSDA MCU New OpenSDA debug interface 95 Host MSD Bootloade _ Target Mass storage device flash programming interface default Mense no tool installation required to evaluate demo apps File System 3 P amp E Debug interface provides run control debugging and Serial T UART RXITX compatibility with IDE tools Termnai ee CMSIS DAP interface new ARM standard for embedded debug interface Refer to the FRDM KE02Z User s Manual OpenSDA A Guide for more information freescale Use 78 a Get to know 02 freedom o Heset Button
10. conversion after previous conversion completes and when the next trigger occurs start the next conversion until all channels in FIFO depth completes conversion then set conversion complete COCO flag y 2 freescale External Use 55 ADC with 8 entry FIFO FIFO scan mode Always use the first dummied channel in spite of the value in the input channel FIFO to simplify the dummy work of input channel FIFO conversion start to work in FIFO mode as soon as the first channel is dummied when the previous conversion is completed start the next conversion until the result FIFO 16 full and then set conversion complete COCO flag In continuous conversion in which the ADC_SC1 ADCO bit is set the ADC starts next round of conversion immediately when all conversions are completed Input channel FIFO Channel conversion H W trigger H W trigger lt gt HNN trigger FIFO Full Write ADC SC1 ADCH Write SC1 ADCH Write ADC SC1 ADCH 2 freescale y PSZ External Use 56 ADC with FIFO ADC hardware trigger selection RTC overflow PIT overflow F T M2 trigger match trigger or initialization trigger with 8 bit programmable delay KEO2 ADC triggers gt ADC H W trigger Init trig FIM2 Bus clock V y 2 freescale aus S Watchdog WDOG Compliant with IEC60730 safety standard Independent clock source Intern
11. power consumption is also improved AXBS FMC 32 bit prefetch speculation buffer 4 Way by 2 set x 32 bit cache for a total of 32bytes 4 2 freescale Flash and EEPROM Flash memory 64 bit security and backdoor key Automated program and erase algorithm with verify Fast sector erase sector size 512B and longword 32 bit program operation Flexible protection scheme to prevent accidental program or erase of flash memory Accessible 64 byte in hidden non volatile information block Ability to set flash read margin levels EEPROM Single bit fault correction and double bit fault detection within a word during read operations Automated program and erase algorithm with verification and generation of ECC parity bits Fast sector erase sector size 2B and byte program operation Protection scheme to prevent accidental program or erase of EEPROM memory Ability to program up to four bytes in a burst sequence Ability to set EEPROM read margin levels 500K program erase cycles Command Interrupt Request Ero Request Flash Interface Bus Clock Registers Securty EEPROM 26 0 CPU a KEOx family has another new flash operation feature read while write It allows read from flash while programming erasing the flash by setting Enable Stalling Flash Controller bit in MCM PLACR freescale ss Pulse Width Timer PWT Capture signal perio
12. to legacy 8 and 16 bit architectures Do more with the same Flash size CoreMark code compiled optimized for size A B C amp D 2 Z freescale 16 Benefits of Moving from 8 16 bit to 32 bit ARM Cortex M0 8 16 bit Performance Older slower architectures amp technology 2x to 40x more than 8 16 bit 9 more than Cortex MO Increased code size complexity when performing complex math operations Fast single cycle access to I O Energy Efficiency Low energy efficiency gt 2x CoreMark mA than closest 8 16 bit MCU 30 CMO Low Cost 6 35kgates Variable code density Ease of Development Limited addressable memory Simplistic interrupt controllers Full featured interrupt controller simpler s w architecture Limited scalability MHz flash features Limited ecosystem support Micro Trace Buffer lightweight non intrusive trace not implemented in Kexx y 2 freescale ITI 2S Cortex M Processor Family Five products two architectures High performance data processing amp 1 0 control Support hardware divide MAC bit field processing DSP Floating point unit optional Cortex M4F ARMv7 M High performance data processing amp 1 0 control architecture Support hardware divide MAC Multiply Accumulate bit field processing General data processing high performance 1 0 control mixed signal ASICs replacement for 8 16 bit MCUs ARMv6 M architecture
13. trigger and interrupt 14 CRC demo 2 freescale semaus Summary Presented general Kinetis E overview e Deep dive the key features design guideline Talked about freedom and KEOx peripheral driver Demo 4 2 freescale Designing with Freescale 2014 seminar topics include QorlQ product family update Kinetis K L E V series MCU product training freescale 83 2 freescale www Freescale com 2014 Freescale Semiconductor Inc External Use
14. Away 4 2 freescale us Freedom and KEOx Driver Lib freescale 76 Kinetis E Series MCUs Entry level Enablement Product Selection Hardware IDE amp Code Generation Freescale Freedom Development Platform FRDM KE02Z40M FRDM KE04Z FRDM KE06Z Low cost platform for entry level developers 12 95 USD Features the Freescale open standard embedded serial and debug adapter OpenSDA a a Ta Vata WMA OW 71 1861 1 Talo siel gor LRA 14521 4 Arduino Compatible External Use 2 freescale Freescale amp 374 party IDEs Freescale CodeWarrior IDE v10 5 free 64KB Keil MDK free 32KB IAR EWARM free 32KB Atollic TrueStudio free 8KB GCC ARM Embedded Launchpad net Freescale Processor Expert Code Generator Free software generation tool for device drivers start up code 7 steps from project creation to debug dramatically reduces development time Available within CodeWarrior IDE or as a 77 standalone plug in for IAR Keil GNU IDEs CodeWarrior SIAR S KEIL SYSTEMS Mp GNU Solution Advisor www freescale com sa Web based interactive MCU selector Filters for operating characteristics packaging memory configuration amp peripherals Verifies muxing compatibility Save download and print summary reports and pin mixing configurations
15. General data processing I O control mixed signal ASICs replacement for 8 16 bit MCUs For FPGA designs only Optimized for FPGA and can work in most FPGA devices freescale 22202 Common Features ARM Many features are available on all Cortex M Microcontrollers NVIC Nested Vector Interrupt Controller Sleep modes and low power features OS support features such as SysTick timer CMSIS Core support API software for processor feature Debug support Different subset of Thumb 2 Instruction Set Architecture Architecture consistency means Using the same tool chain Easy program code reuse Multi sources possible Performance Functionality y 2 Z freescale 19 NVIC Feature Comparisons NVIC features Cortex MO Cortex MO0 Cortex M3 Cortex M4 Max Number of IRQ 32 NMI 32 NMI 240 NMI 240 NMI system exceptions 4 4 8 8 Exception Priority levels 4 2 4 2 25 8to 256 fixed fixed 2 fixed 2 fixed Masking registers 3 3 Interrupt Latency 16 12 12 cycles Dynamic priority change No No Yes Yes Vectortable relocation No Yes optional Yes Yes Registeraccesses 32 bit 32 bit 8 16 32 bit 8 16 32 bit 2 freescale Lao Interrupt Controller NVIC Cortex M family uses a number of methods to improve interrupt latency The first one is called tail chaining And the second method is calle
16. Market Cortex 77 777 gt Compatible with all other Cortex M cores 4 e al Low Power Leadership from ARM oingle cycle 32bx32b instruction ARM Cortex MO e Significant energy efficiency advantages The over 8 16 bit entry level processor e Processor consumption as low as 9 8uW MHz in 90nm process 52 uW MHz in 180nm process Outstanding results of 1 77 CoreMark MHz I O low power improvements with single cycle access to critical peripherals GPIO Helocatable vector table allows for dynamic exception handlers by moving the vector table into RAM Micro trace buffer brings fast debug advantages of trace to low end MCUS not implemented in KEOx 4 M 2 freescale 32 bit Performance and Functionality With 8 bit Ease of Use Streamlined Architecture The new cortex MO core strikes the right balance of performance and simplicity needed in entry level applications Accelerated Debugging Micro trace buffer accelerates software debug without wasting additional I O Plus get faster bug identification and correction with minimal system resources Micro trace buffer not implemented in Closer to the Hardware oingle cycle IO and peripheral bus facilitate bit banding and software protocol emulation keeping it an 8 bit look and feel Ultimate Code Density Cortex MO instruction set provides the most compact code even when compared
17. SMBus compatible IIC Make SMBus connection easier without additional overhead 4 2 freescale Kinetis E Series Selling Point Save Cost oo Scalable amp Wide range of packages with pin Makes code easy to reuse and platform design Pin Compatible compatible easier Low PCBA cost 0 8mm pitch package 64QFP Cost down PCBA process Lost cost development CW special edition free for 64KB Cost down development tool 22 freescale External Use 12 lt Kinetis E EMC Performance Robustness in EFT PESD and AC Power Relay Tests Test Conditions KE02 Controller Board Microwave Oven Controller board with KEO2 as main control MCU Board and System level tests based on EC 61000 4 A EFT EC 61000 4 2 PESD China Appliance local AC Power Relay test Test Results Board level IEC 61000 4 4 EFT 4 4kV IEC 61000 4 2 PESD Indirect Contact Discharge 20kV China Appliance local test on AC Power Relay 6 turns without Reset System level IEC 61000 4 4 EFT 4 4kV IEC 61000 4 2 PESD Contact Discharge at the case 20kV IEC 61000 4 2 PESD Air Discharge at the control panel 15kV Limited by the test equipment max output voltage freescale 13 Deep Dive of Key Features Cortex M0 freescale External Use 14 ARM Cortex M0 Processor The True 8 bit Replacement The smallest lowest power ARM processor L on the
18. U S B oo m i 15 4 3 lt 1 E LE UN d 1 m J A 1 gt M J aks 5 4 AN de 8 AM 7 12 4 d 2 7 2 7 24 Arduino R3 compatible I O Header Arduino H3 compatible I O Header ah UU Gon e NI 21111111111 Accelerometer OO Se Ke re 5 r a na KE02Z764VQH2 esa A T Uu Arduino H3 od Rafa ER 4 LEZ ww lt C 222222 2222 gt 4 ME P I EI i TN m 117917 7 B 40 ar 4 PV LT Uu no gt t 22 d PT v a N T compatible 4 I O Header p RGB LED 77 Touch Slider Z freescale 79 KEOx driver library 2 freescale ARM CMSIS complaint coding format more friendly for ARM users Unified coding style for better readability reusability portability and maintenance Unified API easy to understand for other module developers More efficient code by using inline functions Cover all on chip peripherals providing low level driver register access and high level driver Rich sample code for each module from simple to compl
19. al 32 kHz RC oscillator internal1 kHz RC oscillator External clock 16 bit Programmable timeout period with optional fixed 256 clock prescaler when longer timeout periods are needed Robust write sequence for counter refresh Refresh sequence of writing 0x02A6 and then 0x80B4 MUST be within 16 bus clocks 2 freescale Watchdog WDOG Window mode option for the refresh mechanism Programmable 16 bit window value Provides robust check that program flow is faster than expected Early refresh attempts trigger a reset Robust write sequence for unlocking write once configuration bits Configuration bits and registers are write once after reset to ensure watchdog configuration cannot be mistakenly altered Unlock sequence of writing Ox20C5 and then 0x28D9 within 16 bus clocks for allowing updates to write once configuration bits e Flexible test mode enabling fast testing watchdog in the safety environment either high 8 bit counter or lower 8 bit counter for comparison e Backup reset to prevent hardware lockup condition driven by bus Clock y freescale 2 22 Cyclic Redundancy Check CRC 16 32 bit CRC code for error detection e Programmable 16 32 bit initial seed value Type of Standards Transpos e for CRC Read Type of Transpose for Input 4 freescale 16 0x1021 OxFFFF No transp
20. as possible Defensive Software Design The software design cannot change the physical media which couples the noise into the system or reduce the absolute magnitude of noise generated from external sources The software must be able to identify a particular event if it is a false alarm triggered by noise sources or it is a normal driven event and then make a smart decision on corresponding actions Good defensive software design is one of the key factors to improve overall performance system protection and operating stability in noisy environments e g EMC 4 e freescale External Use 71 System Configuration Line Vdd AC Power Neutral GND Update Status Registers DDR etc once every 50 60 Hz Lost of 50 60 Hz cycles Power Failure wr TL Display Data Input Keys Encoder Pulses a Always check confirm input M High Low for Polling inputs Open and Edge Trigger Interrupts switch EE Software can act as Digital M Microwave mes Filter to suppress EMC noise IE Control 4 freescale External Use 72 Implementations Enable Watch Dog to avoid code runaway e Refresh data direction setting registers periodically Fill unused memory to avoid code runaway e Define all interrupt vectors even those that are not used e Select Frequency Locked Loop FLL engaged mode Always re confirm edge triggered event e Enable digital filter on inp
21. d frequency directly by h w in 16 bit resolution Provide highest response to system e Reduce CPU overhead Can measure positive and or negative pulse width Programmable triggering edge for starting measurement Programmable measuring time between successive alternating edges rising edges or falling edges Programmable prescaler from clock input as 16 bit counter time base Two selectable clock sources bus clock and alternative clock Four selectable pulse inputs Programmable interrupt generation upon pulse width value updated and counter overflow Negative 4 2 freescale 36 4 wire IC support Flexible to interface with external custom line drivers Provide higher bus drive capability e Provide higher noise immunity environment _ Reduced total system BOM SMBus spec v2 compatible 5 bit glitch input filter Range slave address recognition Arbitration lost interrupt with automatic mode switching from master to slave Programmable glitch input filter Low power mode wakeup on slave address match Can be disabled to support traditional 2 wire bi dir y 2 2 Controller Area Network CAN Fully compliant with CAN 2 0A B protocol Automotive proven leading edge CAN controller popular in tough noise EMI environment Receive buffers with FIFO storage scheme Transmit buffers with internal prioritiza
22. d late arrival The third one is Stack pop pre emption Tail chaining operation Highest IRQ1 IRQ2 Interrupt Handling i p Push ISR 2 _ 2 16 Cycles 26 Cycles 16 Cycles Cortex M3 Interrupt Handling i 6 Cycles 12 Cycles Abandon Pop 1 12 Cycles Tail Chaining y 2 gt freescale External Use 21 Interrupt Controller NVIC Late arrival operation Highest IRQ1 Traditional Interrupt Handling 4 4 26 26 16 Cycles 16 Cycles Cortex M3 Er Interrupt Handling lt gt gt 6 Cycles 12 Cycles Tail Chainin e gt freescale External Use 22 Interrupt Controller NVIC Stack pop pre emption operation IRQ 1 IRO 2 Interrupt Interrupt exit exit Interrupt Stacking Unstacking Processing PUSH to stack from stack Unstacking Stack Pop Pre emption 4 2 2 freescale Single cycle GPIO Provide faster response bit banging and software protocol emulation without additional BOM e Up to 50 faster than normal I O e Fast GPIO controller FGPIO have SET CLEAR T OGGLE control for all pins in zero wait states Enabling highest speed I O for efficient I O and peripheral access gt freescale External Use 27 Other Key Features freescale 28 Bit Manipulation Engine The BME is a
23. g system IEC60730 compliant watchdog CRC cost by removing external BOM Safety certified IEC60730 safety S W library 4 p Z freescale uo Kinetis E Series Selling Point Efficiency Fast processing Single cycle 32bx32b ARM Cortex MO Much higher performance than MO and 8 16 bit core MCUs Fast response Nested Vectored Interrupt Controller True hardware interrupt nesting and less interrupt latency than MO and 8 16 bit MCUs Fast response 12 bit x 16ch SAR ADC with 8 entry FIFO Provide faster sampling rate higher resolution and faster response Fast response 2x ACMP with 6 bit DAC Provide over current over voltage protection as well as zero crossing detection for full voltage range Fast response Bit manipulation engine Support bit band on peripherals that extends the core instructions and generates more efficient code Fast response Single cycle fast GPIO Provide faster response bit banging and software protocol emulation without additional BOM freescale to Kinetis E Series Selling Point Application Special BENE Motor control 6 ch 16 bit Flextimer optimized for Make motor control easier motor control with sync to ADC via PDB High drive Up to 8 high drive pins with each Provide direct connection to LED drive circuit supporting 20mA without additional cost Data endurance Up to 256B EEPROM with 500K Provide longer life time of the NVM endurance cycles SMBus
24. hardware block that resides between the platform and E Series Core that allows read modify write operations to be performed on peripheral registers using data stored in the target address Decorated Stores AND OR XOR and Bit field insert BFI Decorated Loads Load and clear one bit LAC1 Load and Set one bit LAS1 Unsigned bit field extract UBF X Core Accesses BME y 4 2 freescale Bit Manipulation Engine BME BME decorated references are only available on system bus transactions generated by the processor core Cortex MO Core CMO Core Platform am we 9 T 10 Port y Note BME can be accessed only by the core 4 2 freescale lt Example Decorated Store Logical AND The data size is specified by the write operation and can be byte 8 bit halfword 16 bit or word 32 bit The core performs the required write data lane replication on byte and halfword transfers 21 20778 1B 17 16 15 14 13 12111 10 8 817 amp b 414 2 1 where addr 28 26 001 specifies the AND operation and mem addr 19 0 specifies the address offset into the peripheral space based at 0x4000 0000 The indicates an address bit don t care Typical operation GPIOA_PDOR amp 0x02 BME operation unsigned long 0 440 000 0x02 4 2 freescale BME vs C code for Bit field insertion with highest speed optimization
25. icated reference manual help user rapid to learn how to use it y External Use 80 kexx lib web build Bw r lar gt L ke06 di sample code quide src common di cpu i r drivers platforms 4 projects KE02 4 KE06 ACMP demo FIFO demo Int demo ADC Poll demo Bitband demo BME demo CAN Nodel demo CAN NodelWithlnt dem 111 Name ACMP demo FIFO demo ADC Int demo Poll demo n Bitband demo J demo Nodel demo 11 CAN NodelWithlnt demo CAN Node2 demo CRC demo di Flash demo FIM Combine demo di FIM DualEdgetapture demo EPWM demo di FIM demo GPIO demo di GPIO OneCycleAccess demo LC Masterlnt demo LC MasterPoll demo LC Slave demo KBI demo PIT demo platinum PMC demo PWT demo o Demo 1 Lab demo for FAT and contain of IrDA accelerometer thermistor SPI communication RTC slip touch down up to switch demo 2 Flash demo 3 Low Power demo 4 BLDC demo 5 RTC calendar with triggering other modules 6 SPI communication 7 Touch sensing with TSS lib demo 8 UART with interrupt demo 9 Fast GPIO demo 10 Flextimer demo 11 PIT demo 12 ADC FIFO 13 ACMP with
26. o initial value known as counter synchronization and update kinds of registers MOD CnV OUTMASK CHnOM with their write buffers and sync two or more 5 Trigger event hardware trigger or software trigger Update point boundary cycle Minimum low boundary FTM counter CNTINH L Men ModO0 Me M M07 2 y a w WU LL Z Init1 2 freescale 5 4 FlexTimer PWM Synchronize with ADC ADC sampling helps to filter the measured current anti aliasing noise free sampling possible when the switch is inactive Conversion at the point when the shunt resistor signal is available Sampling and Average Current Phase Current Shunt Resistor Signals PWM top A PWM Bottom 7 4 AD qm C 777 lt calc 2 A p 9 y 4 2 freescale 52 FlexTimer Fault Protection Channel outputs forced to a safe value when a fault is detected Up to 4 fault control input pins with fault filters able to filter glitches of 15 system clocks wide Manual fault clearing output re enabled only when Fault flag cleared by s w and automatic fault clearing output re enabled when fault input returns to O Automatic fault clearing Manual fault clearing tha of new cycles the of new PMU cycles Fault flag mi 22422 AAA LE rura ume mU dH E With faut
27. ose No CRC transpose CCITT ITU T ADCCP Programmable 16 32 bit Vai SDLC HDL polynomial ITU T 30 e Reverse input and output n d at a Dy b it byte CRC 16 0x1021 0 No Transpose Transpose CRC CCITT only bits in a only bits in Kermit byte a byte reverse XMODE 0x8408 0x0000 No Transpose Transpose XMODEM M only bitsina only bits in Final complement output of bye abe ARC 0x8005 0 0000 No Transpose Transpose ARC zip only bitsina only bits in file byte a byte CRC 32 0x04C OxFFFF Yes Transpose Transpose PKZIP 11DB7 FFFF only bits ina both bits AUTODIN byte and bytes II Ethernet FDDI Analog Comparator ACMP Pin out FIM1 0 SCIO input PTAGO KEIOPC FTIdO CHO SI ii To Ax Capture Function En HXDFE From Internal or External Reference Voltage freescale seau s Periodic Interrupt Timer PIT An array of 32 bit count down to 0 timers that can be used to raise interrupts and triggers KEO2 has two timers in a PIT Each timer can work independently 64 bit timer Two timer can be chained to form a 64 bit timer A timer can be programmed to function in debu iio prog 9 Timer 1 y 4 2 freescale lt EMC Design Guideline for Real Case EMC Performance with Microwave Oven 2 4
28. short ground paths with minimum loop area for other peripheral components around the MCU Use separated ground trace to avoid ESD discharge energy directly inject to MCU ground 4 2 freescale us Fill up a ground plane underneath the MCU and connect all VSS pins together with same potential level Minimize the ground loops by use of the corner points for peripheral components around the MCU Power supply GND 12V GND Avoid the ESD discharge energy injects into the 5V GND directly Z freescale es PCB Layout Recommendation cont Crystal Oscillator Ground Connection Place oscillator circuit components as close as possible to the XTAL and EXTAL pins e Do not place any signal trace near crystal circuit or across the bottom side of the circuit e Connect crystal oscillator load capacitors ground to the common ground plane e Route ground traces in the form of a guard ring along with the traces connecting to the EXTAL and XI AL pins can minimize the noise coupling into the crystal circuit 4 2 freescale lt Layout Example 2 Refer to 4779 2 lt External Use 70 Add guard ring a ground trace with no current flow Connect crystal loading capacitors to a common ground plane Avoid any signal trace near the oscillator circuit or across the bottom side of the circuit Place the oscillator circuit to the EXTAL and XTAL pins as close
29. tion using a local priority concept Flexible maskable identifier filters to receive wanted messages Programmable functionality Wake up with integrated low pass filter Loop back mode supports self test operation Listen only mode for monitoring of CAN bus bus off recovery functionality Separate signaling and interrupt capabilities for all CAN receiver and transmitter error states Warning Error Passive 5 Programmable clock source either system clock or crystal oscillator output Internal timer for time stamping of received and transmitted messages Low power modes Sleep Power Down and MSCAN Enable otubs 1m e Rr CANE E R _ 1200 Twisted pair media 1200 Z freescale Controller Area Network CAN CPU Interface Memory Mapped I O msCAN Receive Transmit Engine Internal Priority Scheduling Global Identifier Filtering or 4 x 16 bit or 8 x 8 bit E freescale External Use 39 4 IEC60730 Safety Standard Class Cert for Household Appliance 60730 safety standard classification Class A Not intended to be relied upon for the safety of the equipment Class B To prevent unsafe operation of the controlled equipment Class C To prevent special hazards IEC 60730 Class B IEC 60730 Class C IEC 60730 32 bit periodic test DSC568XXX MCFS1xx Kinetis DSC568xxx MCFS1xx CPU register test stuck at St
30. uck at stuck at Stuck at Walkpat Walkpat Walkpat es CPU instruction SDI Hine N A N A N A N A instr CPU instr CPU instr test test test test RAM test March X March C MERS Valkpat alkpa Walkpat Flash test CRC 16 bit CRC 16 bit CRC 16 bit CRC 16 bit CRC 16 bit CRC 16 bit Timeout and Timeout and Timeout and Timeout and Timeout and Timeout and Watchdog test reset reset reset reset reset reset reset 2 freescale 40 4 IEC60730 Safety Standard Class Cert for Househoud Appliance e IEC60730 safety standard peripherals Watchdog independent clock source and robust refresh amp protection mechanism provide safety mechanism to monitor he flow of the software Interrupt handling amp execution CPU clock too fast too slow and no clock Cyclic Redundancy Check CRC provides a fast mechanism for Testing the Flash memory Check on serial communication protocols UARTS I2C 4 e freescale External Use 41 Simple Power Mode Core power mode System chip power Mode RUN RUN Sleep WAIT Deep sleep STOP core bus clock 40M 20M Wait mode run code in Flash 20M 20M LE LVD off ADC on 2 freescale External Use 42 core bus clock run code in Flash FEI mode run code in Flash FEI mode enable most modules run code in Flash FEI mode enable most modules while to access 40M 20M 20M 20M clock gating 00
31. ut port 4 2 freescale un Application Note for EMC AN4779 Design Tips for Kinetis E Family AN4438 Design Considerations for 9508 60 AN4476 System Design Guideline for 5V 8 bit families in Home Appliance Applications AN4463 How To Develop a Robust Software in Noise Environment AN2321 Designing for Board Level Electromagnetic Compatibility AN2321 GB Designing for Board Level Electromagnetic Compatibility Chinese Version AN2764 Improving the Transient Immunity Performance of Mircocontroller Based Applications e AN1050 Designing for Electromagnetic Compatibility EMC with HCMOS Microcontrollers e AN1259 System Design and Layout Techniques for Noise Reduction in MCU Based Systems 4 freescale External Use 74 Application Note for EMC AN1263 Designing for Electromagnetic Compatibility with Single Chip Microcontrollers AN1705 Noise Reduction Techniques for Microcontroller Based Systems AN2015 Power On Clock Selection and Noise Reduction Techniques for the Motorola MC68HC908GP32 AN1744 Resetting Microcontrollers During Power Transitions EB413 Resetting MCUs AN1783 Determining MCU Oscillator Start up Parameters EB396 Use of OSC2 XTAL as a Clock Output on Motorola Microcontrollers AN1706 Microcontroller Oscillator Circuit Design Considerations EB398 Techniques to Protect MCU Applications Against Malfunction Due to Code Run
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