PDF version - ARM Information Center
Contents
1. Signal Direction Width Note USER RESETn input HPE RESETn input DUT CLK1 input AHB system clock input DUT CLK4 input Video Pixel Clock input DUT CLK10 input Peripheral reference clock input DUT CLK13 input AACI bit clock input x2 DUT CLK100M input Reference 100MHz input DUT PLL B1 CLKOUTS3 output 25MHz reference clock from FPGA PLL DUT PLL R2 CLKOUTO output AACI 24 576MHz bit clock x2 from FPGA PLL DUT PLL T1 CLKOUTS3 output Video Pixel Clock from FPGA PLL Table 15 Clocks and Resets 6 2 Processor Interface This interface contains the 32bit AHB Lite bus from the processor to the peripherals together with interrupts to the processor and sideband signals between the processor and peripherals FPGA Signal Function Note FPGA IC 31 0 HWDATA 31 0 FPGA IC 32 HWRITE FPGA IC 35 33 HBURST 2 0 FPGA IC 36 HMASTLOCK FPGA IC 40 37 HPROTT S 0 FPGA IC 43 41 HSIZE 2 0 FPGA IC 45 44 HTRANS 1 0 FPGA IC 46 HSEL Not used driven high by the CPU FPGA FPGA IC 78 47 HADDR S1 0 FPGA IC 110 79 HRDATA 31 0 FPGA IC 111 HRESP FPGA IC 112 HREADY FPGA IC 113 HRESETn FPGA IC 125 114 INT 11 0 Interrupt signals to processor L14 DUTOUT DN 1 1 0 INT 23 12 Interrupt signals to processor L14 DUTOUT DN 12 NMI Non maskable interrupt to processor L14 CPUOUT DN 0 SLEEPING L14 CPUOUT DN 1 SLEEPDEEP L14 CPUOU2. celles ieeeeeeseeen eene 13 Figure 12 Timing Diagram of the DChus ees NREEEEEEREEEEEEREEEEE seen enne esent n ensi nnm r nnmnnn mnane nnmnnn mnnn nn nn tnra 14 Figure 13 Top level directory structure eulieieeeeeeeee ee eiieeeeeeseseeeseeee nnne nns n ns nn nn nita na nnne nnmnnn snnt 18 Figure 14 peripherals directory structure lleeeeeeeeesiieieeeeeeieseseiieeeen nnne NEE nn snnt nna NEE EEEEEEEEE nana nn nnn 19 Figure 15 fpgu dut directory structure uleleeeeeeeeeeeiiiieeeeseiseeseseeenn nene s nnn REENEN EE nitens nass n nnn 20 Figure 16 Top level directory structure uleeleeeeeieeeeeiieeeeeesesseeseeee einn nn nns n ns REENEN nass nnne EENEG 27 Figure 17 BootMonitor directory structure lleeeeeeeeesiieieeseeeieeeseeee nennen nena nn nnmnnn nenn nasa ns sn sn nnt nnne 33 Figure 18 Selftest directory structure eeeeeeee ee eiie ee es seeeeee essen nennen nnne nnne nnn nnne mnane nnmnnn sn sn nnns sn nnns 35 Figure 19 Video DDR interface c ececeeeeeeeeeeeee ee eeen eens eeeeee seen sana neeeeeee see ea nn nita ENEE sane nnt nnmnnn sana sans nnn 39 Fig re 20 HUMI DT E 40 Figure 21 MCI Hu ycldHe le e EE 42 Figure 22 2C ConnectlOns 5 ccc costes ccce ea eo tc cenae oc ce saco te ctu
3. 3 3 1 6 25MHz Counter SYS CNT25MHz Name Rest Note Count25MHz 31 0 PO h00000000 Free running counter from 25MHz clock 3 3 1 7 100Hz Counter SYS CNT100Hz Count100Hz 31 0 RO h00000000 Free running counter from 100Hz clock 3 3 2 ADC DAC lC The DS702 peripheral is used for the interface and implements a bit banging method for the C interface The base address for this peripheral is 0x4000_B000 Refer to 2 for further details Register SB CONTROL h0000 R b Status Register of UO signals SB CONTROLS h0000 W b00 Set Output bits SB CONTROLC h0004 WO b00 Clear Output bits 3 3 2 1 SB Status register SB CONTROL Name s Access Rest Note Reserved B2 SB_SDA data wire 1 RO bo Level of SDA signal Application Note 227 Copyright 2009 ARM Limited All rights reserved 13 ARM DAIO227A Programmer s Model SB_SCL clk wire 0 Joo mp Level of SCL signal 3 3 2 2 SB Set register SB CONTROLS Name Bis Dese Reset Noe Reseed w2 JI SB nSDAOUTEN 4 w bo Sets SDA line when 1 SB_SCLOUT o W bo Sets SCL line when 1 3 3 2 3 SB Clear register SB_CONTROLC Name is Weess Best Nol OC Oo Reser pe D SB nSDAOUTEN Wm OeesSDAlnewheni O O sB scLoUT o W o OeasSCLinewheni 3 3 2 4 Basic Timing The basic IC Inter Integrated Circuit timing diagram is shown in Figure 11
4. MEM DDR2 RASn output MEM DDR2 WEn output MEM DDR2 CSn output 1 0 MEM DDR2 ODT output 1 0 MEM DDR2 CKE output 1 0 MEM DDR2 CLKP output 1 0 MEM DDR2 CLKN output 1 0 MEM DDR2 DM output 3 0 MEM DDR2 DQSN bi dir 3 0 MEM DDR2 DQSP bi dir 3 0 MEM DDR2 DQ bi dir 31 0 MEM VAR bi dir 23 0 Table 26 Memory Childboard Connections 6 12 Ethernet Phy Interface This interface is not driven in the example design supplied but goes directly to an Ethernet Phy Intel LXT971A for the user to add their own design It implements an MII interface between the FPGA and Ethernet phy Signal Direction Width Note ETH COL input ETH CRS input ETH MDC output ETH MDIO bi dir ETH MDINTRn OD ETH RESETn bi dir ETH RXCLK input ETH RXD input 3 0 ETH RXDV input ETH RXER input ETH TXCLK input ETH TXD output 3 0 ETH TXEN output ETH TXER output Table 27 Ethernet Phy Connections 6 13 CAN Interface This interface is not implemented in the example design supplied but is connected to a PHY NXP TJA1040 for the user to add their own design Signal Direction Width Note CAN_RXD input CAN_TXD output CAN_STB input Table 28 CAN Connections 6 14 Flexray Interface This interface is not implemented in the example design supplied but is connected to a PHY NXP TJA1080 for the user to add their own design Signa
5. define ARM MPS INCLUDE AACI This includes the Primecell PLO41 Audio Codec interface define ARM MPS INCLUDE MCI This includes the Primecell PL181 MMC SD interface define ARM MPS INCLUDE DMC This includes the DDR memory interface user supplied If these components are not included then the video and LCD controller does not have any route to memory so the address out of the video and LCD controller block is connected to the read data bus giving a static image on any screen attached to that interface define ARM MPS DUT SYS ID REG This is the value shown in the SYS ID register see section 3 3 1 1for details Table 4 System Configuration 4 2 3 By default the audio codec and MMC SD card interfaces are implemented and the DMC and CLCD are not implemented By un commenting or commenting the defines the system configuration can be altered Building the FPGA image To rebuild the image and download to the MPS the Altera Quartus II tools version 8 1 or later and the Hpe amp desk application need to be installed on the PC being used Please refer to the MPS QuickStart guide for details on installing these Once the software is installed the example system FPGA image can be rebuilt by running a single batch script This script invokes the Altera Quartus Il tools to perform both synthesis and place and route functions Once this script has completed the FPGA image file fpga dut sof can
6. 0x4000 F000 0x4000_E000 0x4000_D000 0x4000 C000 0x4000_B000 0x4000_A000 0x4000_9000 0x4000_8000 0x4000_7000 0x4000_6000 0x4000_5000 0x4000_4000 0x4000_3000 0x4000 2000 0x4000 1000 0x4000 0000 CPU FPGA 0x4000 5000 0x4000 401C 0x4000 4018 2 0x4000 4014 0x4000 4010 0x4000_400C 0x4000_4008 0x4000_4004 0x4000 4000 3 3 DUT FPGA Registers 3 3 4 System Registers The DUT specific registers are mapped to a 16KB area at 0x4000 4000 The addresses in this section are all relative to this base address Reset Note h00000000 Sets LED outputs 0 0 Register Offset i RO z S RO SYS CNT2SMHz Ind HO SYS CNTi00Hz hoors HO RO Ro 3 3 1 1 ID register SYS ID h00000000 Free running counter incrementing at 25MHz h00000000 Free running counter incrementing at 100Hz oard Revision B h023 HBI Board number Name s Application Note 227 ARM DAI0227A Copyright 2009 ARM Limited All rights reserved 11 Programmer s Model VARIANT 15 12 RO h Build Variant of board ARCH 118 P h4 s Architecture 4 AHB BUILD pro RO D FPGA build 3 3 1 2 Peripheral configuration SYS PERCFG Name Bis Access Reset Noe Reseved Biig USB FORCE SLOW RW 50 Forces tne USB interface to operate sowy 000 USB_DC_WAKE Status of USB Device Controller Wake Suspend signal ER 5b
7. 2 22 22 11 eaaa taare Eege rus re acce sd Espana E Fd ac Du PO ne ve Sad mw aae aa DL anc 20 Clock and reset settings inei eter cien ire ease Lea EES 25 EXAMPLE SOPT WAR lc 27 BootMonitor ois eran ee Lies uestes d n LE Ls LU 27 fr Me DE EI ers EE 33 EXTERNAL INTERFACE EE deed dere 37 icai RP E 37 Processor Interface one dete inedit ee 37 Video ll ne 38 H man Interface nube AEE EE niin uil alae Role DII II ae et 39 FPGA Configuration connections eeeeeeeseseeeeeseeeeee eese enne nnnm nnn nn nnn ta sain sant n nsn nn assa sas nunnan anneanne 41 SEMULAT OR CONMCCUUONS mee 41 USB ilintertace moe DC EC C E 41 Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A 6 8 Multi Media SD Card Interface neces incessus cece te asseaaseceeece sas suascadetecaddadaeds CO cn aca SeegE ENEE GS RR ENG 42 6 9 Audio AC97 Interface uer EEN dese EE 43 6 10 AD amp D A Interface 2 1er cecinere eddie Leider eid ener eee EEN uua unde eed dan aci SEENEN NENNEN 43 6 11 Memory DDR Interface dei nde ia dle wha eden uini d elie i iilres 43 6 12 Ethernet Phy Interlace scinsioni anana ECKER EES seenaetecestaceesvenceteveccen raa pinna 44 6 13 CAN Interface eege EE EE 44 6 14 Plexray interface nasrini niunia aaia idee ecc
8. CPU PLL T1 CLKOUT3 ol 000000000000 OOOOOOOOOO00SG 00000000000 000000000000 Board Data and Configuration Read Board Data Auto Refresh Board Data Use Spread Spectrum Clock Synthesize and Download Clock Settings Synthesize ClockFactory Design Log Info Details Warnings The Hpe amp desk application has now been configured to connect to the MPS and downloading of FPGA images can now be done 4 2 5 MPS FPGA image download volatile Downloading directly to the FPGA is the fastest method to configure but is a volatile download and once the power to the MPS is removed the downloaded image is lost and the non volatile image is used on power up It is recommended to try new designs using this method before committing to a non volatile download To download a volatile image to the MPS perform the following from the Hpe amp desk application Select from the drop down menus ClockFactory gt Download sof file to System FPGA Application Note 227 Copyright 2009 ARM Limited All rights reserved 23 ARM DAI0227A FPGA Design BS Hpe desk HMALC AS3 50 ClockFactory File Settings Ke a M Automation Window Help P Read Board Data via JTAG Diagnosis od ClockFactory Setting Save ClockFactory Setting Use as Default ClockFactory Setting SYS F Open ClockFactory Documentation for Current Module Synthesize ClockFactory Design Download ClockFactory Design Unconfigure C
9. Programmer s Model 3 3 4 3 3 5 3 3 6 3 3 7 3 3 8 3 3 9 3 3 10 3 3 11 Video Timer RTC WatchDog This is a user supplied component with basic interfaces brought into the DUT FPGA to enable implementation The DVI I controller device Chrontel CH7302 uses an lC serial bus for configuration this is implemented in the CPU FPGA using the DS702 The example clock source for the video pixel clock is derived from the PLL in the DUT FPGA and drives a clock input of the DUT FPGA CLK4p via the clock factory The clock source is set by the Hpe Desk application on the PC and the frequency is determined by the PLL implemented in the DUT FPGA For further data on the video encoding see the Datasheet for Chrontel CH7302 7 The SP804 ADK component is used for the timers See the TRM for details about its functionality 8 The Timer clock is set at 1MHz and is derived from the 100MHz clock The combined interrupt is used so each SP804 implementation only has 1 interrupt output see section 3 1 The PL031 PrimeCell is used as the RTC See the TRM for details about its functionality 9 The RTC clock is feed from the RTCCLK signal and is 1Hz and is derived from the 100MHz clock The SP805 ADK component is used for the watchdog See the TRM for details about its functionality 10 The clock is set at 1Hz and is derived from the 100MHz clock Dynamic Memory Controller This is a user supplied component with basic i
10. data sheet ii Copyright 2009 ARM Limited All rights reserved Change history Issuer Gleichmann Industries Gleichmann Industries Gleichmann Industries Altera Corporation Elsevier by Joseph Yiu ARM Ltd Chrontel ARM Ltd ARM Ltd ARM Ltd ARM Ltd ARM Ltd ARM Ltd ST NXP Wireless Application Note 227 ARM DAI0227A Proprietary notice ARM ARM Powered StrongARM Thumb Multi ICE ModelGen PrimeCell PrimeXsys RealView TrustZone Jazelle ARM7TDMI ARM9TDMI ARMulator AMBA and The Architecture for the Digital World are registered trademarks of ARM Limited Cortex AXI AHB ARM7 ARM7TDMI S ARM7EJ S ARM720T ARM740T ARM9 ARM9TDMI ARM920T ARM922T ARM940T ARM9E ARM9E S ARM926EJ S ARM946E S ARM966E S ARM968E S ARM996HS ARM10 ARM1020E ARM1022E ARM1026EJ S ARM11 ARM1136J S ARM1136JF S ARM1156T2 S ARM1156T2F S ARM1176JZ S ARM1176JZF S EmbeddedICE EmbeddedICE RT AMBA ARM Development Suite ETM ETM7 ETMS ETM10 ETM10RV ETM11 Embedded Trace Macrocell Embedded Trace Buffer ETB ETB11 Embedded Trace Kit Integrator JTEK Mali MultiTrace MPCore MOVE OptimoDE AudioDE SecurCore SC100 SC110 SC200 SC210 Keil p Vision ULINK are trademarks of ARM Limited Java is a trademark of Sun Microsystems Inc XScale is a trademark of Intel Corporation All other brand names or product names are the property of their respective holders ARM is used to represent ARM Holdings
11. 30 Table 31 vi DUT to CPU FPGA video signals eee eeeeeeiies sien nien e nennen nina sinn n nnnm enana stans snas annu nna 38 Video and LCD Connections oec ac caso ds ta ca vec G nuca usui ta comu uS nn Qu pad de aG enc eauetcceteatencbedeecadeleateossedaes 38 H mian le CTT 39 FPGA configuration Connections eeeeeeeeee eiie eiees eiie nennen en nn asina snnm ann tn nasi nasa nunnan anneanne 41 SemulatOr Connections cosa coic teas coco an en cu secede De cC eon aqu aaant raae rcu Cnr c aD epe FAR a aeaea e INA TNR RIO GnSEn A sees 41 BE MenDDIITB HHLIERCRORNEDDOTOIOEODUCOOEEIO DIL 42 SDGard GonnecLliOnhs o coctesseacsas va cona cosadvcacedactetee acaesccatauesnce DR NOR Carn dae En AR TOSCRUR Rad INANE ae iadaaa ainat EE 42 AG97 Gonneclions ensi cccc dete ciedencdccctnadesscdancoceanduddcaddenacaucondsdsacceecd agus aadauscecnaccucasadeceecacncedta ies 43 A D amp D A Connections geg ees EA REENEN ceacccucadsensdecced Suse aasdmuceeuacaaus sdauuaceludacudeaadnc 43 Memory Childboard Connections c ecccsceeseseeeseeeeneeeeeeeeeeseaesenaeeeneeeeseeeesaesaneeeenseeeseeeseseaesaseeeenseees 44 Ethernet Phy Connections inci SEENEN 44 GAN GCONMMECUIONS ERN IEEE 44 Flexray COmnections ii sic E 45 LIN GOMMOECTIONS RH ERI 45 RS232 Ere aT Ie LOTION ME 45
12. Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A Introduction 1 Introduction The Keil Microcontroller Prototyping System MPS enables evaluation and prototyping of ARM Cortex M class processors and user defined peripherals in a single product The MPS is the first prototyping system incorporating a full speed Cortex M class processor implemented in FPGA which can be integrated with third party peripheral IP to deliver a prototyping system for hardware and software application development The MPS enables the implementation a Cortex M class system without needing to have access to the processor RTL meaning different processors can be benchmarked in order to choose the most suitable for the intended devices price performance Additionally the MPS is delivered fully configured with the Cortex M processor and is fully tested so that the user does not have to test the processor implementation and can immediately begin adding third party IP or writing software 1 1 Purpose of this application note The application note explains the example DUT FPGA design how to rebuild it and program it into the MPS It will guide you through and explain the 1 Architecture of the system e How the components are interconnected e Clock and reset structure 2 Programmers model e Interrupt assignment e Memory map e Peripheral register descriptions 3 FPGA design e Structure and directory format e Rebuilding the F
13. be download to the DUT FPGA using the Hpe amp desk application The files in the scripts directory fpga_dut physical MPS_dut altera scripts perform the functions described in Table 5 FPGA scripts Filename Note Build bat Windows batch file to rebuild the FPGA image in the netlist directory fpga dut qpf Quartus II project file This should not be altered fpga dut qsf Quartus II TCL script It defines the FPGA pin assignment instantiation of pullup or down resistors files to be synthesised This will require changes when modifying the DUT FPGA design and adding or removing peripherals fpga_dut sdc Defines the timing constraints for the design and is configured to ensure operation with the example peripherals and processor CPU FPGA This will require changes when modifying the DUT FPGA design and adding or removing peripherals Table 5 FPGA scripts Application Note 227 ARM DAI0227A An explanation of the files contents in Table 5 FPGA scripts is beyond the scope of this application note and reference to the Altera Quartus II documentation is advised for details on the commands and structure of the files To build the FPGA image perform the following tasks 1 Run the build bat file from the fpga_dut physical MPS_dut altera scripts directory 2 Check the FPGA image has been created by looking for the file fpga_dut sof in the foga_dut physical MPS_dut altera netli
14. e Switches buttons and 7 segment displays e Location of the FPGAs CPU and DUT e IDC ribbon cables for selection of RS232 CAN LIN Flexray e Childboard connector for user expansion e JTAG and Trace Mictor connection for debug JTAG SWD e e dine matt Trace Mictor connector DUT User Buttons 12V power to HMALC AS3 DUT User Switches Same as on front panel CPU User Switches 7 4 CPU User Switches 3 0 p Switch no 1 2 3 and 4 marked on the package map to CPU User Switches 0 1 2 and 3 Character LCD interface DUT 7 Segment display Figure 4 Microcontroller Prototyping System Inside 4 Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A Hardware Description 2 Hardware Description This application note explains the example AHB AMBA 2 0 system implemented on the MPS This board contains two FPGAs e The CPU FPGA An ARM Cortex M class processor with debug and trace support depending on the processor two memory controllers to operate interfaces to the noBLRAM and FLASH NOR RAM on the board Touchscreen SPI and Video configuration C peripherals and a configuration register block This design is processor specific and more details can be found in the relevant application note e The DUT FPGA Containing an example system including timers display drivers an audio interface and an MCI SD card interface 2 4 Block Diagram Figure 4 shows how the two FPGAs ar
15. in Figure 2 fitted with Reset button LCD character display 2 rows by 40 characters 4 press buttons to the DUT FPGA 8 LEDs from the CPU FPGA 8 LEDs from the DUT FPGA LEDs to show if the FPGAs are over temperature LEDs to show status of the power supplies LEDs to show FPGAs configuration status USB OTG connector for configuration programming Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A Introduction TOARRE UU Wu Figure 2 Microcontroller Prototyping System Front Panel The rear panel as shown in Figure 3 has the following features e Power connector and switch e USB Host and OTG ports e SDCard slot e RS232 CAN LIN FlexRay connections e 10 100 Ethernet RJ45 interface e RGB video output port DVI A connector e RS232 ports e Childboard expansion slot red plastic plates e Audio line in and line out e JTAG SWD connector for ULINK 2 and other ARM debug hardware e External clock source not supported at present e Analogue port not supported at present JT AG for BootMonitor Console Debug CAN or FlexRay or RS232 x ani gt f 27 7 1 22 a E Ethernet CLK RS232 1 RS232 2 DVI I ine tine 7 SUE T m SD Card 12V PWR USB Figure 3 Microcontroller Prototyping System Rear Panel Application Note 227 Copyright 2009 ARM Limited All rights reserved 3 ARM DAI0227A Introduction The inside of the MPS as shown in Figure 3 shows the
16. or submenu List commands Alias for EXIT Resets this system If the optional IF REQUIRED qualifier is specified the system will only be reset if there has been a configuration change made that requires a reset Sets UART port gt to the specified rate e g SET BAUD 0 9600 available ports 0 4 Sets system date in the form dd mm yy Sets system time in the form hh mm ss Table 9 Configure Submenu 5 1 2 3 Debug Submenu Command Format DEPOSIT address value size DISABLE MESSAGES ENABLE MESSAGES EXAMINE address lt size gt EXIT GO lt address gt HELP lt command gt MODIFY lt address gt lt value gt lt mask gt size QUIT Note Deposit value lt value gt to memory at lt address gt optionally specifying the size it can be BYTE HALFWORD or WORD defaults to WORD Disables debug messages Enables debug messages Examine memory at lt address gt for lt size gt number of bytes Exit Run code at lt address gt List commands Performs a read modify write of memory at lt address gt combining in with lt value gt which will be masked with lt mask gt The size of the transfer can be optionally specified it can be BYTE HALFWORD or WORD defaults to WORD Alias for EXIT 30 Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A Example Software START TIMER Starts a timer which is stopped with the ST
17. plc LSE ARM and NASDAQ ARMHY its operating company ARM Limited and the regional subsidiaries ARM Inc ARM KK ARM Korea Ltd ARM Taiwan Limited ARM France SAS ARM Consulting Shanghai Co Ltd ARM Belgium N V AXYS Design Automation Inc ARM Germany GmbH ARM Embedded Technologies Pvt Ltd ARM Norway AS and ARMSweden AB Neither the whole nor any part of the information contained in or the product described in this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder The product described in this document is subject to continuous developments and improvements All particulars of the product and its use contained in this document are given by ARM in good faith All warranties implied or expressed including but not limited to implied warranties of satisfactory quality or fitness for purpose are excluded This document is intended only to provide information to the reader about the product To the extent permitted by local laws ARM shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information Confidentiality status This document is Open Access This document has no restriction on distribution Feedback on this Application Note If you have any comments on this Application Note please send email to errata arm com giving e the document title e the document number e the page nu
18. table USB HC WAKEUPn bi dir Not connected in this design Table 22 USB Connections 6 8 Multi Media SD Card Interface This interface is driven by the Primecell PL181 see section 3 3 12 and is connected to the MM SDCard connector on the rear panel Signal Direction Width Note SD SCLK output Driven by MCICLKOUT SD CD input See Figure 18 SD WHRP input See Figure 18 SD IRQ bi dir See Figure 18 SD CSn bi dir See Figure 18 SD DAT bi dir See Figure 18 SD DI bi dir See Figure 18 SD DO bi dir See Figure 18 Table 23 SDCard Connections Tri stated driver MCIDATIN 3 0 nMCIDATEN MCIDATOUT 3 0 gt Tri stated driver SD_CSn SD_DAT SD_IRQ SD_DO nMCICMDEN MCICMDOUT gt SD_DI MCICMDIN rm MCICLKOUT SD CLK MCIFBCLK PullUp Pulled down when card MCICARDIN SD CD present MCIWPROT SD WRP PullUp Pulled down when Write protected Figure 21 MCI interface connections 42 Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A External Interfaces The nCARDIN and WPROT signals are feed to the peripheral system registers for use as setting interrupts and detecting the status of the signals 6 9 Audio AC97 Interface This interface is driven by the Primecell PL041 see section 3 3 11 and connects to the AC97 Codec National Semiconductor LM4549B which has implemented the Line in line out on the rear pane
19. the program image into the debugger selftest MPS axf each of the MPS peripherals may be tested individually or altogether using Run all tests The tests perform register level and basic functional tests on the MPS hardware reporting any errors found The source code for the tests are brought together in a single project file build Build_Keil selftest_MPS Uve2 The source code for each peripheral test is split into separate directories for example apaaci contains apaaci c and apaaci h for testing the AACI peripheral The main folder contains main c and common c which provide the user menu and functions that are common to all peripheral tests Note If the default install directory is not used then the project will have to be rebuilt in order for the debugger to display the source code automatically Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A software projects selftest apaaci apcharlcd apcicd apdma apgpio apic apkybd apleds apmem apmmci apmouse aprtc apsbi apssp apswitch aptimer aptsci apuart apusb build Build keil Build RVDS main Executable image and scripts to rebuild with MDK Executable image and scripts to rebuild with RVDS Figure 18 Selftest directory structure 5 2 2 Selftest test hardware Application Note 227 ARM DAI0227A Example Software The MPS test code requires three separate cable assemblie
20. 4 2 6 MPS FPGA image download non volatile Downloading to the Flash memory is a slow method but is non volatile and the image is reloaded on power up It is recommended to use this when the design is stable To download a non volatile image to the MPS perform the following from the Hpe amp desk application 24 Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A FPGA Design Select from the drop down menu ClockFactory gt Download to System Flash Memory ZSHpe desk HMALC AS3 50 ClockFactory File Settings Keys i M Automation Window Help Read Board Data via JTAG Load ClockFactory Setting Save ClockFactory Setting Use as Default ClockFactory Setting Open ClockFactory Documentation for Current Module Synthesize ClockFactory Design Download ClockFactory Design Unconfigure ClockFactory CPLD ClockFactor Clear ClockFactory Synthesis Cache n Download sof file to System FPGA pues BEE c o ES Erase System Flash Memory o HEU Download sof file to Processor FPGA ax er Download to Processor Flash Memory CLKF_CLK1C Erase Processor Flash Memory DUT PL RZ CLKOUTU 23 58 MHz DUT PLL B1 CLKOUT3 CLKF 25 00 MHz DUT PLL T1 CLKOUT3 CLKF 25 00 MHz CPU PLL L2 CLKOUTO 25 00 MHz CPU PLL R2 CLKOUTO 50 00 MHz CPU PLL B1 CLKOUT3 33 33 MHz CPU RL T1 CLKOUT3 40 00 MHz oo0oo0000q o0o000000000 000000000000 Board Data and Configuration Read Board Data Auto Refresh Board Data Us
21. Application Note 227 Using the Microcontroller Prototyping System with the example reference design Document number ARM DAI0227A Issued August 2009 Copyright ARM Limited 2009 ARM Application Note 227 Using the Microcontroller Prototyping System with the example reference design Copyright 2009 ARM Limited All rights reserved Release information The following changes have been made to this Application Note Date Issue Change August 2009 A First release Version controlled by Domino Doc DS158 GENC 009799 0 2 References Document 1 User Manual for HMALC ASS 52 2 User Manual for Hpe midi V2 3 HPE Desk Basic Online Help 4 Altera Double Data Rate I O Megafunctions User Guide 5 The Definitive Guide to the ARM Cortex M3 ISBN 978 0 7506 8534 4 6 PrimeCell Synchronous Serial Port PLO22 Technical Reference Manual 7 CH7303 HDTV DVI Transmitter CH7303 Data Sheet 8 ARM Dual Timer Module SP804 Technical Reference Manual 9 PrimeCell Real Time Clock PL031 Technical Reference Manual 10 ARM Watchdog Module SP805 Technical Reference Manual 11 PrimeCell amp UART PLO011 Technical Reference Manual Revision r1p5 12 PrimeCell amp Advanced Audio CODEC Interface PLO41 Technical Reference Manual 13 ARM PrimeCell Multimedia Card Interface PL181 Technical Reference Manual 14 ISP1761 Hi Speed Universal Serial Bus On The Go controller Rev 05 13 March 2008 Product
22. OP TIMER command STOP TIMER Stop a timer pervious started with the START TIMER command and displays elapsed time Table 10 Debug Submenu 5 1 2 4 Flash Submenu Command Format Note DISPLAY IMAGE lt name gt Display details of image lt name gt ERASE IMAGE lt name gt Erases image or binary file from flash ERASE RANGE lt start_address gt It is only possible to erase entire blocks of flash Therefore lt end_address gt the entire block of flash that contains lt start_address gt the block that contains lt end_address gt and all intervening blocks will be erased This may mean that data before lt start_address gt or after lt end_address gt will be erased if they are not on block boundaries If the optional lt end_address gt parameter is not specified then only the single block of flash that contains lt start_address gt will be erased EXIT Exit HELP List commands LIST AREAS List areas of flash where an area is one or more contiguous blocks that are of the same size and use the same programming algorithms LIST IMAGES List images in flash LOAD lt name gt Load image lt name gt from flash QUIT Alias for EXIT RESERVE SPACE address Reserves space in flash for user applications that the boot size monitor will not use RUN name Load image name from flash and run it UNRESERVE SPACE address Unreserves pervious reserved space in flash Application Note 227 Co
23. PGA image e Configuring Hpe amp desk and MPS e Programming the MPS with the new image 4 Example Software e BootMonitor e Selftest 5 Modifying the design e Connecting to the outside world e FPGA pin signal assignments 1 2 Overview of the hardware platform The MPS was developed with two FPGAs to give the maximum flexibility for user prototyping while maintaining IP protection of a Cortex M class processor to allow wide customer accessibility without the need to license the processor The use of the two FPGAs allows the microcontroller debug and memory subsystem to be implemented in Application Note 227 Copyright 2009 ARM Limited All rights reserved 1 ARM DAIO227A Introduction an encrypted and secure FPGA CPU and the user design with access to the peripheral interfaces to be implemented in the non encrypted FPGA DUT An AHB Lite interface from the CPU FPGA to the DUT FPGA together with interrupts and other sideband signals allows the DUT FPGA to interact with and be controlled by the microcontroller as if it were a single System on Chip Implemente des oo Not Implemented e Hpe _midiv2 Base Board UART Switches LEDs Char LCD Switches LEDs 7SEG Ethernet CAN SE LN HMALC AS3 Processor Board Trace Debug CPU FPGA UARTS AC97 SD MMC TC Video secce seccescs D SMB SP Figure 1 Architecture The MPS has a front panel as shown
24. T DN 2 HALTED L14 CPUOUT DN 3 LOCKUP L14 CPUOUT DN 4 TXEV L14 CPUOUT DN 5 RXEV L14 CPUOUT DN 6 WDOGRES L14 CPUOUT DN 12 7 N C L14 CPUOUT DP 9 0 N C L14 CPUOUT CLK N C Table 16 Processor interface Application Note 227 Copyright 2009 ARM Limited All rights reserved 37 ARM DAI0227A External Interfaces 6 3 Video Interface The interface to the Video and LCD displays is driven by the processor FPGA although the peripheral is in the DUT FPGA The CPU FPGA acts as a pass through for the video LCD signals and will also de multiplex the data for the LCD display FPGA Signal Function Note L14 DUTOUT DPT11 0 Video RGB 1 1 0 DDR 24bit RGB video signals clocked by VIDEOCLK L14 DUTOUT DP 12 Video Resetn Video Reset active low L14 DUTOUT CLK PCLK Video Pixel clock L14 CPUOUT DPT 10 VSync Video vertical sync pulse L14 CPUOUT DPT 1 1 HSync Video horizontal sync pulse L14 CPUOUT DP 12 DE Video data enable strobe Table 17 DUT to CPU FPGA video signals The multiplexed DDR interface is used to drive the video data via the CPU FPGA to the video transmitter device Chrontel CH7302 The signals from the FPGA video inputs are mapped to the video outputs as follows Function L t ane Wide Man Noe video ROBO VIDEO 70 Red Data DDR encoded faling edge 7 VideoRGB 18 VIDEO M 8 Green Data DDR encoded rising and Taling edge VideoRGB 0
25. The ACK is a returned value from the target device responding to a data burst being received SDA MSB X H d LSB ACK SCL Start Stop Figure 12 Timing Diagram of the I Cbus 3 3 3 Character LCD The Character display component is the DS700 and interfaces to the industry standard Hitachi HD44780 controller It uses 11 signals 8 data 1 strobe E read write RnW and Register data select RS Note the interface can be a 4 bit or 8 bit interface For this application it is in 8 bit mode Note When the display is used with a 4 bit interface an 8 bit value has to be written read as two consecutive nibbles writing reading bits 7 4 first into register bits 7 4 then d bits n into register bits 7 4 Register CHAR COM Se Access Rese SORT A write will write to the display controller command register A read will initiate a status register access returns value later in CHAR RD CHAR_DAT h0004 RW h00000000 JA write will write to the display controller data register A read will initiate a data register access returns value later i in CHAR RD em fear e quem oe S read when CHAR RAW 8 is set parr erp ms BEE to bit 8 clears bit completes em erer Bees CHAR MASK 3 3 3 4 Character Command Register CHAR COM 14 Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A Programmer s Model Die 0 RW h00000000 JA write will write to the displ
26. VIDEO Z0 Blue Data DDR encoded rising edge SCS Video RGB 7 0 CD TTL B 5 0 R Blue Data MSB s demux ed by CPU FPGA Video Resetn V e O EOE DECHE Hot Plug interrupt Not Used SCS VIDEOMODE Video Mode GPIO pin of video chip Not Used VIDEO EC SC Video Chip configuration bus controlled by CPU FPGA VIDEO I2C SbA Video Chip configuration bus controlled by CPU FPGA LCD BLON Back Light On output tied to 1 on CPU FPGA LCD VDON LCD Power On output tied to 1 on CPU FPGA Table 18 Video and LCD Connections L fea CE Video RGB 11 8 LCD TTL G 50 Green Data MSB s demux ed by CPU FPGA L IMIDEORESETn 38 Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A External Interfaces L14 DUT OUT DPT 12 0 D QR DR o Es L14 CPU OUT DP 12 10 m o ua VIDEO RQF E A NA VIDEO CLOCK IN ra VIDEOCLK Clock Buffer 1 b0 DF mE DR G X i LCD TTL Figure 19 Video DDR interface 6 4 Human Interface The Human Interface HUMI multiplexes the LED s 7 Segment displays and character LCD together and drives them over the interface to the relevant devices Signal Direction Width Note BUTTON input 4 DUT DSW input 4 DUT HUMI An bi dir DUT HUMI Bn bi dir DUT HUMI Cn bi dir DUT HUMI Dn bi dir DUT HUMI E
27. Y BOOTSCRIPT ECHO text EXIT FLASH HELP lt command gt LOAD image MKDIR directory path QUIT RMDIR directory path RENAME lt file1 gt lt file2 gt RUN lt image gt SDCARD SET BOOTSCRIPT lt script gt TYPE lt file gt List files in lt directory gt Display the current boot script Prints string lt text gt Exits the application or submenu Enter Flash Submenu Provides help information on command If command is not specified then all available commands are listed Loads image lt image gt into memory Creates a new directory at the end of the given path Alias for EXIT Removes a directory at the end of the given path Renames file lt file1 gt to lt file2 gt Load image lt image gt into memory and run it Enter SDCard Submenu Set the current boot script This script will be run at system reset if the run boot script switch is set Displays file lt file gt Table 8 Main Menu Application Note 227 ARM DAI0227A Copyright 2009 ARM Limited All rights reserved 29 Example Software 5 1 2 2 Configure Submenu Command Format DISPLAY DATE DISPLAY HARDWARE DISPLAY TIME EXIT HELP lt command gt QUIT RESET IF REQUIRED SET BAUD port gt rate SET DATE lt dd mm yy gt SET TIME hh mm ss Note Displays the current system date Display hardware information Displays the current system time Exits the application
28. ay controller command register A read will initiate a status register access returns value later in CHAR RAW and CHAR RD 3 3 3 2 Character Data Register CHAR DAT Ser GE See Rest Noe ea o m a DATA 7 0 RW h00000000 JA write will write to the display controller data register A read will initiate a data register access returns value later in CHAR RAW and CHAR RD 3 3 3 3 Character RD Register CHAR RD EE READ 7 0 n00000000 bosseg dm has IG GHAR GON CRAB data from last CHAR_COM or CHAR_DAT read when DONE is set 3 3 3 4 Character Command Register CHAR RAW BEE DONE RW SI WT indicates if access is complete Writing 0 ipm CR RR CR RR RSEN bit Reserved Jm Rw mm Note If a transaction is attempted before DONE is asserted ot EET register by the controller then it may be ignored and the command data transfer could be lost Once DONE is asserted it can be cleared and a transaction started 3 3 3 5 Character Interrupt Mask Register CHAR_MASK anes en a 4 MASKINT RW EE to 1 will generate interrupt when access completes CHAR DONE set 3 3 3 6 Character Status Register CHAR STAT Sen Bi es pee a eeo STATINT RW Returns status of A R EEN DONE ANG DONE ANDed with CHAR_MASKINT Application Note 227 Copyright 2009 ARM Limited All rights reserved 15 ARM DAI0227A
29. chDog Figure 6 Bus Architecture of DUT FPGA Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A Hardware Description 2 3 Clocks and Resets Figure 7 below shows the Clock factory which is a simple switch matrix to select any of the input clock sources and route them to the output clocks for distribution to the CPU and DUT FPGAs Hpe _midiv2 Base Board MCBO 1 33 65 66 HMALC AS3 CLKO 1 Ext MOD Processor Board CPU PLL R2 L2 CLKOUTO DUT PLL R2 CLKOUTO 4 gege DUT PLL T1 B1 CLKOUT3 Y a MCBO_B58 PWR_RESET a MCBO B60 USER RESET E 1 MCBO0 B62 HPE RESET CLK5p 15p CLK1p 10p matched lengths DUT PLL T1 B1 CLKOUT3 MCBO B34 B2 T OLK1p HCLK Ser CLK10p 25MHz reference CLK100M 100MHz reference EI L14 CPUCLK Dit pi a L14 DUTCLK_Diff CPU FPGA USER_RESET HPE_RESET Figure 7 MPS Clock and Reset Architecture The user has control of the input clocks from the DUT FPGA e g DUT PLL R2 CLOCKOUTO and can use PLLs within the FPGA to set operating frequencies and drive these signals to the clock factory The clock factory can then route these signals back to either or both the CPU and DUT FPGA e g CLK15p to allow changes of clock frequency etc on FPGA clock input pins Application Note 227 Copyright 2009 ARM Limited All r
30. e Spread Spectrum Clock Synthesize and Download Clock Settings Synthesize ClockFactory Design Download ClockFactory Design Info Details Warnings Using programming cable USB Blaster USB 0 Started Programmer operation at Thu Jun 25 15 51 09 2009 fo Configuring device index 2 Device 2 contains JTAG ID code 0x021010DD Configuration succeeded 1 device s configured Successfully performed operation s Ended Programmer operation at Thu Jun 25 15 51 15 2009 Quartus II Programmer was successful 0 errors 0 warnings Info Peak virtual memory 117 megabytes Info Processing ended Thu Jun 25 15 51 15 2009 Info Elapsed time 00 00 09 Info Total CPU time on all processors 00 00 02 Runtime for Download to System 00 00 12 77 Ide Navigate to and select the fpga dut sof image from the netlist directory to download to the MPS Download Flash Bitstream for System Look in netlist s incremental db BENEI My Documents 93 My Computer File name fpga dut sof My Network Files of type Altera Bitstreams Cat pol The HpeG desk application will now directly program the FPGA with the image The Blue LED FPGA CONFIG D will go out while it is being configured and turn on once itis done and the text at the bottom of Hpe amp desk application Log window will inform you that it has configured The DUT FPGA has now been updated with the ne
31. e interconnected with a 32bit AHB Lite interface between the CPU and the DUT FPGAs also sideband signals and interrupts between the FPGAs dependant on the processor implemented to enable a realistic system in the DUT HMALC AS3 Processor Board Implemented Not Implemented e Hpe _midiv2 Base Board Emm vwo UART Switches LEDs Switches LEDs 7SEG Sc Ethernet CAN Flexray LIN Trace Debug CPU FPGA m ALB Lit SMB UARTS AC97 SD MMC TC SP lt o Brot o is D e e e e e Z ele ee e ee e Figure 5 Block diagram of the ARM Microcontroller Prototyping System Application Note 227 Copyright 2009 ARM Limited All rights reserved 5 ARM DAI0227A Hardware Description Bus architecture 2 2 Bus Architecture of DUT FPGA VO PADS An AHB Lite system is implemented in the DUT FPGA to give the processor access to all the AHB peripherals within the FPGA An AHB to APB bridge allows implementation of APB peripherals in the system also AHB Interface from 0x4000 0000 CPU FPGA OxDFFE FFFF OxE010 0000 CPU FPGA OxFFFF FFFF CPU FPGA Video Ethernet LIN CAN Flexray VORADS l l Kate es dess See bose DDR I II 0xA000_0000 0x6000_0000 SE ER us OxAO3F FFFF Ste a Ox9FFF_FFFF Character LCD 12C AACI AC97 UART 2 UART 1 UART 0 SD MMC Switches LEDs config Timer 3 2 Timer 1 0 RTC Wat
32. erial port for the console interface to BootMonitor you will need to connect a serial null modem cable to RS232 4 UART port3 above the power connector and use a terminal emulation program e g HyperTerminal configured as 38 400 baud 8bit data no parity 1 stop bit and no flow control to talk to the MPS 5 1 2 Commands 5 1 2 1 Main Menu Command Format ALIAS alias command string CD directory path CLEAR BOOTSCRIPT CONFIGURE CONVERT BINARY lt binary file gt LOAD ADDRESS address ENTRY POINT lt address gt COPY lt file1 gt lt file2 gt CREATE lt file gt DEBUG DELETE lt file gt Note Create an alias command lt alias gt for the string of commands in command string Change directory to the one specified in directory path Clear the current boot script If no boot script is set then the boot monitor will always prompt for input no matter what the state of the run boot script switch Enter Configure Submenu Adds information required by the RUN command to execute a binary file The command will produce a file with the same name as the specified binary file but with the exe file extension Copies file lt file1 gt to lt file2 gt Create a file lt file gt Enter Debug Submenu Delete a file lt file gt 28 Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A Example Software DIRECTORY lt directory gt DISPLA
33. ights reserved 7 ARM DAI0227A Hardware Description ES Hee desk HMALC AS3 50 ClockFactory DK File Settings ClockFactory Automation Window Help p A ia B 2 2 2 e Diagnosis Clock Factory JTAG AMBA IP Manager Editor Website SYSTEM PROCESSOR Hp E uve ClockFactory connection matrix for HMALC AS3 50 SYSTEM InputClk Frequency CLKF CLK1 CLKF CLK10 DUT CLK4 DUT CLK13 Not used Om 100 00 MHz ak CK EXT CLKF CLK100M 100 00 MHz DUT PLL R2 CLKOUTO 24 58 MHz DUT PLL Bi CLKOUT3 CLKF 25 00MHz DUT PLL Ti CLKOUT3 CLKF 25 00 MHz CPU PLL L2 CLKOUTO 25 00 MHz CPU PLL R2 CLKOUTO 50 00 MHz CPU PLL B1 CLKOUT3 CPU PLL T1 CLKOUT3 o00000000000 000000000000 000000000000 Board Data and Configuration Read Board Data Auto Refresh Board Data Use Spread Spectrum Clock Synthesize and Download Clock Settings Synthesize ClockFactory Design Log Info Details Warnings Download to System jtag chain index 2 C work Microcontroller_Prototyping_Board fpga_dut physical mpb_dut altera netlist fpga_dut sof last changed on 03 13 09 17 03 04 The SIMULATED_INTERFACE is selected Trying the ALTERA Interface for the Download Executing quartus_pgm c USB Blaster USB 0 m JTAG o p C work Microcontroller_Prototyping_Board fpga_dut physical mpb_dut altera netlist fpga_dut sof 2 Runtime for Download to System 00 00 09 70 Figure 8 Hpe_desk clock factory configuratio
34. l Direction Width Note FLEX_BGE output FLEX_EN output FLEX ERRn input FLEX RXD input 44 Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A External Interfaces FLEX RXEN Input FLEX STBn output FLEX TXD output FLEX TXEN output FLEX WAKE output Table 29 Flexray Connections 6 15 LIN Interface This interface is not implemented in the example design supplied but is connected to a PHY NXP TJA1020 for the user to add their own design Signal Direction Width Note LIN RXD input LIN TXD output LIN SLPn output LIN ACTIVE output Table 30 LIN Connections 6 16 RS232 connections These interfaces are driven by the Primecell PLO11 see section 3 3 10 There are three UARTS in the example system connected to the DUT FPGA Interface RSO connects to UART 1 UARTS 2 and 3 are connected to the UART ports RS232 1 and RS232 2 on the baseboard respectively RSO xxx MIDI and RS1 xxx MIDI Signal Direction Width Note RS0 RXD LVTTL input RS0 TXD LVTTL output RSO CTS LVTTL input RS0 RTS LVTTL output RS0 RXD MIDI input RS0 TXD MIDI output RS1 RXD MIDI input RS1 TXD MIDI output Table 31 RS232 Connections Application Note 227 Copyright 2009 ARM Limited All rights reserved 45 ARM DAI0227A
35. l PLL CPU PLL T1 CLKOUTS3 Direct FPGA output from internal PLL L14 CPUCLK Diff Direct FPGA differential output for L14 interface L14 DUTCLK Diff DUT CPU Direct FPGA differential output for L14 interface Table 1 Clock Routing 2 3 2 Reset Routing Name Source Destination Note PWR_RESET O D output from supply monitor internal use USER_RESET All CF CPU DUT Push button on Processor board O D HPE_RESET CF BB DUT Driven by USER_RESET and PWR_RESET Table 2 Reset Routing Notes BB BaseBoard CF Clock Factory CPU CPU FPGA DUT DUT FPGA OSC Crystal Oscillator module The System only uses the USER_RESET signal and this drives all internal resets nPOR nHRESET etc The design ignores PWR_RESET and HPE_RESET The CPU FPGA drives the nHRESET signal between the CPU and DUT FPGA to create a synchronous reset with respect to HCLK in the DUT FPGA The DUT FPGA uses this to resynchronise resets to all other clock domains within the FPGA Application Note 227 Copyright 2009 ARM Limited All rights reserved 9 ARM DAI0227A Programmer s Model 3 Programmer e Model 3 4 Interrupts 10 The interrupt controller is integrated into the processor and resides in the CPU FPGA Details of the architecture for this can be found in the relevant processor Application Note and documentation The mapping of the example system peripherals to interrupts is irrespective of the controller implementatio
36. l and the internal speaker Signal Direction Width Note AC BITCLK input 12 288MHz clock from Codec AC EAPD input Not used AC EXT CLK output 24 576MHz reference clock to Codec AC SDATAIN input Drives AACISDATAIN AC SDATAOUT output Driven by AACISDATAOUT AC RESETn output Driven by AACIRESET AC SYNC output Driven by AACISYNC used as an output Table 24 AC97 Connections 6 10 A D amp D A Interface This interface is driven by the serial interface block DS702 see section 3 3 2 and connects to the A D and D A converters Cypress CY8C27543 on the rear panel Signal Direction Width Note ADDA CLK OD Driven by SCL ADDA DATA bi dir Drives SDAin and is driven to 0 by nSDAOUTEN going to 0 Table 25 A D amp D A Connections SDAin SCL ADDA CLK Driver nSDAOUTEN 1 bO gt ADDA_DATA Tri stated driver Figure 22 I C Connections 6 11 Memory DDR Interface The signals are connected to the Childboard connector They reference standard DDR2 signals but can be driven with different signals depending on the Childboard connected This interface is not driven in the example design supplied Signal Direction Width Note MEM_DDR2_ADDR output 15 0 MEM DDR2 BA output 2 0 MEM DDR2 CASn output Application Note 227 Copyright 2009 ARM Limited All rights reserved 43 ARM DAI0227A External Interfaces
37. lash Submenu 5 1 2 5 SDCard Submenu Command Format Note FORMAT QUICK Formats the SDCard MMC as FAT16 with 8 3 filenames VOLUME lt label gt QUICK performs a quick format with only the FAT and bootsector updated VOLUME label will add a Volume label to the disk as specified in the field label INFORM Display details SD MMC Card INITIALISE If the card has been changed use this command to re initialise it to determine it s features before using any other commands EXIT Exit HELP List commands Table 12 SDCard Submenu 5 1 3 Re building the software Currently only a Windows development environment is supported The firmware can be built using MDK and RVCT Figure 16 bootmonitor directory structure shows the position of the executable files and scripts for rebuilding under both RVDS and MDK 32 Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A software projects bootmonitor Firmware Boot Monitor Build keil Build RVDS Debug Release Source Examples Libraries Platform Build keil Build RVDS Debug Release Source Utility Code cli elf flash Figure 17 BootMonitor directory structure 5 2 Selftest Executable image and scripts to rebuild with MDK Scripts to rebuild with RVDS Executable image with debug support Executable image Libraries required to rebuild bootmonitor Executable image and scripts
38. le Software 5 Example Software Under the MPS root directory you can find the software directory which contains the files required to rebuild the BootMonitor and Selftest software It also contains the images for downloading to the MPS MPS docs fpga cpu fpga dut peripherals software Figure 16 Top level directory structure The directory structure is separated as follows e docs Contains related documents including this document e fpga cpu Contains precompiled encrypted images for the CPU FPGA in the design which contains the processor e fpga dut Contains the verilog RTL files which describe the structure and design of the example system in the DUT FPGA e software BootMonitor and selftest example software e peripherals Contains the verilog RTL or precompiled images of the peripherals used by the example design in the DUT FPGA 5 1 BootMonitor This is the application that runs when the system is booted it handles the system initialization and has a command interpreter which accepts user input from the console to perform the following functions e Board configuration e General file operations using MM SDCards configured as FAT16 8 3 filenames e Programming images into flash e Loading and running another application e Console supports semihosting via the debugger not supported in MDK or serial port It supports a single processor environment in little endian mode The BootMonitor reads the CPU User s
39. lockFactory CPLD ClockFactor Clear ClockFactory Synthesis Cache InputClk Download sof file to System FPGA an E EE Download to System Flash Memory ES Erase System Flash Memory ak Download sof file to Processor FPGA CK EXT Download to Processor Flash Memory CLKF CLK1C Erase Processor Flash Memory DUT PU RZ CLKOUTU 23 58 MAZ DUT PLL B1 CLKOUT3 CLKF 25 00 MHz DUT PLL T1 CLKOUT3 CLKF 25 00 MHz CPU PLL L2 CLKOUTO 25 00 MHz CPU PLL R2 CLKOUTO 50 00 MHz CPU PLL B1 CLKOUT3 33 33 MHz CPU PLL T1 CLKOUT3 40 00 MHz 00000000000 00000000000 oo0o0000q o00000q Board Data and Configuration Read Board Data Auto Refresh Board Data Use Spread Spectrum Clock Synthesize and Download Clock Settings Synthesize ClockFactory Design I Download ClockFactory Design Navigate to and select the fpga_dut sof image from the netlist directory to download to the MPS Download System SOF File Look in netist N Ob 2 incremental_db My Recent DEDE Documents My Documents File name fpga dut sof My Network Files of type SOF File Cafi The Hpe _desk application will now directly program the FPGA with the image The Blue LED FPGA CONFIG D will go out while it is being configured and turn on once it is done and the text at the bottom of Hpe _desk application Log window will inform you that it has configured The DUT FPGA has now been updated with the new image
40. mber s to which your comments refer e an explanation of your comments General suggestions for additions and improvements are also welcome ARM web address http www arm com Application Note 227 Copyright 2009 ARM Limited AN rights reserved iii ARM DAI0227A Table of Contents 1 1 1 1 2 2 2 1 2 2 2 3 3 2 3 3 4 1 4 2 4 3 5 1 5 2 6 1 6 2 6 3 6 4 6 5 6 6 6 7 INTRODUCTION ME 1 Purpose of this application note eeeeeeeeeeeeeeeeeeeeeeeeen nennen nnne nenne nnnm nnne nnn nnmnnn nnmnnn nnmnnn na 1 Overview of the hardware platform seseeeseeeeeeeeeeeeesee seen nennen ninth anna natnm nsn tR assa nasa sana nnn nsn nn ns 1 HARDWARE DESCRIPTION ee 5 Block Disgrace E E ILI LS Ie IL 5 Bus Architecture of DUT FPGA eeeeeeeseeeieeeseieeeeee enne inns snnm nnn tn nn si tasa sanas n ase anneanne nass natn Rasen nasa aa 6 Glocks and HReselts rud Led a eee ug mu e 7 PROGRAMMER S MODEL celle rieeeeeeeee nnne n enhn nhan annus nasa anas assa nnns aaa a nana nn 10 uci 10 Memory Tass 11 DUT FPGA UE EC P H 11 FPGA DESIGN D 18 Directory structuren cornaire aR E uai pa eee Ie rice aid ceded I Ire Ir Price ttc EAER 18 Re building the DUT FPQ A
41. n The configuration of the clock factory is performed using Hpe_desk and is a simple button selection matrix to define the routing of clocks Figure 8 shows the selection of source clock CPU PLL R2 CLKOUTO from CPU FPGA driving the destination clock CLKF CLK1 back into both CPU and DUT FPGA CLKF CLK100M is the default 100MHz clock source and should be used as the reference for all PLL generated clocks 2 3 4 Clock Routing Name Source Destination Note CLK100M Osc CF DUT CPU Buffered 100MHz clock output to DUT and CPU CLKO Oscillator module on Baseboard CLK1 Oscillator module on Baseboard EXT External SMB clock input on Baseboard CLK5p Direct connection to CPU only CLK15p Direct connection to CPU only CLKip Buffered match lengths to DUT amp CPU HCLK CLK10p Buffered match lengths to DUT amp CPU CLK25MHz CLK4p Direct connection to DUT only CLK13p Direct connection to DUT only DUT PLL T1 CLKOUT3 DUT X CF CPU MCBO Buffered FPGA output from internal PLL DUT_PLL_B1_CLKOUT3 DUT CF CPU MCBO Buffered FPGA output from internal PLL DUT_PLL_R2_CLKOUTO Direct FPGA output from internal PLL CPU PLL L2 CLKOUTO CPU CF Direct FPGA output from internal PLL 8 Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A Hardware Description Name Source Destination Note CPU PLL R2 CLKOUTO Direct FPGA output from internal PLL CPU PLL B1 CLKOUT3 Direct FPGA output from interna
42. n and detailed here Figure 8 describes which interrupt is driven by each peripheral An NMI input is available on some processors and is also shown below 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 I3 12 T 10 09 08 07 06 05 04 03 02 01 00 NM Reserved Figure 9 Interrupt Allocation Table Copyright 2009 ARM Limited All rights reserved I2C ADC DAC LIN CAN Flexray Character LCD USB HC USB DC Ethernet CLCD combined Int AACI AC97 UART 2 UART 1 UART 0 MCIb MCIa Timer 3 2 Timer 1 0 RTC WatchDog WatchDog Application Note 227 ARM DAI0227A Programmer s Model 3 2 Memory map Figure 10 details the memory ranges available to the DUT FPGA and the assignment of memory locations for the example system 0x10000 0000 OxEO10 0000 OxEOO00 0000 OxD000 0000 0xC000 0000 OxB000 0000 0xA000_0000 0x9000_0000 0x8000_0000 0x7000_0000 0x6000_0000 0x5000_0000 0x4000_0000 0x3000_0000 0x2000_0000 0x1000_0000 0x0000_0000 Figure 10 0xC000 0000 OxA400_0000 0xA000_0000 16x 4kB APB peripherals Int RAM B Exec Int RAM A Exec Int ROM Exec Int ROM Exec DUT FPGA memory map 16x 64kB AHB peripherals W 0xA400_0000 OxA3FF 0006 0xA002 0000 0xA000 0000 0x5000 0000 Ox4FFF 0006 Ox4EF 0000 OXAFFD 0000 Ox4FFC 0000 Ox4FFB 0000 Ox4FFA 0000 Ox4FFO0 0000 0x4001 0000
43. n bi dir DUT HUMI Fn bi dir DUT HUMI Gn bi dir DUT HUMI DPn bi dir DUT HUMI SEGn output 4 DUT HUMI LEDn output DUT LCD REGSEL output DUT LCD RW output DUT LCD ENABLE output Table 19 Human Interface Please refer to section 3 3 for details on the registers used for driving this interface The buttons and switches can be read via the register SYS SW see section 3 3 1 3 The values held in the SYS LED and SYS_7SEG registers see sections 3 3 1 4 and 3 3 1 5 are driven onto this interface based upon the value held in the HUMI MODE field inthe SYS PERCFG register see section 3 3 1 2 Application Note 227 Copyright 2009 ARM Limited All rights reserved 39 ARM DAIO227A External Interfaces CHARLCDDBin 7 0 LED 7 0 DISPO 7 0 DISP1 7 0 DISP2 7 0 DISP3 7 0 CHARLCDDBout 7 0 DUT_HUMI_ A G DP Output Enable CHARLCDDBen 7 0 DUT HUMI LED amp DUT HUMI SEG O f DUT HUMI SEG 1 amp DUT HUMI SEG 2 Scheduler DUT HUMI SEG 3 CHARLCDSync Es CHARLCDidle Logic CHARLCDRS DUT LCD REGSEL CHARLCDE DUT LCD ENABLE CHARLCDRnW DUT LCD RW Notes The Output Enable is driven at all times except when the Char LCD is selected then it is controlled by the CHARLCDDBen signals The CHARLCDSync signal informs the Chart CD controller when it can perform the read and write transactions to the display Enablde the DONE flag to be set The CHARLCDIdle signal informs the scheduler that a transaction is in p
44. nfiguration Connections 6 6 SEMULATOR connections The SEmulator connector is for use by the Gleichmann SEmulator product only The signal assignments are shown for completeness only Signal Direction Width Note SEDUT L4 RXN input 4 SEDUT L4 RXP input 4 SEDUT L4 RXCLKN input SEDUT L4 RXCLKP input SEDUT L4 TXN input 4 SEDUT L4 TXP input 4 SEDUT L4 TXCLKN input SEDUT L4 TXCLKP input SEDUT RESETn input Table 21 Semulator Connections 6 7 USB Interface This interface is driven by a dedicated interface driver 16bit Static memory interface which is designed to drive the NXP ISP1761 USB controller 14 The interface driver is not configurable and is transparent to the rest of the system All accesses to the USB device must be halfword accesses only Signal Direction Width Note USB_A output 17 USB CSn output USB Bin output USB WHn output USB D bi dir 16 USB DC DACK bi dir Not connected in this design Application Note 227 ARM DAI0227A Copyright 2009 ARM Limited All rights reserved 41 External Interfaces USB DC DREQ bi dir Not connected in this design USB DC IRQ bi dir Used as input only See interrupt table USB DC WAKEUPn bi dir Not connected in this design USB HC DACK bi dir Not connected in this design USB HC DREQ bi dir Not connected in this design USB HC IRQ bi dir Used as input only See interrupt
45. nterfaces brought into the DUT FPGA to enable implementation Static Memory Controller The Static memory interface implemented in the design is specifically to allow communication to the ISP1761 USB device 14 It does not require any configuration and is optimized for operation with a 50MHz AHB interface UARTS The PLO11 PrimeCell is used as the UART See the TRM for details about its functionality 11 The clock is set at 25MHz and is derived from the 100MHz clock Audio AACI AC97 The PL041 PrimeCell is used as the AACI See the TRM for details about its functionality 12 The AACI is a modification of the PrimeCell with increased FIFO depth to help improve transfer performance in FPGA The clock source is derived from the baseboard and drives a clock input of the DUT FPGA CLK13p The FPGA can also drive the AC EXT CLK to set the clock but this option is not implemented in the example system Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAIO227A Programmer s Model 3 3 12 MMC SD MMCI The PL181 PrimeCell is used as the MMC SD card controller See the TRM for details about its functionality 13 The MMCI uses the bits in the system registers to identify the write protection and card inserted status see section 3 3 1 for details Application Note 227 Copyright 2009 ARM Limited All rights reserved 17 ARM DAI0227A FPGA Design 4 FPGA Design All of the RTL for this design is p
46. nters deriving the pulse from the reference clock Table 3 dut fpga verilog files Also within this directory is the script for building the images to download to the FPGA The synthesis script is in physical MPS dut altera scripts and produces a routed placed design in the physical MPS dut altera netlist directory See the Hpe desk manuals for downloading this image to the FPGA 2 4 2 2 Configuring the Example System The example system has a definitions file fpga dut defs v in the fpga dut logical verilog directory to allow the selection of section of the design to be implemented or removed It 20 Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A FPGA Design also contains defines to determine the functionality of different sections of the design The description of the defines is given in Table 4 System Configuration Define Note define ARM MPS INCL UDE CLCD This includes the Colour LCD and Video controller block user supplied Without this define the pixel clock is not driven and the data and control lines are tied to 0 which means that the video bus will not drive any data or clock define ARM MPS VGA Implement the VGA Pattern Generator 640x480 if no CLCD present define ARM MPS SVGA Implement the VGA Pattern Generator 800x600 if no CLCD present define ARM MPS XVGA Implement the VGA Pattern Generator 1024x768 if no CLCD present
47. o cuieec ri seetnete EE A SEENEN ai ri ane cR 44 6 15 LINIEI CE Eeer tea AEE TEA 45 6 16 RS232 connections diese iacere cade eie delectet fale eese daaa Eege 45 Table of Figures Figure Edel E 2 Figure 2 Microcontroller Prototyping System Front Panel eeeeeeeesseeseeeeeeenenen nennen nnne 3 Figure 3 Microcontroller Prototyping System Rear Panel eese essen enne nennen nnne 3 Figure 4 Microcontroller Prototyping System Inside eee esee eeeee enne ne ennt 4 Figure 5 Block diagram of the ARM Microcontroller Prototyping System eese 5 Figure 6 Bus Architecture of DUT FPQGA ueseeseeseseeeeeeeeeeeee an aen senem nnn Haan eca deaa eei nnns atn nasa sa eide asa sn aniis 6 Figure 7 MPS Clock and Reset Architecture eieeeseeeeeeeeeiiees esee nennen en nn nnn nn natn n ninth nn an tasas ann ennnen 7 Figure 8 Hpe desk clock factory configuration essei eene nennen nennen nnn nennt annees 8 Figure 9 Interrupt Allocation Table eeeeeeeeeeeeeee eene enne nennen nnn nnmnnn nnmnnn nnmnnn nnnm nenna inse se nnmnnn ennn na 10 Figure 10 DUT FPGA memory map 4 ceeeeeeeeeeees eee ennt nnne nna nina sinn mann nnns sana assa sss R ssa sR ss sata sas m sse sn nns nR nasa a 11 Figure 11 7 Segment Display Segment ldentification
48. o po besen hu II Reseed RB au II Reserved E HO po 4 po jo m CARDIN Status of MCI WPROT bit 1 write protected Status of MCI card Present 1 card inserted The Human Interface HUMI Mode bits define how the scheduler selects the different display components on the system This can be used for system debug Mode Bitvalue Noe Scheduler 000 Round robin schedule to all HUMI devices 7 7 7 7 7Segmeni or 3 3 1 3 Switches SYS_SW maae e a tar USER BUT 3 0 7 4 JRO h jAlweys returns value of user buttons USER SW 3 0 3 0 JRO h Always returns value of user switches 3 3 1 4 LEDs SYS LED Reseved sie dT OCC Relums value in register is LED on OLED off 3 3 1 5 Display output SYS 7SEG Name s Access Reset Note DISP2 23 16 Segments for display 2 DISP1 Segments for display 1 DISPO Segments for display 0 12 Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAIO227A Programmer s Model Disp3 Disp2 Disp1 DispO ODC Figure 11 7 Segment Display Segment Identification Name Bit J Noe O Dp fisDecmalPoitonOisDecmalPontof 5 l G b _ tissegmenton Oissegmentof C 2 fissegmentonOissegmentof B h issegmenonOisegmetot 1 A p iisegmenonOisegmetot
49. pyright 2009 ARM Limited All rights reserved 31 ARM DAI0227A Example Software WRITE BINARY file Writes a binary file to flash NAME lt name gt The image will be identified in flash by a name derived from FLASH ADDRESS lt address gt the filename for example t images boot_monitor bin will be LOAD ADDRESS lt address gt called boot monitor and this can be overridden by using the ENTRY POINT lt address gt option NAME argument You can specify where in flash the image is written by using the optional FLASH ADDRESS argument Note if both FLASH ADDRESS and LOAD ADDRESS are specified and LOAD ADDRESS is located in flash then LOAD ADDRESS will be used and the FLASH ADDRESS argument will be ignored The optional LOAD ADDRESS and ENTRY POINT arguments allow you to specify these parameters if ENTRY POINT is not specified then to defaults to the load address WRITE IMAGE lt file gt Writes an ELF image file to flash NAME lt name gt The image will be identified in flash by a name derived from FLASH ADDRESS lt address gt the file name for example t images boot_monitor axf will be called boot monitor and this can be overridden by using the option NAME argument You can specify where in flash the image is written by using the optional FLASH ADDRESS argument Note if the image is linked to run from flash then this address will be used and the FLASH ADDRESS argument will be ignored Table 11 F
50. rogress and it must hold off switching until it completes The scheduler must update each muxed output at minimum of 60Hz to ensure a flicker free image on 7 Segment displays and LEDs Figure 20 HUMI logic The scheduler runs at a preset rate of 500Hz and selects a new driver for the data lines DUT HUMI A G DP n every 2 ms if the HUMI MODE field is set to Scheduler 8 b000 The order of the cycle is LEDs selected the scheduler drives DUT HUMI LEDn low Segment 0 the scheduler drives DUT HUMI SEGn to 4 b1110 Segment 1 the scheduler drives DUT HUMI SEGn to 4 b1101 Segment 2 the scheduler drives DUT HUMI SEGn to 4 b1011 Segment 3 the scheduler drives DUT HUMI SEGn to 4 b0111 40 Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A External Interfaces Character LCD the scheduler drives DUT HUMI SEGn to 4 b1110 and DUT HUMI LEDn high and enables the DUT LCD interface control lines Should any operation be in progress when the scheduler wishes to switch back to the LED then change is halted whilst the operation completes and any new operation is prevented from starting the CharLCD driver appears busy to the processor 65 FPGA Configuration connections These connections are not used by the design and are for FPGA configuration only Signal Direction Width Note DUTFCP CLK input DUTFCP DATA input DUTFCP PLTXT RDY input DUT PORSEL input Table 20 FPGA co
51. rovided as Verilog or precompiled netlists Example files are provided to allow the system to be rebuilt with the Altera Quartus Il tools The readme files provided with the application note show the version of the tools used to build the design 4 4 Directory structure bal MPS CJ Mx bad docs d fpga cpu CJ software Figure 13 Top level directory structure The directory structure is separated as follows 4 1 4 Peripherals docs fpga_cpu fpga_dut software peripherals Contains related documents including this document Contains precompiled encrypted images for the CPU FPGA in the design which contains the processor Contains the verilog RTL files which describe the structure and design of the example system in the DUT FPGA bootmonitor and selftest example software Contains the verilog RTL or precompiled images of the peripherals used by the example design design In the DUT FPGA The peripherals used in the example system are stored in the peripherals directory which contains either verilog source or netlists These files are read by the synthesis tool at run time and used to create a netlist for place and route Each peripheral has its own directory under either logical for Verilog source or physical for netlists Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A FPGA Design logical ds700 charlcd verilog Verilog source files ds702 i2c verilog Verilog
52. s Synthesize ClockFactory Design Download ClockFactory Design Details Warnings Select the Hardware Settings tab from the options box and then select the ALTERA INTERFACE radio button Select the OK button to complete configuration These are the globally applied options for this application Paths Colour Settings Hardware Settings Lagging Settings JTAG Hardware Interface COHPE_ITAG_SNOOPER S ALTERA INTERFACE FLASH PRO INTERFACE ODIGILENT INTERFACE OSIMULATED INTERFACE Autodetect Hpe FPGA Module on Application Startup 6 To configure the correct FPGA module for MPS 22 Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A FPGA Design Select from the drop down menu Settings gt select FPGA module gt HMALC AS3 gt HMALC AS3 50 BS Hpe_desk HMALC AS3 50 ClockFactory File EE ClockFactory Automation Window Help Select FPGA Module DH Auto Detect FPGA Module B e Hpe desk Options HMALC AS3 gt v HMALC AS3 50 E EES AAP AS2 HMALC AS3 70 Ge PESCHE HMX2 AS2 HMALC AS3 150 50 HMX1 AS2 Hp E rnidive ClockFactory connection matrix for HMALC AS3 50 SYSTEM InputClk Frequency CLKF CLK1 CLKF CLK10 DUT_CLK4 DUT_CLK13 Not used CLKO CLK1 OK ET CLKF CLK100M DUT_PLL_R2_CLKOUTO DUT_PLL_B1_CLKOUT3_CLKF DUT_PLL_T1_CLKOUT3_CLKF CPU PLL L2 CLKOUTO CPU PLL R2 CLKOUTO CPU PL B1 CLKOUT3
53. s to be connected to the board for complete testing Note these cables are not supplied with the MPS but details of their connections are given here Copyright 2009 ARM Limited All rights reserved 35 Example Software 5 2 2 1 AACI loopback cable The AACI test performs a loopback test from Line Level Out to Line Level In This requires two 3 5mm stereo jack plugs which must all be wired as follows Connector A Connector B Tip Tip Ring Ring Screen Screen Table 13 AACI loopback cable Connect the cable between the line in and line out sockets on the MPS back panel 5 2 2 2 UART loopback cable The two UART cables have female 9 pin D sub connectors on either end with connections as follows Connector A Connector A Name Connector B Connector B name Pin Pin T T om s DSR 5 GND GND DSR DTR 7 RTS EE NN CTS 8 CTS RTS 9 N C 9 N C Table 14 UART loopback cable Connect one cable between the top two UART connectors and the other between the bottom two UART connectors one the MPS rear panel 36 Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A 6 External Interfaces External Interfaces This section shows the interfaces available on the Customer DUT FPGA The direction of the signals is shown from the point of view of the DUT FPGA so an O signal goes from the DUT FPGA to the CPU FPGA for example 6 1 Clocks and Resets
54. source files ds704 videogen verilog Verilog source files pl011_uart verilog Verilog source files pl022 ssp verilog Verilog source files pl031 rtc verilog Verilog source files Sp804 timer verilog Verilog source files Sp805 watchdog verilog Verilog source files physical pl041 aaci synplify netlist Netlist files pl181 mmci synplify netlist Netlist files Figure 14 peripherals directory structure The description of each peripheral is outside the scope of this application note The TRM for each peripheral can be found within each peripheral s folder and should be referenced for details about the operation and programmers model These peripheral files are supplied as an example for use in the example system 4 1 2 DUT FPGA The following directory structure shows the position of the files required to re build the DUT FPGA image for the MPS Application Note 227 Copyright 2009 ARM Limited All rights reserved 19 ARM DAI0227A FPGA Design fpga dut logical verilog Verilog source files physical mpb dut altera Build files and FPGA netlist H image Scripts to rebuild the scripts FPGA image Figure 15 fpgu dut directory structure 4 2 Re building the DUT FPGA 4 2 1 Design file description The fpga dut directory contains the Verilog source required for the top level of the example system This directory together with the peripherals directory contains all the files required to build the example s
55. st directory Copyright 2009 ARM Limited All rights reserved 21 FPGA Design 4 2 4 Configuring the MPS and Hpe amp desk Before you can download the FPGA image to the MPS the Hpe amp desk application needs to be installed and configured Follow the following steps to configure 1 Ensure the Hpe amp desk application has been installed 2 Connect the PC via a USB cable to the USB OTG connector on the front of the MPS 3 Power on the MPS 4 Start the Hpe amp desk application 5 Configure the connection method to the MPS Select from the drop down menus Settings gt Hpe desk Options ES Hpe_desk HMALC AS3 50 ClockFactory EIS File ECH ClockFactory Automation Window Help Select FPGA Module gt p Pp B WEE 070707078008 Se Explore Application Data Directory SOR License Hp ES oue ClockFactory connection matrix for HMALC AS3 50 SYSTEM InputClk Frequency CLKF CLK1 CLKF CLK10 DUT CLK4 DUT_CLK13 o o o o o Not used CLKO CLK CLK EXT CLKF_CLK100M 100 00 MHz DUT_PLL_R2_CLKOUTO 24 58 MHz DUT_PLL_B1_CLKOUT3_CLKF 25 00 MHz DUT PLL Ti CLKOUT3 CLKF 25 00 MHz CPU PLL L2 CLKOUTO 25 00 MHz CPU PLL R2 CLKOUTO 50 00 MHz CPU PLL B1 CLKOUT3 33 33 MHz CPU PLL T1 CLKOUT3 40 00 MHz 000000000000 000000000000 000000000000 Board Data and Configuration Read Board Data Auto Refresh Board Data Use Spread Spectrum Clock Synthesize and Download Clock Setting
56. to rebuild with MDK Scripts to rebuild with RVDS Executable image with debug support Executable image Example Software The selftest code allows the user to confirm the functionality of their MPS and provides reference code for the example peripherals The code tests the following peripherals AACI MMCI USB UARTS character LCD LEDs switches SRAM memory RTC and system clocks interrupts Selftest is designed to run on the MPS using MDK and RVDS The user can interact with the software operation via the Serial Console for MDK or additionally the semihosting console window under RVDS The user interface displays a menu and prompts the user on how to operate each test For more information on exactly how each test is working refer to the provided source code and readme files Application Note 227 Copyright 2009 ARM Limited All rights reserved ARM DAI0227A 33 Example Software 5 2 1 Re building the software 34 Currently only a Windows development environment is supported Selftest can be built using MDK and RVCT Figure 17 selftest directory structure shows the location of the executable files and scripts for rebuilding under both RVDS and MDK The project and executable files for selftest can be found under the selftest build Build_Keil directory To run all the tests it is necessary to connect a number of loopback cables to the board for audio and UARTS After connecting the test harness and loading
57. ves ceetuccuectesaccceeeu site Ec En cU EEN 43 Table of Tables Table Kl elei Tele mee 9 Tabie ILIA rem 9 Table 3 dut fpga Verilog files eeeeeeee eerie eeeee eene enne ee nennen nennt nnns nn nnns nennen nnne ras nnne nsns nnt 20 Table 4 System Configuration cessisse E E sa sna annnm asa A m sss m ssa sR nns aa as 21 EI UE E Wd c TE iC 21 Table 6 Clock and Reset Destinations 11 cese esee eiie nn eecieeee esee anne tn mana aa uasa asso sa masa sas a asas s Dama sa sa sa as anra 26 Table 7 Bootmonitor switch utilisation seen 28 Table 8 Main ULT P R H 29 Table 9 Configure Submenwu 4 lese e E a aaa nenne nin na sana na a r aa assa sagas asas Deaan assa Is KREE ni da adha UDe aat 30 Table 10 D bug KEE UE 31 Table 11 Flash SUbMenU RE 32 Table 12 SDCard Submenu WEE 32 Table 13 AAC loopback cable 5 22r eee EENS 36 Table 13 UART loopback cable 1 EELER 36 Table 15 Clocks and Resets uu ost ccs anes tin Rou cea eh st eee dances eh edna SES Ee 37 Table 16 Processor interface oa cuc EES EENEG 37 Application Note 227 Copyright 2009 ARM Limited All rights reserved V ARM DAI0227A Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table
58. w image 4 3 Clock and reset settings Please use the online help of the Hpe amp desk software for details on programming the clocks 2 Section 2 3 1 gives a basic overview of the clock factory settings Application Note 227 Copyright 2009 ARM Limited All rights reserved 25 ARM DAI0227A FPGA Design 4 3 1 Clock and Reset Destinations The following table gives the default clock frequency settings used by the example system and which clock inputs of the DUT FPGA are used Device Clock Freq Clock ref Reset ref Note AHB APB infrastructure Runs at CPU frequency UART 25MHz___ CLK10p HRESETn o SP PsMHz EE HRESETn PLO22 FC DS702 VIDEO Video LCD controller pixel clock AC97 PLOAT SD MMC 25MHz ___ CLK10p_ HRESETn_ PL181 Character LCD DS700 HUMI Multiplexer frequency Timer MHz ge _ HRESETn SP804 Real Time Clock PLO31 Watch Dog Hz te HRESETn SP805 USB External IC ISP1761 Static Memory HCLK CLK1p HRESETn Memory controller on DUT FPGA Table 6 Clock and Reset Destinations All the peripherals that have an AHB or APB interface have that interface running at CLK1p CLK100M is used to derive all peripheral clocks where appropriate since this is a non variable clock and ideal for timers watchdogs etc The Reset column refers to the reset signal that is re synchronised to the respective clock domain 26 Copyright 2009 ARM Limited All rights reserved Application Note 227 ARM DAI0227A Examp
59. witches 0 2 shown in 4 on power up and uses these to select the boot option On delivery all the switches are set to ON and defaults to no boot script with auto detection of console interface either semihosting not supported on MDK or UART port3 shown in Figure 4 SW1 SW2 SW3 Function Note ON X X Normal boot Use this as default Application Note 227 Copyright 2009 ARM Limited All rights reserved 27 ARM DAI0227A Example Software Run boot Script monitor command line X Force UART port3 for Console semihosting support X Do not use undefined behaviour Reserved Do not use undefined behaviour This needs to be pre configured from the boot Always use UART port3 regardless of Table 7 Bootmonitor switch utilisation Note no other switches are used by BootMonitor and are free for user use at power up or reset When the MPS is turned on Boot Monitor will start The character display will show the Firmware F W and Hardware H W versions of the system This is also output to the serial port for display on the terminal if the switches are set correctly you will now enter the Boot Monitor command prompt on the terminal SW 3 1 ON The CPU LEDs 0 to 7 will cycle a lighted bit to show the Boot Monitor is running Pressing the reset button on the front panel will perform a hardware reset and the system will restart as if it had been power cycled 5 1 1 Console via serial port To use the s
60. ystem A description of each file is given in Table 3 Filename Note AHB2APB v AHB to APB bridge AHBAPBSys dut v APB subsystem instantiates the AHB to APB bridge APB address decoder and APB peripherals This requires changes to add or remove APB peripherals AHBDecoder dut v AHB address decoder This requires changes to add or remove AHB peripherals AHBDefaultSlave v Creates the error response if a unmapped AHB address is accessed AHBMuxS2M v AHB multiplexer to direct the correct AHB peripheral access to the processor This requires changes to add or remove AHB peripherals AHBUSBController v AHB to 16bit static memory interface to access the USB controller APBDecoder v APB address decoder This requires changes to add or remove APB peripherals APBRegs dut v APB system registers used for system control See section 3 3 1 for details clock divider v Generates peripheral clocks derived from 25MHz reference clock dut logic v AHB subsystem instantiating the AHB peripherals and APB subsystem fpga dut v Top level instantiating the AHB subsystem Clock and reset logic I O functions tri state I O registers PLL s etc and Human Interface multiplexer fpga_dut_defs v Defines for use by the design as compilation See section 4 2 2 for details humi_mux v Human Interface multiplexer to drive 7 segment displays LEDS and Character LCD pulse_gen v Pulse generator to create enable pulses for cou
Download Pdf Manuals
Related Search