LandTiger V2.0 LPC17XX Development Board
Contents
1. or press Alt F7 Go to Utilities Set programmer to Cortex M R J Link J Trace Click Settings and then click Add Find LPC17xx IAP 512KB Flash Click Add to confirm the selection Finally tick Program Verify and Reset and run And check Erase full chip pode eg 6 2 Compatibility with mbed 6 2 1 Hardware LEDs Pins COMO LandTiger V2 0 User Manual 43 PWM Ethernet mbed microcontroller boards have a built in interface to provide functionality such as drag n drop download reset serial over usb and access to the mbed local file system These functions provide means to control the interface using semihost calls it supports The mbed Ethernet library for example sets the MAC address by calling a weak function extern C void mbed mac address char mac to copy in a 6 Byte 12 character MAC address This function performs a semihosting request to the mbed interface to get the serial number which contains a MAC address unique to every mbed device If you are using the eth library on your own board 1 e not an mbed board like the LandTiger you should implement your own extern C void mbed mac address char mac function to overwrite the existing one and avoid a call to the interface which doesn t exist extern C void mbed mac address char mac MAC address may for example be cloned from scrapped modem box mac 0 0x00 mac 1 0x01 mac 2 0x02 mac 3 0x032. Tabel 11 Databus interface description Description JIOPin 2 8 3 Display Interface The CN7 Databus interface of the Land Tiger LPC17XX development board can be connected to a 2 8 or 3 2 inch 320X240 TFT color LCD The datalines are connected to P2 0 P2 7 and by 8bit 16bit conversion circuit connected to the LCD In addition to the 16 bit databus the LCD interface also supports a touchschreen controller This interface is provided as an SPI bus Depending on the LCD board the LCD backlight may be controlled either as on off or with variable brightness PWM control The databus LCD connector pinout is defined in the table below LandTiger V2 0 User Manual Tabel 12 CN7 Databus Color TFT LCD interface description Pin Description IOPin Comment 2 GND X Ground 4 DBO K P2 1 latched o 5 DBO j P22 athed 6 DBO JP23 ltched O 7 A DBO P2A4 latched h 8 00 DB O P25 latched h O Z o 9 DBO6 JjP26 ltched Jo DBO J P27 athed di DBO P2O bufferedh o Z o 12 DB9 P2I buffered 13 DBIO QJP22 bferd 14 DBIIO v jJP23 buffred Z o is DBI2 X K P2 4 buffered d6 DBI3 X P25 bufferedh 17 DBI4 P26 buffered 18 D I JP27 buffered 20 RS P0 23 RS I Instruction Register Register I BLCNT Brightn Control of the PWM backlight brightness via TP INT Touchscreen Low level while the touch screen detec
3. 26 BLGND Ground Backlight GND UB DO e adjustment via PWM IDE lime NN detects pressing 29 TP CS Touch screen chip select Low active _ o 33 3 3V 3 3V power supply When powered from 3 3V supply Pin 33 amp Pin 34 as power input Pin 1 amp Pin 2 keep NC LandTiger V2 0 User Manual 33 34 GND Ground o Notel The 5V 3V3 converter on the HY32C LCD board is interfering with LandTiger LandTiger mainboard LandTiger V2 0 User Manual 34 4 Downloading Application Software 4 1 In System Programming ISP using FlashMagic Flashing a new program in the LandTiger LPC17xx may be done by entering the ISP bootloader mode and downloading the new code through UART 0 A free PC software application named FlashMagic may be used for this purpose www flashmagictool com All you need is a serial cable fully wired between the PC and LandTiger COMO Set JP6 and JP7 to enable ISP mode via COMO Select the LPC1768 device and the correct PC Com port in FlashMagic select the desired hex file and press Start Then press the Reset button on the LandTiger to execute the new program x Flash Magic NON PRODUCTION USE ONLY File ISP Options Tools Help Step 1 Communications Step 2 Erase Select Device LPCI7ES COM Port COM 3 Baud Rate E 9200 Interface None ISF Oscillator MHz 12000 eg hn E I i Et F N i i J SE all ZE SE Rd Prot a A ta
4. as if the reset button had been pressed Variables returns 1 if successful else 0 e g interface not present GA int mbed interface reset void Function mbed interface disconnect This will disconnect the debug aspect of the interface So semihosting will be disabled The interface will still support the USB serial aspect Variables returns 0 if successful else 1 e g interface not present SEH int mbed interface disconnect void Function mbed interface powerdown This will disconnect the debug aspect of the interface and if the USB cable is not connected also power down the interface If the USB cable is connected the interface will remain powered up and visible to the host Variables returns 0 if successful else 1 e g interface not present T int mbed interface powerdown void E POUNCE LOM mboed interface ura This returns a string containing the 32 character UID of the mbed interface This is a weak function that can be overwritten if required Variables uid A 33 byte array to write the null terminated 32 byte string returns 0 if successful else 1 e g interface not present nnt mbed Tntertace urd char Sula Function mbed mac address This returns a unique 6 byte MAC address based on the interface UID If the interface is not present it returns a default fixed MAC address 00 02 F7 F0 00 00 This is a weak function that c
5. mac 4 0x04 mac 5 0x05 E Notel the mbed has the ability to power down the PHY by disabling its oscillator P1 27 The mbed is also able to reset the PHY through P1 28 Both features are not supported on the LandTiger The PHY 1s always enabled and the reset occurs with the reset the LandTiger board Probably best to avoid using P1 27 and P1 28 in your software to prevent interference with the Ethernet library Note2 mbed uses the PHY LED LINK and LED SPEED outputs as digital inputs on P1 25 and P1 26 This allows mbed software to test the status and perhaps activate some other LED The LandTiger PHY has LEDs connected directly to its Link Speed and Traffic outputs The processor pins P1 25 and P1 26 may be used for other purposes USB Device Set jumpers JP9 JP11 to 1 2 Set jumper JP10 to 1 2 Enable USB CONNECT P2 9 VBUS P1 30 not used USB UP LED DI 18 not used USB Host Set jumpers JP9 JP11 to 3 4 Enable USB PPWR PI 19 low USB PWRD P 19 not used The mbed interface functions that are define in mbed_interface h and which should be overriden by user provide code are fe F nction moeda interface connected Determine whether the mbed interface is connected based on whether debug is enabled LandTiger V2 0 User Manual 44 Variables x returns gt L at intertftac us connected else U int mbed interface connected void fx Runetsorr mbed interface reset Instruct the mbed interface to reset
6. EA Ml je Eire ada ma Erase blocks used by Hex File Step 3 Hex File Hex File C prototype PTY PE HEX Modified T hursday HEE B 2009 00 51 49 more into Step 4 Options _ Veri after programming Fill unused Flash Wer block CHECESUME mira or nd E Ei Rotating fully customizable remotely updated Internet links Embed them in your application www embeddedhints cam Figuur 27 Flashmagic Some compilers e g mbed cloud compiler produce a bin file FlashMagic needs a hex file Convert the compiler bin file with a modern bin2hex utility and use the 4 option for either 24 or 32 bit addressing range not the standard 16 bit range Example bin2hex 4 test bin test hex An alternative bin2hex tool is part of the GNU toolsuite arm none eabi objcopy I binary O ihex test bin test hex Download the Bin2Hex from http www hex2bin com bin2hex or if your running a 64 bit system use this instead http www ht lab com freeutils bin2hex bin2hex zip Download the GNU tools from https sourcery mentor com sgpp lite arm portal release 1 802 Download the Keil bin2hex utility http www keil com download docs 113 asp LandTiger V2 0 User Manual 35 Download FlashMagic from www flashmagictool com 4 2 In System Programming ISP using the onboard JLink device LandTiger LPC17XX development board has onboard support for JTAG debugging downloads and other features The debugging port CN4 provides access to the
7. core Clock frequency up to 100MHz Includes support of eight areas of memory protection unit MPU Built m Nested Vectored Interrupt Controller NVIC 512KB on chip Flash program memory supports in system programming ISP and In Application Programming IAP 64KB SRAM for high performance CPU access through the instruction bus system bus data bus access AHB multi layer matrix with 8 channel general purpose DMA controller GPDMA Supports SSP UART DC DS ADC DAC Timer PWM GPIO etc can be used for memory to memory transfer Standard JT AG test debug interface and a serial wire debugging and serial wire tracking port option Simulation trace module supports real time tracking 4 low power modes sleep deep sleep power down deep power down single 3 3V power supply CAN 3 6V Operating temperature 40 C 85 C Non maskable interrupt NMI input On chip integrated power on reset circuit Built in systems timer SysTick to facilitate operating system migration Onboard resources 2 RS232 serial interfaces using straight through serial cable RS232 Transceiver SP3232 One serial port supports ISP download of programs 2 CAN bus communication interfaces CAN Transceiver SN65 VHD230 RS485 communication interface 485 Transceiver SP3485 RJ45 10 100M Ethernet network interface Ethernet PHY DP83848 DAC output interface on board speaker and speaker output driver LM386 ADC input interf
8. e Press Reset button Reset SW1 e Reset signal is input through the JTAG emulator download e Reset signal is input through the ISP COMI port DTR control 2 4 Analog Input ADC Adjustable potentiometer VR1 is connected to analog channel P1 31 ADO 5 JP12 jumper is used to enable the potmeter input VR1 setting provides input voltages between UY and 3V3 to the ADC Tabel 3 Jumper setting for Analog Input JP12 1s used to enable the VR1 connection to ADC input P1 31 ADO 5 VRI Connected to ADO 5 Jumper short No ADC input Jumper removed Figuur 5 ADC Potmeter and Jumper JP12 LandTiger V2 0 User Manual 8 2 5 Digital Analog Conversion Output DAC External speaker circuit is connected to DAC output pin P0 26 The DAC output is enabled by JP2 jumper The speaker is driven by an onboard audio amplifier U2 LM386 Tabel 4 Jumper setting for DAC output JP2 is used to enable the external speaker Speaker connected to P0 26 Jumper short No Speaker output Jumper removed 3 LOS LDIO LD EPE SCH d lt gt me 6 TESE and Ju umper J2 2 6 USB Host LandTiger LPC17XX development board provides a full speed USB 2 0 Host port CN11 through a standard USB A Type connector The USB host port may be used to connect USB peripherals such as USB disk USB mouse USB keyboard and other equipment Set JP9 JP11 jumpers into 3 4 position for the USB Host interface Select USB D USB host JP9 set to 3 4 S
9. examples located in the Keil examples folder for that specific board It just required some minor changes 1 The LCD files should be replaced by the one from a WayEngineer example GLCD SPI LPC1700 c etc 2 The LED initializing and controlling part should be changed as the LEDs are not connected in the same way 3 If Analog inputs are used in the example this has to be fixed too as in the Keil examples the used Analog inputs are on one of the same pins as the LCD data bus 4 Unfortunately as all of the examples are using the Keil uVision compiler you have to download a use the evaluation period to test some of the examples as they exceed the Lite version limit It would have been good if they had made a couple of demonstrations for the free GNU GCC compiler The WayEngineer website has many application examples download the ZIP file Not all of the demonstrations may compile with the latest Keil uVision Most of the times this just required the removal of the chip system files as these had to be loaded from the compiler directory instead Regarding the Keil uVision everything was reported to works great The On board programmer and debugger integrate nicely with the Keil environment so it is very easy to program and debug your application Some problems were noticed getting Keil to recognize and program the board without giving some kind of error This was fixed by the following steps in each project Go to Option for Target
10. 01072 ee TE 42 Ooi Compaciollty wii KT uos ra o ro pv ro o pva e ree o 42 0 2 Compatibrht wt Debe Ces oaa aaa o S oD t EAN 42 0 2 4 Teal OW Ale CORE MC D 42 6 2 2 Downloading new application software 45 6 3 Compatibility with CooCox CoIDE for ARM 45 TITA Interface De crip HOR EE 46 7 1 JTAG standard connector for ISP and Debugging sees eee eee eee 46 7 2 SWD and SWO SWV also called SWV compatibility sees eee eee eee eee eee 50 7 3 1 Serial Wire Output SWO compatbiltw eee 52 7 3 2 Serial Wire Viewer SWV compatibility eee 22 4 9 Cortex LO Pin De due compatibility ue p cR E Enn Ce theta Cebu enses ad Aa 52 13A Cortex 20 Fin Debus compatibility EE 53 PARM ETM breet 53 KREE 55 LandTiger V2 0 User Manual 1 Overview The LandTiger V2 0 NXP LPC 1768 ARM development board is based on a second generation ARM Cortex M3 microcontroller a high performance low power 32 bit microprocessor designed for embedded system applications suitable for instrumentation industrial communications motor control lighting control alarm systems and other fields The board supports USB2 0 Device and Host dual CAN interfaces RS 485 interface and an on board USB emulator for JLINK The development board is supported by a rich set of example software and detailed information to facilitate the users to quickly project development A short feature overview Powerful LPC1768 MCU Cortex M3
11. 2 0 device port CN12 through a standard USB B Type connector Set JP9 JP11 jumper Plugged into 1 2 position for the USB Device interface Select USB D USB device JP9 set to 1 2 Select USB D USB device JP11 set to 1 2 The D line may have a pull up activated to signal high speed mode LandTiger V2 0 User Manual 11 This pull up may either be permanent or controlled by software Select USB D signal pull up resistor mode LED LD14 is ht when the pull up is activated USB pull up control by P2 9 JP10 set to 1 2 P2 9 control signal 19 active low USB permanent pull up JP10 set to 2 3 JO Pin Descripton O Z o o i Activate USB Device pull up LED LD14 is ht when the pull up is activated USB pull up control by P2 9 JP10 set to 1 2 P2 9 control signal is active low Tabel 7 LPC1768 reserved pins for the USB Device functions USB D Connected to either the Host or Device connector by JP9 Release P0 29 pin by removing JP9 USB D Connected to either the Host or Device connector by JP11 Release P0 30 pin by removing JP11 Sense VBUS from host in USB Device mode VBUS is active high Release P1 30 pin by removing R123 USB Device is up indicator LED LD13 is lit when USB is activated active low P1 18 may be used a general purpose output and LD13 may be used as general purpose indicator when USB Device functions are disabled Activate USB Device pull up LED LD14 is ht when t
12. 5 O OF amp SwWOJ TDO T Li 4 WNC TH GMDDetect RER O D 10 nRESET A 10 pin header Samtec FTSH 105 01 is specified with dimensions 0 25 x 0 188 6 35mm x 4 78mm LandTiger V2 0 User Manual 53 7 3 4 Cortex 20 Pin Debug compatibility The Cortex Debug ETM Connector is a new small 20 pin 0 05 connector that provides access to SWD SWV JT AG and ETM 4 bit signals available on a Cortex M3 device A 20 pin header Samtec FTSH 110 01 is specified with dimensions 0 50 x 0 188 12 70mm x 4 78mm Cortex M3 ETM Debug Interface Z pin Connector WTref O 2 S0W0 TMS GND O 4 SWDCLK TCK GRD O 6 SWOEATATRAGECTL TEO ola NC EXTh TDI GNDDetect O 10 nRESET GHD TatPwr Cap O 12 TRACECLK GMD TgiPwreCap 1 O 14 TRACEDATA U GND O 16 TRACEDATA 1 GND O 18 TRACEDATA 2 Ol GND U TRAGEDATA A CORTEX CORTEX DEBUG DEBUG ETM rm o m Figuur 34 Standard and smaller new connectors 7 3 5 ARM ETM Mictor Connector 38 pin The Mictor Matched Impedance ConnecTOR has been the standard way to connect a trace probe to an ARM target It supports up to 32 bit ETM trace and is really intended for use with very high speed ARM processors such as Cortex R4 and Cortex A9 As Cortex M3 ETM only supports 4 bit trace the best connector solution to support debug and ETM is the 20 pin Cortex Debug ETM connector LandTiger V2 0 User Manual 54 LandTiger V2 0 User Manual 25 8 References PowerM
13. CU www PowerMCU com LandTiger Schematic LandTiger V2 0 Schematic pdf HY32D Schematic HY32D SCH pdf HY32C Schematic http propix com pl pl p LCD 3 2 TFT SSD1289 HY 32C 194 ARM www arm com NXP www nxp com LPC1768 Datasheets and Documentation www nxp com Keil Compilers and IDE www keil com JLINK www segger com GNU tools https sourcery mentor com sgpp lite arm portal release 1802 Flashmagic http www flashmagictool com Mbed www mbed org Bin2Hex http www hex2bin com bin2hex or if your running a 64 bit system use this instead http www ht lab com freeutils bin2hex bin2hex zip CooCox IDE http www coocox org
14. IDEs eg Keil IAR CooCox and GNU GDB support JLink flashing and debugging without the need for the standalone JFlash application 4 3 In System Programming ISP using external JLink devices The JTAG S WD interface CN1 may also be connected to any external general purpose JTAG SWD debugging device In this case the on board JLINK emulator must be disabled by inserting JP4 External JLINK devices may be used for programming and debugging the ARM LPC1768 on Land Tiger The JLLINK device is connected to a USB port on your PC and connects to the targetboard using a JTAG connector CNT USB Ethernet Figuur 30 JLINK Setup LandTiger V2 0 User Manual 37 Figuur 31 JLINK Flash and Debug device A PC application program such as JFlash will accept compiled bin files and flash the target processor See www segger com for a range of available devices and supported features Follow the explanations given above on using JLink Commander and JFlash Notel Many well known IDEs eg Keil AR CooCox and GNU GDB support JLink flashing and debugging without the need for the standalone JFlash application Figuur 32 Converter for different JTAG and SWD connectors Note2 The standard connector on JLINK 1s the 20 pm JTAG connector Converter boards and cables may be needed sometimes to connect JLINK to the some of the other JTAG SWD plugs that are in use LandTiger V2 0 User Manual 38 5 Portpin Usage on LandTiger vs mbed Tabel 31 P
15. LandTiger v2 0 Land Tiger V2 0 LPCI7XX Development Board User Manual Version V1 1 www PowerMCU com www PowerAVR com Copyright 2009 PowerMCU Copyright O 2012 WH LandTiger V2 0 User Manual 2 Table of Content Table E E 2 FOY suo m cc TERCER 3 2C reut and imtertace e ardid 5 E ET 5 DD GM S el ee 6 DAS INESCL M O UC sa ein ar Hm 7 2 4 ANAO Input DC y eit oce ate c EE ees a 7 2 5 Digital Analog Conversion Output DAC aka gadi a 8 AO USB e EE 8 SE 10 Deo D atabus miercoles 12 A EAB AAA A E MU m e Ee TS 12 2 8 Conversion C Ir cult DIE deeg nase hee Pone dashes Res deme ed 13 250 9 DIS DIA bag LE 14 GR A a Pm M UE 16 A o a ve ram 16 AN o e S oso 17 DE DA SOS 202 u ed aid da A o is EP ES 18 PA S OS ea kae de NA 19 IAS na a A e a i M Ee LLL Le tate te 20 zale e ooo um m ann ma o m a e e er 27 Dis ode aT dec IE E M 23 PS MONIS PEOR T m E LI MP ED een 24 ZONE Se Te BOONS EE 25 2 19 JTAG Debug Function and JLINK emulator esse sese sees eee 27 PI RR EE 29 SCD THY SC 3 2 320x240 05K CO QUES la 31 4 Downloading Application Software 34 4 1 In System Programming ISP using FlashMagic eese 34 4 2 In System Programming ISP using the onboard JLink device 35 4 3 In System Programming ISP using external JLink deviees ec ana na nakana 36 5 Portpin Usage on Land Tiger VS MDE Geb ss ioo hetero dei itu ano epu en dad ones o ad Recon diues 38 O SOM are T 8
16. UARTI RX line That will release PO 11 pin P0 10 may be used without risk of conflict 2 13 RS 485 The LandTiger LPC17XX development board supports a bi directional RS 485 communication interface via CN10 to UART3 The 485 Transceiver is U14 SP3485 LandTiger V2 0 User Manual 20 Tabel 16 RS485 interface description CN10 Pin Description IOPin 485A UART3 TX P4 28 485B UART3 RX P4 29 JO Pin Description Comment P4 28 485 TX P4 29 485_RX P2 8 485_DIR R Direction RX is active low TX is active high Notel The 458A and 458B inputs outputs are terminated by R84 120 ohm This means the LandTiger should be located on either end of the RS485 bus rather than somewhere in the middle Note2 The 458A and 458B inputs outputs do not have pull up pull down resistors to provide a defined bias idle voltage These resistors may have to be added externally Note3 The 485 interface may be disabled by removing R77 in 485 RX line that will release P4 29 pin Also remove R76 in 485 DIR line to release P2 8 P4 29 may be used without risk of conflict 244 a 222 py 3934 De 211 if Ssa J 0 9 Gea BAL A RRR e 49 15M E nel NN gt Qu EL E hy d VEH ei BLESS gt dE US AS Figuur 15 CANI und CAN2 connector CN8 RS485 Connector CN10 2 14 SD card The Land Tiger LPC17XX development board supports an SD card interface CN6 The SD card 1s accessed through the LPC1768 s SSPO port A car
17. ace on board adjustable potentiometer input Color LCD display interface supports 2 8 inch or 3 2 inch color TFT 320X240 Touchscreen supported through SPI interface USB2 0 Interface USB host and USB Device interface SD MMC card SPI interface DC Interface connected to onboard 2Kbit EEPROM 24LC02 SPI serial interface connected to onboard 16Mbit Flash AT45DB161D 2 user keys 2 function keys INTO and Reset button 8 LED lights Digital outputs Five way joystick button Digital Inputs LandTiger V2 0 User Manual e Serial ISP download support COMO e Standard JTAG download simulation debugging interface e Integrated JLINK compatible emulator USB support online simulation and debug capabilities support KEIL IAR and other mainstream development environments e Optional external 5V power supply or USB input to provide 5V power supply e Breakout available for all the IOs user friendly connection of external application development circuits EE il Ee Landliger ee www PewerAVRcoom m www Power CU com a Ta LI A a PA e User Key AD adjust 5 DIR KEY 8 t16bit A c TET Reset Key Fo switch Interface Figure 1 Board Overview Note Picture shows version 1 0 of the board L I oT parini L lt 1 D T i a J k ol T i k i Frk x1 a I Fa Loa FL p s D E el L zi i pb kra aaa HH ETT Ce K i EBE Bk leer d RE d b Tek Te X nazala I Sr su 1 9 i
18. an be overwritten if you want to provide your own mechanism to provide a MAC address LandTiger V2 0 User Manual 45 Variables mac A 6 byte array to write the MAC address ui void mbed mac address char mac Function mbed die Cause the mbed to flash the BLOD LED sequence ier void mbed die void 6 2 2 Downloading new application software The mbed cloud compiler produces a bin file Convert the compiler bin file with a modern bin2hex utility to prepare the software for Flashmagic JLINK will accept the bin files directly and flash the processor 6 3 Compatibility with CooCox CoIDE for ARM CooCox CoIDE for ARM 1s a free Eclipse based IDE for ARM Cores using the GNU Compiler GCC It supports ARM7 9 targets as well as Cortex M0 M3 M4 targets More information about CoIDE and the installation process can be found here http www coocox org Please note that when using CoIDE for the first time some additional setup is required to enable GCC in CoIDE For more information please refer to http www coocox org CoIDE Compiler Settings html In the following a short step by step tutorial how to get up and running with CoIDE and J Link in general is given For this tutorial the sample project generator that 19 integrated into CoIDE was used Used components IDE CoIDE V1 4 0 Emulator J Link J Link SW Version V4 40c Evalboard STM32F103ZE EVAL STM32F103ZG Additional SW GCC Toolchain Start CoIDE and clic
19. anual 31 3 Color LCD 3 2 320x240 65K colours LandTiger is compatible with several types of Color LCDs There are currently two types of 3 2 displays available Both displays are functionally identical but have different LCD panels and some differences in the electrical design The displays are identified as HY32C and HY32D Notice that LCD HY32C has only one row of connectors and HY32D has two connectors with identical pinout Physical dimensions and mounting holes are also identical 3 2 TFT LCD Display Module MODEL HY32D www PowerMCU com www PowerAVR com Figuur 26 HY32C left and HY32D right seen from rearside Tabel 29 Characteristics of the LCDs Backlight Backlight LandTiger V2 0 User Manual 32 The main difference in the electrical design is that the HY32C has a different LCD panel which also needs a voltage up converter to drive the backpanel LEDs The converter device is the RT9293 Notel The schematic of HY32C is not available Note2 The schematic of HY32D is available as part of the LandTiger documentation Tabel 30 Pinout Description of LCDs Pin Name Description Comment 5V 5V power supply When powered from 5V supply IT Pin 1 amp Pin 2 as power input Pin 33 amp Pin 34 provide 3 3V output 3 DO T Daa Dnes DODIS _ _ S a 5 A ooo 20 Instruction Data register RS 1 Instruction Register selection RS O The Sg Register INC Domaci Domini
20. ataFlash MOSI P0 17 DataFlash MISO LandTiger V2 0 User Manual 17 P0 16 DataFlash CS active low P0 15 DataFlash SCK Notel The Slaveaddress of the FLASH Note2 The SPI CS has a pull up R installed of 10K to 3V3 Note3 The WriteProtect of the DataFlash 1s disabled pull up to 3V3 Note4 The Flash may be disabled by removing R59 in CS line That will release P0 16 pin P0 15 P017 PO 18 may be used without risk of conflict Figuur 12 SPI Flash 45DB16D U7 2 11 CAN The LandTiger LPC17XX development board supports 2 CAN2 0 A B bus communication interfaces CAN 1 uses UART XX CAN 1 uses UART XX The CAN Transceivers are U12 and U13 SN65HVD230 The CAN bus screw terminal accepts 5 08mm pitch leads Tabel 13 CAN interface description CNS Description IO Pin M e oun ET AA 3 CANIL POOPOL 4 CAN2H PO4ros 5 CAN2L P0 4P05 or JOPin Description Comment P0 0 CANI RX CANRXI TXD3 CANI TX CANTXI RXD3 LandTiger V2 0 User Manual 18 CAN2_RX CANRX2 CAN2_TX CANTX2 R82 j a A A Dn 3 di geg 232 pm 2332 pa Jill AD ES m I o CH dom CH ZC K Ie dad te dl E a Figuur 13 CANI and CANZ2 connector CN 8 RS485 Connector CN10 Notel The CANI and CANT inputs outputs are terminated by R129 and R128 120 ohm This means the LandTiger should be located on either end of the CAN bus rather than somewhere in the middle Note2 The CANI may be disa
21. bled by removing R74 in CANI RX line That will release P0 0 pin PO 1 may be used without risk of conflict Note3 The CAN2 may be disabled by removing R72 in CAN2_RX line That will release DO A pin P0 5 may be used without risk of conflict 2 12 RS 232 The Land Tiger LPC17XX development board supports two bi directional RS 232 Communication interfaces COMI COM connected to LPC1768 UARTO and UART2 The RS232 Transceivers 1s U10 SP3232 The COMI RS 232 interface may also be used for automatic ISP programming serial download program The port provides two control signals for RESET and ISP activation The circuitry is compatible with the ISP standard as defined by NXP Note JP6 JP7 jumpers must be installed to use serial programming procedures Tabel 14 COMI interface description Pin Description IOPin o NC OND 0 GND 6 NC 7 RTS RTS Control ISP P2 10 Boo Je A LandTiger V2 0 User Manual 19 o GND Tabel 15 COM2 interface description Shield Shield Enable ISP Select Enable ISP Select JP6 inserted Disable ISP Select JP6 removed Enable ISP Reset Enable ISP Reset JP7 inserted Disable ISP Reset JP7 removed Figuur 14 RS232 connector COMI COM2 female front view Notel The COMI UARTO may be disabled by removing R70 in UARTO RX line That will release P0 3 pin PO 2 may be used without risk of conflict Note2 The COM2 UARTI may be disabled by removing R71 in
22. completion of download Reset again to activate the new code New program download through JT AG Key2 1s connected to INT2 P2 12 The USB Host will detect the LPC17XX as a mass storage device holding one binary file the current program Delete that file and download a new one through USB Reset again to activate the new code Note a special USB bootloader must be stored in Flash first See NXP documentation Insert Jumper to enable manual entering ISP mode Insert Jumper to enable external Reset Insert Jumper to enable external entering ISP mode LandTiger V2 0 User Manual 27 pecas C67 NW ie Dices cee 7 TELLERE Hilik T Ime Figuur 21 Jumper settings to enable serial port COMI ISP Jumper JP6 ISP mode enable by RTS Jumper JP7 Reset enable by DTR Note Jumper JP5 manual ISP mode enabled by pressing Key2 Notel The serial bootloader is a standard feature of NXP processors Free PC software like FlashMagic may be used to download a compiled application program FlashMagic is able to control Reset and INTO to initiate the ISP without need for the user to press any buttons on the board itself The appropriate jumpers JP6 JP7 must be installed Note2 SW2 INTO may be used as normal IO pin during program execution The special function to enter ISP is only used during reset Note3 SW3 Key2 INT2 may be used as normal IO pin during program execution The special function to ente
23. d ER P1 24 PL24 MCFB2 PWMLS MOSIO MOSIO SDCad NE o y O P1 29 P1 29 MC2B PCAPI I MATO1 JOY UP Joystik NO o y O Tabel 33 Port 2 description u i i Usage LandTiger Comment LandTiger Usage mbed Comment mbed P2 6 P2 6 PCAP1 0 RII TRACECLK_ DB066 LCD Bus NC P27 PZ27RDZRTS DBO LCD Bus NL P2 8 P2 8 TD2 TXD2 485 DIR Ram IN P2 9 P2 9 USB CONNECTIRXD2 gt USB_CONNECT USB Host Device USBCON _________ P2 10 P2 10 EINTO NMI rr ISP SWQ2JPSIRTSJP6 TGTSBLISP LandTiger V2 0 User Manual 4 P2 11 P2 1I EINTI DSTX CLK KEY SW4 NC P2 12 P2 12 EINT2 DSTX WS KEY ISW3 UNI P2 13 P2 13 EINT3 DSTX SDA TP INT EINT3 JTAG IRQ on mbed Tabel 34 Port 3 description e PM Usage LandTiger Comment LandTiger Usage mbed Comment mbed P3 25 P3 25 MATO 0 PWMI 2 SD CD SD Card NCS So P3 26 P3 26 STCLK MATO 1 PWM1 3 SD PWR SD Card INC o Tabel 35 Port 4 description EMO Usage LandTiger Comment LandTiger Usage mbed Comment mbed P4 28 P4 28 RX MCLK MAT2 0 TXD3 485 TX RS485 INC o P4 29 P4 29 TX MCLK MAT2 1 RXD3 485 RX RS485 INC fo LandTiger V2 0 User Manual 42 6 Software compatibility 6 1 Compatibility with Keil See http blog tkjelectronics dk 201 1 09 review poweravr nxp Ipc1768 board The board has basically the same features and connections as the Keil MCB1700 This made it possible to use the
24. d detection signal is available The power supply to the SD card is under control of the LPCI7XX LandTiger V2 0 User Manual 21 Tabel 17 SD Card connector CN9 SD Description Pin 1 SDcard CS P1 21 SSELO Active Low SDcard DIN P1 24 MOSIO Vss GND Vss GND 3V3 P3 26 controlled SDcard CLK P1 20 SCKO Vss GND Vss GND SDcard DOUT P1 23 MISOO NC NC Tabel 18 SD Card controlsignals 7 10 11 6 I 8 9 0 u Description P1 21 SDcard CS Active Low P3 26 SD Power Active Low LD3 is lit when power in on P3 25 SDcard detect Active Low Pl 28 s E po o O OPi 29 po 10 O OPo 1 p2 13 O OP0 11 ss SS TI URL pH IW Jj Figuur 16 SD card socket Power on LED LD3 is located on frontside of board Notel The SD card interface may be not be fully disabled by removing 0 Ohm resistors The best option is to prevent a card from being inserted Removing R52 in SD CS line will release P1 21 pin Remove R54 in SD CD line to release P3 25 P3 26 and LD3 may be used without risk of conflict LandTiger V2 0 User Manual 22 2 15 Ethernet The LandTiger LPC17XX development board has onboard support for 10 100 Mbit s Ethernet communication The LPC1768 chip supports the RMII interface and links to the DP83848 U5 Ethernet PHY chip This device interfaces out via the RJ45 connector CN5 which has internal magnetics and network filters The RJ45 connector has integrated LEDs to indicate link connec
25. ed JIAG speed 166 kHz J Link Jlink exe J Flash 1s PC software running on Windows Windows 2000 and later systems which enables you to program the internal and external flash of your microcontroller via J Link LandTiger V2 0 User Manual 36 24 Krah ARH YL Lia Beta LT Porapram Files B Y SE GER LAA Va a Samples a Pepe igj xj Fe Cot Vee Ted Geto rom hp Correo LISE Erratas D Target diede JTAG m R aal d AEL El PEPE EEE PEt Vt JT Bda gee AM LHS S8ESESSSRREZE 22232323222v FT TTT TT FETT 1 ERES EFETETETE risas 22322332325 82322223 TAIS TES inia Pret ged tage DOJI TESOU gt DOT ZFIFF Band 1 ga j Ou Ma em emm DN DIT X2 bur x T de LI LI LI LI 1 1 1 1 1 1 1 1 1 1 1 LI LI LI LI 1 1 1 1 1 1 LI 1 1 1 1 B aa E E T ER i ENEE 4 LI LI LI LI LI LI LI LI LI LI LI LI LI LI LI LI LI LI LI LI LI LI LI LI LI LI LI LI LI LI LI LI LI LI 1 LI 1 1 LI 1 1 LI 1 1 F kA ZW Do RB W es E b LI LI LI LI T 1 1 1 1 1 1 1 1 1 LI LI LI LI 1 1 1 1 1 1 1 1 1 1 MCU device bn E Porres Fite SEH RA sc ma SC E eet CeCi ed after Z 145 de EE Trnja _ ere ri Figuur 29 JFlash In JFlash you first need to select the proper device LPC1768 from the device database then select the bin file and flash that into the target processor Detailed instructions are given in the JLink and JFlash manuals See www segger com Notel Many well known
26. elect USB D USB host JP11 set to 3 4 Connected devices should be provided with 5V power This power 15 activated under control of the user program Note that maximum current 19 limited LandTiger V2 0 User Manual JO Pin Descripton 4 Activate USB Host power LED LD15 is lit when power is activated USB power control by P1 19 control signal 1s active low Tabel 5 The LPC1768 reserves a number of pins for the USB Host functions JO Pin Descripton O 2 USB D Connected to either the Host or Device connector by JP9 Release P0 29 pin by removing JP9 P0 30 USB D Connected to either the Host or Device connector by JP11 Release P0 30 pin by removing JP11 S Sense USB Host power state USB powersense by P1 22 input signal is active high Release P1 22 pin by removing R78 P1 19 Activate USB Host power LED LD15 is lit when power is activated USB power control by P1 19 control signal 1s active low P1 19 may be used a general purpose output and LD15 may be used as general purpose indicator when USB Host functions are disabled Tabel 6 CN11 USB AB type pin functions Typical wire colour VBUS 5V Notel The figure shows a front view of the socket left and the plug 1s facing you LandTiger V2 0 User Manual d An Zeat E ci2 r Re5 a d Figuur 8 USB Jumpers and LEDs 2 7 USB Device The Land Tiger LPCI7XX development board provides a full speed USB
27. he pull up is activated USB pull up control by P2 9 JP10 set to 1 2 P2 9 control signal is active low P2 9 may be used a general purpose output and LD14 may be used as general purpose indicator when USB Device functions are disabled LandTiger V2 0 User Manual 12 Tabel 8 CN12 USB B type pin functions Pin Description Typical wire color Figuur 9 USB B Device Connector CN12 left and Plug right Notel The USB Device port CN12 can not be used to power the LandTiger board Power must be supplied either by the external power connector or by the USB debug port CN4 2 8 Databus Interface The ARM LPC1768 does not have a separate data address and controlbus The LandTiger board is designed to emulate a simple processorbus by using some of the regular port pins Port pins P2 0 P2 7 represent an 8 bit databus The datalines are connected to an 8bit 16bit conversion circuitry provided by US and U9 A number of controllines are also available that provide RD WR CS and RS The LPC1768 Resetline is also available The main use for the bus is to control an LCD display However the design 19 generic and may be used to control other peripheral hardware also 2 8 1 LED Interface The 8 data lines P2 0 P2 7 are directly connected to a 74LV244 driver U11 followed by 8 red LEDs LD4 LD11 The LEDs display the current bitpattern on the databus The LEDs may be disabled by removing JP8 Enable databus LED
28. his pin 1s not used by J Link when operating in SWD mode If the device may also be accessed via JTAG this pin may be connected to RTCK otherwise leave open 13 SWO Output Serial Wire Output trace port m orm Optional not required for SWD communication 15 RESET I O Target CPU reset signal Typically connected to the RESET pin of the target CPU which is typically called RST nRESET or RESET This pin is not connected in J Link 19 5V Supply Output This pin is used to supply power to some eval boards Not all JLinks supply power on this pin only the KS Kickstart versions Typically left open on target hardware LandTiger V2 0 User Manual 22 Notel Pins 4 6 8 10 12 14 16 18 20 are GND pins connected to GND 1n J Link They should also be connected to GND in the target system 7 3 1 Serial Wire Output SWO compatibility J Link can be used with devices that support Serial Wire Output SWO Serial Wire Output SWO support means support for a single pin output signal from the core It is currently tested with Cortex M3 only The supported SWO speeds depend on the connected emulator They can be retrieved from the emulator Currently the following are supported Speed formula Resulting max speed J Link V6 6MHz n n gt 12 500kHz J Link V7 6MHz n n gt 1 7 3 2 Serial Wire Viewer SWV compatibility The Instrumentation Trace Macrocell ITM and Serial Wire Output SWO can be used
29. i F Clan Ai L y d y a J E a LI I LI GT XJ Wi KESE pas FT s ie Ej EE r A FLASH ZLEL ELIGO Lx a E Lx vw rm i niu Erg o ax atem cuv n d ef De x K i a i i i L 1 d a L LI LI d FE i T F E De xd D d LI L U w 8 x EI n 1 d i d I Lj LandTiger V2 0 User Manual 5 2 Circuit and interface description Due to the limited space 1n this manual please use the circuit schematic reference for additional details on ICs and specific functions 2 1 Power supply The LandTiger development board may be powered by an external 5V power input or by the USB debug interface 5V power input e 5V DC power adapter connected to CN9 power select jumper JP3 plugged into 1 2 selects the external 5V power supply e Connecting the PC USB cable to the USB debug port CN4 and power select jumper J3 plugged into 2 3 will choose USB 5V supply The board will be powered by the PC USB port maximum current of 500mA limit Tabel 1 Jumper settings for powersupply select JP3 is used to select the external 5V power supply or USB powersupply External 5V power supply Jumper short 1 2 USB powered Jumper short 2 3 E c20 OI ca r cooler mogi Figuur 2 Powersupply Jumper JP3 connector CN9 and main powerswitch Main powersupply switch SW6 is provided to switch the board on or off LED LD11 indicates when the board is powered LandTiger V2 0 User Manual Notel CN9 powerconnector inner pin 1s p
30. ically connected to TMS of target CPU JT AG clock signal to target CPU It is recommended that this pin 19 pulled to a defined state of the target board Typically connected to TCK of target CPU Return test clock signal from the target Some targets must synchronize the JT AG inputs to internal clocks To assist in meeting this requirement you can use a returned and retimed TCK to dynamically control the TCK rate J Link supports adaptive clocking which waits for TCK changes to be echoed correctly before making further changes Connect to RTCK if available otherwise to GND JT AG data output from target CPU Typically connected to TDO of target CPU RESET Target CPU reset signal LandTiger V2 0 User Manual 48 Typically connected to the RESET pm of the target CPU which is typically called nRST nRESET or RESET 17 DBGRQ NC This pin is not connected in J Link It is reserved for compatibility with other equipment to be used as a debug request signal to the target system Typically connected to DBGRO if available otherwise left open This pin can be used to supply power supply to the target hardware Notel All pins marked NC are not connected inside J Link Any signal can be applied here J Link will simply ignore such a signal Note2 Pins 4 6 8 10 12 14 16 18 20 are GND pins connected to GND 1n J Link They should also be connected to GND in the target system Note3 Pin 2 19 not connected
31. ing 0 Ohm resistors Removing R65 R66 R67 R68 and R69 will release P1 29 P1 28 P1 27 P1 26 and P1 25 2 17 Switches The LandTiger LPC17XX board features 4 switches Keyl SW4 Key2 SW3 INTO SW2 RESET SWI These switches have several functions See table below Figuur 20 Switches and Alternate functions LandTiger V2 0 User Manual Tabel 22 Switch Description Key type Connected to INTI P2 11 Active Low Pull Up R of 10K installed Connected to INT2 P2 12 Active Low Pull Up R of 10K installed Connected to INTO P2 10 when JP5 is inserted Active Low Pull Up R of 10K installed INTO 25 SW3 Secondary function to enter the USB ISP mode SW2 Secondary function to enter the COMI ISP mode Notel Keyl may be disabled by removing R64 this will release P2 11 Note2 Key2 may be disabled by removing R63 this will release P2 12 2 18 Reset and Booting The LandTiger LPCI7XX development board has several options for Reset and booting Tabel 23 Reset and Boot options Reset type The board will reset when power is applied The LPC17XX will boot by starting the user program stored in internal Flash 512 KB ytes The board will reset whenever the user presses the Reset key Manual Reset and enter ISP mode after Power On reset The device will enter the ISP programming mode when INTO SW2 is pressed and held before applying a Reset The device 1s then ready to accep
32. inside J Link A lot of targets have pin 1 and pin 2 connected Some targets use pin 2 instead of pin 1 to supply VCC These targets will not work with J Link unless Pin 1 and Pin 2 are connected on the target s JTAG connector Note4 Pin 3 TRST should be connected to target CPUs TRST pin sometimes called NTRST J Link will also work if this pin is not connected but you may experience some limitations when debugging TRST should be separate from the CPU Reset pin 15 Note5 Pin 11 RTCK should be connected to RTCK 1f available otherwise to GND Note6 Pin 19 5V Target supply of the connector can be used to supply power to the target hardware Supply voltage is 5V max current is 300mA The output current is monitored and protected againts overload and short circuit There are also other JTAG connectors in use This includes e 20 pin JT AG version with 2mm pin pitch and the same pinout as standard JTAG e 14 pin JT AG version with 2 54mm pin pitch e 10 pin JT AG version with 2 54mm 0 1 pin pitch e 10 pin JT AG version with 2 00mm pin pitch e OpinJT AG version with 1 27mm 0 05 pin pitch e 19 pin JTAG version with 1 27mm 0 05 pin pitch e Opin 2 54mm pin pitch socket SWD Interface for Cortex Core e 4pin2 54mm pin pitch socket SWD Interface Cortex Core Tabel 38 JTAG interface 14 pin connector signals Pin Signal Type Description l VTref Input This is the target reference voltage It is used t
33. k New Project button from the status bar Enter a Project Name and click Finish Zie screendumps Zie http www segger com cms IDE_Integration_coocox html Copy ook de screenshots LandTiger V2 0 User Manual 46 7 JTAG Interface Description The JT AG technology was defined by IEEE Std 1149 1 standard and it exists for over a decade JT AG is used mostly for Connection testing and In System Programming ISP The JT AG interface is 4 5 pin interface added to a chip the interface is designed such that multiple chips having a JT AG interface have their JTAG lines daisy chained together and a test probe need only connect to a single JTAG port to have access to all chips on a circuit board The basic connector pins are Tabel 36 Basic JTAG Signals Pin Signal Description Comment Test Data In TDO TesDaaOu 3 mk tex oc 7 4 TMS TestModeSelet o o TRST 7 1 JTAG standard connector for ISP and Debugging Many modern programmable devices such as FPGAs and CPLDs are designed not only to be JTAG compliant but also support additional JTAG functionality to allow them to be programmed after they have been attached to the circuit Other devices such as some flash memories can be programmed indirectly through their connection to devices in the JTAG chain The ability to use JTAG to program devices in system avoids the need to buy expensive programmers and socketed devices There is also the advantage of bei
34. l Tabel 27 JTAG Mode Settings JP4 JTAG SEL Insert Jumper to enable external JTAG device Remove Jumper to enable onboard JLINK emulator Tabel 28 JLINK Interface Status Flash 10Hz Un Initialized FlashlHz Pool Solid on Initialized Ready Short Flash Communication Ooo E BE 29 Notel The board may be powered by the USB JLINK debugging port CN4 Set Jumper JP3 to position 2 3 2 20 External Connector The LandTiger LPC17XX development board has soldering connectors to provide access to all processor I O pins powersupply and GND KEE EN petir Ulo EP FA Es SS A HY LandTiger www PowerAVE com www PowerMCU com AE TANIA BEAN ik r un Figuur 23 External Connector front on sana O p2 9 20 16 10 POIS POLIT OO p010 POIS E pt 20 PO zi PO TZ GHO wy c 2 Pili oO Pele ALS UNZ LandTiger V2 0 User Manual oct ma OD Pa O 0 ni ene CO O an Ha D O Mi ma O O SI 1 O Or Bis OO RI ER o o AE en O O x i a OO ka FE BR Daten mas ma OO CS OO mE room HY LandTiger no 00 Se 00m www PowerAVR com Hi CH CO mi ka con mu e O wh Ai OO AU d 0 O raj a D O mm se OC t7 Lie ot ma is O O 5 www PowerMCU com Figuur 24 External Connector rear The pindescription is printed on the silkscreen both front and rearside of PCB A detailed list of all pins and how they are used on the LandTiger is given in the Appendix LandTiger V2 0 User M
35. levels to the target It is normally fed from LandTiger V2 0 User Manual 50 Vdd of the target board and must not have a series resistor Vsupply NC This pin is not connected in J Link It is reserved for compatibility with other equipment Connect to Vdd or leave open in target RESET RESET board Typically connected to TDI of target CPU system Target CPU reset signal Typically connected to the RESET pin NC TDO NC Input JT AG data output from target CPU m Typically connected to TDO of target CPU Output JT AG mode set input of target CPU This pin should be pulled up on the of the target CPU which is typically called nRST nRESET or target Typically connected to TMS of target CPU E O RESET Target CPU reset signal Typically connected to the RESET pin of the target CPU which is typically called nRST nRESET or RESET JTAG data input of target CPU It is recommended that this pin is pulled to a defined state on the target JTAG clock signal to target CPU It is recommended that this pin is pulled to a defined state of the target board Typically connected to TCK of target CPU CM T 10 y 7 2 SWD and SWO SWV also called SWV compatibility The J Link and J Trace support ARMs Serial Wire Debug SWD The SWD replaces the standard JTAG port with a clock SWDCLK and a single bi directional data pin SWDIO providing all the normal JTAG debug and test functionali
36. ng able to easily update the image held on the device The standard 20 pin 2 54mm 0 17 JTAG connector was defined by ARM J Link has a built in 20 pin JTAG connector which is compatible with this standard v 19 71 1513 119 7 53 1 LIU UL LUDU LL D LI EJ 1 LIEIULILELILI EI DH 20 181614 1210 6 6 4 2 Figuur 33 JTAG Standard 20 Pin Connector Tabel 37 Standard JTAG interface 20 pin connector signals Pin Signal Type Description VV This 1s the target reference voltage LandTiger V2 0 User Manual Vsupply i DO RTCK Input d Input 47 It is used to check if the target has power to create the logic level reference for the input comparators and to control the output logic levels to the target It is normally fed from Vdd of the target board and must not have a series resistor This pin 1s not connected in J Link It is reserved for compatibility with other equipment Connect to Vdd or leave open in target system JT AG Reset Output from J Link to the Reset signal of the target JT AG port Typically connected to nTRST of the target CPU This pin is normally pulled HIGH on the target to avoid unin tentional resets when there is no connection JT AG data input of target CPU It is recommended that this pin 19 pulled to a defined state on the target board Typically connected to TDI of target CPU JT AG mode set input of target CPU This pin should be pulled up on the target Typ
37. o check 1f the target has LandTiger V2 0 User Manual TT 6 GND LI 8 GND Bl 49 power to create the logic level reference for the input comparators and to control the output logic levels to the target It is normally fed from Vdd of the target board and must not have a series resistor Target CPU reset signal Typically connected to the RESET pin of the target CPU which is typically called nRST nRESET or RESET JT AG data input of target CPU It is recommended that this pin is pulled to a defined state on the target board Typically connected to TDI of _ o CPU Rt mode a a CP mode set input of target CPU This pin should be pulled up on the target Typically connected to TMS of nm CPU TAC a OR clock signal to target CPU It is recommended that this pin 1s pulled to a defined state of the target board Typically connected to TCK of CPU Hs naa CRIT data output from target CPU Typically connected to TDO of target CPU 42 nSRST II B This pin 19 not connected in J Link It is reserved for compatibility with other equipment Connect to Vdd or leave open in target system 14 GND J Jg O Tabel 39 JTAG interface 10 pin connector signals Pin Signal Type Description This 1s the target reference voltage It is used to check if the target has power to create the logic level reference for the input comparators and to control the output logic
38. on board JLINK emulator U3 JLINK is a JTAG emulator designed for ARM cores It connects via USB CN4 to a PC running Microsoft Windows 2000 Windows XP Windows 2003 Windows Vista or Windows 7 The JTAG SWD interface and JLINK emulator supports KEIL IAR and other mainstream development environments A PC application program such as JFlash will accept compiled bin files and flash the target processor See www segger com for supported features Download JFlash software from www segger com Install the software and run the JLink commander application J Link commander JLink exe is a command line based utility that can be used for verifying proper functionality of J Link as well as for simple analysis of the target system It supports some simple commands such as memory dump halt step go etc to verify the target connection E C Program Files x86 SEGGER JLiINkKARM_V445a JLink exe SEGGER J Link Commander W4 45a 477 for help Compiled Apr 2 2612 19 53 38 DLL version V4 45a compiled Apr 2 2812 19 53 21 Firmware J Link ARM US compiled Mar 19 2612 10 24 49 Hardware U B SzH 58004070 UTarget 3 3HHU TotalIRLen IRPrint p E S T 8 E Found Cortex M3 ripi Little endian TPIU fitted FPUnit 6 code CBP slots and 2 literal slots Found 2 JTAG devices Total IRLen 9 HA Id Bx3BABB477 IRLen 64 IRFrint Axi CoreSight JTAG DP CARM gt Hi Id 6x66410841 IRLen HE IHPrint Bxl STM32 Boundary Scan Cortex M3 identifi
39. ort O description m ai Usage LandTiger Comment LandTiger Usage mbed Comment mbed P0 0 PO O RDI TXD3SDAL CANLRX CAN JP SDAVTXD3 P0 6 PO 6 2SRX SDA SSELI MAT2 O TP_CS Touchscreen Ip asp ol PUR PO 8 2STX WS MISOILMAT22 MISOI Touchscreen PO MO _P0 9_ PO 9 2STX SDA MOSII MAT23 MOSII Touchscreen JP MOST P012 NA ll CAME O E BE NA IIS P0 19 PO IS DSRISDAL 1 LCDEN LOhzie NC P0 20 PO 20 DTRI SCLI LCD LE ICD8 l6 NC O P0 21 PO 2VRIVRDI LCDDIR LCD8_16 NC o y O P0 23 P0 23 AD0 0 122SRX_CLK CAP3 0 LCD RS ADO 0 LandTiger V2 0 User Manual 39 P0 27 PO27 SDAUUSB SDA 1 SDA EEPROM NE P0 28 PO28 SCLUUSB st SCL EEPROM NL mii 1 X Tabel 32 Port 1 description dk AIR Usage LandTiger Comment LandTiger Usage mbed Comment mbed IB gt PL3 NAC PLS NAC Pio INe e FE e A OM DI VJs RM N J M A AS ee PL INA TTT FE A E PL I6 PI I6 ENET MDC ENET MDC EN MDC LandTiger V2 0 User Manual 40 _PL 18_ P118 USB UP LED PWMLICAPLO USB UP LED USB Host Device LEDI o o P1 19 P1 19 MC0A USB_PPWR CAP1 1 USB_PPWR_ USB Host Device NC P1 20 P1 20 MCFBO PWM1 2 SCKO_ SCKO SDCard______ LED2 J o P1 21 P1 21 MCABORT PWM1 3 SSELO SD CS SD Card ER P1 22 PL22 MCOB USB PWRD MATIO USB PWRD USB Host Device NC o Z o o y y O P1 23 PL2 MCEBI PWMI 4MISO0 MISOO SD Ca
40. ositive outer ring 1s negative The mput voltage must not exceed 5V 5 Plug dimensions 5mm outside 2 5mm inside DC 5V Figuur 3 External 5V powersupply connector CN 9 Note2 The USB Device port CN12 can not be used to power the LandTiger board Note3 Insert JP1 jumper to connect the onboard battery to the RTC when the board is disconnected from the external powersupply when JP1 1s open the RTC will only run as long as power is supplied and not maintain time when switched off Tabel 2 Jumper settings for RTC powersupply JP1 is used to connect onboard backup battery to the RTC Battery backup Jumper inserted No battery backup Jumper removed batteryholder BT1 Notel The RTC backup battery type 1s CR1225 Lithium 3V 2 2 Clock source The development board has four different clock sources System clock Realtime Clock RTC clock Ethernet clock and Debugger interface clock e Y1 12 MHz crystal is the main system clock source the internal RC oscillator of the CPU can not be used e Y2 32 768 kHz crystal is the clock source for the RTC e U4 SOMHZ crystal is the Ethernet PHY chip DP83848 clock LandTiger V2 0 User Manual 7 e Y3 8 MHz is the clock for the JLink Debugger interface Note 1 See section 2 1 on powersupply and onboard battery backup for the RTC 2 3 Reset Mode The reset signal in the Land Tiger LPCI7XX development board is active low reset The reset modes include the following
41. r USB bootloader is only used during reset 2 19 JTAG Debug Function and JLINK emulator LandTiger LPC17XX development board has onboard support for JTAG debugging downloads and other features The debugging port CN4 provides access to the on board JLINK emulator U3 JLINK is a JTAG emulator designed for ARM cores It connects via USB CN4 to a PC running Microsoft Windows 2000 Windows XP Windows 2003 Windows Vista or Windows 7 JLink has a built in 20 pin JTAG connector CN 1 which is compatible with the standard 20 pin connector defined by ARM The JTAG SWD interface and JLINK emulator supports KEIL IAR and other mainstream development environments The JTAG SWD interface CN1 may also be connected to any external general purpose JTAG SWD debugging device In this case the on board JLINK emulator must be disabled by inserting JP4 LED LD1 shows the current status of the JLINK debugger interface LandTiger V2 0 User Manual v 19 17 1513 119 7 5 3 1 LI UI DU U D LU D ETT U GUO ROA DH 20 181614 1210 8 6 4 2 Figuur 22 JTAG Connector CN1 for External JTAG device Tabel 25 JTAG Connector CN1 IIA OND LI TDI 0 OND J TMSISWDIO o OND TCKISWDCLK OND TI PRICK LI OND Il TDOSWO J 9 DBGACK OND a Tabel 26 SWD CN3 Connector Pin Description Comment END O SWDIO Il OND 5 SWDCLK AAA OND TI 28 LandTiger V2 0 User Manua
42. s LEDs enabled JP8 inserted LEDs disabled JP8 removed Notel the datalines are shared with the LCD and the LEDs will show any databus activity to the LCD Note2 P2 7 corresponds to LD4 leftmost P2 0 corresponds to LD11 rightmost LandTiger V2 0 User Manual 13 LDS LD6 LD7 LOS LDS LDIO LD1 i f E e N sf LI 2 P A d u Figuur 10 LEDs and Enable Jumper J8 2 8 2 Conversion Circuit 8bit 16bit The datalines are connected to an 8bit 16bit conversion circuitry provided by US 16bit bidirectional buffer 74ALVC164245 and U9 8bit latch 74LV 573 The tables below show the steps needed to use the 8 16 bit conversion circuitry for Read and Write operations There are 3 specific controllines required for the 8 16 bit conversion unit LCD DIR LCD EN LCD LE Tabel 9 Write operation sequence for 16 bit Databus Control datapin IOPin Set P2 0 P2 7 as Output Set Buffer Direction LCD DIR 1 P0 21 to WR pe Tabel 10 Read operation sequence for 16 bit Databus Control datapin IOPin Set P2 0 P2 7 as Input E H Set Buffer Direction LCD DIR P0 21 to RD Enable MSB buffer outputs LCD EN 0 P019 LCD CS 0 P0 22 0 Select Data Control Reg LCD RS X P0 23 Read Data Start LCD RD 20 P0 25 LandTiger V2 0 User Manual 14 Read DOS D15 Read MSBs P2 0 P2 7 Enable LSB buffer outputs LCD ENZ P019 Read DOO D07 Read LSBs P2 0 P2 7 Read Data End LCD RD 1 P0 25 LCD CS 1 P0 22
43. t and store new user code in the internal Flash The board will reset whenever DTR is activated on COMI and then behaves just as after Power On reset External Reset SW1 and then behaves just as SW2 is only connected to INTO P2 10 when JP5 is inserted New program download through COMI UARTO On completion of download Reset again to activate the new code DTR is only connected to Reset when JP7 is inserted The board will reset and enter DTR is only connected to LandTiger V2 0 User Manual Reset and enter ISP mode External Reset and enter ISP mode Manual Reset and enter ISP mode the ISP programming mode whenever DTR 1s activated Reset and RTS 19 activated ISP on COMI The board then behaves just as like manually entering the ISP mode and it is ready to accept and store new user code in the internal Flash The device may be Reset and brought in ISP mode through the JT AG port The device will enter the USB Secondary bootloader programming mode when Key2 SW3 is pressed and held before applying a Reset The device 1s then ready to accept and store new user code through the USB device port Tabel 24 Reset and Boot Jumper settings INTO P2 10 connected to Key2 Reset activated by DTR INTO P2 10 activated by RTS 26 Reset when JP7 1s inserted RTS is only connected to INTO P2 10 when JP6 is inserted New program download through COMI UARTO On
44. tivity and collisions A separate LED indicates 10 100 Mbit s linkspeed LD2 6 c25 Ber R48 ER Ke SE is i P100 250 IEA T 1R12 Figuur 17 Ethernet PHY and RJ45 connector Tabel 19 Ethernet controlsignals IO Pin Description ENET TX EN ENET TX DO ENET TX DI LandTiger V2 0 User Manual 23 Figuur 18 RJ45 connector CNS frontview Tabel 20 RJ45 interface description Pin Description Notel The Ethernet interface may be not be fully disabled by removing 0 Ohm resistors Removing R49 R50 and R51 will release P1 15 P1 16 and PI 17 2 16 Joystick The LandTiger LPC17XX board features a 5 way digital joystick SW5 The joystick may be used for example to select options in a menu shown on the LCD Each direction up down left right and the Select function are connected to a dedicated digital inputpin on the LPCIT7XX Multiple keys can be pressed at the same time e g up and right Inputpins are active low when a key 1s pressed The inputpins are hardware debounced LandTiger V2 0 User Manual m BBI n 8 C45 B C61 EB EB UT st C62 ES BHL 4 2 C63 BEBIA EB BE BD 1 1 EJR63 E EJR3O jl R23 ELR25 N N a ES RY 27 7 pm atr A ber Res al R62 ti Figuur 19 Joystick 5 Way Switch Tabel 21 Joystick 5 way switchsignals TO Pin Description Up Active Low Notel The Joystick interface may be fully disabled by remov
45. to form a Serial Wire Viewer SWV The Serial Wire Viewer provides a low cost method of obtaining information from inside the MCU The SWO can output trace data in two output formats but only one output mechanism is valid at any one time The two defined encodings are UART and Manchester The current J Link implementation supports only UART encoding Serial Wire Viewer uses the SWO pin to transmit different packets for different types of information The three sources in the Cortex M3 core which can output information via this pin are e Instrumentation Trace Macrocell ITM for application driven trace source that supports printf style debugging It supports 32 different channels which allow it to be used for other purposes such as real time kernel information as well e Data Watchpoint and Trace DWT for real time variable monitoring and PC sampling which can in turn be used to periodically output the PC or various CPU internal counters which can be used to obtain profiling information from the target e Timestamping Timestamps are emitted relative to packets 7 3 3 Cortex 10 Pin Debug compatibility The Cortex Debug Connector provides support for Serial Wire and JT AG interface modes in a very small low cost 10 pin 0 05 connector This new style connector provides access to all SWD SWV and JT AG signals available on a Cortex Mx device Cortex Debus 10 pin Connector CE 1 o O 2 SDWIO Y TMS SHO 37 O O do SWWDCLK TCK GMD
46. ts pressing 29 TP_CSTouchscreen P0 6 Lowacive Touchscreen SCK Touchscreen MOSI TP_MISO Connects to SPI Touchscreen MISO 34 GND LOND LI LandTiger V2 0 User Manual 16 Notel details on the LCD operation may be found in Chapter 3 Note2 The 5V 3V3 converter on the HY32 C LCD board is interfering with mainboard 3V3 2 9 EEPROM LandTiger LPC17XX development board includes a 24L C02 2 kbit 256kByte EEPROM U6 connected to the LPC1768 I2C 0 port fast mode supported upto 1 Mbit s JO Pin Description Z O O S P0 27 EEPROM SDA P0 28 EEPROM SCL Notel The DC Slaveaddress of the EEPROM is hardcoded at OxAO 8 bit address Note2 The I2CO SDA and SCL lines have R121 and R122 pull up Rs installed 4K7 to 3V3 This may interfere with Pull Up Rs on an external I2C bus Note3 The Write Protect of the EEPROM is disabled pull to GND Note4 The DC EEPROM may be disabled by removing R53 in the SDA line That will release P0 27 pin however the pull up R is still activated P0 28 may be used without risk of conflict however the pull up R also remains activated 29 2E D Olai 2 X Em y ue Pao EY Riise L RN tos V r 4 i E KA Figuur 11 I2C EEPROM 24002 U6 2 10 DataFlash LandTiger LPCI7XX development board includes an AT45DB16D 16 Mbit 2MB yte DataFlash U7 connected to the LPC1768 SPL O port JO Pin Description o A4 P0 18 D
47. ty SWDIO and SWCLK are overlaid on the TMS and TCK pins In order to communicate with a SWD device J Link sends out data on SWDIO synchronous to the SWCLK With every rising edge of SWCLK one bit of data is trans mitted or received on the SWDIO The data read from SWDIO can than be retrieved from the input buffer LandTiger V2 0 User Manual 51 Tabel 40 SWD pinout on 20 pin connector Pin Signal Type Description l VTref Input This is the target reference voltage It is used to check 1f the target has power to create the logic level reference for the input comparators and to control the output logic levels to the target It is normally fed from Vdd of the target board and must not have a series resistor 2 Vsupply NC This pin is not connected in J Link It is reserved for compatibility with other equipment Connect to Vdd or leave open in target system 3 Not used NC This pin is not used by J Link If the II device may also be accessed via JT AG this pin may be connected to nTRST otherwise leave open 5 Not used NC This pin is not used by J Link If the II device may also be accessed via JTAG this pin may be connected to TDI otherwise leave open SWDIO Single bi directional data pin SWCLK Output Clock signal to target CPU It is recommended that this pin 1s pulled to a defined state of the target board Typically connected to TCK of target CPU 11 Not used NC This pin is not used by J Link T
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