Stellaris Development Board User`s Manual and Schematics
Contents
1. 9 m Stellaris Daughterboard Connectors L rRESET Trac gt UARTO JTAG sel lt UART1 Photocell olo 2 UN E SEN Port Headers A t PA ojojojojojo oo CO C1 C2 A o o o o o o o o IFC Bus a ojojojojojojojo Se olo EEPROM jo ol PD ojojojojojojojo Slololo 22 ADC 1 3 5 7 PE perbere SEI dl 9 9 C0 C1 C2 USB Potentiometer Flash a 3 3 V Expansion lelelelelelelelololo SPI Bus L Regulator Headers erre 50050900 p User LEDs PDC Em User Pushbutton GPIOX ojojojojojojojo GPIOY mols GPIOZ EBBEBEEB 00000000 GPIOs DIP Switch eis OO00000000000000 DOE 50000000 puzzel LCD Panel LEDs Motherboard 10 February 6 2007 Stellaris amp Family Development Board User s Manual Functional De2. VDD 33v TL3 T SERRE 2 RI 0 1 Ohm q d 0 5 y E SuS9399 9885 DEE PES che PEA n PE 31h EE PEZ a Pa RSTn Ea TOO ate 14 e7 OSCO a La OSCI 10 59 PC7 11 Pit PCE 12 oi SOCKET QFP48 DNP dadd C12 C13 04uF 0 1uF PO P d PAO PAI e PA2 P P P l Ji R2 221 eJ 196 SMA ca 8pF 50V 10 J7 o ul PD7 PO4 PC6 2 3 3v mii BR ul ET PES XPB1 ur PBO alt XPEZ iz ata EN PB2 TH 3 3v 3 3v 5v no PB3 10 yy o mit PD5 pai Da 102 103 ti PES zia 10uF R10uF 10uF 12 PD4 PAZ Gs TANT TANT TANT Bus PAS 14 16V 16y 16V milis PAZ 15 mus PEI E 16 Ta MEET PEO PDS la ELE PAO Leg PDI 19 P 19 PAT 20 20 PDO 21 21 21x1 SKT 21x1SKT Ja IDIO SEELEN GLK32K POS PB4 LE PB6 JP1 1 PD6 1X3HDR a 2 PB1 XPC7 PB1 3 XPBI e JP2 1 1xakDR ae PC7 Pcr 13 XPC7 JP3 ur 1 1X3HDR 1 2 PEZ PE2 a XPE2 e 36 FEI P36 PEO es ih Pagas P Z P32 le j 1 p31
3. ei ase ae 9 Block Diagram p LM 10 Functional Description EEEE 11 Datighterboald A 11 Bode EI a a aa 11 leaders CI oa EE dao a 11 Potenitlometer s isin tadi daar da a lae o kaa 11 iler 11 User LEDS erac e dai deer a ELASTAN d Y eae dde dea a Ea NE eas 11 User Pushbutton n ass k ad 11 JAG Debug GONNector Em 12 USB Debug suisse mida dis a reela eee lo EE Qe kep bean bls rnvo 12 IZC EEPROM ros REM 12 SPI EN VA 12 BUZZON ERR 12 acria qM ou E ao asasine tea apa os KE o KEE eda La 12 Extemal Reset 12 ieu 12 Peripheral Device Controller PDC eese see sennnonteseoosonkteetannantisennnantttsennnantseennenttiegannantaso 12 Power Gupphy RR nwms 13 Motherboard Layout ete eerte kuo evas tado o eee Ee Pace e E YE MEE E ERR u DR La ala E ERA DE Ak kas ban eka 13 Development Board Configuration eene rre 14 Daughterboard Installatiori 2 cer heic ere dad dee cdd 14 UAR Toninas
4. PAO J4 19 JP7 1 2 UO RX Serial port 0 receive PA1 J4 20 JP6 1 2 UO TX Serial port 0 transmit PA2 J4 13 JP15 2 1 SPI CLK Serial peripheral interface clock PA3 J4 16 JP18 2 1 SPI SEL Serial peripheral interface select PA4 J4 15 JP17 2 1 SPI MISO Serial peripheral interface master in slave out PAS J4 14 JP16 2 1 SPI MOSI Serial peripheral interface master out slave in JP26 1 2 PWM Buzzer signal PBO J4 6 JP22 1 2 ULEDO User LED JP1 2 1 P 3 7 CLK32K 32 768 KHz clock ES JP1 2 3 gt J4 5 JP23 1 2 ULED1 User LED JP14 1 2 DC SCL 12C clock signal to EEPROM PB2 J4 9 JP24 1 2 ULED2 User LED JP34 2 3 IDX Motor index signal JP13 1 2 DC SDA 12C data signal to EEPROM PB3 J4 10 JP25 1 2 ULED3 User LED JP35 2 3 FAULT Motor fault signal PB4 J3 20 JP5 2 1 CO Connects to 10k potentiometer PB5 J3 19 JP5 4 3 C1 Connects to 10k potentiometer PB6 J3 18 JP3 2 1 CO Connects to photocell PB7 J1 21 J14 3 TRST JTAG signal used by emulator PCO J1 18 J14 9 TCK JTAG signal used by emulator PC1 J1 19 J14 7 TMS JTAG signal used by emulator PC2 J1 20 J14 5 TDI JTAG signal used by emulator PC3 J1 16 J14 13 TDO JTAG signal used by emulator PC4 J1 3 PC4 Not used PC5 J3 21 JP3 4 3 C1 Connects to photocell PC6 J1 4 JP3 6 5 C2 Connects to photocell February 6 2007 31 DB48 Daughterboard Table 3 3 Development Board Signals Used by DB48 Daughterboar
5. Designer Drawing Title Aseo ene Stellaris DB28 Daughterboard Drawn by Page Title Amaldo Cruz Table of Contents Approved Size Document Number Rev lt Approver gt Cc 0001 R2 Date Saturday March 18 2006 Sheet 1 of 2 5 4 3 2 1 o RSTn lt PC3 TDO PCO TCK PCT TMS PC2 TDI PB7 3 3v J4 J2 3 3v Vila mii 21 a e ata ra 41a mil XPB1 a Ei ki PBO Se Lag Cim ul ata EN PB2 Sita 3 3v 3 3v AE PB3 10m m0 11 Mai C2 mit a 10uF 10uF EEC PAZ fila TANT TANT sis PAS 14 16V 16V milis PA4 15 m5 PAS 16 ly CHE Gs ali ala mis PAO 19 y m Li19 BAT 20 o 21 wt 21x1 SKT 21x1SKT Ja RRE TIR RRE eo do dd dd a dada gwo Qo GND GND PB4 PB5 PEG CLKS2K 1 a Pt 219 1X3HDR ate P Mu se l FIDI FID2 40 Mil Pad 40MilPad 9 RI 400 Mil Mask 100 Mil Mask l VDD Ze 78 l l l l I FID3 FIDA U2 40 Mil Pad 40MilPad 100M Mask 100 Mil Mask PB7 1 28 Fon l en rate ae PES 28 PC2 y Pn aja soe28 P2
6. l Ci8 Ci9 C20 C21 C22 C23 ca cas l 01uF 04uF 04uF 04uF pmil0uE ANF Kall 0 33uF SS zi TANT TANT DNP sv DNP L 0NP DNP DNP L ev 10 UT DNP DNP DNP l l LUMINARYMICRO l l 1 T t l Drawing Title C26 C27 C28 C29 l 0 01 uF 001uF 001 uF 001 uF Stellaris DB48 Daughterboard l DNP DNP DNP DNP l Page Tile l E LM3SXXX Connectors S Located on bottom layer l cem Pn e Date Thursday May 18 2006 She 2 of 2 5 4 3 2 1 Table of Contents Table of Contents Revision Control LM3SXXX Socket Connectors Ui Luminary Micro Inc 2499 S Capital of Texas Hwy LUMINARYMICRO Z3 This document contains information proprietary to Luminary Micro Inc and shall not be used for engineering design procurement or manufacture in whole or in part without the express written permission of Luminary Micro Inc Copyright 2005 Luminary Micro Inc All rights reserved Designer Drawing Title Aseo ene Stellaris DB48 Daughterboard Drawn by Page Title Amaldo Cruz Table of Contents Approved Size Document Number Rev lt Approver gt Cc 0001 R2 Date Saturday March 18 2006 Sheet 1 of 2 5 4 3 2 1 PB6 PB7 PCO PC1 PC2 PC3 RSTn TO
7. 14 SPI Port On Board Peripherals sss nennen nemen enne inen nennt eren 14 ez NEN cm 14 BUZZEF M 14 LCD Panel DIP Switch LEDs and GPIOS ooocccncccononnnoncncconoconenenocononononenonnronnnonononnnrnnnnnonnrnnnnnnnnnonernnnnnnnnnos 14 UserPBushbutlon eS 15 BEIGE DITE 15 io m 15 Potentiometer 15 JTAG Debug Connector eei n e rad dee aea io es aer klo d c Ye ven uev ka 15 USB DO DUG c M oso 15 32 7698 KHZ Clock OSCINAtON ET 15 BG ra E A e pa sides LD vee 16 GPIO Headers 16 ewer akote ke v via sis r sdl be bin ea da gwan ane ee a pd kk oa 16 Peripheral Device Controller PDC 16 Stellaris Microcontroller to PDC Interface 17 PD CMO seankaii da 17 PDC Ke 18 February 6 2007 5 e SNE e e EEN 19 Chapter 2 DB28 Daughterboard esee eene nenne nennen nennt n erint nnns nine nn nnns innt nsn nnmnnn nna 21 gud ct 21 Block EISES s dt ra e LR LE ad LL i EE 21 Daughterboard Interface eiiis etie titii cdt 21 Daught rboard Layout zeegt t tee EELER EA idea RT EO tg rba 22 A EE 23 Development Board Signal Usage ssss sieissennnneeeeennnneeeesannnnneeesnsnnnntteaennnnnteetennenteseennnntesennnnn
8. _PA3 gt m JP18 12 e E i 49 SPLSEL gt 13 LCD Display 16x2 SPSE 197 GPLD TMS E e PPLD TMS 402 Ge 16 1X3HDR R71 A e 196 csi 1X76HDR LLo1uF A R72 280K Q2 MMBT3904 i R25 i PDC k l 108 L CONTRAST 10 gt CONTRAST PL2A PR2A is 4 PL2B PROB 3 n LAS PL3A PR3A i van PR3B LO LRA AE SPARE 6 Sl prae puc ECH L GEN E gue 5 Ure FRED L BLIGAT SPARE 4 SPARE 3 TW bis 3 SPARE 2 m zin 2 SPARE 1 SPARE 0 Bi PL5B PLSC PLSD GSRN CTE 48 gt g PLGA m IP 4 PL6B TSALL i e ozz i uro R28 330 a Aa e opoze ZC 1871 Gr ia a o GE EE 19 ste GREEN LED GPIOZ GPIOZ 4 Sn LEDO e GPIOZ 3 D2 e GPIOZ 2 is leren R23 330 Ma GPIOZ 1 l 22 bras GPIOZ 0 GREEN LED 23 LED1 A x R24 330 2 Aa J26 T 1 GPIOX 0 100 29 GREEN LED E epoxi 4 99 PRA PB2A Can LED2 e 3 GPIOX 2 4 98 E See 32 D4 1 e Fon S de PT2D pp2p L3 R29 330 2 y p 6 GPIOX 5 95 E GREEN LED 7 GPIOX 6 LED3 33 i 8 GPIOX 7 PT3A PB3A CLKI 1 4 E O e D6 PT3B PB3B St 2 Ze 1 4 R65 PT3C PB3C CLKI 0 4 TP10 10K PT3D PB3D 2 DSWO GREEN LED 43 DSW1 D6 gt PTAA CLKO 0 PB4A P J27 S PTAB CLK0 PB4B EE Bewa 2 X A m GPIOY o 77 PTC PB4C DSW3 AER aen 2 GPIOY 1 sp PTAD PB4D DSW4 isos cu e erore Ap PT4E eo GPiov ell ceiovs PT4F R32 330 Lu 5 GPIOY 4 55 3 em 2 y 1 l e 5 GPIOYS 78 PISA PBSA Ce DSW6 GREEN LED 7 GPIOY 6 7 PTSB PBSC L ine e 2 SE PTSC PBSD DSWT a 33v 1X8HDR ub R37 330 2 P
9. engineering design procurement or manufacture in whole or in part without the express written permission of Luminary Micro Inc Copyright 2005 Luminary Micro Inc All rights reserved Designer Drawing Title Aseo ae Stellaris DB48 Daughterboard Drawn by Page Title Amaldo Cruz Table of Contents Approved Size Document Number Rev lt Approver gt C 0001 R3 Date Thursday May 18 2006 Sheet 1 o 2 5 4 3 2 1 RSTn c 7 PD7 PO4 PC6 2 3 3v mii BR ul AE PES ula PES XPB1 PBO Lag XPEZ E ata EN PB2 TH 3 3v 3 3v 5v no PBS 10 yy 9 mit PD5 La Da 102 103 11 PES Gi 10uF 10uF 10uF 12 PD4 PAZ Gs TANT TANT TANT Bus PAS 14 16V 16V 16V milis PA4 15 m PE1 PAS eLa Ee PEO PD2 izla E LU PD3 18 Le m 8 PAO 19 La mio PD1 PAL 20 20 PDO 21 21 21x1 SKT 21x1SKT Ja IDIO ear I JJI JIII GLK32K POS PB4 PBS PB6 JP1 PDE 1X3HDR E PBI GND GND GN
10. 1 DB48 Daughterboard Interface GND 2 3 4 5 XPB1 6 PBO 7 XPE2 8 9 E o 11 16 PC3 TDO 17 PD6 PD2 18 PCO TCK PB6 PD3 19 PC1 TMS PD1 PB5 PAO 20 PC2 TDI PDO PB4 PA1 21 PB7 TRST GND PC5 GND Daughterboard Layout 28 There are two different layouts of the DB48 daughterboard Layout 1 shown on Figure 3 2 on page 29 has the Stellaris microcontroller soldered at U1 on the center of the board Layout 2 shown on Figure 3 3 on page 30 has the Stellaris microcontroller soldered at location U1 on the left side of the board Both layouts include four ground test loops TL1 TL4 in Layout 1 and TL1 TL4 TL5 and TL7 in Layout 2 TL6 in Layout 1 and TL2 in Layout 2 are connected to the LDO pin The gray squares show the location of pin 1 for each connector Note that TL5 in Layout 1 and TL6 in Layout 2 as well as pin 1 of J2 and J4 are 3 3 V A clock signal can be applied to SMA connector J6 after removing crystal Y1 February 6 2007 Stellaris amp Family Development Board User s Manual Figure 3 2 DB48 Daughterboard Layout 1 R3 J1 3 3V 3 3V BH 00000000000000000000M O O O O O O O O O O TL1 TL6 O O Co O O GND LDO GND O O JP2 JP3 JP1 O o O OJ4 LA J20 O E O 2 J6 33V 2 O O TL4 PE TL3 ES o O O O O M O o OOOOOOOOOOOOOOOOOPOOO E O NOTE The gray squares indicate the location of pin 1
11. 2 DB28 Daughterboard on page 21 and Chapter 3 DB48 Daughterboard on page 27 Features The Stellaris Family Development Board includes the following features Note that not all features are implemented on all Stellaris microcontrollers February 6 2007 Daughterboards enable support for multiple package pin out options Two UART transceivers and DB9 male connectors All UO available on headers One potentiometer and one photocell for driving the Analog to Digital Converter ADC and comparator inputs Eight user LEDs and one pushbutton for use with the Stellaris GPIOs Standard ARM 20 pin JTAG debug connector USB 2 0 full speed interface allows JTAG SWD debug without in circuit emulator ICE 8 Kbit 12C EEPROM memory 1 Mbit SPI based flash memory One buzzer for PWM use 32 768 KHz oscillator for real time clock External reset switch and power on reset supervisor 5 V and 3 3 V LED power indicators User prototype area Peripheral Device Controller PDC CPLD for interface with the following 16 character by 2 line LCD display 8 status LEDs 8 position dual inline package DIP switch 24 GPIOs Stellaris amp Family Development Board Block Diagram Figure 1 1 Stellaris amp Family Development Board Block Diagram
12. February 6 2007 29 DB48 Daughterboard Figure 3 3 DB48 Daughterboard Layout 2 R2 3 3V x 3 3V B OOO000000000000000008H a O O O TL1 TL2 TL3 TL4 O O GND O LDO VDD GND O O O O O y O O O O O o E O OJ4 U1 T J20 O O O O O O O O O O O qi O O TL5 TL6 TL7 O O Cn O O V T 3 3V GND O O oo0oooooooooooooooooooN o NOTE The gray squares indicate the location of pin 1 Shunt Jumpers There are three shunt jumpers for connection of a 32 768 KHz clock as shown in Table 3 2 Table 3 2 Jumper Settings for DB48 Daughterboard JP1 No shunt PB1 is unconnected Shunt 1 2 PB1 is connected to 32 768 KHz clock Shunt 2 3 PB1 is connected to daughterboard connector J4 5 XPB1 JP2 No shunt PC7 is unconnected Shunt 1 2 PC7 is connected to 32 768 KHz clock Shunt 2 3 PC7 is connected to daughterboard connector J4 5 XPC7 JP3 No shunt PE2 is unconnected Shunt 1 2 PE2 is connected to 32 768 KHz clock Shunt 2 3 PE2 is connected to daughterboard connector J4 5 XPE2 30 February 6 2007 Stellaris amp Family Development Board User s Manual Development Board Signal Usage Table 3 3 shows the signal connectivity and usage between the DB48 daughterboard and the motherboard For the jumpers column the numbers in brackets show the jumper position Table 3 3 Development Board Signals Used by DB48 Daughterboard
13. the SPI flash memory place a shunt jumper on JP10 NOTE The Stellaris microcontroller s SSI port can be programmed for one of three serial modes Freescale SPI National Semiconductor MICROWIRE or Texas Instruments synchronous serial The mode is set with the FRF bit in the SSI Control0 SSICRO register The Stellaris Family Development Board is designed for use with SPI mode although MICROWIRE and TI synchronous serial modes can be used when implementing user circuits in the prototype area SPI mode must be set to use the board s LCD DIP switch LEDs and GPIOX GPIOY and GPIOZ ports To connect the 12C port for access to the on board EEPROM place shunt jumpers on JP13 and JP14 To write protect the EEPROM memory place a shunt jumper on JP12 Address line A2 for the EEPROM memory can be set to 0 by placing a shunt jumper on JP11 Removing the jumper sets A2 to 1 NOTE The 12C interface is available on select Stellaris microcontrollers To enable the buzzer BZ1 connect a shunt jumper to JP21 To connect the buzzer power driver to the Stellaris microcontroller PBO port place a shunt jumper on JP26 To use a different port to drive the buzzer remove the shunt at JP26 and connect a fly wire from the desired port to JP26 2 LCD Panel DIP Switch LEDs and GPIOs 14 To use the LCD panel DIP switch LEDs LEDO LED7 D1 D8 and the GPIOs the SPI port must be connected as described above The SPI port connects to the PDC to control
14. 0000000 Oo uo 9 oo lool loo loo o loj mo O oo oo oo DO fol Bo 0 SW1 pig OO JP3 OO JP5 O Bo A i JP2 JP4 sw2 bi mo Q 2 mo a Sl sw port oj BLE lo mo DOI R5 REV3 LEDO JP22 ULEDO NOTE The gray squares indicate the location of pin 1 for all connectors and headers February 6 2007 13 Stellaris amp Family Development Board Development Board Configuration NOTE In the descriptions that follow reference designators are used to indicate locations on the board layout as shown in Figure 1 2 In addition reference designators in parenthesis refer to parts in the schematics in Appendix B Schematics Daughterboard Installation UART The daughterboard connects to the motherboard header connectors J1 J4 With no power applied to the motherboard place the daughterboard and align each connector of the motherboard with the corresponding daughterboard connector Press the daughterboard down until the daughterboard is firmly seated and visually inspect all four connectors to ensure proper connection before proceeding To connect the UARTO transceiver connect shunt jumpers on headers JP6 and JP7 To connect UART1 connect shunt jumpers on headers JP8 and JP9 SPI Port On Board Peripherals I2C Port Buzzer To connect the Serial Peripheral Interface port which is used to communicate with the PDC and the on board flash memory connect shunt jumpers to pins 1 2 of headers JP15 JP16 JP17 and JP18 To write protect
15. 007 7 List of Tables Table 1 1 Table 1 2 Table 1 3 Table 1 4 Table 2 1 Table 2 2 Table 2 3 Table 3 1 Table 3 2 Table 3 3 Possible Board POWer SOUNCCS pake sad ake td anvan ad e tate kat x pida ey pacc o ug bo dad y venes Edd eda 16 Stellaris Microcontroller to PDC Interface sssssssseseeee enne nennen 17 Peripheral to PDC Interface sar sman deu ek NAS el 17 ARA HM 18 DB28 Daughterboard Interface pw tire ort o pe e ect bed v dee do ig ue adn 22 Jumper Settings for DB28 Daughterboard sss eene ener 23 Development Board Signals Used by DB28 Daugbterboard A 24 DB48 Daughterboard Interface ceseeno see EEE 28 Jumper Settings for DB48 Daughterboard enne 30 Development Board Signals Used by DB48 Daughterboard sse 31 February 6 2007 CHA PTER 1 Stellaris Family Development Board The and and The Stellaris Family Development Board provides a platform for product development Hardware software engineers use this board for evaluation of Stellaris family microcontroller features functionality and for software development development board includes the Stellaris motherboard and a daughterboard with a Stellaris family microcontroller The DB28 daughterboard is available for 28 pin SOIC devices and the DB48 daughterboard is available for 48 pin LQFP devices These daughterboards are described in Chapter
16. 1 1 J2 21 J3 8 J4 21 Connects to ground plane Connects to 1 3 microfarad capacitor and to test loop 2 February 6 2007 25 DB28 Daughterboard 26 February 6 2007 CHAPTER 3 DB48 Daughterboard The DB48 daughterboard contains a 48 pin LQFP Stellaris microcontroller and connects to the motherboard with four 21 pin connectors NOTE In the descriptions that follow reference designators are used to indicate locations on the board layout as shown in Figure 3 2 on page 29 and Figure 3 3 on page 30 In addition reference designators in parenthesis refer to parts in the schematics in Appendix B Schematics Features Designed for 48 pin LQFP Stellaris microcontroller 6 MHz crystal mounted on pin sockets for easy crystal changes SMA connector for external clock Power and ground test loops Jumper selectable 32 768 KHz clock All daughterboard connector signals accessible via headers on the daughterboard Block Diagram Figure 3 1 DB48 Daughterboard Block Diagram pa Stellaris ps JP2 JP1 o o o ererel folelo l t Connectors Daughterboard Interface The DB48 daughterboard connects to the motherboard with four connectors J1 J4 see Figure 1 2 on page 13 Table 3 1 on page 28 lists the connections February 6 2007 27 DB48 Daughterboard Table 3
17. 6 Tos POS Fiducials D I ls des PB3 l NI MDO pe pena mo c OOOO LIIIIR DD NV NV LP P22 224 OSCI 8 P8 P21 Zi PB1 osco alpo poo 20 osci 10 bio big cio PBO Pel ipn pig la A PA1 12 1 PA jajne RAET PAS t P13 16 eu PAS 14 P14 p15 15 PAS es ce 0AuF 9E SOCKET SOP28 DNP vi 19 PAO PAO UORx PBO CCPO gt PBO PAI PA1 UOTx PB1 32KHz 22 PB1 PAZ PA2 SSICIk PB2 I2CSCL 22 PB2 PAZ PA3 SSIFss PB3 l2CSDA PB3 PA4 PA4 SSIRX PB4 CO PB4 PAS PASISSITx PBS C1 C0o PB5 PB6 CO CCP1 PB6 PB7 TRST PB7 PCO PCO TCK SWCLK PC PCI TMS SWDIO PC2 PC2 TDI LD m PC3 PC3 TDO SWO ed mo j R2 22 1 OSCO al O G 1 T OSCI 10 ken SMA LD m n j Pen D EST LDO E DO o H H O GND VDD bd Be ge GND EE ME 838 M INARYMICRO 18pF KR GND VDD So UE 0 33uF LUMIN 50V res cie cu 16V Dis TH 1096 L LM3S1XX SOP28 0 1uF 0 1uF 0 1uF 1 10 rawing Title Stellaris DB28 Daughterboard Page Title LM3S1XX Socket Connectors Size Document Number Cc 0001 Date Saturday March 18 2006 Sheet 2 of 2 4 3 2 1 Table of Contents Table of Contents Revision Control LM3SXXX Connectors UT Luminary Micro Inc 2499 S Capital of Texas Hwy LUMINARYMICRO Ze This document contains information proprietary to Luminary Micro Inc and shall not be used for
18. 7 1K 64X16 USB_OFF TEST XTIN XTOUT 1x2 HDR 20K Drawing Title Stellaris Development Board Page Title USB to JTAG SWD Size Document Number Rev E R3 Date 2 5 2007 Sheet 7 of 7 ula RESET RSTOUT GND GND GND GND 18 25 34 45 FT2232C ADBUSO R94 e 10K R95 R86 10K 10K R87 0 ADBUSI ADBUS2 ADBUS3 ADBUS4 ADBUSS ADBUS6 ADBUS7 ACBUSO ACBUSI ACBUS2 ACBUS3 SIWUA BDBUSO BDBUSI BDBUS2 BDBUS3 BDBUS4 BDBUS5 BDBUS6 BDBUS7 BCBUSO BCBUSI BCBUS2 BCBUS3 SIWUB PWREN C36 0 1uF 33v vec vcc VCCIOA VCCIOB FB3 C37 C38 C35 R82 475 ki 0 1uF 0 1uF 0 1uF avee LE EE Leen A C39 390hm 100 MHz 9 0 4uF l uminaryeicro Table of Contents Table of Contents Revision Control LM3S1XX Socket Connectors Ui Luminary Micro Inc 2499 S Capital of Texas Hwy LUMINARYMICRO Ze This document contains information proprietary to Luminary Micro Inc and shall not be used for engineering design procurement or manufacture in whole or in part without the express written permission of Luminary Micro Inc Copyright 2005 Luminary Micro Inc All rights reserved
19. A 1 l SLEBEN GREEN LED 3 LED7 TCK TMS 4 TDI ToO 33v A DEBUG GND vec I Wi 33v GND vec Les Lee len E VAUX To 1uF ow E peri i GND 0 VIO 0 3 m mi JE GND 0 VIO 0 elct Loto sos DEWA 5 12 DSW5 6 Du 0 1uF pe 0 1uF DSWS m GND 1 VIO 1 cD Do GND_I VIOLI PLD TDI GND 1 VIO 1 CPLD JTAG TES GE SIR SW DIP 8 Rocker Em ul o LCMXO256 T100C CPLD TMS I 4 CPLD TCK 1X8HDR c30 L 0 tuF R36 4 75K JE Drawing Title Stellaris Development Board Page Title PDC LCD Display LEDs DIP Switch Size Document Number Rev C R3 Date 2 5 2007 Sheet 5 of 7 I 6 GND TL1 33v sw2 33v A gt R46 SYSRST 10K JP19 USER PB gt R47 swa 2 1 a 10K si e IEM 1x2 HDR MAX6386 S USER 1 2 N SRST B gt me 1x2 HDR LINK SRST JP21 PWM Buzzer sy 1x2 HDR A gt R49 R50 511 332 BZ1 A 1 Dii GREEN LED 2 gt PWM LED N BUZZER CEM 1206S d R56 2 80K P Qi 1 2 d 1 PBO gt K MMBT3904 1x2 HDR R55 a PWM 82 5K BL Power provided by external 5v DC supply or USB port as selected by switch Use of USB power requires a high power port 500mA USB 5v 5 0V 3 3V ay TLS TLE 33v 1 St ug MIC5209 ns 2 21 vin vout 4 O 1101M2S3CQE2 o R60 R63 D20 511 R61 R62 82 5K AN f k Lim 8 2
20. D GND XPC7 pei Sta XPB1 T T2 TW a JP2 1X3HDR Kc PC7 Pcr 13 XPC7 Jm 1X3HDR 2 PE2 Pe ela XPE2 Ie tes M ui FID1 FID2 40 Mil Pad 40MilPad 100MilMask 100 Mil Mask PAO PAO UORx PBO PWMZJCCPO LS PBO l PA PA1 UOTx PB1 PWM3 CCP2 PB1 l PAZ PA2 SSICIk PB2 1208CL L PB2 l i PAZ PA3 SSIFss PB3 2CSDA LZ PB3 i PA4 PA4 SSIRx PBA CO F43 PB4 l I PAS PAS SSITx PBSICT CCPS AS PBS Fibs A l PB6 C0 PB6 l PESTEST LA PB7 A0 Mil Pad 40 Mil Pad TOO MILMask 100 Mil Mask PCO PCO TCK SWCLK PDO PWMO 23 PDO l PC1 PC1 TMS SWDIO PD1 PWM1 2 amp PD1 l PC2 PC2 TDI PD2 U1Rx 2 PD2 i PC3 PC3 TDO SWO PD3 U1Tx Eg PD3 l i PC4 PC4 CCP5 PhA PDA ADC7 CCPO 4 PD4 l Fiducials PC5 PC5 C1 C10 COo CCP1 PDS ADC6 CCP2 77 PD5 i PC6 PC6 C2 C20 CCP3 PhB PD6 ADC5 Fault 3 EEE E E PC7 PC7 C2 CCP4 PDZ ADC4 GOo IDX H 48 PD7 PEO PEO PWM4 PE1 PE1 PWM5 PEZ PE2 ADC3 CCP4 PES PES ADC2 CCP1 PE4 PE4 ADC1 CCP3 PES PES ADCO CCP5 3 3v LDO Je TL5 TL6 1 RI 22 1 gt OSCO 9 3 3v 2 OSCO 9 sm 196 OSC1 10 osci 6 LDO 7 vi Je RSTn da L sin LDO O Wir O GND VDD c4 9548 6 000MHz 9548 enD Yon C8 c9 C10 on 016 ee or 18pF EAS M 04uF 04uF Q1uF 0 1uF WE lur 0 33uF 50V TANT 16V 10 L 16V LI 0 LM3SXXX QFP48 gt C12 Ci3 Ci4 C15 C17 N 0 01 uF 0 01 uF 0 01 uF 0 01 UFAZ10UF TANT 16V AAA MODUM HD omara pese 1
21. FF position is read as 0 A switch in the ON position is read as 1 LED 0x5 R W The LED Output LED register controls LEDO LED7 Bit i controls LED Writing a bit to 1 turns on the corresponding LED Writing a bit to 0 turns off the corresponding LED LCDCSR 0x6 RWD The LCD Command Status LCDCSR register is used to write configuration and control commands and to read status information from the LCD panel For more information refer to the CFAH1602B LCD panel data sheet available from www crystalfontz com LCDRAM Ox7 RWD The LCD RAM LCDRAM register is used to write and read the LCD display data RAM DDRAM and the character generator RAM CGRAM For more information refer to the CFAH1602B LCD panel data sheet available from www crystalfontz com GPXDAT 0x8 R W The GPIOX Data GPXDAT register is used to access the general purpose UO port GPIOX at location J26 Bit i corresponds with the GPIOX i port signal Each bit can be configured for input or output in the GPXDIR register Writing a bit to 1 sets the corresponding GPIOX port signal to 1 if the port signal is configured as an output Writing a bit to O sets the corresponding GPIOX port signal to 0 if the port signal is configured as an output Reading a bit reads the value of the corresponding GPIOX port signal If the GPIOX port is 0 the bit will read as 0 If the GPIOX port signal is 1 the bit will read as 1 Note that a read of the GPXDAT register alwa
22. LUMINARYMICRO Stellaris Family Development Board USER S MANUAL DM LM3SFAM 04 Copyright 2005 2007 Luminary Micro Inc Legal Disclaimers and Trademark Information INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN LUMINARY MICRO S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCIS LUMINARY MICRO ASSUMES NO LIABILITY WHATSOEVER AND LUMINARY MICRO DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF LUMINARY MICRO S PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT LUMINARY MICRO S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL LIFE SAVING OR LIFE SUSTAINING APPLICATIONS Luminary Micro may make changes to specifications and product descriptions at any time without notice Contact your local Luminary Micro sales office or your distributor to obtain the latest specifications before placing your product order Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Luminary Micro reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them Copyr
23. Pal a Eso E30 PB1 29 PEO 29 Pag 22 Eo PAO PAO UORx PBo PWM2 CCPO LS PBO p28 H2 FDE PAI PA1 UOTx PBI PWIM3 CCP2 3 PB1 par e PDI PA2 PA2 SSICIk PB2 I2CSCL 2 PB2 p26 38 POO PAZ PA3 SSIFss PB3 I2CSDA 34 PB3 P25 PA4 PA4 SSIRX PB4 C0 4 PB4 PAS PASISSITx PB5 C1 CCPS PB5 PB6 CO H42 PB6 PB7 TRST PB7 PCO PCO TCK SWCLK PDO PWMO LZ PDO PC PC1 TMS SWDIO PD1 PWM1 L PD1 Rei PC2 TDI PD2 U1Rx 27 PD2 PC3 PC3 TDO SWO PDS UITx 28 PD3 c14 C15 PC4 PC4 CCPS PhA PD4 ADC7 CCPO 46 PD4 sL Stur oE PCS PC5 C1 C10 C00 CCP1 PDS ADCG CCP2 A PD5 p a PC6 PC6 024 020 COP3 PhB PDG ADCS Fault A PD6 PC7 PC7 C2 CCP4 PD7 ADC4 COo IDX 48 PD7 PEO PEO PWM4 PEI PE1 PWM5 PEZ PE2 ADC3 CCP4 PES PES ADC2 CCP1 PE4 PE4 ADC1 CCP3 PES PES ADCO CCP5 3 3v LDO TL6 T osco gl osco OSCT 10d Gece vi je RSTn gt RT LDo E A Ch GND VDD su GND VDD E 9548 6 000MHz 9548 C5 jo C6 C7 18pF ND VDD so e l iuF 0 33uF Tou Cs c9 C10 on b Lio 1 109 LM3SXXX QFP48 EZo1uF SOF 0 uF Sour ES GND GND GND GND TL ma T5 TL7 We tes M I FID1 FID2 40 Mil Pad 40MilPad 100MilMask 100 Mil Mask l l l l l l l l l l l FID3 FID4 20 Mil Pad 40MilPad 100 MilMask 100 Mil Mask l l l l l i Fiducials l l l UMiumiNarymicro Drawing Title Stellaris DB48 Daughterboard Page Title LM3SXXX Socket Connectors Size Document Number Rev Cc 0001 R2 Date Saturday Mar
24. RS Out LCD register select L RW Out LCD read write L CEN Out LCD chip enable L BLIGHT Out LCD backlight LD 7 0 InOut LCD data bus LED 7 0 Out LED select outputs DSWI7 0 In DIP switch inputs GPIOX 7 0 InOut GPIOX I O ports GPIOY 7 0 InOut GPIOY UO ports GPIOZ 7 0 InOut GPIOZ I O ports February 6 2007 Stellaris amp Family Development Board PDC Registers PDC registers are 8 bits and there are three types Read Only RO Read Write R W and Read Write delayed RWD A RWD transaction requires an additional dummy transfer due to peripheral device latency Table 1 4 PDC Registers VERSION 0x0 RO The VERSION register contains the version of the PDC design programmed in the CPLD CSR 0x1 R W The Command Status CSR register is used to set special configuration options and read device status Unused bits are reserved and should be written to 0 The following bits are defined BitO LCBL The LCD backlight bit controls the LCD panel backlight Setting this bit to 1 turns on the LCD backlight Setting this bit to O turns off the LCD backlight Bit7 LCBSY The LCD busy bit reflects the value of the LCD panel busy flag When this bit is 1 the LCD panel is busy processing a command When this bit is 0 a new command can be written to the LCD panel DIPSW 0x4 RO The DIP Switch DIPSW register contains the value of the debug DIP switch at location SW1 Bit i corresponds to switch i 1 A switch in the O
25. WP SCK I GND SI ci2 AT25F1024AN Je 33v R17 10K JP11 1 33v E icu a2 BI 1x2 HDR R18 330 33v va JP12 8 1 I2CM WP 7 2 6 5 2 RI9 1x2 HDR C13 10K 0 1uF AT24C08A 8Kbits R20 R21 2 80K 2 80K JPi3 IC SDA gef l 2 CH BIO 120 BLA 1x2 HDR JP14 GC SCL 2 l 2 DC SCL lt PRE gt He 1x2 HDR Ul uminARYMICRO Drawing Title Stellaris Development Board Page Title UART SPI I2C Size Document Number Rev R3 Date 2 5 2007 Sheet 4 of 7 tl 3 3v PA gt SPI_CLK PAS gt 5v 5v SPI MOSI 4 el GPLD TDI Ap 1 TXGHDR Y re PAS AS 770 u5 JP17 l e li 5 FEEEEOEEEEEKEEGE H Ti lt SPLMISO e 7 6 SFL MSO 3 CPLD TDO E 9 1X3HDR 10
26. ani HS 4 sou 7 p T C24 C25 o E C26 R64 C27 1N5819 EN 22uF 0 1uF 470 pF 137K p ex RAPC722 Di8 TANT la TANT D19 GREEN LED 16v i E tev GREEN LED M 5 0V M 33V x x J21 D21 5 0V S 1 2 GND Term Block V 2pos 1N5819 40 Mil Pad 100 Mil Mask 40 Mil Pad 100 Mil Mask 40 Mil Pad 100 Mil Mask 40 Mil Pad 100 Mil Mask GND GND e e e e TL2 FIDS FIDE FID7 FID8 40 Mil Pad 40 Mil Pad 40 Mil Pad 40 Mil Pad 100 Mil Mask 100 Mil Mask 100 Mil Mask 100 Mil Mask o e Fiducials JP22 ULEDO D9 ED me 2 R48 330 2 PA 1x2 HDR icone LED JP23 ULED1 D10 el R51 330 2 gt PA 4 1x2 HDR Es LED JP24 ULED2 D12 D ne 2 R52 330 2 gt PA 1x2 HDR an LED JP25 ULED3 D13 D ne 2 R53 330 2 AP i 1x2 HDR iene LED JP27 ULED4 D14 EE ne 2 R54 330 2 PA 4 1x2 HDR Gita LED JP28 ULED5 D15 ED me 2 R57 330 2 PA i i 1x2 HDR uiis LED JP29 ULED6 Di6 EE me 2 R58 330 2 yo 1 1 1x2 HDR GREEN LED JP30 ULED7 kise T En el R59 330 2 PA i 1x2 HDR EE LED all Duminarymicro Drawing Title Stellaris Development Board Page Title Power Reset Size Document Number Rev e R3 Date 2 5 2007 Sheet 6 of 7 e tl Dr 390hm 100 MHz R80 27 3V30UT USBDM R81 1 50K USBDP EECS EESK EEDATA AT93C46A 10SI 2
27. aughterboard Connects to 1 3 microfarad capacitor and to test loop 2 a Jumpers 34 and 35 are only available on Rev3 or later boards February 6 2007 33 DB48 Daughterboard 34 February 6 2007 APPENDIXA Contact Information Company Information Founded in 2004 Luminary Micro Inc designs markets and sells ARM Cortex M3 based microcontrollers MCUs Austin Texas based Luminary Micro is the lead partner for the Cortex M3 processor delivering the world s first silicon implementation of the Cortex M3 processor Luminary Micro s introduction of the Stellaris amp family of products provides 32 bit performance for the same price as current 8 and 16 bit microcontroller designs With entry level pricing at 1 00 for an ARM technology based MCU Luminary Micro s Stellaris product line allows for standardization that eliminates future architectural upgrades or software tool changes Luminary Micro Inc 108 Wild Basin Suite 350 Austin TX 78746 Main 1 512 279 8800 Fax 1 512 279 8879 http www luminarymicro com salesQluminarymicro com Support Information For support on Luminary Micro products contact supportQluminarymicro com 1 512 279 8800 ext 3 February 6 2007 35 36 February 6 2007 APPENDIX B Schematics Schematics for the development board follow E Stellaris Motherboard on page 39 m DB28 Daughterboard on page 46 m DB48 Daughterboard Layout 1 board revision R3 on page 48 m DB48 D
28. aughterboard Layout 2 board revision R2 on page 50 February 6 2007 37 38 February 6 2007 s Table of Contents 1 Table of Contents Revision Control Block Diagram Board Connectors GPIO JTAG UART SPI 12C 4 m PDC LCD Display LEDs DIP Switch 6 Reset Power USB to JTAG SWD a Luminary Micro Inc 108 Wild Basin Rd M LUMINARYMICRO lannan D This document contains information proprietary to Luminary Micro Inc and shall not be used for engineering design procurement of manufacture in whole or in part without the express written permission of Luminary Micro Inc Copyright 2007 Luminary Micro Inc All rights reserved Designer Drawing Title Arnaldo Cruz Stellaris Development Board Drawn by Page Title Arnaldo Cruz Table of Contents Approved Size Document Number c Date 2 5 2007 Sheet of 7 tl Board Connectors Ji J2 J3 T SYSTEM Reset JTAG p JUMPER 32kHz BLOCK PORTO Oscillator SMA NUMERA PORTI Photocell Jumper block BLOCK aa ADC 0 2 4 6 Headers C0 C1 C2 0 0 0 Jumper block 0 Potentiometer ADC 1 3 5 7 0 I2C BUS JUMPER T2C C0 C1 C2 BLOCK EEPROM 8kbit JUMPER BLOCK i SPI BUS 3 3V Regulator Expansion Headers FLASH 1Mbit p LEDS BLOCK a User Pushbutton PDC Peripheral D
29. ch 18 2006 Sheet 2 of 2 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to an
30. ck Set SPI SEL Low for 200 nanoseconds to reset the PDC February 6 2007 19 Stellaris amp Family Development Board Every transaction is composed of at least two 8 bit SPI transfers The first byte contains a 4 bit address on the lower bits bits 3 0 and a read write R W bit to indicate transfer direction on the most significant bit bit 7 The remaining bits bits 6 4 are reserved and must be 0 The next byte is driven by the Stellaris microcontroller for write transfers R W bit 0 and by the PDC for read transfers R W bit 1 For read transfers to LCD registers a dummy byte follows the first byte with a valid data byte afterwards Timing diagrams are shown in Figure 1 3 Figure 1 3 PDC Timing Diagrams PDC Read Transfer SPI SEL saak XI X ITI E EJ EJA e a ax SPI MOSI RWV 0 o 0 A3 A2 A1 A SPI MSO D7 X D6 X D5 X D4 X D3 Y D2 Y D1 DO LCD Read Transfer SPI SEL aak ll ASP EO A IA I E EPS SPO EE Wish E E ko SPI MOSI RWV0 o o A3 A2 IA LA SPI MSO 3 6A SY 4X 3 2X 1X 0 DZ D6 D5 X D4 Y D3 Y D2 f D1 DO ee ner PDC LCD Write Transfer SPI SEL L siak MPE PR E Ke oT eror RAT SPI MEI Rw o o o a3 Ya2 Yat VA D7 De D5 Y Da Y D3 D2 f D1 DO SPI MSO 20 February 6 2007 CHAPTER 2 DB28 Daughterboard The DB28 daughterboard contains a 28 pin SOIC Stellaris microcontroller and
31. connects to the motherboard with four 21 pin connectors NOTE In the descriptions that follow reference designators are used to indicate locations on the board layout as shown in Figure 2 2 on page 23 In addition reference designators in parenthesis refer to parts in the schematics in Appendix B Schematics Features Designed for 28 pin SOIC Stellaris microcontroller 6 MHz crystal mounted on pin sockets for easy crystal changes SMA connector for external clock Power and ground test loops Jumper selectable 32 768 KHz clock All daughterboard connector signals accessible via headers on the daughterboard Block Diagram Figure 2 1 DB28 Daughterboard Block Diagram Stellaris of EPI Connectors Daughterboard Interface The DB28 daughterboard connects to the motherboard with four connectors J1 J4 see Figure 1 2 on page 13 Table 2 1 on page 22 lists the connections February 6 2007 21 DB28 Daughterboard Table 2 1 DB28 Daughterboard Interface CLK32K GND Qo 0 OC SI wo hd E o 11 PC3 TDO PCO TCK 19 PC1 TMS 20 PC2 TDI 21 PB7 TRST GND Daughterboard Layout The DB28 daughterboard layout is shown in Figure 2 2 on page 23 A single Stellaris microcontroller is soldered at location U1 There are four ground test loops TL1 TL4 TL5 and TL7 TL2 is c
32. d JP2 2 1 gt J3 7 JP5 6 5 C2 32 768 KHz clock PC Dd JP5 6 5 C2 Connects to 10k potentiometer PDO J2 20 JP27 1 2 ULEDA User LED PD1 J2 19 JP28 1 2 ULED5 User LED JP9 1 2 U1 RX Serial port 1 receive PD2 J4 17 JP29 1 2 ULED6 User LED JP8 1 2 U1 TX Serial port 1 transmit PD3 J4 18 JP30 1 2 ULED7 User LED PD4 J2 12 JP4 8 7 ADC7 Connects to 10k potentiometer PD5 J2 10 JP2 8 7 ADC6 Connects to photocell PD6 J3 17 JP4 6 5 ADC5 Connects to 10k potentiometer JP35 1 2 FAULT Motor fault signal PD7 J1 2 JP2 6 5 ADC4 Connects to photocell JP34 1 2 IDX Motor index signal PEO J2 16 PEO Not used PE1 J2 15 PE1 Not used JP3 2 115 J3 7 CLK32K 32 768 KHz clock pee JP3 2 3 gt J4 7 JP4 4 3 ADC3 Connects to 10k potentiometer PE3 J2 11 JP2 4 3 ADC2 Connects to photocell PE4 J2 4 JP4 2 1 ADC1 Connects to 10k potentiometer PE5 J2 3 JP2 2 1 ADCO Connects to photocell RST J1 12 SYSRST B Connects to reset supervisor OSCO J7 C4 Connects to pin socket and capacitor for crystal OSC1 J8 C5 Connects to pin socket and capacitor for crystal VDD TL5 Layout 1 3 3V Connects to 3 3 V plane U1 TL6 Layout 2 J2 1 J4 1 GND J1 1 J2 21 GND Connects to ground plane J3 8 J4 21 32 February 6 2007 Stellaris amp Family Development Board User s Manual Table 3 3 Development Board Signals Used by DB48 D
33. eeeaennna 24 Chapter 3 DB48 Daughterboard eese esee nennen enin nnne nini n nnne inan nnne nnne nnns sn nnn nennen 27 lug nrc m 27 Block Tiagra ki 27 Daughterboard Interace EE 27 Daughterboard Layout ut Eten ode an ed snl leat baled ated oem eI o 28 SONUNEJUMPETS ede eec ran re dees tui et p a da tk pa age astu Sad aa ae uid on n dta da kara epa ekono ada ar 30 Development Board Signal Usage taa aaa aa te a aaa ata nnne ennt aeeaaottsesosoottessssaonsesosoon 31 Appendix A Contact Information ccccccccnnnnnnnnnnonnncnenenencnnncnnnnnnnnnnn cn eee eeee enana tnnt nnne sn nasse sinn h tnnt nnne nnns nns 35 Appendix B Schematics E 37 6 February 6 2007 Stellaris amp Family Development Board User s Manual List of Figures Figure 1 1 Stellaris amp Family Development Board Block Diagram ooooonnccccnnnonacccccnnnonccccnononn cnn nar rn crono 10 Figure 1 2 Stellaris Family Motherboard Layout nenne nnne nnne nene 13 Figure 1 3 PDC Timing Diagrams iicet iciatis ad aid anes 20 Figure 2 1 DB28 Daughterboard Block Diagram sssssssss eene eene enne nnns 21 Figure 2 2 DB28 Daughterboard Layout 4 iicet ttn ak kaa en Ra nad dann AE 23 Figure 3 1 DB48 Daughterboard Block Diagram ssssssseenee ene nee 27 Figure 3 2 DB48 Daughterboard Layout 1 R3 lL eene nennen nnn rennen 29 Figure 3 3 DB48 Daughterboard Layout 2 RI 30 February 6 2
34. eement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be resp
35. evice Controller JUMPER GPIO Port Headers GPIOX 7 0 GPIOY 7 0 GPIOZ 7 0 DIP Switch 7 0 LCD panel 16 char x 2 rows LEDS 7 0 ON LUMINARYMICRO Drawing Title Stellaris Development Board Page Title Block Diagram Size Document Number Rev R3 Date 2 5 2007 Sheet 2 of 7 4 Jojo CTT 66666660006 Conne J5 SSI FSS 1X8HDR PortA 33v J9 l e 2 ChA PC4 PWM3 PDO 3 4 ChB PCS 12CSCL J6 PDI 5 6 IDX PD7X 12CSDA 1X8HDR PBO 7 8 ci POS PortB PB1 9 10 c2 POZ PEO Pi 1I e ADC6 PD5 PEI P 13 ee 14 ADC5 PD6X 33v SYSRST B Tees C0 PB4 PD4 ADC7 17 18 Et PB5 2 i51 99176 Cor HU PB6 390hm 100 MHz 2X10 HDR J7 C66 C65 PWM QEI ADC CMP 1X8HDR 0 1UF e L oAuUF PortC J10 1X8HDR PortD SMA 32k Di 2i CLK32K 1X3HDR A FAULT 33v PA UO RX 2 TCK POO Note JP34 and JP35 are present only PAI UO TX 4 TMS PCI on the REV 3 board Previous board e PAZ e 6 TDI PCS versions have s
36. ight 2006 2007 Luminary Micro Inc All rights reserved Stellaris is a registered trademark and the Luminary Micro logo is a trademark of Luminary Micro Inc or its subsidiaries in the United States and other countries ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited Other names and brands may be claimed as the property of others Luminary Micro Inc 108 Wild Basin Suite 350 B Austin TX 78746 m m m m Eu Main 1 512 279 8800 ES Cor e i Fax 1 512 279 8879 ARM 2 a http www luminarymicro com Intelligent Processors by ARM LUMINARYMICRO 2 February 6 2007 Stellaris amp Family Development Board User s Manual Revision History This table provides a summary of the document revisions March 2006 00 Initial release of doc to customers May 2006 01 Release of DB48 daughterboard and documentation May 2006 02 Added missing DB48 schematics to board manual PDF July 2006 03 Switched DB48 Layout 1 and Layout 2 figures so most current board is first Added QEI text to Headers paragraph in Chapter 1 February 2007 04 Release of revision 3 of motherboard which adds two headers JP34 and JP35 February 6 2007 3 February 6 2007 Stellaris amp Family Development Board User s Manual Table of Contents Chapter 1 Stellaris Family Development Board seeeeeeeeeeeeeeeeeeeeeeeaneeeeeeeeeeeeeeeaaneaneaeeeseeeeeeeeeneneenes 9 re LE
37. ignal PD7 directly 7 o E d TDO connected to J9 6 and signal PD6 Ul RX y ae 14 Me a pa T Se Ti UI CIBUS directly connected to J9 14 l 3 33v PB2 13 14 ccp4 PEZ PortE senos JERE ED QUT PBS 15 16 Geri PES x 2 2 4 PB7 17 18 CCP3 PE4 axe T SD Ves c6 d oiee P5 PES 32 768KHz AUF 2X10 HDR SERIAL CCP i 3 3v li R3 PHOTOCELL P8102 JP2 ADC 1 2 0 PES 3 eti 2 PE3 5 eT 4 PD7 PHOTOCELL 7 gt 8 6 PDS 2x4 HDR JP3 1 e De PB6 33v 3 4 Cit PC5 A 5 6 C PCS 2x3 HDR Es gt R66 R6 9 R7 opp RA RIO Ri R12 JTAG 10K 10K 10K 1 PE4 3 PE2 5 PDS e T PD4 DBGRQ UT DBGACK C0 PB4 Ci PBs LUMINARYMICRO C2 PC7 EN Drawing Title Stellaris Development Board Page Title Board Connectors GPIO JTAG Size Document Number Rev E R3 Date 2 5 2007 Sheet 3 of I 2 3 4 5 6 Jpg UO TX 1 mo 2 Pi UO TX 1x2 HDR jp UO RX 1 LO 2 UO RX 1x2 HDR upg Ut TX 1 a 2 e Ui TX 8 1x2 HDR gpo Ut RX 16 1 me 2 UL RX 9 1x2 HDR ci 3 0 47uF 33v y 0 47uF e R68 R67 R13 10K 10K 10K L C2 FORCEON 4 FORCEOFF GND vcc du MAX3224 T 33v R15 10K JP10 1 3 3y sem we BET e 1x2 HDR 3 33v e 1Mbit ve SO HOLD
38. ion for signals IDX PD7 or PB2 and FAULT PD6 or PB3 JP34 and JP35 are highlighted in the figure with a red box Figure 1 2 Stellaris Family Motherboard Layout P1 P2 0000000000 P mj E Y g8 oo 00000 21 S s p BERE 0000000000 5555 Z 596060000000 00 HB a Pell o o o o ET ajajaje JP10 o lo o lo o o gevry Ex J1 a 0000 SE o Bg MA Dl 3 3v o o lo00000000000000000008 m IS o o o Port e Fone GRIO o El o o o o o o o lon 3 3V o o o o o E o o o oun l ae REN RER d i o o Jo ollo3 qmoo goo o o o o o ail HO o BRO po o o o o L22 Ebo JG o o o o o o B eloj ooo o o CD J4 o o J2 al lo lol io OS o EI PortD PortE Spare GPIOX GPIOY p o o m a a a a p e i o o o o o p o lo o oi o i o j i o lo lo o o Sek o o o o o o o eoWMhieaeeeesees a o lo lo o o b o 9 e ie ie laj le DE O lo00000000000000000008H O o o BZ1 ou J3 o wu JP12 O Bl wP JP21 JP1 J11 Gi Bl JP14 OM SCL HOF O L4 l JP13 OB sDA MO E J LED7 JP30 ULED7 JP26 JP20 mo mo mo mo R25 g 20000000
39. jack J19 Slide switch S1 towards the board edge to turn on power 5 V 500 mA bench supply Slide switch S1 towards the center of the board Connect a 5 V supply with two wires to terminal block J21 Connect the 5 V wire to J21 1 5V and the ground wire to J21 2 GND Slide switch S1 towards the board edge to turn on power J21 SV GND Peripheral Device Controller PDC The PDC provides access to a common set of peripherals across all Stellaris microcontrollers since they all include an SSI port The Stellaris SSI port is used in SPI mode for communications with the PDC The PDC operates at 1 MHz 16 February 6 2007 Stellaris amp Family Development Board User s Manual Stellaris Microcontroller to PDC Interface The Stellaris microcontroller connects to the PDC with a SPI port using the signals shown in PDC UO Table 1 2 Table 1 2 Stellaris Microcontroller to PDC Interface SPI CLK Input SPI clock signal 1 MHz SPI SEL Input SPI select signal set high to enable SPI transfers Set to low for reset of the PDC minimum 200 nanoseconds Note that with SPI SEL low the SPI flash at location U3 is selected SPI MOSI Input Master output slave input data transfer signal SPI MISO Output Master input slave output data transfer signal The PDC connects to supported peripherals with the following signals Table 1 3 Peripheral to PDC Interface L
40. log comparator inputs and three ADC inputs Header J22 has the remaining Stellaris signals and includes UART SSI 12C JTAG and timer CCP input signals NOTE PWM QEI ADC I C and analog comparators are available on select Stellaris microcontrollers Potentiometer One potentiometer is included to drive selected Analog to Digital Converter ADC inputs and or analog comparator inputs The voltage range is 0 to 3 0 Shunt headers are used for signal selection NOTE ADC and analog comparators are available on select Stellaris microcontrollers Photocell One photocell is included to drive selected ADC inputs and or analog comparator inputs The voltage range is 0 to 3 0 Shunt headers are used for signal selection NOTE ADC and analog comparators are available on select Stellaris microcontrollers User LEDs Eight user LEDs ULEDO ULED7 are provided for general use Headers are provided for connectivity User Pushbutton One user pushbutton SW3 is provided for general use A header is provided for connectivity February 6 2007 11 Stellaris amp Family Development Board JTAG Debug Connector A standard 20 pin connector for JTAG debug is provided This port is also used to access the Serial Wire Debug SWD interface of the Stellaris microcontroller When using this connector the USB interface cannot be used for JTAG SWD debug USB can still be used for providing board power A shunt jumper at location JP31 may be req
41. ntroller PDC A Peripheral Device Controller PDC implemented with a CPLD is accessible via the SPI interface and provides access to several devices including a 16 character by 2 line LCD display an 8 bit DIP switch 8 general purpose user LEDs and 24 GPIOs 12 February 6 2007 Stellaris amp Family Development Board User s Manual Power Supply The Stellaris amp Family Development Board requires 5 volts at 500 mA for operation and three options are provided for supply connection 1 A USB connector can be used when connected to a high power 500 mA USB hub port 2 A5 V jack can be used with an external power supply 3 Aterminal block can be wired to a 5 V external bench supply A slide switch selects between USB power and the other two options see Figure 1 2 on page 13 Table 1 1 on page 16 describes how to select the power supply Motherboard Layout The StellarisTM family motherboard layout is shown in Figure 1 2 The gray squares show the location of pin 1 for all connectors and headers On the board silk screen white arrows indicate pin 1 There are four ground test loops TL1 TL4 TL5 is 5 0 V and TL6 is 3 3 V NOTE Two motherboard revisions are in production Rev 2 and Rev 3 The revision is marked in the lower left corner of the board as indicated in the figure The only functional difference between these revisions is the addition in Rev 3 of headers JP34 and JP35 next to the GPIOZ headers to allow source select
42. on board 32 768 KHz oscillator can be used to drive the Stellaris real time clock To enable this oscillator remove the shunt jumper on JP1 To disable the oscillator output place a shunt jumper on JP1 February 6 2007 15 Stellaris amp Family Development Board Reset Switch Reset switch SW2 generates a 140 ms minimum system reset signal Powering up the board also generates a 140 ms system reset signal A shunt jumper can be placed on JP20 to link the JTAG emulator reset with the system reset GPIO Headers All Stellaris GPIO ports are available on 8 pin headers labeled PortA J5 PortB J6 PortC J7 PortD J10 and PortE J12 The 20 pin headers J9 and J22 include all the GPIOs and provide a convenient connection for expansion to another board The 8 pin headers labeled GPIOX J26 GPIOY J27 and GPIOZ J16 provide a connection to the GPIOs implemented in the PDC Power Three options are available for board power and only one should be connected to the board These are described in Table 1 1 The two power indicators light once there is power to the board Table 11 Possible Board Power Sources USB high power hub 500 mA Slide switch S1 towards the board edge Connect a USB cable from the USB hub to the USB B receptacle J18 Slide switch S1 towards the board center to turn on power 5 V 500 mA supply with 2 5 mm plug Slide switch S1 towards the center of the board Connect a 5 V supply with a 2 5 mm plug to
43. onnected to the LDO pin and TL3 is connected to VDD The gray squares show the location of pin 1 for each connector Note that TL6 and pin 1 of J2 and J4 are 3 3 V A clock signal can be applied to SMA connector J6 after removing crystal Y1 22 February 6 2007 Stellaris amp Family Development Board User s Manual Figure 2 2 DB28 Daughterboard Layout V J1 OOOOOOOOOOOOODOOOOOOOOO w w w 00000000000000000000la TL1 TL2 TL TL4 Q DE ni GND LDO VDD GND TL5 TL6 TL7 Ca GND 3 3V GND J3 OOOOOOOOOOOOOOOOOOOO O O0000000000000000000107 NOTE The gray squares indicate the location of pin 1 Shunt Jumper There is a single shunt jumper JP1 see Figure 2 2 used for selecting the connection of port B1 PB1 as shown in Table 2 2 Table 2 2 Jumper Settings for DB28 Daughterboard No shunt PB1 is unconnected Shunt 1 2 PB1 is connected to 32 768 KHz clock Shunt 2 3 PB1 is connected to daughterboard connector J4 5 XPB1 February 6 2007 23 DB28 Daughterboard Development Board Signal Usage Table 2 3 shows the signal connectivity and usage between the DB28 daughterboard and the motherboard For the jumpers column the numbers in brackets show the jumper position Table 2 3 Development Board Signals Used by DB28 Daughterboard PAO J4 19 JP7 1 2 UO RX Serial p
44. onsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DLP Products www dlp com Broadband www ti com broadband DSP dsp ti com Digital Control www ti com digitalcontrol Clocks and Timers www ti com clocks Medical www ti com medical Interface interface ti com Military www ti com military Logic logic ti com Optical Networking www ti com opticalnetwork Power Mgmt power ti com Security www ti com security Microcontrollers microcontroller ti com Telephony www ti com telephony RFID www ti rfid com Video amp Imaging www ti com video RF IF and ZigBee Solutions www ti com lprf Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2009 Texas Instruments Incorporated
45. ort Writing a bit to 0 sets the corresponding GPYDAT bit as an input port GPZDAT OxC R W The GPIOZ Data GPZDAT register is used to access the general purpose UO port GPIOZ at location J16 Bit i corresponds with the GPICZ i port signal Each bit can be configured for input or output in the GPZDIR register Writing a bit to 1 sets the corresponding GPIOZ port signal to 1 if the port signal is configured as an output Writing a bit to O sets the corresponding GPIOZ port signal to O if the port signal is configured as an output Reading a bit reads the value of the corresponding GPIOZ port signal If the GPIOZ port is 0 the bit will read as 0 If the GPIOZ port signal is 1 the bit will read as 1 Note that a read of the GPZDAT register always reads the GPIOZ port signals not the internal register GPZDIR OxD R W The GPIOZ Direction GPZDIR register is used to select the data transfer direction for the GPZDAT register Bit i corresponds with GPZDAT bit i Writing a bit to 1 sets the corresponding GPZDAT bit as an output port Writing a bit to 0 sets the corresponding GPZDAT bit as an input port SPI Protocol The SPI slave interface is enabled when SPI SEL goes High All SPI commands and data are received via the SPI MOSI input signal with data sampled on the rising edge of the SPI clock All SPI output data is transmitted on the SPI MISO output signal with data shifted out on the falling edge of the SPI clo
46. ort 0 receive PA1 J4 20 JP6 1 2 UO TX Serial port 0 transmit PA2 J4 13 JP15 2 1 SPI CLK Serial peripheral interface clock PA3 J4 16 JP18 2 1 SPI SEL Serial peripheral interface select PA4 J4 15 JP17 2 1 SPI_MISO Serial peripheral interface master in slave out PAS J4 14 JP16 2 1 SPI MOSI Serial peripheral interface master out slave in JP26 1 2 PWM Buzzer signal PBO J4 6 JP22 1 2 ULEDO User LED JP1 2 1 F 3 7 CLK32K 32 768 KHz clock ES JP1 2 3 7 J4 5 JP23 1 2 ULED1 User LED J4 9 DC SCL 12C clock signal to EEPROM PB2 J4 9 JP24 1 2 ULED2 User LED J4 10 I2C SDA 12C data signal to EEPROM PB3 J4 10 JP25 1 2 ULED3 User LED PB4 J3 20 JP5 2 1 CO Connects to 10k potentiometer PB5 J3 19 JP5 4 3 C1 Connects to 10k potentiometer PB6 J3 18 JP3 2 1 CO Connects to photocell PB7 J1 21 J14 3 TRST JTAG signal used by emulator PCO J1 18 J14 9 TCK JTAG signal used by emulator PC1 J1 19 J14 7 TMS JTAG signal used by emulator PC2 J1 20 J14 5 TDI JTAG signal used by emulator PC3 J1 16 J14 13 TDO JTAG signal used by emulator RST J1 12 SYSRST_B Connects to reset supervisor OSCO J7 C4 Connects to pin socket and capacitor for crystal OSC1 J8 C5 Connects to pin socket and capacitor for crystal VDD TL6 J2 1 J4 1 3 3V Connects to 3 3 V plane U1 24 February 6 2007 Stellaris amp Family Development Board User s Manual Table 2 3 Development Board Signals Used by DB28 Daughterboard J
47. re available on select Stellaris microcontrollers Potentiometer Potentiometer R5 can be used to provide an analog signal to drive the ADC analog to digital converter and the analog comparator using headers JP4 ADC1 ADC3 ADC5 ADC7 PE4 PE2 PD6 PD4 and JP5 CO C1 C2 PB4 PB5 PC7 To connect the potentiometer to an ADC channel place a shunt jumper on the corresponding JP4 header To connect the potentiometer to a comparator channel place a shunt jumper on the corresponding JP5 header NOTE ADC and analog comparators are available on select Stellaris microcontrollers JTAG Debug Connector For JTAG debug with an external ICE connect the ICE to connector J14 with a standard 20 pin JTAG debug cable To link the motherboard reset to the JTAG emulator reset place a shunt jumper on JP20 Depending on the ICE a shunt jumper at location JP31 may be required if a USB driver conflict occurs USB Debug For debug with USB connect the USB cable to the USB device connector Ensure that no shunt jumper is present at location JP31 Note that a corresponding USB driver must be installed on the host computer The USB driver selects the mode of operation by controlling the USB MOD signal from the FTDI part ADBUS7 If USB MOD is 1 JTAG mode is selected If USB MOD is 0 SWD mode is selected JTAG SWD signals are driven to the Stellaris microcontroller when the USB driver sets USB DEN ADBUS6 to 0 32 768 KHz Clock Oscillator An
48. scription Daughterboard The daughterboard contains the Stellaris microcontroller and connects to the motherboard with four 21 pin connectors The Stellaris PLL clock is generated from a 6 MHz crystal provided on pin sockets for easy crystal changes An optional SMA connector can be used to drive an external clock source UART Two UART transceivers and DB9 connectors are provided to connect with the Stellaris microcontroller UART peripherals The UARTO peripheral TX RX is included in all Stellaris microcontrollers UART1 is available in all 48 pin microcontrollers except the LM3S301 On the LM3S101 LM3S102 and LM3S301 UART is available for external use Headers All Stellaris UO signals are available on five 8 pin GPIO headers labeled Port A through Port E to match the Stellaris microcontroller GPIO ports For each port header pin 1 is bit 0 and pin 8 is bit 7 of the corresponding Stellaris GPIO For example Port B pin 1 is PBO and Port B pin 8 is PB7 of the Stellaris microcontroller Note that ports A and E have only six I O signals with the remaining two header pins connected to ground Jumper shunts are used to connect Stellaris signals to on board devices to allow connect disconnect Stellaris signals can be rewired with the included fly wires There are also two 20 pin expansion headers J9 and J22 Header J9 is intended primarily as an interface for a motor driver board and includes all the Stellaris PWM outputs QEI inputs ana
49. these devices The potentiometer R25 is used to adjust the contrast of the LCD panel The LCD panel DIP switch LEDs and GPIOs are controlled with the PDC registers see Table 1 4 on page 18 February 6 2007 Stellaris amp Family Development Board User s Manual User Pushbutton Pushbutton SW3 is available for general use To connect this switch to PB4 place a shunt jumper on JP19 To use a different port remove shunt at JP19 and connect a fly wire from the desired port to JP19 2 User LEDs User LEDs ULEDO ULED7 D9 D10 D12 D13 D17 are available for general use Each user LED has an associated header for connection to a Stellaris GPIO PDC GPIO or external circuitry To connect a user LED to its associated Stellaris GPIO place a shunt jumper on the corresponding header ULEDO ULED3 PBO PB3 ULED4 ULED7 PDO PD3 To use a different port remove the shunt jumper from the header and connect a fly wire from the desired port to pin 2 of the header Photocell Photocell R3 can be used to provide an analog signal to drive the ADC analog to digital converter and the analog comparator using headers JP2 ADCO ADC2 ADC4 ADC6 gt PE5 PE3 PD7 PD5 and JP3 C0 C1 C2 gt PB6 PC5 PC6 To connect the photocell to an ADC channel place a shunt jumper on the corresponding JP2 header To connect the photocell to a comparator channel place a shunt jumper on the corresponding JP3 header NOTE ADC and analog comparators a
50. uired when using this port USB Debug A USB 2 0 full speed interface provides debug capability via JTAG or SWD without the need for an ICE Note that use of this interface requires installation of the corresponding USB drivers When using this interface the 20 pin JTAG connector cannot be used for JTAG SWD debug Ensure that no shunt jumper is present at location JP31 VC EEPROM Memory An 8 Kbit 12C memory is included for use with the Inter Integrated Circuit 12C bus interface A jumper block is provided for connecting this memory NOTE The I2C interface is available on select Stellaris microcontrollers SPI Flash Memory A 1 Mbit SPI flash memory is included for use with the Serial Port Interface SPI port A jumper block is provided for connecting this memory Buzzer A buzzer is provided for use with one of the PWM outputs Real Time Clock A 32 768 KHz crystal oscillator generates a clock signal that can be used to drive the Stellaris real time clock Shunt jumpers on the daughterboard can be used to connect this clock source External Reset The external reset is implemented with a reset switch SW2 connected to a reset supervisor circuit and provides a system reset signal Prototype Area A prototype area is provided for implementing user circuits To supply power there are power and ground rows The prototype area is indicated on the board with a Luminary Micro logo see Figure 1 2 on page 13 Peripheral Device Co
51. y combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agr
52. ys reads the GPIOX port signals not the internal register 18 February 6 2007 Stellaris amp Family Development Board User s Manual Table 1 4 PDC Registers GPXDIR 0x9 R W The GPIOX Direction GPXDIR register is used to select the data transfer direction for the GPXDAT register Bit i corresponds to GPXDAT bit i Writing a bit to 1 sets the corresponding GPXDAT bit as an output port Writing a bit to 0 sets the corresponding GPXDAT bit as an input port GPYDAT OxA R W The GPIOY Data GPYDAT register is used to access the general purpose UO port GPIOY at location J27 Bit i corresponds with the GPIOY i port signal Each bit can be configured for input or output in the GPYDIR register Writing a bit to 1 sets the corresponding GPIOY port signal to 1 if the port signal is configured as an output Writing a bit to O sets the corresponding GPIOY port signal to 0 if the port signal is configured as an output Reading a bit reads the value of the corresponding GPIOY port signal If the GPIOY port is 0 the bit will read as 0 If the GPIOY port signal is 1 the bit will read as 1 Note that a read of the GPYDAT register always reads the GPIOY port signals not the internal register GPYDIR OxB R W The GPIOY Direction GPYDIR register is used to select the data transfer direction for the GPYDAT register Bit i corresponds with GPYDAT bit i Writing a bitto 1 sets the corresponding GPYDAT bit as an output p
Download Pdf Manuals
Related Search