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Caen V1495

1. PULSE pu ee a GATE Tdly Toffset Tset Toffset 11 5 2ns Tset SETBINARY Ins STARTx WIDTHMIN 320ns recommended 22ns absolute min STARTx PERIODMIN 640ns recommended 46ns absolute min Fig 3 1 Timers diagram The use of STARTx signals with timing shorter than those recommended is possible although the linearity on the set delay scale is no longer guaranteed 3 1 2 Timer2 Timer3 Each timer is made up of one digital circuit which produces a typical fixed time base with 10ns period and 5096 duty cycle These timers are proposed for generating any Gate pulse 10ns with a 10ns step The following figure shows an example of a Gate generation made with Timer2 and n 3 PULSE width Fig 3 2 Gate pulse example ISTART SN s 7 PULSE 2 EA I L Tod yl COUNT 2 COUNTO X COUNT COUNT 2 GATE oL 2 A FPGA USER drives a STARTx pulse and after Tey time FPGA USER will receive a PULSEx clock signal A counter with clock PULSEx implemented in the FPGA USER allows to generate a pulse with programmable duration It is possible to reduce to one half bns the counter step by advancing the counter on both sides of PULSEx Since the circuit is completely digital no recovery time is necessary between one stop and the following start it is thus possible to generate multiple gate pulses with very high rate Timer2 and Timer3 can be used together for handling one single Gate pulse from multiple overla
2. CONTROL REGISTER e a e o er 17 4 3 STATUS REGISTER cccococononononononononononononononononononononononononononononononononononononononononononononono nono nonononononononononononenos 17 4 4 INTERRUPT LEVEL REGISTER 0 sccccssevscesescssscsssencecnvecssccecsesccentecssccssnencecstecsscceesesscentecsuncssnescevaneeseneneses 17 4 5 INTERRUPT STATUS ID REGISTER eee en een nennen nnne n n n nnn e nnne nnn n nne p an pap eee 18 Z6 GBO ADDRESS RECTA 18 Ale MODUEERESET REGISTER aut didactica 18 4 8 FIRMWARE REVISION REGISTER cococonoconononononononononononononononononononononononononononononononononononononononononononononononos 18 4 9 SERATCHLO REGISTER aiii 19 4 10 SCRATCH92 REGISTER e Mar nU 19 4 11 SELECT VME FPGA FLASH REGISTER eee e eene nennen nnn nnne nn nnn n n en n nna p nena 19 4 12 SELECT USER FPGA FLASH REGISTER eee e e nennen nnne nn nnn nnn nnn nnn n nnn e nane auda 19 4 13 VME FPGA FLASH MEMORY cccccccceeeeseseseseseseseseseseseseseseseseseseseseseseseseseseseseseseseeesecesesesesesesesesens 19 NPO Filename Number of pages Page 00117 04 V 1495 MUTx 01 V1495 REVI DOC 40 3 CA Ema PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 4 14 USER FPGA FLASH MEMORY cccccccseseeeseseseseseseseseseseseseseseseseseseseseseseseseseseseseseeeseseseseseeeseeeeeeees 19 4 15 USER FPGA
3. eee ee emen a a e etes e ese sss ese ese s esse esses sese eset esee stesse 17 FIG 4 2 INTERRUPT VECTOR REGISTER ooccccccccncnconononononononononononononononononononononononononononononononononononononononononenenoneneness 18 FIG 4 3 GEOGRAPHICAL ADDRESS REGISTER ccccccccccncnnnnnnnnononononononononononononononononononononononononononononononononononenenoneneneso 18 FIG 4 4 FIRMWARE REVISION REGISTER occccccccccconocnnonononononononononononononononononononononononononononononononononononononononeneneneness 18 FIG 4 5 USER FPGA CONFIGURATION REGISTER occccccccccncnnononononononononononononononononononononononononononononononononenononeneness 19 FiS t USER FPGA BLOCK DIAGRAM caida 20 NPO Filename Number of pages Page 00117 04 V 1495 MUTx 01 V1495 REVI DOC 40 4 CA Ema PRELIMINARY Document type Title Revision date Revision Users Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 FIG 5 2 FRONT PANEL PORTS INTERFACE DIAGRAM ocococoncnoconocononcnnncconononnnccono nono nc entere enn entente ente neon nc en nente enne 26 E1G 5 3 PDE CONTROL BIT FIELDS 535 ier etr REO OR UE eC EEO etr Uere beatior t 31 FIG 5 4 DELAY UNIT WITH PDLS iii 32 ElG 3 9 PDES DELAY LINE TIMING ice eee exe oi 32 FiG 5 6 DELAY UNIT WITH DL OS iiie ra e eR idear socorrer osea anot nia 33 FiG 5 7 DEOS DELAY LINE TIMING reise nete eden eee R ete Tee IEEE aUe one da eu e ee ve ep EN ERR Adnan ERR 33 FIG 5 8 QUARTU
4. Inputs are not referred to a system clock As a consequence the gate signal will be generated without any time reference It is possible to use the implementation described above with the freedom of choosing the clock source between external or internal 40MHz The resulting Gate signal will have stable duration but with maximum position jitter equal to one clock period Such position jitter can be rejected by using the asynchronous timers present on the V1495 which allow to generate references synchronous with the occurred trigger 3 1 1 Timer0 Timer1 NPO Each timer is based on a programmable delay line FPGA USER drives a STARTx pulse and after the programmed delay it receives the return signal PULSEx The time difference between transmission and reception logic implementation inside the FPGA USER can be used to drive a gate signal The programming of the delay time can be done manually as binary value either via 8 bit dip switches SW4 and SW5 or via VME register with a 1ns resolution max delay 255ns The software setting has higher priority with respect to the dip switches The following figure shows a diagram of the timers usage Filename Number of pages Page 12 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 PAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 lt Tperiod gt q iih y START 0 mooo qr Tset Toffset
5. Filename Number of pages Page 00117 04 V 1495 MUTx 01 V1495 REVI DOC 40 21 EA Rel PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 PORT NAME DIRECTION WIDTH DESCRIPTION E_IDCODE IN 3 E slot mezzanine Identifier E LEV OUT 1 E slot Port Signal Level Select the level selection depends on the mezzanine expansioon board mounted onto this port E DIR OUT 1 E slot Port Direction E DIN IN 32 E slot Data In Bus E DOUT OUT 32 E slot Data Out Bus F IDCODE IN 3 F slot mezzanine Identifier F LEV OUT 1 F slot Port Signal Level Select the level selection depends on the mezzanine expansioon board mounted onto this port F DIR OUT 1 F slot Port Direction F DIN IN 32 F slot DataIn Bus F DOUT OUT 32 F slot Data Out Bus PDL CONFIGURATION INTERFACE PDL WR OUT 1 Write Enable PDL SEL OUT 1 PDL Selection 0 gt PDLO 1 gt PDL1 PDL_READ IN 8 Read Data PDL_WRITE OUT 8 Write Data PDL_DIR OUT 1 Direction 0 gt Write 1 gt Read DELAY LINES AND OSCILLATORS I O PDLO_OUT IN 1 Signal from PDLO Output PDL1_OUT IN 1 Signal from PDL1 Output DLOO OUT IN 1 Signal from DLOO Output DLO1_OUT IN 1 Signal from DLO1 Output PDLO_IN OUT 1 Signal to PDLO PDL1_IN OUT 1 Signal to PDL1 Input DLOO GATE OUT 1 Signal to DLOO Input DLOI GATE OUT 1 Signal to DLOI Input SPARE INTERFACE SPARE
6. V1495 Front Panel Ports Registers PORT A B C G eese eene 29 3 3 2 V1495 Mezzanine Expansion Ports Registers PORT D E F essent 30 5 5 3 Delay SCLECtI ON PT Q 30 5 5 4 PDL DELAY VALUE SETTING AND READBACK cioocononiccninnonononnoninonononanononononononononononononinininanos 30 5 5 5 Delay Unit using PDDs uie bet neto etm eee sevens eee SERERE Rede rides 32 5 5 6 Delay Unitusing DEOS 30000 ei met Me d e e SEE Re REI ME Erg ORI 33 5 6 QUARTUS II WEB EDITION PROJECT cccssssscessssceceessececsssseceesececsessececsessecsesaeeecseaaececsesaeesssesecsenaeess 34 3 4 EIRMWAREUPGRADE S ices euoneueeinadeerc ien eee EE i 39 LIST OF FIGURES FIG 1 1 MOD V1495 BLOCK DIAGRAM a eene a ese e ase sse ssse ses es esses assesses esses ses eset esse esee 7 FIG 2 1 MODEL V1495 FRONT PANEL WITH A395A B C PIGGY BACK BOARDS cierre ener 9 FIG 3 TETIMERSDIAGRAM erre eee eer e eee eet e eet e eR Pe Ree ee e wee e eee etes eye ec e HERE 13 FIG 3 2 GATE PULSE EXAMPLE eee e e emenenennnenennne ese e ese ese e ese se e esses sese PUPUSE Ero PESEE esee esas es eses esee sees eset Eoi 13 FIG 3 3 TIMER2 AND TIMER3 USED TOGETHER FOR HANDLING A GATE PULSE eeee eene 14 FIG 3 4 FPGA VME DIAGRAM gt secci n debio etie tne d ceda oet e ee tenebo dere tee ee epe o eren oe 14 FIG 3 5 FPGA USER DIAGRAM ecco ed eee ere ec ree eee o dodo ede e dece 15 FIG 4 1 INTERRUPT LEVEL REGISTER
7. is set to 0 the C O bit is masked output bit is stuck at 0 The x_STATUS_ y x can be A B C y can be L or H registers can be used to read back eack port bit Each status register is split into two 16 bit register STATUS_L corresponds to STATUS 15 0 while STATUS H corresponds to STATUS 31 0 There is not a STATUS register associated with G port The x STATUS vy register reflects the status of the unmasked input and output ports A control register C CONTROL is available to set the C port when the board is configured in I O register mode 5 5 2 V1495 Mezzanine Expansion Ports Registers PORT D E F The mezzanine expansion ports D E F can be configured and accessed using a set of registers In this reference design no mask register is implemented for the expansion ports The x DATA y x can be D E F y can be L or H registers can be used to read back each port bit Each status register is split into two 16 bit register D DATA L corresponds to D 15 0 while D DATA H corresponds to D 31 16 The expansion ports can be bidirectional In case the port is configured as an output the register value set the port value In case the port is configured as an input the register content reflects current port value A x CONTROL register x can be D E F is available to set the corresponding port direction and logic level selection 5 5 3 Delay Selection The selection of the asynchronous timer is made through the MODE registe
8. ID Register Base Address 0x8006 read write D16 This register contains the STATUS ID that the V1495 places on the VME data bus during the Interrupt Acknowledge cycle Bits 8 to 15 are meaningless Default setting is OXDD Not implemented in VME FPGA Rev 1 0 Available in next releases 15 14 13 121 120110 9 81 7 6 5 4 3 2 1 0 STATUS ID Fig 4 2 Interrupt Vector Register 4 6 GEO Address Register Base Address 0x8008 read D16 The register content is the following GEO ADDR 0 GEO ADDR 1 GEO ADDR 2 GEO ADDR 3 GEO ADDR 4 Fig 4 3 Geographical address register This register allows readback of the level of GEO pins for the selected board The register content is valid only for the VME64X board version The register content for the VME64 version is Ox1F 4 7 Module Reset Register Base Address 0x800A write only D16 A dummy access to this register allows to generate a single shot RESET of the module 4 8 Firmware Revision Register Base Address 0x800C read only D16 This register contains the firmware revision number coded on 8 bit For instance the REV 1 2 register content is EXER EIE ESTER GA CURES ERES CREDI o oro ojo ejoj1 o ojo ojo ojt o Ox1 0x2 Fig 4 4 Firmware Revision Register NPO Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 18 PAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 Gen
9. Rel PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 3 2 2 FPGA USER The microcontroller provides the firmware uploading at board s power on The flash memory contains two versions of the firmware Standard or Backup FPGA USER Program Circuit P Ww a NME gt y gt FPGA USER S b LT i Fig 3 5 FPGA USER diagram FPGA VME aim is to handle the operation of FPGA USER which can be programmed on the fly i e without turning off the system thus allowing quick debug operations by the Developer Register implemented on FPGA VME allows the following operations e FPGA USER flash memory programming e Standard Backup Firmware selection FPGA USER updating N B it is strongly suggested to upgrade ONLY one of the stored firmware revisions generally the Standard one per time NPO Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 15 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 4 VME Interface 4 1 Register address map The Address map for the Model V1495 is listed in Table 4 1 All register addresses are referred to the Base Address of the board i e the addresses reported in the Tables are the offsets to be added to the board Base Address Ta
10. datum to be written via G DOUT or to be read via G DIN 5 3 4 V1495 Mezzanine Expansion Ports PORT D E F INTERFACE These signals allows to handle the interface with the piggy back board ports D E F The following table explains the available signals Table 5 2 V1495 Mezzanine Expansion Ports signals Port Signal Function Applies to D D DIR Selects direction Bidirectional port D DIN Read the logic level Input Bidirectional D DOUT Set the logic level Output Bidirectional D IDCODE Read IDCODE for piggy back identification All D LEV Set the logic level Output Bidirectional E E DIR Selects direction Bidirectional port E DIN Read the logic level Input Bidirectional E DOUT Set the logic level Output Bidirectional E IDCODE Read IDCODE for piggy back identification All E LEV Set the logic level Output Bidirectional F F DIR Selects direction Bidirectional port F DIN Read the logic level Input Bidirectional F DOUT Set the logic level Output Bidirectional F IDCODE Read IDCODE for piggy back identification All F LEV Set the logic level Output Bidirectional 5 3 5 PDL Configuration Interface PDL Configuration Interface signals are as follows Table 5 3 PDL Configuration Interface signals PDL WR OUT 1 Write Enable PDL SEL OUT 1 PDL Selection 0 gt PDLO 1 gt PDL1 PDL_READ IN 8 Read Data PDL_WRITE OUT 8 Write Data PDL_DIR OUT 1 Directi
11. flop state The pulse width Tp is Tp Tpd Tpf Where Tpd is the delay of the selected PDL programmable via VME or by on board dip switches whichever mode is enabled Tpf is the delay introduced by the FPGA pad and internal logic The maximum pulse width is limited by the PDL maximum delay in this case 5 5 6 Delay Unit using DLOs The following diagram shows the implementation of the DELAY UNIT using two oscillators based on delay lines DLO present on the board DLOx DELAY COUNTER Fig 5 6 Delay Unit with DLOs COINC DLOx GATE l DLOx OUT L LS I l PULSE STARTDELAY DELAY_COUNTER 0 X 1i Y 2 XY s Yayo STOPDELAY rq PULSE_OUT Fig 5 7 DLOs Delay line timing NPO Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 33 EXA ga PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 5 6 NPO When a coincidence occurs leading edge of COINC signal the STARTDELAY signal becomes active high STARTDELAY enables the oscillator on external delay line DLOx selected via MODE register At the same time the DELAY COUNTER is enabled The PULSE signal leading edge increases the counter until the value set via GATEWIDTH register is reached The PULSE signal corresponds in this reference with the selected PDL output On the first PULSE l
12. 042 D16 Read Slot D mezzazine ID Code ID Code is X 0007 if mezzanine is plugged E_IDCODE 0x0044 D16 Read Slot E mezzazine ID Code ID Code is X 0007 if mezzanine is plugged F_IDCODE 0x0046 D16 Read Slot F mezzazine ID Code ID Code is X 0007 if mezzanine is plugged 5 5 REGISTER DETAILED DESCRIPTION 5 5 1 V1495 Front Panel Ports Registers PORT A B C G The Front Panel ports A B C G can be configured and accessed using a set of registers The x MASK y x can be A B C y can be L or H registers can be used to selectively mask a bit of a port Each status register is split into two 16 bit register MASK L corresponds to MASK 15 0 while MASK H corresponds to MASK 31 16 There is not a MASK register associated with G port Each bit of the input ports A B mask registers are internally used in a logic AND operation with the corresponding bit of the port so it is an active low mask bit For instance when A_ MASK L 0 is set to 0 the A 0 bit is internally masked logic 0 NPO Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 29 EA Rel PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 NPO Each bit of the output port C mask register is internally used in a logic AND operation with the corresponding bit of the internal signal so it is an active low mask bit For instance when C MASK _L 0
13. CONFIGURATION REGISTER cccccsscsessseseseseseseseseseeeseseseseseseseseseseseseseseceseseseseseseeeeees 19 5 V1495 USER FPGA REFERENCE DESIGN KIT ecce ee eee eee ee eee enne eee tn eset ea ene e ense eese en eese eaae 20 Deli JINTROD CTION ede NEN 20 PHA D Cen uM 20 3 21 VIdJO5HAL detecte TN 20 3 2 2 COIN REEERENCGE Desigti iie tie cesses aee SER SEA e NENNT cents en REIe P RAS eee dba a 21 5 3 INTERFACE DESCRIPTION ccccccccccccccccccccceccccccscscscscececscsceccescscseseseececsesescesecsescececsesesesesesssesesesosseososeserss 23 5 3 1 GlobalSighalss ste ea v pai ERG DARAN iss DA ON E P MG ees 23 5 3 2 REGISTER INTERFACE esie ici 23 5 3 3 V1495 Front Panel Ports PORT A B C G INTERFACE essent 24 5 3 4 V1495 Mezzanine Expansion Ports PORT D E F INTERFACE eese 24 3 3 3 PDE Configuration Interface ssec getestet dederit ep oas a aka 24 5 3 6 Delay Lines and Oscillators I O eese eee esee seen entente nennen nennt ron n non nn entes ennt enne 25 5 3 7 SPARE Interface a Ge Adr E e RES a ees o ie e prede 25 5 3 8 LEDilnterlQces su al chases desde ahs BOR REOR OUO 25 5 4 REFERENCE DESIGN DESCRIPTION cccccceccoccsceccoccsceccoesscececccscecceccececseccsceccoscscscecsescecceccesessesesseceeeveseoevees 25 5 5 REGISTER DETAILED DESCRIPTION eeeeeeeeee e e e enn nnn nnn nnnm nn nnn nnn nnn nnn nnn nnne sanas anne 29 5 5 1
14. D TBD TBD 2 3 Front panel displays The front panel refer to 2 4 hosts the following LEDs DTACK Colour green Function it lights up green whenever a VME read write access to the board is performed USER Colour green orange red Function programmable NPO 00117 04 V 1495 MUTx 01 Filename V1495 REVI DOC 40 Number of pages Page 8 PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 2 4 Front Panel Mod V1495 USER DTACK e e e A rom 00 lt r z w A rom oocrz Fig 2 1 Model V1495 front panel with A395A B C piggy back boards NPO Filename Number of pages Page 00117 04 V 1495 MUTx 01 V1495 REVI DOC 40 9 Document type User s Manual MUT 2 5 Motherboard Specifications Title Mod V1495 General Purpose VME Board Revision date 12 05 2006 PRELIMINARY Revision 1 The Mod V1495 Motherboard is composed by four l O sections see 1 2 described in the following table Table 2 2 V1495 Motherboard I O sections Board No of Ch Direction Logic Signal Bandwidth Front panel connector LVDS ECL PECL single ended TTL optional 1100hm Rt Ro
15. ME by writing the Flash for this purpose download the software package available at http www caen it nuclear software_download php The program is provided as executable source code and project Microsoft Visual C The executable file il the pre compiled program for Windows platform The program is based on the CAENVMEIib library available both for Windows and Linux In order to update the flash memory of the FPGA USER the program must be launched as follows V1495Upgrade FileName BaseAdd TargetFPGA image With FileName the path to be followed of the RBF file generated with Quartus Il see 8 5 6 BaseAdd the base address Hex 32 bit of the V1495 board TargetFPGA the TargetFPGA value must be user Image standard STD or backup BKP For example in order to update the standard firmware of a V1495 with base address 32100000 it is necessary to launch V1495Upgrade V1495 rbf 32100000 user standard NPO Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 39 EA Rel PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 If the upgrading is successful the number of transferred bytes is reported and the program is exited If the upgrading fails then an error message is reported In case of successful upgrading the new firmware can be loaded without turning the board and the crate off by performing a write access
16. S E PROJECT PLOW sas eo cis a en ht dct hs re Act ia Ard nei e ie Es 35 FIG 5 9 QUARTUS II MAIN MENU sssccessssseceesstsecssoeeecssssecsensssecseneseesssnseceessssecsensssecsensececnsntecsensusesssneeessssnsecsens 35 FIG 5 10 QUARTUS IL FILE MENU 5 derit o is 36 FIG 5 11 QUARTUS II PROJECT BROWSER cssscccceessececssseececseseeceesaececsenaececseaceceesuececsesaececeeeeeeseaeeecseuesesseaaeeeeas 36 FIG 5 12 QUARTUS IT NETLIST a ceiba 37 FIG 5 13 QUARTUS II HIERARCHICAL STRUCTURE ss cccssssecessssceceessececsesaececsnceecseeeeecsesaececeeseecessaeeecseaeeesseneeenees 38 FIG 5 14 QUARTUS II COMPILER LAUNCHING e e e aeea rare e aE EE EEr E E E EEEE EEEE OaE EEES 38 FIG 5 15 QUARTUS II COMPILING SUMMARY cccsssseceeseseeeesessceceesaececsesaececseeeeceesaeeecsesaeeecnaeecessaeeecsesaeeesseaaeeeees 39 LIST OF TABLES TABLE 2 1 MODEL V1495 AND PIGGYBACK BOARDS POWER REQUIREMENTS ccce eene eene nnne 8 TABLE 2 2 V1495 MOTHERBOARD I O SECTIONS ocooocococcconcnononccononononcconononnocono nro nc cono nro nn cnn nono nn entere enr entere enne enne 10 TABLE 2 3 V1495 PIGGYBACK BOARDS eerte nee teer e XR ER EXER EE EXER eee e ERE cnc ds ERES ERE trennen Eie 10 TABLE 4 1 ADDRESS MAP FOR THE MODEL V 1495 ooo ceeceessecesececsseceeeeecsaeceeneecsaeceeneecsaeceseeecsaeceeneecaeeeeneesaeeees 16 TABLE 4 2 ROM ADDRESS MAP FOR THE MODEL V 1495 ooo ceeceesseceseceesseceseeecsseceeeeenaeceseeeenaecueecaeceseeecsae
17. _OUT OUT 12 SPARE Data Out SPARE_IN IN 12 SPARE Data In NPO Filename 00117 04 V1495 MUTx 01 V1495 REVI DOC Number of pages Page 40 22 PAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 PORT NAME DIRECTION WIDTH DESCRIPTION SPARE_DIR OUT 1 SPARE Direction LED INTERFACE RED_PULSE OUT 1 RED Led Pulse active high GREEN PULSE OUT 1 GREEN Led Pulse active high 5 3 Interface description NPO 5 3 1 Global Signals The nLBRES must be used as an asynchronous reset signal by the user An active low pulse will be generated when a write is done at the Module Reset register address see 8 4 1 The LBCLK is a 40 MHz clock It is the FPGA main clock 5 3 2 REGISTER INTERFACE The signals of the Register Interface allows to read write into the USER FPGA registers which can be accessed via VMEbus The COIN REFERENCE module shows how to implement a set of registers The following table shows the registers map as it is provided Each register address is coded via constants in V1495pkg vhd file This file allows to modify the registers map all registers allow D16 accesses write only read only or read write Registers default value is the value after a reset for write only and read write registers read only registers return the status of the signals read by the FPGA and have no default value The Register In
18. are if rtl vhd i lo SRC vI495ust demo tiistate if nlLvhd Implements for Poe 3 us SRC vi495usr dema v1495usr demo vhd Ti NS Low Cost Processor i m TM i SRC v1495hal v1495usr_halvam in Cyclone I FPGAs p Software Files 73 Dther Files Fig 5 14 Quartus II compiler launching Quartus at this point launches in sequence the steps of the flow chart synthesis fitting place amp route then shows the correct compiling and the following screen Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 38 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 Quartus l C V1495_USER_DEMO v1495usr_demo v1495usr_demo Compilation Report Flow Summary aj Er File Edit View Project Assignments Processing Tools Window Help Bx Dui 8 BE c NN viassusr demo RLS SGVE Dr ro hr SO u Project Navigator BE Compilation Report Flow Su Entity Logic Cells LC Registers Mer SS Compilation Report Flow Summary Cyclone EP1C4F40006 amp B Legal Notice EE fF Flow summary s coin BE Flow settings 55 vl9Susr hatl 1788 50 0 SE Flow Non Default Global Settir 53 Flow Elapsed Time amp B Flow Log geo tristate_ f13 0 0 0 SU Analysis amp Synthesis Sa Fitter Flow Status Successful Mon May 15 10 15 55 2006 i eS a ze Quartus Il Version 6 0 Build 178 04 27 2006 SJ Web Ed
19. binson Nugent P50E A 32 Input Direct Extended 200MHz 068 P1 SR1 TG type Common Mode 34434 pins input range 4V to 5V Fail Safe input feature LVDS ECL PECL single ended TTL optional 1100hm Rt Robinson Nugent P50E B 32 Input Direct Extended 200MHz 068 P1 SR1 TG type Common Mode 34434 pins input range 4V to 5V Fail Safe input feature LVDS Robinson Nugent P50E C 32 Output Direct 1000hm RI 250MHz 068 P1 SR1 TG type 34 34 pins TTL IN Direct NIM TTL 1 0 TTL OUT Direct e 2 selectable NIM IN Invert io SM UE LEMO 00 NIM OUT Direct 2 6 Piggyback Specifications The four I O Piggyback boards developed so far are described in the following table Table 2 3 V1495 Piggyback boards Board No of Ch Direction Logic Signal Bandwidth Front panel connector LVDS ECL PECL single ended TTL optional E Robinson Nugent P50E A395A 32 Input Direct Common 200MHz 068 P1 SR1 TG type Mode input 844 34 pins range 4V to 5V Fail Safe input feature LVDS Robinson Nugent P50E A395B 32 Output Direct 1000hm RI 250MHz 068 P1 SR1 TG type 34434 pins Robinson Nugent P50E A395C 32 Output Direct ECL 300MHz 068 P1 SR1 TG type 34 34 pins TTL IN Direct A395D 8 Ya TTLOUT Direst oni 250MHz LEMO 00 selectable NIM IN Invert 500hm Rt NIM OUT Direct NPO Filename Number of pages 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 Page 10 Documen
20. ble 4 1 Address Map for the Model V1495 ADDRESS REGISTER CONTENT ADDR DATA Read Write Base 0x0000 0x7FFC USER FPGA Access A24 A32 R W Base 0x8000 Control Register A24 A32 Base 0x8002 Status Register A24 A32 Base 0x8004 Interrupt Level A24 A32 Base 0x8006 Interrupt Status ID A24 A32 Base 0x8008 Geo Address_Register A24 A32 Base 0x800A Module Reset A24 A32 Base 0x800C Firmware revision A24 A32 Base 0x800E Select VME FPGA Flash A24 A32 Base 0x8010 VME FPGA Flash memory A24 A32 Base 0x8012 Select USER FPGA Flash A24 A32 Base 0x8014 USER FPGA Flash memory A24 A32 Base 0x8016 USER FPGA Configuration A24 A32 Base 0x8018 Scratch16 A24 A32 Base 0x8020 Scratch32 A24 A32 Base 0x8100 0x801FE Configuration ROM A24 A32 Read Write capability depends on USER FPGA implementation See Appendix A 4 1 1 Configuration ROM The following registers contain some module s information according to the Table 3 2 they are D16 accessible read only OUI manufacturer identifier IEEE OUI Version purchased version Board ID Board identifier Revision hardware revision identifier Serial MSB serial number MSB Serial LSB serial number LSB Table 4 2 ROM Address Map for the Model V1495 checksum length2 0x8104 MEM checksum length1 0x8108 MEM checksum lengthO 0x810C PO NPO Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 16 EA Rel PRELIMINARY D
21. cidence and or I O register unit This reference design give access to A B C G ports So no mezzanine expansion cards are needed in order to use this design The MODE register can be used to set the preferred operating mode When the board is switched on the default operating mode is I O Register mode NPO Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 25 EA Rel PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 In I O Register Mode C port is directly driven by the C CONTROL register The coincidence is anyway still active so that a pulse in generated on G port when a coincidence event is detected In Coincidence Mode the C port is used to report the coincidence operator on A and B port In this case the C port can be masked through a mask register C MASK A gate pulse is generated on G port when data patterns on input ports A and B satisfy a trigger condition The trigger condition implemented in this reference design is true when a bit per bit logic operation on port A and B is true The logic operator applied to Port A and B is selectable by means of a register bit MODE Register Bit 4 If MODE bit 4 is set to 0 an AND logic operation is applied to corresponding bits in Port A and B i e A 0 AND B 0 A 1 AND B 1 etc In this case a trigger is generated if corresponding A and B port bits are 1 at th
22. e vhd SRC v1485usr demo spare if itl vhd is SRC vi4S5usr demo tristate if rtl vhd SRE v1485usr demo v14935usr demo vhd i SRCA14985hal v1435usr hal vqm E Software Files tr Hierarchy B Files df Design Units Fig 5 12 Quartus II netlist The first time the project is launched the hierarchy includes only the name of the head of the project v1495usr_demo At the end of the project flow the whole hierarchical structure of the project is shown NPO Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 37 PRELIMINAR Y Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 NPO Quartus Il C V1495 USER DEMO v1495usr demo v1495us5r demo File Edit View Project Assignments Processing Tools Window Help Dog e y Bam eoe v1495usr demo xl for FIZA Fig 5 13 Quartus II hierarchical structure In order to generate a new programmation file it is necessary to launch the compiler by clicking on the red play button on the tool bar Quartus Il C 41495 USER DEMO v1495usr demo v1495usr demo File Edit View Project Assignments Processing Tools Window Help Ca gd a 3 am oe v1485usr demo L3 S O a Pose 2 xl pono nen 495usr pka vhd e SRC v143Busr demo coin reference vhd SRC v1495usr demo sp
23. e design provided is developed through VHDL a VHDL knowledge is required in order to modify this design A different description can be developed with a different language among those allowed by the Quartus tool Syntesis translates the descritpion into a format compatible with the subsequent place amp route step Place amp route starting from the netlist performs the placing place and the subsequent interconnection route of the FPGA capabilities Simulation and timing analysis allow to verify the functionality of the project The reference design includes a minimum set of contraints in order to allow the design to perform the foreseen function The last important step is the generation of the programmation file Quartus allows to generate different formats the RBF format is the one used to program the FPGA USER via VME The provided reference project produces automatically this format in the project directory under the filename v1495usr demo rbf Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 34 EXA ga PRELIMINAR Y Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 Design Entry Power Synthesis Analysis Engineering Timing Change Analysis Management Includes block based design system level design software development Programming amp Configuration Fig 5 8 Quartus II project flow The following scre
24. e same time If MODE bit 4 is set to 1 an OR logic operation is applied to corresponding bits in Port A and B i e A 0 OR B 0 A 1 OR B 1 etc In this case a trigger is generated if there is a 1 on one bit of either port A or B Port A and B bits can be singularly masked through a register so that a 1 on that bit doesn t generate any trigger Expansion mezzanine cards can be directly controlled through registers already implemented in this design The expansion mezzanine is identified by a unique identification code that can be read through a register PORTA A MASK operator de M ADIN lA A S AND K M S M K BDN a B OR S A COINCIDENCE E PORTB LOGIC COINC G DOUT 0 e DELAY G DOUT 1 E READ ONLY REG WRITE ONLY REG PDLO PDL1 DLOO DLO1 Fig 5 2 Front Panel Ports Interface Diagram The following table illustrates the the register map of the USER FPGA reference design COIN REFERENCE NPO Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 26 Document type User s Manual MUT Title Mod V1495 General Purpose VME Board PRELIMINAR Y Revision 1 Revision date 12 05 2006 Table 5 7 COIN_REFERENCE register
25. eading edge after the coincidence PULSE OUT is activated high and is kept high until a time GATEWIDTH times the period of the selected DLO The period in this case is constant The maximum pulse width is limited by the GATEWIDTH counter in the case of this reference design the GATEWIDTH register is 16 bit wide so a maximum width of 65536 Td Td is the intrinsic delay of the selected DLO Quartus Il Web Edition Project The freely available Altera Quartus II it can be downloaded from the Altera Web site software must be used in order to generate a user firmware for the USER FPGA It includes the source of VHDL reference design which can be modified according to the decription provided with the manual in order to modify the card functionalities The tool provides a complete pinout of the FPGA it is also enabled to generate the file type of programming RBF format used fot the flash programming This software tool requires the Quartus Il Web Edition rel 5 1 and newer and can be freely downloaded at http www caen it nuclear software download php Quartus II manual is available at www altera com literature hb ats The following figure shows the typical project flow for generating the firmware for an ALTERA FPGA through the following steps Design Entry is the functional descritption of the circuit it could be either a description of the hardware VHDL Verilog AHDL or a scheme made with the tool provide by Quartus The referenc
26. ee tease leere Tale era TO s Ua be eee pea Pee PE aa 8 Dive cPAGCKAGING neue weeene mele noa PO aee ec eer e Te 8 2 23 POWER REQUIREMENTS a PN ER Ree 8 2 3 iFRONTPANEEDISPEAYS eet ree rr re e ee e e e RR HER ere ret ceste he 8 pr NEED UV IU MMMMMMRu BA ARmWA xcxax cc XX 9 2 3 MOTHERBOARD SPECIEICATIONS eere i n 10 2 6 PIGGYBACK SPBGIEICATIONS cuidadito teca cool Sevens tette testet tores tee ee eee hee eet do eee o P v e Re eeu 10 2 71 PIGGYBACK BOARDS INSTALLATION ccoccccccnnononononnnononononononononononononononononononononononononononononononononenonenenenenes 11 3 OPERATING MODES m M 12 3S B D E E e a ati det ltda ds doses dt en bodes sce lade e e HE RC 12 3 1 1 TAI lA ct e eaea n a A e duabn ena e a A reed desks bev 12 3 1 2 TUNECVZ MES das 13 3 2 FPGA PROGRAMMING ooccoocococococonononononononononononononnnn nn nono nn nn nn sese nn sese nn sese esee sese sess sese E sees esse esee sess esse sees esee 14 3 2 1 EPGAVME 5 etes e tou bead be es t E a e ted ot b ced Toke rS iUe 14 3 2 2 PPGA USER t eue et Eure bie d f bet reete dut EE aea decae Pe iM dc 15 4 VME INTERFACE o 16 4 1 REGISTER ADDRESS MAP csceccsssssssevssesenenesosesecesenensecsesesecessnsnesssesesesesenensecsesenscesesesenesesesesesenensnesenesenss 16 4 1 1 Configuration ROM esae ree dr br e Er p aet EPI eer RN eae BE Er SEGi 16 42
27. eesees 16 TABLE 3 1 COIN REBERENCE SIGNALS ertet ee tete o etr ce e te e eerte e EE eR 21 TABLE 5 2 V1495 MEZZANINE EXPANSION PORTS SIGNALS oooococccoconcconononnncconononnncconononnncconn ennt tenet entente enne 24 TABLE 5 3 PDL CONFIGURATION INTERFACE SIGNALS eese enne nennen nente entente cnn neon nc enne 24 TABLE 5 4 DELAY LINES AND OSCILLATORS SIGNALS s cccssccesececsseceseeecsseceneeceaecesneecsaeceeeecsaeceeeeeesaeceeneesaeeeses 25 TABLE 3 5 SPARE INTERFACE SIGNALS 4 eiie eve i iii 25 TABLE 5 0 LED INTERFACESIGNALS 5 tscscnissessensostcsehssboistusetedesyasnessouiacieseh assasaancesoisenasopssanioedesceashansdyes liado 22 TABLE 5 7 COIN REFERENCE REGISTER MAP eeeeeeeeeeeeee enne nente entente enhn intent enne en tentent en tenerse en eren ene 27 TABLE3 8 SELECTION OF THE DELAY LINE 4 eerie fe iter e cuss e Fue exe Eee ee ta cuvsns cv ERN te eoe sits de subeus cadnneus dra ee Pe den 30 NPO Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 5 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 1 General description 1 1 NPO Overview The Mod V1495 is a VME 6U board 1U wide suitable for various digital Gate Trigger Translate Buffer Test applications which can be directly customised by the User and whose management is handled by two FPGA s FPGA Bridge which is used f
28. enshot shows the main menu of Quartus II File Edit View Project Assignments Processing Tools Window Help osujs ae o e Aer e eelol gt raela Project Navigator By Compilation Hierarchy A N Implement n for ENS Low Cost Processor in Cyclone Il FPGAs Y Documentation Bl System Procesna X Emari V Ino A Waring A Onea Waring A Ena A Supera Beene El P kocsin Locate For Help press F1 Toran Idle yum Fig 5 9 Quartus II main menu NPO Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 35 PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 Now select File gt Open Project Edit View Project Assignments Processing Tools Window Help ow Jeep Xx evejo AA Ima ou Project Wizard Convert MAX PLUS II Project Save Project f No s Implement a dur fia SS Low Cost Processor SS in Cydone Il FPGAs YN gt m A UA a Bl MN Ue EAZIEP NA Elle Pr i I UARTUS II Create Update C 4 Export Version 6 0 Convert Programming Files Recent Files Recent Projects Exit At F4 System A Processing A Estra Info A Info A W ami Critical Waming Enor Suppressed Message 4 F ross Locate Opens an existing project D m de Pa Fig 5 10 Quartus II file menu browse the file p
29. eral Purpose VME Board 12 05 2006 1 4 9 Scratch16 Register 4 10 4 11 4 12 4 13 4 14 4 15 NPO Base Address 0x8018 D16 read write This register allows to perform 16 bit test accesses for test purposes Scratch32 Register Base Address 0x8020 D32 read write This register allows to perform 32 bit test accesses for test purposes Select VME FPGA Flash Register Base Address 0x800E read write D16 Select USER FPGA Flash Register Base Address 0x8012 read write D16 VME FPGA Flash Memory Base Address 0x8010 read write D16 USER FPGA Flash Memory Base Address 0x8014 read write D16 These four registers allow the VME and USER FPGA configuration update stored into on board flash memory via VMEBUS The configuration can be updated by the user by means of the V1495Upgrade software developed and distributed by CAEN USER FPGA Configuration Register Base Address 0x8016 read write D16 This register allows the update of the USER FPGA configuration A write access to this register generates a configuration reload The configuration image that will be uploaded into the USER FPGA depends on the IMAGE SELECT bit IMAGE SELECT 0 Backup image 1 Standard image default corran aa IMAGE_SELECT Fig 4 5 USER FPGA Configuration Register Filename Number of pages Page 19 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 PAE PRELIMINARY Document type Title R
30. evision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 5 V1495 USER FPGA Reference Design Kit 5 1 Introduction The CAEN V1495 board provides a user customizable FPGA called USER FPGA The COIN REFERENCE reference design illustrates how to use the USER FPGA to implement a Coincidence Unit amp 1 O Register Unit This design can be customised by the user in order to adapt its functionality to his own needs ON BOARD DELAY LINES HARDWARE ABSTRACTION LAYER MEZZANINE CARD N ON SLOT D MEZZANINE N CARD Ni ON SLOT 22 E USER DEFINED LOGIC CAEN LOCAL BUS MEZZANINE CARD N ONSLOT F Port A 32 IN ECL LVDS Port B 32 IN ECL LVDS Port C 32 OUT LVDS Fig 5 1 USER FPGA block diagram 5 2 Design Kit 5 2 1 V1495HAL The V1495 Hardware Abstraction Layer V1495HAL is a HDL module provided in Verilog format at netlist level in order to help the hardware interfacing NPO Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 20 EA Rel PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 5 2 2 COIN_REFERENCE Design The COIN REFERENCE design VHDL entity is the interface to the V1495HAL If the User wi
31. ition gem Revision Name w1495us1_demo Top evel Entity Name vl485usr demo Family Cyclone Device EPIC4F400C6 Timing Models Final Met timing requirements Yes Total logic elements 873 4000 22 Total pins 205 301 91 Total virtual pins 0 Total memory bits 0 78 336 0 Total PLLs 0 2 0 7 Hierarchy B Files d Design Units Status ES i Full Compilation BIGEN m2 Analysis amp Synthesis RINNE 00 00 35 Fitter 00 00 40 Assembler 00 00 06 Timing Analyzer MARY 00 00 05 E 5 Info Quartus II Timing Analyzer was successful 0 errors 4 warnings be 3 Info Quartus II Full Compilation was successful 0 errors 13 warnings 3 gt lt System Processing Extra Info A Info Warming A Critical Warming Error A Suppressed T Message 0 of 698 4 xz al For Help press F1 haa Idle NUM Messages Fig 5 15 Quartus II compiling summary At this point an updated RBF file is generated in the project directory This file can be used for updating the firmware as described in S 5 7 5 7 Firmware upgrade The board can store two firmware versions called STD and BKP respectively at Power On a microcontroller reads the Flash Memory and programs the module with the firmware version selected via the SW9 jumper on the motherboard which can be placed either on the STD position or in the BKP position It is possible to upgrade the board firmware via V
32. map NAME ADDRESS DATA SIZING ACCESS NOTES DEFAULT C_MASK_L 0x0014 C_MASK_H 0x0016 GATEWIDTH 0x0018 Filename NPO 00117 04 V 1495 MUTx 01 MER 16 D V1495 REVI DOC Port A status This register reflects A 15 0 bit status Port A status This register reflects A 31 16 bit status Port B status This register reflects B 15 0 bit status Port B status This register reflects B 31 16 bit status Port C status This register reflects C 15 0 bit status Port C status This register reflects C 31 16 bit status Port A mask This register X FFFF A 15 0 Mask bit is active low Port A mask This register X FFFF A 31 16 Mask bit is active low Port B mask This register X FFFF B 15 0 Mask bit is active low Port B mask This register X FFFF B 31 16 Mask bit is active low Port C mask This register X FFFF C 15 0 Mask bit is active low Port C mask This masks C 31 16 register X FFFF Mask bit is active low Gate signal width This number X 0004 represents a multiple of the selected delay line period see detailed description Number of pages 40 EA Rel PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 NAME ADDRESS DATA SIZING ACCESS NOTES DEFAULT C CONTROL L 0x001A D16 WO Port C control When the port C is X 0000 configured to be an output under
33. ocument type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 nse man oma mma CATE hee CTI hme wmm 0x8130 NS CTO mma we mma ww mma rem oo emn COC These data are written into one Flash page at Power ON the Flash content is loaded into the Configuration ROM see Appendix A 4 2 Control Register Base Address 0x8000 read write D16 This register allows performing some general settings of the module Not used for VME FPGA Rev 1 0 Foreseen for future development 4 3 Status Register Base 0x8002 read only D16 This register contains information on the status of the module Not used for VME FPGA Rev 1 0 Foreseen for future development 4 4 Interrupt Level Register Base Address 0x8004 read write D16 The 3 LSB of this register contain the value of the interrupt level Bits 3 to 15 are meaningless Default setting is 0x0 In this case interrupt generation is disabled Not implemented in VME FPGA Rev 1 0 Available in next releases 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reg Fig 4 1 Interrupt Level Register NPO Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 17 PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 4 5 Interrupt Status
34. on 0 gt Write 1 gt Read Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 24 PAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 5 3 6 Delay Lines and Oscillators I O Delay Lines and Oscillators signals are as follows see also 5 5 5 and 5 5 6 Table 5 4 Delay Lines and Oscillators signals PDLO_OUT IN 1 Signal from PDLO Output PDL1_OUT IN 1 Signal from PDL1 Output DLOO OUT IN 1 Signal from DLOO Output DLOI OUT IN 1 Signal from DLO1 Output PDLO_IN OUT 1 Signal to PDLO PDL1_IN OUT 1 Signal to PDL1 Input DLOO_GATE OUT 1 Signal to DLOO Input DLO1_GATE OUT 1 Signal to DLO1 Input 5 3 7 SPARE Interface These signals allow to set and read the status of SPARE pin present on the board Table 5 5 SPARE Interface signals SPARE_OUT OUT 12 SPARE Data Out SPARE_IN IN 12 SPARE Data In SPARE_DIR OUT 1 SPARE Direction 5 3 8 LED Interface These signals when active for one clock cycle allow to generate a blink of the relevant Led Table 5 6 LED Interface signals RED_PULSE OUT 1 RED Led Pulse active high GREEN PULSE OUT 1 GREEN Led Pulse active high 5 4 Reference design description The reference design preloaded into the USER FPGA is given as a design guide It is a full functional application of the usage of the board as a con
35. on the USER FPGA Configuration register Base Address 0x8016 it is necessary to write 1 in order to load the standard version and to write O in order to load the backup version N B it is strongly suggested to upgrade ONLY one of the stored firmware revisions generally the STD one if both revision are simoultaneously updated and a failure occurs it will not be possible to upload the firmware via VME again NPO Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 40
36. or PDL programming 0 the selected PDL has as delay value on its parallel programming bus the dip switch value 1 the selected PDL has as delay value on its parallel programming bus the PDL_DATA register 8 LSB PDL_SEL allows to select one of the PDL s PDLO and PDL1 for read write operations PDL_DATA register is used to Write the delay value for the next delay update via VMEbus Read the on board switch status Examples updating of PDLO delay via switch the default value in the PDL_CONTROL allows to update the delay directly via dip switch just after the board turning ON each change in the dip switch status set immediately a new delay value The sequence to be followed is Step 1 write 0x1 in the PDL_CONTROL register Step2 update the dip switches value B updating of PDL1 delay via switch Step 1 write 0x5 in the PDL_CONTROL register Step 2 update the dip switches value C updating of PDLO delay via VMEbus Step 1 write 0x3 in the PDL_CONTROL register Step2 write the delay value in the PDL_DATA register D updating of PDL1 delay via VMEbus Step 1 write 0x7 in the PDL_CONTROL register Step2 write the delay value in the PDL_DATA register GATE WIDTH USING Delay Line Oscillators Filename Number of pages Page 31 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 EXA gana PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 The GATEWIDTH regis
37. or the VME interface and for the connection between the VME interface and the 2nd FPGA FPGA User through a proprietary local bus FPGA Bridge manages also the programming via VME of the FPGA User FPGA User which manages the front panel I O channels FPGA User is provided with a basic firmware which allows to perform coincidence matrix I O register and asynchronous timers functions FPGA User can be also free reprogrammed by the user with own custom logic function see 5 1 It is connected as slave to the FPGA Bridge via CAEN Local Bus whose protocol shall be used in order to communicate with the FPGA Bridge and thus with the VME bus The I O channel digital interface is composed by four sections A B C G placed on the motherboard see 1 2 The channel interface can be expanded in the D E F sections by using up to 3 piggyback boards which can be added choosing between the four types developed in order to cover the l O functions and the ECL LVDS NIM TTL electrical standard see 3 1 2 The maximum number of channels can be expanded up to 194 The FPGA User can be programmed on the fly directly via VME without external hardware tools without disconnecting the board from the set up without resetting it or turning the crate off allowing quick debug operations by the developer with his own firmware A flash memory on the board can store two different programming files which can be loaded to
38. pped triggers NPO Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 13 PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 START 2 Lo cape PULSE 2 E be COUNT 0 COUNT 1 COUNT 2 COUNT 2 START 3 PULSES COUNT 3 COUNTO COUNT 1 COUNT 2 GATE Fig 3 3 Timer2 and Timer3 used together for handling a Gate pulse 3 2 FPGA Programming The programming of FPGA VME and FPGA USER are handled by two independent microcontrollers flash memory The updating of the firmware contained in the flash memories does not require the use of external tools and can be executed via VME The flash related to FPGA VME contains the firmware dedicated to the interface of the board with the FPGA USER and the VME bus such firmware is developed by CAEN The flash related to the FPGA USER contains the firmware developed by the User according to his own application requirements 3 2 1 FPGA VME The microcontroller provides the firmware uploading at board s power on The flash memory contains two versions of the firmware which can be selected manually via jumper Standard or Backup FPGA VME Program Circuit VME BUS VME FPGA Fig 3 4 FPGA VME diagram NPO Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 14 EA
39. py Technical Information Manual Revision n 1 12 May 2006 MOD V1495 GENERAL PURPOSE VME BOARD NPO 00117 04 V1495 MUTx 01 CAEN will repair or replace any product within the guarantee period if the Guarantor declares that the product is defective due to workmanship or materials and has not been caused by mishandling negligence on behalf of the User accident or any abnormal conditions or operations CAEN declines all responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It is strongly recommended to read thoroughly the CAEN User s Manual before any kind of operation CE CAEN reserves the right to change partially or entirely the contents of this Manual at any time and without giving any notice Disposal of the Product The product must never be dumped in the Municipal Waste Please check your local regulations for disposal of electronics products CA Ema PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 TABLE OF CONTENTS 1 GENERAL DESCRIPTION se eo os taie eee vase eo Eri Se to Foot shoe io Ea ni oe ea EE e Ne EBoeoY EE a svdesecssuasesog staeesseesscesouceseseetes 6 d5 OVERVIEW A ehh eei ob oma oni been V an AS 6 132 3 BLOCK DIAGRAM zi certe nemo de au ER 7 2 TECHNICAL SPECIFICATIONS 2 vin toos opea ko eo ero aa n e poo eit Fla ae erre a aeter
40. r by means of the DELAY SEL bit MODE 1 0 The selection of the delay line is made according to the following table Table 5 8 Selection of the delay line MODE MODB 0 DELAY LINE 0 0 PDLO 0 1 PDLI 1 0 DLOO 1 1 DLOI 5 5 4 PDL DELAY VALUE SETTING AND READBACK The programmable delay lines chip available on board can be programmed with a specific delay using on board 8 bit dip switch SW6 for Delay 0 and SW5 for Delay1 on motherboard via VMEbus Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 30 PAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 NPO Two registers are available to configure PDLs PDL CONTROL PDL DATA PDL CONTROL is used to Select target PDL for read write operations Enable delay update Select programming mode via VME register or by on board switches The PDL CONTROL bit fields are shown in the following figure 2 1 L gt X PDL WR PDL DIR PDL SEL isi is ou 10 9 8 7 6 5 4 3 0 Fig 5 3 PDL_CONTROL bit fields PDL_WR 1 enables the updating of the PDL delay value in this way the delay value set either via dip switch or via PDL_DATA register is automatically loaded By setting this bit to 0 the delay value cannot be changed PDL_DIR allows to select the source of data f
41. register control see MODE register the status of C 15 0 is controlled by this register C CONTROL H 0x001C D16 WO Port C control When the port C is X 0000 configured to be an output under register control see MODE register the status of C 31 16 is controlled by this register MODE 0x001E D16 WO It configures the behaviour of the X 0008 system Default I O MODE 1 0 DELAY SEL Register MODE 3 UNIT MODE Mode 0 Coincidcence Unit 1 VO Register MODE 4 OPERATOR 0 C A AND B 1 C A ORB MODE 5 PULSE_MODE See Description SCRATCH 0x0020 D16 RW This register is available to test X 5A5A read and write to a register G CONTROL 0x0022 D16 W Only Bit 0 G CONTROL 0 is X 0000 used in this reference design It can be used to select G output level 0 TTL mcomonr mwc os w www NPO Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 28 EA Rel PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 e ee ee mcomonr nms os fw i mcomons nwe ois fw eow __A ____A A gt REVISION 0x003C Firmware revision For example X XXYY the register conent for release 1 0 is X 0100 PDL CONTROL 0x003E D16 It allows to either set the PDL X 0001 delay though either on board Default PDL switches or via VMEbus delay is set by on board dip switches D IDCODE 0x0
42. roject v1 495usr demo qpf File Edi Vew Project Assignments Processing Tools Window Help Bs m sls ERES 1 dixe we s rie ja Project Navigator diy Compilation Hierarchy Cerca in E V14886 USER DEMO eB sec TI irsion 6 Risorse del computer Risorse direle Nome file v1485u81 cemo qpf Tipo file Quartus lI Project File qpf quartus qar Annulla d essing A Extra Info it Eee ES 3 ae A Dwe For Help press F1 E ie NM Fig 5 11 Quartus II project browser NPO Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 36 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 Once the project is open the Project Navigator shows the following information There are 5 VHDL files filename vhd and a Verilog netlist listname vqm The reference design is included in the coin_reference vhd file The other files provide support to the project and shall not be midified by the developer HAL Hardware Abstraction Layer is implemented on the netlist Verilog v1495usr hal vqm Y Quartus Il C 41495 USER DEMO v1495usr demo v File Edit View Project Assignments Processing Tools Window n GP hd A v ca Y vt495usr dem Project Navigator i xi SY Files i E We SRC v1495usr demo v1495usr pkg vhd oo SRC vi4985usr demo coin referenc
43. shes to use V1495HAL to develop his own application on the V1495 platform the VHDL entity must not be modified this means that signals names and function of the COIN REFERENCE entity must be used as shown in the following table Table 5 1 COIN REFERENCE signals PORT NAME DIRECTION WIDTH DESCRIPTION GLOBAL SIGNALS NLBRES IN 1 Async Reset active low LCLK IN 1 Local Bus Clock 40 MHz REGISTER INTERFACE REG_WREN IN 1 Write pulse active high REG_RDEN IN 1 Read pulse active high REG_ADDR IN 16 Register address REG_DIN IN 16 Data from CAEN Local Bus REG_DOUT OUT 16 Data to CAEN Local Bus USR_ACCESS IN 1 Current register access is at user address space Active high V1495 Front Panel Ports PORT A B C G INTERFACE A_DIN IN 32 In A 32 x LVDS ECL B_DIN IN 32 In B 32 x LVDS ECL C_DOUT OUT 32 Out C 32 x LVDS G LEV OUT 1 Output Level Select 0 gt TTL 1 gt NIM G DIR OUT 1 Output Enable 0 gt Output 1 gt Input G_DOUT OUT 2 Out G LEMO 2 x NIM TTL G_DIN IN 2 In G LEMO Q x NIM TTL V1495 Mezzanine Expansion Ports PORT D E F INTERFACE D IDCODE IN 3 D slot mezzanine Identifier D LEV OUT 1 D slot Port Signal Level Select the level selection depends on the mezzanine expansioon board mounted onto this port D DIR OUT 1 D slot Port Direction D DIN IN 32 D slot Data In Bus D DOUT OUT 32 D slot Data Out Bus NPO
44. t type User s Manual MUT 2 7 NPO 00117 04 V1495 MUTx 01 PRELIMINARY Title Revision 1 Revision date Mod V1495 General Purpose VME Board 12 05 2006 Piggyback boards installation In order to install one A395x series piggyback board on the V1495 motherboard it is necessary to follow these steps Remove unscrew the metal cover one at will Plug the piggyback board into the 100 pin connector on the motherboard Fix the piggyback board with the screws Filename Number of pages Page V1495 REVI DOC 40 11 CAE PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 3 Operating modes 3 1 Timers Gate Trigger applications require the production of an output signal with programmable width Gate whenever an input signal Trigger occurs Gates can be produced in several ways according to the system set up which can be either synchronous or asynchronous Synchronous systems Input levels are referred to a system clock they can be sampled by the clock itself and the output is a gate signal obtained with a counter whose width and delay is a multiple of the clock period If the application requires a width and delay of the Gate signal synchronous but with step smaller than the clock system duration this can be achieved by enabling the PLL in the USER FPGA and enter the reference clock on channel GO Asynchronous systems
45. ter can be used to set the gate signal width on the G port see Delay Unit using DLOs see 8 5 5 6 5 5 5 Delay Unit using PDLs The following diagram shows the implementation of the DELAY UNIT using the one of the two programmable delay lines PDL available on the boards MONOSTABLE 360 ns pulse Fig 5 4 Delay Unit with PDLs Tmon COINC PDLXIN OL PDLxOUT ofS L PDL PULSEOUT STARTDELAY STOPDELAY Fig 5 5 PDLs Delay line timing The pulse width generated using PDLs Tp can be adjusted setting the PDL delay using either on board dip switches or through register When a coincidence occurs leading edge of COINC signal the STARTDELAY signal becomes active high STARTDELAY triggers a monostable in order to generate a pulse with a duration large enough to ensure maximum linearity performance of the This value should be more than 320 ns PDL see 3D3428 component datasheet The selected value in the reference design is 360 ns NPO Filename Number of pages Page 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 32 EXA ga PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 The PDL_PULSEOUT internal signal is generated as the logic OR of PDL_IN and PDL_OUT so generating a pulse whose width is proportional to the PDL actual delay The PDL_PULSEOUT signal falling edge is used to reset the flip
46. terface allows to abstract the VME registers access The User can access a simple register interface two signals REG WREN e REG RDEN are pulses with a one clock cycle duration which enables respectively a write or a read access to a register REG ADDR signal represents the register address Writing into a register In case of a write operation into a register via VME the 16 bit datum is available through the REG DIN signal The datum is guaranteed stable on the CLK leading edge where REG WREN is active The register access is valid only when USR ACCESS is at logic level 1 Reading from a register In case of a read operation from a register via VME the datum to be returned must drive the REG DOUT and be stable on the CLK leading edge where REG RDEN is active The register access is valid only when USR ACCESS is at logic level 1 Filename Number of pages Page 23 00117 04 V1495 MUTx 01 V1495 REVI DOC 40 EA Rel PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 5 3 3 V1495 Front Panel Ports PORT A B C G INTERFACE These signals allows to handle the interface with the motherboard ports A B C G A DIN and B DIN signals show the logic level of A and B ports 32 bit input only The output logic level on port C can be set via C DOUT signal The logic level on port G LEMO connectors can be set via G LEV signal the direction via G DIR the
47. the FPGA User at any moment Four independent digital programmable asynchronous timers are available for Gate Trigger applications lt is possible to chain them for generating complex Gate Trigger pulse Filename Number of pages Page 6 00117 04 V 1495 MUTx 01 V1495 REVI DOC 40 PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 1 2 Block Diagram BRIDGE FPGA 16 32 64 bit VME interface 8 bit USER PROGRAMMABLE FPGA FW LOADING optional r v FLASH USER FPGA CONFIG Asyn Timers A Fig 1 1 Mod V1495 Block Diagram NPO Filename Number of pages Page 00117 04 V 1495 MUTx 01 V1495 REVI DOC 40 7 PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 05 2006 1 2 Technical specifications 2 1 Packaging The module is housed in a 6U high 1U wide VME unit The board is provided the VME P1 and P2 connectors and fits into both VME standard and V430 backplanes 2 2 Power requirements The power requirements of the modules are as follows Table 2 1 Model V1495 and piggyback boards power requirements Power supply Mod V1495 Mod A395A Mod A395B Mod A395C Mod A395D 5 V TBD TBD TB

Caen V1495

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