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SARA-G3 and SARA-U2 series

1. E gt a a n z z z E a a a ao8Soaocaccoorao aoaosoaoaoarano aoosoooooO0prano aosoaoaaarano 22222222222 zz 22222222 zz 22222222 zz 22222222 P oozoooooxoo0 oomrooooo0xo0 oozooooOozoo0 LACER 00 OOS 00 Pe 5 a 3 2 po po 5 7 4 gt 2 fs ss oes GND GND NN vec cn vec ga EE E C2 CD C2 Es vc E GND vcc GND A 5 4 a a 73 P72 0 75 I 7 S95 LISA C2 series LISA U1 series LISA U2 series vin on oona AE GNb d i H 5 GND KR EZ E ESI Rsvp Mic P REND Top View Top View Top View DSR ERI EA nsVD MIC N RI Dl RSVD MIC GND GND SPI MRDY KJ SPI MRDY GPIO14 KZ DCD E RSVD MIC BIAS GND SPI SRDY EHI SPI SRDY GPIO13 EJ DTE Eu og RSVD SPICN SPI MISO EZ SPI MISO GPIO12 Ei RTS ED iae EIN RSVD SPK P E SPI MOSIZ SPI MOSI GPIO11 IE Gis E SARA G3 series Ea cno SPI SCLK EHI SPI SCLK GPIO10 E Top Vi TXD op View SIM DET RSVD SPK N EJ GPIO9 I251 WA EJ RXD EHI Sin RSVD SPK P ESI GPIO8 251 CLK EH cnp EA Li AEA sm rst RSVD CODEC_CLK EH PUR ON E smio RSVD GPIO1 EE EJ sm c k nsen nee in 65 96 6N0 DER oe cu Rsvo ea Ed EG E Eg svo os xo GND ETIN EJ Rsvb 2s wA ome Ed E E Ed Gea Peeler err amga S8Saaqq aba axx Q SaSgeer p aoa eva ui 32K O Figure 91 LISA series vs SARA G3 series modules pin assignment highlighted pads that can be shared on the application board This is the basis of the Nes
2. RM 82 PIEEEESU UV EIDEM 83 2 2 1 Moduilesupply VCC ite treten E pne uda KD Mad qe Pr aM RUE 83 2 2 2 RTC supply V BCKP sssssssssetettet tette tette ttt ttt trt ttt 95 2 23 Interface supply V INIT s nera epp nte ettet ten Eoi itane Utd ieur tu en bar idend 97 2 3 System f nctions Interfaces beet dte bet tabe o a a dat de RD a te uade cs tdt te becas 98 2 3 1 Module power on PWR ON e ene ene nnnm nnnrn nennen enn nennen irren enne nns nnns 98 2 3 2 Module reset RESET N sssssesen eee emen enennenrereser ener erre sse s s sese eere ne seeds EE 99 2 3 3 32 KAZ signal EXT32K and 32K OUT uut dtt qu ctn teat ret nde cem det oue teure i 100 2 4 Antenrna riterface eee Le ete te i ed ef eet itat tee Lotes ted d 102 2 4 1 Antenna RF interface ANT ssssssssssesesee eren eeenememeneeeer enne eene ne ness s ne neta renes e sss sae Ent 102 2 4 2 Antenna detection interface ANT DET ssssseseseen Renee eneneemrne ener enne 109 2 5 SWIC ACE in eMe ADR ME MEM UR M DM MENS 112 PA SeralinternlateS RR RRORRURRE 118 2 6 1 Asynchronous serial interface UART cccccccccccsscccsececsseeecsseecseecsseeecsseeccsseeesaescsaeeecsteccsaeeesaes 118 2 6 2 Auxiliary asynchronous serial interface UART AUX csssssssssee e ene 123 2 6 3 Universal Serial Bus USB sssssssssee eene eene n ao E rene erase
3. FIRST SARA G3 SARA U2 SIM CARD 3V8 VPP C6 4E en L VCC C1 Switch e Io C7 VSIM P NSM T CLK C3 E 005 INS RST C2 SIM 10 IKE DAT am 1 x GND C5 C1 C2 C3 C4 C5 pil p2 D3 pa SIM CLK E CLK gt Je F SIM_RST EG rst e JRST PARE SEL al VPP C6 T ove o e vec C1 10 C7 Application CLK C3 Processor e RST C2 GPIO e a ok X GND C5 R1 C6 C7 C8 C9 C10 pd og p7 p J2 Figure 58 Application circuit for the connection to two removable SIM cards with SIM detection not implemented Reference Description Part Number Manufacturer C1 C4 C6 C9 33 pF Capacitor Ceramic COG 0402 596 25 V GRM1555C1H330JZ01 Murata C5 C10 C11 100 nF Capacitor Ceramic X7R 0402 1096 16 V GRM155R71C104KA01 Murata D1 D8 Very Low Capacitance ESD Protection PESD0402 140 Tyco Electronics R1 47 KQ Resistor 0402 5 0 1 W RC0402JR 0747KL Yageo Phycomp J1 J2 SIM Card Holder Various Manufacturers 6 positions without card presence switch C707 10M006 136 2 Amphenol U1 4PDT Analog Switch FSA2567 Fairchild Semiconductor with Low On Capacitance and Low On Resistance Table 39 Example of components for the connection to two removable SIM cards with SIM detection not implemented 2 5 1 2 Guidelines for SIM layout design The layout of the SIM card interface lines VSIM SIM_CLK SIM_IO SIM_RST may be critical if the SIM card is placed far away from the SARA G3
4. 4 B4 CTS DIR2 OE _ DIRA GND zx nA Unidirectional 3V0 Voltage Translator 1v8 pun VCCA VCCB TS DIR1 DTR a B1 DTR DSR 3 42 B2 DSR RI 4 3 A3 B3 RI DCD 4 B4 DCD DIR2 M 1 1 DIR3 OE GND DIR4 GND GND u2 Figure 60 UART interface application circuit with complete V 24 link in DTE DCE serial communication 3 0 V DTE Reference Description Part Number Manufacturer C1 C2 C3 CA 100 nF Capacitor Ceramic X7R 0402 10 16 V GRM155R61A104KA01 Murata U1 U2 Unidirectional Voltage Translator SN74AVC4T774 Texas Instruments Table 40 Component for UART application circuit with complete V 24 link in DTE DCE serial communication 3 0 V DTE UBX 13000995 R10 Early Production Information Design in Page 118 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual Providing the TXD RXD RTS CTS and DTR lines only not using the complete V 24 link If the functionality of the DSR DCD and RI lines is not required or the lines are not available Leave DSR DCD and RI lines of the module unconnected and floating If RS 232 compatible signal levels are needed two different external voltage translators e g Maxim MAX3237E and Texas Instruments SN74AVCAT774 can be used The Texas Instruments chips provide the translation from 1 8 V to 3 3 V while the Maxim chip provides the translation from 3 3 V to RS 232 compatible signal leve
5. 3V8 15pF 33pF Connector Y External up ll K J fe Antenna oo I L3 i m 5 E E 10k S 82nH 330pF 100nF 10nF 56pF 15pF E t x 27pF ESD N E 00 for SARA G300 SARA G310 SIM Card pi Connector V_BCKP V_INT dk L sw1 wc of ee back up T 1900 p LL E z Ccvcc C1 o o l a pude Application CCIO C7 Processor Ia E CCCLK C3 WEIN CCRST C2 Dra X X XX GND C5 Output 470k 47PF 47pF 47pF ATpF 100nF ESD ESD ESD ESD ESD ESD Open u blox 1 8V Drain 3v8 LDO Regulator 1V8 GPS GNSS Receiver Output L a ad RSVD GPIO2 RSVD SDA RSVD SCL 32K OUT GPIO3 RSVD GPIO4 Audio Codec MAX9860 EXT32K RSVD IRQn MICBIAS 1uF 32 2k SDA Microphone riuF EMI RSVD VUSB DET id miar H bi 1uF EMI RSVD 125_TXD som man jH pe z ai RSVD 12S_RXD SDOUT MICGND 10nF 10nr 27pF 27pF Esp eso RSVD 125 CLK BCLK ien aen es E Speaker RSVD I25 WA LRCLK gurp e E e x EMI RSVD CODEC CLK Mak SUIN ecc TXD_AUX USB D x RXD AUX USB D 10nF 10nF 27pr 27pF esp esp D cus RSVD MIC BlAS T SS cw uu T0uF 2 2k I 2 2k RSVD MIC P Il ava 100nF i RSVD MIC_N i ROOF LEGEND Network 37 2 2k 1 C Mount for SARA G3 and SARA U2 modules Indicator y RSVD MIC GND C Mount for
6. 4 615 ms 1 frame 8 slots 1 frame 8 slots Figure 6 VCC current consumption profile versus time during a GSM call 1 TX slot 1 RX slot Figure 7 illustrates VCC voltage profile versus time during a GSM call according to the related VCC current consumption profile described in Figure 6 Voltage overshoot 3 8 V typ ripple unused unused unused unused MON unused GSM frame 4 615 ms 1 frame 8 slots GSM frame 4 615 ms 1 frame 8 slots Time Figure 7 Description of the VCC voltage profile versus time during a GSM call 1 TX slot 1 RX slot UBX 13000995 R10 Early Production Information System description Page 21 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual When a GPRS connection is established more than one slot can be used to transmit and or more than one slot can be used to receive The transmitted power depends on network conditions which set the peak current consumption but following the GPRS specifications the maximum transmitted RF power is reduced if more than one slot is used to transmit so the maximum peak of current is not as high as can be in case of a GSM call If the module transmits in GPRS multi slot class 10 or 12 in 850 or 900 MHz bands at maximum RF power level the consumption can reach a quite high peak but lower than the one achievable in 2G single slot mode This happens for 1
7. ssssssssssssssssssse ener eene enn rennen enne 161 DERI G upeee c E A E eee ere ce eee ee eee ere 161 3 3 11 Grounding metal covers ssssssssssssssssseee eee eene ener eenr nnne eene nenne 161 3312 se Ot ultrasonic prOCesSes coser ede pla ttd E EErEE neve sy ET tret tn pe pudet fs 161 LE 162 4 1 Product certification approval OVer Vi W enserre ee arr E Ea ana NE Eea eee enne 162 4 2 Federal Communications Commission and Industry Canada notice 163 4 2 1 Safety warnings review the structure nene 163 4 2 2 Declaration of conformity United States only sss 163 4 2 3 Modifications sse eene rennen enne nre nnn nnn enn enn enne nnne 164 4 3 R amp TTED and European conformance CE mark 165 Z4 Anatel certifications redet a xad ha etd ndn ene xad tuens educate MES 166 4 5 SARA G350 ATEX conformance for use in explosive atmospheres ssssssssssssss 167 5 APOC CE TE io 0 S 0 nSS nS4nn4 XSnS 168 5 1 u blox in series production test emere enr nnne enn nene nnns 168 5 2 Test parameters for OEM manufacturer enn ns 168 UBX 13000995 R10 Early Production Information Contents Page 6 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 5 2 1 Go No go tests for integrated devices ssssssssssssssseeeeeeeeeeeeeneenen nnne 169 5 2 2 Functional tests providing RF operation s
8. GNSS supply enabled TES SHDN 1V8 1V8 Ci SPIO 7 R3 SDA2 SCL2 TxD St data ready rr Gpio3 EXTINTO ge GNSS RTC sharing iru poA Figure 72 Application circuit for connecting SARA G3 SARA U2 modules to u blox 1 8 V GNSS receivers Reference Description Part Number Manufacturer R1 R2 4 7 kQ Resistor 0402 5 0 1 W RC0402JR 074K7L Yageo Phycomp R3 47 kQ Resistor 0402 5 0 1 W RC0402JR 0747KL Yageo Phycomp U1 Voltage Regulator for GNSS receiver See GNSS receiver Hardware Integration Manual Table 46 Components for connecting SARA G3 SARA U2 modules to u blox 1 8 V GNSS receivers Figure 73 illustrates an alternative solution as supply for u blox 1 8 V GNSS receivers the V INT 1 8 V regulated supply output of SARA G340 SARA G350 SARA U2 cellular modules can be used to supply a u blox 1 8 V GNSS receiver of the u blox 6 generation or any newer u blox GNSS receiver generation instead of using an external voltage regulator as shown in the previous Figure 72 The V INT supply is able to support the maximum current consumption of these positioning receivers The internal switching step down regulator that generates the V INT supply is set to 1 8 V typical when the cellular module is switched on and it is disabled when the module is switched off UBX 13000995 R10 Early Production Information Design in Page 128 of 192 Qo Ox SARA G3 and SARA U2 series System Integration
9. Active Any wake up event described in the module operating modes summary table above System description Page 19 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 5 Supply interfaces 1 5 1 Module supply input VCC The modules must be supplied via the three VCC pins that represent the module power supply input The VCC pins are internally connected to the RF power amplifier and to the integrated Power Management Unit all supply voltages needed by the module are generated from the VCC supply by integrated voltage regulators including V BCKP Real Time Clock supply V INT digital interfaces supply and VSIM SIM card supply During operation the current drawn by the SARA G3 and SARA U2 series modules through the VCC pins can vary by several orders of magnitude This ranges from the high peak of current consumption during GSM transmitting bursts at maximum power level in connected mode as described in section 1 5 1 2 to the low current consumption during low power idle mode with power saving enabled as described in section 1 5 1 4 1 5 1 1 VCC supply requirements Table 7 summarizes the requirements for the VCC module supply See section 2 2 1 for all the suggestions to properly design a VCC supply circuit compliant to the requirements listed in Table 7 VCC supply circuit affects the RF compliance of the device integrating SARA G3 and SARA U2 series modules with applicable required certification schem
10. 6 Analog audio interface MIC BIAS MIC GND MIC P MIC N uplink and SPK P SPK N downlink pins Accurate design is required to obtain clear and high quality audio reducing the risk of noise from audio lines due to both supply burst noise coupling and RF detection Carefully follow the suggestions provided in section 2 7 1 for schematic and layout design 7 Other digital interfaces UART and auxiliary UART interfaces DDC l C compatible interface digital audio interface and GPIOs Accurate design is required to guarantee proper functionality and reduce the risk of digital data frequency harmonics coupling Follow the suggestions provided in sections 2 6 1 2 6 2 2 6 4 2 7 2 and 2 8 for schematic and layout design 8 32 kHz signal the EXT32K input pin and the 32K OUT output pin of SARA G300 and SARA G310 modules require accurate layout design as it may affect the stability of the RTC reference Follow the suggestions provided in section 2 3 3 for schematic and layout design 9 Other supplies the V BCKP RTC supply input output and the V INT digital interfaces supply output Accurate design is required to guarantee proper functionality Follow the suggestions provided in sections 2 2 2 and 2 2 3 for schematic and layout design UBX 13000995 R10 Early Production Information Design in Page 82 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 2 2 Supply interfaces 2 2 1 Module supply VCC 2 2 1 1 General guideli
11. e e a EN R1 pM Ne B C9 C10 C11 C12 C13 ISET VCC e 8 R3 e TMR Xx ME GND C3 C6 C7 C8 D1TD2 B1 C1 C2 AGND PGND Figure 43 Li lon or Li Polymer battery charging and power path management application circuit Reference Description Part Number Manufacturer B1 Li lon or Li Polymer battery pack with 10 kQ NTC Various manufacturer C1 C5 C6 22 yF Capacitor Ceramic X5R 1210 1096 25 V GRM32ER61E226KE15 Murata C2 C4 C10 00 nF Capacitor Ceramic X7R 0402 1096 16 V GRM155R61A104KA01 Murata C3 uF Capacitor Ceramic X7R 0603 10 25 V GRM188R71E105KA12 Murata C7 C12 56 pF Capacitor Ceramic COG 0402 5 25 V GRM1555C1E560JA01 Murata C8 C13 5 pF Capacitor Ceramic COG 0402 596 25 V GRM1555C1E150JA01 Murata C9 330 pF Capacitor Tantalum D SIZE 6 3 V 45 mQ T520D337MO006ATEO045 KEMET C11 O nF Capacitor Ceramic X7R 0402 10 16 V GRM155R71C103KA01 Murata D1 D2 Low Capacitance ESD Protection CG0402MLE 18G Bourns R1 R3 R5 0 kQ Resistor 0402 5 1 16 W RC0402JR 0710KL Yageo Phycomp R2 0 kQ Resistor 0402 5 0 1 W RC0402JR 071KOL Yageo Phycomp R4 22 kQ Resistor 0402 5 1 16 W RCO0402JR 0722KL Yageo Phycomp L1 2 uH Inductor 6 A 21 mQ 20 7447745012 Wurth U1 Li lon Li Polymer Battery DC DC Charger Regulator MP2617 Monolithic Power Systems MPS with integrated Power Path Management function Table 27 Suggested components for Li lon or Li Poly
12. 32 kHz output RF input output for antenna Input for antenna detection Early Production Information Remarks VCC pins are internally connected each other VCC supply circuit affects the RF performance and compliance of the device integrating the module with applicable required certification schemes See section 1 5 1 for functional description and requirements for the VCC module supply See section 2 2 1 for external circuit design in GND pins are internally connected each other External ground connection affects the RF and thermal performance of the device See section 1 5 1 for functional description See section 2 2 1 for external circuit design in V BCKP 2 3 V typical on SARA G3 series V BCKP 1 8 V typical on SARA U2 series V BCKP is generated by internal low power linear regulator when valid VCC supply is present See section 1 5 2 for functional description See section 2 2 2 for external circuit design in V INT 1 8 V typical generated by internal DC DC regulator when the module is switched on See section 1 5 3 for functional description See section 2 2 3 for external circuit design in High input impedance input voltage level has to be properly fixed e g adding external pull up See section 1 6 1 for functional description See section 2 3 1 for external circuit design in A series Schottky diode is integrated in the module as protection and then an interna
13. Higher protection level could be required if the line is externally accessible on the application board Higher protection level can be achieved by mounting an ESD protection e g EPCOS CA05P4S14THSG varistor array close to accessible point If the V INT supply output is not required by the customer application since DDC l C interface and SIM detection functions are not used voltage translations of digital interfaces are not needed and sensing when the module is switched on is not needed the V INT pin can be left unconnected to external components but it is recommended providing direct access on the application board by means of accessible testpoint directly connected to the V INT pin 2 2 3 2 Guidelines for V INT layout design V INT digital interfaces supply output is generated by an integrated switching step down converter used internally to supply the digital interfaces Because of this it can be a source of noise avoid coupling with sensitive signals UBX 13000995 R10 Early Production Information Design in Page 97 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual 2 3 System functions interfaces 2 3 1 Module power on PWR ON 2 3 1 1 Guidelines for PWR ON circuit design Connecting the PWR ON input to a push button that shorts the PWR ON pin to ground provide an external pull up resistor e g 100 kQ biased by the V BCKP supply pin of the module as described in Figure 45 and Table 29 Connecti
14. OFF ON B time gt 1 TXD input Wake up time 20 ms I OFF j ON Wake up character F gt time Not recognized by DCE Figure 26 Wake up via data reception without further communication UBX 13000995 R10 Early Production Information System description Page 50 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Figure 27 shows the case where in addition to the wake up character further valid characters are sent The wake up character wakes up the module UART The other characters must be sent after the wake up time of 20 ms If this condition is satisfied the module DCE recognizes characters The module will disable the UART after 2000 GSM frames from the latest data reception UART DCE UART is enabled for 2000 GSM frames 9 2s OFF after the last data received ON i time e TXD input 1 Wake up time 20 ms I I OFF ON Wake up character 1 Valid characters i Not recognized by DCE Recognized by DCE ime Figure 27 Wake up via data reception with further communication e The wake up via data reception feature cannot be disabled S In command mode if autobauding is enabled and the DTE does not implement HW flow control the DTE must always send a character to the module before the AT prefix set at the beginning of each command line the first character is ignored if the module is in active mode or it represents the wake up character if the
15. Qo ox SARA G3 and SARA U2 series System Integration Manual The time period between two paging receptions is defined by the current base station i e by the network If the module is registered with a 2G network the paging reception period can vary from 0 47 s DRX 2 i e 2x 51 2G frames up to 2 12 s DRX 9 i e 9 x 51 2G frames If the module is registered with a 3G network the paging reception period can vary from 0 64 s DRX 6 i e 2 3G frames up to 5 12 s DRX 9 i e 2 3G frames The time period of the UART enable disable cycle is configured differently when the module is registered with a 2G network compared to when the module is registered with a 3G network 2G the UART is synchronously enabled to every paging reception on SARA G3 modules whereas the UART is not necessarily enabled at every paging reception on SARA U2 modules the UART is enabled concurrently to a paging reception and then as data has not been received or sent the UART is disabled until the first paging reception that occurs after a timeout of 2 0 s and therefore the interface is enabled again 3G the UART is asynchronously enabled to paging receptions as the UART is enabled for 20 ms and then if data are not received or sent the UART is disabled for 2 5 s and afterwards the interface is enabled again Not registered when a module is not registered with a network the UART is enabled for 20 ms and then if data has not been received o
16. The AT UPSV command configures both the module power saving and also the UART behavior in relation to the power saving The conditions for the module entering idle mode also depend on the UART power saving configuration Three different power saving configurations can be set by the AT UPSV command AT UPSV 0 power saving disabled module forced on active mode and UART interface enabled default AT UPSV 1 power saving enabled module cyclic active idle mode and UART enabled disabled AT UPSV 2 power saving enabled and controlled by the UART RTS input line AT UPSV 3 power saving enabled and controlled by the UART DTR input line Se The AT UPSV 3 power saving configuration is not supported by SARA G3 modules The different power saving configurations that can be set by the UPSV AT command are described in details in the following subsections Table 12 summarizes the UART interface communication process in the different power saving configurations in relation with HW flow control settings and RTS input line status For more details on the UPSV AT command description refer to u blox AT commands Manual 3 AT UPSV HW flow control RTS line DTR line Communication during idle mode and wake up 0 Enabled AT amp K3 ON ON or OFF Data sent by the DTE are correctly received by the module Data sent by the module is correctly received by the DTE 0 Enabled AT amp K3 OFF ON or OFF Data sent by the DTE should be buffered by the DTE and will be cor
17. 30 Oct 2012 28 Mar 2013 12 Apr 2013 03 Jul 2013 08 Aug 2013 29 Nov 2013 23 J an 2014 29 Apr 2014 20 J 23 un 2014 Jul 2014 UBX 13000995 R10 Name SSes sses Ipah sses lpah sses Ipah sses Sses sses sses SARA G3 and SARA U2 series System Integration Manual Status Comments Initial release Updated status to Advance Information pdated suggested paste mask pdated current consumption description U U Updated voice band processing system block diagram Updated DDC l C application circuit for 3V u blox GPS GNSS receivers U pdated status to Preliminary Last revision with old doc number GSM G2 HW 12003 c pdated status to Advance Information Added integration description for SARA G350 ATEX modules pdated SARA G300 SARA G310 supported features Circuit Switched Data GPRS multi slot class 10 32K OUT pin Current consumption c Updated status to Preliminary FW version for SARA G300 00S and SARA G310 00S is 08 58 SIM detection not supported by SARA G300 and SARA G310 modules Added migration between SARA G3 and SARA U2 modules Added the ANATEL label SARA G310 and SARA G350 Document applicability extended to SARA G340 Initial release including SARA U2 series Document applicability extended to SARA G340 01S SARA G350 01S and SARA G350 01B with minor other corrections and clarifications Added additional antennas and external audio codecs exampl
18. AT CPWROFF command more details in u blox AT Commands Manual 3 The SARA U2 series modules can be properly switched off also by Low pulse on the PWR_ON pin which is normally set high by an external pull up for a valid time period see the SARA U2 series Data Sheet 2 for the detailed electrical characteristics of the PWR_ON input In both the cases listed above the current parameter settings are saved in the module s non volatile memory and a proper network detach is performed these are the correct ways to switch off the modules An abrupt under voltage shutdown occurs on SARA G3 and SARA U2 series modules when the VCC module supply is removed but in this case the current parameter settings are not saved in the module s non volatile memory and a proper network detach cannot be performed Se It is highly recommended to avoid an abrupt removal of the VCC supply during SARA G3 and SARA U2 series modules normal operations the power off procedure must be properly started by the appplication as by the AT CPWROFF command waiting the command response for a proper time period see u blox AT Commands Manual 3 and then a proper VCC supply must be held at least until the end of the modules internal power off sequence which occurs when the generic digital interfaces supply output V INT is switched off by the module An abrupt hardware shutdown occurs on SARA U2 modules when a low level is applied to the RESET N input In this case
19. As a result Se RI line monitoring cannot be used by the DTE to determine the number of received SMSes e For multiple events incoming call plus SMS received the RI line cannot be used to discriminate the two events but the DTE must rely on the subsequent URCs and interrogate the DCE with proper commands The RI line can additionally notify all the URCs and all the incoming data PPP Direct Link sockets FTP if the feature is enabled by the AT URING command for more details see u blox AT Commands Manual 3 the RI line is asserted when one of the configured events occur and it remains asserted for 1 s unless another configured event will happen with the same behavior described in Figure 24 ee The AT URING command for the notification of all the URCs and all the incoming data PPP Direct Link sockets FTP over the RI line output is not supported by SARA G3 modules UBX 13000995 R10 Early Production Information System description Page 45 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 9 1 4 UART and power saving The power saving configuration is controlled by the AT UPSV command for the complete description see u blox AT Commands Manual 3 When power saving is enabled the module automatically enters low power idle mode whenever possible and otherwise the active mode is maintained by the module see section 1 4 for definition and description of module operating modes referred to in this section
20. Qo ox SARA G3 and SARA U2 series System Integration Manual A 4 3 Antenna interface RF interface for Tx Rx antenna The same compatible external circuit can be implemented for SARA and LISA series ANT pin even if there are some differences in the operating bands frequency ranges as summarized in Figure 93 SARA G300 900 900 TTTTTTTT TITTITTITITTTITTTITITTITTTITITTITTITITTTTTITTTTITTTTTITTTTITTTTTTT SARA G340 265 850 900 950 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 880 960 1710 1880 SARA G310 900 9o0 TT T ubddmieicbchcbebsies TTTTTTTTITTTTITTTITTTTITTTTITTTITTTITTITTTITTITITTTTTITTITTTTTTT SARA G350 850 900 950 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 824 960 1710 1990 800 800 1900 1900 LISA C200 Tie T T T T T T T TTTTTTOTTOOTTOOTT RTT RTTRTT TT TTTTTTTTTTTTTTTTTTTTT 800 850 900 950 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 824 894 1850 1990 v v I LISA U100 so 3190 190 LISA U120 900 900 C 1900 1 TT T gesketsisbpizisiekciso s T Trrrrrrrirrrirrirrrirrirrrirrrrrrirrrrirrrrririrrit LISA U260 s00 850 900 950 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 824 960 1710 1990 vill vill 1 I LISA U110 sso sso 190 1 LISA U130 200 900 so TTT BS A T T
21. Use a suitable 50 Q connector providing proper PCB to RF cable transition Strictly follow the connector manufacturer s recommended layout for example o SMA Pin Through Hole connectors require GND keep out i e clearance a void area on all the layers around the central pin up to annular pads of the four GND posts as shown in Figure 52 o U FL surface mounted connectors require no conductive traces i e clearance a void area in the area below the connector between the GND land pads Cut out the GND layer under RF connectors and close to buried vias to remove stray capacitance and thus keep the RF line 50 O e g the active pad of U FL connectors needs to have a GND keep out i e clearance a void area at least on first inner layer to reduce parasitic capacitance to ground If an integrated antenna is used the RF termination is represented by the integrated antenna itself Use an antenna designed by an antenna manufacturer providing the best possible return loss or V S W R Provide a ground plane large enough according to the related integrated antenna requirements the ground plane of the application PCB can be reduced to a minimum size that must be similar to one quarter of wavelength of the minimum frequency that has to be radiated As numerical example Frequency 824 MHz gt Wavelength 36 4 cm gt Minimum GND plane size 9 1 cm It is highly recommended to strictly follow the detailed and specific guidelines provided by
22. 0 0 0 0 0 SARA G340 G350 series e e e e o o e e o o ee o o o SARA U2 series e e o o e o o e o o e o e o o o o o Table 61 Summary of SARA G3 and SARA U2 series modules interfaces UBX 13000995 R10 Early Production Information Appendix Page 184 of 192 biox B 2 Pin out comparison between SARA G3 and SARA U2 Pin No 20 22 23 24 SARA G3 Pin Name GND V_BCKP GND V_INT GND DSR RI DCD DTR RTS CTS TXD RXD GND PWR ON GPIO1 RSVD RSVD RESET N RSVD GND GPIO2 RSVD GPIO3 32K OUT UBX 13000995 R10 Description Ground RTC Supply I O Output characteristics 2 3 V typ 2 mA max Input op range 10V 24V Ground Interfaces Supply Out Output characteristics 1 8 V typ 50 mA max Ground RT DSR Output T RI Output V m V RT DCD Output V RT DTR Input V RT RTS Input RT CTS Output Data Input I 00 00 00 00 D 0 D o0 07 T Data Output oo Ground Power on Input No internal pull up L level 0 10 V 0 65 V H level 2 00 V 4 50 V ON L level time 5 ms min OFF L level pulse time Not Available 1 8 V GPIO Reserved Default Pin disabled Driver strength 6 mA Internal pull down 35 k Reserved Reset signal Internal diode amp pull up L level 0 30 V 0 30 V H level 2 00 V 4 70 V Reset L level pulse time Reserved Ground 1 8 V GPIO Reserved Default GNSS supply enable
23. 10 uF to decouple the bias present at the module input as described in the Figure 78 left side Guidelines for the connection to a single ended analog audio output A proper single ended to differential circuit has to be inserted from the single ended output of the external audio device to the MIC P MIC N balanced input of the module as described in the Figure 78 right side 10 pF series capacitors are provided to decouple the bias present at the module input and a voltage divider is provided to properly adapt the signal level from the external device output to the module input Additional guidelines for any connection The DC block series capacitor acts as high pass filter for audio signals with cut off frequency depending on both the values of capacitor and on the input impedance of the device For example in case of differential input impedance of 600 Q the two 10 uF capacitors will set the 3 dB cut off frequency to 53 Hz while for single ended connection to 600 Q external device the cut off frequency with just the single 10 uF capacitor will be 103 Hz In both cases the high pass filter has a low enough cut off for proper frequency response Use a suitable power on sequence to avoid audio bump due to charging of the capacitor the final audio stage should be always enabled as last one The signal levels can be adapted by setting gain using AT commands see u blox AT Commands Manual 3 USGC UMGC but additional circuitry must
24. 2 7 1 3 Guidelines for external analog audio device connection circuit design The differential analog audio I O can be used to connect the module to an external analog audio device Audio devices with a differential analog I O are preferable as they are more immune to external disturbances Figure 78 and Table 52 describe the application circuits following the suggested circuit design in Guidelines for the connection to a differential analog audio input The SPK P SPK N balanced output of the module must be connected to the differential input of the external audio device by means of series capacitors for DC blocking e g 10 pF to decouple the bias present at the module output as described in the left side of Figure 78 Guidelines for the connection to a single ended analog audio input A proper differential to single ended circuit must be inserted from the SPK_P SPK_N balanced output of the module to the single ended input of the external audio device as described in the Figure 78 right side 10 uF series capacitors are provided to decouple the bias present at the module output and a voltage divider is provided to properly adapt the signal level from module output to external audio device input Guidelines for the connection to a differential analog audio output The MIC P MIC N balanced input of the module must be connected to the differential output of the external audio device by means of series capacitors for DC blocking e g
25. AT amp K3 AT amp S1 AT amp D1 AT amp C1 MUX protocol disabled Comments AT command interface is enabled by default on the UART physical interface Automatic baud rate detection enabled by default on SARA G3 series One shot automatic baud rate detection enabled by default on SARA U2 series Automatic frame format recognition enabled by default on SARA G3 series One shot automatic frame format recognition enabled by default on SARA U2 series HW flow control enabled by default DSR line set ON in data mode and set OFF in command mode Upon an ON to OFF transition of DTR the DCE enters online command mode and issues an OK result code Circuit 109 changes in accordance with the Carrier detect status ON if the Carrier is detected OFF otherwise Multiplexing mode is disabled by default and it can be enabled by AT CMUX command The following virtual channels are defined Channel 0 control channel Channel 1 AT and Data Channel 2 AT and Data Channel 3 AT and Data not available on SARA G300 SARA G310 modules Channel 4 AT and Data not available on SARA G300 SARA G310 modules Channel 5 AT and Data not available on SARA G300 SARA G310 modules Channel 6 GNSS tunneling not available on SARA G300 SARA G310 modules Channel 7 SIM Access Profile not available on SARA G3 series modules Table 11 Default UART AT interface configuration Refer to the u blox AT Commands Manual 3 for the definition of the interf
26. How to use this Manual The SARA G3 and SARA U2 series System Integration Manual provides the necessary information to successfully design in and configure these u blox cellular modules This manual has a modular structure It is not necessary to read it from the beginning to the end The following symbols are used to highlight important information within the manual e An index finger points out key information pertaining to module integration and performance A A warning symbol indicates actions that could negatively impact or damage the module Questions If you have any questions about u blox cellular Integration Read this manual carefully Contact our information service on the homepage http Awww u blox com Technical Support Worldwide Web Our website www u blox com is a rich pool of information Product information and technical documents can be accessed 24h a day By E mail If you have technical problems or cannot find the required information in the provided documents contact the closest Technical Support office To ensure that we process your request as soon as possible use our service pool email addresses rather than personal staff email addresses Contact details are at the end of the document Helpful Information when Contacting Technical Support When contacting Technical Support have the following information ready Module type e g SARA G350 and firmware version Module configuration Clear description of your question
27. I2S sample rate parameter l S word alignment is set high for 1 or 2 clock cycles for the synchronization and then is set low for 16 clock cycles of sample width The frame length according to the length of the high pulse for the synchronization can be 1 16 17 bits or 2 16 18 bits S clock frequency depends on the frame length and the sample rate It can be 17 x I2S sample rate or 18 x I2S sample rate l S transmit and IS receive data are 16 bit words long with the same sampling rate as S word alignment mono Data is in 2 s complement notation MSB is transmitted first When PS word alignment toggles high the first synchronization bit is always low Second synchronization bit present only in case of 2 bit long l S word alignment configuration is MSB of the transmitted word MSB is transmitted twice in this case l S transmit data changes on l S clock rising edge l S receive data changes on I S clock falling edge 1 10 2 2 I S interface Normal I S mode Normal l S supports 16 bits word Mono interface Sample rate I2S sample rate parameter Main features of I S interface in normal IS mode configurable by AT UI2S command l S runs in normal I S long alignment mode l S word alignment signal always runs at the I2S sample rate and synchronizes 2 channels timeslots on word alignment high word alignment low l S transmit data is composed of 16 bit words dual mono the words are written on both
28. RXD RIS RTS CTS CTS DTR DTR DSR DSR RL RI DCD DCD GND GND 1 8V DTE TXD TXD AUX RXD RXD AUX GND GND KB s EB evo LUAM RSVD LS RSVD SIM DET fy SIM CLK SIM RST EIU 32K OUT Connector ant MEN rsvD a V_INT VSIM Ea SIM IO RSVD RSVD BR RSVD IJ EXT32K RsvD EN RsvD EIN rsv EIN RSVD EZ RsvD ZZ RsvD IN RSVD RSVD RSVD RSVD IP External Antenna SIM Card Holder CCVCC C1 CCVPP C6 CCIO C7 CCCLK C3 CCRST C2 GND C5 Figure 85 Example of schematic diagram to integrate SARA G300 G310 modules in an application board using all the interfaces UBX 13000995 R10 Early Production Information Design in Page 153 of 192 biox 2 15 2 Schematic for SARA G340 SARA G350 modules integration Figure 86 is an example of a schematic diagram where a SARA G340 SARA G350 module is integrated into an application board using all the available interfaces and functions of the module SARA G3 and SARA U2 series System Integration Manual SARA G340 SARA G350 3V8 vcc VCC eile lls VCC 330yF 100nF 10nF 56pF 15pF 2 GND V BCKP e EH v cx RTC back up T 100HF ME cv Application Processor 10
29. Rd GND Ml GND DIR2 Ul Figure 68 UART AUX interface application circuit connecting a 3 0 V application processor Reference Description Part Number Manufacturer C1 C2 100 nF Capacitor Ceramic X7R 0402 10 16 V GRM155R61A104KA01 Murata U1 Unidirectional Voltage Translator SN74AVC2T245 Texas Instruments Table 44 Component for UART AUX interface application circuit connecting a 3 0 V application processor See Firmware Update Application Note 25 for additional guidelines regarding the procedure for SARA G3 modules firmware upgrade over the auxiliary UART interface using the u blox EasyFlash tool er Any external signal connected to the auxiliary UART interface must be tri stated or set low when the module is in power down mode and during the module power on sequence at least until the activation of the V INT output to avoid latch up of circuits and allow a proper boot of the module If the external signals connected to the cellular module cannot be tri stated or set low insert a multi channel digital switch e g TI SN74CB3Q16244 TS5A3159 or TS5A63157 between the two circuit connections and set to high impedance during module power down mode and during the module power on sequence ESD sensitivity rating of auxiliary UART pins is 1 kV Human Body Model according to JESD22 A1 14 Higher protection level could be required if the lines are externally accessible on th
30. See the u blox AT Commands Manual 3 UPSV command UBX 13000995 R10 Early Production Information System description Page 29 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual 1 6 System function interfaces 1 6 1 Module power on 1 6 1 1 Switch on events Table 9 summarizes the possible switch on events for the SARA G3 and SARA U2 series modules SARA G3 SARA U2 From Applying valid VCC supply voltage i e VCC rise edge Applying valid VCC supply voltage i e VCC rise edge Not Powered Mode ramping from 2 5 V to 3 2 V within 4 ms ramping from 2 5 V to 3 2 V within 1 ms From Low level on PWR ON pin for 5 ms min Low pulse on PWR ON pin for 50 us min 80 us max Power orm Mode RTC alarm programmed by AT CALA command RTC alarm programmed by AT CALA command Not supported by SARA G300 SARA G310 RESET_N pin released from low level Table 9 Summary of SARA G3 and SARA U2 modules switch on events When the SARA G3 and SARA U2 series modules are in the not powered mode i e switched off with the VCC module supply not applied they can be switched on by Rising edge on the VCC supply input to a valid voltage for modules supply the modules switch on applying VCC supply starting from a voltage value lower than 2 25 V providing a fast VCC voltage slope as it must ramp from 2 5 V to 3 2 V within 4 ms on SARA G3 modules and within 1 ms on SARA U2 modules and reaching a proper nominal VCC voltage value within t
31. VCC VCCA VCCB 4o m V INT a c2 DIR1 TxD A1 B1 n o TXD RxD j a2 82 ag RXD DIR2 OE GND ui a DTR DSR RI DCD GND RTS crs fe Figure 66 UART interface application circuit with partial V 24 link 3 wire in DTE DCE serial communication 3 0 V DTE Reference Description Part Number Manufacturer C1 C2 100 nF Capacitor Ceramic X7R 0402 10 16 V GRM155R61A104KA01 Murata U1 Unidirectional Voltage Translator SN74AVC2T245 Texas Instruments Table 43 Component for UART application circuit with partial V 24 link 3 wire in DTE DCE serial communication 3 0 V DTE If only TXD and RXD lines are provided as described in Figure 65 or in Figure 66 and HW flow control is disabled AT amp KO the power saving must be enabled in this way AT UPSV 1 the module automatically enters the low power idle mode whenever possible and the UART interface is periodically enabled as described in section 1 9 1 4 reaching low current consumption With this configuration when the module is in idle mode the UART is re enabled 20 ms after the first data reception and the recognition of subsequent characters is guaranteed until the module is in active mode Se If only TXD and RXD lines are provided data delivered by the DTE can be lost with these settings o HW flow control enabled in the module AT amp K3 that is the default setting o Module power saving enabled by AT
32. Yageo Phycomp R2 4 7 kO Resistor 0402 596 0 1 W RC0402JR 074K7L Yageo Phycomp U1 LDO Linear Regulator ADJ 3 0 A LP38501ATJ ADJ NOPB Texas Instrument Table 24 Suggested components for VCC voltage supply application circuit using an LDO linear regulator 2 2 1 4 Guidelines for VCC supply circuit design using a rechargeable Li lon or Li Pol battery Rec hargeable Li lon or Li Pol batteries connected to the VCC pins should meet the following prerequisites to comply with the module VCC requirements summarized in Table 7 Maximum pulse and DC discharge current the rechargeable Li lon battery with its output circuit must be capable of delivering to VCC pins the specified maximum peak pulse current with 1 8 duty cycle and a DC current greater than the module maximum average current consumption refer to the SARA G3 series Data Sheet 1 or the SARA U2 series Data Sheet 2 The maximum pulse discharge current and the maximum DC discharge current are not always reported in battery data sheets but the maximum DC discharge current is typically almost equal to the battery capacity in Amp hours divided by 1 hour DC series resistance the rechargeable Li lon battery with its output circuit must be capable of avoiding a VCC voltage drop greater than 400 mV during transmit bursts 2 2 1 5 Guidelines for VCC supply circuit design using a primary disposable battery The characteristics of a primary non rechargeable battery connected to VCC pi
33. after 20 ms The UART wake up via data reception configuration is active in the following cases On SARA G3 series the TXD input line is configured to wake up the system via data reception if o AT UPSV 1 is set with HW flow control disabled o AT UPSV 2 is set with HW flow control disabled and the RTS line is set OFF On SARA U2 series the TXD input line is configured to wake up the system via data reception only if o AT UPSV 1 is set with hardware flow control disabled ee On SARA U2 series the UART wake up via data reception configuration is not active on the TXD input and therefore all the data sent by the DTE is lost if o AT UPSV 2 is set with HW flow control disabled and the RTS line is set OFF o AT UPSV 3 is set regardless HW flow control setting and the DTR line is set OFF Figure 26 and Figure 27 show examples of common scenarios and timing constraints AT UPSV 1 power saving configuration is active and the timeout from last data received to idle mode start is set to 2000 frames AT UPSV 1 2000 Hardware flow control is disabled Figure 26 shows the case where the module UART is disabled and only a wake up is forced In this scenario the only character sent by the DTE is the wake up character as a consequence the DCE module UART is disabled when the timeout from last data received expires 2000 frames without data reception as the default case UART Sa i I I f DCE UART is enabled for 2000 GSM frames 9 2 s l
34. for AT UTEST command user guide limitations and examples of use UBX 13000995 R10 Early Production Information Product testing Page 169 of 192 bb Qo Ox SARA G3 and SARA U2 series System Integration Manual Wireless Wideband Antenna Antenna Application SARA G3 Processor AT SARA U2 Spectrum Commands gt Analyzer lt lt _ gt TX or Power Meter Application Board Wireless Wideband Antenna Antenna Application SARA G3 Processor AT SARA U2 g Commands Signal RX Generator Application Board Figure 90 Setup with spectrum analyzer and signal generator for radiated measurement This feature allows the measurement of the transmitter and receiver power levels to check component assembly related to the module antenna interface and to check other device interfaces from which depends the RF performance To avoid module damage during transmitter test a proper antenna according to module specifications or a 50 Q termination must be connected to ANT pin To avoid module damage during receiver test the maximum power level received at ANT pin must meet module specifications Se The AT UTEST command sets the module to emit RF power ignoring the 2G 3G signalling protocol This emission can generate interference that can be prohibited by law in some countries The use of this feature is intended for testing purpose in controlled env
35. 074K7L Yageo Phycomp C2 70 mF Capacitor XH414H IVO1E Seiko Instruments Table 28 Example of components for V_BCKP buffering If longer buffering time is required to allow the RTC time reference to run during a disconnection of the VCC supply then an external battery can be connected to V_BCKP pin The battery should be able to provide a proper nominal voltage and must never exceed the maximum operating voltage for V_BCKP specified in the Input characteristics of Supply Power pins table in the SARA G3 series Data Sheet 1 or in the SARA U2 series Data Sheet 2 The connection of the battery to V_BCKP should be done with a suitable series resistor for a rechargeable battery or with an appropriate series diode for a non rechargeable battery The purpose of the series resistor is to limit the battery charging current due to the battery specifications and also to allow a fast rise time of the voltage value at the V_BCKP pin after the VCC supply has been provided The purpose of the series diode is to avoid a current flow from the module V_BCKP pin to the non rechargeable battery Se If the RTC timing is not required when the VCC supply is removed it is not needed to connect the V_BCKP pin to an external capacitor or battery In this case the date and time are not updated when VCC UBX 13000995 R10 Early Production Information Design in Page 95 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual is disconnected If VCC is
36. 154 ms width of the 2 Tx slots bursts in case of multi slot class 10 or for 2 308 ms width of the 4 Tx slots bursts in case of multi slot class 12 with a periodicity of 4 615 ms width of 1 frame 8 slots bursts so with a 1 4 or 1 2 duty cycle according to GSM TDMA If the module is in GPRS connected mode in 1800 or 1900 MHz bands consumption figures are lower than in the 850 or 900 MHz band due to 3GPP Tx power specifications Figure 8 reports the current consumption profiles in GPRS connected mode in the 850 or 900 MHz bands with 2 slots used to transmit and 1 slot used to receive as for the GPRS multi slot class 10 Current A Peak current depends on TX power and actual antenna load GSM frame GSM frame 4 Ht _ _ 4 615 ms 4 615 ms 1 frame 8 slots 1 frame 8 slots Figure 8 VCC current consumption profile versus time during a GPRS multi slot class 10 connection 2 TX slots 1 RX slot Figure 9 reports the current consumption profiles in GPRS connected mode in the 850 or 900 MHz bands with 4 slots used to transmit and 1 slot used to receive as for the GPRS multi slot class 12 Current A Peak current depends on TX power and actual antenna load 0 5 Time ms GSM frame GSM frame 4 pe 4 615 ms 4 615 ms 1 frame 8 slots 1 frame 8 slots Fig
37. 2 14 3 Guidelines for antenna RF interface design 152 2 15 Schematic for SARA G3 and SARA U2 series module integration sssssssssssess 153 2 15 1 Schematic for SARA G300 SARA G310 modules integration sss 153 2 15 2 Schematic for SARA G340 SARA G350 modules integration sse 154 2 15 3 Schematic for SARA U2 series modules integration ssssssssseeee s 155 2 16 pI3eulspeeedjmee t ER 156 2 16 1 Schematic enecklist orna te ent e adult the ride Rep geese Lease dede 156 2 16 2 Layout checklist ssssssssssssssssseseneeeeenee eee enne en nnne nnne rere nnn nene 157 2 16 3 Antenna checklist Eb Rete netus ERE Re Mene SR RS ERR RO 157 3 Handling and soldering ioi t en E EcKEEXY IS exe EDO EAS IE cX EUIS cre PUY IEEE XC NE Or EDU GRE 158 3 1 Packaging shipping storage and moisture preconditioning ssssssssse eee 158 SPEM oe e E E 158 3 3 Solderitig iit en EA EE TEE ee A E eee eee 159 3 3 1 SOIGSKING PASTE sa iccss 159 3 3 2 Reflow solderlng tone plan erae tatto item dena ritu uda bitten is 159 3 323 OPUGANMS DOCU OM E eT 160 SP MER Mt 160 3 3 5 Repeated reflow SolderiNg isnin iann Ea eene ener enn nns 161 3 36 Wave Sold auc we 161 3 3 7 aee M 161 BBS REWOG cei enr Eti a eee ee ee 161 3 3 8 Conformal coating
38. 698 960 MHz 1575 42 MHz 1710 2170 MHz 2490 2690 MHz 105 x 30x 7 7 mm GSM WCDMA low profile adhesive mount Antenna with cable and Fakra code D connector 824 960 MHz 1710 2170 MHz 106 7 x 14 7 x 5 8 mm GSM WCDMA LTE swivel dipole Antenna with SMA M connector 698 960 MHz 1575 42 MHz 1710 2170 MHz 2400 2700 MHz 148 6 x 49 x 10 mm GSM WCDMA pole mount Antenna with N type F connector 824 960 MHz 1710 2170 MHz 527 x 26 mm GSM WCDMA whip monopole Antenna with RP N type M connector 824 960 MHz 1710 2170 MHz 274 x 20 mm GSM WCDMA swivel monopole Antenna with SMA M connector 824 960 MHz 1710 2170 MHz 179 3 x 22x 6 5 mm GSM WCDMA swivel monopole Antenna with SMA M connector 824 960 MHz 1575 42 MHz 1710 2170 MHz 2400 2500 MHz 161 x 9 3 mm GSM WCDMA screw mount Antenna with N type F connector 824 960 MHz 1710 2170 MHz 69 8 x 38 1 mm GSM WCDMA LTE ceiling mount Antenna with N type F connector 698 960 MHz 1575 42 MHz 1710 2700 MHz 86 x 199 mm GSM WCDMA LTE pole mount Antenna with N type M connector 698 960 MHz 1710 2690 MHz 248 x 24 5 mm GSM WCDMA low profile adhesive mount Antenna with cable and SMA M connector 824 960 MHz 1710 2170 MHz 138x21x6 mm Early Production Information Design in Page 108 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual 2 4 2 Antenna detection in
39. 80 Application circuit for connecting SARA G3 SARA U2 modules with an external audio codec UBX 13000995 R10 Early Production Information Design in Page 140 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual As in general any external digital audio device compliant to the configuration of the digital audio interface of the cellular module can be used various external audio codecs other than the one described in Figure 79 Figure 80 and Table 53 can be used to provide voice capability For example the Maxim MAX9867 audio codec or the Maxim MAX9880A audio codec can be used instead of the Maxim MAX9860 audio codec described above implementing and configuring an appropriate application circuit according to the specific device and application requirements er E Any external signal connected to the digital audio interface must be tri stated or set low when the module is in power down mode and during the module power on sequence at least until the activation of the V_INT supply output of the module to avoid latch up of circuits and allow a proper boot of the module If the external signals connected to the cellular module cannot be tri stated or set low insert a multi channel digital switch e g Texas Instruments SN74CB3Q16244 TS5A3159 or TS5A63157 between the two circuit connections and set to high impedance during module power down mode and during the module power on sequence ESD sensitivity rating of lS int
40. ANA gp E U Duplexer gt Transceiver PERL Filter 3G PA a SIM card detection i E UART Cellular BaseBand USB Processor Memory i DDC I2C eee Digital audio I2S V BCKP RTC Power GPIO i Managemen V INT I O gement Antenna detection Figure 3 SARA U260 and SARA U270 modules block diagram 32 768 kHz Power On ANT Reset SIM 1 1 SIM card detection UART Cellular BaseBand USB i Processor Memory PE i DDC I2O VCC Supply Digital audio 12S V_BCKP RTC Power GPIO Man men V INT I O anagement Antenna detection Figure 4 SARA U280 and SARA U290 modules block diagram UBX 13000995 R10 Early Production Information System description Page 11 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 2 1 Internal blocks SARA G3 and SARA U2 series modules internally consist of the RF Baseband and Power Management sections here described with more details than the simplified block diagrams of Figure 1 Figure 2 Figure 3 and Figure 4 RF section The RF section is composed of the following main elements 2G 3G RF transceiver performing modulation up conversion of the baseband l Q signals down conversion and demodulation of the RF received signals The RF transceiver includes Constant gain direct conversion receiver with integrated LNAs Highly linear RF quadrature GMSK demodulator Digital Sigma Delta tr
41. AT command the module reports the resistance value evaluated from the antenna connector provided on the application board to GND Reported values close to the used diagnostic resistor nominal value i e values from 13 kQ to 17 kQ if a 15 kQ diagnostic resistor is used indicate that the antenna is properly connected Values close to the measurement range maximum limit approximately 50 kQ or an open circuit over range report see u blox AT Commands Manual 3 means that that the antenna is not connected or the RF cable is broken Reported values below the measurement range minimum limit 1 KQ highlights a short to GND at antenna or along the RF cable Measurement inside the valid measurement range and outside the expected range may indicate an improper connection damaged antenna or wrong value of antenna load resistor for diagnostic Reported value could differ from the real resistance value of the diagnostic resistor mounted inside the antenna assembly due to antenna cable length antenna cable capacity and the used measurement method Se If the antenna detection function is not required by the customer application the ANT_DET pin can be left not connected and the ANT pin can be directly connected to the antenna connector by means of a 50 Q transmission line as described in Figure 52 UBX 13000995 R10 Early Production Information Design in Page 110 of 192 VP biox SARA G3 and SARA U2 series System Integration Manual 2 4 2 1 G
42. Aa eles fuae due sete ts 68 1 159 2 JAMMING detectlOD cio Cbr rt egere test po aba eigen eee 68 UBX 13000995 R10 Early Production Information Contents Page 4 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual 1 13 4 EIC uU LEEEEEEEEEEMEMEMMMMMMMMMMMMUMMMMM 69 DVS co JRTP E 69 De MiGs ATIR T 69 PWS SMP casts enira ER DA e autein ND C m aA RM E IDEM 69 IN GTC ME ASS D M 70 12 95 3D al Stack IPVAVIPUO oret edet Pte a ote needs etree oles teint ML EUR dep any tte 71 1 13 10 Smart temperature Management sidus seta dies nacre bere neues ve hne turo e Ee bn sea ia Rx S scu 72 1 13 11 AssistNow clients and GNSS integration sssssssssssseee eene 75 1 13 12 Hybrid positioning and Cellbocate 5 e esse tiacntratksn ntt tana g iR rena e pna sog dran cR Mdb auadaS 75 1 13 13 Firmware upgrade Over AT FOAT sssssseeee em eene nre nnne nne nnns 78 1 13 14 Firmware upgrade Over The Air FOTA scsssssssseeme ene nemen 78 1 13 15 In Band modem eCall ERA GLONASS ssssssee eee eene eene eres eren ener terrse niis 79 1 13 16 SIM Access Profile SAP eeneeeemeeneemenen eene eren nr esser ener nnne elis 79 T E3 7 SPOWBISaVIDIO oi ee de ede d eR LEN MEM UE 81 2 DGSIONHIN Mee 82 2 1 e e
43. Coating of the module will void the warranty 3 3 10 Casting If casting is required use viscose or another type of silicon pottant The OEM is strongly advised to qualify such processes in combination with the SARA G3 and SARA U2 series modules before implementing this in the production e Casting will void the warranty 3 3 11 Grounding metal covers Attempts to improve grounding by soldering ground cables wick or other forms of metal strips directly onto the EMI covers is done at the customer s own risk The numerous ground pins should be sufficient to provide optimum immunity to interferences and noise Se u blox gives no warranty for damages to the SARA G3 and SARA U2 series modules caused by soldering metal cables or any other forms of metal strips directly onto the EMI covers 3 3 12 Use of ultrasonic processes SARA G3 and SARA U2 series modules contain components which are sensitive to Ultrasonic Waves Use of any Ultrasonic Processes cleaning welding etc may cause damage to the module ee u blox gives no warranty against damages to the SARA G3 and SARA U2 series modules caused by any Ultrasonic Processes UBX 13000995 R10 Early Production Information Handling and soldering Page 161 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 4 Approvals Se For the complete list of all the certification schemes approvals of SARA G3 and SARA U2 series modules and the corresponding declarations of conformit
44. DTR signal behavior The DTR module input line is set by default to the OFF state high level at UART initialization The module then holds the DTR line in the OFF state if the line is not activated by the DTE an active pull up is enabled inside the module on the DTR input Module behavior according to DTR status can be changed by AT command for more details see u blox AT Commands Manual 3 AT amp D command description If AT UPSV 3 is set the DTR line is monitored by the module to manage the power saving configuration When an OFF to ON transition occurs on the DTR input line the UART is enabled and the module wakes up to active mode after 20 ms from the OFF to ON transition the UART module wake up is completed and data can be received without loss The module cannot enter the low power idle mode and the UART is kept enabled as long as the DTR input line is held in the ON state If the DTR input line is set to the OFF state by the DTE the UART is disabled held in low power mode and the module automatically enters low power idle mode whenever possible For more details see section 1 9 1 4 and u blox AT Commands Manual 3 AT UPSV command er AT UPSV 3 power saving configuration control by the DTR input is not supported by SARA G3 modules UBX 13000995 R10 Early Production Information System description Page 43 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual DCD signal behavior If AT amp C1 is se
45. Driver strength 4 mA nner pull down 30 pA 1 8 V configurable GPIO Default Pin disabled Driver strength 4 mA nner pull down 30 pA 1 8 V configurable GPIO Default Pin disabled Driver strength 4 mA Inner pull down 30 pA Not Available Not Available Not Available Not Available Not Available Not Available Not Available Early Production Information LISA U1 series Not Available 1 8 V configurable GPIO Default Pin disabled Driver strength 1 mA Inner pull down 100 pA 1 8 V configurable GPIO Default GNSS supply en Driver strength 1 mA nner pull down 85 pA 1 8 V configurable GPIO Default GNSS data ready Driver strength 4 mA nner pull down 55 pA 1 8 V configurable GPIO Default GNSS RTC sharing 4 7 k external pull down required for RTC sharing Driver strength 4 mA Inner pull down 55 pA 1 8 V configurable GPIO Default SIM detection Driver strength 2 5 mA Inner pull down 55 pA Not Available Not Available Not Available Not Available Not Available Not Available Not Available LISA U2 series 1 8 V 13 26 MHz Out Driver strength 4 mA LISA U200 00S N A 1 8 V configurable GPIO Default Pin disabled Driver strength 6 mA Inner pull down 200 pA 1 8 V configurable GPIO Default GNSS supply en Driver strength 1 mA Inner pull down 150 pA 1 8 V configurable GPIO Default GNSS data ready Driver strength 6 mA Inner pull down 200 pA
46. Driver strength 6 mA Internal pull down 35 k 1 8 V GPIO 32 kHz Output Default GNSS data ready Driver strength 5 mA Inner pull down 67 k Driver strength 6 mA Driver strength 6 mA Driver strength 6 mA Internal pull up 33k V Internal pull up 58 k V Driver strength 6 mA RI V Internal pull up 18 k RI V Driver strength 6 mA 50 ms min SARA G350 G340 3 s min SARA G300 G310 SARA G3 and SARA U2 series System Integration Manual SARA U2 Pin Name GND V BCKP GND V INT GND DSR RI DCD DTR RTS CTS TXD RXD GND PWR ON GPIO1 VUSB DET RESET N CODEC CLK GND GPIO2 GPIO3 Description Ground RTC Supply O Output characteristics 1 8 V typ 3 mA max Input op range 1 0V 1 9V Ground Interfaces Supply Out Output characteristics 8 V typ 50 mA max Ground UART DSR Output UART RI Output UART DCD Output UART DTR Input UART RTS Input UART CTS Output UART Data Input UART Data Output Ground Power on Input No internal pull up L level 0 30 V 0 65 V H level 1 50 V 4 40 V ON L level pulse time 50 us min 80 us max OFF L level pulse time 1s min 1 8 V GPIO Default Pin disabled Driver strength 6 mA Internal pull down 9 k USB Detect Input 5 V Supply detection Reset signal 10 kQ internal pull up L level 0 30 V 0 51 V H level 1 32 V 2 01 V Reset L level pulse time 50 ms min 13 or 26
47. ETSI EN 301 489 1 19 as the physical boundary through which the electromagnetic field radiates If the device implements an integral antenna the enclosure port is defined as all insulating and conductive surfaces housing the device If the device implements a removable antenna the antenna port can be separated from the enclosure port The antenna port includes the antenna element and its interconnecting cable surfaces The applicability of the ESD immunity test to the whole device depends on the device classification as defined by ETSI EN 301 489 1 19 Applicability of the ESD immunity test to the relative device ports or the relative interconnecting cables to auxiliary equipments depends on device accessible interfaces and manufacturer requirements as defined by ETSI EN 301 489 1 19 Contact discharges are performed at conductive surfaces while air discharges are performed at insulating surfaces Indirect contact discharges are performed on the measurement setup horizontal and vertical coupling planes as defined in CENELEC EN 61000 4 2 18 Se For the definition of integral antenna removable antenna antenna port device classification see ETSI EN 301 489 1 19 whereas for contact and air discharges definitions see CENELEC EN 61000 4 2 18 Application Category Immunity Level All exposed surfaces of the radio equipment and ancillary equipment ina Contact Discharge 4 kV representative configuration n Air Discharge 8 kV Table 56 E
48. Each downlink path mode defines the physical output i e the analog or the digital audio output and the set of parameters to process the downlink audio signal downlink gains downlink digital filters and sidetone For example the Mono headset downlink path uses the differential analog audio output with the default parameters for the headset profile The set of parameters to process the uplink or the downlink audio signal can be changed with dedicated AT commands for each uplink or downlink path and then stored in two profiles in the non volatile memory refer to u blox AT Commands Manual 3 for Audio parameters tuning commands 1 10 1 Analog audio interface ee SARA U2 modules do not provide analog audio interface 1 10 1 1 Uplink path SARA G340 SARA G350 pins related to the analog audio uplink path are MIC P MIC_N Differential analog audio signal inputs positive negative These two pins are internally directly connected to the differential input of an integrated Low Noise Amplifier without any internal series capacitor for DC blocking The LNA output is internally connected to the digital processing system by an integrated sigma delta analog to digital converter MIC BIAS Supply output for an external microphone The pin is internally connected to the output of a low noise LDO linear regulator provided with proper internal bypass capacitor to guarantee stable operation of the linear regulator MIC GND Local ground for the ex
49. Figure 17 PWR_ON input description The SARA G340 SARA G350 and SARA U2 series can be also switched on from power off mode by RTC alarm pre programmed by AT CALA command at specific time see u blox AT Commands Manual 3 The SARA U2 series modules can be also switched on from power off mode by Low pulse on the RESET N pin which is normally set high by an internal pull up refer to section 1 6 3 and to the SARA U2 series Data Sheet 2 for the description of the RESET N input electrical characteristics UBX 13000995 R10 Early Production Information System description Page 30 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 6 1 2 Switch on sequence from not powered mode Figure 18 shows the modules power on sequence from the not powered mode describing the following phases e e Digital Pins State The external supply is applied to the VCC module supply inputs representing the start up event The status of the PWR ON input pin while applying the VCC module supply is not relevant during this phase the PWR ON pin can be set high or low by the external circuit but in Figure 18 it is assumed that the PWR ON line rise suddenly to high logic level due to external pull up connected to V BCKP or VCC The V BCKP RTC supply output is suddenly enabled by the module as VCC reaches a valid voltage value The RESET N line of SARA U2 series rise suddenly to high logic level due to internal pull up to V BCKP All
50. GSM 900 MHz DCS 1800 MHz PCS 1900 MHz Class 4 33 dBm for 850 900 bands Class 1 30 dBm for 1800 1900 bands GPRS multi slot class 10 CS 1 4 85 6 kb s DL CS 1 4 42 8 kb s UL Up to 9 6 kb s DL UL Transparent mode Non transparent mode SARA U290 3GPP Release 7 Class A Band VIII 900 MHz Band 2100 MHz Class 3 24 dBm for all bands HSUPA category 6 5 76 Mb s UL HSDPA category 8 7 2 Mb s DL Up to 64 kb s DL UL Device can be attached to both GPRS and GSM services i e Packet Switch and Circuit Switch mode using one service at a time The 2G 850 1900 MHz and 3G 850 1900 MHz bands are mainly operative in America The 2G 900 1800 MHz and 3G 900 2100 MHz bands are mainly operative in Europe Asia and other countries The maximum bit rate of the module depends on the actual network environmental conditions and settings GPRS EDGE multi slot class 12 implies a maximum of 4 slots in DL reception and 4 slots in UL transmission with 5 slots in total GPRS multi slot class 10 implies a maximum of 4 slots in DL reception and 2 slots in UL transmission with 5 slots in total Device can work simultaneously in Packet Switch and Circuit Switch mode voice calls are possible while the data connection is active without any interruption in service UBX 13000995 R10 Early Production Information System description Page 9 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manua
51. I2S_CLK I2S_RXD SIM_CLK SIM IO SIM RST VSIM SIM DET GND RSVD RSVD RSVD RSVD RSVD RSVD GND VCC GND ANT GND ANT_DET GND Description 1 8 V GPIO Default GNSS RTC sharing Driver strength 6 mA nternal pull down 9 k C Data I O 1 8 V open drain Driver strength 1 mA C Clock Output 1 8 V open drain Driver strength 1 mA USB Data I O D High Speed USB 2 0 USB Data I O D High Speed USB 2 0 Ground Reserved Ground Reserved PS Word Alignment 1 8 V Driver strength 2 mA PS Data Output 1 8 V Driver strength 2 mA PS Clock 1 8 V Driver strength 2 mA PS Data Input 1 8 V Inner pull down 9 k SIM Clock Output SIM Data l O SIM Reset Output SIM Supply Output SIM Detection Input 1 8 V Inner pull down 9 k Ground Reserved Reserved Reserved Reserved Reserved Reserved Ground Module Supply Input Normal op range 3 3V 44V Extended op range 3 1V 45V Ground RF Antenna I O ESD immunity IEC 61000 4 2 2 kV contact 4 kV air ESD Ground Antenna Detection Input Ground Table 62 SARA G3 and SARA U2 pin assignment with remarks for migration For the detailed functional description of each interface of SARA G3 and SARA U2 series modules see the Remarks for migration No functional difference No functional difference o functional difference USB instead of Auxiliary UART USB instead of Auxiliary UART o functional difference o func
52. II subdivision RF threshold power limits according to the IEC 60079 0 ATEX standard IIA a typical gas is propane 6 0 W IIB a typical gas is ethylene 3 5W IIC a typical gas is hydrogen 2 0 W Table 58 RF threshold power limits for the different gas group II subdivisions according to the IEC 60079 0 ATEX standard 32 e The system antenna s implemented used on the application device for SARA G350 ATEX modules must be designed selected so that the antenna gain i e the combined transmission line connector cable losses and radiating element gain multiplied by the output power of the transmitter SARA G350 ATEX module does not exceed the limits shown in Table 58 UBX 13000995 R10 Early Production Information Design in Page 152 of 192 biox 2 15 Schematic for SARA G3 and SARA U2 series module integration SARA G3 and SARA U2 series System Integration Manual 2 15 1 Schematic for SARA G300 SARA G310 modules integration Figure 85 is an example of a schematic diagram where a SARA G300 SARA G310 module is integrated into an application board using all the available interfaces and functions of the module SARA G300 SARA G310 T vcc vcc vcc 330pF 100nF 10nF S6pF 15PF GND V BCKP eo Eeer RTC jl back up T 100HF MEE co Application Processor 100kQ TP PWR ON Open Drain Output e E RESET_N Open a Drain Output 1 8V DTE TXD TXD RXD
53. Inductor 0402 SRF 1 GHz LQG15HN39NJO2 Murata SARA G3 Do not install C4 22 pF Capacitor Ceramic COG 0402 596 25 V GRM1555C1H220 Murata L3 68 nH Multilayer Inductor 0402 SRF 1 GHz LQG15HS68NJO2 Murata R2 15 kQ Resistor for Diagnostic Various Manufacturers Table 35 Suggested components for antenna detection circuit on application board and diagnostic circuit on antenna assembly The antenna detection circuit and diagnostic circuit suggested in Figure 53 and Table 35 are here explained When antenna detection is forced by the UANTR AT command the ANT_DET pin generates a DC current measuring the resistance R2 from the antenna connector J1 provided on the application board to GND DC blocking capacitors are needed at the ANT pin C2 and at the antenna radiating element C3 to decouple the DC current generated by the ANT DET pin Choke inductors with a Self Resonance Frequency SRF in the range of 1 GHz are needed in series at the ANT DET pin L1 and in series at the diagnostic resistor L2 to avoid a reduction of the RF performance of the system improving the RF isolation of the load resistor Additional components R1 C1 and D1 in Figure 53 are needed at the ANT DET pin as ESD protection UBX 13000995 R10 Early Production Information Design in Page 109 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Additional high pass filter C3 and L2 in Figure 53 is provided at the ANT pin as ESD
54. Institute ANSI In addition to standard ESD safety practices the following measures should be taken into account whenever handling the SARA G3 and SARA U2 series modules Unless there is a galvanic coupling between the local GND i e the work table and the PCB GND then the first point of contact when handling the PCB must always be between the local GND and PCB GND Before mounting an antenna patch connect ground of the device When handling the module do not come into contact with any charged capacitors and be careful when contacting materials that can develop charges e g patch antenna coax cable soldering iron To prevent electrostatic discharge through the RF pin do not touch any exposed antenna area If there is any risk that such exposed antenna area is touched in non ESD protected work area implement proper ESD protection measures in the design When soldering the module and patch antennas to the RF pin make sure to use an ESD safe soldering iron For more robust designs employ additional ESD protection measures on the application device integrating the SARA G3 and SARA U2 series modules as described in section 2 13 3 UBX 13000995 R10 Early Production Information Handling and soldering Page 158 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 3 3 Soldering 3 3 1 Soldering paste Use of No Clean soldering paste is strongly recommended as it does not require cleaning after the solderi
55. Level Remarks Contact Discharge Enclosure 4 kV A kV to coupling planes indirect contact discharge Contact Discharges Enclosure port Not Applicable Test not applicable to u blox reference design because it to conducted surfaces does not provide enclosure surface direct contact discharge The test is applicable only to equipments providing conductive enclosure surface Antenna port 4 kV A kV Test applicable to u blox reference design because it provides antenna with conductive amp insulating surfaces The test is applicable only to equipments providing antenna with conductive surface Air Discharge Enclosure port Not Applicable Test not applicable to the u blox reference design at insulating surfaces because it does not provide an enclosure surface The test is applicable only to equipments providing insulating enclosure surface Antenna port 8 kV 8 kV Test applicable to u blox reference design because it provides antenna with conductive amp insulating surfaces The test is applicable only to equipments providing antenna with insulating surface Table 57 Enclosure ESD immunity level of u blox SARA G3 and SARA U2 reference designs ee SARA G3 and SARA U2 reference designs implement all the ESD precautions described in section 2 13 3 2 13 3 ESD application circuits The application circuits described in this section are recommended and should be implemented in any device that integrates a SARA G3 and SARA U2 serie
56. MHz Output Driver strength 4 mA Ground 1 8 V GPIO Driver strength 1 mA 1 8 V GPIO Driver strength 6 mA nternal pull down 9 k Early Production Information 8 V Driver strength 1 mA 8 V Driver strength 2 mA 8 V Driver strength 2 mA 8 V Internal pull up 14 k 8 V Internal pull up 8 k 8 V Driver strength 6 mA 8 V Internal pull up 8 k 8 V Driver strength 6 mA Default GNSS supply enable nternal pull down 14 k Default GNSS data ready Remarks for migration No functional difference No functional difference No functional difference No functional difference No functional difference No functional difference No functional difference No functional difference No functional difference No functional difference No functional difference No functional difference USB detection instead of Reserved No functional difference Clock output instead of Reserved No functional difference No functional difference Appendix Page 185 of 192 biox Pin No 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 53 54 55 56 57 61 62 63 96 SARA G3 Pin Name GPIO4 RSVD SDA RSVD SCL RSVD RXD_AUX TXD_AUX GND RSVD EXT32K GND RSVD I2S_WA RSVD I2S_TXD RSVD 125 CLK RSVD 125 RXD RSVD SIM CLK SIM IO SIM RST VSIM SIM DET GND SPK P RSVD SPK N RS
57. Manual The supply of the u blox 1 8 V GNSS receiver can be switched off using an external p channel MOSFET controlled by the GPIO2 pin by means of a proper inverting transistor as shown in Figure 73 implementing the GNSS supply enable function If this feature is not required the V INT supply output can be directly connected to the u blox 1 8 V GNSS receiver so that it will be switched on when V_INT output is enabled The V_INT supply output provides low voltage ripple up to 15 mVpp when the module is in active mode or in connected mode but it provides higher voltage ripple up to 90 mVpp on SARA G3 series or up to 70 mVpp on SARA U2 series when the module is in the low power idle mode with power saving configuration enabled by the AT UPSV see u blox AT Commands Manual 3 According to the voltage ripple characteristic of the V INT supply output The power saving configuration cannot be enabled to use V INT output to properly supply any 1 8 V GNSS receiver of the u blox 6 generation and any 1 8 V GNSS receiver of the u blox 7 generation or any newer u blox GNSS receiver generation with TCXO The power saving configuration can be enabled to use V INT output to properly supply any 1 8 V GNSS receiver of the u blox 7 generation or any newer u blox GNSS receiver generation without TCXO Additional filtering may be needed to properly supply an external LNA depending on the characteristics of the used LNA adding a series ferrite bead and a bypa
58. Over The Air FOTA ee Not supported by SARA G300 and SARA G310 modules and SARA U2 series a Supported upon request on SARA G340 and SARA G350 modules This feature allows upgrading the module firmware over the air i e over the cellular network The main idea with updating firmware over the air is to reduce the amount of data required for transmission to the module This is achieved by downloading only a delta file instead of the full firmware The delta contains only the differences between the two firmware versions old and new and is compressed For more details see the Firmware Update Application Note 25 UBX 13000995 R10 Early Production Information System description Page 78 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 13 15 In Band modem eCall ERA GLONASS ee Not supported by SARA G300 SARA G310 SARA U260 SARA U280 modules SARA G340 SARA G350 and SARA U2 modules support an In Band modem solution for the European eCall and the Russian ERA GLONASS emergency call applications over cellular networks implemented according to 3GPP TS 26 267 22 BS EN 16062 2011 30 and ETSI TS 122 101 31 specifications eCall European and ERA GLONASS Russian are initiatives to combine mobile communications and satellite positioning to provide rapid assistance to motorists in the event of a collision The eCall automated emergency response system is based on GPS and the ERA GLONASS is based on t
59. PWR ON KE EJ smio PwRoN EH EJ smo PWR ON KE EJ smo RSVD EG EJ 5v cx GPIO1 EIN EJ 5v cx GPIO1 KT EJ sw ck RSVD Ba Ee RSVD RSVD Ba I Ee I2S RXD VUSB DET Ee j E I2S RXD Pin 65 96 GND Pin 65 96 GND Pin 65 96 GND RESET N EN EJ Rsvp RESET_N ET EJ 5 cx RESET N REJ EJ 75 cx RSVD EE El El El El EJ Rsvp RSVD EE El El El El EJ os1xp coprec ax KB E E El El EJ 5 1x GND ETN jor mn Bi m a a EJ Rsvp GND ET m mn Ee m a a EJ 2s wA GND ETN 2 n n n n EJ 02s w GND EIN EB Rsvp GND Ei EJ Rsvp GND Ei EJ Rsvp elkeet vkb tekki ekk kkkt aOnortoanoaoxxaxa OQOwamutauxxaaoon anmsaegpqgare aaa 6n8aubspasa p 229g97228268 See eas sas Lg eee E 000 aa Uo ag Gd 8 ED ER 55 Figure 94 SARA G3 and SARA U2 series modules pin layout and pin assignment Table 61 summarizes the interfaces provided by SARA G3 and SARA U2 series modules all the interfaces provided by different modules are electrically compatible so that the same compatible external circuit can be implemented on the application board Modules Power Antenna System SIM Serial Audio Other t 4a 9 gt a 2 S 9 5 50290 HP mm z x oca 2288 oo00902575 eu 2 Z a 3 So c aS JF amp Ua 2is 5 lt Q do Ss pets 2554 SX Se Ze SEE O wT ni A cas BY Faal Ple e SE o E X B 3m E O 0 y a D x o O a Puola c 82 pS z sla a amna aaa E 9 o tc z oo oo oo o co eo zZz zZ zZ S k 2 3 ale Aal ale ee 5 Slee ele 2 Oo oS SARA G300 G310 series e e e GO O 9
60. SARA G3 and SARA U2 series System Integration Manual o cet appareil doit accepter toute interf rence notamment les interf rences qui peuvent affecter son fonctionnement Informations concernant l exposition aux fr quences radio RF La puissance de sortie mise par l appareil de sans fil u blox Cellular Module est inf rieure la limite d exposition aux fr quences radio d Industrie Canada IC Utilisez l appareil de sans fil u blox Cellular Module de facon minimiser les contacts humains lors du fonctionnement normal Ce p riph rique a t valu et d montr conforme aux limites d exposition aux fr quences radio RF d IC lorsqu il est install dans des produits h tes particuliers qui fonctionnent dans des conditions d exposition des appareils mobiles les antennes se situent plus de 20 centim tres du corps d une personne Ce p riph rique est homologu pour l utilisation au Canada Pour consulter l entr e correspondant l appareil dans la liste d quipement radio REL Radio Equipment List d Industrie Canada rendez vous sur http www ic gc ca app sitt reltel srch nwRdSrch do lang fra Pour des informations suppl mentaires concernant l exposition aux RF au Canada rendez vous sur http www ic gc ca eic site smt gst nsf eng sf08792 html IMPORTANT les fabricants d applications portables contenant les modules SARA G310 SARA G350 SARA U260 SARA U280 doivent faire certifier leur produit final et d po
61. Table 23 Suggested components for VCC voltage supply application circuit using an LDO linear regulator Figure 39 and the components listed in Table 24 show an example of a low cost power supply circuit where the VCC module supply is provided by an LDO linear regulator capable of delivering the specified highest peak pulse current with proper power handling capability The regulator described in this example supports a limited input voltage range and it includes internal circuitry for current and thermal protection It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly below the maximum limit of the module VCC normal operating range e g 4 1 V as in the circuit described in Figure 39 and Table 24 This reduces the power on the linear regulator and improves the whole thermal design of the supply circuit UBX 13000995 R10 Early Production Information Design in Page 87 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual SARA G3 SARA U2 5V DR VCC 21N out 4 vcc vcc ca R1 C2 1 EN ADJ 2 e d EE 7 GND Figure 39 Suggested schematic design for the VCC voltage supply application circuit using an LDO linear regulator Reference Description Part Number Manufacturer C1 C2 10 pF Capacitor Ceramic X5R 0603 20 6 3 V GRM188R60J106ME47 Murata R1 27 kQ Resistor 0402 596 0 1 W RC0402JR 0727KL
62. The required certification scheme approvals and relative testing specifications differ depending on the country or the region where the device that integrates SARA G3 and SARA U2 series modules must be deployed on the relative vertical market of the device on type features and functionalities of the whole application device and on the network operators where the device must operate C8 The certification of the application device that integrates a SARA G3 and SARA U2 series module and the compliance of the application device with all the applicable certification schemes directives and standards are the sole responsibility of the application device manufacturer SARA G3 and SARA U2 series modules are certified according to all capabilities and options stated in the Protocol Implementation Conformance Statement document PICS of the module The PICS according to 3GPP TS 51 010 2 16 and 3GPP TS 34 121 2 17 is a statement of the device capabilities and options Se The PICS document of the application device integrating a SARA G3 and SARA U2 series module must be updated from the module PICS statement if any feature stated as supported by the module in its PICS document is not implemented or disabled in the application device For more details regarding the AT commands settings that affect the PICS see the u blox AT Commands Manual 3 ee Check the specific settings required for mobile network operators approvals as they may differ from the AT
63. The use of switching step down provides the best power efficiency for the overall application and minimizes current drawn from the main supply source Refer to sections 2 2 1 2 and 2 2 1 6 2 2 1 9 2 2 1 10 for specific design in The use of an LDO linear regulator becomes convenient for a primary supply with a relatively low voltage e g less than 5 V In this case the typical 9096 efficiency of the switching regulator diminishes the benefit of voltage Step down and no true advantage is gained in input current savings On the opposite side linear regulators are not recommended for high voltage step down as they dissipate a considerable amount of energy in thermal power Refer to sections 2 2 1 3 and 2 2 1 6 2 2 1 9 2 2 1 10 for specific design in If the modules are deployed in a mobile unit where no permanent primary supply source is available then a battery will be required to provide VCC A standard 3 cell Li lon or Li Pol battery pack directly connected to VCC is the usual choice for battery powered devices During charging batteries with Ni MH chemistry typically reach a maximum voltage that is above the maximum rating for VCC and should therefore be avoided Refer to Sections 2 2 1 4 and 2 2 1 6 2 2 1 9 2 2 1 10 for specific design in Keep in mind that the use of rechargeable batteries requires the implementation of a suitable charger circuit which is not included in SARA G3 and SARA U2 series modules The charger circuit has to be desig
64. and SARA U2 series modules or in close proximity to the RF antenna these two cases should be avoided or at least mitigated as described below In the first case the long connection can cause the radiation of some harmonics of the digital data frequency as any other digital interface keep the traces short and avoid coupling with RF line or sensitive analog inputs In the second case the same harmonics can be picked up and create self interference that can reduce the sensitivity of GSM UMTS receiver channels whose carrier frequency is coincidental with harmonic frequencies placing the RF bypass capacitors suggested in Figure 57 near the SIM connector will mitigate the problem In addition since the SIM card is typically accessed by the end user it can be subjected to ESD discharges add adequate ESD protection as suggested in Figure 57 to protect module SIM pins near the SIM connector Limit capacitance and series resistance on each SIM signal to match the SIM specifications the connections should always be kept as short as possible Avoid coupling with any sensitive analog circuit since the SIM signals can cause the radiation of some harmonics of the digital data frequency UBX 13000995 R10 Early Production Information Design in Page 117 of 192 SARA G3 and SARA U2 series System Integration Manual biox 2 6 Serial interfaces 2 6 1 Asynchronous serial interface UART 2 6 1 1 Guidelines for UART circuit design Providing the
65. be inserted if SPK P SPK N output level of the module is too high for the audio device input or if the audio device output level is too high for MIC P MIC N as the voltage dividers present in the circuits described in Figure 78 right side to properly adapt the signal level anis Audio Device 3ARA G340 Audio Device SARA G350 SARA G350 SPK P EZN Analog IN SPK P EZB ES RI Analog IN sPK_N E Analog IN sPK_N EEE R2 GND m 7 GND GND Reference MIC BIAS ETIN MIC BIAS EG MIC GND MIC GND MIC P Eg Analog OUT MiC P EZ 73 analog OUT MIC N EG c4 Analog OUT Mic N E m GND GND GND LR GND Z Figure 78 Application circuits to connect the module to audio devices with proper differential or single ended input output UBX 13000995 R10 Early Production Information Design in Page 137 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Reference Description Part Number Manufacturer C1 C2 C3 C4 10 uF Capacitor X5R 0603 596 6 3 V GRM188R60J106M Murata C5 C6 C7 C8 R1 R3 0 Q Resistor 0402 5 0 1 W RC0402JR 070RL Yageo Phycomp R2 R4 Not populated Table 52 Connection to an analog audio device 2 7 1 4 Guidelines for analog audio layout design Accurate analog audio design is very important to obtain clear and high quality audio The GSM signal burst has a repetition rate of 217 Hz that lies in th
66. can be properly switched off by low pulse on the PWR ON pin as reported in Table 60 or in the relative datasheet of the module 6 Module reset SARA and LISA modules reset can be performed in one of the following ways Forcing a low level on the RESET N pin causing an external or hardware reset By means of the AT CFUN command causing an internal or software reset The same compatible external reset circuit can be implemented for SARA and LISA modules even if there are minor differences in the RESET N input voltage levels ranges and in the low level time as reported in Table 60 or in the relative datasheet of the module 1 4 5 6 Additional precautions are suggested for the RESET N line of LISA U series modules depending on the application board handling to satisfy ESD immunity test requirements as described in the LISA U Series System Integration Manual 8 External 32 kHz input and internal 32 kHz output The EXT32K input and the 32K OUT output are available only on the SARA G300 and SARA G310 modules to provide the 32 kHz reference clock for the Real Time Clock RTC timing used by the module processor to reach the low power idle mode and provide the RTC functions SARA G340 SARA G350 and LISA U modules are equipped with internal 32 kHz oscillator to provide the same functions LISA C2 series do not provide RTC and the relative functions UBX 13000995 R10 Early Production Information Appendix Page 175 of 192
67. case of SARA G300 and SARA G310 modules S SARA G300 and SARA G310 need a 32 kHz signal at EXT32K input to reach the low power idle mode For the complete description of the AT UPSV command refer to the u blox AT Commands Manual 3 For the definition and the description of SARA G3 and SARA U2 series modules operating modes including the events forcing transitions between the different operating modes refer to section 1 4 For the description of current consumption in idle and active operating modes refer to sections 1 5 1 4 1 5 1 5 For the description of the UART settings related to module power saving configuration refer to section 1 9 1 4 For the description of the USB settings related to module power saving configuration refer to section 1 9 3 2 For the description of the EXT32K input and related application circuit design in refer to sections 1 6 4 2 3 3 UBX 13000995 R10 Early Production Information System description Page 81 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 2 Design in 2 1 Overview For an optimal integration of SARA G3 and SARA U2 series modules in the final application board follow the design guidelines stated in this section Every application circuit must be properly designed to guarantee the correct functionality of the related interface however a number of points require higher attention during the design of the application device The following list provides a ranking of
68. channels Data are in 2 s complement notation MSB is transmitted first The bits are written on PS clock rising or falling edge configurable l S receive data is read as 16 bit words mono words are read only on the timeslot with WA high Data is read in 2 s complement notation MSB is read first The bits are read on the l S clock edge opposite to lS transmit data writing edge configurable l S clock frequency is 16 bits x 2 channels x I2S sample rate The modes are configurable through a specific AT command refer to the related section in the u blox AT Commands Manual 3 UI2S AT command and the following parameters can be set MSB can be 1 bit delayed or non delayed on I S word alignment edge l S transmit data can change on rising or falling edge of I S clock signal l S receive data are read on the opposite front of lS clock signal UBX 13000995 R10 Early Production Information System description Page 59 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 10 3 Voice band processing system 1 10 3 1 SARA G340 SARA G350 modules audio processing The voice band processing on the SARA G340 SARA G350 modules is implemented in the DSP core inside the baseband chipset The analog audio front end of the chipset is connected to the digital system through 16 bit ADC converters in the uplink path and through 16 bit DAC converters in the downlink path External digital audio devices can directly be interf
69. circuit design in input negative or all the analog uplink path modes headset hands free mode nal DC blocking capacitor ion 1 10 1 for functional description ion 2 7 tial analog audio signal for external circuit design in input positive or all the analog uplink path modes headset hands free mode nal DC blocking capaci ion 2 7 ial analog audio signa or all the analog down ial analog audio signal or all the analog down Or ion 1 10 1 for functional description for external ci rcuit design in output positive ink path modes headset and loudspeaker mode ion 1 10 1 for functional description ion 2 7 1 for external ci rcuit design in output negative ink path modes headset and loudspeaker mode ion 1 10 1 for functional description ion 2 7 1 for external ci rcuit design in 1 8 V serial clock for PCM normal l S modes igurable also as GPIO on SARA U2 series Pin confi See sec See sec Pin confi See sec See sec ion 1 10 2 for functional description ion 2 7 2 for external circuit design in 1 8 V data input for PCM normal S modes igurable also as GPIO on SARA U2 series Internal active pull down to GND ion 1 10 2 for functional description ion 2 7 2 for external circuit design in 1 8 V data output for PCM normal S modes Pin confi See sec See sec igurable also as GPIO on SARA U2 series ion 1 10 2 for functio
70. com Support support jpQu blox com Regional Office Korea Phone 82 2 542 0861 E mail info_kr u blox com Support support krGu blox com Regional Office Taiwan Phone 886 2 2657 1090 E mail info twQu blox com Support support twQu blox com Contact Page 192 of 192
71. command See the u blox AT Commands Manual 3 for more details on this feature The ANT DET pin generates a DC current 20 pA for 5 4 ms on SARA G340 SARA G350 10 pA for 128 us on SARA U2 modules and measures the resulting DC voltage thus determining the resistance from the antenna connector provided on the application board to GND So the requirements to achieve antenna detection functionality are the following an RF antenna assembly with a built in resistor diagnostic circuit must be used an antenna detection circuit must be implemented on the application board See section 2 4 2 for antenna detection circuit on application board and diagnostic circuit on antenna assembly design in guidelines 1 8 SIM interface 1 8 1 U SIM card interface SARA G3 and SARA U2 series modules provide a high speed SIM ME interface including automatic detection and configuration of the voltage required by the connected U SIM card or chip Both 1 8 V and 3 V SIM types are supported activation and deactivation with automatic voltage switch from 1 8 V to 3 V is implemented according to ISO IEC 7816 3 specifications The VSIM supply output pin provides internal short circuit protection to limit start up current and protect the device in short circuit situations The SIM driver supports the PPS Protocol and Parameter Selection procedure for baud rate selection according to the values determined by the SIM Card SIM Application Toolkit is supported b
72. commands settings defined in the module as integrated in the application device UBX 13000995 R10 Early Production Information Approvals Page 162 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual 4 2 Federal Communications Commission and Industry Canada notice Federal Communications Commission FCC ID For SARA G310 modules XPYSARAG350 For SARA G350 modules XPYSARAG350 For SARA U260 modules XPYSARAU260 For SARA U280 modules to be defined Industry Canada IC Certification Numbers For SARA G310 modules 8595A SARAG350 For SARA G350 modules 8595A SARAG350 For SARA U260 modules 8595A SARAU260 For SARA U280 modules to be defined 4 2 1 Safety warnings review the structure Equipment for building in The requirements for fire enclosure must be evaluated in the end product The dearance and creepage current distances required by the end product must be withheld when the module is installed The cooling of the end product shall not negatively be influenced by the installation of the module Excessive sound pressure from earphones and headphones can cause hearing loss No natural rubbers no hygroscopic materials nor materials containing asbestos are employed 4 2 2 Declaration of conformity United States only This device complies with Part 15 of the FCC rules Operation is subject to the following two conditions this device may not cause harmful interference this device must accept any interference received i
73. design using a switching regulator The use of a switching regulator is suggested when the difference from the available supply rail to the VCC value is high switching regulators provide good efficiency transforming a 12 V or greater voltage supply to the typical 3 8 V value of the VCC supply The characteristics of the switching regulator connected to VCC pins should meet the following prerequisites to comply with the module VCC requirements summarized in Table 7 Power capability the switching regulator with its output circuit must be capable of providing a voltage value to the VCC pins within the specified operating range and must be capable of delivering to VCC pins the specified maximum peak pulse current with 1 8 duty cycle refer to the SARA G3 series Data Sheet 1 or the SARA U2 series Data Sheet 2 Low output ripple the switching regulator together with its output circuit must be capable of providing a clean low noise VCC voltage profile High switching frequency for best performance and for smaller applications select a switching frequency 2 600 kHz since L C output filter is typically smaller for high switching frequency The use of a switching regulator with a variable switching frequency or with a switching frequency lower than 600 kHz must be carefully evaluated since this can produce noise in the VCC voltage profile and therefore negatively impact GSM modulation spectrum performance An additional L C low pass filter betw
74. does not lose the data sent by the GNSS receiver even if power saving is enabled The RTC synchronization signal to the GNSS receiver GNSS RTC sharing function provided by GPIO4 improves GNSS receiver performance decreasing the Time To First Fix TTFF and thus allowing to calculate the position in a shorter time with higher accuracy When GPS local aiding is enabled the cellular module automatically uploads data such as position time ephemeris almanac health and ionospheric parameter from the positioning receiver into its local memory and restores this to the GNSS receiver at the next power up of the positioning receiver ee For more details regarding the handling of the DDC l C interface the GNSS aiding features and the GNSS related functions over GPIOs see section 1 11 to the u blox AT Commands Manual 3 AT UGPS AT UGPRF AT UGPIOC AT commands and the GNSS Implementation Application Note 24 Se GNSS data ready and GNSS RTC sharing functions are not supported by all u blox GNSS receivers HW or ROM FW versions See the GNSS Implementation Application Note 24 or to the Hardware Integration Manual of the u blox GNSS receivers for the supported features As additional improvement for the GNSS receiver performance the V_BCKP supply output of SARA G340 SARA G350 and SARA U2 modules can be connected to the V_BCKP supply input pin of u blox positioning chips and modules to provide the supply for the GNSS real time c
75. e iter nndis 125 2 6 4 DDC PC interface ssessssse eee rere ee rennen serrer trees e renes d 127 ZI AudiolttelTd6e ect et Ste dE ML LE LU LAS p 133 2 7 1 Analog audio interface sirsenis aii innri aatan i entai enr nnt nennen nennen 133 2 2 Digital audio Interface io retire sea te eee tia testudo bestie Ged ieee 139 2 8 GeneralPurposeInput Output GPIO krsnera ipis ordiri O EEE 142 29 MEE omoi E P 143 2 10 Module placement ssssssssssssseeee eene ener sere enne rennen ner inrer enne nnne nnn 143 2 11 Module footprint and paste mask ssssssssssssseeeeeeeeeeeeee eene 144 2 12 Thermal guidelines iut er e ett etd etes e epo rea tte e hone nde eat eee 145 2 13 ESD guidelines ERE DEDE iuit Mp nM M uM 147 2 131 ESD immunity test OVerVIeW essai sanina sasaaa aaa ud quet ite dee 147 UBX 13000995 R10 Early Production Information Contents Page 5 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 2 13 2 ESD immunity test of u blox SARA G3 and SARA U2 reference designs sss 147 ZAS 3 ESD application clreults oo eee uite ese ete bie ute eeepc Potete mia tbe 148 2 14 SARA G350 ATEX integration in explosive atmospheres applications ssssssssssss 150 2 14 1 General guidelifi8s ete ERE psi t ee tad nap epe tacui nba mortis 150 2 14 2 Guidelines for VCC supply circuit design ssssssssssssseeee eene 151
76. for more details see u blox AT Commands Manual 3 AT amp K AT Q AT IFC command descriptions If AT UPSV 2 is set and HW flow control is disabled the module monitors the RTS line to manage the power saving configuration When an OFF to ON transition occurs on the RTS input line the UART is enabled and the module wakes up to active mode after 20 ms from the OFF to ON transition the UART module wake up is completed and data can be received without loss The module cannot enter the low power idle mode and the UART is kept enabled as long as the RTS input line is held in the ON state If the RTS input line is set to the OFF state by the DTE the UART is disabled held in low power mode and the module automatically enters low power idle mode whenever possible For more details see section 1 9 1 4 and u blox AT Commands Manual 3 AT UPSV command DSR signal behavior If AT amp S1 is set as it is by default the DSR module output line is set by default to the OFF state high level at UART initialization The DSR line is then set to the OFF state when the module is in command mode or in online command mode and is set to the ON state when the module is in data mode see the u blox AT Commands Manual 3 for the definition of the interface data mode command mode and online command mode If AT amp SO is set the DSR module output line is set by default to the ON state low level at UART initialization and is then always held in the ON state
77. frequency Inner pull down 150 pA Driver strength 1 mA LISA U200 00S N A 1 8 V Clock In Out Configurable frequency Inner pull down 150 pA Driver strength 1 mA LISA U200 00S N A Appendix Page 181 of 192 biox Pin Name N Other CODEC_CLK GPIO GPIO1 16 GPIO2 23 GPIO3 24 GPIO4 25 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 UBX 13000995 R10 SARA G3 series Not Available SARA G340 SARA G350 1 8 V configurable GPIO Default Pin disabled Driver strength 6 mA Inner pull down 51 pA SARA G340 SARA G350 1 8 V configurable GPIO Default GNSS supply ena Driver strength 6 mA Inner pull down 51 pA SARA G340 SARA G350 1 8 V configurable GPIO Default GNSS data ready Driver strength 5 mA Inner pull down 27 pA SARA G340 SARA G350 1 8 V configurable GPIO Default GNSS RTC shar Driver strength 6 mA Inner pull down 51 pA Not Available Not Available Not Available Not Available Not Available Not Available Not Available Not Available N 52 20 21 23 24 51 39 40 53 54 55 56 57 SARA G3 and SARA U2 series System Integration Manual LISA C2 series Not Available 1 8 V configurable GPIO Default Pin disabled Driver strength 4 mA nner pull down 30 pA 1 8 V configurable GPIO Default Pin disabled Driver strength 4 mA nner pull down 30 pA 1 8 V configurable GPIO Default Pin disabled
78. full RS 232 functionality using the complete V 24 link If RS 232 compatible signal levels are needed two different external voltage translators e g Maxim MAX3237E and Texas Instruments SN74AVC8T245PW can be used to provide full RS 232 9 lines functionality The Texas Instruments chip provides the translation from 1 8 V to 3 3 V while the Maxim chip provides the translation from 3 3 V to RS 232 compatible signal level If a 1 8 V application processor is used for complete RS 232 functionality as per ITU Recommendation 10 in the DTE DCE serial communication the complete UART interface of the module DCE must be connected to a 1 8 V application processor DTE as described in Figure 59 SARA G3 SARA U2 1 8V DCE Application Processor 1 8V DTE TxD RxD RTS CTS DTR DSR RI DCD GND Figure 59 UART interface application circuit with complete V 24 link in DTE DCE serial communication 1 8 V DTE If a 3 0 V Application Processor is used appropriate unidirectional voltage translators must be provided using the module V INT output as 1 8 V supply as described in Figure 60 Application Processor SARA G3 SARA U2 3 0V DTE Unidirectional 1 8V DCE 3V0 Voltage Translator 1V8 3 VCC VCCA VCCB __ of um V_INT a L DIR1 a DIR3 ES 02 TP TxD 1 B1 TXD 02 TP RxD 42 B2 RXD 02 TP RTS A3 B3 RTS 02 TP CTS 4
79. ia is permitted however other semiconductors and controllable semiconductor devices shall be used as series current limiting devices only in Level of Protection ib or ic apparatus However for power limitation purposes Level of Protection ia apparatus may use series current limiters consisting of controllable and non controllable semiconductor devices The use of semiconductors and controllable semiconductor devices as current limiting devices for spark ignition limitation is not permitted for Level of Protection ia apparatus because of their possible use in areas in which a continuous or frequent presence of an explosive atmosphere may coincide with the possibility of a brief transient which could cause ignition The maximum current that may be delivered may have a brief transient but will not be taken as lo because the compliance with the spark ignition test of the clause 10 1 of IEC 60079 11 standard 33 would have established the successful limitation of the energy in this transient Protection against polarity reversal Protection against polarity reversal shall be provided within intrinsically safe apparatus to prevent invalidation of the type of protection as a result of reversal of the polarity of supplies to that intrinsically safe apparatus or at connections between cells of a battery where this could occur For this purpose single diode shall be acceptable Other considerations All the recommendations repor
80. immunity improvement for SARA U2 modules a series 0 Q jumper can be mounted for SARA G340 and SARA G350 modules instead of the high pass filter as no further precaution to ESD immunity test is needed The ANT pin must be connected to the antenna connector by means of a transmission line with nominal characteristics impedance as close as possible to 50 Q The DC impedance at RF port for some antennas may be a DC open e g linear monopole or a DC short to reference GND e g PIFA antenna For those antennas without the diagnostic circuit of Figure 53 the measured DC resistance is always at the limits of the measurement range respectively open or short and there is no mean to distinguish between a defect on antenna path with similar characteristics respectively removal of linear antenna or RF cable shorted to GND for PIFA antenna Furthermore any other DC signal injected to the RF connection from ANT connector to radiating element will alter the measurement and produce invalid results for antenna detection Se It is recommended to use an antenna with a built in diagnostic resistor in the range from 5 kO to 30 kQ to assure good antenna detection functionality and avoid a reduction of module RF performance The choke inductor should exhibit a parallel Self Resonance Frequency SRF in the range of 1 GHz to improve the RF isolation of load resistor For example Consider an antenna with built in DC load resistor of 15 kO Using the UANTR
81. is still not so low as in the equivalent 2G case also due to module continuous baseband processing and transceiver activity Figure 10 shows an example of current consumption profile of SARA U2 series modules in 3G WCDMA HSPA continuous transmission and reception mode For detailed current consumption values during a 3G connection see the SARA U2 series Data Sheet 2 Current mA 800 D f en l n MP caasa preme 700 600 500 Current consumption depends on TX power and 400 actual antenna load 300 200 1001 gt Time ms 3G frame 10 ms 1 frame 15 slots A Figure 10 VCC current consumption profile versus time during a 3G connection TX and RX continuously enabled UBX 13000995 R10 Early Production Information System description Page 23 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 5 1 4 VCC current consumption in cyclic idle active mode power saving enabled The power saving configuration is by default disabled but it can be enabled using the appropriate AT command see u blox AT Commands Manual 3 AT UPSV command When power saving is enabled the module automatically enters low power idle mode whenever possible reducing current consumption During idle mode the module processor runs with 32 kHz reference clock the internal oscillator automatically generates the 32 kHz clock on SA
82. module Connect the UICC SIM contact C2 RST to the SIM RST pin of the module Connect the UICC SIM contact C5 GND to ground Provide a 100 nF bypass capacitor e g Murata GRM155R71C104K at the SIM supply line VSIM close to the related pad of the SIM connector to prevent digital noise Provide a bypass capacitor of about 22 pF to 47 pF e g Murata GRM1555C1H470J on each SIM line VSIM SIM CLK SIM IO SIM RST very close to each related pad of the SIM connector to prevent RF coupling especially in case the RF antenna is placed closer than 10 30 cm from the SIM card holder Provide a low capacitance i e less than 10 pF ESD protection e g Tyco Electronics PESD0402 140 on each externally accessible SIM line close to each related pad of the SIM connector ESD sensitivity rating of the SIM interface pins is 1 kV Human Body Model according to JESD22 A114 so that according to the EMC ESD requirements of the custom application higher protection level can be required if the lines are externally accessible on the application device Limit capacitance and series resistance on each SIM signal SIM CLK SIM IO SIM RST to match the requirements for the SIM interface 27 7 ns is the maximum allowed rise time on the SIM CLK line 1 0 us is the maximum allowed rise time on the SIM IO and SIM RST lines SARA G3 SARA U2 V INT EN e SIM CARD siM DET EM HOLDER VPP C6 v
83. module is a good solution to prevent operation of the device outside of the specified range Smart Temperature Supervisor STS The Smart Temperature Supervisor is activated and configured by a dedicated AT USTS command See u blox AT Commands Manual 3 for more details The cellular module measures the internal temperature Ti and its value is compared with predefined thresholds to identify the actual working temperature range ee Temperature measurement is done inside the module the measured value could be different from the environmental temperature Ta Valid temperature range Dangerous Warning Safe Warning Dangerous area area area area area t t4 thy t42 Figure 30 Temperature range and limits The entire temperature range is divided into sub regions by limits see Figure 30 named t t t and t Within the first limit t lt Ti lt t the cellular module is in the normal working range the Safe Area In the Warning Area t lt Ti lt t or t lt Ti lt t the cellular module is still inside the valid temperature range but the measured temperature approaches the limit upper or lower The module sends a warning to the user through the active AT communication interface which can take if possible the necessary actions to return to a safer temperature range or simply ignore the indication The module is still in a valid and good working condition Outside the valid temperature range Ti lt t or Ti
84. modules do not support antenna detection UBX 13000995 R10 Early Production Information Appendix Page 176 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual A 4 4 SIM interface SIM interface The same compatible external circuit can be implemented for SARA and LISA modules 1 8 V and 3 0 V SIM are supported LISA C2 modules do not need an external SIM for Sprint and Verizon mobile operators LISA C2 series SIM interface is hardware ready but the support of external SIM card IC will be provided by the upcoming firmware releases SIM detection interface The same compatible external circuit can be implemented for SARA and LISA modules SIM detection function is provided by the SIM DET pin on SARA G3 modules and by the GPIO5 pin on LISA U modules SIM card hot insertion removal is additionally supported by all LISA U2 series except LISA U200 00S LISA C2 modules do not support SIM detection A 4 5 Serial interfaces UART interface The same compatible external circuit can be implemented for SARA and LISA modules a 1 8 V unbalanced asynchronous serial port with RS 232 functionality is provided on SARA G3 modules for AT command data communication MUX functionality FW upgrade over AT LISA C2 modules for AT command data communication MUX functionality LISA U modules for AT command data communication MUX functionality FW upgrade over AT or using the u blox EasyFlash tool LISA C2 modules do not support D
85. n T o o T oU T T o T o n T t T T s T T n o n n T nmm T T T LISA U270 amp o 850 900 950 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 824 960 1710 2170 ww wi wol Ly Ivi Ivi 1 l v Lv m USA U00 m ss cw 99 LISA U230 597 39 99 TT T BEES mit irri rrr n p iii ii ii ia ai ai aii m nnm mimm T T 800 850 900 950 1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200 824 960 1710 2170 Figure 93 Summary of operating bands frequency ranges among modules An external circuit can be implemented on the application device integrating SARA U2 and LISA U2 modules to satisfy ESD immunity test requirements at the antenna port as described in sections 2 13 and 2 4 and in the LISA U Series System Integration Manual 8 The same external circuit is not required for SARA G3 LISA U1 and LISA C2 modules RF interface for Rx diversity antenna Only the LISA U230 modules provide the RF input for Rx diversity antenna ANT DIV SARA G3 LISA C2 LISA U1 and the other LISA U2 series modules do not support Rx diversity Antenna detection interface An external application circuit can be implemented on the application device integrating SARA G340 SARA G350 modules to provide antenna detection functionality with a proper connection between the ANT DET pin and the ANT pin as described in section 2 4 2 LISA U modules are equipped with internal circuit for antenna detection support SARA G300 SARA G310 and LISA C2 series
86. nF capacitor e g Murata GRM155R71C103K to filter digital logic noise from clocks and data sources 56 pF capacitor with Self Resonant Frequency in 800 900 MHz range e g Murata GRM1555C1E560J to filter transmission EMI in the GSM EGSM bands 15 pF capacitor with Self Resonant Frequency in 1800 1900 MHz range e g Murata GRM1555C1E150J to filter transmission EMI in the DCS PCS bands A series ferrite bead for GHz band noise e g Murata BLM18EG221SN1 can be placed close to the VCC pins of the module for additional noise filtering but in general it is not strictly required ee Figure 40 shows the complete configuration but the mounting of each single component depends on the application design it is recommended to provide all the VCC bypass capacitors as described in Figure 40 and Table 25 if the application device integrates an internal antenna SARA G3 SARA U2 3V8 vcc EE HE vcc e e e e e vcc C5 C4 C3 C2 C1 GND EE Figure 40 Suggested schematic and layout design for the VCC bypass capacitors to reduce ripple noise on VCC voltage profile and to avoid undershoot overshoot on VCC voltage drops UBX 13000995 R10 Early Production Information Design in Page 89 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Reference Description Part Number Manufacturer C1 330 uF Capacitor Tantalum D SIZE 6 3 V 45 mQ T520D337MO006ATE045 KEMET C2 10
87. not be set high before the switch on of the V INT supply of the DDC l C pins to avoid latch up of circuits and let a proper boot of the module The signal shape is defined by the values of the pull up resistors and the bus capacitance Long wires on the bus increase the capacitance If the bus capacitance is increased use pull up resistors with nominal resistance value lower than 4 7 kQ to match the C bus specifications 15 regarding rise and fall times of the signals ee Capacitance and series resistance must be limited on the bus to match the l C specifications 1 0 us is the maximum allowed rise time on the SCL and SDA lines route connections as short as possible Se ESD sensitivity rating of the DDC l C pins is 1 kV Human Body Model according to JESD22 A114 Higher protection level could be required if the lines are externally accessible and it can be achieved by mounting an ESD protection e g EPCOS CAO5PAS14THSG varistor array close to accessible points S If the pins are not used as DDC bus interface they can be left unconnected UBX 13000995 R10 Early Production Information Design in Page 127 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual Connection with u blox 1 8 V GNSS receivers Figure 72 shows an application circuit example for connecting a SARA G340 SARA G350 or SARA U2 cellular module to a u blox 1 8 V GNSS receiver The SDA and SCL pins of the cellular module are directly connected
88. not provide a completely insulated enclosure able to provide protection to direct contact discharge up to 4 kV and protection to air discharge up to 8 kV to the whole antenna and cable surfaces an external high pass filter consisting of a series 15 pF capacitor Murata GRM1555C1H150JA01 and a shunt 39 nH coil Murata UBX 13000995 R10 Early Production Information Design in Page 148 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual LQG15HN39NJO2 should be implemented at the antenna port as described in the Figure 52 Figure 53 and Figure 54 as implemented in the EMC ESD approved reference design of SARA U2 modules The antenna interface application circuit implemented in the EMC ESD approved reference designs of SARA G3 and SARA U2 series modules is described in Figure 52 in case of antenna detection circuit not implemented and is described in Figure 53 and Table 35 in case of antenna detection circuit implemented section 2 4 RESET N pin The following precautions are suggested for the RESET N line of SARA G3 and SARA U2 series modules depending on the application board handling to satisfy ESD immunity test requirements It is recommended to keep the connection line to RESET N as short as possible Maximum ESD sensitivity rating of the RESET N pin is 1 kV Human Body Model according to JESD22 A1 14 Higher protection level could be required if the RESET N pin is externally accessible on the application board The f
89. or the problem A short description of the application Your complete contact details UBX 13000995 R10 Early Production Information Preface Page 3 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Contents jr 3 CONTIONE osse es S I DM E II 4 1 System description e G 0 X X aiae aain 8 1 1 OVENNEVNTE EAD d tte ec itl E 8 BA ACNEE e a c Oe a mur I AC MM tU Pe HII UN RII CET 10 1 2 1 internal DOCK S ire E EAE AEE E E E E 12 1 3 Pinout aane a E E EE a EA A 13 1 4 Operating modes een ener enne enn nnn seres nnne nenne nnn enr n nnne nnne 18 1 5 Supply Interfaces ous e et n ctt ett ultus a dana et teure eE e tae eR aes 20 1 5 1 Modulesupply Input MVC Dti etatis entem tut dts ud ons seb ere pd Ortus 20 1 5 2 RTCsupply inp t output V BCKB J abet et pei te ere a Hat pu pe iR pea EE 28 1 5 8 Generic digital interfaces supply output V INT 29 1 6 System function interfaces enne nnne rennen nennen 30 1 6 1 Mod le pOWISOnL sen tt ettet te ettet tuerit e tee iag he 30 1 6 2 Module power off isses ee eeereereenre enne enn enne nennen nens 33 1 6 3 Moduleres te een SU Deco IA PT I DU OE IM MEM IM PRD 35 1 6 4 External 32 kHz signal input EXT32K ssssssssssseee eee eene ene meer erre enne 36 1 6 5 Internal 32 kHz signal output 32K OUT isssssssssseeemn e nemen nennen nennen nnne 36 to BNET m m 37 1 7 1 Antenna RF interface A
90. ox SARA G3 and SARA U2 series System Integration Manual 1 Several devices reported their position to the CellLocate server when observing a specific cell the As in the picture represent the position of the devices which observed the same cell A A A A A AAA A A gt gt E gt gt 3 If a new device reports the observation of Cell A CellLocate is able to provide the estimated position from the area of visibility UBX 13000995 R10 Early Production Information System description Page 76 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 4 Thevisibility of multiple cells provides increased accuracy based on the intersection of areas of visibility ss Intersection Cell A N Cell B N Cell C CellLocate is implemented using a set of two AT commands that allow configuration of the CellLocate service AT ULOCCELL and requesting position according to the user configuration AT ULOC The answer is provided in the form of an unsolicited AT command including latitude longitude and estimated accuracy ee The accuracy of the position estimated by CellLocate depends on the availability of historical observations in the specific area Hybrid positioning With u blox hybrid positioning technology u blox cellular modules can be triggered to provide their current position using either a u blox GNSS receiver or the position estimated from CellLocate The choice depends on which p
91. path with suitable uninterrupted ground plane to main DC source It is recommended to implement one layer of the application board as ground plane as wide as possible If the application board is a multilayer PCB then all the board layers should be filled with GND plane as much as possible and each GND area should be connected together with complete via stack down to the main ground layer of the board If the whole application device is composed by more than one PCB then it is required to provide a good and solid ground connection between the GND areas of all the different PCBs Good grounding of GND pins also ensures thermal heat sink This is critical during call connection when the real network commands the module to transmit at maximum power proper grounding helps prevent module overheating UBX 13000995 R10 Early Production Information Design in Page 94 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual 2 2 2 RTC supply V BCKP 2 2 3 1 Guidelines for V BCKP circuit design If RTC timing is required to run for a time interval of T s at 25 C when VCC supply is removed place a capacitor with a nominal capacitance of C uF at the V BCKP pin Choose the capacitor using the following formula C uF Current Consumption uA x T s Voltage Drop V 1 5 x T s for SARA G3 series 2 5 x T s for SARA U2 series For example a 100 uF capacitor such as the Murata GRM43SR60J107M can be placed at V B
92. possible to access the embedded TCP IP and UDP IP stack functionalities over the Packet Switched data connection For more details about AT commands see u blox AT Commands Manual 3 Direct Link mode for TCP and UDP sockets is supported Sockets can be set in Direct Link mode to establish a transparent end to end communication with an already connected TCP or UDP socket via serial interface In Direct Link mode data sent to the serial interface from an external application processor is forwarded to the network and vice versa To avoid data loss while using Direct Link enable HW flow control on the serial interface 1 13 5 FTP ee Not supported by SARA G300 and SARA G310 modules SARA G340 SARA G350 and SARA U2 series modules support the File Transfer Protocol functionalities via AT commands Files are read and stored in the local file system of the module SARA U2 series modules support also Secure File Transfer Protocol functionalities providing SSL encryption For more details about AT commands see the u blox AT Commands Manual 3 1 13 6 HTTP ee Not supported by SARA G300 and SARA G310 modules SARA G340 SARA G350 and SARA U2 modules support Hyper Text Transfer Protocol functionalities as an HTTP client is implemented HEAD GET POST DELETE and PUT operations are available The file size to be uploaded downloaded depends on the free space available in the local file system FFS at the moment of the operation Up to 4 HTTP client c
93. received by the module Data sent by the module is correctly received by the DTE if it is ready to receive data otherwise data is lost 2 Disabled AT amp KO OFF ON or OFF Data sent by the DTE is lost by SARA U2 modules The first character sent by the DTE is lost by SARA G3 modules but after 20 ms the UART and the module are waked up recognition of subsequent characters is guaranteed after the complete UART module wake up Data sent by the module is correctly received by the DTE if it is ready to receive data otherwise data is lost UBX 13000995 R10 Early Production Information System description Page 46 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual AT UPSV HW flow control RTS line DTR line Communication during idle mode and wake up 3 Enabled AT amp K3 ON ON Data sent by the DTE is correctly received by the module Data sent by the module is correctly received by the DTE 3 Enabled AT amp K3 ON OFF Data sent by the DTE is lost by the module Data sent by the module is correctly received by the DTE 3 Enabled AT amp K3 OFF ON Data sent by the DTE is correctly received by the module Data sent by the module is buffered by the module and will be correctly received by the DTE when it is ready to receive data i e RTS line will be ON 3 Enabled AT amp K3 OFF OFF Data sent by the DTE is lost by the module Data sent by the module is buffered by the module and will be corr
94. registered visitor network voice or data call enabled by means of the AT UGPIOC command For the detailed description see section 1 11 and to u blox AT Commands Manual 3 GPIO commands 1 13 2 Antenna detection Se Not supported by SARA G300 and SARA G310 modules ANT_DET pin of SARA G340 SARA G350 and SARA U2 series modules is an Analog to Digital Converter ADC provided to sense the presence of an external antenna when optionally set by the UANTR AT command The external antenna assembly must be provided with a built in resistor diagnostic circuit to be detected and an antenna detection circuit must be implemented on the application board properly connecting the antenna detection input ANT_DET to the antenna RF interface ANT For more details regarding feature description and detection diagnostic circuit design in see sections 1 7 2 and 2 4 2 and to the u blox AT Commands Manual 3 1 13 3 Jamming detection ee Not supported by SARA G300 and SARA G310 modules In real network situations modules can experience various kind of out of coverage conditions limited service conditions when roaming to networks not supporting the specific SIM limited service in cells which are not suitable or barred due to operators choices no cell condition when moving to poorly served or highly interfered areas In the latter case interference can be artificially injected in the environment by a noise generator covering a given spectrum thu
95. speech codecs are supported by SARA G340 SARA G350 firmware on the DSP e GSM Half Rate TCH HS e GSM Full Rate TCH FS e GSM Enhanced Full Rate TCH EFR e 3GPP Adaptive Multi Rate AMR TCH AFS TCH AHS o In AMR Full Rate AFS the Active CODEC Set is selected from an overall set of 8 data rates 12 2 10 2 7 95 7 40 6 70 5 90 5 15 4 75 kb s o ln AMR Half Rate AHS the overall set comprises 6 different data rates 7 95 7 40 6 70 5 90 5 15 4 75 kb s 1 10 3 2 SARA U2 modules audio processing system The voiceband processing on the SARA U2 modules is implemented in the DSP core inside the baseband chipset The external digital audio devices can be interfaced directly to the DSP digital processing part via the l S digital interface With exception of the speech encoder decoder audio processing can be controlled by AT commands The audio processing is implemented within the different blocks of the voiceband processing system e Sample based Voice band Processing single sample processed at 16 kHz for Wide Band AMR codec or 8 kHz for all other speech codecs e Frame based Voice band Processing frames of 320 samples for Wide Band AMR codec or 160 samples for all other speech codecs are processed every 20 ms These blocks are connected by buffers circular buffer and voiceband sample buffer and sample rate converters for 8 16 to 47 6 kHz conversion The voiceband audio processing implemented in the D
96. the VCC pins and all the GND pins are internally connected within the module it is recommended to properly connect all of them to supply the module to minimize series resistance losses To avoid voltage drop undershoot and overshoot at the start and end of a transmit burst during a single slot 2G voice data call when current consumption on the VCC supply can rise up to the maximum peak pulse current specified in the SARA G3 series Data Sheet 1 or in the SARA U2 series Data Sheet 2 place a bypass capacitor with large capacitance more than 100 uF and low ESR near the VCC pins for example 330 pF capacitance 45 mQ ESR e g KEMET T520D337MOO6ATE045 Tantalum Capacitor The use of very large capacitors i e greater then 1000 pF on the VCC line should be carefully evaluated since the voltage at the VCC pins voltage must ramp from 2 5 V to 3 2 V in less than 1 ms to switch on the SARA U2 modules or in less than 4 ms to switch on the SARA G3 modules by applying VCC supply that otherwise can be switched on by forcing a low level on the RESET_N pin during the VCC rising edge and then releasing the RESET_N pin when the VCC supply voltage stabilizes at its proper nominal value To reduce voltage ripple and noise especially if the application device integrates an internal antenna place the following bypass capacitors near the VCC pins 100 nF capacitor e g Murata GRM155R61C 104k to filter digital logic noise from clocks and data sources 10
97. the module VCC normal operating range The characteristics of the LDO linear regulator connected to the VCC pins should meet the following prerequisites to comply with the module VCC requirements summarized in Table 7 Power capabilities the LDO linear regulator with its output circuit must be capable of providing a proper voltage value to the VCC pins and of delivering to VCC pins the specified maximum peak pulse current with 1 8 duty cycle refer to the SARA G3 series Data Sheet 1 or the SARA U2 series Data Sheet 2 Power dissipation the power handling capability of the LDO linear regulator must be checked to limit its junction temperature to the maximum rated operating range i e check the voltage drop from the max input voltage to the min output voltage to evaluate the power dissipation of the regulator UBX 13000995 R10 Early Production Information Design in Page 86 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual Output voltage slope the use of the soft start function provided by some voltage regulator should be carefully evaluated since the VCC pins voltage must ramp from 2 5 V to 3 2 V in less than 1 ms to switch on the SARA U2 modules or in less than 4 ms to switch on the SARA G3 modules by applying VCC supply that otherwise can be switched on by forcing a low level on the RESET_N pin during the VCC rising edge and then releasing the RESET_N pin when the VCC supply voltage stabilizes at its proper n
98. the USB is connected and not suspended the module is forced to stay in active mode therefore the AT UPSV settings are overruled but they have effect on the power saving configuration of the other interfaces The modules are capable of USB remote wake up signaling i e it may request the host to exit suspend mode or selective suspend by using electrical signaling to indicate remote wake up This notifies the host that it should resume from its suspended mode if necessary and service the external event Remote wake up is accomplished using electrical signaling described in the USB 2 0 specifications 14 For the module current consumption description with power saving enabled and USB suspended or with power saving disabled and USB not suspended see sections 1 5 1 4 1 5 1 5 and SARA U2 series Data Sheet 2 1 9 4 DDC lC interface Se SARA G300 and SARA G310 modules do not support DDC C interface An IC bus compatible Display Data Channel DDC interface for communication with u blox GNSS receivers is available on SDA and SCL pins of SARA G340 SARA G350 and SARA U2 modules Only this interface provides the communication between the u blox cellular module and u blox positioning chips and modules SARA U2 modules additionally support the communication with other external IC devices as an audio codec The AT commands interface is not available on the DDC C interface DDC IC slave mode operation is not supported the cellular module can act
99. the antenna manufacturer regarding correct installation and deployment of the antenna system including PCB layout and matching circuitry Further to the custom PCB and product restrictions the antenna may require a tuning to comply with all the applicable required certification schemes It is recommended to consult the antenna manufacturer for the design in guidelines for the antenna related to the custom application Additionally these recommendations regarding the antenna system must be followed Do not include antenna within closed metal case Do not place the antenna in close vicinity to end users since the emitted radiation in human tissue is limited by regulatory requirements Place the antenna far from sensitive analog systems or employ countermeasures to reduce electromagnetic compatibility issues Take care of interaction between co located RF systems since the GSM UMTS transmitted RF power may interact or disturb the performance of companion systems The antenna shall provide optimal efficiency figure over all the operating frequencies The antenna shall provide appropriate gain figure i e combined antenna directivity and efficiency figure so that the electromagnetic field radiation intensity does not exceed the regulatory limits specified in some countries e g by FCC in the United States as reported in section 4 2 2 UBX 13000995 R10 Early Production Information Design in Page 106 of 192 Qo ox SARA G3 and SARA U2
100. the modules Se The internal reset state of all digital pins is reported in the pin description table in the SARA G3 series Data Sheet 1 and in the SARA U2 series Data Sheet 2 UBX 13000995 R10 Early Production Information System description Page 35 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 6 4 External 32 kHz signal input EXT32K E The EXT32K pin is not available on SARA G340 SARA G350 and SARA U2 series modules The EXT32K pin of SARA G300 SARA G310 modules is an input pin that must be fed by a proper 32 kHz signal to make available the reference clock for the Real Time Clock RTC timing used by the module processor when in the low power idle mode SARA G300 SARA G310 modules can enter the low power idle mode only if a proper 32 kHz signal is provided at the EXT32K input pin with power saving configuration enabled by the AT UPSV command In this way the different current consumption figures can be reached with the EXT32K input fed by the 32K_OUT output or by a proper external 32 kHz signal for more details see section 1 5 1 4 and to Current consumption section in SARA G3 series Data Sheet 1 SARA G300 SARA G310 modules can provide the RTC functions as RTC timing by AT CCLK command and RTC alarm by AT CALA command only if a proper 32 kHz signal is provided at the EXT32K input pin The RTC functions will be available only when the module is switched on if the EXT32K input is fed by the 32K
101. to the related pins of the u blox 1 8 V GNSS receiver with appropriate pull up resistors connected to the 1 8 V GNSS supply enabled after the V INT supply of the C pins of the cellular module The GPIO2 pin is connected to the active high enable pin of the voltage regulator that supplies the u blox 1 8 V GNSS receiver providing the GNSS supply enable function A pull down resistor is provided to avoid a switch on of the positioning receiver when the cellular module is switched off or in the reset state The GPIO3 and GPIO4 pins are directly connected respectively to TXD1 and EXTINTO pins of the u blox 1 8 V GNSS receiver providing GNSS data ready and GNSS RTC sharing functions The V BCKP supply output of the cellular module is connected to the V BCKP backup supply input pin of the GNSS receiver to provide the supply for the GNSS real time clock and backup RAM when the VCC supply of the cellular module is within its operating range and the VCC supply of the GNSS receiver is disabled This enables the u blox GNSS receiver to recover from a power breakdown with either a hot start or a warm start depending on the actual duration of the GNSS VCC outage and to maintain the configuration settings saved in the backup RAM u blox GNSS SARA G340 SARA G350 1 8 V receiver SARA U2 series V BCKP 4 gt v BckP GNSSLDO VMAIN Regulator vcc e ees OUT IN k
102. 0 Module SARA G3 SARA G3 SARA U2 SARA U2 SARA U2 SARA G340 SARA G350 SARA U2 SARA G340 SARA G350 SARA U2 Pin No 28 28 29 27 26 1 0 VO VO VO SARA G3 and SARA U2 series System Integration Manual Description Auxiliary UART data output Auxiliary UART data input USB detect input USB Data Line D USB Data Line D PC bus clock line l C bus data line Early Production Information Remarks 1 8 V output Circuit 104 RXD in ITU T V 24 for FW upgrade via EasyFlash tool and diagnostic Access by external test point is recommended See section 1 9 2 for functional description See section 2 6 2 for external circuit design in 1 8 V input Circuit 103 TXD in ITU T V 24 for FW upgrade via EasyFlash tool and diagnostic Access by external test point is recommended Internal active pull up to V_INT See section 1 9 2 for functional description See section 2 6 2 for external circuit design in High Speed USB 2 0 interface input for VBUS 5 V typical USB supply sense USB available for AT data FOAT FW upgrade via EasyFlash tool and diagnostic See section 1 9 3 for functional description See section 2 6 3 for external circuit design in High Speed USB 2 0 interface data line for AT data FOAT FW upgrade via EasyFlash tool and diagnostic 90 Q nominal differential impedance Pull up pull down and series resistors as required by USB 2 0 specifications 14
103. 0 SARA G350 Differential input No internal capacitor or DC blocking SARA G340 SARA G350 Differential input No internal capacitor or DC blocking SARA G340 SARA G350 Differential output 16 ohm load capable SARA G340 SARA G350 Differential output 16 ohm load capable SARA G340 SARA G350 1 8 V Data Out PCM Normal I2S mode Driver strength 5 mA SARA G340 SARA G350 1 8 V Data In PCM Normal I2S mode Inner pull down 103 pA SARA G340 SARA G350 1 8 V Word align Out Fixed frequency Driver strength 6 mA SARA G340 SARA G350 1 8 V Clock Out Fixed frequency Driver strength 5 mA Not Available Not Available Not Available Not Available N 40 39 53 54 42 44 41 43 54 40 53 39 SARA G3 and SARA U2 series System Integration Manual LISA C2 series Not Available Not Available Differential input 100 nF internal capacitor or DC blocking Differential input 100 nF internal capacitor or DC blocking Differential output 32 ohm load capable Differential output 32 ohm load capable PCM_DO 1 8 V PCM Data Out PCM DI 1 8 V PCM Data In PCM SYNC 1 8 V PCM Sync Out PCM CLK 1 8 V PCM Clock Out Not Available Not Available Not Available Not Available Early Production Information LISA U1 series Not Available ot Available LISA U120 U130 only Differential input 00 nF internal c
104. 0 nF Capacitor Ceramic X7R 0402 1096 16 V GRM155R71C104KA01 Murata C3 10 nF Capacitor Ceramic X7R 0402 1096 16 V GRM155R71C103KA01 Murata C4 56 pF Capacitor Ceramic COG 0402 596 25 V GRM1555C1E560JA01 Murata C5 15 pF Capacitor Ceramic COG 0402 596 25 V GRM1555C1E150JA01 Murata Table 25 Suggested components to reduce ripple noise on VCC and to avoid undershoot overshoot on VCC voltage drops ee ESD sensitivity rating of the VCC supply pins is 1 kV Human Body Model according to JESD22 A114 Higher protection level can be required if the line is externally accessible on the application board e g if accessible battery connector is directly connected to VCC pins Higher protection level can be achieved by mounting an ESD protection e g EPCOS CAO5PAS14THSG varistor array close to accessible point 2 2 1 7 Guidelines for external battery charging circuit Application devices that are powered by a Li lon or Li Polymer battery pack should implement a suitable battery charger design as SARA G3 and SARA U2 series modules do not have an on board charging circuit In the application circuit example described in Figure 41 a rechargeable Li lon or Li Polymer battery pack that features proper pulse and DC discharge current capabilities and proper DC series resistance is directly connected to the VCC supply input of the module Battery charging is fully managed by the STMicroelectronics L6924U Battery Charger IC that from a USB source 5 0 V t
105. 00 MHz Class 4 33 dBm for 900 band Class 1 30 dBm for 1800 band GPRS multi slot class 12 CS 1 4 85 6 kb s DL CS 1 4 85 6 kb s UL EDGE multi slot class 12 MCS 1 9 236 8 kb s DL MCS 1 4 70 4 kb s UL Up to 9 6 kb s DL UL Transparent mode Non transparent mode SARA G300 SARA G340 3GPP Release 99 Class B E GSM 900 MHz DCS 1800 MHz Class 4 33 dBm for 900 band Class 1 30 dBm for 1800 band GPRS multi slot class 10 CS 1 4 85 6 kb s DL CS 1 4 42 8 kb s UL Up to 9 6 kb s DL UL Transparent mode Non transparent mode Table 3 reports a summary of 3G cellular characteristics of SARA U2 series modules Item Protocol stack UE class Bands Power class PS data rate CS data rate SARA U260 3GPP Release 7 Class A Band V 850 MHz Band Il 1900 MHz Class 3 24 dBm for all bands HSUPA category 6 5 76 Mb s UL HSDPA category 8 7 2 Mb s DL Up to 64 kb s DL UL SARA U270 3GPP Release 7 Class A Band VIII 900 MHz Band 2100 MHz Class 3 24 dBm for all bands HSUPA category 6 5 76 Mb s UL HSDPA category 8 7 2 Mb s DL Up to 64 kb s DL UL Table 3 SARA U2 series 3G characteristics summary SARA U280 3GPP Release 7 Class A Band V 850 MHz Band Il 1900 MHz Class 3 24 dBm for all bands HSUPA category 6 5 76 Mb s UL HSDPA category 8 7 2 Mb s DL Up to 64 kb s DL UL SARA G310 SARA G350 3GPP Release 99 Class B GSM 850 MHz E
106. 0kQ on PWR_ON Open Drain Output 4 _ gt n RESET_N Open Drain Output _ 1 8V DTE XD PN TXD RXD EN RXD RTS m RTs cTs IN c DTR EMM ptr DSR HN osr RI 7 Ri DCD HE oco GND GND E OQ TP TXD i O0 9 TXD AUX oQ P RXD RXD AUX GND GND 3V8 ENS Network A X X Indicator 3f X EE crio EB rsvp EB rsvp RSVD RSVD 33pF Connector External Antenna ANT BEN e 10k 82nH ANT DET ZI t e 27pF Esp SIM Card Holder Tp ik v_int Bl Swi siM_DeT EZ sw2 vsim EY CCVCC C1 CCVPP C6 siM 10 KE CCIO C7 siM ck ER CCCLK C3 siM RST IET CCRST C2 or XXE E RR lowes 470k 47PF 47pF 47pF 47pF 100nF gsp EsD ESD ESD ESD ESD u blox 1 8 V 3V8 LDO Regulator 1V8 GPS GNSS Receiver IN OUT e e Vcc GPio2 IEEIS e SHN 47k GND zB 4 7k 4 7k SDA SDA2 SCL SCL2 GPIO3 TxD1 GPIO4 EXTINTO 2 2k mic Bias IT e Taur F 22k i 2 2k Mic P TN E 100nF MIC N ES i Microphone n 100nF ine A 2 2k 82nH 4h MIC GND EE e PPS e Q X Connector 27pF 27pF ESD ESD Speaker sek P ENTE e e
107. 1 8V 3V SIM supply SIM DET 42 8 V SIM detect input Inner pull down 103 pA UART DSR 6 8 V DSR output Driver strength 6 mA RI 7 8 V RI output Driver strength 6 mA DCD 8 8 V DCD output Driver strength 6 mA DTR 9 8 V DTR input Internal pull up 55 pA RTS 0 8 V Flow ctrl input Internal pull up 31 pA CTS 1 8 V Flow ctrl output Driver strength 6 mA TXD 2 8 V Data input Internal pull up 102 pA RXD 3 8 V Data output Driver strength 5 mA UART AUX TXD AUX 29 8 V Data input Internal pull up 102 pA RXD_AUX 28 8 V Data output Driver strength 5 mA USB VUSB_DET ot Available USB_D Not Available USB_D Not Available SPI SPI_SCLK Not Available SPI_MOSI ot Available SPI_MISO ot Available SPI_SRDY ot Available SPI MRDY Not Available DDC lC SCL 27 SARA G340 SARA G350 1 8 V open drain Driver strength 3 mA SDA 26 SARA G340 SARA G350 1 8 V open drain Driver strength 3 mA UBX 13000995 R10 N 47 48 49 50 18 26 27 55 56 57 58 59 45 46 SARA G3 and SARA U2 series System Integration Manual LISA C2 series 8V 3V SIM clock upcoming FW releases 8V 3V SIM data upcoming FW releases Internal 10k pull up 8V 3V SIM reset upcoming FW releases 8V 3V SIM supply upcoming FW releases Not Available Not Available 1 8 V Rl output Driver strength 6 mA Not Available Not Available 8 V Flow
108. 1 8 V configurable GPIO Default GNSS RTC sharing Driver strength 6 mA Inner pull down 200 pA 1 8 V configurable GPIO Default SIM detection Driver strength 6 mA Inner pull down 200 pA 1 8 V configurable GPIO Default 12S1_RXD Driver strength 1 mA Inner pull down 150 pA 1 8 V configurable GPIO Default 12S1_TXD Driver strength 1 mA Inner pull down 150 pA 1 8 V configurable GPIO Default 12S1_CLK Driver strength 1 mA Inner pull down 150 pA 1 8 V configurable GPIO Default 1291 WA Driver strength 1 mA Inner pull down 150 pA 1 8 V configurable GPIO Default SPI SCLK Driver strength 6 mA Inner pull down 200 pA 1 8 V configurable GPIO Default SPI_MOSI Driver strength 6 mA Inner pull down 200 pA 1 8 V configurable GPIO Default SPI_MISO Driver strength 6 mA Inner pull down 200 pA Appendix Page 182 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Pin Name N SARA G3 series N LISA C2 series LISA U1 series GPIO13 Not Available 58 Not Available Not Available GPIO14 Not Available 59 Not Available Not Available Table 60 Summary of pin differences and compatibility level among modules UBX 13000995 R10 Early Production Information LISA U2 series 1 8 V configurable GPIO Default SPI SRDY Driver strength 6 mA Inner pull down 200 pA 1 8 V configurable GPIO Default SPI MRDY Driver strength 6 mA Inner pull down 200 pA Appendix Page 183 of 192 SARA
109. 1 9 1 4 and the u blox AT Commands Manual 3 Table 6 Module operating modes description SARA G3 and SARA U2 series System Integration Manual Transition between operating modes When the module is switched on by an appropriate power on event see 2 3 1 the module enters active mode from not powered or power off mode If power saving configuration is enabled by the AT UPSV command the module automatically switches from active to idle mode whenever possible and the module wakes up from idle to active mode in the events listed above see idle to active transition description When a voice call or a data call is initiated the module switches from active mode to connected mode When a voice call or a data call is initiated the module enters connected mode from active mode When a voice call or a data call is terminated the module returns to the active mode Figure 5 describes the transition between the different operating modes Switch ON Apply VCC Incoming outgoing call or other dedicated device network communication Connected No RF TX Rx in progress Call terminated Communication dropped Figure 5 Operating modes transition UBX 13000995 R10 Switch ON PWR ON RTC alarm Early Production Information Not powered Remove VCC Power off Switch OFF AT CPWROFF PWR ON SARA U2 If power saving is enabled and there is no activity for a defined time interval
110. 2 Qo ox SARA G3 and SARA U2 series System Integration Manual 2 14 SARA G350 ATEX integration in explosive atmospheres applications 2 14 1 General guidelines SARA G350 ATEX modules are certified as components intended for use in potentially explosive atmospheres see section 4 5 and see the Approvals section of the SARA G3 series Data Sheet 1 for further details with the following marking Ex II 1G Ex ia IIC IIB According to the marking stated above the SARA G350 ATEX modules are certified as electrical equipment of group Il intended for use in areas with explosive gas atmosphere other than mines susceptible to firedamp category 1G intended for use in zone O hazardous areas in which explosive atmospheres caused by mixtures of air and gases vapours or mists are continuously present for long periods or frequently so that the modules are also suitable for applications intended for use in zone 1 and zone 2 hazardous areas level of protection ia intrinsically safe apparatus with very high level of protection not capable of causing ignition in normal operation and with the application of one countable fault or a combination of any two countable fault plus those non countable faults which give the most onerous condition subdivision IIC IIB intended for use in areas where the nature of the explosive gas atmosphere is considered very dangerous based on the Maximum Experimental Safe Gap or the Minimum Ignition Current r
111. 40 and SARA G350 modules do not provide DC blocking capacitors at the MIC P MIC N input pins and provide supply output and local ground for an external microphone at the MIC_BIAS MIC_GND pins W Check digital audio requirements SARA G340 and SARA G350 modules provide a 4 wire 1 8 V interface supporting PCM and Normal 12S modes master role and fixed sample rate W Check internal active pull up down values at digital interface input pins and the current capability of digital interface output pins since they are slightly different between SARA G3 and LISA modules E 5E B 8 SS Check SARA G3 modules software requirements WY Not all of the functionalities available with LISA modules are supported by all the SARA G3 modules versions SARA G300 and SARA G310 modules do not support o Audio interfaces DDC lC interface Antenna detection interface GPIOs o Low power idle mode if a 32 kHz signal at EXT32K input pin is not provided o TCP IP UDP IP FTP HTTP o GNSS via Modem AssistNow clients Hybrid positioning and CellLocate functionalities o Jamming detection UBX 13000995 R10 Early Production Information Appendix Page 173 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual A 3 Software migration Software migration between SARA G3 and LISA cellular modules is a straightforward procedure Nevertheless there are some differences to be considered with firmware version Each cellular module supports AT commands
112. 402 1096 10V uF Capacitor Ceramic X5R 0402 10 6 3 V O uF Capacitor Ceramic X5R 0603 20 6 3 V 27 pF Capacitor Ceramic COG 0402 596 25 V O nF Capacitor Ceramic X5R 0402 1096 50V Low Capacitance ESD Protection Chip Ferrite Bead Noise EMI Suppression Filter 800 Ohm at 100 MHz 2700 Ohm at 1 GHz Microphone Connector Speaker Connector 2 2 kQ Electret Microphone 4 7 kO Resistor 0402 5 0 1 W 10 kO Resistor 0402 596 0 1 W 2 2 kO Resistor 0402 5 0 1 W 32 Q Speaker 16 Bit Mono Audio Voice Codec Part Number Manufacturer GRM155R71C104KA01 Murata GRM155R60J105KE19 Murata GRM188R60J106ME47 Murata GRM1555C1H270JZ01 Murata GRM155R71C103KA88 Murata CG0402MLE 18G Bourns BLM15HD182SN1 Murata Various manufacturers Various manufacturers Various manufacturers RC0402JR 074K7L Yageo Phycomp RC0402JR 0710KL Yageo Phycomp RC0402JR 072K2L Yageo Phycomp Various manufacturers MAX9860ETG Maxim Table 53 Example of components for connecting SARA U2 modules with an external audio codec to provide voice capability Figure 80 describes an application circuit example for connecting the l S digital audio interface of SARA G340 SARA G350 and SARA U2 modules to an external audio voice codec using the same parts listed in Table 53 The module s I S interface l S master is connected to the related pins of the external audio codec I S slave The V INT output supplies the external audio codec defining pro
113. 5 B 3 Schematic for SARA G3 and SARA U2 integration ees 187 SERCL ptr Em 188 Related GOcum ents Eee M 190 Revision hiStory cas Do M DD HE RCM EM EIE M MEE EOM 191 ROOT EE CE eer 192 UBX 13000995 R10 Early Production Information Contents Page 7 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual 1 System description 1 1 Overview SARA G3 series GSM GPRS cellular modules and SARA U2 series GSM EGPRS HSPA cellular modules are versatile solutions offering voice and or data communication over diverse radio access technologies in the same miniature SARA LGA form factor 26 x 16 mm that allows seamless drop in migration between the two SARA G3 and SARA U2 series and easy migration to u blox LISA U series GSM EGPRS HSPA modules LISA C2 series CDMA modules TOBY L1 series LTE modules and to TOBY L2 series GSM EGPRS DC HSPA LTE modules SARA G350 and SARA G340 are respectively quad band and dual band full feature GSM GPRS cellular modules with a comprehensive feature set including an extensive set of internet protocols and access to u blox GNSS positioning chips and modules with embedded A GPS AssistNow Online and AssistNow Offline functionality SARA G310 and SARA G300 are respectively quad band and dual band GSM GPRS cellular modules targeted for high volume cost sensitive applications providing GSM GPRS functionalities with a reduced set of additional features to minimize
114. 71 Example of USB line design with Z close to 90 Q and Z close to 30 Q for the described 2 layer board layup UBX 13000995 R10 Early Production Information Design in Page 126 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 2 6 4 DDC IC interface Se DDC lC interface is not supported by SARA G300 and SARA G310 modules 2 6 4 1 Guidelines for DDC I C circuit design General considerations The DDC l C bus master interface of SARA G340 SARA G350 and SARA U2 cellular modules can be used to communicate with u blox GNSS receivers and on SARA U2 modules only it can be also used to communicate with other external l C bus slaves as an audio codec Beside the general considerations reported below see the following parts of this section for specific guidelines for the connection to u blox GNSS receivers the section 2 7 2 for an application circuit example with an external audio codec l C bus slave To be compliant to the l C bus specifications the module bus interface pins are open drain output and pull up resistors must be mounted externally Resistor values must conform to I C bus specifications 15 for example 4 7 kQ resistors can be commonly used ee Connect the external DDC IC pull ups to the V INT 1 8 V supply source or another supply source enabled after V INT e g as the GNSS 1 8 V supply present in Figure 72 application circuit as any external signal connected to the DDC lC interface must
115. 76 7 2 85 6 236 8 900 2100 900 1800 1 1 9 F 1 o o o o o o o o o o o e SARA U280 5 76 7 2 850 1900 1 1 9 F 1 o o o o o o o o o SARA U290 5 132 900 2100 1 1 9 F 1 o o o o o o o o o o o o e E 32 kHz signal at EXT32K input pin is required for low power idle mode F Not supported by 00 FW versions Table 1 SARA G3 series and SARA U2 series features summary SARA G350 ATEX modules provide the same feature set of the SARA G350 modules plus the certification for use in potentially explosive SARA U290 modules include 00 and 60 FW versions SARA U290 60S is approved and locked for SoftBank Japanese network operator UBX 13000995 R10 Early Production Information System description Page 8 of 192 biox Table 2 reports a summary of 2G cellular characteristics of SARA G3 and SARA U2 series modules Item Protocol stack MS class Bands Power class PS data rate CS data rate Table 2 SARA G3 series and SARA U2 series 2G characteristics summary SARA U260 3GPP Release 7 Class B GSM 850 MHz PCS 1900 MHz Class 4 33 dBm for 850 band Class 1 30 dBm for 1900 band GPRS multi slot class 12 CS 1 4 85 6 kb s DL CS 1 4 85 6 kb s UL EDGE multi slot class 12 MCS 1 9 236 8 kb s DL MCS 1 4 70 4 kb s UL Up to 9 6 kb s DL UL Transparent mode Non transparent mode SARA G3 and SARA U2 series System Integration Manual SARA U270 3GPP Release 7 Class B E GSM 900 MHz DCS 18
116. 95 R10 Early Production Information System description Page 24 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Figure 12 roughly describes the current consumption profile of SARA G300 and SARA G310 modules when the EXT32K input pin is fed by the 32K OUT output pin provided by these modules when power saving is enabled The module is registered with the network automatically enters the low power idle mode and periodically wakes up to active mode to monitor the paging channel for paging block reception Current mA 100 60 120 mA 50 IDLE MODE 0 44 2 09 s Time s ACTIVE MODE Current mA 20 30 ms 100 60 120 mA 50 20 40 mA Active Mode RX DSP Idle Mode Time ms Enabled Enabled Enabled Enabled o gt 20 30 ms IDLE MODE ACTIVE MODE IDLE MODE Figure 12 VCC current consumption profile versus time of the SARA G300 and SARA G310 modules with the EXT32K input pin fed by the 32K_OUT output pin provided by these modules when registered with the network with power saving enabled the low power idle mode is reached and periodical wake up to active mode are performed to monitor the paging channel For detailed current consumption values with the module registered with 2G or 3G network with power saving enabled cyclic idle active mode see SARA G3 series Data Sheet 1 and SARA U2 series Data Sheet 2 UBX 13000995 R10 Early Production Information System descri
117. 995 R10 Early Production Information Design in Page 130 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual Figure 75 shows an application circuit example for connecting a SARA U2 cellular module to a u blox 3 0 V GNSS receiver As the SDA and SCL pins of the SARA U2 cellular module are not tolerant up to 3 0 V the connection to the related l C pins of the u blox 3 0 V GNSS receiver must be provided using a proper l C bus Bidirectional Voltage Translator e g TI TCA9406 which additionally provides the partial power down feature so that the GNSS 3 0 V supply can be ramped up before the V INT 1 8 V cellular supply with proper pull up resistors The GPIO2 is connected to the active high enable pin of the voltage regulator that supplies the u blox 3 0 V GNSS receiver providing the GNSS supply enable function A pull down resistor is provided to avoid a Switch on of the positioning receiver when the cellular module is switched off or in the reset state As the GPIO3 and GPIOA pins of the SARA U2 cellular modules are not tolerant up to 3 0 V the connection to the related pins of the u blox 3 0 V GNSS receiver must be provided using a proper Unidirectional General Purpose Voltage Translator e g Tl SN74AVC2T245 which additionally provides the partial power down feature so that the 3 0 V GNSS supply can be also ramped up before the V INT 1 8 V cellular supply The V BCKP supply output of the cellular module can be direct
118. 995 R10 Early Production Information Design in Page 129 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual Connection with u blox 3 0 V GNSS receivers Figure 74 shows an application circuit example for connecting a SARA G340 or a SARA G350 cellular module to a u blox 3 0 V GNSS receiver The SDA and SCL pins of SARA G340 SARA G350 are directly connected to the related pins of the u blox 3 0 V GNSS receiver with appropriate pull up resistors connected to the 3 0 V GNSS supply enabled after the V INT supply of the C pins of the cellular module An l C bus Voltage Translator is not needed because the SARA G340 SARA G350 DDC IC pins are capable up to 3 3 V The GPIO2 is connected to the active high enable pin of the voltage regulator that supplies the u blox 3 0 V GNSS receiver providing the GNSS supply enable function A pull down resistor is provided to avoid a switch on of the positioning receiver when the cellular module is switched off or in the reset state As the GPIO3 and GPIO4 pins of SARA G340 SARA G350 cellular modules are not tolerant up to 3 0 V the connection to the related pins of the u blox 3 0 V GNSS receiver must be provided using a proper Unidirectional General Purpose Voltage Translator e g Tl SN74AVC2T245 which additionally provides the partial power down feature so that the 3 0 V GNSS supply can be also ramped up before the V INT 1 8 V cellular supply The V BCKP supply output of S
119. A G350 SARA G340 SARA G350 SARA G340 SARA G350 SARA G340 SARA G350 SARA G340 SARA G350 SARA G340 SARA G350 SARA G340 SARA G350 SARA U2 SARA G340 SARA G350 SARA U2 SA SA SA SA SA SA SA RA G340 RA G350 RA U2 RA G340 RA G350 RA U2 RA U2 Pin No 46 47 48 49 44 45 36 37 35 34 19 1 0 O VO VO O VO O VO SARA G3 and SARA U2 series System Integration Manual Description Microphone supply output Microphone analog reference Differential analog audio input negative Differential analog audio input positive Differential analog audio output positive Differential analog audio output negative PS clock GPIO PS receive data GPIO PS transmit data GPIO PS word alignment GPIO Clock output Early Production Information Remarks Supply output 2 2 V typ for external microphone See sec See sec ion 1 10 1 for functional description ion 2 7 1 for external circuit design in Local ground for the external microphone reference for the analog audio uplink path See sec See sec Differen shared handset No inter See sec See sec Differen shared f handset No inter See sec See sec Differen shared earpiece See sec See sec Differen shared earpiece See sec See sec ion 2 7 ial analog audio signal ion 1 10 1 for functional description for external
120. A G350 ATEX module in an application device intended for use in potentially explosive atmospheres Total internal capacitance Ci 103 pF Total internal inductance Li 4 1 uH The module does not contain blocks which increase the voltage e g like step up duplicators boosters etc The nameplate of SARA G350 ATEX modules is described in the Product labeling section of the SARA G3 series Data Sheet 1 Additional information can be found on the SARA G350 ATEX modules certificate of compliancy for use in potentially explosive atmospheres available on our website www u blox com ee The final enclosure of the application device integrating SARA G350 ATEX modules intended for use in potentially explosive atmospheres must guarantee a minimum degree of ingress protection of IP20 2 14 2 Guidelines for VCC supply circuit design The power supply ratings average and pulse must be considered in the design of the VCC supply circuit on the application device integrating SARA G350 ATEX module implementing proper circuits providing adequate maximum voltage and current to the VCC supply input of SARA G350 ATEX modules according to the specific potentially explosive gas atmosphere category subdivision where the apparatus is intended for use The following maximum input and equivalent parameters must be considered in gas sub division IIC Ui 2 3 8V li 1 6 A burst Pi 2 5 W Ci 103 pF Li 2 4 1 uH The following maximum input and equi
121. A U2 series Rising edge on the VCC pins toa Rising edge on the VCC pins toa Rising edge on the VCC pins toa Rising edge on the VCC pins to a valid voltage as module supply valid voltage as module supply valid voltage as module supply valid voltage as module supply with PWR ON pin permanently low when VCC is applied Low level on the PWR ON pin Low pulse on the PWR ON pin Low pulse on the PWR ON pin Low pulse on the PWR ON pin for appropriate time period for appropriate time period for appropriate time period for appropriate time period Pre programmed RTC alarm not Pre programmed RTC alarm Pre programmed RTC alarm supported by SARA G300 G310 RESET N input pin released RESET N input pin released from the low level from the low level Table 59 Summary of power on events among modules The same compatible external power on circuit can be implemented for SARA and LISA modules even if there are minor differences in the PWR ON input voltage levels ranges and in the low level time or low pulse time to switch on the module as reported in Table 60 or in the relative datasheet of the module 1 4 5 6 PWR ON falling edge i e low pulse is required for LISA series but it is not required for SARA External pull up is not needed for LISA C2 series since internal pull up is provided Module power off SARA and LISA modules can all be properly switched off by means of the AT CPWROFF command Additionally all LISA U2 modules except LISA U200 00S
122. ARA G310 modules are not equipped with an internal 32 768 kHz crystal a proper 32 kHz signal must be provided at the EXT32K input pin of the modules to give the RTC clock reference and to provide the RTC functions as well as to reach the very low power idle mode with power saving configuration enabled by AT UPSV The 32K OUT output pin of SARA G300 and SARA G310 provides a 32 kHz reference signal suitable only to feed the EXT32K input pin furnishes the reference clock for the RTC and allows low power idle mode and RTC functions support with modules switched on UBX 13000995 R10 Early Production Information System description Page 12 of 192 VP biox 1 3 Pin out SARA G3 and SARA U2 series System Integration Manual Table 4 lists the pin out of the SARA G3 and SARA U2 series modules with pins grouped by function Function Pin Name Power vcc GND V_BCKP V_INT System PWR_ON RESET_N EXT32K 32K_OUT Antenna ANT ANT_DET UBX 13000995 R10 Module All All All All All All SARA G300 SARA G310 SARA G300 SARA G310 All SARA G340 SARA G350 SARA U2 Pin No 51 52 53 1 3 5 14 20 22 30 32 43 50 54 55 57 61 63 96 2 4 15 18 31 24 56 62 1 0 N A D VO VO Description Module supply input Ground Real Time Clock supply input output Generic Digital Interfaces supply output Power on input External reset input 32 kHz input
123. ARA G340 SARA G350 is directly connected to the V BCKP backup supply input pin of the u blox 3 0 V GNSS receiver as in the application circuit for a u blox 1 8 V GNSS receiver u blox GNSS M SARA G340 SARA G350 3 0 V receiver V BCKP 4 vy BcKP GNSS LDO 3V0 Regulator VMAIN vcc ly OUT N a _ GNSS supply enabled 3V0 3v0 C1 SHDN GPIO2 R3 SDA2 SCL2 4 rd sc Unidirectional 3v0 Voltage Translator 1v8 T TP VCCA VCCB o M EM V_INT a N oll 3 a DIR1 TxD1 gt Ai gi LL ON data ready AIETE GPIO3 EXTINTO 4 42 B2 CQNSS RIC sharing MEE GPIO4 DIR2 OE GND U2 Figure 74 Application circuit for connecting SARA G3 modules to u blox 3 0 V GNSS receivers Reference Description Part Number Manufacturer R1 R2 4 7 kQ Resistor 0402 596 0 1 W RC0402JR 074K7L Yageo Phycomp R3 47 kQ Resistor 0402 596 0 1 W RC0402JR 0747KL Yageo Phycomp 2 3 100 nF Capacitor Ceramic X5R 0402 1096 10V GRM155R71C104KA01 Murata U1 Voltage Regulator for GNSS receiver See GNSS receiver Hardware Integration Manual U2 Generic Unidirectional Voltage Translator SN74AVC2T245 Texas Instruments Table 48 Components for connecting SARA G3 modules to u blox 3 0 V GNSS receivers UBX 13000
124. C3 C4 47 pF Capacitor Ceramic COG 0402 596 50 V GRM1555C1H470JAO01 Murata C5 100 nF Capacitor Ceramic X7R 0402 1096 16 V GRM155R71C104KA01 Murata U1 SIM chip M2M UICC Form Factor Various Manufacturers Table 37 Example of components for the connection to a single solderable SIM chip with SIM detection not implemented UBX 13000995 R10 Early Production Information Design in Page 114 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual Guidelines for single SIM card connection with detection er SIM card detection is not supported by SARA G300 00S and SARA G310 00S modules An application circuit for the connection to a single removable SIM card placed in a SIM card holder is described in Figure 57 where the optional SIM card detection feature is implemented Follow these guidelines connecting the module to a SIM connector implementing SIM presence detection Connect the UICC SIM contacts C1 VCC and C6 VPP to the VSIM pin of the module Connect the UICC SIM contact C7 I O to the SIM_IO pin of the module Connect the UICC SIM contact C3 CLK to the SIM_CLK pin of the module Connect the UICC SIM contact C2 RST to the SIM_RST pin of the module Connect the UICC SIM contact C5 GND to ground Connect one pin of the mechanical switch integrated in the SIM connector as the SW2 pin in Figure 57 to the SIM DET input pin providing a weak pull down resistor e g 470 kQ as R2 in Figure 57 Con
125. CC C1 SIM 10 KEIN e e 10 C7 SIM CLK KEIN CLK C3 SIM RST E e E RST C2 SIM Card Bottom View GND C5 1 C2 C3 C4 C5 pi pol p3 p4 Kd eere J Figure 57 Application circuit for the connection to a single removable SIM card with SIM detection implemented Reference Description Part Number Manufacturer C1 C2 C3 CA 47 pF Capacitor Ceramic COG 0402 596 50 V GRM1555C1H470JA01 Murata C5 100 nF Capacitor Ceramic X7R 0402 1096 16 V GRM155R71C104KA01 Murata D1 D6 Very Low Capacitance ESD Protection PESD0402 140 Tyco Electronics R1 1 kO Resistor 0402 596 0 1 W RC0402JR 071KL Yageo Phycomp R2 470 kQ Resistor 0402 5 0 1 W RC0402JR 07470KL Yageo Phycomp Ji SIM Card Holder Various Manufacturers 6 2 positions with card presence switch CCMO03 3013LFT R102 C amp K Components Table 38 Example of components for the connection to a single removable SIM card with SIM detection implemented UBX 13000995 R10 Early Production Information Design in Page 115 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Guidelines for dual SIM card chip connection Two SIM card chip can be connected to the modules SIM interface as described in the circuit of Figure 58 SARA G3 and SARA U2 modules do not support the usage of two SIM at the same time but two SIM can be populated on the application board providing a proper switch to connect only the first SIM
126. CKP to provide a long buffering time This capacitor holds V BCKP voltage within its valid range for around 70 s SARA G3 series or for around 40 s SARA U2 series at 25 C after the VCC supply is removed If a very long buffering time is required a 70 mF super capacitor e g Seiko Instruments XH414H IVO1E can be placed at V BCKP with a 4 7 KQ series resistor to hold the V BCKP voltage within its valid range for 13 hours SARA G3 series or for 8 hours SARA U2 series at 25 C after the VCC supply is removed The purpose of the series resistor is to limit the capacitor charging current due to the large capacitor specifications and also to let a fast rise time of the voltage value at the V BCKP pin after VCC supply has been provided These capacitors allow the time reference to run during battery disconnection a SARA G3 series b SARA G3 series c SARA G3 series SARA U2 series SARA U2 series SARA U2 series EE Vv BCKP EB v Bckp D V BCKP ds R2 le D3 de de T 3 superCap Figure 44 Real time clock supply V BCKP application circuits a using a 100 pF capacitor to let the RTC run for 1 minute after VCC removal b using a 70 mF capacitor to let RTC run for 10 hours after VCC removal c using a non rechargeable battery Reference Description Part Number Manufacturer C1 100 uF Tantalum Capacitor GRMA3SR60J107M Murata R2 4 7 kQ Resistor 0402 5 0 1 W RC0402JR
127. D Audio Amplifier in the circuit described in Figure 77 Provide proper parts on each line connected to the external loudspeaker as noise and EMI improvements to minimize RF coupling according to EMC requirements of the custom application o Mount a 27 pF bypass capacitor e g Murata GRM1555C1H270J from each loudspeaker line to solid ground plane C6 and C7 capacitors in Figure 77 Provide additional ESD protection e g Bourns CGO402MLE 18G varistor if the analog audio lines will be externally accessible on the application device according to the EMC ESD requirements of the custom application The protection should be mounted close to an accessible point of the line D1 D4 parts in the circuit described in Figure 77 UBX 13000995 R10 Early Production Information Design in Page 135 of 192 i Q biox SARA G3 and SARA U2 series System Integration Manual Figure 77 Analog audio interface hands free mode application circuit Reference C1 C10 C2 C3 C11 C4 C5 C6 C7 C8 C9 D1 D2 D3 D4 Ji J2 L1 L2 LSPK IC R1 R2 R3 R4 R5 R6 U1 Description 10 pF Capacitor Ceramic X5R 0603 20 6 3 V 100 nF Capacitor Ceramic X7R 0402 10 16 V 27 pF Capacitor Ceramic COG 0402 5 25 V 47 nF Capacitor Ceramic X7R 0402 10 16V Low Ca
128. EXT32K pin of SARA G300 G310 modules to let idle mode that otherwise cannot be reached this is not needed for the other SARA G3 and SARA U2 series modules UBX 13000995 R10 Early Production Information Module processor core runs with 26 MHz reference generated by the internal oscillator Voice or data call enabled and processor core runs with 26 MHz reference Transition between operating modes When VCC supply is removed the module enters not powered mode When in not powered mode the modules cannot be switched on by PWR ON RESET N or RTC alarm When in not powered mode the modules can be switched on applying VCC supply see 2 3 1 so that the module switches from not powered to active mode When the module is switched off by an appropriate power off event see 1 6 2 the module enters power off mode from active mode When in power off mode the modules can be switched on by PWR ON RESET N or RTC alarm see 2 3 1 the module switches from power off to active mode When VCC supply is removed the module switches from power off mode to not powered mode The module automatically switches from active mode to idle mode whenever possible if power saving is enabled see sections 1 5 1 4 1 9 1 4 and to the u blox AT Commands Manual 3 AT UPSV The module wakes up from idle to active mode in the following events Automatic periodic monitoring of the paging channel for the paging block reception according to network conditi
129. Extended op range Extended op range 3 00 V 4 5V Not applicable 3 1V 42V 3 1V 45V High pulse current No high pulse current High pulse current High pulse current due to GSM TDMA due to CDMA due to GSM TDMA due to GSM TDMA V_BCKP 2 Output characteristics 2 Not Available Output characteristics Output characteristics 2 3 V typ 2 mA max 2 3 V typ 3 mA max 8 V typ 3 mA max Input op range Input op range Input op range 10V 24V 1 0V 2 5V OV 1 9V V_INT 4 Output characteristics 4 Output characteristics Output characteristics Output characteristics 1 8 V typ 50 mA max 1 8 V typ 50 mA max 1 8 V typ 50 mA max 8 V typ 50 mA max Antenna ANT 56 RF input output for Tx Rx 68 RF input output for RF input output for RF input output for antenna Tx Rx antenna Tx Rx antenna main Tx Rx antenna ANT DIV Not Available 74 Not Available Not Available LISA U230 only RF input for Rx diversity antenna ANT DET 62 SARA G340 SARA G350 Not Available Internal antenna Internal antenna Input for antenna detection circuit detection circuit detection circuit System PWR ON 15 No internal pull up 19 180 KQ internal pull up No internal pull up No internal pull up L level 0 10 V 0 65 V L level 0 30 V 0 30 V L level 0 30 V 0 65V L level 0 30 V 0 65 V H level 2 00 V 4 50 V H level 2 00 V 4 70V Hdevel 2 00 V 4 50 V HHevel 1 50 V 4 40 V ON L level time ON L level pulse time ON L level pulse time ON L level pulse time 5 ms min 150 ms min 5 ms
130. G3 and SARA U2 series System Integration Manual biox B Migration between SARA G3 and SARA U2 B 1 Overview SARA G3 and SARA U2 series cellular modules have exactly the same SARA form factor 26 0 x 16 0 mm LGA with exactly the same 96 pin layout as described in Figure 91 so that the modules can be alternatively mounted on a single application board using exactly the same copper mask solder mask and paste mask LE Im u bm au 8 aOoooor caoa aoa a oooaonorcaoa qa a Bagaar asna zzuzzzzzzzzzzz zzzzzzzzzzzrz 22222222222 oococuoo0oouuouuoaxuu oo a ououoououuoaxuu uuo ax uouo0uo0oooa xuugu I II I II al 2 pps GND EE EB vcc GND EE EB vcc GND EE EJ vcc V_BCKP EN E El El El EA vcc v BCKP EI E El El El EA vcc v ECKP EN E El El El EA vcc EmmgmpgmmmmgE Hapa oon vag E E mium V_INT GND V_INT GND V_INT GND GND ERI E Rsvp GND ES EJ vc GND ERI EJ Rsvp DSR NN EJ Rsvp DSR i EJ mcn DSR E EJ Rsvp RI RSVD RI MIC_GND RI RSVD pcp El c Ed Rsvp Dco El El E wc ss Do El Ee Ed 5v DTR E SARA G300 Eg Rsvp DTR NI SARA G340 EB sPx_n DTR EE Eg Rsvp RTS ET EJ Rsvp RTS ET ES RTS KT SARA U2 EB Rsvp cts i SARA G310 EER cw cts i SARA G350 EER cw cts EEE s ES cw TxD KE ES sw prr TXD Er i EA sw prr TxD EE Top View ES sw rr RXD KENN Top View EB vsm RXD KENN Top View EB vsm RXD EW ES vsiv GND RZ B E EJ sw ns GND EN Bl E KE sw ns GND EZ B El E sw nir
131. G3 modules increasing the RESET_N input voltage range Refer to the SARA G3 series Data Sheet 1 and the SARA U2 series Data Sheet 2 for the detailed electrical characteristics of the RESET_N input SARA G3 series SARA U2 series V_INT Baseband V_BCKP Power Baseband EN Processor D Management Processor 10k 10k RESET N E Reset RESET N KEll e Reset p Reset Figure 21 RESET N input description When a low level is applied to the RESET N input it causes an external or hardware reset of the modules with the following behavior of SARA G3 and SARA U2 series modules due to different internal circuits SARA G3 modules reset of the processor core excluding the Power Management Unit and the RTC block The V INT generic digital interfaces supply is switched on and each digital pin is set in its internal reset state The V BCKP supply and the RTC block are switched on SARA U2 modules reset of the processor core and the Power Management Unit excluding the RTC block The V INT generic digital interfaces supply is switched off and all digital pins are tri stated not supplied The V BCKP supply and the RTC block are switched on ee Before the switch on of the generic digital interface supply source V_INT of the module no voltage driven by an external application should be applied to any generic digital interface of
132. G340 SARA G350 and LISA series A 1 8 V DDC l C bus compatible interface is provided to communicate with u blox GNSS receivers UBX 13000995 R10 Early Production Information Appendix Page 177 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual SARA G300 SARA G310 and LISA U200 00S modules do not support the DDC IC interface LISA C2 modules will support the DDC I C interface in the upcoming firmware releases All LISA U2 modules except LISA U200 00S additionally support the communication with I C slaves by means of dedicated AT commands other than u blox positioning receivers over the same DDC P C interface A 4 6 Audio interfaces Analog audio interfaces Differential analog audio input is provided on the MIC P MIC N pins of SARA G340 SARA G350 modules without internal DC blocking capacitor and LISA C2 series LISA U120 and LISA U130 modules with an internal DC blocking capacitor Supply output and local ground for an external microphone is provided on the MIC BIAS MIC GND pins of SARA G340 SARA G350 modules only the supply for an external microphone has to be provided by an external LDO linear regulator with the other modules Differential analog audio output is provided on the SPK P SPK N pins of SARA G340 SARA G350 LISA U120 LISA U130 modules 16 ohm load capable and LISA C2 series modules 32 ohm load capable SARA G300 SARA G310 LISA U100 U110 LISA U200 00S modules do not provi
133. Integration Manual 2 3 2 2 Guidelines for RESET N layout design The reset circuit RESET N requires careful layout due to the pin function ensure that the voltage level is well defined during operation and no transient noise is coupled on this line otherwise the module might detect a spurious reset request It is recommended to keep the connection line to RESET N as short as possible 2 3 3 32 kHz signal EXT32K and 32K OUT n d The EXT32K and 32K OUT pins are not available on SARA G340 SARA G350 and SARA U2 modules 2 3 3 1 Guidelines for EXT32K and 32K OUT circuit design The application circuit of Figure 47 describes how the 32K OUT output pin of SARA G300 SARA G310 modules can be connected to the EXT32K input pin providing the 32 kHz signal which constitutes the Real Time Clock RTC reference clock so that the modules can enter the low power idle mode reaching low current consumption figures refer to the section 1 5 1 4 and to the SARA G3 series Data Sheet 1 and can provide the RTC functions when the module is switched on SARA G300 SARA G310 EJ 32K our LEE ExT32K Figure 47 EXT32K application circuit using the 32 kHz signal provided by the 32K OUT output The application circuit of Figure 48 and Table 31 describe how an external oscillator can be connected to the EXT32K input pin of SARA G300 SARA G310 modules providing the external 32 kHz signal which constitutes the RTC reference clock so that th
134. MC ESD immunity requirements as defined by CENELEC EN 61000 4 2 ETSI EN 301 489 1 301 489 7 301 489 24 2 13 2 ESD immunity test of u blox SARA G3 and SARA U2 reference designs EMC certification tests including ESD immunity have been successfully performed on the u blox SARA G3 and SARA U2 reference designs according to applicable European Norms see Table 56 as required for customized devices integrating the modules for R amp TTED and European Conformance CE mark The EMC ESD approved u blox reference designs consist of a SARA G3 or a SARA U2 module soldered onto a motherboard which provides supply interface SIM card headset and communication port An external cellular antenna is connected to an SMA connector provided on the motherboard Since an external antenna is used the antenna port can be separated from the enclosure port The reference design is not enclosed in a box so that the enclosure port is not indentified with physical surfaces Therefore some test cases cannot be applied Only the antenna port is identified as accessible for direct ESD exposure UBX 13000995 R10 Early Production Information Design in Page 147 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Table 57 reports the u blox SARA G3 and SARA U2 reference designs ESD immunity test results according to the CENELEC EN 61000 4 2 18 ETSI EN 301 489 1 19 301 489 7 20 301 489 24 21 test requirements Category Application Immunity
135. NT sssssssssssesee eene kniee tatt EAEE eher e rene nr eser e EEEE EREEREER sse EEEE Eeee 37 1 7 2 Antenna detection interface ANT DET sssssssseeenm eee eene nennen nnne eee e enne 38 UE SINTON ACO RR s 38 1 8 1 AU SIMI card Interface osrin t attente bite rire ru EAA sive Shad Ee Adde 38 1 8 2 SIM card detection interface SIM DET mene attt EEEE enen eene aeee enis 38 L9 SenaliMernlates REEERETR E P EM 39 1 9 1 Asynchronous serial interface UART ccccccccccsccccssecccsecesetecsseeccseeecseeecsseeccsaeecsesesstesesieeseaaeesns 39 1 9 2 Auxiliary asynchronous serial interface UART AUX isses eene 52 1 9 3 WI SBC ACE castrate tetas mets cele es es aac M ILLINS ELA eaten tl 52 192 DDC PC interface aera re eae A eT Ee NEU e EE 54 1 10 PANU To font a 1a aE ee ete e Hed E uisi 56 1 10 1 Analog audio interface issnin i kannan eene ns 56 1 10 2 Digital audio interface ssssssssssssssssseeeee eee nre nens 58 1 10 3 Voice band processing system ee ener ener nnne nnns 60 1 11 General Purpose Input Output GPIO ssssssssssssssseeee eene eene eene 63 1 12 Reserved IMS RS VD sus atttem iter NOE HAIR I UD NM CIIM DD ACRES 67 1 13 System feature Ssnan annaia Da reaS ana EA ESEE EEE A a 68 1 13 1 Network indication iissssssssssssseseeene RI m nennen nnnm nnne nene nnne s sse sene nn nsns sse sanete nnn sn nl ie 68 133 2 Antenna detection ee feet eere t etatis et dte aE aa
136. RA G340 SARA G350 SARA U2 series a valid 32 kHz signal must be properly provided to the EXT32K input pin of the SARA G300 and SARA G310 modules to let low power idle mode that otherwise cannot be reached by these modules When the power saving configuration is enabled and the module is registered or attached to a network the module automatically enters the low power idle mode whenever possible but it must periodically monitor the paging channel of the current base station paging block reception in accordance to the 2G or 3G system requirements even if connected mode is not enabled by the application When the module monitors the paging channel it wakes up to the active mode to enable the reception of paging block In between the module switches to low power idle mode This is known as discontinuous reception DRX The module processor core is activated during the paging block reception and automatically switches its reference clock frequency from 32 kHz to the 26 MHz used in active mode The time period between two paging block receptions is defined by the network This is the paging period parameter fixed by the base station through broadcast channel sent to all users on the same serving cell In case of 2G radio access technology the paging period varies from 470 8 ms DRX 2 length of 2 x 51 2G frames 2 x 51 x 4 615 ms up to 2118 4 ms DRX 9 length of 9 x 51 2G frames 9 x 51 x 4 615 ms In case of 3G radio access technology t
137. SARA G3 modules m RSVD GPIO1 Mount for SARA U2 modules i L Mount for SARA G300 SARA G310 modules i L Mount for SARA G340 SARA G350 modules i i C Mount for SARA G340 SARA G350 SARA U2 modules RSVD SPK_P RSVD RSVD SPK_N Figure 95 Example of complete schematic diagram to integrate SARA G3 and SARA U2 modules on the same application board UBX 13000995 R10 Early Production Information Appendix Page 187 of 192 biox C Glossary 3GPP ADC AP AT CS CSD CTS DC DCD DCE DCS DDC DL DRX DSP DSR DTE DTM DTR EMC EMI Q UBX 13000995 R10 SARA G3 and SARA U2 series System Integration Manual 3rd Generation Partnership Project Analog to Digital Converter Application Processor AT Command Interpreter Software Subsystem or attention Coding Scheme Circuit Switched Data Clear To Send Direct Current Data Carrier Detect Data Communication Equipment Digital Cellular System Display Data Channel interface Down link Reception Discontinuous Reception Digital Signal Processing Data Set Ready Data Terminal Equipment Dual Transfer Mode Data Terminal Ready Electro magnetic Compatibility Electro magnetic Interference Electro static Discharge Equivalent Series Resistance Front End Module Firmware Over AT commands File Transfer Protocol FTP Secure Firmware Gaussian Minimum Shift Keying modulation Ground Global Navigation Satelli
138. SD Protection CG0402MLE 18G Bourns R1 R2 24 kQ Resistor 0402 5 0 1 W RC0402JR 0724KL Yageo Phycomp R3 3 3 kQ Resistor 0402 5 0 1 W RC0402JR 073K3L Yageo Phycomp R4 1 0 kQ Resistor 0402 5 0 1 W RC0402JR 071KOL Yageo Phycomp U1 Single Cell Li lon or Li Polymer Battery Charger IC L6924U STMicroelectronics for USB port and AC Adapter Table 26 Suggested components for Li lon or Li Polymer battery charging application circuit 2 2 1 8 Guidelines for external battery charging and power path management circuit Application devices where both a permanent primary supply charging source e g 12 V and a rechargeable back up battery e g 3 7 V Li Pol are available at the same time as possible supply source should implement a suitable charger regulator with integrated power path management function to supply the module and the whole device while simultaneously and independently charging the battery Figure 42 reports a simplified block diagram circuit showing the working principle of a charger regulator with integrated power path management function This component allows the system to be powered by a permanent primary supply source e g 12 V using the integrated regulator which simultaneously and independently recharges the battery e g 3 7 V Li Pol that represents the back up supply source of the system the power path management feature permits the battery to supplement the system current requirements when the primary supply s
139. SP core of SARA U2 modules is summarized in Figure 29 Uplink Digital Gain To Radio TX 12S_RXD 12Sx RX Tone Generator Sidetone Scal_Rec Digital Gain Speech level From 12S_TXD 12Sx TX Radio RX Switch Legend UBF Uplink Biquad Filter DBF Downlink Biquad Filter Figure 29 SARA U2 modules audio processing system block diagram UBX 13000995 R10 Early Production Information System description Page 61 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual SARA U2 modules audio signal processing algorithms are Speech encoding uplink and decoding downlink The following speech codecs are supported in firmware on the DSP for speech encoding and decoding GERAN GMSK codecs o GSM HR GSM Half Rate GSM FR GSM Full Rate GSM EFR GSM Enhanced Full Rate HR AMR GSM Half Rate Adaptive Multi Rate Narrow Band FR AMR GSM Full Rate Adaptive Multi Rate Narrow Band o FRAMR WB GSM Full Rate Adaptive Multi Rate Wide Band UTRAN codecs o UMTS AMR2 UMTS Adaptive Multi Rate version 2 Narrow Band o UMTS AMR WB UMTS Adaptive Multi Rate Wide Band Mandatory sub functions o Discontinuous transmission DTX GSM 46 031 46 041 46 081 and 46 093 standards o Voice activity detection VAD GSM 46 032 46 042 46 082 and 46 094 standards o Background noise calculation GSM 46 012 46 022 46 062 and 46 092 standards Function configurable via specific AT c
140. SR DCD and DTR functions Table 60 and the module s datasheet 1 4 5 6 report minor differences in the internal pull ups and drivers strengths These are the default settings of the UART interfaces SARA G3 modules automatic baud rate and frame format detection LISA U2 except LISA U200 00S modules one shot automatic baud rate and frame format detection LISA C2 LISA U1 and LISA U200 00S modules 115200 b s baud rate and 8N1 frame format For further details regarding UART interface settings see the module s datasheet 1 4 5 6 and to the related AT commands manual of the module 3 9 UART AUX interface Only the SARA G3 modules provide an auxiliary UART interface for FW upgrade using the u blox EasyFlash tool and for diagnostic purpose LISA modules do not provide an auxiliary UART interface USB interface SARA G3 modules do not provide a USB interface such as is available on LISA U modules High Speed USB 2 0 for AT command data communication FW upgrade over AT or using the u blox EasyFlash tool and for Trace log capture and on LISA C2 modules Full Speed USB 2 0 for AT command Data communication FW upgrade SPI interface SARA G3 and LISA C2 modules do not provide an SPI interface such as is available on LISA U modules 5 wire IPC interface for AT command data communication MUX functionality FW upgrade over AT DDC IC interface The same compatible external circuit can be implemented for SARA
141. System description Page 65 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Pin disabled All the GPIOs can be configured in tri state with an internal active pull down enabled as a not used pin setting the parameter gpio mode of UGPIOC AT command to 255 The Pin disabled mode can be provided on more than one pin per time it is possible to simultaneously set the same mode on another pin also on all the GPIOs The pin configured to provide the Pin disabled function is set as o Tri State with an internal active pull down enabled Table 13 describes the configurations of all SARA G340 SARA G350 and SARA U2 modules GPIO pins Pin Module Name Description Remarks 16 SARA G340 GPIO1 GPIO By default the pin is configured as Pin disabled SARA G350 Can be alternatively configured by the AT UGPIOC command as Output Input Network Status Indication GNSS Supply Enable GSM Tx Burst Indication SARA U260 GPIO1 GPIO By default the pin is configured as Pin disabled SARA U270 Can be alternatively configured by the AT UGPIOC command as Output Input Network Status Indication GNSS Supply Enable GSM Tx Burst Indication Module Status Indication SARA U280 GPIO1 GPIO By default the pin is configured as Pin disabled SARA U290 Can be alternatively configured by the AT UGPIOC command as Output Input Network Status Indication GNSS Supply Enable Module Status Indication 23 SARA G340 GPIO2 GPIO By def
142. T245 Texas Instruments Table 49 Components for connecting SARA U2 modules to u blox 3 0 V GNSS receivers UBX 13000995 R10 Early Production Information Design in Page 131 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual For additional guidelines regarding the design of applications with u blox 3 0 V GNSS receivers see the GNSS Implementation Application Note 24 and to the Hardware Integration Manual of the u blox GNSS receivers 2 6 4 2 Guidelines for DDC lC layout design The DDC IC serial interface requires the same consideration regarding electro magnetic interference as any other digital interface Keep the traces short and avoid coupling with RF line or sensitive analog inputs since the signals can cause the radiation of some harmonics of the digital data frequency UBX 13000995 R10 Early Production Information Design in Page 132 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 2 7 Audio interface 2 7 1 Analog audio interface CS SARA G300 SARA G310 and SARA U2 modules do not provide analog audio interface 2 7 1 1 Guidelines for microphone and speaker connection circuit design headset handset modes SARA G340 and SARA G350 modules provide one analog audio input path and one analog audio output path the same paths are used for both headset and handset modes so that basically the same application circuit can be implemented for both headset and handset modes Fi
143. TXD RXD RTS and CTS lines are provided as implemented in Figure 63 and in Figure 64 and if HW flow control is enabled AT amp K3 default setting the power saving can be activated in this way AT UPSV 1 the module automatically enters the low power idle mode whenever possible and the UART interface is periodically enabled as described in section 1 9 1 4 reaching low current consumption With this configuration when the module is in idle mode data transmitted by the DTE will be buffered by the DTE and will be correctly received by the module when active mode is entered If the HW flow control is disabled AT amp KO it is recommended to enable the power saving in this way AT UPSV 2 the module automatically enters the low power idle mode whenever possible and the UART interface is enabled by the RTS line as described in section 1 9 1 4 reaching very low current consumption With this configuration when the module is in idle mode the UART is re enabled 20 ms after RTS has been set ON and the recognition of subsequent characters is guaranteed until the module is in active mode Providing the TXD and RXD lines only not using the complete V24 link If the functionality of the CTS RTS DSR DCD RI and DTR lines is not required in the application or the lines are not available Connect the module RTS input line to GND or to the CTS output line of the module since the module requires RTS active low electrical level if HW flow cont
144. U2 series System Integration Manual 4 5 CCC mark SARA G350 modules are certificated for China compulsory product certification CCC mark blox i T GSMEPX E FRIR 4 Model SARA G350 BXXXXX XXXX 000 IMEI XXXXXXXXXXXXXXX 1909 FCC ID XPYSARAG350 C 8595A SARAG350 SR Ht Fl dE Made in Austria 4 6 SARA G350 ATEX conformance for use in explosive atmospheres SARA G350 ATEX modules are certified as components intended for use in potentially explosive atmospheres compliant to the following standards IEC 60079 0 2011 IEC 60079 11 2011 IEC 60079 26 2006 The certification number of SARA G350 ATEX modules according to the ATEX directive 94 9 EC is SIQ 13 ATEX 032 U The certification number of SARA G350 ATEX modules according to the IECEx conformity assessment system is IECEx SIQ 13 0004U According to the standards listed above the SARA G350 ATEX modules are certified with the following marking Ex II 1G Ex ia IIC IIB The temperature range for using SARA G350 ATEX modules is defined in the Operating temperature range section of the SARA G3 series Data Sheet 1 The RF radiating profile of SARA G350 ATEX modules is compliant to all the applicable 3GPP ETSI standards with a maximum of 2 W RF pulse power and 1 15 mJ RF pulse energy according to the GSM GPRS power class stated in Table 3 The nameplate of SARA G350 ATEX modules is described in the Product labeling section of the SARA G3 series Data Sh
145. UPSV 1 o HW flow control disabled in the DTE ee In this case the first character sent when the module is in idle mode will be a wake up character and will not be a valid communication character see section 1 9 1 4 for the complete description UBX 13000995 R10 Early Production Information Design in Page 122 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual E If power saving is enabled the application circuit with the TXD and RXD lines only is not recommended During command mode the DTE must send to the module a wake up character or a dummy AT before each command line see section 1 9 1 4 for the complete description but during data mode the wake up character or the dummy AT would affect the data communication Additional considerations C If the USB interface of SARA U2 modules is connected to the host application processor the UART can be left unconnected as not required for AT and data communication but it is anyway highly recommended to provide direct access to the TXD RXD RTS CTS pins of SARA U2 modules for the execution of firmware upgrade over UART using the u blox EasyFlash tool and for dignostic purpose provide a testpoint on each line to accommodate the access and provide a 0 Q series resistor on each line to detach the module pin from any other connected device Any external signal connected to the UART interface must be tri stated or set low when the module is in power down mode and duri
146. V 1 8V DTE 3V8 LDO Regulator 1V8_GPS GNSS Receiver DD IN OUT Sa vec RXD GPio2 IS e SHDN RTS 47k GND E 4 7k 47k CTS E DR SCL SCL2 RI GND GPIO4 EXTINTO Audio Codec VINT MAX9860 VINT veus __ e gt EE VusB_DET 10k VDD e jioonr igr _ 10pF Dg IROn MICBIAS USB_D 1uF 2 2k alt L D USB_D SDA T SCL n EMI M X 100nF MICLP H e e e e m EMI F a S ps TxD ERI so meN Fg m 2 2k 125_RXD I 4 spout gt y 3V8 MICGND 10nF 10nF 27pF 27pF ESD ESD E ps ck Efl eck ME b rac Network y 7 us wa IE 9 uci SPK Indicator x E EMI s X EE croi copec cx I I vc T aL OUTN e e e rsvp El gt Xy RSVD HE 10nF 10nF 27pF 27pF ESD ESD E rsvp nsvD EA ee a ee rsvp E rsvp EA EB rsvp RsvD EY Figure 87 Example of schematic diagram to integrate SARA U2 module in an application board using all the interfaces UBX 13000995 R10 Early Production Information For a complete schematic example
147. VD MIC BIAS RSVD MIC GND RSVD MIC N RSVD MIC P RSVD GND VCC GND ANT GND ANT_DET RSVD GND Description 1 8 V GPIO Reserved Default GNSS RTC sharing Driver strength 6 mA Internal pull down 35 k PC Data I O Reserved 8 V open drain Driver strength 3 mA PC Clock Output Reserved 8 V open drain Driver strength 3 mA Aux UART Data Out 8 V Driver strength 5 mA Aux UART Data In 8 V Internal pull up 18 k Ground Reserved 32 kHz Input Ground Reserved PS Word Alignment Reserved 1 8 V Driver strength 6 mA PS Data Output Reserved 1 8 V Driver strength 5 mA PS Clock Reserved 1 8 V Driver strength 5 mA PS Data Input Reserved 1 8 V Internal pull down 18 k SIM Clock Output SIM Data O SIM Reset Output SIM Supply Output SIM Detection Input 1 8 V Internal pull down 18 k Ground Analog Audio Out Reserved Analog Audio Out Reserved Microphone Supply Out Reserved Microphone Ground Reserved Analog Audio In Reserved Analog Audio In Reserved Ground Module Supply Input Normal op range 3 35V 4 5V Extended op range 3 00V 4 5V Ground RF Antenna I O ESD immunity IEC 61000 4 2 4 kV contact 8 kV air ESD Ground Antenna Detection Input Reserved Ground SARA G3 and SARA U2 series System Integration Manual SARA U2 Pin Name GPIO4 SDA SCL USB_D USB_D GND RSVD GND RSVD I2S_WA 12S TXD
148. WA SIM DET The following functions are available Network status indication The GPIO1 or the GPIO2 GPIO3 GPIO4 and on SARA U2 series only the SIM DET alternatively from their default settings can be configured to indicate network status i e no service registered home network registered visitor network voice or data call enabled setting the parameter gpio mode of AT UGPIOC command to 2 No GPIO pin is by default configured to provide the Network status indication function The Network status indication mode can be provided only on one pin per time it is not possible to simultaneously set the same mode on another pin The pin configured to provide the Network status indication function is set as o Continuous Low if no service no network coverage or not registered o Cydlically High for 100 ms Low for 2 s if registered home 2G network o Cydlically High for 50 ms Low for 50 ms High for 50 ms Low for 2 s if registered home 3G network o Cydlically High for 100 ms Low for 100 ms High for 100 ms Low for 2 s if registered visitor 2G network roaming o Cyclically High for 50 ms Low for 50 ms High for 50 ms Low for 100 ms if registered visitor 3G network roaming o Continuous High if voice or data 2G 3G call enabled GSM Tx burst indication GPIO1 pin can be configured by AT UGPIOC to indicate when a GSM Tx burst slot occurs setting the parameter gpio mode of AT UGPIOC command to 9 No GPIO pi
149. _OUT output or they will be available also when the module is not powered or switched off if the EXT32K input is fed by a proper external 32 kHz signal SARA G3 series Data Sheet 1 describes the detailed electrical characteristics of the EXT32K input pin The 32 kHz reference clock for the RTC timing is automatically generated by the internal oscillator provided on the SARA G340 SARA G350 and SARA U2 series modules the same pin 31 is a reserved RSVD pin internally not connected since an external 32 kHz signal is not needed to enter the low power idle mode and to provide the RTC functions 1 6 5 Internal 32 kHz signal output 32K OUT Se The 32K_OUT pin is not available on SARA G340 SARA G350 and SARA U2 series modules The 32K_OUT pin of SARA G300 SARA G310 modules is an output pin that provides a 32 kHz reference signal generated by the module suitable only to feed the EXT32K input pin of SARA G300 SARA G310 modules to make available the reference clock for the Real Time Clock RTC timing so that the modules can enter the low power idle mode and can provide the RTC functions with modules switched on The 32K_OUT pin does not provide the 32 kHz output signal when the SARA G300 SARA G310 modules are in power down mode the EXT32K input pin must be fed by an external proper 32 kHz signal to make available the RTC functions when the modules are not powered or switched off SARA G340 SARA G350 and SARA U2 series modules do not provid
150. ablishes and controls the Bluetooth connection using the SAP profile and routes data received over a serial interface channel to data transferred over a Bluetooth interface and vice versa as shown in Figure 34 Device including SIM Device including SARA U2 Mobile SARA U2 Equipment Z SAP SAP GSM UMTS fe Bluetooth Y Bluetooth Bluetooth Application Serial Interface Interface SAP Server Transceiver Interface Transceiver Processor SAP Client SAP channel over USB or UART EB j Remote SIM Local SIM optional Figure 34 Remote SIM access via Bluetooth and wired connection The application processor can start an SAP connection negotiation between SARA U2 module SAP client and an SAP server using custom AT command for more details refer to u blox AT Commands Manual 3 While the connection with the SAP server is not fully established the SARA U2 module continues to operate with the attached local SIM if present Once the connection is established and negotiated the SARA U2 module performs a detach operation from the local SIM followed by an attach operation to the remote one Then the remotely attached SIM is used for any GSM UMTS network operation URC indications are provided to inform the user about the state of both the local and remote SIM The insertion and the removal of the local SIM card are notified if a proper card presence detec
151. according to 3GPP standards TS 27 007 11 TS 27 005 12 TS 27 010 13 and the u blox AT command extension Backward compatibility has been maintained as far as possible ee For the complete list of supported AT commands and their syntax see the relevant AT commands manual of the module 3 9 A 4 Hardware migration SARA modules have been designed with backward compatibility to LISA series modules in mind but some minor differences were unavoidable These minor differences are however not relevant for the majority of the designs The following subsections describe the hardware differences between the interfaces of SARA G3 modules and LISA modules while Table 60 summarizes the detailed differences between the pins A 4 1 Supply interfaces Module supply input VCC The same compatible external circuit can be implemented for SARA and LISA modules even if there are minor differences in the VCC input voltage ranges and some differences in the current consumption figures The voltage provided must be within the normal operating range limits to allow module switch on and must be above the minimum limit of the extended operating range to avoid module switch off For the detailed VCC input voltage ranges values see Table 60 or to the relative datasheet of the module 1 4 5 6 The SARA G3 maximum average current consumption is lower than the LISA one due to the lower data rate or the different channel access technology SARA G3 module
152. ace data mode command mode and online command mode UBX 13000995 R10 Early Production Information System description Page 41 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 9 1 3 UART signal behavior At the module switch on before the UART interface initialization as described in the power on sequence reported in Figure 18 or Figure 19 each pin is first tri stated and then is set to its related internal reset state At the end of the boot sequence the UART interface is initialized the module is by default in active mode and the UART interface is enabled as AT commands interface The configuration and the behavior of the UART signals after the boot sequence are described below See section 1 4 for definition and description of module operating modes referred to in this section RXD signal behavior The module data output line RXD is set by default to the OFF state high level at UART initialization The module holds RXD in the OFF state until the module does not transmit some data TXD signal behavior The module data input line TXD is set by default to the OFF state high level at UART initialization The TXD line is then held by the module in the OFF state if the line is not activated by the DTE an active pull up is enabled inside the module on the TXD input CTS signal behavior The module hardware flow control output CTS line is set to the ON state low level at UART initialization If the ha
153. aced to the DSP digital processing part via the l S digital interface The analog amplifiers are skipped in this case The voice band processing system can be split up into three different blocks e Sample based Voice band Processing single sample processed at 8 kHz every 125 us e Frame based Voice band Processing frames of 160 samples are processed every 20 ms e MIDI synthesizer running at 47 6 kHz These three blocks are connected by buffers and sample rate converters for 8 to 47 6 kHz conversion 12S_RXD MIC a Switch alin Uplink O Hands To Filter 1 Filter 2 Free e Uplink Uplink Analog Gain Digital Gain Sidetone Tone AMR Digital Gain Generator Player Downlink Downlink S Filter 2 Filter 1 Scal_Rec Gain_Out K Speech gt Digital Gain Digital Gain Level SPK Switch SPK Analog Gain MIDI Player 12S_TXD Figure 28 SARA G340 SARA G350 modules audio processing system block diagram From Radio RX Voiceband Sample Buffer Circular Buffer The sample based voice band processing main task is to transfer the voice band samples from either analog audio front end uplink path or I2Sx RX path to the Voice band Sample Buffer and from the Voice band Sample Buffer to the analog audio front end downlink path and or I2Sx TX path While doing this the samples are scaled by digital gains and processed by digital filters both in the uplink and downlink direction and the sidetone is generated mixing scaled uplink samples to the dow
154. ack the SIM used or the specific device UBX 13000995 R10 Early Production Information System description Page 77 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 13 13 Firmware upgrade Over AT FOAT Overview This feature allows upgrading the module Firmware over the AT interface of the module the UART for SARA G3 modules the UART or the USB for SARA U2 modules using AT Commands The AT UFWUPD command triggers a reboot followed by the upgrade procedure at specified a baud rate see u blox AT Commands Manual 3 for more details A special boot loader on the module performs firmware installation security verifications and module reboot Firmware authenticity verification is performed via a security signature during the download The firmware is then installed overwriting the current version In case of power loss during this phase the boot loader detects a fault at the next wake up and restarts the firmware download from the Xmodem 1k handshake After completing the upgrade the module is reset again and wakes up in normal boot FOAT procedure The application processor must proceed in the following way Send the AT UFWUPD command through the AT interface specifying file type and desired baud rate Reconfigure serial communication at selected baud rate with the used protocol Send the new FW image via the used protocol For more details see the Firmware Update Application Note 25 1 13 14 Firmware upgrade
155. age when the battery voltage reaches the regulated output voltage 4 2 V the current is progressively reduced until the charge termination is done The charging process ends when the charging current reaches the 10 of the fast charge current or when the charging timer reaches the value configured by an external capacitor Using a battery pack with an internal NTC resistor the MP2617 can monitor the battery temperature to protect the battery from operating under unsafe thermal conditions Several parameters as the charging current the charging timings the input current limit the input voltage limit the system output voltage can be easily set according to the specific application requirements as the actual electrical characteristics of the battery and the external supply charging source proper resistors or capacitors have to be accordingly connected to the related pins of the IC UBX 13000995 R10 Early Production Information Design in Page 92 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual Li lon Li Polymer Battery Charger Regulator with Power Path Managment SARA G3 SARA U2 BST C4 u 12V sw em VCC Primary d VIN SYS e oo oe o o o VCC Source vcc i cs Li lon Li Po VLIM D Battery Pack R5 BAT e e
156. always supplied then the internal regulator is supplied from the main supply and there is no need for an external component on V_BCKP Combining a SARA G3 or a SARA U2 cellular module with a u blox GNSS positioning receiver the positioning receiver VCC supply is controlled by the cellular module by means of the GNSS supply enable function provided by the GPIO2 of the cellular module In this case the V BCKP supply output of the cellular module can be connected to the V_BCKP backup supply input pin of the GNSS receiver to provide the supply for the positioning real time clock and backup RAM when the VCC supply of the cellular module is within its operating range and the VCC supply of the GNSS receiver is disabled This enables the u blox GNSS receiver to recover from a power breakdown with either a hot start or a warm start depending on the duration of the positioning VCC outage and to maintain the configuration settings saved in the backup RAM Refer to section 2 6 4 for more details regarding the application circuit with a u blox GNSS receiver On SARA G300 and SARA G310 modules the V_BCKP supply output can be used to supply an external 32 kHz oscillator which provides a 32 kHz signal to the EXT32K input pin as reference clock for the RTC timing so that the modules can enter the low power idle mode and can make available the RTC functions Se The internal regulator for V_BCKP is optimized for low leakage current and very light loads Do not app
157. amic X7R 0402 10 16 V GRM155R71C104KA88 Murata C4 C5 C6 C7 27 pF Capacitor Ceramic COG 0402 596 25 V GRM1555C1H270JA01 Murata D1 D2 D3 D4 Low Capacitance ESD Protection CG0402MLE 18G Bourns J Microphone Connector Various Manufacturers J2 Speaker Connector Various Manufacturers L1 L2 82 nH Multilayer inductor 0402 LQG15HS82NJO2 Murata self resonance frequency 1 GHz MIC 2 2 kQ Electret Microphone Various Manufacturers R1 R2 R3 R4 2 2 kQ Resistor 0402 5 0 1 W RC0402JR 072K2L Yageo Phycomp SPK 16 O Speaker Various Manufacturers Table 50 Example of components for analog audio interface headset and handset mode application circuit If the analog audio interface is not used the analog audio pins MIC BIAS MIC GND MIC P MIC N SPK P SPK N can be left unconnected on the application board UBX 13000995 R10 Early Production Information Design in Page 134 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 2 7 1 2 Guidelines for microphone and loudspeaker connection circuit design hands free mode Figure 77 shows an application circuit for the analog audio interface in hands free mode connecting a 2 2 kO electret microphone and an 8 Q or 4 Q loudspeaker External microphone can be connected to the uplink path of the module since the module provides supply and reference as well as differential signal input for the external microphone Using a 8 Q or 4 Q loudspeaker for the hands fr
158. ansmitter GMSK modulator Fractional N Sigma Delta RF synthesizer 3 8 GHz VCO Digital controlled crystal oscillator 2G 3G Power Amplifier which amplifies the signals modulated by the RF transceiver RF switch which connects the antenna input output pin ANT of the module to the suitable RX TX path RX diplexer SAW band pass filters 26 MHz crystal connected to the digital controlled crystal oscillator to perform the clock reference in active mode or connected mode Baseband and Power Management section The Baseband and Power Management section is composed of the following main elements Baseband processor a mixed signal ASIC which integrates Microprocessor for controller functions DSP core for 2G 3G Layer 1 and audio processing Dedicated peripheral blocks for parallel control of the digital interfaces Audio analog front end Memory system in a multi chip package integrating two devices NOR flash non volatile memory RAM volatile memory Voltage regulators to derive all the system supply voltages from the module supply VCC Circuit for the RTC clock reference in low power idle mode SARA G340 SARA G350 and SARA U2 series modules are equipped with an internal 32 768 kHz crystal connected to the oscillator of the RTC Real Time Clock block that gives the RTC clock reference needed to provide the RTC functions as well as to reach the very low power idle mode with power saving configuration enabled by the AT UPSV command SARA G300 and S
159. apacitor for DC blocking LISA U120 U130 only Differential input 00 nF internal capacitor for DC blocking LISA U120 U130 only Differential output 16 ohm load capable LISA U120 U130 only Differential output 16 ohm load capable LISA U120 U130 only 8 V Data Out PCM Normal I25 mode Driver strength 2 5 mA LISA U120 U130 only 8 V Data In PCM Normal I25 mode Inner pull down 100 pA LISA U120 U130 only 8 V Word align In Out Configurable frequency Inner pull down 100 pA Driver strength 2 5 mA LISA U120 U130 only 1 8 V Clock In Out Configurable frequency Inner pull down 100 pA Driver strength 2 5 mA Not Available Not Available Not Available Not Available LISA U2 series Not Available Not Available Not Available Not Available Not Available Not Available 1 8 V Data Out PCM Normal I25 mode Driver strength 2 mA LISA U200 00S N A 1 8 V Data In PCM Normal I2S mode Inner pull down 200 pA LISA U200 00S N A 1 8 V Word align In Out Configurable frequency Inner pull down 200 pA Driver strength 2 mA LISA U200 00S N A 1 8 V Clock In Out Configurable frequency Inner pull down 200 pA Driver strength 2 mA LISA U200 00S N A 1 8 V Data Out PCM Normal I2S mode Driver strength 1 mA LISA U200 00S N A 1 8 V Data In PCM Normal I2S mode Inner pull down 150 pA LISA U200 00S N A 1 8 V Word align In Out Configurable
160. apacitors in the pF range described in Figure 40 and Table 25 should be placed as close as possible to the VCC pins This is highly recommended if the application device integrates an internal antenna Since VCC is directly connected to RF Power Amplifiers voltage ripple at high frequency may result in unwanted spurious modulation of transmitter RF signal This is more likely to happen with switching DC DC converters in which case it is better to select the highest operating frequency for the switcher and add a large L C filter before connecting to the SARA G3 and SARA U2 series modules in the worst case If VCC is protected by transient voltage suppressor to ensure that the voltage maximum ratings are not exceeded place the protecting device along the path from the DC source toward the cellular module preferably closer to the DC source otherwise protection functionality may be compromised 2 2 1 10 Guidelines for grounding layout design Good connection of the module GND pins with application board solid ground layer is required for correct RF performance It significantly reduces EMC issues and provides a thermal heat sink for the module Connect each GND pin with application board solid GND layer It is strongly recommended that each GND pin surrounding VCC pins have one or more dedicated via down to the application board solid ground layer The VCC supply current flows back to main DC source through GND as ground current provide adequate return
161. are by default configured as the l S digital audio interface Only these pins of SARA U2 modules can be configured as the l S digital audio interface by correctly setting the parameter gpio mode of AT UGPIOC command to 12 default setting ee SARA G3 series do not support the l S digital audio interface over GPIOs General purpose input All the GPIOs can be configured as input to sense high or low digital level through AT UGPIOR command setting the parameter lt gpio_mode gt of AT UGPIOC command to 1 The General purpose input mode can be provided on more than one pin at a time No GPIO pin is by default configured as General purpose input The pin configured to provide the General purpose input function is set as o Input to sense high or low digital level by AT UGPIOR command General purpose output All the GPIOs can be configured as output to set the high or the low digital level through AT UGPIOW command setting the parameter gpio mode of UGPIOC AT command to O The General purpose output mode can be provided on more than one pin per time No GPIO pin is by default configured as General purpose output The pin configured to provide the General purpose output function is set as o Output Low if the parameter gpio out val of AT UGPIOW command is set to O o Output High if the parameter gpio out val of AT UGPIOW command is set to 1 UBX 13000995 R10 Early Production Information
162. are part of the USB pin driver and need not be provided externally See section 1 9 3 for functional description See section 2 6 3 for external circuit design in High Speed USB 2 0 interface data line for AT data FOAT FW upgrade via EasyFlash tool and diagnostic 90 Q nominal differential impedance Pull up pull down and series resistors as required by USB 2 0 specifications 14 are part of the USB pin driver and need not be provided externally See section 1 9 3 for functional description See section 2 6 3 for external circuit design in 1 8 V open drain for the communication with the u blox positioning modules chips Communication with other external l C slave devices as an audio codec is additionally supported by SARA U2 series External pull up required See section 1 9 4 for functional description See section 2 6 4 for external circuit design in 1 8 V open drain for the communication with u blox positioning modules chips Communication with other external l C slave devices as an audio codec is additionally supported by SARA U2 series External pull up required See section 1 9 4 for functional description See section 2 6 4 for external circuit design in System description Page 15 of 192 biox Function Pin Name Analog MIC_BIAS Audio MIC_GND MIC_N MIC_P SPK_P SPK_N Digital Audio 12S_CLK 12S_RXD 12S_TXD 12S_WA CODEC_CLK UBX 13000995 R10 Module SARA G340 SAR
163. as default setting of the AT UGPIOC command the SIM card detection function is enabled as the parameter gpio mode of AT UGPIOC command is set to 7 default setting The SIM DET pin configured to provide the SIM card detection function is set as o Input with an internal active pull down enabled to sense SIM card mechanical presence The SIM DET pin can sense the SIM card mechanical presence only if properly connected to the mechanical switch of a SIM card holder as described in section 2 5 o Low logic level at SIM DET input pin is recognized as SIM card not present o High logic level at SIM DET input pin is recognized as SIM card present SARA U2 modules provide the additional function SIM card hot insertion removal on the SIM DET pin which can be enabled using the AT UDCONF 50 command if the SIM card detection function is enabled by AT UGPIOC for more details see u blox AT Commands Manual 3 in this case the SIM interface of the SARA U2 modules is disabled when a Low logic level is recognized at SIM DET input pin within 20 ms from the start of the Low level and it is enabled when an High logic level at SIM DET input pin is recognized SARA G3 series do not support the additional function SIM card hot insertion removal UBX 13000995 R10 Early Production Information System description Page 64 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Module status indication The GPIO1 pin of SARA U2 mo
164. as master only and the connected u blox GNSS receiver or any other external IC devices acts as slave in the DDC IC communication Two lines serial data SDA and serial clock SCL carry information on the bus SCL is used to synchronize data transfers and SDA is the data line To be compliant to the l C bus specifications the module interface pins are open drain output and pull up resistors must be externally provided conforming to the l C bus specifications 15 u blox has implemented special features in SARA G340 SARA G350 and SARA U2 modules to ease the design effort required for the integration of a u blox cellular module with a u blox GNSS receiver UBX 13000995 R10 Early Production Information System description Page 54 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Combining a u blox cellular module with a u blox GNSS receiver allows designers to have full access to the positioning receiver directly via the cellular module it relays control messages to the GNSS receiver via a dedicated DDC FC interface A 2 interface connected to the positioning receiver is not necessary AT commands via the UART or USB serial interface of the cellular module allows a fully control of the GNSS receiver from any host processor SARA G340 SARA G350 and SARA U2 modules feature embedded GNSS aiding that is a set of specific features developed by u blox to enhance GNSS performance decreasing the Time To First Fix TTFF t
165. asyFlash tool or by means of AT command for more details see section 1 13 13 and Firmware update application note 25 Audio over USB capabilities can be enabled by specific AT command refer to u blox AT Commands Manual 3 the Audio Device Class provides a streaming interface which transfers audio data on isochronous pipes ee The USB Audio Device Class is not supported by initial firmware release Se For more details on the configuration of the USB interface of SARA U2 modules see the u blox AT Commands Manual 3 UUSBCONF AT command USB CDC ACM drivers are available for the following operating system platforms Windows 2000 Windows XP Windows Vista Windows 7 Windows 8 Windows CE 5 0 Windows Embedded CE 6 0 Windows Embedded Compact 7 Windows Embedded Automotive 7 Windows Mobile 5 Windows Mobile 6 Windows Mobile 6 1 Windows Mobile 6 5 SARA U2 modules are compatible with standard Linux Android USB kernel drivers The USB profile of SARA U2 module identifies itself by its VID Vendor ID and PID Product ID combination included in the USB device descriptor according to the USB 2 0 specifications 14 VID and PID of the SARA U2 module USB profile with the set of USB functions described in details above AT and Data GNSS tunneling Diagnostic SAP are the following VID 0x1546 PID 0x1102 UBX 13000995 R10 Early Production Information System description Page 53 of 192 Qo ox SARA G3 and SARA U2 series System I
166. atio of the explosive gas atmosphere in which the equipment may be installed typical gases are hydrogen acetylene carbon disulphide so that the modules are also suitable for applications intended for use in subdivision IIB typical gases are ethylene coke oven gas and other industrial gases and subdivision IIA typical gases are industrial methane propane petrol and the majority of industrial gases The temperature range of use of SARA G350 ATEX modules is defined in the Operating temperature range section of the SARA G3 series Data Sheet 1 Even if the SARA G350 ATEX modules are certified as components intended for use in potentially explosive atmospheres as described above the application device that integrates the module must be approved under all the certification schemes required by the specific application device to be deployed in the market as apparatus intended for use in potentially explosive atmospheres The certification scheme approvals required for the application device integrating SARA G350 ATEX modules intended for use in potentially explosive atmospheres may differ depending on the following topics the country or the region where the application device must be deployed the classification of the application device in relation to the use in potentially explosive atmospheres the classification of the hazardous areas in which the application device is intended for use Se Any specific applicable requirement for the imp
167. ault the pin is configured to provide GNSS Supply Enable function SARA G350 Can be alternatively configured by the UGPIOC command as SARA U2 series Output Input Network Status Indication Pin disabled 24 SARA G340 GPIO3 GPIO By default the pin is configured to provide GNSS Data Ready function SARA G350 Can be alternatively configured by the UGPIOC command as SARA U2 series Output Input Network Status Indication GNSS Supply Enable Pin disabled 25 SARA G340 GPIO4 GPIO By default the pin is configured to provide GNSS RTC sharing function SARA G350 Can be alternatively configured by the UGPIOC command as SARA U2 series Output Input Network Status Indication GNSS Supply Enable Pin disabled UBX 13000995 R10 Early Production Information System description Page 66 of 192 biox Pin 42 34 39 36 37 Table 13 GPIO pins configurations Module SARA G340 SARA G350 SARA U2 series SARA U2 series SARA U2 series SARA U2 series SARA U2 series Name SIM_DET SIM_DET 12S_WA 12S_TXD 12S_CLK 12S_RXD Description SIM detection GPIO GPIO GPIO GPIO GPIO 1 12 Reserved pins RSVD SARA G3 and SARA U2 series modules have pins reserved for future use they can all be left unconnected on the application board except the RSVD pin number 33 that must be externally connected to ground UBX 13000995 R10 SARA G3 and SARA U2 series System Integration Manual R
168. bypass capacitor and a series chip ferrite bead noise EMI suppression filter provided on each microphone line input and speaker line output of the external codec as described in Figure 79 and Table 53 The necessity of these or other additional parts for EMC improvement may depend on the specific application board design SARA U2 series V INT e Audio Codec c c cs R3 VDD L IRQn TO ET me I2S5 TXD SDIN MICBIAS 1 1 125 RXD ERN SDOUT c4 R4 Microphone 12S_CLK nn BCLK mr Efi Connector MIC I25 WA LRCLK MICLP e D c5 EMI2 MICLN e e C6 n 1V8 V8 ms C12 C11 Tcs Te7 MICGND oe D1 ED D2 RI R2 B 7 Speaker SPK SDA SDA Connector EMI3 SCL SCL OUTP e ra C EMIA CODEC CLK KIB MCLK OUTN e e e X y 2 PX C14 C13 C10 C9 GND E 5 GND i Ds s Figure 79 Application circuit for connecting SARA U2 modules with an external audio codec to provide voice capability UBX 13000995 R10 Early Production Information Design in Page 139 of 192 biox Reference C1 C2 C4 C5 C6 C3 C7 C8 C9 C10 C11 C12 C13 C14 D1 D2 D3 D4 EMI1 EMI2 EMI3 EMIA Ji J2 MIC R1 R2 R3 R4 R5 SPK U1 SARA G3 and SARA U2 series System Integration Manual Description 00 nF Capacitor Ceramic X5R 0
169. call 1 TX slot 1 RX slot at the maximum TX power e 2 C during a GPRS data transfer 2 TX slots 3 RX slots at the maximum TX power Beside the reduction of the Module to Ambient thermal resistance implemented by the hardware design of the application device integrating a SARA G3 and SARA U2 series module the increase of module temperature can be moderated by the software implementation of the application Since the most critical condition concerning module thermal power occurs when module connected mode is enabled the actual module thermal power depends as module current consumption on the radio access mode the operating band and the average TX power A few software techniques may be implemented to reduce the module temperature increase in the application e Select the radio access mode which provides lower temperature increase by means of AT command see the u blox AT Commands Manual 3 e Select by means of AT command the GPRS multi slot class which provides lower current consumption see current consumption values reported in SARA G3 series Data Sheet 1 or SARA U2 series Data Sheet 2 and u blox AT Commands Manual 3 UCLASS command e Select by means of AT command the operating band which provides lower current consumption see current consumption values reported in SARA G3 series Data Sheet 1 or SARA U2 series Data Sheet 2 and u blox AT Commands Manual 3 UBANDSEL command e Enable module connected mode for a given t
170. ces USB UART of the modules until the end of this interfaces configuration phase to allow a proper boot of the module After the interfaces configuration phase the application can start sending AT commands and the following starting procedure is suggested to check the effective completion of the module internal boot sequence send AT and wait for the response with a 30 s timeout iterate it 4 times without resetting or removing the VCC supply of the module and then run the application Start up Start of interface Module interfaces event configuration are configured VCC V_BCKP PWR_ON V_INT Internal Reset i id System State OFF e Digital Pins State Tristate Floating Internal Reset Internal Reset gt Operational Figure 19 SARA G3 and SARA U2 series power on sequence from power off mode Se The Internal Reset signal is not available on a module pin but the application can monitor the V_INT pin to sense the start of the power on sequence ee Before the switch on of the generic digital interface supply source V_INT of the module no voltage driven by an external application should be applied to any generic digital interface of the modules UBX 13000995 R10 Early Production Information System description Page 32 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 6 2 Module power off 1 6 2 1 Switch off events The SARA G3 and SARA U2 series modules can be properly switched off by
171. ct specification This document applies to the following products Product name Type number Firmware version SDN IN PCN SARA G300 SARA G300 00S 00 08 58 GSM G2 TN 13007 SARA G310 SARA G310 00S 00 08 58 GSM G2 TN 13007 SARA G340 SARA G340 00S 00 08 49 UBX 14000382 SARA G340 015 00 08 64 UBX 14015742 SARA G350 SARA G350 00S 00 08 49 GSM G2 TN 13002 SARA G350 015 00 08 64 UBX 14015742 SARA G350 01B 00 TBD TBD SARA G350 ATEX SARA G350 00X 00 08 49 GSM G2 TN 13002 SARA U260 SARA U260 005 00 23 20 UBX 14015739 SARA U270 SARA U270 005 00 23 20 UBX 14015739 SARA U280 SARA U280 005 00 TBD TBD SARA U290 SARA U290 005 00 TBD TBD SARA U290 605 00 TBD TBD u blox reserves all rights to this document and the information contained herein Products names logos and designs described herein may in whole or in part be subject to intellectual property rights Reproduction use modification or disclosure to third parties of this document or any part thereof without the express permission of u blox is strictly prohibited The information contained herein is provided as is and u blox assumes no liability for the use of the information No warranty either express or implied is given including but not limited with respect to the accuracy correctness reliability and fitness for a particular purpose of the information This document may be revised by u blox at any time For most recent documents please visit www u blox com Copyr
172. ctrl input nternal pull up 30 uA 8 V Flow ctrl output Driver strength 4 mA 8 V Data input nternal pull up 30 pA 8 V Data output Driver strength 4 mA Not Available Not Available 5 V Supply detection Full Speed USB 2 0 Full Speed USB 2 0 Not Available Not Available Not Available Not Available Not Available 1 8 V open drain upcoming FW releases 1 8 V open drain upcoming FW releases Early Production Information LISA U1 series 8V 3V SIM clock 8V 3V SIM data Internal 4 7k pull up 8V 3V SIM reset 8V 3V SIM supply Provided by GPIOS 1 8 V SIM detect input Inner pull down 55 pA 8 V DSR output Driver strength 4 mA 8 V RI output Driver strength 4 mA 8 V DCD output Driver strength 4 mA 8 V DTR input nternal pull up 110 pA 8 V Flow ctrl input nternal pull up 60 pA 8 V Flow ctrl output Driver strength 4 mA 8 V Data input nternal pull up 60 pA 8 V Data output Driver strength 4 mA Not Available ot Available 5 V Supply detection High Speed USB 2 0 High Speed USB 2 0 8 V Clock input Inner pull down 100 pA 8 V Data input Internal pull up 220 pA 8 V Data output Driver strength 2 5 mA 8 V Flow ctrl output Driver strength 4 mA 8 V Flow ctrl input Inner pull down 55 pA 8 V open drain Driver strength 1 mA 8 V open drain Driver strength 1 mA LISA U2 serie
173. cuit using step down regulator Reference Description Part Number Manufacturer C1 22 yF Capacitor Ceramic X5R 1210 1096 25 V GRM32ER61E226KE15 Murata C2 100 pF Capacitor Tantalum B SIZE 20 6 3V 15mQ T520B107MOO6ATEO015 Kemet C3 5 6 nF Capacitor Ceramic X7R 0402 1096 50 V GRM155R71H562KA88 Murata C4 6 8 nF Capacitor Ceramic X7R 0402 1096 50 V GRM155R71H682KA88 Murata C5 56 pF Capacitor Ceramic COG 0402 596 50 V GRM1555C1H560JA01 Murata C6 220 nF Capacitor Ceramic X7R 0603 1096 25 V GRM188R71E224KA88 Murata D1 Schottky Diode 25V 2 A STPS2L25 STMicroelectronics L1 5 2 UH Inductor 30 5 28A 22 mQ MSS1038 522NL Coilcraft R1 4 7 kQ Resistor 0402 1 0 063 W RCO402FR 074K7L Yageo R2 910 Q Resistor 0402 196 0 063 W RCO402FR 07910RL Yageo R3 82 Q Resistor 0402 596 0 063 W RC0402JR 0782RL Yageo R4 8 2 kQ Resistor 0402 5 0 063 W RC0402JR 078K2L Yageo R5 39 kQ Resistor 0402 5 0 063 W RC0402JR 0739KL Yageo U1 Step Down Regulator 8 VFQFPN 3 A 1 MHz L5987TR ST Microelectronics Table 22 Suggested components for low cost solution VCC voltage supply application circuit using a step down regulator 2 2 1 3 Guidelines for VCC supply circuit design using a Low Drop Out LDO linear regulator The use of a linear regulator is suggested when the difference from the available supply rail and the VCC value is low linear regulators provide high efficiency when transforming a 5 V supply to a voltage value within
174. d Circuit Card niversal Mobile Telecommunications System niversal Serial Bus U U U Up link Transmission U U U MTS Terrestrial Radio Access Voltage Controlled Oscillator Voltage Standing Wave Ratio Early Production Information Appendix Page 189 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual Related documents O WAN DUN S UN e 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 u blox SARA G3 series Data Sheet Docu No UBX 13000993 u blox SARA U2 series Data Sheet Docu No UBX 13005287 u blox AT Commands Manual Docu No UBX 13002752 u blox LISA C200 series Data Sheet Docu No UBX 13000623 u blox LISA U1 series Data Sheet Docu No UBX 13002048 u blox LISA U2 series Data Sheet Docu No UBX 13001734 u blox LISA C200 amp FW75 C200 System Integration Manual Docu No UBX 13000620 u blox LISA U series System Integration Manual Docu No UBX 13001118 u blox C200 AT Commands Manual Docu No CDMA 2X 11002 ITU T Recommendation V 24 02 2000 List of definitions for interchange circuits between the Data Terminal Equipment DTE and the Data Circuit terminating Equipment DCE http www itu int rec T REC V 24 200002 I en 3GPP TS 27 007 AT command set for User Equipment UE Release 1999 3GPP TS 27 005 Use of Data Terminal Equipment Data Circuit terminating Equipment DTE DCE interface for Short Message Service SMS and Cell Broadcast S
175. d mode current profiles VCC peak current Support with margin the highest peak VCC current The specified highest peak of VCC current consumption consumption value specified in SARA G3 series Data occurs during GSM single transmit slot in 850 900 MHz Sheet 1 and in SARA U2 series Data Sheet 2 connected mode in case of mismatched antenna See 1 5 1 2 for 2G connected mode current profiles VCC voltage drop Lower than 400 mV VCC voltage drop directly affects the RF compliance with during 2G Tx slots applicable certification schemes Figure 7 describes VCC voltage drop during Tx slots VCC voltage ripple Lower than 30 mVpp if f S 200 kHz VCC voltage ripple directly affects the RF compliance with during 2G 3G Tx Lower than 10 mVpp if 200 kHz lt f S 400 kHz applicable certification schemes Lower than 2 mVpp if fig gt 400 kHz Figure 7 describes VCC voltage ripple during Tx slots VCC under over shoot Absent or at least minimized VCC under over shoot directly affects the RF compliance at start end of Tx slots with applicable certification schemes Figure 7 describes VCC voltage under over shoot Table 7 Summary of VCC supply requirements UBX 13000995 R10 Early Production Information System description Page 20 of 192 Qo OX SARA G3 and SARA U2 series System Integration Manual 1 5 1 2 VCC current consumption in 2G connected mode When a GSM call is established the VCC consumption is determined by the current c
176. d to VSIM Package Pin 3 UICC Contact C7 I O Data input output gt It must be connected to SIM_IO Package Pin 4 UICC Contact C8 AUX2 Auxiliary contact gt It must be left not connected A solderable SIM chip has 8 contacts and can provide also the auxiliary contacts C4 AUX1 and C8 AUX2 for USB interfaces and other uses but only 6 contacts are required and must be connected to the module SIM card interface as described above since SARA G3 and SARA U2 modules do not support the additional auxiliary features contacts C4 AUX1 and C8 AUX2 Solderable SIM chips are suitable for M2M applications where it is not required to change the SIM once installed UBX 13000995 R10 Early Production Information Design in Page 112 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual Guidelines for single SIM card connection without detection An application circuit for the connection to a single removable SIM card placed in a SIM card holder is described in Figure 55 where the optional SIM detection feature is not implemented see the circuit described in Figure 57 if the SIM detection feature is required Follow these guidelines connecting the module to a SIM connector without SIM presence detection Connect the UICC SIM contacts C1 VCC and C6 VPP to the VSIM pin of the module Connect the UICC SIM contact C7 I O to the SIM IO pin of the module Connect the UICC SIM contact C3 CLK to the SIM CLK pin of the
177. data bits No parity 1 stop bit default frame configuration with fixed baud rate 8E1 8 data bits even parity 1 stop bit 801 8 data bits odd parity 1 stop bit 8N2 8 data bits No parity 2 stop bits 7E1 7 data bits even parity 1 stop bit 701 7 data bits odd parity 1 stop bit Figure 22 describes the 8N1 frame format which is the default configuration with fixed baud rate Normal Transfer 8N1 Start of 1 Byte Possible Start of cs next ede Start Bit fso Bit Always 0 Aways 1 tot 1Baudrate Figure 22 Description of UART default frame format 8N1 with fixed baud rate UBX 13000995 R10 Early Production Information System description Page 40 of 192 biox SARA G3 and SARA U2 series System Integration Manual The module firmware can be updated over the UART interface by means of the Firmware upgrade Over AT FOAT feature on all the SARA G3 and SARA U2 series modules the u blox EasyFlash tool on SARA U2 series modules only For more details on FW upgrade procedures see section 1 13 and Firmware update application note 25 1 9 1 2 UART AT interface configuration The UART interface of SARA G3 and SARA U2 series modules is available as AT command interface with the default configuration described in Table 11 for more details and information about further settings see the u blox AT Commands Manual 3 Interface AT Settings UART interface AT interface enabled AT IPR 0 AT ICF 0
178. de analog audio interfaces LISA U2 series modules do not provide analog audio interfaces but analog audio can be provided with external audio codec connected to a digital audio interface of all LISA U2 series modules except LISA U200 00S e g the 4 wire IS digital audio interface provided instead of the 4 analog audio pins The modules provide control of the external codec by means of the l C interface and clock reference by means of the CODEC CLK pin For further details regarding analog audio interfaces characteristics usage and settings see the related module datasheet 1 4 5 6 System Integration Manual 1 10 1 2 7 1 7 8 and AT commands manual 3 9 Digital audio interfaces The digital audio interface is provided on the I2S TXD I2S RXD I2S CLK I2S WA pins of SARA G340 SARA G350 modules 1 8 V PCM amp Normal I2S modes master fixed sample rate and LISA U120 U130 and all LISA U2 series modules except LISA U200 00S 1 8 V PCM amp Normal I2S modes master amp slave configurable sample rate It is provided on the PCM DO PCM DI PCM CLK PCM SYNC pins of LISA C2 series modules 1 8 V PCM The same compatible external circuit can be implemented according to external digital audio device capabilities An additional digital audio interface is provided on I2S1 TXD 1I2S1 RXD 12S1 CLK I2S1 WA pins of all LISA U2 series except LISA U200 00S 1 8 V PCM amp Normal I2S modes master amp slave configurable sampl
179. detailed electrical characteristics see SARA G3 series Data Sheet 1 and SARA U2 series Data Sheet 2 SARA G3 and SARA U2 series modules are designed to operate as a 2G or 3G cellular modem which represents the Data Circuit terminating Equipment DCE according to the ITU T V 24 Recommendation 10 The application processor connected to the module through the UART interface represents the Data Terminal Equipment DTE Se The signal names of SARA G3 and SARA U2 series modules UART interface conform to the ITU T V 24 Recommendation 10 e g the TXD line represents the data transmitted by the DTE application processor data line output and received by the DCE module data line input All flow control handshakes are supported by the UART interface and can be set by appropriate AT commands see u blox AT Commands Manual 3 amp K IFC Q AT commands hardware flow control RTS CTS software flow control XON XOFF or none flow control Se Hardware flow control is enabled by default SARA G3 modules support the autobauding the baud rate automatic detection is performed each time the DTE sends AT commands After the detection the module works at the detected baud rate and the baud rate can be runtime changed by the DTE or by AT command see u blox AT Commands Manual 3 IPR command SARA U2 modules support only the one shot autobauding the baud rate automatic detection is performed only once at module start up After the detecti
180. direction since the signal names follow the ITU T V 24 Recommendation 10 Provide accessible testpoints directly connected to the following pins of the SARA G3 series modules TXD AUX and RXD_AUX pins V INT pin RESET N and or PWR ON pins for module FW upgrade by the u blox EasyFlash tool and for diagnostic purpose Provide accessible testpoints directly connected to the following pins of the SARA U2 series modules VUSB DET USB D USB D and or RXD TXD CTS RTS pins V INT pin RESET N and or PWR ON pins for module FW upgrade by the u blox EasyFlash tool and for diagnostic purpose Add a proper pull up resistor e g 4 7 KQ to V INT or another proper 1 8 V supply on each DDC lC interface line if the interface is used Capacitance and series resistance must be limited on each high speed line of the USB interface Capacitance and series resistance must be limited on each line of the DDC IC interface Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 kQ resistor on the board in series to the GPIO when those are used to drive LEDs Connect the pin number 33 RSVD to ground Insert the suggested passive filtering parts on each used analog audio line Check the digital audio interface specifications to connect a proper device Capacitance and series resistance must be limited on CODEC CLK line and each I S interface line Provide proper precautions for ESD immunity as required on the app
181. downlink gt parameters of the AT USPM command must be properly configured to select the I S digital audio interfaces paths for more details refer to u blox AT Commands Manual 3 main uplink must be properly set to select o the PS interface using I2 RKXD module input main downlink must be properly set to select o the PS interface using I2 TXD module output Parameters of digital path can be configured and saved as described in the u blox AT Commands Manual 3 USGC UMGC USTN AT commands Analog gain parameters are not used when digital path is selected The I S receive data input and the l S transmit data output signals are respectively connected in parallel to the analog microphone input and speaker output signals so resources available for analog path can be shared Digital filters and digital gains are available in both uplink and downlink direction Ringer tone and service tone are mixed on the TX path when active downlink The HF algorithm acts on l S path ee Refer to the u blox AT Commands Manual 3 AT UI2S command for possible settings of I S interface UBX 13000995 R10 Early Production Information System description Page 58 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 10 2 1 I S interface PCM mode Main features of the I S interface in PCM mode configurable by AT UI2S command PS runs in PCM short alignment mode l S word alignment signal is configured by the
182. ds Manual 3 AT USPM AT USGC AT UDBF AT USTN commands The differential analog audio output of SARA G340 and SARA G350 modules SPK P SPK N is able to directly drive loads with resistance rating greater than 14 Q it can be directly connected to a headset earpiece or handset earpiece but cannot directly drive a 8 or 4 Q loudspeaker for the hands free mode SARA G3 series Data Sheet 1 provides the detailed electrical characteristics of the analog audio downlink path Ay Warning excessive sound pressure from headphones can cause hearing loss 1 10 1 3 Headset mode Headset mode is the default audio operating mode of the modules The headset profile is configured when the uplink audio path is set to Headset microphone and the downlink audio path is set to Mono headset refer to u blox AT Commands Manual 3 AT USPM command lt main_uplink gt lt main_downlink gt parameters 1 10 1 4 Handset mode The handset profile is configured when the uplink audio path is set to Handset microphone and the downlink audio path is set to Normal earpiece refer to u blox AT commands manual 3 AT USPM command lt main_uplink gt lt main_downlink gt parameters 1 10 1 5 Hands free mode The hands free profile is configured when the uplink audio path is set to Hands free microphone and the downlink audio path is set to Loudspeaker refer to u blox AT commands manual 3 AT USPM command lt main_uplink gt
183. dules can be configured to indicate module status power off mode i e module switched off versus idle active or connected mode i e module switched on by properly setting the parameter gpio mode of AT UGPIOC command to 10 No GPIO pin is by default configured to provide the Module status indication The pin configured to provide the Module status indication function is set as o High when the module is switched on any operating mode during module normal operation o Low when the module is switched off power off mode Se SARA G3 series do not support Module status indication function Module operating mode indication The SIM_DET pin of SARA U2 modules can be configured to indicate module operating mode status the low power idle mode versus active or connected mode by properly setting the parameter lt gpio_mode gt of AT UGPIOC command to 11 No GPIO pin is by default configured to provide the Module operating mode indication The pin configured to provide the Module operating mode indication function is set as o Output High when the module is in active or connected mode o Output Low when the module is in idle mode that can be reached if power saving is enabled by UPSV AT command for further details see u blox AT Commands Manual 3 Se SARA G3 series do not support Module operating mode indication PS digital audio interface The I2S RXD I2S TXD I2S CLK I2S5 WA pins of SARA U2 modules
184. e gt 1 5 dB gt 7096 recommended gt 3 0 dB gt 50 acceptable See section 4 2 2 for maximum gain limits gt 2 W peak Application board with antenna detection circuit Antenna assembly with built in diagnostic circuit Table 10 Summary of antenna RF interface ANT requirements E Remarks The nominal characteristic impedance of the antenna RF connection must match the ANT pin 50 Q impedance The required frequency range of the antenna depends on he operating bands supported by the cellular module The Return loss or the S as the VSWR refers to the amount of reflected power measuring how well the RF antenna connection matches the 50 Q impedance The impedance of the antenna RF termination must match as much as possible the 50 Q impedance of the ANT pin over the operating frequency range reducing as much as possible the amount of reflected power The radiation efficiency is the ratio of the radiated power o the power delivered to antenna input the efficiency is a measure of how well an antenna receives or transmits The efficiency needs to be enough high over the operating requency range to comply with the Over The Air radiated performance requirements as Total Radiated Power and Total Isotropic Sensitivity specified by certification schemes The power gain of an antenna is the radiation efficiency multiplied by the directivity the maximum gain describes how much power is transmitted in the dir
185. e CPWROFF AT command is sent the module starts the switch off routine e The module replies OK on the AT interface the switch off routine is in progress e At the end of the switch off routine all the digital pins are tri stated and all the internal voltage regulators are turned off including the generic digital interfaces supply V INT except the RTC supply V BCKP e Then the module remains in power off mode as long as a switch on event does not occur e g applying a proper low level to the PWR ON input or applying a proper low level to the RESET N input and enters not powered mode if the supply is removed from the VCC pins AT CPWROFF OK VCC sent to the module replied by the module can be removed Y Y M Pu a Internal Reset System State Digital Pins State Operational gt Tristate Figure 20 SARA G3 and SARA U2 series power off sequence description The Internal Reset signal is not available on a module pin but the application can monitor the V_INT pin to sense the end of the SARA G3 and SARA U2 series power off sequence The duration of each phase in the SARA G3 and SARA U2 series modules switch off routines can largely vary depending on the application network settings and the concurrent module activities UBX 13000995 R10 Early Production Information System description Page 34 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual 1 6 3 Module reset SARA G3 and SARA U2 serie
186. e information as well as drying for preconditioning see the SARA G3 series Data Sheet 1 or the SARA U2 series Data Sheet 2 and the u blox Package Information Guide 27 3 2 Handling The SARA G3 and SARA U2 series modules are Electro Static Discharge ESD sensitive devices Ay Ensure ESD precautions are implemented during handling of the module Electrostatic discharge ESD is the sudden and momentary electric current that flows between two objects at different electrical potentials caused by direct contact or induced by an electrostatic field The term is usually used in the electronics and other industries to describe momentary unwanted currents that may cause damage to electronic equipment The ESD sensitivity for each pin of SARA G3 and SARA U2 series modules as Human Body Model according to JESD22 A1 14F is specified in the SARA G3 series Data Sheet 1 or the SARA U2 series Data Sheet 2 ESD prevention is based on establishing an Electrostatic Protective Area EPA The EPA can be a small working station or a large manufacturing area The main principle of an EPA is that there are no highly charging materials near ESD sensitive electronics all conductive materials are grounded workers are grounded and charge build up on ESD sensitive electronics is prevented International standards are used to define typical EPA and can be obtained for example from International Electrotechnical Commission IEC or American National Standards
187. e rate SARA G300 SARA G310 LISA U100 LISA U110 LISA U200 00S modules do not provide digital audio interfaces For further details regarding digital audio interfaces characteristics usage and settings see the related module datasheet 1 4 5 6 System Integration Manual 1 10 2 2 7 2 7 8 and AT commands manual 3 9 A 4 7 GPIO pins The same compatible external circuit can be implemented for SARA G340 SARA G350 and LISA series four 1 8 V GPIOs are provided by SARA G340 SARA G350 modules providing the same functionalities as LISA series modules except Module Status and Operating Mode Indications The SIM DET pin provides the SIM detection function on SARA modules rather than the GPIO5 pin as on LISA U series modules SARA G300 and SARA G310 modules do not provide GPIOs A 4 8 Reserved pins SARA modules RSVD pin 33 must be connected to ground as does the RSVD pin 5 on LISA modules UBX 13000995 R10 Early Production Information Appendix Page 178 of 192 SARA G3 and SARA U2 series System Integration Manual biox A 4 9 Pin out comparison between LISA and SARA G3 Table 60 summarizes the pin electrical differences between LISA and SARA G3 cellular modules Pin Name N SARA G3 series N LISA C2 series LISA U1 series LISA U2 series Power VCC 51 53 Normal op range 61 63 Normal op range Normal op range Normal op range 3 35V 4 5V 3 3V 44V 3 4V 42V 3 3V 44V Extended op range Extended op range
188. e the USB all the AT profiles are updated accordingly Refer to the u blox AT Commands Manual 3 for the definition of the interface data mode command mode and online command mode UBX 13000995 R10 Early Production Information System description Page 51 of 192 Qo OX SARA G3 and SARA U2 series System Integration Manual 1 9 1 5 Multiplexer protocol 3GPP 27 010 SARA G3 and SARA U2 series modules have a software layer with MUX functionality the 3GPP TS 27 010 Multiplexer Protocol 13 available on the UART physical link The auxiliary UART the USB and the DDC I C serial interfaces do not support the multiplexer protocol This is a data link protocol layer 2 of OSI model which uses HDLC like framing and operates between the module DCE and the application processor DTE and allows a number of simultaneous sessions over the used physical link UART or SPI the user can concurrently use AT command interface on one MUX channel and Packet Switched Circuit Switched Data communication on another multiplexer channel Each session consists of a stream of bytes transferring various kinds of data such as SMS CBS PSD GNSS AT commands in general This permits for example SMS to be transferred to the DTE when a data connection is in progress The following virtual channels are defined Channel 0 control channel Channel 1 AT and Data Channel 2 AT and Data Channel 3 AT and Data not available on SARA G300 SARA G310 module
189. e SARA U2 modules implement an integrated self protection algorithm when operating in the 3G cellular radio access technology the module reduces the transmitted power when the temperature internally sensed in the integrated 3G Power Amplifier approaches the maximum allowed internal temperature to guarantee device functionality and long life span The spreading of the Module to Ambient thermal resistance Rth M A depends on module operating condition the overall temperature distribution is influenced by the configuration of the active components during the specific mode of operation and their different thermal resistance toward the case interface Mounting a SARA G3 module on a 79 mm x 62 mm x 1 41 mm 4 Layers PCB with a high coverage of copper in still air conditions the increase of the module temperature in different modes of operation referred to idle state initial condition can be summarized as following 8 C during a GSM voice call 1 TX slot 1 RX slot at max TX power 12 C during a GPRS data transfer 2 TX slots 3 RX slots at max TX power Se The Module to Ambient thermal resistance value and the relative increase of module temperature are application dependent according to the specific mechanical deployment of the module e g application PCB dimensions and characteristics mechanical shells enclosure and air flow conditions The increase of thermal dissipation i e the Module to Ambient thermal resistance reduction will dec
190. e application board Higher protection level can be achieved by mounting an ESD protection e g EPCOS CAO5PAS14THSG varistor array close to accessible points 2 6 2 2 Guidelines for UART AUX layout design The auxiliary UART serial interface is not critical for the layout design since it is not used during normal operation of SARA G3 modules Ensure accessibility to the TXD_AUX and RXD_AUX pins providing test points on the application board UBX 13000995 R10 Early Production Information Design in Page 124 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual 2 6 3 Universal Serial Bus USB ee USB interface is not supported by SARA G3 modules 2 6 3 1 Guidelines for USB circuit design The USB_D and USB_D lines carry the USB serial data and signaling The lines are used in single ended mode for full speed signaling handshake as well as in differential mode for high speed signaling and data transfer USB pull up or pull down resistors on USB_D and USB_D as required by the Universal Serial Bus Revision 2 0 specification 14 are part of the USB pin driver and do not need to be externally provided Series resistors on USB_D and USB_D as required by Universal Serial Bus Revision 2 0 specification 14 are also integrated and do not need to be externally provided Since the module acts as a USB device the VBUS USB supply 5 0 V typ generated by the USB host must be connected to the VUSB_DET input which absorbs
191. e audible range A careful layout is required to reduce the risk of noise from audio lines due to both VCC burst noise coupling and RF detection Guidelines for the uplink path which is the most sensitive since the analog input signals are in the microVolts range are the following Avoid coupling of any noisy signal to microphone lines it is strongly recommended to route microphone lines away from module VCC supply line any switching regulator line RF antenna lines digital lines and any other possible noise source Keep ground separation from microphone lines to other noisy signals Use an intermediate ground layer or vias wall for coplanar signals Route microphone signal lines as a differential pair embedded in ground to reduce differential noise pick up The balanced configuration will help reject the common mode noise Route microphone reference as a signal line since the MIC GND pin is internally connected to ground as a sense line as the reference for the analog audio input Cross other signals lines on adjacent layers with 90 crossing Place bypass capacitor for RF very close to active microphone The preferred microphone should be designed for GSM applications which typically have internal built in bypass capacitor for RF very close to active device If the integrated FET detects the RF burst the resulting DC level will be in the pass band of the audio circuitry and cannot be filtered by any other device Guidelines for the downlink pat
192. e cleaning step after the soldering UBX 13000995 R10 Early Production Information Handling and soldering Page 160 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 3 3 5 Repeated reflow soldering Only a single reflow soldering process is encouraged for boards with a SARA G3 and SARA U2 series module populated on it The reason for this is the risk of the module falling off due to high weight in relation to the adhesive properties of the solder 3 3 6 Wave soldering Boards with combined through hole technology THT components and surface mount technology SMT devices require wave soldering to solder the THT components Only a single wave soldering process is encouraged for boards populated with SARA G3 and SARA U2 series modules 3 3 7 Hand soldering Hand soldering is not recommended 3 3 8 Rework Rework is not recommended Se Never attempt a rework on the module itself e g replacing individual components Such actions immediately terminate the warranty 3 3 9 Conformal coating Certain applications employ a conformal coating of the PCB using HumiSeal or other related coating products These materials affect the RF properties of the SARA G3 and SARA U2 series modules and it is important to prevent them from flowing into the module The RF shields do not provide 100 protection for the module from coating liquids with low viscosity therefore care is required in applying the coating Se Conformal
193. e greater than 14 Q UBX 13000995 R10 Early Production Information Design in Page 133 of 192 SARA G3 and SARA U2 series System Integration Manual biox Provide proper parts on each line connected to the receiver speaker as noise and EMI improvements to minimize RF coupling according to EMC requirements of the custom application o Mount a 27 pF bypass capacitor e g Murata GRM1555C1H270 J from each speaker line to solid ground plane C6 and C7 capacitors in Figure 76 Provide additional ESD protection e g Bourns CGO402MLE 18G varistor if the analog audio lines will be externally accessible on the application device according to the EMC ESD requirements of the custom application Mount the protection close to an accessible point of the line D1 D4 in Figure 76 SARA G340 SARA G350 MIC BIAS Gi e e R1 e R2 R4 C2 MIC P El e C3 MIC N E Microphone Connector MIC L1 R3 e e Q Ct MIC_GND e e ANNA e e J1 C4 C5 X D1 D2 Speaker SPK E Connector SPK_P E e e SPK N El e e J2 C6 C7 XX D3 D4 6 e Figure 76 Analog audio interface headset and handset mode application circuit CS Reference Description Part Number Manufacturer C1 10 pF Capacitor Ceramic X5R 0603 20 6 3 V GRM188R60J106ME47 Murata C2 C3 100 nF Capacitor Cer
194. e module Connect the UICC SIM contact C7 I O to the SIM_IO pin of the module Connect the UICC SIM contact C3 CLK to the SIM_CLK pin of the module Connect the UICC SIM contact C2 RST to the SIM_RST pin of the module Connect the UICC SIM contact C5 GND to ground Provide a 100 nF bypass capacitor e g Murata GRM155R71C104K at the SIM supply line VSIM close to the related pad of the SIM chip to prevent digital noise Provide a bypass capacitor of about 22 pF to 47 pF e g Murata GRM1555C1H470J on each SIM line VSIM SIM_CLK SIM_IO SIM_RST to prevent RF coupling especially in case the RF antenna is placed closer than 10 30 cm from the SIM card holder Limit capacitance and series resistance on each SIM signal SIM_CLK SIM_IO SIM_RST to match the requirements for the SIM interface 27 7 ns is the maximum allowed rise time on the SIM_CLK line 1 0 us is the maximum allowed rise time on the SIM_IO and SIM_RST lines SARA G3 SARA U2 V_INT Ze sIM DET EM SIM CHIP 2 VPP c6 VSIM ee 8 vcc c1 SIM 10 IEEE e 3 lo c7 HS P SIM CLK EC 6 CLK C3 iB d SIM RST ET 7 RsT C2 SIM Chip C1 C2 C3 C4 C5 l clad Contacts side U1 Figure 56 Application circuit for the connection to a single solderable SIM chip with SIM detection not implemented Reference Description Part Number Manufacturer C1 C2
195. e modules can enter the very low power idle mode reaching very low current consumption figures refer to the section 1 5 1 4 and to the SARA G3 series Data Sheet 1 and can provide the RTC functions when the RTC block is switched on since V BCKP voltage is within the valid range SARA G300 SARA G310 IN v BCkP 32 kHz Oscillator T VCC CLKOUT EJ EXT32K ET OE GND Ul L Figure 48 EXT32K application circuit using an external 32 kHz oscillator Reference Description Remarks C1 100 nF Capacitor Ceramic X7R 0402 1096 16 V GRM155R61A104KA01 Murata U1 Low Power Clock Oscillator 32 768 kHz OV 7604 C7 Micro Crystal or SG 3040LC EPSON TOYOCOM Table 31 Example of components for the EXT32K application circuit UBX 13000995 R10 Early Production Information Design in Page 100 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual The two different solutions described in Figure 47 and Figure 48 are alternative and mutually exclusive only one of the two proposed solutions must be implemented according to the required current consumption figures for the idle mode for the detailed characteristics see the SARA G3 series Data Sheet 1 As additional solution alternative and mutually exclusive to the two described in Figure 47 and Figure 48 a proper 32 kHz signal can be provided to the EXT32K input by the used application processor if capable The EXT32K input and the 32K_OUT ou
196. e the 32K_OUT output as there is no EXT32K input to feed on the modules the pin 24 constitute the GPIO3 on these modules UBX 13000995 R10 Early Production Information System description Page 36 of 192 biox SARA G3 and SARA U2 series System Integration Manual 1 7 Antenna interface 1 7 1 Antenna RF interface ANT The ANT pin of SARA G3 and SARA U2 series modules represents the RF input output for 2G or 3G cellular RF signals reception and transmission The ANT pin has a nominal characteristic impedance of 50 Q and must be connected to the antenna through a 50 O transmission line for proper RF signals reception and transmission 1 7 1 1 Antenna RF interface requirements Table 10 summarizes the requirements for the antenna RF interface ANT See section 2 4 1 for suggestions to properly design an antenna circuit compliant to these requirements A The antenna circuit affects the RF compliance of the device integrating SARA G3 and SARA U2 series module with applicable required certification schemes Compliance is guaranteed if the antenna RF interface ANT requirements summarized in Table 10 are fulfilled Item Impedance Frequency Range Return Loss Efficiency Maximum Gain Input Power Detection Requirements 50 Q nominal characteristic impedance See the SARA G3 series Data Sheet 1 and the SARA U2 series Data Sheet 2 lt 10 dB VSWR lt 2 1 recommended lt 6 dB VSWR lt 3 1 acceptabl
197. e to active mode after 20 ms this is the UART and module wake up time If the DTR line is set to ON by the DTE the module is not allowed to enter idle mode and the UART is kept enabled until the DTR line is set to OFF When the AT UPSV 3 configuration is enabled the DTR input line can still be used by the DTE to control the module behavior according to AT amp D command configuration see u blox AT Commands Manual 3 ee The CTS output line indicates the UART power saving state as illustrated in Figure 25 if HW flow control is enabled with AT UPSV 3 UBX 13000995 R10 Early Production Information System description Page 49 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Wake up via data reception The UART wake up via data reception consists of a special configuration of the module TXD input line that causes the system wake up when a low to high transition occurs on the TXD input line In particular the UART is enabled and the module switches from the low power idle mode to active mode within 20 ms from the first character received this is the system wake up time As a consequence the first character sent by the DTE when UART is disabled i e the wake up character is not a valid communication character even if the wake up via data reception configuration is active because it cannot be recognized and the recognition of the subsequent characters is guaranteed only after the complete system wake up i e
198. ection of peak radiation to that of an isotropic source The maximum gain of the antenna connected to ANT pin must not exceed the values stated in section 4 2 2 to comply with regulatory agencies radiation exposure limits The antenna connected to ANT pin must support the maximum power transmitted by the modules If antenna detection is required by the custom application proper antenna detection circuit must be implemented on the application board as described in section 2 4 2 If antenna detection is required by the custom application the external antenna assembly must be provided with proper diagnostic circuit as described in section 2 4 2 For the additional specific requirements applicable to the integration of SARA G350 ATEX modules in applications intended for use in potentially explosive atmospheres see section 2 14 UBX 13000995 R10 Early Production Information System description Page 37 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 7 2 Antenna detection interface ANT DET Se Antenna detection interface ANT_DET is not supported by SARA G300 and SARA G310 modules The antenna detection is based on ADC measurement The ANT_DET pin is an Analog to Digital Converter ADC provided to sense the antenna presence The antenna detection function provided by ANT_DET pin is an optional feature that can be implemented if the application requires it The antenna detection is forced by the UANTR AT
199. ectly received by the DTE when it is ready to receive data i e RTS line will be ON 3 Disabled AT amp KO ONorOFF Data sent by the DTE is correctly received by the module Data sent by the module is correctly received by the DTE if it is ready to receive data otherwise data are lost 3 Disabled AT amp KO ONorOFF OFF Data sent by the DTE is lost by the module Data sent by the module is correctly received by the DTE if it is ready to receive data otherwise data are lost Table 12 UART and power saving summary AT UPSV 0 power saving disabled fixed active mode The module does not enter idle mode and the UART interface is enabled data can be sent and received the CTS line is always held in the ON state after UART initialization This is the default configuration AT UPSV 1 power saving enabled cyclic idle active mode On SARA G3 modules when the AT UPSV 1 command is issued by the DTE the UART is disabled after the timeout set by the second parameter of the UPSV AT command for more details see u blox AT commands Manual 3 On SARA U2 modules when the AT UPSV 1 command is issued by the DTE the UART is immediately disabled Afterwards the UART of SARA G3 and SARA U2 series modules is periodically enabled to receive or send data and if data has not been received or sent over the UART the interface is automatically disabled whenever possible according to the timeout configured by the second paramet
200. ed the Maxim 13234E voltage level translator can be used This chip translates voltage levels from 1 8 V module side to the RS 232 standard If a 1 8 V application processor is used the circuit should be implemented as described in Figure 63 Application Processor SARA G3 SARA U2 1 8V DTE 1 8V DCE Figure 63 UART interface application circuit with partial V 24 link 5 wire in the DTE DCE serial communication 1 8 V DTE UBX 13000995 R10 Early Production Information Design in Page 120 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual If a 3 0 V Application Processor is used appropriate unidirectional voltage translators must be provided using the module V INT output as 1 8 V supply as described in Figure 64 Application Processor SARA G3 SARA U2 3 0V DTE Unidirectional 1 8V DCE Voltage Translator vcc VCCA VCCB LE V INT Rz a L DIR1 DIR3 TxD A1 B1 Figure 64 UART interface application circuit with partial V 24 link 5 wire in DTE DCE serial communication 3 0 V DTE Reference Description Part Number Manufacturer C1 C2 100 nF Capacitor Ceramic X7R 0402 10 16 V GRM155R61A104KA01 Murata U1 Unidirectional Voltage Translator SN74AVC4T774 Texas Instruments Table 42 Component for UART application circuit with partial V 24 link 5 wire in DTE DCE serial communication 3 0 V DTE If only
201. edance computation To achieve a 50 characteristic impedance the width of the transmission line must be chosen depending on e the thickness of the transmission line itself e g 35 um in the example of Figure 50 and Figure 51 e the thickness of the dielectric material between the top layer where the transmission line is routed and the inner closer layer implementing the ground plane e g 270 um in Figure 50 1510 um in Figure 51 e the dielectric constant of the dielectric material e g dielectric constant of the FR 4 dielectric material in Figure 50 and Figure 51 e the gap from the transmission line to the adjacent ground plane on the same layer of the transmission line e g 500 um in Figure 50 400 um in Figure 51 If the distance between the transmission line and the adjacent GND area on the same layer does not exceed 5 times the track width of the micro strip use the Coplanar Waveguide model for the 50 Q calculation UBX 13000995 R10 Early Production Information Design in Page 104 of 192 VP biox SARA G3 and SARA U2 series System Integration Manual Additionally to the 50 Q impedance the following guidelines are recommended for the transmission line design e Minimize the transmission line length the insertion loss should be minimized as much as possible in the order of a few tenths of a dB e Add GND keep out i e clearance a void area on buried metal layers below any pad of component present on the RF transmi
202. ee mode an external audio amplifier must be provided on the application board to amplify the low power audio signal provided by the downlink path of the module so that the external audio amplifier will drive the 8 Q or 4 Q loudspeaker since differential analog audio output of the module is able to directly drive loads with resistance rating greater than 14 O As in the example circuit in Figure 77 follow the general guidelines for the design of an analog audio circuit for hands free mode Provide proper supply to the used electret microphone providing a proper connection from the MIC BIAS supply output to the microphone It is suggested to implement a bridge o The electret microphone with its nominal intrinsic resistance value represents one resistor of the bridge o To achieve good supply noise rejection the ratio of the two resistance in one leg R2 R3 should be equal to the ratio of the two resistance in the other leg RA MIC i e R2 has to be equal to R4 e g 2 2 kQ and R3 must be equal to the microphone nominal intrinsic resistance value e g 2 2 kQ Provide a series resistor at the MIC BIAS supply output and then mount a good bypass capacitor to provide additional supply noise filtering as the R1 series resistor 2 2 kQ and the C1 bypass capacitor 10 pF Do not place a bypass capacitor directly at the MIC BIAS supply output since proper internal bypass capacitor is already provided to guarantee stable operation of the int
203. een the switching regulator output to VCC supply pins can mitigate the ripple on VCC but adds extra voltage drop due to resistive losses on series inductors UBX 13000995 R10 Early Production Information Design in Page 84 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual PWM mode operation it is preferable to select regulators with Pulse Width Modulation PWM mode While in connected mode Pulse Frequency Modulation PFM mode and PFM PWM mode transitions must be avoided to reduce the noise on the VCC voltage profile Switching regulators that are able to switch between low ripple PWM mode and high efficiency burst or PFM mode can be used provided the mode transition occurs when the module changes status from idle active mode to connected mode where current consumption increases to a value greater than 100 mA it is permissible to use a regulator that switches from the PWM mode to the burst or PFM mode at an appropriate current threshold e g 60 mA Output voltage slope the use of the soft start function provided by some voltage regulators should be carefully evaluated since the VCC pins voltage must ramp from 2 5 V to 3 2 V in less than 1 ms to switch on the SARA U2 modules or in less than 4 ms to switch on the SARA G3 modules by applying VCC supply that otherwise can be switched on by forcing a low level on the RESET N pin during the VCC rising edge and then releasing the RESET N pin when the VCC supply voltage stab
204. eet 1 The following maximum input and equivalent parameters must be considered in sub division IIC Ui 2 3 8V li 2 1 6 A burst Pi 2 5W Ci 103 pF Li 2 4 1 uH The following maximum input and equivalent parameters must be considered in sub divisions IIB IIA Ui 24 2V li 2 5 A burst Pi 2 5 W Ci 103 uF Li 4 1 uH UBX 13000995 R10 Early Production Information Approvals Page 167 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 5 Product testing 5 1 u blox in series production test u blox focuses on high quality for its products All units produced are fully tested Defective units are analyzed in detail to improve the production quality This is achieved with automatic test equipment which delivers a detailed test report for each unit The following measurements are done e Digital self test firmware download Flash firmware verification IMEI programming e Measurement of voltages and currents e Adjustment of ADC measurement interfaces e Functional tests Serial interface communication analog audio interface real time clock temperature sensor antenna detection SIM card communication e Digital tests GPIOs digital interfaces e Measurement and calibration of RF characteristics in all supported bands Receiver S N verification frequency tuning of reference clock calibration of transmitter and receiver power levels e Verification of RF characteristics after calibration modulati
205. efault UART disabled UART enabled UART enabled Figure 25 CTS behavior with power saving enabled AT UPSV 1 and HW flow control enabled the CTS output line indicates when the UART interface of the module is enabled CTS ON low level or disabled CTS OFF high level UBX 13000995 R10 Early Production Information System description Page 48 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual AT UPSV 2 power saving enabled and controlled by the RTS line This configuration can only be enabled with the module hardware flow control disabled by AT amp KO command The UART interface is immediately disabled after the DTE sets the RTS line to OFF Then the module automatically enters idle mode whenever possible according to any required activity related to the network or any other required activity related to the functions interfaces of the module The UART is disabled as long as the RTS line is held to OFF but the UART is enabled in the following cases If the module needs to transmit some data over the UART e g URC On SARA G3 modules during a CSD data call and a PSD data call with external context activation On SARA G3 modules during a voice call On SARA G3 modules if a data is sent by the DTE it causes the system wake up due to the wake up via data reception feature described in the following subsection and the UART will be then kept enabled after the last data received according to the timeout previously s
206. eference clock simplified block diagram The RTC provides the module time reference date and time that is used to set the wake up interval during the idle mode periods between network paging and is able to make available the programmable alarm functions The RTC functions are available also in power down mode when the V BCKP voltage is within its valid range specified in the Input characteristics of Supply Power pins table in the SARA G3 series Data Sheet 1 and SARA U2 series Data Sheet 2 and for SARA G300 SARA G310 modules only when their EXT32K input pin is fed by an external 32 768 kHz signal with proper characteristics specified in the EXT32K pin characteristics table in SARA G3 series Data Sheet 1 See the u blox AT Commands Manual 3 for more details The RTC can be supplied from an external back up battery through the V BCKP when the main voltage supply is not provided to the module through VCC This lets the time reference date and time run until the V BCKP voltage is within its valid range even when the main supply is not provided to the module The RTC oscillator does not necessarily stop operation i e the RTC counting does not necessarily stop when V BCKP voltage value drops below the specified operating range minimum limit 1 00 V the RTC value read after a system restart could be not reliable as explained in Table 8 V BCKP voltage value RTC value reliability Notes 1 00 V V BCKP 2 40 V RTC oscillator doe
207. emarks By default the pin is configured to provide SIM card detection function The pin cannot be alternatively configured by the UGPIOC command By default the pin is configured to provide SIM card detection function Can be alternatively configured by the UGPIOC command as Output Input Network Status Indication GNSS Supply Enable Module Operating Mode Indication gt Pin disabled By default the pin is configured to provide l S word alignment function Can be alternatively configured by the UGPIOC command as Output Inpu Pin disabled By default the pin is configured to provide I S data output function Can be alternatively configured by the UGPIOC command as Output Inpu Pin disabled By default the pin is configured to provide IS clock function Can be alternatively configured by the UGPIOC command as Output Inpu Pin disabled By default the pin is configured to provide I S data input function Can be alternatively configured by the UGPIOC command as Output Inpu Pin disabled Early Production Information System description Page 67 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 13System features 1 13 1 Network indication Se Not supported by SARA G300 and SARA G310 modules The GPIO1 or the GPIO2 GPIO3 GPIO4 and on SARA U2 series only the SIM_DET alternatively from their default settings can be configured to indicate network status i e no service registered home network
208. emperature rise rate max 3 C s If the temperature rise is too rapid in the preheat phase it may cause excessive slumping Time 60 to 120s If the preheat is insufficient rather large solder balls tend to be generated Conversely if performed excessively fine balls and large balls will be generated in clusters End Temperature 150 to 200 C If the temperature is too low non melting tends to be caused in areas containing large heat capacity Heating reflow phase The temperature rises above the liquidus temperature of 217 C Avoid a sudden rise in temperature as the slump of the paste could become worse Limit time above 217 C liquidus temperature 40 to 60 s Peak reflow temperature 245 C Cooling phase A controlled cooling avoids negative metallurgical effects solder becomes more brittle of the solder and possible mechanical tensions in the products Controlled cooling helps to achieve bright solder fillets with a good shape and low contact angle Temperature fall rate max 4 C s UBX 13000995 R10 Early Production Information Handling and soldering Page 159 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual ee To avoid falling off modules should be placed on the topside of the motherboard during soldering The soldering temperature profile chosen at the factory depends on additional external factors like choice of soldering paste size thickness and properties of the base board etc A Exceed
209. enna PCB antennas such as patches or ceramic SMT elements o Internal integrated antenna implies physical restriction to the design of the PCB the ground plane can be reduced down to a minimum size that must be similar to the quarter of the wavelength of the minimum frequency that has to be radiated As numerical example Frequency 824 MHz gt Wavelength 36 4 cm gt Minimum GND plane size 9 1 cm o The radiation performance depends on the whole PCB and antenna system design including product mechanical design and usage select the antenna with optimal radiating performance in the operating bands according to the mechanical specifications of the PCB and the whole product o Select a complete custom antenna designed by an antenna manufacturer if the required ground plane dimensions are very small e g less than 6 5 cm long and 4 cm wide the antenna design process should begin at the start of the whole product design process o Select an integrated antenna solution provided by an antenna manufacturer if the required ground plane dimensions are large enough according to the related integrated antenna solution specifications the antenna selection and the definition of its placement in the product layout should begin at the start of the product design process o lt is highly recommended to strictly follow the detailed and specific guidelines provided by the antenna manufacturer regarding correct installation and deployment of the antenna sy
210. er of the UPSV AT command The module automatically enters the low power idle mode whenever possible but it wakes up to active mode according to the UART periodic wake up so that the module cyclically enters the low power idle mode and the active mode Additionally the module wakes up to active mode according to any required activity related to the network or any other required activity related to the functions interfaces of the module The UART is enabled and the module does not enter low power idle mode in the following cases During the periodic UART wake up to receive or send data If the module needs to transmit some data over the UART e g URC On SARA G3 modules during a CSD data call and a PSD data call with external context activation On SARA G3 modules during a voice call If a character is sent by the DTE with HW flow control disabled the first character sent causes the system wake up due to the wake up via data reception feature described in the following subsection and the UART will be then kept enabled after the last data received according to the timeout set by the second parameter of the AT UPSV 1 command The module outside an active call periodically wakes up from idle mode to active mode to monitor the paging channel of the current base station paging block reception according to 2G or 3G discontinuous reception DRX specification UBX 13000995 R10 Early Production Information System description Page 47 of 192
211. erface application circuit implemented in the EMC ESD approved reference design of SARA G3 modules is described in Figure 57 and Table 38 section 2 5 Other pins and interfaces All the module pins that are externally accessible on the device integrating SARA G3 and SARA U2 series module should be included in the ESD immunity test since they are considered to be a port as defined in ETSI EN 301 489 1 19 Depending on applicability to satisfy ESD immunity test requirements according to ESD category level all the module pins that are externally accessible should be protected up to 4 kV for direct Contact Discharge and up to x8 kV for Air Discharge applied to the enclosure surface The maximum ESD sensitivity rating of all the other pins of the module is 1 kV Human Body Model according to JESD22 A114 Higher protection level could be required if the related pin is externally accessible on the application board The following precautions are suggested to achieve higher protection level A very low capacitance i e less or equal to 1 pF ESD protection device e g Tyco Electronics PESD0402 140 should be mounted on each high speed USB line close to accessible points i e close to the USB connector A general purpose ESD protection device e g EPCOS CAO5P4S14THSG or EPCOS CT0402S14AHSG varistor should be mounted on each generic interface line close to accessible point UBX 13000995 R10 Early Production Information Design in Page 149 of 19
212. erface pins is 1 kV Human Body Model according to JESD22 A114 Higher protection level could be required if the lines are externally accessible on the application board Higher protection level can be achieved by mounting a general purpose ESD protection e g EPCOS CAO5P4S14THSG varistor array close to accessible points If the lS digital audio pins are not used they can be left unconnected on the application board 2 7 2 2 Guidelines for digital audio layout design The l S interfaces lines I2S CLK I2S RX I2S TX I2S WA require the same consideration regarding electro magnetic interference as any other digital interface Keep the traces short and avoid coupling with RF lines parts or sensitive analog inputs since the signals can cause the radiation of some harmonics of the digital data frequency UBX 13000995 R10 Early Production Information Design in Page 141 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual 2 8 General Purpose Input Output GPIO 2 8 1 1 Guidelines for GPIO circuit design The following application circuits are suggested as a general guideline for the usage of the GPIO pins available with the SARA G340 SARA G350 and SARA U2 series modules according to the related custom function Figure 81 describes an application circuit for a typical usage of some GPIO functions of the modules Network indication function provided by the GPIO1 pin GNSS supply enable function provided by the GPIO2
213. ernal regulator Connect the reference of the microphone circuit to the MIC GND pin of the module as a sense line Provide a proper series capacitor at both MIC P and MIC N analog uplink inputs for DC blocking C2 and C3 100 nF Murata GRM155R71C104K capacitors in Figure 77 This provides a high pass filter for the microphone DC bias with proper cut off frequency according to the value of the resistors of the microphone supply circuit Then connect the signal lines to the microphone Provide proper parts on each line connected to the external microphone as noise and EMI improvements to minimize RF coupling and TDMA noise according to the custom application requirements o Mount an 82 nH series inductor with a Self Resonance Frequency 1 GHz e g the Murata LQG15HS82NJO2 on each microphone line L1 and L2 inductors in Figure 77 o Mount a 27 pF bypass capacitor e g Murata GRM1555C1H270J from each microphone line to solid ground plane C4 and C5 capacitors in Figure 77 Use a microphone designed for GSM applications which typically have internal built in bypass capacitor Provide a 47 nF series capacitor at both SPK P and SPK N analog downlink outputs for DC blocking C8 and C9 Murata GRM155R71C473K capacitors in Figure 77 Then connect the lines to the differential input of a proper external audio amplifier differential output which must be connected to the 8Q or 4 Q loudspeaker See the Analog Devices SSM2305CPZ filter less mono 2 8 W class
214. ervice CBS Release 1999 3GPP TS 27 010 Terminal Equipment to User Equipment TE UE multiplexer protocol Release 1999 Universal Serial Bus Revision 2 0 specification http Awww usb org developers docs I2C bus specification and user manual Rev 5 9 October 2012 NXP Semiconductors http www nxp com documents user manual UM 10204 pdf 3GPP TS 51 010 2 Technical Specification Group GSM EDGE Radio Access Network Mobile Station MS conformance specification Part 2 Protocol Implementation Conformance Statement PICS 3GPP TS 34 121 2 Technical Specification Group Radio Access Network User Equipment UE conformance specification Radio transmission and reception FDD Part 2 Implementation Conformance Statement ICS CENELEC EN 61000 4 2 2001 Electromagnetic compatibility EMC Part 4 2 Testing and measurement techniques Electrostatic discharge immunity test ETSI EN 301 489 1 V1 8 1 Electromagnetic compatibility and Radio spectrum Matters EMC standard for radio equipment and services Part 1 Common technical requirements ETSI EN 301 489 7 V1 3 1 Electromagnetic compatibility and Radio spectrum Matters EMC standard for radio equipment and services Part 7 Specific conditions for mobile and portable radio and ancillary equipment of digital cellular radio telecommunications systems GSM and DCS ETSI EN 301 489 24 V1 4 1 Electromagnetic compatibility and Radio spectrum Matters EMC standard for radio equip
215. es that may act as master or slave The same mode PCM short alignment mode or Normal S mode long alignment mode The same sample rate and serial clock frequency Compatible voltage levels 1 80 V typ otherwise the lines must be connected by means of a proper unidirectional voltage translator e g Texas Instruments SN74AVC4T774 or SN74AVC2T245 Figure 79 and Table 53 describe an application circuit example for the l S digital audio interface of SARA U2 modules providing voice capability using an external audio voice codec DAC and ADC integrated in the external audio codec respectively converts an incoming digital data stream to analog audio output through a mono amplifier and converts the microphone input signal to the digital bit stream over the digital audio interface The module s I S interface l S master is connected to the related pins of the external audio codec I S slave The V INT output supplies the external audio codec defining proper digital interfaces voltage level The external audio codec is controlled by the SARA U2 module using the DDC lC interface this interface can be concurrently used to communicate with u blox GNSS receivers and with an external audio codec The CODEC CLK pin of the SARA U2 module that provides a suitable digital output clock is connected to the clock input of the external audio codec to provide clock reference Additional components are provided for EMC and ESD immunity conformity a 10 nF
216. es with minor other corrections and clarifications Updated SSL supported features Added SARA G350 CCC mark Early Production Information Revision history Page 191 of 192 biox Contact SARA G3 and SARA U2 series System Integration Manual For complete contact information visit us at www u blox com u blox Offices North Central and South America u blox America Inc Phone 1 703 483 3180 E mail info_us u blox com Regional Office West Coast Phone 1 408 573 3640 E mail info_us u blox com Technical Support Phone 1 703 483 3185 E mail support_us u blox com UBX 13000995 R10 Headquarters Europe Middle East Africa u blox AG Phone 41 44 722 74 44 E mail info u blox com Support supportQu blox com Early Production Information Asia Australia Pacific u blox Singapore Pte Ltd Phone 65 6734 3811 E mail info_ap u blox com Support support apQu blox com Regional Office Australia Phone 61 2 8448 2016 E mail info_anz u blox com Support support apQu blox com Regional Office China Beijing Phone 86 10 68 133 545 E mail info cnQu blox com Support support cnQu blox com Regional Office China Shenzhen Phone 86 755 8627 1083 E mail info cnQu blox com Support support cnQu blox com Regional Office India Phone 91 959 1302 450 E mail info inQu blox com Support support inQu blox com Regional Office Japan Phone 81 3 5775 3850 E mail info jpQu blox
217. es as well as antenna circuit design Compliance is guaranteed if the VCC requirements summarized in the Table 7 are fulfilled Se For the additional specific requirement for SARA G350 ATEX modules integration in potentially explosive atmospheres applications see section 2 14 Item Requirement Remark VCC nominal voltage Within VCC normal operating range The module cannot be switched on if VCC voltage value 3 35 V min 4 50 V max for SARA G3 series is below the normal operating range minimum limit 3 30 V min 4 40 V max for SARA U2 series Ensure that the input voltage at VCC pins is above the minimum limit of the normal operating range for at least more than 3 s after the module switch on VCC voltage during Within VCC extended operating range The module may switch off when VCC voltage drops normal operation 3 00 V min 4 50 V max for SARA G3 series below the extended operating range minimum limit 3 10 V min 4 50 V max for SARA U2 series Operation above extended operating range limit is not recommended and may affect device reliability VCC average current Support with adequate margin the highest averaged The highest averaged VCC current consumption can be VCC current consumption value in connected mode greater than the specified value according to the actual conditions specified in SARA G3 series Data Sheet 1 antenna mismatching temperature and VCC voltage and in SARA U2 series Data Sheet 2 See 1 5 1 2 1 5 1 3 for connecte
218. et with the AT UPSV 1 configuration When an OFF to ON transition occurs on the RTS input line the UART is re enabled and the module if it was in idle mode switches from idle to active mode after 20 ms this is the UART and module wake up time If the RTS line is set to ON by the DTE the module is not allowed to enter the low power idle mode and the UART is kept enabled ee On SARA G3 modules the CTS output line indicates the power saving state as illustrated in Figure 25 even with AT UPSV 2 AT UPSV 3 power saving enabled and controlled by the DTR line Se The AT UPSV 3 power saving configuration is not supported by SARA G3 modules The AT UPSV 3 configuration can be enabled regardless the flow control setting on UART In particular the HW flow control can be enabled AT amp K3 or disabled AT amp KO on UART during this configuration The UART interface is immediately disabled after the DTE sets the DTR line to OFF Then the module automatically enters idle mode whenever possible according to any required activity related to the network or any other required activity related to the functions interfaces of the module The UART is disabled as long as the DTR line is set to OFF but the UART is enabled in the following cases If the module needs to transmit some data over the UART e g URC When an OFF to ON transition occurs on the DTR input line the UART is re enabled and the module if it was in idle mode switches from idl
219. facturers of mobile or fixed devices incorporating SARA G310 SARA G350 SARA U260 SARA U280 modules are authorized to use the FCC Grants and Industry Canada Certificates of the SARA G310 SARA G350 SARA U260 SARA U280 modules for their own final products according to the conditions referenced in the certificates The FCC Label shall in the above case be visible from the outside or the host device shall bear a second label stating For SARA G310 and SARA G350 modules Contains FCC ID XPYSARAG350 resp For SARA U260 modules Contains FCC ID XPYSARAU260 resp For SARA U280 modules to be defined The IC Label shall in the above case be visible from the outside or the host device shall bear a second label stating For SARA G310 and SARA G350 modules Contains IC 8595A SARAG350 resp For SARA U260 modules Contains IC 8595A SARAU260 resp For SARA U280 modules to be defined Canada Industry Canada IC Notices This Class B digital apparatus complies with Canadian CAN ICES 3 B NMB 3 B and RSS 210 Operation is subject to the following two conditions o this device may not cause interference o this device must accept any interference including interference that may cause undesired operation of the device Radio Frequency RF Exposure Information The radiated output power of the u blox Cellular Module is below the Industry Canada IC radio frequency exposure limits The u blox Cellular Module should be used in such a manner
220. few microamperes to sense the host connection and enable the USB interface of the module If connecting the USB_D and USB_D pins to a USB device connector the pin will be externally accessible on the application device According to EMC ESD requirements of the application an additional ESD protection device with very low capacitance should be provided close to accessible point on the line connected to this pin as described in Figure 69 and Table 45 Se The USB interface pins ESD sensitivity rating is 1 kV Human Body Model according to JESD22 A114F Higher protection level could be required if the lines are externally accessible and it can be achieved by mounting a very low capacitance i e less or equal to 1 pF ESD protection e g Tyco Electronics PESD0402 140 ESD protection device on the lines connected to these pins close to accessible points The USB pins of the modules can be directly connected to the USB host application processor without additional ESD protections if they are not externally accessible or according to EMC ESD requirements USB DEVICE USB HOST CONNECTOR SARA U2 series PROCESSOR SARA U2 series VBUS s e VUSB DET VBUS Bl e VUSB DET D e EJ USB_D D MN EN Usb p D E USB_D D Bl EJ USB_D X kan aaa D1 D2 D3 C1 C1 GND oe o e EN cub GND EN e EN GND Figure 69 USB Interface application circuits Reference Descripti
221. gt t the device is working outside the specified range and represents a dangerous working condition This condition is indicated and the device shuts down to avoid damage ee For security reasons the shutdown is suspended in case an emergency call in progress In this case the device switches off at call termination Se The user can decide at anytime to enable disable the Smart Temperature Supervisor feature If the feature is disabled there is no embedded protection against disallowed temperature conditions UBX 13000995 R10 Early Production Information System description Page 72 of 192 Qo OX SARA G3 and SARA U2 series System Integration Manual Figure 31 shows the flow diagram implemented in the SARA G340 and SARA G350 modules for the Smart Temperature Supervisor IF STS enabled Feature enabled Yes full logic or indication only Feature disabled no action Read temperature Temperature is within normal operating range Previously outside of Safe Area No further actions Yes Tempetature is outside valid temperature range Tempetature is back to safe area Tempetature is within warning area Send notification Send notification dangerous Send notification safe IF Full Logic Enabled Feature enabled in indication only mode no further actions Featuere enabled Yes in full
222. gure 76 shows an application circuit for the analog audio interface in headset and handset modes connecting a 2 2 kO electret microphone and a 16 Q receiver speaker External microphone can be connected to the uplink path of the module since the module provides supply and reference as well as differential signal input for the external microphone A 16 Q receiver speaker can be directly connected to the balanced output of the module since the differential analog audio output of the module is able to directly drive loads with resistance rating greater than 14 Q As in the example circuit in Figure 76 follow the general guidelines for the design of an analog audio circuit for both headset and handset modes Provide proper supply to the used electret microphone providing a proper connection from the MIC BIAS supply output to the microphone It is suggested to implement a bridge structure o The electret microphone with its nominal intrinsic resistance value represents one resistor of the bridge o To achieve good supply noise rejection the ratio of the two resistance in one leg R2 R3 should be equal to the ratio of the two resistance in the other leg R4 MIC i e R2 has to be equal to R4 e g 2 2 kQ and R3 has to be equal to the microphone nominal intrinsic resistance value e g 2 2 kQ Provide a proper series resistor at the MIC BIAS supply output and then mount a proper large bypass capacitor to provide additional supply noise fil
223. h are the following The physical width of the audio output lines on the application board must be wide enough to minimize series resistance since the lines are connected to low impedance speaker transducer Avoid coupling of any noisy signal to speaker lines it is recommended to route speaker lines away from module VCC supply line any switching regulator line RF antenna lines digital lines and any other possible noise source Route speaker signal lines as a differential pair embedded in ground up to reduce differential noise pick up The balanced configuration will help reject the common mode noise Cross other signals lines on adjacent layers with 90 crossing Place bypass capacitor for RF close to the speaker UBX 13000995 R10 Early Production Information Design in Page 138 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 2 7 2 Digital audio interface Se SARA G300 and SARA G310 modules do not provide digital audio interface 2 7 2 1 Guidelines for digital audio circuit design The l S digital audio interface of SARA G3 and SARA U2 series modules can be connected to an external digital audio device for voice applications Any external digital audio device compliant to the configuration of the digital audio interface of the cellular module can be used given that the external digital audio device has to provide The opposite role slave for SARA G3 modules that act as master only slave or master for SARA U2 modul
224. he GLONASS positioning system When activated the in vehicle systems IVS automatically initiate an emergency call carrying both voice and data including location data directly to the nearest Public Safety Answering Point PSAP to determine whether rescue services should be dispatched to the known position GPS GLONASS satellites a gt ri Cellular network M 0 adj 41 See Public Safety LE S j aa In vehicle emergency call system voice data Figure 32 eCall and ERA GLONASS automated emergency response systems diagram flow For more details regarding the In Band modem solution for the European eCall and the Russian ERA GLONASS emergency call applications see the u blox eCall ERA GLONASS Application Note 29 1 13 16 SIM Access Profile SAP Se Not supported by SARA G3 modules SIM access profile SAP feature allows SARA U2 modules to access and use a remote U SIM card instead of the local SIM card directly connected to the module U SIM interface SARA U2 modules provide a dedicated USB SAP channel and dedicated multiplexer SAP channel over UART for communication with the remote U SIM card The communication between SARA U2 modules and the remote SIM is conformed to client server paradigm the SARA U2 module is the SAP client establishing a connection and performing data exchange to an SAP server directly connected to the remote SIM that is used by SARA U2 module for GSM UMTS network operations The SAP communicat
225. he modules pins layout while the proposed stencil apertures layout is slightly different see the F H I J O parameters compared to the F H I J O ones The Non Solder Mask Defined NSMD pad type is recommended over the Solder Mask Defined SMD pad type implementing the solder mask opening 50 um larger per side than the corresponding copper pad The recommended solder paste thickness is 150 um according to application production process requirements B B MNEEEEEHHEN 5 LERERERER RR e a ma eee ee Zummmuu MB m Hum t am Hum M2 M2 m E Mm E EH MHA EX EN mm un E EN m ee M E m EH zi EH ae m BE zm HE MS NM EH ON Hum muENNENZ Pl ar MANN mi I L1 Li LE Figure 83 SARA G3 and SARA U2 series modules suggested footprint and paste mask application board top view Parameter Value Parameter Value Parameter Value A 26 0 mm G 1 10 mm K 2 75 mm B 16 0 mm H 0 80 mm L 2 75 mm C 3 00 mm H 0 75 mm M1 1 80 mm D 2 00 mm r 1 50 mm M2 3 60 mm E 2 50 mm 1 55 mm N 2 10 mm F 1 05 mm J 0 30 mm O 1 10 mm FY 1 00 mm J 0 35 mm Oo 1 05 mm Table 55 SARA G3 and SARA U2 series modules suggested footprint and paste mask dimensions ee These are recommendations only and not specifications The exact copper solder and paste mask geometries distances stencil thicknesses and solder paste volumes mu
226. he normal operating range Alternately the RESET_N pin can be held low during the VCC rising edge so that the module switches on by releasing the RESET_N pin when the VCC voltage stabilizes at its nominal value within the normal range The status of the PWR_ON input pin of SARA G3 and SARA U2 series modules while applying the VCC module supply is not relevant during this phase the PWR_ON pin can be set high or low by the external circuit When the SARA G3 and SARA U2 series modules are in the power off mode i e switched off by means of the AT CPWROFF command with valid VCC module supply applied they can be switched on by Low level pulse on PWR_ON pin which is normally set high by an external pull up for a valid time period As described in Figure 17 there is no internal pull up resistor on the PWR_ON pin of the modules the pin has high input impedance and is weakly pulled high by the internal circuit Therefore the external circuit must be able to hold the high logic level stable e g providing an external pull up resistor for design in see section 2 3 1 The PWR_ON input voltage thresholds are different from the other generic digital interfaces of the modules refer to SARA G3 series Data Sheet 1 and SARA U2 series Data Sheet 2 for detailed electrical characteristics SARA G3 SARA U2 series Power Baseband Management Processor PWR ON KElI Power on gt Power on
227. he paging period can vary from 640 ms DRX 6 i e length of 26 3G frames 64 x 10 ms up to 5120 ms DRX 9 length of 29 3G frames 512 x 10 ms Figure 11 roughly describes the current consumption profile of SARA G300 and SARA G310 modules when their EXT32K input pin is fed by an external 32 kHz signal with characteristics compliant to the one specified in SARA G3 series Data Sheet 1 or the SARA G340 and SARA G350 modules or the SARA U2 modules when power saving is enabled The module is registered with the network automatically enters the very low power idle mode and periodically wakes up to active mode to monitor the paging channel for paging block reception Current mA 100 60 120 mA 50 IDLE MODE 2G case 0 44 2 09 s 3G case 0 61 5 09 s Time s ACTIVE MODE Current mA 20 30 ms 100 60 120 mA 50 20 40 mA Active Mode RX DSP Idle Mode Time ms Enabled Enabled Enabled Enabled E 20 30 ms T IDLE MODE ACTIVE MODE IDLE MODE Figure 11 VCC current consumption profile versus time of the SARA G300 and SARA G310 modules with the EXT32K input fed by a proper external 32 kHz signal or the SARA G340 and SARA G350 modules or the SARA U2 modules when registered with the network with power saving enabled the very low power idle mode is reached and periodical wake up to active mode are performed to monitor the paging channel UBX 130009
228. high level voltage of the push pull output pin of the application processor is greater than the maximum input voltage operating range of the V_BCKP pin refer to the SARA G3 series Data Sheet 1 and the SARA U2 series Data Sheet 2 the V_BCKP supply cannot be used to bias the pull up resistor the supply rail of the application processor or the module VCC supply could be used but this increases the V_BCKP RTC supply current consumption when the module is in not powered mode VCC supply not present Using a push pull output of the external device take care to fix the proper level in all the possible scenarios to avoid an inappropriate module switch on SARA G3 series Application SARA G3 series SARA U2 series Processor SARA U2 series V BCKP V BCKP Power on Rext open Rext Drain push button T Output TP aliis P sue e PWR ON PWR ON x ESD Figure 45 PWR_ON application circuits using a push button and an open drain output of an application processor Reference Description Remarks Rext 100 kQ Resistor 0402 5 0 1 W External pull up resistor ESD CT0402S14AHSG EPCOS Varistor array for ESD protection Table 29 Example of pull up resistor and ESD protection for the PWR_ON application circuit e It is recommended to provide direct access to the PWR_ON pin on the application board by means of accessible testpoint directly connected to the PWR_ON pin UBX 13000995 R10 Early Production Infor
229. hus allowing to calculate the position in a shorter time with higher accuracy SARA G340 SARA G350 and SARA U2 modules support these GNSS aiding types Local aiding AssistNow Online AssistNow Offline AssistNow Autonomous The embedded GNSS aiding features can be used only if the DDC IC interface of the cellular module is connected to the u blox GNSS receivers SARA G340 SARA G350 and SARA U2 cellular modules provide additional custom functions over GPIO pins to improve the integration with u blox positioning chips and modules GPIO pins can handle GNSS receiver power on off GNSS supply enable function provided by GPIO2 improves the positioning receiver power consumption When the GNSS functionality is not required the positioning receiver can be completely switched off by the cellular module that is controlled by AT commands The wake up from idle mode when the GNSS receiver is ready to send data GNSS data ready function provided by GPIO3 improves the cellular module power consumption When power saving is enabled in the cellular module by the AT UPSV command and the GNSS receiver does not send data by the DDC I C interface the module automatically enters idle mode whenever possible With the GNSS data ready function the GNSS receiver can indicate to the cellular module that it is ready to send data by the DDC C interface the positioning receiver can wake up the cellular module if it is in idle mode so the cellular module
230. ial pair with 30 Q common mode impedance Route analog audio signals away from noisy sources primarily RF interface VCC switching supplies The audio outputs lines on the application board must be wide enough to minimize series resistance Keep routing short and minimize parasitic capacitance on the SIM lines to preserve signal integrity Ensure optimal thermal dissipation from the module to the ambient in particular for SARA U2 modules NANNNANAAAAN ER K 2 16 3 Antenna checklist v Antenna termination should provide 50 characteristic impedance with V S W R at least less than 3 1 recommended 2 1 on operating bands in deployment geographical area Follow the recommendations of the antenna producer for correct antenna installation and deployment PCB layout and matching circuitry v v Follow the additional guidelines for products marked with the FCC logo United States only reported in section 4 2 2 v Follow the guidelines in section 2 4 2 to get proper antenna detection functionality if required UBX 13000995 R10 Early Production Information Design in Page 157 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 3 Handling and soldering Se No natural rubbers no hygroscopic materials or materials containing asbestos are employed 3 1 Packaging shipping storage and moisture preconditioning For information pertaining to reels and tapes Moisture Sensitivity levels MSD shipment and storag
231. ight 2014 u blox AG Trademark Notice Microsoft and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and or other countries All other registered trademarks or trademarks mentioned in this document are property of their respective owners UBX 13000995 R10 Page 2 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual Preface u blox Technical Documentation As part of our commitment to customer support u blox maintains an extensive volume of technical documentation for our products In addition to our product specific technical data sheets the following manuals are available to assist u blox customers in product design and development AT Commands Manual This document provides the description of the AT commands supported by the u blox cellular modules System Integration Manual This document provides the description of u blox cellular modules system from the hardware and the software point of view it provides hardware design guidelines for the optimal integration of the cellular modules in the application device and it provides information on how to set up production and final product tests on application devices integrating the cellular modules Application Notes These documents provide guidelines and information on specific hardware and or software topics on u blox cellular modules See Related documents for a list of application notes related to your cellular module
232. ignal behavior The RI module output line is set by default to the OFF state high level at UART initialization Then during an incoming call the RI line is switched from the OFF state to the ON state with a 4 1 duty cycle and a 5 s period ON for 1 s OFF for 4 s see Figure 23 until the DTE attached to the module sends the ATA string and the module accepts the incoming data call The RING string sent by the module DCE to the serial port at constant time intervals is not correlated with the switch of the RI line to the ON state 1s RI OFF RI ON TT 0 5 10 15 time s Call incomes Figure 23 RI behavior during an incoming call The RI line can notify an SMS arrival When the SMS arrives the RI line switches from OFF to ON for 1 s see Figure 24 if the feature is enabled by the AT CNMI command see the u blox AT Commands Manual 3 1s lt gt RI OFF RI ON gt time s SMS arrives Figure 24 RI behavior at SMS arrival This behavior allows the DTE to stay in power saving mode until the DCE related event requests service For SMS arrival if several events coincidently occur or in quick succession each event independently triggers the RI line although the line will not be deactivated between each event As a result the RI line may stay to ON for more than 1 s If an incoming call is answered within less than 1 s with ATA or if auto answering is set to ATSO 1 than the RI line is set to OFF earlier
233. ilizes at its proper nominal value Figure 36 and the components listed in Table 21 show an example of a high reliability power supply circuit where the module VCC is supplied by a step down switching regulator capable of delivering to VCC pins the specified maximum peak pulse current with low output ripple and with fixed switching frequency in PWM mode operation greater than 1 MHz AN L SARA G3 SARA U2 4 VIN VCC R1 3 RUN BD H m e vcc 9 211 6 vcc vC BOOST ipe za TT 10 RT sw lB i e C7 C8 7g Ul ELE Ali R2 R3 sync re S e C1 C2 C3 C4 C5 GND 11 R5 MEM GND Figure 36 Suggested schematic design for the VCC voltage supply application circuit using a step down regulator Reference Description Part Number Manufacturer C1 10 uF Capacitor Ceramic X7R 5750 1596 50 V C5750X7R1H106MB TDK C2 10 nF Capacitor Ceramic X7R 0402 1096 16 V GRM155R71C103KA01 Murata C3 680 pF Capacitor Ceramic X7R 0402 1096 16 V GRM155R71H681KA01 Murata C4 22 pF Capacitor Ceramic COG 0402 596 25 V GRM1555C1H220JZ01 Murata C5 10 nF Capacitor Ceramic X7R 0402 1096 16 V GRM155R71C103KA01 Murata C6 470 nF Capacitor Ceramic X7R 0603 1096 25 V GRM188R71E474KA12 Murata C7 22 yF Capacitor Ceramic X5R 1210 1096 25 V GRM32ER61E226KE15 Murata C8 330 pF Capacitor Tantalu
234. ime period and then disable it for a time period enough long to properly mitigate temperature increase UBX 13000995 R10 Early Production Information Design in Page 146 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual 2 13 ESD guidelines The sections 2 13 1 and 2 13 2 are related to EMC ESD immunity herein described in section 2 13 1 The modules are ESD sensitive devices and the ESD sensitivity for each pin as Human Body Model according to JESD22 A114F is specified in SARA G3 series Data Sheet 1 or SARA U2 series Data Sheet 2 requiring special precautions when handling for ESD handling guidelines see section 3 2 2 13 1 ESD immunity test overview The immunity of devices integrating SARA G3 and SARA U2 series modules to Electro Static Discharge ESD is part of the Electro Magnetic Compatibility EMC conformity which is required for products bearing the CE marking compliant with the R amp TTE Directive 99 5 EC the EMC Directive 89 336 EEC and the Low Voltage Directive 73 23 EEC issued by the Commission of the European Community Compliance with these directives implies conformity to the following European Norms for device ESD immunity ESD testing standard CENELEC EN 61000 4 2 18 and the radio equipment standards ETSI EN 301 489 1 19 ETSI EN 301 489 7 20 ETSI EN 301 489 24 21 which requirements are summarized in Table 56 The ESD immunity test is performed at the enclosure port defined by
235. importance in the application design starting from the highest relevance 1 Module antenna connection ANT and ANT DET pins Antenna circuit directly affects the RF compliance of the device integrating a SARA G3 and SARA U2 series module with the applicable certification schemes Very carefully follow the suggestions provided in section 2 4 for schematic and layout design 2 Module supply VCC and GND pins The supply circuit affects the RF compliance of the device integrating a SARA G3 and SARA U2 series module with applicable certification schemes as well as antenna circuit design Very carefully follow the suggestions provided in section 2 2 1 for schematic and layout design 3 USB interface USB D USB D and VUSB DET pins Accurate design is required to guarantee USB 2 0 high speed interface functionality Carefully follow the suggestions provided in the related section 2 6 1 for schematic and layout design 4 SIM interface VSIM SIM CLK SIM IO SIM RST SIM DET pins Accurate design is required to guarantee SIM card functionality and compliance with applicable conformance standards reducing also the risk of RF coupling Carefully follow the suggestions provided in section 2 5 for schematic and layout design 5 System functions RESET N PWR ON pins Accurate design is required to guarantee that the voltage level is well defined during operation Carefully follow the suggestions provided in section 2 3 for schematic and layout design
236. including all SARA G3 and SARA U2 series modules see Figure 95 Design in Page 155 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 2 16 Design in checklist This section provides a design in checklist 2 16 1 Schematic checklist The following are the most important points for a simple schematic check NANNNANAAAN KN AA S NANQNANANA KARKR RI S DC supply must provide a nominal voltage at VCC pin above the minimum operating range limit DC supply must be capable of providing 1 9 A current pulses providing a voltage at VCC pin above the minimum operating range limit and with a maximum 400 mV voltage drop from the nominal value VCC supply should be clean with very low ripple noise provide the suggested bypass capacitors in particular if the application device integrates an internal antenna VCC voltage must ramp from 2 5 V to 3 2 V within 4 ms to allow a proper switch on of the module Do not leave PWR ON floating fix properly the level e g adding a proper pull up resistor to V BCKP Do not apply loads which might exceed the limit for maximum available current from V INT supply Check that voltage level of any connected pin does not exceed the relative operating range Capacitance and series resistance must be limited on each SIM signal to match the SIM specifications Insert the suggested capacitors on each SIM signal and low capacitance ESD protections if accessible Check UART signals
237. ing the maximum soldering temperature and the maximum liquidus time limit in the recommended soldering profile may permanently damage the module Peak Temp 245 C Liquidus Temperature Typical Leadfree Soldering Profile Elapsed time s Figure 88 Recommended soldering profile e SARA G3 and SARA U2 series modules must not be soldered with a damp heat process 3 3 3 Optical inspection After soldering the SARA G3 and SARA U2 series modules inspect the modules optically to verify that the module is properly aligned and centered 3 3 4 Cleaning Cleaning the soldered modules is not recommended Residues underneath the modules cannot be easily removed with a washing process e Cleaning with water will lead to capillary effects where water is absorbed in the gap between the baseboard and the module The combination of residues of soldering flux and encapsulated water leads to short circuits or resistor like interconnections between neighboring pads Water will also damage the sticker and the ink jet printed text e Cleaning with alcohol or other organic solvents can result in soldering flux residues flooding into the two housings areas that are not accessible for post wash inspections The solvent will also damage the sticker and the ink jet printed text e Ultrasonic cleaning will permanently damage the module in particular the quartz oscillators For best results use a no clean soldering paste and eliminate th
238. ingle serial port from any host processor 1 13 12 Hybrid positioning and CellLocate Se Not supported by SARA G300 and SARA G310 versions Although GNSS is a widespread technology reliance on the visibility of extremely weak GNSS satellite signals means that positioning is not always possible particularly in shielded environments such as indoors and enclosed park houses or when a GNSS jamming signal is present The situation can be improved by augmenting GNSS receiver data with network cell information to provide a level of redundancy that can benefit numerous applications Positioning through cellular information CellLocate u blox CellLocate enables the device position estimation based on the parameters of the mobile network cells visible to the specific device To estimate its position the module sends the CellLocate server the parameters of network cells visible to it using a UDP connection In return the server provides the estimated position based on the CellLocate database SARA G340 SARA G350 and SARA U2 modules can either send the parameters of the visible home network cells only normal scan or the parameters of all surrounding cells of all mobile operators deep scan The CellLocate database is compiled from the position of devices which observed in the past a specific cell or set of cells historical observations as follows UBX 13000995 R10 Early Production Information System description Page 75 of 192 Qo
239. ion between module and GNSS GPIOs etc and to perform RF performance tests 5 2 1 Go No go tests for integrated devices A Go No go test is to compare the signal quality with a Golden Device in a position with excellent network coverage and after having dialed a call see u blox AT Commands Manual 3 AT CSQ command rssi ber parameters ee These kinds of test may be useful as a go no go test but not for RF performance measurements This test is suitable to check the communication with host controller and SIM card the audio and power supply functionality and verify if components at antenna interface are well soldered 5 2 2 Functional tests providing RF operation Overall RF performance test of the device including antenna can be performed with basic instruments such as a spectrum analyzer or an RF power meter and a signal generator using AT UTEST command over AT interface The AT UTEST command gives a simple interface to set the module to Rx and Tx test modes ignoring 2G 3G signaling protocol The command can set the module In transmitting mode in a specified channel and power level in all the supported modulation schemes single slot GMSK single slot 8PSK WCDMA and bands 2G 3G In receiving mode in a specified channel to returns the measured power level in all 2G 3G supported bands Se See the u blox AT Commands Manual 3 for AT UTEST command syntax description ee See the End user test Application Note 26
240. ion protocol is based on the SIM Access Profile Interoperability Specification 28 ee SARA U2 modules do not support SAP server role the module acts as SAP client only A typical application using the SAP feature is the scenario where a device such as an embedded car phone with an integrated SARA U2 module uses a remote SIM included in an external user device e g a simple SIM card reader or a portable phone which is brought into the car The car phone accesses the GSM UMTS network using the remote SIM in the external device UBX 13000995 R10 Early Production Information System description Page 79 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual SARA U2 modules acting as an SAP client can be connected to an SAP server by a completely wired connection as shown in Figure 33 Device including SIM Device including SARA U2 Mobile SARA U2 Equipment SAP SAP Y GSM UMTS Serial Interf icati i eria interrace Application Serial Interface Interface Processor SAP channel over USB or UART Remote SIM Local SIM optional Figure 33 Remote SIM access via completely wired connection As stated in the SIM Access Profile Interoperability Specification 28 the SAP client can be connected to the SAP server by means of a Bluetooth wireless link using additional Bluetooth transceivers In this case the application processor wired to SARA U2 modules est
241. ironments by qualified user and must not be used during the normal module operation Follow instructions suggested in u blox documentation u blox assumes no responsibilities for the inappropriate use of this feature UBX 13000995 R10 Early Production Information Product testing Page 170 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Example of production tests for OEM manufacturer 1 Trigger TX GMSK burst at low Power Control Level lower than 15 or a RX measure reporting to check o If ANT pin is soldered o If ANT pin is in short circuit o If the module was damaged during soldering process or during handling ESD mechanical shock o lf antenna matching components on application board are soldered o If integrated antenna is correctly connected A To avoid module damage during transmitter test when good antenna termination is not guaranteed use a low Power Control Level i e PCL lower or equal to 15 u blox assumes no responsibilities for module damaging caused by an inappropriate use of this feature 2 Trigger TX GMSK burst at maximum PCL o Tocheck if the power supply is correctly assembled and is able to deliver the required current 3 Trigger TX GMSK burst TX 8PSK burst and TX WCDMA signal o To measure current consumption o To check if module components were damaged during soldering process or during handling ESD mechanical shock 4 Trigger RX measurement o To test receiver signal leve
242. l Figure 61 describes the circuit that should be implemented as if a 1 8 V application processor is used given that the DTE will behave properly regardless DSR input setting Application Processor SARA G3 SARA U2 1 8V DTE 1 8V DCE Figure 61 UART interface application circuit with partial V 24 link 6 wire in the DTE DCE serial communication 1 8 V DTE If a 3 0 V application processor is used appropriate unidirectional voltage translators must be provided using the module V INT output pin as 1 8 V supply as described in Figure 62 given that the DTE will behave properly regardless DSR input setting Application Processor SARA G3 SARA U2 3 0V DTE Unidirectional 1 8V DCE 2D Voltage Translator vcc VCCA VCCB EN VNT e DIRI mus vi DIR3 z TxD 3 i B1 TXD RxD 2 B2 RXD RTS A3 B3 RTS CTS 4 4 4 B4 CTS DIR2 OE DIR4 GND Ul Unidirectional 3V0 Voltage Translator tat VCCA VCCB C3 s DIR1 DIR2 DTR c a B1 DTR DSR A2 B2 DSR RI m RI DCD p DCD U2 GND GND Figure 62 UART interface application circuit with partial V 24 link 6 wire in DTE DCE serial communication 3 0 V DTE Reference Description Part Number Manufacturer C1 C2 C3 C4 100 nF Capacitor Ceramic X7R 0402 10 16 V GRM155R61A104KA01 Murata U1 Unidirectional Voltage Translato
243. l 1 2 Architecture Figure 1 summarizes the architecture of SARA G300 and SARA G310 modules while Figure 2 summarizes the architecture of SARA G340 and SARA G350 modules describing the internal blocks of the modules consisting of the RF Baseband and Power Management main sections and the available interfaces 32 kHz WANHERIESEESERENAIET SEIEN RETE EE 32 kHz Power On eset lt M gt ANT Filter i Transceiver a UART a P Auxiliary UART 1 Cellular BaseBand Processor VCC Supply V_BCKP RTC i Power i Management V INT VO mho A Power On ANT Reset SIM Card Detection q UAI _Auniliary UART Cellular DDC for GNSS gt BaseBand Analog Audio Processor d Digital Audio PEN VCC Supply V BCKP RTO Power 4 i i Management V INT I O Antenna Detection Figure 2 SARA G340 and SARA G350 modules block diagram UBX 13000995 R10 Early Production Information System description Page 10 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual Figure 3 summarizes the architecture of SARA U260 and SARA U270 modules while Figure 4 summarizes the architecture of SARA U280 and SARA U290 modules describing the internal blocks of the modules consisting of the RF Baseband and Power Management main sections and the available interfaces 26 MHz 32 768 kHz Power On
244. l Assuming that there are no losses between ANT pin and input power source be aware that the power level estimated by the module can vary approximately within 3GPP tolerances for the average value o To check if module was damaged during soldering process or during handling ESD mechanical shock 5 Trigger TX GMSK TX 8PSK burst and TX WCDMA signal and RX measurement to check o Overall RF performance of the device including antenna measuring TX and RX power levels UBX 13000995 R10 Early Production Information Product testing Page 171 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Appendix A Migration between LISA and SARA G3 modules A 1 Overview Migrating between LISA U1 LISA U2 LISA C2 series and SARA G3 series module designs is a straight forward procedure that allows customers to take maximum advantage of their hardware and software investments The SARA cellular modules 26 0 x 16 0 mm LGA have a different form factor than the LISA cellular modules 33 2 x 22 4 mm LCC but the footprint of SARA and LISA modules has been developed to provide pin to pin compatibility on the lateral edge of the antenna pin so that each SARA LISA pin can share the same pad on the application board due to the same pitch and nearly the same functions provided as described in Figure 91
245. l 10 kQ pull up resistor to V INT is provided See section 1 6 3 for functional description See section 2 3 2 for external circuit design in Input for RTC reference clock needed to enter the low power idle mode and provide RTC functions See section 1 6 4 for functional description See section 2 3 3 for external circuit design in 32 kHz output suitable only to feed the EXT32K input giving the RTC reference clock allowing low power idle mode and RTC functions support See section 1 6 5 for functional description See section 2 3 3 for external circuit design in 50 O nominal characteristic impedance Antenna circuit affects the RF performance and compliance of the device integrating the module with applicable required certification schemes See section 1 7 for functional description and requirements for the antenna RF interface See section 2 4 for external circuit design in ADC input for antenna detection function See section 1 7 2 for functional description See section 2 4 2 for external circuit design in System description Page 13 of 192 biox Pin Name Function SIM VSIM SIM_IO SIM_CLK SIM_RST SIM_DET UART RXD TXD CTS RTS DSR RI DTR DCD UBX 13000995 R10 Module All All All All All All All Pin No 41 39 38 40 42 1 0 VO VO SARA G3 and SARA U2 series System Integration Manual Description SIM supply ou
246. le the VUSB_DET input pin senses the VBUS USB supply presence nominally 5 V at the source to detect the host connection and enable the interface The USB interface of the module is enabled only if a valid voltage is detected by the VUSB DET input see the SARA U2 series Data Sheet 2 Neither the USB interface nor the whole module is supplied by the VUSB DET input the VUSB DET senses the USB supply voltage and absorbs few microamperes UBX 13000995 R10 Early Production Information System description Page 52 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual SARA U2 modules provide by default the following USB profile with the listed set of available USB functions USB CDCs Communications Device Classes USB1 AT and Data AT command interface and packet switched circuit switched data communication USB2 AT and Data AT command interface and packet switched circuit switched data communication USB3 AT and Data AT command interface and packet switched circuit switched data communication USB4 GPS tunneling communication with the u blox GNSS receiver connected over I C interface USB5 Primary Log diagnostic purpose USB6 Secondary Log diagnostic purpose USB7 SAP SIM Access Profile The user can concurrently use the AT command interface on one CDC and packet switched circuit switched data communication on another CDC The module firmware can be upgraded over the USB interface using the u blox E
247. lementation of the appratus integrating SARA G350 ATEX modules intended for use in potentially explosive atmospheres must be fulfilled according to the exact applicable standards check the detailed requisites on the pertinent normatives for the application as for example the IEC 60079 0 32 IEC 60079 11 33 IEC 60079 26 34 standards e The certification of the application device that integrates a SARA G350 ATEX module and the compliance of the application device with all the applicable certification schemes directives and standards required for use in potentially explosive atmospheres are the sole responsibility of the application device manufacturer The application device integrating a SARA G350 ATEX module for use in potentially explosive atmospheres must be designed so that any circuit part of the apparatus shall not invalidate the specific characteristics of the type of protection of the SARA G350 ATEX module electrical equipment The intrinsic safety i type of protection of SARA G350 ATEX modules is based on the restriction of electrical energy within equipment and of interconnecting wiring exposed to the explosive atmosphere to a level below that which can cause ignition by either sparking or heating effects UBX 13000995 R10 Early Production Information Design in Page 150 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual The following input and equivalent parameters must be considered integrating a SAR
248. lication PCB close to the pad designed for the ANT pin On a multi layer board the whole layer stack below the RF connection should be free of digital lines Increase GND keep out i e clearance a void area around the ANT pad on the top layer of the application PCB to at least 250 um up to adjacent pads metal definition and up to 400 um on the area below the module to reduce parasitic capacitance to ground as described in the left picture in Figure 49 Add GND keep out i e clearance a void area on the buried metal layer below the ANT pad if the top layer to buried layer dielectric thickness is below 200 um to reduce parasitic capacitance to ground as described in the right picture in Figure 49 GND clearance GND clearance on top layer on very close buried layer around ANT pad below ANT pad NEN EN E ec MEM in ee e mU 7 in m ANT Min 400 p Figure 49 GND keep out area on the top layer around ANT pad and on the very close buried layer below ANT pad Guidelines for RF transmission line design The transmission line from the ANT pad up to antenna connector or up to the internal antenna pad must be designed so that the characteristic impedance is as close as possible to 50 Q The transmission line can be designed as a micro strip consists of a conducting strip separated from a ground plane by a dielectric material or a strip line consists of a flat strip of metal which is sandwiched between two parallel ground planes withi
249. lication board Any external signal connected to any generic digital interface pin must be tri stated or set low when the module is in power down mode and during the module power on sequence at least until the activation of the V INT output of the module to avoid latch up of circuits and let a proper boot of the module All unused pins can be left unconnected except the PWR ON pin its level must be properly fixed e g adding a 100 kQ pull up to V BCKP and the RSVD pin number 33 it must be connected to GND UBX 13000995 R10 Early Production Information Design in Page 156 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 2 16 2 Layout checklist The following are the most important points for a simple layout check v Check 50 Q nominal characteristic impedance of the RF transmission line connected to the ANT pad antenna RF input output interface Follow the recommendations of the antenna producer for correct antenna installation and deployment PCB layout and matching circuitry Ensure no coupling occurs between the RF interface and noisy or sensitive signals primarily analog audio input output signals SIM signals high speed digital lines VCC line should be wide and short Route VCC supply line away from sensitive analog signals Ensure proper grounding Optimize placement for minimum length of RF line and closer path from DC source for VCC Design USB D USB D connection as 90 Q different
250. lock and backup RAM when the VCC supply of the cellular module is within its operating range and the VCC supply of the GNSS receiver is disabled This enables the u blox positioning receiver to recover from a power breakdown with either a hot start or a warm start depending on the duration of the GNSS receiver VCC outage and to maintain the configuration settings saved in the backup RAM UBX 13000995 R10 Early Production Information System description Page 55 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 10 Audio interface es SARA G300 and SARA G310 modules do not support audio interface The following audio interfaces are provided by SARA G3 and SARA U2 series modules SARA G340 and SARA G350 modules provide one analog audio interface and one digital audio interface SARA U2 modules provide one digital audio interface The audio interfaces can be selected and set by the dedicated AT command USPM refer to the u blox AT Commands Manual 3 this command allows setting the audio path mode composed by the uplink audio path and the downlink audio path Each uplink path mode defines the physical input i e the analog or the digital audio input and the set of parameters to process the uplink audio signal uplink gains uplink digital filters echo canceller parameters For example the Headset microphone uplink path uses the differential analog audio input with the default parameters for the headset profile
251. logic mode IF emerg call in progress Wait emergency call termination Send shutdown notification Shut the device down Figure 31 Smart Temperature Supervisor STS flow diagram UBX 13000995 R10 Early Production Information System description Page 73 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Threshold definitions When the module application operates at extreme temperatures with Smart Temperature Supervisor enabled the user should note that outside the valid temperature range the device automatically shuts down as described above The input for the algorithm is always the temperature measured within the cellular module Ti internal This value can be higher than the working ambient temperature Ta ambient since for example during transmission at maximum power a significant fraction of DC input power is dissipated as heat This behavior is partially compensated by the definition of the upper shutdown threshold t that is slightly higher than the declared environmental temperature limit Table 19 defines the temperature thresholds for SARA G340 and SARA G350 modules Symbol Parameter Temperature Remarks Equal to the absolute minimum temperature rating for the cellular t Low temperature snutdown ee module the lower limit of the extended temperature range t Low temperature warning 30 C 10 C above t 10 C below t The higher warning area for u
252. lt main_downlink gt parameters Hands free functionality is implemented using appropriate digital signal processing algorithms for voice band handling echo canceller and automatic gain control managed via software refer to u blox AT commands manual 3 AT UHFP command UBX 13000995 R10 Early Production Information System description Page 57 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 10 2 Digital audio interface SARA G340 SARA G350 and SARA U2 modules provide one 1 8 V bidirectional 4 wire IBS TXD data output I2S RXD data input 12S_CLK clock 128_WA world alignment lS digital audio interface that can be used for digital audio communication with external digital audio devices as an audio codec The l S interface can be set to two modes by the I2S mode parameter of the AT UI2S command PCM mode Normal l S mode The I S interface can be set to two configurations by the I2S Master Slave parameter of AT UI2S Master mode Slave mode Se SARA G340 and SARA G350 modules do not support l S slave mode module acts as master only The sample rate of transmitted received words can be set by the I2S sample rate parameter of AT UI2S to 8 kHz 11 025 kHz 12 kHz 16 kHz 22 05 kHz 24 kHz 32 kHz 44 1 kHz 48 kHz ee SARA G340 and SARA G350 modules do not support the lt I2S_sample_rate gt parameter of AT UI2S the sample rate is fixed at 8 kHz only The lt main_uplink gt and lt main_
253. ly loads which might exceed the limit for maximum available current from V_BCKP supply as this can cause malfunctions in the module SARA G3 series Data Sheet 1 and SARA U2 series Data Sheet 2 describe the detailed electrical characteristics V_BCKP supply output pin provides internal short circuit protection to limit start up current and protect the device in short circuit situations No additional external short circuit protection is required ee ESD sensitivity rating of the V_BCKP supply pin is 1 kV Human Body Model according to JESD22 A114 Higher protection level can be required if the line is externally accessible on the application board e g if an accessible back up battery connector is directly connected to V_BCKP pin and it can be achieved by mounting an ESD protection e g EPCOS CAO5PAS14THSG varistor array close to the accessible point 2 2 2 2 Guidelines for V_BCKP layout design RTC supply V_BCKP requires careful layout avoid injecting noise on this voltage domain as it may affect the stability of the 32 kHz oscillator UBX 13000995 R10 Early Production Information Design in Page 96 of 192 biox 2 2 3 Interface supply V INT 2 2 3 4 Guidelines for V INT circuit design The V INT digital interfaces 1 8 V supply output can be mainly used to ee Pull up DDC lC interface signals see section 2 6 4 for more details Pull up SIM detection signal see section 2 5 for more details Supply voltage translator
254. ly connected to the V BCKP backup supply input pin of the GNSS receiver as in the application circuit for a u blox 1 8 V GNSS receiver u blox GNSS 3 0 V receiver V BCKP 4 WEM v BCKP GNSSLDO Regulator vcc a a a OUT IN aa GNSS supply enabled ee SHDN jg py Ene EW GPIO2 SARA U2 series 3vo VMAIN ui Bi I2C bus Bidirectional Voltage Translator VCCB VCCA V INT OE SDA2 SDA B SDA A SDA SCL2 SCL_B SCLA SCL GND U2 Unidirectional 3v0 Voltage Translator 1v8 VCCA VCCB T Teas Tcs DIRI TxD1 Ai B1 GNSS data read GPIO3 EXTINTO 4 22 82 GNSS RIC sharin GPIO4 DIR2 GND OE Figure 75 Application circuit for connecting SARA U2 modules to u blox 3 0 V GNSS receivers Reference Description Part Number Manufacturer R1 R2 R4 R5 4 7 kQ Resistor 0402 5 0 1 W RC0402JR 074K7L Yageo Phycomp R3 47 KQ Resistor 0402 5 0 1 W RC0402JR 0747KL Yageo Phycomp C2 C3 C4 C5 100 nF Capacitor Ceramic X5R 0402 10 10V GRM155R71C104KA01 Murata U1 C1 Voltage Regulator for GNSS receiver and related See GNSS receiver Hardware Integration Manual output bypass capacitor U2 I2C bus Bidirectional Voltage Translator TCA9406DCUR Texas Instruments U3 Generic Unidirectional Voltage Translator SN74AVC2
255. m D SIZE 6 3 V 45 mQ T520D337MO006ATEO045 KEMET D1 Schottky Diode 40V 3A MBRA340T3G ON Semiconductor L1 10 pH Inductor 744066100 3096 3 6 A 744066100 Wurth Electronics R1 470 kQ Resistor 0402 5 0 1 W 2322 705 87474 L Yageo R2 15 kQ Resistor 0402 596 0 1 W 2322 705 87153 L Yageo R3 22 kQ Resistor 0402 596 0 1 W 2322 705 87223 L Yageo RA 390 kQ Resistor 0402 1 0 063 W RCO402FR 07390KL Yageo R5 100 kQ Resistor 0402 5 0 1 W 2322 705 70104 L Yageo U1 Step Down Regulator MSOP10 3 5 A 2 4 MHz LT3972IMSE PBF Linear Technology Table 21 Suggested components for the VCC voltage supply application circuit using a step down regulator UBX 13000995 R10 Early Production Information Design in Page 85 of 192 SARA G3 and SARA U2 series System Integration Manual biox Figure 37 and the components listed in Table 22 show an example of a low cost power supply circuit where the VCC module supply is provided by a step down switching regulator capable of delivering to VCC pins the specified maximum peak pulse current transforming a 12 V supply input 12V l SARA G3 SARA U2 8 VCC VCC 3 NH out H mm ee eo VCC K pi T vcc s R1 6 U1 B9 T Ci C6 FSW FB m e dies 21 SYNC comp H4 GND La R2 P C5 E GND Figure 37 Suggested low cost solution for the VCC voltage supply application cir
256. m Integration Manual The conformity assessment procedure for SARA G350 ATEX modules referred to in Article 10 and detailed in Annex IV of Directive 1999 5 EC has been followed with the involvement of the following Notified Body number 1304 Thus the following marking is included in the product C 1304 The conformity assessment procedure for SARA U270 and SARA U290 modules referred to in Article 10 and detailed in Annex IV of Directive 1999 5 EC has been followed with the involvement of the following Notified Body number 1588 Thus the following marking is included in the product C 1588 There is no restriction for the commercialization of the SARA G3 series SARA U270 and SARA U290 modules in all the countries of the European Union 4 4 Anatel certification SARA G310 and SARA G350 modules are certified by the Brazilian Agency of Telecommunications Ag ncia Nacional de Telecomunica es in Portuguese Anatel oD anarer oDanarer Ag ncia Nacional de Telecomunica es Ag ncia Nacional de Telecomunica es 3419 13 5903 3420 13 5903 01 0 789 8941 57509 0 01 0 789 8941 575106 Anatel IDs for the SARA G310 modules EAN barcode 01 0 789 8941 57509 0 Homologation number 3419 13 5903 Anatel IDs for the SARA G350 modules EAN barcode 01 0 789 8941 57510 6 Homologation number 3420 13 5903 UBX 13000995 R10 Early Production Information Approvals Page 166 of 192 Qo ox SARA G3 and SARA
257. mation Design in Page 98 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual 2 3 1 2 Guidelines for PWR ON layout design The power on circuit PWR_ON requires careful layout since it is the sensitive input available to switch on the SARA G3 and SARA U2 series modules until a valid VCC supply is provided after that the module has been switched off by the AT CPWROFF command ensure that the voltage level is well defined during operation and no transient noise is coupled on this line otherwise the module might detect a spurious power on request 2 3 2 Module reset RESET N 2 3 2 1 Guidelines for RESET N circuit design As described in Figure 21 the module has an internal pull up resistor on the reset input line an external pull up is not required on the application board Connecting the RESET N input to a push button that shorts the RESET N pin to ground the pin will be externally accessible on the application device according to EMC ESD requirements of the application provide an additional ESD protection e g EPCOS CAO5P4S14THSG varistor array on the line connected to this pin close to accessible point as described in Figure 46 and Table 30 er ESD sensitivity rating of the RESET_N pin is 1 kV Human Body Model according to JESD22 A114 Higher protection level can be required if the line is externally accessible on the application board e g if an accessible push button is directly connected to RESET_N pin Highe
258. mendations described in section 2 2 1 4 The MP2617 IC constantly monitors the battery voltage and selects whether to use the external main primary supply charging source or the battery as supply source for the module and starts a charging phase accordingly The MP2617 IC normally provides a supply voltage to the module regulated from the external main primary source allowing immediate system operation even under missing or deeply discharged battery the integrated switching step down regulator is capable to provide up to 3 A output current with low output ripple and fixed 1 6 MHz switching frequency in PWM mode operation The module load is satisfied in priority then the integrated switching charger will take the remaining current to charge the battery Additionally the power path control allows an internal connection from battery to the module with a low series internal ON resistance 40 mQ typical in order to supplement additional power to the module when the current demand increases over the external main primary source or when this external source is removed Battery charging is managed in three phases Pre charge constant current active when the battery is deeply discharged the battery is charged with a low current set to 10 of the fast charge current Fast charge constant current the battery is charged with the maximum current configured by the value of an external resistor to a value suitable for the application Constant volt
259. ment and services Part 24 Specific conditions for IMT 2000 CDMA Direct Spread UTRA for Mobile and portable UE radio and ancillary equipment 3GPP TS 26 267 V10 0 0 eCall Data Transfer In band modem solution General description Rel 10 u blox Multiplexer Implementation Application Note Docu No UBX 13001887 u blox GNSS Implementation Application Note Docu No UBX 13001849 u blox Firmware Update Application Note Docu No UBX 13001845 u blox End user test Application Note Docu No WLS CS 12002 u blox Package Information Guide Docu No UBX 14001652 SIM Access Profile Interoperability Specification Revision V11r00 http www bluetooth org u blox eCall ERA GLONASS Application Note Docu No UBX 13001924 BS EN 16062 2011 Intelligent transport systems eSafety eCall high level application requirements ETSI TS 122 101 V8 7 0 Service aspects Service principles 3GPP TS 22 101 v 8 7 0 Rel 8 IEC 60079 0 Explosive atmospheres Part 0 Equipment general requirements 2011 06 IEC 60079 11 Explosive atmospheres Part 11 Equipment protection by intrinsic safety i 2011 06 IEC 60079 26 Explosive atmospheres Part 26 Equipment with EPL Ga 2006 08 Some of the above documents can be downloaded from u blox web site http Avww u blox com UBX 13000995 R10 Early Production Information Related documents Page 190 of 192 biox Revision history Date Revision 1 A1 RO6 RO7 ROS RO9 R10
260. mer battery charging and power path management application circuit UBX 13000995 R10 Early Production Information Design in Page 93 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 2 2 1 9 Guidelines for VCC supply layout design Good connection of the module VCC pins with DC supply source is required for correct RF performance Guidelines are summarized in the following list All the available VCC pins must be connected to the DC source VCC connection must be as wide as possible and as short as possible Any series component with Equivalent Series Resistance ESR greater than few milliohms must be avoided VCC connection must be routed through a PCB area separated from sensitive analog signals and sensitive functional units it is good practice to interpose at least one layer of PCB ground between VCC track and other signal routing Coupling between VCC and audio lines especially microphone inputs must be avoided because the typical GSM burst has a periodic nature of approx 217 Hz which lies in the audible audio range The tank bypass capacitor with low ESR for current spikes smoothing described in Figure 40 and Table 25 should be placed close to the VCC pins If the main DC source is a switching DC DC converter place the large capacitor close to the DC DC output and minimize the VCC track length Otherwise consider using separate capacitors for DC DC converter and cellular module tank capacitor The bypass c
261. min 50 us min 80 us max OFF L level pulse time OFF L level pulse time OFF L level pulse time OFF L level pulse time Not Available Not Available Not Available 1smin RESET N 18 Internal diode amp pull up 22 550 Q internal pull up 10 kQ internal pull up 10 kQ internal pull up L level 0 30 V 0 30 V L level 0 30 V 0 63 V L level 0 30 V 0 65 V L level 0 30 V 0 51 V H level 2 00 V 4 70 V H level 1 32V 2 10V H4devel 1 69 V 2 48 V HHevel 1 32 V 2 01 V Reset L level pulse time Reset L level pulse time Reset L level pulse time Reset L level pulse time SARA G340 SARA G350 300 ms min 50 ms min 50 ms min 50 ms min SARA G300 SARA G310 3smin EXT32K 31 SARA G300 SARA G310 Not Available Not Available Not Available 32 kHz input for RTC Internal reference for Internal 32 kHz for RTC Internal 32 kHz for RTC amp low power idle mode low power idle mode amp low power idle mode amp low power idle mode SARA G340 SARA G350 Not Available Internal 32 kHz for RTC amp low power idle mode 32K OUT 24 SARA G300 SARA G310 Not Available Not Available Not Available 32 kHz output only to feed the EXT32K input SARA G340 SARA G350 Not Available UBX 13000995 R10 Early Production Information Appendix Page 179 of 192 biox Pin Name N SARA G3 series SIM SIM_CLK 38 8V 3V SIM clock SIM IO 39 8V 3V SIM data Internal 4 7k pull up SIM RST 40 8V 3V SIM reset VSIM 4
262. mmunity test is needed UBX 13000995 R10 Early Production Information Design in Page 111 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 2 5 SIM interface 2 5 1 1 Guidelines for SIM circuit design Guidelines for SIM cards SIM connectors and SIM chips selection The ISO IEC 7816 the ETSI TS 102 221 and the ETSI TS 102 671 specifications define the physical electrical and functional characteristics of Universal Integrated Circuit Cards UICC which contains the Subscriber Identification Module SIM integrated circuit that securely stores all the information needed to identify and authenticate subscribers over the cellular network Removable UICC SIM card contacts mapping is defined by ISO IEC 7816 and ETSI TS 102 221as follows Contact C1 2 VCC Supply gt It must be connected to VSIM Contact C2 RST Reset It must be connected to SIM_RST Contact C3 CLK Clock It must be connected to SIM_CLK Contact C4 AUX1 Auxiliary contact It must be left not connected Contact C5 GND Ground It must be connected to GND Contact C6 VPP Programming supply It must be connected to VSIM Contact C7 I O Data input output It must be connected to SIM_IO Contact C8 AUX2 Auxiliary contact gt It must be left not connected A removable SIM card can have 6 contacts C1 VCC C2 RST C3 CLK C5 GND C6 VPP C7 I O or 8 contacts providing also the auxiliary contacts C4 AUX1 and C8 AUX2 for USB inte
263. module is in idle mode Se In command mode if autobauding is disabled the DTE must always send a dummy AT before each command line the first character is not ignored if the module is in active mode i e the module replies OK or it represents the wake up character if the module is in low power idle mode i e the module does not reply Se No wake up character or dummy AT is required from the DTE during a voice or data call since the module UART interface continues to be enabled and does not need to be woken up Furthermore in data mode a dummy AT would affect the data communication Additional considerations for SARA U2 modules SARA U2 modules are forced to stay in active mode if the USB is connected and not suspended and therefore the AT UPSV 1 AT UPSV 2 or AT UPSV 3 settings are overruled but they have effect on the UART behavior they configure UART interface power saving so that UART is enabled disabled according to the AT UPSV 1 AT UPSV 2 or AT UPSV 3 settings To set the AT UPSV 1 AT UPSV 2 or AT UPSV 3 configuration over the USB interface of SARA U2 modules the autobauding must be previously disabled on the UART by the IPR AT command over the used AT interface the USB and this IPR AT command configuration must be saved in the module non volatile memory see u blox AT Commands Manual 3 Then after the subsequent module re boot AT UPSV 1 AT UPSV 2 or AT UPSV 3 can be issued over the used AT interfac
264. n 1 8 V input Circuit 103 TXD in ITU T V 24 for AT data FOAT on SARA G3 series modules for AT data FOAT FW upgrade via EasyFlash tool and diagnostic on SARA U2 series modules Internal active pull up to V INT See section 1 9 1 for functional description See section 2 6 1 for external circuit design in 1 8 V output Circuit 106 CTS in ITU T V 24 See section 1 9 1 for functional description See section 2 6 1 for external circuit design in 1 8 V input Circuit 105 RTS in ITU T V 24 Internal active pull up to V INT See section 1 9 1 for functional description See section 2 6 1 for external circuit design in 8 V output Circuit 107 DSR in ITU T V 24 See section 1 9 1 for functional description See section 2 6 1 for external circuit design in 8 V output Circuit 125 RI in ITU T V 24 See section 1 9 1 for functional description See section 2 6 1 for external circuit design in 8 V input Circuit 108 2 DTR in ITU T V 24 Internal active pull up to V INT See section 1 9 1 for functional description See section 2 6 1 for external circuit design in 1 8 V input Circuit 109 DCD in ITU T V 24 See section 1 9 1 for functional description See section 2 6 1 for external circuit design in System description Page 14 of 192 biox Function Pin Name Auxiliary RKXD AUX UART TXD AUX USB VUSB DET USB D USB_D DDC SCL SDA UBX 13000995 R1
265. n a dielectric material The micro strip implemented as a coplanar waveguide is the most common configuration for printed circuit board UBX 13000995 R10 Early Production Information Design in Page 103 of 192 Qo OX SARA G3 and SARA U2 series System Integration Manual Figure 50 and Figure 51 provide two examples of proper 50 Q coplanar waveguide designs The first transmission line can be implemented in case of 4 layer PCB stack up herein described the second transmission line can be implemented in case of 2 layer PCB stack up herein described 500um 380um 500um E L1 Copper 35 um FR 4 dielectric 270 um L2 Copper 35um FR 4 dielectric 760 um L3 Copper 35um FR 4 dielectric 270 um L4 Copper 35 um Figure 50 Example of 50 Q coplanar waveguide transmission line design for the described 4 layer board layup 400um 1200um 400um Y L1 Copper 35 um FR 4 dielectric 1510 um L2 Copper 35 um Figure 51 Example of 50 coplanar waveguide transmission line design for the described 2 layer board layup If the two examples do not match the application PCB layup the 50 Q characteristic impedance calculation can be made using the HFSS commercial finite element method solver for electromagnetic structures from Ansys Corporation or using freeware tools like AppCAD from Agilent www agilent com or TXLine from Applied Wave Research www mwoffice com taking care of the approximation formulas used by the tools for the imp
266. n is by default configured to provide the GSM Tx burst indication function The pin configured to provide the GSM Tx burst indication function is set as o High since 10 us before the start of first Tx slot until 5 us after the end of last Tx slot o Low otherwise ee SARA U280 and SARA U290 modules do not support the GSM Tx burst indication function on GPIO1 as the modules do not support 2G radio access technology UBX 13000995 R10 Early Production Information System description Page 63 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual E GNSS supply enable The GPIO2 is by default configured by AT UGPIOC command to enable or disable the supply of the u blox GNSS receiver connected to the cellular module The GPIO1 GPIO3 GPIO4 pins and on SARA U2 series only also the SIM_DET pin can be configured to provide the GNSS supply enable function alternatively to the default GPIO2 pin setting the parameter lt gpio_mode gt of AT UGPIOC command to 3 The GNSS supply enable mode can be provided only on one pin per time it is not possible to simultaneously set the same mode on another pin The pin configured to provide the GNSS supply enable function is set as o High to switch on the u blox GNSS receiver if AT UGPS parameter mode is set to 1 o Low to switch off the u blox GNSS receiver if AT UGPS parameter mode is set to 0 default GNSS data ready Only the GPIO3 pin p
267. n the 2G and 3G operating bands 2 4 1 Antenna RF interface ANT 2 4 1 1 General guidelines for antenna selection and design The cellular antenna is the most critical component to be evaluated care must be taken about it at the start of the design development when the physical dimensions of the application board are under analysis decision since the RF compliance of the device integrating a SARA G3 and SARA U2 series module with all the applicable required certification schemes depends from antenna radiating performance Cellular antennas are typically available as External antenna e g linear monopole o External antenna usage basically does not imply physical restrictions on the design of the PCB where the SARA G3 and SARA U2 series module is mounted o The radiation performance mainly depends on the antenna select the antenna with optimal radiating performance in the operating bands o lf antenna detection functionality is required select an antenna assembly provided with a proper built in diagnostic circuit with a resistor connected to ground see guidelines in section 2 4 2 o Select an RF cable with minimum insertion loss additional insertion loss due to low quality or long cable reduces radiation performance o Select a suitable 50 Q connector providing proper PCB to RF cable transition it is recommended to strictly follow the layout and cable termination guidelines provided by the connector manufacturer Integrated ant
268. n the power saving configuration is enabled and the hardware flow control is not implemented in the DTE DCE connection data sent by the DTE can be lost the first character sent when the module is in the low power idle mode will not be a valid communication character see 1 9 1 4 for more details Refer to the pin description table in the SARA G3 series Data Sheet 1 and SARA U2 series Data Sheet 2 UBX 13000995 R10 Early Production Information System description Page 42 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual RTS signal behavior The hardware flow control input RTS line is set by default to the OFF state high level at UART initialization The module then holds the RTS line in the OFF state if the line is not activated by the DTE an active pull up is enabled inside the module on the RTS input If the HW flow control is enabled as it is by default the module monitors the RTS line to detect permission from the DTE to send data to the DTE itself If the RTS line is set to the OFF state any on going data transmission from the module is interrupted until the subsequent RTS line change to the ON state ee The DTE must still be able to accept a certain number of characters after the RTS line is set to the OFF state the module guarantees the transmission interruption within two characters from RTS state change Module behavior according to RTS hardware flow control status can be configured by AT commands
269. nal description ion 2 7 2 for external circuit design in 1 8 V word alignment for PCM normal IS modes Pin confi See sec See sec igurable also as GPIO on SARA U2 series ion 1 10 2 for functional description ion 2 7 2 for external circuit design in 1 8 V master clock output for external audio codec See sec See sec ion 1 10 2 for functional description ion 2 7 2 for external circuit design in System description Page 16 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Function Pin Name Module Pin No 1 0 Description Remarks GPIO GPIO1 SARA G340 16 1 0 GPIO 1 8 V GPIO by default configured as pin disabled SARA G350 See section 1 11 for functional description SARA U2 See section 2 8 for external circuit design in GPIO2 SARA G340 23 1 0 GPIO 1 8 V GPIO by default configured to provide the SARA G350 custom GNSS supply enable function SARA U2 See section 1 11 for functional description See section 2 8 for external circuit design in GPIO3 SARA G340 24 y o GPIO 1 8 V GPIO by default configured to provide the SARA G350 custom GNSS data ready function SARA U2 See section 1 11 for functional description See section 2 8 for external circuit design in GPIO4 SARA G340 25 y o GPIO 1 8 V GPIO by default configured to provide the SARA G350 custom GNSS RTC sharing function SARA U2 See section 1 11 for functional description See section 2 8 for external circuit design in Rese
270. nal quality problems e Route USB D USB D lines as a differential pair e Route USB D USB D lines as short as possible e Ensure the differential characteristic impedance Z is as close as possible to 90 Q e Ensure the common mode characteristic impedance Z is as close as possible to 30 Q e Consider design rules for USB D USB D similar to RF transmission lines being them coupled differential micro strip or buried stripline avoid any stubs abrupt change of layout and route on clear PCB area e Avoid coupling with any RF line or sensitive analog inputs since the signals can cause the radiation of some harmonics of the digital data frequency Figure 70 and Figure 71 provide two examples of coplanar waveguide designs with differential characteristic impedance close to 90 O and common mode characteristic impedance close to 30 Q The first transmission line can be implemented in case of 4 layer PCB stack up herein described the second transmission line can be implemented in case of 2 layer PCB stack up herein described 400um 350um 400um 350um 400 ym L1 Copper 35 um FR 4 dielectric 270 um L2 Copper 35 um FR 4 dielectric 760 um L3 Copper 35 um FR 4 dielectric 270 um L4 Copper 35 um Figure 70 Example of USB line design with Z close to 90 Q and Z close to 30 Q for the described 4 layer board layup 410um 740um 410ygm 740gm 410 pm L1 Copper 35 um FR 4 dielectric 1510 um L2 Copper 35 um Figure
271. ncluding interference that may cause undesired operation Radiofrequency radiation exposure Information this equipment complies with FCC radiation exposure limits prescribed for an uncontrolled environment for fixed and mobile use conditions This equipment should be installed and operated with a minimum distance of 20 cm between the radiator and the body of the user or nearby persons This transmitter must not be co located or operating in conjunction with any other antenna or transmitter except as authorized in the certification of the product The gain of the system antenna s used for SARA G310 SARA G350 modules i e the combined transmission line connector cable losses and radiating element gain must not exceed 8 39 dBi 850 MHz and 3 11 dBi 1900 MHz for mobile and fixed or mobile operating configurations The gain of the system antenna s used for SARA U260 SARA U280 modules i e the combined transmission line connector cable losses and radiating element gain must not exceed 3 5 dBi 850 MHz and 2 0 dBi 1900 MHz for mobile and fixed or mobile operating configurations UBX 13000995 R10 Early Production Information Approvals Page 163 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual 4 2 3 Modifications The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by u blox could void the user s authority to operate the equipment Manu
272. nect the other pin of the mechanical switch integrated in the SIM connector as SW1 pin in Figure 57 to the V INT 1 8 V supply output by means of a strong pull up resistor e g 1 KQ as R1 in Figure 57 Provide a 100 nF bypass capacitor e g Murata GRM155R71C104K at the SIM supply line VSIM close to the related pad of the SIM connector to prevent digital noise Provide a bypass capacitor of about 22 pF to 47 pF e g Murata GRM1555C1H470J on each SIM line VSIM SIM CLK SIM IO SIM RST very close to each related pad of the SIM connector to prevent RF coupling especially in case the RF antenna is placed closer than 10 30 cm from the SIM card holder Provide a low capacitance i e less than 10 pF ESD protection e g Tyco Electronics PESD0402 140 on each externally accessible SIM line close to each related pad of the SIM connector ESD sensitivity rating of SIM interface pins is 1 kV HBM according to JESD22 A114 so that according to the EMC ESD requirements of the custom application higher protection level can be required if the lines are externally accessible Limit capacitance and series resistance on each SIM signal to match the requirements for the SIM interface 27 7 ns max allowed rise time on SIM CLK 1 0 us max allowed rise time on SIM IO and SIM RST SIM CARD SARA G3 SARA U2 HOLDER TP v INT EMI e Swi SIM DET KA e sw2 J R2 VPP C6 vsiM EXB e e e L V
273. ned to prevent over voltage on VCC pins of the module and it should be selected according to the application requirements a DC DC switching charger is the typical choice when the charging source has an high nominal UBX 13000995 R10 Early Production Information Design in Page 83 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual voltage e g 12 V whereas a linear charger is the typical choice when the charging source has a relatively low nominal voltage 5 V If both a permanent primary supply charging source e g 12 V and a rechargeable back up battery e g 3 7 V Li Pol are available at the same time in the application as possible supply source then a proper charger regulator with integrated power path management function can be selected to supply the module while simultaneously and independently charging the battery Refer to sections 2 2 1 7 2 2 1 8 2 2 1 6 2 2 1 9 and 2 2 1 10 for specific design in The use of a primary not rechargeable battery is in general uncommon but appropriate parts can be selected given that the most cells available are seldom capable of delivering the burst peak current for a GSM call due to high internal resistance Refer to sections 2 2 1 5 2 2 1 6 2 2 1 9 and 2 2 1 10 for specific design in The usage of more than one DC supply at the same time should be carefully evaluated depending on the supply source characteristics different DC supply systems can result as mutuall
274. nes for VCC supply circuit selection and design VCC pins are internally connected but connect all the available pins to the external supply to minimize the power loss due to series resistance GND pins are internally connected but connect all the available pins to solid ground on the application board since a good low impedance connection to external ground can minimize power loss and improve RF and thermal performance SARA G3 and SARA U2 series modules must be supplied through the VCC pins by a proper DC power supply that should comply with the module VCC requirements summarized in Table 7 The proper DC power supply can be selected according to the application requirements see Figure 35 between the different possible supply sources types which most common ones are the following e Switching regulator e Low Drop Out LDO linear regulator e Rechargeable Lithium ion Li lon or Lithium ion polymer Li Pol battery e Primary disposable battery Main Supply No portable device Available Battery Li lon 3 7 V Yes always available Linear LDO Regulator Main Supply No less than 5 V Voltage gt 5V Yes greater than 5 V Switching Step Down Regulator Figure 35 VCC supply concept selection The DC DC switching step down regulator is the typical choice when the available primary supply source has a nominal voltage much higher e g greater than 5 V than the modules VCC operating supply voltage
275. network with power saving disabled the active mode is always held and the receiver and the DSP are periodically activated to monitor the paging channel For detailed current consumption values with the module registered with 2G or 3G network with power saving disabled fixed active mode see the SARA G3 series Data Sheet 1 and SARA U2 series Data Sheet 2 UBX 13000995 R10 Early Production Information System description Page 27 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual 1 5 2 RTC supply input output V BCKP The V_BCKP pin of SARA G3 and SARA U2 series modules connects the supply for the Real Time Clock RTC and Power On internal logic This supply domain is internally generated by a linear LDO regulator integrated in the Power Management Unit as described in Figure 15 The output of this linear regulator is always enabled when the main voltage supply provided to the module through the VCC pins is within the valid operating range with the module switched off or switched on SARA G340 SARA G350 SARA U2 series SARA G300 SARA G310 Power Baseband Power Baseband Management Processor Management Processor vec i vec VCC te he RTC VCC ep he RTC vcc E VCCEHI V BCKP IF Il V BCKP 32 kHz 32 kHz EXT32K Figure 15 RTC supply input output V BCKP and 32 kHz RTC timing r
276. network to the remote DCE attached to a remote DTE ee The DCD is set to ON during the execution of the CMGS CMGW USOWR USODL AT commands requiring input data from the DTE the DCD line is set to the ON state as soon as the switch to binary text input mode is completed and the prompt is issued DCD line is set to OFF as soon as the input mode is interrupted or completed for more details see the u blox AT Commands Manual 3 C8 The DCD line is kept in the ON state even during the online command mode to indicate that the data call is still established even if suspended while if the module enters command mode the DSR line is set to the OFF state For more details see DSR signal behavior description Se For scenarios when the DCD line setting is requested for different reasons e g SMS texting during online command mode the DCD line changes to guarantee the correct behavior for all the scenarios For instance in case of SMS texting in online command mode if the data call is released the DCD line is kept to ON till the SMS command execution is completed even if the data call release would request the DCD setting to OFF If AT amp CO is set the DCD module output line is set by default to the ON state low level at UART initialization and is then always held in the ON state UBX 13000995 R10 Early Production Information System description Page 44 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual RI s
277. ng process has taken place The paste listed in the example below meets these criteria Soldering Paste OM338 SAC405 Nr 143714 Cookson Electronics Alloy specification 95 596 Sn 3 996 Ag 0 6 Cu 95 5 Tin 3 9 Silver 0 696 Copper 95 596 Sn 4 096 Ag 0 596 Cu 95 5 Tin 4 0 Silver 0 596 Copper Melting Temperature 217 C Stencil Thickness 150 um for base boards The final choice of the soldering paste depends on the approved manufacturing procedures The paste mask geometry for applying soldering paste should meet the recommendations in section 2 11 ee The quality of the solder joints on the connectors half vias should meet the appropriate IPC specification 3 3 2 Reflow soldering A convection type soldering oven is strongly recommended over the infrared type radiation oven Convection heated ovens allow precise control of the temperature and all parts will be heated up evenly regardless of material properties thickness of components and surface color Consider the IPC 7530 Guidelines for temperature profiling for mass soldering reflow and wave processes published 2001 Reflow profiles are to be selected according to the following recommendations A Failure to observe these recommendations can result in severe damage to the device Preheat phase Initial heating of component leads and balls Residual humidity will be dried out Note that this preheat phase will not replace prior baking procedures T
278. ng the PWR ON input to a push button the pin will be externally accessible on the application device according to EMC ESD requirements of the application provide an additional ESD protection e g EPCOS CAO5PAS14THSG varistor array on the line connected to this pin close to accessible point ee The PWR_ON pin has high input impedance and is weakly pulled to the high level on the module Avoid keeping it floating in a noisy environment To hold the high logic level stable the PWR_ON pin must be connected to a pull up resistor e g 100 kQ biased by the V_BCKP supply pin of the module Se ESD sensitivity rating of the PWR_ON pin is 1 kV Human Body Model according to JESD22 A114 Higher protection level can be required if the line is externally accessible on the application board e g if an accessible push button is directly connected to PWR_ON pin Higher protection level can be achieved by mounting an ESD protection e g EPCOS CAO5PAS14THSG varistor array close to accessible point When connecting the PWR_ON input to an external device e g application processor use an open drain output on the external device with an external pull up resistor e g 100 kQ biased by the V_BCKP supply pin of the module as described in Figure 45 and Table 29 A compatible push pull output of an application processor can also be used in this case the pull up can be provided to pull the PWR_ON level high when the application processor is switched off If the
279. ng the module power on sequence at least until the activation of the V_INT supply output of the module to avoid latch up of circuits and allow a proper boot of the module If the external signals connected to the cellular module cannot be tri stated or set low insert a multi channel digital switch e g Texas Instruments SN74CB3Q16244 TS5A3159 or TS5A63157 between the two circuit connections and set to high impedance during module power down mode and during the module power on sequence ESD sensitivity rating of UART interface pins is 1 kV Human Body Model according to JESD22 A1 14 Higher protection level could be required if the lines are externally accessible on the application board Higher protection level can be achieved by mounting an ESD protection e g EPCOS CAO5PAS14THSG varistor array close to accessible points 2 6 1 2 Guidelines for UART layout design The UART serial interface requires the same consideration regarding electro magnetic interference as any other digital interface Keep the traces short and avoid coupling with RF line or sensitive analog inputs since the signals can cause the radiation of some harmonics of the digital data frequency 2 6 2 Auxiliary asynchronous serial interface UART AUX er Auxiliary UART interface is not supported by SARA U2 modules 2 6 2 1 Guidelines for UART AUX circuit design The auxiliary UART interface can be connected to an application processor if it can be set in pass through m
280. nlink samples refer to the u blox AT Commands Manual 3 UUBF UDBF UMGC USGC USTN commands The frame based voice band processing implements the Hands Free algorithm This consists of the Echo Canceller the Automatic Gain Control and the Noise Suppressor Hands Free algorithm acts on the uplink signal only Algorithms are configurable with AT commands refer to the u blox AT Commands Manual 3 UHFP command The frame based voice band processing also implements an AMR player The speech uplink path final block before radio transmission is the speech encoder Symmetrically on downlink path the starting block is the speech decoder which extracts speech signal from the radio receiver The circular buffer is a 3000 word buffer to store and mix the voice band samples from Midi synthesizer The buffer has a circular structure so that when the write pointer reaches the end of the buffer it is wrapped to the begin address of the buffer UBX 13000995 R10 Early Production Information System description Page 60 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Two different sample based sample rate converters are used an interpolator required to convert the sample based voice band processing sampling rate of 8 kHz to the analog audio front end output rate of 47 6 kHz a decimator required to convert the circular buffer sampling rate of 47 6 kHz to the I2Sx TX or the uplink path sample rate of 8 kHz The following
281. ns should meet the following prerequisites to comply with the module VCC requirements summarized in Table 7 Maximum pulse and DC discharge current the non rechargeable battery with its output circuit must be capable of delivering to VCC pins the specified maximum peak pulse current with 1 8 duty cycle and a DC current greater than the module maximum average current consumption refer to the SARA G3 series Data Sheet 1 or the SARA U2 series Data Sheet 2 The maximum pulse and the maximum DC discharge current is not always reported in battery data sheets but the maximum DC discharge current is typically almost equal to the battery capacity in Amp hours divided by 1 hour DC series resistance the non rechargeable battery with its output circuit must be capable of avoiding a VCC voltage drop greater than 400 mV during transmit bursts UBX 13000995 R10 Early Production Information Design in Page 88 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 2 2 1 6 Additional guidelines for VCC supply circuit design To reduce voltage drops use a low impedance power source The resistance of the power supply lines connected to the VCC and GND pins of the module on the application board and battery pack should also be considered and minimized cabling and routing must be as short as possible to minimize power losses Three pins are allocated for VCC supply Another twenty pins are designated for GND connection Even if all
282. ntegration Manual If the USB interface of a SARA U2 module is connected to the host before the module switch on or if the module is reset with the USB interface connected to the host the VID and PID are automatically updated runtime after the USB detection First VID and PID are the following VID 0x058B PID 0x0041 This VID and PID combination identifies a USB profile where the set of USB functions described in details above AT and Data GNSS tunneling Diagnostic SAP are not available AT commands must not be sent to the module over the USB profile identified by this VID and PID combination Then after a time period roughly 5 s depending on the host device enumeration timings the VID and PID are updated to the following ones which are related to the SARA U2 module USB profile with the set of USB functions described in details above AT and Data GNSS tunneling Diagnostic SAP VID 0x1546 PID 0x1102 1 9 3 2 USB and power saving If power saving is enabled by the AT UPSV command the modules automatically enter the USB suspended state when the device has observed no bus traffic for a specified time period see the USB 2 0 specifications 14 In suspended state the module maintains any USB internal status as device In addition the module enters the suspended state when the hub port it is attached to is disabled This is referred to as USB selective suspend The module exits suspend mode when there is bus activity If
283. oc lt 1 m LLJ SARA G3 and SARA U2 series GSM GPRS and GSM EGPRS HSPA Cellular Modules System Integration Manual Abstract This document describes the features and the system integration of the SARA G3 series GSM GPRS cellular modules and the SARA U2 GSM EGPRS HSPA cellular modules These modules are complete and cost efficient solutions offering voice and or data communication over diverse cellular radio access technologies in the same compact SARA form factor the SARA G3 series support up to 4 band GSM GPRS while the SARA U2 series support 2 band high speed HSPA and up to 2 band GSM EGPRS www u blox com UBX 13000995 R10 biox Qo Ox SARA G3 and SARA U2 series System Integration Manual Document Information Title SARA G3 and SARA U2 series GSM GPRS and GSM EGPRS HSPA SUDUME Cellular Modules Document type System Integration Manual Document number UBX 13000995 Revision date R10 23 Jul 2014 Document status Early Production Information Document status explanation Objective Specification Document contains target values Revised and supplementary data will be published later Advance Information Document contains data based on early testing Revised and supplementary data will be published later Early Production Information Document contains data from product verification Revised and supplementary data may be published later Production Information Document contains the final produ
284. ode so that the auxiliary UART interface can be accessed for SARA G3 modules firmware upgrade by means of the u blox EasyFlash tool and for diagnostic purpose Se It is highly recommended to provide direct access to the TXD_AUX RXD AUX pins of SARA G3 modules for execution of firmware upgrade over auxiliary UART using the u blox EasyFlash tool and for diagnostic purpose provide a testpoint on each line to accommodate the access and provide a 0 Q series resistor on each line to detach the module pin from any other connected device UBX 13000995 R10 Early Production Information Design in Page 123 of 192 VP biox The circuit with a 1 8 V application processor should be implemented as described in Figure 65 Application Processor 1 8V DTE Oohm TestPoint SARA G3 and SARA U2 series System Integration Manual SARA G3 series 1 8V DCE TxD oo e TXD AUX RxD onam eam RXD AUX GND GND Figure 67 UART AUX interface application circuit connecting a 1 8 V application processor If a 3 0 V application processor is used appropriate unidirectional voltage translators must be provided using the module V INT output as 1 8 V supply as described in Figure 66 Application Processor SARA G3 series 3 0V DTE Unidirectional 1 8V DCE 3V0 Voltage Translator 1v8 TP VCC VCCA VCCB e um V INT C1 C2 DIR1 ES Oohm TP TxD A1 B1 TXD_AUX Oohm TP RxD 4 3 A2 B2 RXD AUX
285. oglas PC29 09 0100A TheStripe GSM WCDMA PCB Antenna with cable and MMCX M RA connector 824 960 MHz 1710 2170 MHz 80 4 x 29 4 mm Taoglas FXUB63 07 0150C GSM WCDMA LTE PCB Antenna with cable and U FL connector 698 960 MHz 1575 42 MHz 1710 2170 MHz 2400 2690 MHz 96 0 x 21 0 mm Ethertronics P522310 Prestta GSM WCDMA PCB Antenna with cable and U FL connector 824 960 MHz 1710 2170 MHz 41 0x 15 0 mm EAD FSQS35241 UF 10 SQ7 GSM WCDMA LTE PCB Antenna with cable and U FL connector 690 960 MHz 1710 2170 MHz 2500 2700 MHz 110 0 x 21 0 mm Yaego ANTX100P001BWPEN3 GSM WCDMA PCB Antenna with cable and I PEX connector 824 960 MHz 1710 2170 MHz 50 0 x 20 0 mm Table 33 Examples of internal antennas with cable and connector UBX 13000995 R10 Early Production Information Design in Page 107 of 192 biox Table 34 lists some examples of possible external antennas Manufacturer Part Number Product Name Taoglas GSA 8827 A 101111 Phoenix Taoglas GSA 8821 A 301721 l Bar Taoglas TG 30 8112 Taoglas OMB 8912 03F21 Taoglas FW 92 RNT M Nearson T6150AM Laird Tech MAF94300 HEPTA SM Laird Tech TRA806 171033P Laird Tech CMS69273 Laird Tech OC69271 FNM Abracon APAMS 102 Table 34 Examples of external antennas UBX 13000995 R10 Description SARA G3 and SARA U2 series System Integration Manual GSM WCDMA LTE low profile adhesive mount Antenna with cable and SMA M connector
286. oints UBX 13000995 R10 Early Production Information Design in Page 142 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual ee Any external signal connected to the GPIOs must be tri stated or set low when the module is in power down mode and during the module power on sequence at least until the activation of the V_INT supply output of the module to avoid latch up of circuits and allow a proper boot of the module If the external signals connected to the cellular module cannot be tri stated or set low insert a multi channel digital switch e g Texas Instruments SN74CB3Q16244 TS5A3159 or TS5A63157 between the two circuit connections and set to high impedance during module power down mode and during the module power on sequence ee If the GPIO pins are not used they can be left unconnected on the application board 2 8 1 1 Guidelines for GPIO layout design The general purpose input output pins are generally not critical for layout 2 9 Reserved pins RSVD SARA G3 and SARA U2 series modules have pins reserved for future use All the RSVD pins except pin number 33 can be left unconnected on the application board Figure 82 illustrates the application circuit CS Pin 33 RSVD must be connected to GND SARA G3 SARA U2 RSVD EE RSVD EMI Figure 82 Application circuit for the reserved pins RSVD 2 10Module placement Optimize placement for minimum length of RF line and closer
287. ollowing precautions are suggested to achieve higher protection level A general purpose ESD protection device e g EPCOS CAO5P4S14THSG varistor array or EPCOS CT0402S14AHSG varistor should be mounted on the RESET N line close to accessible point The RESET N application circuit implemented in the EMC ESD approved reference design of SARA G3 modules is described in Figure 46 and Table 30 section 2 3 2 SIM interface The following precautions are suggested for SARA G3 and SARA U2 modules SIM interface VSIM SIM RST SIM IO SIM CLK depending on the application board handling to satisfy ESD immunity test requirements A 47 pF bypass capacitor e g Murata GRM1555C1H470J must be mounted on the lines connected to VSIM SIM RST SIM IO and SIM CLK pins to assure SIM interface functionality when an electrostatic discharge is applied to the application board enclosure It is suggested to use as short as possible connection lines at SIM pins Maximum ESD sensitivity rating of SIM interface pins is 1 kV Human Body Model according to JESD22 A114 Higher protection level could be required if SIM interface pins are externally accessible on the application board The following precautions are suggested to achieve higher protection level A low capacitance i e less than 10 pF ESD protection device e g Tyco Electronics PESD0402 140 should be mounted on each SIM interface line close to accessible points i e close to the SIM card holder The SIM int
288. ominal value Figure 38 and the components listed in Table 23 show an example of a high reliability power supply circuit where the VCC module supply is provided by an LDO linear regulator capable of delivering the specified highest peak pulse current with proper power handling capability The regulator described in this example supports a wide input voltage range and it includes internal circuitry for reverse battery protection current limiting thermal limiting and reverse current protection It is recommended to configure the LDO linear regulator to generate a voltage supply value slightly below the maximum limit of the module VCC normal operating range e g 4 1 V as in the circuit described in Figure 38 and Table 23 This reduces the power on the linear regulator and improves the whole thermal design of the supply circuit SARA G3 SARA U2 gE VCC 2 iN our 4 e e vcc vcc n U1 a C1 R1 C2 SHDN ADJ 2 gt a R2 ME GND Figure 38 Suggested schematic design for the VCC voltage supply application circuit using an LDO linear regulator Reference Description Part Number Manufacturer C1 C2 10 pF Capacitor Ceramic X5R 0603 20 6 3 V GRM188R60J106ME47 Murata R1 9 1 kQ Resistor 0402 5 0 1 W RC0402JR 079K1L Yageo Phycomp R2 3 9 kQ Resistor 0402 5 0 1 W RC0402JR 073K9L Yageo Phycomp U1 LDO Linear Regulator ADJ 3 0 A LT1764AEQ PBF Linear Technology
289. ommands refer to the u blox AT Commands Manual 3 o Signal routing USPM command o Analog amplification digital amplification USGC CLVL CRSL CMUT command o Digital filtering UBF UDBF commands O Hands free algorithms echo cancellation Noise suppression Automatic Gain control UHFP command Sidetone generation feedback of uplink speech signal to downlink path USTN command Playing mixing of alert tones Service tones Tone generator with 3 sinus tones UPAR command User generated tones Tone generator with a single sinus tone UTGN command PCM audio files for prompting The storage format of PCM audio files is 8 kHz sample rate signed 16 bits little endian mono O O O O O UBX 13000995 R10 Early Production Information System description Page 62 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 11General Purpose Input Output GPIO C SARA G300 and SARA G310 modules do not support GPIOs SARA G340 SARA G350 and SARA U2 modules provide pins which can be configured as general purpose input or output or can be configured to provide special functions via u blox AT commands for further details refer to the u blox AT Commands Manual 3 UGPIOC UGPIOR UGPIOW UGPS UGPRF SARA G340 and SARA G350 modules provide 4 configurable GPIO pins GPIO1 GPIO2 GPIO3 GPIO4 SARA U2 modules provide 9 configurable GPIO pins GPIO1 GPIO2 GPIO3 GPIO4 I2S RXD I2S TXD I2S CLK I2S5
290. ommunication interfaces UART interface 9 wire unbalanced 1 8 V asynchronous serial interface available for AT commands data communication FW upgrades by means of the FOAT feature see 1 9 1 Auxiliary UART interface not supported by SARA U2 series 3 wire unbalanced 1 8 V asynchronous serial interface available for FW upgrades by means of the u blox EasyFlash tool and for diagnostic see 1 9 2 USB interface not supported by SARA G3 series High Speed USB 2 0 compliant interface available for AT commands data communication FW upgrades by means of the FOAT feature FW upgrades by means of the u blox EasyFlash tool and for diagnostic see 1 9 3 DDC interface not supported by SARA G300 SARA G310 IC compatible 1 8 V interface available for the communication with u blox positioning chips modules and additionally except for SARA G3 series with other external l C devices as an audio codec see 1 9 4 1 9 1 Asynchronous serial interface UART 1 9 1 1 UART features The UART interface is a 9 wire 1 8 V unbalanced asynchronous serial interface available for AT commands and for packet switched circuit switched data communication on all the SARA G3 and SARA U2 series modules The UART interface provides RS 232 functionality conforming to the ITU T V 24 Recommendation more details available in ITU Recommendation 10 with CMOS compatible signal levels O V for low data bit or ON state and 1 8 V for high data bit or OFF state For
291. on Part Number Manufacturer C1 100 nF Capacitor Ceramic X7R 0402 1096 16 V GRM155R61A104KA01 Murata D1 D2 D3 Very Low Capacitance ESD Protection PESD0402 140 Tyco Electronics Table 45 Component for USB application circuits ee If the USB interface is not required by the customer application as the UART interface is used for AT and data communication with the host application processor the USB pins can be left unconnected but it is highly recommended providing direct access on the application board by means of accessible testpoint directly connected to the VUSB_DET USB_D USB_D pins of SARA U2 modules UBX 13000995 R10 Early Production Information Design in Page 125 of 192 Qo OX SARA G3 and SARA U2 series System Integration Manual 2 6 3 2 Guidelines for USB layout design The USB D USB D lines require accurate layout design to achieve reliable signaling at the high speed data rate up to 480 Mb s supported by the USB serial interface The characteristic impedance of the USB D USB D lines is specified by the Universal Serial Bus Revision 2 0 specification 14 The most important parameter is the differential characteristic impedance applicable for the odd mode electromagnetic field which should be as close as possible to 90 Q differential Signal integrity may be degraded if PCB layout is not optimal especially when the USB signaling lines are very long Use the following general routing guidelines to minimize sig
292. on accuracy power levels and spectrum performance are checked to be within tolerances when calibration parameters are applied Figure 89 Automatic test equipment for module tests 5 2 Test parameters for OEM manufacturer Because of the testing done by u blox with 10096 coverage an OEM manufacturer does not need to repeat firmware tests or measurements of the module RF performance or tests over analog and digital interfaces in their production test An OEM manufacturer should focus on e Module assembly on the device it should be verified that o Soldering and handling process did not damaged the module components o A All module pins are well soldered on device board o There are no short circuits between pins UBX 13000995 R10 Early Production Information Product testing Page 168 of 192 Qo OX SARA G3 and SARA U2 series System Integration Manual Component assembly on the device it should be verified that o Communication with host controller can be established o Theinterfaces between module and device are working o Overall RF performance test of the device including antenna Dedicated tests can be implemented to check the device For example the measurement of module current consumption when set in a specified status can detect a short circuit if compared with a Golden Device result Module AT commands are used to perform functional tests communication with host controller check SIM card interface check communicat
293. on the module works at the detected baud rate and the baud rate can only be changed by AT command see u blox AT Commands Manual 3 IPR command ee SARA G3 modules autobauding and SARA U2 modules one shot autobauding are enabled by default UBX 13000995 R10 Early Production Information System description Page 39 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual The following baud rates can be configured by AT command see u blox AT Commands Manual 3 IPR 1200 b s 2400 b s 4800 b s 9600 b s 19200 b s 38400 b s 57600 b s 115200 b s default value when the autobauding or the one shot autobauding are disabled 230400 b s 460800 b s 921600 b s ee 460800 b s and 921600 b s baud rates are not supported by SARA G3 series modules e 1200 b s and 230400 b s baud rates cannot be automatically detected by SARA G3 series modules e 460800 b s and 921600 b s baud rates cannot be automatically detected by SARA U2 series modules SARA G3 modules support the automatic frame recognition in conjunction with autobauding SARA U2 modules support the one shot automatic frame recognition in conjunction with one shot autobauding e SARA G3 series modules automatic frame recognition and SARA U2 series modules one shot automatic frame recognition are enabled by default as autobauding and one shot autobauding The following frame formats can be configured by AT command see u blox AT Commands Manual 3 ICF 8N1 8
294. onnected Mode Table 5 Module operating modes definition Operating Mode Not Powered Description Module is switched off Application interfaces are not accessible Internal RTC operates on SARA G340 G350 SARA U2 if a valid voltage is applied to V_BCKP Additionally a proper external 32 kHz signal must be fed to EXT32K on SARA G300 G310 modules to let internal RTC timer running Power Off odule is switched off normal shutdown by an appropriate power off event see 1 6 2 Application interfaces are not accessible nternal RTC operates on SARA G340 G350 SARA U2 as V_BCKP is internally generated A proper external 32 kHz signal must be fed to he EXT32K pin on SARA G300 G310 to let RTC imer running that otherwise is not in operation Idle The module is not ready to communicate with an external device by means of the application interfaces as configured to reduce consumption The module automatically enters idle mode whenever possible if power saving is enabled by he AT UPSV command see u blox AT Commands Manual 3 reducing power consumption see section 1 5 1 4 The CTS output line indicates when the UART interface is disabled enabled due to the module idle active mode according to power saving and HW flow control settings see 1 9 1 3 1 9 1 4 Power saving configuration is not enabled by default it can be enabled by AT UPSV see the u blox AT Commands Manual 3 A proper 32 kHz signal must be fed to the
295. ons see 1 5 1 4 1 9 1 4 Automatic periodic enable of the UART interface to receive and send data if AT UPSV 1 power saving is set see 1 9 1 4 RTC alarm occurs see u blox AT Commands Manual 3 CALA Data received on UART interface according to HW flow control AT amp K and power saving AT UPSV settings see 1 9 1 4 RTS input line set to the ON state by the DTE if HW flow control is disabled by AT amp K3 and AT UPSV 2 is set see 1 9 1 4 DTR input line set to the ON state by the DTE if AT UPSV 3 power saving is set see 1 9 1 4 USB detection applying 5 V typ to VUSB DET input see 1 9 3 The connected USB host forces a remote wakeup of the module as USB device see 1 9 3 GNSS data ready when the GPIO3 pin is informed by the connected u blox GNSS receiver that it is ready to send data over the DDC l C communication interface see 1 11 1 9 4 System description Page 18 of 192 VP biox Operating Mode Active Connected Description The module is ready to communicate with an external device by means of the application interfaces unless power saving configuration is enabled by the AT UPSV command see sections 1 5 1 4 1 9 1 4 and to the u blox AT Commands Manual 3 A voice call or a data call is in progress The module is ready to communicate with an external device by means of the application interfaces unless power saving configuration is enabled by the AT UPSV command see sections 1 5 1 4
296. onsumption profile typical of the GSM transmitting and receiving bursts The current consumption peak during a transmission slot is strictly dependent on the transmitted power which is regulated by the network The transmitted power in the transmit slot is also the more relevant factor for determining the average current consumption If the module is transmitting in 2G single slot mode as in GSM talk mode in the 850 or 900 MHz bands at the maximum RF power control level approximately 2 W or 33 dBm in the Tx slot burst the current consumption can reach an high peak pulse see SARA G3 series Data Sheet 1 and SARA U2 series Data Sheet 2 for 576 9 us width of the transmit slot burst with a periodicity of 4 615 ms width of 1 frame 8 slots burst so with a 1 8 duty cycle according to GSM TDMA Time Division Multiple Access If the module is transmitting in 2G single slot mode in the 1800 or 1900 MHz bands the current consumption figures are quite less high than the one in the low bands due to 3GPP transmitter output power specifications During a GSM call current consumption is not so significantly high in receiving or in monitor bursts and it is low in the bursts unused to transmit receive Figure 6 shows an example of the module current consumption profile versus time in GSM talk mode Current A 2 0 Peak current depends on TX power and actual antenna load 0 5 TX is slot Time ms GSM frame
297. ontexts can simultaneously be used SARA U2 modules support also Secure Hyper Text Transfer Protocol functionalities providing SSL encryption For more details about AT commands see the u blox AT Commands Manual 3 1 13 7 SMTP Se Not supported by SARA G300 SARA G310 and SARA U2 modules SARA G340 and SARA G350 modules support SMTP client functionalities It is possible to specify the common parameters e g server data authentication method etc can be specified to send an email to a SMTP server Emails can be sent with or without attachment Attachments are stored in the module local file system For more details about AT commands see the u blox AT Commands Manual 3 UBX 13000995 R10 Early Production Information System description Page 69 of 192 biox 1 13 8 SSL SARA G3 and SARA U2 series System Integration Manual Se Not supported by SARA G300 and SARA G310 modules ee Not supported by SARA G340 00S and SARA G350 00S SARA G350 00X modules The modules support the Secure Sockets Layer SSL Transport Layer Security TLS with certificate key sizes up to 4096 bits to provide security over the FTP and HTTP protocols ee The modules o support the server authentication without the root certificate verification o do not support the mutual authentication use of client certificates SSL TLS Version SSL 2 0 SSL 3 0 TLS 1 0 TLS 1 1 TLS 1 2 Table 14 SSL TLS version support Algorithm RSA PSK Table 15 A
298. oper VCC is present the RESET N of SARA U2 series is set to high logic level due to internal pull up to V BCKP the PWR ON is set to high logic level due to external pull up connected to V BCKP or VCC The PWR ON input pin is set low for a valid time period representing the start up event All the generic digital pins of the modules are tri stated until the switch on of their supply source V INT any external signal connected to the generic digital pins must be tri stated or set low at least until the activation of the V INT supply output to avoid latch up of circuits and allow a proper boot of the module The V INT generic digital interfaces supply output is enabled by the integrated power management unit The RESET N line of SARA G3 series rise suddenly to high logic level due to internal pull up to V INT The internal reset signal is held low by the integrated power management unit the baseband processor core and all the digital pins of the modules are held in reset state When the internal reset signal is released by the integrated power management unit the processor core starts to configure the digital pins of the modules to each default operational state The duration of this pins configuration phase differs within generic digital interfaces 3 s typical and the USB interface due to specific host device enumeration timings 5 s typical see section 1 9 3 The host application processor should not send any AT command over the AT interfa
299. or only the second SIM per time to the SIM interface of the SARA G3 and SARA U2 modules as described in Figure 58 SARA G3 modules do not support SIM hot insertion removal the module is able to properly use a SIM only if the SIM module physical connection is provided before the module boot and then held for normal operation Switching from one SIM to another one can only be properly done within one of these two time periods after module switch off by the AT CPWROFF and before module switch on by PWR ON after network deregistration by AT COPS 2 and before module reset by AT CFUN 16 or RESET N SARA U2 modules support SIM hot insertion removal on the SIM DET pin if the feature is enabled using the specific AT commands refer to sections 1 8 2 and 1 11 and to the u blox AT Commands Manual 3 UGPIOC UDCONF commands the switch from first SIM to the second SIM can be properly done when a Low logic level is present on the SIM DET pin SIM not inserted SIM interface not enabled without the necessity of a module re boot so that the SIM interface will be re enabled by the module to use the second SIM when an High logic level will be re applied on the SIM DET pin In the application circuit example represented in Figure 58 the application processor will drive the SIM switch using its own GPIO to properly select the SIM that is used by the module Another GPIO may be used to handle the SIM hot insertion removal function of SARA U2 modules
300. ositioning method provides the best and fastest solution according to the user configuration exploiting the benefit of having multiple and complementary positioning methods Hybrid positioning is implemented through a set of three AT commands that allow GNSS receiver configuration AT ULOCGNSS CellLocate service configuration AT ULOCCELL and requesting the position according to the user configuration AT ULOC The answer is provided in the form of an unsolicited AT command including latitude longitude and estimated accuracy if the position has been estimated by CellLocate and additional parameters if the position has been computed by the GNSS receiver The configuration of mobile network cells does not remain static e g new cells are continuously added or existing cells are reconfigured by the network operators For this reason when a hybrid positioning method has been triggered and the GNSS receiver calculates the position a database self learning mechanism has been implemented so that these positions are sent to the server to update the database and maintain its accuracy The use of hybrid positioning requires a connection via the DDC l C bus between the cellular modules and the u blox GNSS receiver see section 2 6 4 See GNSS Implementation Application Note 24 for the complete description of the feature ee u blox is extremely mindful of user privacy When a position is sent to the CellLocate server u blox is unable to tr
301. ource is not available or cannot deliver the peak system currents A power management IC should meet the following prerequisites to comply with the module VCC requirements summarized in Table 7 High efficiency internal step down converter compliant with the performances specified in section 2 2 1 2 Low internal resistance in the active path Vout Vbat typically lower than 50 mQ High efficiency switch mode charger with separate power path control UBX 13000995 R10 Early Production Information Design in Page 91 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Power path management IC System Uv Vin gt Vout Primary O Source T DC DC converter H and battery FET control logic d Li lon Li Pol E Battery Pack Vbat Charge controller E 8 GND GND g b Le Figure 42 Charger regulator with integrated power path management circuit block diagram Figure 43 and the components listed in Table 27 provide an application circuit example where the MPS MP2617 switching charger regulator with integrated power path management function provides the supply to the cellular module while concurrently and autonomously charging a suitable Li lon or Li Polymer battery with proper pulse and DC discharge current capabilities and proper DC series resistance according to the rechargeable battery recom
302. ow analog switch e g Fairchild F5A2567 Connect the contact C5 GND of the two UICC SIM to ground Provide a 100 nF bypass capacitor e g Murata GRM155R71C104K at the SIM supply line VSIM close to the related pad of the two SIM connectors to prevent digital noise Provide a bypass capacitor of about 22 pF to 47 pF e g Murata GRM1555C1H470J on each SIM line VSIM SIM CLK SIM IO SIM RST very close to each related pad of the two SIM connectors to prevent RF coupling especially in case the RF antenna is placed closer than 10 30 cm from the SIM card holders Provide a very low capacitance i e less than 10 pF ESD protection e g Tyco Electronics PESD0402 140 on each externally accessible SIM line close to each related pad of the two SIM connectors according to the EMC ESD requirements of the custom application Limit capacitance and series resistance on each SIM signal SIM CLK SIM IO SIM RST to match the requirements for the SIM interface 27 7 ns is the maximum allowed rise time on the SIM CLK line 1 0 us is the maximum allowed rise time on the SIM IO and SIM RST lines UBX 13000995 R10 Early Production Information Design in Page 116 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual
303. pacitance ESD Protection Microphone Connector Speaker Connector 82 nH Multilayer inductor 0402 self resonance frequency 1 GHz 8 Q Loud Speaker 2 2 kQ Electret Microphone 2 2 kQ Resistor 0402 5 0 1 W 0 Q Resistor 0402 5 0 1 W Filter less Mono 2 8 W Class D Audio Amplifier SARA G340 SARA G350 MIC_BIAS ZG e R1 C1 R2 R4 C2 MIC P K e C3 MIC N Eli Microphone Connector MIC Mg n R3 L2 FJ MIC GND e e Dev e e Q VCC n DT c4 C5 Audio ats D1 D2 Amplifier ciol c11 M Loud Speaker LSPK VDD eut LIS Connector sPK_P ES IN OUT e m C8 R5 SPK N Eti IN OUT C9 R6 GND J2 U1 C6 C7 X D3 D4 e e Part Number Manufacturer GRM188R60J106ME47 Murata GRM155R71C104KA88 Murata GRM1555C1H270JA01 Murata GRM155R71C473KA01 Murata CG0402MLE 18G Bourns Various Manufacturers Various Manufacturers LQG15HS82NJO2 Murata Various Manufacturers Various Manufacturers RC0402JR 072K2L Yageo Phycomp RC0402JR 070RL Yageo Phycomp SSM2305CPZ Analog Devices Table 51 Example of components for analog audio interface hands free mode application circuit If the analog audio interface is not used the analog audio pins MIC BIAS MIC GND MIC P MIC N SPK P SPK N can be left unconnected on the application board UBX 13000995 R10 Early Production Information Design in Page 136 of 192 SARA G3 and SARA U2 series System Integration Manual biox
304. path from DC source for VCC Make sure that the module RF and analog parts circuits are clearly separated from any possible source of radiated energy including digital circuits that can radiate some digital frequency harmonics which can produce Electro Magnetic Interference affecting module RF and analog parts circuits performance or implement proper countermeasures to avoid any possible Electro Magnetic Compatibility issue Make sure that the module RF and analog parts circuits high speed digital circuits are clearly separated from any sensitive part circuit which may be affected by Electro Magnetic Interference or employ countermeasures to avoid any possible Electro Magnetic Compatibility issue Provide enough clearance between the module and any external part ee The heat dissipation during transmission at maximum power can raise the temperature of the module and its environment as the application board locations near and below the SARA G3 series modules and more significantly the locations near and below the SARA U2 series modules avoid placing temperature sensitive devices close to the module UBX 13000995 R10 Early Production Information Design in Page 143 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 2 11 Module footprint and paste mask Figure 83 and Table 55 describe the suggested footprint i e copper mask and paste mask layout for SARA modules the proposed land pattern layout reflects t
305. per digital interfaces voltage level The external audio codec is controlled by the application processor using the DDC I C interface The clock output of the application processor is connected to the clock input of the external audio codec to provide clock reference Additional components are provided for EMC and ESD immunity conformity a 10 nF bypass capacitor and a series chip ferrite bead noise EMI suppression filter provided on each microphone line input and speaker line output of the external codec as described in Figure 80 and Table 53 The necessity of these or other additional parts for EMC improvement may depend on the specific application board design SARA U2 series SARA G340 SARA G350 1V8 V_INT EE e e Audio Codec a c c3 GND EN es v i E IRQn 12S_TXD SDIN MICBIAS 12S_RXD SDOUT je RA Microphone 25 CLK KEfl BCLK ES ENT Connector MIC 128 WA EZB Leck MICLP e e e e cs EMI 4h MICLN EE e e t AT interface J1 1V8 1V8 ks Deme Tes Te MICGND e ss DIle D2 Application Processor L d Ll R1 R2 2 Speaker SPK SDA SDA ae Connector SCL SCL OUTP reves e EMIA Clock Output BEN CLK OUTN e e e J2 GND INN GND C14 C13 C10 C9 i 4 e D3 L_ D4 Figure
306. pin GNSS data ready function provided by the GPIO3 pin GNSS RTC sharing function provided by the GPIO4 pin SARA G340 SARA G350 u blox GNSS SARA U2 series 1 8 V receiver 3V8 LDO Regulator 1V8 IN OUT e VCC GPIO2 GNSS Supply Enable SHDN d C1 R1 GND U GPIO3 EJ GNSS Data Ready TXD4 GPlO4 EEE GNSS RTC Sharing EXTINTO Network Indicator R2 GPIO1 ET Ti be Figure 81 GPIO application circuit Reference Description Part Number Manufacturer R1 47 KQ Resistor 0402 5 0 1 W Various manufacturers U1 Voltage Regulator for GNSS receiver See GNSS module Hardware Integration Manual R2 10 kO Resistor 0402 5 0 1 W Various manufacturers R3 47 KQ Resistor 0402 5 0 1 W Various manufacturers R4 820 O Resistor 0402 5 0 1 W Various manufacturers DL1 LED Red SMT 0603 LTST C190KRKT Lite on Technology Corporation T1 NPN BJT Transistor BC847 Infineon Table 54 Components for GPIO application circuit Se Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 kQ resistor on the board in series to the GPIO Se ESD sensitivity rating of the GPIO pins is 1 kV Human Body Model according to JESD22 A114 Higher protection level could be required if the lines are externally accessible on the application board Higher protection level can be achieved by mounting an ESD protection e g EPCOS CAO5P4S14THSG varistor array close to accessible p
307. pper range ensures t High temperature warning 485 C that any countermeasures used to limit the thermal heating will become effective even considering some thermal inertia of the complete assembly Equal to the internal temperature Ti measured in the worst case operating condition at typical supply voltage when the ambient F High temperature shutdown 95 C temperature Ta in the reference setup equals the absolute maximum temperature rating upper limit of the extended temperature range SARA G340 SARA G350 module mounted on a 79 x 62 x 1 41 mm 4 Layers PCB with a high coverage of copper Table 19 Thresholds definition for Smart Temperature Supervisor on the SARA G340 and SARA G350 modules Table 20 defines the temperature thresholds for SARA U2 modules Symbol Parameter Temperature Remarks Equal to the absolute minimum temperature rating for the cellular Low temperature shutdown EREL module the lower limit of the extended temperature range f Low temperature warning 30 C 10 C above t 20 C below t The higher warning area for upper range ensures that any countermeasures used to limit the thermal heating will become effective even considering some thermal inertia of the complete assembly High temperature warning 77 C Equal to the internal temperature Ti measured in the worst case operating condition at typical supply voltage when the ambient m High temperature shutdown 97 C temperature Ta in the refe
308. pplication device that integrates the module so that it provides good thermal dissipation e Force ventilation air flow within mechanical enclosure e Provide a heat sink component attached to the module top side with electrically insulated high thermal conductivity adhesive or on the backside of the application board below the cellular module as a large part of the heat is transported through the GND pads and dissipated over the backside of the application board Module PCB m m ums L Application PCB Heat Sink on application PCB bottom side Heat flow over Pa Module Pads CN fi 2A Application PCB EUN S Heat Sink Nu i Figure 84 Thermal solution example providing a heat sink on the backside of the application board below the cellular module For example after the installation of a robust aluminum heat sink with forced air ventilation on the back of the same application board described above the Module to Ambient thermal resistance Rth M A is reduced up to the Module to Case thermal resistance Rth M c defined in the SARA G3 series Data Sheet 1 or the SARA U2 series Data Sheet 2 The effect of lower Rth M A due to the installation of a robust heat sink on the backside of the application board with forced air ventilation can be seen from the module temperature increase which now can be summarized as following for SARA G3 modules e 1 C during a GSM voice
309. ption Page 25 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 5 1 5 VCC current consumption in fixed active mode power saving disabled Power saving configuration is by default disabled or it can be disabled using the appropriate AT command see u blox AT Commands Manual 3 AT UPSV command When power saving is disabled the module does not automatically enter idle mode whenever possible the module remains in active mode The module processor core is activated during active mode and the 26 MHz reference clock frequency is used Figure 13 roughly describes the current consumption profile of the SARA G300 and SARA G310 modules when the EXT32K input pin is fed by external 32 kHz signal with characteristics compliant to the one specified in SARA G3 series Data Sheet 1 or by the 32K OUT output pin provided by these modules or the SARA G340 and SARA G350 modules except 00 versions when power saving is disabled the module is registered with the network active mode is maintained and the receiver and the DSP are periodically activated to monitor the paging channel for paging block reception Current mA 100 60 120 mA 50 Paging period 0 47 2 12 s Time s Current mA 100 60 120 mA 50 20 40 mA DSP Time ms Enabled Enabled lt gt ACTIVE MODE Figure 13 VCC current consumption profile versus time of the SARA G300 and SARA G310 modules wi
310. r SN74AVC4T774 Texas Instruments U2 Unidirectional Voltage Translator SN74AVC2T245 Texas Instruments Table 41 Component for UART application circuit with partial V 24 link 6 wire in DTE DCE serial communication 3 0 V DTE UBX 13000995 R10 Early Production Information Design in Page 119 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual If only TXD RXD RTS CTS and DTR lines are provided as implemented in Figure 61 and in Figure 62 and if HW flow control is enabled AT amp K3 default setting the power saving can be activated as it can be done when the complete UART link is provided 9 wire as implemented in Figure 59 and in Figure 60 i e in these ways AT UPSV 1 the module automatically enters the low power idle mode whenever possible and the UART interface is periodically enabled as described in section 1 9 1 4 reaching low current consumption With this configuration when the module is in idle mode the data transmitted by the DTE will be buffered by the DTE and will be correctly received by the module when active mode is entered AT UPSV 3 the module automatically enters the low power idle mode whenever possible and the UART interface is enabled by the DTR line as described in section 1 9 1 4 reaching very low current consumption With this configuration not supported only by SARA G3 modules when the module is in idle mode the UART is re enabled 20 ms after DTR has been set ON and the recogni
311. r protection level can be achieved by mounting an ESD protection e g EPCOS CAO5PAS14THSG varistor array close to accessible point Connecting the RESET_N input to an external device e g application processor an open drain output can be directly connected without any external pull up as described in Figure 46 and Table 30 the internal pull up resistor provided by the module pulls the line to the high logic level when the RESET_N pin is not forced low by the application processor A compatible push pull output of an application processor can be used too SARA G3 series Application SARA G3 series SARA U2 series Processor SARA U2 series Reset Rad push button Output mE e TN RESET N L e KT nEsET N x ESD Figure 46 RESET_N application circuits using a push button and an open drain output of an application processor Reference Description Remarks ESD Varistor for ESD protection CT0402S14AHSG EPCOS Table 30 Example of ESD protection component for the RESET_N application circuit ee If the external reset function is not required by the customer application the RESET_N input pin can be left unconnected to external components but it is recommended providing direct access on the application board by means of accessible testpoint directly connected to the RESET_N pin UBX 13000995 R10 Early Production Information Design in Page 99 of 192 Qo Ox SARA G3 and SARA U2 series System
312. r sent the UART is disabled for 2 1 s on SARA G3 modules or for 2 5 s on SARA U2 modules and afterwards the interface is enabled again The module active mode duration outside an active call depends on Network parameters related to the time interval for the paging block reception minimum of 11 ms Duration of UART enable time in absence of data reception 20 ms The time period from the last data received at the serial port during the active mode the module does not enter idle mode until a timeout expires The second parameter of the UPSV AT command configures this timeout from 40 2G frames i e 40 x 4 615 ms 184 ms up to 65000 2G frames i e 65000 x 4 615 ms 300 s Default value is 2000 2G frames i e 2000 x 4 615 ms 2 9 2 s The active mode duration can be extended indefinitely since every subsequent character received during the active mode resets and restarts the timer The timeout is ignored only by SARA U2 modules immediately after AT UPSV 1 has been sent so that the UART interface is disabled and the module may enter idle mode immediately after the AT UPSV 1 is sent The hardware flow control output CTS line indicates when the UART interface is enabled data can be sent and received over the UART if HW flow control is enabled as illustrated in Figure 25 Data input CTS OFF y CTS ON lt gt P ii 4 9i time s 0 47 2 10 5 10 ms min 9 2 s d
313. rdware flow control is enabled as it is by default the CTS line indicates when the UART interface is enabled data can be sent and received The module drives the CTS line to the ON state or to the OFF state when it is either able or not able to accept data from the DTE over the UART see 1 9 1 4 for more details ee If hardware flow control is enabled then when the CTS line is OFF it does not necessarily mean that the module is in low power idle mode but only that the UART is not enabled as the module could be forced to stay in active mode for other activities e g related to the network or related to other interfaces ee When the multiplexer protocol is active the CTS line state is mapped to FCon FCoff MUX command for flow control issues outside the power saving configuration while the physical CTS line is still used as a power state indicator For more details see Mux Implementation Application Note 23 The CTS hardware flow control setting can be changed by AT commands for more details see u blox AT Commands Manual 3 AT amp K AT Q AT IFC AT command If the hardware flow control is not enabled the CTS line after the UART initialization behaves as following on SARA U2 modules the CTS line is always held in the ON state on SARA G3 modules the CTS line is set in the ON or OFF state accordingly to the power saving state as illustrated in Figure 25 if AT UPSV 2 is set and the CTS line is held in the ON state otherwise Se Whe
314. rease the temperature for internal circuitry of the SARA G3 and SARA U2 series modules for a given operating ambient temperature This improves device long term reliability for applications operating at high ambient temperature A few hardware techniques may be used to reduce the Module to Ambient thermal resistance in the application Connect each GND pin with solid ground layer of the application board and connect each ground area of the multilayer application board with complete via stack down to main ground layer Provide a ground plane as wide as possible on the application board Optimize antenna return loss to optimize overall electrical performance of the module including a decrease of module thermal power Refer to SARA G3 and SARA U2 series Data Sheet 1 for the Rth m a value in this application condition Temperature is measured by internal sensor of cellular module Steady state thermal equilibrium is assumed The module s temperature in idle state can be considered equal to ambient temperature UBX 13000995 R10 Early Production Information Design in Page 145 of 192 Q Ox SARA G3 and SARA U2 series System Integration Manual e Optimize the thermal design of any high power component included in the application as linear regulators and amplifiers to optimize overall temperature distribution in the application device e Select the material the thickness and the surface of the box i e the mechanical enclosure of the a
315. rectly received by the module when RTS is set to ON Data sent by the module is buffered by the module and will be correctly received by the DTE when it is ready to receive data i e RTS line will be ON 0 Disabled AT amp KO ONorOFF ON or OFF Data sent by the DTE is correctly received by the module Data sent by the module is correctly received by the DTE if it is ready to receive data otherwise data is lost 1 Enabled AT amp K3 ON ON or OFF Data sent by the DTE should be buffered by the DTE and will be correctly received by the module when active mode is entered Data sent by the module is correctly received by the DTE 1 Enabled AT amp K3 OFF ON or OFF Data sent by the DTE should be buffered by the DTE and will be correctly received by the module when active mode is entered Data sent by the module is buffered by the module and will be correctly received by the DTE when it is ready to receive data i e RTS line will be ON 1 Disabled AT amp KO ON or OFF ON or OFF The first character sent by the DTE is lost but after 20 ms the UART and the module are waked up recognition of subsequent characters is guaranteed after he complete UART module wake up Data sent by the module is correctly received by the DTE if it is ready to receive data otherwise data is lost 2 Enabled AT amp K3 ONor OFF ONorOFF Not Applicable HW flow control cannot be enabled with AT UPSV 2 Disabled AT amp KO ON ON or OFF Data sent by the DTE is correctly
316. rence setup equals the absolute maximum temperature rating upper limit of the extended temperature range SARA U2 module mounted on a 79 x 62 x 1 41 mm 4 Layers PCB with a high coverage of copper Table 20 Thresholds definition for Smart Temperature Supervisor on the SARA U2 modules Se The sensor measures board temperature inside the shields which can differ from ambient temperature UBX 13000995 R10 Early Production Information System description Page 74 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 13 11 AssistNow clients and GNSS integration ee Not supported by SARA G300 and SARA G310 modules For customers using u blox GNSS receivers SARA G340 SARA G350 and SARA U2 modules feature embedded AssistNow clients AssistNow A GPS provides better GNSS performance and faster Time To First Fix The clients can be enabled and disabled with an AT command see the u blox AT Commands Manual 3 SARA G340 SARA G350 and SARA U2 modules act as a stand alone AssistNow client making AssistNow available with no additional requirements for resources or software integration on an external host micro controller Full access to u blox positioning receivers is available via the cellular modules through a dedicated DDC PC interface while the available GPIOs can handle the positioning chipset module power on off This means that the cellular module and the positioning chips and modules can be controlled through a s
317. rfaces and other uses Only 6 contacts are required and must be connected to the module SIM card interface as described above since the modules do not support the additional auxiliary features contacts C4 AUX1 and C8 AUX2 Removable SIM card are suitable for applications where the SIM changing is required during the product lifetime VUVVVY A SIM card holder can have 6 or 8 positions if a mechanical card presence detector is not provided or it can have 6 2 or 8 2 positions if two additional pins related to the normally open mechanical switch integrated in the SIM connector for the mechanical card presence detection are provided select a SIM connector providing 6 2 or 8 2 positions if the optional SIM detection feature is required by the custom application otherwise a connector without integrated mechanical presence switch can be selected Solderable UICC SIM chip contacts mapping M2M UICC Form Factor is defined by ETSI TS 102 671 as follows Package Pin 8 UICC Contact C1 VCC Supply gt It must be connected to VSIM Package Pin 7 UICC Contact C2 RST Reset gt It must be connected to SIM_RST Package Pin 6 UICC Contact C3 CLK Clock gt It must be connected to SIM_CLK Package Pin 5 UICC Contact C4 AUX1 Auxiliary contact gt It must be left not connected Package Pin 1 UICC Contact C5 GND Ground gt It must be connected to GND Package Pin 2 UICC Contact C6 VPP Programming supply gt It must be connecte
318. rol is enabled AT amp K3 that is the default setting the pin can be connected using a 0 Q series resistor to GND or to the active module CTS low electrical level when the module is in active mode the UART interface is enabled and the HW flow control is enabled Connect the module DTR input line to GND since the module requires DTR active low electrical level Leave DSR DCD and RI lines of the module unconnected and floating If RS 232 compatible signal levels are needed the Maxim 13234E voltage level translator can be used This chip translates voltage levels from 1 8 V module side to the RS 232 standard UBX 13000995 R10 Early Production Information Design in Page 121 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual If a 1 8 V application processor is used the circuit that should be implemented as described in Figure 65 Application Processor SARA G3 SARA U2 1 8V DTE 1 8V DCE TxD RxD RTS CTS DTR DSR RI DCD GND Figure 65 UART interface application circuit with partial V 24 link 3 wire in the DTE DCE serial communication 1 8 V DTE If a 3 0 V Application Processor is used appropriate unidirectional voltage translators must be provided using the module V INT output as 1 8 V supply as described in Figure 66 Application Processor SARA G3 SARA U2 3 0V DTE Unidirectional 1 8V DCE 3V0 Voltage Translator 1v8 TP
319. rovides the GNSS data ready function to sense when a u blox GNSS receiver connected to the cellular module is ready to send data via the DDC lC interface setting the parameter gpio mode of AT UGPIOC command to 4 The pin configured to provide the GNSS data ready function is set as o Input to sense the line status waking up the cellular module from idle mode when the u blox GNSS receiver is ready to send data via the DDC I C interface if the first AT UGPS parameter is set to 1 and the first AT UGPRF parameter is set to 16 o Tri state with an internal active pull down enabled otherwise default setting GNSS RTC sharing Only the GPIO4 pin provides the GNSS RTC sharing function to provide an RTC Real Time Clock synchronization signal to the u blox GNSS receiver connected to the cellular module setting the parameter gpio mode of AT UGPIOC command to 5 The pin configured to provide the GNSS RTC sharing function is set as o Output to provide an RTC Real Time Clock synchronization signal to the u blox GNSS receiver if the first AT UGPS parameter is set to 1 and the first AT UGPRF parameter is set to 32 o Low otherwise default setting SIM card detection The SIM DET pin of SARA G3 modules is by default configured to detect SIM card mechanical presence and this configuration cannot be changed by AT command The SIM DET pin of SARA U2 modules is by default configured to detect SIM card mechanical presence
320. rved RSVD All 33 A RESERVED pin This pin must be connected to ground See section 2 9 RSVD SARA G3 17 19 A RESERVED pin Leave unconnected See section 2 9 RSVD SARA G340 31 A RESERVED pin Internally not connected Leave unconnected SARA G350 See section 2 9 SARA U2 RSVD SARA G300 16 23 A RESERVED pin Pin disabled Leave unconnected SARA G310 25 27 See section 2 9 34 37 RSVD SARA G300 44 49 A RESERVED pin Leave unconnected SARA G310 See section 2 9 SARA U2 RSVD SARA G300 62 A RESERVED pin Leave unconnected SARA G310 See section 2 9 Table 4 SARA G3 and SARA U2 series modules pin definition grouped by function UBX 13000995 R10 Early Production Information System description Page 17 of 192 biox 1 4 Operating modes SARA G3 and SARA U2 series System Integration Manual SARA G3 modules have several operating modes The operating modes defined in Table 5 and described in detail in Table 6 provide general guidelines for operation General Status Operating Mode Definition Not Powered Mode Power Off Mode Idle Mode Power down Normal Operation VCC supply not present or below operating range module is switched off VCC supply within operating range and module is switched off Module processor core runs with 32 kHz reference that is generated by The internal 32 kHz oscillator SARA G340 SARA G350 and SARA U2 series The 32 kHz signal provided at the EXT32K pin SARA G300 and SARA G310 Active Mode C
321. s 1 8V 3V SIM clock 1 8V 3V SIM data Internal 4 7k pull up 8V 3V SIM reset 8V 3V SIM supply Provided by GPIO5 1 8 V SIM detect input nner pull down 200 pA 8 V DSR output Driver strength 1 mA 1 8 V RI output Driver strength 2 mA 1 8 V DCD output Driver strength 2 mA 1 8 V DTR input Internal pull up 125 pA 8 V Flow ctrl input Internal pull up 240 pA 8 V Flow ctrl output Driver strength 6 mA 8 V Data input Internal pull up 240 pA 1 8 V Data output Driver strength 6 mA Not Available Not Available 5 V Supply detection High Speed USB 2 0 High Speed USB 2 0 1 8 V Clock input Inner pull down 200 pA 8 V Data input Internal pull up 240 pA 8 V Data output Driver strength 6 mA 8 V Flow ctrl output Driver strength 6 mA 1 8 V Flow ctrl input Inner pull down 200 pA 8 V open drain Driver strength 1 mA LISA U200 00S N A 8 V open drain Driver strength 1 mA LISA U200 00S N A Appendix Page 180 of 192 biox Pin Name Audio Analog MIC_BIAS MIC_GND MIC_P MIC_N SPK P SPK N Digital I2S5 TXD 125 RXD I2S_WA I2S_CLK I251 WA 1251 TXD I2S1_CLK 12S1_RXD UBX 13000995 R10 N 46 47 49 48 44 45 35 27 34 36 SARA G3 series SARA G340 SARA G350 2 2 V supply output for external microphone SARA G340 SARA G350 Local ground sense for external microphone SARA G34
322. s Channel 4 AT and Data not available on SARA G300 SARA G310 modules Channel 5 AT and Data not available on SARA G300 SARA G310 modules Channel 6 GNSS tunneling not available on SARA G300 SARA G310 modules Channel 7 SIM Access Profile not available on SARA G3 series modules For more details refer to Mux implementation Application Note 23 1 9 2 Auxiliary asynchronous serial interface UART AUX C8 The auxiliary UART interface is not available on SARA U2 series modules SARA G3 modules provide the auxiliary UART interface it is a 3 wire unbalanced 1 8 V asynchronous serial interface only the RXD_AUX data output and TXD_AUX data input are provided available for module FW upgrade by means of the u blox EasyFlash tool and for diagnostic purpose The AT commands interface is not available on the auxiliary UART interface 1 9 3 USB interface ee The USB interface is not available on SARA G3 series modules 1 9 3 1 USB features SARA U2 modules include a High Speed USB 2 0 compliant interface with maximum data rate of 480 Mb s between the module and a host processor The module itself acts as a USB device and can be connected to any USB host such as a Personal Computer or an embedded application microprocessor for AT commands data communication FW upgrade by means of the FOAT feature FW upgrade by means of the u blox EasyFlash tool and for diagnostic purpose The USB_D USB_D pins carry USB serial data and signaling whi
323. s module according to the application board classification see ETSI EN 301 489 1 19 to satisfy the requirements for ESD immunity test summarized in Table 56 Antenna interface The ANT pin of SARA G3 modules provides ESD immunity up to 4 kV for direct Contact Discharge and up to 8 kV for Air Discharge according to IEC 61000 4 2 no further precaution to ESD immunity test is needed as implemented in the EMC ESD approved reference design of SARA G3 modules The ANT pin of SARA U2 modules provides ESD immunity up to 2 kV for direct Contact Discharge and up to 4 kV for Air Discharge according to IEC 61000 4 2 higher protection level is required if the line is externally accessible on the device i e the application board where the SARA U2 module is mounted The following precautions are suggested for satisfying ESD immunity test requirements using SARA U2 modules If the device implements an embedded antenna the device insulating enclosure should provide protection to direct contact discharge up to 4 kV and protection to air discharge up to 8 kV to the antenna interface If the device implements an external antenna the antenna and its connecting cable should provide a completely insulated enclosure able to provide protection to direct contact discharge up to 4 kV and protection to air discharge up to 8 kV to the whole antenna and cable surfaces If the device implements an external antenna and the antenna and its connecting cable do
324. s modules can be properly reset rebooted by AT CFUN command see the u blox AT Commands Manual 3 for more details This command causes an internal or software reset of the module which is an asynchronous reset of the module baseband processor The current parameter settings are saved in the module s non volatile memory and a proper network detach is performed this is the proper way to reset the modules An abrupt hardware reset occurs on SARA G3 and SARA U2 series modules when a low level is applied on the RESET N input pin for a specific time period In this case the current parameter settings are not saved in the module s non volatile memory and a proper network detach is not performed ee It is highly recommended to avoid an abrupt hardware reset of the module by forcing a low level on the RESET_N input during modules normal operation the RESET_N line should be set low only if reset or shutdown via AT commands fails or if the module does not provide a reply to a specific AT command after a time period longer than the one defined in the u blox AT Commands Manual 3 As described in Figure 21 both the SARA G3 and SARA U2 series modules are equipped with an internal pull up resistor which pulls the line to the high logic level when the RESET_N pin is not forced low from the external The pull up is internally biased by V INT on SARA G3 modules and is biased by V_BCKP on SARA U2 modules A series Schottky diode is mounted inside the SARA
325. s not stop operation V BCKP within operating range RTC value read after a restart of the system is reliable 0 05 V V BCKP 1 00 V RTC oscillator does not necessarily stop operation V BCKP below operating range RTC value read after a restart of the system is not reliable 0 00 V V BCKP 0 05 V RTC oscillator stops operation V BCKP below operating range RTC value read after a restart of the system is reliable Table 8 RTC value reliability as function of V BCKP voltage value Consider that the module cannot switch on if a valid voltage is not present on VCC even when the RTC is supplied through V BCKP meaning that VCC is mandatory to switch on the module UBX 13000995 R10 Early Production Information System description Page 28 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual The RTC has very low power consumption but is highly temperature dependent For example at 25 C with the V_BCKP voltage equal to the typical output value the current consumption is approximately 2 pA see the Input characteristics of Supply Power pins table in the SARA G3 series Data Sheet 1 and SARA U2 series Data Sheet 2 for the detailed specification whereas at 70 C and an equal voltage the current consumption increases to 5 10 pA If V_BCKP is left unconnected and the module main voltage supply is removed from VCC the RTC is supplied from the bypass capacitor mounted inside the module However this capacitor is no
326. s obscuring the operator s carriers entitled to give access to the cellular service The Jamming Detection Feature detects such artificial interference and reports the start and stop of such conditions to the client which can react appropriately by e g switching off the radio transceiver to reduce power consumption and monitoring the environment at constant periods The feature detects at radio resource level an anomalous source of interference and signals it to the client with an unsolicited indication when the detection is entered or released The jamming condition occurs when The module has lost synchronization with the serving cell and cannot select any other cell The band scan reveals at least n carriers with power level equal or higher than threshold On all such carriers no synchronization is possible The client can configure the number of minimum disturbing carriers and the power level threshold by using the AT UCD command 3 The jamming condition is cleared when any of the above mentioned statements does not hold The congestion i e jamming detection feature can be enabled and configured by the UCD AT command for more details see the u blox AT Commands Manual 3 UBX 13000995 R10 Early Production Information System description Page 68 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 13 4 TCP IP and UDP IP Se Not supported by SARA G300 and SARA G310 modules Via the AT commands it is
327. s require large current pulses in connected mode as well as LISA U series when a 2G call is enabled LISA C2 series do not require large current pulses due to the CDMA channel access technology For the detailed current consumption values see the related module datasheet 1 4 5 6 Detailed supply circuit design in guidelines are reported in section 2 2 1 and in the corresponding System Integration Manual of the module 7 8 RTC supply input output V BCKP The same compatible external circuit can be implemented for SARA and LISA U series even if there are minor differences in the V_BCKP typical output voltage and input voltage range as reported in Table 60 or in the relative datasheet of the module 1 4 5 6 LISA C2 series do not provide V_BCKP RTC supply input output as well as the whole RTC functionality Interfaces supply output V_INT The same compatible external circuit can be implemented for SARA and LISA series there are no differences in the V_INT output characteristics UBX 13000995 R10 Early Production Information Appendix Page 174 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual A 4 2 System functions interfaces Module power on SARA G3 and LISA series power on sequence is initiated in one of the ways summarized in Table 59 For more details see section 1 6 1 or to the relative System Integration Manual of the module 7 8 SARA G3 series LISA C2 series LISA U1 series LIS
328. s to connect digital interfaces of the module to a 3 0 V device see section 2 6 1 Supply a 1 8 V u blox 6 or subsequent GNSS receiver see section 2 6 4 for more details Indicate when the module is switched on see sections 1 6 1 1 6 2 for more details SARA G3 and SARA U2 series System Integration Manual Do not apply loads which might exceed the limit for maximum available current from V_INT supply as this can cause malfunctions in internal circuitry supplies to the same domain The SARA G3 series Data Sheet 1 and the SARA U2 series Data Sheet 2 describe the detailed electrical characteristics V_INT can only be used as an output do not connect any external regulator on V_INT Since the V_INT supply is generated by an internal switching step down regulator the V_INT voltage ripple can range from 15 mVpp during active mode or connected mode when the switching regulator operates in PWM mode to 90 mVpp SARA G3 series or 70 mVpp SARA U2 series in low power idle mode when the switching regulator operates in PFM mode CS It is not recommended to supply sensitive analog circuitry without adequate filtering for digital noise V INT supply output pin provides internal short circuit protection to limit start up current and protect the device in short circuit situations No additional external short circuit protection is required E ESD sensitivity rating of the V_INT supply pin is 1 kv Human Body Model according to JESD22 A114
329. sek N EZB e Connector 27pF 27pF esp ESD IST MEL 8V Digital Audio Device 12S_RXD 125 Data Output I2S5 CLK 12S Clock 128 TXD 125 Data Input 12S WA 12S Word Alligment Figure 86 Example of schematic diagram to integrate SARA G340 G350 module in an application board using all the interfaces UBX 13000995 R1 0 Early Production Information Design in Page 154 of 192 Se biox 2 15 3 Schematic for SARA U2 series modules integration SARA G3 and SARA U2 series System Integration Manual Figure 87 is an example of a schematic diagram where a SARA U2 module is integrated into an application board using all the available interfaces and functions of the module SARA U2 series 3V8 15pF 33pF Connector External F m vec ant EA e Antenna vcc 39nH vcc 10k 82nH 330uF 100nF 10nF S6pF 15PF MEME GND ANT_DET Ga e Y L L L 27pF X ESD V BCKP VINT E SIM Card Holder e E ere tp 1k RTC V_INT swi back up T 00uF MEN c SIM DET aye ENS VSIM CCVCC C1 Application CCVPP C6 Processor 100kQ B siM 10 Kf CCIO C7 Open F 9 EH ws ov siM ck IKE CCCLK C3 DR siM RsT IK CCRST C2 mpm 3x LL LO x23 owes Open l gt KB reset v 470k 47bF 47pF 47pF 47pF 100nF Esp Esp ESD ESD ESD ESD Drain VE i ae u blox 1 8
330. ser directement leur candidature pour une certification FCC ainsi que pour un certificat Industrie Canada d livr par l organisme charg de ce type d appareil portable Ceci est obligatoire afin d tre en accord avec les exigences SAR pour les appareils portables Tout changement ou modification non express ment approuv par la partie responsable de la certification peut annuler le droit d utiliser l quipement 4 3 R amp TTED and European conformance CE mark SARA G3 series SARA U270 and SARA U290 modules have been evaluated against the essential requirements of the 1999 5 EC Directive In order to satisfy the essential requirements of the 1999 5 EC Directive the modules are compliant with the following standards Radio Frequency spectrum use R amp TTE art 3 2 o EN301 511 V9 02 Electromagnetic Compatibility R amp TTE art 3 15 o EN301 489 1 V1 9 2 o EN30OI 489 7 V1 4 1 Health and Safety R amp TTE art 3 1a o EN 60950 1 2006 A11 2009 A1 2010 A12 2011 AC 2011 o EN62311 2008 The conformity assessment procedure for all the SARA G3 series modules except SARA G350 ATEX modules referred to in Article 10 and detailed in Annex IV of Directive 1999 5 EC has been followed with the involvement of the following Notified Body number 1909 Thus the following marking is included in the product C 1909 UBX 13000995 R10 Early Production Information Approvals Page 165 of 192 Qo Ox SARA G3 and SARA U2 series Syste
331. series System Integration Manual Examples of antennas Table 32 lists some examples of possible internal on board surface mount antennas Manufacturer Part Number Product Name Description Taoglas PA 25 A Anam GSM WCDMA SMD Antenna 824 960 MHz 1710 2170 MHz 36 0 x 6 0 x 5 0 mm Taoglas PA 710 A Warrior GSM WCDMA LTE SMD Antenna 698 960 MHz 1710 2170 MHz 2300 2400 MHz 2490 2690 MHz 40 0 x 6 0 x 5 0 mm Taoglas PCS 06 A Havok GSM WCDMA LTE SMD Antenna 698 960 MHz 1710 2170 MHz 2500 2690 MHz 42 0 x 10 0 x 3 0 mm Antenova A10340 Calvus GSM WCDMA SMD Antenna 824 960 MHz 1710 2170 MHz 28 0 x 8 0 x 3 2 mm Ethertronics P522304 Prestta GSM WCDMA SMD Antenna 824 960 MHz 1710 2170 MHz 35 0x9 0x 3 2 mm 2J 2JE04 GSM WCDMA SMD Antenna 824 960 MHz 1710 2170 MHz 24 0 x 5 5 x 4 4 mm Yaego ANT3505BOOOTWPENA GSM WCDMA SMD Antenna 824 960 MHz 1710 2170 MHz 35 0 x 5 0 x 6 0 mm Table 32 Examples of internal surface mount antennas Table 33 lists some examples of possible internal off board PCB type antennas with cable and connector Manufacturer Part Number Product Name Description Taoglas FXP14 A 07 0100A GSM WCDMA PCB Antenna with cable and U FL connector 824 960 MHz 1710 2170 MHz 70 4 x 20 4 mm Taoglas FXP14R A 07 0100A GSM WCDMA PCB Antenna with cable and U FL connector Integrated 10k shunt diagnostic resistor 824 960 MHz 1710 2170 MHz 80 0 x 20 8 mm Ta
332. siM EIB e o LU VCC C1 SIM IO EJ e e 10 C7 SIM CLK EC CLK C3 1121314 SIM RST ET e e RST C2 SIM Card C1 C2 C3 C4 C5 pil p2 E i contact so n Figure 55 Application circuit for the connection to a single removable SIM card with SIM detection not implemented Reference Description Part Number Manufacturer C1 C2 C3 CA 47 pF Capacitor Ceramic COG 0402 596 50 V GRM1555C1H470JA01 Murata C5 100 nF Capacitor Ceramic X7R 0402 1096 16 V GRM155R71C104KA01 Murata D1 D2 D3 D4 Very Low Capacitance ESD Protection PESD0402 140 Tyco Electronics J1 SIM Card Holder Various Manufacturers 6 positions without card presence switch C707 10M006 136 2 Amphenol Table 36 Example of components for the connection to a single removable SIM card with SIM detection not implemented UBX 13000995 R10 Early Production Information Design in Page 113 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual Guidelines for single SIM chip connection An application circuit for the connection to a single solderable SIM chip M2M UICC Form Factor is described in Figure 56 where the optional SIM detection feature is not implemented see the circuit described in Figure 57 if the SIM detection feature is required Follow these guidelines connecting the module to a solderable SIM chip without SIM presence detection Connect the UICC SIM contacts C1 VCC and C6 VPP to the VSIM pin of th
333. ss capacitor e g the Murata BLM15HD182SN1 ferrite bead and the Murata GRM1555C1H220J 22 pF capacitor at the input of the external LNA supply line u blox GNSS SARA G340 SARA G350 1 8 V receiver SARA U2 series V BCKP V BCKP T n TP VCC 4 i o EE v iNT Te RS 1V8 1v8 X pa GNSS supply enabled EE GPio2 T2 if R3 SDA2 SCL2 GNSS data ready TxD1 EXTINTO GPIO3 GNSS RTC sharin GPIOA Figure 73 Application circuit for connecting SARA G3 SARA U2 modules to u blox 1 8 V GNSS receivers using V INT as supply Reference Description Part Number Manufacturer R1 R2 4 7 kO Resistor 0402 596 0 1 W RC0402JR 074K7L Yageo Phycomp R3 47 kQ Resistor 0402 596 0 1 W RC0402JR 0747KL Yageo Phycomp R4 10 kQ Resistor 0402 5 0 1 W RC0402JR 0710KL Yageo Phycomp R5 100 kQ Resistor 0402 5 0 1 W RC0402JR 07100KL Yageo Phycomp T1 P Channel MOSFET Low On Resistance IRLML6401 International Rectifier or NTZS3151P ON Semi T2 NPN BJT Transistor BC847 Infineon C1 100 nF Capacitor Ceramic X7R 0402 1096 16 V GRM155R71C104KA01 Murata Table 47 Components for connecting SARA G3 SARA U2 modules to u blox 1 8 V GNSS receivers using V_INT as supply For additional guidelines regarding the design of applications with u blox 1 8 V GNSS receivers see the GNSS Implementation Application Note 24 and to the Hardware Integration Manual of the u blox GNSS receivers UBX 13000
334. ssion line if top layer to buried layer dielectric thickness is below 200 um to reduce parasitic capacitance to ground e The transmission line width and spacing to GND must be uniform and routed as smoothly as possible avoid abrupt changes of width and spacing to GND e Add GND vias around transmission line as described in Figure 52 e Ensure solid metal connection of the adjacent metal layer on the PCB stack up to main ground layer providing enough on the adjacent metal layer as described in Figure 52 e Route RF transmission line far from any noise source as switching supplies and digital lines and from any sensitive circuit as analog audio lines e Avoid stubs on the transmission line e Avoid signal routing in parallel to transmission line or crossing the transmission line on buried metal layer e Do not route microstrip line below discrete component or other mechanics placed on top layer Two examples of proper RF circuit design are reported in the Figure 52 where the antenna detection circuit is not implemented if the antenna detection function is required by the application follow the guidelines for circuit and layout implementation reported in section 2 4 2 e n the first example described on the left the ANT pin is directly connected to an SMA connector by means of a proper 50 Q transmission line designed with proper layout e Inthe second example described on the right the ANT pin is connected to an SMA connector b
335. sssssssssssseeeeeem eene 169 Appendix ae S 172 A Migration between LISA and SARA G3 modules eese 172 DWNENO SV SEA 172 AJ Checklist f r IMMIGRATION eas acesseadstes eet te tote e eO eder tees tee ta etu n etu c a ERR sta 173 A3 Softwatemligratilohesssodessd esee atus enact Aled a au mate aec wea ad a une excidat ese futs 174 A4 Hardware mlgratloriz suited o peo Ua v md FIM NUMEN 174 AAT SUpply INGENTA CES creen ineine ka nr thun SR ERa Eaa Dn SEAE d us 174 A 4 2 X System functions interfaces ssssssssssssssssssseeeeeeeeeeeeeee eene enn ene enne 175 A43 Antenna interface i e ttis ilt ecd ie d nta edlen ce sigh suaseedsensns dateaannesaneldvaadhnas 176 A 4 4 SIM nterface eerte Rete qe tee netten dr Decade instet emer Bnet ee denn eh ends 177 BAS Serial interfaces sid eects sock acct sate tp uti ade pen E E Ente eae rubi bd uv tage 177 PAG AUGIO IDEetTaces csset mentita andes etes det th Rd Dat adeft tuu adt lu dd denken 178 A 4 7 ide 178 AUG R s pni d PINS cette cate ott Me PEL e de a O Ue 178 A 4 9 Pin out comparison between LISA and SARA G3 sssssssssssssseeeeeeeeeeeeenenen 179 B Migration between SARA G3 and SARA U2 cccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseeeeeeees 184 MEE UTR 184 B 2 Pin out comparison between SARA G3 and SARA U2 sssssssssssseeeeeeneeneenennn 18
336. st be adapted to the specific production processes e g soldering etc of the customer UBX 13000995 R10 Early Production Information Design in Page 144 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 2 12 Thermal guidelines ee SARA G3 and SARA U2 series module operating temperature range and module thermal resistance are specified in the SARA G3 series Data Sheet 1 or the SARA U2 series Data Sheet 2 The most critical condition concerning module thermal performance is the uplink transmission at maximum power data upload or voice call in connected mode when the baseband processor runs at full speed radio circuits are all active and the RF power amplifier is driven to higher output RF power This scenario is not often encountered in real networks however the application should be correctly designed to cope with it During transmission at maximum RF power the SARA G3 modules generate thermal power that can exceed 1 W whereas the SARA U2 modules generate thermal power that can exceed 2 W these are indicative values since the exact generated power strictly depends on operating condition such as the cellular radio access technology the number of allocated TX slot the transmitting frequency band etc The generated thermal power must be adequately dissipated through the thermal and mechanical design of the application in particular for SARA U2 modules when operating in the 3G cellular radio access technology e
337. stem including PCB layout and matching circuitry o Further to the custom PCB and product restrictions the antenna may require tuning to obtain the required performance for compliance with the applicable certification schemes It is recommended to ask the antenna manufacturer for the design in guidelines related to the custom application UBX 13000995 R10 Early Production Information Design in Page 102 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual In both cases selecting an external or an internal antenna observe these recommendations Select an antenna providing optimal return loss or V S W R figure over all the operating frequencies Select an antenna providing optimal efficiency figure over all the operating frequencies Select an antenna providing appropriate gain figure i e combined antenna directivity and efficiency figure so that the electromagnetic field radiation intensity do not exceed the regulatory limits specified in some countries e g by FCC in the United States as reported in section 4 2 2 e For the additional specific guidelines for SARA G350 ATEX modules integration in potentially explosive atmospheres applications see section 2 14 2 4 1 2 Guidelines for antenna RF interface design Guidelines for ANT pin RF connection design Proper transition between the ANT pin and the application board PCB must be provided implementing the following design in guidelines for the layout of the app
338. such that the potential for human contact during normal operation is minimized This device has been evaluated and shown compliant with the IC RF Exposure limits under mobile exposure conditions antennas are greater than 20 cm from a person s body This device has been certified for use in Canada Status of the listing in the Industry Canada s REL Radio Equipment List can be found at the following web address http www ic gc ca app sitt reltel srch nwRdSrch do lang zeng Additional Canadian information on RF exposure also can be found at the following web address http www ic gc ca eic site smt gst nsf eng sf08792 html IMPORTANT Manufacturers of portable applications incorporating the SARA G310 SARA G350 SARA U260 SARA U280 modules are required to have their final product certified and apply for their own FCC Grant and Industry Canada Certificate related to the specific portable device This is mandatory to meet the SAR requirements for portable devices Changes or modifications not expressly approved by the party responsible for compliance could void the user s authority to operate the equipment Canada avis d Industrie Canada IC Cet appareil num rique de classe B est conforme aux normes canadiennes CAN ICES 3 B NMB 3 B et RSS 210 Son fonctionnement est soumis aux deux conditions suivantes o cet appareil ne doit pas causer d interf rence UBX 13000995 R10 Early Production Information Approvals Page 164 of 192 Qo Ox
339. t as it is by default the DCD module output line is set by default to the OFF state high level at UART initialization The module then sets the DCD line according to the carrier detect status ON if the carrier is detected OFF otherwise For voice calls DCD is set to the ON state when the call is established For a data call there are the following scenarios see the u blox AT Commands Manual 3 for the definition of the interface data mode command mode and online command mode Packet Switched Data call Before activating the PPP protocol data mode a dial up application must provide the ATD 99 lt context_number gt to the module with this command the module switches from command mode to data mode and can accept PPP packets The module sets the DCD line to the ON state then answers with a CONNECT to confirm the ATD 99 command The DCD ON is not related to the context activation but with the data mode Circuit Switched Data call To establish a data call the DTE can send the ATD lt number gt command to the module which sets an outgoing data call to a remote modem or another data module Data can be transparent non reliable or non transparent with the reliable RLP protocol When the remote DCE accepts the data call the module DCD line is set to ON and the CONNECT communication baudrate string is returned by the module At this stage the DTE can send characters through the serial line to the data module which sends them through the
340. t able to provide a long buffering time within few milliseconds the voltage on V_BCKP will go below the valid range 1 V min This has no impact on cellular connectivity as all the module functionalities do not rely on date and time setting 1 5 3 Generic digital interfaces supply output V INT The same 1 8 V voltage domain used internally to supply the generic digital interfaces of SARA G3 and SARA U2 series modules is also available on the V INT supply output pin as described in Figure 16 SARA G3 SARA U2 series Power Baseband Management Processor vcc E Switching Digital O VCC EHI o gt Step Down Interfaces vcc V_INT Figure 16 SARA G3 and SARA U2 series interfaces supply output V_INT simplified block diagram The internal regulator that generates the V_INT supply is a switching step down converter that is directly supplied from VCC The voltage regulator output is set to 1 8 V typical when the module is switched on and it is disabled when the module is switched off The switching regulator operates in Pulse Width Modulation PWM for greater efficiency at high output loads when the module is in active mode or in connected mode When the module is in low power idle mode between paging periods and with power saving configuration enabled by the appropriate AT command it automatically switches to Pulse Frequency Modulation PFM for greater efficiency at low output loads
341. te System General Purpose Input Output General Packet Radio Service Global Positioning System Global System for Mobile Communication Hands free HyperText Transfer Protocol Hypertext Transfer Protocol over Secure Socket Layer Hardware In phase and Quadrature Early Production Information Appendix Page 188 of 192 PCM PCS PFM PMU PSRAM PWM RF RI RTC RTS SAW SDN IN PCN SIM SMS SMTP SPI SRF TBD TCP TDMA TP UART UDP UICC UL UMTS USB UTRA VCO VSWR UBX 13000995 R10 SARA G3 and SARA U2 series System Integration Manual nter Integrated Circuit interface nter IC Sound interface nternet Protocol Leadless Chip Carrier Low Dropout Land Grid Array Low Noise Amplifier Machine to Machine Modulation Coding Scheme Not Applicable Not Available Power Amplifier Pulse Code Modulation Personal Communications Service Pulse Frequency Modulation Power Management Unit Pseudo Static RAM Pulse Width Modulation Radio Frequency Ring Indicator Real Time Clock Request To Send Surface Acoustic Wave Sample Delivery Note Information Note Product Change Notification Subscriber Identification Module Short Message Service Simple Mail Transfer Protocol Serial Peripheral Interface Self Resonant Frequency To Be Defined Transmission Control Protocol Time Division Multiple Access Test Point niversal Asynchronous Receiver Transmitter ser Datagram Protocol niversal Integrate
342. ted Design concept any SARA G3 LISA U1 LISA U2 or LISA C2 module can be mounted on the same nested board as shown in Figure 92 enabling straightforward development of products supporting either GSM GPRS W CDMA or CDMA cellular technology with the same application board ANT pad NESTED APPLICATION BOARD LISA mounting option SARA mounting option Top Layer and Solder Mask with LISA Paste Mask with SARA Paste Mask Figure 92 Nested Design concept description LISA and SARA modules alternatively mounted on the same application board UBX 13000995 R10 Early Production Information Appendix Page 172 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual The voltage level of all the digital interfaces of SARA and LISA modules is 1 8 V this allows the direct connection from a 1 8 V external device e g application processor to all the modules The following sections explain in detail all the points to consider during the migration between LISA and SARA designs implementing or not a nested design For further details regarding SARA G3 and LISA characteristics usage or settings see the related module datasheet 1 4 5 6 System Integration Manual 7 8 and AT commands manual 3 9 A 2 Checklist for migration Have you chosen the optimal SARA G3 module For quad band GSM GPRS full feature set select the SARA G350 module For dual band GSM GPRS full feature set select the SARA G340 module For q
343. ted in the section 2 14 1 must be considered for the implementation of the VCC supply circuit on application integrating SARA G350 ATEX modules intended for use in potentially explosive atmospheres Any specific applicable requirement for the VCC supply circuit design must be fulfilled according to all the exact applicable standards for the apparatus e Check the detailed requisites on the pertinent normatives for the application apparatus as for example the IEC 60079 0 32 IEC 60079 11 33 IEC 60079 26 34 standards 2 14 3 Guidelines for antenna RF interface design The RF output power of the SARA G350 ATEX modules transmitter is compliant to all the applicable 3GPP ETSI standards with a maximum output of 2 W RF pulse power and 1 15 mJ RF pulse energy in 850 900 MHz bands and with a maximum output of 1 W RF pulse power and 0 58 mJ RF pulse energy in the 1800 1900 MHz bands according to the GSM GPRS power classes stated in Table 3 The RF threshold power of the application device integrating a SARA G350 ATEX module is defined according to the IEC 60079 0 ATEX standard 32 as the product of the effective output power of the transmitter the SARA G350 ATEX module multiplied by the antenna gain implemented used on the application device The RF threshold power of the application device integrating a SARA G350 ATEX module transmitter according to the IEC 60079 0 ATEX standard 32 must not exceed the limits shown in Table 58 Gas group
344. terface ANT DET er Antenna detection interface ANT_DET is not supported by SARA G300 and SARA G310 modules 2 4 3 1 Guidelines for ANT DET circuit design Figure 53 and Table 35 describe the recommended schematic and components for the antenna detection circuit to be provided on the application board for the diagnostic circuit that must be provided on the antenna assembly to achieve antenna detection functionality Diagnostic Radiating SARA G340 SARA G350 a ca SARA U2 series ce 2 Zo 50 ohm C4 ANT KT eo Antenna Cable 3 L3 ANT DET oe cno MES H Application Board Antenna Assembly Figure 53 Suggested schematic for antenna detection circuit on application board and diagnostic circuit on antenna assembly Reference Description Part Number Manufacturer C1 27 pF Capacitor Ceramic COG 0402 596 50 V GRM1555C1H270J Murata C2 33 pF Capacitor Ceramic COG 0402 5 50 V GRM1555C1H330J Murata D1 Very Low Capacitance ESD Protection PESD0402 140 Tyco Electronics L1 68 nH Multilayer Inductor 0402 SRF 1 GHz LQG15HS68NJO2 Murata R1 10 kQ Resistor 0402 1 0 063 W RK73H1ETTP1002F KOA Speer J1 SMA Connector 50 Q Through Hole Jack SMA6251A1 3GT50G 50 Amphenol c3 SARA U2 15 pF Capacitor Ceramic COG 0402 5 50V GRM1555C1H150J Murata SARA G3 0 Q jumper 0402 Various Manufacturers L2 SARA U2 39 nH Multilayer
345. tering See the R1 series resistor 2 2 KQ and the C1 bypass capacitor 10 pF Do not place a bypass capacitor directly at the MIC BIAS supply output since proper internal bypass capacitor is already provided to guarantee stable operation of the internal regulator Connect the reference of the microphone circuit to the MIC GND pin of the module as a sense line Provide a proper series capacitor at both MIC P and MIC N analog uplink inputs for DC blocking as the C2 an C3 100 nF Murata GRM155R71C104K capacitors in Figure 76 This provides a high pass filter for the microphone DC bias with proper cut off frequency according to the value of the resistors of the microphone supply circuit Then connect the signal lines to the microphone Provide proper parts on each line connected to the external microphone as noise and EMI improvements to minimize RF coupling and TDMA noise according to the custom application requirements o Mount an 82 nH series inductor with a Self Resonance Frequency 1 GHz e g the Murata LQG15HS82NJO2 on each microphone line L1 and L2 inductors in Figure 76 o Mount a 27 pF bypass capacitor e g Murata GRM1555C1H270J from each microphone line to solid ground plane C4 and C5 capacitors in Figure 76 Use a microphone designed for GSM applications which typically has an internal built in bypass capacitor Connect the SPK P and SPK N analog downlink outputs directly to the receiver speaker which resistance rating must b
346. ternal microphone The pin is internally connected to ground as a sense line as the reference for the analog audio input The analog audio input is selected when the parameter main uplink in AT USPM command is set to Headset microphone Handset microphone or Hands free microphone the uplink analog path profiles use the same physical input but have different sets of audio parameters for more details refer to u blox AT Commands Manual 3 AT USPM AT UMGC AT UUBF AT UHFP commands SARA G3 series Data Sheet 1 provides the detailed electrical characteristics of the analog audio uplink path UBX 13000995 R10 Early Production Information System description Page 56 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 10 1 2 Downlink path SARA G340 SARA G350 pins related to the analog audio downlink path are SPK P SPK N Differential analog audio signal output positive negative These two pins are directly connected internally to the differential output of a low power audio amplifier for which the input is connected internally to the digital processing system by to an integrated digital to analog converter The analog audio output is selected when the parameter main downlink in AT USPM command is set to Normal earpiece Mono headset or Loudspeaker the downlink analog path profiles use the same physical output but have different sets of audio parameters for more details refer to the u blox AT Comman
347. th the EXT32K input pin fed by proper external 32 kHz signal or by 32K_OUT output pin or SARA G340 and SARA G350 modules except 00 versions when registered with the network with power saving disabled the active mode is always held and the receiver and the DSP are periodically activated to monitor the paging channel UBX 13000995 R10 Early Production Information System description Page 26 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Figure 14 roughly describes the current consumption profile of the SARA G300 and SARA G310 modules when their EXT32K input is not fed by a signal i e left unconnected or the SARA G340 and SARA G350 modules 00 versions only or the SARA U2 modules when power saving is disabled the module is registered with the network active mode is maintained and the receiver and the DSP are periodically activated to monitor the paging channel for paging block reception Current mA 100 60 120 mA 50 10 18 mA Time s Paging period 2G case 0 47 2 12 s 3G case 0 64 5 12 s Current mA 100 60 120 mA 50 20 40 mA 10 18 mA 10 18 mA i5i Time ms Enabled Enabled lt gt ACTIVE MODE Figure 14 VCC current consumption profile versus time of the SARA G300 and SARA G310 modules when their EXT32K input is not fed by a signal or the SARA G340 and SARA G350 modules 00 versions only or the SARA U2 modules when registered with the
348. the current parameter settings are not saved in the module s non volatile memory and a proper network detach is not performed ee It is highly recommended to avoid an abrupt hardware shutdown of the module by forcing a low level on the RESET_N input pin during module normal operation the RESET_N line should be set low only if reset or shutdown via AT commands fails or if the module does not reply to a specific AT command after a time period longer than the one defined in the u blox AT Commands Manual 3 An over temperature or an under temperature shutdown occurs on SARA G3 and SARA U2 series modules when the temperature measured within the cellular module reaches the dangerous area if the optional Smart Temperature Supervisor feature is enabled and configured by the dedicated AT command For more details see section 1 13 10 and to the u blox AT Commands Manual 3 USTS AT command ee The Smart Temperature Supervisor feature is not supported by SARA G300 and SARA G310 UBX 13000995 R10 Early Production Information System description Page 33 of 192 4 4 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 6 2 2 Switch off sequence by AT CPWROFF Figure 20 describes the SARA G3 and SARA U2 series modules power off sequence properly started sending the AT CPWROFF command allowing storage of current parameter settings in the module s non volatile memory and a proper network detach with the following phases e When th
349. the customer s total cost of ownership SARA U2 series include variants supporting band combination for North America and band combination for Europe Asia and other countries For each combination a complete UMTS GSM variant and a cost saving UMTS only variant are available All SARA U2 series modules provide a rich feature set including an extensive set of internet protocols dual stack IPv4 IPv6 and access to u blox GNSS positioning chips and modules with embedded A GPS AssistNow Online and AssistNow Offline functionality Table 1 describes a summary of interfaces and features provided by SARA G3 and SARA U2 series modules Module Data rate Bands Interfaces Audio Functions ea a uo E Sei 5 54 g p28 e v Sila 2 sys eoesrt Fe S FZ2E ce S 5 9 F mg sso2crcle 52 B r S z 8 cx I CcOSEHSEFCEA SHE segoh 2 ERES SE z z SoostesFeFrnAgA SERVE gle E m Soocta o ovonvo2z uwWtit5tv5t Bx 3 2 3 2 E O B3SsSHdezseS 2955552sfM 3 3 3 S S S kK e S ow g E 5 9 m E wi zZ 5 qam ey V od 2 A 2 a a a t moVvVOnegResL ESSER SI5 SKS m cli deep ae 4 SgES855882x amp xs amp amp to20SzuS3ka8 SARA G300 42 8 85 6 900 1800 2 E SARA G310 42 8 85 6 4 band 2 E SARA G340 42 8 85 6 900 1800 2 ZI 1 o o o o e o o o o o SARA G350 42 8 85 6 4 band 2 41 1e e o e e F o o e o o o SARA G350 ATEX 42 8 85 6 4 band 2 4 1 1 e o o o o e o o o o o o SARA U260 5 76 7 2 85 6 236 8 850 1900 850 1900 1 1 9 F 1 o o o o o o o o o SARA U270 5
350. the generic digital pins of the modules are tri stated until the switch on of their supply source V INT any external signal connected to the generic digital pins must be tri stated or set low at least until the activation of the V INT supply output to avoid latch up of circuits and allow a proper boot of the module The V INT generic digital interfaces supply output is enabled by the integrated power management unit The RESET N line of SARA G3 series rise suddenly to high logic level due to internal pull up to V INT The internal reset signal is held low by the integrated power management unit the baseband processor core and all the digital pins of the modules are held in reset state When the internal reset signal is released by the integrated power management unit the processor core starts to configure the digital pins of the modules to each default operational state The duration of this pins configuration phase differs within generic digital interfaces 3 s typical and the USB interface due to specific host device enumeration timings 5 s typical see section 1 9 3 The host application processor should not send any AT command over the AT interfaces USB UART of the modules until the end of this interfaces configuration phase to allow a proper boot of the module After the interfaces configuration phase the application can start sending AT commands and the following starting procedure is suggested to check the effective comple
351. tion Manual Registry value 0x00 0x2F 0x00 0x3C 0x00 0x35 0x00 0x3D 0x00 0x0A 0x00 0x09 0x00 0x04 0x00 0x05 0x00 0x8C 0x00 0x8D 0x00 0x8B 0x00 0x94 0x00 0x95 0x00 0x93 Ox00 0xAE 0x00 0xAF 0x00 0xB6 0x00 0xB7 Not supported by SARA G3 modules UBX 13000995 R10 SARA U series YES N OoOO00 0 z lt lt rn rm MIN zzz Zz OOOOcOocO0o0o000 Early Production Information SARA G series YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES System description Page 71 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 13 10 Smart temperature management Se Not supported by SARA G300 and SARA G310 modules Cellular modules independent of the specific model always have a well defined operating temperature range This range should be respected to guarantee full device functionality and long life span Nevertheless there are environmental conditions that can affect operating temperature e g if the device is located near a heating cooling source if there is is not air circulating etc The module itself can also influence the environmental conditions such as when it is transmitting at full power In this case its temperature increases very quickly and can raise the temperature nearby The best solution is always to properly design the system where the module is integrated Nevertheless an extra check security mechanism embedded into the
352. tion circuit using the SIM DET pin of SARA U2 modules is implemented as shown in the section 2 5 and if the related SIM card detection and SIM hot insertion removal functions are enabled by AT commands for more details see u blox AT Commands Manual 3 UGPIOC UDCONF 50 AT commands Upon SAP deactivation the SARA U2 modules perform a detach operation from the remote SIM followed by an attach operation to the local one if present UBX 13000995 R10 Early Production Information System description Page 80 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 13 17 Power saving The power saving configuration is by default disabled but it can be enabled using the AT UPSV command When power saving is enabled the module automatically enters the low power idle mode whenever possible reducing current consumption During low power idle mode the module is not ready to communicate with an external device by means of the application interfaces since it is configured to reduce power consumption It can be woken up from idle mode to active mode by the connected application processor by the connected u blox positioning receiver or by network activities as described in Table 6 During idle mode the module processor core runs with the RTC 32 kHz reference clock which is generated by The internal 32 kHz oscillator in case of SARA G340 SARA G350 and SARA U2 modules The 32 kHz signal provided at the EXT32K input pin in
353. tion of subsequent characters is guaranteed until the module is in active mode If the HW flow control is disabled AT amp KO it is recommended to enable the power saving in one of these ways AT UPSV 2 the module automatically enters the low power idle mode whenever possible and the UART interface is enabled by the RTS line as described in section 1 9 1 4 reaching very low current consumption With this configuration when the module is in idle mode the UART is re enabled 20 ms after RTS has been set ON and the recognition of subsequent characters is guaranteed until the module is in active mode AT UPSV 3 the module automatically enters the low power idle mode whenever possible and the UART interface is enabled by the DTR line as described in section 1 9 1 4 reaching very low current consumption With this configuration not supported only by SARA G3 modules when the module is in idle mode the UART is re enabled 20 ms after DTR has been set ON and the recognition of subsequent characters is guaranteed until the module is in active mode Providing the TXD RXD RTS and CTS lines only not using the complete V 24 link If the functionality of the DSR DCD RI and DTR lines is not required in or the lines are not available Connect the module DTR input line to GND since the module requires DTR active low electrical level Leave DSR DCD and RI lines of the module unconnected and floating If RS 232 compatible signal levels are need
354. tion of the module internal boot sequence send AT and wait for the response with a 30 s timeout iterate it 4 times without resetting or removing the VCC supply of the module and then run the application Start up Start of interface Module interfaces event configuration are configured VCC V_BCKP PWR ON SARA U2 RESET N V INT SARA G3 RESET N Internal Reset System State Internal Reset Internal Reset gt Operational Operational Figure 18 SARA G3 and SARA U2 series power on sequence from not powered mode ee The Internal Reset signal is not available on a module pin but the application can monitor the V_INT pin to sense the start of the power on sequence Se Before the switch on of the generic digital interface supply source V_INT of the module no voltage driven by an external application should be applied to any generic digital interface of the modules UBX 13000995 R10 Early Production Information System description Page 31 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 6 1 3 Switch on sequence from power off mode Figure 19 shows the modules power on sequence from the power off mode describing the following phases e SARA U2 RESET N SARA G3 RESET N The external supply is still applied to the VCC inputs as it is assumed that the module has been previously switched off by means of the AT CPWROFF command the V BCKP output is internally enabled as pr
355. tional difference o functional difference o functional difference o functional difference No functional difference No functional difference No functional difference No functional difference No functional difference No functional difference Analog audio not supported Analog audio not supported Analog audio not supported Analog audio not supported Analog audio not supported Analog audio not supported No functional difference No functional difference No functional difference related section in the section 1 whereas for detailed design in see the related section in the chapter 2 For the detailed electrical characteristics of each interface of SARA G3 and SARA U2 series modules see the SARA G3 series Data Sheet 1 and the SARA U2 series Data Sheet 2 UBX 13000995 R10 Early Production Information Appendix Page 186 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual B 3 Schematic for SARA G3 and SARA U2 integration Figure 95 shows an example of schematic diagram where a SARA G3 or SARA U2 series module can be integrated into the same application board using all the available interfaces and functions of the modules The different mounting options for the external parts are highlighted in different colors as described in the legend according to the interfaces supported by the relative modules SARA G3 SARA U2 OQ for SARA G3 modules n
356. tput SIM data SIM clock SIM reset detection PIO Cu UART data output UART data input UART clear to send output UART ready to send input UART data set ready output UART ring indicator output UART data terminal ready inpu UART data carrier detect output Early Production Information Remarks VSIM 1 80 V typ or 2 85 V typ automatically generated according to the connected SIM type See section 1 8 for functional description See section 2 5 for external circuit design in Data input output for 1 8 V 3 V SI Internal 4 7 kQ pull up to VSIM See section 1 8 for functional description See section 2 5 for external circuit design in 3 25 MHz clock output for 1 8 V 3 V SI See section 1 8 for functional description See section 2 5 for external circuit design in Reset output for 1 8 V 3 V SIM See section 1 8 for functional description See section 2 5 for external circuit design in 1 8 V input for SIM presence detection function Pin configurable also as GPIO on SARA U2 series See section 1 8 2 for functional description See section 2 5 for external circuit design in 1 8 V output Circuit 104 RXD in ITU T V 24 for AT data FOAT on SARA G3 series modules for AT data FOAT FW upgrade via EasyFlash tool and diagnostic on SARA U2 series modules See section 1 9 1 for functional description See section 2 6 1 for external circuit design i
357. tput are not available on SARA G340 and SARA G350 modules since the internal oscillator generates the 32 kHz RTC reference clock Se ESD sensitivity rating of the EXT32K input pin and the 32K_OUT output pin is 1 kV Human Body Model according to JESD22 A114 Higher protection level can be required if the line is externally accessible on the application board Higher protection level can be achieved by mounting an ESD protection e g EPCOS CAO5PAS14THSG varistor array close to accessible point Se If the customer application does not require the low power idle mode and the RTC functions the EXT32K input pin and the 32K OUT output pin can be left not connected 2 3 3 2 Guidelines for EXT32K and 32K OUT layout design The EXT32K input pin and the 32K OUT output pin require accurate layout design avoid injecting noise on these pins as it may affect the stability of the RTC timing reference UBX 13000995 R10 Early Production Information Design in Page 101 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 2 4 Antenna interface The ANT pin provided by all the SARA G3 and SARA U2 series modules represents the RF input output used to transmit and receive the 2G 3G RF cellular signals the antenna must be connected to this pin The ANT pin has a nominal characteristic impedance of 50 Q and must be connected to the antenna through a 50 Q transmission line to allow transmission and reception of radio frequency RF signals i
358. uad band GSM GPRS reduced feature set select the SARA G310 module For dual band GSM GPRS reduced feature set select the SARA G300 module KEBS Check SARA G3 modules hardware requirements W Check power capabilities of the external supply circuit SARA G3 modules require large current pulses in connected mode as well as LISA U series modules when a 2G call is enabled LISA C2 series modules do not require large current pulses due to the CDMA channel access technology Check supported bands for proper antenna circuit development SARA G3 modules frequency ranges are within LISA U modules ranges but LISA C2 modules range is quite different Check antenna detection requirements SARA G340 and SARA G350 modules provide the antenna detection function implementing an external application circuit between ANT_DET and ANT pins Check the module power on requirements Table 59 and relative section summarize differences between SARA G3 and LISA modules Check the module requirements to enter low power idle mode SARA G300 and SARA G310 modules require a 32 kHz signal at EXT32K input which for example can be provided by the 32K_OUT output Check serial interfaces requirements SARA G3 modules provide UART interface for AT command data communication multiplexer functionality FW upgrade over AT and provide auxiliary UART interface for FW upgrade using the u blox EasyFlash tool and for diagnostic purpose W Check analog audio requirements SARA G3
359. uidelines for ANT DET layout design Figure 54 describes the recommended layout for the antenna detection circuit to be provided on the application board to achieve antenna detection functionality implementing the recommended schematic described in the previous Figure 53 and Table 35 SARA G340 SARA G350 SARA U2 series module ERI Ml E c eT CLIE ALICE LIE I dud Figure 54 Suggested layout for antenna detection circuit on application board The antenna detection circuit layout suggested in Figure 54 is here explained The ANT pin is connected to the antenna connector by means of a 50 O transmission line implementing the design guidelines described in section 2 4 1 and the recommendations of the SMA connector manufacturer DC blocking capacitor at the ANT pin C2 is placed in series to the 50 Q transmission line The ANT DET pin is connected to the 50 Q transmission line by means of a sense line Choke inductor in series at the ANT DET pin L1 is placed so that one pad is on the 50 O transmission line and the other pad represents the start of the sense line to the ANT DET pin The additional components R1 C1 and D1 on the ANT DET line are placed as ESD protection The additional high pass filter C3 and L2 on the ANT line are placed as ESD immunity improvement for SARA U2 modules a series 0 O jumper can be mounted for SARA G340 and SARA G350 modules instead of the high pass filter as no further precaution to ESD i
360. ure 9 VCC current consumption profile versus time during a GPRS multi slot class 12 connection 4 TX slots 1 RX slot For detailed current consumption values during 2G single slot or multi slot connection see SARA G3 series Data Sheet 1 and SARA U2 series Data Sheet 2 UBX 13000995 R10 Early Production Information System description Page 22 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 5 1 3 VCC current consumption in 3G connected mode During a 3G connection the SARA U2 modules can transmit and receive continuously due to the Frequency Division Duplex FDD mode of operation with the Wideband Code Division Multiple Access WCDMA The current consumption depends again on output RF power which is always regulated by network commands These power control commands are logically divided into a slot of 666 ys thus the rate of power change can reach a maximum rate of 1 5 kHz There are no high current peaks as in the 2G connection since transmission and reception are continuously enabled due to FDD WCDMA implemented in the 3G that differs from the TDMA implemented in the 2G case In the worst scenario corresponding to a continuous transmission and reception at maximum RF output power approximately 250 mW or 24 dBm the average current drawn by the module at the VCC pins is high see the SARA U2 series Data Sheet 2 Even at lowest RF output power level approximately 0 01 uW or 50 dBm the average current
361. uthentication Algorithm RCA DES 3DES AES128 AES256 Table 16 Encryption Algorithm MD5 SHA SHA1 SHA256 SHA384 Table 17 Message digest UBX 13000995 R10 SARA U series NO YES YES NO NO SARA U series YES NO SARA U series YES NO NO YES NO SARA U series YES YES NO NO Early Production Information SARA G series NO NO YES NO NO SARA G series YES YES SARA G series YES YES YES YES YES SARA G series YES YES YES YES System description Page 70 of 192 VP biox Description TLS_RSA_WITH_AES_128_CBC_SHA TLS_RSA_WITH_AES_128_CBC_SHA256 TLS_RSA_WITH_AES_256_CBC_SHA TLS_RSA_WITH_AES_256_CBC_SHA256 TLS_RSA_WITH_3DES_EDE_CBC_SHA TLS_RSA_WITH_DES_CBC_SHA TLS_RSA_WITH_RC4_128_MD5 TLS_RSA_WITH_RC4_128_SHA TLS_PSK_WITH_AES_128_CBC_SHA TLS_PSK_WITH_AES_256_CBC_SHA TLS_PSK_WITH_3DES_EDE_CBC_SHA TLS RSA PSK WITH AES 128 CBC SHA TLS RSA PSK WITH AES 256 CBC SHA TLS RSA PSK WITH 3DES EDE CBC SHA TLS PSK WITH AES 128 CBC SHA256 TLS PSK WITH AES 256 CBC SHA384 TLS RSA PSK WITH AES 128 CBC SHA256 TLS RSA PSK WITH AES 256 CBC SHA384 Table 18 TLS cipher suite registry 1 13 9 Dual stack IPvA IPv6 CS SARA U2 modules support both Internet Protocol version 4 and Internet Protocol version 6 For more details about dual stack IPvA IPv6 see the u blox AT Commands Manual 3 SARA G3 and SARA U2 series System Integra
362. valent parameters must be considered in gas sub divisions IIB IIA Ui242V li 2 5 A burst Pi 2 5W Ci 103 pF Li 2 4 1 uH Primary and secondary cells and batteries Cells and batteries incorporated into equipment with intrinsic safety i protection to potentially explosive gas atmosphere shall conform to the requirements of the IEC 60079 0 32 and IEC 60079 11 ATEX standards 33 Shunt voltage limiters For Level of Protection ia the application of controllable semiconductor components as shunt voltage limiting devices for example transistors thyristors voltage current regulators etc may be permitted if both the input and output circuits are intrinsically safe circuits or where it can be shown that they cannot be subjected to transients from the power supply network In circuits complying with the above two devices are considered to be an infallible assembly For Level of Protection ia three independent active voltage limitation semiconductor circuits may be used in associated apparatus provided the transient conditions of the clause 7 5 1 of IEC 60079 11 standard are met These circuits shall also be tested in accordance with the clause 10 1 5 3 of the IEC 60079 11 standard 33 UBX 13000995 R10 Early Production Information Design in Page 151 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual Series current limiters The use of three series blocking diodes in circuits of Level of Protection
363. wer dissipation UBX 13000995 R10 Early Production Information Design in Page 90 of 192 Qo Ox SARA G3 and SARA U2 series System Integration Manual Li lon Li Polymer Battery Charger IC SARA G3 SARA U2 5V USB oe Supply VIN Vout vcc Vinsns Vosns e e o o o o o VCC Li lon Li Pol MODE Vs Battery Pack vec ISEL L LE 4 tw R1 C3 R4 C4 n lusB lac TH e e R3 e END C5 C6 C7 C8 C9 m TPRG E e SD GND X B1 MEN GND C1 C2 D1 D2 U1 EE Figure 41 Li lon or Li Polymer battery charging application circuit Reference Description Part Number Manufacturer B1 Li lon or Li Polymer battery pack with 470 Q NTC Various manufacturer C1 C4 uF Capacitor Ceramic X7R 0603 10 16 V GRM188R71C105KA12 Murata C2 C6 O nF Capacitor Ceramic X7R 0402 10 16 V GRM155R71C103KA01 Murata C3 nF Capacitor Ceramic X7R 0402 1096 50 V GRM155R71H102KA01 Murata C5 330 pF Capacitor Tantalum D SIZE 6 3 V 45 mQ T520D337MO006ATEO045 KEMET C7 00 nF Capacitor Ceramic X7R 0402 1096 16 V GRM155R61A104KA01 Murata C8 56 pF Capacitor Ceramic COG 0402 596 25 V GRM1555C1E560JA01 Murata C9 5 pF Capacitor Ceramic COG 0402 596 25 V GRM1555C1E150JA01 Murata D1 D2 Low Capacitance E
364. which can also be handled by other external circuits or by the cellular module GPIO according to the application requirements The dual SIM connection circuit described in Figure 58 can be implemented for SIM chips as well providing proper connection between SIM switch and SIM chip as described in Figure 56 If it is required to switch between more than two SIMs a circuit similar to the one described in Figure 58 can be implemented for example in case of four SIM circuit using a proper 4 pole 4 throw switch or alternatively four 1 pole 4 throw switches instead of the suggested 4 pole 2 throw switch Follow these guidelines connecting the module to two SIM connectors Use a proper low on resistance i e few ohms and low on capacitance i e few pF 2 throw analog switch e g Fairchild F5A2567 as SIM switch to ensure high speed data transfer according to SIM requirements Connect the contacts C1 VCC and C6 VPP of the two UICC SIM to the VSIM pin of the module by means of a proper 2 throw analog switch e g Fairchild F5A2567 Connect the contact C7 I O of the two UICC SIM to the SIM IO pin of the module by means of a proper 2 throw analog switch e g Fairchild FSA2567 Connect the contact C3 CLK of the two UICC SIM to the SIM CLK pin of the module by means of a proper 2 throw analog switch e g Fairchild F5A2567 Connect the contact C2 RST of the two UICC SIM to the SIM RST pin of the module by means of a proper 2 thr
365. y see the u blox web site http Awww u blox com 4 1 Product certification approval overview Product certification approval is the process of certifying that a product has passed all tests and criteria required by specifications typically called certification schemes that can be divided into three distinct categories Regulatory certification o Country specific approval required by local government in most regions and countries as CE Conformit Europ enne marking for European Union FCC Federal Communications Commission approval for United States Industry certification o Telecom industry specific approval verifying the interoperability between devices and networks GCF Global Certification Forum partnership between European device manufacturers and network operators to ensure and verify global interoperability between devices and networks PTCRB PCS Type Certification Review Board created by United States network operators to ensure and verify interoperability between devices and North America networks Operator certification o Operator specific approval required by some mobile network operator as AT amp T network operator in United States Even if the SARA G3 and SARA U2 series modules are approved under all major certification schemes the application device that integrates the modules must be approved under all the certification schemes required by the specific application device to be deployed in the market
366. y all SARA G3 and SARA U2 series except SARA G300 and SARA G310 1 8 2 SIM card detection interface SIM DET Se Not supported by SARA G300 00S and SARA G310 00S modules The SIM_DET pin is configured as an external interrupt to detect the SIM card mechanical physical presence The pin is configured as input with an internal active pull down enabled and it can sense SIM card presence only if properly connected to the mechanical switch of a SIM card holder as described in section 2 5 Low logic level at SIM_DET input pin is recognized as SIM card not present High logic level at SIM_DET input pin is recognized as SIM card present The SIM card detection function provided by SIM_DET pin is an optional feature that can be implemented used or not according to the application requirements an Unsolicited Result Code URC is generated each time that there is a change of status for more details see the u blox AT Commands Manual 3 simind value of the descr parameter of the CIND and CMER commands The optional function SIM card hot insertion removal can be additionally enabled on the SARA U2 modules SIM DET pin by AT commands see section 1 11 and u blox AT Commands Manual 3 UGPIOC UDCONF UBX 13000995 R10 Early Production Information System description Page 38 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual 1 9 Serial interfaces SARA G3 and SARA U2 series modules provide the following serial c
367. y exclusive The usage of a regulator or a battery not able to support the highest peak of VCC current consumption specified in the SARA G3 series Data Sheet 1 and in the SARA U2 series Data Sheet 2 is generally not recommended However if the selected regulator or battery is not able to support the highest peak current of the module it must be able to support at least the highest averaged current consumption value specified in the SARA G3 series Data Sheet 1 and in the SARA U2 series Data Sheet 2 The additional energy required by the module during a 2G Tx slot can be provided by an appropriate bypass tank capacitor or supercapacitor with very large capacitance and very low ESR placed close to the module VCC pins Depending on the actual capability of the selected regulator or battery the required capacitance can be considerably larger than 1 mF and the required ESR can be in the range of few tens of mQ Carefully evaluate the implementation of this solution since aging and temperature conditions significantly affect the actual capacitor characteristics The following sections highlight some design aspects for each of the supplies listed above providing application circuit design in compliant with the module VCC requirements summarized in Table 7 ee For the additional specific guidelines for SARA G350 ATEX modules integration in potentially explosive atmospheres applications refer to section 2 14 2 2 1 2 Guidelines for VCC supply circuit
368. y means of a proper 50 Q transmission line designed with proper layout with an additional high pass filter consisting of a proper series capacitor and a proper shunt inductor to improve the ESD immunity at the antenna port of SARA U2 modules as described in section 2 13 a series O Q jumper can be mounted for SARA G3 modules instead of the high pass filter as no further precaution to ESD immunity test is needed SARA module SARA module OQ High pass filter for SARA U2 ANT port SMA ESD immunity increase SMA connector S connector Figure 52 Suggested circuit and layout for antenna RF circuit on application board if antenna detection is not required UBX 13000995 R10 Early Production Information Design in Page 105 of 192 Qo ox SARA G3 and SARA U2 series System Integration Manual Guidelines for RF termination design The RF termination must provide a characteristic impedance of 50 Q as well as the RF transmission line up to the RF termination itself to match the characteristic impedance of the ANT pin of the module However real antennas do not have perfect 50 Q load on all the supported frequency bands Therefore to reduce as much as possible performance degradation due to antenna mismatch the RF termination must provide optimal return loss or V S W R figure over all the operating frequencies as summarized in Table 10 If an external antenna is used the antenna connector represents the RF termination on the PCB
369. yp charges as a linear charger the battery in three phases Pre charge constant current active when the battery is deeply discharged the battery is charged with a low current set to 10 of the fast charge current Fast charge constant current the battery is charged with the maximum current configured by the value of an external resistor to a value suitable for USB power source 500 mA Constant voltage when the battery voltage reaches the regulated output voltage 4 2 V the L6924U starts to reduce the current until the charge termination is done The charging process ends when the charging current reaches the value configured by an external resistor to 15 mA or when the charging timer reaches the value configured by an external capacitor to 9800 s Using a battery pack with an internal NTC resistor the L6924U can monitor the battery temperature to protect the battery from operating under unsafe thermal conditions The L6924U as linear charger is more suitable for applications where the charging source has a relatively low nominal voltage 5 V so that a switching charger is suggested for applications where the charging source has a relatively high nominal voltage e g 12 V refer to the following section 2 2 1 8 for specific design in even if the L6924U can also charge from an AC wall adapter as its input voltage range is tolerant up to 12 V when a current limited adapter is used it can operate in quasi pulse mode reducing po

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