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UM10524 LPC1315/16/17/45/46/47 User manual

1. 181 11 5 11 _HID_DESCRIPTOR _HID_DESCRIPTOR_ 11 5 33 USBD_HID_INITPARAM 182 ee 161 445 84 USBD HW APIs 232eu seeder dak vs 188 11 5 12 JID REPORT OM o an anaana 161 11 5 35 USBD MSC API 005 197 11 5 13 MSC_CBW 0 00000 162 11 5 36 USBD MSC_INIT_PARAM 198 Chapter 12 LPC1315 16 17 45 46 47 USART 12 1 How to read this chapter 203 12 5 3 USART Divisor Latch LSB and MSB Registers 12 2 Basic configuration 00 203 when DLAB 1 fete te eens 206 12 3 Features 0 0 0 0 ccc cece cece cece anes 203 12 5 4 pel ee Enable Register when e 12 4 Pin dESCripH OT siinne nie aes aaa 203 12 5 5 USART Interrupt Identification Register Read 12 5 Register description 204 o E E cae eee 207 12 5 1 USART Receiver Buffer Register when 12 5 6 USART FIFO Control Register Write Only 209 DLAB 0 Read Only 205 12 5 7 USART Line Control Register 210 12 5 2 USART Transmitter Holding Register when 12 5 8 USART Modem Control Register 211 DLAB 0 Write Only 055 205 12 5 8 1 Auto flow control 00 0eee 212 12 5 8 1 1 Auto RTS 0000 0020 eee eee 212 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 400 of 404 NXP Semiconductors UM10524 Cha
2. e Mass Storage Class MSC function driver Mass Storage Class function driver initialization parameter data structure Table 201 MSC class API functions structure This module exposes functions which interact directly with the USB device controller hardware Table 200 11 4 Calling the USB device driver UM10524 A fixed location in ROM contains a pointer to the ROM driver table i e Ox1FFF 1FF8 The ROM driver table contains a pointer to the USB driver table Pointers to the various USB driver functions are stored in this table USB driver functions can be called by using a C structure Figure 15 illustrates the pointer mechanism used to access the on chip USB driver typedef struct USBD_API const USBD_HW_API_T hw const USBD_CORE_API_T core const USBD_MSC_API_T msc const USBD_DFU_API_T dfu const USBD_HID_API_T hid const USBD_CDC_API_T cdc All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 157 of 404 NXP Semiconductors UM10524 Chapter 11 LPC1345 46 47 USB on chip drivers const uint32_t reserved6 const uint32_t version USBD_API_T 0x1 FFF 1FF8 Ox1 FFF 1FFC 0x1 FFF 2000 0x1 FFF 2004 gt Ptr to USB ROM Driver table 0x1 FFF 1FF8 ROM Driver Table Ptr to USB Driver Table Ptr to Device Table 1 Ptr to Device Table 2 Ptr t
3. 149 DLAB 0 Write Only THR address Table 166 __WORD_BYTE class structure 158 0x4000 8000 bit description 205 Table 167 BM_T class structure 159 Table 206 USART Divisor Latch LSB Register when Table 168 DLAB 1 DLL address 0x4000 8000 bit _CDC_ABSTRACT_CONTROL_MANAGEMENT description 00 cece eee eee 206 _DESCRIPTOR class structure 159 Table 207 USART Divisor Latch MSB Register when Table 169 CDC CALL_MANAGEMENT_DESCRIPTOR DLAB 1 DLM address 0x4000 8004 bit class structure 0 e eee eee 159 COSCIPUON i e eke ee eee eee 206 Table 170 CDC HEADER _DESCRIPTOR class Table 208 USART Interrupt Enable Register when SUCTUS iee ai u Wend een als Rte 2 159 DLAB 0 IER address 0x4000 8004 bit Table 171 CDC LINE CODING class structure 160 Gescription cg ecw ss sae eee ver DERSTE 206 Table 172 CDC_UNION_1SLAVE_DESCRIPTOR class Table 209 USART Interrupt Identification Register Read SUUCCUIC aiina i cen ond aoe ee ee ee w 160 only IIR address 0x4004 8008 bit Table 173 CDC UNION DESCRIPTOR class description 0 0c e ee eee 207 SUUCTULC ini tides dimer baked hale be Soe 160 Table 210 USART Interrupt Handling 208 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 392 of 404 NXP Semiconductors
4. 314 co 0 0 0 sesa ee eee eee 321 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 402 of 404 NXP Semiconductors UM10524 Chapter 23 Supplementary information 16 8 Example timer operation 322 16 9 Archit ct re aonana eaaa 323 Chapter 17 LPC1315 16 17 45 46 47 Windowed Watchdog Timer WWDT 17 1 How to read this chapter 325 17 7 3 Changing the WWDT reload value 328 17 2 Basic configuration 0005 325 17 8 Register description 005 329 17 3 Features 0 0 00 cece eee eee eee 325 17 8 1 Watchdog mode register 329 17 4 Applications 000eeees 326 Wish Cue a register ee wp 8 atchdog Feed register ie 1 pa m ee ae 17 8 4 Watchdog Timer Value register 332 A A eerste ea mre Seman 17 8 5 Watchdog Clock Select register 332 17 6 Clocking and power control 327 17 8 6 Watchdog Timer Warning Interrupt register 332 17 7 Using the WWDT lock features 328 17 8 7 Watchdog Timer Window register 333 17 7 1 Accidental overwrite of the WWDT clock 328 17 9 Watchdog timing examples 333 17 7 2 Changing the WWDT clock source 328 Chapter 18 LPC1315 16 17 45 46 47 System tick timer 18 1 How to read this c
5. 349 20 2 Basic configuration 345 20 5 5 A D Status Register STAT 350 20 3 Features 2 0 cccceeeeeeeeeeeees 345 2096 AD HMSO IIe TANM ionik 350 20 4 Pindescription 0000eeees 345 20 6 Operation de guatinawatie 351 20 5 Register description 346 20 6 1 Hardware triggered conversion 351 20 5 1 A D Control Reaister CR 347 20 6 2 INTOMUPIS 2a moca eee Png Vinee ears 351 Qno megia Joor erkedesedi 20 6 3 Accuracy vs digital receiver 351 20 5 2 A D Global Data Register GDR 348 20 6 4 Optional operating modes 351 20 5 3 A D Interrupt Enable Register INTEN 349 Da aia a ee E Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming firmware 21 1 How to read this chapter 353 21 7 Criterion for Valid User Code 355 21 2 Bootloader 0 0c eee eee eee 353 21 8ISP IAP communication protocol 356 213 Featdres vised cenciivad nant denen O08 353 21 8 1 ISP command format 356 24 4 Description ecec eee eee eee 354 a apis format 005 8 ata format 2 220 ele Memon TAR E reset ees 354 21 8 4 ISP flow control 0 0000 356 21 6 Flash content protection mechanism 354 21 8 5 ISP commandabort 0000 356 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012
6. Bits 31 8 and bit 0 of the mask registers are unused and should not be written to These bits will always read back as zeros When an address match interrupt occurs the processor will have to read the data register DAT to determine what the received address was that actually caused the match Table 256 I2C Mask registers MASK 0 1 2 3 0x4000 00 30 34 38 3C bit description Bit Symbol Description Reset value 0 Reserved User software should not write ones to reserved 0 bits This bit reads always back as 0 7 1 MASK Mask bits 0x00 31 8 Reserved The value read from reserved bits is undefined 0 14 8 I C operating modes UM10524 14 8 1 In a given application the I2C block may operate as a master a slave or both In the slave mode the I2C hardware looks for any one of its four slave addresses and the General Call address If one of these addresses is detected an interrupt is requested If the processor wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave operation is not interrupted If bus arbitration is lost in the master mode the 12C block switches to the slave mode immediately and can detect its own slave address in the same serial transfer Master Transmitter mode In this mode data is transmitted from master to slave Before the master transmitter mode can be entered the CONSET register must be initialized as sh
7. 331 Table 304 Watchdog Feed register FEED 0x4000 4008 bit description 0 ee eee 332 Table 305 Watchdog Timer Value register TV 0x4000 400C bit description 332 Table 306 Watchdog Clock Select register CLKSEL 0x4000 4010 bit description 332 Table 307 Watchdog Timer Warning Interrupt register WARNINT 0x4000 4014 bit description 333 Table 308 Watchdog Timer Window register WINDOW 0x4000 4018 bit description 333 Table 309 Register overview SysTick timer base address 0xE000 E000 005 337 Table 310 SysTick Timer Control and status register SYST_CSR 0xE000 E010 bit description 337 Table 311 System Timer Reload value register SYST_RVR OxE000 E014 bit description 338 Table 312 System Timer Current value register SYST_CVR OxE000 E018 bit description 338 Table 313 System Timer Calibration value register SYST_CALIB OxE000 E01C bit COSCIPUON sse eeee a pete ends ee ees 338 Table 314 Register overview Repetitive Interrupt Timer RIT base address 0x4006 4000 341 Table 315 RI Compare Value LSB register COMPVAL address 0x4006 4000 bit description 342 Table 316 RI Mask LSB register MASK address 0x4006 NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 394 of 404 NXP Semiconductors UM10524 4004 bit descrip
8. Toggle on match Do nothing on match For each timer up to four match registers can be configured as PWM allowing to use up to three match outputs as single edge controlled PWM outputs All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 310 of 404 NXP Semiconductors U M1 0524 Chapter 16 LPC1315 16 17 45 46 47 32 bit counter timers CT32B0 1 16 4 Applications e Interval timer for counting internal events e Pulse Width Demodulator via capture input e Free running timer e Pulse Width Modulator via match outputs 16 5 General description Each Counter timer is designed to count cycles of the peripheral clock PCLK or an externally supplied clock and can optionally generate interrupts or perform other actions at specified timer values based on four match registers Each counter timer also includes one capture input to trap the timer value when an input signal transitions optionally generating an interrupt In PWM mode three match registers can be used to provide a single edge controlled PWM output on the match output pins One match register is used to control the PWM cycle length 16 6 Pin description Table 284 gives a brief summary of each of the counter timer related pins Table 284 Counter timer pin description Pin Type Description CT32B0_CAP 1 0 Input Capture Signals CT32B1_CAP 1
9. Toggle on match Do nothing on match For each timer up to four match registers can be configured as PWM allowing to use up to two match outputs as single edge controlled PWM outputs All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 295 of 404 NXP Semiconductors U M1 0524 Chapter 15 LPC1315 16 17 45 46 47 16 bit counter timers CT16B0 1 15 4 Applications e Interval timer for counting internal events e Pulse Width Demodulator via capture input e Free running timer e Pulse Width Modulator via match outputs 15 5 Description Each Counter timer is designed to count cycles of the peripheral clock PCLK or an externally supplied clock and can optionally generate interrupts or perform other actions at specified timer values based on four match registers Each counter timer also includes one capture input to trap the timer value when an input signal transitions optionally generating an interrupt In PWM mode two match registers can be used to provide a single edge controlled PWM output on the match output pins It is recommended to use the match registers that are not pinned out to control the PWM cycle length Remark The 16 bit counter timer0 CT16BO0 and the 16 bit counter timer1 CT16B1 are functionally identical except for the peripheral base address 15 6 Pin description Table 268 gives
10. All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 175 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 194 USBD_CORE_API class structure Member SetupStage DatalnStage DataOutStage UM10524 Description void void USBD_CORE_API SetupStage USBD_HANDLE_T hUsb Function to set EPO state machine in setup state This function is called by USB stack and the application layer to set the EPO state machine in setup state This function will read the setup packet received from USB host into stack s buffer Remark This interface is provided to users to invoke this function in other scenarios which are not handle by current stack In most user applications this function is not called directly Also this function can be used by users who are selectively modifying the USB device stack s standard handlers through callback interface exposed by the stack Parameters 1 hUsb Handle to the USB device stack Returns Nothing void void USBD_CORE_API DataInStage USBD_HANDLE_T hUsb Function to set EPO state machine in data_in state This function is called by USB stack and the application layer to set the EPO state machine in data_in state This function will write the data present in EPOData buffer to EPO FIFO for transmission to host Remark This interface is provided to
11. 2 cece cece eeeeee 382 ARE Ar E pocanaineee 369 Signature generation 0 382 21 13 14 ReadUID 00cccec eee eee 370 SSE AOD etic og ays senses ee 21 13 15 ISP Return Codes 370 Chapter 22 LPC1315 16 17 45 46 47 Serial Wire Debugger SWD 22 1 How to read this chapter 384 22 5 Pin description 00 eee eee 384 22 2 Features 0 cece eee ees 384 22 6 Functional description 385 22 3 Introduction 020000eeeeeeae 384 22 6 1 Debug limitations 385 22 44 Description 0 0ceseeeeeees 384 22 6 2 Debug connections forSWD 385 22 6 3 Boundary scan 0 e eee eee 386 Chapter 23 Supplementary information 23 1 Abbreviations 5 387 23 3 Vales rice ens otc eer eee teen 389 23 2 Legal information 00000es 388 23 4 FiQ ureS cece cee eee 396 23 2 1 Definitions 222000005 388 23 5 ContentS 00 cece eee eee eee 397 23 2 2 Disclaimers 0000002 ee e i 388 23 2 3 Trademarks 00020220 ee eee 388 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2012 For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of releas
12. Event for USB interface reset This event fires when the USB host requests that the device reset its interface This event fires after the control endpoint has been automatically configured by the library Remark This event is called from USB_ISR context and hence is time critical Having delays in this callback will prevent the device from enumerating correctly or operate properly USB_Suspend_Event USB_CB_TUSB_CB_T USBD_API_INIT_PARAM USB_Suspend_Event UM10524 Event for USB suspend This event fires when the USB host suspends the device by halting its transmission of Start Of Frame pulses to the device This is generally hooked in order to move the device over to a low power state until the host wakes up the device Remark This event is called from USB_ISR context and hence is time critical Having delays in this callback will cause other system issues All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 167 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 191 USBD_API_INIT_PARAM class structure Member USB_Resume_Event reserved_sbz USB_SOF_Event USB_WakeUpCfg USB_Power_Event USB_Error_Event UM10524 Description USB_CB_TUSB_CB_T USBD_API_INIT_PARAM USB_Resume_Event Event for USB wake up or resume This event fires when a the USB device interface is
13. define IAP_LOCATION Oxlffflffl Define data structure or pointers to pass IAP command table and result table to the IAP function unsigned long command 5 unsigned long result 4 or unsigned long command unsigned long result command unsigned long 0x result unsigned long 0x All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 371 of 404 NXP Semiconductors U M1 0524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming Define pointer to function type which takes two parameters and returns void Note the IAP returns the result with the base address of the table residing in R1 typedef void IAP unsigned int unsigned int IAP iap_entry Setting function pointer iap_entry IAP IAP_LOCATION Whenever you wish to call IAP you could use the following statement iap_entry command result As per the ARM specification The ARM Thumb Procedure Call Standard SWS ESPC 0002 A 05 up to 4 parameters can be passed in the rO r1 r2 and r3 registers respectively Additional parameters are passed on the stack Up to 4 parameters can be returned in the rO r1 r2 and r3 registers respectively Additional parameters are returned indirectly via memory Some of the IAP calls require more than 4 parameters If the ARM suggested scheme is used for the parameter passing returning then it mig
14. 381 FMSW1 register FMSW1 address 0x4003 C030 bit description 381 FMSW2 register FMSW2 address 0x4003 C034 bit description 381 FMSWS register FMSW3 address 0x4003 40C8 bit description 381 Flash module status register FMSTAT 0x4003 CFEO bit description 381 Flash module status clear register FMSTATCLR 0x0x4003 CFE8 bit description 382 Serial Wire Debug pin description 385 JTAG boundary scan pin description 385 Abbreviations 000 eee eee 387 NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 395 of 404 NXP Semiconductors UM10524 23 4 Figures Chapter 23 Supplementary information Fig 1 Block diagram 0 eee eee eee 7 Fig 46 Recovering from a bus obstruction caused by a Fig 2 LPC1315 16 17 45 46 47 memory map 10 LOW level on SDA 0 0 02 ee eee 286 Fig 3 LPC1315 16 17 45 46 47 CGU block diagram 12 Fig 47 Sample PWM waveforms with a PWM cycle length Fig4 Start up timing 0c eee ee eee 35 of 100 selected by MR3 and MAT3 0 enabled as Fig5 System PLL block diagram 42 PWM outputs by the PWCON register 307 Fig 6 Power profiles pointer structure 49 Fig 48 A timer cycle in which PR 2 MRx 6 and both Fig 7 Power profiles usage 005 54 interrupt and
15. Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x3 to 0x7 are reserved 0 0x0 PIOO_21 0x1 CT16B1_MATO 0x2 MOSI1 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 82 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 77 I O configuration for pin PlIOO_21 CT16B1_MAT0 MOSI1 PIO0_21 address 0x4004 4054 bit description Bit Symbol Value Description Reset value 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 23 I O configuration for pin PIOO_22 Table 78 I O configuration for pin PlOO_22 AD6 CT16B1_MAT1 MISO1 PIOO_22 address 0x4004 4058 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x4 to 0x7 are reserved 0 0x0 PIOO_22 0x1
16. NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 318 of 404 NXP Semiconductors U M1 0524 Chapter 16 LPC1315 16 17 45 46 47 32 bit counter timers CT32B0 1 Table 296 External Match Register EMR address 0x4001 403C CT32B0 and 0x4001 803C CT32B1 bit description Bit Symbol Value Description Reset value 0x3 Toggle the corresponding External Match bit output 9 8 EMC2 External Match Control 2 Determines the functionality of External Match 2 00 0x0 Do Nothing 0x1 Clear the corresponding External Match bit output to 0 CT32Bi_MAT2 pin is LOW if pinned out 0x2 Set the corresponding External Match bit output to 1 CT32Bi_MAT2 pin is HIGH if pinned out 0x3 Toggle the corresponding External Match bit output 11 10 EMC3 External Match Control 3 Determines the functionality of External Match 3 00 0x0 Do Nothing 0x1 Clear the corresponding External Match bit output to 0 CT32Bi_MATS3 pin is LOW if pinned out 0x2 Set the corresponding External Match bit output to 1 CT32Bi_MATS3 pin is HIGH if pinned out 0x3 Toggle the corresponding External Match bit output 31 12 Reserved user software should not write ones to reserved bits The value read from a NA reserved bit is not defined Table 297 External match control EMR 11 10 EMR 9 8 Function EMR 7 6 or EMR 5 4 UM10524 00 Do Nothing 01 Clear the corresponding External Match bit output to 0 CT32Bn_MATm pin i
17. NXP Semiconductors U M1 0524 Chapter 22 LPC1315 16 17 45 46 47 Serial Wire Debugger SWD Table 378 Serial Wire Debug pin description Pin Name Type Description SWCLK Input Serial Wire Clock This pin is the clock for SWD debug logic when in the Serial Wire Debug mode SWD This pin is pulled up internally SWDIO Input Serial wire debug data input output The SWDIO pin is used by an Output external debug tool to communicate with and control the LPC1315 16 17 45 46 47 This pin is pulled up internally SWO Output Serial Wire Output The SWO pin optionally provides data from the ITM and or the ETM for an external debug tool to evaluate Table 379 JTAG boundary scan pin description Pin Name Type Description TCK Input JTAG Test Clock This pin is the clock for JTAG boundary scan when the RESET pin is LOW TMS Input JTAG Test Mode Select The TMS pin selects the next state in the TAP state machine This pin includes an internal pull up and is used for JTAG boundary scan when the RESET pin is LOW TDI Input JTAG Test Data In This is the serial data input for the shift register This pin includes an internal pull up and is used for JTAG boundary scan when the RESET pin is LOW TDO Output JTAG Test Data Output This is the serial data output from the shift register Data is shifted out of the device on the negative edge of the TCK signal This pin is used for JTAG boundary scan when the RESET pin is LOW TRST
18. RESET T T COMPARE COMPARE_H gt PBUS register registers PBUS PBUS gt CLR MASK MASK_H L registers Fig 60 Repetitive Interrupt Timer RI Timer block diagram 19 5 Register description Table 314 Register overview Repetitive Interrupt Timer RIT base address 0x4006 4000 Name Access Address Description Reset value Reference COMPVAL R W 0x000 Compare value LSB register Holds the 32 LSBs of the OxFFFFFFFF Table 315 compare value MASK R W 0x004 Mask LSB register This register holds the 32 LSBs of 0 Table 316 the mask value A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register CTRL R W 0x008 Control register OxC Table 317 COUNTER R W 0x00C Counter LSB register 32 LSBs of the counter 0 Table 318 COMPVAL_H R W 0x010 Compare value MSB register Holds the 16 MSBs of OxOOOO FFFF Table 315 the compare value MASK_H R W 0x014 Mask MSB register This register holds the 16 MSBs of 0 Table 316 the mask value A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register COUNTER_H R W 0x018 Counter MSB register 16 MSBs of the counter 0 Table 318 1 Reset Value reflects the data stored in used bits only It does not include content of reserved bits UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved
19. All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 259 of 404 NXP Semiconductors U M1 0524 UM10524 14 7 7 1 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller Table 253 I12C Monitor mode control register MMCTRL 0x4000 001C bit description Bit Symbol Value Description Reset value 0 MM_ENA Monitor mode enable 0 0 Monitor mode disabled 1 The 12C module will enter monitor mode In this mode the SDA output will be forced high This will prevent the 12C module from outputting data of any kind including ACK onto the 12C data bus Depending on the state of the ENA_SCL bit the output may be also forced high preventing the module from having control over the 12C clock line 1 ENA_SCL SCL output enable 0 0 When this bit is cleared to 0 the SCL output will be forced high when the module is in monitor mode As described above this will prevent the module from having any control over the I C clock line 1 When this bit is set the 12C module may exercise the same control over the clock line that it would in normal operation This means that acting as a slave peripheral the 12C module can stretch the clock line hold it low until it has had time to respond to an 12C interrupt 2 MATCH_ALL Select interrupt register match 0 0 When this bit is cleared an interrupt will only be generated
20. Break Interrupt When RXD1 is held in the spacing state all 0 zeros for one full character transmission start data parity stop a break interrupt occurs Once the break condition has been detected the receiver goes idle until RXD1 goes to marking state all ones A LSR read clears this status bit The time of break detection is dependent on FCR O Note The break interrupt is associated with the character at the top of the USART RBR FIFO Break interrupt status is inactive Break interrupt status is active Transmitter Holding Register Empty THRE is set immediately 1 upon detection of an empty USART THR and is cleared on a THR write THR contains valid data THR is empty Transmitter Empty TEMT is set when both THR and TSR are 1 empty TEMT is cleared when either the TSR or the THR contain valid data THR and or the TSR contains valid data THR and the TSR are empty Error in RX FIFO LSR 7 is set when a character with a RX 0 error such as framing error parity error or break interrupt is loaded into the RBR This bit is cleared when the LSR register is read and there are no subsequent errors in the USART FIFO RBR contains no USART RX errors or FCR 0 0 USART RBR contains at least one USART RX error Tx Error In smart card T 0 operation this bit is set when the 0 smart card has NACKed a transmitted character one more than the number of times indicated by the TXRETRY field Reserved A UM10524 All
21. CT16B0 1 are available on all LPC 1315 16 17 45 46 47 parts The following pins are available on the LQFP64 package only CT16B0_CAP1 CT16B1_CAP1 CT32B1_CAP1 The following pin is available on the LQFP64 and LQFP48 packages only CT32B0_CAP1 15 2 Basic configuration 15 3 Features The CT16B0 1 counter timers are configured through the following registers Pins The CT16B0 1 pins must be configured in the IOCON register block Power In the SYSAHBCLKCTRL register set bit 7 and 8 in Table 19 The peripheral clock is determined by the system clock Table 18 UM10524 Two 16 bit counter timers with a programmable 16 bit prescaler Counter or timer operation Two 16 bit capture channels that can take a snapshot of the timer value when an input signal transitions A capture event may also optionally generate an interrupt The timer and prescaler may be configured to be cleared on a designated capture event This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge Four 16 bit match registers that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Two external outputs corresponding to match registers with the following capabilities Set LOW on match Set HIGH on match
22. CT16B1 bit description 303 Table 280 External Match Register EMR address 0x4000 C03C CT16B0 and 0x4001 003C CT16B1 bit description 0 0 ee eee eee 303 Table 281 External match control 304 Table 282 Count Control Register CTCR address 0x4000 C070 CT16B0 and 0x4001 0070 CT16B1 bit description strecis eae ees eee 305 Table 283 PWM Control Register PWMC address 0x4000 C074 and 0x4001 0074 CT16B1 bit description w225 cee te eee be ee eee 306 Table 284 Counter timer pin description 311 Table 285 Register overview 32 bit counter timer 0 CT32B0 base address 0x4001 4000 Table 286 Register overview 32 bit counter timer 1 CT32B1 base address 0x4001 8000 Table 287 Interrupt Register IR address 0x4001 4000 CT32B0 and IR address 0x4001 8000 bit description 0 eee eee 314 Table 288 Timer Control Register TCR address 0x4001 4004 CT32B0 and 0x4001 8004 CT32B1 bit description 314 Table 289 Timer counter registers TC address 0x4001 4008 CT32B0 and 0x4001 8008 CT32B1 bit description 314 Table 290 Prescale registers PR address 0x4001 400C CT32B0 and 0x4001 800C CT32B1 bit description ss sace saoi aulua pinia kanie 315 Table 291 Prescale registers PC address 0x4001 4010 UM10524 All information provided in this document is subject to legal disclaimers Chapter 23 Supplementary informat
23. I2C interrupt routine Determine the 12C state and which state routine will be used to handle it 1 Read the I C status from STA 2 Use the status value to branch to one of 26 possible state routines Non mode specific states State 0x00 Bus Error Enter not addressed Slave mode and release bus 1 Write 0x14 to CONSET to set the STO and AA bits 2 Write 0x08 to CONCLR to clear the SI flag 3 Exit Master States State 08 and State 10 are for both Master Transmit and Master Receive modes The R W bit decides whether the next state is within Master Transmit mode or Master Receive mode State 0x08 A START condition has been transmitted The Slave Address R W bit will be transmitted an ACK bit will be received 1 Write Slave Address with R W bit to DAT 2 Write 0x04 to CONSET to set the AA bit 3 Write 0x08 to CONCLR to clear the SI flag 4 Set up Master Transmit mode data buffer All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 288 of 404 NXP Semiconductors U M1 0524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller 5 Set up Master Receive mode data buffer 6 Initialize Master data counter 7 Exit 14 11 5 4 State 0x10 14 11 6 14 11 6 1 14 11 6 2 14 11 6 3 UM10524 A Repeated START condition has been transmitted The Slave Address R W bit will be transmitted an ACK bit
24. NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 21 of 404 NXP Semiconductors U M1 0524 UM10524 3 5 15 3 5 16 Chapter 3 LPC1315 16 17 45 46 47 System control block Table 19 System clock control SYSAHBCLKCTRL address 0x4004 8080 bit description Bit Symbol Value Description Reset value 18 SSP1 Enables clock for SSP1 0 0 Disable 1 Enable 19 PINT Enables clock to GPIO Pin interrupts register 0 interface 0 Disable 1 Enable 22 20 Reserved 23 GROUPOINT Enables clock to GPIO GROUPO interrupt register 0 interface 0 Disable 1 Enable 24 GROUP1INT Enables clock to GPIO GROUP1 interrupt register 0 interface 0 Disable 1 Enable 25 g Reserved 26 RAM1 Enables clock for SRAM1 located at 0x2000 0000 1 to 0x2000 0800 0 Disable 1 Enable 27 USBSRAM Enables USB SRAM block located at 0x2000 4000 0 to 0x2000 4800 0 Disable 1 Enable 31 28 z Reserved SSP0 clock divider register SSPOCLKDIV This register configures the SSPO peripheral clock SPIO_PCLK SPIO_PCLK can be shut down by setting the DIV field to zero Table 20 SSP0O clock divider SSPOCLKDIV address 0x4004 8094 bit description Bit Symbol Description Reset value 7 0 DIV SPIO_PCLK clock divider values 0 0 System clock disabled 1 Divide by 1 to 255 Divide by 255 31 8 Reserved gt UART clock divider register UARTCLKDIV This register configures the USART peripheral clock UART_PCLK The
25. 364 21 14 12 Read EEPROM 377 21 13 38 Echo lt setting gt 00 00 cece ee 364 21 14 13 IAP Status Codes 0 378 21 13 4 Write to RAM lt start address gt 21 15 Debug notes cc eee eee eee 378 lt number of bytes gt 0000 364 21 15 1 Comparing flash images 378 21 13 5 Read Memory lt address gt lt no of bytes gt 365 21 15 2 Serial Wire Debug SWD flash programming 21 13 6 Prepare sector s for write operation lt start sector interface 2 oe ccc cece ccc cecccceeeee 378 number gt lt end sector number gt 365 24 46 Flash controller registers 379 21 13 7 COPY RAM to flash lt Flas hiaddress lt RAM 21 16 1 Flash memory access register 379 address gt cfo Of DYESS i Pay siasa 306 21 16 2 Flash signature generation 379 21 13 8 Go lt address gt lt mode gt 367 21 16 3 Signature generation address and control 21 13 9 Erase sector s lt start sector number gt lt end VEJISTOIS oii eide ee paren aaa 380 rrr Baek cone poe nie aoe 368 51 16 4 Signature generation result registers 380 eo sector numbers 368 21 16 5 Flash module status register oe 381 21 13 11 Read Part Identification number ee 368 21 16 6 Flash module status clear register 381 ete Gna hgh tyes Ee 21 16 7 Algorithm and procedure for signature 21 13 12 Read Boot code version number 369 generation
26. Bit 7 6 5 4 3 2 1 0 Symbol I2EN STA STO Sl AA Value 1 0 0 0 1 I2EN must be set to 1 to enable the 12C function AA bit must be set to 1 to acknowledge its own slave address or the General Call address The STA STO and SI bits are set to 0 After ADR and CONSET are initialized the 12C interface waits until it is addressed by its own address or general address followed by the data direction bit If the direction bit is 0 W it enters slave receiver mode If the direction bit is 1 R it enters slave transmitter mode After the address and direction bit have been received the SI bit is set and a valid status code can be read from the Status register STAT Refer to Table 265 for the status codes and actions All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 264 of 404 NXP Semiconductors U M1 0524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller n bytes data received A Acknowledge SDA low A Not acknowledge SDA high S START condition P STOP condition Sr Repeated START condition E from Master to Slave O from Slave to Master Fig 35 Format of Slave Receiver mode 14 8 4 Slave Transmitter mode The first byte is received and handled as in the slave receiver mode However in this mode the direction bit will be 1 indicating a read operation Serial data is trans
27. Chapter 11 LPC1345 46 47 USB on chip drivers Table 194 USBD_CORE_API class structure Member RegisterClassHandler RegisterEpHandler UM10524 Description ErrorCode_t ErrorCode_t USBD_CORE_API RegisterClassHandler USBD_HANDLE_T hUsb USB_EP_HANDLER_T pfn void data Function to register class specific EPO event handler with USB device stack The application layer uses this function when it has to register the custom class s EPO handler The stack calls all the registered class handlers on any EPO event before going through default handling of the event This gives the class handlers to implement class specific request handlers and also to override the default stack handling for a particular event targeted to the interface Check USB_EP_HANDLER_T for more details on how the callback function should be implemented Also application layer could use this function to register EPO handler which responds to vendor specific requests hUsbHandle to the USB device stack pfnClass specific EPO handler function dataPointer to the data which will be passed when callback function is called by the stack Parameters 1 hUsb Handle to the USB device stack 2 pfn Class specific EPO handler function 3 data Pointer to the data which will be passed when callback function is called by the stack Returns Returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_TOO_MANY_CLAS
28. ErrorCode_t USBD_HID_INIT_PARAM HID_Ep0_Hdlr USBD_HANDLE_T hUsb void data uint32_t event USBD_HANDLE_T hUsb void data uint32_t event Optional user overridable function to replace the default HID class handler The application software could override the default EPO class handler with their own by providing the handler function address as this data member of the parameter structure Application which like the default handler should set this data member to zero before calling the USBD_HID_API Init Remark Parameters 1 hUsb Handle to the USB device stack 2 data Pointer to the data which will be passed when callback function is called by the stack 3 event Type of endpoint event See USBD_EVENT_T for more details Returns The call back should returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_ xxx For other error conditions 11 5 34 USBD_HW_API Hardware API functions structure This module exposes functions which interact directly with USB device controller hardware UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 188 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 199 USBD_HW_API class structure Member Descripti
29. No STDAT action or No STDAT action 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 Oo Next action taken by I2C hardware Switched to not addressed SLV mode no recognition of own SLA or General call address Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if ADR 0 logic 1 Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if ADR 0 logic 1 A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode no recognition of own SLA or General call address Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if ADR 0 logic 1 Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if ADR 0 logic 1 A START condition will be transmitted when the bus becomes free UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 279 of 404 NXP Semi
30. Symbol FUNC MODE HYS Value Description 0x0 0x1 0x2 0x0 0x1 0x2 0x3 All information provided in this document is subject to legal disclaimers Selects pin function Values 0x3 to 0x7 are reserved PIO1_16 RI CT16BO_CAPO Selects function mode on chip pull up pull down resistor control Inactive no pull down pull up resistor enabled Pull down resistor enabled Pull up resistor enabled Repeater mode Hysteresis Disable Enable Reset value 0 0x2 NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 94 of 404 NXP Semiconductors U M1 0524 7 4 39 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 93 I O configuration for pin PIO1_16 RI CT16B0_CAP0 PIO1_16 address 0x4004 40A0 bit description Bit Symbol Value Description Reset value 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 I O configuration for PIO1_17 Table 94 I O configuration for PlIO1_17 CT16B0_CAP1 RXD P1IO1_17 address 0x4004 40A4 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x3 to 0x7 are reserved 0 0x0 PIO1_1
31. Table 291 Prescale registers PC address 0x4001 4010 CT32B0 and 0x4001 8010 CT32B1 bit description Bit Symbol Description Reset value 31 0 PC Prescale counter value 0 Match Control Register The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter The function of each of the bits is shown in Table 292 Table 292 Match Control Register MCR address 0x4001 4014 CT32B0 and 0x4001 8014 CT32B1 bit description Bit Symbol Value Description Reset value 0 MROI Interrupt on MRO an interrupt is generated when MRO matches the value in the TC 0 1 Enabled 0 Disabled 1 MROR Reset on MRO the TC will be reset if MRO matches it 0 1 Enabled 0 Disabled 2 MROS Stop on MRO the TC and PC will be stopped and TCR O will be set to 0 if MRO matches 0 the TC 1 Enabled 0 Disabled 3 MR11 Interrupt on MR1 an interrupt is generated when MR1 matches the value in the TC 0 1 Enabled 0 Disabled UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 315 of 404 NXP Semiconductors U M1 0524 Chapter 16 LPC1315 16 17 45 46 47 32 bit counter timers CT32B0 1 Table 292 Match Control Register MCR address 0x4001 4014 CT32B0 and 0x4001 8014 CT32B1 bit description Bit Symbol Value Description Reset value 4 MR1R Reset on MR1 the TC will be
32. USART Line Status Register Read Only 3 For details see Section 12 5 1 USART Receiver Buffer Register when DLAB 0 Read Only 4 For details see Section 12 5 5 USART Interrupt Identification Register Read Only and Section 12 5 2 USART Transmitter Holding Register when DLAB 0 Write Only The USART THRE interrupt IIR 3 1 001 is a third level interrupt and is activated when the USART THR FIFO is empty provided certain initialization conditions have been met These initialization conditions are intended to give the USART THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start up The initialization conditions implement a one character delay minus the stop bit whenever THRE 1 and there have not been at least two characters in the THR at one time since the last THRE 1 event This delay is provided to give the CPU time to write data to THR without a THRE interrupt to decode and service A THRE interrupt is set immediately if the USART THR FIFO has held two or more characters at one time and currently the THR is empty The THRE interrupt is reset when a THR write occurs or a read of the IIR occurs and the THRE is the highest interrupt IIR 3 1 001 The modem status interrupt IIR3 1 000 is the lowest priority USART interrupt and is activated whenever there is a state change on the CTS DCD or DSR or a trailing edge on the RI pin The source of the
33. User manual Rev 1 17 February 2012 341 of 404 NXP Semiconductors U M1 0524 UM10524 19 5 1 19 5 2 19 5 3 Chapter 19 LPC1315 16 17 45 46 47 Repetitive Interrupt Timer RI RI Compare Value LSB register Table 315 RI Compare Value LSB register COMPVAL address 0x4006 4000 bit description Bit Symbol Description Reset value 31 0 RICOMP Compare register Holds the 32 LSBs of the compare value OxFFFF FFFF which is compared to the counter RI Mask LSB register Table 316 RI Mask LSB register MASK address 0x4006 4004 bit description Bit Symbol Description Reset value 31 0 RIMASK Mask register This register holds the 32 LSBs of the mask value A 0 one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register causes the comparison of the register bits to be always true RI Control register Table 317 RI Control register CTRL address 0x4006 4008 bit description Bit Symbol Value Description Reset value 0 RITINT Interrupt flag 0 1 This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers Writing a 1 to this bit will clear it to 0 Writing a 0 has no effect 0 The counter value does not equal the masked compare value 1 RITENCLR Timer enable clear 1 The timer will be cleared to 0 whenever the counter value 0 equals the mas
34. e Program one IOCON register to enable a USART TXD function e f the smart card to be communicated with requires a clock program one IOCON register for the USART SCLK function The USART will use it as an output e Program UARTCLKDIV Table 21 for an initial USART frequency of 3 58 MHz e Program the OSR Section 12 5 15 for 372x oversampling e If necessary program the DLM and DLL Section 12 5 3 to 00 and 01 respectively to pass the USART clock through without division e Program the LCR Section 12 5 7 for 8 bit characters parity enabled even parity e Program the GPIO signals associated with the smart card so that in this order a Reset is low b VCC is provided to the card GPIO pins do not have the required 200 mA drive c VPP if provided to the card is at idle state e Program SCICTRL Section 12 5 18 to enable the smart card feature with the desired options e Set up one or more timer s to provide timing as needed for ISO 7816 startup e Program SYSAHBCLKCTRL Table 19 to enable the USART clock Thereafter software should monitor card insertion handle activation wait for answer to reset as described in ISO7816 3 12 7 Architecture The architecture of the USART is shown below in the block diagram The APB interface provides a communications link between the CPU or host and the USART The USART receiver block RX monitors the serial input line RXD for valid input The USART RX Shift Reg
35. l CT32B0_CAP0 Capture input 0 for 32 bit timer 0 VO SCLK Serial clock input output for USART in synchronous mode PIO0_18 RXD 61 46 31 B PU I O PIO0_18 General purpose digital input output pin CT32B0_MATO I RXD Receiver input for USART Used in UART ISP mode O CT32B0_MAT0 Match output 0 for 32 bit timer 0 PIO0_19 TXD 62 47 32 Bl IPU VO PIO0_19 General purpose digital input output pin CT32B0_MAT1 O TXD Transmitter output for USART Used in UART ISP mode O CT32B0_MAT1 Match output 1 for 32 bit timer 0 PIOO_20 CT16B1_CAPO 11 9 7 B IPU O PIO0_20 General purpose digital input output pin l CT16B1_CAP0 Capture input 0 for 16 bit timer 1 PIOO_21 CT16B1_MATO 22 17 12 1 PU lO PIO0_21 General purpose digital input output pin MOSI CT16B1_MATO0 Match output 0 for 16 bit timer 1 1 0 MOSI1 Master Out Slave In for SSP1 PIOO_22 AD6 40 30 20 amp 1 PU O PIO0_22 General purpose digital input output pin CT16B1_MAT1 MISO1 l AD6 A D converter input 6 O CT16B1_MAT1 Match output 1 for 16 bit timer 1 1 0 MISO1 Master In Slave Out for SSP1 PIO0_23 AD7 56 42 27 6 PU VO PIO0_23 General purpose digital input output pin l AD7 A D converter input 7 PIO1_0 CT32B1_MATO 1 5 E BI PU I O PIO1_0 General purpose digital input output pin O CT32B1_MAT0 Match output 0 for 32 bit timer 1 PIO1_1 CT32B1_MAT1 17 z BI PU VO PIO
36. logic 1 A START condition will be transmitted when the bus becomes free 0xC8 Last data byte in DAT No DAT actionor 0 0 0 0 Switched to not addressed SLV mode no has been transmitted recognition of own SLA or General call AA 0 ACK has address been received No DAT action or 0 0 0 1 Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if ADR 0 logic 1 No DAT action or 1 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free No DAT action 1 0 0 01 Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if ADR O logic 1 A START condition will be transmitted when the bus becomes free UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 282 of 404 NXP Semiconductors U M1 0524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller acknowledged Master and last data byte I2CON 0 reception of the own Slave address and l one or more Data DATA A PORS bytes all are I arbitration lost as Io gt 1 A l addressed as Slave transmitted Switched to Not Addressed ALL ONES PORS Slave AA bit in Fig 43 Format and states in the Slave Transmitter mode from Master to Sla
37. n UM10524 BUS LPC1315 16 17 45 46 47 User manual Rev 1 17 February 2012 User manual Document information Info Content Keywords LPC1315 16 17 45 46 47 ARM Cortex M3 microcontroller USB Abstract LPC1315 16 17 45 46 47 User manual NXP Semiconductors U M1 0524 LPC1315 16 17 45 46 47 User manual Revision history Rev Date Description 1 20120217 Initial version Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 2 of 404 UM10524 Chapter 1 LPC1315 16 17 45 46 47 Introductory information Rev 1 17 February 2012 User manual 1 1 Introduction The LPC1315 16 17 45 46 47 are ARM Cortex M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption The ARM Cortex M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration The LPC1315 1 6 17 45 46 47 operate at CPU frequencies of up to 72 MHz The ARM Cortex M3 CPU incorporates a 3 stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third
38. this field as soon after reset as possible 0 5 MHz 0 8 MHz 1 1 MHz 1 4 MHz 1 6 MHz 1 8 MHz 2 0 MHz 2 2 MHz 2 4 MHz 2 6 MHz 2 7 MHz 2 9 MHz 3 1 MHz 3 2 MHz 3 4 MHz Reserved System reset status register SYSRSTSTAT If another reset signal for example the external RESET pin remains asserted after the POR signal is negated then its bit is set to detected Table 14 System reset status register SYSRSTSTAT address 0x4004 8030 bit description Bit Symbol Value 0 POR 0 1 1 EXTRST 0 1 2 WDT 0 1 3 BOD 0 Description POR reset status No POR detected POR detected Status of the external RESET pin No reset event detected Reset detected Status of the Watchdog reset No WDT reset detected WDT reset detected Status of the Brown out detect reset No BOD reset detected BOD reset detected All information provided in this document is subject to legal disclaimers Reset value 0 NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 18 of 404 NXP Semiconductors U M1 0524 UM10524 3 5 10 3 5 11 3 5 12 Chapter 3 LPC1315 16 17 45 46 47 System control block Table 14 System reset status register SYSRSTSTAT address 0x4004 8030 bit description Bit Symbol Value Description Reset value 4 SYSRST Status of the software system reset 0 0 No System reset detected 1 System reset detected 31 5 Reserved System PLL clock source s
39. 1 Enable rising edge or level interrupt 31 8 Reserved Pin interrupt level rising edge interrupt set register For each of the 8 pin interrupts selected in the PINTSEL registers see Table 35 one bit in the SIENR register sets the corresponding bit in the IENR register depending on the pin interrupt mode configured in the PINTMODE register e lf the pin interrupt mode is edge sensitive PMODE 0 the rising edge interrupt is set e lf the pin interrupt mode is level sensitive PMODE 1 the level interrupt is set Table 117 Pin interrupt level rising edge interrupt set register SIENR address 0x4004 C008 bit description Bit Symbol Description Reset Access value 7 0 SETENRL Ones written to this address set bits in the PINTEN_R NA WO thus enabling interrupts Bit n sets bit n in the PINTEN_R register 0 No operation 1 Enable rising edge or level interrupt 31 8 Reserved All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 122 of 404 NXP Semiconductors U M1 0524 UM10524 9 5 1 4 9 5 1 5 9 5 1 6 Chapter 9 LPC1315 16 17 45 46 47 GPIO Pin interrupt level rising edge interrupt clear register For each of the 8 pin interrupts selected in the PINTSEL registers see Table 35 one bit in the CIENR register clears the corresponding bit in the IENR register depending o
40. 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_ xxx For other error conditions UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 202 of 404 UM10524 Chapter 12 LPC1315 16 17 45 46 47 USART Rev 1 17 February 2012 User manual 12 1 How to read this chapter The USART controller is available on all LPC1315 16 17 45 46 47 parts 12 2 Basic configuration 12 3 Features The USART is configured as follows The USART block is enabled through the SYSAHBCLKCTRL register see Table 19 The peripheral USART clock PCLK which is used by the USART baud rate generator is controlled by the UARTCLKDIV register see Table 21 16 byte receive and transmit FIFOs Register locations conform to 550 industry standard Receiver FIFO trigger points at 1 4 8 and 14 bytes Built in baud rate generator Software or hardware flow control RS 485 EIA 485 9 bit mode support with output enable RTS CTS flow control and other modem control signals 1X clock send or receive ISO 7816 3 compliant smart card interface IrDA support 12 4 Pin description UM10524 Some of the following pins are not available in some packages Table 202 USART pin description Pin Type Description RXD Input Serial Input Serial r
41. 175 Table 158 USB Endpoint Buffer in use EPINUSE address Table 195 USBD_DFU_API class structure 178 0x4008 0018 bit description 144 Table 196 USBD_DFU_INIT_PARAM class structure 179 Table 159 USB Endpoint Buffer Configuration EPBUFCFG Table 197 USBD_HID_API class structure 182 address 0x4008 001C bit description 144 Table 198 USBD_HID_INIT_PARAM class structure 183 Table 160 USB interrupt status register INTSTAT address Table 199 USBD_HW_API class structure 189 0x4008 0020 bit description 145 Table 200 USBD_MSC_API class structure 198 Table 161 USB interrupt enable register INTEN address Table 201 USBD_MSC_INIT_PARAM class structure 199 0x4008 0024 bit description 146 Table 202 USART pin description 203 Table 162 USB set interrupt status register INTSETSTAT Table 203 Register overview USART base address address 0x4008 0028 bit description 147 0x4000 8000 2 0 000 204 Table 163 USB interrupt routing register INTROUTING Table 204 USART Receiver Buffer Register when address 0x4008 002C bit description 147 DLAB 0 Read Only RBR address Table 164 USB Endpoint toggle EPTOGGLE address 0x4000 8000 bit description 205 0x4008 0034 bit description 147 Table 205 USART Transmitter Holding Register when Table 165 Endpoint commands
42. 21 UM10524 Value Description Reset Value Selects which of the AD7 0 pins is are to be sampled and converted Bit 0 selects 0x00 Pin ADO bit 1 selects pin AD1 and bit 7 selects pin AD7 In software controlled mode BURST 0 only one channel can be selected i e only one of these bits should be 1 In hardware scan mode BURST 1 any numbers of channels can be selected i e any or all bits can be set to 1 If all bits are set to 0 channel 0 is selected automatically SEL 0x01 The main clock PCLK_ADC is divided by this value plus one to produce the clock 0 for the A D converter The clock should be less than or equal to 15 5 MHz 12 bit mode or 31 MHz 10 bit mode in software controlled mode BURST bit 0 Typically software should program the smallest value in this field that yields aclock of 15 5 MHZ or slightly less but in certain cases such as a high impedance analog source a slower clock may be desirable Burst mode 0 Remark If BURST is set to 1 the ADGINTEN bit in the INTEN register Table 326 must be set to 0 Software controlled mode Conversions are software controlled and require 31 clocks Hardware scan mode The AD converter does repeated conversions at the rate selected by the CLKS field scanning if necessary through the pins selected by ones in the SEL field The first conversion after the start corresponds to the least significant bit set to 1 in the SEL field then the n
43. 21 2 Bootloader 21 3 Features The bootloader controls initial operation after reset and also provides the means to program the flash memory This could be initial programming of a blank device erasure and re programming of a previously programmed device or programming of the flash memory by the application program in a running system The bootloader version can be read by ISP IAP calls see Section 21 13 12 or Section 21 14 6 UM10524 e In System Programming In System programming ISP is programming or reprogramming the on chip flash memory using the bootloader software and the UART serial port This can be done when the part resides in the end user board e In Application Programming In Application IAP programming is performing erase and write operation on the on chip flash memory as directed by the end user application code All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 353 of 404 NXP Semiconductors U M1 0524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming e Small size 256 B page erase programming e Flash access times can be configured through a register in the flash controller block e Erase time for one sector is 100 ms 5 Programming time for one block of 256 bytes is 1 ms 5 21 4 Description The bootloader code is executed every time the part is powered on or
44. 263 Fig 33 Format of Master Receiver mode 264 Fig 34 A Master Receiver switches to Master Transmitter after sending Repeated START 264 Fig 35 Format of Slave Receiver mode 265 Fig 36 Format of Slave Transmitter mode 265 Fig 37 12C serial interface block diagram 266 Fig 38 Arbitration procedure 268 Fig 39 Serial clock synchronization 268 Fig 40 Format and states in the Master Transmitter MOIS anssen ested eee eget e Ree e 273 Fig 41 Format and states in the Master Receiver MOOG iets florian ke Pace di i e pnw Re aden ee Goma 276 Fig 42 Format and states in the Slave Receiver mode 280 Fig 43 Format and states in the Slave Transmitter MOOG oie ied endear dee eee a a teed 283 Fig 44 Simultaneous Repeated START conditions from two MASTE S snc cece ae tb eodals ue ds ade stele 285 Fig 45 Forced access to a busy l2C bus 285 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 396 of 404 NXP Semiconductors U M1 0524 Chapter 23 Supplementary information 23 5 Contents Chapter 1 LPC1315 16 17 45 46 47 Introductory information 1 1 INtrOdUCTION 2 eee eee srani eee eee 3 1 3 Ordering information 0000ees 5 1 2 Features ssscsee bs ete o ececae Skee erecta erecs 3 1 4 Block diagram 22
45. 283 14 11 6 4 State Ox30 0 0 0 ee eee 290 14 10 5 2 STAT 0x00 000005 283 14 11 6 5 State 0x38 2 eee 290 14 10 6 Some special cases 005 284 14 11 7 Master Receive states 290 14 10 6 1 Simultaneous Repeated START conditions from 14 11 7 1 State Ox40 0 00 0022 ee 290 two masters eee eee eee eee 284 14 11 7 2 State 0x48 0 eee 290 14 10 6 2 Data transfer after loss of arbitration 285 14 11 7 3 State Ox50 0 eee eee 290 14 10 6 3 Forced access to the I C bus 285 14 11 7 4 State 0x58 eee 291 14 10 6 4 I C bus obstructed by a LOW level on SCL or 14 11 8 Slave Receiver states 291 SDA 26 oie dS ob ah be wok ei eng ened 286 14 11 8 1 State Ox60 0 0 0 0 eee eee 291 14 10 6 5 Buserror 0 ee eee 286 14 11 8 2 State Ox68 0 0 0 cee eee 291 14 10 7 IC state service routines 286 14 11 8 3 State Ox70 0 0 ee eee 291 14 10 8 Initialization 0 0 6 eee ee 287 14 11 8 4 State Ox78 0 eee 292 14 10 9 IC interrupt service 287 14 11 8 5 State Ox80 0 0 002 292 14 10 10 The state service routines 287 14 11 8 6 State Ox88 0 eee 292 14 10 11 Adapting state services to an application 287 14 11 8 7 State Ox90 0 000 200 008 292 14 11 Software example 05
46. 3 FLASHREG Enables clock for flash register interface 1 0 Disabled 1 Enabled UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 20 of 404 NXP Semiconductors UM10524 UM10524 Table 19 Chapter 3 LPC1315 16 17 45 46 47 System control block System clock control SYSAHBCLKCTRL address 0x4004 8080 bit description Bit 10 11 12 13 14 15 16 17 Symbol Value FLASHARRAY 12C GPIO CT16B0 CT16B1 CT32B0 CT32B1 SSPO USART ADC USB WWDT IOCON All information provided in this document is subject to legal disclaimers Description Enables clock for flash array access Disabled Enabled Enables clock for 12C Disable Enable Enables clock for GPIO port registers Disable Enable Enables clock for 16 bit counter timer 0 Disable Enable Enables clock for 16 bit counter timer 1 Disable Enable Enables clock for 32 bit counter timer 0 Disable Enable Enables clock for 32 bit counter timer 1 Disable Enable Enables clock for SSPO Disable Enable Enables clock for UART Disable Enable Enables clock for ADC Disable Enable Enables clock to the USB register interface Disable Enable Enables clock for WWDT Disable Enable Enables clock for I O configuration block Disable Enable Reserved Reset value 1
47. 7 4 48 I O configuration for pin PIO1_26 Table 103 I O configuration for pin PIO1_26 CT32B0_MAT2 RXD PIO1_26 address 0x4004 40C8 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x3 to 0x7 are reserved 0 0x0 PIO1_26 0x1 CT32B0_MAT2 0x2 RXD 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 49 I O configuration for pin PIO1_27 Table 104 I O configuration for pin PIO1_27 CT32B0_MAT3 TXD PIO1_27 address 0x4004 40CC bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x3 to 0x7 are reserved 0 0x0 PIO1_27 0x1 CT32B0_MAT3 0x2 TXD UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 102 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I
48. All rights reserved User manual Rev 1 17 February 2012 328 of 404 NXP Semiconductors U M1 0524 Chapter 17 LPC1315 16 17 45 46 47 Windowed Watchdog Timer 17 8 Register description The Watchdog Timer contains the registers shown in Table 300 Table 300 Register overview Watchdog timer base address 0x4000 4000 Name Access Address Description Reset Reference offset Valuel1 MOD R W 0x000 Watchdog mode register This register contains the basic 0 Table 301 mode and status of the Watchdog Timer TC R W 0x004 Watchdog timer constant register This 24 bit register OxFF Table 303 determines the time out value FEED WO 0x008 Watchdog feed sequence register Writing OxAA followed by NA Table 304 0x55 to this register reloads the Watchdog timer with the value contained in WDTC TV RO 0x00C Watchdog timer value register This 24 bit register reads out OxFF Table 305 the current value of the Watchdog timer CLKSEL R W 0x010 Watchdog clock select register 0 Table 305 WARNINT R W 0x014 Watchdog Warning Interrupt compare value 0 Table 307 WINDOW R W 0x018 Watchdog Window compare value OxFF FFFF Table 308 1 Reset Value reflects the data stored in used bits only It does not include reserved bits content 17 8 1 Watchdog mode register The WDMOD register controls the operation of the Watchdog Note that a watchdog feed must be performed before any changes to the WDMOD register take effect Table 301 Watc
49. Chapter 10 LPC1345 46 47 USB2 0 device controller 10 7 2 Control endpoint 0 Write EPOOUT Activ Stall 1 0 Bytes Write EPOIN Active 0 Stall 1 Clear EPOIN interrupt Stall 1 Write EPOOUT Activ Stall NBytes Write EPOOUT Active 0 If not all IN data transferred the host aborts Control Read Otherwise it is a normal completion by the host Yes No No IN Data phase on going OUT Data phase on going Yes No No EP Oln Interrupt All OUT data received Yes Write EPOIN Active 1 Stall 1 0 Bytes Host aborts Control Write Write EP0Out Stall f Clear EPOIN interrupt STALL bit must only be set when it is the last packet during the data phase for this Control Transfer Fig 13 Flowchart of control endpoint 0 OUT direction Wait on EP 0Setup Out interrupt No EP0Setup Out Interrupt 1 Yes Clear EP 0 Setup Out interrupt Read DevStatus Setup bit Clear EPOOUT Stall Note It is very important that the Clear EPOIN Active DevStatus Setup is only cleared after Clear EPOIN Stall setting EPOOUT Active EPOOUT Stal Clear EPOIN interrupt i ii Clear DevStatus Setup IntonNak _CO IntonNak _Cl EPOIN Active and EPOIN Stall bits are Read SETUP bytes to zero Write EPOIN Active 0 SETUP request i wrteepooun S supporte
50. For each timer a maximum of three single edge controlled PWM outputs can be selected on the MATn 2 0 outputs One additional match register determines the PWM cycle length When a match occurs in any of the other match registers the PWM output is set to HIGH The timer is reset by the match register that is configured to set the PWM cycle length When the timer is reset to zero all currently HIGH match outputs configured as PWM outputs are cleared Table 299 PWM Control Register PWMC 0x4001 4074 CT32B0 and 0x4001 8074 CT32B1 bit description Bit Symbol Value Description Reset value 0 PWMENO PWM mode enable for channel0 0 0 CT32Bi_MATO is controlled by EMO 1 PWM mode is enabled for CT32Bi_MATO 1 PWMEN1 PWM mode enable for channel1 0 0 CT32Bi_MAT01 is controlled by EM1 1 PWM mode is enabled for CT32Bi_MAT1 2 PWMEN2 PWM mode enable for channel2 0 0 CT32Bi_MAT2 is controlled by EM2 1 PWM mode is enabled for CT32Bi_MAT2 3 PWMENS3 PWM mode enable for channel3 Note It is 0 recommended to use match channel 3 to set the PWM cycle 0 CT32Bi_MAT3 is controlled by EM3 1 PWM mode is enabled for CT132Bi_MATS3 31 4 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined 16 7 13 Rules for single edge controlled PWM outputs 1 All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle timer is set to zero unless their match value is equal
51. HID_GetReportDesc USBD_HANDLE_T hHid USB_SETUP_PACKET pSetup uint8_t pBuf uint1l6_t length USBD_HANDLE_T hHid USB_SETUP_PACKET pSetup uint8_t pBuf uintl6_t length Optional user overridable function to replace the default HID_GetReportDesc handler The application software could override the default HID_GetReportDesc handler with their own by providing the handler function address as this data member of the parameter structure Application which like the default handler should set this data member to zero before calling the USBD_HID_API Init and also provide report data array Remark Parameters 1 hUsb Handle to the USB device stack 2 data Pointer to the data which will be passed when callback function is called by the stack 3 event Type of endpoint event See USBD_EVENT_T for more details Returns The call back should returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_xxx For other error conditions UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 187 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 198 USBD_HID_INIT_PARAM class structure Member Description HID_Ep0_Hadlr ErrorCode_t
52. LPC1345 46 47 USB on chip drivers Table 198 USBD_HID_INIT_PARAM class structure Member HID_SetReport UM10524 Description ErrorCode_t ErrorCode_t USBD_HID_INIT_PARAM HID_SetReport USBD_HANDLE_T hHid USB_SETUP_PACKET pSetup uint8_t pBuffer uintl6_t length USBD_HANDLE_T hHid USB_SETUP_PACKET pSetup uint8_t pBuffer uintl6_t length HID set report callback function This function is provided by the application software This function gets called when host sends a HID_REQUEST_SET REPORT request The setup packet data hHidHandle to HID function driver pSetupPointer to setup packet received from host pBufferPointer to a pointer of data buffer containing report data Pointer to pointer is used to implement zero copy buffers See Zero Copy Data Transfer model for more details on zero copy concept lengthAmount of data copied to destination buffer Parameters 1 hHid Handle to HID function driver 2 pSetup Pointer to setup packet received from host 3 pBuffer Pointer to a pointer of data buffer containing report data Pointer to pointer is used to implement zero copy buffers See Zero Copy Data Transfer model for more details on zero copy concept 4 length Amount of data copied to destination buffer Returns The call back should returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the even
53. MATCHALL l2CnMMCTRL 3 INPUT PIETER 2CnDATABUFFER K gt a Mn MONITOR MODE REGISTER gt 12CnMMCTRL APB BUS BIT COUNTER INPUT ARBITRATION and lt PCLK FILTER SYNC LOGIC TIMING and CONTROL LOGIC OUTPUT SERIAL CLOCK interrupt STAGE GENERATOR CONTROL REGISTER and SCL DUTY CYLE REGISTERS I2CnCONSET I2CnCONCLR I2CnSCLH I2CnSCLL status STATUS bus DECODER Fig 37 1 C serial interface block diagram 14 9 1 Input filters and output stages Input signals are synchronized with the internal clock and spikes shorter than three clocks are filtered out The output for 12C is a special pad designed to conform to the 12C specification UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 266 of 404 NXP Semiconductors U M1 0524 UM10524 14 9 2 14 9 3 14 9 4 14 9 5 14 9 6 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller Address Registers ADRO to ADR3 These registers may be loaded with the 7 bit slave address 7 most significant bits to which the 12C block will respond when programmed as a slave transmitter or receiver The LSB GC is used to enable General Call address 0x00 recognition When multiple slave addresses are enabled the actual address received may be read from the DAT register at the
54. NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 26 of 404 NXP Semiconductors U M1 0524 UM10524 3 5 29 3 5 30 Chapter 3 LPC1315 16 17 45 46 47 System control block Setting this parameter to a very low value e g zero will guarantee the best possible interrupt performance but will also introduce a significant degree of uncertainty and jitter Requiring the system to always take a larger number of cycles whether it needs it or not will reduce the amount of uncertainty but may not necessarily eliminate it Theoretically the ARM Cortex M3 core should always be able to service an interrupt request within 15 cycles System factors external to the cpu however bus latencies peripheral response times etc can increase the time required to complete a previous instruction before an interrupt can be serviced Therefore accurately specifying a minimum number of cycles that will ensure determinism will depend on the application The default setting for this register is 0x010 Table 33 IQR delay IRQLATENCY address 0x4004 8170 bit description Bit Symbol Description Reset value 7 0 LATENCY _ 8 bit latency value 0x010 31 8 Reserved NMI Source Control register NMISRC The NMI source selection register selects a peripheral interrupts as source for the NMI interrupt of the ARM Cortex M3 core For a list of all peripheral interrupts and their IRQ numbers see Table 53 For a descripti
55. System PLL status SYSPLLSTAT address 0x4004 800C bit description Bit Symbol Value Description Reset value 0 LOCK PLL lock status 0 0 PLL not locked 1 PLL locked 31 1 Reserved UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 15 of 404 NXP Semiconductors U M1 0524 Chapter 3 LPC1315 16 17 45 46 47 System control block 3 5 5 USB PLL control register USBPLLCTRL The USB PLL is identical to the system PLL and is used to provide a dedicated clock to the USB block if available see Section 3 1 This register connects and enables the USB PLL and configures the PLL multiplier and divider values The PLL accepts an input frequency from 10 MHz to 25 MHz from various clock sources The input frequency is multiplied up to a high frequency then divided down to provide the actual clock 48 MHz clock used by the USB subsystem Table 10 USB PLL control USBPLLCTRL address 0x4004 8010 bit description Bit Symbol Value Description Reset value 4 0 MSEL Feedback divider value The division value M is the 0x000 programmed MSEL value 1 00000 Division ratio M 1 to 11111 Division ratio M 32 6 5 PSEL Post divider ratio P The division ratio is 2 x P 0x00 0x0 P 1 0x1 P 2 0x2 P 4 0x3 P 8 31 7 Reserved Do not write ones to reserved bits 0x00 3 5 6 USB PLL status register USBPLLSTAT This
56. The following steps must be performed to enter Deep power down mode Pull the WAKEUP pin externally HIGH Ensure that bit 3 in the PCON register Table 48 is cleared Write 0x3 to the PD bits in the PCON register see Table 48 Store data to be retained in the general purpose registers Section 4 3 2 Write one to the SLEEPDEEP bit in the ARM Cortex M3 SCR register Ensure that the IRC is powered by setting bits IRCOUT_PD and IRC_PD to zero in the PDRUNCFG register before entering Deep power down mode 7 Use the ARM WEI instruction oar WwW DY Wake up from Deep power down mode Pulling the WAKEUP pin LOW wakes up the LPC1315 16 17 45 46 47 from Deep power down and the chip goes through the entire reset process Section 3 6 1 On the WAKEUP pin transition from HIGH to LOW The PMU will turn on the on chip voltage regulator When the core voltage reaches the power on reset POR trip point a system reset will be triggered and the chip re boots All registers except the GPREGO to GPREG4 will be in their reset state All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 41 of 404 NXP Semiconductors U M1 0524 Chapter 3 LPC1315 16 17 45 46 47 System control block 2 Once the chip has booted read the deep power down flag in the PCON register Table 48 to verify that the reset was caused by a
57. These bits contain the channel from which the result bits V_VREF were converted Reserved These bits always read as zeros This bit is 1 in burst mode if the results of one or more conversions was were lost and overwritten before the conversion that produced the result in the V_VREF bits This bit is set to 1 when an A D conversion completes It is cleared 0 when this register is read and when the ADCR is written If the ADCR is written while a conversion is still in progress this bit is set and a new conversion is started 20 5 3 A D Interrupt Enable Register INTEN This register allows control over which A D channels generate an interrupt when a conversion is complete For example it may be desirable to use some A D channels to monitor sensors by continuously performing conversions on them The most recent results are read by the application program whenever they are needed In this case an interrupt is not desirable at the end of each conversion for some A D channels Table 326 A D Interrupt Enable Register INTEN address 0x4001 C00C bit description Bit Symbol 7 0 ADINTEN 8 ADGINTEN 31 9 Description Reset Value These bits allow control over which A D channels generate 0x00 interrupts for conversion completion When bit 0 is one completion of a conversion on A D channel 0 will generate an interrupt when bit 1 is one completion of a conversion on A D channel 1 will generate an interrupt etc Whe
58. User manual Rev 1 17 February 2012 NXP B V 2012 All rights reserved 109 of 404 NXP Semiconductors U M1 0524 Chapter 8 LPC1315 16 17 45 46 47 Pin configuration Table 108 Pin description L_PC1315 16 17 no USB Symbol Description 3g eeh 8 oy es a Ee PIO1_19 DTR SSEL1 3 2 1 B GPU VO PIO1_19 General purpose digital input output pin O DTR Data Terminal Ready output for USART 1 0 SSEL1 Slave select for SSP1 PIO1_20 DSR SCK1 18 13 BI PU VO P101_20 General purpose digital input output pin l DSR Data Set Ready input for USART 1 0 SCK1 Serial clock for SSP1 PIO1_21 DCD MISO1 35 26 BI PU VO P101_21 General purpose digital input output pin DCD Data Carrier Detect input for USART 0 MISO1 Master In Slave Out for SSP1 PIO1_22 RI MOSI1 51 38 BI PU VO P101_22 General purpose digital input output pin l RI Ring Indicator input for USART VO MOSI1 Master Out Slave In for SSP1 PIO1_23 CT16B1_MAT1 24 18 13 B IPU VO PIO1_23 General purpose digital input output pin SSEL1 z O CT16B1_MAT1 Match output 1 for 16 bit timer 1 0 SSEL1 Slave select for SSP1 PIO1_24 CT32B0_MATO 27 21 14 BI PU VO PIO1_24 General purpose digital input output pin O CT32B0_MAT0 Match output 0 for 32 bit timer 0 PIO1_25 CT32BO_MAT1 2 1 BI PU VO P101_25 General purpose digital input output pin O CT32B0_MAT1 Mat
59. is initially the Reset vector mapped from the boot block At that point all of the processor and peripheral registers have been initialized to predetermined values 3 7 Start up behavior See Figure 4 for the start up timing after reset The IRC is the default clock at Reset and provides a clean system clock shortly after the supply voltage reaches the threshold value of 1 8 V UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 34 of 404 NXP Semiconductors U M1 0524 Chapter 3 LPC1315 16 17 45 46 47 System control block IRC starts RESET Se ee VDD valid threshold 1 8V q rj gt 80 us 101 us GND supply ramp up gt boot time time 55 s user code gt processor status boot code execution finishes user code starts Fig 4 Start up timing 3 8 Brown out detection The LPC1315 16 17 45 46 47 includes four levels for monitoring the voltage on the Vpp pin If this voltage falls below one of the four selected levels the BOD asserts an interrupt signal to the NVIC or issues a reset depending on the value of the BODRSTENA bit in the BOD control register Table 31 The interrupt signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC see Table 348 in order to cause a CPU interrupt if not software
60. more important if the device draws power from the bus bus powered device The following constraints should be met by the bus powered device e A device in the non configured state should draw a maximum of 100mA from the USB bus e A configured device can draw only up to what is specified in the Max Power field of the configuration descriptor The maximum value is 500 mA e A suspended device should draw a maximum of 500 uA A device will go into the L2 suspend state if there is no activity on the USB bus for more than 3 ms A suspended device wakes up if there is transmission from the host host initiated wake up The USB controller on the LPC1315 1 6 1 7 45 46 47 also supports software initiated remote wake up To initiate remote wake up software on the device must enable all clocks and clear the suspend bit This will cause the hardware to generate a remote wake up signal upstream The USB controller supports Link Power Management Link Power Management defines an additional link power management state L1 that supplements the existing L2 state by utilizing most of the existing suspend resume infrastructure but provides much faster transitional latencies between L1 and LO On The assertion of USB suspend signal indicates that there was no activity on the USB bus for the last 3 ms At this time an interrupt is sent to the processor on which the software can start preparing the device for suspend If there is no activity for the next
61. the SSPnCPSR value must be properly initialized or the SPI controller will not be able to transmit data correctly In Slave mode the SPI clock rate provided by the master must not exceed 1 12 of the SPI peripheral clock selected in Table 20 Table 22 The content of the SSPnCPSR register is not relevant In master mode CPSDVSRmin 2 or larger even numbers only 13 6 6 SSP SPI Interrupt Mask Set Clear Register This register controls whether each of the four possible interrupt conditions in the SPI controller are enabled UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 242 of 404 NXP Semiconductors U M1 0524 UM10524 13 6 7 13 6 8 Chapter 13 LPC1315 16 17 45 46 47 SSP SPI Table 239 SSP SPI Interrupt Mask Set Clear register IMSC address 0x4004 0014 SSP0 and 0x4005 8014 SSP1 bit description Bit Symbol Description Reset Value 0 RORIM Software should set this bit to enable interrupt when a Receive 0 Overrun occurs that is when the Rx FIFO is full and another frame is completely received The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs 1 RTIM Software should set this bit to enable interrupt when a Receive 0 Time out condition occurs A Receive Time out occurs when the Rx FIFO is not empty and no has not been read for a time ou
62. 0 A transition on a capture pin can be configured to load one of the Capture Registers with the value in the Timer Counter and optionally generate an interrupt The counter timer block can select a capture signal as a clock source instead of the PCLK derived clock For more details see Section 16 7 11 Count Control Register on page 319 CT32B0_MAT 3 0 Output External Match Output of CT32B0 1 CT32B1_MAT 3 0 When a match register MR3 0 equals the timer counter TC this output can either toggle go LOW go HIGH or do nothing The External Match Register EMR and the PWM Control register PWMCON control the functionality of this output 16 7 Register description 32 bit counter timerO contains the registers shown in Table 285 and 32 bit counter timer1 contains the registers shown in Table 286 More detailed descriptions follow UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 311 of 404 NXP Semiconductors U M1 0524 Chapter 16 LPC1315 16 17 45 46 47 32 bit counter timers CT32B0 1 Table 285 Register overview 32 bit counter timer 0 CT32B0 base address 0x4001 4000 Name Access Address Description Reset Reference offset valuel IR R W 0x000 Interrupt Register The IR can be written to clear interrupts The IR 0 Table 287 can be read to identify which of eight possible interrupt sources are p
63. 0 to 255 bit times may be programmed All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 228 of 404 NXP Semiconductors U M1 0524 Chapter 12 LPC1315 16 17 45 46 47 USART Table 229 USART RS 485 Delay value register RS485DLY address 0x4000 8054 bit description Bit Symbol Description Reset value 7 0 DLY Contains the direction control RTS or DTR delay value This 0x00 register works in conjunction with an 8 bit counter 31 8 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 12 5 22 USART Synchronous mode control register SYNCCTRL register controls the synchronous mode When this mode is in effect the USART generates or receives a bit clock on the SCLK pin and applies it to the transmit and receive shift registers Synchronous mode should not be used with smart card mode Table 230 USART Synchronous mode control register SYNCCTRL address 0x4000 8058 bit description Bit Symbol Value Description Reset value 0 SYNC Enables synchronous mode 0 0 Disabled 1 Enabled 1 CSRC Clock source select 0 0 Synchronous slave mode SCLK in 1 Synchronous master mode SCLK out 2 FES Falling edge sampling 0 0 RxD is sampled on the rising edge of SCLK 1 RxD is sampled on the falling edge of SCLK 3 TSBYPASS Transmit synchronization bypass in sync
64. 0005 7 Chapter 2 LPC1315 16 17 45 46 47 Memory mapping 2 1 How to read this chapter 8 2 2 1 On chip flash programming memory 8 2 2 Memory MAD Ss ftasc cae anne oes cana ned 8 2 2 2 EEPROM 0000 cee eee eae 9 2 2 3 SRAM a ia bith ceeded ede 9 Chapter 3 LPC1315 16 17 45 46 47 System control block 3 1 How to read this chapter 11 3 5 24 POR captured PIO status 0 register 3 2 Introduction 000 eeeeeeeeeee 11 PIOPORCAPO preteens 25 3 3 Pin description 0 00eeeee qf 3325 FOR captured PIO status 1 register 34 Clocki d trol 11 PIOPORCAP1 nananana anaa 25 i OE ANC POWE COMTO asiingie 3 5 26 Brown Out Detect register BODCTRL 25 3 5 Register description 0000eee 13 3 5 27 System tick counter calibration register 3 5 1 System memory remap register SYSTCKCAL 2 0200 00005 26 SYSMEMREMAP 20 2225 Seeker es 14 3 5 28 IQR delay register IRQLATENCY 26 3 5 2 Peripheral reset control register 3 5 29 NMI Source Control register NMISRC 27 PRESETCTRL 0 sees eae 14 3 5 30 GPIO Pin Interrupt Select register PINTSEL 27 3 5 3 System PLL control register SYSPLLCTRL 15 3 5 31 USB clock control register USBCLKCTRL 28 3 5 4 System PLL status register SYSPLLSTAT 15 3 5 32 USB clock status register USBCLKST 28 3 5 5 USB PLL control register USBPLLCTRL 16 3 5 33 Start logic 0 interru
65. 0x3 Repeater mode UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 65 of 404 NXP Semiconductors UM10524 UM10524 7 4 2 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 56 I O configuration for pin RESET PIOO_0 RESET_PIO0_0 address 0x4004 4000 bit description Bit Symbol Value Description Reset value 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 31 11 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD Reserved 0 I O configuration for pin PIOO_1 I O configuration for pin PlOO_1 CLKOUT CT32B0_MAT2 USB_FTOGGLE PIO0_1 address 0x4004 4004 bit description Table 57 Bit Symbol 2 0 FUNC 4 3 MODE 5 HYS 6 INV 9 7 Value Description Reset value Selects pin function Values 0x4 to 0x7 are reserved 0 0x0 PIOO_1 0x1 CLKOUT 0x2 CT32B0_MAT2 0x3 USB_FTOGGLE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode Hysteresis 0 0 Disable 1 Enable Inver
66. 0x30 Data byte in DAT has Load data byteor 0 0 0 Data byte will be transmitted ACK bit will been transmitted be received ie a has been No DAT action or 0 Repeated START will be transmitted No DAT actionor 0 STOP condition will be transmitted STO flag will be reset No DAT action 1 1 0 STOP condition followed by a START condition will be transmitted STO flag will be reset 0x38 Arbitration lost in No DAT actionor 0 0 0 I2C bus will be released not addressed SLA R W or Data slave will be entered bytes No DAT action 1 0 0 A START condition will be transmitted when the bus becomes free UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 272 of 404 NXP Semiconductors U M1 0524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller MT successful transmission to a Slave Receiver next transfer started with a Repeated Start condition Not Acknowledge l received after gt l the Slave l address i to Master Not big Acknowledge y meS received after a i et Data byte E arbitration lost i ies i in Slave gt AOR A other Master IAORA other Master address or i continues I continues Data byte arbitration lost and other Master addressed as continues Slave to corresponding states in Slave mode from Master to Slave from Slave to Master DATA i any number of data bytes and their associated
67. 0x4 to 0x7 are reserved 0 0x0 PIOO_8 0x1 MISOO 0x2 CT16BO_MATO 0x3 ARM_TRACE_CLK 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 71 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 64 I O configuration for pin PIOO_8 MISO0 CT16B0_MAT0 ARM_TRACE_CLK PIO0_8 address 0x4004 4020 bit description Bit Symbol Value Description Reset value 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 10 I O configuration for pin PIOO_9 Table 65 I O configuration for pin PIOO_9 MOSI0 CT16B0_MAT1 ARM_TRACE_SWV PIO0_9 address 0x4004 4024 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x4 to 0x7 are reserved 0 0x0 PIOO_9 0x1 MOSIO 0x2 CT16BO_MAT1 0x3 ARM_TRACE_SWV 4 3 MODE Se
68. 0x4004 8080 bit description 20 Table 47 Register overview PMU base address 0x4003 Table 20 SSPO clock divider SSPOCLKDIV address 8000 idee ie a Ad db ba tied 45 0x4004 8094 bit description 22 Table 48 Power control register PCON address 0x4003 Table 21 UART clock divider UARTCLKDIV address 8000 bit description 45 0x4004 8098 bit description 23 Table 49 General purpose registers 0 to 3 GPREGO Table 22 SSP1 clock divider SSP1CLKDIV address GPREG3 address 0x4003 8004 to 0x4003 8010 0x4004 809C bit description 23 bit description 000 eee eee 46 Table 23 ARM trace clock divider TRACECLKDIV address Table 50 General purpose register 4 GPREG4 address 0x4004 80AC bit description 23 0x4003 8014 bit description 47 Table 24 SYSTICK clock divider SYSTICKCLKDIV Table 51 set_pll routine 0 50 address 0x4004 80B0 bit description 23 Table 52 set_power routine 55 Table 25 USB clock source select USBCLKSEL address Table 53 Connection of interrupt sources to the Vectored 0x4004 80C0 bit description 24 Interrupt Controller 05 57 Table 26 USB clock source divider USBCLKDIV address Table 54 IOCON registers available 60 0x4004 80C8 bit description 24 Table 55 Register overview IOCON base address
69. 1 9 7 Reserved 001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 92 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration 7 4 36 I O configuration for PIO1_14 Table 91 1 O configuration for PIO1_14 DSR CT16B0_MAT1 RXD PIO1_14 address 0x4004 4098 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x4 to 0x7 are reserved 0 OxO PIO1_14 0x1 DSR 0x2 CT16B0_MAT1 0x3 RXD 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 37 I O configuration for pin PIO1_15 Table 92 I O configuration for pin PIO1_15 DCD CT16B0_MAT2
70. 16 17 45 46 47 System control block SYSAHBCLKCTRLn AHB clock enable IRC oscillator ialok main cloc SSPO PERIPHERAL CLOCK DIVIDER SSPO watchdog oscillator USART PERIPHERAL CLOCK DIVIDER UART MAINCLKSEL main clock select IRC oscillator SYSTEM PLL system oscillator SSP1 PERIPHERAL CLOCK DIVIDER CPU system control PMU SYSTEM CLOCK System clock n DIVIDER 4 memories peripheral clocks SSP1 SYSPLLCLKSEL system PLL clock select system oscillator USB PLL USB 48 MHz CLOCK USB USBPLLCLKSEL USB clock select USBCLKSEL USB clock select IRC oscillator system oscillator CLKOUT PIN CLOCK CLKOUT pin watchdog oscillator CLKOUTSEL CLKOUT clock select IRC oscillator WDT watchdog oscillator WDCLKSEL WDT clock select 002aag563 Fig 3 LPC1315 16 17 45 46 47 CGU block diagram UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 12 of 404 NXP Semiconductors UM10524 3 5 Register description Chapter 3 LPC1315 16 17 45 46 47 System control block Table 5 Register overview SYSCON base address 0x4004 8000 Name Access Address Description Reset Reference offset value SYSMEMREMAP read write 0x000 System memory remap 0 Table 6 PRESETCTRL read write 0x004 Peripheral reset control 0 Table 7 SYSPLLCTRL read
71. 2012 44 of 404 UM10524 Chapter 4 LPC1315 16 17 45 46 47 Power Management Unit PMU Rev 1 17 February 2012 User manual 4 1 How to read this chapter The PMU is identical on all LPC1315 16 1 7 45 46 47 parts Also refer to Chapter 5 for power control 4 2 Introduction The PMU controls the Deep power down mode Four general purpose register in the PMU can be used to retain data during Deep power down mode 4 3 Register description UM10524 4 3 1 Table 47 Register overview PMU base address 0x4003 8000 Name Access Address Description Reset Reference offset value PCON R W 0x000 Power control register 0x0 Table 48 GPREGO R W 0x004 General purpose register 0 0x0 Table 49 GPREG1 R W 0x008 General purpose register 1 0x0 Table 49 GPREG2 R W 0x00C General purpose register 2 0x0 Table 49 GPREG3 R W 0x010 General purpose register 3 0x0 Table 49 GPREG4 R W 0x014 General purpose register 4 0x0 Table 50 Power control register The power control register selects whether one of the ARM Cortex M3 controlled power down modes Sleep mode or Deep sleep Power down mode or the Deep power down mode is entered and provides the flags for Sleep or Deep sleep Power down modes and Deep power down modes respectively See Section 3 9 for details on how to enter the power down modes Table 48 Power control register PCON address 0x4003 8000 bit description Bit Symbol Value Description Reset value 2 0 PM Power mode
72. 46 47 SSP SPI b Continuous back to back frames transfer Fig 23 Texas Instruments Synchronous Serial Frame Format a Single and b Continuous back to back Two Frames Transfer 4 to 16 bits 4 to 16 bits UM10524 13 7 2 13 7 2 1 For device configured as a master in this mode CLK and FS are forced LOW and the transmit data line DX is in 3 state mode whenever the SSP is idle Once the bottom entry of the transmit FIFO contains data FS is pulsed HIGH for one CLK period The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the transmit logic On the next rising edge of CLK the MSB of the 4 bit to 16 bit data frame is shifted out on the DX pin Likewise the MSB of the received data is shifted onto the DR pin by the off chip serial slave device Both the SSP and the off chip serial slave device then clock each data bit into their serial shifter on the falling edge of each CLK The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched SPI frame format The SPI interface is a four wire interface where the SSEL signal behaves as a slave select The main feature of the SPI format is that the inactive state and phase of the SCK signal are programmable through the CPOL and CPHA bits within the SSPCRO control register Clock Polarity CPOL and Phase CPHA control When the CPOL clock polar
73. 46 47 USB on chip drivers Table 201 USBD_MSC_INIT_PARAM class structure Member MSC_Verify MSC_GetWriteBuf UM10524 Description ErrorCode_t ErrorCode_t USBD_MSC_INIT_PARAM MSC_Verify uint32_t offset uint8_t buf uint32_t length uint32_t offset uint8_t buf uint32_t length MSC Verify callback function This function is provided by the application software This function gets called when host sends a verify command The callback function should compare the buffer with the destination memory at the requested offset and offsetDestination start address bufBuffer containing the data sent by the host lengthNumber of bytes to verify Parameters 1 offset Destination start address 2 buf Buffer containing the data sent by the host 3 length Number of bytes to verify Returns Returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK If data in the buffer matches the data at destination 2 ERR_FAILED At least one byte is different void void USBD_MSC_INIT_PARAM MSC_GetWriteBuf uint32_t offset uint8_t buff_adr uint32_t length uint32_t offset uint8_t buff_adr uint32_t length Optional callback function to optimize MSC_Write buffer transfer This function is provided by the application software This function gets called when host sends SCSI_WRITE10 SCSI_WRITE12 command The callback function should update the offsetDestination start address bufBuffe
74. 47 SSP SPI sJ UUUUUUUUVUU e oS ee SI bit Soni 0 msa ese 4 to 16 bits_ of output data Fig 28 Microwire frame format single transfer lt lt 8 bit contro gt s lt 4 to 16 bits p lt 4 to 16 bits _y of output data of output data Fig 29 Microwire frame format continuous transfers Microwire format is very similar to SPI format except that transmission is half duplex instead of full duplex using a master slave message passing technique Each serial transmission begins with an 8 bit control word that is transmitted from the SSP SPI to the off chip slave device During this transmission no incoming data is received by the SSP SPI After the message has been sent the off chip slave decodes it and after waiting one serial clock after the last bit of the 8 bit control message has been sent responds with the required data The returned data is 4 to 16 bit in length making the total frame length anywhere from 13 to 25 bits In this configuration during idle periods e The SK signal is forced LOW e CS is forced HIGH e The transmit data line SO is arbitrarily forced LOW A transmission is triggered by writing a control byte to the transmit FIFO The falling edge of CS causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic and the MSB of the 8 bit control frame to be shifted out onto
75. 60 I O configuration for pin PIOO_4 SCL PIOO_4 address 0x4004 4054 bit description 82 address 0x4004 4010 bit description 68 Table 78 I O configuration for pin Table 61 I O configuration for pin PIOO_5 SDA PIO0_5 PIOO_22 AD6 CT16B1_MAT1 MISO1 PIOO_22 address 0x4004 4014 bit description 69 address 0x4004 4058 bit description 83 Table 62 I O configuration for pin Table 79 I O configuration for pin PIOO_23 AD7 PIOO_23 PIOO_6 USB_CONNECT SCKO PIO0_6 address 0x4004 405C bit description 84 address 0x4004 4018 bit description 69 Table 80 1 O configuration for pin PlO1_0 CT32B1_MATO Table 63 I O configuration for pin PIOO_7 CTS PIOO_7 PlO1_0 address 0x4004 4060 bit description85 address 0x4004 401C bit description 70 Table 81 I O configuration for pin PlO1_1 CT32B1_MAT1 Table 64 I O configuration for pin PlO1_1 address 0x4004 4064 bit description86 PIO0_8 MISO0 CT16BO_MATO ARM_TRACE_C Table 82 I O configuration for pin PlO1_2 CT32B1_MAT2 LK PIOO_8 address 0x4004 4020 bit PlO1_2 address 0x4004 4068 bit description86 GESCHIPUON assetadet wi al ae Bd AMEE Bud Bd 71 Table 83 I O configuration for pin PlO1_3 CT32B1_MAT3 Table 65 1 O configuration for pin PIO1_3 address 0x4004 406C bit PIOO_9 MOSI0 CT16B0O_MAT1 ARM_TRACE_S description 0000 eee eee ee eee 87 WV PIOO_9 address 0x4004 4024 bit Table 84 1 O configuration for pin PlO1_4 CT32B1_CAPO CESCHPUO
76. 7 Peripheral reset control PRESETCTRL address 0x4004 0004 bit description Bit Symbol Value Description Reset value 0 SSPO_RST_N SSPO0 reset control 0 0 Resets the SSPO peripheral 1 SSPO0 reset de asserted 1 I2C_RST_N 12C reset control 0 0 Resets the I2C peripheral 1 12C reset de asserted 2 SSP1_RST_N SSP1 reset control 0 0 Resets the SSPO peripheral 1 SSP1 reset de asserted 3 Reserved 31 4 Reserved System PLL control register SYSPLLCTRL This register connects and enables the system PLL and configures the PLL multiplier and divider values The PLL accepts an input frequency from 10 MHz to 25 MHz from various clock sources The input frequency is multiplied to a higher frequency and then divided down to provide the actual clock used by the CPU peripherals and memories The PLL can produce a clock up to the maximum allowed for the CPU Table 8 System PLL control SYSPLLCTRL address 0x4004 8008 bit description Bit Symbol Value Description Reset value 4 0 MSEL Feedback divider value The division value M is the 0 programmed MSEL value 1 00000 Division ratio M 1 to 11111 Division ratio M 32 6 5 PSEL Post divider ratio P The division ratio is 2 x P 0 0x0 P 1 0x1 P 2 0x2 P 4 0x3 P 8 31 7 Reserved Do not write ones to reserved bits System PLL status register SYSPLLSTAT This register is a Read only register and supplies the PLL lock status see Section 3 10 1 Table 9
77. A START condition Load SLA W X 0 0 SLA W will be transmitted ACK bit will has been transmitted clear STA be received 0x10 A Repeated START Load SLA Wor X 0 0 As above condition hasbeen gad SLA R x 0 SLA R will be transmitted the I2C block transmitted Clear STA will be switched to MST REC mode 0x18 SLA W has been Load data byte or 0 0 0 Data byte will be transmitted ACK bit will transmitted ACK has be received been received NoDATactionor 1 0 0 Repeated START will be transmitted No DAT actionor 0 0 STOP condition will be transmitted STO flag will be reset No DAT action 1 1 0 STOP condition followed by a START condition will be transmitted STO flag will be reset 0x20 SLA W has been Load databyte or 0 0 0 Data byte will be transmitted ACK bit will transmitted NOT ACK be received has been received No DAT action or 0 Repeated START will be transmitted No DAT actionor 0 1 STOP condition will be transmitted STO flag will be reset No DAT action 1 1 0 STOP condition followed by a START condition will be transmitted STO flag will be reset 0x28 Data byte in DAT has Load data byteor 0 0 0 Data byte will be transmitted ACK bit will been transmitted be received cok sey been No DAT actionor 1 0 O Repeated START will be transmitted l No DAT actionor 0 1 0 STOP condition will be transmitted STO flag will be reset No DAT action 1 1 0 STOP condition followed by a START condition will be transmitted STO flag will be reset
78. AAD mode When both RS485CTRL register bits 0 9 bit mode enable and 2 AAD mode enable are set the USART is in auto address detect mode In this mode the receiver will compare any address byte received parity 1 to the 8 bit value programmed into the RS485ADRMATCH register If the receiver is disabled RS485CTRL bit 1 1 any received byte will be discarded if it is either a data byte OR an address byte which fails to match the RS485ADRMATCH value When a matching address character is detected it will be pushed onto the RXFIFO along with the parity bit and the receiver will be automatically enabled RS485CTRL bit 1 will be cleared by hardware The receiver will also generate an Rx Data Ready Interrupt All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 231 of 404 NXP Semiconductors U M1 0524 12 6 2 UM10524 Chapter 12 LPC1315 16 17 45 46 47 USART While the receiver is enabled RS485CTRL bit 1 0 all bytes received will be accepted and stored in the RXFIFO until an address byte which does not match the RS485ADRMATCH value is received When this occurs the receiver will be automatically disabled in hardware RS485CTRL bit 1 will be set The received non matching address character will not be stored in the RXFIFO RS 485 EIA 485 Auto Direction Control RS485 EIA 485 mode includes the opt
79. AD6 0x2 CT16B1_MAT1 0x3 MISO1 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 83 of 404 NXP Semiconductors U M1 0524 UM10524 7 4 24 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 78 I O configuration for pin PlOO_22 AD6 CT16B1_MAT1 MISO1 PIOO_22 address 0x4004 4058 bit description Bit Symbol Value Description Reset value 7 ADMODE Selects Analog Digital mode 1 0 Analog input mode 1 Digital functional mode 8 FILTR Selects 10 ns input glitch filter 0 0 Filter disabled 1 Filter enabled 9 Reserved 0 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 I O configuration for pin PIOO_23 Table 79 I O configuration for pin PIOO_23 AD7 PIO0_23 address 0x4004 405C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin fun
80. B V 2012 All rights reserved User manual Rev 1 17 February 2012 40 of 404 NXP Semiconductors U M1 0524 UM10524 3 9 6 3 9 6 1 3 9 6 2 3 9 6 3 Chapter 3 LPC1315 16 17 45 46 47 System control block WWD0T interrupt using the interrupt wake up register 1 Table 39 The WWDT interrupt must be enabled in the NVIC The WWDT interrupt must be set in the WWDT MOD register Reset from the watchdog timer The WWDT reset must be set in the WWDT MOD register e USB wake up signal interrupt wake up register 1 Table 41 For details see Section 10 7 6 e GPIO group interrupt signal see Table 39 Deep power down mode In Deep power down mode power and clocks are shut off to the entire chip with the exception of the WAKEUP pin The Deep power down mode is controlled by the PMU see Chapter 4 During Deep power down mode the contents of the SRAM and registers are not retained except for a small amount of data which can be stored in the general purpose registers of the PMU block All functional pins are tri stated in Deep power down mode except for the WAKEUP pin Remark Setting bit 3 in the PCON register Section 4 3 1 prevents the part from entering Deep power down mode Power configuration in Deep power down mode Deep power down mode has no configuration options All clocks the core and all peripherals are powered down Only the WAKEUP pin is powered Programming Deep power down mode
81. C000 297 NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 393 of 404 NXP Semiconductors UM10524 Table 270 Register overview 16 bit counter timer 1 CT16B1 base address 0x4001 0000 Table 271 Interrupt Register IR address 0x4000 C000 CT16B0 and 0x4001 0000 CT16B1 bit COSCHPUON joie acide aeei eae stl eens 299 Table 272 Timer Control Register TCR address 0x4000 C004 CT16B0 and 0x4001 0004 CT16B1 bit description 0 0 eee eee 299 Table 273 Timer counter registers TC address 0x4000 C008 CT16B0 and 0x4001 0008 CT16B1 bit description 299 Table 274 Prescale registers PR address 0x4000 C00C CT16B0 and 0x4001 000C CT16B1 bit description 0 0c cee eee eee 300 Table 275 Prescale counter registers PC address 0x4000 C010 CT16B0 and 0x4001 0010 CT16B1 bit description 300 Table 276 Match Control Register MCR address 0x4000 C014 CT16B0 and 0x4001 0014 CT16B1 bit description Table 277 Match registers MRO to 3 addresses 0x4000 C018 to 24 CT16B0 and 0x4001 0018 to 24 CT16B1 bit description 302 Table 278 Capture Control Register CCR address 0x4000 C028 CT16B0 and 0x4001 0028 CT16B1 bit CeSCHPLON es hed dbearke eset bake bbe e 302 Table 279 Capture registers CR addresses 0x4000 C02C CRO to 0x4000 C030 CR1 CT16B0 and 0x4001 002C CRO to 0x4001 0030 CR1
82. CRO RO 0x02C Capture Register 0 CRO is loaded with the value of TC when there 0 Table 295 is an event on the CT32B0_CAP0 input CR1 RO 0x02C Capture Register 1 CR1 is loaded with the value of TC when there 0 Table 295 is an event on the CT32B0_CAP1 input s 0x034 Reserved 7 x 0x038 EMR R W 0x03C External Match Register The EMR controls the match function and 0 Table 296 the external match pins CT32Bn_MAT 3 0 0x040 Reserved 0x06C CTCR R W 0x070 Count Control Register The CTCR selects between Timer and 0 Table 298 Counter mode and in Counter mode selects the signal and edge s for counting PWMC R W 0x074 PWM Control Register The PWMCON enables PWM mode for the 0 Table 299 external match pins CT32Bn_MAT 3 0 1 Reset value reflects the data stored in used bits only It does not include reserved bits content UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 312 of 404 NXP Semiconductors U M1 0524 Chapter 16 LPC1315 16 17 45 46 47 32 bit counter timers CT32B0 1 Table 286 Register overview 32 bit counter timer 1 CT32B1 base address 0x4001 8000 Name Access Address Description Reset Reference offset value IR R W 0x000 Interrupt Register The IR can be written to clear interrupts The IR 0 Table 287 can be read to identify which of eight possible interrupt sources are pending
83. CT16Bn_CAP0 falling edge a sequence of 1 then 0 on CT16Bn_CAPO will 0 cause CRO to be loaded with the contents of TC Enabled Disabled Interrupt on CT16Bn_CAPO0 event a CRO load due to a CT16Bn_CAPO event will 0 generate an interrupt Enabled Disabled Capture on CT16Bn_CAP1 rising edge a sequence of 0 then 1 on CT16Bn_CAP1 will 0 cause CRO to be loaded with the contents of TC Enabled Disabled Capture on CT16Bn_CAP1 falling edge a sequence of 1 then 0 on CT16Bn_CAP1 will 0 cause CRO to be loaded with the contents of TC Enabled Disabled Interrupt on CT16Bn_CAP1 event a CRO load due to a CT16Bn_CAP1 event will 0 generate an interrupt Enabled Disabled Reserved user software should not write ones to reserved bits The value read froma NA reserved bit is not defined UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 302 of 404 NXP Semiconductors U M1 0524 15 7 9 15 7 10 Chapter 15 LPC1315 16 17 45 46 47 16 bit counter timers CT16B0 1 Capture Registers Each Capture register is associated with a device pin and may be loaded with the counter timer value when a specified event occurs on that pin The settings in the Capture Control Register register determine whether the capture function is enabled and whether a capture event happens on the rising edge of the associated pi
84. CTI 0x1 3 THRE Interrupt 0x0 4 Modem status 5 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 7 6 FIFOEN These bits are equivalent to FCR 0 0 ABEOINT End of auto baud interrupt True if auto baud has finished 0 successfully and interrupt is enabled 9 ABTOINT Auto baud time out interrupt True if auto baud has timed 0 out and interrupt is enabled 31 10 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 207 of 404 NXP Semiconductors U M1 0524 UM10524 Chapter 12 LPC1315 16 17 45 46 47 USART Bits IIR 9 8 are set by the auto baud function and signal a time out or end of auto baud condition The auto baud interrupt conditions are cleared by setting the corresponding Clear bits in the Auto baud Control Register If the IntStatus bit is one and no interrupt is pending and the Intld bits will be zero If the IntStatus is 0 a non auto baud interrupt is pending in which case the Intld bits identify the type of interrupt and handling as described in Table 210 Given the status of IIR 3 0 an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt The IIR must be read in order
85. CTS functional timing All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 213 of 404 NXP Semiconductors U M1 0524 Chapter 12 LPC1315 16 17 45 46 47 USART UART1 TX bits0 7 start bits0 7 bitsO 7 CTS1 pin Fig 17 Auto CTS Functional Timing During transmission of the second character the CTS signal is negated The third character is not sent thereafter The USART maintains 1 on TXD as long as CTS is negated high As soon as CTS is asserted transmission resumes and a start bit is sent followed by the data bits of the next character 12 5 9 USART Line Status Register Read Only The LSR is a read only register that provides status information on the USART TX and RX blocks Table 215 USART Line Status Register Read only LSR address 0x4000 8014 bit description Bit Symbol Value Description Reset Value 0 RDR Receiver Data Ready LSR 0 is set when the RBR holds an 0 unread character and is cleared when the USART RBR FIFO is empty 0 RBR is empty RBR contains valid data 1 OE Overrun Error The overrun error condition is set as soon as it 0 occurs ALSR read clears LSR 1 LSR 1 is set when USART RSR has a new character assembled and the USART RBR FIFO is full In this case the USART RBR FIFO will not be overwritten and the character in the USART RSR will be lost 0 Overrun error status
86. Chapter 23 Supplementary information address 0x4004 0010 SSPO and 0x4005 8010 SSP1 bit description 242 Table 239 SSP SPI Interrupt Mask Set Clear register IMSC address 0x4004 0014 SSPO and 0x4005 8014 SSP1 bit description 243 Table 240 SSP SPI Raw Interrupt Status register RIS address 0x4004 0018 SSPO and 0x4005 8018 SSP1 bit description 243 Table 241 SSP SPI Masked Interrupt Status register MIS address 0x4004 001C SSPO and 0x4005 801C SSP1 bit description 244 Table 242 SSP SPI interrupt Clear Register ICR address 0x4004 0020 SSPO and 0x4005 8020 SSP1 bit description 0 00 e 244 Table 243 I C bus pin description 254 Table 244 Register overview 12C base address 0x4000 0000 ices e bei iodi seriei ned Saeed 254 Table 245 l2 C Control Set register CONSET address 0x4000 0000 bit description 255 Table 246 I2C Status register STAT 0x4000 0004 bit description 00000 eee eee 257 Table 247 I C Data register DAT 0x4000 0008 bit description 000 eee eee 257 Table 248 I C Slave Address register 0 ADRO 0x4000 000C bit description 258 Table 249 I C SCL HIGH Duty Cycle register SCLH address 0x4000 0010 bit description 258 Table 250 I2C SCL Low duty cycle register SCLL 0x4000 0014 bit description 258
87. Chapter 7 LPC1315 16 17 45 46 47 I O configuration 7 4 33 I O configuration for pin PIO1_10 Table 88 I O configuration for pin PIO1_10 PIO1_10 address 0x4004 4088 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x1 to 0x7 are reserved 0 OxO PIO1_10 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 34 I O configuration for pin PIO1_11 Table 89 I O configuration for pin PIO1_11 PIO1_11 address 0x4004 408C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x1 to 0x7 are reserved 000 OxO PIO1_11 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable UM10524 All info
88. Clear the corresponding External Match bit output to 0 CT16Bn_MATm pin is LOW if pinned out Set the corresponding External Match bit output to 1 CT16Bn_MATm pin is HIGH if pinned out Toggle the corresponding External Match bit output UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 304 of 404 NXP Semiconductors U M1 0524 Chapter 15 LPC1315 16 17 45 46 47 16 bit counter timers CT16B0 1 15 7 11 Count Control Register The Count Control Register CTCR is used to select between Timer and Counter mode and in Counter mode to select the pin and edges for counting When Counter Mode is chosen as a mode of operation the CAP input selected by the CTCR bits 3 2 is sampled on every rising edge of the PCLK clock After comparing two consecutive samples of this CAP input one of the following four events is recognized rising edge falling edge either of edges or no changes in the level of the selected CAP input Only if the identified event occurs and the event corresponds to the one selected by bits 1 0 in the CTCR register will the Timer Counter register be incremented Effective processing of the externally supplied clock to the counter has some limitations Since two successive rising edges of the PCLK clock are used to identify only one edge on the CAP selected input the frequency of the CAP input can
89. Four breakpoints Four instruction breakpoints that can also be used to remap instruction addresses for code patches Two data comparators that can be used to remap addresses for patches to literal values e Two data watchpoints that can also be used as triggers e Supports JTAG boundary scan e Instrumentation Trace Macrocell allows additional software controlled trace 22 3 Introduction Debug functions are integrated into the ARM Cortex M3 Serial wire debug functions are supported The ARM Cortex M3 is configured to support up to four breakpoints and two watchpoints 22 4 Description Debugging with the LPC1315 16 17 45 46 47 uses the Serial Wire Debug mode Support for boundary scan is available Trace can be done using the Serial Wire Output When the Serial Wire Output is used less data can be traced but it uses no application related pins Note that the trace function available for the ARM Cortex M3 is functionally very different than the trace that was available for previous ARM7 based devices 22 5 Pin description The tables below indicate the various pin functions related to debug Some of these functions share pins with other functions which therefore may not be used at the same time Trace using the Serial Wire Output has limited bandwidth UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 384 of 404
90. HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 7 ADMODE Selects Analog Digital mode 1 0 Analog input mode 1 Digital functional mode 8 FILTR Selects 10 ns input glitch filter 0 0 Filter disabled 1 Filter enabled 9 Reserved 0 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 13 I O configuration for pin TMS PIO0O_12 Table 68 I O configuration for pin TMS PIO0_12 AD1 CT32B1_CAP0 TMS_PIO0_12 address 0x4004 4030 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x4 to 0x7 are reserved 0 0x0 TMS 0x1 PIOO_12 0x2 AD1 0x3 CT32B1_CAPO UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 74 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 68 I O configuration for pin TMS PIO0_12 AD1 CT32B1_CAP0 TMS_PIO0_12 address 0x4004 4030 bit description Bit Symbol Value Description Reset value 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Di
91. ISP Read Memory command Command R Input Start Address Address from where data bytes are to be read This address should be a word boundary Number of Bytes Number of bytes to be read Count should be a multiple of 4 Return Code CMD _SUCCESS followed by lt actual data UU encoded gt ADDR_ERROR Address not on word boundary ADDR_NOT_MAPPED COUNT_ERROR Byte count is not a multiple of 4 PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to read data from RAM or flash memory This command is blocked when code read protection is enabled Example R 268435456 4 lt CR gt lt LF gt reads 4 bytes of data from address 0x1000 0000 Prepare sector s for write operation lt start sector number gt lt end sector number gt This command makes flash write erase operation a two step process All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 365 of 404 NXP Semiconductors UM10524 UM10524 21 13 7 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming Table 342 ISP Prepare sector s for write operation command Command Input Return Code Description Example P Start Sector Number End Sector Number Should be greater than or equal to start sector number CMD_SUCCESS BUSY INVALID_SECTOR PARAM_ERROR This command must be executed before exec
92. If the clock source is not locked the watchdog oscillator must be powered by using the PDSLEEPCFG register Do not lock the clock source with the IRC selected All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 36 of 404 NXP Semiconductors U M1 0524 Chapter 3 LPC1315 16 17 45 46 47 System control block 3 9 2 Active mode In Active mode the ARM Cortex M3 core and memories are clocked by the system clock and peripherals are clocked by the system clock or a dedicated peripheral clock The chip is in Active mode after reset and the default power configuration is determined by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers The power configuration can be changed during run time 3 9 2 1 Power configuration in Active mode Power consumption in Active mode is determined by the following configuration choices e The SYSAHBCLKCTRL register controls which memories and peripherals are running Table 19 e The power to various analog blocks PLL oscillators the ADC the BOD circuit and the flash block can be controlled at any time individually through the PDRUNCFG register Table 42 e The clock source for the system clock can be selected from the IRC default the system oscillator or the watchdog oscillator see Figure 3 and related registers e The system clock frequency can be selected by the SYSPLLCT
93. Input JTAG Test Reset The TRST pin can be used to reset the test logic within the debug logic This pin includes an internal pull up and is used for JTAG boundary scan when the RESET pin is LOW 22 6 Functional description UM10524 22 6 1 22 6 2 Debug limitations Important Due to limitations of the ARM Cortex M3 integration the LPC1315 16 17 45 46 47 cannot wake up in the usual manner from Deep sleep mode It is recommended not to use this mode during debug Another issue is that debug mode changes the way in which reduced power modes work internal to the ARM Cortex M3 CPU and this ripples through the entire system These differences mean that power measurements should not be made while debugging the results will be higher than during normal operation in an application During a debugging session the System Tick Timer is automatically stopped whenever the CPU is stopped Other peripherals are not affected Debug connections for SWD For debugging purposes it is useful to provide access to the ISP entry pin PIOO_1 This pin can be used to recover the part from configurations which would disable the SWD port such as improper PLL configuration reconfiguration of SWD pins as ADC inputs entry into Deep power down mode out of reset etc This pin can be used for other functions such as GPIO but it should not be held LOW on power up or reset All information provided in this document is subject to legal disclaim
94. LOW by a device on the bus no further serial transfer is possible and the problem must be resolved by the device that is pulling the SCL bus line LOW Typically the SDA line may be obstructed by another device on the bus that has become out of synchronization with the current bus master by either missing a clock or by sensing a noise pulse as a clock In this case the problem can be solved by transmitting additional clock pulses on the SCL line see Figure 46 The 12C interface does not include a dedicated time out timer to detect an obstructed bus but this can be implemented using another timer in the system When detected software can force clocks up to 9 may be required on SCL until SDA is released by the offending device At that point the slave may still be out of synchronization so a START should be generated to insure that all 12C peripherals are synchronized STA flag 9 SDA line p p SCL line ke start gt condition 1 3 Successful attempt to send a START condition State 08H is entered ae Unsuccessful attempt to send a START condition SDA line is released D Fig 46 Recovering from a bus obstruction caused by a LOW level on SDA Bus error A bus error occurs when a START or STOP condition is detected at an illegal position in the format frame Examples of illegal positions are during the serial transfer of an address byte a data bit or an acknowledge bit The 12
95. LPC1346FHN33 48 8 2 4 yes 2 1 8 26 LPC1346FBD48 48 8 2 4 yes 2 1 8 40 LPC1347FHN33 64 8 2 2 4 yes 2 1 8 26 LPC1347FBD48 64 8 2 2 4 yes 2 1 8 40 LPC1347FBD64 64 8 2 2 4 yes 2 1 8 51 LPC1315FHN33 32 8 2 no 2 1 8 28 LPC1315FBD48 32 8 2 no 2 1 8 40 LPC1316FHN33 48 8 4 no 2 1 8 28 LPC1316FBD48 48 8 4 no 2 1 8 40 LPC1317FHN33 64 8 2 4 no 2 1 8 28 LPC1317FBD48 64 8 2 4 no 2 1 8 40 LPC1317FBD64 64 8 2 4 no 2 1 8 51 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 6 of 404 NXP Semiconductors U M1 0524 Chapter 1 LPC1315 16 17 45 46 47 Introductory information 1 4 Block diagram SWD JTAG LPC1315 16 17 LPC1345 46 47 TEST DEBUG INTERFACE XTALIN XTALOUT RESET CLOCK GENERATION POWER CONTROL CLKOUT SYSTEM FUNCTIONS ARM CORTEX M3 SRAM ROM System bus 8 10 12 kB kA save slave slave GPIO ports 0 1 Bo C AHB LITE BUS slave CONTROLLER N tPC1345 46147 USB_DP USB_DM USB_VBUS USB_FTOGGLE slave USB_CONNECT AHB TO APB AXD BRIDGE P USART TT me RD at Don PSRS TH SMARTCARD INTERFACE E C wia Ef AD 7 0 SCLK SCL SDA 16 bit COUNTER TIMER 0 C CT16B0_CAP 1 0 2 7 He 16 bit COUNTER TIMER 1 MISOO MOSIO CT16B1_CAP 1 0 2 SCK1 SSEL1 see ete ses couvrentiveno K Meet esi 2 NTER TIMER CT32B0_CAP 1 0 ees 2 l CTo2B1MATIS 0 32
96. LSB of the ADR register is the General Call bit When this bit is set the General Call address 0x00 is recognized If these registers contain 0x00 the 12C will not acknowledge any address on the bus All four registers will be cleared to this disabled state on reset also see Table 248 Table 254 I2C Slave Address registers ADR 1 2 3 0x4000 00 20 24 28 bit description Bit Symbol Description Reset value 0 GC General Call enable bit 0 7 1 Address The IC device address for slave mode 0x00 31 8 Reserved The value read from a reserved bit is not defined 0 I2C Data buffer register DATA_BUFFER In monitor mode the 12C module may lose the ability to stretch the clock stall the bus if the ENA_SCL bit is not set This means that the processor will have a limited amount of time to read the contents of the data received on the bus If the processor reads the DAT shift register as it ordinarily would it could have only one bit time to respond to the interrupt before the received data is overwritten by new data To give the processor more time to respond a new 8 bit read only DATA_BUFFER register will be added The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits 8 bits of data plus ACK or NACK has been received on the bus This means that the processor will have nine bit transmission times to respond to the interrupt and read the data before it
97. O configuration for pin PlIOO_16 AD5 CT32B1_MAT3 WAKEUP PIOO_ 16 address 0x4004 4040 bit description Bit Symbol Value Description Reset value 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 7 ADMODE Selects Analog Digital mode 1 0 Analog input mode 1 Digital functional mode 8 FILTR Selects 10 ns input glitch filter 0 0 Filter disabled 1 Filter enabled 9 Reserved 0 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 18 I O configuration for pin PIOO_17 Table 73 1 O configuration for pin PlIOO_17 RTS CT32B0_CAP0 SCLK PIO0_17 address 0x4004 4044 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x4 to 0x7 are reserved 0 0x0 PIOO_17 0x1 RTS 0x2 CT32B0_CAPO 0x3 SCLK UART synchronous clock UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 79 of 404 NXP Semiconduct
98. O functionality 0x2 Fast mode Plus 12C 0x3 Reserved 31 10 Reserved 7 4 7 I O configuration for pin PIOO_6 Table 62 I O configuration for pin PIO0_6 USB_CONNECT SCKO PIO0_6 address 0x4004 4018 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x3 to 0x7 are reserved 0 0x0 PIOO_6 0x1 USB_CONNECT 0x2 SCKO UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 69 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 62 I O configuration for pin PlOO_6 USB_CONNECT SCKO PIO0_6 address 0x4004 4018 bit description Bit Symbol Value Description Reset value 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 8 I O configuration for pin PIOO_7 Table 63 I O configu
99. Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 42 1 O configuration for pin PIO1_20 Table 97 I O configuration for pin PIO1_20 DSR SCK1 PIO1_20 address 0x4004 40B0 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x3 to 0x7 are reserved 0 0x0 PIO1_20 0x1 DSR 0x2 SCK1 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 001 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 97 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 97 I O configuration for pin PIO1_20 DSR SCK1 PIO1_20 address 0x4004 40B0 bit description Bit Symbol Value Description Reset value 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7
100. RS 485 EIA 485 feature allows the USART to be configured as an addressable slave The addressable slave is one of multiple slaves controlled by a single master The USART master transmitter will identify an address character by setting the parity 9th bit to 1 For data characters the parity bit is set to 0 Each USART slave receiver can be assigned a unique address The slave can be programmed to either manually or automatically reject data following an address which is not theirs RS 485 EIA 485 Normal Multidrop Mode Setting the RS485CTRL bit 0 enables this mode In this mode an address is detected when a received byte causes the USART to set the parity error and generate an interrupt If the receiver is disabled RS485CTRL bit 1 1 any received data bytes will be ignored and will not be stored in the RXFIFO When an address byte is detected parity bit 1 it will be placed into the RXFIFO and an Rx Data Ready Interrupt will be generated The processor can then read the address byte and decide whether or not to enable the receiver to accept the following data While the receiver is enabled RS485CTRL bit 1 0 all received bytes will be accepted and stored in the RXFIFO regardless of whether they are data or address When an address character is received a parity error interrupt will be generated and the processor can decide whether or not to disable the receiver RS 485 EIA 485 Auto Address Detection
101. Reserved PIO1_7 read write 0x07C I O configuration for pin PIO1_7 0x0000090 Table 86 PIO1_8 read write 0x080 I O configuration for pin PIO1_8 0x0000090 Table 87 0x084 Reserved PIO1_10 read write 0x088 I O configuration for pin PIO1_10 0x0000090_ Table 88 PIO1_11 read write 0x08C I O configuration for pin PIO1_ 11 0x0000090 Table 89 0x090 Reserved 5 PIO1_13 Access 0x094 I O configuration for 0x0000090 Table 90 PIO1_13 DTR CT16B0O_MATO TXD UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 64 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 55 Register overview IOCON base address 0x4004 4000 Name Access Address Description Reset value Reference offset PIO1_14 Access 0x098 I O configuration for 0x0000090 Table 91 PIO1_14 DSR CT16B0_MAT1 RXD PIO1_15 read write 0x09C I O configuration for pin PIO1_15 DCD 0x0000090 Table 92 CT16B0_MAT2 SCK1 PIO1_16 read write 0x0A0 I O configuration for pin 0x0000090 Table 93 P1O1_16 RI CT16BO_CAPO PIO1_17 Access 0x0A4 I O configuration for 0x0000090 Table 94 P1O1_17 CT16BO_CAP1 RXD PIO1_18 Access 0x0A8 I O configuration for 0x0000090 Table 95 PIO1_18 CT16B1_CAP1 TXD PIO1_19 read write Ox0AC I O configuration for pin PIO1_19 DTR SSEL1 0x0000090 Table 96 PIO1_20 read write O0x0BO I O configuration for pin PIO1_20 DS
102. STAT DAT ADRO SCLH SCLL CONCLR MMCTRL ADR1 UM10524 Access Address Description Reset Reference R W RO R W R W R W R W WO R W R W offset valuell 0x000 12C Control Set Register When a one is written toa bit 0x00 Table 245 of this register the corresponding bit in the 12C control register is set Writing a zero has no effect on the corresponding bit in the 12C control register 0x004 12C Status Register During 1 C operation this register OxF8 Table 246 provides detailed status codes that allow software to determine the next action needed 0x008 12C Data Register During master or slave transmit mode 0x00 Table 247 data to be transmitted is written to this register During master or slave receive mode data that has been received may be read from this register 0x00C I2C Slave Address Register 0 Contains the 7 bit slave 0x00 Table 248 address for operation of the 12C interface in slave mode and is not used in master mode The least significant bit determines whether a slave responds to the General Call address 0x010 SCH Duty Cycle Register High Half Word Determines 0x04 Table 249 the high time of the 12C clock 0x014 SCL Duty Cycle Register Low Half Word Determines 0x04 Table 250 the low time of the I C clock I2nSCLL and I2nSCLH together determine the clock frequency generated by an 12C master and certain times used in slave mode 0x018 I2C Control Clear Register When a one
103. Status Register 243 respect to SK in Microwire mode 251 13 6 8 SSP SPI Masked Interrupt Status Register 243 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller 14 1 How to read this chapter 252 14 7 7 2 Loss of arbitration in Monitor mode 261 14 2 Basic configuration 0 252 14 7 8 C Slave Address registers ADR 1 2 3 261 14 3 Features 252 14 7 9 12C Data buffer register DATA_BUFFER 261 N oe Aha ele Se tee 14 7 10 12C Mask registers MASK O 1 2 3 262 14 4 Applications 252 14 81 2C operating modes 262 z f ing modes pi 1 po RE eee 14 8 1 Master Transmitter mode 262 S g gt files een E 14 8 2 Master Receiver mode 263 14 6 Pin description eeee eee ee 254 14 8 3 Slave Receiver mode 264 14 7 Register description 00040 254 14 8 4 Slave Transmitter mode 265 14 7 1 12C Control Set register CONSET 255 14 91 2C implementation and operation 265 14 7 2 re Status register STAT s gt 257 149 1 Input filters and output stages 266 14 7 3 ae Data register DAT dg te GN Gre Se a ee 257 14 9 2 Address Registers ADRO to ADR3 267 14 7 4 12C Slave Address register 0 ADRO EEEE 258 14 9 3 Address mask registers MASKO to MASK3 267 14 7 5 IC SCL HIGH and LOW duty cycle registers 14 9 4 Comparator a na 26
104. Table 146 GPIO toggle port 0 register NOTO address 0x5000 2300 bit description Bit Symbol Description Reset Access value 31 0 NOTPO Toggle output bits NA WO 0 no operation 1 Toggle output bit Table 147 GPIO toggle port 1 register NOT1 address 0x5000 2304 bit description Bit Symbol Description Reset Access value 31 0 NOTP1 Toggle output bits NA WO 0 no operation 1 Toggle output bit 9 6 Functional description 9 6 1 Reading pin state Software can read the state of all GPIO pins except those selected for analog input or output in the I O Configuration logic A pin does not have to be selected for GPIO in I O Configuration in order to read its state There are four ways to read pin state e The state of a single pin can be read with 7 high order zeros from a Byte Pin register e The state of a single pin can be read in all bits of a byte halfword or word from a Word Pin register e The state of multiple pins in a port can be read as a byte halfword or word from a PORT register e The state of a selected subset of the pins in a port can be read from a Masked Port MPORT register Pins having a 1 in the port s Mask register will read as 0 from its MPORT register 9 6 2 GPIO output Each GPIO pin has an output bit in the GPIO block These output bits are the targets of write operations to the pins Two conditions must be met in order for a pin s output bit to be driv
105. Table 241 ICR WO 0x020 SSPICR Interrupt Clear Register NA Table 242 Table 233 Register overview SSP SPI1 base address 0x4005 8000 Name Access Address Description Reset Reference offset value CRO R W 0x000 Control Register 0 Selects the serial clock rate bus type anddata 0 Table 234 size CR1 R W 0x004 Control Register 1 Selects master slave and other modes 0 Table 235 DR R W 0x008 Data Register Writes fill the transmit FIFO and reads empty the 0 Table 236 receive FIFO SR RO 0x00C Status Register 0x0000 Table 237 0003 CPSR R W 0x010 Clock Prescale Register 0 Table 238 IMSC R W 0x014 Interrupt Mask Set and Clear Register 0 Table 239 RIS RO 0x018 Raw Interrupt Status Register 0x0000 Table 240 0008 MIS RO 0x01C Masked Interrupt Status Register 0 Table 241 ICR WO 0x020 SSPICR Interrupt Clear Register NA Table 242 13 6 1 SSP SPI Control Register 0 This register controls the basic operation of the SSP SPI controller UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 239 of 404 NXP Semiconductors UM10524 UM10524 13 6 2 Chapter 13 LPC1315 16 17 45 46 47 SSP SPI Table 234 SSP SPI Control Register 0 CRO address 0x4004 0000 SSPO and 0x4005 8000 SSP1 bit description Bit Symbol 3 0 DSS 5 4 FRF 6 CPOL 7 CPHA 15 8 SCR 31 16 Value 0x3 0x4 0x5 0x6 0x7 0x8 0x9 OxA
106. Table 251 SCLL SCLH values for selected 12C clock Values iat yet te ahs dockins Rape Gao ee ahs a 259 Table 252 I2 C Control Clear register CONCLR 0x4000 0018 bit description 259 Table 253 I2C Monitor mode control register MMCTRL 0x4000 001C bit description 260 Table 254 I C Slave Address registers ADR 1 2 3 0x4000 00 20 24 28 bit description 261 Table 255 1 C Data buffer register DATA_BUFFER 0x4000 002C bit description 262 Table 256 I C Mask registers MASK O 1 2 3 0x4000 00 80 34 38 3C bit description 262 Table 257 CONSET used to configure Master mode 263 Table 258 CONSET used to configure Slave mode 264 Table 259 Abbreviations used to describe an 12C Operation 0002 cee eee eee 270 Table 260 CONSET used to initialize Master Transmitter MOIE ia aae a e ra aa ara Er r 270 Table 261 Master Transmitter mode 272 Table 262 Master Receiver mode 275 Table 263 ADR usage in Slave Receiver mode 277 Table 264 CONSET used to initialize Slave Receiver MOE skies beds Ga ea wen eho da eee we 277 Table 265 Slave Receiver mode 278 Table 266 Slave Transmitter mode 282 Table 267 Miscellaneous States 284 Table 268 Counter timer pin description 296 Table 269 Register overview 16 bit counter timer 0 CT16B0 base address 0x4000
107. Table 27 CLKOUT clock source select CLKOUTSEL 0x4004 4000 2 eee eee eee 63 address 0x4004 80E0 bit description 25 Table 56 I O configuration for pin RESET PIOO_0 Table 28 CLKOUT clock divider CLKOUTDIV address RESET_PIOO_0 address 0x4004 4000 bit 0x4004 80E8 bit description 25 description 200 0 eee eee eee 65 Table 29 POR captured PIO status 0 PIOPORCAPO Table 57 I O configuration for pin address 0x4004 8100 bit description 25 PIOO_1 CLKOUT CT32B0_MAT2 USB_FTOGGL Table 30 POR captured PIO status 1 PIOPORCAP1 E PIOO_1 address 0x4004 4004 bit UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 389 of 404 NXP Semiconductors UM10524 Chapter 23 Supplementary information description iee eener stacked accu een eae 66 PIO0_19 TXD CT32B0_MAT1 PIO0_19 address Table 58 I O configuration for pin 0x4004 404C bit description 81 PIOO_2 SSEL0 CT16B0O_CAPO PIOO_ 2 Table 76 I O configuration for pin PlOO_20 CT16B1_CAPO address 0x4004 4008 bit description 67 PIOO_20 address 0x4004 4050 bit Table 59 I O configuration for pin PlOO_3 USB_VBUS description 024 2 cra twa dead dae eta 82 PIOO_3 address 0x4004 400C bit Table 77 I O configuration for pin description 0 00 eee eee eee 68 PIOO_21 CT16B1_MATO MOSI1 PIOO_21 Table
108. UART_PCLK can be shut down by setting the DIV field to zero All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 22 of 404 NXP Semiconductors U M1 0524 3 5 17 3 5 18 3 5 19 Chapter 3 LPC1315 16 17 45 46 47 System control block Table 21 UART clock divider UARTCLKDIV address 0x4004 8098 bit description Bit Symbol Description Reset value 7 0 DIV UART_PCLK clock divider values 0 0 Disable UART_PCLK 1 Divide by 1 to 255 Divide by 255 31 8 Reserved SSP1 clock divider register SSP1CLKDIV This register configures the SSP1 peripheral clock SSP1_PCLK The SSP1_PCLK can be shut down by setting the DIV bits to 0x0 Table 22 SSP1 clock divider SSP1CLKDIV address 0x4004 809C bit description Bit Symbol Description Reset value 7 0 DIV SSP1_PCLK clock divider values 0x00 0 Disable SSP1_PCLK 1 Divide by 1 to 255 Divide by 255 31 8 Reserved 0x00 ARM trace clock divider register TRACECLKDIV This register configures the ARM trace clock The ARM trace clock can be shut down by setting the DIV field to zero Table 23 ARM trace clock divider TRACECLKDIV address 0x4004 80AC bit description Bit Symbol Description Reset value 7 0 DIV ARM trace clock divider values 0x00 0 Disable TRACE_CLK 1 Divide by 1 to 255 Divide by 255 31 8 Reserved 0x00 SYSTICK clock div
109. UM10524 Table 211 USART FIFO Control Register Write only FCR address 0x4000 8008 bit description 210 Table 212 USART Line Control Register LCR address 0x4000 800C bit description Table 213 USART Modem Control Register MCR address 0x4000 8010 bit description 211 Table 214 Modem status interrupt generation 213 Table 215 USART Line Status Register Read only LSR address 0x4000 8014 bit description 214 Table 216 USART Modem Status Register MSR address 0x4000 8018 bit description 216 Table 217 USART Scratch Pad Register SCR address 0x4000 801C bit description 216 Table 218 USART Auto baud Control Register ACR address 0x4000 8020 bit description 217 Table 219 USART IrDA Control Register ICR 0x4000 8024 bit description 220 Table 220 IrDA Pulse Width 220 Table 221 USART Fractional Divider Register FDR address 0x4000 8028 bit description 221 Table 222 Fractional Divider setting look up table 224 Table 223 USART Oversampling Register OSR address 0x4000 802C bit description 225 Table 224 USART Transmit Enable Register TER address 0x4000 8030 bit description 226 Table 225 USART Half duplex enable register HDEN addresses 0x4000 8040 bit description 226 Table 226 USART Smart Card Interface Control register SCICTRL address 0x4000 8048
110. USART interrupt 22 USB_IRQ USB_IRQ interrupt 23 USB_FIQ USB_FIQ interrupt 24 ADC ADC interrupt 25 WWDT WWDT interrupt 26 BOD BOD interrupt 27 FLASH Flash interrupt 28 29 30 USB_WAKEUP USB _WAKEUP interrupt 31 Flag s Reserved Reserved Reserved Tx FIFO half empty Rx FIFO half full Rx Timeout Rx Overrun SI state change Match 0 2 Capture 0 Match 0 1 Capture 0 Match 0 3 Capture 0 Match 0 3 Capture 0 Tx FIFO half empty Rx FIFO half full Rx Timeout Rx Overrun Rx Line Status RLS Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CTI End of Auto Baud ABEO Auto Baud Time Out ABTO Modem control interrupt USB IRQ interrupt USB FIQ interrupt A D Converter end of conversion Windowed Watchdog interrupt WDINT Brown out detect Reserved Reserved USB wake up interrupt Reserved All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 58 of 404 NXP Semiconductors U M1 0524 Chapter 6 LPC1315 16 17 45 46 47 NVIC 6 5 Register description See the ARM Cortex M3 technical reference manual UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 59 of 404 UM10524 Chapter 7 LPC1315 16
111. USB device stack Returns Nothing StallEpo void void USBD_CORE_API StallEp0 USBD_HANDLE_T hUsb Function to set EPO state machine in stall state This function is called by USB stack and the application layer to generate STALL signalling on EPO endpoint This function will also reset the EPOData buffer Remark This interface is provided to users to invoke this function in other scenarios which are not handle by current stack In most user applications this function is not called directly Also this function can be used by users who are selectively modifying the USB device stack s standard handlers through callback interface exposed by the stack Parameters 1 hUsb Handle to the USB device stack Returns Nothing 11 5 30 USBD_DFU_API DFU class API functions structure This module exposes functions which interact directly with USB device controller hardware UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 177 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 195 USBD_DFU_API class structure Member Description GetMemSize uint32_t uint32_t USBD_DFU_API GetMemSize USBD_DFU_INIT_PARAM_T param Function to determine the memory required by the DFU function driver module This function is called by application layer before calling pUsbApi gt dfu gt Init to
112. USB_CONNECT USB_FTOGGLE USB_DP USB_DM Direction Description 1 0 1 0 Vgus Status input When this function is not enabled via its corresponding IOCON register it is driven HIGH internally SoftConnect control signal USB 1 ms SoF signal Positive differential data Negative differential data 10 6 Register description Table 151 Register overview USB base address 0x4008 0000 Name Access Address Description Reset Reference offset value DEVCMDSTAT R W 0x000 USB Device Command Status 0x0000080 Table 152 register 0 INFO R W 0x004 USB Info register 0 Table 153 EPLISTSTART R W 0x008 USB EP Command Status List 0 Table 154 start address DATABUFSTART R W 0x00C USB Data buffer start address 0 Table 155 LPM R W 0x010 Link Power Management 0 Table 156 register EPSKIP R W 0x014 USB Endpoint skip 0 Table 157 EPINUSE R W 0x018 USB Endpoint Buffer in use 0 Table 158 EPBUFCFG R W 0x01C USB Endpoint Buffer 0 Table 159 Configuration register INTSTAT R W 0x020 USB interrupt status register 0 Table 160 INTEN R W 0x024 USB interrupt enable register 0 Table 161 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 139 of 404 NXP Semiconductors UM10524 Chapter 10 LPC1345 46 47 USB2 0 device controller Table 151 Register overview USB base address 0x4008 0000 Name INTSETSTAT INTROUTING
113. a brief summary of each of the counter timer related pins Table 268 Counter timer pin description Pin Type Description CT16BO_CAP 1 0 Input Capture Signal CT16B1_CAP 1 0 A transition on a capture pin can be configured to load the Capture Register with the value in the counter timer and optionally generate an interrupt Counter Timer block can select a capture signal as a clock source instead of the PCLK derived clock For more details see Section 15 7 11 CT16BO_MAT 1 0 Output External Match Outputs of CT16B0 1 CT16B1_MAT 1 0 When a match register of CT16B0 1 MR1 0 equals the timer counter TC this output can either toggle go LOW go HIGH or do nothing The External Match Register EMR and the PWM Control Register PWMCON control the functionality of this output 15 7 Register description UM10524 The 16 bit counter timer0O contains the registers shown in Table 269 and the 16 bit counter timer1 contains the registers shown in Table 270 More detailed descriptions follow All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 296 of 404 NXP Semiconductors U M1 0524 Chapter 15 LPC1315 16 17 45 46 47 16 bit counter timers CT16B0 1 Table 269 Register overview 16 bit counter timer 0 CT16B0 base address 0x4000 C000 Name Access Address Description Reset Reference offset valuel IR R
114. allocate memory used by DFU function driver module The application should allocate the memory which is accessible by USB controller DMA controller Remark Some memory areas are not accessible by all bus masters Parameters 1 param Structure containing DFU function driver module initialization parameters Returns Returns the required memory size in bytes init ErrorCode_t ErrorCode_t USBD_DFU_API init USBD_HANDLE_T hUsb USBD_DFU_INIT_PARAM_T param uint32_t init_state Function to initialize DFU function driver module This function is called by application layer to initialize DFU function driver module hUsbHandle to the USB device stack paramStructure containing DFU function driver module initialization parameters Parameters 1 hUsb Handle to the USB device stack 2 param Structure containing DFU function driver module initialization parameters Returns Returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4 byte aligned or smaller than required 3 ERR_API_INVALID_PARAM2 Either DFU_Write or DFU_Done or DFU_Read callbacks are not defined 4 ERR_USBD_BAD_DESC USB_DFU_DESCRIPTOR_TYPE is not defined immediately after interface descriptor wTransferSize in descriptor doesn t match the value passed in param gt wTransferSize DFU_Detach is not defined while USB_DFU_WILL_DETACH is set in DFU descriptor 5 ERR_U
115. and WDWINDOW 5 LOCK A 1 in this bit prevents disabling or powering down the 0 clock source selected by bit 0 of the WOCLKSRC register and also prevents switching to a clock source that is disabled or powered down This bit can be set once by software and is only cleared by any reset Remark If this bit is one and the WWDT clock source is the IRC when Deep sleep or Power down modes are entered the IRC remains running thereby increasing power consumption in Deep sleep mode and potentially preventing the part from entering Power down mode correctly see Section 17 7 31 6 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined Once the WDEN WDPROTECT or WDRESET bits are set they can not be cleared by software Both flags are cleared by an external reset or a Watchdog timer reset WDTOF The Watchdog time out flag is set when the Watchdog times out when a feed error occurs or when PROTECT 1 and an attempt is made to write to the TC register This flag is cleared by software writing a 0 to this bit WDINT The Watchdog interrupt flag is set when the Watchdog counter reaches the value specified by WARNINT This flag is cleared when any reset occurs and is cleared by software by writing a 0 to this bit In all power modes except Deep power down mode a Watchdog reset or interrupt can occur when the watchdog is running and has an operating clock source The watchdog osci
116. are either divided by 2xP by the programmable post divider to create the output clocks or are sent directly to the outputs The main output clock is then divided by M by the programmable feedback divider to generate the feedback clock The output signal of the phase frequency detector is also monitored by the lock detector to signal when the PLL has locked on to the input clock UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 42 of 404 NXP Semiconductors U M1 0524 3 10 1 3 10 2 3 10 3 3 10 4 UM10524 Chapter 3 LPC1315 16 17 45 46 47 System control block Lock detector The lock detector measures the phase difference between the rising edges of the input and feedback clocks Only when this difference is smaller than the so called lock criterion for more than eight consecutive input clock periods the lock output switches from low to high A single too large phase difference immediately resets the counter and causes the lock signal to drop if it was high Requiring eight phase measurements in a row to be below a certain figure ensures that the lock detector will not indicate lock until both the phase and frequency of the input and feedback clocks are very well aligned This effectively prevents false lock indications and thus ensures a glitch free lock signal Power down control To reduce the power co
117. are set This bit can be used by software when handling isochronous endpoints Software can clear this bit by writing a one to it 31 DEV_INT Device status interrupt This bit is set by HW when one of the bits in the 0 R WC Device Status Change register are set Software can clear this bit by writing a one to it 10 6 10 USB interrupt enable register INTEN Table 161 USB interrupt enable register INTEN address 0x4008 0024 bit description Bit Symbol Description Reset Access value 9 0 EP_INT_EN If this bit is set and the corresponding USB 0 R W interrupt status bit is set a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit 29 10 Reserved 0 RO 30 FRAME_INT_EN lf this bit is set and the corresponding USB R W interrupt status bit is set a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit 31 DEV_INT_EN If this bit is set and the corresponding USB 0 R W interrupt status bit is set a HW interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing bit Oo UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 146 of 404 NXP Semiconductors UM10524 UM10524 10 6 11 USB set interrupt status register INTSETSTAT 10 6 12 10 6 13 Chapter 10 LPC 1
118. be a multiple of 4 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 369 of 404 NXP Semiconductors U M1 0524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming Table 350 ISP Compare command Command M Return Code CMD _SUCCESS Source and destination data are equal COMPARE_ERROR Followed by the offset of first mismatch COUNT_ERROR Byte count is not a multiple of 4 ADDR_ERROR ADDR_NOT_MAPPED PARAM_ERROR Description This command is used to compare the memory contents at two locations Compare result may not be correct when source or destination address contains any of the first 512 bytes starting from address zero First 512 bytes are re mapped to boot ROM Example M 8192 268468224 4 lt CR gt lt LF gt compares 4 bytes from the RAM address 0x1000 8000 to the 4 bytes from the flash address 0x2000 21 13 14 ReadUID Table 351 ReadUID command Command N Input None Return Code CMD_SUCCESS followed by four 32 bit words of a unique serial number in ASCII format The word sent at the lowest address is sent first Description This command is used to read the unique ID 21 13 15 ISP Return Codes Table 352 ISP Return Codes Summary Return Mnemonic Description Code 0 CMD_SUCCESS Command is executed successfully Sent by ISP handler only when command given by the ho
119. bit description 00020 cee eee 227 Table 227 USART RS485 Control register RS485CTRL address 0x4000 804C bit description Table 228 USART RS 485 Address Match register RS485ADRMATCH address 0x4000 8050 bit description reide iana i eee ee eee 228 Table 229 USART RS 485 Delay value register RS485DLY address 0x4000 8054 bit description 229 Table 230 USART Synchronous mode control register SYNCCTRL address 0x4000 8058 bit description 2 00 i cece ee eee 229 Table 231 SSP SPI pin descriptions 238 Table 232 Register overview SSP SPIO base address 0x4004 0000 2 2 220 0 5 239 Table 233 Register overview SSP SPI1 base address 0x4005 8000 2 2 0020 00 239 Table 234 SSP SPI Control Register 0 CRO address 0x4004 0000 SSPO and 0x4005 8000 SSP 1 bit description 0 00 eee 240 Table 235 SSP SPI Control Register 1 CR1 address 0x4004 0004 SSPO and 0x4005 8004 SSP1 bit description 0 00085 241 Table 236 SSP SPI Data Register DR address 0x4004 0008 SSPO and 0x4005 8008 SSP1 bit description 00085 241 Table 237 SSP SPI Status Register SR address 0x4004 000C SSPO and 0x4005 800C SSP1 bit description 200200 ee eee 242 Table 238 SSP SPI Clock Prescale Register CPSR UM10524 All information provided in this document is subject to legal disclaimers
120. bit is not defined SSP SPI Interrupt Clear Register Software can write one or more ones to this write only register to clear the corresponding interrupt conditions in the SPI controller Note that the other two interrupt conditions can be cleared by writing or reading the appropriate FIFO or disabled by clearing the corresponding bit in SSPIMSC registers Table 242 SSP SPI interrupt Clear Register ICR address 0x4004 0020 SSP0 and 0x4005 8020 SSP1 bit description Bit Symbol Description Reset Value 0 RORIC Writing a 1 to this bit clears the frame was received when NA RxFIFO was full interrupt 1 RTIC Writing a 1 to this bit clears the Rx FIFO was not empty and NA has not been read for a timeout period interrupt The timeout period is the same for master and slave modes and is determined by the SSP bit rate 32 bits at PCLK CPSDVSR x SCR 1 31 22 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 13 7 Functional description UM10524 13 7 1 Texas Instruments synchronous serial frame format Figure 23 shows the 4 wire Texas Instruments synchronous serial frame format supported by the SPI module All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 244 of 404 NXP Semiconductors U M1 0524 Chapter 13 LPC1315 16 17 45
121. bit will be set if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is successfully received for the control EPO If the IntOnNAK_CO is set this bit will also be set when a NAK is transmitted for the Control EPO OUT direction Software can clear this bit by writing a one to it Interrupt status register bit for the Control EPO IN direction This bit will be set if NBytes transitions to zero or the skip bit is set by software If the IntOnNAK_Cl is set this bit will also be set when a NAK is transmitted for the Control EPO IN direction Software can clear this bit by writing a one to it Interrupt status register bit for the EP1 OUT direction This bit will be set if the corresponding Active bit is cleared by HW This is done in case the programmed NBytes transitions to zero or the skip bit is set by software If the IntOnNAK_AO is set this bit will also be set when a NAK is transmitted for the EP1 OUT direction Software can clear this bit by writing a one to it Interrupt status register bit for the EP1 IN direction This bit will be set if the corresponding Active bit is cleared by HW This is done in case the programmed NBytes transitions to zero or the skip bit is set by software If the IntOnNAK_AI is set this bit will also be set when a NAK is transmitted for the EP1 IN direction Software can clear this bit by writing a one to it Interrupt status register bit for the EP2 OUT direction T
122. bits for the capture interrupts If an interrupt is generated then the corresponding bit in the IR will be HIGH Otherwise the bit will be LOW Writing a logic one to the corresponding IR bit will reset the interrupt Writing a zero has no effect Table 271 Interrupt Register IR address 0x4000 C000 CT16B0 and 0x4001 0000 CT16B1 bit description Bit Symbol Description Reset value 0 MROINT Interrupt flag for match channel 0 0 1 MRI1INT Interrupt flag for match channel 1 0 2 MR2INT Interrupt flag for match channel 2 0 3 MRS3INT Interrupt flag for match channel 3 0 4 CROINT Interrupt flag for capture channel 0 event 0 5 CRIINT Interrupt flag for capture channel 1 event 0 31 6 Reserved 15 7 2 Timer Control Register The Timer Control Register TCR is used to control the operation of the counter timer Table 272 Timer Control Register TCR address 0x4000 C004 CT16B0 and 0x4001 0004 CT16B1 bit description Bit Symbol Value Description Reset value 0 CEN Counter enable 0 0 The counters are disabled 1 The Timer Counter and Prescale Counter are enabled for counting 1 CRST Counter reset 0 0 Do nothing 1 The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK The counters remain reset until TCR 1 is returned to zero 31 Reserved user software should not write ones to reserved bits NA 2 The value read from a reserved bit is not defined 15 7 3 Timer Count
123. bus for peripherals The ARM Cortex M3 CPU also includes an internal prefetch unit that supports speculative branching Equipped with a highly flexible and configurable Full Speed USB 2 0 device controller available on the LPC 1345 46 47 this series brings unparalleled design flexibility and seamless integration to today s demanding connectivity solutions The peripheral complement of the LPC1315 16 1 7 45 46 47 includes up to 64 kB of flash memory 8 kB or 10 kB of SRAM data memory one Fast mode Plus 2C bus interface one RS 485 EIA 485 USART with support for synchronous mode and smart card interface two SSP interfaces four general purpose counter timers an 8 channel 12 bit ADC and up to 51 general purpose I O pins 1 2 Features e System ARM Cortex M3 r2p1 processor running at frequencies of up to 72 MHz ARM Cortex M3 built in Nested Vectored Interrupt Controller NVIC Non Maskable Interrupt NMI input selectable from several input sources System tick timer e Memory Upto 64 kB on chip flash program memory with a 256 byte page erase function In System Programming ISP and In Application Programming IAP via on chip bootloader software Flash updates via USB supported Up to 4kB on chip EEPROM data memory with on chip API support Upto 12 kB SRAM data memory 16kB boot ROM with API support for USB API power control EEPROM and flash IAP ISP UM10524 All information provided in this documen
124. by the CPU Table 305 Watchdog Timer Value register TV 0x4000 400C bit description Bit Symbol Description Reset Value 23 0 COUNT Counter timer value 0x00 OOFF 31 24 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined Watchdog Clock Select register Table 306 Watchdog Clock Select register CLKSEL 0x4000 4010 bit description Bit Symbol Value Description Reset Value 0 CLKSEL Selects source of WDT clock 0 0 IRC 1 Watchdog oscillator WDOSC 30 1 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 31 LOCK If this bit is set to one writing to this register does not affect bit 0 0 The clock source can only be changed by first clearing this bit then writing the new value of bit 0 Watchdog Timer Warning Interrupt register The WOWARNINT register determines the watchdog timer counter value that will generate a watchdog interrupt When the watchdog timer counter matches the value defined by WOWARNINT an interrupt will be generated after the subsequent WDCLK A match of the watchdog timer counter to WOWARNINT occurs when the bottom 10 bits of the counter have the same value as the 10 bits of WARNINT and the remaining upper bits of the counter are all 0 This gives a maximum time of 1 023 watchdog timer counts 4 096 watchdog clocks for the interrupt to occur prior to a watchdog
125. causes an immediate reset interrupt when the Watchdog is enabled and sets the WDTOF flag The reset will be generated during the second PCLK following an incorrect access to a Watchdog register during a feed sequence It is good practise to disable interrupts around a feed sequence if the application is such that some any interrupt might result in rescheduling processor control away from the current task in the middle of the feed and then lead to some other access to the WDT before control is returned to the interrupted task All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 331 of 404 NXP Semiconductors U M1 0524 UM10524 17 8 4 17 8 5 17 8 6 Chapter 17 LPC1315 16 17 45 46 47 Windowed Watchdog Timer Table 304 Watchdog Feed register FEED 0x4000 4008 bit description Bit Symbol Description Reset Value 7 0 FEED Feed value should be OxAA followed by 0x55 NA 31 8 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined Watchdog Timer Value register The WDTV register is used to read the current value of Watchdog timer counter When reading the value of the 24 bit counter the lock and synchronization procedure takes up to 6 WDCLK cycles plus 6 PCLK cycles so the value of WDTV is older than the actual value of the timer when it s being read
126. chip drivers Table 199 USBD_HW_API class structure Member Description ConfigEP void void USBD_HW_API ConfigEP USBD_HANDLE_T hUsb USB_ENDPOINT_DESCRIPTOR pEPD Function to configure USB Endpoint according to descriptor This function is called automatically when USB_REQUEST_SET_ CONFIGURATION request is received by the stack from USB host All the endpoints associated with the selected configuration are configured This interface is provided to users to invoke this function in other scenarios which are not handle by current stack In most user applications this function is not called directly Also this function can be used by users who are selectively modifying the USB device stack s standard handlers through callback interface exposed by the stack hUsbHandle to the USB device stack pEPDEndpoint descriptor structure defined in USB 2 0 specification Parameters 1 hUsb Handle to the USB device stack 2 pEPD Endpoint descriptor structure defined in USB 2 0 specification Returns Nothing DirCtrlEP void void USBD_HW_API DirCtrlEP USBD_HANDLE_T hUsb uint32_t dir Function to set direction for USB control endpoint EPO This function is called automatically by the stack on need basis This interface is provided to users to invoke this function in other scenarios which are not handle by current stack In most user applications this function is not called directly Also this function can be used by users who are selectively modify
127. concurrent interfaces supported by this configuration uint8_tuint8_t _USB_INTERFACE_DESCRIPTOR bAlternateSetting Value used to select this alternate setting for the interface identified in the prior field uint8_tuint8_t _USB_INTERFACE_DESCRIPTOR bNumEndpoints Number of endpoints used by this interface excluding endpoint zero If this value is zero this interface only uses the Default Control Pipe uint8_tuint8_t _USB_INTERFACE_DESCRIPTOR bInterfaceClass Class code assigned by the USB IF uint8_tuint8_t _USB_INTERFACE_DESCRIPTOR bInterfaceSubClass Subclass code assigned by the USB IF uint8_tuint8_t _USB_INTERFACE_DESCRIPTOR bInterfaceProtocol Protocol code assigned by the USB ilnterface uint8_tuint8_t _USB_INTERFACE_ DESCRIPTOR ilnterface Index of string descriptor describing this interface 11 5 21 USB OTHER_SPEED_CONFIGURATION UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 164 of 404 NXP Semiconductors UM10524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 186 _USB_OTHER_SPEED_CONFIGURATION class structure Member bLength bDescriptorType wTotalLength bNumInterfaces bConfigurationValue IConfiguration bmAttributes bMaxPower Description uint _tuint8_t _USB_OTHER_SPEED_CONFIGURATION bLength Size of descriptor uint8_
128. description Bit Symbol Value Description Reset value 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 I O configuration for pin PIO1_8 Table 87 I O configuration for pin PIO1_8 PIO1_8 address 0x4004 4080 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x1 to 0x7 are reserved 0 0x0 PIO1_8 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 90 of 404 NXP Semiconductors U M1 0524
129. drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 104 of 404 NXP Semiconductors UM10524 UM10524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration 7 4 52 I O configuration for pin PIO1_31 Table 107 I O configuration for pin PIO1_31 PIO1_31 address 0x4004 40DC bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x1 to 0x7 are reserved 0 OxO PIO1_31 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 0x2 0x3 5 HYS 6 INV 9 7 10 OD 31 11 Pull down resistor enabled Pull up resistor enabled Repeater mode Hysteresis 0 Disable Enable Invert input 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 Reserved 0x1 Open drain mode 0 Disable Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD Reserved 0 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 105 of 404 UM10524 Chapt
130. for the 12C block to operate in the slave transmitter mode After its own slave address and the R bit have been received the serial interrupt flag SI is set and a valid status code can be read from STAT This status code is used to vector to a state service routine and the appropriate action to be taken for each of these status codes is detailed in Table 266 The slave transmitter mode may also be entered if arbitration is lost while the 12C block is in the master mode see state OxBO If the AA bit is reset during a transfer the 12C block will transmit the last byte of the transfer and enter state OxCO or OxC8 The IC block is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer Thus the master receiver receives all 1s as serial data While AA is reset the 12C block does not respond to its own slave address or a General Call address However the I C bus is still monitored and address recognition may be resumed at any time by setting AA This means that the AA bit may be used to temporarily isolate the I2C block from the I C bus All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 281 of 404 NXP Semiconductors UM10524 Table 266 Slave Transmitter mode Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller Status Status of the I2C bus Application software respon
131. frequency Fclkout with M Fetkout Felkin 3 Find a value so that FCCO 2 x P x Felkout 4 Verify that all frequencies and divider values conform to the limits specified in Table 8 and Table 10 Table 46 shows how to configure the PLL for a 12 MHz crystal oscillator using the SYSPLLCTRL register Table 8 The main clock is equivalent to the system clock if the system clock divider SYSAHBCLKDIV is set to one see Table 19 Table 46 PLL configuration examples PLL input Main clock MSEL bits M divider PSEL bits P divider FCCO clock Fcikout Table 8 value Table 8 value frequency sys_plliclkin Fclkin 12 MHz 48 MHz 00011 binary 4 01 binary 2 192 MHz 12 MHz 36 MHz 00010 binary 3 10 binary 4 288 MHz 12 MHz 24 MHz 00001 binary 2 10 binary 4 192 MHz Power down mode In this mode the internal current reference will be turned off the oscillator and the phase frequency detector will be stopped and the dividers will enter a reset state While in Power down mode the lock output will be low to indicate that the PLL is not in lock When the Power down mode is terminated by SYSPLL_PD bit to zero in the Power down configuration register Table 42 the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February
132. in high impedance If the SSP SPI is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW Master s MOSI is enabled After a further one half SCK period both master and slave data are enabled onto their respective transmission lines At the same time the SCK is enabled with a falling edge transition Data is then captured on the rising edges and propagated on the falling edges of the SCK signal After all bits have been transferred in the case of a single word transmission the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured For continuous back to back transmissions the SSEL pins remains in its active LOW state until the final bit of the last word has been captured and then returns to its idle state as described above In general for continuous back to back transfers the SSEL pin is held LOW between successive data words and termination is the same as that of the single word transfer Semiconductor Microwire frame format Figure 28 shows the Microwire frame format for a single frame Figure 29 shows the same format when back to back frames are transmitted All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 249 of 404 NXP Semiconductors U M1 0524 UM10524 Chapter 13 LPC1315 16 17 45 46
133. is written to abit NA Table 252 of this register the corresponding bit in the 12C control register is cleared Writing a zero has no effect on the corresponding bit in the 12C control register 0x01C Monitor mode control register 0x00 Table 253 0x020 I2C Slave Address Register 1 Contains the 7 bit slave 0x00 Table 254 address for operation of the 12C interface in slave mode and is not used in master mode The least significant bit determines whether a slave responds to the General Call address All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 254 of 404 NXP Semiconductors UM10524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller Table 244 Register overview I2C base address 0x4000 0000 continued Name ADR2 ADR3 Access Address R W R W DATA_BUFFER RO MASKO MASK1 MASK2 MASK3 R W R W R W R W offset 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C Description I2C Slave Address Register 2 Contains the 7 bit slave address for operation of the 12C interface in slave mode and is not used in master mode The least significant bit determines whether a slave responds to the General Call address I2C Slave Address Register 3 Contains the 7 bit slave address for operation of the 12C interface in slave mode and is not used in master mode The least sign
134. locations Eight bytes of code is sufficient for most of the service routines see the software example in this section 14 10 Details of I2C operating modes UM10524 The four operating modes are e Master Transmitter e Master Receiver e Slave Receiver e Slave Transmitter Data transfers in each mode of operation are shown in Figure 40 Figure 41 Figure 42 Figure 43 and Figure 44 Table 259 lists abbreviations used in these figures when describing the 12C operating modes All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 269 of 404 NXP Semiconductors U M1 0524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller Table 259 Abbreviations used to describe an I C operation Abbreviation Explanation S START Condition SLA 7 bit slave address R Read bit HIGH level at SDA W Write bit LOW level at SDA A Acknowledge bit LOW level at SDA A Not acknowledge bit HIGH level at SDA Data 8 bit data byte P STOP condition In Figure 40 to Figure 44 circles are used to indicate when the serial interrupt flag is set The numbers in the circles show the status code held in the STAT register At these points a service routine must be executed to continue or complete the serial transfer These service routines are not critical since the serial transfer is suspended until the serial interrupt flag i
135. mode A pseudo open drain mode can be enabled for all digital pins Note that except for the I2C bus pins this is not a true open drain mode Analog mode In analog mode the digital receiver is disconnected to obtain an accurate input voltage for analog to digital conversions This mode can be selected in those IOCON registers that control pins with an analog function If analog mode is selected hysteresis pin mode inverter glitch filter and open drain settings have no effect For pins without analog functions the analog mode setting has no effect 2C mode If the 12C function is selected by the FUNC bits of registers PIOO_4 Table 60 and PIOO_5 Table 61 then the I2C bus pins can be configured for different I C modes e Standard mode Fast mode I C with 50 ns input glitch filter An open drain output according to the C bus specification can be configured separately e Fast mode Plus 12C with 50 ns input glitch filter In this mode the pins function as high current sinks An open drain output according to the I2C bus specification can be configured separately e Standard functionality without input filter Remark Either Standard mode Fast mode C or Standard I O functionality should be selected if the pin is used as GPIO pin All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 62 of 404 NXP Semiconductors UM105
136. module status register FMSTAT 0x4003 CFE0 bit description Bit Symbol Description Reset value 1 0 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 2 SIG_DONE When 1 a previously started signature generation has 0 completed See FMSTATCLR register description for clearing this flag 31 3 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined Flash module status clear register The FMSTATCLR register is used to clear the signature generation completion flag All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 381 of 404 NXP Semiconductors U M1 0524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming Table 377 Flash module status clear register FMSTATCLR 0x0x4003 CFE8 bit description Bit Symbol Description Reset value 1 0 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 2 SIG_DONE_CLR_ Writing a 1 to this bits clears the signature generation 0 completion flag SIG_DONE in the FMSTAT register 31 3 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 21 16 7 Algorithm and procedure for signature generation Signature g
137. pin l AD1 A D converter input 1 3 l CT32B1_CAP0 Capture input 0 for 32 bit timer 1 TDO PIOO_13 AD2 45 34 23 61 PU O TDO Test Data Out for JTAG interface CT32B1_MATO S TMS PIO0_12 AD1 44 33 22 CT32B1_CAPO 5 Cc 1 0 PIO0_13 General purpose digital input output pin l AD2 A D converter input 2 O CT32B1_MAT0 Match output 0 for 32 bit timer 1 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 107 of 404 NXP Semiconductors UM10524 Table 108 Pin description L_PC1315 16 17 no USB Chapter 8 LPC1315 16 17 45 46 47 Pin configuration Symbol 1 an 2 32 2 a o a amp L uw Oo N O O gt v 4 TRST PIOO_14 AD3 46 35 24 6 1 PU CT32B1_MAT1 g SWDIO PIOO_15 AD4 52 39 25 l 1 PU CT32B1_MAT2 PIOO_16 AD5 53 40 26 Z PU CT32B1_MAT3 WAKEUP PIOO_17 RTS 60 45 30 B IPU CT32B0_CAP0 SCLK i PIOO_18 RXD 61 46 31 B IPU CT32B0_MATO PIOO_19 TXD 62 47 32 Bl 1 PU CT32B0_MAT1 PIOO_20 CT16B1_CAPO 1 9 7 B PU PIOO_21 CT16B1_MATO 22 17 12 B 1 PU MOSI1 PIOO_22 AD6 40 30 20 l 1 PU CT16B1_MAT1 MISO1 g PIOO_23 AD7 56 42 27 PU UM10524 Type All information provided in this document is subject to legal disclaimers Description TRST Test Reset for JTAG interface PIO0_14 General purpose digital input output pin AD
138. pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 7 ADMODE Selects Analog Digital mode 1 0 Analog input mode 1 Digital functional mode 8 FILTR Selects 10 ns input glitch filter 0 0 Filter disabled 1 Filter enabled 9 Reserved 0 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 16 I O configuration for pin SWDIO PIOO_15 Table 71 I O configuration for pin SWDIO PIO0_15 AD4 CT32B1_MAT2 SWDIO_PIO0_15 address 0x4004 403C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x4 to 0x7 are reserved 0 0x0 SWDIO 0x1 PIOO_15 0x2 AD4 0x3 CT32B1_MAT2 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 77 of 404 NXP Semiconductors UM10524 UM10524 7 4 17 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 71 I O configuration for pin SWDIO PIO0_15 AD4 CT32B1_MAT2 SWDIO_PIO0_15 address 0x4004 403C bit description Bit Symbol Value Description Reset value 4 3 M
139. read this chapter 60 7 2 Introduction 0 0 ccc eee eee 60 7 3 General description 00 000es 60 7 3 1 PIN fUNCHON 2 0 e en ae ee be ede tati 61 7 3 2 PIM MO0 2 5 eden esha ea eee eee 61 7 3 3 Hystereesi Sine eae epee esa ene vanes 62 7 3 4 Input inverter 0000 eee eee 62 7 3 5 Input glitch filter 2 eee eee eee 62 7 3 6 Open drain mode 000e eee 62 7 3 7 Analog mode 00 eee eee eee 62 7 3 8 FPG Modes o heise Sethe ebedid bd boon 62 7 3 9 RESET pin pin RESET_PIOO_0 63 7 3 10 WAKEUP pin pin PIOO_16 63 7 4 Register description 63 7 4 1 I O configuration for pin RESET_PIO0_0 65 UM10524 7 4 2 7 4 3 7 4 4 7 4 5 7 4 6 7 4 7 7 4 8 7 4 9 7 4 10 7 4 11 7 4 12 7 4 13 7 4 14 7 4 15 7 4 16 7 4 17 All information provided in this document is subject to legal disclaimers I O configuration for pin PIOO_1 66 I O configuration for pin PIOO_2 67 I O configuration for pin PIOO_3 68 I O configuration for pin PIOO_4 68 I O configuration for pin PIOO_5 69 I O configuration for pin PIOO_6 69 I O configuration for pin PIOO_7 70 I O configuration for pin PIOO_8 71 I O configuration for pin PIOO_9 72 I O configuration for pin SWCLK PIOO_10 73 I O configuration for pin TDI PIOO_11 73 I O configuration f
140. read this chapter CT32B0 1 are available on all LPC1315 16 17 45 46 47 parts The following pin is available on the LQFP64 package only CT32B1_CAP1 The following pin is available on the LQFP64 and LQFP48 packages only CT32B0_CAP1 16 2 Basic configuration 16 3 Features The CT32B0 1 counter timers are configured through the following registers Pins The CT32B0 1 pins must be configured in the IOCON register block Power In the SYSAHBCLKCTRL register set bit 9 and 10 in Table 19 The peripheral clock is determined by the system clock see Table 18 UM10524 Two 32 bit counter timers with a programmable 32 bit prescaler Counter or timer operation Four 32 bit capture channels that can take a snapshot of the timer value when an input signal transitions A capture event may also optionally generate an interrupt The timer and prescaler may be configured to be cleared on a designated capture event This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge Four 32 bit match registers that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Four external outputs corresponding to match registers with the following capabilities Set LOW on match Set HIGH on match
141. register SETO address 0x5000 2200 bit description Bit Symbol Description Reset Access value 31 0 SETPO Read or set output bits 0 R W 0 Read output bit write no operation 1 Read output bit write set output bit Table 143 GPIO set port 1 register SET1 address 0x5000 2204 bit description Bit Symbol Description Reset Access value 31 0 SETP1 Read or set output bits 0 R W 0 Read output bit write no operation 1 Read output bit write set output bit GPIO port clear registers Output bits can be cleared by writing ones to these write only registers regardless of MASK registers Table 144 GPIO clear port 0 register CLRO address 0x5000 2280 bit description Bit Symbol Description Reset Access value 31 0 CLRPO Clear output bits NA WO 0 No operation 1 Clear output bit Table 145 GPIO clear port 1 register CLR1 address 0x5000 2284 bit description Bit Symbol Description Reset Access value 31 0 CLRP1 Clear output bits NA WO 0 No operation 1 Clear output bit GPIO port toggle registers Output bits can be toggled inverted complemented by writing ones to these write only registers regardless of MASK registers All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 131 of 404 NXP Semiconductors U M1 0524 Chapter 9 LPC1315 16 17 45 46 47 GPIO
142. reset see Figure 61 The loader can execute the ISP command handler or the user application code A LOW level during reset at the PIOO_1 pin is considered an external hardware request to start the ISP command handler or on the LPC 1345 46 47 the USB device handler if pin PIOO_3 is HIGH without checking for a valid user code first Assuming that power supply pins are at their nominal levels when the rising edge on RESET pin is generated it may take up to 3 ms before PIOO_1 is sampled and the decision whether to continue with user code or ISP handler is made If PIOO_1 is sampled LOW and the watchdog overflow flag is set the external hardware request to start the ISP command handler is ignored If there is no request for the ISP command handler execution PIOO_1 is sampled HIGH after reset a search is made for a valid user program If a valid user program is found then the execution control is transferred to it If a valid user program is not found the auto baud routine is invoked For the LPC 1345 46 47 parts the state of PIOO_3 determines whether the UART or USB interface will be used e f PIOO_3 is sampled HIGH the bootloader connects the LPC 1345 46 47 as a MSC USB device to a PC host The LPC1345 46 47 flash memory space is represented as a drive in the host s Windows operating system f PIOO_3 is sampled LOW the bootloader configures the UART serial port using pins PIOO_18 and PIOO_19 for RXD and TXD and calls the ISP c
143. reset on match are enabled 308 Fig 8 Standard I O pin configuration 61 Fig 49 A timer cycle in which PR 2 MRx 6 and both Fig9 Reset pad configuration 63 interrupt and stop on match are enabled 308 Fig 10 USB block diagram 0 0000 136 Fig 50 16 bit counter timer block diagram 309 Fig 11 USB software interface 137 Fig 51 Sample PWM waveforms with a PWM cycle length Fig 12 Endpoint command status list see also of 100 selected by MR3 and MAT3 0 enabled as Table 165 oe ase nce Genk oy ane S wads Rea Ras 148 PWM outputs by the PWCON register 322 Fig 13 Flowchart of control endpoint 0 OUT direction 151 Fig 52 A timer cycle in which PR 2 MRx 6 and both Fig 14 Flowchart of control endpoint 0 IN direction 152 interrupt and reset on match are enabled 323 Fig 15 USB device driver pointer structure 158 Fig 53 A timer cycle in which PR 2 MRx 6 and both Fig 16 Auto RTS Functional Timing 213 interrupt and stop on match are enabled 323 Fig 17 Auto CTS Functional Timing 214 Fig 54 32 bit counter timer block diagram 324 Fig 18 Auto baud a mode 0 and b mode 1 waveform 219 Fig 55 Watchdog block diagram 327 Fig 19 Algorithm for setting USART dividers 223 Fig 56 Early Watchdog Feed with Windowed Mode Fig 20 Typical smart card application 233 E
144. resistor is required on this pin for the Deep power down mode 3 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis see Figure 8 4 1 C bus pins compliant with the 1 C bus specification for I2C standard mode 12C Fast mode and I2C Fast mode Plus 5 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis see Figure 8 includes high current output driver 6 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors configurable hysteresis and analog input When configured as a ADC input digital section of the pad is disabled and the pin is not 5 V tolerant see Figure 8 includes programmable digital input glitch filter 7 WAKEUP pin 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors configurable hysteresis and analog input When configured as a ADC input digital section of the pad is disabled and the pin is not 5 V tolerant see Figure 8 includes digital input glitch filter 8 Pad provides USB functions It is designed in accordance with the USB specification revision 2 0 Full speed and Low speed mode only This pad is not 5 V tolerant 9 When the system oscillator is not used connect XTALIN and XTALOUT as follows XTALIN can be left floating or can be grounded grounding is preferred to redu
145. resistor to signal a connect 31 29 Reserved RO 10 6 2 USB Info register INFO Table 153 USB Info register INFO address 0x4008 0004 bit description Bit Symbol Value Description Access 10 0 FRAME_NR Frame number This contains the frame number of the last RO successfully received SOF In case no SOF was received by the device at the beginning of a frame the frame number returned is that of the last successfully received SOF In case the SOF frame number contained a CRC error the frame number returned will be the corrupted frame number as received by the device 14 11 ERR_CODE The error code which last occurred RW 0x0 No error 0x1 PID encoding error 0x2 PID unknown 0x3 Packet unexpected 0x4 Token CRC error 0x5 Data CRC error 0x6 Time out 0x7 Babble 0x8 Truncated EOP 0x9 Sent Received NAK OxA Sent Stall 0xB Overrun OxC Sent empty packet OxD Bitstuff error OxE Sync error OxF Wrong data toggle 15 Reserved RO 31 16 Reserved RO 10 6 3 USB EP Command Status List start address EPLISTSTART This 32 bit register indicates the start address of the USB EP Command Status List Only a subset of these bits is programmable by software The 8 least significant bits are hardcoded to zero because the list must start on a 256 byte boundary The bits 31 to 8 can be programmed by software UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manua
146. sector numbers and memory addresses for LPC1315 16 17 45 46 47 devices The size of a sector is 4 kB the size of a page is 256 Byte One sector contains 16 pages Table 332 LPC1315 16 17 45 46 47 flash sectors Sector Sector Page Address range LPC1345 LPC1346 LPC1347 number size kB number LPC1315 LPC1316 LPC1317 0 4 0 15 0x0000 0000 0x0000 OFFF yes yes yes 1 4 16 31 0x0000 1000 0x0000 1FFF yes yes yes 2 4 32 47 0x0000 2000 0x0000 2FFF yes yes yes 3 4 48 63 0x0000 3000 0x0000 3FFF yes yes yes 4 4 64 79 0x0000 4000 0x0000 4FFF yes yes yes 5 4 80 95 0x0000 5000 Ox0000 5FFF yes yes yes 6 4 96 111 0x0000 6000 0x0000 6FFF yes yes yes 7 4 112 127 0x0000 7000 0x0000 7FFF yes yes yes 8 4 128 143 0x0000 8000 0x0000 8FFF no yes yes 9 4 144 159 0x0000 9000 0x0000 9FFF no yes yes 10 4 160 175 0x0000 A000 0x0000 AFFF no yes yes 11 4 176 191 0x0000 B000 0x0000 BFFF no yes yes 12 4 192 207 0x0000 C000 0x0000 CFFF no no yes 13 4 208 223 0x0000 D000 0x0000 DFFF no no yes 14 4 224 239 0x0000 E000 0x0000 EFFF no no yes 15 4 240 255 0x0000 F000 0x0000 FFFF no no yes 21 12 Code Read Protection CRP Code Read Protection is a mechanism that allows the user to enable different levels of security in the system so that access to the on chip flash and use of the ISP can be restricted When needed CRP is invoked by programming a specific pattern in flash location at 0x0000 02FC IAP commands are not affecte
147. slave mode a defined state and to clear the STO flag no other bits in CON are affected The SDA and SCL lines are released a STOP condition is not transmitted Table 267 Miscellaneous States Status Status of the I C bus Application software response Next action taken by IC hardware Code ee To FromDAT ToCON STAT STA STO SI AA OxF8 No relevant state No DAT action No CON action Wait or proceed current transfer information available SI 0 0x00 Bus error during MST No DAT action 0 1 0 X Only the internal hardware is affected in or selected slave the MST or addressed SLV modes In all modes due to an cases the bus is released and the 2C illegal START or block is switched to the not addressed STOP condition State SLV mode STO is reset 0x00 can also occur when interference causes the 12C block to enter an undefined state 14 10 6 Some special cases The 12C hardware has facilities to handle the following special cases that may occur during a serial transfer e Simultaneous Repeated START conditions from two masters e Data transfer after loss of arbitration e Forced access to the I2C bus e 2C bus obstructed by a LOW level on SCL or SDA e Bus error 14 10 6 1 Simultaneous Repeated START conditions from two masters A Repeated START condition may be generated in the master transmitter or master receiver modes A special case occurs if another master simultaneously generates a Repeated START condition see F
148. sources for each peripheral function Each peripheral device may have one or more interrupt lines to the Vectored Interrupt Controller Each line may represent more than one interrupt source There is no significance or priority about what line is connected where except for certain standards from ARM See Section 21 5 2 for the NVIC register bit descriptions Table 53 Connection of interrupt sources to the Vectored Interrupt Controller Exception Name Description Flag s Number 0 PIN_INTO GPIO pin interrupt 0 1 PIN_INT1 GPIO pin interrupt 1 2 PIN_INT2 GPIO pin interrupt 2 a 3 PIN_INT3 GPIO pin interrupt 3 5 4 PIN_INT4 GPIO pin interrupt 4 5 PIN_INT5 GPIO pin interrupt 5 6 PIN_INT6 GPIO pin interrupt 6 7 PIN_INT7 GPIO pin interrupt 7 a 8 GINTO GPIO GROUPO interrupt UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 57 of 404 NXP Semiconductors UM10524 UM10524 Chapter 6 LPC1315 16 17 45 46 47 NVIC Connection of interrupt sources to the Vectored Interrupt Controller Table 53 Exception Name Description Number 9 GINT1 GPIO GROUP1 interrupt 11 to 10 a s 12 RIT RIT interrupt 13 14 SSP1 SSP1 interrupt 15 12C 12C interrupt 16 CT16B0 CT16B0 interrupt 17 CT16B1 CT16B1 interrupt 18 CT32B0 CT32B0 interrupt 19 CT32B1 CT32B1 interrupt 20 SSPO SSPO0 interrupt 21 USART
149. state where the own slave address has been received Address mask registers MASKO to MASK3 The four mask registers each contain seven active bits 7 1 Any bit in these registers which is set to 1 will cause an automatic compare on the corresponding bit of the received address when it is compared to the ADRn register associated with that mask register In other words bits in an ADRn register which are masked are not taken into account in determining an address match When an address match interrupt occurs the processor will have to read the data register DAT to determine what the received address was that actually caused the match Comparator The comparator compares the received 7 bit slave address with its own slave address 7 most significant bits in ADR It also compares the first received 8 bit byte with the General Call address 0x00 If an equality is found the appropriate status bits are set and an interrupt is requested Shift register DAT This 8 bit register contains a byte of serial data to be transmitted or a byte which has just been received Data in DAT is always shifted from right to left the first bit to be transmitted is the MSB bit 7 and after a byte has been received the first bit of received data is located at the MSB of DAT While data is being shifted out data on the bus is simultaneously being shifted in DAT always contains the last byte present on the bus Thus in the event of lost arbitration
150. supported 1 LPM supported 12 INTONNAK_AO Interrupt on NAK for interrupt and bulk OUT EP 0 RW 0 Only acknowledged packets generate an interrupt 1 Both acknowledged and NAKed packets generate interrupts 13 INTONNAK_AI Interrupt on NAK for interrupt and bulk IN EP 0 RW 0 Only acknowledged packets generate an interrupt 1 Both acknowledged and NAKed packets generate interrupts 14 INTONNAK_CO Interrupt on NAK for control OUT EP 0 RW 0 Only acknowledged packets generate an interrupt 1 Both acknowledged and NAKed packets generate interrupts 15 INTONNAK_Cl Interrupt on NAK for control IN EP 0 RW 0 Only acknowledged packets generate an interrupt 1 Both acknowledged and NAKed packets generate interrupts UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 140 of 404 NXP Semiconductors U M1 0524 Chapter 10 LPC 1345 46 47 USB2 0 device controller Table 152 USB Device Command Status register DEVCMDSTAT address 0x4008 0000 bit description Bit Symbol Value Description Reset Access value 16 DCON Device status connect 0 RW The connect bit must be set by SW to indicate that the device must signal a connect The pull up resistor on USB_DP will be enabled when this bit is set and the VobusDebounced bit is one 17 DSUS Device status suspend 0 RW The suspend bit indicates the current suspend state It is set to 1 when the device
151. the HW will set the toggle value equal to the value indicated in the toggle value TV bit For the control endpoint zero this is not needed to be used because the hardware resets the endpoint toggle to one for both directions when a setup token is received For the other endpoints the toggle can only be reset to zero when the endpoint is reset Rate Feedback mode Toggle value For bulk endpoints and isochronous endpoints this bit is reserved and must be set to zero For the control endpoint zero this bit is used as the toggle value When the toggle reset bit is set the data toggle is updated with the value programmed in this bit When the endpoint is used as an interrupt endpoint it can be set to the following values 0 Interrupt endpoint in toggle mode 1 Interrupt endpoint in rate feedback mode This means that the data toggle is fixed to zero for all data packets When the interrupt endpoint is in rate feedback mode the TR bit must always be set to zero All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 149 of 404 NXP Semiconductors UM10524 UM10524 Chapter 10 LPC1345 46 47 USB2 0 device controller Table 165 Endpoint commands Symbol Access T RW NBytes RW Address RW Offset Description Endpoint Type 0 Generic endpoint The endpoint is configured as a bulk or inte
152. the block diagram All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 326 of 404 NXP Semiconductors U M1 0524 Chapter 17 LPC1315 16 17 45 46 47 Windowed Watchdog Timer feed ok wd_clk enable count compare interrupt compare shadow bit feed ok A Y yY MOD WDPROTECT WDTOF WDINT WDRESET WDEN register MOD 4 MOD _ 2 MOD _ 3 MOD _ 1 MOD _ 0 L chip reset S watchdog interrupt s Fig 55 Watchdog block diagram 17 6 Clocking and power control The watchdog timer block uses two clocks PCLK and WDCLK PCLK is used for the APB accesses to the watchdog registers and is derived from the system clock see Figure 3 The WDCLK is used for the watchdog timer counting and is derived from the wdt_clk in Figure 3 Either the IRC or the watchdog oscillator can be used as wat_clk in Active mode or Sleep mode but in Deep sleep or Power down modes only the watchdog oscillator is available Remark If the LOCK bit is set in the MOD register Table 301 and the IRC is selected as a clock source for the WWDT the IRC is forced on during Deep sleep and Power down modes resulting in increased power consumption There is some synchronization logic between these two clock domains When the MOD an
153. timer can be configured to run in Deep sleep or Power down mode when using the watchdog oscillator as the clock source Debug mode All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 325 of 404 NXP Semiconductors U M1 0524 Chapter 17 LPC1315 16 17 45 46 47 Windowed Watchdog Timer 17 4 Applications The purpose of the Watchdog Timer is to reset or interrupt the microcontroller within a programmable time if it enters an erroneous state When enabled a watchdog reset and or will be generated if the user program fails to feed reload the Watchdog within a predetermined amount of time When a watchdog window is programmed an early watchdog feed is also treated as a watchdog event This allows preventing situations where a system failure may still feed the watchdog For example application code could be stuck in an interrupt service that contains a watchdog feed Setting the window such that this would result in an early feed will generate a watchdog event allowing for system recovery 17 5 Description UM10524 17 5 1 The Watchdog consists of a fixed divide by 4 pre scaler and a 24 bit counter which decrements when clocked The minimum value from which the counter decrements is OxFF Setting a value lower than OxFF causes OxFF to be loaded in the counter Hence the minimum Watchdog interval is Twoc_k x 256
154. value 0x0000 0000 This event does not cause an interrupt but a Match register can be used to detect an overflow if needed Table 289 Timer counter registers TC address 0x4001 4008 CT32B0 and 0x4001 8008 CT32B1 bit description Bit Symbol Description Reset value 31 0 TC Timer counter value 0 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 314 of 404 NXP Semiconductors U M1 0524 16 7 4 16 7 5 16 7 6 Chapter 16 LPC1315 16 17 45 46 47 32 bit counter timers CT32B0 1 Prescale Register The 32 bit Prescale Register specifies the maximum value for the Prescale Counter Table 290 Prescale registers PR address 0x4001 400C CT32B0 and 0x4001 800C CT32B1 bit description Bit Symbol Description Reset value 31 0 PCVAL Prescaler value 0 Prescale Counter Register The 32 bit Prescale Counter controls division of PCLK by some constant value before it is applied to the Timer Counter This allows control of the relationship between the resolution of the timer and the maximum time before the timer overflows The Prescale Counter is incremented on every PCLK When it reaches the value stored in the Prescale Register the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK This causes the TC to increment on every PCLK when PR 0 every 2 PCLKs when PR 1 etc
155. was designed to find a balance between active current and the CPU s ability to execute code and process data In this mode the device outperforms the default mode both in terms of providing higher CPU performance and lowering active current PWR_LOW_CURRENT is intended for those solutions that focus on lowering power consumption rather than CPU performance Current system clock The current system clock is the clock rate at which the microcontroller is running when set_power is called This parameter is an integer between from 1 and 50 MHz inclusive All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 55 of 404 NXP Semiconductors U M1 0524 UM10524 5 6 1 4 5 6 1 4 1 5 6 1 4 2 Chapter 5 LPC1315 16 17 45 46 47 Power profiles Code examples The following examples illustrate some of the set_power features discussed above Invalid frequency device maximum clock rate exceeded command 0 55 command 1 PWR_CPU_PERFORMANCE command 2 12 rom gt pWRD gt set_power command result The above setup would be used in a system running at 12 MHz attempting to switch to 55 MHz system clock with a need for maximum CPU processing power Since the specified 55 MHz clock is above the 50 MHz maximum set_power returns PWR_INVALID_FREQ in result 0 without changing anything in the existing power setup An app
156. when a match occurs to one of the up to four address registers described above That is the module will respond as anormal slave as far as address recognition is concerned 1 When this bit is set to 1 and the 12C is in monitor mode an interrupt will be generated on ANY address received This will enable the part to monitor all traffic on the bus 31 3 Reserved The value read from reserved bits is not defined 1 When the ENA_SCL bit is cleared and the 12C no longer has the ability to stall the bus interrupt response time becomes important To give the part more time to respond to an 12C interrupt under these conditions a DATA _BUFFER register is used Section 14 7 9 to hold received data for a full 9 bit word transmission time Remark The ENA_SCL and MATCH_ALL bits have no effect if the MM_ENA is 0 i e if the module is NOT in monitor mode Interrupt in Monitor mode All interrupts will occur as normal when the module is in monitor mode This means that the first interrupt will occur when an address match is detected any address received if the MATCH_ALL bit is set otherwise an address matching one of the four address registers Subsequent to an address match detection interrupts will be generated after each data byte is received for a slave write transfer or after each byte that the module thinks it has transmitted for a slave read transfer In this second case the data register will actually cont
157. when callback function is called by the stack 3 event Type of endpoint event See USBD_EVENT_T for more details Returns The call back should returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_ xxx For other error conditions ErrorCode_t ErrorCode_t USBD_CDC_INIT_PARAM SendEncpsCmd USBD_HANDLE_T hCDC uint8_t buffer uintl6_t len USBD_HANDLE_T hCDC uint8_t buffer uint16_t len ErrorCode_t ErrorCode_t USBD_CDC_INIT_PARAM GetEncpsResp USBD_HANDLE_T hCDC uint8_t buffer uint16_t len USBD_HANDLE_T hCDC uint8_t buffer uintl6_t len ErrorCode_t ErrorCode_t USBD_CDC_INIT_PARAM SetCommFeature USBD_HANDLE_T hCDC uintl6 _t feature uint8_t buffer uint16_t len USBD_HANDLE_T hCDC uintl6_t feature uint8_t buffer uintl6_t len ErrorCode_t ErrorCode_t USBD_CDC_INIT_PARAM GetCommFeature USBD_HANDLE_T hCDC uintl6_t feature uint8_t pBuffer uintl6_t len USBD_HANDLE_T hCDC uintl6_t feature uint8_t pBuffer uintl6_t len ErrorCode_t ErrorCode_t USBD_CDC_INIT_PARAM ClrCommFeature USBD_HANDLE_T hCDC uintl6_t feature USBD_HANDLE_T hCDC uint1l6_t feature SetCtrlLineState ErrorCode_t ErrorCode_t USBD_CDC_INIT_PARAM SetCtrlLineState USBD_HANDLE_T hCDC uintl6_t state USBD_HANDLE_T hCDC
158. which edges of the 0 Table 278 capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place CRO RO 0x02C Capture Register 0 CRO is loaded with the value of TC when there 0 Table 279 is an event on the CT16BO_CAPO input CR1 RO 0x030 Capture Register 1 CR1 is loaded with the value of TC when there 0 Table 279 is an event on the CT16BO_CAP1 input 0x034 Reserved 0x38 EMR R W 0x03C External Match Register The EMR controls the match function and 0 Table 280 the external match pins CT16BO_MAT 1 0 and CT16B1_MAT 1 0 0x040 Reserved 0x06C CTCR RW 0x070 Count Control Register The CTCR selects between Timer and 0 Table 282 Counter mode and in Counter mode selects the signal and edge s for counting PWMC R W 0x074 PWM Control Register The PWMCON enables PWM mode for the 0 Table 283 external match pins CT16BO_MAT 1 0 and CT16B1_MATT 1 0 1 Reset value reflects the data stored in used bits only It does not include reserved bits content UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 297 of 404 NXP Semiconductors U M1 0524 Chapter 15 LPC1315 16 17 45 46 47 16 bit counter timers CT16B0 1 Table 270 Register overview 16 bit counter timer 1 CT16B1 base address 0x4001 0000 Name Access Address Description Reset Refe
159. write 0x008 System PLL control 0 Table 8 SYSPLLSTAT read 0x00C System PLL status 0 Table 9 USBPLLCTRL read write 0x010 USB PLL control 0 Table 10 USBPLLSTAT read 0x014 USB PLL status 0 Table 11 SYSOSCCTRL read write 0x020 System oscillator control 0x000 Table 12 WDTOSCCTRL read write 0x024 Watchdog oscillator control Ox0A0 Table 13 0x028 Reserved g a SYSRSTSTAT read write 0x030 System reset status register 0 Table 14 SYSPLLCLKSEL read write 0x040 System PLL clock source select 0 Table 15 0x044 Reserved z USBPLLCLKSEL read write 0x048 USB PLL clock source select 0 Table 16 0x04C Reserved MAINCLKSEL read write 0x070 Main clock source select 0 Table 17 0x074 Reserved z SYSAHBCLKDIV read write 0x078 System clock divider 0x001 Table 18 SYSAHBCLKCTRL read write 0x080 System clock control Table 19 SSPOCLKDIV read write 0x094 SSPO clock divider 0 Table 20 UARTCLKDIV read write 0x098 UART clock divider 0 Table 21 SSP1CLKDIV read write 0x09C SSP1 clock divider 0x0000 Table 22 TRACECLKDIV read write 0x0AC ARM trace clock divider 0x0000 Table 23 0000 SYSTICKCLKDIV read write 0x0BO SYSTICK clock divider 0x0000 Table 24 0000 USBCLKSEL read write 0x0CO USB clock source select 0 Table 25 0x0C4 Reserved USBCLKDIV read write 0x0C8 USB clock source divider 0 Table 26 CLKOUTSEL read write Ox0E0 CLKOUT clock source select 0 Table 27 Ox0E4 Reserved E CLKOUTDIV read write 0x0E8 CLKOUT clock divider 0 Table 28 PIOPORCAPO read 0x100 POR capt
160. x 4 and the maximum Watchdog interval is Twocik x 224 x 4 in multiples of TwocLk x 4 The Watchdog should be used in the following manner e Set the Watchdog timer constant reload value in the TC register e Set the Watchdog timer operating mode in the MOD register e Seta value for the watchdog window time in the WINDOW register if windowed operation is desired e Seta value for the watchdog warning interrupt in the WARNINT register if a warning interrupt is desired e Enable the Watchdog by writing OxAA followed by 0x55 to the FEED register e The Watchdog must be fed again before the Watchdog counter reaches zero in order to prevent a watchdog event If a window value is programmed the feed must also occur after the watchdog counter passes that value When the Watchdog Timer is configured so that a watchdog event will cause a reset and the counter reaches zero the CPU will be reset loading the stack pointer and program counter from the vector table as for an external reset The Watchdog time out flag WDTOF can be examined to determine if the Watchdog has caused the reset condition The WDTOF flag must be cleared by software When the Watchdog Timer is configured to generate a warning interrupt the interrupt will occur when the counter matches the value defined by the WARNINT register Block diagram The block diagram of the Watchdog is shown below in the Figure 55 The synchronization logic PCLK WDCLK is not shown in
161. 0 0 eee eee eee 37 3 5 17 SSP1 clock divider register SSP1CLKDIV 23 3 9 3 1 Power configuration in Sleep mode 37 3 5 18 ARM trace clock divider register 3 9 3 2 Programming Sleep mode 37 TRACECLKDIV 0020 00 ee 23 3 9 3 3 Wake up from Sleep mode 38 3 5 19 SYSTICK clock divider register 3 9 4 Deep sleep mode 0 0e0 ee 38 SYSTICKCLKDIV 00000005 23 3 9 4 1 Power configuration in Deep sleep mode 38 3 5 20 USB clock source select register 3 9 4 2 Programming Deep sleep mode 38 USBCLKSEL 0 000 e ee eee 24 3 9 4 3 Wake up from Deep sleep mode 39 3 5 21 USB clock source divider register 3 9 5 Power down mode 0 05 39 USBCLKDIV 00 000000 eee 24 3 9 5 1 Power configuration in Power down mode 40 3 5 22 CLKOUT clock source select register 3 9 5 2 Programming Power down mode 40 CLKOUTSEL 0 000 e ee eee 24 3 9 5 3 Wake up from Power down mode 40 3 5 23 CLKOUT clock divider register CLKOUTDIV 25 3 9 6 Deep power down mode 41 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 397 of 404 NXP Semiconductors UM10524 3 9 6 1 Power configuration in Deep power down MOJE pc ivcdenaecand hed end kee weds 41 3 9 6 2 Programming Deep power down mod
162. 0 001F bit GESCrIPLON c oseaan ae eae Sees 128 Table 131 GPIO port 1 byte pin registers B32 to B63 addresses 0x5000 0020 to 0x5000 002F bit description 22 02 0c eee eee 128 Table 132 GPIO port 0 word pin registers WO to W31 addresses 0x5000 1000 to 0x5000 107C bit descriptio se ibid poe etek ee ed 128 Table 133 GPIO port 1 word pin registers W32 to W63 addresses 0x5000 1080 to 0x5000 10FC bit GSSCriplON secre ei eede seed ete awe ed 129 Table 134 GPIO direction port 0 register DIRO address 0x5000 2000 bit description 129 Table 135 GPIO direction port 1 register DIR1 address 0x5000 2004 bit description 129 Table 136 GPIO mask port 0 register MASKO address 0x5000 2080 bit description 129 Table 137 GPIO mask port 1 register MASK1 address 0x5000 2084 bit description 130 Table 138 GPIO port 0 pin register PINO address 0x5000 2100 bit description 130 Table 139 GPIO port 1 pin register PIN1 address 0x5000 2104 bit description 130 Table 140 GPIO masked port 0 pin register MPINO address 0x5000 2180 bit description 130 Table 141 GPIO masked port 1 pin register MPIN1 address 0x5000 2184 bit description 131 Table 142 GPIO set port 0 register SETO address 0x5000 2200 bit description 131 Table 143 GPIO set port 1 register SET1 address 0x5000 N
163. 00 these bits select which CAP pin or comparator output is sampled for clocking Values 0x1 to 0x3 are reserved 0x0 CT16Bn_CAPO 0x1 CT16Bn_CAP1 4 ENCC Setting this bit to 1 enables clearing of the timer and the 0 prescaler when the capture edge event specified in bits 7 5 occurs UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 305 of 404 NXP Semiconductors U M1 0524 UM10524 15 7 12 Chapter 15 LPC1315 16 17 45 46 47 16 bit counter timers CT16B0 1 Table 282 Count Control Register CTCR address 0x4000 C070 CT16B0 and 0x4001 0070 CT16B1 bit description Bit Symbol Value Description Reset value 7 5 SELCC When bit 4 is a 1 these bits select which capture input edge 0 will cause the timer and prescaler to be cleared These bits have no effect when bit 4 is low Values 0x4 to 0x7 are reserved 0x0 Rising Edge of CAPO clears the timer if bit 4 is set 0x1 Falling Edge of CAPO clears the timer if bit 4 is set 0x2 Rising Edge of CAP1 clears the timer if bit 4 is set 0x3 Falling Edge of CAP1 clears the timer if bit 4 is set 31 8 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined PWM Control register The PWM Control Register is used to configure the match outputs as PWM outputs Each match output can be independently set
164. 000 0x0 Default The part is in active or sleep mode 0x1 ARM WFI will enter Deep sleep mode 0x2 ARM WFI will enter Power down mode 0x3 ARM WFI will enter Deep power down mode ARM Cortex M3 core powered down All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 45 of 404 NXP Semiconductors U M1 0524 UM10524 4 3 2 4 3 3 Chapter 4 LPC1315 16 17 45 46 47 Power Management Unit PMU Table 48 Power control register PCON address 0x4003 8000 bit description continued Bit Symbol Value Description Reset value 3 NODPD A 1 in this bit prevents entry to Deep power down mode 0 when 0x3 is written to the PM field above the SLEEPDEEP bit is set and a WFI is executed Execution continues after the WFI if this bit is 1 This bit is cleared only by power on reset so writing a one to this bit locks the part in a mode in which Deep power down mode is blocked 7 4 Reserved Do not write ones to this bit SLEEPFLAG Sleep mode flag 0 Read No power down mode entered LPC1315 16 17 45 46 47 is in Active mode Write No effect 1 Read Sleep Deep sleep or Deep power down mode entered Write Writing a 1 clears the SLEEPFLAG bit to 0 10 9 Reserved Do not write ones to this bit 11 DPDFLAG Deep power down flag 0 Read Deep power down mode not entered Write No effect 1 Read Deep power down mod
165. 07 rate divisor value The full divisor is used to generate a baud rate from the fractional rate divider DLAB 1 IER R W 0x004 Interrupt Enable Register Contains individual interrupt 0 Table 208 enable bits for the seven potential USART interrupts DLAB 0 IIR RO 0x008 Interrupt ID Register Identifies which interrupt s are 0x01 Table 209 pending FCR WO 0x008 FIFO Control Register Controls USART FIFO usage 0 Table 211 and modes LCR R W 0x00C Line Control Register Contains controls for frame 0 Table 212 formatting and break generation MCR R W 0x010 Modem Control Register 0 Table 213 LSR RO 0x014 Line Status Register Contains flags for transmit and 0x60 Table 214 receive status including line errors MSR RO 0x018 Modem Status Register 0 Table 216 SCR R W 0x01C Scratch Pad Register Eight bit temporary storage for 0 Table 217 software ACR R W 0x020 Auto baud Control Register Contains controls for the 0 Table 218 auto baud feature ICR R W 0x024 IrDA Control Register Enables and configures the IrDA 0 Table 219 remote control mode FDR R W 0x028 Fractional Divider Register Generates a clock input for 0x10 Table 221 the baud rate divider OSR R W 0x02C Oversampling Register Controls the degree of OxFO Table 223 oversampling during each bit time TER R W 0x030 Transmit Enable Register Turns off USART transmitter 0x80 Table 224 for use with software flow control HDEN R W 0x040 Half duplex enable register 0 Table 225 SCI
166. 0x4001 C000 6 32 bit counter timer 1 0x4001 8000 0x1000 2000 5 32 bit counter timer 0 0x4001 4000 8 kB SRAMO 0x1000 0000 4 16 bit counter timer 1 0x4001 0000 3 16 bit counter timer 0 0x4000 C000 _ reserved 2 1 USART SMART CARD x4000 8000 0x0001 0000 64 kB on chip flash LPC1317 47 0x0000 C000 z 48 kB on chip flash LPC1316 46 0x0000 8000 0x0000 00C0 32 kB on chip flash LPC1315 45 active interrupt vectors 0x0000 0000 0GB 0x0000 0000 WWDT 0x4000 4000 2C bus 0x4000 0000 002aag562 Fig 2 LPC1315 16 17 45 46 47 memory map UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 10 of 404 UM10524 Chapter 3 LPC1315 16 17 45 46 47 System control block Rev 1 17 February 2012 User manual 3 1 How to read this chapter All USB related registers and register bits are available on parts LPC134x only The USB PLL is available on parts LPC134x only Remark The DEVICE_ID register is located at address offset OxF8 This register location is different from other LPC1xxx parts 3 2 Introduction The system configuration block controls oscillators some aspects of the power management and the clock generation of the LPC1315 16 17 45 46 47 Also included in this block is a register for remapping flash SRAM and ROM memory areas 3 3 Pin description Table 4
167. 0xB OxC OxD OxE OxF 0x0 0x1 0x2 0x3 Reset Value 0000 Description Data Size Select This field controls the number of bits transferred in each frame Values 0000 0010 are not supported and should not be used 4 bit transfer 5 bit transfer 6 bit transfer 7 bit transfer 8 bit transfer 9 bit transfer 10 bit transfer 11 bit transfer 12 bit transfer 13 bit transfer 14 bit transfer 15 bit transfer 16 bit transfer Frame Format 00 SPI TI Microwire This combination is not supported and should not be used Clock Out Polarity This bit is only used in SPI mode 0 SPI controller maintains the bus clock low between frames SPI controller maintains the bus clock high between frames Clock Out Phase This bit is only used in SPI mode 0 SPI controller captures serial data on the first clock transition of the frame that is the transition away from the inter frame state of the clock line SPI controller captures serial data on the second clock transition of the frame that is the transition back to the inter frame state of the clock line Serial Clock Rate The number of prescaler output clocks per 0x00 bit on the bus minus one Given that CPSDVSR is the prescale divider and the APB clock PCLK clocks the prescaler the bit frequency is PCLK CPSDVSR x SCR 1 Reserved E SSP SPI Control Register 1 This register controls certain aspects of the operation of the SSP SPI controller All inform
168. 12 24 of 404 NXP Semiconductors U M1 0524 Chapter 3 LPC1315 16 17 45 46 47 System control block Table 27 CLKOUT clock source select CLKOUTSEL address 0x4004 80E0 bit description Bit Symbol Value Description Reset value 1 0 SEL CLKOUT clock source 0 0x0 IRC oscillator 0x1 Crystal oscillator SYSOSC 0x2 Watchdog oscillator 0x3 Main clock 31 2 Reserved 0 3 5 23 CLKOUT clock divider register CLKOUTDIV This register determines the divider value for the signal on the CLKOUT pin Table 28 CLKOUT clock divider CLKOUTDIV address 0x4004 80E8 bit description Bit Symbol Description Reset value 7 0 DIV CLKOUT clock divider values 0 0 Disable CLKOUT clock divider 1 Divide by 1 to 255 Divide by 255 31 8 Reserved 3 5 24 POR captured PIO status 0 register PIOPORCAPO0 The PIOPORCAPO register captures the state of GPIO port 0 at power on reset Each bit represents the reset state of one GPIO pin This register is a read only status register Table 29 POR captured PIO status 0 PIOPORCAPO address 0x4004 8100 bit description Bit Symbol Description Reset value 23 0 PIOSTAT State of PO_23 through PO_0 at power on reset Implementation dependent 31 24 Reserved 3 5 25 POR captured PIO status 1 register PIOPORCAP1 The PIOPORCAP 1 register captures the state of GPIO port 1 at power on reset Each bit represents the reset state of one GPIO pin This register is a read only status regist
169. 12 366 of 404 NXP Semiconductors UM10524 UM10524 21 13 8 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming Table 343 ISP Copy command Command Input Return Code Description Example Cc Flash Address DST Destination flash address where data bytes are to be written The destination address should be a 256 byte boundary RAM Address SRC Source RAM address from where data bytes are to be read Number of Bytes Number of bytes to be written Should be 256 512 1024 4096 CMD_SUCCESS SRC_ADDR_ERROR Address not on word boundary DST_ADDR_ERROR Address not on correct boundary SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR Byte count is not 256 512 1024 4096 SECTOR_NOT_PREPARED_FOR WRITE_OPERATION BUSY CMD_LOCKED PARAM_ERROR CODE_READ_PROTECTION_ENABLED This command is used to program the flash memory The Prepare Sector s for Write Operation command should precede this command The affected sectors are automatically protected again once the copy command is successfully executed The boot block cannot be written by this command This command is blocked when code read protection is enabled Also see Section 21 6 for the number of bytes that can be written C 0 268467504 512 lt CR gt lt LF gt copies 512 bytes from the RAM address 0x1000 0800 to the flash address 0 Go lt address gt lt mode gt Table 344 ISP Go command Comman
170. 15 16 17 no USB 106 Table 109 Pin description LPC1345 46 47 with USB 112 Table 110 GPIO pins available 118 Table 111 Register overview GPIO pin interrupts base address 0x4004 C000 120 Table 112 Register overview GPIO GROUPO interrupt base address 0x4005 C000 120 Table 113 Register overview GPIO GROUP1 interrupt base address 0x4006 0000 121 Table 114 Register overview GPIO port base address 0x5000 0000 2 2 220 0 5 121 Table 115 Pin interrupt mode register ISEL address 0x4004 C000 bit description 122 Table 116 Pin interrupt level rising edge interrupt enable register IENR address 0x4004 C004 bit description 0 200 eee eee eee 122 Table 117 Pin interrupt level rising edge interrupt set register SIENR address 0x4004 C008 bit description 0 eee eee 122 Table 118 Pin interrupt level rising edge interrupt clear register PCIENR address 0x4004 COOC bit CESCHPLON sor ove caspa drese bee eed ee 123 Table 119 Pin interrupt active level falling edge interrupt enable register IENF address 0x4004 C010 bit COSCHPUON s isi tie ee eh aed dee 123 Table 120 Pin interrupt active level falling edge interrupt set register SIENF address 0x4004 C014 bit CESCHPLION a se senar phere Ase ee 124 Table 121 Pin interrupt active level falling edge interrupt UM10524 All information prov
171. 17 45 46 47 I O configuration Rev 1 17 February 2012 User manual 7 1 How to read this chapter The IOCON register map depends on the package type see Table 54 Registers for pins that are not available are reserved Table 54 IOCON registers available Package Port 0 Port 1 LQFP64 PIO0_0 to PIOO_23 PIO1_0 to PIO1_5 PIO1_7 to PIO1_8 PIO1_10 to PIO1_29 LQFP48 PIOO_0 to PIOO_23 PIO1_13 to PIO1_16 PIO1_19 to PIO1_ 23 to PIO1_29 PIO1_31 HVQEFN no USB PIO0O_0 to PIOO_23 PIO1_15 PIO1_19 PIO1_23 to PIO1_24 HVQFN USB PIO0_0 to PIOO_23 PIO1_15 PIO1_19 7 2 Introduction The I O configuration registers control the electrical characteristics of the pads The following features are programmable e Pin function e Internal pull up pull down resistor or bus keeper function repeater mode e Open drain mode for standard I O pins e Hysteresis e Input inverter e Glitch filter on selected pins e Analog input or digital mode for pads hosting the ADC inputs e 2C mode for pads hosting the I2C bus function 7 3 General description The IOCON registers control the function GPIO or peripheral function and the electrical characteristics of the port pins see Figure 8 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 60 of 404 NXP Semiconductors UM10524 Chapter 7 LPC1315 16 17 45 46 4
172. 1_1 General purpose digital input output pin E O CT32B1_MAT1 Match output 1 for 32 bit timer 1 PIO1_2 CT32B1_MAT2 34 BI PU VO PIO1_2 General purpose digital input output pin z O CT32B1_MAT2 Match output 2 for 32 bit timer 1 PIO1_3 CT32B1_MAT3 50 3 BI PU VO PIO1_3 General purpose digital input output pin O CT32B1_MAT3 Match output 3 for 32 bit timer 1 PIO1_4 CT32B1_CAPO 16 BI PU VO PIO1_4 General purpose digital input output pin l CT32B1_CAP0 Capture input 0 for 32 bit timer 1 PIO1_5 CT32B1_CAP1 32 BI PU IO PIO1_5 General purpose digital input output pin l CT32B1_CAP1 Capture input 1 for 32 bit timer 1 PIO1_7 6 BI PU VO P101_7 General purpose digital input output pin PIO1_8 39 z BI PU VO PIO1_8 General purpose digital input output pin UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 114 of 404 NXP Semiconductors UM10524 Table 109 Pin description LPC1345 46 47 with USB Chapter 8 LPC1315 16 17 45 46 47 Pin configuration Symbol Tt A WL ej al PIO1_10 12 PIO1_11 43 PIO1_13 DTR 47 CT16BO_MAT0 TXD PIO1_14 DSR 49 CT16BO_MAT1 RXD PIO1_15 DCD 57 CT16BO_MAT2 SCK1 PIO1_16 RI CT16BO_CAPO 63 PlO1_17 CT16BO_CAP1 23 RXD PlO1_18 CT16B1_CAP1 28 TXD PIO1_19 DTR SSEL1 3 PIO1_20 DSR SCK1 18 PIO1_21 DCD M
173. 2 235 of 404 NXP Semiconductors U M1 0524 Chapter 12 LPC1315 16 17 45 46 47 USART TX DMA CL lt lt TX DMA RE CTS THR TSR TDI a M E NTXRDY DSR MSR RI DCD DTR DIR DLL NBAUDOUT RTS DIR MCR DLM RCLK RX DMA Cl a RX DMA RI RBR RSR BXD NRXRDY U1INTR IER E pL LT LSR LCR PA 2 0 PSEL PSTB PWRITE APB Piel INTERFACE DDIS AR MR PCLK Fig 22 USART block diagram UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 236 of 404 UM10524 Chapter 13 LPC1315 16 17 45 46 47 SSP SPI Rev 1 17 February 2012 User manual 13 1 How to read this chapter Two SSP SPI interfaces are available on all LPC1315 16 1 7 45 46 47 parts 13 2 Basic configuration The SSP0 1 are configured using the following registers 1 Pins The SSP SPI pins must be configured in the IOCON register block 2 Power In the SYSAHBCLKCTRL register set bit 11 for SSPO and bit 18 for SSP1 Table 19 3 Peripheral clock Enable the SSPO SSP1 peripheral clocks by writing to the SSP0 1CLKDIV registers Table 20 Table 22 4 Reset Before accessing the SSP SPI block ensure that the SSP0 1_RST_N bits bit 0 and bit 2 in the PRESETCTRL register Table 7 are set to 1 This de asserts the reset signal to the SSP SPI block 13 3 Features e Compatible with Motorola SPI 4 wire TI SSI and National Semicon
174. 2 ms the USB need_clock signal will go low This indicates that the USB main clock can be switched off When activity is detected on the USB bus the USB suspend signal is deactivated and USB need_clock signal is activated This process is fully combinatorial and hence no USB main clock is required to activate the US B need_clock signal Frame toggle output The USB_FTOGGLE output pin reflects the 1 kHz clock derived from the incoming Start of Frame tokens sent by the USB host All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 138 of 404 NXP Semiconductors UM10524 10 4 7 Clocking Chapter 10 LPC 1345 46 47 USB2 0 device controller The LPC1315 16 17 45 46 47 USB device controller has the following clock connections e USB main clock The USB main clock is the 48 MHz 500 ppm clock from the dedicated USB PLL or the main clock see Table 25 If the main clock is used the system PLL output must be 48 MHz and derived from the system oscillator The USB main clock is used to recover the 12 MHz clock from the USB bus e AHB clock This is the AHB system bus clock The minimum frequency of the AHB clock is 16 MHz when the USB device controller is receiving or transmitting USB packets 10 5 Pin description The device controller can access one USB port Table 150 USB device pin description Name Veus
175. 20 shows the possible pulse widths Table 220 IrDA Pulse Width FixPulseEn PulseDiv IrDA Transmitter Pulse width ys 3 16 x baud rate 2 x TpcLK 4 x Teck 8 x Teck 16 x Teck 32 x TpcLK 64 x TecLk 128 x Tpoik 0 i J r 7 7 1 256 x TpeLK NO fF WD OX All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 220 of 404 NXP Semiconductors U M1 0524 Chapter 12 LPC1315 16 17 45 46 47 USART 12 5 14 USART Fractional Divider Register The USART Fractional Divider Register FDR controls the clock pre scaler for the baud rate generation and can be read and written at the user s discretion This pre scaler takes the APB clock and generates an output clock according to the specified fractional requirements Important If the fractional divider is active DIVADDVAL gt 0 and DLM 0 the value of the DLL register must be 3 or greater Table 221 USART Fractional Divider Register FDR address 0x4000 8028 bit description Bit Function Description Reset value 3 0 DIVADDVAL Baud rate generation pre scaler divisor value If this field is 0 0 fractional baud rate generator will not impact the USART baud rate 7 4 MULVAL Baud rate pre scaler multiplier value This field must be greater 1 or equal 1 for USART to operate properly regardless of whether the fractional baud rate generator is used or no
176. 24 Chapter 7 LPC1315 16 17 45 46 47 I O configuration 7 3 9 RESET pin pin RESET_PIO0O_0 See Figure 9 for the reset pad configuration RESET functionality is not available in Deep power down mode Use the WAKEUP pin to reset the chip and wake up from Deep power down mode An external pull up resistor is required on this pin for the Deep power down mode The reset pin includes a fixed 20 ns glitch filter Fig 9 20 ns RC bee GLITCH FILTER lt l Reset pad configuration 002aat274 7 3 10 WAKEUP pin pin PIOO_16 The WAKEUP pin is combined with pin PIOO_16 and includes a 20 ns fixed glitch filter This pin must be pulled HIGH externally to enter Deep power down mode and pulled LOW to exit Deep power down mode A LOW going pulse as short as 50 ns wakes up the part 7 4 Register description Table 55 Register overview IOCON base address 0x4004 4000 Name RESET_PIO0O_0 PIOO_1 PIOO 2 PIOO_3 PIOO_4 PIOO_5 PIOO_6 PIOO_7 PIOO_8 UM10524 Access read write read write read write read write read write read write read write read write read write Address offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 Description I O configuration for pin RESET PIOO_0 I O configuration for pin PIOO_1 CLKOUT CT32B0_MAT2 USB_FTOGGLE I O configuration for pin PIO0_2 SSEL0 CT16B0_CAPO I O configuration for p
177. 287 14 11 8 8 State 0x98 02 eee 293 14 11 1 Initialization routine 0 0 000 287 14 11 8 9 State OxAO 2 1 eee eee eee 293 14 11 2 Start Master Transmit function 287 1411 9 Slave Transmitter states 293 14 11 3 Start Master Receive function 288 14 11 9 1 State OxA8 00 0 0 00 000 293 14 11 4 120 interrupt routine e ee e 288 14 11 9 2 State OxBO 0 0 000 293 14 11 5 Non mode specific states 288 14 11 9 3 State OxB8 0 000 293 14 11 5 1 State 0x00 0 0 0 0 cece e eee ee eee ogg 1411 9 4 State 0xCO 2 2 esses eee eee 294 14 11 5 2 Master States 00 00 288 1411 9 5 State OxC8 eee eee 294 Chapter 15 LPC1315 16 17 45 46 47 16 bit counter timers CT16B0 1 15 1 How to read this chapter 295 15 7 5 Prescale Counter register 300 15 2 Basic configuration 295 15 7 6 Match Control Register 300 15 3 Features 00002000eeee eee eee 295 pac ie Ay EE eee erect Le ve apture Control Register 15 4 Applications 22 5 296 15 7 9 Capture Registers 303 15 5 Description 1s eee reece eens 296 15 7 10 External Match Register 303 15 6 Pin description 296 15 7 11 Count Control Register 305 15 7 Regist
178. 2B1_MAT1 Table 92 I O configuration for pin PIO1_15 DCD TRST_PIOO_14 address 0x4004 4038 bit CT16B0_MAT2 SCK1 PIO1_ 15 address 0x4004 description 0 0 0002028 76 409C bit description 93 Table 71 I O configuration for pin Table 93 I O configuration for pin SWDIO PIOO_15 AD4 CT32B1_MAT2 P1O1_16 RI CT16BO_CAPO PIO1_16 address SWDIO_PIOO_15 address 0x4004 403C bit 0x4004 40A0 bit description 94 description 20 e eee eee 77 Table 94 I O configuration for Table 72 I O configuration for pin PIO1_17 CT16BO_CAP1 RXD PIO1_17 PIOO_16 AD5 CT32B1_MAT3 WAKEUP address 0x4004 40A4 bit description 95 PIOO_16 address 0x4004 4040 bit Table 95 1 O configuration for COSCHDLION sctades fed gedes bd die pannorna ia 78 PlO1_18 CT16B1_CAP1 TXD PIO1_18 Table 73 I O configuration for pin address 0x4004 40A8 bit description 96 PIO0O_17 RTS CT32B0O_CAP0 SCLK PIOO_17 Table 96 1 O configuration for pin PlO1_19 DTR SSEL1 address 0x4004 4044 bit description 79 PIO1_19 address 0x4004 40AC bit Table 74 I O configuration for pin description 2 200 0c eee eee 96 PIO0_18 RXD CT32B0_MATO PIOO_18 Table 97 I O configuration for pin PIO1_20 DSR SCK1 address 0x4004 4048 bit description 80 PlO1_20 address 0x4004 40B0 bit Table 75 I O configuration for pin description 200 0 eee eee eee 97 UM10524 All information provided in this do
179. 3 A D converter input 3 CT32B1_MAT1 Match output 1 for 32 bit timer 1 SWDIO Serial wire debug input output PIO0_15 General purpose digital input output pin AD4 A D converter input 4 CT32B1_MAT2 Match output 2 for 32 bit timer 1 PIO0_16 General purpose digital input output pin AD5 A D converter input 5 CT32B1_MAT3 Match output 3 for 32 bit timer 1 WAKEUP Deep power down mode wake up pin with 20 ns glitch filter This pin must be pulled HIGH externally to enter Deep power down mode and pulled LOW to exit Deep power down mode A LOW going pulse as short as 50 ns wakes up the part PIO0_17 General purpose digital input output pin RTS Request To Send output for USART CT32B0_CAP0 Capture input 0 for 32 bit timer 0 SCLK Serial clock input output for USART in synchronous mode PIO0_18 General purpose digital input output pin RXD Receiver input for USART Used in UART ISP mode CT32B0_MAT0 Match output 0 for 32 bit timer 0 PIO0_19 General purpose digital input output pin TXD Transmitter output for USART Used in UART ISP mode CT32B0_MAT1 Match output 1 for 32 bit timer 0 PIO0_20 General purpose digital input output pin CT16B1_CAP0 Capture input 0 for 16 bit timer 1 PIO0_21 General purpose digital input output pin CT16B1_MATO Match output 0 for 16 bit timer 1 MOSI1 Master Out Slave In for SSP1 PIO0_22 Gener
180. 3 Yes X No No NA CRP1 No X No Yes Yes CRP2 No Xx No Yes No CRP3 No xX No Yes No Table 335 ISP commands allowed for different CRP levels ISP command CRP1 CRP2 CRP3 no entry in ISP mode allowed Unlock yes yes n a Set Baud Rate yes yes n a Echo yes yes n a Write to RAM yes above 0x1000 0300 no n a only Read Memory no no n a Prepare sector s for yes yes n a write operation Copy RAM to flash yes not to sector 0 no n a Go no no n a Erase sector s yes sector 0 can only be yes all sectors n a erased when all sectors are only erased Blank check sector s no no n a Read Part ID yes yes n a Read Boot code version yes yes n a Compare no no n a ReadUID yes yes n a In case a CRP mode is enabled and access to the chip is allowed via the ISP an unsupported or restricted ISP command will be terminated with return code CODE_READ_PROTECTION_ENABLED ISP entry protection In addition to the three CRP modes the user can prevent the sampling of pin PIOO_1 for entering ISP mode and thereby release pin PIOO_1 for other uses This is called the NO_ISP mode The NO_ISP mode can be entered by programming the pattern 0x4E69 7370 at location 0x0000 02FC The NO_ISP mode is identical to the CRP3 mode except for SWD access which is allowed in NO_ISP mode but disabled in CRP3 mode The NO_ISP mode does not offer any code protection All information provided in this document is subject to legal disclaimers NXP B V 2012 All rig
181. 345 46 47 USB2 0 device controller Table 162 USB set interrupt status register INTSETSTAT address 0x4008 0028 bit description Bit Symbol 9 0 EP_SET_INT 29 10 30 FRAME_SET_INT 31 DEV_SET_INT Reserved Description If software writes a one to one of these bits the corresponding USB interrupt status bit is set When this register is read the same value as the USB interrupt status register is returned If software writes a one to one of these bits the corresponding USB interrupt status bit is set When this register is read the same value as the USB interrupt status register is returned If software writes a one to one of these bits the corresponding USB interrupt status bit is set When this register is read the same value as the USB interrupt status register is returned Reset Access value 0 R W 0 RO 0 R W 0 R W USB interrupt routing register INTROUTING Table 163 USB interrupt routing register INTROUTING address 0x4008 002C bit description Bit Symbol Description Reset Access value 9 0 ROUTE_INT This bit can control on which hardware interrupt line 0 R W the interrupt will be generated 0 IRQ interrupt line is selected for this interrupt bit 1 FIQ interrupt line is selected for this interrupt bit 29 10 Reserved 0 RO 30 ROUTE_INT This bit can control on which hardware interrupt line 0 R W the interrupt will be generated 0 IRQ interrupt line is selected for this interrupt b
182. 4 bit description Bit Symbol Description Reset Access value 31 0 DIRP1 Selects pin direction for pin P1_n bitO0 P1_0 bit1 P1_1 O R W bit 31 P1_31 0 input 1 output GPIO port mask registers These registers affect writing and reading the MPORT registers Zeroes in these registers enable reading and writing ones disable writing and result in zeros in corresponding positions when reading Table 136 GPIO mask port 0 register MASKO address 0x5000 2080 bit description Bit Symbol Description Reset Access value 31 0 MASKPO Controls which bits corresponding to PO_n are active in the 0 R W POMPORT register bit 0 PO_O bit 1 PO_1 bit 31 PO_31 0 Read MPORT pin state write MPORT load output bit 1 Read MPORT 0 write MPORT output bit not affected All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 129 of 404 NXP Semiconductors U M1 0524 9 5 3 5 9 5 3 6 UM10524 Chapter 9 LPC1315 16 17 45 46 47 GPIO Table 137 GPIO mask port 1 register MASK1 address 0x5000 2084 bit description Bit Symbol Description Reset Access value 31 0 MASKP1 Controls which bits corresponding to P1_n are active in the 0 R W P1MPORT register bit 0 P1_0 bit 1 P1_1 bit 31 P1_ 31 0 Read MPORT pin state write MPORT load output bit 1 Read MPORT 0 write MPORT o
183. 4 43 I O configuration for pin PIO1_21 Table 98 1 O configuration for pin PlIO1_21 DCD MISO1 PIO1_21 address 0x4004 40B4 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x3 to 0x7 are reserved 0 OxO 3 PIO1_21 0x1 DCD 0x2 MISO1 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 98 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration 7 4 44 1 O configuration for pin PIO1_22 7 4 45 Table 99 I O configuration for pin PIO1_22 RI MOSI1 PIO1_22 address 0x4004 40B8 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x3 to 0x7 are reserved 0 0x0 3 PIO1_22 0x1 RI 0x2 MOSI1 4 3 MODE
184. 46 47 Power Management Unit PMU Table 50 General purpose register 4 GPREG4 address 0x4003 8014 bit description Bit Symbol Value Description Reset value 9 0 Reserved Do not write ones to this bit 0x0 10 WAKEUPHYS WAKEUP pin hysteresis enable 0x0 0 Hysteresis for WAKUP pin disabled 1 Hysteresis for WAKEUP pin enabled 31 11 GPDATA Data retained during Deep power down mode 0x0 4 4 Functional description For details of entering and exiting reduced power modes see Section 3 9 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 47 of 404 UM10524 Chapter 5 LPC1315 16 17 45 46 47 Power profiles Rev 1 17 February 2012 User manual 5 1 How to read this chapter The power profiles are available for all LPC1315 16 1 7 45 46 47 5 2 Features e Includes ROM based application services e Power Management services e Clocking services 5 3 Description The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile The power configuration routine configures the LPC1315 16 17 45 46 47 for one of the following power modes e Default mode corresponding to power configuration after reset e CPU performance mode corresponding to optimized processing capability e Efficiency mode corresponding to optimized balance of current
185. 5 16 17 45 46 47 flash sectors 360 Table 333 Code Read Protection CRP options 361 Table 334 Code Read Protection hardware software interaction 0 2 c ee eee 361 Table 335 ISP commands allowed for different CRP levels Folin dye anda e aceite ar aa Semptetuct ats 362 Table 336 ISP command summary 363 Table 337 ISP Unlock command 5 363 Table 338 ISP Set Baud Rate command 364 Table 339 ISP Echo command 5 364 Table 340 ISP Write to RAM command 365 Table 341 ISP Read Memory command 365 Table 342 ISP Prepare sector s for write operation command 0c e eee eee eee 366 Table 343 ISP Copy command 367 Table 344 ISP Go command 055 367 Table 345 ISP Erase sector command 368 Table 346 ISP Blank check sector command 368 Table 347 ISP Read Part Identification command 368 Table 348 LPC1315 16 1 7 45 46 47 device identification NUMDETS osaeran aE ax aha eae a desea ar aes 369 Table 349 ISP Read Boot Code version number COMMANG iiicgs hone ae a ee aa ae ee ae 369 Table 350 ISP Compare command 369 Table 351 ReadUID command 005 370 Table 352 ISP Return Codes Summary 370 Table 353 IAP Command Summary 372 Table 354 IAP Prepare sector s for write operation UM10524 Table 355 Tab
186. 5 16 17 45 46 47 incorporates several distinct memory regions shown in the following figures Figure 2 shows the overall map of the entire address space from the user program viewpoint following reset The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals Each peripheral of either type is allocated 16 kB of space This allows simplifying the address decoding for each peripheral On chip flash programming memory The LPC1315 1 6 1 7 45 46 47 contain up to 128 kB on chip flash program memory The flash can be programmed using In System Programming ISP or In Application Programming IAP via the on chip boot loader software Flash updates via USB are supported as well The flash memory is divided into 4 kB sectors with each sector consisting of 16 pages Individual pages of 256 byte each can be erased using the IAP erase page command All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 8 of 404 NXP Semiconductors U M1 0524 Chapter 2 LPC1315 16 17 45 46 47 Memory mapping 2 2 2 EEPROM The LPC1315 16 1 7 45 46 47 contain 2 kB or 4 kB of on chip byte erasable and byte programmable EEPROM data memory The EEPROM can be programmed using In Application Programming IAP via the on chip boot loader so
187. 65 Endpoint commands Symbol A TR RF TV UM10524 Access RW RW RW RW RW Description Active The buffer is enabled HW can use the buffer to store received OUT data or to transmit data on the IN endpoint Software can only set this bit to 1 As long as this bit is set to one software is not allowed to update any of the values in this 32 bit word In case software wants to deactivate the buffer it must write a one to the corresponding skip bit in the USB Endpoint skip register Hardware can only write this bit to zero It will do this when it receives a short packet or when the NBytes field transitions to zero or when software has written a one to the skip bit Disabled 0 The selected endpoint is enabled 1 The selected endpoint is disabled If a USB token is received for an endpoint that has the disabled bit set hardware will ignore the token and not return any data or handshake When a bus reset is received software must set the disable bit of all endpoints to 1 Software can only modify this bit when the active bit is zero Stall 0 The selected endpoint is not stalled 1 The selected endpoint is stalled The Active bit has always higher priority than the Stall bit This means that a Stall handshake is only sent when the active bit is zero and the stall bit is one Software can only modify this bit when the active bit is zero Toggle Reset When software sets this bit to one
188. 6Bi_MATO pin is HIGH if pinned out 0x3 Toggle the corresponding External Match bit output 7 6 EMC1 External Match Control 1 Determines the functionality of External Match 1 00 0x0 Do Nothing 0x1 Clear the corresponding External Match bit output to 0 CT16Bi_MAT1 pin is LOW if pinned out 0x2 Setthe corresponding External Match bit output to 1 CT16Bi_MAT1 pin is HIGH if pinned out 0x3 Toggle the corresponding External Match bit output 9 8 EMC2 External Match Control 2 Determines the functionality of External Match 2 00 0x0 Do Nothing 0x1 Clear the corresponding External Match bit output to 0 CT16Bi_MAT2 pin is LOW if pinned out 0x2 Setthe corresponding External Match bit output to 1 CT16Bi_MAT2 pin is HIGH if pinned out 0x3 Toggle the corresponding External Match bit output 11 EMC3 External Match Control 3 Determines the functionality of External Match 3 Table 281 00 10 shows the encoding of these bits 0x0 Do Nothing 0x1 Clear the corresponding External Match bit output to 0 CT16Bi_MATS3 pin is LOW if pinned out 0x2 Setthe corresponding External Match bit output to 1 CT16Bi_MATS pin is HIGH if pinned out 0x3 Toggle the corresponding External Match bit output 31 Reserved user software should not write ones to reserved bits The value read from a 12 reserved bit is not defined Table 281 External match control EMR 11 10 EMR 9 8 Function EMR 7 6 or EMR 5 4 00 01 10 11 Do Nothing
189. 7 0x1 CT16B0_CAP1 0x2 RXD 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 95 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration 7 4 40 I O configuration for PIO1_18 Table 95 I O configuration for PIO1_18 CT16B1_CAP1 TXD PIO1_18 address 0x4004 40A8 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x3 to 0x7 are reserved 0 0x0 PIO1_18 0x1 CT16B1_CAP1 0x2 TXD 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 IN
190. 7 BELT ane SCI enire reei 258 14 9 5 Shift register DAT 267 14 7 5 1 Selecting the appropriate IFC data rate and duty 14 9 6 Arbitration and synchronization logic 267 oe 258 14 9 7 Serial clock generator 268 14 7 6 IC Control Clear register CONCLR 259 14 9 8 Timing andcontrol 5 269 14 7 7 12C Monitor mode control register MMCTRL 259 14 9 9 Control register CONSET and CONCLR 269 14 7 7 1 Interrupt in Monitor mode 260 14 9 10 Status decoder and status register 269 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 401 of 404 NXP Semiconductors UM10524 Chapter 23 Supplementary information 14 10 Det ails of I2C operating modes 269 14 11 5 3 State Ox08 0 eee eee 288 14 10 1 Master Transmitter mode 270 14 11 5 4 State Ox10 0 0 0 cee eee 289 14 10 2 Master Receiver mode 274 14 11 6 Master Transmitter states 289 14 10 3 Slave Receivermode 277 14 11 6 1 State 0x18 00 0 0 eee eee 289 14 10 4 Slave Transmitter mode 281 14 11 6 2 State Ox20 20 0 0c ce eee 289 14 10 5 Miscellaneous states 283 14 11 6 3 State Ox28 0 0 0 0 0s 289 14 10 5 1 STAT OxF8 0200000
191. 7 February 2012 306 of 404 NXP Semiconductors U M1 0524 Chapter 15 LPC1315 16 17 45 46 47 16 bit counter timers CT16B0 1 15 7 13 Rules for single edge controlled PWM outputs 1 All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle timer is set to zero unless their match value is equal to zero 2 Each PWM output will go HIGH when its match value is reached If no match occurs i e the match value is greater than the PWM cycle length the PWM output remains continuously LOW 3 If a match value larger than the PWM cycle length is written to the match register and the PWM signal is HIGH already then the PWM signal will be cleared on the next start of the next PWM cycle 4 If a match register contains the same value as the timer reset value the PWM cycle length then the PWM output will be reset to LOW on the next clock tick Therefore the PWM output will always consist of a one clock tick wide positive pulse with a period determined by the PWM cycle length i e the timer reload value 5 If a match register is set to zero then the PWM output will go to HIGH the first time the timer goes back to zero and will stay HIGH continuously Note When the match outputs are selected to perform as PWM outputs the timer reset MRnR and timer stop MRnS bits in the Match Control Register MCR must be set to zero except for the match register setting the PWM cycle length For this register set the MRnR bit
192. 7 I O configuration pin configured as digital output driver pin configured as digital input pin configured as analog input Fig 8 The 10 ns glitch filter is available on selected pins only Standard I O pin configuration VDD VDD open drain enable T output enable oE ati ESD data output k E strong pull down ESD Vss pull up enable weak pull down repeater mode enable pull down enable data input 10 ns RC GLITCH FILTER select analog input select data inverter select glitch filter analog input 002aaf695 7 3 1 7 3 2 UM10524 Pin function The FUNC bits in the IOCON registers can be set to GPIO FUNC 0 or to a peripheral function If the pins are GPIO pins the DIR registers determine whether the pin is configured as an input or output see Section 9 5 3 3 For any peripheral function the pin direction is controlled automatically depending on the pin s functionality The DIR registers have no effect for peripheral functions Pin mode The MODE bits in the IOCON register allow the selection of on chip pull up or pull down resistors for each pin or select the repeater mode The possible on chip resistor configurations are pull up enabled pull down enabled or no pull up pull down The default value is pull up enabled The repeater mode enables the pull up resistor if the pin is at a logic HIGH and enables the pull d
193. 71 show the bit assignments in the FAUSSTART and FMSSTOP registers respectively Table 370 Flash module signature start register FMSSTART 0x4003 C020 bit description Bit Symbol Description Reset value 16 0 START Signature generation start address corresponds to AHB byte 0 address bits 20 4 31 17 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined Table 371 Flash module signature stop register FMSSTOP 0x4003 C024 bit description Bit Symbol Value Description Reset value 16 0 STOP BIST stop address divided by 16 corresponds to AHB 0 byte address 20 4 17 SIG_START Start control bit for signature generation 0 0 Signature generation is stopped 1 Initiate signature generation 31 18 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined 21 16 4 Signature generation result registers The signature generation result registers return the flash signature produced by the embedded signature generator The 128 bit signature is reflected by the four registers FMSWO0O FMSW1 FMSW2 and FMSWS3 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 380 of 404 NXP Semiconductors U M1 0524 UM10524 21 16 5 21 16 6 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming The generated flash sig
194. 8 0x1A02 0525 LPC1317FBD64 0x1A02 0525 value part depen dent UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 33 of 404 NXP Semiconductors U M1 0524 Chapter 3 LPC1315 16 17 45 46 47 System control block 3 6 Reset Reset has four sources on the LPC1315 16 17 45 46 47 the RESET pin Watchdog Reset Power On Reset POR and Brown Out Detect BOD In addition there is an ARM software reset The RESET pin is a Schmitt trigger input pin Assertion of chip Reset by any source once the operating voltage attains a usable level starts the IRC causing reset to remain asserted until the external Reset is de asserted the oscillator is running and the flash controller has completed its initialization On the assertion of any reset source Arm software reset POR BOD reset External reset and Watchdog reset the following processes are initiated 1 The IRC starts up After the IRC start up time maximum of 6 us on power up the IRC provides a stable clock output 2 The boot code in the ROM starts The boot code performs the boot tasks and may jump to the flash 3 The flash is powered up This takes approximately 100 us Then the flash initialization sequence is started which takes about 250 cycles When the internal Reset is removed the processor begins executing at address 0 which
195. 8 1257 SS Early Feed Event l l Watchdog J Reset Conditions WINDOW 0x1200 WARNINT Ox3FF TC 0x2000 Fig 56 Early Watchdog Feed with Windowed Mode Enabled UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 333 of 404 NXP Semiconductors UM10524 Chapter 17 LPC1315 16 17 45 46 47 Windowed Watchdog Timer wocLk 4 J UUAA Watchdog 125A Y 1259 X 1258 y 1257 X Counter Early Feed Event Watchdog Reset Conditions WINDOW 0x1200 WARNINT Ox3FF TC 0x2000 Fig 57 Correct Watchdog Feed with Windowed Mode Enabled woer VJ VIVIAVI AA Watchdog Counter Watchdog Interrupt 0403 X 0402 X 0401 ia 03FE avian ors Conditions WINDOW 0x1200 WARNINT 0x3FF TC 0x2000 Fig 58 Watchdog Warning Interrupt UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 334 of 404 UM10524 Chapter 18 LPC1315 16 17 45 46 47 System tick timer Rev 1 17 February 2012 User manual 18 1 How to read this chapter The system tick timer SysTick timer is part of the ARM Cortex M3 core and is identical for all LPC1315 16 17 45 46 47 parts 18 2 Basic confi
196. 8 System Timer Current value register 0 Table 312 R W 0x01C System Timer Calibration value register 0x4 Table 313 1 Reset Value reflects the data stored in used bits only It does not include content of reserved bits UM10524 18 5 1 18 5 2 System Timer Control and status register The SYST_CSR register contains control information for the SysTick timer and provides a status flag This register is part of the ARM Cortex M3 core system timer register block For a bit description of this register see Section 21 5 4 This register determines the clock source for the system tick timer Table 310 SysTick Timer Control and status register SYST_CSR 0xE000 E010 bit description Bit Symbol Description Reset value 0 ENABLE System Tick counter enable When 1 the counter is enabled 0 When 0 the counter is disabled 1 TICKINT System Tick interrupt enable When 1 the System Tick interrupt 0 is enabled When 0 the System Tick interrupt is disabled When enabled the interrupt is generated when the System Tick counter counts down to 0 2 CLKSOURCE System Tick clock source selection When 1 the system clock 0 CPU clock is selected When 0 the output clock from the system tick clock divider SYSTICKDIV is selected as the reference clock In this case the core clock must be at least 2 5 times faster than the reference clock otherwise the count values are unpredictable 15 3 Reserved user software should not write ones
197. A corresponds to a defined state of the PC bus Fig 41 Format and states in the Master Receiver mode UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 276 of 404 NXP Semiconductors U M1 0524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller 14 10 3 Slave Receiver mode In the slave receiver mode a number of data bytes are received from a master transmitter see Figure 42 To initiate the slave receiver mode ADR and CON must be loaded as follows Table 263 ADR usage in Slave Receiver mode Bit 7 6 5 4 3 2 1 0 Symbol own slave 7 bit address GC The upper 7 bits are the address to which the 12C block will respond when addressed by a master If the LSB GC is set the 12C block will respond to the General Call address 0x00 otherwise it ignores the General Call address Table 264 CONSET used to initialize Slave Receiver mode Bit 7 6 5 4 3 2 1 0 Symbol I2EN STA STO SI AA Value 1 0 0 0 1 The C bus rate settings do not affect the 12C block in the slave mode I2EN must be set to logic 1 to enable the I2C block The AA bit must be set to enable the I2C block to acknowledge its own slave address or the General Call address STA STO and SI must be reset When ADR and CON have been initialized the 1 C block waits until it is addressed by its own slave address followed by the data direction b
198. AM USB descriptors data structure UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 182 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 198 USBD_HID_INIT_PARAM class structure Member mem_base mem_size max_reports pad intf_desc report_data HID_GetReport UM10524 Description uint32_tuint32_t USBD_HID_INIT_PARAM mem_base Base memory location from where the stack can allocate data and buffers Remark The memory address set in this field should be accessible by USB DMA controller Also this value should be aligned on 4 byte boundary uint32_tuint32_t USBD_HID_INIT_PARAM mem_size The size of memory buffer which stack can use Remark The mem_size should be greater than the size returned by USBD_HID_API GetMemSize routine uint8_tuint8_t USBD_HID_INIT_PARAM max_reports Number of HID reports supported by this instance of HID class driver uint8_tuint8_t USBD_HID_INIT_PARAM pad 3 3 uint8_t uint8_t USBD_HID_INIT_PARAM intf_desc Pointer to the HID interface descriptor within the descriptor array USB_HID_REPORT_T USB_HID_REPORT_T USBD_HID_INIT_PARAM report_data Pointer to an array of HID report descriptor data structure Remark This array should be of global scope ErrorCode_t ErrorCode_t USBD_HID_INIT_PARAM HI
199. AM address where data bytes are to be written This address should be a word boundary Number of Bytes Number of bytes to be written Count should be a multiple of 4 Return Code CMD SUCCESS ADDR_ERROR Address not on word boundary ADDR_NOT_MAPPED COUNT_ERROR Byte count is not multiple of 4 PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to download data to RAM Data should be in UU encoded format This command is blocked when code read protection is enabled Example W 268436224 4 lt CR gt lt LF gt writes 4 bytes of data to address 0x1000 0300 Read Memory lt address gt lt no of bytes gt The data stream is followed by the command success return code The check sum is sent after transmitting 20 UU encoded lines The checksum is generated by adding raw data before UU encoding bytes and is reset after transmitting 20 UU encoded lines The length of any UU encoded line should not exceed 61 characters bytes i e it can hold 45 data bytes When the data fits in less than 20 UU encoded lines then the check sum is of actual number of bytes sent The host should compare it with the checksum of the received bytes If the check sum matches then the host should respond with OK lt CR gt lt LF gt to continue further transmission If the check sum does not match then the host should respond with RESEND lt CR gt lt LF gt In response the ISP command handler sends the data again Table 341
200. AP MAT signal 31 28 Reserved user software should not write ones to reserved bits The value read from NA a reserved bit is not defined 1 Note that this does not require that the timer match function appear on a device pin 20 5 2 A D Global Data Register GDR The A D Global Data Register contains the result of the most recent A D conversion This includes the data DONE and Overrun flags and the number of the A D channel to which the data relates UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 348 of 404 NXP Semiconductors UM10524 UM10524 Chapter 20 LPC1315 16 17 45 46 47 ADC Table 325 A D Global Data Register GDR address 0x4001 C004 bit description Bit Symbol 3 0 15 4 V_VREF 23 16 26 24 CHN 29 27 30 OVERRUN 31 DONE Description Reset Value Reserved These bits always read as zeros 0 When DONE is 1 this field contains a binary fraction representing X the voltage on the ADn pin selected by the SEL field divided by the voltage on the Vpp pin or as it falls within the range of VREFP to VREFN Zero in the field indicates that the voltage on the ADn pin was less than equal to or close to that on Vgs VREFN while OxFFF indicates that the voltage on ADn was close to equal to or greater than that on Vpp VREFP Reserved These bits always read as zeros 0
201. Acknowledge bits this number contained in I2STA corresponds to a defined state of the PC bus Fig 40 Format and states in the Master Transmitter mode UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 273 of 404 NXP Semiconductors U M1 0524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller 14 10 2 Master Receiver mode In the master receiver mode a number of data bytes are received from a slave transmitter see Figure 41 The transfer is initialized as in the master transmitter mode When the START condition has been transmitted the interrupt service routine must load DAT with the 7 bit slave address and the data direction bit SLA R The SI bit in CON must then be cleared before the serial transfer can continue When the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received the serial interrupt flag SI is set again and a number of status codes in STAT are possible These are 0x40 0x48 or 0x38 for the master mode and also 0x68 0x78 or OxBO if the slave mode was enabled AA 1 The appropriate action to be taken for each of these status codes is detailed in Table 262 After a Repeated START condition state 0x10 the 12C block may switch to the master transmitter mode by loading DAT with SLA W UM10524 All information provided in this document is subjec
202. All rights reserved User manual Rev 1 17 February 2012 403 of 404 NXP Semiconductors UM10524 Chapter 23 Supplementary information 21 8 6 Interrupts during ISP 356 21 14 IAP commands 000 e ee eeee 371 21 8 7 Interrupts during IAP 357 21 14 1 Prepare sector s for write operation 373 21 8 8 RAM used by ISP command handler 357 21 142 Copy RAMtoflash 373 21 8 9 RAM used by IAP command handler 357 21 14 38 Erase Sector s 2 0000 eee 374 21 9 USB communication protocol 357 21 14 4 Blank check sector s 375 21 9 1 Usage note 2 cee eee eee eee 358 21 14 5 Read Part Identification number 375 21 10 Boot process flowchart 0 0 359 21 14 6 Read Boot code version number 375 21 11 Sector numbers 22 20055 360 LJA Compare lt addr ss1 lt adorass2 lt no of bytes gt 2 eee eee ee 376 21 12 Code Read Protection CRP 360 21 148 Reinvoke ISP 0 0c e eee 376 21 12 1 ISP entry protection 362 21 14 9 ReadUID 2000 cece eee eee 376 21 13 ISP commands 00 eee eee eee 363 21 14 10 Erase page 0 eee eee eee 377 21 13 1 Unlock lt Unlock code gt 005 363 21 14 11 Write EEPROM 377 21 13 2 Set Baud Rate lt Baud Rate gt lt stop bit gt
203. BD48 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4mm SOT313 2 LPC1347FBD64 LQFP64 LQFP64 plastic low profile quad flat package 64 leads body 10 x 10 x SOT314 2 1 4mm LPC1315FHN33 HVQFN33 plastic thermal enhanced very thin quad flat package no leads 33 terminals n a body 7 x 7 x 0 85 mm LPC1315FBD48 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4mm SOT313 2 LPC1316FHN33 HVQFN33 plastic thermal enhanced very thin quad flat package no leads 33 terminals n a body 7 x 7 x 0 85 mm LPC1316FBD48 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4mm SOT313 2 LPC1317FHN33 HVQFN33 plastic thermal enhanced very thin quad flat package no leads 33 terminals n a body 7 x 7 x 0 85 mm LPC1317FBD48 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4mm SOT313 2 LPC1317FBD64 LQFP64 LQFP64 plastic low profile quad flat package 64 leads body 10 x 10 x SOT314 2 1 4mm UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 5 of 404 NXP Semiconductors U M1 0524 Chapter 1 LPC1315 16 17 45 46 47 Introductory information Table 2 Ordering options Type number Flash SRAM kB EEPROM USB ___ SSP I2C FM ADC GPIO kB kB device channels pins SRAMO USB SRAM1 SRAM LPC1345FHN33 32 8 2 2 yes 2 1 8 26 LPC1345FBD48 32 8 2 2 yes 2 1 8 40
204. C bus interface is configured using the following registers 1 Pins The l2C pin functions and the 12C mode are configured in the IOCON register block Table 60 and Table 61 2 Power and peripheral clock In the SYSAHBCLKCTRL register set bit 5 Table 19 3 Reset Before accessing the I2C block ensure that the 12C_RST_N bit bit 1 in the PRESETCTRL register Table 7 is set to 1 This de asserts the reset signal to the I2C block 14 3 Features e The l C bus contains a standard I C compliant bus interface with two pins e The I C bus interfaces may be configured as Master Slave or Master Slave e Supports Fast mode Plus e Arbitration is handled between simultaneously transmitting masters without corruption of serial data on the bus e Programmable clock allows adjustment of 12C transfer rates e Data transfer is bidirectional between masters and slaves e Serial clock synchronization allows devices with different bit rates to communicate via one serial bus e Serial clock synchronization is used as a handshake mechanism to suspend and resume serial transfer e Optional recognition of up to four distinct slave addresses e Monitor mode allows observing all I C bus traffic regardless of slave address e 2C bus can be used for test and diagnostic purposes 14 4 Applications Interfaces to external 12C standard parts such as serial RAMs LCDs tone generators other microcontrollers etc 14 5 General descriptio
205. C hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave When a bus error is detected the 12C block immediately switches to the not addressed slave mode releases the SDA and SCL lines sets the interrupt flag and loads the status register with 0x00 This status code may be used to vector to a state service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in Table 267 I2C state service routines This section provides examples of operations that must be performed by various 12C state service routines This includes e Initialization of the 12C block after a Reset e 2C Interrupt Service e The 26 state service routines providing support for all four 12C operating modes All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 286 of 404 NXP Semiconductors U M1 0524 14 10 8 14 10 9 14 10 10 14 10 11 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller Initialization In the initialization example the 12C block is enabled for both master and slave modes For each mode a buffer is used for transmission and reception The initialization routine performs the following functions e ADR is loaded with the part s own slave address and the General Call bit GC e The I C interrupt enable and int
206. C1315 16 17 45 46 47 I2C bus controller 14 11 8 8 State 0x98 Previously addressed with General Call Data has been received NOT ACK has been returned Received data will not be saved Not addressed Slave mode is entered 1 Write 0x04 to CONSET to set the AA bit 2 Write 0x08 to CONCLR to clear the SI flag 3 Exit 14 11 8 9 State OxA0 A STOP condition or Repeated START has been received while still addressed as a Slave Data will not be saved Not addressed Slave mode is entered 1 Write 0x04 to CONSET to set the AA bit 2 Write 0x08 to CONCLR to clear the SI flag 3 Exit 14 11 9 Slave Transmitter states 14 11 9 1 State 0xA8 Own Slave Address Read has been received ACK has been returned Data will be transmitted ACK bit will be received Load DAT from Slave Transmit buffer with first data byte Write 0x04 to CONSET to set the AA bit Write 0x08 to CONCLR to clear the SI flag Set up Slave Transmit mode data buffer Increment Slave Transmit buffer pointer Exit ona FWD 14 11 9 2 State 0xBO Arbitration lost in Slave Address and R W bit as bus Master Own Slave Address Read has been received ACK has been returned Data will be transmitted ACK bit will be received STA is set to restart Master mode after the bus is free again Load DAT from Slave Transmit buffer with first data byte Write 0x24 to CONSET to set the STA and AA bits Write 0x08 to CONCLR to clear the SI flag Set up S
207. CT32Bn_MAT2 whether or not this 0 output is connected to its pin When a match occurs between the TC and MRz2 this bit can either toggle go LOW go HIGH or do nothing Bits EMR 9 8 control the functionality of this output This bit is driven to the CT32BO_MAT2 CT32B1_MAT2 pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH External Match 3 This bit reflects the state of output CT32Bn_MATS3 whether or not this 0 output is connected to its pin When a match occurs between the TC and MR3 this bit can either toggle go LOW go HIGH or do nothing Bits EMR 11 10 control the functionality of this output This bit is driven to the CT32B3_MAT0 CT32B1_MATS3 pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH External Match Control 0 Determines the functionality of External Match 0 00 Do Nothing Clear the corresponding External Match bit output to 0 CT32Bi_MATO pin is LOW if pinned out Set the corresponding External Match bit output to 1 CT32Bi_MATO pin is HIGH if pinned out Toggle the corresponding External Match bit output External Match Control 1 Determines the functionality of External Match 1 00 Do Nothing Clear the corresponding External Match bit output to 0 CT32Bi_MAT1 pin is LOW if pinned out Set the corresponding External Match bit output to 1 CT32Bi_MAT1 pin is HIGH if pinned out All information provided in this document is subject to legal disclaimers
208. CTRL R W 0x048 Smart Card Interface Control register Enables and 0 Table 226 configures the Smart Card Interface feature RS485CTRL R W 0x04C RS 485 EIA 485 Control Contains controls to configure 0O Table 227 various aspects of RS 485 EIA 485 modes UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 204 of 404 NXP Semiconductors U M1 0524 Chapter 12 LPC1315 16 17 45 46 47 USART Table 203 Register overview USART base address 0x4000 8000 Name Access Address Description Reset Reference offset valuel RS485ADRMATCH R W 0x050 RS 485 EIA 485 address match Contains the address 0 Table 228 match value for RS 485 EIA 485 mode RS485DLY R W 0x054 RS 485 EIA 485 direction control delay 0 Table 229 SYNCCTRL R W 0x058 Synchronous mode control register 0 Table 230 1 Reset Value reflects the data stored in used bits only It does not include reserved bits content UM10524 12 5 1 12 5 2 USART Receiver Buffer Register when DLAB 0 Read Only The RBR is the top byte of the USART RX FIFO The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface The LSB bit 0 contains the first received data bit If the character received is less than 8 bits the unused MSBs are padded with zeros The Divisor Latch Access Bit DLAB in the LCR must be zero in order to ac
209. Chapter 16 LPC1315 16 17 45 46 47 32 bit counter timers CT32B0 1 Bits 7 4 of this register are also used to enable and configure the capture clears timer feature This feature allows for a designated edge on a particular CAP input to reset the timer to all zeros Using this mechanism to clear the timer on the leading edge of an input pulse and performing a capture on the trailing edge permits direct pulse width measurement using a single capture input without the need to perform a subtraction operation in software Table 298 Count Control Register CTCR address 0x4001 4070 CT32B0 and 0x4001 8070 CT32B1 bit description Bit Symbol Value Description Reset value 1 0 CTM Counter Timer Mode This field selects which rising PCLK 00 edges can increment Timer s Prescale Counter PC or clear PC and increment Timer Counter TC Remark If Counter mode is selected in the CTCR bits 2 0 in the Capture Control Register CCR must be programmed as 000 0x0 Timer Mode every rising PCLK edge 0x1 Counter Mode TC is incremented on rising edges on the CAP input selected by bits 3 2 0x2 Counter Mode TC is incremented on falling edges on the CAP input selected by bits 3 2 0x3 Counter Mode TC is incremented on both edges on the CAP input selected by bits 3 2 3 2 CIS Count Input Select In counter mode when bits 1 0 in this 00 register are not 00 these bits select which CAP pin or comparator output is sampled for clocking R
210. DSLEEPCFG register WWD0T interrupt using the interrupt wake up register 1 Table 39 The WWDT interrupt must be enabled in the NVIC The WWDT interrupt must be set in the WWDT MOD register Reset from the watchdog timer The WWDT reset must be set in the WWDT MOD register In this case the watchdog oscillator must be running in Deep sleep mode see PDSLEEPCFG register and the WDT must be enabled in the SYSAHBCLKCTRL register e USB wake up signal using the interrupt wake up register 1 Table 39 For details see Section 10 7 6 e GPIO group interrupt signal see Table 39 Remark If the watchdog oscillator is running in Deep sleep mode its frequency determines the wake up time Power down mode In Power down mode the system clock to the processor is disabled as in Sleep mode All analog blocks are powered down except for the BOD circuit and the watchdog oscillator which must be selected or deselected during Power down mode in the PDSLEEPCFG register The main clock and therefore all peripheral clocks are disabled except for the clock to the watchdog timer if the watchdog oscillator is selected The IRC itself and the flash are powered down decreasing power consumption compared to Deep sleep mode Remark Do not set the LOCK bit in the WWDT MOD register Table 301 when the IRC is selected as a clock source for the WWDT This prevents the part from entering the Power down mode correctly All information provided in th
211. D_GetReport USBD_HANDLE_T hHid USB_SETUP_PACKET pSetup uint8_t pBuffer uintl6_t length USBD_HANDLE_T hHid USB_SETUP_PACKET pSetup uint8_t pBuffer uintl6_t length HID get report callback function This function is provided by the application software This function gets called when host sends a HID_REQUEST_GET_REPORT request The setup packet data Remark HID reports are sent via interrupt IN endpoint also This function is called only when report request is received on control endpoint Application should implement HID_EpIn_Hdlr to send reports to host via interrupt IN endpoint Parameters 1 hHid Handle to HID function driver 2 pSetup Pointer to setup packet received from host 3 pBuffer Pointer to a pointer of data buffer containing report data Pointer to pointer is used to implement zero copy buffers See Zero Copy Data Transfer model for more details on zero copy concept 4 length Amount of data copied to destination buffer Returns The call back should returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_xxx For other error conditions All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 183 of 404 NXP Semiconductors U M1 0524 Chapter 11
212. EPTOGGLE Access Address Description Reset Reference offset value R W 0x028 USB set interrupt status 0 Table 162 register R W 0x02C USB interrupt routing register Table 163 R 0x034 USB Endpoint toggle register Table 164 10 6 1 USB Device Command Status register DEVCMDSTAT Table 152 USB Device Command Status register DEVCMDSTAT address 0x4008 0000 bit description Bit Symbol Value Description Reset Access value 6 0 DEV_ADDR USB device address After bus reset the address is reset to 0 RW 0x00 If the enable bit is set the device will respond on packets for function address DEV_ADDR When receiving a SetAddress Control Request from the USB host software must program the new address before completing the status phase of the SetAddress Control Request 7 DEV_EN USB device enable If this bit is set the HW will start responding 0 RW on packets for function address DEV_ADDR 8 SETUP SETUP token received If a SETUP token is received and 0 RWC acknowledged by the device this bit is set As long as this bit is set all received IN and OUT tokens will be NAKed by HW SW must clear this bit by writing a one If this bit is zero HW will handle the tokens to the CTRL EPO as indicated by the CTRL EPO IN and OUT data information programmed by SW 9 PLL_ON USB Clock PLL control 0 RW 0 USB_NeedClk functional 1 USB_NeedClk always 1 Clock will not be stopped in case of suspend 10 Reserved 0 RO 11 LPM_SUP LPM Support 1 RW 0 LPM not
213. General Call address has been received while the General Call bit GC in the ADR register is set 3 A data byte has been received while the 12C is in the master receiver mode 4 A data byte has been received while the 12C is in the addressed slave receiver mode The AA bit can be cleared by writing 1 to the AAC bit in the CONCLR register When AA is 0 a not acknowledge HIGH level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 A data byte has been received while the I C is in the master receiver mode 2 A data byte has been received while the 12C is in the addressed slave receiver mode I2C Status register STAT Each I C Status register reflects the condition of the corresponding 12C interface The 1 C Status register is Read Only Table 246 I2C Status register STAT 0x4000 0004 bit description Bit Symbol Description Reset value 2 0 These bits are unused and are always 0 0 7 3 Status These bits give the actual status information about the 12C Ox1F interface 31 8 Reserved The value read from a reserved bit is not defined The three least significant bits are always 0 Taken as a byte the status register contents represent a status code There are 26 possible status codes When the status code is OxF8 there is no relevant information available and the SI bit is not set All other 25 status codes correspond to defined 12C states When any of these states en
214. ICOMP Compare value MSB register Holds the 16 MSBs of the 0x0000 FFFF compare value which is compared to the counter 31 16 Reserved RI Mask MSB register Table 320 RI Mask MSB register MASK_H address 0x4006 4014 bit description Bit Symbol Description Reset value 15 0 RIMASK Mask register This register holds the 16 MSBs of the mask value A 0 one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register causes the comparison of the register bits to be always true 31 16 Reserved RI Counter MSB register Table 321 RI Counter MSB register COUNTER_H address 0x4006 4018 bit description Bit Symbol Description Reset value 15 0 RICOUNTER 16 LSBs of the up counter Counts continuously unless RITEN bit 0 in RICTRL register is cleared or debug mode is entered if enabled by the RITNEBR bit in RICTRL Can be loaded to any value in software 31 16 Reserved All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 343 of 404 NXP Semiconductors U M1 0524 Chapter 19 LPC1315 16 17 45 46 47 Repetitive Interrupt Timer RI 19 6 RI timer operation UM10524 Following reset the counter begins counting up from 0 Whenever the counter value equals the 48 bit value programmed into the COMPVAL and COMPVAL_H registers the interrup
215. ISO1 35 PIO1_22 RI MOSIH 51 PIO1_23 CT16B1_MAT1 24 SSEL1 UM10524 LQFP48 37 43 48 13 26 38 18 HVQFN33 28 All information provided in this document is subject to legal disclaimers 3 3 3 Reset state v uv v clcic 1 0 1 0 Description P101_10 General purpose digital input output pin P101_11 General purpose digital input output pin P101_13 General purpose digital input output pin DTR Data Terminal Ready output for USART CT16B0_MATO Match output 0 for 16 bit timer 0 TXD Transmitter output for USART P101_14 General purpose digital input output pin DSR Data Set Ready input for USART CT16B0_MAT1 Match output 1 for 16 bit timer 0 RXD Receiver input for USART P101_15 General purpose digital input output pin DCD Data Carrier Detect input for USART CT16B0_MAT2 Match output 2 for 16 bit timer 0 SCK1 Serial clock for SSP1 PIO1_16 General purpose digital input output pin RI Ring Indicator input for USART CT16B0_CAPO0 Capture input 0 for 16 bit timer 0 PIO1_17 General purpose digital input output pin CT16B0_CAP1 Capture input 1 for 16 bit timer 0 RXD Receiver input for USART P101_18 General purpose digital input output pin CT16B1_CAP1 Capture input 1 for 16 bit timer 1 TXD Transmitter output for USART P101_19 General purpose digital input output pin DTR Data Terminal R
216. Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 I O configuration for pin PIO1_25 Table 102 I O configuration for pin PIO1_25 CT32B0_MAT1 PIO1_25 address 0x4004 40C4 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x2 to 0x7 are reserved 0 0x0 PIO1_25 0x1 CT32B0_MAT1 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 101 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration
217. Interface Control register This register allows the USART to be used in asynchronous smart card applications All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 226 of 404 NXP Semiconductors UM10524 UM10524 12 5 19 Chapter 12 LPC1315 16 17 45 46 47 USART Table 226 USART Smart Card Interface Control register SCICTRL address 0x4000 8048 bit description Bit 4 3 7 5 15 8 31 16 Symbol Value Description SCIEN NACKDIS PROTSEL TXRETRY XTRAGUARD Smart Card Interface Enable Smart card interface disabled Asynchronous half duplex smart card interface is enabled NACK response disable Only applicable in T 0 A NACK response is enabled A NACK response is inhibited Protocol selection as defined in the ISO7816 3 standard T 0 T 1 Reserved When the protocol selection T bit above is 0 the field controls the maximum number of retransmissions that the USART will attempt if the remote device signals NACK When NACK has occurred this number of times plus one the Tx Error bit in the LSR is set an interrupt is requested if enabled and the USART is locked until the FIFO is cleared When the protocol selection T bit above is 0 this field indicates the number of bit times ETUs by which the guard time after a character transmitted by the USART should exceed the nominal 2 b
218. LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 67 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration 7 4 4 I O configuration for pin PIOO_3 Table 59 1 O configuration for pin PlIOO_3 USB_VBUS PIO0_3 address 0x4004 400C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x2 to 0x7 are reserved 0 0x0 PIOO_3 0x1 USB_VBUS 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 5 I O configuration for pin PIOO_4 Table 60 I O configuration for pin PIOO_4 SCL PIO0O_4 address 0x4004 4010 bi
219. LT n command result table Fig 62 IAP parameter passing 21 14 1 Prepare sector s for write operation This command makes flash write erase operation a two step process Table 354 IAP Prepare sector s for write operation command Command Prepare sector s for write operation Input Command code 50 decimal Param0 Start Sector Number Param1 End Sector Number should be greater than or equal to start sector number Return Code CMD SUCCESS BUSY INVALID_SECTOR Result None Description This command must be executed before executing Copy RAM to flash or Erase Sector s command Successful execution of the Copy RAM to flash or Erase Sector s command causes relevant sectors to be protected again The boot sector can not be prepared by this command To prepare a single sector use the same Start and End sector numbers 21 14 2 Copy RAM to flash See Section 21 13 7 for limitations on the write to flash process UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 373 of 404 NXP Semiconductors UM10524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming Table 355 IAP Copy RAM to flash command Command Input Return Code Result Description Copy RAM to flash Command code 51 decimal Param0 DST Destination flash address where data bytes are to be writ
220. L_PC1315 16 17 no USB Symbol Description oO 22 3 t g a R Si ae Vppa 59 analog 3 3 V pad supply voltage This should be nominally the same voltage as Vpp but should be isolated to minimize noise and error This voltage is used to power the ADC This pin should be tied to 3 3 V if the ADC is not used VREFN 48 ADC negative reference voltage This should be nominally the same voltage as Vss but should be isolated to minimize noise and error Level on this pin is used as a reference for ADC VREFP 64 ADC positive reference voltage This should be nominally the same voltage as Vppa but should be isolated to minimize noise and error Level on this pin is used as a reference for ADC This pin should be tied to 3 3 V if the ADC is not used Vssa 55 analog ground 0 V reference This should nominally be the same voltage as Vss but should be isolated to minimize noise and error Vpp 10 8 6 Supply voltage to the internal regulator and the external 33 44 29 rail On LQFP48 and HVQFN33 packages this pin is also 58 connected to the 3 3 V ADC supply and reference voltage Vss 7 5 33 d Ground 54 41 1 Pin state at reset for default function Input O Output PU internal pull up enabled IA inactive no pull up down enabled F floating floating pins if not used should be tied to ground or power to minimize power consumption 2 See Figure 9 for the reset pad configur
221. N sss see dig pate sana Sane aia 72 PIO1_4 address 0x4004 4070 bit description88 Table 66 I O configuration for pin SWCLK PIOO_10 Table 85 O configuration for pin PlO1_5 CT32B1_CAP1 SCKO0 CT16B0O_MAT2 SWCLK_PIO0_10 PIO1_5 address 0x4004 4074 bit description89 address 0x4004 4028 bit description 73 Table 86 I O configuration for pin PIO1_7 PIO1_7 address Table 67 I O configuration for pin 0x4004 407C bit description 89 TDI PIOO_11 AD0 CT32B0_MAT3 Table 87 I O configuration for pin PIO1_8 PIO1_8 address TDI_PIOO_11 address 0x4004 402C bit 0x4004 4080 bit description 90 CESCHPLON wese vias pee eee ee baa ee Be eS 73 Table 88 I O configuration for pin PIO1_10 PIO1_ 10 Table 68 I O configuration for pin address 0x4004 4088 bit description 91 TMS PIOO_12 AD1 CT32B1_CAPO Table 89 I O configuration for pin PlO1_11 PIO1_11 TMS_PIOO_12 address 0x4004 4030 bit address 0x4004 408C bit description 91 CESCHPLON o 5655 eas ba Saeed eS natat RES 74 Table 90 I O configuration for Table 69 I O configuration for pin PIO1_13 DTR CT16B0_MATO TXD PIO1_ 13 TDO PIOO_13 AD2 CT32B1_MATO address 0x4004 4094 bit description 92 TDO_PIOO_13 address 0x4004 4034 bit Table 91 I O configuration for description s ccecce ipari iresi arimei 75 PIO1_14 DSR CT16B0_MAT1 RXD PIO1_14 Table 70 I O configuration for pin address 0x4004 4098 bit description 93 TRST PIOO_14 AD3 CT3
222. O configuration Table 104 I O configuration for pin PIO1_27 CT32B0_MAT3 TXD PIO1_27 address 0x4004 40CC bit description Bit Symbol Value Description Reset value 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 50 I O configuration for pin PIO1_28 Table 105 I O configuration for pin PlIO1_28 CT32B0_CAP0 SCLK PIO1_28 address 0x4004 40D0 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x3 to 0x7 are reserved 0 0x0 PIO1_28 0x1 CT32B0_CAPO 0x2 SCLK 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 A
223. ODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 7 ADMODE Selects Analog Digital mode 1 0 Analog input mode 1 Digital functional mode 8 FILTR Selects 10 ns input glitch filter 0 0 Filter disabled 1 Filter enabled 9 Reserved 0 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 I O configuration for pin PIOO_16 Table 72 I O configuration for pin PIOO_16 AD5 CT32B1_MAT3 WAKEUP PIOO_16 address 0x4004 4040 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function This pin functions as WAKEUP pin if the 0 0x0 0x1 0x2 All information provided in this document is subject to legal disclaimers LPC1315 16 17 45 46 47 is in Deep power down mode regardless of the value of FUNC Values 0x3 to 0x7 are reserved PIOO_16 AD5 CT32B1_MATS NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 78 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 72 I
224. Out interrupt STALL bit must only be set when it is the last packet during the data phase for this Control Transfer UM10524 10 7 3 Generic endpoint single buffering To enable single buffering software must set the corresponding USB EP Buffer Config bit to zero In the USB EP Buffer in use register software can indicate which buffer is used in this case When software wants to transfer data it programs the different bits in the Endpoint command status entry and sets the active bits The hardware will transmit receive multiple packets for this endpoint until the NBytes value is equal to zero When NBytes goes to zero hardware clears the active bit and sets the corresponding interrupt status bit All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 152 of 404 NXP Semiconductors U M1 0524 UM10524 10 7 4 10 7 5 10 7 5 1 10 7 5 2 10 7 5 3 Chapter 10 LPC 1345 46 47 USB2 0 device controller Software must wait until hardware has cleared the Active bit to change some of the command status bits This prevents hardware from overwriting a new value programmed by software with some old values that were still cached If software wants to disable the active bit before the_hardware has finished handling the complete buffer it can do this by setting the corresponding endpoint skip bit in USB endpoi
225. P USBD_HANDLE_T hUsb uint32_t EPNum uint8_t pData uint32_t cnt Function to write data to be sent on the requested endpoint This function is called by USB stack and the application layer to send data on the requested endpoint hUsbHandle to the USB device stack EPNumEndpoint number as per USB specification ie An EP1_IN is represented by 0x81 number pDataPointer to the data buffer from where data is to be copied cntNumber of bytes to write Parameters 1 hUsb Handle to the USB device stack 2 EPNum Endpoint number as per USB specification ie An EP1_IN is represented by 0x81 number 3 pData Pointer to the data buffer from where data is to be copied 4 cnt Number of bytes to write Returns Returns the number of bytes written void void USBD_HW_API WakeUp USBD_HANDLE_T hUsb Function to generate resume signaling on bus for remote host wake up This function is called by application layer to remotely wake up host controller when system is in suspend state Application should indicate this remote wake up capability by setting USB_CONFIG_REMOTE_WAKEUP in bmAttributes of Configuration Descriptor Also this routine will generate resume signalling only if host enables USB_FEATURE_REMOTE_WAKEUP by sending SET_FEATURE request before suspending the bus hUsbHandle to the USB device stack Parameters 1 hUsb Handle to the USB device stack Returns Nothing ErrorCode_t ErrorCode_t USBD_HW_API EnableEven
226. PIO1_3 7 4 46 I O configuration for pin PIO1_24 100 7 4 29 I O configuration for pin PIO1_4 7 4 47 I O configuration for pin PIO1_25 101 7 4 30 I O configuration for pin PIO1_5 7 4 48 I O configuration for pin PIO1_26 102 7 4 31 I O configuration for pin PIO1_7 7 4 49 I O configuration for pin PIO1_27 102 7 4 32 I O configuration for pin PIO1_8 7 4 50 I O configuration for pin PIO1_28 103 7 4 33 I O configuration for pin PIO1_10 7 4 51 I O configuration for pin PIO1_29 104 7 4 34 I O configuration for pin PIO1_11 7 4 52 I O configuration for pin PlIO1_31 105 7 4 35 I O configuration for PIO1_13 Chapter 8 LPC1315 16 17 45 46 47 Pin configuration 8 1 Pin configuration 000 eee eee 8 1 1 Pin description 00085 106 Chapter 9 LPC1315 16 17 45 46 47 GPIO 9 1 How to read this chapter 9 5 1 9 Pin interrupt falling edge register 125 9 2 Basic configuration 00e005 9 5 1 10 Pin interrupt status register 126 9 3 Features ay edis needstuwdiassaneGuawadeas 9 5 2 ta irate interrupt register ma an min pin interrupt di loeb ondis ap a 9 5 2 1 Grouped interrupt control register 126 3 group interrupt features 9 5 2 2 GPIO grouped interrupt port polarity 9 3 3 GPIO port features 005 oo YEJIS TEIS e jee ies See
227. PLL can be turned off Table 25 USB clock source select USBCLKSEL address 0x4004 80C0 bit description Bit Symbol Value Description Reset value 1 0 SEL USB clock source Values 0x2 and 0x3 are 0x00 reserved 0x0 USB PLL out 0x1 Main clock 31 2 Reserved 0x00 USB clock source divider register USBCLKDIV This register allows the USB clock usb_clk to be divided to 48 MHz The usb_clk can be shut down by setting the DIV bits to 0x0 Table 26 USB clock source divider USBCLKDIV address 0x4004 80C8 bit description Bit Symbol Description Reset value 7 0 DIV USB clock divider values 0x01 0 Disable USB clock 1 Divide by 1 to 255 Divide by 255 31 8 Reserved 0x00 CLKOUT clock source select register CLKOUTSEL This register selects the signal visible on the CLKOUT pin Any oscillator or the main clock can be selected To change the clock source visible on the CLKOUT pin first enable the new clock source with the currently selected clock source still running change the clock source using the SEL bit and then remove the current clock source If the clock source selected on the CLKOUT pin is powered down in the PDRUNCFG or PDSLEEPCFG registers this same clock source must be re enabled before another clock source can be selected through this register All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 20
228. R SCK1 0x0000090 Table 97 PIO1_ 21 read write 0x0B4 I O configuration for pin PIO1_21 DCD MISO1 0x0000090 Table 98 PIO1_22 read write 0x0B8 I O configuration for pin PIO1_22 RI MOSI1 0x0000090 Table 99 PIO1_23 read write O0x0BC I O configuration for pin 0x0000090 Table 100 PIO1_23 CT16B1_MAT1 SSEL1 PIO1_24 read write O0x0CO I O configuration for pin PIO1_24 0x0000090 Table 101 CT32B0_MATO PIO1_25 read write 0x0C4 I O configuration for pin PlO1_25 CT32BO_MAT1 0x0000090 Table 102 PIO1_26 read write 0x0C8 I O configuration for pin 0x0000090 Table 103 PIO1_26 CT32B0_MAT2 RXD PIO1_27 read write Ox0CC I O configuration for pin 0x0000090 Table 104 P1O1_27 CT32B0_MAT3 TXD PIO1_28 read write O0x0DO I O configuration for pin 0x0000090 Table 105 PIO1_28 CT32B0_CAP0 SCLK PIO1_29 read write 0x0D4 I O configuration for pin PIO1_29 SCK0 0x0000090 Table 106 CT32B0_CAP1 0x0D8 Reserved PIO1_ 31 read write Ox0DC I O configuration for pin PIO1_ 31 0x0000090 Table 107 7 4 1 I O configuration for pin RESET_PIO0_0 Table 56 I O configuration for pin RESET PIOO_0 RESET_PIO0_0 address 0x4004 4000 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x2 to 0x7 are reserved 0 0x0 RESET 0x1 PIOO_0 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled
229. RL Table 8 and the SYSAHBCLKDIV register Table 18 e Selected peripherals USART SSP0 1 USB CLKOUT use individual peripheral clocks with their own clock dividers The peripheral clocks can be shut down through the corresponding clock divider registers Table 20 to Table 24 3 9 3 Sleep mode In Sleep mode the system clock to the ARM Cortex M3 core is stopped and execution of instructions is suspended until either a reset or an interrupt occurs Peripheral functions if selected to be clocked in the SYSAHBCLKCTRL register continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution Sleep mode eliminates dynamic power used by the processor itself memory systems and related controllers and internal buses The processor state and registers peripheral registers and internal SRAM values are maintained and the logic levels of the pins remain static 3 9 3 1 Power configuration in Sleep mode Power consumption in Sleep mode is configured by the same settings as in Active mode e The clock remains running e The system clock frequency remains the same as in Active mode but the processor is not clocked e Analog and digital peripherals are selected as in Active mode 3 9 3 2 Programming Sleep mode The following steps must be performed to enter Sleep mode 1 The PD bits in the PCON register must be set to the default value 0x0 2 The SLEEPDEEP bit in the ARM Cortex M3 SCR reg
230. RT1 Rx FIFO level Fig 16 Auto RTS Functional Timing bits0 7 UM10524 12 5 8 1 2 Auto CTS The Auto CTS function is enabled by setting the CTSen bit If Auto CTS is enabled the transmitter circuitry checks the CTS input before sending the next data byte When CTS is active low the transmitter sends the next byte To stop the transmitter from sending the following byte CTS must be released before the middle of the last stop bit that is currently being sent In Auto CTS mode a change of the CTS signal does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set but the Delta CTS bit in the MSR will be set Table 214 lists the conditions for generating a Modem Status interrupt Table 214 Modem status interrupt generation Enable CTSen CTS Delta CTS Delta DCD or trailing edge Modem modem MCR 7 interrupt MSR 0 RI or status status enable Delta DSR MSR 3 1 interrupt interrupt IER 7 IER 3 0 x x x x No 1 0 x 0 0 No 1 0 X 1 x Yes 1 0 x x 1 Yes 1 1 0 x 0 No 1 1 0 x 1 Yes 1 1 1 0 0 No 1 1 1 1 x Yes 1 1 1 x 1 Yes The auto CTS function typically eliminates the need for CTS interrupts When flow control is enabled a CTS state change does not trigger host interrupts because the device automatically controls its own transmitter Without Auto CTS the transmitter sends any data present in the transmit FIFO and a receiver overrun error can result Figure 17 illustrates the Auto
231. SBD_BAD_INTF_DESC Wrong interface descriptor is passed 11 5 31 USBD_DFU_INIT_PARAM USB descriptors data structure UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 178 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 196 USBD_DFU_INIT_PARAM class structure Member mem_base mem_size wtTransferSize Description uint32_tuint32_t USBD_DFU_INIT_PARAM mem_base Base memory location from where the stack can allocate data and buffers Remark The memory address set in this field should be accessible by USB DMA controller Also this value should be aligned on 4 byte boundary uint32_tuint32_t USBD_DFU_INIT_PARAM mem_size The size of memory buffer which stack can use Remark The mem_size should be greater than the size returned by USBD_DFU_API GetMemSize routine uintl6_tuintl6_t USBD_DFU_INIT_PARAM wTransferSize DFU transfer block size in number of bytes This value should match the value set in DFU descriptor provided as part of the descriptor array pad uintl6_tuintl6_t USBD_DFU_INIT_PARAM pad intf_desc uint8_t uint8_t USBD_DFU_INIT_PARAM intf_desc Pointer to the DFU interface descriptor within the descriptor array DFU_Write uint8_t uint8_t USBD_DFU_INIT_PARAM DFU_Write uint32_t block_num uint8_t src uint32_t length uint8
232. SCK1 PIO1_15 address 0x4004 409C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x4 to 0x7 are reserved 0 0x0 PIO1_15 0x1 DCD 0x2 CT16B0_MAT2 0x3 SCK1 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 93 of 404 NXP Semiconductors UM10524 UM10524 7 4 38 Chapter 7 LPC1315 16 17 45 46 47 I O configuration 0x4004 409C bit description VO configuration for pin PlO1_15 DCD CT16B0_MAT2 SCK1 PIO1_15 address Table 92 Bit Symbol 4 3 MODE 5 HYS 6 INV 9 7 10 OD 31 11 Value Description 0x0 0x1 0x2 0x3 Selects function mode on chip pull up pull down resistor control Inactive no pull down pull up resistor enabled Pull down resistor enabled Pull up resistor enabled Repeater mode Hysteresis Disable Enable Invert input Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 Reserved Open drain mode Disable Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD Reserved Reset value 0x2 001 I O configuration for pin PIO1_16 Table 93 40A0 bit description I O configuration for pin PIO1_16 RI CT16B0_CAP0 PIO1_16 address 0x4004 Bit 2 0 4 3
233. SP SPI 13 6 4 SSP SPI Status Register This read only register reflects the current status of the SPI controller Table 237 SSP SPI Status Register SR address 0x4004 000C SSPO and 0x4005 800C SSP1 bit description Bit Symbol Description Reset Value 0 TFE Transmit FIFO Empty This bit is 1 is the Transmit FIFO is 1 empty 0 if not 1 TNF Transmit FIFO Not Full This bit is 0 if the Tx FIFO is full 1 if not 1 2 RNE Receive FIFO Not Empty This bit is 0 if the Receive FIFO is 0 empty 1 if not 3 RFF Receive FIFO Full This bit is 1 if the Receive FIFO is full Oif 0 not 4 BSY Busy This bit is 0 if the SPI controller is idle 1 if itis currently 0 sending receiving a frame and or the Tx FIFO is not empty 31 5 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 13 6 5 SSP SPI Clock Prescale Register This register controls the factor by which the Prescaler divides the SPI peripheral clock SPI_PCLK to yield the prescaler clock that is in turn divided by the SCR factor in the SSPCRO registers to determine the bit clock Table 238 SSP SPI Clock Prescale Register CPSR address 0x4004 0010 SSPO and 0x4005 8010 SSP1 bit description Bit Symbol Description Reset Value 7 0 CPSDVSR This even value between 2 and 254 by which SPI_PCLK is 0 divided to yield the prescaler output clock Bit 0 always reads as 0 31 8 Reserved Important
234. S_HDLR 0x0004000c The number of class handlers registered is greater than the number of handlers allowed by the stack ErrorCode_t ErrorCode_t USBD_CORE_API RegisterEpHandler USBD_HANDLE_T hUsb uint32_t ep_index USB_EP_HANDLER_T pfn void data Function to register interrupt event handler for the requested endpoint with USB device stack The application layer uses this function to register the custom class s EPO handler The stack calls all the registered class handlers on any EPO event before going through default handling of the event This gives the class handlers to implement class specific request handlers and also to override the default stack handling for a particular event targeted to the interface Check USB_EP_HANDLER_T for more details on how the callback function should be implemented hUsbHandle to the USB device stack ep_indexClass specific EPO handler function pfnClass specific EPO handler function dataPointer to the data which will be passed when callback function is called by the stack Parameters 1 hUsb Handle to the USB device stack 2 ep_index Class specific EPO handler function 3 pfn Class specific EPO handler function 4 data Pointer to the data which will be passed when callback function is called by the stack Returns Returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_TOO_MANY_CLASS_HDLR 0x0004000c Too many endpoint handlers
235. Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 I O configuration for pin PIO1_23 Table 100 I O configuration for pin PIO1_23 CT16B1_MAT1 SSEL1 PIO1_23 address 0x4004 40BC bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x3 to 0x7 are reserved 0 0x0 PIO1_23 0x1 CT16B1_MAT1 0x2 SSEL1 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 99 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 100 I O configuration for pin PIO1_23 CT16B1_MAT1 SSEL1 PIO1_23 address 0x4004 40BC bit description Bit Symbol Value Description Reset value 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull do
236. Symbol Description Reset Access value 31 0 PWORD Read 0 pin is LOW ext R W Write 0 clear output bit Read OxFFFF FFFF pin is HIGH Write any value 0x0000 0001 to OxFFFF FFFF set output bit Remark Only 0 or OxFFFF FFFF can be read Writing any value other than 0 will set the output bit All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 128 of 404 NXP Semiconductors U M1 0524 UM10524 9 5 3 3 9 5 3 4 Chapter 9 LPC1315 16 17 45 46 47 GPIO Table 133 GPIO port 1 word pin registers W32 to W63 addresses 0x5000 1080 to 0x5000 10FC bit description Bit Symbol Description Reset Access value 31 0 PWORD Read 0 pin is LOW ext R W Write 0 clear output bit Read OxFFFF FFFF pin is HIGH Write any value 0x0000 0001 to OxFFFF FFFF set output bit Remark Only 0 or OxFFFF FFFF can be read Writing any value other than 0 will set the output bit GPIO port direction registers Each GPIO port has one direction register for configuring the port pins as inputs or outputs Table 134 GPIO direction port 0 register DIRO address 0x5000 2000 bit description Bit Symbol Description Reset Access value 31 0 DIRPO Selects pin direction for pin PO_n bit 0 PO_0 bit1 PO_1 0 R W bit 31 PO_31 0 input 1 output Table 135 GPIO direction port 1 register DIR1 address 0x5000 200
237. T Transmit Enable Register 225 12 6 2 1_ Smartcard set up procedure 233 Teele USART Haltduplex enable register cs 226 427 Architecture 0 00 cc0seee ees 234 Chapter 13 LPC1315 16 17 45 46 47 SSP SPI 13 1 How to read this chapter 237 13 6 9 SSP SPI Interrupt Clear Register 244 13 2 Basic configuration 237 13 7 Functional description 244 13 3 FOAMS cocci da dined cand iedva dae te 237 13 7 1 Texas Instruments synchronous serial frame 13 4 General description 237 format 0 c eee ete eee ee 244 13 5 Pin description 238 13 7 2 SPI frame format 0 0005 245 P Vom i fp 13 7 2 1 Clock Polarity CPOL and Phase CPHA 13 6 Register description 005 238 GOON ae ae see sacs s ed wed a oe eas tae ese 245 13 6 1 SSP SPI Control Register One k an dels oe 239 13 7 2 2 SPI format with CPOL 0 CPHA 0 246 13 6 2 SSP SPI Control Register Tinga oree ne cee 240 13 7 2 3 SPI format with CPOL 0 CPHA 1 247 13 6 3 SSP SPI Data Register ee eee 241 13 7 2 4 SPI format with CPOL 1 CPHA 0 247 13 6 4 SSP SPI Status Register oe 242 13 7 2 5 SPI format with CPOL 1 CPHA 1 249 13 6 5 SSP SPI Clock Prescale Register 242 1373 Semiconductor Microwire frame format 249 13 6 6 SSP SPI Interrupt Mask Set Clear Register 242 413 7 3 1 Setup and hold time requirements on CS with 13 6 7 SSP SPI Raw Interrupt
238. T in Deep sleep mode Deep sleep mode eliminates all power used by analog peripherals and all dynamic power used by the processor itself memory systems and related controllers and internal buses The processor state and registers peripheral registers and internal SRAM values are maintained and the logic levels of the pins remain static Power configuration in Deep sleep mode Power consumption in Deep sleep mode is determined by the Deep sleep power configuration setting in the PDSLEEPCFG Table 40 register e The watchdog oscillator can be left running in Deep sleep mode if required for the WWDT e Ifthe IRC is locked as the WWDT clock source see Section 17 7 the IRC continues to run and clock the WWDT in Deep sleep mode independently of the setting in the PDSLEEPCFG register e The BOD circuit can be left running in Deep sleep mode if required by the application 3 9 4 2 Programming Deep sleep mode The following steps must be performed to enter Deep sleep mode 1 The PD bits in the PCON register must be set to 0x1 Table 48 2 Select the power configuration in Deep sleep mode in the PDSLEEPCFG Table 40 register 3 Determine if the WWDT clock source must be locked to override the power configuration if the IRC is selected see Section 17 7 4 If the watchdog oscillator is shut down ensure that the IRC is powered in the PDRUNCFG register and switch the clock source to IRC in the MAINCLKSEL register Table 17 This
239. TCR R W 0x004 Timer Control Register The TCR is used to control the Timer 0 Table 288 Counter functions The Timer Counter can be disabled or reset through the TCR TC R W 0x008 Timer Counter The 32 bit TC is incremented every PR 1 cycles of 0 Table 289 PCLK The TC is controlled through the TCR PR R W 0x00C Prescale Register When the Prescale Counter below is equal to 0 Table 290 this value the next clock increments the TC and clears the PC PC R W 0x010 Prescale Counter The 32 bit PC is a counter which is incremented 0 Table 291 to the value stored in PR When the value in PR is reached the TC is incremented and the PC is cleared The PC is observable and controllable through the bus interface MCR R W 0x014 Match Control Register The MCR is used to control if an interruptis 0 Table 292 generated and if the TC is reset when a Match occurs MRO R W 0x018 Match Register 0 MRO can be enabled through the MCR to reset 0 Table 293 the TC stop both the TC and PC and or generate an interrupt every time MRO matches the TC MR1 R W 0x01C Match Register 1 See MRO description 0 Table 293 MR2 R W 0x020 Match Register 2 See MRO description 0 Table 293 MR3 R W 0x024 Match Register 3 See MRO description 0 Table 293 CCR R W 0x028 Capture Control Register The CCR controls which edges of the 0 Table 294 capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place CRO RO 0
240. TRACT_CONTROL_MANAGEMENT_DESCRIPTOR bDescriptorSubtype bmCapabilities uint8_tuint8_t _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR bmCapabilities 11 5 4 CDC _CALL_MANAGEMENT_DESCRIPTOR Table 169 _CDC_CALL_MANAGEMENT_DESCRIPTOR class structure Member Description bFunctionLength uint8_tuint8 CDC_CALL_MANAGEMENT_DESCRIPTOR bFunctionLength bDescriptorType uint8 _tuint8 CDC_CALL_MANAGEMENT_DESCRIPTOR bDescriptorType t t bDescriptorSubtype uint8_tuint8_t _CDC_CALL_MANAGEMENT_DESCRIPTOR bDescriptorSubtype t t bmCapabilities uint8_tuint8 CDC_CALL_MANAGEMENT_DESCRIPTOR bmCapabilities bDatalnterface uint8_tuints CDC_CALL_MANAGEMENT_DESCRIPTOR bDataInterface 11 5 5 _CDC_HEADER_DESCRIPTOR Table 170 _CDC_HEADER_DESCRIPTOR class structure Member Description bFunctionLength uint8_tuint8_t _CDC_HEADER_DESCRIPTOR bFunctionLength bDescriptorType uint8_tuint8_t _CDC_HEADER_DESCRIPTOR bDescriptorType bDescriptorSubtype uint8_tuint8_t _CDC_HEADER_DESCRIPTOR bDescriptorSubtype bcedCDC uintl6_tuint16_t _CDC_HEADER_DESCRIPTOR bcedCDC 11 5 6 _CDC_LINE_CODING UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 159 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 171 _CDC_LINE_CODING class structure Member Descripti
241. The reset assertion threshold voltage is 2 63 V the reset de assertion threshold voltage is 2 71 V 3 2 BODINTVAL BOD interrupt level 00 0x0 Level 0 The interrupt assertion threshold voltage is 1 65 V the interrupt de assertion threshold voltage is 1 80 V 0x1 Level 1 The interrupt assertion threshold voltage is 2 22 V the interrupt de assertion threshold voltage is 2 35 V 0x2 Level 2 The interrupt assertion threshold voltage is 2 52 V the interrupt de assertion threshold voltage is 2 66 V 0x3 Level 3 The interrupt assertion threshold voltage is 2 80 V the interrupt de assertion threshold voltage is 2 90 V 4 BODRSTENA BOD reset enable 0 0 Disable reset function 1 Enable reset function 31 55 Reserved 0x00 System tick counter calibration register SYSTCKCAL This register determines the value of the SYST_CALIB register see Table 313 Table 32 System tick counter calibration SYSTCKCAL address 0x4004 8154 bit description Bit Symbol Description Reset value 25 0 CAL System tick timer calibration value 31 26 j Reserved 7 IQR delay register IRQLATENCY The IRQLATENCY register is an 8 bit register which specifies the minimum number of cycles 0 255 permitted for the system to respond to an interrupt request The intent of this register is to allow the user to select a trade off between interrupt response time and determinism All information provided in this document is subject to legal disclaimers
242. This function flushes the endpoint buffers and resets data toggle logic hUsbHandle to the USB device stack EPNumEndpoint number as per USB specification ie An EP1_IN is represented by 0x81 number Parameters 1 hUsb Handle to the USB device stack 2 EPNum Endpoint number as per USB specification ie An EP1_IN is represented by 0x81 number Returns Nothing SetStallEP void void USBD_HW_API SetStallEP USBD_HANDLE_T hUsb uint32_t EPNum Function to STALL selected USB endpoint Generates STALL signalling for requested endpoint hUsbHandle to the USB device stack EPNumEndpoint number as per USB specification ie An EP1_IN is represented by 0x81 number Parameters 1 hUsb Handle to the USB device stack 2 EPNum Endpoint number as per USB specification ie An EP1_IN is represented by 0x81 number Returns Nothing ClrStallEP void void USBD_HW_API ClrStallEP USBD_HANDLE_T hUsb uint32_t EPNum Function to clear STALL state for the requested endpoint This function clears STALL state for the requested endpoint hUsbHandle to the USB device stack EPNumEndpoint number as per USB specification ie An EP1_IN is represented by 0x81 number Parameters 1 hUsb Handle to the USB device stack 2 EPNum Endpoint number as per USB specification ie An EP1_IN is represented by 0x81 number Returns Nothing UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved
243. User manual Rev 1 17 February 2012 112 of 404 UM10524 Chapter 8 LPC1315 16 17 45 46 47 Pin configuration NXP Semiconductors Table 109 Pin description LPC1345 46 47 with USB Symbol Description gee 3 66 F g amp I ek a PIO0_9 MOSIO 37 28 18 Bl IPU I O PIO0_9 General purpose digital input output pin a r O MOSIO Master Out Slave In for SSPO O CT16B0_MAT1 Match output 1 for 16 bit timer 0 O SWO Serial wire trace output SWCLK PIOO_10 SCKO 38 29 19 BI PU SWCLK Serial wire clock and test clock TCK for JTAG CT16B0_MAT2 interface 5 0 PIO0_10 General purpose digital input output pin Z O SCKO Serial clock for SSPO O CT16B0_MAT2 Match output 2 for 16 bit timer 0 TDI PIOO_11 AD0 42 32 21 6 PU TDI Test Data In for JTAG interface CT32B0_MAT3 VO PIO0_11 General purpose digital input output pin ADO A D converter input 0 O CT32B0_MAT3 Match output 3 for 32 bit timer 0 TMS PIO0_12 AD1 44 33 22 l PU I TMS Test Mode Select for JTAG interface CT32B1_CAP0 O PIO_12 General purpose digital input output pin z l AD1 A D converter input 1 l CT32B1_CAP0 Capture input 0 for 32 bit timer 1 TDO PIO0_13 AD2 45 34 23 6 I PU O TDO Test Data Out for JTAG interface CT32B1_MATO 1 0 PIO0_13 General purpose digital input output pin z l AD2 A D converter input 2 O CT32B1_MAT0 Match output 0 for 32 bit t
244. User manual Rev 1 17 February 2012 179 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 196 USBD_DFU_INIT_PARAM class structure Member Description DFU_Read uint32_t uint32_t USBD_DFU_INIT_PARAM DFU_Read uint32_t block_num uint8_t dst uint32_t length uint32_t block_num uint8_t dst uint32_t length DFU Read callback function This function is provided by the application software This function gets called when host sends a read command block_numDestination start address dstPointer to a pointer to the source of data Pointer to pointer is used to implement zero copy buffers See Zero Copy Data Transfer model for more details on zero copy concept lengthAmount of data copied to destination buffer Parameters 1 block_num Destination start address 2 dst Pointer to a pointer to the source of data Pointer to pointer is used to implement zero copy buffers See Zero Copy Data Transfer model for more details on zero copy concept 3 length Amount of data copied to destination buffer Returns Returns DFU_STATUS_ values defined in mw_usbd_dfu h UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 180 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 196 USBD_DFU_INIT_PARAM class structure Member Descripti
245. User manual Rev 1 17 February 2012 194 of 404 UM10524 Chapter 11 LPC1345 46 47 USB on chip drivers NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 199 USBD_HW_API class structure Member Description SetTestMode ErrorCode_t ErrorCode_t USBD_HW_API SetTestMode USBD_HANDLE_T hUsb uint8_t mode Function to set high speed USB device controller in requested test mode USB IF requires the high speed device to be put in various test modes for electrical testing This USB device stack calls this function whenever it receives USB_REQUEST_CLEAR_FEATURE request for USB_FEATURE_TEST_MODE Users can put the device in test mode by directly calling this function Returns ERR_USBD_INVALID_REQ when device controller is full speed only hUsbHandle to the USB device stack modeTest mode defined in USB 2 0 electrical testing specification Parameters 1 hUsb Handle to the USB device stack 2 mode Test mode defined in USB 2 0 electrical testing specification Returns Returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK 0 On success 2 ERR_USBD_INVALID_REQ 0x00040001 Invalid test mode or Device controller is full speed only ReadEP uint32_t uint32_t USBD_HW_API ReadEP USBD_HANDLE_T hUsb uint32_t EPNum uint8_t pData Function to read data received on the requested endpoint This function is called by USB stack and the application layer to read t
246. V Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 41 I O configuration for pin PIO1_19 Table 96 I O configuration for pin PIO1_19 DTR SSEL1 PIO1_19 address 0x4004 40AC bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x3 to 0x7 are reserved 0 0x0 PIO1_19 0x1 DTR 0x2 SSEL1 4 3 MODE mode on chip pull up pull down resistor control 0x2 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 96 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 96 I O configuration for pin PIO1_19 DTR SSEL1 PIO1_19 address 0x4004 40AC bit description Bit Symbol Value Description Reset value 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 001 10 OD
247. W 0x000 Interrupt Register The IR can be written to clear interrupts The IR 0 Table 271 can be read to identify which of eight possible interrupt sources are pending TCR R W 0x004 Timer Control Register The TCR is used to control the Timer 0 Table 272 Counter functions The Timer Counter can be disabled or reset through the TCR TC R W 0x008 Timer Counter The 16 bit TC is incremented every PR 1 cycles of 0 Table 273 PCLK The TC is controlled through the TCR PR R W 0x00C Prescale Register When the Prescale Counter below is equal to 0 Table 274 this value the next clock increments the TC and clears the PC PC R W 0x010 Prescale Counter The 16 bit PC is a counter which is incremented 0 Table 275 to the value stored in PR When the value in PR is reached the TC is incremented and the PC is cleared The PC is observable and controllable through the bus interface MCR R W 0x014 Match Control Register The MCR is used to control if an interrupt is 0 Table 276 generated and if the TC is reset when a Match occurs MRO R W 0x018 Match Register 0 MRO can be enabled through the MCR to reset 0 Table 277 the TC stop both the TC and PC and or generate an interrupt every time MRO matches the TC MR1 R W 0x01C Match Register 1 See MRO description 0 Table 277 MR2 R W 0x020 Match Register 2 See MRO description 0 Table 277 MR3 R W 0x024 Match Register 3 See MRO description 0 Table 277 CCR R W 0x028 Capture Control Register The CCR controls
248. XP B V 2012 All rights reserved User manual Rev 1 17 February 2012 391 of 404 NXP Semiconductors UM10524 2204 bit description 131 Table 144 GPIO clear port 0 register CLRO address 0x5000 2280 bit description 131 Table 145 GPIO clear port 1 register CLR1 address 0x5000 2284 bit description 131 Table 146 GPIO toggle port 0 register NOTO address 0x5000 2300 bit description 132 Table 147 GPIO toggle port 1 register NOT1 address 0x5000 2304 bit description 132 Table 148 Pin interrupt registers for edge and level sensitive pins 04 134 Table 149 Fixed endpoint configuration 137 Table 150 USB device pin description 139 Table 151 Register overview USB base address 0x4008 0000 cerei dese easaetedeeed deeds 139 Table 152 USB Device Command Status register DEVCMDSTAT address 0x4008 0000 bit CGESCIIPLION 2 225 pete woe ee ea ee pitaa 140 Table 153 USB Info register INFO address 0x4008 0004 bit description 0 0022 142 Table 154 USB EP Command Status List start address EPLISTSTART address 0x4008 0008 bit Chapter 23 Supplementary information Table 174 DFU _STATUS class structure 160 Table 175 HID DESCRIPTOR class structure 161 Table 176 _HID_DESCRIPTOR _HID_DESCRIPTOR_LIS T class structure 000000 161 Ta
249. XP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 191 USBD_API_INIT_PARAM class structure Member Description USB_Configure_Event USB_CB_TUSB_CB_T USBD_API_INIT PARAM USB_Configure_Event USB_Interface_Event USB_Feature_Event virt_to_phys cache_flush Event for USB configuration number changed This event fires when a the USB host changes the selected configuration number On receiving configuration change request from host the stack enables configures the endpoints needed by the new configuration before calling this callback function Remark This event is called from USB_ISR context and hence is time critical Having delays in this callback will prevent the device from enumerating correctly or operate properly USB_CB_TUSB_CB_T USBD_API_INIT_PARAM USB_Interface_Event Event for USB interface setting changed This event fires when a the USB host changes the interface setting to one of alternate interface settings On receiving interface change request from host the stack enables configures the endpoints needed by the new alternate interface setting before calling this callback function Remark This event is called from USB_ISR context and hence is time critical Having delays in this callback will prevent the device from enumerating correctly or operate properly USB_CB_TUSB_CB_T USBD_API_INIT_PARAM USB_Feature_Event Event for USB feature changed This event fires when a the USB
250. _CAP1 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 31 I O configuration for pin PIO1_7 Table 86 1 O configuration for pin PIO1_7 PIO1_7 address 0x4004 407C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x2 to 0x7 are reserved 0 0x0 3 PIO1_7 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 89 of 404 NXP Semiconductors U M1 0524 7 4 32 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 86 1 O configuration for pin PIO1_7 PIO1_7 address 0x4004 407C bit
251. _t bwPollTimeout uint32_t block_num uint8_t src uint32_t length uint8_t bwPollTimeout DFU Write callback function This function is provided by the application software This function gets called when host sends a write command For application using zero copy buffer scheme this function is called for the first time with block_numDestination start address srcPointer to a pointer to the source of data Pointer to pointer is used to implement zero copy buffers See Zero Copy Data Transfer model for more details on zero copy concept bwPollTimeoutPointer to a 3 byte buffer which the callback implementer should fill with the amount of minimum time in milliseconds that the host should wait before sending a subsequent DFU_GETSTATUS request lengthNumber of bytes to be written Parameters 1 block_num Destination start address 2 src Pointer to a pointer to the source of data Pointer to pointer is used to implement zero copy buffers See Zero Copy Data Transfer model for more details on zero copy concept 3 bwPollTimeout Pointer to a 3 byte buffer which the callback implementer should fill with the amount of minimum time in milliseconds that the host should wait before sending a subsequent DFU_GETSTATUS request 4 length Number of bytes to be written Returns Returns DFU_STATUS_ values defined in mw_usbd_dfu h UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved
252. a buffer Initialize Slave data counter Exit ar OUO N gt State 0x68 Arbitration has been lost in Slave Address and R W bit as bus Master Own Slave Address Write has been received ACK has been returned Data will be received and ACK will be returned STA is set to restart Master mode after the bus is free again Write 0x24 to CONSET to set the STA and AA bits Write 0x08 to CONCLR to clear the SI flag Set up Slave Receive mode data buffer Initialize Slave data counter Exit ar WO N gt State 0x70 General call has been received ACK has been returned Data will be received and ACK returned 1 Write 0x04 to CONSET to set the AA bit 2 Write 0x08 to CONCLR to clear the SI flag 3 Set up Slave Receive mode data buffer All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 291 of 404 NXP Semiconductors U M1 0524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller 4 Initialize Slave data counter 5 Exit 14 11 8 4 State 0x78 Arbitration has been lost in Slave Address R W bit as bus Master General call has been received and ACK has been returned Data will be received and ACK returned STA is set to restart Master mode after the bus is free again Write 0x24 to CONSET to set the STA and AA bits Write 0x08 to CONCLR to clear the SI flag Set up Slave Receive mode dat
253. a buffer Initialize Slave data counter Exit ar WD gt 14 11 8 5 State 0x80 Previously addressed with own Slave Address Data has been received and ACK has been returned Additional data will be read Read data byte from DAT into the Slave Receive buffer Decrement the Slave data counter skip to step 5 if not the last data byte Write 0x0C to CONCLR to clear the SI flag and the AA bit Exit Write 0x04 to CONSET to set the AA bit Write 0x08 to CONCLR to clear the SI flag Increment Slave Receive buffer pointer Exit ONOaAR OD 14 11 8 6 State 0x88 Previously addressed with own Slave Address Data has been received and NOT ACK has been returned Received data will not be saved Not addressed Slave mode is entered 1 Write 0x04 to CONSET to set the AA bit 2 Write 0x08 to CONCLR to clear the SI flag 3 Exit 14 11 8 7 State 0x90 Previously addressed with General Call Data has been received ACK has been returned Received data will be saved Only the first data byte will be received with ACK Additional data will be received with NOT ACK 1 Read data byte from DAT into the Slave Receive buffer 2 Write 0x0C to CONCLR to clear the SI flag and the AA bit 3 Exit UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 292 of 404 NXP Semiconductors U M1 0524 Chapter 14 LP
254. a hardware handshaking TX permit signal CTS has gone false or with software handshaking when it receives an XOFF character DC3 Software can set this bit again when it detects that the TX permit signal has gone true or when it receives an XON DC1 character 31 8 Reserved USART Half duplex enable register Remark The HDEN register should be disabled when in smart card mode or IrDA mode smart card and IrDA by default run in half duplex mode After reset the USART will be in full duplex mode meaning that both TX and RX work independently After setting the HDEN bit the USART will be in half duplex mode In this mode the USART ensures that the receiver is locked when idle or will enter a locked state after having received a complete ongoing character reception Line conflicts must be handled in software The behavior of the USART is unpredictable when data is presented for reception while data is being transmitted For this reason the value of the HDEN register should not be modified while sending or receiving data or data may be lost or corrupted Table 225 USART Half duplex enable register HDEN addresses 0x4000 8040 bit description Bit Symbol Value Description Reset value 0 HDEN Half duplex mode enable 0 0 Disable half duplex mode 1 Enable half duplex mode 31 1 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined USART Smart Card
255. a has been received ACK has been returned Data will be read from DAT Additional data will be received If this is the last data byte then NOT ACK will be returned otherwise ACK will be returned 1 Read data byte from DAT into Master Receive buffer 2 Decrement the Master data counter skip to step 5 if not the last data byte 3 Write 0x0C to CONCLR to clear the SI flag and the AA bit UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 290 of 404 NXP Semiconductors U M1 0524 14 11 7 4 14 11 8 14 11 8 1 14 11 8 2 14 11 8 3 UM10524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller Exit Write 0x04 to CONSET to set the AA bit Write 0x08 to CONCLR to clear the SI flag Increment Master Receive buffer pointer Exit ON ODO OO Ff State 0x58 Data has been received NOT ACK has been returned Data will be read from DAT A STOP condition will be transmitted 1 Read data byte from DAT into Master Receive buffer 2 Write 0x14 to CONSET to set the STO and AA bits 3 Write 0x08 to CONCLR to clear the SI flag 4 Exit Slave Receiver states State 0x60 Own Slave Address Write has been received ACK has been returned Data will be received and ACK returned Write 0x04 to CONSET to set the AA bit Write 0x08 to CONCLR to clear the SI flag Set up Slave Receive mode dat
256. address 0 This pin also serves as the debug select input LOW level selects the JTAG boundary scan HIGH level selects the ARM SWD debug mode 1 0 PIO0_0 General purpose digital input output pin PIOO_1 CLKOUT 5 4 3 B LPU VO PIO0_1 General purpose digital input output pin A CT32B0_MAT2 LOW level on this pin during reset starts the ISP command handler O CLKOUT Clockout pin O CT32B0_MAT2 Match output 2 for 32 bit timer 0 PIOO_2 SSELO 13 10 8 B IPU O PIO0_2 General purpose digital input output pin CT16B0_CAP0 VO SSELO Slave select for SSPO l CT16B0_CAP0 Capture input 0 for 16 bit timer 0 PIOO_3 19 14 9 B LPU IO PIO0_3 General purpose digital input output pin UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 106 of 404 NXP Semiconductors U M1 0524 Chapter 8 LPC1315 16 17 45 46 47 Pin configuration Table 108 Pin description L_PC1315 16 17 no USB Symbol Description o oO Bee ses j l l lt Fd 2 PIOO_4 SCL 20 15 10 IA 0 PIO0_4 General purpose digital input output pin open drain O SCL l C bus clock input output open drain High current sink only if 2C Fast mode Plus is selected in the I O configuration register PIOO_5 SDA 21 16 1 IA O PIO0_5 General purpose digital input output pin open drain O SDA C bus data inpu
257. address set in this field should be accessible by USB DMA controller Also this value should be aligned on 4 byte boundary uint32_tuint32_t USBD_MSC_INIT_PARAM mem_size The size of memory buffer which stack can use Remark The mem_size should be greater than the size returned by USBD_MSC_API GetMemSize routine uint8_t uint8_t USBD_MSC_INIT_PARAM InquiryStr Pointer to the 28 character string This string is sent in response to the SCSI Inquiry command Remark The data pointed by the pointer should be of global scope uint32_tuint32 t USBD_MSC_INI1 PARAM BlockCount Number of blocks uint32_tuint32 t USBD_MSC_INI present in the mass storage device PARAM BlockSize Block size in num uint32_tuint32 ber of bytes t USBD_MSC_INI1 PARAM MemorySize Memory size in number of bytes uint8_t uint8 t USBD_MSC_IN T_PARAM intf_desc Pointer to the interface descriptor within the descriptor array void void USBD_MSC_INIT_PARAM MSC_Write uint32_t offset uint8_t src uint32_t length uint32_t offset uint8_t src uint32_t length MSC Write callback function This function is provided by the application software This function gets called when host sends a write command offsetDestination start address srcPointer to a pointer to the source of data Pointer to pointer is used to implement zero copy buffers See Zero Copy Data Transfer model for more details
258. ain data transmitted by some other slave on the bus which was actually addressed by the master All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 260 of 404 NXP Semiconductors U M1 0524 UM10524 14 7 7 2 14 7 8 14 7 9 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller Following all of these interrupts the processor may read the data register to see what was actually transmitted on the bus Loss of arbitration in Monitor mode In monitor mode the 12C module will not be able to respond to a request for information by the bus master or issue an ACK Some other slave on the bus will respond instead This will most probably result in a lost arbitration state as far as our module is concerned Software should be aware of the fact that the module is in monitor mode and should not respond to any loss of arbitration state that is detected In addition hardware may be designed into the module to block some all loss of arbitration states from occurring if those state would either prevent a desired interrupt from occurring or cause an unwanted interrupt to occur Whether any such hardware will be added is still to be determined I2C Slave Address registers ADR 1 2 3 These registers are readable and writable and are only used when an I C interface is set to slave mode In master mode this register has no effect The
259. ake up 0 0 Disabled 1 Enabled 31 22 Reserved z Deep sleep mode configuration register PDSLEEPCFG The bits in this register BOD_PD and WDTOSC_OD can be programmed to control aspects of Deep sleep and Power down modes The bits are loaded into corresponding bits of the PDRUNCFG register when Deep sleep mode or Power down mode is entered Remark Hardware forces the analog blocks to be powered down in Deep sleep and Power down modes according to the power configuration described in Section 3 9 4 1 and Section 3 9 5 1 An exception are the exception of BOD and watchdog oscillator which can be configured to remain running through this register The WDTOSC_PD value written to the PDSLEEPCFG register is overwritten if the LOCK bit in the WWDT MOD register see Table 301 is set See Section 17 7 for details Table 40 Deep sleep mode configuration register PDSLEEPCFG address 0x4004 8230 bit description Bit Symbol Value Description Reset value 2 0 Reserved 111 3 BOD_PD BOD power down control for Deep sleep and 1 Power down mode 1 Powered down 0 Powered All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 30 of 404 NXP Semiconductors U M1 0524 UM10524 3 5 36 Chapter 3 LPC1315 16 17 45 46 47 System control block Table 40 Deep sleep mode configuration register PDSLEEPCFG address 0x4004 8230 bit descriptio
260. al disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 368 of 404 NXP Semiconductors UM10524 UM10524 21 13 12 21 13 13 Table 348 LPC1315 16 17 45 46 47 device identification numbers Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming Device LPC1345FHN33 LPC1345FBD48 LPC1346FHN33 LPC1346FBD48 LPC1347FHN33 LPC1347FBD48 LPC1347FBD64 LPC1315FHN33 LPC1315FBD48 LPC1316FHN33 LPC1316FBD48 LPC1317FHN33 LPC1317FBD48 LPC1317FBD64 Hex coding 0x2801 0541 0x2801 0541 0x0801 8542 0x0801 8542 0x0802 0543 0x0802 0543 0x0802 0543 0x3A01 0523 0x3A01 0523 0x1A01 8524 0x1A01 8524 0x1A02 0525 0x1A02 0525 0x1A02 0525 Read Boot code version number Table 349 ISP Read Boot Code version number command Command K Input None Return Code CMD _SUCCESS followed by 2 bytes of boot code version number in ASCII format It is to be interpreted as lt byte1 Major gt lt byte0 Minor gt Description This command is used to read the boot code version number Compare lt address1 gt lt address2 gt lt no of bytes gt Table 350 ISP Compare command Command M Input Address1 DST Starting flash or RAM address of data bytes to be compared This address should be a word boundary Address2 SRC Starting flash or RAM address of data bytes to be compared This address should be a word boundary Number of Bytes Number of bytes to be compared should
261. al purpose digital input output pin AD6 A D converter input 6 CT16B1_MAT1 Match output 1 for 16 bit timer 1 MISO1 Master In Slave Out for SSP1 PIO0_23 General purpose digital input output pin AD7 A D converter input 7 NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 108 of 404 NXP Semiconductors UM10524 Table 108 Pin description L_PC1315 16 17 no USB Chapter 8 LPC1315 16 17 45 46 47 Pin configuration Symbol P1O1_0 CT32B1_MATO PIO1_1 CT32B1_MAT1 PIO1_2 CT32B1_MAT2 PIO1_3 CT32B1_MAT3 PIO1_4 CT32B1_CAPO PIO1_5 CT32B1_CAP1 PIO1_7 PIO1_8 PIO1_10 PIO1_11 PlO1_13 DTR CT16B0_MATO0 TXD PIO1_14 DSR CT16B0_MAT1 RXD PlO1_15 DCD CT16BO_MAT2 SCK1 P1O1_16 RI CT16B0_CAPO PlO1_17 CT16BO_CAP1 RXD PIO1_18 CT16B1_CAP1 TXD UM10524 gt LQFP64 34 50 32 39 12 43 47 49 57 63 23 28 LQFP48 36 37 43 48 HVQFN33 28 All information provided in this document is subject to legal disclaimers 1 Reset state Type Description P101_0 General purpose digital input output pin CT32B1_MATO Match output 0 for 32 bit timer 1 PIO1_1 General purpose digital input output pin CT32B1_MAT1 Match output 1 for 32 bit timer 1 PIO1_2 General purpose digital input output pin CT32B1_MAT2 Match output 2 for 32 bit timer 1 P101_3 General purpose digital input out
262. al serial transfer can commence Forced access to the I2C bus In some applications it may be possible for an uncontrolled source to cause a bus hang up In such situations the problem may be caused by interference temporary interruption of the bus or a temporary short circuit between SDA and SCL If an uncontrolled source generates a superfluous START or masks a STOP condition then the I2C bus stays busy indefinitely If the STA flag is set and bus access is not obtained within a reasonable amount of time then a forced access to the I C bus is possible This is achieved by setting the STO flag while the STA flag is still set No STOP condition is transmitted The 1 C hardware behaves as if a STOP condition was received and is able to transmit a START condition The STO flag is cleared by hardware see Figure 45 I lt time limit STA flag STO flag SDA line SCL line start condition Fig 45 Forced access to a busy I2C bus All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 285 of 404 NXP Semiconductors U M1 0524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller 14 10 6 4 I C bus obstructed by a LOW level on SCL or SDA 14 10 6 5 UM10524 14 10 7 An 2C bus hang up can occur if either the SDA or SCL line is held LOW by any device on the bus If the SCL line is obstructed pulled
263. alue 31 0 _MPORTPO Masked port register bit O PO_O bit 1 PO_1 bit31 ext R W P0_31 0 Read pin is LOW and or the corresponding bit in the MASK register is 1 write clear output bit if the corresponding bit in the MASK register is 0 1 Read pin is HIGH and the corresponding bit in the MASK register is 0 write set output bit if the corresponding bit in the MASK register is 0 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 130 of 404 NXP Semiconductors U M1 0524 UM10524 9 5 3 7 9 5 3 8 9 5 3 9 Chapter 9 LPC1315 16 17 45 46 47 GPIO Table 141 GPIO masked port 1 pin register MPIN1 address 0x5000 2184 bit description Bit Symbol Description Reset Access value 31 0 _MPORTP1 Masked port register bit O P1_0 bit 1 P1_1 bit31 ext R W P1_31 0 Read pin is LOW and or the corresponding bit in the MASK register is 1 write clear output bit if the corresponding bit in the MASK register is 0 1 Read pin is HIGH and the corresponding bit in the MASK register is 0 write set output bit if the corresponding bit in the MASK register is 0 GPIO port set registers Output bits can be set by writing ones to these registers regardless of MASK registers Reading from these register returns the port s output bits regardless of pin directions Table 142 GPIO set port 0
264. ameter data structure Table 191 USBD_API_INIT_PARAM class structure All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 156 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers USB device stack core API functions structure Table 194 USBD_CORE_API class structure e Device Firmware Upgrade DFU class function driver DFU descriptors data structure Table 196 USBD_DFU_INIT_PARAM class structure DFU class API functions structure This module exposes functions which interact directly with the USB device controller hardware Table 195 USBD_DFU_API class structure e HID class function driver struct Table 175 _HID_DESCRIPTOR class structure struct Table 177 _HID_REPORT_T class structure USB descriptors data structure Table 198 USBD_HID_INIT_PARAM class structure HID class API functions structure This structure contains pointers to all the functions exposed by the HID function driver module Table 199 USBD_ HW_API class structure e USB device controller driver Hardware API functions structure This module exposes functions which interact directly with the USB device controller hardware Table 199 USBD_HW_API class structure
265. and Command Read boot code version number Input Command code 55 decimal Parameters None Return Code CMD SUCCESS Result Result0 2 bytes of boot code version number Read as lt byte1 Major gt lt byte0 Minor gt Description This command is used to read the boot code version number UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 375 of 404 NXP Semiconductors UM10524 UM10524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming 21 14 7 Compare lt address1 gt lt address2 gt lt no of bytes gt 21 14 8 21 14 9 Table 360 IAP Compare command Command Input Return Code Result Description Compare Command code 56 decimal Param0 DST Starting flash or RAM address of data bytes to be compared This address should be a word boundary Param1 SRC Starting flash or RAM address of data bytes to be compared This address should be a word boundary Param2 Number of bytes to be compared should be a multiple of 4 CMD_SUCCESS COMPARE_ERROR COUNT_ERROR Byte count is not a multiple of 4 ADDR_ERROR ADDR_NOT_MAPPED Result0 Offset of the first mismatch if the Status Code is COMPARE_ERROR This command is used to compare the memory contents at two locations The result may not be correct when the source or destination includes any of the first 512 byt
266. andler takes appropriate action according to the data received on the USB bus hUsbHandle to the USB device stack Parameters 1 hUsb Handle to the USB device stack Returns Nothing void void USBD_HW_API Reset USBD_HANDLE_T hUsb Function to Reset USB device stack and hardware controller Reset USB device stack and hardware controller Disables all endpoints except EPO Clears all pending interrupts and resets endpoint transfer queues This function is called internally by pUsbApi gt hw gt init and from reset event hUsbHandle to the USB device stack Parameters 1 hUsb Handle to the USB device stack Returns Nothing void void USBD_HW_API ForceFullSpeed USBD_HANDLE_T hUsb uint32_t cfg Function to force high speed USB device to operate in full speed mode This function is useful for testing the behavior of current device when connected to a full speed only hosts hUsbHandle to the USB device stack cfgWhen 1 set force full speed or 0 clear force full speed Parameters 1 hUsb Handle to the USB device stack 2 cfg When 1 set force full speed or 0 clear force full speed Returns Nothing All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 190 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 199 USBD_HW_API class structure Member D
267. anual Rev 1 17 February 2012 126 of 404 NXP Semiconductors U M1 0524 Chapter 9 LPC1315 16 17 45 46 47 GPIO Table 126 GPIO grouped interrupt port 0 polarity registers PORT_POLO addresses 0x4005 C020 GROUPO INT and 0x4006 0020 GROUP1 INT bit description Bit Symbol Description Reset Access value 31 0 POLO Configure pin polarity of port O pins for group interrupt Bitn 1 corresponds to pin PO_n of port 0 0 the pin is active LOW If the level on this pin is LOW the pin contributes to the group interrupt 1 the pin is active HIGH If the level on this pin is HIGH the pin contributes to the group interrupt Table 127 GPIO grouped interrupt port 1 polarity registers PORT_POL1 addresses 0x4005 C024 GROUPO INT and 0x4006 0024 GROUP 1 INT bit description Bit Symbol Description Reset Access value 31 0 POL1 Configure pin polarity of port 1 pins for group interrupt Bitn 1 s corresponds to pin P1_n of port 1 0 the pin is active LOW If the level on this pin is LOW the pin contributes to the group interrupt 1 the pin is active HIGH If the level on this pin is HIGH the pin contributes to the group interrupt 9 5 2 3 GPIO grouped interrupt port enable registers The grouped interrupt port enable registers enable the pins which contribute to the grouped interrupt Each port is associated with its own port enable register and the values of both registers together determine which pins contrib
268. are mode can be used in a half duplex way under control of a higher layer protocol in which the source of SCLK toggles it in groups of N cycles whenever data is to be sent in either direction N being the number of bits character When the LPC1315 16 1 7 45 46 47 USART is the clock source CSRC 1 such half duplex operation can lead to the rather artificial seeming requirement of writing a dummy character to the Transmitter Holding Register in order to generate 8 clocks so that a character can be received The CCCLR bit provides a more natural way of programming half duplex reception When the higher layer protocol dictates that the LPC1315 16 17 45 46 47 USART should receive a character software should write the All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 230 of 404 NXP Semiconductors U M1 0524 Chapter 12 LPC1315 16 17 45 46 47 USART SYNCCTRL register with CSCEN 1 and CCCLR 1 After the USART has sent N clock cycles and thus received a character it clears the CSCEN bit If more characters need to be received thereafter software can repeat setting CSCEN and CCCLR Aside from such half duplex operation the primary use of CSCEN 1 is with SSDIS 0 so that start bits indicate the transmission of each character in each direction 12 6 Functional description UM10524 12 6 1 RS 485 EIA 485 modes of operation The
269. at produced the result in the V_VREF bits This bit is cleared by reading this register 31 DONE This bit is set to 1 when an A D conversion completes It is cleared 0 when this register is read 20 5 5 A D Status Register STAT The A D Status register allows checking the status of all A D channels simultaneously The DONE and OVERRUN flags appearing in the DRn register for each A D channel are mirrored in ADSTAT The interrupt flag the logical OR of all DONE flags is also found in ADSTAT Table 328 A D Status Register STAT address 0x4001 C030 bit description Bit Symbol Description Reset Value 7 0 DONE These bits mirror the DONE status flags that appear in the result 0 register for each A D channel n 15 8 OVERRUN These bits mirror the OVERRRUN status flags that appear inthe 0 result register for each A D channel n Reading ADSTAT allows checking the status of all A D channels simultaneously 16 ADINT This bit is the A D interrupt flag It is one when any of the 0 individual A D channel Done flags is asserted and enabled to contribute to the A D interrupt via the ADINTEN register 31 17 Reserved Unused always 0 0 20 5 6 A D Trim register TRM This register will be set by the boot code on start up It contains the trim values for the DAC and the ADC The offset trim values for the ADC can be overwritten by the user All 12 bits are visible when this register is read UM10524 All information provided in thi
270. atchdog feed prior to reaching the value of WDWINDOW will also cause a watchdog reset Watchdog Timer Constant register The TC register determines the time out value Every time a feed sequence occurs the value in the TC is loaded into the Watchdog timer The TC resets to 0x00 OOFF Writing a value below OxFF will cause 0x00 OOFF to be loaded into the TC Thus the minimum time out interval is Twoctk x 256 x 4 If the WDPROTECT bit in WDMOD 1 an attempt to change the value of TC before the watchdog counter is below the values of WOWARNINT and WDWINDOW will cause a watchdog reset and set the WDTOF flag Table 303 Watchdog Timer Constant register TC 0x4000 4004 bit description Bit Symbol Description Reset Value 23 0 COUNT Watchdog time out value 0x00 OOFF 31 24 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined Watchdog Feed register Writing OxAA followed by 0x55 to this register will reload the Watchdog timer with the WDTC value This operation will also start the Watchdog if it is enabled via the WOMOD register Setting the WDEN bit in the WDMOD register is not sufficient to enable the Watchdog A valid feed sequence must be completed after setting WDEN before the Watchdog is capable of generating a reset Until then the Watchdog will ignore feed errors After writing OxAA to WDFEED access to any Watchdog register other than writing 0x55 to WDFEED
271. ation RESET functionality is not available in Deep power down mode Use the WAKEUP pin to reset the chip and wake up from Deep power down mode An external pull up resistor is required on this pin for the Deep power down mode 3 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis see Figure 8 4 1 C bus pins compliant with the 1 C bus specification for I2C standard mode 2C Fast mode and 12C Fast mode Plus 5 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis see Figure 8 includes high current output driver 6 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors configurable hysteresis and analog input When configured as a ADC input digital section of the pad is disabled and the pin is not 5 V tolerant see Figure 8 includes programmable digital input glitch filter 7 WAKEUP pin 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors configurable hysteresis and analog input When configured as a ADC input digital section of the pad is disabled and the pin is not 5 V tolerant see Figure 8 includes digital input glitch filter 8 When the system oscillator is not used connect XTALIN and XTALOUT as follows XTALIN can be left floating or can be grounded grounding is preferred to reduce susceptibility
272. ation provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 240 of 404 NXP Semiconductors U M1 0524 UM10524 13 6 3 Chapter 13 LPC1315 16 17 45 46 47 SSP SPI Table 235 SSP SPI Control Register 1 CR1 address 0x4004 0004 SSPO and 0x4005 8004 SSP1 bit description Bit Symbol Value Description Reset Value 0 LBM Loop Back Mode 0 0 During normal operation Serial input is taken from the serial output MOSI or MISO rather than the serial input pin MISO or MOSI respectively 1 SSE SPI Enable 0 0 The SPI controller is disabled The SPI controller will interact with other devices on the serial bus Software should write the appropriate control information to the other SSP SPI registers and interrupt controller registers before setting this bit 2 MS Master Slave Mode This bit can only be written when the 0 SSE bit is 0 0 The SPI controller acts as a master on the bus driving the SCLK MOSI and SSEL lines and receiving the MISO line 1 The SPI controller acts as a slave on the bus driving MISO line and receiving SCLK MOSI and SSEL lines 3 SOD Slave Output Disable This bit is relevant only in slave 0 mode MS 1 If it is 1 this blocks this SPI controller from driving the transmit data line MISO 31 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved
273. ation provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 116 of 404 NXP Semiconductors U M1 0524 Chapter 8 LPC1315 16 17 45 46 47 Pin configuration Table 109 Pin description LPC1345 46 47 with USB Symbol Description o Se zee 3 ses j l l lt 2 VREFP 64 3 ADC positive reference voltage This should be nominally the same voltage as Vppa but should be isolated to minimize noise and error Level on this pin is used as a reference for ADC This pin should be tied to 3 3 V if the ADC is not used Vssa 55 analog ground 0 V reference This should nominally be the same voltage as Vss but should be isolated to minimize noise and error Vpp 10 8 6 Supply voltage to the internal regulator and the external 33 44 29 rail On LQFP48 and HVQFN33 packages this pin is also 58 connected to the 3 3 V ADC supply and reference voltage Vss 7 5 33 Ground 54 41 1 Pin state at reset for default function Input O Output PU internal pull up enabled IA inactive no pull up down enabled F floating floating pins if not used should be tied to ground or power to minimize power consumption 2 See Figure 9 for the reset pad configuration RESET functionality is not available in Deep power down mode Use the WAKEUP pin to reset the chip and wake up from Deep power down mode An external pull up
274. ave transmitter mode and slave receiver mode The 2C interface complies with the entire 12C specification supporting the ability to turn power off to the ARM Cortex M3 without interfering with other devices on the same I2C bus pull up resistor pull up resistor SDA 12C bus SCL SDA SCL OTHER DEVICE WITH OTHER DEVICE WITH LPC11xx 12C INTERFACE C INTERFACE Fig 31 I C bus configuration 14 5 1 I2C Fast mode Plus Fast Mode Plus supports a 1 Mbit sec transfer rate to communicate with the 1 C bus products which NXP Semiconductors is now providing UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 253 of 404 NXP Semiconductors U M1 0524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller 14 6 Pin description Table 243 I2C bus pin description Pin Type Description SDA Input Output 12C Serial Data SCL Input Output 12C Serial Clock The C bus pins must be configured through the IOCON_PIOO_4 Table 60 and IOCON_PIO0_5 Table 61 registers for Standard Fast mode or Fast mode Plus In Fast mode Plus rates above 400 kHz and up to 1 MHz may be selected The 1 C bus pins are open drain outputs and fully compatible with the I C bus specification 14 7 Register description Table 244 Register overview I C base address 0x4000 0000 Name CONSET
275. bReserved Reserved for future use must be zero 11 5 19 _USB_DFU_FUNC_DESCRIPTOR UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 163 of 404 NXP Semiconductors UM10524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 184 _USB_DFU_FUNC_DESCRIPTOR class structure Member bLength bDescriptorType bmAttributes wDetachTimeOut wTransferSize bcdDFUVersion Description uint8_tuint8_t _USB_DFU_FUNC_DESCRIPTOR bLength uint8_tuint8_t _USB_DFU_FUNC_DESCRIPTOR bDescriptorType uint8_tuint8_t _USB_DFU_FUNC_DESCRIPTOR bmAttributes uintl6_tuint1l6_t _USB_DFU_FUNC_DESCRIPTOR wDetachTimeOut uintl _tuintl6_t _USB_DFU_FUNC_DESCRIPTOR wIransferSize uintl _tuintl6_t _USB_DFU_FUNC_DESCRIPTOR bcdDFUVersion 11 5 20 _USB_INTERFACE_DESCRIPTOR Table 185 _USB_INTERFACE_DESCRIPTOR class structure Member bLength bDescriptorType bInterface Number bAlternateSetting bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol Description uint8_tuint8_t _USB_INTERFACE_DESCRIPTOR bLength Size of this descriptor in bytes uint8_tuint8_t _USB_INTERFACE_DESCRIPTOR bDescriptorType INTERFACE Descriptor Type uint8_tuint8_t _USB_INTERFACE_DESCRIPTOR bInterfaceNumber Number of this interface Zero based value identifying the index in the array of
276. bit COUNTER TIMER 1 C gt ocon DI CT32B1_CAP 1 0 2 SYSTEM CONTROL WINDOWED WATCHDOG K RI TIMER GPIO pins GPIO PIN INTERRUPT C GPIO pins GPIO GROUPO INTERRUPT lt GPIO pins GPIO GROUP1 INTERRUPT lt boa 002aag241 1 Available on LQFP48 and LQFP64 packages only 2 CT16B0_CAP1 CT16B1_CAP1 CT32B1_CAP1 inputs available on LQFP64 packages only CT32B0_CAP0 input available on LQFP48 and LQFP64 packages only Fig 1 Block diagram UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 7 of 404 UM10524 Chapter 2 LPC1315 16 17 45 46 47 Memory mapping Rev 1 17 February 2012 2 1 How to read this chapter User manual See Table 3 for the memory configuration of the LPC1315 16 1 7 45 46 47 parts Table 3 LPC1315 16 17 45 46 47 memory configuration Type number LPC1345FHN33 LPC1345FBD48 LPC1346FHN33 LPC1346FBD48 LPC1347FHN33 LPC1347FBD48 LPC1347FBD64 LPC1315FHN33 LPC1315FBD48 LPC1316FHN33 LPC1316FBD48 LPC1317FHN33 LPC1317FBD48 LPC1317FBD64 Flash kB 32 32 48 48 64 64 64 32 32 48 48 64 64 64 SRAM kB EEPROM kB SRAMO co oOo o USB SRAM 2 YINI MY NY LN LH SRAM1 Oo NN mo wy PP BR A A A SNM NY FH HHP HP HPN YD 2 2 Memory map UM10524 2 2 1 The LPC131
277. bit is not defined SSP SPI Data Register Software can write data to be transmitted to this register and read data that has been received Table 236 SSP SPI Data Register DR address 0x4004 0008 SSPO and 0x4005 8008 SSP1 bit description Bit Symbol Description Reset Value 15 0 DATA Write software can write data to be sent in a future frame to this 0x0000 register whenever the TNF bit in the Status register is 1 indicating that the Tx FIFO is not full If the Tx FIFO was previously empty and the SPI controller is not busy on the bus transmission of the data will begin immediately Otherwise the data written to this register will be sent as soon as all previous data has been sent and received If the data length is less than 16 bit software must right justify the data written to this register Read software can read data from this register whenever the RNE bit in the Status register is 1 indicating that the Rx FIFO is not empty When software reads this register the SPI controller returns data from the least recent frame in the Rx FIFO If the data length is less than 16 bit the data is right justified in this field with higher order bits filled with Os 31 16 Reserved All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 241 of 404 NXP Semiconductors U M1 0524 Chapter 13 LPC1315 16 17 45 46 47 S
278. ble 177 HID _REPORT_T class structure 161 Table 178 MSC CBW class structure 162 Table 179 MSC CSW class structure 162 Table 180 REQUEST TYPE class structure 162 Table 181 USB COMMON_DESCRIPTOR class StruCtUre soaa cerere ee eee 162 Table 182 USB CORE_DESCS _T class structure 163 Table 183 USB DEVICE _QUALIFIER_DESCRIPTOR class structure 00000 eee 163 Table 184 USB DFU FUNC DESCRIPTOR class StruCtUre 2 es 164 Table 185 USB INTERFACE_DESCRIPTOR class SUUCIUING dreti Gace ons oo dlere eee Adon e ROR 164 Table 186 USB OTHER_SPEED CONFIGURATION class structure 0 000000 cues 165 Table 187 USB SETUP_PACKET class structure 165 Table 188 USB STRING DESCRIPTOR class structure description 0 20 e eee eee 143 166 Table 155 USB Data buffer start address DATABUFSTART Table 189 WB_T class structure 166 address 0x4008 000C bit description 143 Table 190 USBD_API class structure 166 Table 156 Link Power Management register LPM address Table 191 USBD_API_INIT_PARAM class structure 167 0x4008 0010 bit description 143 Table 192 USBD_CDC_API class structure 169 Table 157 USB Endpoint skip EPSKIP address 0x4008 Table 193 USBD_CDC_INIT_PARAM class structure 171 0014 bit description 144 Table 194 USBD_CORE_API class structure
279. ble in their device descriptors before going to low power state The application layer should implement this callback if they have any special on board circuit to triger remote wake up event Also application can use this callback to differentiate the following SUSPEND event is caused by cable plug out or host SUSPEND request The device can wake up host only after receiving this callback and remote wake up feature is enabled by host To signal remote wake up the device has to generate resume signaling on bus by calling usapi hw gt WakeUp routine Parameters 1 hUsb Handle to the USB device stack 2 param1 When 0 Clear the wake up configuration 1 Enable the wake up configuration Returns The call back should return ErrorCode_t type to indicate success or error condition USB_PARAM_CB_TUSB_PARAM_CB_T USBD_API_INIT_PARAM USB_Power_Event Reserved parameter should be set to zero USB_PARAM_CB_TUSB_PARAM_CB_T USBD_API_INIT_PARAM USB_Error_Event Event for error condition This event fires when USB device controller detect an error condition in the system Parameters 1 hUsb Handle to the USB device stack 2 param1 USB device interrupt status register Returns The call back should return ErrorCode_t type to indicate success or error condition All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 168 of 404 N
280. can monitor the signal by reading a dedicated status register If the BOD interrupt is enabled in the STARTERP1 register see Table 39 and in the NVIC the BOD interrupt can wake up the chip from Deep sleep and power down mode If the BOD reset is enabled the forced BOD reset can wake up the chip from Deep sleep or Power down mode UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 35 of 404 NXP Semiconductors U M1 0524 Chapter 3 LPC1315 16 17 45 46 47 System control block 3 9 Power management UM10524 3 9 1 The LPC1315 16 1 7 45 46 47 support a variety of power control features In Active mode when the chip is running power and clocks to selected peripherals can be optimized for power consumption In addition there are four special modes of processor power reduction with different peripherals running Sleep mode Deep sleep mode Power down mode and Deep power down mode Table 44 Peripheral configuration in reduced power modes Peripheral Sleep mode Deep sleep Power down Deep power down mode mode mode IRC software configurable on offl off IRC output software configurable offl offl off Flash software configurable on off off BOD software configurable software software off configurable configurable PLL software configurable off off off SysOsc software configurable off off off WDosc WWDT software co
281. ccessible by all bus masters Parameters 1 param Structure containing CDC function driver module initialization parameters Returns Returns the required memory size in bytes UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 169 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 192 USBD_CDC_API class structure Member Description init ErrorCode_t ErrorCode_t USBD_CDC_API init USBD_HANDLE_T hUsb USBD_CDC_INIT_PARAM_T param USBD_HANDLE_T phCDC Function to initialize CDC function driver module This function is called by application layer to initialize CDC function driver module hUsbHandle to the USB device stack paramStructure containing CDC function driver module initialization parameters Parameters 1 hUsb Handle to the USB device stack 2 param Structure containing CDC function driver module initialization parameters Returns Returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4 byte aligned or smaller than required 3 ERR_API_INVALID_PARAM2 Either CDC_Write or CDC_Read or CDC_Verify callbacks are not defined 4 ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed 5 ERR_USBD_BAD_EP_DESC Wrong endpoint descriptor is passe
282. ce HIGH through a 1 5 kOhm pull up resistor The SoftConnect feature can be used to allow software to finish its initialization sequence before deciding to establish connection to the USB Re initialization of the USB bus connection can also be performed without having to unplug the cable UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 137 of 404 NXP Semiconductors U M1 0524 UM10524 10 4 4 10 4 5 10 4 6 Chapter 10 LPC1345 46 47 USB2 0 device controller To use the SoftConnect feature the CONNECT signal should control an external switch that connects the 1 5 kOhm resistor between USB_DP and Vpp 3 3 V Software can then control the CONNECT signal by writing to the DCON bit in the DEVCMDSTAT register Interrupts The USB controller has two interrupt lines USB_Int_Req_IRQ and USB_Int_Req_FlQ Software can program the corresponding bit in the USB interrupt routing register to route the interrupt condition to one of these entries in the NVIC table Table 53 An interrupt is generated by the hardware if both the interrupt status bit and the corresponding interrupt enable bit are set The interrupt status bit is set by hardware if the interrupt condition occurs irrespective of the interrupt enable bit setting Suspend and resume The USB protocol insists on power management by the USB device This becomes even
283. ce susceptibility to noise XTALOUT should be left floating 15 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 117 of 404 UM10524 Chapter 9 LPC1315 16 17 45 46 47 GPIO Rev 1 17 February 2012 User manual 9 1 How to read this chapter All GPIO registers refer to 32 pins on each port Depending on the package type not all pins are available and the corresponding bits in the GPIO registers are reserved see Table 110 Table 110 GPIO pins available Package GPIO Port 0 GPIO Port 1 LQFP64 PIOO_0 to PIOO_23 PIO1_0 to PIO1_5 PIO1_7 to PIO1_8 PIO1_10 to PIO1_29 LQFP48 PIO0_0 to PIOO_23 PIO1_13 to PIO1_16 PIO1_19 to PIO1_ 23 to PIO1_29 PIO1_31 HVQFN no USB PIO0_0 to PIOO_23 PIO1_15 PIO1_19 PIO1_23 to PIO1_24 HVQFN USB PIO0_0 to PIOO_23 PIO1_15 PIO1_19 9 2 Basic configuration Various register blocks must be enabled to use the GPIO port and pin interrupt features e For the pin interrupts select up to 8 external interrupt pins from all GPIO port pins in the SYSCON block Table 35 and enable the clock to the pin interrupt register block in the SYSAHBCLKCTRL register Table 19 bit 19 The pin interrupt wake up feature is enabled in the STARTERPO register Table 38 e For the group interrupt feature enable the clock to the GROUPO and GROUP1 register interfaces in the SYSAHBCLKCTRL re
284. cess the RBR The RBR is always Read Only Since PE FE and BI bits see Table 215 correspond to the byte on the top of the RBR FIFO i e the one that will be read in the next read from the RBR the right approach for fetching the valid pair of received byte and its status bits is first to read the content of the LSR register and then to read a byte from the RBR Table 204 USART Receiver Buffer Register when DLAB 0 Read Only RBR address 0x4000 8000 bit description Bit Symbol Description Reset Value 7 0 RBR The USART Receiver Buffer Register contains the oldest undefined received byte in the USART RX FIFO 31 8 Reserved USART Transmitter Holding Register when DLAB 0 Write Only The THR is the top byte of the USART TX FIFO The top byte is the newest character in the TX FIFO and can be written via the bus interface The LSB represents the first bit to transmit The Divisor Latch Access Bit DLAB in the LCR must be Zero in order to access the THR The THR is always Write Only Table 205 USART Transmitter Holding Register when DLAB 0 Write Only THR address 0x4000 8000 bit description Bit Symbol Description Reset Value 7 0 THR Writing to the USART Transmit Holding Register causes the data NA to be stored in the USART transmit FIFO The byte will be sent when it is the oldest byte in the FIFO and the transmitter is available 31 8 Reserved All information provided in this document is subj
285. ch output 1 for 32 bit timer 0 PIO1_26 CT32B0_MAT2 14 11 BI PU VO PIO1_26 General purpose digital input output pin RXD CT32B0_MAT2 Match output 2 for 32 bit timer 0 l RXD Receiver input for USART PIO1_27 CT32B0_MAT3 15 12 BI PU VO P101_27 General purpose digital input output pin TXD O CT32B0_MAT3 Match output 3 for 32 bit timer 0 O TXD Transmitter output for USART PIO1_28 CT32B0_CAP0 31 24 BI PU VO P101_28 General purpose digital input output pin SCLK l CT32B0_CAP0 Capture input 0 for 32 bit timer 0 VO SCLK Serial clock input output for USART in synchronous mode PIO1_29 SCKO 41 31 BI PU VO P101_29 General purpose digital input output pin CT32B0_CAP1 VO SCK0 Serial clock for SSPO l CT32B0_CAP1 Capture input 1 for 32 bit timer 0 PIO1_31 25 BI PU VO PIO1_31 General purpose digital input output pin n c 25 19 E Not connected n c 26 20 Not connected XTALIN 8 6 4 B Input to the oscillator circuit and internal clock generator circuits Input voltage must not exceed 1 8 V XTALOUT 9 7 5 B Output from the oscillator amplifier UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 110 of 404 NXP Semiconductors U M1 0524 Chapter 8 LPC1315 16 17 45 46 47 Pin configuration Table 108 Pin description
286. ch physical endpoint Buffer in use This register has one bit per physical 0 R W endpoint 0 HW is accessing buffer 0 1 HW is accessing buffer 1 Reserved 0 R USB Endpoint Buffer Configuration EPBUFCFG Table 159 USB Endpoint Buffer Configuration EPBUFCFG address 0x4008 001C bit description Bit Symbol Description Reset Access value 1 0 Reserved Fixed to zero because the control endpoint 0 R zero is fixed to single buffering for each physical endpoint 9 2 BUF_SB Buffer usage This register has one bit per physical 0 R W endpoint 0 Single buffer 1 Double buffer If the bit is set to single buffer 0 it will not toggle the corresponding EPINUSE bit when it clears the active bit If the bit is set to double buffer 1 HW will toggle the EPINUSE bit when it clears the Active bit for the buffer 31 10 Reserved 0 R UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 144 of 404 NXP Semiconductors UM10524 Chapter 10 LPC1345 46 47 USB2 0 device controller 10 6 9 USB interrupt status register INTSTAT Table 160 USB interrupt status register INTSTAT address 0x4008 0020 bit description Bit Symbol 0 EPOOUT 1 EPOIN 2 EP10OUT 3 EP1IN 4 EP2OUT 5 EP2IN 6 EP30UT UM10524 Description Interrupt status register bit for the Control EPO OUT direction This
287. ch pin interrupt Bit n configures the pin interrupt selected in PINTSELn 0 Disable falling edge interrupt or set active interrupt level LOW 1 Enable falling edge interrupt enabled or set active interrupt level HIGH 31 8 Reserved Pin interrupt active level falling edge interrupt set register For each of the 8 pin interrupts selected in the PINTSEL registers see Table 35 one bit in the SIENF register sets the corresponding bit in the IENF register depending on the pin interrupt mode configured in the ISEL register e lf the pin interrupt mode is edge sensitive PMODE 0 the falling edge interrupt is set All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 123 of 404 NXP Semiconductors U M1 0524 9 5 1 7 9 5 1 8 UM10524 Chapter 9 LPC1315 16 17 45 46 47 GPIO e If the pin interrupt mode is level sensitive PMODE 1 the HIGH active interrupt is selected Table 120 Pin interrupt active level falling edge interrupt set register SIENF address 0x4004 C014 bit description Bit Symbol Description Reset Access value 7 0 SETENAF Ones written to this address set bits in the IENF thus NA WO enabling interrupts Bit n sets bit n in the IENF register 0 No operation 1 Select HIGH active interrupt or enable falling edge interrupt 31 8 Reserved Pin interrupt active le
288. character LSB for Mode 0 the rate counter will continue incrementing with the pre scaled USART input clock UART_PCLKk 5 If Mode 0 the rate counter will stop on next falling edge of the USART Rx pin If Mode 1 the rate counter will stop on the next rising edge of the USART Rx pin All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 218 of 404 NXP Semiconductors U M1 0524 Chapter 12 LPC1315 16 17 45 46 47 USART 6 The rate counter is loaded into DLM DLL and the baud rate will be switched to normal operation After setting the DLM DLL the end of auto baud interrupt IIR ABEOInt will be set if enabled The RSR will now continue receiving the remaining bits of the character A 0x41 or a 0x61 start bitO biti bit2 bit3 bit4 bits bit6 bit7 parity stop UARTn RX start bit LSB of A or a UOACR start rate counter 16xbaud_rate 16 cycles 16 cycles a Mode 0 start bit and LSB are used for auto baud A 0x41 or a 0x61 start bitO biti bit2 bit3 bit4 bits bit6 bit7 parity stop UARTn RX start bit LSB of A or a U1ACR start rate counter 16 cycles b Mode 1 only start bit is used for auto baud Fig 18 Auto baud a mode 0 and b mode 1 waveform 12 5 13 USART IrDA Control Register The IrDA Control Register enables an
289. ched parity bit will be odd Even Parity Number of 1s in the transmitted character and the attached parity bit will be even Forced 1 stick parity Forced 0 stick parity Break Control 0 Disable break transmission Enable break transmission Output pin USART TXD is forced to logic 0 when LCR 6 is active high Divisor Latch Access Bit 0 Disable access to Divisor Latches Enable access to Divisor Latches Reserved 12 5 8 USART Modem Control Register The MCR enables the modem loopback mode and controls the modem output signals Table 213 USART Modem Control Register MCR address 0x4000 8010 bit description Bit Symbol Value Description Reset 0 DTRCTRL 1 RTSCTRL 3 2 4 LMS UM10524 All information provided in this document is subject to legal disclaimers value Source for modem output pin DTR This bit reads as 0 when 0 modem loopback mode is active Source for modem output pin RTS This bit reads as 0 when 0 modem loopback mode is active Reserved user software should not write ones to reserved bits 0 The value read from a reserved bit is not defined Loopback Mode Select The modem loopback mode providesa 0 mechanism to perform diagnostic loopback testing Serial data from the transmitter is connected internally to serial input of the receiver Input pin RXD has no effect on loopback and output pin TXD is held in marking state The DSR CTS DCD and RI pins are ignored Externally DTR an
290. ck bit and then select the watchdog oscillator as the WWDT clock source 4 If the watchdog oscillator is shut down ensure that the IRC is powered in the PDRUNCFG register and switch the clock source to IRC in the MAINCLKSEL register Table 17 This ensures that the system clock is shut down glitch free 5 Select the power configuration after wake up in the PDAWAKECFG Table 41 register 6 If any of the available wake up interrupts are used for wake up enable the interrupts in the interrupt wake up registers Table 38 Table 39 and in the NVIC 7 Write one to the SLEEPDEEP bit in the ARM Cortex M3 SCR register 8 Use the ARM WFI instruction Wake up from Power down mode The microcontroller can wake up from Power down mode in the same way as from Deep sleep mode e Signal on one of the eight pin interrupts selected in Table 35 Each pin interrupt must also be enabled in the STARTERP0 register Table 38 and in the NVIC e BOD signal if the BOD is enabled in the PDSLEEPCFG register BOD interrupt using the interrupt wake up register 1 Table 39 The BOD interrupt must be enabled in the NVIC The BOD interrupt must be selected in the BODCTRL register Reset from the BOD circuit In this case the BOD reset must be enabled in the BODCTRL register Table 31 e WWDT signal if the watchdog oscillator is enabled in the PDSLEEPCFG register All information provided in this document is subject to legal disclaimers NXP
291. ck is 24 MHz System clock greater than or equal to the expected value command 0 12000 command 1 25000 command 2 CPU_FREQ_GTE command 3 0 rom gt pWRD gt set_pll command result The above code specifies a 12 MHz PLL input clock a system clock of at least 25 MHz and no locking time out set_p returns PLL_CMD_SUCCESS in result 0 and 36000 in result 1 The new system clock is 36 MHz System clock approximately equal to the expected value command 0 12000 command 1 16500 command 2 CPU_FREQ_ APPROX command 3 0 rom gt pWRD gt set_pll command result The above code specifies a 12 MHz PLL input clock a system clock of approximately 16 5 MHz and no locking time out set_p returns PLL_CMD_SUCCESS in result 0 and 16000 in result 7 The new system clock is 16 MHz All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 52 of 404 NXP Semiconductors U M1 0524 Chapter 5 LPC1315 16 17 45 46 47 Power profiles 5 6 Power routine 5 6 1 set_power This routine configures the device s internal power control settings according to the calling arguments The goal is to reduce active power consumption while maintaining the feature of interest to the application close to its optimum set_power returns a result code that reports if the power setting was successfully changed o
292. class A B or C power requirements be aware of the logic level tolerances and requirements when communicating or powering cards that use different power rails than the LPC1315 16 1 7 45 46 47 12 6 2 1 Smart card set up procedure A T 0 protocol transfer consists of 8 bits of data an even parity bit and two guard bits that allow for the receiver of the particular transfer to flag parity errors through the NACK response see Figure 21 Extra guard bits may be added according to card requirements If no NACK is sent provided the interface accepts them in SCICTRL the next byte may be transmitted immediately after the last guard bit If the NACK is sent the transmitter will retry sending the byte until successfully received or until the SCICTRL retry limit has been met UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 233 of 404 NXP Semiconductors U M1 0524 Chapter 12 LPC1315 16 17 45 46 47 USART Clock Next transfer or Asynchronous transfer First retry o on oe oe ow ois oe or oan 1 It l I I extra extra y 4 extra pouardl jouarde guardi tguard2 sguardn TXD start l Fig 21 Smart card T 0 waveform The smart card must be set up with the following considerations e f necessary program PRESETCTRL Table 7 so that the USART is not continuously reset
293. clear rising and falling edge detection for this pin Write 1 level sensitive switch the active level for this pin in the PINTENT_F register 31 8 Reserved GPIO GROUPO GROUP 1 interrupt register description Grouped interrupt control register Table 125 GPIO grouped interrupt control register CTRL addresses 0x4005 C000 GROUPO INT and 0x4006 0000 GROUP1 INT bit description Bit Symbol Value Description Reset value 0 INT Group interrupt status This bit is cleared by writinga 0 one to it Writing zero has no effect 0 No interrupt request is pending 1 Interrupt request is active 1 COMB Combine enabled inputs for group interrupt 0 0 OR functionality A grouped interrupt is generated when any one of the enabled inputs is active based on its programmed polarity 1 AND functionality An interrupt is generated when all enabled bits are active based on their programmed polarity 2 TRIG Group interrupt trigger 0 0 Edge triggered 1 Level triggered 31 3 Reserved 0 GPIO grouped interrupt port polarity registers The grouped interrupt port polarity registers determine how the polarity of each enabled pin contributes to the grouped interrupt Each port is associated with its own port polarity register and the values of both registers together determine the grouped interrupt All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User m
294. clockout Table 51 set_pll routine Routine set_pll Input Param0 system PLL input frequency in kHz Param1 expected system clock in kHz Param2 mode CPU_FREQ_EQU CPU_FREQ_LTE CPU_FREQ_GTE CPU_FREQ_APPROX Param3 system PLL lock timeout Result Result0 PLL_CMD_SUCCESS PLL_INVALID_FREQ PLL_INVALID_MODE PLL_FREQ_NOT_FOUND PLL_NOT_LOCKED Result1 system clock in kHz The following definitions are needed when making set_pll power routine calls set_pll mode options define CPU_FREQ_EQU 0 define CPU_FREQ_LTE 1 define CPU_FREQ_GTE 2 define CPU_FREQ_APPROX 3 set_pll result0 options define PLL_CMD_SUCCESS define PLL_INVALID_FREQ define PLL_INVALID_MODE define PLL_FREQ_NOT_FOUND define PLL_NOT_LOCKED Bm w Ne o System PLL input frequency and expected system clock set_pll looks for a setup in which the system PLL clock does not exceed 50 MHz It easily finds a solution when the ratio between the expected system clock and the system PLL input frequency is an integer value but it can also find solutions in other cases The system PLL input frequency Param0 must be between 10000 to 25000 kHz 10 MHz to 25 MHz inclusive The expected system clock Param must be between 1 and 50000 kHz inclusive If either of these requirements is not met set_pll returns PLL_INVALID_FREQ and returns Param0 as Result1 since the PLL setting is unchanged Mode The first priority of set_pll is to fi
295. conductors UM10524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller reception of the own Slave address and one or more Data bytes all are acknowledged last data byte received is Not acknowledged arbitration lost as l Master and addressed gt as Slave 88H gt l reception of the bytes last data byte is Not acknowledged Master and addressed l A as Slave by General l Call from Master to Slave from Slave to Master _ DATA I A any number of data bytes and their associated Acknowledge bits l this number contained in I2STA corresponds to a defined state of the C bus Fig 42 Format and states in the Slave Receiver mode General Call address GENERAL CALL DATA A PORS and one or more Data l arbitration lost as D UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 280 of 404 NXP Semiconductors U M1 0524 UM10524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller 14 10 4 Slave Transmitter mode In the slave transmitter mode a number of data bytes are transmitted to a master receiver see Figure 43 Data transfer is initialized as in the slave receiver mode When ADR and CON have been initialized the 12C block waits until it is addressed by its own slave address followed by the data direction bit which must be 1 R
296. consumption and CPU performance e Low current mode corresponding to lowest power consumption In addition the power profile includes routines to select the optimal PLL settings for a given system clock and PLL input clock The API calls to the ROM are performed by executing functions which are pointed by a pointer within the ROM Driver Table Figure 6 shows the pointer structure used to call the Power Profiles API UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 48 of 404 NXP Semiconductors U M1 0524 5 4 Definitions Chapter 5 LPC1315 16 17 45 46 47 Power profiles Power API Function ROM Driver Table Table Ptr to Driver Table 1 Ptr to Driver Table 2 set_pll Points to ROM Driver Table set_power Ptr to Driver Table 3 Ptr to Power Profiles API Ptr to Driver Table 5 fF a H i Ptr to Driver Table n Fig 6 Power profiles pointer structure The following elements have to be defined in an application that uses the power profiles typedef struct _PWRD void set_pll unsigned int cmd unsigned int resp void set_power unsigned int cmd unsigned int resp PWRD typedef struct _ROM const PWRD pWRD ROM ROM rom ROM Qx1FFFIFF8 unsigned int command 4 result 2 5 5 Clocking routine UM10524 5 5 1 set_
297. controller e Supports 10 physical 5 logical endpoints including one control endpoint e Single and double buffering supported e Each non control endpoint supports bulk interrupt or isochronous endpoint types e Supports wake up from Deep sleep mode on USB activity and remote wake up e Supports SoftConnect 10 4 General description UM10524 The Universal Serial Bus USB is a four wire bus that supports communication between a host and one or more up to 127 peripherals The host controller allocates the USB bandwidth to attached devices through a token based protocol The bus supports hot plugging and dynamic configuration of the devices All transactions are initiated by the host controller The host schedules transactions in 1 ms frames Each frame contains a Start Of Frame SOF marker and transactions that transfer data to or from device endpoints Each device can have a maximum of 16 logical or 32 physical endpoints The LPC1315 16 1 7 45 46 47 device controller supports up to 10 physical endpoints There are four types of transfers defined for the endpoints Control transfers are used to configure the device Interrupt transfers are used for periodic data transfer Bulk transfers are used when the latency of transfer is not critical Isochronous transfers have guaranteed delivery time but no error correction For more information on the Universal Serial Bus see the USB Implementers Forum website All information provid
298. ction Values 0x2 to 0x7 are reserved 0 0x0 PIOO_23 0x1 AD7 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 7 ADMODE Selects Analog Digital mode 1 0 Analog input mode 1 Digital functional mode 8 FILTR Selects 10 ns input glitch filter 0 0 Filter disabled 1 Filter enabled All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 84 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 79 I O configuration for pin PlOO_23 AD7 PIO0_23 address 0x4004 405C bit description Bit Symbol Value Description Reset value 9 Reserved 0 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 25 I O configuration for pin PIO1_0 Table 80 I O configuration for pin PlIO1_0 CT32B1_MATO PIO1_0 address 0x4004 4060 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Va
299. cument is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 390 of 404 NXP Semiconductors UM10524 Table 98 I O configuration for pin PlO1_21 DCD MISO1 PIO1_21 address 0x4004 40B4 bit CGeSCIIPUOMN saze sauces eke seeded 98 Table 99 I O configuration for pin PlO1_22 RI MOSI1 PIO1_22 address 0x4004 40B8 bit description s lt ss eatis ganiri cee eee eee 99 Table 100 I O configuration for pin PIO1_23 CT16B1_MAT1 SSEL1 PIO1_23 address 0x4004 40BC bit description 99 Table 101 I O configuration for pin PlO1_24 CT32BO_MATO PIO1_24 address 0x4004 40C0 bit description 0 ee eee eee 100 Table 102 I O configuration for pin PIO1_25 CT32BO_MAT1 PIO1_25 address 0x4004 40C4 bit description 2 200 e eee eee eee 101 Table 103 I O configuration for pin P1O1_26 CT32B0_MAT2 RXD PIO1_26 address 0x4004 40C8 bit description 102 Table 104 I O configuration for pin P1O1_27 CT32B0_MAT3 TXD PIO1_27 address 0x4004 40CC bit description 102 Table 105 I O configuration for pin PIO1_28 CT32B0_CAP0 SCLK PIO1_ 28 address 0x4004 40D0 bit description 103 Table 106 I O configuration for pin PlO1_29 SCKO CT32B0_CAP1 PIO1_29 address 0x4004 40D4 bit description 0 00085 104 Table 107 I O configuration for pin PlO1_31 PIO1_ 31 address 0x4004 40DC bit description 105 Table 108 Pin description LPC13
300. d RX Trigger Level These two bits determine how many USART 0 FIFO characters must be received by the FIFO before an interrupt is activated Trigger level 0 1 character or 0x01 Trigger level 1 4 characters or 0x04 Trigger level 2 8 characters or 0x08 Trigger level 3 14 characters or 0x0E Reserved USART Line Control Register The LCR determines the format of the data character that is to be transmitted or received Table 212 USART Line Control Register LCR address 0x4000 800C bit description Bit Symbol Value 1 0 WLS 0x0 0x1 0x2 0x3 2 SBS 0 Description Reset Value Word Length Select 0 5 bit character length 6 bit character length 7 bit character length 8 bit character length Stop Bit Select 0 1 stop bit 2 stop bits 1 5 if LCR 1 0 00 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 210 of 404 NXP Semiconductors UM10524 Chapter 12 LPC1315 16 17 45 46 47 USART Table 212 USART Line Control Register LCR address 0x4000 800C bit description Bit Symbol Value Description 3 PE 0 1 5 4 PS 0x0 0x1 0x2 0x3 6 BC 0 1 7 DLAB 0 1 31 8 Reset Value Parity Enable 0 Disable parity generation and checking Enable parity generation and checking Parity Select 0 Odd parity Number of 1s in the transmitted character and the atta
301. d Active 0 Stall 1 Yes Write EPOOUT Active 1 No No Stall 1 CtrlRead CtrlWriteNoDataStage NBytes Write DevStatus IntOnNak _CO 0 IntOnNak _Cl 1 Yes Write EPOIN Active 1 Stall 1 NBytes Write DevStatus IntOnNak _CO 1 IntOnNak _Cl 0 Write EPOOUT Write EPOIN 0 Bytes UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 151 of 404 NXP Semiconductors U M1 0524 Chapter 10 LPC1345 46 47 USB2 0 device controller Fig 14 Flowchart of control endpoint 0 IN direction Wait on EP Oln interrupt EPOIn Interrupt 1 If not all OUT data transferred the Yes host aborts Control Write Otherwise it is a normal completion by the host Write EPOIN Active 1 Stall 1 0 Bytes Write EPOOUT Clear EP OIn interrupt Active 0 Stall 1 Clear EP OOUT interrupt Write EPOIN Active 0 OUT data phase Stall 1 on going IN data phase on going Write EPOIN Active 1 Stall 1 EP 0Out Interrupt NBytes All IN data transmitted Write EPOOUT Active 1 Stall 1 Host aborts Control Read 0 Bytes Write EPOIN ctive 0 A Stall 1 Clear EP 0
302. d SendNotification ErrorCode_t ErrorCode_t USBD_CDC_API SendNotification USBD_HANDLE_T hCdc uint8_t bNotification uintl6_t data Function to initialize CDC function driver module This function is called by application layer to initialize CDC function driver module hUsbHandle to the USB device stack paramStructure containing CDC function driver module initialization parameters Parameters 1 hUsb Handle to the USB device stack 2 param Structure containing CDC function driver module initialization parameters Returns Returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4 byte aligned or smaller than required 3 ERR_API_INVALID_PARAM2 Either CDC_Write or CDC_Read or CDC_Verify callbacks are not defined 4 ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed 5 ERR_USBD_BAD_EP_DESC Wrong endpoint descriptor is passed 11 5 23 USBD_CDC_INIT_PARAM Communication Device Class function driver initialization parameter data structure UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 170 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 193 USBD_CDC_INIT_PARAM class structure Member mem_base mem_size cif_i
303. d Input Return Code Description Example G Address Flash or RAM address from which the code execution is to be started This address should be on a word boundary Mode T Execute program in Thumb Mode A Execute program in ARM mode CMD_SUCCESS ADDR_ERROR ADDR_NOT_MAPPED CMD_LOCKED PARAM_ERROR CODE_READ_PROTECTION_ENABLED This command is used to execute a program residing in RAM or flash memory It may not be possible to return to the ISP command handler once this command is successfully executed This command is blocked when code read protection is enabled G 0 A lt CR gt lt LF gt branches to address 0x0000 0000 in ARM mode All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 367 of 404 NXP Semiconductors U M1 0524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming 21 13 9 Erase sector s lt start sector number gt lt end sector number gt Table 345 ISP Erase sector command Command E Input Start Sector Number End Sector Number Should be greater than or equal to start sector number Return Code CMD_SUCCESS BUSY INVALID_SECTOR SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION CMD_LOCKED PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to erase one or more sector s of on chip flash memory The boot block can not be erased using th
304. d MR1 this bit can either toggle go LOW go HIGH or do nothing Bits EMR 7 6 control the functionality of this output This bit is driven to the CT16B0O_MAT0 CT16B1_MATO pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH External Match 2 This bit reflects the state of match channel 2 When a match occurs 0 between the TC and MRz2 this bit can either toggle go LOW go HIGH or do nothing Bits EMR 9 8 control the functionality of this output External Match 3 This bit reflects the state of output of match channel 3 When a match 0O occurs between the TC and MR3 this bit can either toggle go LOW go HIGH or do nothing Bits EMR 11 10 control the functionality of this output All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 303 of 404 NXP Semiconductors U M1 0524 Chapter 15 LPC1315 16 17 45 46 47 16 bit counter timers CT16B0 1 Table 280 External Match Register EMR address 0x4000 C03C CT16B0 and 0x4001 003C CT16B1 bit description Bit Symbol Value Description Reset value 5 4 EMCO External Match Control 0 Determines the functionality of External Match 0 Table 281 00 shows the encoding of these bits 0x0 Do Nothing 0x1 Clear the corresponding External Match bit output to 0 CT16Bi_MATO pin is LOW if pinned out 0x2 Setthe corresponding External Match bit output to 1 CT1
305. d RTS are set inactive Internally the upper four bits of the MSR are driven by the lower four bits of the MCR This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR Disable modem loopback mode Enable modem loopback mode Reserved user software should not write ones to reserved bits 0 The value read from a reserved bit is not defined NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 211 of 404 NXP Semiconductors U M1 0524 Chapter 12 LPC1315 16 17 45 46 47 USART Table 213 USART Modem Control Register MCR address 0x4000 8010 bit description Bit Symbol Value Description Reset value 6 RTSEN RTS enable 0 0 Disable auto rts flow control 1 Enable auto rts flow control 7 CTSEN CTS enable 0 0 Disable auto cts flow control 1 Enable auto cts flow control 31 8 Reserved s 12 5 8 1 Auto flow control If auto RTS mode is enabled the USART s receiver FIFO hardware controls the RTS output of the USART If the auto CTS mode is enabled the USART s transmitter will only start sending if the CTS pin is low 12 5 8 1 1 Auto RTS The auto RTS function is enabled by setting the RTSen bit Auto RTS data flow control originates in the RBR module and is linked to the programmed receiver FIFO trigger level If auto RTS is enabled the data flow is controlled as follows When the receiver FIFO level reaches the programmed tr
306. d TC registers are updated by APB operations the new value will take effect in 3 WDCLK cycles on the logic in the WDCLK clock domain When the watchdog timer is counting on WDCLK the synchronization logic will first lock the value of the counter on WDCLK and then synchronize it with the PCLK for reading as the WDTV register by the CPU UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 327 of 404 NXP Semiconductors U M1 0524 Chapter 17 LPC1315 16 17 45 46 47 Windowed Watchdog Timer 17 7 Using the WWDT lock features UM10524 17 7 1 17 7 2 17 7 3 The WWDT supports several lock features which can be enabled to ensure that the WWDT is running at all times e Accidental overwrite of the WWDT clock source e Changing the WWDT clock source e Changing the WWDT reload value Accidental overwrite of the WWDT clock If bit 31 of the WWDT CLKSEL register Table 306 is set writes to bit 0 of the CLKSEL register the clock source select bit will be ignored and the clock source will not change The clock source overwrite lock mechanism can simply be disabled by clearing bit 31 in the CLKSEL register Changing the WWDT clock source If bit 5 in the WWDT MOD register is set the current clock source as selected in the CLKSEL register is locked and can not be changed either by software or by hardware when Sleep De
307. d be greater than or equal to 10 MHz In USART ISP mode the LPC1315 16 17 45 46 47 is clocked by the IRC and the crystal frequency is ignored Once the crystal frequency is received the part is initialized and the ISP command handler is invoked For safety reasons an Unlock command is required before executing the commands resulting in flash erase write operations and the Go command The rest of All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 355 of 404 NXP Semiconductors U M1 0524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming the commands can be executed without the unlock command The Unlock command is required to be executed once per ISP session The Unlock command is explained in Section 21 13 ISP commands on page 363 21 8 ISP IAP communication protocol UM10524 21 8 1 21 8 2 21 8 3 21 8 4 21 8 5 21 8 6 All ISP commands should be sent as single ASCII strings Strings should be terminated with Carriage Return CR and or Line Feed LF control characters Extra lt CR gt and lt LF gt characters are ignored All ISP responses are sent as lt CR gt lt LF gt terminated ASCII strings Data is sent and received in UU encoded format ISP command format Command Parameter_0 Parameter_1 Parameter_n lt CR gt lt LF gt Data Data only for Write commands ISP res
308. d by the code read protection Important any CRP change becomes effective only after the device has gone through a power cycle UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 360 of 404 NXP Semiconductors U M1 0524 UM10524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming Table 333 Code Read Protection CRP options Name Pattern Description programmed in 0x0000 02FC NO_ISP 0x4E69 7370 Prevents sampling of pin PIOO_1 for entering ISP mode PIOO_1 is available for other uses CRP1 0x12345678 Access to chip via the SWD pins is disabled This mode allows partial flash update using the following ISP commands and restrictions e Write to RAM command cannot access RAM below 0x1000 0300 e Copy RAM to flash command can not write to Sector 0 e Erase command can erase Sector 0 only when all sectors are selected for erase e Compare command is disabled e Read Memory command is disabled This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased Since compare command is disabled in case of partial updates the secondary loader should implement checksum mechanism to verify the integrity of the flash CRP2 0x87654321 Access to chip via the SWD pins is disabled The following ISP commands are disabled e Read Memory e Write to RAM e Go e C
309. d configures the IrDA mode The value of the ICR should not be changed while transmitting or receiving data or data loss or corruption may occur UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 219 of 404 NXP Semiconductors U M1 0524 UM10524 Chapter 12 LPC1315 16 17 45 46 47 USART Table 219 USART IrDA Control Register ICR 0x4000 8024 bit description Bit Symbol Value Description Reset value 0 IRDAEN IrDA mode enable 0 0 IrDA mode is disabled 1 IrDA mode is enabled 1 IRDAINV Serial input inverter 0 0 The serial input is not inverted 1 The serial input is inverted This has no effect on the serial output 2 FIXPULSEEN IrDA fixed pulse width mode 0 0 IrDA fixed pulse width mode disabled 1 IrDA fixed pulse width mode enabled 5 3 PULSEDIV Configures the pulse width when FixPulseEn 1 0 0x0 3 16 x baud rate 0x1 2 x TpeLk 0x2 4x TpceLk 0x3 8x Tpcik 0x4 16x TpceLk 0x5 32x Tpcik 0x6 64x Tpcik 0x7 128 x TpceLk 31 6 Reserved user software should not write ones to 0 reserved bits The value read from a reserved bit is not defined The PulseDiv bits in the ICR are used to select the pulse width when the fixed pulse width mode is used in IrDA mode IrDAEn 1 and FixPulseEn 1 The value of these bits should be set so that the resulting pulse width is at least 1 63 us Table 2
310. d on channel 4 DR5 R W 0x024 A D Channel 5 Data Register This register contains the result NA Table 327 of the most recent conversion completed on channel 5 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 346 of 404 NXP Semiconductors UM10524 Chapter 20 LPC1315 16 17 45 46 47 ADC Table 323 Register overview ADC base address 0x4001 C000 Name Access Address Description DR6 R W DR7 R W STAT RO TRM R W offset 0x028 0x02C 0x030 0x034 Reset Reference Value A D Channel 6 Data Register This register contains the result NA Table 327 of the most recent conversion completed on channel 6 A D Channel 7 Data Register This register contains the result NA Table 327 of the most recent conversion completed on channel 7 A D Status Register This register contains DONE and 0 Table 328 OVERRUN flags for all of the A D channels as well as the A D interrupt flag A D trim register OxFOO Table 329 1 Reset Value reflects the data stored in used bits only It does not include reserved bits content 20 5 1 A D Control Register CR The A D Control Register provides bits to select A D channels to be converted A D timing A D modes and the A D start trigger Table 324 A D Control Register CR address 0x4001 C000 bit description Bit Symbol 7 0 SEL 15 8 CLKDIV 16 BURST 20 17
311. d take no more than 100 us for the system PLL to lock if a valid configuration is selected If Param3 is zero set_p will wait indefinitely for the PLL to lock If a non zero value is provided that is how many times the code will check for a successful PLL lock event before it returns PLL_NOT_LOCKED In this case the PLL settings are unchanged and Param is returned as Result Hint setting Param3 equal to the system PLL frequency Hz divided by 10000 will provide more than enough PLL lock polling cycles Code examples The following examples illustrate some of the features of set_p discussed above Invalid frequency device maximum clock rate exceeded command 0 12000 command 1 60000 command 2 CPU_FREQ_EQU command 3 0 rom gt pWRD gt set_pll command result The above code specifies a 12 MHz PLL input clock and a system clock of exactly 60 MHz The application was ready to infinitely wait for the PLL to lock But the expected system clock of 60 MHz exceeds the maximum of 50 MHz Therefore set_pll returns PLL_INVALID_FREQ in result 0 and 12000 in result 1 without changing the PLL settings Invalid frequency selection system clock divider restrictions command 0 12000 command 1 40 command 2 CPU_FREQ_LTE command 3 0 rom gt pWRD gt set_pll command result The above code specifies a 12 MHz PLL input clock a system clock of no more than 40 kHz and no time out while waiting f
312. ddress 0x4004 8234 bit description Bit Symbol Value Description Reset value 9 Reserved Always write this bit as 0 10 USBPAD_PD USB transceiver wake up configuration 1 0 USB transceiver powered 1 USB transceiver powered down 11 Reserved This bit must be set to one in Run 1 mode 12 Reserved 0 31 13 Reserved Power configuration register PDRUNCFG The PDRUNCFG register controls the power to the various analog blocks This register can be written to at any time while the chip is running and a write will take effect immediately with the exception of the power down signal to the IRC To avoid glitches when powering down the IRC the IRC clock is automatically switched off at a clean point Therefore for the IRC a delay is possible before the power down state takes effect Table 42 Power configuration register PDRUNCFG address 0x4004 8238 bit description Bit Symbol Value Description Reset value 0 IRCOUT_PD IRC oscillator output power down 0 1 Powered down 0 Powered 1 IRC_PD IRC oscillator power down 0 1 Powered down 0 Powered 2 FLASH_PD Flash power down 0 1 Powered down 0 Powered 3 BOD_PD BOD power down 0 1 Powered down 0 Powered 4 ADC_PD ADC power down 1 1 Powered down 0 Powered 5 SYSOSC_PD Crystal oscillator power down 1 1 Powered down 0 Powered 6 WDTOSC_PD Watchdog oscillator power down 1 1 Powered down 0 Powered All information provided in this document is subject to legal disclaim
313. des Table 366 IAP Status Codes Summary Status Mnemonic Code 0 A OUO N gt 10 11 CMD_SUCCESS INVALID_COMMAND SRC_ADDR_ERROR DST_ADDR_ERROR SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR INVALID_SECTOR SECTOR_NOT_BLANK SECTOR_NOT_PREPARED _ FOR_WRITE_OPERATION COMPARE_ERROR BUSY Description Command is executed successfully Invalid command Source address is not on a word boundary Destination address is not on a correct boundary Source address is not mapped in the memory map Count value is taken in to consideration where applicable Destination address is not mapped in the memory map Count value is taken in to consideration where applicable Byte count is not multiple of 4 or is not a permitted value Sector number is invalid Sector is not blank Command to prepare sector for write operation was not executed Source and destination data is not same flash programming hardware interface is busy 21 15 Debug notes 21 15 1 Comparing flash images Depending on the debugger used and the IDE debug settings the memory that is visible when the debugger connects might be the boot ROM the internal SRAM or the flash To help determine which memory is present in the current debug environment check the value contained at flash address 0x0000 0004 This address contains the entry point to the code in the ARM Cortex M3 vector table which is the bottom of the boot ROM the int
314. descriptors Remark Parameters 1 hUsb Handle to the USB device stack 2 data Pointer to the data which will be passed when callback function is called by the stack 3 event Type of endpoint event See USBD_EVENT_T for more details Returns The call back should returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_ xxx For other error conditions UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 172 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 193 USBD_CDC_INIT_PARAM class structure Member CDC_BulkOUT_Hdlr SendEncpsCmd GetEncpsResp SetCommFeature GetCommFeature ClrCommFeature Description ErrorCode_t ErrorCode_t USBD_CDC_INIT_PARAM CDC_BulkOUT_Hdlr USBD_HANDLE_T hUsb void data uint32_t event USBD_HANDLE_T hUsb void data uint32_t event Communication Device Class specific BULK OUT endpoint handler The application software should provide the BULK OUT endpoint handler Applications should transfer data depending on the communication protocol type set in descriptors Remark Parameters 1 hUsb Handle to the USB device stack 2 data Pointer to the data which will be passed
315. device configuration descriptor when device is operating in high speed mode For full speed only implementation this pointer should be same as full_speed_desc device_qualifier uint _t uint8_t _USB_CORE_DESCS_T device_qualifier Pointer to USB device qualifier descriptor For full speed only implementation this pointer should be set to null 0 11 5 18 _USB_DEVICE_QUALIFIER_DESCRIPTOR Table 183 _USB_DEVICE_QUALIFIER_DESCRIPTOR class structure Member Description bLength uint8_tuint8_t _USB_DEVICE_QUALIFIER_DESCRIPTOR bLength Size of descriptor bDescriptorType uint8_tuint8_t _USB_DEVICE_QUALIFIER_DESCRIPTOR bDescriptorType Device Qualifier Type bcdUSB intl6_tuintl6_t _USB_DEVICE_QUALIFIER_DESCRIPTOR bcdUSB ce SB specification version number e g 0200H for V2 00 bDeviceClass uint8_tuint8_t _USB_DEVICE_QUALIFIER_DESCRIPTOR bDeviceClass Class Code bDeviceSubClass uint8_tuint8_t _USB_DEVICE_QUALIFIER_DESCRIPTOR bDeviceSubClass SubClass Code bDeviceProtocol uint8_tuint8_t _USB_DEVICE_QUALIFIER_DESCRIPTOR bDeviceProtocol Protocol Code bMaxPacketSize0 uint8_tuint8_t _USB_DEVICE_QUALIFIER_DESCRIPTOR bMaxPacketSize0 Maximum packet size for other speed bNumConfigurations uint8_tuint8_t _USB_DEVICE_QUALIFIER_DESCRIPTOR bNumConfigurations Number of Other speed Configurations bReserved uint8_tuint8_t _USB_DEVICE_QUALIFIER_DESCRIPTOR
316. ditions UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 186 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 198 USBD_HID_INIT_PARAM class structure Member Description HID_EpOut_Hdlr ErrorCode_t ErrorCode_t USBD_HID_INIT_PARAM HID_EpOut_Hdlr USBD_HANDLE_T hUsb void data uint32_t event USBD_HANDLE_T hUsb void data uint32_t event Optional Interrupt OUT endpoint event handler The application software could provide Interrupt OUT endpoint event handler Application which receives reports from host on interrupt endpoint should provide an endpoint event handler through this data member This data member is ignored if the interface descriptor hUsbHandle to the USB device stack dataHandle to HID function driver eventType of endpoint event See USBD_EVENT_T for more details Parameters 1 hUsb Handle to the USB device stack 2 data Handle to HID function driver 3 event Type of endpoint event See USBD_EVENT_T for more details Returns The call back should return ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_ xxx For other error conditions HID_GetReportDesc ErrorCode_t ErrorCode_t USBD_HID_INIT_PARAM
317. driver ROM API consists of the following modules Communication Device Class CDC function driver Communication Device Class function driver initialization parameter data structure Table 193 USBD_CDC_INIT_PARAM class structure CDC class API functions structure This module exposes functions which interact directly with USB device controller hardware Table 192 USBD_CDC_API class structure USB core layer struct Table 189 WB _T class structure union Table 166 __WORD_BYTE class structure struct Table 167 _BM_T class structure struct Table 180 _REQUEST_TYPE class structure struct Table 187 _USB_SETUP_PACKET class structure struct Table 183 _USB_DEVICE_QUALIFIER_DESCRIPTOR class structure struct USB device descriptor struct Table 183 _USB_DEVICE_QUALIFIER_DESCRIPTOR class structure struct USB configuration descriptor struct Table 185 _USB_INTERFACE DESCRIPTOR class structure struct USB endpoint descriptor struct Table 188 _USB_STRING_DESCRIPTOR class structure struct Table 181 _USB_COMMON_DESCRIPTOR class structure struct Table 186 _USB_OTHER_ SPEED CONFIGURATION class structure USB descriptors data structure Table 182 _USB_CORE_DESCS_T class structure USB device stack initialization par
318. ductor Microwire buses e Synchronous Serial Communication e Supports master or slave operation e Ejight frame FIFOs for both transmit and receive e 4 bit to 16 bit frame 13 4 General description The SSP SPI is a Synchronous Serial Port SSP controller capable of operation on a SPI 4 wire SSI or Microwire bus It can interact with multiple masters and slaves on the bus Only a single master and a single slave can communicate on the bus during a given data transfer Data transfers are in principle full duplex with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master In practice it is often the case that only one of these data flows carries meaningful data UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 237 of 404 NXP Semiconductors U M1 0524 Chapter 13 LPC1315 16 17 45 46 47 SSP SPI 13 5 Pin description Table 231 SSP SPI pin descriptions Interface pin Type name function Pin description SPI SSI Microwire SCK0 1 IO SCK CLK SK Serial Clock SCK CLK SK is a clock signal used to synchronize the transfer of data It is driven by the master and received by the slave When SSP SPI interface is used the clock is programmable to be active high or active low otherwise it is always active high SCK only switches during a data transfer Any oth
319. duration may also be stretched for handshaking purposes This can be done after each bit or after a complete byte transfer the 12C block will stretch the SCL space duration after a byte has been transmitted or received and the acknowledge bit has been transferred The serial interrupt flag SI is set and the stretching continues until the serial interrupt flag is cleared Serial clock generator This programmable clock pulse generator provides the SCL clock pulses when the 12C block is in the master transmitter or master receiver mode It is switched off when the 12C block is in slave mode The 12C output clock frequency and duty cycle is programmable All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 268 of 404 NXP Semiconductors U M1 0524 14 9 8 14 9 9 14 9 10 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller via the 12C Clock Control Registers See the description of the IZCSCLL and I2CSCLH registers for details The output clock pulses have a duty cycle as programmed unless the bus is synchronizing with other SCL clock sources as described above Timing and control The timing and control logic generates the timing and control signals for serial byte handling This logic block provides the shift pulses for DAT enables the comparator generates and detects START and STOP conditions receives and transmits ackno
320. e 41 3 9 6 3 Wake up from Deep power down mode 41 3 10 System PLL USB PLL functional description 42 3 10 1 Lock detector 0c eee ee eee 43 3 10 2 Power down control 0 00 43 3 10 3 3 10 4 3 10 4 1 3 10 4 2 Chapter 23 Supplementary information Divider ratio programming 43 Post divider 200000 eee eee 43 Feedback divider 2 2 5 43 Changing the divider values 43 Frequency selection 43 Normal mode 000000000s 44 Power down mode 2 44 Chapter 4 LPC1315 16 17 45 46 47 Power Management Unit PMU 4 1 How to read this chapter 45 4 2 Introduction 220 0055 45 4 3 Register description 0000eees 45 4 3 1 Power control register 45 4 3 2 General purpose registers 0 t03 46 4 3 3 General purpose register 4 46 4 4 Functional description 47 Chapter 5 LPC1315 16 17 45 46 47 Power profiles 5 1 How to read this chapter 48 5 5 1 4 4 System clock less than or equal to the expected 5 2 ery 10 lt don raa aaa aA 48 VANUG s ee itag i ir hon e ha pedi ent iaei 52 5 3 Description 00ccce cece eee eeee 4g 5 5 1 4 5 System clock greater than or equal to the 54 Definiti 49 expected value 2 200ee eee 52 i aaa a A a ie aa ee ele 5 5 1 4 6 System cl
321. e If the SSP SPI is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW This causes slave data to be enabled onto the MISO input line of the master Master s MOSI is enabled One half SCK period later valid master data is transferred to the MOSI pin Now that both the master and slave data have been set the SCK master clock pin goes HIGH after one further half SCK period The data is captured on the rising and propagated on the falling edges of the SCK signal UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 246 of 404 NXP Semiconductors U M1 0524 Chapter 13 LPC1315 16 17 45 46 47 SSP SPI In the case of a single word transmission after all bits of the data word have been transferred the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured However in the case of continuous back to back transmissions the SSEL signal must be pulsed HIGH between each data word transfer This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the CPHA bit is logic zero Therefore the master device must raise the SSEL pin of the slave device between each data transfer to enable the serial peripheral data write On completion of the c
322. e 17 February 2012 Document identifier UM10524 All rights reserved
323. e and level sensitive pins Name Edge sensitive function Level sensitive function PINTEN_R Enables rising edge interrupts Enables interrupts PINTSEN_R Write to enable rising edge interrupts Write to enable interrupts PINTCEN_R Write to disable rising edge interrupts Write to disable interrupts PINTEN_F Enables falling edge interrupts Selects active level PINTSEN_F Write to enable falling edge interrupts Write to select high active PINTCEN_F Write to disable falling edge interrupts Write to select low active 9 6 4 2 Group interrupts In this interrupt facility an interrupt can be requested for each port based on any selected subset of pins within each port The pins that contribute to each port interrupt are selected by 1s in the port s Enable register and an interrupt polarity can be selected for each pin in the port s Polarity register The level on each pin is exclusive ORed with its polarity bit and the result is ANDed with its enable bit and these results are then inclusive ORed among all the pins in the port to create the port s raw interrupt request The raw interrupt request from each of the two group interrupts is sent to the NVIC which can be programmed to treat it as level or edge sensitive see Section 6 4 or it can be edge detected by the wake up interrupt logic see Table 39 9 6 5 Recommended practices The following lists some recommended uses for using the GPIO port registers e For initial setu
324. e GPIO port registers can be used to configure each GPIO pin as input or output and read the state of each pin if the pin is configured as input or set the state of each pin if the pin is configured as output 9 5 Register description UM10524 The GPIO consists of the following blocks All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 119 of 404 NXP Semiconductors UM10524 UM10524 Chapter 9 LPC1315 16 17 45 46 47 GPIO The GPIO pin interrupts block at address 0x4004 C000 Registers in this block enable the up to 8 pin interrupts selected in the syscon block PINTSEL registers see Table 35 and configure the level and edge sensitivity for each selected pin interrupt The GPIO interrupt registers are listed in Table 111 and Section 9 5 1 The GPIO GROUPO interrupt block at address 0x4005 C000 Registers in this block allow to configure any pin on port 0 and 1 to contribute to a combined interrupt The GPIO GROUPO registers are listed in Table 112 and Section 9 5 2 The GPIO GROUP 1 interrupt block at address 0x4005 8000 Registers in this block allow to configure any pin on port 0 and 1 to contribute to a combined interrupt The GPIO GROUP 1 registers are listed in Table 113 and Section 9 5 2 e The GPIO port block at address 0x5000 0000 Registers in this block allow to read and write to port pins and con
325. e General Call recognition if needed 2 Enable IC interrupt 3 Write 0x44 to CONSET to set the I2EN and AA bits enabling Slave functions For Master only functions write 0x40 to CONSET Start Master Transmit function Begin a Master Transmit operation by setting up the buffer pointer and data count then initiating a START 1 Initialize Master data counter All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 287 of 404 NXP Semiconductors U M1 0524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller Set up the Slave Address to which data will be transmitted and add the Write bit Write 0x20 to CONSET to set the STA bit Set up data to be transmitted in Master Transmit buffer Initialize the Master data counter to match the length of the message being sent Exit oOo oa fF W PP 14 11 3 Start Master Receive function 14 11 4 14 11 5 14 11 5 1 14 11 5 2 14 11 5 3 UM10524 Begin a Master Receive operation by setting up the buffer pointer and data count then initiating a START Initialize Master data counter Set up the Slave Address to which data will be transmitted and add the Read bit Write 0x20 to CONSET to set the STA bit Set up the Master Receive buffer Initialize the Master data counter to match the length of the message to be received Exit ona WO YP
326. e The updated buffer address should be accessible by USB DMA master If user doesn t want to use zero copy model then the user should copy data to the address pointed by the passed buffer pointer parameter and shouldn t change the address value See Zero Copy Data Transfer model for more details on zero copy concept lengthNumber of bytes to be read Parameters 1 offset Source start address 2 dst Pointer to a pointer to the source of data The MSC function drivers implemented in stack are written with zero copy model Meaning the stack doesn t make an extra copy of buffer before writing reading data from USB hardware FIFO Hence the parameter is pointer to a pointer containing address buffer uint8_t dst So that the user application can update the buffer pointer instead of copying data to address pointed by the parameter note The updated buffer address should be access able by USB DMA master If user doesn t want to use zero copy model then the user should copy data to the address pointed by the passed buffer pointer parameter and shouldn t change the address value See Zero Copy Data Transfer model for more details on zero copy concept 3 length Number of bytes to be read Returns Nothing UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 200 of 404 NXP Semiconductors UM10524 Chapter 11 LPC1345
327. e USBD_EVENT_T for more details enable1 enable event 0 disable event Parameters 1 hUsb Handle to the USB device stack 2 EPNum Endpoint number corresponding to the event as per USB specification ie An EP1_IN is represented by 0x81 number For device events set this param to 0x0 3 event Type of endpoint event See USBD_EVENT_T for more details 4 enable 1 enable event 0 disable event Returns Returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK 0 On success 2 ERR_USBD_INVALID_REQ 0x00040001 Invalid event type void void USBD_HW_API DisableEP USBD_HANDLE_T hUsb uint32_t EPNum Function to disable selected USB endpoint This function disables interrupts on selected endpoint hUsbHandle to the USB device stack EPNumEndpoint number as per USB specification ie An EP1_IN is represented by 0x81 number Parameters 1 hUsb Handle to the USB device stack 2 EPNum Endpoint number as per USB specification ie An EP1_IN is represented by 0x81 number Returns Nothing All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 193 of 404 NXP Semiconductors Table 199 USBD_HW_API class structure Member Description ResetEP void void USBD_HW_API ResetEP USBD_HANDLE_T hUsb uint32_t EPNum Function to reset selected USB endpoint
328. e VDD 31 11 Reserved 0 7 4 29 I O configuration for pin PIO1_4 Table 84 1 O configuration for pin PIO1_4 CT32B1_CAPO0 PIO1_4 address 0x4004 4070 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x2 to 0x7 are reserved 0 OxO PIO1_4 0x1 CT32B1_CAPO 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 88 of 404 NXP Semiconductors UM10524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration 7 4 30 I O configuration for pin PIO1_5 Table 85 I O configuration for pin PIO1_5 CT32B1_CAP1 PIO1_5 address 0x4004 4074 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x2 to 0x7 are reserved 0 0x0 3 PIO1_5 0x1 CT32B1
329. e entered Write Clear the Deep power down flag 31 12 Reserved Do not write ones to this bit 0 General purpose registers 0 to 3 The general purpose registers retain data through the Deep power down mode when power is still applied to the Vpp pin but the chip has entered Deep power down mode Only a cold boot when all power has been completely removed from the chip will reset the general purpose registers Table 49 General purpose registers 0 to 3 GPREGO GPREG3 address 0x4003 8004 to 0x4003 8010 bit description Bit Symbol Description Reset value 31 0 GPDATA Data retained during Deep power down mode 0x0 General purpose register 4 The general purpose register 4 retains data through the Deep power down mode when power is still applied to the Vpp pin but the chip has entered Deep power down mode Only a cold boot when all power has been completely removed from the chip will reset the general purpose registers Remark If there is a possibility that the external voltage applied on pin Vpp drops below 2 2 V during Deep power down the hysteresis of the WAKEUP input pin has to be disabled in this register before entering Deep power down mode in order for the chip to wake up All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 46 of 404 NXP Semiconductors U M1 0524 Chapter 4 LPC1315 16 17 45
330. e of the USB need_clock triggers the USB wake up 31 22 Reserved 0x00 USB clock status register USBCLKST This register is read only and returns the status of the USB need_clock signal For details of how to use the USB need_clock signal for waking up the part from Deep sleep or Power down modes see Section 10 7 6 Table 37 USB clock status USBCLKST address 0x4004 819C bit description Bit Symbol Value Description Reset value 0 NEED_CLKST USB need_clock signal status 0x0 0 LOW 1 HIGH 31 1 Reserved 0x00 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 28 of 404 NXP Semiconductors U M1 0524 UM10524 3 5 33 3 5 34 Chapter 3 LPC1315 16 17 45 46 47 System control block Start logic 0 interrupt wake up enable register 0 STARTERPO The STARTERPO register enables the individual GPIO pins selected through the Pin interrupt select registers see Table 35 for wake up The pin interrupts must also be enabled in the NVIC interrupts 0 to 8 in Table 53 Table 38 Start logic 0 interrupt wake up enable register 0 STARTERPO address 0x4004 8204 bit description Bit Symbol Value Description Reset value 0 PINTO Pin interrupt 0 wake up 0 0 Disabled 1 Enabled 1 PINT1 Pin interrupt 1 wake up 0 0 Disabled 1 Enabled 2 PINT2 Pin interrupt 2 wake up 0 0 Disabled 1 Enabled 3 PINT3 Pin inte
331. e read in order to clear the corresponding DONE flag Accuracy vs digital receiver While the A D converter can be used to measure the voltage on any ADC input pin regardless of the pin s setting in the IOCON block selecting the ADC in the IOCON registers function improves the conversion accuracy by disabling the pin s digital receiver see also Section 7 3 7 Optional operating modes There are two optional modes of A D operation which may be selected in the CR register 1 The 10 bit mode In this mode two bits of ADC accuracy are sacrificed in order to double the conversion rate The maximum ADC clock rate when this mode is selected is increased to 31 MHz BURST bit 0 The two LSB of the conversion result will be forced to 00 when this mode is enabled 2 The low power mode When this mode is selected the analog portions of the ADC are automatically shut down when no conversions are in progress The ADC is automatically restarted whenever any hardware or software triggering event occurs provided the ADC is not powered down in the PDRUNCFG register or the part is in Deep sleep Power down or Deep power down mode When the requested conversion completes the analog ADC circuitry will be returned to its power down state unless a new conversion is pending Setting the BURST bit will override low power mode and prevent the ADC from being automatically powered down All information provided in this document is subject to legal disc
332. e request The wlndex field is often used in requests to specify an endpoint or an interface uintl6_tuintl6_t _USB_SETUP_PACKET wlength This field specifies the length of the data transferred during the second phase of the control transfer 11 5 23 USB _STRING_DESCRIPTOR UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 165 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 188 _USB_STRING_DESCRIPTOR class structure Member bLength bDescriptorType bString Description uint8_tuint8_t _USB_STRING_DESCRIPTOR bLength Size of this descriptor in bytes uint8_tuint8_t _USB_STRING_DESCRIPTOR bDescriptorType STRING Descriptor Type uint16_tuint16_t _USB_STRING_DESCRIPTOR bString UNICODE encoded string 11 5 24 _WB_T Table 189 _WB_T class structure Member L Description uint8_tuint8_t _WB_T L lower byte uint8_tuint8_t _WB_T H upper byte 11 5 25 USBD_API Main USBD API functions structure This structure contains pointer to various USB Device stack s sub module function tables This structure is used as main entry point to access various methods grouped in sub modules exposed by ROM based USB device stack Table 190 USBD_API class structure Member Description hw const USBD_HW_API_T c
333. e used by users who are selectively modifying the USB device stack s standard handlers through callback interface exposed by the stack hUsbHandle to the USB device stack adrUSB bus Address to which the device controller should respond Usually assigned by the USB host Parameters 1 hUsb Handle to the USB device stack 2 adr USB bus Address to which the device controller should respond Usually assigned by the USB host Returns Nothing Configure void void USBD_HW_API Configure USBD_HANDLE_T hUsb uint32_t cfg Function to configure device controller hardware with selected configuration This function is called automatically when USB_REQUEST_SET CONFIGURATION request is received by the stack from USB host This interface is provided to users to invoke this function in other scenarios which are not handle by current stack In most user applications this function is not called directly Also this function can be used by users who are selectively modifying the USB device stack s standard handlers through callback interface exposed by the stack hUsbHandle to the USB device stack cfgConfiguration index Parameters 1 hUsb Handle to the USB device stack 2 cfg Configuration index Returns Nothing UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 191 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on
334. e will be received and NOT ACK been received ACK will be returned has been returned No DAT action X 0 0 1 Data byte will be received and ACK will be returned 0x68 Arbitration lost in No DAT actionor X 0 0 0 Data byte will be received and NOT ACK SLA R W as master will be returned Own SLA W has No DAT action X 0 0 1 Data byte will be received and ACK will been received ACK be returned returned 0x70 General call address No DAT actionor X 0 0 0 Data byte will be received and NOT ACK 0x00 has been will be returned received ACK has No DAT action X 0 0 1 Data byte will be received and ACK will been returned be retumed 0x78 Arbitration lost in No DAT actionor X 0 0 0 Data byte will be received and NOT ACK SLA R W as master will be returned General call address No DAT action x 0 0 1 Data byte will be received and ACK will has been received be returned ACK has been returned 0x80 Previously addressed Read data byte or X 0 0 0 Data byte will be received and NOT ACK with own SLV will be returned address DATA has Read data byte X 0 0 1 Databyte will be received and ACK will been received ACK be returned has been returned 0x88 Previously addressed Read data byte or 0 0 0 0 Switched to not addressed SLV mode no with own SLA DATA recognition of own SLA or General call byte has been address received NOT ACK Read data byte or 0 0 0 1 Switched to not addressed SLV mode has been returned Own SLA will be recognized General call addres
335. eady output for USART SSEL1 Slave select for SSP1 P101_20 General purpose digital input output pin DSR Data Set Ready input for USART SCK1 Serial clock for SSP1 P101_21 General purpose digital input output pin DCD Data Carrier Detect input for USART MISO1 Master In Slave Out for SSP1 P101_22 General purpose digital input output pin RI Ring Indicator input for USART MOSI1 Master Out Slave In for SSP1 P101_23 General purpose digital input output pin CT16B1_MAT1 Match output 1 for 16 bit timer 1 SSEL1 Slave select for SSP1 User manual Rev 1 17 February 2012 NXP B V 2012 All rights reserved 115 of 404 NXP Semiconductors UM10524 Chapter 8 LPC1315 16 17 45 46 47 Pin configuration Table 109 Pin description LPC1345 46 47 with USB Symbol 1 Description A 2 Bee 3 ses f 8 l al aks w G PIO1_24 CT32B0_MATO 27 21 BI PU VO PIO1_24 General purpose digital input output pin O CT32B0_MAT0 Match output 0 for 32 bit timer 0 PIO1_25 CT32BO_MAT1 2 1 BI PU VO P101_25 General purpose digital input output pin O CT32B0_MAT1 Match output 1 for 32 bit timer 0 PIO1_26 CT32B0_MAT2 14 11 BI PU VO PIO1_26 General purpose digital input output pin RXD z O CT32B0_MAT2 Match output 2 for 32 bit timer 0 5 l RXD Receiver input for USART PIO1_27 CT32B0_MAT3 15 12 BI PU VO P101_27 Gene
336. eceive data TXD Output Serial Output Serial transmit data input output in smart card mode RTS Output Request To Send RS 485 direction control pin CTS Input Clear To Send DTR Output Data Terminal Ready DSR Input Data Set Ready DCD Input Data Carrier Detect RI Input Ring Indicator SCLK I O Serial Clock All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 203 of 404 NXP Semiconductors U M1 0524 Chapter 12 LPC1315 16 17 45 46 47 USART 12 5 Register description The USART contains registers organized as shown in Table 203 The Divisor Latch Access Bit DLAB is contained in LCR 7 and enables access to the Divisor Latches Offsets addresses not shown in Table 203 are reserved Table 203 Register overview USART base address 0x4000 8000 Name Access Address Description Reset Reference offset value RBR RO 0x000 Receiver Buffer Register Contains the next received NA Table 204 character to be read DLAB 0 THR WO 0x000 Transmit Holding Register The next character to be NA Table 205 transmitted is written here DLAB 0 DLL R W 0x000 Divisor Latch LSB Least significant byte of the baud 0x01 Table 206 rate divisor value The full divisor is used to generate a baud rate from the fractional rate divider DLAB 1 DLM R W 0x004 Divisor Latch MSB Most significant byte of the baud 0 Table 2
337. ect USBD_HANDLE_T hUsb uint32_t con Function to make USB device visible invisible on the USB bus This function is called after the USB initialization This function uses the soft connect feature to make the device visible on the USB bus This function is called only after the application is ready to handle the USB data The enumeration process is started by the host after the device detection The driver handles the enumeration process according to the USB descriptors passed in the USB initialization function hUsbHandle to the USB device stack conStates whether to connect 1 or to disconnect 0 Parameters 1 hUsb Handle to the USB device stack 2 con States whether to connect 1 or to disconnect 0 Returns Nothing UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 189 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 199 USBD_HW_API class structure Member ISR Reset ForceFullSpeed UM10524 Description void void USBD_HW_API ISR USBD_HANDLE_T hUsb Function to USB device controller interrupt events When the user application is active the interrupt handlers are mapped in the user flash space The user application must provide an interrupt handler for the USB interrupt and call this function in the interrupt handler routine The driver interrupt h
338. ect to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 205 of 404 NXP Semiconductors U M1 0524 UM10524 12 5 3 12 5 4 Chapter 12 LPC1315 16 17 45 46 47 USART USART Divisor Latch LSB and MSB Registers when DLAB 1 The USART Divisor Latch is part of the USART Baud Rate Generator and holds the value used optionally with the Fractional Divider to divide the UART_PCLK clock in order to produce the baud rate clock which must be the multiple of the desired baud rate that is specified by the Oversampling Register typically 16X The DLL and DLM registers together form a 16 bit divisor DLL contains the lower 8 bits of the divisor and DLM contains the higher 8 bits A zero value is treated like 0x0001 The Divisor Latch Access Bit DLAB in the LCR must be one in order to access the USART Divisor Latches Details on how to select the right value for DLL and DLM can be found in Section 12 5 14 Table 206 USART Divisor Latch LSB Register when DLAB 1 DLL address 0x4000 8000 bit description Bit Symbol Description Reset value 7 0 DLLSB The USART Divisor Latch LSB Register along with the DLM 0x01 register determines the baud rate of the USART 31 8 Reserved Table 207 USART Divisor Latch MSB Register when DLAB 1 DLM address 0x4000 8004 bit description Bit Symbol Description Reset value 7 0 DLMSB The USART Divisor Latch MSB Register along with
339. ected on that pin 20 5 Register description The ADC contains registers organized as shown in Table 323 Table 323 Register overview ADC base address 0x4001 C000 Name Access Address Description Reset Reference offset Valuelt CR R W 0x000 A D Control Register The CR register must be written to 0x0000 0000 Table 324 select the operating mode before A D conversion can occur GDR RAW 0x004 A D Global Data Register Contains the result of the most NA Table 325 recent A D conversion 0x008 Reserved INTEN R W 0x00C A D Interrupt Enable Register This register contains enable 0x0000 0100 Table 326 bits that allow the DONE flag of each A D channel to be included or excluded from contributing to the generation of an A D interrupt DRO R W 0x010 A D Channel 0 Data Register This register contains the result NA Table 327 of the most recent conversion completed on channel 0 DR1 R W 0x014 A D Channel 1 Data Register This register contains the result NA Table 327 of the most recent conversion completed on channel 1 DR2 R W 0x018 A D Channel 2 Data Register This register contains the result NA Table 327 of the most recent conversion completed on channel 2 DR3 R W 0x01C A D Channel 3 Data Register This register contains the result NA Table 327 of the most recent conversion completed on channel 3 DR4 R W 0x020 A D Channel 4 Data Register This register contains the result NA Table 327 of the most recent conversion complete
340. ed User manual Rev 1 17 February 2012 124 of 404 NXP Semiconductors U M1 0524 UM10524 9 5 1 9 Chapter 9 LPC1315 16 17 45 46 47 GPIO Table 122 Pin interrupt rising edge register RISE address 0x4004 C01C bit description Bit Symbol Description Reset Access value 7 0 RDET Rising edge detect Bit n detects the rising edge of the pin 0 R W selected in PINTSELn Read 0 No rising edge has been detected on this pin since Reset or the last time a one was written to this bit Write 0 no operation Read 1 a rising edge has been detected since Reset or the last time a one was written to this bit Write 1 clear rising edge detection for this pin 31 8 Reserved 7 7 Pin interrupt falling edge register This register contains ones for pin interrupts selected in the PINTSEL registers see Table 35 on which a falling edge has been detected Writing ones to this register clears falling edge detection Ones in this register assert an interrupt request for pins that are enabled for falling edge interrupts All edges are detected for all pins selected by the PINTSEL registers regardless of whether they are interrupt enabled Table 123 Pin interrupt falling edge register FALL address 0x4004 C020 bit description Bit Symbol Description Reset Access value 7 0 FDET Falling edge detect Bit n detects the falling edge of the pin 0O R W selected in PINTSELn Read 0 No falling edge has been detected on th
341. ed in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 135 of 404 NXP Semiconductors U M1 0524 Chapter 10 LPC 1345 46 47 USB2 0 device controller The USB device controller on the LPC1315 16 1 7 45 46 47 enables full speed 12 Mb s data exchange with a USB host controller Figure 10 shows the block diagram of the USB device controller REGISTER USB SYNC SIE INTERFACE URONIZER INTERFACE AHB_SLAVE SERIAL INTERFACE DMA ENGINE ENGINE SIE AHB_MASTER CLKREC USB ATX USB_CONNECT USB_VBUS USB_FTOGGLE USB_DP USB_DM Fig 10 USB block diagram The USB Device Controller has a built in analog transceiver ATX The USB ATX sends receives the bi directional USB_DP and USB_DM signals of the USB bus The SIE implements the full USB protocol layer It is completely hardwired for speed and needs no software intervention It handles transfer of data between the endpoint buffers in USB RAM and the USB bus The functions of this block include synchronization pattern recognition parallel serial conversion bit stuffing de stuffing CRC checking generation PID verification generation address recognition and handshake evaluation generation UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 136 of 404 NXP Se
342. ee 11 Table 32 System tick counter calibration SYSTCKCAL Table 5 Register overview SYSCON base address address 0x4004 8154 bit description 26 0x4004 8000 2 eee eee eee 13 Table 33 IQR delay IRQLATENCY address 0x4004 8170 Table 6 System memory remap SYSMEMREMAP bit description 200 20005 27 address 0x4004 8000 bit description 14 Table 34 NMI Source Control NMISRC address 0x4004 Table 7 Peripheral reset control PRESETCTRL address 8174 bit description 0 27 0x4004 0004 bit description 15 Table 35 GPIO Pin Interrupt Select register PINTSEL Table 8 System PLL control SYSPLLCTRL address address 0x4004 8178 bit description 28 0x4004 8008 bit description 15 Table 36 USB clock control USBCLKCTRL address Table 9 System PLL status SYSPLLSTAT address 0x4004 8198 bit description 28 0x4004 800C bit description 15 Table 37 USB clock status USBCLKST address 0x4004 Table 10 USB PLL control USBPLLCTRL address 0x4004 819C bit description 28 8010 bit description 00 16 Table 38 Start logic 0 interrupt wake up enable register 0 Table 11 USB PLL status USBPLLSTAT address 0x4004 STARTERPO address 0x4004 8204 bit 8014 bit description 16 description 200 e eee 29 Table 12 System oscillator control SYSOSCCTRL Table 39 Start log
343. eg 1 628 Since FRest 1 628 is within the specified range of 1 1 and 1 9 DIVADDVAL and MULVAL values can be obtained from the attached look up table The closest value for FRest 1 628 in the look up Table 222 is FR 1 625 It is equivalent to DIVADDVAL 5 and MULVAL 8 Based on these findings the suggested USART setup would be DLM 0 DLL 4 DIVADDVAL 5 and MULVAL 8 According to Equation 3 the USART s baud rate is 115384 This rate has a relative error of 0 16 from the originally specified 115200 USART Oversampling Register In most applications the USART samples received data 16 times in each nominal bit time and sends bits that are 16 input clocks wide This register allows software to control the ratio between the input clock and bit clock This is required for smart card mode and provides an alternative to fractional division for other modes All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 224 of 404 NXP Semiconductors U M1 0524 12 5 16 UM10524 Chapter 12 LPC1315 16 17 45 46 47 USART Table 223 USART Oversampling Register OSR address 0x4000 802C bit description Bit Symbol Description Reset value 0 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 3 1 OSFRAC Fractional part of the oversampling ratio in un
344. elect register SYSPLLCLKSEL This register selects the clock source for the system PLL Table 15 System PLL clock source select SYSPLLCLKSEL address 0x4004 8040 bit description Bit Symbol Value Description Reset value 1 0 SEL System PLL clock source 0 0x0 IRC 0x1 Crystal Oscillator SYSOSC 0x2 Reserved 0x3 Reserved 31 2 Reserved USB PLL clock source select register USBPLLCLKSEL This register selects the clock source for the dedicated USB PLL Remark When switching clock sources both clocks must be running Table 16 USB PLL clock source select USBPLLCLKSEL address 0x4004 8048 bit description Bit Symbol Value Description Reset value 1 0 SEL USB PLL clock source 0x00 0x0 IRC The USB PLL clock source must be switched to system oscillator for correct USB operation 0x1 System oscillator 0x2 Reserved 0x3 Reserved 31 22 Reserved 0x00 Main clock source select register MAINCLKSEL This register selects the main system clock which can be the system PLL sys_pllclkout or the watchdog oscillator or the IRC oscillator The main system clock clocks the core the peripherals and the memories All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 19 of 404 NXP Semiconductors U M1 0524 3 5 13 3 5 14 Chapter 3 LPC1315 16 17 45 46 47 System control block Table 17 Main c
345. emark If Counter mode is selected in the CTCR the 3 bits for that input in the Capture Control Register CCR must be programmed as 000 Values 0x2 to 0x3 are reserved 0x0 CT32Bn_CAPO 0x1 CT32Bn_CAP1 4 ENCC Setting this bit to 1 enables clearing of the timer and the 0 prescaler when the capture edge event specified in bits 7 5 occurs 7 5 SEICC When bit 4 is a 1 these bits select which capture input edge will cause the timer and prescaler to be cleared These bits have no effect when bit 4 is low Values 0x3 to 0x7 are reserved 0x0 Rising Edge of CAPO clears the timer if bit 4 is set 0x1 Falling Edge of CAPO clears the timer if bit 4 is set 0x2 Rising Edge of CAP1 clears the timer if bit 4 is set 0x3 Falling Edge of CAP1 clears the timer if bit 4 is set 31 8 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 320 of 404 NXP Semiconductors U M1 0524 Chapter 16 LPC1315 16 17 45 46 47 32 bit counter timers CT32B0 1 16 7 12 PWM Control Register The PWM Control Register is used to configure the match outputs as PWM outputs Each match output can be independently set to perform either as PWM output or as match output whose function is controlled by the External Match Register EMR
346. en onto the pin 1 The pin must be selected for GPIO operation in the I O Configuration block and 2 the pin must be selected for output by a 1 in its port s DIR register If either or both of these conditions is are not met writing to the pin has no effect There are seven ways to change GPIO output bits e Writing to a Byte Pin register loads the output bit from the least significant bit e Writing to a Word Pin register loads the output bit with the OR of all of the bits written This feature follows the definition of truth of a multi bit value in programming languages e Writing to a port s PORT register loads the output bits of all the pins written to UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 132 of 404 NXP Semiconductors U M1 0524 UM10524 9 6 3 9 6 4 9 6 4 1 Chapter 9 LPC1315 16 17 45 46 47 GPIO e Writing to a ports MPORT register loads the output bits of pins identified by zeros in corresponding positions of the port s MASK register e Writing ones to a port s SET register sets output bits e Writing ones to a port s CLR register clears output bits e Writing ones to a port s NOT register toggles complements inverts output bits The state of a port s output bits can be read from its SET register Reading any of the registers described in 9 6 1 returns
347. ending TCR R W 0x004 Timer Control Register The TCR is used to control the Timer 0 Table 288 Counter functions The Timer Counter can be disabled or reset through the TCR TC R W 0x008 Timer Counter The 32 bit TC is incremented every PR 1 cycles of 0 Table 289 PCLK The TC is controlled through the TCR PR R W 0x00C Prescale Register When the Prescale Counter below is equalto 0 Table 290 this value the next clock increments the TC and clears the PC PC R W 0x010 Prescale Counter The 32 bit PC is a counter which is incremented 0 Table 291 to the value stored in PR When the value in PR is reached the TC is incremented and the PC is cleared The PC is observable and controllable through the bus interface MCR R W 0x014 Match Control Register The MCR is used to control if an interruptis 0 Table 292 generated and if the TC is reset when a Match occurs MRO R W 0x018 Match Register 0 MRO can be enabled through the MCR to reset 0 Table 293 the TC stop both the TC and PC and or generate an interrupt every time MRO matches the TC MR1 R W 0x01C Match Register 1 See MRO description 0 Table 293 MR2 R W 0x020 Match Register 2 See MRO description 0 Table 293 MR3 R W 0x024 Match Register 3 See MRO description 0 Table 293 CCR R W 0x028 Capture Control Register The CCR controls which edges of the 0 Table 294 capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place
348. eneral Call address 0x00 is recognized If this register contains 0x00 the 12C will not acknowledge any address on the bus All four registers ADRO to ADR3 will be cleared to this disabled state on reset See also Table 254 Table 248 I2C Slave Address register 0 ADRO 0x4000 000C bit description Bit Symbol Description Reset value 0 GC General Call enable bit 0 7 1 Address The lC device address for slave mode 0x00 31 8 Reserved The value read from a reserved bit is not defined I2C SCL HIGH and LOW duty cycle registers SCLH and SCLL Table 249 1 C SCL HIGH Duty Cycle register SCLH address 0x4000 0010 bit description Bit Symbol Description Reset value 15 0 SCLH Count for SCL HIGH time period selection 0x0004 31 16 Reserved The value read from a reserved bit is not defined Table 250 12C SCL Low duty cycle register SCLL 0x4000 0014 bit description Bit Symbol Description Reset value 15 0 SCLL Count for SCL low time period selection 0x0004 31 16 Reserved The value read from a reserved bit is not defined Selecting the appropriate IC data rate and duty cycle Software must set values for the registers SCLH and SCLL to select the appropriate data rate and duty cycle SCLH defines the number of I12C_PCLK cycles for the SCL HIGH time SCLL defines the number of I2C_PCLK cycles for the SCL low time The frequency is determined by the following formula l2C_PCLK is the frequency of the pe
349. eneration A signature can be generated for any part of the flash contents The address range to be used for signature generation is defined by writing the start address to the FASSTART register and the stop address to the FMSSTOP register The signature generation is started by writing a 1 to the SIG_START bit in the FASSTOP register Starting the signature generation is typically combined with defining the stop address which is done in the STOP bits of the same register The time that the signature generation takes is proportional to the address range for which the signature is generated Reading of the flash memory for signature generation uses a self timed read mechanism and does not depend on any configurable timing settings for the flash A safe estimation for the duration of the signature generation is Duration int 60 tcy 3 x FMSSTOP FMSSTART 1 When signature generation is triggered via software the duration is in AHB clock cycles and tcy is the time in ns for one AHB clock The SIG_DONE bit in FMSTAT can be polled by software to determine when signature generation is complete After signature generation a 128 bit signature can be read from the FMSWO to FMSW3 registers The 128 bit signature reflects the corrected data read from the flash The 128 bit signature reflects flash parity bits and check bit values Content verification The signature as it is read from the FMSWO to FMSWS3 registers must be equal
350. enerator must be disabled DIVADDVAL 0 during auto baud Also when auto baud is used any write to DLM and DLL registers should be done before ACR register write The minimum and the maximum baud rates supported by USART are a function of USART_PCLK and the number of data bits stop bits and parity bits 2 ratemax 2 x PCLK PCLK t lt S UART L a ee Cs lox 245 y baudrate 16 x 2 databits paritybits stopbits Auto baud modes When the software is expecting an AT command it configures the USART with the expected character format and sets the ACR Start bit The initial values in the divisor latches DLM and DLM don t care Because of the A or a ASCII coding A 0x41 a 0x61 the USART Rx pin sensed start bit and the LSB of the expected character are delimited by two falling edges When the ACR Start bit is set the auto baud protocol will execute the following phases 1 On ACR Start bit setting the baud rate measurement counter is reset and the USART RSR is reset The RSR baud rate is switched to the highest rate 2 A falling edge on USART Rx pin triggers the beginning of the start bit The rate measuring counter will start counting UART_PCLK cycles 3 During the receipt of the start bit 16 pulses are generated on the RSR baud input with the frequency of the USART input clock guaranteeing the start bit is stored in the RSR 4 During the receipt of the start bit and the
351. ensures that the system clock is shut down glitch free All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 38 of 404 NXP Semiconductors U M1 0524 UM10524 Chapter 3 LPC1315 16 17 45 46 47 System control block 5 Select the power configuration after wake up in the PDAWAKECFG Table 41 register 6 If any of the available wake up interrupts are needed for wake up enable the interrupts in the interrupt wake up registers Table 38 Table 39 and in the NVIC 7 Write one to the SLEEPDEEP bit in the ARM Cortex M3 SCR register 8 Use the ARM WFI instruction 3 9 4 3 Wake up from Deep sleep mode 3 9 5 The microcontroller can wake up from Deep sleep mode in the following ways e Signal on one of the eight pin interrupts selected in Table 35 Each pin interrupt must also be enabled in the STARTERP0 register Table 38 and in the NVIC e BOD signal if the BOD is enabled in the PDSLEEPCFG register BOD interrupt using the deep sleep interrupt wake up register 1 Table 39 The BOD interrupt must be enabled in the NVIC The BOD interrupt must be selected in the BODCTRL register Reset from the BOD circuit In this case the BOD circuit must be enabled in the PDSLEEPCFG register and the BOD reset must be enabled in the BODCTRL register Table 31 e WWDT signal if the watchdog oscillator is enabled in the P
352. ep sending data as long as they are available As soon as TxEn becomes 0 USART transmission will stop Although Table 224 describes how to use TxEn bit in order to achieve hardware flow control it is strongly suggested to let the USART hardware implemented auto flow control features take care of this and limit the scope of TxEn to software flow control Table 224 describes how to use TXEn bit in order to achieve software flow control All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 225 of 404 NXP Semiconductors U M1 0524 12 5 17 12 5 18 UM10524 Chapter 12 LPC1315 16 17 45 46 47 USART Table 224 USART Transmit Enable Register TER address 0x4000 8030 bit description Bit Symbol Description Reset Value 6 0 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 7 TXEN When this bit is 1 as it is after a Reset data written tothe THR 1 is output on the TXD pin as soon as any preceding data has been sent If this bit cleared to 0 while a character is being sent the transmission of that character is completed but no further characters are sent until this bit is set again In other words a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register Software can clear this bit when it detects that the
353. ep sleep or Power down modes are entered Therefore the user must ensure that the appropriate WWDT clock source for each power mode is selected before setting bit 5 in the MOD register e Active or Sleep modes Both the IRC or the watchdog oscillator are allowed e Deep sleep mode Both the IRC and the watchdog oscillator are allowed However using the IRC during Deep sleep mode will increase the power consumption To minimize power consumption use the watchdog oscillator as clock source e Power down mode Only the watchdog oscillator is allowed as clock source for the WWDT Therefore before setting bit 5 and locking the clock source the WWDT clock source must be set to the watchdog oscillator Otherwise the part may not be able to enter Power down mode e Deep power down mode No clock locking mechanisms are in effect as neither the WWDT nor any of the clocks are running However an additional lock bit in the PMU can be set to prevent the part from even entering Deep power down mode see Table 48 The clock source lock mechanism can only be disabled by a reset of any type Changing the WWDT reload value If bit 4 is set in the WWDT MOD register the watchdog time out value TC can be changed only after the counter is below the value of WOWARNINT and WOWINDOW The reload overwrite lock mechanism can only be disabled by a reset of any type All information provided in this document is subject to legal disclaimers NXP B V 2012
354. ept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities 23 2 3 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I2C bus logo is a trademark of NXP B V NXP B V 2012 All rights reserved User manual Rev 1 17 February 201 388 of 404 NXP Semiconductors UM10524 Chapter 23 Supplementary information 23 3 Tables Table 1 Ordering information 04 5 address 0x4004 8104 bit description 25 Table 2 Ordering options 0005 6 Table 31 Brown Out Detect BODCTRL address 0x4004 Table 3 LPC1315 16 17 45 46 47 memory configuration 8 8150 bit description 0 26 Table 4 Pinsummary 00 e eee eee e
355. er Table 30 POR captured PIO status 1 PIOPORCAP1 address 0x4004 8104 bit description Bit Symbol Description Reset value 31 0 PIOSTAT State of P1_31 through P1_0 at Implementation power on reset dependent 3 5 26 Brown Out Detect register BODCTRL The BOD control register selects four separate threshold values for sending a BOD interrupt to the NVIC and for forced reset Reset and interrupt threshold values listed in Table 31 are typical values UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 25 of 404 NXP Semiconductors U M1 0524 UM10524 3 5 27 3 5 28 Chapter 3 LPC1315 16 17 45 46 47 System control block Both the BOD interrupt and the BOD reset depending on the value of bit BODRSTENA in this register can wake up the chip from Sleep Deep sleep and Power down modes See Section 3 9 Table 31 Brown Out Detect BODCTRL address 0x4004 8150 bit description Bit Symbol Value Description Reset value 1 0 BODRSTLEV BOD reset level 00 0x0 Level 0 The reset assertion threshold voltage is 1 46 V the reset de assertion threshold voltage is 1 63 V 0x1 Level 1 The reset assertion threshold voltage is 2 06 V the reset de assertion threshold voltage is 2 15 V 0x2 Level 2 The reset assertion threshold voltage is 2 35 V the reset de assertion threshold voltage is 2 43 V 0x3 Level 3
356. er The 16 bit Timer Counter is incremented when the Prescale Counter reaches its terminal count Unless it is reset before reaching its upper limit the TC will count up to the value 0x0000 FFFF and then wrap back to the value 0x0000 0000 This event does not cause an interrupt but a Match register can be used to detect an overflow if needed Table 273 Timer counter registers TC address 0x4000 C008 CT16B0 and 0x4001 0008 CT16B1 bit description Bit Symbol Description Reset value 15 0 TC Timer counter value 0 31 16 Reserved UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 299 of 404 NXP Semiconductors U M1 0524 15 7 4 15 7 5 15 7 6 Chapter 15 LPC1315 16 17 45 46 47 16 bit counter timers CT16B0 1 Prescale Register The 16 bit Prescale Register specifies the maximum value for the Prescale Counter Table 274 Prescale registers PR address 0x4000 C00C CT16B0 and 0x4001 000C CT16B1 bit description Bit Symbol Description Reset value 15 0 PCVAL Prescale value 0 31 16 Reserved Prescale Counter register The 16 bit Prescale Counter controls division of PCLK by some constant value before it is applied to the Timer Counter This allows control of the relationship between the resolution of the timer and the maximum time before the timer overflows The Prescale Counter is incremented on ever
357. er 8 LPC1315 16 17 45 46 47 Pin configuration Rev 1 17 February 2012 User manual 8 1 Pin configuration 8 1 1 Pin description Table 108 and Table 109 show all pins and their assigned digital or analog functions ordered by GPIO port number The default function after reset is listed first All port pins have internal pull up resistors enabled after reset with the exception of the true open drain pins PIOO_4 and PIOO_5 Every port pin has a corresponding IOCON register through which the digital or analog function pull up pull down configuration repeater and open drain modes can be programmed To select a port pin for one of the peripheral functions in program the FUNC bits in the port pin s IOCON register with this function The user must ensure that the assignment of a function to a port pin is unambiguous for functions that are multiplexed to more than one port pin The debug functions for JTAG and SWD are selected by default in their corresponding IOCON registers All other functions must be programmed in the IOCON block before they can be used Table 108 Pin description L_PC1315 16 17 no USB Symbol Description Q 2 T 393 2 5S 8 8 l l lt ed E RESET PIO0_0 4 3 2 2 PU I RESET External reset input with 20 ns glitch filter A LOW going pulse as short as 50 ns on this pin resets the device causing I O ports and peripherals to take on their default states and processor execution to begin at
358. er description 5 296 15 7 12 PWM Control register 306 15 7 1 Interrupt Register 299 15 7 13 Rules for single edge controlled PWM 15 7 2 Timer Control Register 299 Outputs 6 2 eee 307 15 7 3 Timer Counter 0 eee ee eee 299 15 8 Example timer operation 307 15 7 4 Prescale Register 300 15 9 Architecture 200eee eee 308 Chapter 16 LPC1315 16 17 45 46 47 32 bit counter timers CT32B0 1 16 1 How to read this chapter 310 16 7 4 Prescale Register 0055 315 16 2 Basic configuration 0055 310 16 7 5 Prescale Counter Register 315 16 3 Features ceceeececececcueeees 310 pate eel Sake Register 4 z ees A atch Registers 0 000 eae 164 Applications Bote ee aes ees am 16 7 8 Capture Control Register 317 16 5 General description 311 16 7 9 Capture Register 0ee0eee 317 16 6 Pin description n n nananana 311 16 7 10 External Match Register 318 16 7 Register description 311 16 7 11 Count Control Register 319 16 7 1 Interrupt Register 314 16 7 12 PWM Control Register 321 16 7 2 Timer Control Register 314 16 7 13 Rules for single edge controlled PWM 16 7 3 Timer Counter registers
359. er time the SSP SPI interface either holds it in its inactive state or does not drive it leaves it in high impedance state SSELO 1 I O SSEL FS CS Frame Sync Slave Select When the SSP SPI interface is a bus master it drives this signal to an active state before the start of serial data and then releases it to an inactive state after the data has been sent The active state of this signal can be high or low depending upon the selected bus and mode When the SSP SPI interface is a bus slave this signal qualifies the presence of data from the Master according to the protocol in use Pin name When there is just one bus master and one bus slave the Frame Sync or Slave Select signal from the Master can be connected directly to the slave s corresponding input When there is more than one slave on the bus further qualification of their Frame Select Slave Select inputs will typically be necessary to prevent more than one slave from responding to a transfer MISOO 1 YO MISO DR M SI M Master In Slave Out The MISO signal transfers DX S SO S serial data from the slave to the master When the SSP SPI is a slave serial data is output on this signal When the SSP SPI is a master it clocks in serial data from this signal When the SSP SPI is a slave and is not selected by FS SSEL it does not drive this signal leaves it in high impedance state MOSI0 1 IYO MOSI DX M SO M Master Out Slave In The MOSI signal transfers DR S SI S se
360. erased by this command To erase a single sector use the same Start and End sector numbers UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 374 of 404 NXP Semiconductors U M1 0524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming 21 14 4 Blank check sector s Table 357 IAP Blank check sector s command Command Blank check sector s Input Command code 53 decimal Param0 Start Sector Number Param1 End Sector Number should be greater than or equal to start sector number Return Code CMD SUCCESS BUSY SECTOR_NOT_BLANK INVALID_SECTOR Result Result0 Offset of the first non blank word location if the Status Code is SECTOR_NOT_BLANK Result1 Contents of non blank word location Description This command is used to blank check a sector or multiple sectors of on chip flash memory To blank check a single sector use the same Start and End sector numbers 21 14 5 Read Part Identification number Table 358 IAP Read Part Identification command Command Read part identification number Input Command code 54 decimal Parameters None Return Code CMD SUCCESS Result Result0 Part Identification Number Description This command is used to read the part identification number 21 14 6 Read Boot code version number Table 359 IAP Read Boot Code version number comm
361. eresis Disable Enable Invert input Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 Reserved Open drain mode Disable Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD Reserved Reset value 0x2 0x1 7 4 12 I O configuration for pin TDI PIO0_11 Table 67 I O configuration for pin TDI PIO0_11 AD0 CT32B0_MAT3 TDI_PIO0_11 address 0x4004 402C bit description Bit Symbol 2 0 FUNC UM10524 Value Description 0x0 0x1 0x2 0x3 All information provided in this document is subject to legal disclaimers Selects pin function Values 0x4 to 0x7 are reserved TDI PIOO_11 ADO CT32B0_MATS3 Reset value 0 NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 73 of 404 NXP Semiconductors UM10524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 67 I O configuration for pin TDI PIO0_11 AD0 CT32B0_MAT3 TDI_PIOO_11 address 0x4004 402C bit description Bit Symbol Value Description Reset value 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted
362. ernal SRAM or the flash memory respectively Table 367 Memory mapping in debug mode Memory mapping mode Bootloader mode User flash mode User SRAM mode Memory start address visible at 0x0000 0004 0x1FFF 0000 0x0000 0000 0x1000 0000 21 15 2 Serial Wire Debug SWD flash programming interface Debug tools can write parts of the flash image to RAM and then execute the IAP call Copy RAM to flash repeatedly with proper offset UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 378 of 404 NXP Semiconductors U M1 0524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming 21 16 Flash controller registers UM10524 21 16 1 21 16 2 Table 368 Register overview FMC base address 0x4003 C000 Name Access Address Description Reset Reference offset value FLASHCFG R W 0x010 Flash memory access time Table 369 configuration register FMSSTART R W 0x020 Signature start address register 0 Table 370 FMSSTOP R W 0x024 Signature stop address register 0 Table 371 FMSWO R 0x02C Word 0 31 0 Table 372 FMSW1 R 0x030 Word 1 63 32 Table 373 FMSW2 R 0x034 Word 2 95 64 Table 374 FMSW3 R 0x038 Word 3 127 96 Table 375 FMSTAT R OxFEO Signature generation status register 0 Section 21 16 5 FMSTATCLR W OxFE8 Signature generation status clear Section 21 register 16 6 F
363. errupt priority bits are set e The slave mode is enabled by simultaneously setting the I2EN and AA bits in CON and the serial clock frequency for master modes is defined by is defined by loading the SCLH and SCLL registers The master routines must be started in the main program The 12C hardware now begins checking the C bus for its own slave address and General Call If the General Call or the own slave address is detected an interrupt is requested and STAT is loaded with the appropriate state information I2C interrupt service When the 12C interrupt is entered STAT contains a status code which identifies one of the 26 state services to be executed The state service routines Each state routine is part of the 1 C interrupt routine and handles one of the 26 states Adapting state services to an application The state service examples show the typical actions that must be performed in response to the 26 I C state codes If one or more of the four I2 C operating modes are not used the associated state services can be omitted as long as care is taken that the those states can never occur In an application it may be desirable to implement some kind of time out during 1 C operations in order to trap an inoperative bus or a lost service routine 14 11 Software example UM10524 14 11 1 14 11 2 Initialization routine Example to initialize 1 C Interface as a Slave and or Master 1 Load ADR with own Slave Address enabl
364. ers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 32 of 404 NXP Semiconductors UM10524 3 5 38 Chapter 3 LPC1315 16 17 45 46 47 System control block Table 42 Power configuration register PDRUNCFG address 0x4004 8238 bit description Bit Symbol Value 7 SYSPLL_PD 1 0 8 USBPLL_PD 0 1 9 10 USBPAD_PD 0 1 11 12 15 13 31 16 Description System PLL power down Powered down Powered USB PLL power down Powered Powered down Reserved Always write this bit as 0 USB transceiver power down configuration USB transceiver powered USB transceiver powered down suspend mode Reserved This bit must be set to one in Run mode Reserved Reserved Always write these bits as 111 Reserved Reset value 111 Device ID DEVICE_ID This device ID register is a read only register and contains the part ID for each part This register is also read by the ISP IAP commands see Table 348 Table 43 Device ID DEVICE_ID address 0x4004 83F8 bit description Bit Symbol Description Reset 31 0 DEVICEID LPC1345FHN33 0x2801 0541 LPC1345FBD48 0x2801 0541 LPC1346FHN33 0x0801 8542 LPC1346FBD48 0x0801 8542 LPC1347FHN33 0x0802 0543 LPC1347FBD48 0x0802 0543 LPC1347FBD64 0x0802 0543 LPC1315FHN33 0x3A01 0523 LPC1315FBD48 0x3A01 0523 LPC1316FHN33 0x1A01 8524 LPC1316FBD48 0x1A01 8524 LPC1317FHN33 0x1A02 0525 LPC1317FBD4
365. ers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 358 of 404 NXP Semiconductors U M1 0524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming 21 10 Boot process flowchart RESET INITIALIZE no CRP1 2 3 ENABLED Vv ENABLE DEBUG USER CODE VALID WATCHDOG FLAG SET CRP3 NO_ISP ENABLED Vv yes ENTER ISP EXECUTE INTERNAL MODE USER CODE PIOO_1 LOW USB ISP USB ISP ENUMERATE AS MSG PIO0_3 HIGH DEVICE TO PC LPC11345 46 47 only USER CODE VALID RUN AUTO BAUD UART ISP AUTO BAUD SUCCESSFUL RECEIVE CRYSTAL FREQUENCY RUN ISP COMMAND HANDLER 1 For details on handling the crystal frequency see Section 21 14 8 2 For details on available ISP commands based on the CRP settings see Section 21 12 Fig 61 Boot process flowchart UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 359 of 404 NXP Semiconductors U M1 0524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming 21 11 Sector numbers Some IAP and ISP commands operate on sectors and specify sector numbers In addition the LPCLPC1315 16 1 7 45 46 47 support a page erase command The following table shows the correspondence between page numbers
366. ers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 385 of 404 NXP Semiconductors U M1 0524 Chapter 22 LPC1315 16 17 45 46 47 Serial Wire Debugger SWD VDD VTREF LPC13xx Signals from SWD connector n O ISP entry The VTREF pin on the SWD connector enables the debug connector to match the target voltage Fig 64 Connecting the SWD pins to a standard SWD connector 22 6 3 Boundary scan The RESET pin selects between the test TAP controller for JTAG boundary scan RESET LOW and the ARM SWD debug port TAP controller RESET HIGH The ARM SWD debug port is disabled while the LPC1315 16 17 45 46 47 is in reset A LOW on the TRST pin resets the test TAP controller Remark Boundary scan operations should not be started until 250 us after POR The test TAP must be reset after the boundary scan and left in either TLR or RTO state Boundary scan is not affected by Code Read Protection Remark POR BOD reset or a LOW on the TRST pin puts the test TAP controller in the Test Logic Reset state The first TCK clock while RESET HIGH places the test TAP in Run Test Idle mode UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 386 of 404 UM10524 Chapter 23 Supplementary information Rev 1 17 February 2012 User manual 23 1 Abbreviati
367. es EPO OUT Buffer Address Offset 0x00 rl Gab CRR RIR Reserved SETUP bytes Buffer Address Offset 0x04 AJR SJ TR TW R EPO IN Buffer NBytes EPO IN Buffer Address Offset 0x08 R R R JR RIR Reserved Reserved 0x0C A D Ss tm T EP1 OUT Buffer 0 NBytes EP1 OUT Buffer 0 Address Offset 0x10 A D S m MIT EP1 OUT Buffer 1 NBytes EP 1 OUT Buffer 1 Address Offset 0x14 A D S i T EP1 IN Buffer 0 NBytes EP1 IN Buffer 0 Address Offset 0x18 A D s m T EP1 IN Buffer 1 NBytes EP1 IN Buffer 1 Address Offset Ox1C A D S i fF T EP2 OUT Buffer 0 NBytes EP2 OUT Buffer 0 Address Offset 0x20 A D sS m T EP2 OUT Buffer 1 NBytes EP2 OUT Buffer 1 Address Offset 0x24 A D s m T EP2 IN Buffer 0 NBytes EP2 IN Buffer 0 Address Offset 0x28 A D S ta T EP2 IN Buffer 1 NBytes EP2 IN Buffer 1 Address Offset 0x2C A D s m ET EP4 OUT Buffer 0 NBytes EP4 OUT Buffer 0 Address Offset 0x40 A D s m RE T EP4 OUT Buffer 1 NBytes EP4 OUT Buffer 1 Address Offset 0x44 A D sS m T EP4 IN Buffer 0 NBytes EP4 IN Buffer 0 Address Offset 0x48 A D s m T EP4 IN Buffer 1 NBytes EP4 IN Buffer 1 Address Offset Ox4C Fig 12 Endpoint command status list see also Table 165 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 148 of 404 NXP Semiconductors UM10524 Chapter 10 LPC1345 46 47 USB2 0 device controller Table 1
368. es starting from address zero The first 512 bytes can be re mapped to RAM Reinvoke ISP Table 361 Reinvoke ISP Command Input Return Code Result Compare Command code 57 decimal None None Description This command is used to invoke the bootloader in ISP mode It maps boot vectors sets PCLK CCLK configures UART pins RXD and TXD resets counter timer CT32B1 and resets the FDR register see Table 221 This command may be used when a valid user program is present in the internal flash memory and the PIOO_1 pin is not accessible to force the ISP mode ReadUID Table 362 IAP ReadUID command Command Compare Input Command code 58 decimal Return Code Result Description CMD_SUCCESS Result0 The first 32 bit word at the lowest address Result1 The second 32 bit word Result2 The third 32 bit word Result3 The fourth 32 bit word This command is used to read the unique ID All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 376 of 404 NXP Semiconductors U M1 0524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming 21 14 10 Erase page Table 363 IAP Erase page command Command Erase page Input Command code 59 decimal Param0 Start page number Param1 End page number should be greater than or equal to start page Param2 System Clock Frequency CCLKk
369. escription 4 139 10 6 13 USB Endpoint toggle EPTOGGLE 147 10 6 1 USB Device Command Status register 10 7 Functional description 148 DEVCMDSTAT 00000008 140 10 7 1 Endpoint command status list 148 10 6 2 USB Info register INFO 142 10 7 2 Control endpointO 04 151 10 6 3 USB EP Command Status List start address 10 7 3 Generic endpoint single buffering 152 EPLISTSTART 0000000 142 10 7 4 Generic endpoint double buffering 153 10 6 4 USB Data buffer start address 10 7 5 Special CaSCS E E NEEE AE EEEE TEER 153 DATABUFSTART 0 00 143 10 7 5 1 Use of the Active bit 153 10 6 5 Link Power Management register LPM 143 10 7 5 2 Generation of a STALL handshake 153 10 6 6 USB Endpoint skip EPSKIP 144 10 7 5 3 Clear Feature endpoint halt 153 10 6 7 USB Endpoint Buffer in use EPINUSE 144 10 7 5 4 Set configuration 154 10 6 8 USB Endpoint Buffer Configuration 10 7 6 USB wake up EAEE eh des kittie Reeds 154 EPBUFCFG 00c ccc ee eee 144 10 7 6 1 Waking up from Deep sleep and Power down 10 6 9 USB interrupt status register INTSTAT 145 modes on USB activity 154 10 6 10 USB interrupt enable register INTEN 146 10 7 6 2 Remote wake up 154 Chapter 11 LPC1345 46 47 USB on chip dr
370. escription void void USBD_CORE_API StatusInStage USBD_HANDLE_T hUsb Function to set EPO state machine in status_in state This function is called by USB stack and the application layer to set the EPO state machine in status_in state This function will send zero length IN packet on EPO to host indicating positive status Remark This interface is provided to users to invoke this function in other scenarios which are not handle by current stack In most user applications this function is not called directly Also this function can be used by users who are selectively modifying the USB device stack s standard handlers through callback interface exposed by the stack Parameters 1 hUsb Handle to the USB device stack Returns Nothing StatusOutStage void void USBD_CORE_API StatusOutStage USBD_HANDLE_T hUsb Function to set EPO state machine in status_out state This function is called by USB stack and the application layer to set the EPO state machine in status_out state This function will read the zero length OUT packet received from USB host on EPO Remark This interface is provided to users to invoke this function in other scenarios which are not handle by current stack In most user applications this function is not called directly Also this function can be used by users who are selectively modifying the USB device stack s standard handlers through callback interface exposed by the stack Parameters 1 hUsb Handle to the
371. escription WakeUpCfg void void USBD_HW_API WakeUpCfg USBD_HANDLE_T hUsb uint32_t cfg Function to configure USB device controller to walk up host on remote events This function is called by application layer to configure the USB device controller to wake up on remote events It is recommended to call this function from users s USB_WakeUpCfg callback routine registered with stack Remark User s USB_WakeUpCfg is registered with stack by setting the USB_WakeUpCfg member of USBD_API_INIT_PARAM_T structure before calling pUsbApi gt hw gt Init routine Certain USB device controllers needed to keep some clocks always on to generate resume signaling through pUsbApi gt hw gt WakeUp This hook is provided to support such controllers In most controllers cases this is an empty routine Parameters 1 hUsb Handle to the USB device stack 2 cfg When 1 Configure controller to wake on remote events or 0 Configure controller not to wake on remote events Returns Nothing SetAddress void void USBD_HW_API SetAddress USBD_HANDLE_T hUsb uint32_t adr Function to set USB address assigned by host in device controller hardware This function is called automatically when USB_REQUEST_SET_ADDRESS request is received by the stack from USB host This interface is provided to users to invoke this function in other scenarios which are not handle by current stack In most user applications this function is not called directly Also this function can b
372. et and the status code in the STAT register is 0x08 This status code is used to vector to a state service routine which will load the slave address and Write bit to the DAT register and then clear the SI bit SI is cleared by writing a 1 to the SIC bit in the CONCLR register When the slave address and R W bit have been transmitted and an acknowledgment bit has been received the SI bit is set again and the possible status codes now are 0x18 0x20 or 0x38 for the master mode or 0x68 0x78 or OxBO if the slave mode was enabled by setting AA to 1 The appropriate actions to be taken for each of these status codes are shown in Table 261 to Table 266 n bytes data transmitted A Acknowledge SDA low A Not acknowledge SDA high S START condition P STOP condition E from Master to Slave D from Slave to Master Fig 32 Format in the Master Transmitter mode Master Receiver mode In the master receiver mode data is received from a slave transmitter The transfer is initiated in the same way as in the master transmitter mode When the START condition has been transmitted the interrupt service routine must load the slave address and the data direction bit to the 1 C Data register DAT and then clear the SI bit In this case the data direction bit R W should be 1 to indicate a read When the slave address and data direction bit have been transmitted and an acknowledge bit has been received the SI bit is
373. event If WARNINT is 0 the interrupt will occur at the same time as the watchdog event All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 332 of 404 NXP Semiconductors U M1 0524 Chapter 17 LPC1315 16 17 45 46 47 Windowed Watchdog Timer Table 307 Watchdog Timer Warning Interrupt register WARNINT 0x4000 4014 bit description Bit Symbol Description Reset Value 9 0 WARNINT Watchdog warning interrupt compare value 0 31 10 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined 17 8 7 Watchdog Timer Window register The WDWINDOW register determines the highest WDTV value allowed when a watchdog feed is performed If a feed sequence occurs when WDTV is greater than the value in WDWINDOW a watchdog event will occur WDWINDOW resets to the maximum possible WDTV value so windowing is not in effect Table 308 Watchdog Timer Window register WINDOW 0x4000 4018 bit description Bit Symbol Description Reset Value 23 0 WINDOW Watchdog window value OxFF FFFF 31 24 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined 17 9 Watchdog timing examples The following figures illustrate several aspects of Watchdog Timer operation were PVP fo Eoo 125a 1259 125
374. ext higher bits pins set to one are scanned if applicable Repeated conversions can be terminated by clearing this bit but the conversion in progress when this bit is cleared will be completed Important START bits must be 000 when BURST 1 or conversions will not start Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 347 of 404 NXP Semiconductors U M1 0524 Chapter 20 LPC1315 16 17 45 46 47 ADC Table 324 A D Control Register CR address 0x4001 C000 bit description Bit Symbol Value Description Reset Value 22 LPWRMODE Low power mode 0 0 Disable the low power ADC mode The analog circuitry remains activated when no conversions are requested 1 Enable the low power ADC mode The analog circuitry is automatically powered down when no conversions are taking place When any hardware or software triggering event is detected the analog circuitry is enabled After the required start up time the requested conversion will be launched Once the conversion completes the analog circuitry will again be powered down provided no further conversions are pending Remark This mode will NOT p
375. fers See Zero Copy Data Transfer model for more details on zero copy concept lengthAmount of data to be sent back to host Parameters 1 hCdc Handle to CDC function driver 2 pSetup Pointer to setup packet received from host 3 pBuffer Pointer to a pointer of data buffer containing request data Pointer to pointer is used to implement zero copy buffers See Zero Copy Data Transfer model for more details on zero copy concept 4 length Amount of data to be sent back to host Returns The call back should returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_ xxx For other error conditions All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 171 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 193 USBD_CDC_INIT_PARAM class structure Member Description CIC_SetRequest ErrorCode_t ErrorCode_t USBD_CDC_INIT_PARAM CIC_SetRequest USBD_HANDLE_T hCdc USB_SETUP_PACKET pSetup uint8_t pBuffer uintl6_t length USBD_HANDLE_T hCdc USB_SETUP_PACKET pSetup uint8_t pBuffer uintl6_t length Communication Interface Class specific set request callback function This function is provided by the application software This
376. figure port pins as inputs or outputs The GPIO port registers are listed in Table 114 and Section 9 5 3 Note In all GPIO registers bits that are not shown are reserved Table 111 Register overview GPIO pin interrupts base address 0x4004 C000 Name Access Address Description Reset Reference offset value ISEL R W 0x000 Pin Interrupt Mode register 0 Table 115 IENR R W 0x004 Pin Interrupt Enable Rising register 0 Table 116 SIENR WO 0x008 Set Pin Interrupt Enable Rising register NA Table 117 CIENR WO 0x00C Clear Pin Interrupt Enable Rising register NA Table 118 IENF R W 0x010 Pin Interrupt Enable Falling Edge Active 0 Table 119 Level register SIENF WO 0x014 Set Pin Interrupt Enable Falling Edge NA Table 120 Active Level register CIENF WO 0x018 Clear Pin Interrupt Enable Falling Edge NA Table 121 Active Level address RISE R W 0x01C Pin Interrupt Rising Edge register Table 122 FALL R W 0x020 Pin Interrupt Falling Edge register Table 123 IST R W 0x024 Pin Interrupt Status register Table 124 Table 112 Register overview GPIO GROUPO interrupt base address 0x4005 C000 Name Access Address Description Reset value Reference offset CTRL R W 0x000 GPIO grouped interrupt control 0 Table 125 register PORT_POLO R W 0x020 GPIO grouped interrupt port 0 OxFFFF Table 126 polarity register FFFF PORT_POL1 R W 0x024 GPIO grouped interrupt port 1 OxFFFF Table 127 polarity register FFFF PORT_ENAO R W 0x040 GPIO gro
377. fter the LSB of the received data from the current frame Each of the received values is transferred from the receive shifter on the falling edge SK after the LSB of the frame has been latched into the SSP SPI Setup and hold time requirements on CS with respect to SK in Microwire mode In the Microwire mode the SSP SPI slave samples the first bit of receive data on the rising edge of SK after CS has gone LOW Masters that drive a free running SK must ensure that the CS signal has sufficient setup and hold margins with respect to the rising edge of SK Figure 30 illustrates these setup and hold time requirements With respect to the SK rising edge on which the first bit of receive data is to be sampled by the SSP SPI slave CS must have a setup of at least two times the period of SK on which the SSP SPI operates With respect to the SK rising edge previous to this edge CS must have a hold of at least one SK period terur tsk t SK HOLD SK CS Fig 30 Microwire frame format setup and hold details All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 251 of 404 UM10524 Chapter 14 LPC1315 16 17 45 46 47 12C bus controller Rev 1 17 February 2012 User manual 14 1 How to read this chapter The C bus block is identical for all LPC1315 16 17 45 46 47 parts 14 2 Basic configuration The 2
378. ftware 2 2 3 SRAM The LPC1315 16 17 45 46 47 contain a total of 8 kB 10 kB or 12 kB on chip static RAM memory The USB SRAM block is available on parts LPC134x only SRAM block SRAM1 is available on parts LPC1347 17 only The SRAM1 and USB SRAM clocks are turned off by default Enable the clocks in the SYSHBCLKCTRL register Table 19 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 9 of 404 NXP Semiconductors U M1 0524 Chapter 2 LPC1315 16 17 45 46 47 Memory mapping LPC1315 16 17 45 46 47 OxFFFF FFFF s reserved 4 GB 0xE010 0000 rivate peripheral bus reserved APB peripherals 0x4008 0000 0x5000 4000 26 31 reserved 0x4006 8000 i RI Ti 0x5000 0000 25i S 0x4006 4000 GPIO GROUP1 i f 24 GPIO GROUP1 interrupt 0x4006 0000 reserved z 23 GPIO GROUPO interrupt 0x4005 C000 0x4008 4000 SSP1 0x4008 0000 20 21 reserved APBperipherals oxaao0 0000 A Tob APB peripherals 0x4000 0000 191 GPIO pin interrupt e reserved 0x4004 C000 J7 0x2000 4800 18 system control 0x4004 8000 2 kB USB SRAM LPC134x Gide aban ie OCON dooa reserved i SSPO 0 5 GB 2kB SRAM1 LPC1317 47 0x2000 0000 a 0x4003 C000 t PMU 0x4003 8000 reserved M 10 13 reserved 0x1FFF 4000 16 kB boot ROM 0x4002 8000 0x1FFF 0000 9 reserved 0x4002 4000 8 reserved 0x4002 0000 reserved 7 ADC
379. ftware Table 312 System Timer Current value register SYST_CVR 0xE000 E018 bit description Bit Symbol Description Reset value 23 0 CURRENT Reading this register returns the current value of the System Tick 0 counter Writing any value clears the System Tick counter and the COUNTFLAG bit in STCTRL 31 24 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined System Timer Calibration value register SYST_CALIB 0xE000 E01C The value of the SYST_CALIB register is driven by the value of the SYSTCKCAL register in the system configuration block see Table 24 Table 313 System Timer Calibration value register SYST_CALIB 0xE000 E01C bit description Bit Symbol Value Description Reset value 23 0 TENMS See Table 367 0x4 29 24 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined 30 SKEW See Table 367 0 31 NOREF See Table 367 0 18 6 Functional description UM10524 The SysTick timer is a 24 bit timer that counts down to zero and generates an interrupt The intent is to provide a fixed 10 millisecond time interval between interrupts The SysTick timer is clocked from the CPU clock the system clock see Figure 2 or from the reference clock which is fixed to half the frequency of the CPU clock In order to generate recurring interrupts at a specific interval the SYST_RVR register
380. function gets called when host sends a CIC management element requests The setup packet data hCdcHandle to CDC function driver pSetupPointer to setup packet received from host pBufferPointer to a pointer of data buffer containing request data Pointer to pointer is used to implement zero copy buffers See Zero Copy Data Transfer model for more details on zero copy concept lengthAmount of data copied to destination buffer Parameters 1 hCdc Handle to CDC function driver 2 pSetup Pointer to setup packet received from host 3 pBuffer Pointer to a pointer of data buffer containing request data Pointer to pointer is used to implement zero copy buffers See Zero Copy Data Transfer model for more details on zero copy concept 4 length Amount of data copied to destination buffer Returns The call back should returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_ xxx For other error conditions CDC_BulkIN_Hdlr ErrorCode_t ErrorCode_t USBD_CDC_INIT_PARAM CDC_BulkIN_Hdlr USBD_HANDLE_T hUsb void data uint32_t event USBD_HANDLE_T hUsb void data uint32_t event Communication Device Class specific BULK IN endpoint handler The application software should provide the BULK IN endpoint handler Applications should transfer data depending on the communication protocol type set in
381. gister Table 19 bit 19 The group interrupt wake up feature is enabled in the STARTERP1 register Table 39 e For the GPIO port registers enable the clock to the GPIO port register in the SYSAHBCLKCTRL register Table 19 bit 6 9 3 Features 9 3 1 GPIO pin interrupt features Up to 8 pins can be selected from all GPIO pins as edge or level sensitive interrupt requests Each request creates a separate interrupt in the NVIC e Edge sensitive interrupt pins can interrupt on rising or falling edges or both e Level sensitive interrupt pins can be HIGH or LOW active 9 3 2 GPIO group interrupt features e The inputs from any number of GPIO pins can be enabled to contribute to a combined group interrupt e The polarity of each input enabled for the group interrupt can be configured HIGH or LOW UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 118 of 404 NXP Semiconductors U M1 0524 9 3 3 Chapter 9 LPC1315 16 17 45 46 47 GPIO e Enabled interrupts can be logically combined through an OR or AND operation e Two group interrupts are supported to reflect two distinct interrupt patterns e The GPIO group interrupts can wake up the part from sleep deep sleep or power down modes GPIO port features e GPIO pins can be configured as input or output by software e All GPIO pins default to inputs with interru
382. grows downwards 21 9 USB communication protocol UM10524 The LPC1345 46 47 is enumerated as a Mass Storage Class MSC device to a PC or another embedded system In order to connect via the USB interface the part must use the external crystal at a frequency of 12 MHz The MSC device presents an easy integration with the PC s Windows operating system The flash memory space is represented as a drive in the host file system The entire available user flash is mapped to a file of the size of the LPC 1345 46 47 flash in the host s folder with the default name firmware bin The firmware bin file can be deleted and a new file can be copied into the directory thereby updating the user code in flash Note that the filename of the new flash image file is not important After a reset or a power cycle the new file is visible in the host s file system under it s default name firmware bin Remark USB ISP commands are supported for the Windows operating system only The code read protection CRP see Table 331 level determines how the flash is reprogrammed If CRP1 or CRP2 is enabled the user flash is erased when the file is deleted If CRP1 is enabled or no CRP is selected the user flash is erased and reprogrammed when the new file is copied However only the area occupied by the new file is erased and reprogrammed Remark The only Windows commands supported for the LPC 1345 46 47 flash image folder are copy and dele
383. guration The system tick timer is configured using the following registers 1 Pins The system tick timer uses no external pins 2 Power The system tick timer is enabled through the SysTick control register Table 364 The system tick timer clock is fixed to half the frequency of the system clock 3 Enable the clock source for the SysTick timer in the SYST_CSR register Table 364 18 3 Features e Simple 24 bit timer e Uses dedicated exception vector e Clocked internally by the system clock or the SYSTICKCLK 18 4 General description The block diagram of the SysTick timer is shown below in the Figure 59 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 335 of 404 NXP Semiconductors U M1 0524 Chapter 18 LPC1315 16 17 45 46 47 System tick timer STCALIB STRELOAD load data STCURR private system clook 24 bit down counter popora us Systick clock clock under count load flow enable E STCTRL COUNTFLAG TICKINT System Tick interrupt Fig 59 System tick timer block diagram The SysTick timer is an integral part of the Cortex M3 The SysTick timer is intended to generate a fixed 10 millisecond interrupt for use by an operating system or other system management software Since the SysTick timer is a part of the Cortex M3 it facilitates porting of software by p
384. h Register provides both control and status of the external match pins CAP32Bn_MAT 3 0 If the match outputs are configured as PWM output the function of the external match registers is determined by the PWM rules Section 16 7 13 Rules for single edge controlled PWM outputs on page 321 Table 296 External Match Register EMR address 0x4001 403C CT32B0 and 0x4001 803C CT32B1 bit description Bit 5 4 7 6 UM10524 Symbol EMO EM1 EM2 EM3 EMCO EMC1 Value Description Reset 0x0 0x1 0x2 0x3 0x0 0x1 0x2 value External Match 0 This bit reflects the state of output CT32Bn_MATO whether or not this 0 output is connected to its pin When a match occurs between the TC and MRO this bit can either toggle go LOW go HIGH or do nothing Bits EMR 5 4 control the functionality of this output This bit is driven to the CT32BO_MAT0 CT32B1_MATO pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH External Match 1 This bit reflects the state of output CT32Bn_MAT1 whether or not this 0 output is connected to its pin When a match occurs between the TC and MR this bit can either toggle go LOW go HIGH or do nothing Bits EMR 7 6 control the functionality of this output This bit is driven to the CT32BO_MAT1 CT32B1_MAT 1 pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH External Match 2 This bit reflects the state of output
385. hapter 335 18 5 4 System Timer Calibration value register 18 2 Basic configuration 335 SYST_CALIB OxE000 E01C 338 18 3 Features 00 eee eee eee ees 335 18 6 Functional description 338 18 4 General description 335 18 7 Example timer calculations 339 18 5 Register description 336 System clock 72 MHz 339 18 5 1 System Timer Control and status register 337 System tick timer clock 24 MHz 339 18 5 2 System Timer Reload value register 337 System clock 12 MHz 5 339 18 5 3 System Timer Current value register 338 Chapter 19 LPC1315 16 17 45 46 47 Repetitive Interrupt Timer RI timer 19 1 How to read this chapter 340 19 5 3 RI Control register 0 342 19 2 Basic configuration 5 340 19 5 4 RI Counter LSB register 343 19 3 Features u ceee 340 nee PAF P Bea register s eion a i D as register 194 senera AEScHpUON ainsi ay 340 495 7 RI Counter MSBregister 343 19 3 Register description eee ee 341 19 6 RI timer operation 344 19 5 1 RI Compare Value LSB register 342 19 5 2 RI Mask LSB register a an aanu 342 Chapter 20 LPC1315 16 17 45 46 47 ADC 20 1 How to read this chapter 345 20 5 4 A D Data Registers DRO to DR7
386. hapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming The address range for generating a signature must be aligned on flash word boundaries i e 128 bit boundaries Once started signature generation completes independently While signature generation is in progress the flash memory cannot be accessed for other purposes and an attempted read will cause a wait state to be asserted until signature generation is complete Code outside of the flash e g internal RAM can be executed during signature generation This can include interrupt services if the interrupt vector table is re mapped to memory other than the flash memory The code that initiates signature generation should also be placed outside of the flash memory 21 16 3 Signature generation address and control registers These registers control automatic signature generation A signature can be generated for any part of the flash memory contents The address range to be used for generation is defined by writing the start address to the signature start address register FMSSTART and the stop address to the signature stop address register FMSSTOP The start and stop addresses must be aligned to 128 bit boundaries and can be derived by dividing the byte address by 16 Signature generation is started by setting the SIG_START bit in the FMSSTOP register Setting the SIG_START bit is typically combined with the signature stop address in a single write Table 370 and Table 3
387. has been Read data byte or 0 0 0 0 Data byte will be received NOT ACK bit received ACK has will be returned been returned Read data byte 0 0 0 1 Data byte will be received ACK bit will be returned 0x58 Data byte has been Read data byte or 1 0 0 X Repeated START condition will be received NOT ACK transmitted has been returned Read data byte or 0 1 0 xX STOP condition will be transmitted STO flag will be reset Read data byte 1 1 0 X STOP condition followed by a START condition will be transmitted STO flag will be reset UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 275 of 404 NXP Semiconductors UM10524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller successful transmission to a Slave transmitter next transfer started with a Repeated Start condition Not Acknowledge I I l received after the gt 1A Iwi Slave address l l I to Master transmit mode entry MT arbitration lost in i j Slave address or I AORA other Master 1A other Master Acknowledge bit continues continues arbitration lost gt and addressed gt other Master as Slave continues to corresponding states in Slave mode from Master to Slave from Slave to Master I DATA A any number of data bytes and their associated i Acknowledge bits this number contained in I2ST
388. hasn t seen any activity on its upstream port for more than 3 milliseconds It is reset to 0 on any activity When the device is suspended Suspend bit DSUS 1 and the software writes a 0 to it the device will generate a remote wake up This will only happen when the device is connected Connect bit 1 When the device is not connected or not suspended a writing a 0 has no effect Writing a 1 never has an effect 18 Reserved 0 RO 19 LPM_SUS Device status LPM Suspend 0 RW This bit represents the current LPM suspend state It is set to 1 by HW when the device has acknowledged the LPM request from the USB host and the Token Retry Time of 10us has elapsed When the device is in the LPM suspended state LPM suspend bit 1 and the software writes a zero to this bit the device will generate a remote walk up Software can only write a zero to this bit when the LPM_REWP bit is set to 1 HW resets this bit when it receives a host initiated resume HW only updates the LPM_SUS bit when the LPM_SUPP bit is equal to one 20 LPM_REWP LPM Remote Wake up Enabled by USB host 0 RO HW sets this bit to one when the bRemoteWake bit in the LPM extended token is set to 1 HW will reset this bit to O when it receives the host initiated LPM resume when a remote wake up is sent by the device or when a USB bus reset is received Software can use this bit to check if the remote wake up feature is enabled by the host for the LPM transaction 23 21 Re
389. hdog mode register MOD 0x4000 4000 bit description Bit Symbol Value Description Reset value 0 WDEN Watchdog enable bit Once this bit has been written with 0 a 1 it cannot be rewritten with a 0 0 The watchdog timer is stopped The watchdog timer is running 1 WDRESET Watchdog reset enable bit Once this bit has been 0 written with a 1 it cannot be rewritten with a 0 0 A watchdog timeout will not cause a chip reset A watchdog timeout will cause a chip reset 2 WDTOF Watchdog time out flag Set when the watchdog timer 0 only times out by a feed error or by events associated with after WDPROTECT Cleared by software Causes a chip external reset if WORESET 1 reset 3 WDINT Warning interrupt flag Set when the timer reaches the 0 value in WOWARNINT Cleared by software UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 329 of 404 NXP Semiconductors U M1 0524 Chapter 17 LPC1315 16 17 45 46 47 Windowed Watchdog Timer Table 301 Watchdog mode register MOD 0x4000 4000 bit description Bit Symbol Value Description Reset value 4 WDPROTECT Watchdog update mode This bit can be set once by 0 software and is only cleared by a reset 0 The watchdog time out value TC can be changed at any time 1 The watchdog time out value TC can be changed only after the counter is below the value of WOWARNINT
390. he state of two pins and read or write words to sense or set the state of four pins Table 130 GPIO port 0 byte pin registers BO to B31 addresses 0x5000 0000 to 0x5000 001F bit description Bit Symbol Description Reset Access value 0 PBYTE Read state of the pin PO_n regardless of direction masking ext R W or alternate function except that pins configured as analog I O always read as 0 Write loads the pin s output bit 7 1 Reserved 0 on read ignored on write 0 Table 131 GPIO port 1 byte pin registers B32 to B63 addresses 0x5000 0020 to 0x5000 002F bit description Bit Symbol Description Reset Access value 0 PBYTE Read state of the pin P1_n regardless of direction masking ext R W or alternate function except that pins configured as analog I O always read as 0 Write loads the pin s output bit 7 1 Reserved 0 on read ignored on write 0 GPIO port word pin registers Each GPIO pin has a word register in this address range Any byte halfword or word read in this range will be all zeros if the pin is low or all ones if the pin is high regardless of direction masking or alternate function except that pins configured as analog I O always read as zeros Any write will clear the pin s output bit if the value written is all zeros else it will set the pin s output bit Table 132 GPIO port 0 word pin registers W0 to W31 addresses 0x5000 1000 to 0x5000 107C bit description Bit
391. he data received on the requested endpoint hUsbHandle to the USB device stack EPNumEndpoint number as per USB specification ie An EP1_IN is represented by 0x81 number pDataPointer to the data buffer where data is to be copied Parameters 1 hUsb Handle to the USB device stack 2 EPNum Endpoint number as per USB specification ie An EP1_IN is represented by 0x81 number 3 pData Pointer to the data buffer where data is to be copied Returns Returns the number of bytes copied to the buffer UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 195 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 199 USBD_HW_API class structure Member Description ReadReqEP uint32_t uint32_t USBD_HW_API ReadRegEP USBD_HANDLE_T hUsb uint32_t EPNum uint8_t pData uint32_t len Function to queue read request on the specified endpoint This function is called by USB stack and the application layer to queue a read request on the specified endpoint hUsbHandle to the USB device stack EPNumEndpoint number as per USB specification ie An EP1_IN is represented by 0x81 number pDataPointer to the data buffer where data is to be copied This buffer address should be accessible by USB DMA master lenLength of the buffer passed Parameters 1 hUsb Handle to the USB device stack 2 EPNum End
392. he value 0x3 which selects the clock from the system tick clock divider use DIV 3 as the clock source and enables the SysTick timer and the SysTick timer interrupt RELOAD system tick timer clock frequency x 10 ms 1 24 MHz x 10 ms 1 240000 1 239999 0x0003A97F System clock 12 MHz Program the CTRL register with the value 0x7 which selects the system clock as the clock source and enables the SysTick timer and the SysTick timer interrupt In this case the system clock is derived from the IRC clock RELOAD system clock frequency x 10 ms 1 12 MHz x 10 ms 1 120000 1 119999 0x0001 D4BF UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 339 of 404 UM10524 Chapter 19 LPC1315 16 17 45 46 47 Repetitive Interrupt Timer RI timer Rev 1 17 February 2012 User manual 19 1 How to read this chapter The RI timer is available on all LPC1315 16 17 45 46 47 parts 19 2 Basic configuration The RI timer is configured through the following registers e Power to the register interface RI timer clock In the SYSAHBCLKCTRL register set bit 25 in Table 19 19 3 Features e 48 bit counter running from the main clock Counter can be free running or be reset by a generated interrupt e 48 bit compare value e 48 bit compare mask An interrupt is generated when the counter va
393. his bit will be set if the corresponding Active bit is cleared by HW This is done in case the programmed NBytes transitions to zero or the skip bit is set by software If the IntOnNAK_AO is set this bit will also be set when a NAK is transmitted for the EP2 OUT direction Software can clear this bit by writing a one to it Interrupt status register bit for the EP2 IN direction This bit will be set if the corresponding Active bit is cleared by HW This is done in case the programmed NBytes transitions to zero or the skip bit is set by software If the IntOnNAK_AI is set this bit will also be set when a NAK is transmitted for the EP2 IN direction Software can clear this bit by writing a one to it Interrupt status register bit for the EP3 OUT direction This bit will be set if the corresponding Active bit is cleared by HW This is done in case the programmed NBytes transitions to zero or the skip bit is set by software If the IntOnNAK_AO is set this bit will also be set when a NAK is transmitted for the EP3 OUT direction Software can clear this bit by writing a one to it All information provided in this document is subject to legal disclaimers Reset Access value 0 R WC 0 R WC 0 R WC 0 R WC 0 R WC 0 R WC NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 145 of 404 NXP Semiconductors U M1 0524 Chapter 10 LPC 1345 46 47 USB2 0 device controller Table 160 USB
394. host send set clear feature request The stack handles this request for USB_FEATURE_REMOTE_WAKEUP USB_FEATURE_TEST_MODE and USB_FEATURE_ENDPOINT_STALL features only On receiving feature request from host the stack handle the request appropriately and then calls this callback function Remark This event is called from USB_ISR context and hence is time critical Having delays in this callback will prevent the device from enumerating correctly or operate properly uint32_t uint32_t USBD_API_INIT_PARAM virt_to_phys void vaddr void vaddr Reserved parameter for future use should be set to zero void void USBD_API_INIT_PARAM cache_flush uint32_t start_adr uint32_t end_adr uint32_t start_adr uint32_t end_adr Reserved parameter for future use should be set to zero 11 5 27 USBD_CDC_API CDC class API functions structure This module exposes functions which interact directly with USB device controller hardware Table 192 USBD_CDC_API class structure Member Description GetMemSize uint32_t uint32_t USBD_CDC_API GetMemSize USBD_CDC_INIT_PARAM_T param Function to determine the memory required by the CDC function driver module This function is called by application layer before calling pUsbApi gt CDC gt Init to allocate memory used by CDC function driver module The application should allocate the memory which is accessible by USB controller DMA controller Remark Some memory areas are not a
395. hronous slave 0 mode 0 The input clock is synchronized prior to being used in clock edge detection logic 1 The input clock is not synchronized prior to being used in clock edge detection logic This allows for a high er input clock rate at the expense of potential metastability 4 CSCEN Continuous master clock enable used only when 0 CSRC is 1 0 SCLK cycles only when characters are being sent on TxD 1 SCLK runs continuously characters can be received on RxD independently from transmission on TxD 5 SSDIS Start stop bits 0 0 Send start and stop bits as in other modes 1 Do not send start stop bits UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 229 of 404 NXP Semiconductors U M1 0524 UM10524 Chapter 12 LPC1315 16 17 45 46 47 USART Table 230 USART Synchronous mode control register SYNCCTRL address 0x4000 8058 bit description Bit Symbol Value Description Reset value 6 CCCLR Continuous clock clear 0 0 CSCEN is under software control 1 Hardware clears CSCEN after each character is received 31 7 Reserved The value read from a reserved bit is not NA defined After reset synchronous mode is disabled Synchronous mode is enabled by setting the SYNC bit When SYNC is 1 the USART operates as follows 1 The CSRC bit controls whether the USART sends master mode or receives slave mode a seria
396. ht create problems due to difference in the C compiler implementation from different vendors The suggested parameter passing scheme reduces such risk The flash memory is not accessible during a write or erase operation IAP commands which results in a flash write erase operation use 32 bytes of space in the top portion of the on chip RAM for execution The user program should not be use this space if IAP flash programming is permitted in the application Table 353 IAP Command Summary IAP Command Command Code Described in Prepare sector s for write operation 50 decimal Table 354 Copy RAM to flash 51 decimal Table 355 Erase sector s 52 decimal Table 356 Blank check sector s 53 decimal Table 357 Read Part ID 54 decimal Table 358 Read Boot code version 55 decimal Table 359 Compare 56 decimal Table 360 Reinvoke ISP 57 decimal Table 361 Read UID 58 decimal Table 362 Erase page 59 decimal Table 363 EEPROM Write 61 decimal Table 364 EEPROM Read 62 decimal Table 365 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 372 of 404 NXP Semiconductors U M1 0524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming COMMAND CODE PARAMETER 1 PARAMETER 2 PARAMETER n command parameter table ARM REGISTER r0 ARM REGISTER r1 STATUS CODE RESULT 1 RESULT 2 RESU
397. hts reserved User manual Rev 1 17 February 2012 362 of 404 NXP Semiconductors UM10524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming 21 13 ISP commands UM10524 21 13 1 The following commands are accepted by the ISP command handler Detailed status codes are supported for each command The command handler sends the return code INVALID COMMAND when an undefined command is received Commands and return codes are in ASCII format CMD_SUCCESS is sent by ISP command handler only when received ISP command has been completely executed and the new ISP command can be given by the host Exceptions from this rule are Set Baud Rate Write to RAM Read Memory and Go commands Table 336 ISP command summary ISP Command Usage Described in Unlock U lt Unlock Code gt Table 337 Set Baud Rate B lt Baud Rate gt lt stop bit gt Table 338 Echo A lt setting gt Table 339 Write to RAM W lt start address gt lt number of bytes gt Table 340 Read Memory R lt address gt lt number of bytes gt Table 341 Prepare sector s for P lt start sector number gt lt end sector number gt Table 342 write operation Copy RAM to flash C lt Flash address gt lt RAM address gt lt number of bytes gt Table 343 Go G lt address gt lt Mode gt Table 344 Erase sector s E lt start sector number gt lt end sector number gt Table 345 Blank check sector s lt start sector number gt lt end sector n
398. ic 1 interrupt wake up enable register address 0x4004 8020 bit description 16 STARTERP1 address 0x4004 8214 bit Table 13 Watchdog oscillator control WDTOSCCTRL description 00000 eee eee 30 address 0x4004 8024 bit description 17 Table 40 Deep sleep mode configuration register Table 14 System reset status register SYSRSTSTAT PDSLEEPCFG address 0x4004 8230 bit address 0x4004 8030 bit description 18 description 0 2000 eee ee eee 30 Table 15 System PLL clock source select Table 41 Wake up configuration PDAWAKECFG address SYSPLLCLKSEL address 0x4004 8040 bit 0x4004 8234 bit description 31 description 20 20 e eee eee 19 Table 42 Power configuration register PDRUNCFG Table 16 USB PLL clock source select USBPLLCLKSEL address 0x4004 8238 bit description 32 address 0x4004 8048 bit description 19 Table 43 Device ID DEVICE_ID address 0x4004 83F8 bit Table 17 Main clock source select MAINCLKSEL address description 0 0 c cee eee eee 33 0x4004 8070 bit description 20 Table 44 Peripheral configuration in reduced power Table 18 System clock divider SYSAHBCLKDIV address MOES i pede deeded eh Seer es Rew bars 36 0x4004 8078 bit description 20 Table 45 PLL frequency parameters 44 Table 19 System clock control SYSAHBCLKCTRL Table 46 PLL configuration examples 44 address
399. ice receives this request the endpoint must be unstalled and the toggle bit for that endpoint must be reset back to zero In order to do that the software must program the following items for the endpoint that is indicated If the endpoint is used in single buffer mode program the following e Set STALL bit S to 0 e Set toggle reset bit TR to 1 and set toggle value bit TV to 0 If the endpoint is used in double buffer mode program the following All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 153 of 404 NXP Semiconductors U M1 0524 UM10524 10 7 5 4 10 7 6 10 7 6 1 10 7 6 2 Chapter 10 LPC 1345 46 47 USB2 0 device controller e Set the STALL bit of both buffer 0 and buffer 1 to 0 e Read the buffer in use bit for this endpoint Set the toggle reset bit TR to 1 and set the toggle value bit TV to O for the buffer indicated by the buffer in use bit Set configuration When a SetConfiguration request is received with a configuration value different from zero the device software must enable all endpoints that will be used in this configuration and reset all the toggle values To do so it must generate the procedure explained in Section 10 7 5 3 for every endpoint that will be used in this configuration For all endpoints that are not used in this configuration it must set the Disabled bit D
400. ided in this document is subject to legal disclaimers Chapter 23 Supplementary information clear register CIENF address 0x4004 C018 bit description 0 2000 2 eee eee eee 124 Table 122 Pin interrupt rising edge register RISE address 0x4004 C010 bit description 125 Table 123 Pin interrupt falling edge register FALL address 0x4004 C020 bit description 125 Table 124 Pin interrupt status register IST address 0x4004 C024 bit description 126 Table 125 GPIO grouped interrupt control register CTRL addresses 0x4005 C000 GROUPO INT and 0x4006 0000 GROUP1 INT bit description 126 Table 126 GPIO grouped interrupt port 0 polarity registers PORT_POLO addresses 0x4005 C020 GROUPO INT and 0x4006 0020 GROUP1 INT bit description 0 0005 127 Table 127 GPIO grouped interrupt port 1 polarity registers PORT_POL1 addresses 0x4005 C024 GROUPO INT and 0x4006 0024 GROUP1 INT bit description 0005 127 Table 128 GPIO grouped interrupt port 0 enable registers PORT_ENAO addresses 0x4005 C040 GROUPO INT and 0x4006 0040 GROUP1 INT bit description 0 0005 127 Table 129 GPIO grouped interrupt port 1 enable registers PORT_ENA1 addresses 0x4005 C044 GROUPO INT and 0x4006 0044 GROUP1 INT bit description 0 000 127 Table 130 GPIO port 0 byte pin registers BO to B31 addresses 0x5000 0000 to 0x500
401. ider register SYSTICKCLKDIV This register configures the SYSTICK peripheral clock The SYSTICK timer clock can be shut down by setting the DIV field to zero Table 24 SYSTICK clock divider SYSTICKCLKDIV address 0x4004 80B0 bit description Bit Symbol Description Reset value 7 0 DIV SYSTICK clock divider values 0x00 0 Disable SYSTICK timer clock 1 Divide by 1 to 255 Divide by 255 31 8 Reserved 0x00 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 23 of 404 NXP Semiconductors U M1 0524 UM10524 3 5 20 3 5 21 3 5 22 Chapter 3 LPC1315 16 17 45 46 47 System control block USB clock source select register USBCLKSEL This register selects the clock source for the USB usb_clk The clock source can be either the USB PLL output or the main clock and the clock can be further divided by the USBCLKDIV register see Table 26 to obtain a 48 MHz clock Remark When switching clock sources both clocks must be running before the clock source is updated The default clock source for the USB controller is the USB PLL output For switching the clock source to the main clock ensure that the system PLL and the USB PLL are running to make both clock sources available for switching The main clock must be set to 48 MHz and configured with the main PLL and the system oscillator After the switch the USB
402. ificant bit determines whether a slave responds to the General Call address Data buffer register The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits 8 bits of data plus ACK or NACK has been received on the bus I2C Slave address mask register 0 This mask register is associated with IZADRO to determine an address match The mask register has no effect when comparing to the General Call address 0000000 I2C Slave address mask register 1 This mask register is associated with IZADRO to determine an address match The mask register has no effect when comparing to the General Call address 0000000 I2C Slave address mask register 2 This mask register is associated with IZADRO to determine an address match The mask register has no effect when comparing to the General Call address 0000000 I2C Slave address mask register 3 This mask register is associated with I2ADRO to determine an address match The mask register has no effect when comparing to the General Call address 0000000 Reset valuell 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Reference Table 254 Table 254 Table 255 Table 256 Table 256 Table 256 Table 256 1 Reset value reflects the data stored in used bits only It does not include reserved bits content UM10524 14 7 1 12C Control Set register CONSET The CONSET regis
403. igger level RTS is deasserted to a high value It is possible that the sending USART sends an additional byte after the trigger level is reached assuming the sending USART has another byte to send because it might not recognize the deassertion of RTS until after it has begun sending the additional byte RTS is automatically reasserted to a low value once the receiver FIFO has reached the previous trigger level The reassertion of RTS signals the sending USART to continue transmitting data If Auto RTS mode is disabled the RTSen bit controls the RTS output of the USART If Auto RTS mode is enabled hardware controls the RTS output and the actual value of RTS will be copied in the RTS Control bit of the USART As long as Auto RTS is enabled the value of the RTS Control bit is read only for software Example Suppose the USART operating in type 550 mode has the trigger level in FCR set to 0x2 then if Auto RTS is enabled the USART will deassert the RTS output as soon as the receive FIFO contains 8 bytes Table 211 on page 210 The RTS output will be reasserted as soon as the receive FIFO hits the previous trigger level 4 bytes UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 212 of 404 NXP Semiconductors U M1 0524 Chapter 12 LPC1315 16 17 45 46 47 USART UART1 Rx RTS1 pin UART1 Rx FIFO read UA
404. igure 44 Until this occurs arbitration is not lost by either master since they were both transmitting the same data If the 12C hardware detects a Repeated START condition on the I2C bus before generating a Repeated START condition itself it will release the bus and no interrupt request is generated If another master frees the bus by generating a STOP condition the 12C block will transmit a normal START condition state 0x08 and a retry of the total serial data transfer can commence UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 284 of 404 NXP Semiconductors U M1 0524 14 10 6 2 14 10 6 3 UM10524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller OTHER MASTER T caclanan o LA SLA 1WiAi DATA 1A ee Pelee other Master sends repeated START earlier retry Fig 44 Simultaneous Repeated START conditions from two masters Data transfer after loss of arbitration Arbitration may be lost in the master transmitter and master receiver modes see Figure 38 Loss of arbitration is indicated by the following states in STAT 0x38 0x68 0x78 and OxBO see Figure 40 and Figure 41 If the STA flag in CON is set by the routines which service these states then if the bus is free again a START condition state 0x08 is transmitted without intervention by the CPU and a retry of the tot
405. imer 1 TRST PIOO_14 AD3 46 35 24 Il 1 PU TRST Test Reset for JTAG interface C132B1_MAT1 O PIO0_14 General purpose digital input output pin l AD3 A D converter input 3 O CT32B1_MAT1 Match output 1 for 32 bit timer 1 SWDIO PIOO_15 AD4 52 39 25 6 PU VO SWDIO Serial wire debug input output C1T32B1_MAT2 O PIO0_15 General purpose digital input output pin z l AD4 A D converter input 4 O CT32B1_MAT2 Match output 2 for 32 bit timer 1 PIOO_16 AD5 53 40 26 B k PU I O PIO0_16 General purpose digital input output pin CT32B1_MAT3 WAKEUP AD5 A D converter input 5 O CT32B1_MAT3 Match output 3 for 32 bit timer 1 UM10524 All information provided in this document is subject to legal disclaimers WAKEUP Deep power down mode wake up pin with 20 ns glitch filter This pin must be pulled HIGH externally to enter Deep power down mode and pulled LOW to exit Deep power down mode A LOW going pulse as short as 50 ns wakes up the part NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 113 of 404 NXP Semiconductors U M1 0524 Chapter 8 LPC1315 16 17 45 46 47 Pin configuration Table 109 Pin description LPC1345 46 47 with USB Symbol Description 3g 3 SeS g amp J yes aw Ee PIOO_17 RTS 60 45 30 B IPU I O PIO0_17 General purpose digital input output pin CT32B0_CAPO SCLK O RTS Request To Send output for USART
406. imer Match signal 20 4 Pin description Table 322 gives a brief summary of the ADC related pins UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 345 of 404 NXP Semiconductors UM10524 Chapter 20 LPC1315 16 17 45 46 47 ADC Table 322 ADC pin description Pin Type Description AD 7 0 Input Analog Inputs The A D converter cell can measure the voltage on any of these input signals Remark While the pins are 5 V tolerant in digital mode the maximum input voltage must not exceed Vpp when the pins are configured as analog inputs VREFP Reference Voltage References These pins provide a voltage reference level for the VREFN ADC Note VREFP should be tied to VDD 3V3 and VREFN should be tied to VSS if the ADC is not used Vpop Vppa Power Analog Power and Ground These should typically be the same voltages as VDD and VSS but should be isolated to minimize noise and error Note Vppa should be tied to VDD and VSSA should be tied to VSS if the ADC is not used The ADC function must be selected via the IOCON registers in order to get accurate voltage readings on the monitored pin For a pin hosting an ADC input it is not possible to have a have a digital function selected and yet get valid ADC readings An inside circuit disconnects ADC hardware from the associated pin whenever a digital function is sel
407. imer counter match value 0 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 316 of 404 NXP Semiconductors U M1 0524 Chapter 16 LPC1315 16 17 45 46 47 32 bit counter timers CT32B0 1 16 7 8 Capture Control Register The Capture Control Register is used to control whether one of the four Capture Registers is loaded with the value in the Timer Counter when the capture event occurs and whether an interrupt is generated by the capture event Setting both the rising and falling bits at the same time is a valid configuration resulting in a capture event for both edges In the description below n represents the Timer number 0 or 1 Table 294 Capture Control Register CCR address 0x4001 4028 CT32B0 and 0x4001 8028 CT32B1 bit description Bit Symbol Value Description Reset value 0 CAPORE Capture on CT32Bn_CAP0 rising edge a sequence of 0 then 1 on CT32Bn_CAPO will 0 cause CRO to be loaded with the contents of TC 1 Enabled 0 Disabled 1 CAPOFE Capture on CT32Bn_CAPO0 falling edge a sequence of 1 then 0 on CT32Bn_CAPO will 0 cause CRO to be loaded with the contents of TC 1 Enabled 0 Disabled 2 CAPOI Interrupt on CT32Bn_CAPO event a CRO load due to a CT32Bn_CAPO event will 0 generate an interrupt 1 Enabled 0 Disabled 3 CAP1RE Capture on CT32Bn_CAP1 rising edge a sequence of 0 then 1 on CT32Bn_CAP1 wil
408. in PIOO_3 USB_VBUS I O configuration for pin PIOO_4 SCL I O configuration for pin PIOO_5 SDA I O configuration for pin PIOO_6 USB_CONNECT SCKO I O configuration for pin PlOO_7 CTS I O configuration for pin PIOO_8 MISO0 CT16B0_MAT0 ARM_TRACE_C LK All information provided in this document is subject to legal disclaimers Reset value 0x0000090 0x0000090 0x0000090 0x0000090 0x0000080 0x0000080 0x0000090 0x0000090 0x0000090 Reference Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 63 of 404 NXP Semiconductors UM10524 Table 55 Register overview Chapter 7 LPC1315 16 17 45 46 47 I O configuration IOCON base address 0x4004 4000 Name Access Address Description Reset value Reference offset PIOO_9 read write 0x024 I O configuration for pin 0x0000090 Table 65 PIO0_9 MOSI0 CT16B0_MAT1 ARM_TRACE_S WV SWCLK_PIO0_10 read write 0x028 I O configuration for pin SWCLK PIOO_10 0x0000090 Table 66 SCKO0 CT16BO_MAT2 TDI_PIOO_11 read write 0x02C I O configuration for pin 0x0000090 Table 67 TDI PIOO_11 AD0 CT32B0O_MAT3 TMS_PIOO_12 read write 0x030 I O configuration for pin 0x0000090_ Table 68 TMS PIOO_12 AD1 CT32B1_CAPO TDO_PIOO_13 read write 0x034 I O configuration for pin 0x0000090 Table 69 TDO PIOO_13 AD2 CT32B1_MATO TRST_PIOO_14 read write 0x038 I O configuration f
409. in boot ROM allow optimized performance and minimized power consumption for any given application through one simple function call Processor wake up from Deep sleep and Power down modes via reset selectable GPIO pins watchdog interrupt or USB port activity Processor wake up from Deep power down mode using one special function pin Integrated PMU Power Management Unit to minimize power consumption during Sleep Deep sleep Power down and Deep power down modes Power On Reset POR Brownout detect with four separate thresholds for interrupt and forced reset e Unique device serial number for identification e Single 3 3 V power supply 2 0 V to 3 6 V e Temperature range 40 C to 85 C e Available as LQFP64 LQFP48 and HVQFN33 package 1 3 Ordering information Table 1 Ordering information Type number Package Name Description Version LPC1345FHN33 HVQFN33 plastic thermal enhanced very thin quad flat package no leads 33 terminals n a body 7 x 7 x 0 85 mm LPC1345FBD48 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4mm SOT313 2 LPC1346FHN33 HVQFN33 plastic thermal enhanced very thin quad flat package no leads 33 terminals n a body 7 x 7 x 0 85 mm LPC1346FBD48 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4mm SOT313 2 LPC1347FHN33 HVQFN33 plastic thermal enhanced very thin quad flat package no leads 33 terminals n a body 7 x 7 x 0 85 mm LPC1347F
410. in interrupt active level falling edge interrupt set 9 6 4 GPIO Interrupts 0 0 cece ee eee 133 he 9 6 4 1 Pininterrupts 2 000000 133 9 5 1 7 Pin interrupt active level falling edge interrupt 9 6 4 2 Groupinterrupts 0000 134 Clear register 2 0 0 eee eee 9 6 5 Recommended practices 134 9 5 1 8 Pin interrupt rising edge register Chapter 10 LPC1345 46 47 USB2 0 device controller 10 1 How to read this chapter 10 4 1 USB software interface 137 10 2 Basic configuration 10 4 2 Fixed endpoint configuration 137 10 3 Bai reek doe ah eatin asta tee 10 4 3 SoftConnect 0 0 e eee eee eee 137 10 4 General description u uoo 10 4 4 Interrupts 200 eee eee 138 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 399 of 404 NXP Semiconductors UM10524 Chapter 23 Supplementary information 10 4 5 Suspend and resume 138 10 6 11 USB set interrupt status register 10 4 6 Frame toggle output 138 INTSETSTAT 2 052 oe chescenag renee 147 10 4 7 CIOCKING ee cenia siene soa ede ee ee 139 10 6 12 USB interrupt routing register 10 5 Pindescription 0 000e 139 INTROUTING este eee 147 10 6 Register d
411. in kHz Return Code CMD _SUCCESS BUSY SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION INVALID_SECTOR Result None Description This command is used to erase a page or multiple pages of on chip flash memory To erase a single page use the same start and end page numbers 21 14 11 Write EEPROM Table 364 IAP Write EEPROM command Command Compare Input Command code 61 decimal Return Code CMD_SUCCESS SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED Result Param0 EEPROM address Param1 RAM address Param2 Number of bytes to be written Param3 System Clock Frequency CCLK in kHz Description Data is copied from the RAM address to the EEPROM address Remark The top 64 bytes of the EEPROM memory are reserved and cannot be written to 21 14 12 Read EEPROM Table 365 IAP Read EEPROM command Command Compare Input Command code 62 decimal Return Code CMD SUCCESS SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED Result Param0 EEPROM address Param1 RAM address Param2 Number of bytes to be read Param3 System Clock Frequency CCLKk in kHz Description Data is copied from the EEPROM address to the RAM address UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 377 of 404 NXP Semiconductors UM10524 21 14 13 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming IAP Status Co
412. information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 215 of 404 NXP Semiconductors U M1 0524 UM10524 Chapter 12 LPC1315 16 17 45 46 47 USART 12 5 10 USART Modem Status Register 12 5 11 The MSR is a read only register that provides status information on USART input signals Bit 0 is cleared when after this register is read Table 216 USART Modem Status Register MSR address 0x4000 8018 bit description Bit Symbol Value Description Reset value 0 DCTS Delta CTS 0 Set upon state change of input CTS Cleared on an MSR read 0 No change detected on modem input CTS 1 State change detected on modem input CTS 1 DDSR Delta DSR 0 Set upon state change of input DSR Cleared on an MSR read 0 No change detected on modem input DSR 1 State change detected on modem input DSR 2 TERI Trailing Edge RI 0 Set upon low to high transition of input RI Cleared on an MSR read 0 No change detected on modem input RI 1 Low to high transition detected on RI 3 DDCD Delta DCD Set upon state change of input DCD Clearedon 0 an MSR read 0 No change detected on modem input DCD 1 State change detected on modem input DCD 4 CTS Clear To Send State Complement of input signal CTS This 0 bit is connected to MCR 1 in modem loopback mode 5 DSR Data Set Ready State Complement of input signal DSR 0 This bit
413. ing the USB device stack s standard handlers through callback interface exposed by the stack hUsbHandle to the USB device stack cfgWhen 1 Set EPO in IN transfer mode 0 Set EPO in OUT transfer mode Parameters 1 hUsb Handle to the USB device stack 2 cfg When 1 Set EPO in IN transfer mode 0 Set EPO in OUT transfer mode Returns Nothing UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 192 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 199 USBD_HW_API class structure Member EnableEP DisableEP UM10524 Description void void USBD_HW_API EnableEP USBD_HANDLE_T hUsb uint32_t EPNum Function to enable selected USB endpoint This function enables interrupts on selected endpoint hUsbHandle to the USB device stack EPNumEndpoint number as per USB specification ie An EP1_IN is represented by 0x81 number Parameters 1 hUsb Handle to the USB device stack 2 EPNum Endpoint number as per USB specification ie An EP1_IN is represented by 0x81 number Returns Nothing This function enables interrupts on selected endpoint hUsbHandle to the USB device stack EPNumEndpoint number corresponding to the event as per USB specification ie An EP1_IN is represented by 0x81 number For device events set this param to 0x0 eventType of endpoint event Se
414. ing the bit will return the status of auto baud pending finished All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 217 of 404 NXP Semiconductors U M1 0524 12 5 12 2 UM10524 Chapter 12 LPC1315 16 17 45 46 47 USART Two auto baud measuring modes are available which can be selected by the ACR Mode bit In Mode 0 the baud rate is measured on two subsequent falling edges of the USART Rx pin the falling edge of the start bit and the falling edge of the least significant bit In Mode 1 the baud rate is measured between the falling edge and the subsequent rising edge of the USART Rx pin the length of the start bit The ACR AutoRestart bit can be used to automatically restart baud rate measurement if a time out occurs the rate measurement counter overflows If this bit is set the rate measurement will restart at the next falling edge of the USART Rx pin The auto baud function can generate two interrupts e The IIR ABTOInt interrupt will get set if the interrupt is enabled IER ABTolntEn is set and the auto baud rate measurement counter overflows e The IIR ABEOInt interrupt will get set if the interrupt is enabled IER ABEOIntEn is set and the auto baud has completed successfully The auto baud interrupts have to be cleared by setting the corresponding ACR ABTOIntClr and ABEOIntEn bits The fractional baud rate g
415. ingle word transmission after all bits of the data word are transferred the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured However in the case of continuous back to back transmissions the SSEL signal must be pulsed HIGH between each data word transfer This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the CPHA bit is logic zero Therefore the master device must raise the SSEL pin of the slave device between each data transfer to enable the serial peripheral data write On completion of the continuous transfer the SSEL pin is returned to its idle state one SCK period after the last bit has been captured UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 248 of 404 NXP Semiconductors U M1 0524 13 7 2 5 13 7 3 UM10524 Chapter 13 LPC1315 16 17 45 46 47 SSP SPI SPI format with CPOL 1 CPHA 1 The transfer signal sequence for SPI format with CPOL 1 CPHA 1 is shown in Figure 27 which covers both single and continuous transfers SCK SSEL MOSI MISO A 4to16biits gt Fig 27 SPI Frame Format with CPOL 1 and CPHA 1 In this configuration during idle periods e The CLK signal is forced HIGH e SSEL is forced HIGH e The transmit MOSI MISO pad is
416. interrupt reset the Timer Counter or stop the timer Actions are controlled by the settings in the MCR register UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 301 of 404 NXP Semiconductors UM10524 15 7 8 Chapter 15 LPC1315 16 17 45 46 47 16 bit counter timers CT16B0 1 Table 277 Match registers MRO to 3 addresses 0x4000 C018 to 24 CT16B0 and 0x4001 0018 to 24 CT16B1 bit description Bit Symbol Description Reset value 15 0 MATCH Timer counter match value 0 31 16 Reserved Capture Control Register The Capture Control Register is used to control whether the Capture Register is loaded with the value in the Counter timer when the capture event occurs and whether an interrupt is generated by the capture event Setting both the rising and falling bits at the same time is a valid configuration resulting in a capture event for both edges In the description below n represents the Timer number 0 or 1 Table 278 Capture Control Register CCR address 0x4000 C028 CT16B0 and 0x4001 0028 CT16B1 bit description Bit Symbol Value Description Reset 0 CAPORE 1 CAPOFE 2 CAPOI 3 CAP1RE 4 CAP1FE 5 CAP1I value Capture on CT16Bn_CAP0 rising edge a sequence of 0 then 1 on CT16Bn_CAPO will 0 cause CRO to be loaded with the contents of TC Enabled Disabled Capture on
417. interrupt status register INTSTAT address 0x4008 0020 bit description Bit Symbol Description Reset Access value 7 EP3IN Interrupt status register bit for the EP3 IN direction 0 R WC This bit will be set if the corresponding Active bit is cleared by HW This is done in case the programmed NBytes transitions to zero or the skip bit is set by software If the IntOnNAK_AI is set this bit will also be set when a NAK is transmitted for the EP3 IN direction Software can clear this bit by writing a one to it 8 EP40OUT Interrupt status register bit for the EP4 OUT direction 0 R WC This bit will be set if the corresponding Active bit is cleared by HW This is done in case the programmed NBytes transitions to zero or the skip bit is set by software If the IntOnNAK_AO is set this bit will also be set when a NAK is transmitted for the EP4 OUT direction Software can clear this bit by writing a one to it 9 EP4IN Interrupt status register bit for the EP4 IN direction 0 R WC This bit will be set if the corresponding Active bit is cleared by HW This is done in case the programmed NBytes transitions to zero or the skip bit is set by software If the IntOnNAK_AI is set this bit will also be set when a NAK is transmitted for the EP4 IN direction Software can clear this bit by writing a one to it 29 10 Reserved 0 RO 30 FRAME_INT Frame interrupt 0 R WC This bit is set to one every millisecond when the VousDebounced bit and the DCON bit
418. ion CT32B0 and 0x4001 8010 CT32B1 bit GESCHPION aeoe eie hee EN 315 Table 292 Match Control Register MCR address 0x4001 4014 CT32B0 and 0x4001 8014 CT32B1 bit description 315 Table 293 Match registers MRO to 3 addresses 0x4001 4018 to 24 CT32B0 and 0x4001 8018 to 24 CT32B1 bit description 316 Table 294 Capture Control Register CCR address 0x4001 4028 CT32B0 and 0x4001 8028 CT32B1 bit description 317 Table 295 Capture registers CR addresses 0x4001 402C CRO to 0x4001 4030 CR1 CT32B0 and 0x4001 802C CRO to 0x4001 4030 CR1 CT32B1 bit description 318 Table 296 External Match Register EMR address 0x4001 403C CT32B0 and 0x4001 803C CT32B1 bit description 318 Table 297 External match control 319 Table 298 Count Control Register CTCR address 0x4001 4070 CT32B0 and 0x4001 8070 CT32B1 bit description 320 Table 299 PWM Control Register PWMC 0x4001 4074 CT32B0 and 0x4001 8074 CT32B1 bit description 20000 cece eee 321 Table 300 Register overview Watchdog timer base address 0x4000 4000 329 Table 301 Watchdog mode register MOD 0x4000 4000 bit description 0 00050 329 Table 302 Watchdog operating modes selection 331 Table 303 Watchdog Timer Constant register TC 0x4000 4004 bit description
419. ion is lost and this 12C enters Slave Receiver mode 3 This 12C is in Slave Receiver mode but still generates clock pulses until the current byte has been transmitted This 1 C will not generate clock pulses for the next byte Data on SDA originates from the new master once it has won arbitration Fig 38 Arbitration procedure The synchronization logic will synchronize the serial clock generator with the clock pulses on the SCL line from another device If two or more master devices generate clock pulses the mark duration is determined by the device that generates the shortest marks and the space duration is determined by the device that generates the longest spaces Figure 39 shows the synchronization procedure SDA line X X 1 3 1 4 y y SCL line ko high low period period 1 Another device pulls the SCL line low before this 12C has timed a complete high time The other device effectively determines the shorter HIGH period 2 Another device continues to pull the SCL line low after this 12C has timed a complete low time and released SCL The I2C clock generator is forced to wait until SCL goes HIGH The other device effectively determines the longer LOW period 3 The SCL line is released and the clock generator begins timing the HIGH time Fig 39 Serial clock synchronization A slave may stretch the space duration to slow down the bus master The space
420. ion of allowing the transmitter to automatically control the state of the DIR pin as a direction control output signal Setting RS485CTRL bit 4 1 enables this feature Keep RS485CTRL bit 3 zero so that direction control if enabled will use the RTS pin When Auto Direction Control is enabled the selected pin will be asserted driven LOW when the CPU writes data into the TXFIFO The pin will be de asserted driven HIGH once the last bit of data has been transmitted See bits 4 and 5 in the RS485CTRL register The RS485CTRL bit 4 takes precedence over all other mechanisms controlling the direction control pin with the exception of loopback mode RS485 EIA 485 driver delay time The driver delay time is the delay between the last stop bit leaving the TXFIFO and the de assertion of RTS This delay time can be programmed in the 8 bit RS485DLY register The delay time is in periods of the baud clock Any delay time from 0 to 255 bit times may be used RS485 EIA 485 output inversion The polarity of the direction control signal on the RTS or DTR pins can be reversed by programming bit 5 in the RS485CTRL register When this bit is set the direction control pin will be driven to logic 1 when the transmitter has data waiting to be sent The direction control pin will be driven to logic 0 after the last bit of data has been transmitted Smart card mode Figure 20 shows a typical asynchronous smart card application All information pro
421. is overwritten The processor will still have the ability to read the DAT register directly as usual and the behavior of DAT will not be altered in any way Although the DATA_BUFFER register is primarily intended for use in monitor mode with the ENA_SCL bit 0 it will be available for reading at any time under any mode of operation All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 261 of 404 NXP Semiconductors U M1 0524 14 7 10 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller Table 255 I C Data buffer register DATA_BUFFER 0x4000 002C bit description Bit Symbol Description Reset value 7 0 Data This register holds contents of the 8 MSBs of the DAT shift 0 register 31 8 Reserved The value read from a reserved bit is not defined 0 I2C Mask registers MASK O 1 2 3 The four mask registers each contain seven active bits 7 1 Any bit in these registers which is set to 1 will cause an automatic compare on the corresponding bit of the received address when it is compared to the ADRn register associated with that mask register In other words bits in an ADRn register which are masked are not taken into account in determining an address match On reset all mask register bits are cleared to 0 The mask register has no effect on comparison to the General Call address 0000000
422. is command This command only allows erasure of all user sectors when the code read protection is enabled Example E 2 3 lt CR gt lt LF gt erases the flash sectors 2 and 3 21 13 10 Blank check sector s lt sector number gt lt end sector number gt Table 346 ISP Blank check sector command Command Input Start Sector Number End Sector Number Should be greater than or equal to start sector number Return Code CMD _SUCCESS SECTOR_NOT_BLANK followed by lt Offset of the first non blank word location gt lt Contents of non blank word location gt INVALID_SECTOR PARAM_ERROR Description This command is used to blank check one or more sectors of on chip flash memory Blank check on sector 0 always fails as first 64 bytes are re mapped to flash boot block When CRP is enabled the blank check command returns 0 for the offset and value of sectors which are not blank Blank sectors are correctly reported irrespective of the CRP setting Example 2 3 lt CR gt lt LF gt blank checks the flash sectors 2 and 3 21 13 11 Read Part Identification number Table 347 ISP Read Part Identification command Command J Input None Return Code CMD_SUCCESS followed by part identification number in ASCII see Table 348 LPC1315 16 17 45 46 47 device identification numbers Description This command is used to read the part identification number UM10524 All information provided in this document is subject to leg
423. is connected to MCR 0 in modem loopback mode 6 RI Ring Indicator State Complement of input RI This bit is 0 connected to MCR 2 in modem loopback mode 7 DCD Data Carrier Detect State Complement of input DCD This 0 bit is connected to MCR 3 in modem loopback mode 31 8 Reserved the value read from a reserved bit is not defined NA USART Scratch Pad Register The SCR has no effect on the USART operation This register can be written and or read at user s discretion There is no provision in the interrupt interface that would indicate to the host that a read or write of the SCR has occurred Table 217 USART Scratch Pad Register SCR address 0x4000 801C bit description Bit Symbol Description Reset Value 7 0 PAD A readable writable byte 0x00 31 8 Reserved All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 216 of 404 NXP Semiconductors U M1 0524 Chapter 12 LPC1315 16 17 45 46 47 USART 12 5 12 USART Auto baud Control Register 12 5 12 1 UM10524 The USART Auto baud Control Register ACR controls the process of measuring the incoming clock data rate for baud rate generation and can be read and written at the user s discretion Table 218 USART Auto baud Control Register ACR address 0x4000 8020 bit description Bit Symbol Value Description Reset value 0 START This bit is a
424. is document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 39 of 404 NXP Semiconductors U M1 0524 3 9 5 1 3 9 5 2 3 9 5 3 UM10524 Chapter 3 LPC1315 16 17 45 46 47 System control block Power down mode eliminates all power used by analog peripherals and all dynamic power used by the processor itself memory systems and related controllers and internal buses The processor state and registers peripheral registers and internal SRAM values are maintained and the logic levels of the pins remain static Wake up times are longer compared to the Deep sleep mode Power configuration in Power down mode Power consumption in Power down mode can be configured by the power configuration setting in the PDSLEEPCFG Table 40 register in the same way as for Deep sleep mode see Section 3 9 4 1 e The watchdog oscillator can be left running in Deep sleep mode if required for the WWDT e The BOD circuit can be left running in Deep sleep mode if required by the application Programming Power down mode The following steps must be performed to enter Power down mode 1 The PD bits in the PCON register must be set to 0x2 Table 48 2 Select the power configuration in Power down mode in the PDSLEEPCFG Table 40 register 3 If the lock bit 5 in the WWDT MOD register is set Table 301 and the IRC is selected as the WWDT clock source reset the part to clear the lo
425. is inactive Overrun error status is active 2 PE Parity Error When the parity bit of a received character is in 0 the wrong state a parity error occurs A LSR read clears LSR 2 Time of parity error detection is dependent on FCR 0 Note A parity error is associated with the character at the top of the USART RBR FIFO 0 Parity error status is inactive Parity error status is active UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 214 of 404 NXP Semiconductors UM10524 Chapter 12 LPC1315 16 17 45 46 47 USART Table 215 USART Line Status Register Read only LSR address 0x4000 8014 bit description continued Bit Symbol Value Description Reset 3 FE 5 THRE 6 TEMT 7 RXFE 8 TXERR 31 9 Value Framing Error When the stop bit of a received characterisa 0 logic 0 a framing error occurs A LSR read clears LSR 3 The time of the framing error detection is dependent on FCRO Upon detection of a framing error the RX will attempt to re synchronize to the data and assume that the bad stop bit is actually an early start bit However it cannot be assumed that the next received byte will be correct even if there is no Framing Error Note A framing error is associated with the character at the top of the USART RBR FIFO Framing error status is inactive Framing error status is active
426. is pin since Reset or the last time a one was written to this bit Write 0 no operation Read 1 a falling edge has been detected since Reset or the last time a one was written to this bit Write 1 clear falling edge detection for this pin 31 8 Reserved All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 125 of 404 NXP Semiconductors U M1 0524 UM10524 9 5 1 10 9 5 2 9 5 2 1 9 5 2 2 Chapter 9 LPC1315 16 17 45 46 47 GPIO Pin interrupt status register Reading this register returns ones for pin interrupts that are currently requesting an interrupt For pins identified as edge sensitive in the Interrupt Select register writing ones to this register clears both rising and falling edge detection for the pin For level sensitive pins writing ones inverts the corresponding bit in the Active level register thus switching the active level on the pin Table 124 Pin interrupt status register IST address 0x4004 C024 bit description Bit Symbol Description Reset Access value 7 0 PSTAT Pin interrupt status Bit n returns the status clears the edge 0 R W interrupt or inverts the active level of the pin selected in PINTSELn Read 0 interrupt is not being requested for this interrupt pin Write 0 no operation Read 1 interrupt is being requested for this interrupt pin Write 1 edge sensitive
427. ister RSR accepts valid characters via RXD After a valid character is assembled in the RSR it is passed to the USART RX Buffer Register FIFO to await access by the CPU or host via the generic host interface UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 234 of 404 NXP Semiconductors U M1 0524 UM10524 Chapter 12 LPC1315 16 17 45 46 47 USART The USART transmitter block TX accepts data written by the CPU or host and buffers the data in the USART TX Holding Register FIFO THR The USART TX Shift Register TSR reads the data stored in the THR and assembles the data to transmit via the serial output pin TXD1 The USART Baud Rate Generator block BRG generates the timing enables used by the USART TX block The BRG clock input source is USART_PCLK The main clock is divided down per the divisor specified in the DLL and DLM registers This divided down clock is a 16x oversample clock NBAUDOUT The interrupt interface contains registers IER and IIR The interrupt interface receives several one clock wide enables from the TX and RX blocks Status information from the TX and RX is stored in the LSR Control information for the TX and RX is stored in the LCR All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 201
428. ister must be set to zero UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 37 of 404 NXP Semiconductors U M1 0524 UM10524 3 9 3 3 3 9 4 3 9 4 1 Chapter 3 LPC1315 16 17 45 46 47 System control block 3 Use the ARM Cortex M3 Wait For Interrupt WFI instruction Wake up from Sleep mode Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the processor or a reset occurs After wake up due to an interrupt the microcontroller returns to its original power configuration defined by the contents of the PDRUNCFG and the SYSAHBCLKDIV registers If a reset occurs the microcontroller enters the default configuration in Active mode Deep sleep mode In Deep sleep mode the system clock to the processor is disabled as in Sleep mode All analog blocks are powered down except for the BOD circuit and the watchdog oscillator which must be selected or deselected during Deep sleep mode in the PDSLEEPCFG register The main clock and therefore all peripheral clocks are disabled except for the clock to the watchdog timer if the watchdog oscillator is selected The IRC is running but its output is disabled The flash is in stand by mode Remark If the LOCK bit is set in the WWDT MOD register Table 301 and the IRC is selected as a clock source for the WWDT the IRC continues to clock the WWD
429. it 1 FIQ interrupt line is selected for this interrupt bit 31 ROUTE_INT This bit can control on which hardware interrupt line 0 R W the interrupt will be generated 0 IRQ interrupt line is selected for this interrupt bit 1 FIQ interrupt line is selected for this interrupt bit USB Endpoint toggle EPTOGGLE Table 164 USB Endpoint toggle EPTOGGLE address 0x4008 0034 bit description Bit 9 0 31 10 Symbol Description TOGGLE Endpoint data toggle This field indicates the current value of the data toggle for the corresponding endpoint Reserved Reset Access value 0 R All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 147 of 404 NXP Semiconductors U M1 0524 Chapter 10 LPC1345 46 47 USB2 0 device controller 10 7 Functional description 10 7 1 Endpoint command status list Figure 12 gives an overview on how the Endpoint List is organized in memory The USB EP Command Status List start register points to the start of the list that contains all the endpoint information in memory The order of the endpoints is fixed as shown in the picture USB EP CommandStatus FIFO start 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset A R S TTR TV R EPO OUT Buffer NByt
430. it is set to one and this bit is zero HW will return an ACK handshake on every LPM token it receives If SW has still data pending and LPM is supported it must set this bit to 1 31 9 Reserved 0 RO UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 143 of 404 NXP Semiconductors UM10524 Chapter 10 LPC1345 46 47 USB2 0 device controller 10 6 6 USB Endpoint skip EPSKIP 10 6 7 10 6 8 Table 157 USB Endpoint skip EPSKIP address 0x4008 0014 bit description Bit 29 0 31 30 Symbol SKIP Description Reset Access value Endpoint skip Writing 1 to one of these bits will indicate 0 R W to HW that it must deactivate the buffer assigned to this endpoint and return control back to software When HW has deactivated the endpoint it will clear this bit but it will not modify the EPINUSE bit An interrupt will be generated when the Active bit goes from 1 to 0 Note In case of double buffering HW will only clear the Active bit of the buffer indicated by the EPINUSE bit Reserved 0 R USB Endpoint Buffer in use EPINUSE Table 158 USB Endpoint Buffer in use EPINUSE address 0x4008 0018 bit description Bit 1 0 9 2 31 10 Symbol BUF Description Reset Access value Reserved Fixed to zero because the control endpoint 0 R zero is fixed to single buffering for ea
431. it times OxFF in this field may indicate that there is just a single bit after a character and 11 bit times character Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Reset value 0 NA USART RS485 Control register The RS485CTRL register controls the configuration of the USART in RS 485 EIA 485 mode Table 227 USART RS485 Control register RS485CTRL address 0x4000 804C bit description Bit Symbol Value Description Reset value 0 NMMEN NMM enable 0 0 RS 485 EIA 485 Normal Multidrop Mode NMM All information provided in this document is subject to legal disclaimers is disabled RS 485 EIA 485 Normal Multidrop Mode NMM is enabled In this mode an address is detected when a received byte causes the USART to set the parity error and generate an interrupt NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 227 of 404 NXP Semiconductors U M1 0524 UM10524 12 5 20 12 5 21 Chapter 12 LPC1315 16 17 45 46 47 USART Table 227 USART RS485 Control register RS485CTRL address 0x4000 804C bit description continued Bit Symbol Value Description Reset value 1 RXDIS Receiver enable 0 0 The receiver is enabled 1 The receiver is disabled 2 AADEN AAD enable 0 0 Auto Address Detect AAD is disabled 1 Auto Address Detect AAD is enabled 3 SEL Select direction control pin 0 0 If directi
432. it which must be 0 W for the 12C block to operate in the slave receiver mode After its own slave address and the W bit have been received the serial interrupt flag SI is set and a valid status code can be read from STAT This status code is used to vector to a state service routine The appropriate action to be taken for each of these status codes is detailed in Table 265 The slave receiver mode may also be entered if arbitration is lost while the I2C block is in the master mode see status 0x68 and 0x78 If the AA bit is reset during a transfer the 12C block will return a not acknowledge logic 1 to SDA after the next received data byte While AA is reset the 12C block does not respond to its own slave address or a General Call address However the 1 C bus is still monitored and address recognition may be resumed at any time by setting AA This means that the AA bit may be used to temporarily isolate the 12C block from the I2C bus UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 277 of 404 NXP Semiconductors UM10524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller Table 265 Slave Receiver mode Status Status of the I2C bus Application software response Next action taken by I2C hardware Code andinardware TolFromDAT ToCON STAT STA STO SI AA 0x60 Own SLA W has No DAT actionor X 0 0 0 Data byt
433. itialize MSC function driver module hUsbHandle to the USB device stack paramStructure containing MSC function driver module initialization parameters Parameters 1 hUsb Handle to the USB device stack 2 param Structure containing MSC function driver module initialization parameters Returns Returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4 byte aligned or smaller than required 3 ERR_API_INVALID_PARAM2 Either MSC_Write or MSC_Read or MSC_Verify callbacks are not defined 4 ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed 5 ERR_USBD_BAD_EP_DESC Wrong endpoint descriptor is passed 11 5 36 USBD_MSC_INIT_PARAM Mass Storage class function driver initialization parameter data structure UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 198 of 404 NXP Semiconductors UM10524 Table 201 USBD_MSC_INIT_PARAM class structure Chapter 11 LPC1345 46 47 USB on chip drivers Member mem_base mem_size InquiryStr BlockCount BlockSize MemorySize intf_desc MSC_Write UM10524 Description uint32_tuint32_t USBD_MSC_INIT_PARAM mem_base Base memory location from where the stack can allocate data and buffers Remark The memory
434. its The NA value read from a reserved bit is not defined SSP SPI Masked Interrupt Status Register This read only register contains a 1 for each interrupt condition that is asserted and enabled in the IMSC registers When an SSP SPI interrupt occurs the interrupt service routine should read this register to determine the causes of the interrupt All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 243 of 404 NXP Semiconductors U M1 0524 13 6 9 Chapter 13 LPC1315 16 17 45 46 47 SSP SPI Table 241 SSP SPI Masked Interrupt Status register MIS address 0x4004 001C SSP0 and 0x4005 801C SSP1 bit description Bit Symbol Description Reset value 0 RORMIS This bit is 1 if another frame was completely received while the 0 RxFIFO was full and this interrupt is enabled 1 RTMIS This bit is 1 if the Rx FIFO is not empty has not been read for a 0 time out period and this interrupt is enabled The time out period is the same for master and slave modes and is determined by the SSP bit rate 32 bits at PCLK CPSDVSR x SCR 1 2 RXMIS This bit is 1 if the Rx FIFO is at least half full and this interrupt is 0 enabled 3 TXMIS This bit is 1 if the Tx FIFO is at least half empty and this interruptis 0 enabled 31 4 Reserved user software should not write ones to reserved bits The NA value read from a reserved
435. its of 1 8th of an 0 input clock period 001 0 125 111 0 875 7 4 OSINT Integer part of the oversampling ratio minus 1 The reset values OxF equate to the normal operating mode of 16 input clocks per bit time 14 83 FDINT In Smart Card mode these bits act as a more significant extension 0 of the OSint field allowing an oversampling ratio up to 2048 as required by ISO7816 3 In Smart Card mode bits 14 4 should initially be set to 371 yielding an oversampling ratio of 372 31 15 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined Example For a baud rate of 3 25 Mbps with a 24 MHz USART clock frequency the ideal oversampling ratio is 24 3 25 or 7 3846 Setting OSINT to 0110 for 7 clocks bit and OSFrac to 011 for 0 375 clocks bit results in an oversampling ratio of 7 375 In Smart card mode OSInt is extended by FDINT This extends the possible oversampling to 2048 as required to support ISO 7816 3 Note that this value can be exceeded when D lt 0 but this is not supported by the USART When Smart card mode is enabled the initial value of OSINT and FDINT should be programmed as 00101110011 372 minus one USART Transmit Enable Register In addition to being equipped with full hardware flow control auto cts and auto rts mechanisms described above TER enables implementation of software flow control When TxEn 1 the USART transmitter will ke
436. itself is stored in a flash memory not accessible by user s code to either read from it or write into it on its own A byte of ECC corresponds to every consecutive 128 bits of the user accessible Flash Consequently Flash bytes from 0x0000 0000 to 0x0000 OOOF are protected by the first ECC byte Flash bytes from 0x0000 0010 to 0x0000 001F are protected by the second ECC byte etc Whenever the CPU requests a read from user s Flash both 128 bits of raw data containing the specified memory location and the matching ECC byte are evaluated If the ECC mechanism detects a single error in the fetched data a correction will be applied before data are provided to the CPU When a write request into the user s Flash is made write of user specified content is accompanied by a matching ECC value calculated and stored in the ECC memory When a sector of Flash memory is erased the corresponding ECC bytes are also erased Once an ECC byte is written it can not be updated unless it is erased first Therefore for the implemented ECC mechanism to perform properly data must be written into the flash memory in groups of 16 bytes or multiples of 16 aligned as described above 21 7 Criterion for Valid User Code UM10524 The reserved ARM Cortex M3 exception vector location 7 offset 0x0000 001C in the vector table should contain the 2 s complement of the check sum of table entries 0 through 6 This causes the checksum of the first 8 table entries
437. ity control bit is LOW it produces a steady state low value on the SCK pin If the CPOL clock polarity control bit is HIGH a steady state high value is placed on the CLK pin when data is not being transferred All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 245 of 404 NXP Semiconductors U M1 0524 Chapter 13 LPC1315 16 17 45 46 47 SSP SPI The CPHA control bit selects the clock edge that captures data and allows it to change state It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge When the CPHA phase control bit is LOW data is captured on the first clock edge transition If the CPHA clock phase control bit is HIGH data is captured on the second clock edge transition 13 7 2 2 SPI format with CPOL 0 CPHA 0 Single and continuous transmission signal sequences for SPI format with CPOL 0 CPHA 0 are shown in Figure 24 SCK SSEL MOSI MISO lt _ fio 16 bits gt a Single transfer with CPOL 0 and CPHA 0 b Continuous transfer with CPOL 0 and CPHA 0 Fig 24 SPI frame format with CPOL 0 and CPHA 0 a Single and b Continuous Transfer In this configuration during idle periods e The CLK signal is forced LOW e SSEL is forced HIGH e The transmit MOSI MISO pad is in high impedanc
438. ivers 11 1 How to read this chapter 156 11 5 14 MSC_CSW 00 2 162 11 2 Introduction sso nannaa 156 11 5 15 _REQUEST_TYPE 0 5 162 14 3 USB driver functions 156 3 oe ee ea 11 4 Calling the USB device driver 157 11 5 18 USB DEVICE QUALIFIER DESCRIPTOR 163 11 5 USB API iii aici naa eamanaaaae 158 11 5 19 USB DFU FUNC DESCRIPTOR 163 11 5 1 WORD BY TE wvisscs dae chai en pia 158 11 5 20 _USB_INTERFACE_DESCRIPTOR 164 11 5 2 BMT cin Sd itd deb ida dese Meee hs 158 11 5 21 USB OTHER SPEED CONFIGURATION 164 11 5 3 11 5 22 USB SETUP_PACKET 165 _CDC_ABSTRACT_CONTROL_MANAGEMENT 11 5 23 _USB_STRING_DESCRIPTOR 165 DESCRIPTOR o on nonna 159 44 64 WBT oaaao 166 11 5 4 _CDC_CALL_MANAGEMENT_ 11 5 25 USBD_API n on nnana onanan 166 DESCRIPTOR oonan pe acecnneaialn Beier ns 159 11 5 26 USBD_APIINIT_PARAM 167 11 5 5 CDC_HEADER_DESCRIPTOR 159 41527 USBD CDC APIic 3 tcccc ev yeyeide ven 169 11 5 6 _CDC_LINE_CODING 159 11 5 28 USBD_CDC_INIT_PARAM 170 11 5 7 CDC_UNION_1SLAVE_ DESCRIPTOR 160 11 5 29 USBD CORE API 174 11 5 8 _CDC_UNION_DESCRIPTOR 160 14 5 30 USBD DFU_API 0 0 177 11 5 9 _DFU_STATUS 000005 160 11 5 31 USBD_DFU_INIT_PARAM 178 11 5 10 _HID_DESCRIPTOR 222 2002 nese5ene 160 11 5 32 USBD_HID_API
439. ked compare value specified by the contents of COMPVAL COMPVAL_H and MASK MASK_H registers This will occur on the same clock that sets the interrupt flag 0 The timer will not be cleared to 0 2 RITENBR Timer enable for debug 1 1 The timer is halted when the processor is halted for debugging 0 Debug has no effect on the timer operation 3 RITEN Timer enable 1 1 Timer enabled Remark This can be overruled by a debug halt if enabled in bit 2 0 Timer disabled 31 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 342 of 404 NXP Semiconductors U M1 0524 19 5 4 19 5 5 19 5 6 19 5 7 UM10524 Chapter 19 LPC1315 16 17 45 46 47 Repetitive Interrupt Timer RI RI Counter LSB register Table 318 RI Counter register COUNTER address 0x4006 400C bit description Bit Symbol Description Reset value 31 0 RICOUNTER 32 LSBs of the up counter Counts continuously unless RITEN bit 0 in CTRL register is cleared or debug mode is entered if enabled by the RITNEBR bit in RICTRL Can be loaded to any value in software RI Compare Value MSB register Table 319 RI Compare Value MSB register COMPVAL_H address 0x4006 4010 bit description Bit Symbol Description Reset value 15 0 R
440. l Rev 1 17 February 2012 142 of 404 NXP Semiconductors U M1 0524 Chapter 10 LPC 1345 46 47 USB2 0 device controller Table 154 USB EP Command Status List start address EPLISTSTART address 0x4008 0008 bit description Bit Symbol Description Reset Access value 7 0 Reserved 0 RO 31 8 EP_LIST Start address of the USB EP Command Status List 0 R W 10 6 4 USB Data buffer start address DATABUFSTART This register indicates the page of the AHB address where the endpoint data can be located Table 155 USB Data buffer start address DATABUFSTART address 0x4008 000C bit description Bit Symbol Description Reset Access value 21 0 Reserved 0 R 31 22 DA_BUF Start address of the buffer pointer page where all 0 R W endpoint data buffers are located 10 6 5 Link Power Management register LPM Table 156 Link Power Management register LPM address 0x4008 0010 bit description Bit Symbol Description Reset Access value 3 0 HIRD _HW Host Initiated Resume Duration HW Thisis 0 RO the HIRD value from the last received LPM token 7 4 HIRD_SW Host Initiated Resume Duration SW Thisis 0 R W the time duration required by the USB device system to come out of LPM initiated suspend after receiving the host initiated LPM resume 8 DATA_PENDING As long as this bit is set to one and LPM 0 R W supported bit is set to one HW will return a NYET handshake on every LPM token it receives If LPM supported b
441. l 0 cause CR1 to be loaded with the contents of TC 1 Enabled 0 Disabled 4 CAP1FE Capture on CT32Bn_CAP1 falling edge a sequence of 1 then 0 on CT32Bn_CAP1 will 0 cause CR1 to be loaded with the contents of TC 1 Enabled 0 Disabled 5 CAP1I Interrupt on CT32Bn_CAP1 event a CR1 load due to a CT32Bn_CAP1 event will 0 generate an interrupt 1 Enabled 0 Disabled 316 Reserved user software should not write ones to reserved bits The value read froma NA reserved bit is not defined 16 7 9 Capture Register Each Capture register is associated with a device pin and may be loaded with the Timer Counter value when a specified event occurs on that pin The settings in the Capture Control Register register determine whether the capture function is enabled and whether a capture event happens on the rising edge of the associated pin the falling edge or on both edges UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 317 of 404 NXP Semiconductors U M1 0524 16 7 10 Chapter 16 LPC1315 16 17 45 46 47 32 bit counter timers CT32B0 1 Table 295 Capture registers CR addresses 0x4001 402C CRO to 0x4001 4030 CR1 CT32B0 and 0x4001 802C CRO to 0x4001 4030 CR1 CT32B1 bit description Bit Symbol Description Reset value 31 0 CAP Timer counter capture value 0 External Match Register The External Matc
442. l LPC1315 16 1 7 45 46 47 parts 17 2 Basic configuration 17 3 Features The WWDT is configured through the following registers Power to the register interface WWDT PCLK clock In the SYSAHBCLKCTRL register set bit 15 in Table 19 Enable the WWDT clock source the watchdog oscillator or the IRC in the PDRUNCFG register Table 42 If needed enable the watchdog interrupt for wake up in the STARTERP1 register Table 39 UM10524 Internally resets chip if not reloaded during the programmable time out period Optional windowed operation requires reload to occur between a minimum and maximum time out period both programmable Optional warning interrupt can be generated at a programmable time prior to watchdog time out Programmable 24 bit timer with internal fixed pre scaler Selectable time period from 1 024 watchdog clocks Twpc k x 256 x 4 to over 67 million watchdog clocks Twocik x 224 x 4 in increments of 4 watchdog clocks Safe watchdog operation Once enabled requires a hardware reset or a Watchdog reset to be disabled Incorrect feed sequence causes immediate watchdog event if enabled The watchdog reload value can optionally be protected such that it can only be changed after the warning interrupt time is reached Flag to indicate Watchdog reset The Watchdog clock WDCLK source can be selected as the Internal High frequency oscillator IRC or the WatchDog oscillator The Watchdog
443. l Register MCR address 0x4000 C014 CT16B0 and 0x4001 0014 CT16B1 bit description continued Bit Symbol Value Description Reset value 3 MR11 Interrupt on MR1 an interrupt is generated when MR1 matches the value in the TC 0 1 Enabled 0 Disabled 4 MR1R Reset on MR1 the TC will be reset if MR1 matches it 0 i Enabled 0 Disabled 5 MR1S Stop on MR1 the TC and PC will be stopped and TCR O will be set to 0 if MR1 matches 0 the TC 1 Enabled 0 Disabled 6 MR2I Interrupt on MR2 an interrupt is generated when MR2 matches the value in the TC 0 1 Enabled 0 Disabled 7 MR2R Reset on MR2 the TC will be reset if MR2 matches it 0 1 Enabled 0 Disabled 8 MR2S Stop on MR2 the TC and PC will be stopped and TCR O will be set to 0 if MR2 matches 0 the TC 1 Enabled 0 Disabled 9 MR3l Interrupt on MR3 an interrupt is generated when MR3 matches the value in the TC 0 1 Enabled 0 Disabled 10 MR3R Reset on MR3 the TC will be reset if MR3 matches it 0 1 Enabled 0 Disabled 11 MR3S Stop on MR3 the TC and PC will be stopped and TCR O will be set to 0 if MR3 matches 0 the TC 1 Enabled 0 Disabled 31 12 Reserved user software should not write ones to reserved bits The value read froma NA reserved bit is not defined 15 7 7 Match Registers The Match register values are continuously compared to the Timer Counter value When the two values are equal actions can be triggered automatically The action possibilities are to generate an
444. l Register The CCR controls which edges of the 0 Table 278 capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place CRO RO 0x02C Capture Register 0 CRO is loaded with the value of TC when thereis 0 Table 279 an event on the CT16B1_CAPO input CR1 RO 0x030 Capture Register 1 CR1 is loaded with the value of TC when thereis 0 Table 279 an event on the CT16B1_CAP1 input 0x034 Reserved 0x038 EMR R W 0x03C External Match Register The EMR controls the match function and 0 Table 280 the external match pins CT16BO_MAT 1 0 and CT16B1_MAT 1 0 0x040 reserved 0x06C CTCR R W 0x070 Count Control Register The CTCR selects between Timer and 0 Table 282 Counter mode and in Counter mode selects the signal and edge s for counting PWMC R W 0x074 PWM Control Register The PWMCON enables PWM mode for the 0 Table 283 external match pins CT16B0_MAT 1 0 and CT16B1_MAT 1 0 1 Reset value reflects the data stored in used bits only It does not include reserved bits content UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 298 of 404 NXP Semiconductors U M1 0524 15 7 1 Chapter 15 LPC1315 16 17 45 46 47 16 bit counter timers CT16B0 1 Interrupt Register The Interrupt Register consists of four bits for the match interrupts and two
445. l bit clock on the SCLK pin 2 When CSRC is 1 selecting master mode the CSCEN bit selects whether the USART produces clocks on SCLK continuously CSCEN 1 or only when transmit data is being sent on TxD CSCEN 0 3 The SSDIS bit controls whether start and stop bits are used When SSDIS is 0 the USART sends and samples for start and stop bits as in other modes When SSDIS is 1 the USART neither sends nor samples for start or stop bits and each falling edge on SCLK samples a data bit on RxD into the receive shift register as well as shifting the transmit shift register The rest of this section provides further details of operation when SYNC is 1 Data changes on TxD from falling edges on SCLK When SSDIS is 0 the FES bit controls whether the USART samples serial data on RxD on rising edges or falling edges on SCLK When SSDIS is 1 the USART ignores FES and always samples RxD on falling edges on SCLK The combination SYNC 1 CSRC 1 CSCEN 1 and SSDIS 1 is a difficult operating mode because SCLK applies to both directions of data flow and there is no defined mechanism to signal the receivers when valid data is present on TxD or RxD Lacking such a mechanism SSDIS 1 can be used with CSCEN 0 or CSRC 0 in a mode similar to the SPI protocol in which characters are at least conceptually exchanged between the USART and remote device for each set of 8 clock cycles on SCLK Such operation can be called full duplex but the same hardw
446. laimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 351 of 404 UM10524 Chapter 20 LPC1315 16 17 45 46 47 ADC NXP Semiconductors Low power mode can save an appreciable amount of power when the ADC is not in continuous use at the expense of a delay between the trigger event and the onset of sampling and conversion These two optional modes are not mutually exclusive All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Rev 1 17 February 2012 352 of 404 UM10524 User manual UM10524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming firmware Rev 1 17 February 2012 User manual 21 1 How to read this chapter See Table 330 for different flash configurations Table 330 LPC1315 16 17 45 46 47 flash configurations Type number Flash EEPROM ISP via UART ISP via USB LPC1345FHN33 32 2 yes yes LPC1345FBD48 32 2 yes yes LPC1346FHN33 48 4 yes yes LPC1346FBD48 48 4 yes yes LPC1347FHN33 64 4 yes yes LPC1347FBD48 64 4 yes yes LPC1347FBD64 64 4 yes yes LPC1315FHN33 32 2 yes no LPC1315FBD48 32 2 yes no LPC1316FHN33 48 4 yes no LPC1316FBD48 48 4 yes no LPC1317FHN33 64 4 yes no LPC1317FBD48 64 4 yes no LPC1317FBD64 64 4 yes no Remark In addition to the ISP and IAP commands a register can be accessed in the flash controller block to configure flash memory access times see Section 21 16 1
447. lash memory access register Depending on the system clock frequency access to the flash memory can be configured with various access times by writing to the FLASHCFG register at address 0x4003 C010 Remark Improper setting of this register may result in incorrect operation of the LPC1315 16 17 45 46 47 flash memory Table 369 Flash configuration register FLASHCFG address 0x4003 C010 bit description Bit Symbol Value Description Reset value 1 0 FLASHTIM Flash memory access time FLASHTIM 1 is equal to the 0x2 number of system clocks used for flash access 0x1 1 system clock flash access time for system clock frequencies of up to 20 MHz 0x2 2 system clocks flash access time for system clock frequencies of up to 40 MHz 0x3 3 system clocks flash access time for system clock frequencies of up to 50 MHz 0x4 Reserved 31 2 Reserved User software must not change the value of these bits Bits 31 2 must be written back exactly as read Flash signature generation The flash module contains a built in signature generator This generator can produce a 128 bit signature from a range of flash memory A typical usage is to verify the flashed contents against a calculated signature e g during programming All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 379 of 404 NXP Semiconductors U M1 0524 C
448. lave Transmit mode data buffer Increment Slave Transmit buffer pointer Exit oar Wn 14 11 9 3 State 0xB8 Data has been transmitted ACK has been received Data will be transmitted ACK bit will be received 1 Load DAT from Slave Transmit buffer with data byte UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 293 of 404 NXP Semiconductors U M1 0524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller 2 Write 0x04 to CONSET to set the AA bit 3 Write 0x08 to CONCLR to clear the SI flag 4 Increment Slave Transmit buffer pointer 5 Exit 14 11 9 4 State 0xC0 Data has been transmitted NOT ACK has been received Not addressed Slave mode is entered 1 Write 0x04 to CONSET to set the AA bit 2 Write 0x08 to CONCLR to clear the SI flag 3 Exit 14 11 9 5 State 0xC8 The last data byte has been transmitted ACK has been received Not addressed Slave mode is entered 1 Write 0x04 to CONSET to set the AA bit 2 Write 0x08 to CONCLR to clear the SI flag 3 Exit UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 294 of 404 UM10524 Chapter 15 LPC1315 16 17 45 46 47 16 bit counter timers CT16B0 1 Rev 1 17 February 2012 User manual 15 1 How to read this chapter
449. le 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 27 O configuration for pin PIO1_2 Table 82 I O configuration for pin PlIO1_2 CT32B1_MAT2 PIO1_2 address 0x4004 4068 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x2 to 0x7 are reserved 0 0x0 PIO1_2 0x1 CT32B1_MAT2 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 86 of 404 NXP Semiconductors UM10524 UM10524 7 4 28 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 82 I O configuration for pin PIO1_2 CT32B1_MAT2 PIO1_2 address 0x4004 4068 bit description Bit Symbol Value Description Reset value 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pi
450. le 356 Table 357 Table 358 Table 359 Table 360 Table 361 Table 362 Table 363 Table 364 Table 365 Table 366 Table 367 Table 368 Table 369 Table 370 Table 371 Table 372 Table 373 Table 374 Table 375 Table 376 Table 377 Table 378 Table 379 Table 380 All information provided in this document is subject to legal disclaimers Chapter 23 Supplementary information Command pai it awh sakes nay iE 373 IAP Copy RAM to flash command 374 IAP Erase Sector s command 374 IAP Blank check sector s command 375 IAP Read Part Identification command 375 IAP Read Boot Code version number command 2200ee eee e eee 375 IAP Compare command 376 Reinvoke ISP 2000e ee eeee 376 IAP ReadUID command 376 IAP Erase page command 377 IAP Write EEPROM command 377 IAP Read EEPROM command 377 IAP Status Codes Summary 378 Memory mapping in debug mode 378 Register overview FMC base address 0x4003 C000 snncebeeetetdeae dete ede ke ces 379 Flash configuration register FLASHCFG address 0x4003 C010 bit description 379 Flash module signature start register FMSSTART 0x4003 C020 bit description 380 Flash module signature stop register FMSSTOP 0x4003 C024 bit description 380 FMSWO register FMSWO address 0x4003 C02C bit description
451. lects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 72 of 404 NXP Semiconductors UM10524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration 7 4 11 I O configuration for pin SWCLK PIOO_10 Table 66 I O configuration for pin SWCLK PIO0_10 SCK0 CT16B0_MAT2 SWCLK_PIOO_10 address 0x4004 4028 bit description Bit Symbol 2 0 FUNC 4 3 MODE 5 HYS 6 INV 9 7 10 OD 31 11 Value Description 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x3 Selects pin function Values 0x4 to 0x7 are reserved SWCLK PIOO_10 SCKO CT16BO_MAT2 Selects function mode on chip pull up pull down resistor control Inactive no pull down pull up resistor enabled Pull down resistor enabled Pull up resistor enabled Repeater mode Hyst
452. licable power setup command 0 24 command 1 PWR_CPU_EFFICIENCY command 2 12 rom gt pWRD gt set_power command result The above code specifies that an application running at a system clock of 12 MHz will switch to 24 MHz with emphasis on efficiency set_power returns PWR_CMD_SUCCESS in result O after configuring the microcontroller s internal power control features All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 56 of 404 UM10524 Chapter 6 LPC1315 16 17 45 46 47 NVIC Rev 1 17 February 2012 User manual 6 1 How to read this chapter The USB related interrupts 22 23 and 30 are only available on LPC134x parts 6 2 Introduction 6 3 Features The Nested Vectored Interrupt Controller NVIC is an integral part of the Cortex M3 The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts e Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex M3 e Tightly coupled interrupt controller provides low interrupt latency e Controls system exceptions and peripheral interrupts e The NVIC supports 32 vectored interrupts e 8 programmable interrupt priority levels with hardware priority level masking e Software interrupt generation e Support for NMI 6 4 Interrupt sources Table 53 lists the interrupt
453. ll rights reserved User manual Rev 1 17 February 2012 103 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 105 I O configuration for pin PlIO1_28 CT32B0_CAP0 SCLK PIO1_28 address 0x4004 40D0 bit description Bit Symbol Value Description Reset value 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 51 I O configuration for pin PIO1_29 Table 106 I O configuration for pin PIO1_29 SCK0 CT32B0_CAP1 PIO1_29 address 0x4004 40D4 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x3 to 0x7 are reserved 0 0x0 PIO1_29 0x1 SCKO 0x2 CT32BO_CAP1 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open
454. llator or the IRC can be selected to keep running in Sleep and Deep sleep modes In Power down mode only the watchdog oscillator is allowed If a watchdog interrupt occurs in Sleep Deep sleep mode or Power down mode and the WWDT interrupt is enabled in the NVIC the device will wake up Note that in Deep sleep and Power down modes the WWDT interrupt must be enabled in the STARTERP1 register in addition to the NVIC UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 330 of 404 NXP Semiconductors U M1 0524 UM10524 17 8 2 17 8 3 Chapter 17 LPC1315 16 17 45 46 47 Windowed Watchdog Timer Table 302 Watchdog operating modes selection WDEN WDRESET Mode of Operation 0 X 0or1 Debug Operate without the Watchdog running 1 0 Watchdog interrupt mode the watchdog warning interrupt will be generated but watchdog reset will not When this mode is selected the watchdog counter reaching the value specified by WOWARNINT will set the WDINT flag and the Watchdog interrupt request will be generated 1 1 Watchdog reset mode both the watchdog interrupt and watchdog reset are enabled When this mode is selected the watchdog counter reaching the value specified by WOWARNINT will set the WDINT flag and the Watchdog interrupt request will be generated and the watchdog counter reaching zero will reset the microcontroller A w
455. lock source select MAINCLKSEL address 0x4004 8070 bit description Bit Symbol Value Description Reset value 1 0 SEL Clock source for main clock 0 0x0 IRC Oscillator 0x1 PLL input 0x2 Watchdog oscillator 0x3 PLL output 31 2 Reserved System clock divider register SYSAHBCLKDIV This register controls how the main clock is divided to provide the system clock to the core memories and the peripherals The system clock can be shut down completely by setting the DIV field to zero Table 18 System clock divider SYSAHBCLKDIV address 0x4004 8078 bit description Bit Symbol Description Reset value 7 0 DIV System AHB clock divider values 0x01 0 System clock disabled 1 Divide by 1 to 255 Divide by 255 31 8 Reserved z System clock control register SYSAHBCLKCTRL The SYSAHBCLKCTRL register enables the clocks to individual system and peripheral blocks The system clock bit 0 provides the clock for the AHB the APB bridge the ARM Cortex M3 the Syscon block and the PMU This clock cannot be disabled Table 19 System clock control SYSAHBCLKCTRL address 0x4004 8080 bit description Bit Symbol Value Description Reset value 0 SYS Enables the clock for the AHB the APB bridge the 1 Cortex M3 FCLK and HCLK SysCon and the PMU This bit is read only and always reads as 1 0 Reserved 1 Enable 1 ROM Enables clock for ROM 1 0 Disable 1 Enable 2 RAMO Enables clock for SRAMO 1 0 Disable 1 Enable
456. lting in the transfer of the remaining 5 characters Table 210 USART Interrupt Handling IIR 3 0 Priority Interrupt Interrupt source Interrupt value type reset 0001 None None 0110 Highest RX Line OE or PEL or FEL or BIL LSR Readl2 Status Error 0100 Second RX Data Rx data available or trigger level reached in FIFO RBR Available FCR0 1 Read or USART FIFO drops below trigger level All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 208 of 404 NXP Semiconductors U M1 0524 Chapter 12 LPC1315 16 17 45 46 47 USART Table 210 USART Interrupt Handling IIR 3 0 Priority Interrupt Interrupt source Interrupt value type reset 1100 Second Character Minimum of one character in the RX FIFO and no RBR Time out character input or removed during a time period Readls indication depending on how many characters are in FIFO and what the trigger level is set at 3 5 to 4 5 character times The exact time will be word length x 7 2 x 8 trigger level number of characters x 8 1 RCLKs 0010 Third THRE THRE IIR Readl4 if source of interrupt or THR write 0000 Fourth Modem CTS DSR RI or DCD MSR Read Status 1 Values 0000 0011 0101 0111 1000 1001 1010 1011 1101 1110 1111 are reserved 2 For details see Section 12 5 9
457. lue equals the compare value after masking This allows for combinations not possible with a simple compare 19 4 General description The Repetitive Interrupt Timer RIT provides a versatile means of generating interrupts at specified time intervals without using a standard timer It is intended for repeating interrupts that aren t related to Operating System interrupts The RIT could also be used as an alternative to the Cortex M3 System Tick Timer if there are different system requirements The RI timer can be used in conjunction with the Embedded Trace Macrocell ETM of the ARM Cortex M9 v r2p1 for ETM timestamping The RI timer allows periodic insertion of a time value based on specific events exceptions return from exceptions trace FIFO flush into the trace data stream of the ETM With the ETM timestamping feature multiple trace data streams can be correlated to obtain a rough measure of code performance UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 340 of 404 NXP Semiconductors U M1 0524 Chapter 19 LPC1315 16 17 45 46 47 Repetitive Interrupt Timer RI RESET 4 CNT_ENA L RESET 48 bit COUNTER SET ENABLE_TIMER 3 gt o PBUS gt ENABLE_BREAK 48 2 BREAK q ENABLE _CLK PBUS gt CLR RESET COMPARATOR 2 ii gt INTR
458. lues 0x2 to 0x7 are reserved 0 0x0 PIO1_0 0x1 CT32B1_MAT1 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 85 of 404 NXP Semiconductors UM10524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration 7 4 26 I O configuration for pin PIO1_1 Table 81 I O configuration for pin PIO1_1 CT32B1_MAT1 PIO1_1 address 0x4004 4064 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x2 to 0x7 are reserved 0 OxO PIO1_1 0x1 CT32B1_MAT1 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enab
459. member to zero before calling the USBD_HID_API Init Parameters 1 hHid Handle to HID function driver 2 pSetup Pointer to setup packet recived from host 3 idleTime Idle time to be set for the specified report Returns The call back should returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_ xxx For other error conditions UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 185 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 198 USBD_HID_INIT_PARAM class structure Member Description HID_SetProtocol ErrorCode_t ErrorCode_t USBD_HID_INIT_PARAM HID_SetProtocol USBD_HANDLE_T hHid USB_SETUP_PACKET pSetup uint8_t protocol USBD_HANDLE_T hHid USB_SETUP_PACKET pSetup uint8_t protocol Optional callback function to handle HID_ REQUEST_SET PROTOCOL request The application software could provide this callback to handle HID_REQUEST_SET_PROTOCOL requests sent by the host This callback is provided to applications to adjust modes of their code between boot mode and report mode Remark Applications which don t support protocol modes should set this data member to zero before calling the USBD_HID_API Init Paramete
460. miconductors U M1 0524 Chapter 10 LPC 1345 46 47 USB2 0 device controller 10 4 1 USB software interface 31 31 25 15 0 USB EP List Start Address EP_LIST a CS Endpoint Control Status bits 4 SRAM cs NBytes ADDR OFFSET 1 cs NBytes ADDR OFFSET 2 z P F ADDR OFFSET 1 0x00 Data for endpoint 1 OUT 31 22 6 0 SRAM ADDR OFFSET 2 0x00 Data for endpoint 1 IN USB Registers System Memory Fig 11 USB software interface 10 4 2 Fixed endpoint configuration Table 149 shows the supported endpoint configurations The packet size is configurable up to the maximum value shown in Table 149 for each type of end point Table 149 Fixed endpoint configuration Logical Physical Endpoint type Direction Max packet Double endpoint endpoint size byte buffer 0 0 Control Out 64 No 0 1 Control In 64 No 1 2 Interrupt Bulk Isochronous Out 64 64 1023 Yes 1 3 Interrupt Bulk Isochronous In 64 64 1023 Yes 2 4 Interrupt Bulk Isochronous Out 64 64 1023 Yes 2 5 Interrupt Bulk Isochronous In 64 64 1023 Yes 3 6 Interrupt Bulk Isochronous Out 64 64 1023 Yes 3 7 Interrupt Bulk Isochronous In 64 64 1023 Yes 4 8 Interrupt Bulk Isochronous Out 64 64 1023 Yes 4 9 Interrupt Bulk Isochronous In 64 64 1023 Yes 10 4 3 SoftConnect The connection to the USB is accomplished by bringing USB_DP for a full speed devi
461. mitted via SDA while the serial clock is input through SCL START and STOP conditions are recognized as the beginning and end of a serial transfer In a given application I C may operate as a master and as a slave In the slave mode the I2C hardware looks for its own slave address and the General Call address If one of these addresses is detected an interrupt is requested When the microcontrollers wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted If bus arbitration is lost in the master mode the 12C interface switches to the slave mode immediately and can detect its own slave address in the same serial transfer n bytes data transmitted A Acknowledge SDA low A Not acknowledge SDA high S START condition P STOP condition E from Master to Slave D from Slave to Master Fig 36 Format of Slave Transmitter mode 14 9 I2C implementation and operation Figure 37 shows how the on chip I2C bus interface is implemented and the following text describes the individual blocks UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 265 of 404 NXP Semiconductors U M1 0524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller 8 rs ADDRESS REGISTERS I2CnADDRO to 12CnADDR3
462. modem interrupt can be read in MSR3 0 Reading the MSR clears the modem interrupt 12 5 6 USART FIFO Control Register Write Only The FCR controls the operation of the USART RX and TX FIFOs UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 209 of 404 NXP Semiconductors UM10524 UM10524 12 5 7 Chapter 12 LPC1315 16 17 45 46 47 USART Table 211 USART FIFO Control Register Write only FCR address 0x4000 8008 bit description Bit Symbol Value 0 FIFOEN 0 1 1 RXFIFO RES 0 1 2 TXFIFO RES 0 1 5 4 7 6 RXTL 0x0 0x1 0x2 0x3 31 8 z Description Reset value FIFO enable 0 USART FIFOs are disabled Must not be used in the application Active high enable for both USART Rx and TX FIFOs and FCR 7 1 access This bit must be set for proper USART operation Any transition on this bit will automatically clear the USART FIFOs RX FIFO Reset 0 No impact on either of USART FIFOs Writing a logic 1 to FCR 1 will clear all bytes in USART Rx FIFO reset the pointer logic This bit is self clearing TX FIFO Reset 0 No impact on either of USART FIFOs Writing a logic 1 to FCR 2 will clear all bytes in USART TX FIFO reset the pointer logic This bit is self clearing Reserved 0 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not define
463. must be initialized with the correct value for the desired interval A default value is provided in the SYST_CALIB register and may be changed by software The default value gives a 10 millisecond interrupt rate if the CPU clock is set to 50 MHz All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 338 of 404 NXP Semiconductors U M1 0524 Chapter 18 LPC1315 16 17 45 46 47 System tick timer 18 7 Example timer calculations To use the system tick timer do the following 1 Program the LOAD register with the reload value RELOAD to obtain the desired time interval 2 Clear the VAL register by writing to it This ensures that the timer will count from the LOAD value rather than an arbitrary value when the timer is enabled The following examples illustrate selecting SysTick timer reload values for different system configurations All of the examples calculate an interrupt interval of 10 milliseconds as the SysTick timer is intended to be used and there are no rounding errors System clock 72 MHz Program the CTRL register with the value 0x7 which selects the system clock as the clock source and enables the SysTick timer and the SysTick timer interrupt RELOAD system clock frequency x 10 ms 1 72 MHz x 10 ms 1 720000 1 719999 0x000AFC7F System tick timer clock 24 MHz Program the CTRL register with t
464. n A typical 1 C bus configuration is shown in Figure 31 Depending on the state of the direction bit R W two types of data transfers are possible on the I C bus UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 252 of 404 NXP Semiconductors U M1 0524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller e Data transfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave returns an acknowledge bit after each received byte Data transfer from a slave transmitter to a master receiver The first byte the slave address is transmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all received bytes other than the last byte At the end of the last received byte a not acknowledge is returned The master device generates all of the serial clock pulses and the START and STOP conditions A transfer is ended with a STOP condition or with a Repeated START condition Since a Repeated START condition is also the beginning of the next serial transfer the 12C bus will not be released The 12C interface is byte oriented and has four operating modes master transmitter mode master receiver mode sl
465. n Bit Symbol Value Description Reset value 6 WDTOSC_PD Watchdog oscillator power down control for 1 Deep sleep and Power down mode 1 Powered down 0 Powered 31 7 Reserved z Wake up configuration PDAWAKECFG This register controls the power configuration of the device when waking up from Deep sleep or Power down mode Table 41 Wake up configuration PDAWAKECFG address 0x4004 8234 bit description Bit Symbol Value Description Reset value 0 IRCOUT_PD IRC oscillator output wake up configuration 0 1 Powered down 0 Powered 1 IRC_PD IRC oscillator power down wake up 0 configuration 1 Powered down 0 Powered 2 FLASH_PD Flash wake up configuration 0 1 Powered down 0 Powered 3 BOD_PD BOD wake up configuration 0 1 Powered down 0 Powered 4 ADC_PD ADC wake up configuration 1 1 Powered down 0 Powered 5 SYSOSC_PD Crystal oscillator wake up configuration 1 1 Powered down 0 Powered 6 WDTOSC_PD Watchdog oscillator wake up configuration 1 1 Powered down 0 Powered 7 SYSPLL_PD System PLL wake up configuration 1 1 Powered down 0 Powered 8 USBPLL_PD USB PLL wake up configuration 1 0 Powered 1 Powered down All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 31 of 404 NXP Semiconductors U M1 0524 UM10524 3 5 37 Chapter 3 LPC1315 16 17 45 46 47 System control block Table 41 Wake up configuration PDAWAKECFG a
466. n the falling edge or on both edges Table 279 Capture registers CR addresses 0x4000 C02C CRO to 0x4000 C030 CR1 CT16B0 and 0x4001 002C CRO to 0x4001 0030 CR1 CT16B1 bit description Bit Symbol Description Reset value 15 0 CAP Timer counter capture value 0 31 16 Reserved External Match Register The External Match Register provides both control and status of the external match pins CT16Bn_MAT 1 0 If the match outputs are configured as PWM output the function of the external match registers is determined by the PWM rules Section 15 7 13 Rules for single edge controlled PWM outputs on page 307 Table 280 External Match Register EMR address 0x4000 C03C CT16B0 and 0x4001 003C CT16B1 bit description Bit Symbol 0 EMO 1 EM1 2 EM2 3 EM3 UM10524 Value Description Reset value External Match 0 This bit reflects the state of output CT16BO_MAT0 CT16B1_MATO 0 whether or not this output is connected to its pin When a match occurs between the TC and MRO this bit can either toggle go LOW go HIGH or do nothing Bits EMR 5 4 control the functionality of this output This bit is driven to the CT16BO_MAT0 CT16B1_MATO pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH External Match 1 This bit reflects the state of output CT16BO_MAT1 CT16B1_MAT1 0 whether or not this output is connected to its pin When a match occurs between the TC an
467. n 1 enables the global DONE flag in ADDR to generate an 1 interrupt When 0 only the individual A D channels enabled by ADINTEN 7 0 will generate interrupts Remark This bit must be set to 0 in burst mode BURST 1 in the CR register Reserved Unused always 0 0 20 5 4 A D Data Registers DRO to DR7 The A D Data Register hold the result when an A D conversion is complete and also include the flags that indicate when a conversion has been completed and when a conversion overrun has occurred All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 349 of 404 NXP Semiconductors U M1 0524 Chapter 20 LPC1315 16 17 45 46 47 ADC Table 327 A D Data registers DRO to DR7 addresses 0x4001 C010 to 0x4001 C02C bit description Bit Symbol Description Reset Value 3 0 Reserved 0 15 4 V_VREF When DONE is 1 this field contains a binary fraction representing the NA voltage on the ADn pin as it falls within the range of VREFP to VREFN Zero in the field indicates that the voltage on the ADn pin was less than equal to or close to that on VREFN Vgg while OxFFF indicates that the voltage on AD input was close to equal to or greater than that on VREFP VDD 29 16 Reserved 0 30 OVERRUN This bit is 1 in burst mode if the results of one or more conversions 0 was were lost and overwritten before the conversion th
468. n reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 31 11 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD Reserved 0 I O configuration for pin PIO1_3 Table 83 1 O configuration for pin PIO1_3 CT32B1_MAT3 PIO1_3 address 0x4004 406C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x2 to 0x7 are reserved 0 0x0 PIO1_3 0x1 CT32B1_MAT3 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 87 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 83 I O configuration for pin PIO1_3 CT32B1_MAT3 PIO1_3 address 0x4004 406C bit description Bit Symbol Value Description Reset value 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up abov
469. n the pin interrupt mode configured in the ISEL register e If the pin interrupt mode is edge sensitive PMODE 0 the rising edge interrupt is cleared e If the pin interrupt mode is level sensitive PMODE 1 the level interrupt is cleared Table 118 Pin interrupt level rising edge interrupt clear register PCIENR address 0x4004 C00C bit description Bit Symbol Description Reset Access value 7 0 CENRL Ones written to this address clear bits in the IENR thus NA WO disabling the interrupts Bit n clears bit n in the IENR register 0 No operation 1 Disable rising edge or level interrupt 31 8 Reserved Pin interrupt active level falling edge interrupt enable register For each of the 8 pin interrupts selected in the PINTSEL registers see Table 35 one bit in the PINTSEN_F register enables the falling edge interrupt or the configures the level sensitivity depending on the pin interrupt mode configured in the ISEL register e If the pin interrupt mode is edge sensitive PMODE 0 the falling edge interrupt is enabled e If the pin interrupt mode is level sensitive PMODE 1 the active level of the level interrupt HIGH or LOW is configured Table 119 Pin interrupt active level falling edge interrupt enable register IENF address 0x4004 C010 bit description Bit Symbol Description Reset Access value 7 0 ENAF Enables the falling edge or configures the active level interrupt 0 R W for ea
470. nabledis2 4 iiccrie Se Vieira eed 333 Fig 21 Smartcard T Owaveform 234 Fig 57 Correct Watchdog Feed with Windowed Mode Fig 22 USART block diagram 00 236 Enabled cc sc ch vied ein hy ewe wea oe 334 Fig 23 Texas Instruments Synchronous Serial Frame Fig 58 Watchdog Warning Interrupt 334 Format a Single and b Continuous back to back Fig 59 System tick timer block diagram 336 Two Frames Transfer 0005 245 Fig 60 Repetitive Interrupt Timer RI Timer block Fig 24 SPI frame format with CPOL 0 and CPHA 0 a CIAGKAM ess ia pew dare eee ay he Betas Shed bos 341 Single and b Continuous Transfer 246 Fig 61 Boot process flowchart 359 Fig 25 SPI frame format with CPOL 0 and CPHA 1 247 Fig 62 IAP parameter passing 373 Fig 26 SPI frame format with CPOL 1 and CPHA 0 a Fig 63 Algorithm for generating a 128 bit signature 383 Single and b Continuous Transfer 248 Fig 64 Connecting the SWD pins to a standard SWD Fig 27 SPI Frame Format with CPOL 1 and CONNGCIOM eir ariaa ee te ee Eee nese 386 CPHA Wie sete cman dno eee eee ont 249 Fig 28 Microwire frame format single transfer 250 Fig 29 Microwire frame format continuous transfers 250 Fig 30 Microwire frame format setup and hold details 251 Fig 31 I C bus configuration 0005 253 Fig 32 Format in the Master Transmitter mode
471. nal sequences for SPI format with CPOL 1 CPHA 0 are shown in Figure 26 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 247 of 404 NXP Semiconductors U M1 0524 Chapter 13 LPC1315 16 17 45 46 47 SSP SPI SCK SSEL MOSI MISO cm fio 16 bits gt a Single transfer with CPOL 1 and CPHA 0 SCK SSEL MOSI MISO cm 4to 16 bits gt mM 4to 16 bis gt b Continuous transfer with CPOL 1 and CPHA 0 Fig 26 SPI frame format with CPOL 1 and CPHA 0 a Single and b Continuous Transfer In this configuration during idle periods e The CLK signal is forced HIGH e SSEL is forced HIGH e The transmit MOSI MISO pad is in high impedance If the SSP SPI is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW which causes slave data to be immediately transferred onto the MISO line of the master Master s MOSI pin is enabled One half period later valid master data is transferred to the MOSI line Now that both the master and slave data have been set the SCK master clock pin becomes LOW after one further half SCK period This means that data is captured on the falling edges and be propagated on the rising edges of the SCK signal In the case of a s
472. nature can be used to verify the flash memory contents The generated signature can be compared with an expected signature and thus makes saves time and code space The method for generating the signature is described in Section 21 16 2 Table 375 show bit assignment of the FMSWO and FMSW1 FMSW2 FMSWS3 registers respectively Table 372 FMSWO0 register FMSWO address 0x4003 C02C bit description Bit Symbol Description Reset value 31 0 SWO 31 0 Word 0 of 128 bit signature bits 31 to 0 Table 373 FMSW1 register FMSW1 address 0x4003 C030 bit description Bit Symbol Description Reset value 31 0 SW1 63 32 Word 1 of 128 bit signature bits 63 to 32 Table 374 FMSW2 register FMSW2 address 0x4003 C034 bit description Bit Symbol Description Reset value 31 0 SW2 95 64 Word 2 of 128 bit signature bits 95 to 64 Table 375 FMSW3 register FMSW3 address 0x4003 40C8 bit description Bit Symbol Description Reset value 31 0 SW93 127 96 Word 3 of 128 bit signature bits 127 to 96 Flash module status register The read only FMSTAT register provides a means of determining when signature generation has completed Completion of signature generation can be checked by polling the SIG_DONE bit in FMSTAT register SIG_DONE should be cleared via the FMSTATCLR register before starting a signature generation operation otherwise the status might indicate completion of a previous operation Table 376 Flash
473. nd a setup that generates the system clock at exactly the rate specified in Param7 If it is unlikely that an exact match can be found input parameter mode Param2 should be used to specify if the actual system clock can be less than or equal greater than or equal or approximately the value specified as the expected system clock Param7 A call specifying CPU_FREQ_EQU will only succeed if the PLL can output exactly the frequency requested in Param7 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 50 of 404 NXP Semiconductors U M1 0524 UM10524 5 1 3 5 5 1 4 5 5 1 4 1 5 5 1 4 2 Chapter 5 LPC1315 16 17 45 46 47 Power profiles CPU_FREQ_LTE can be used if the requested frequency should not be exceeded such as overall current consumption and or power budget reasons CPU_FREQ_GTE helps applications that need a minimum level of CPU processing capabilities CPU_FREQ_APPROxX results in a system clock that is as close as possible to the requested value it may be greater than or less than the requested value If an illegal mode is specified set_pi returns PLL_INVALID_MODE If the expected system clock is out of the range supported by this routine set_p returns PLL_FREQ_NOT_FOUND In these cases the current PLL setting is not changed and Param0 is returned as Result1 System PLL lock time out It shoul
474. nfigurable software software off configurable configurable ADC software configurable off off off Digital peripherals software configurable off off off USB software configurable off off off 1 If bit 5 the clock source lock bit in the WWDT MOD register is set and the IRC is selected as the WWDT clock source the IRC and the IRC output are forced on during this mode Table 306 This increases power consumption and may cause the part not to enter Power down mode correctly For details see Section 17 7 Remark The Debug mode is not supported in Sleep Deep sleep Power down or Deep power down modes Reduced power modes and WWDT lock features The WWDT clock select lock feature influences the power consumption in any of the power modes because locking the WWDT clock source forces the selected WWDT clock source to be on independently of the Deep sleep and Power down mode software configuration through the PDSLEEPCFG register For details see Section 17 7 If the part uses Deep sleep mode with the WWDT running the watchdog oscillator is the preferred clock source as it minimizes power consumption If the clock source is not locked the watchdog oscillator must be powered by using the PDSLEEPCFG register Alternatively the IRC may be selected and locked in WWDT MOD register which forces the IRC on during Deep sleep mode If the part uses Power down mode with the WWDT running the watchdog oscillator must be selected as the clock source
475. nformation provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 27 of 404 NXP Semiconductors U M1 0524 3 5 31 3 5 32 Chapter 3 LPC1315 16 17 45 46 47 System control block To enable each pin interrupt and configure its edge or level sensitivity use the GPIO pin interrupt registers see Section 9 4 1 Table 35 GPIO Pin Interrupt Select register PINTSEL address 0x4004 8178 bit description Bit Symbol Value Description Reset value 4 0 INTPIN Pin number within the port selected by the PORTSEL 0 bit in this register 5 PORTSEL Select the port for the pin number to be selected inthe 0 INTPIN bits of this register 0 Port 0 1 Port 1 31 6 Reserved E USB clock control register USBCLKCTRL This register controls the use of the USB need_clock signal and the polarity of the need_clock signal for triggering the USB wake up interrupt For details of how to use the USB need_clock signal for waking up the part from Deep sleep or Power down modes see Section 10 7 6 Table 36 USB clock control USBCLKCTRL address 0x4004 8198 bit description Bit Symbol Value Description Reset value 0 AP_CLK USB need_clock signal control 0x0 0 Under hardware control 1 Forced HIGH 1 POL_CLK USB need_clock polarity for triggering the USB 0x0 wake up interrupt 0 Falling edge of the USB need_clock triggers the USB wake up default 1 Rising edg
476. not be used to temporarily release the 1 C bus since when I2EN is reset the I2C bus status is lost The AA flag should be used instead STA is the START flag Setting this bit causes the 12C interface to enter master mode and transmit a START condition or transmit a Repeated START condition if it is already in master mode When STA is 1 and the 12C interface is not already in master mode it enters master mode checks the bus and generates a START condition if the bus is free If the bus is not free it waits for a STOP condition which will free the bus and generates a START condition after a delay of a half clock period of the internal clock generator If the 12C interface is already in master mode and data has been transmitted or received it transmits a Repeated START condition STA may be set at any time including when the I C interface is in an addressed slave mode STA can be cleared by writing 1 to the STAC bit in the CONCLR register When STA is 0 no START condition or Repeated START condition will be generated If STA and STO are both set then a STOP condition is transmitted on the I C bus if it the interface is in master mode and transmits a START condition thereafter If the 12C interface is in slave mode an internal STOP condition is generated but is not transmitted on the bus STO is the STOP flag Setting this bit causes the 12C interface to transmit a STOP condition in master mode or recover from an error condition in sla
477. not exceed one half of the PCLK clock Consequently the duration of the HIGH LOW levels on the same CAP input in this case can not be shorter than 1 PCLK Bits 7 4 of this register are also used to enable and configure the capture clears timer feature This feature allows for a designated edge on a particular CAP input to reset the timer to all zeros Using this mechanism to clear the timer on the leading edge of an input pulse and performing a capture on the trailing edge permits direct pulse width measurement using a single capture input without the need to perform a subtraction operation in software Table 282 Count Control Register CTCR address 0x4000 C070 CT16B0 and 0x4001 0070 CT16B1 bit description Bit Symbol Value Description Reset value 1 0 CTM Counter Timer Mode This field selects which rising PCLK 0 edges can increment Timer s Prescale Counter PC or clear PC and increment Timer Counter TC Remark If Counter mode is selected in the CTCR bits 2 0 in the Capture Control Register CCR must be programmed as 000 0x0 Timer Mode every rising PCLK edge 0x1 Counter Mode TC is incremented on rising edges on the CAP input selected by bits 3 2 0x2 Counter Mode TC is incremented on falling edges on the CAP input selected by bits 3 2 0x3 Counter Mode TC is incremented on both edges on the CAP input selected by bits 3 2 3 2 CIS Count Input Select In counter mode when bits 1 0 in this 0 register are not
478. nsumption when the PLL clock is not needed a Power down mode has been incorporated This mode is enabled by setting the SYSPLL_PD bit to one in the Power down configuration register Table 42 In this mode the internal current reference will be turned off the oscillator and the phase frequency detector will be stopped and the dividers will enter a reset state While in Power down mode the lock output will be low to indicate that the PLL is not in lock When the Power down mode is terminated by setting the SYSPLL_PD bit to zero the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock Divider ratio programming Post divider The division ratio of the post divider is controlled by the PSEL bits The division ratio is two times the value of P selected by PSEL bits as shown in Table 8 and Table 10 This guarantees an output clock with a 50 duty cycle Feedback divider The feedback divider s division ratio is controlled by the MSEL bits The division ratio between the PLL s output clock and the input clock is the decimal value on MSEL bits plus one as specified in Table 8 and Table 10 Changing the divider values Changing the divider ratio while the PLL is running is not recommended As there is no way to synchronize the change of the MSEL and PSEL values with the dividers the risk exists that the counter will read in an undefined value which could lead to unwanted
479. nt skip register Generic endpoint double buffering To enable double buffering software must set the corresponding USB EP Buffer Config bit to one The USB EP Buffer in use register indicates which buffer will be used by HW when the next token is received When HW clears the active bit of the current buffer in use it will switch the buffer in use Software can also force HW to use a certain buffer by writing to the USB EP Buffer in use bit Special cases Use of the Active bit The use of the Active bit is a bit different between OUT and IN endpoints When data must be received for the OUT endpoint the software will set the Active bit to one and program the NBytes field to the maximum number of bytes it can receive When data must be transmitted for an IN endpoint the software sets the Active bit to one and programs the NBytes field to the number of bytes that must be transmitted Generation of a STALL handshake Special care must be taken when programming the endpoint to send a STALL handshake A STALL handshake is only sent in the following situations e The endpoint is enabled Disabled bit 0 e The active bit of the endpoint is set to 0 No packet needs to be received transmitted for that endpoint e The stall bit of the endpoint is set to one Clear Feature endpoint halt When a non control endpoint has returned a STALL handshake the host will send a Clear Feature Endpoint Halt for that endpoint When the dev
480. nter timer counter reset interrupt Fig 48 A timer cycle in which PR 2 MRx 6 and both interrupt and reset on match are enabled 4 5 i A ee counter enable interrupt Fig 49 A timer cycle in which PR 2 MRx 6 and both interrupt and stop on match are enabled 15 9 Architecture The block diagram for counter timerO and counter timer1 is shown in Figure 50 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 308 of 404 NXP Semiconductors U M1 0524 UM10524 Chapter 15 LPC1315 16 17 45 46 47 16 bit counter timers CT16B0 1 MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER INTERRUPT REGISTER CONTROL MAT 2 0 INTERRUPT CAP 1 0 STOP ON MATCH RESET ON MATCH LOAD 0 CAPTURE REGISTER 0 CAPTURE REGISTER 1 TIMER COUNTER CE ct TCI PCLK PRESCALE COUNTER reset enable MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER Fig 50 16 bit counter timer block diagram All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 309 of 404 UM10524 Chapter 16 LPC1315 16 17 45 46 47 32 bit counter timers CT32B0 1 Rev 1 17 February 2012 User manual 16 1 How to
481. ntf_desc dif_intf_desc CIC_GetRequest UM10524 Description uint32_tuint32_t USBD_CDC_INIT_PARAM mem_base Base memory location from where the stack can allocate data and buffers Remark The memory address set in this field should be accessible by USB DMA controller Also this value should be aligned on 4 byte boundary uint32_tuint32_t USBD_CDC_INIT_PARAM mem_size The size of memory buffer which stack can use Remark The mem_size should be greater than the size returned by USBD_CDC_API GetMemSize routine uint8_t uint8_t USBD_CDC_INIT_PARAM cif_intf_desc Pointer to the control interface descriptor within the descriptor array uint8_t uint8_t USBD_CDC_INIT_PARAM dif_intf_desc Pointer to the data interface descriptor within the descriptor array ErrorCode_t ErrorCode_t USBD_CDC_INIT_PARAM CIC_GetRequest USBD_HANDLE_T hHid USB_SETUP_PACKET pSetup uint8_t pBuffer uintl6_t length USBD_HANDLE_T hHid USB_SETUP_PACKET pSetup uint8_t pBuffer uintl6_t length Communication Interface Class specific get request callback function This function is provided by the application software This function gets called when host sends CIC management element get requests The setup packet data hCdcHandle to CDC function driver pSetupPointer to setup packet received from host pBufferPointer to a pointer of data buffer containing request data Pointer to pointer is used to implement zero copy buf
482. ntical for all LPC1315 16 1 7 45 46 47 parts For better immunity to noise the VREFN P and Vppa Vssa are pinned out on the LQFP64 package For theLQFP48 and HVQFN33 pin packages use Vpp and Vss for the ADC reference pins 20 2 Basic configuration The ADC is configured using the following registers 1 Pins The ADC pin functions are configured in the IOCON register block Table 55 2 Power and peripheral clock In the SYSAHBCLKCTRL register set bit 13 Table 19 Power to the ADC is controlled through the PDRUNCFG register Table 42 Remark Basic clocking for the A D converters is provided by the APB clock A programmable divider is included in each converter to scale this clock to the clock maximum 15 5 MHz in 12 bit mode or 31 MHz in 10 bit mode BURST bit 0 needed by the successive approximation process A fully accurate conversion requires 31 of these clocks 20 3 Features e 12 bit successive approximation Analog to Digital Converter ADC Input multiplexing among 8 pins e Power down mode see PDRUNCFG register in the SYSCON block Table 42 e Low power mode e Measurement range VREFN to VREFP or 0 V to Vpp for pin packages without VREFP and VREFN pins Do not exceed the Vpp voltage level e 12 bit conversion rate of 500 kSamples s e 10 bit double conversion rate mode up to 1 Msamples s e Burst conversion mode for single or multiple inputs e Optional conversion on transition on input pin or T
483. ntrol handshake interface and support for RS 485 9 bit mode and synchronous mode USART supports an asynchronous smart card interface ISO 7816 3 Two SSP controllers with FIFO and multi protocol capabilities 2C bus interface supporting the full I C bus specification and Fast mode Plus with a data rate of up to 1 Mbit s with multiple address recognition and monitor mode Clock generation Crystal Oscillator with an operating range of 1 MHz to 25 MHz system oscillator with failure detector 12 MHz high frequency Internal RC oscillator IRC trimmed to 1 accuracy over the entire voltage and temperature range The IRC can optionally be used as a system clock Internal low power low frequency WatchDog Oscillator WDO with programmable frequency output PLL allows CPU operation up to the maximum CPU rate with the system oscillator or the IRC as clock sources A second dedicated PLL is provided for USB LPC1345 46 47 Clock output function with divider that can reflect the crystal oscillator the main clock the IRC or the watchdog oscillator Power control All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 4 of 404 NXP Semiconductors UM10524 Chapter 1 LPC1315 16 17 45 46 47 Introductory information Four reduced power modes Sleep Deep sleep Power down and Deep power down Power profiles residing
484. o Device Table n Device 1 Ptr to Function 1 Ptr to Function 2 Ptr to Function 3 Ptr to Function n Fig 15 USB device driver pointer structure USB hardware function table USB core function table USB MSC function table USB DFU function table USB HID function table USB CDC function table 11 5 USB API 11 5 1 __WORD_BYTE Table 166 _ WORD_BYTE class structure Member Ww WB Description uintl6_tuint1l6_t __WORD_BYTE W data member to do 16 bit access WB_TWB_T __ WORD _BYTE WB data member to do 8 bit access UM10524 11 5 2 _BM_T All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 158 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 167 _BM_T class structure Member Description Recipient uint8_tuint8_t _BM_T Recipient Recipient type Type uint8_tuint8_t _BM T Type Request type Dir uint8_tuint8 t _BM_T Dir Direction type 11 5 3 CDC _ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR Table 168 _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR class structure Member Description bFunctionLength uint8_tuint8_t _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR bFunctionLength bDescriptorType uint8_tuint8_t _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR bDescriptorType bDescriptorSubtype uint8_tuint8_t _CDC_ABS
485. o enable the timer reset when the timer value matches the value of the corresponding match register l l l l l l l l PWM2 MAT2 i l l MR2 100 l l l T l PWM1 MAT1 J MR1 41 Ao A d d 0 41 65 100 counter is reset Fig 51 Sample PWM waveforms with a PWM cycle length of 100 selected by MR3 and MAT3 0 enabled as PWM outputs by the PWCON register 16 8 Example timer operation Figure 52 shows a timer configured to reset the count and generate an interrupt on match The prescaler is set to 2 and the match register set to 6 At the end of the timer cycle where the match occurs the timer count is reset This gives a full length cycle to the match value The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value Figure 53 shows a timer configured to stop and generate an interrupt on match The prescaler is again set to 2 and the match register set to 6 In the next clock after the timer reaches the match value the timer enable bit in TCR is cleared and the interrupt indicating that a match occurred is generated UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 322 of 404 NXP Semiconductors U M1 0524 Chapter 16 LPC1315 16 17 45 46 47 32 bit counter timers CT32B0 1 prescale counter me Lek 5S I e J o Jo t counter timer c
486. ock approximately equal to the expected 5 5 Clocking routine 5 49 value ooo oonu 52 ah P PLL re fee i ee 2 ee 49 5 6 Power routine 0 0 e eee eee eee ees 53 als a m input frequency and expected ae 5 6 1 set_POWEr 0 eee eee 53 ARSE ee Ween ea era te sets es 5 6 1 1 New system clock 20 5 55 5 5 1 2 Mode cece eee 50 55143 System PLL lock time out 51 5 6 12 Mod cure viv epee aces eia si e tanai i 55 ie use a Pore na ease es 5 6 1 3 Current system clock 55 5 5 1 4 Code examples 00e ee aes 51 5514 1 Invalid fr ncy device maximum clock rat 5 6 1 4 Code examples 0005 56 a equency device maximum clock rate 5 6 1 4 1 Invalid frequency device maximum clock rate exceeded 000 cece eee eee 51 5 5 1 4 2 Invalid fr n lection tern clack divider exceeded csicac eens canines nE nE ene s 56 Pe sprig che tai aire system cloc F 5 6 1 4 2 An applicable power setup 56 restrictiONS 0 020 cee eee 51 5 5 1 4 3 Exact solution cannot be found PLL 52 Chapter 6 LPC1315 16 17 45 46 47 NVIC 6 1 How to read this chapter 57 6 4 Interrupt Sources 57 6 2 Introduction 2 0 0 c eee eee 57 6 5 Register description 00eeeee 59 6 3 Features ini n a evi cacwcate aemcan evel 57 Chapter 7 LPC1315 16 17 45 46 47 I O configuration 7 1 How to
487. of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 175 _HID_ DESCRIPTOR class structure Member Description bLength uint8_tuint8_t _HID_DESCRIPTOR bLength Size of the descriptor in bytes bDescriptorType uint8_tuint8_t _HID_DESCRIPTOR bDescriptorType Type of HID descriptor bcdHID uintl6_tuintl6_t _HID_DESCRIPTOR bcdHID BCD encoded version that the HID descriptor and device complies to bCountryCode uint8_tuint8_t _HID_DESCRIPTOR bCountryCode Country code of the localized device or zero if universal bNumDescriptors uint8_tuint8_t _HID_DESCRIPTOR bNumDescriptors Total number of HID report descriptors for the interface DescriptorList PRE_PACK struct POST_PACK _HID_DESCRIPTOR _HID_DESCRIPTOR_LISTPRE_PACK struct POST_PACK _HID_DESCRIPTOR _HID_DESCRIPTOR_LIST _HID_DESCRIPTOR DescriptorList 1 1 Array of one or more descriptors 11 5 11 _HID_DESCRIPTOR _HID_DESCRIPTOR_LIST Table 176 _HID_DESCRIPTOR _HID_DESCRIPTOR_LIST class structure Member Description bDescriptorType uint8_tuint8_t _HID_DESCRIPTOR _HID_DESCRIPTOR_LIST bDescriptorType Type of HID report wDescriptorLength uintl6_tuintl6_t _HID_DESCRIPTOR _HID_DESCRIPTOR_LIST wDescriptorLength Length of the associated HID report descriptor in bytes 11 5 12 _HID_REPORT_T HID report descriptor data structure Table 177 _HID_REPORT_T class structure Member Description len uintl6_t
488. ommand handler Remark The sampling of pin PIOO_1 can be disabled through programming flash location 0x0000 02FC see Section 21 12 1 21 5 Memory map after any reset The boot block is 16 kB in size and is located in the memory region starting from the address 0x1FFF 0000 The bootloader is designed to run from this memory area but both the ISP and IAP software use parts of the on chip RAM The RAM usage is described later in this chapter The interrupt vectors residing in the boot block of the on chip flash memory also become active after reset i e the bottom 512 bytes of the boot block are also visible in the memory region starting from the address 0x0000 0000 21 6 Flash content protection mechanism UM10524 The LPC1315 16 1 7 45 46 47 is equipped with the Error Correction Code ECC capable Flash memory The purpose of an error correction module is twofold Firstly it decodes data words read from the memory into output data words Secondly it encodes data words to be written to the memory The error correction capability consists of single bit error correction with Hamming code All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 354 of 404 NXP Semiconductors U M1 0524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming The operation of ECC is transparent to the running application The ECC content
489. on GetMemSize uint32_t uint32_t USBD_HW_API GetMemSize USBD_API_INIT_PARAM_T param Function to determine the memory required by the USB device stack s DCD and core layers This function is called by application layer before calling pUsbApi gt hw gt Remark Some memory areas are not accessible by all bus masters Parameters 1 param Structure containing USB device stack initialization parameters Returns Returns the required memory size in bytes Init ErrorCode_t ErrorCode_t USBD_HW_API Init USBD_HANDLE_T phUsb USB_CORE_DESCS_T pDesc USBD_API_INIT_PARAM_T param Function to initialize USB device stack s DCD and core layers This function is called by application layer to initialize USB hardware and core layers On successful initialization the function returns a handle to USB device stack which should be passed to the rest of the functions phUsbPointer to the USB device stack handle of type USBD_HANDLE_T paramStructure containing USB device stack initialization parameters Parameters 1 phUsb Pointer to the USB device stack handle of type USBD_HANDLE_T 2 param Structure containing USB device stack initialization parameters Returns Returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK 0 On success 2 ERR_USBD_BAD_MEM_BUF 0x0004000b When insufficient memory buffer is passed or memory is not aligned on 2048 boundary Connect void void USBD_HW_API Conn
490. on dwDTERate uint32_tuint32_t _CDC_LINE_CODING dwDTERate bCharFormat uint8_tuint8_t _CDC_LINE_CODING bCharFormat bParityType uint8_tuint8_t _CDC_LINE_CODING bParityType bDataBits uint8_tuint8_t _CDC_LINE_CODING bDataBits 11 5 7 _CDC_UNION_1SLAVE_DESCRIPTOR Table 172 _CDC_UNION_1SLAVE_DESCRIPTOR class structure Member Description sUnion CDC_UNION_DESCRIPTORCDC_UNION_DESCRIPTOR _CDC_UNION_1SLAVE_DESCRIPTOR sUnion bSlavelnterfaces uint8_tuint8_t _CDC_UNION_1SLAVE_DESCRIPTOR bSlaveInterfaces 1 1 11 5 8 _CDC_UNION_DESCRIPTOR Table 173 _CDC_UNION_DESCRIPTOR class structure Member Description bFunctionLength uint8_tuint8_t _CDC_UNION_DESCRIPTOR bFunctionLength bDescriptorType uint8_tuint8_t _CDC_UNION_DESCRIPTOR bDescriptorType bDescriptorSubtype uint8_tuint8_t _CDC_UNION_DESCRIPTOR bDescriptorSubtype bMasterInterface uint8_tuint8_t _CDC_UNION_DESCRIPTOR bMasterInterface 11 5 9 _DFU_STATUS Table 174 _DFU_STATUS class structure Member Description bStatus uint8_tuint8_t _DFU_STATUS bStatus bwPollTimeout uint8_tuint8_t _DFU_STATUS bwPollTimeout 3 3 bState uint8_tuint8_t _DFU_STATUS bState iString uint8_tuint8_t _DFU_STATUS iString 11 5 10 _HID_DESCRIPTOR HID class specific HID Descriptor UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 160
491. on DFU_Done void void USBD_DFU_INIT_PARAM DFU_Done void void DFU done callback function This function is provided by the application software This function gets called after download is finished Nothing Returns Nothing DFU_Detach void void USBD_DFU_INIT_PARAM DFU_Detach USBD_HANDLE_T hUsb USBD_HANDLE_T hUsb DFU detach callback function This function is provided by the application software This function gets called after USB_REQ_DFU_DETACH is received Applications which set USB_DFU_WILL_DETACH bit in DFU descriptor should define this function As part of this function application can call Connect routine to disconnect and then connect back with host For application which rely on WinUSB based host application should use this feature since USB reset can be invoked only by kernel drivers on Windows host By implementing this feature host doesn t have to issue reset instead the device has to do it automatically by disconnect and connect procedure hUsbHandle DFU control structure Parameters 1 hUsb Handle DFU control structure Returns Nothing DFU_Ep0_Hdlr ErrorCode_t ErrorCode_t USBD_DFU_INIT_PARAM DFU_Ep0_Hdlr USBD_HANDLE_T hUsb void data uint32_t event USBD_HANDLE_T hUsb void data uint32_t event Optional user overridable function to replace the default DFU class handler The application software could override the default EPO class handler with their own by providing the handler function addres
492. on control is enabled bit DCTRL 1 pin RTS is used for direction control 1 If direction control is enabled bit DCTRL 1 pin DTR is used for direction control 4 DCTRL Auto direction control enable 0 0 Disable Auto Direction Control 1 Enable Auto Direction Control 5 OINV Polarity control This bit reverses the polarity of 0 the direction control signal on the RTS or DTR pin 0 The direction control pin will be driven to logic 0 when the transmitter has data to be sent It will be driven to logic 1 after the last bit of data has been transmitted 1 The direction control pin will be driven to logic 1 when the transmitter has data to be sent It will be driven to logic 0 after the last bit of data has been transmitted 31 6 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined USART RS 485 Address Match register The RS485ADRMATCH register contains the address match value for RS 485 EIA 485 mode Table 228 USART RS 485 Address Match register RS485ADRMATCH address 0x4000 8050 bit description Bit Symbol Description Reset value 7 0 ADRMATCH_ Contains the address match value 0x00 31 8 Reserved USART RS 485 Delay value register The user may program the 8 bit RS485DLY register with a delay between the last stop bit leaving the TXFIFO and the de assertion of RTS or DTR This delay time is in periods of the baud clock Any delay time from
493. on of the NMI functionality see ARM Cortex M3 technical reference manual Table 34 NMI Source Control NMISRC address 0x4004 8174 bit description Bit Symbol Description Reset value 4 0 IRQNO The IRQ number of the interrupt that acts as the Non Maskable 0 Interrupt NMI if bit 31 is 1 See Table 53 for the list of interrupt sources and their IRQ numbers 30 5 Reserved s 31 NMIEN Write a 1 to this bit to enable the Non Maskable Interrupt NMI 0 source selected by bits 4 0 Remark If the NMISRC register is used to select an interrupt as the source of Non Maskable interrupts and the selected interrupt is enabled one interrupt request can result in both a Non Maskable and a normal interrupt This can be avoided by disabling the normal interrupt in the NVIC as described in the ARM Cortex M3 technical reference manual GPIO Pin Interrupt Select register PINTSEL Each of these 8 registers selects one GPIO pin from all GPIO pins on both ports as the source of a pin interrupt To select a pin for any of the eight pin interrupts write the pin number as 0 to 23 for pins PIOO_0 to PIOO_23 and 24 to 55 for pins PIO1_0 to PIO1_ 31 to the INTPIN bits For example setting INTPIN to 0x5 in PINTSELO selects pin PIOO_5 for pin interrupt 0 Setting INTPIN in PINTSEL7 to 0x32 pin 50 selects pin PIO1_ 26 for pin interrupt 7 Each of the 8 pin interrupts must be enabled in the NVIC using interrupt slots 0 to 7 see Table 53 All i
494. on should allocate the memory which is accessible by USB controller DMA controller Remark Some memory areas are not accessible by all bus masters Parameters 1 param Structure containing HID function driver module initialization parameters Returns Returns the required memory size in bytes init ErrorCode_t ErrorCode_t USBD_HID_API init USBD_HANDLE_T hUsb USBD_HID_INIT_PARAM_T param Function to initialize HID function driver module This function is called by application layer to initialize HID function driver module On successful initialization the function returns a handle to HID function driver module in passed param structure hUsbHandle to the USB device stack paramStructure containing HID function driver module initialization parameters Parameters 1 hUsb Handle to the USB device stack 2 param Structure containing HID function driver module initialization parameters Returns Returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_BAD_MEM_BUF Memory buffer passed is not 4 byte aligned or smaller than required 3 ERR_API_INVALID_PARAM2 Either HID_GetReport or HID_SetReport callback are not defined 4 ERR_USBD_BAD_DESC HID_HID_DESCRIPTOR_TYPE is not defined immediately after interface descriptor 5 ERR_USBD_BAD_INTF_DESC Wrong interface descriptor is passed 6 ERR_USBD_BAD_EP_DESC Wrong endpoint descriptor is passed 11 5 33 USBD_HID_INIT_PAR
495. on zero copy concept lengthNumber of bytes to be written Parameters 1 offset Destination start address 2 src Pointer to a pointer to the source of data Pointer to pointer is used to implement zero copy buffers See Zero Copy Data Transfer model for more details on zero copy concept 3 length Number of bytes to be written Returns Nothing All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 199 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 201 USBD_MSC_INIT_PARAM class structure Member Description MSC_Read void void USBD_MSC_INIT_PARAM MSC_Read uint32_t offset uint8_t dst uint32_t length uint32_t offset uint8_t dst uint32_t length MSC Read callback function This function is provided by the application software This function gets called when host sends a read command offsetSource start address dstPointer to a pointer to the source of data The MSC function drivers implemented in stack are written with zero copy model Meaning the stack doesn t make an extra copy of buffer before writing reading data from USB hardware FIFO Hence the parameter is pointer to a pointer containing address buffer uint8_t dst So that the user application can update the buffer pointer instead of copying data to address pointed by the parameter not
496. ons UM10524 Table 380 Abbreviations Acronym A D ADC AHB APB BOD GPIO JTAG PLL RC SPI SSI SSP TAP UART USART Description Analog to Digital Analog to Digital Converter Advanced High performance Bus Advanced Peripheral Bus BrownOut Detection General Purpose Input Output Joint Test Action Group Phase Locked Loop Resistor Capacitor Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Test Access Port Universal Asynchronous Receiver Transmitter Universal Synchronous Asynchronous Receiver Transmitter All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 387 of 404 NXP Semiconductors UM10524 23 2 Legal information Chapter 23 Supplementary information 23 2 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 23 2 2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties ex
497. onst USBD_HW_API_T USBD_API hw Pointer to function table which exposes functions which interact directly with USB device stack s core layer core const USBD_CORE_API_T const USBD_CORE_API_T USBD_API core Pointer to function table which exposes functions which interact directly with USB device controller hardware msc const USBD_MSC_API_T const USBD_MSC_API_T USBD_API msc Pointer to function table which exposes functions provided by MSC function driver module dfu const USBD_DFU_API_T const USBD_DFU_API_T USBD_API dfu Pointer to function table which exposes functions provided by DFU function driver module hid const USBD_HID_API_T const USBD_HID_API_T USBD_API hid Pointer to function table which exposes functions provided by HID function driver module UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 166 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 190 USBD_API class structure Member cdc reserved6 version Description const USBD_CDC_API_T const USBD_CDC_API_T USBD_API cdc Pointer to function table which exposes functions provided by CDC ACM function driver module const uint32_t const uint32_t USBD_API reserved6 Reserved for future function driver module const uint32_tconst uint32_t USBD_API version Version identifier of USB ROM stack The version i
498. ontinuous transfer the SSEL pin is returned to its idle state one SCK period after the last bit has been captured 13 7 2 3 SPI format with CPOL 0 CPHA 1 The transfer signal sequence for SPI format with CPOL 0 CPHA 1 is shown in Figure 25 which covers both single and continuous transfers SCK SSEL MOSI MISO lt 4 to 16 bits gt Fig 25 SPI frame format with CPOL 0 and CPHA 1 In this configuration during idle periods e The CLK signal is forced LOW e SSEL is forced HIGH e The transmit MOSI MISO pad is in high impedance If the SSP SPI is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW Master s MOSI pin is enabled After a further one half SCK period both master and slave valid data is enabled onto their respective transmission lines At the same time the SCK is enabled with a rising edge transition Data is then captured on the falling edges and propagated on the rising edges of the SCK signal In the case of a single word transfer after all bits have been transferred the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured For continuous back to back transfers the SSEL pin is held LOW between successive data words and termination is the same as that of the single word transfer 13 7 2 4 SPI format with CPOL 1 CPHA 0 Single and continuous transmission sig
499. opy RAM to flash e Compare When CRP2 is enabled the ISP erase command only allows erasure of all user sectors CRP3 0x43218765 Access to chip via the SWD pins is disabled ISP entry by pulling PIOO_1 LOW is disabled if a valid user code is present in flash sector 0 This mode effectively disables ISP override using PIOO_1 pin It is up to the user s application to provide a flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UARTO Caution If CRP3 is selected no future factory testing can be performed on the device Table 334 Code Read Protection hardware software interaction CRP option User Code PIO0_1 pin at SWD enabled LPC1315 16 1 partial flash Valid reset 7 45 46 47 Update in ISP enters ISP mode mode None No x Yes Yes Yes None Yes High Yes No NA None Yes Low Yes Yes Yes CRP1 Yes High No No NA CRP1 Yes Low No Yes Yes All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 361 of 404 NXP Semiconductors U M1 0524 UM10524 21 12 1 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming Table 334 Code Read Protection hardware software interaction continued CRP option User Code PIO0_1 pin at SWD enabled LPC1315 16 1 partial flash Valid reset 7145 46 47 Update in ISP enters ISP mode mode CRP2 Yes High No No NA CRP2 Yes Low No Yes No CRP
500. or MASK registers GPIO Interrupts Two separate GPIO interrupt facilities are provided With pin interrupts up to eight GPIO pins can each have separately vectored edge or level sensitive interrupts With group interrupts any subset of the pins in each port can be selected to contribute to a common interrupt Any of the pin and port interrupts can be enabled to wake the part from Deep sleep mode or Power down mode Pin interrupts In this interrupt facility up to 8 pins are identified as interrupt sources by the Pin Interrupt Select registers PINTSELO 7 All of the other Pin Interrupt registers contain 8 bits corresponding to the pins called out by the PINTSELO 7 registers The PINTMODE register defines whether each interrupt pin is edge or level sensitive The PINTRISE and All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 133 of 404 NXP Semiconductors U M1 0524 Chapter 9 LPC1315 16 17 45 46 47 GPIO PINTFALL registers detect edges on each interrupt pin and can be written to clear and set edge detection The PINTST register indicates whether each interrupt pin is currently requesting an interrupt and PINTST can be written to clear interrupts The other pin interrupt registers play different roles for edge sensitive and level sensitive pins as described in Table 148 Table 148 Pin interrupt registers for edg
501. or pin 0x0000090 Table 70 TRST PIOO_14 AD3 CT32B1_MAT1 SWDIO_PIO0O_15 read write 0x03C I O configuration for pin 0x0000090 Table 71 SWDIO PIOO_15 AD4 CT32B1_MAT2 PIOO_16 read write 0x040 I O configuration for pin 0x0000090 Table 72 PIOO_16 AD5 CT32B1_MAT3 WAKEUP PIOO_17 read write 0x044 I O configuration for pin 0x0000090 Table 73 PIOO_17 RTS CT32B0_CAP0 SCLK PIOO_18 read write 0x048 I O configuration for pin 0x0000090 Table 74 PIOO_18 RXD CT32B0_MATO PIOO_19 read write 0x04C I O configuration for pin 0x0000090 Table 75 PIO0_19 TXD CT32B0_MAT1 PIOO_20 read write 0x050 I O configuration for pin PIOO_20 CT16B1_CAPO 0x0000090 Table 76 PIOO_ 21 read write 0x054 I O configuration for pin 0x0000090 Table 77 PIOO_21 CT16B1_MATO MOSI1 PIOO_22 read write 0x058 I O configuration for pin 0x0000090_ Table 78 PIOO_22 AD6 CT16B1_MAT1 MISO1 PIOO_23 read write 0x05C I O configuration for pin PIOO_23 AD7 0x0000090 Table 79 PIO1_0 read write 0x060 I O configuration for pin PIO1_0 CT32B1_MATO 0x0000090 Table 80 PIO1_1 read write 0x064 I O configuration for pin PIO1_1 CT32B1_MAT1 0x0000090 Table 81 PIO1_ 2 read write 0x068 I O configuration for pin PIO1_2 CT32B1_MAT2 0x0000090 Table 82 PIO1_3 read write O0x06C I O configuration for pin PIO1_3 CT32B1_MAT3 0x0000090 Table 83 PIO1_4 read write 0x070 I O configuration for pin PIO1_4 CT32B1_CAPO 0x0000090 Table 84 PIO1_5 read write 0x074 I O configuration for pin PlO1_5 CT32B1_CAP1 0x0000090 Table 85 0x078
502. or pin TMS PIO0_12 74 I O configuration for pin TDO PIO0_13 75 I O configuration for pin TRST PIOO_14 76 I O configuration for pin SWDIO PIOO_15 77 I O configuration for pin PlOO_16 78 NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 398 of 404 NXP Semiconductors UM10524 Chapter 23 Supplementary information 7 4 18 I O configuration for pin PlOO_17 7 4 36 I O configuration for PIO1_14 93 7 4 19 I O configuration for pin PlOO_18 7 4 37 I O configuration for pin PIO1_15 93 7 4 20 I O configuration for pin PlOO_19 7 4 38 I O configuration for pin PIO1_16 94 7 4 21 I O configuration for pin PlOO_20 7 4 39 I O configuration for PIO1_17 95 7 4 22 I O configuration for pin PlOO_21 7 4 40 I O configuration for PIO1_18 96 7 4 23 I O configuration for pin PlOO_22 7 4 41 I O configuration for pin PIO1_19 96 7 4 24 I O configuration for pin PlOO_23 7 4 42 I O configuration for pin PIO1_20 97 7 4 25 I O configuration for pin PIO1_0 7 4 43 I O configuration for pin PIO1_21 98 7 4 26 I O configuration for pin PIO1_1 7 4 44 I O configuration for pin PIO1_22 99 7 4 27 I O configuration for pin PIO1_2 7 4 45 I O configuration for pin PIO1_23 99 7 4 28 I O configuration for pin
503. or the PLL to lock Since the maximum divider value for the system clock is 255 and running at 40 kHz would need a divide by value of 300 set_pil returns PLL_INVALID_FREQ in result 0 and 12000 in result 1 without changing the PLL settings All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 51 of 404 NXP Semiconductors U M1 0524 UM10524 5 5 1 4 3 5 5 1 4 4 5 5 1 4 5 5 5 1 4 6 Chapter 5 LPC1315 16 17 45 46 47 Power profiles Exact solution cannot be found PLL command 0 12000 command 1 25000 command 2 CPU_FREQ_EQU command 3 0 rom gt pWRD gt set_pll command result The above code specifies a 12 MHz PLL input clock and a system clock of exactly 25 MHz The application was ready to infinitely wait for the PLL to lock Since there is no valid PLL setup within earlier mentioned restrictions set_p returns PLL_FREQ_NOT_FOUND in result 0 and 12000 in result 1 without changing the PLL settings System clock less than or equal to the expected value command 0 12000 command 1 25000 command 2 CPU_FREQ_LTE command 3 0 rom gt pWRD gt set_pll command result The above code specifies a 12 MHz PLL input clock a system clock of no more than 25 MHz and no locking time out set_p returns PLL_CMD_SUCCESS in result 0 and 24000 in result 1 The new system clo
504. ors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 73 I O configuration for pin PIOO_17 RTS CT32B0_CAP0 SCLK PIO0_17 address 0x4004 4044 bit description Bit Symbol Value Description Reset value 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 19 I O configuration for pin PlIOO_18 Table 74 I O configuration for pin PlIOO_18 RXD CT32B0_MATO PIO0_18 address 0x4004 4048 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x3 to 0x7 are reserved 0 0x0 PIOO_18 0x1 RXD 0x2 CT32B0_MAT0 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable UM10524 All information provided in this document is s
505. ounter reset interrupt Fig 52 A timer cycle in which PR 2 MRx 6 and both interrupt and reset on match are enabled 4 5 i A ee counter enable interrupt Fig 53 A timer cycle in which PR 2 MRx 6 and both interrupt and stop on match are enabled 16 9 Architecture The block diagram for 32 bit counter timerO and 32 bit counter timer1 is shown in Figure 54 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 323 of 404 NXP Semiconductors UM10524 Chapter 16 LPC1315 16 17 45 46 47 32 bit counter timers CT32B0 1 MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER INTERRUPT REGISTER CONTROL MAT 3 0 INTERRUPT CAP 1 0 STOP ON MATCH RESET ON MATCH LOADJ 3 0 reset enable TIMER CONTROL REGISTER Fig 54 32 bit counter timer block diagram TCI PCLK PRESCALE COUNTER CE MAXVAL PRESCALE REGISTER UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 324 of 404 UM10524 Chapter 17 LPC1315 16 17 45 46 47 Windowed Watchdog Timer WWDT Rev 1 17 February 2012 User manual 17 1 How to read this chapter The WWDT is identical on al
506. ower up the A D if the ADC is powered down ADC_PD bit in the PDRUNCFG register is HIGH or if the part is in Deep sleep Power down or Deep power down mode 23 MODE10BIT 10 bit conversion rate mode 0 Disable the 10 bit conversion rate mode 1 Enable the 10 bit conversion rate mode with high conversion rate The A D resolution is reduced to 10 bits the two LSB of the conversion result will be forced to 0 The clock rate set via the CLKDIV field can be doubled to up to 31 MHz to achieve a conversion rate of up to one million samples per second 26 24 START When the BURST bit is 0 these bits control whether and when an A D conversionis 0 started 0x0 No start this value should be used when clearing PDN to 0 0x1 Start conversion now 0x2 Start conversion when the edge selected by bit 27 occurs on PIOO_2 SSEL CT16B0_CAPO0 0x3 Start conversion when the edge selected by bit 27 occurs on P1O1_5 DIR CT32B0_CAPO 0x4 Start conversion when the edge selected by bit 27 occurs on CT32B0_MATOL 0x5 Start conversion when the edge selected by bit 27 occurs on CT32B0_MATII1I 0x6 Start conversion when the edge selected by bit 27 occurs on CT16B0_MATOL 0x7 Start conversion when the edge selected by bit 27 occurs on CT16BO_MATII I 27 EDGE Edge control This bit is significant only when the START field contains 010 111 0 0 Start conversion on a rising edge on the selected CAP MAT signal 1 Start conversion on a falling edge on the selected C
507. own in Table 257 I2EN must be set to 1 to enable the 12C function If the AA bit is 0 the 12C interface will not acknowledge any address when another device is master of the bus so it can not enter slave mode The STA STO and SI bits must be 0 The SI Bit is cleared by writing 1 to the SIC bit in the CONCLR register THe STA bit should be cleared after writing the slave address All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 262 of 404 NXP Semiconductors U M1 0524 UM10524 14 8 2 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller Table 257 CONSET used to configure Master mode Bit 7 6 5 4 3 2 1 0 Symbol I2EN STA STO SI AA Value 1 0 0 0 0 The first byte transmitted contains the slave address of the receiving device 7 bits and the data direction bit In this mode the data direction bit R W should be 0 which means Write The first byte transmitted contains the slave address and Write bit Data is transmitted 8 bits at a time After each byte is transmitted an acknowledge bit is received START and STOP conditions are output to indicate the beginning and the end of a serial transfer The 12C interface will enter master transmitter mode when software sets the STA bit The 12C logic will send the START condition as soon as the bus is free After the START condition is transmitted the SI bit is s
508. own resistor if the pin is at a logic LOW This causes the pin to retain its last known state if it is configured as an input and is not driven externally The state retention is All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 61 of 404 NXP Semiconductors U M1 0524 UM10524 7 3 3 7 3 4 7 3 5 7 3 6 7 3 7 7 3 8 Chapter 7 LPC1315 16 17 45 46 47 I O configuration not applicable to the Deep power down mode Repeater mode may typically be used to prevent a pin from floating and potentially using significant power if it floats to an indeterminate state if it is temporarily not driven Hysteresis The input buffer for digital functions can be configured with hysteresis or as plain buffer through the IOCON registers If the external pad supply voltage Vpp is between 2 5 V and 3 6 V the hysteresis buffer can be enabled or disabled If Vpp is below 2 5 V the hysteresis buffer must be disabled to use the pin in input mode Input inverter If the input inverter is enabled a HIGH pin level is inverted to 0 and a LOW pin level is inverted to 1 Input glitch filter Selected pins pins PlIOO_22 PIOO_23 and PIOO_11 to PIOO_16 provide the option of turning on or off a 10 ns input glitch filter The glitch filter is turned off by default The RESET pin has a 20 ns glitch filter not configurable Open drain
509. p after Reset or re initialization write the PORT register s e To change the state of one pin write a Byte Pin or Word Pin register e To change the state of multiple pins at a time write the SET and or CLR registers e To change the state of multiple pins in a tightly controlled environment like a software state machine consider using the NOT register This can require less write operations than SET and CLR e To read the state of one pin read a Byte Pin or Word Pin register e To make a decision based on multiple pins read and mask a PORT register UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 134 of 404 UM10524 Chapter 10 LPC1345 46 47 USB2 0 device controller Rev 1 17 February 2012 User manual 10 1 How to read this chapter The USB block is available on the LPC1345 46 47 parts 10 2 Basic configuration 10 3 Features e Pins Configure the USB pins in the IOCON register block e In the SYSAHBCLKCTRL register enable the clock to the USB controller register interface by setting bit 14 and to the USB RAM by setting bit 27 see Table 19 e Power Enable the power to the USB PHY and to the USB PLL if used in the PDRUNCFG register Table 42 e Configure the USB main clock see Table 25 e Configure the USB wake up signal See Section 10 7 6 if needed e USB2 0 full speed device
510. pll This routine sets up the system PLL according to the calling arguments If the expected clock can be obtained by simply dividing the system PLL input set_p bypasses the PLL to lower system power consumption IMPORTANT Before this routine is invoked the PLL clock source IRC system oscillator must be selected Table 15 the main clock source must be set to the input clock to the system PLL Table 17 and the system AHB clock divider must be set to 1 Table 18 set_pll attempts to find a PLL setup that matches the calling parameters Once a combination of a feedback divider value SYSPLLCTRL M a post divider ratio SYSPLLCTRL P and the system AHB clock divider SYSAHBCLKDIV is found set_pll applies the selected values and switches the main clock source selection to the system PLL clock out if necessary All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 49 of 404 NXP Semiconductors U M1 0524 UM10524 5 5 1 1 5 5 1 2 Chapter 5 LPC1315 16 17 45 46 47 Power profiles The routine returns a result code that indicates if the system PLL was successfully set PLL_CMD_SUCCESS or not in which case the result code identifies what went wrong The current system frequency value is also returned The application should use this information to adjust other clocks in the device the SSP UART and USB clocks and or
511. point number as per USB specification ie An EP1_IN is represented by 0x81 number 3 pData Pointer to the data buffer where data is to be copied This buffer address should be accessible by USB DMA master 4 len Length of the buffer passed Returns Returns the length of the requested buffer ReadSetupPkt uint32_t uint32_t USBD_HW_API ReadSetupPkt USBD_HANDLE_T hUsb uint32_t EPNum uint32_t pData Function to read setup packet data received on the requested endpoint This function is called by USB stack and the application layer to read setup packet data received on the requested endpoint hUsbHandle to the USB device stack EPNumEndpoint number as per USB specification ie An EPO_IN is represented by 0x80 number pDataPointer to the data buffer where data is to be copied Parameters 1 hUsb Handle to the USB device stack 2 EPNum Endpoint number as per USB specification ie An EPO_IN is represented by 0x80 number 3 pData Pointer to the data buffer where data is to be copied Returns Returns the number of bytes copied to the buffer UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 196 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 199 USBD_HW_API class structure Member WriteEP WakeUp EnableEvent Description uint32_t uint32_t USBD_HW_API WriteE
512. ponse format Return_Code lt CR gt lt LF gt Response_0 lt CR gt lt LF gt Response_1 lt CR gt lt LF gt Response_n lt CR gt lt LF gt Data Data only for Read commands ISP data format The data stream is in UU encoded format The UU encode algorithm converts 3 bytes of binary data in to 4 bytes of printable ASCII character set It is more efficient than Hex format which converts 1 byte of binary data in to 2 bytes of ASCII hex The sender should send the check sum after transmitting 20 UU encoded lines The length of any UU encoded line should not exceed 61 characters bytes i e it can hold 45 data bytes The receiver should compare it with the check sum of the received bytes If the check sum matches then the receiver should respond with OK lt CR gt lt LF gt to continue further transmission If the check sum does not match the receiver should respond with RESEND lt CR gt lt LF gt In response the sender should retransmit the bytes ISP flow control A software XON XOFF flow control scheme is used to prevent data loss due to buffer overrun When the data arrives rapidly the ASCII control character DC3 stop is sent to stop the flow of data Data flow is resumed by sending the ASCII control character DC1 start The host should also support the same flow control scheme ISP command abort Commands can be aborted by sending the ASCII control character ESC This feature is not documented as a command under ISP Commands
513. pressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or
514. pt disabled at reset e Pin registers allow pins to be sensed and set individually 9 4 Introduction 9 4 1 9 4 2 9 4 3 The GPIO pins can be used in several ways to set pins as inputs or outputs and use the inputs as combinations of level and edge sensitive interrupts GPIO pin interrupts From all available GPIO pins up to eight pins can be selected in the system control block to serve as external interrupt pins see Table 35 The external interrupt pins are connected to eight individual interrupts in the NVIC and are created based on rising or falling edges or on the input level on the pin GPIO group interrupt For each port pin connected to one of the two the GPIO Grouped Interrupt blocks GROUPO and GROUP1 the GPIO grouped interrupt registers determine which pins are enabled to generate interrupts and what the active polarities of each of those inputs are The GPIO grouped interrupt registers also select whether the interrupt output will be level or edge triggered and whether it will be based on the OR or the AND of all of the enabled inputs When the designated pattern is detected on the selected input pins the GPIO grouped interrupt block will generate an interrupt If the part is in a power savings mode it will first asynchronously wake the part up prior to asserting the interrupt request The interrupt request line can be cleared by writing a one to the interrupt status bit in the control register GPIO port Th
515. pt wake up enable register 0 3 5 6 USB PLL status register USBPLLSTAT 16 STARTERPO ves ivecucsecded teneeedas 29 3 5 7 System oscillator control register 3 5 34 Start logic 1 interrupt wake up enable register SYSOSCCTRL 0 eee e eee eee 16 STARTERP 6 i ccddercucavoesose anus 29 3 5 8 Watchdog oscillator control register 3 5 35 Deep sleep mode configuration register WDTOSCCTRL ci5200 inate wie Gaede 17 PDSLEEPCFG 00005 30 3 5 9 System reset status register SYSRSTSTAT 18 3 5 36 Wake up configuration PDAWAKECFG 31 3 5 10 System PLL clock source select register 3 5 37 Power configuration register PDRUNCFG 32 SYSPLLCLKSEL eens 19 3 5 38 Device ID DEVICE_ID 33 age woni TA select register jg 36 SE 34 3 5 12 Main clock source select register 3 7 Start up behavior sige Ria EPT wie ace 34 MAINCLKSEL 0 0e 0s eee 19 3 8 Brown out detection 00000s 35 3 5 13 System clock divider register 3 9 Power management 0 36 SYSAHBCLKDIV 00002 2 eee 20 3 9 1 Reduced power modes and WWDT lock 3 5 14 System clock control register features 000000 eee 36 SYSAHBCLKCTRL 20 3 9 2 Active mode 2 2 000e0e eee ee 37 3 5 15 SSPO0 clock divider register SSPOCLKDIV 22 3 9 2 1 Power configuration in Active mode 37 3 5 16 UART clock divider register UARTCLKDIV 22 3 9 3 Sleep mode
516. pter 23 Supplementary information 12 5 8 1 2 Auto CTS 0 0 eee eee 213 12 5 18 USART Smart Card Interface Control 12 5 9 USART Line Status Register Read Only 214 FEQISIOl rai ieie oaei Shade wee Eee as 226 12 5 10 USART Modem Status Register 216 12 5 19 USART RS485 Control register 227 12 5 11 USART Scratch Pad Register 216 12 5 20 USART RS 485 Address Match register 228 12 5 12 USART Auto baud Control Register 217 12 5 21 USART RS 485 Delay value register 228 12 5421 Auto bads oseta meee Wecaae data 217 12 5 22 USART Synchronous mode control register 229 12 5 12 2 Auto baud modes pope Pathash ea 218 12 6 Functional description erga Saag dei ate caeea anew ecd 231 12 5 13 USART IrDA Control Register Se 219 12 6 1 RS 485 EIA 485 modes of operation 231 12 5 14 USART Fractional Divider Register 221 RS 485 EIA 485 Normal Multidrop Mode 231 12 5 14 1 Baud rate calculation 222 RS 485 EIA 485 Auto Address Detection AAD 12 5 14 1 1 Example 1 UART_PCLK 14 7456 MHz BR MODE ooo ovo ccc LL 231 9600 2 eee 224 RS 485 EIA 485 Auto Direction Control 232 12 5 14 1 2 Example 2 UART_PCLK 12 0 MHz BR RS485 EIA 485 driver delay time 232 115200 geia bap iepa meae ari 224 RS485 EIA 485 output inversion 232 12 5 15 USART Oversampling Register 224 12 6 2 Smartcardmode 0000 232 12 5 16 USAR
517. put pin CT32B1_MAT3 Match output 3 for 32 bit timer 1 PIO1_4 General purpose digital input output pin CT32B1_CAP0 Capture input 0 for 32 bit timer 1 P101_5 General purpose digital input output pin CT32B1_CAP1 Capture input 1 for 32 bit timer 1 PIO1_7 General purpose digital input output pin P101_8 General purpose digital input output pin P101_10 General purpose digital input output pin P101_11 General purpose digital input output pin P101_13 General purpose digital input output pin DTR Data Terminal Ready output for USART CT16B0_MATO Match output 0 for 16 bit timer 0 TXD Transmitter output for USART P101_14 General purpose digital input output pin DSR Data Set Ready input for USART CT16B0_MAT1 Match output 1 for 16 bit timer 0 RXD Receiver input for USART P101_15 General purpose digital input output pin DCD Data Carrier Detect input for USART CT16B0_MAT2 Match output 2 for 16 bit timer 0 SCK1 Serial clock for SSP1 P101_16 General purpose digital input output pin RI Ring Indicator input for USART CT16B0_CAP0 Capture input 0 for 16 bit timer 0 P101_17 General purpose digital input output pin CT16B0_CAP1 Capture input 1 for 16 bit timer 0 RXD Receiver input for USART P101_18 General purpose digital input output pin CT16B1_CAP1 Capture input 1 for 16 bit timer 1 TXD Transmitter output for USART
518. r containing the data sent by the host lengthNumber of bytes to write Parameters 1 offset Destination start address 2 buf Buffer containing the data sent by the host 3 length Number of bytes to write Returns Nothing All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 201 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 201 USBD_MSC_INIT_PARAM class structure Member MSC_Ep0_Hdlr Description ErrorCode_t ErrorCode_t USBD_MSC_INIT_PARAM MSC_Ep0_Hdlr USBD_HANDLE_T hUsb void data uint32_t event USBD_HANDLE_T hUsb void data uint32_t event Optional user overridable function to replace the default MSC class handler The application software could override the default EPO class handler with their own by providing the handler function address as this data member of the parameter structure Application which like the default handler should set this data member to zero before calling the USBD_MSC_API Init Remark Parameters 1 hUsb Handle to the USB device stack 2 data Pointer to the data which will be passed when callback function is called by the stack 3 event Type of endpoint event See USBD_EVENT_T for more details Returns The call back should returns ErrorCode_t type to indicate success or error condition Return values
519. r not UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 53 of 404 NXP Semiconductors UM10524 Chapter 5 LPC1315 16 17 45 46 47 Power profiles True using power profiles and changing system clock current_clock current_mode new_clock new_mode True current_clock new_clock use power routine call to change mode from current_mode to new_mode current_mode DEFAULT and current_mode new_mode use either clocking routine call or custom code to change system clock from current_clock to new_clock use power routine call to change mode from current_mode to new_mode wait 50 us use either clocking routine call or custom code to change system clock from current_clock to new_clock current_clock lt new_clock use either clocking routine call or custom code to change system clock from current_clock to new_clock use power routine call to change mode from current_mode to new_mode End Fig 7 Power profiles usage UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 54 of 404 NXP Semiconductors U M1 0524 5 6 1 1 5 6 1 2 5 6 1 3 UM10524 Chapter 5 LPC1315 16 17 45 46 47 Power profiles Table 52 set_power routine Routine
520. r tah e sane iit 126 9 4 INErOAUCHON saai san eterna ns gawan 9 5 2 3 GPIO grouped interrupt port enable registers 127 9 4 1 GPIO pin interrupts seein 9 5 3 GPIO port register description 128 9 4 2 GPIO group interrupt 9 5 3 1 GPIO port byte pin registers 128 9 4 3 GPIO port 06 6 eee eee eee eee 9 5 3 2 GPIO port word pin registers 128 9 5 Register description 9 5 3 3 GPIO port direction registers 129 9 5 1 GPIO pin interrupts block register description 121 9 5 3 4 GPIO port mask registers 129 9 5 1 1 Pin interrupt mode register 9 5 3 5 GPIO port pin registers 130 9 5 1 2 Pin interrupt level rising edge interrupt enable 9 5 3 6 GPIO masked port pin registers 130 FEQISICN ieron pe een p a EE 9 5 3 7 GPIO port set registers 131 9 5 1 3 Pin interrupt level rising edge interrupt set 9 5 3 8 GPIO port clear registers 131 FEQISTE epoupeio i E onpa a a avi 9 5 3 9 GPIO port toggle registers 131 9 5 1 4 Pin interrupt level rising edge interrupt clear 9 6 Functional description 132 register 6 eee eee 9 6 1 Reading pin state 000 132 9 5 1 5 Pin interrupt active level falling edge interrupt 9 6 2 GPIO output 0 0c eee eee 132 enable register 9 6 3 Masked Gs a nea dameneuee eee 133 9 5 1 6 P
521. ractional Divider setting look up table FR DivAddVal FR DivAddVal FR DivAddVal FR DivAddVal MulVal MulVal MulVal MulVal 1 000 0 1 1 250 1 4 1 500 1 2 1 750 3 4 1 067 1 15 1 267 4 15 1 5383 8 15 1 769 10 13 1 071 1 14 1 273 93 11 1 538 7 13 1 778 7 9 1 077 1 13 1 286 2 7 1 545 6 11 1 786 11 14 1 083 1 12 1 300 3 10 1 556 5 9 1 800 4 5 1 091 1 11 1 308 4 13 1 571 4 7 1 818 9 11 1 100 1 10 1 333 1 3 1 583 7 12 1 833 5 6 1 111 1 9 1 357 5 14 1 600 3 5 1 846 11 13 1 125 1 8 1 364 4 11 1 615 8 13 1 857 6 7 1 133 2 15 1 375 3 8 1625 5 8 1 867 13 15 1 143 1 7 1 385 5 13 1 636 7 11 1 875 7 8 1 154 2 13 1 400 2 5 1 643 9 14 1 889 8 9 1 167 1 6 1 417 5 12 1 667 2 3 1 900 9 10 1 182 2 11 1 429 3 7 1 692 9 13 1 909 10 11 1 200 1 5 1 444 4 9 1 700 7 10 1 917 11 12 1 214 3 14 1 455 5 11 1 714 5 7 1 923 12 13 1 222 2 9 1 462 6 13 1 727 8 11 1 929 13 14 1 231 3 13 1 467 7 15 1 733 11 15 1 933 14 15 Example 1 UART_PCLK 14 7456 MHz BR 9600 According to the provided algorithm DLest PCLK 16 x BR 14 7456 MHz 16 x 9600 96 Since this DLgg is an integer number DIVADDVAL 0 MULVAL 1 DLM 0 and DLL 96 Example 2 UART_PCLK 12 0 MHz BR 115200 According to the provided algorithm DLest PCLK 16 x BR 12 MHz 16 x 115200 6 51 This DL gg is not an integer number and the next step is to estimate the FR parameter Using an initial estimate of FReg 1 5 a new DL eg 4 is calculated and FRest is recalculated as FR
522. ral purpose digital input output pin TXD O CT32B0_MAT3 Match output 3 for 32 bit timer 0 O TXD Transmitter output for USART PIO1_28 CT32B0_CAP0 31 24 BI PU VO P101_28 General purpose digital input output pin SCLK l CT32B0_CAP0 Capture input 0 for 32 bit timer 0 VO SCLK Serial clock input output for USART in synchronous mode PIO1_29 SCKO 41 31 BI PU VO P101_29 General purpose digital input output pin CT32B0_CAP1 O SCKO Serial clock for SSPO l CT32B0_CAP1 Capture input 1 for 32 bit timer 0 PIO1_31 25 BI PU I O PIO1_31 General purpose digital input output pin USB_DM 25 19 13 B F USB_DM USB bidirectional D line LPC1345 46 46 only USB_DP 26 20 14 BI F USB_DP USB bidirectional D line LPC1345 46 46 only XTALIN 8 6 4 B Input to the oscillator circuit and internal clock generator circuits Input voltage must not exceed 1 8 V XTALOUT 9 7 5 B Output from the oscillator amplifier Vppa 59 analog 3 3 V pad supply voltage This should be nominally the same voltage as Vpp but should be isolated to minimize noise and error This voltage is used to power the ADC This pin should be tied to 3 3 V if the ADC are not used VREFN 48 ADC negative reference voltage This should be nominally the same voltage as Vss but should be isolated to minimize noise and error Level on this pin is used as a reference for ADC UM10524 All inform
523. rate calculation UM10524 The USART can operate with or without using the Fractional Divider In real life applications it is likely that the desired baud rate can be achieved using several different Fractional Divider settings The following algorithm illustrates one way of finding a set of DLM DLL MULVAL and DIVADDVAL values Such a set of parameters yields a baud rate with a relative error of less than 1 1 from the desired one All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 222 of 404 NXP Semiconductors U M1 0524 UM10524 Chapter 12 LPC1315 16 17 45 46 47 USART Calculating UART baudrate BR DL PCLK 16 x BR DL is an integer DIVADDVAL 0 MULVAL 1 Pick another FR gx from the range 1 1 1 9 DL s Int PCLK 16 x BR x FR FR PCLK 16 x BR x DL 1 1 lt FR 4 lt 1 9 DIVADDVAL table FR MULVAL table FR DLM DL 15 8 DLL DL 7 0 est Fig 19 Algorithm for setting USART dividers All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 223 of 404 NXP Semiconductors U M1 0524 12 5 14 1 1 12 5 14 1 2 UM10524 12 5 15 Chapter 12 LPC1315 16 17 45 46 47 USART Table 222 F
524. ration for pin PIOO_7 CTS PIO0_7 address 0x4004 401C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x2 to 0x7 are reserved 0 0x0 PIOO_7 0x1 CTS 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 70 of 404 NXP Semiconductors UM10524 UM10524 7 4 9 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 63 I O configuration for pin PlIOO_7 CTS PIO0_7 address 0x4004 401C bit description Bit Symbol Value Description Reset value 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 I O configuration for pin PIO0_8 Table 64 I O configuration for pin PIOO_8 MISO0 CT16B0_MAT0 ARM_TRACE_CLK PIO0_8 address 0x4004 4020 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values
525. register is a Read only register and supplies the PLL lock status see Section 3 10 1 Table 11 USB PLL status USBPLLSTAT address 0x4004 8014 bit description Bit Symbol Value Description Reset value 0 LOCK PLL lock status 0x0 0 PLL not locked 1 PLL locked 31 1 5 Reserved 0x00 3 5 7 System oscillator control register SYSOSCCTRL This register configures the frequency range for the system oscillator Table 12 System oscillator control SYSOSCCTRL address 0x4004 8020 bit description Bit Symbol Value Description Reset value 0 BYPASS Bypass system oscillator 0x0 0 Oscillator is not bypassed 1 Bypass enabled PLL input sys_osc_clk is fed directly from the XTALIN and XTALOUT pins UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 16 of 404 NXP Semiconductors U M1 0524 3 5 8 Chapter 3 LPC1315 16 17 45 46 47 System control block Table 12 System oscillator control SYSOSCCTRL address 0x4004 8020 bit description Bit Symbol Value Description Reset value 1 FREQRANGE Determines frequency range for Low power oscillator 0x0 0 1 20 MHz frequency range 1 15 25 MHz frequency range 31 2 Reserved 0x00 Watchdog oscillator control register WDTOSCCTRL This register configures the watchdog oscillator The oscillator consists of an analog anda digital part The analog part contains
526. rence value IR R W 0x000 Interrupt Register The IR can be written to clear interrupts The IR 0 Table 271 can be read to identify which of eight possible interrupt sources are pending TCR R W 0x004 Timer Control Register The TCR is used to control the Timer 0 Table 272 Counter functions The Timer Counter can be disabled or reset through the TCR TC R W 0x008 Timer Counter The 16 bit TC is incremented every PR 1 cycles of 0 Table 273 PCLK The TC is controlled through the TCR PR R W 0x00C Prescale Register When the Prescale Counter below is equal to 0 Table 274 this value the next clock increments the TC and clears the PC PC R W 0x010 Prescale Counter The 16 bit PC is a counter which is incremented to 0 Table 275 the value stored in PR When the value in PR is reached the TC is incremented and the PC is cleared The PC is observable and controllable through the bus interface MCR R W 0x014 Match Control Register The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs MRO R W 0x018 Match Register 0 MRO can be enabled through the MCR to reset the 0 Table 277 TC stop both the TC and PC and or generate an interrupt every time MRO matches the TC oO Table 276 MR1 R W 0x01C Match Register 1 See MRO description 0 Table 277 MR2 R W 0x020 Match Register 2 See MRO description 0 Table 277 MR3 R W 0x024 Match Register 3 See MRO description 0 Table 277 CCR R W 0x028 Capture Contro
527. reset if MR1 matches it 0 1 Enabled 0 Disabled 5 MR1S Stop on MR1 the TC and PC will be stopped and TCR 0 will be set to 0 if MR1 matches 0 the TC 1 Enabled 0 Disabled 6 MR2I Interrupt on MR2 an interrupt is generated when MR2 matches the value in the TC 0 1 Enabled 0 Disabled 7 MR2R Reset on MR2 the TC will be reset if MR2 matches it 0 1 Enabled 0 Disabled 8 MR2S Stop on MR2 the TC and PC will be stopped and TCR O will be set to 0 if MR2 matches 0 the TC 1 Enabled 0 Disabled 9 MR3l Interrupt on MR3 an interrupt is generated when MR3 matches the value in the TC 0 1 Enabled 0 Disabled 10 MR3R Reset on MR3 the TC will be reset if MR3 matches it 0 1 Enabled 0 Disabled 11 MR3S Stop on MR3 the TC and PC will be stopped and TCR O will be set to 0 if MR3 matches 0 the TC 1 Enabled 0 Disabled 31 12 Reserved user software should not write ones to reserved bits The value read froma NA reserved bit is not defined 16 7 7 Match Registers The Match register values are continuously compared to the Timer Counter value When the two values are equal actions can be triggered automatically The action possibilities are to generate an interrupt reset the Timer Counter or stop the timer Actions are controlled by the settings in the MCR register Table 293 Match registers MRO to 3 addresses 0x4001 4018 to 24 CT32B0 and 0x4001 8018 to 24 CT32B1 bit description Bit Symbol Description Reset value 31 0 MATCH T
528. rial data from the master to the slave When the SSP SPI is a master it outputs serial data on this signal When the SSP SPI is a slave it clocks in serial data from this signal 13 6 Register description The register addresses of the SPI controllers are shown in Table 232 The reset value reflects the data stored in used bits only It does not include the content of reserved bits UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 238 of 404 NXP Semiconductors U M1 0524 Chapter 13 LPC1315 16 17 45 46 47 SSP SPI Remark Register names use the SSP prefix to indicate that the SPI controllers have full SSP capabilities Table 232 Register overview SSP SPI0O base address 0x4004 0000 Name Access Address Description Reset Reference offset value CRO R W 0x000 Control Register 0 Selects the serial clock rate bus type anddata 0 Table 234 size CR1 R W 0x004 Control Register 1 Selects master slave and other modes 0 Table 235 DR R W 0x008 Data Register Writes fill the transmit FIFO and reads empty the 0 Table 236 receive FIFO SR RO 0x00C Status Register 0x0000 Table 237 0003 CPSR R W 0x010 Clock Prescale Register 0 Table 238 IMSC R W 0x014 Interrupt Mask Set and Clear Register 0 Table 239 RIS RO 0x018 Raw Interrupt Status Register 0x0000 Table 240 0008 MIS RO 0x01C Masked Interrupt Status Register 0
529. ripheral 12C clock 4 2 _ I2CPCLK 1 Coifrequenes SCLH SCLL The values for SCLL and SCLH must ensure that the data rate is in the appropriate 12C data rate range Each register value must be greater than or equal to 4 Table 251 gives some examples of C bus rates based on I2C_PCLK frequency and SCLL and SCLH values All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 258 of 404 NXP Semiconductors U M1 0524 UM10524 14 7 6 14 7 7 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller Table 251 SCLL SCLH values for selected 12C clock values 12C mode 12C bit 12C_PCLK MHz frequency 8 10 12 16 20 30 40 50 SCLH SCLL Standard mode 100kHz 60 80 100 120 160 200 300 400 500 Fast mode 400kHz 15 20 25 30 40 50 75 100 125 Fast mode Plus 1 MHz 8 10 12 16 20 30 40 50 SCLL and SCLH values should not necessarily be the same Software can set different duty cycles on SCL by setting these two registers For example the I2C bus specification defines the SCL low time and high time at different values for a Fast mode and Fast mode Plus IC IC Control Clear register CONCLR The CONCLR register control clearing of bits in the CON register that controls operation of the 12C interface Writing a one to a bit of this register causes the corresponding bit in the 12C control register to be cleared Writing a
530. rmation provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 91 of 404 NXP Semiconductors U M1 0524 UM10524 7 4 35 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 89 I O configuration for pin PIO1_11 PIO1_11 address 0x4004 408C bit description Bit Symbol Value Description Reset value 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 I O configuration for PIO1_13 Table 90 I O configuration for PIO1_13 DTR CT16B0_MATO TXD PIO1_13 address 0x4004 4094 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x4 to 0x7 are reserved 0 0x0 PIO1_13 0x1 DTR 0x2 CT16BO_MATO 0x3 TXD 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as
531. ro has no effect Table 287 Interrupt Register IR address 0x4001 4000 CT32B0 and IR address 0x4001 8000 bit description Bit Symbol Description Reset value 0 MROINT Interrupt flag for match channel 0 0 1 MRI1INT Interrupt flag for match channel 1 0 2 MR2INT Interrupt flag for match channel 2 0 3 MRS3INT Interrupt flag for match channel 3 0 4 CROINT Interrupt flag for capture channel 0 event 0 5 CRIINT Interrupt flag for capture channel 1 event 0 31 6 Reserved 16 7 2 Timer Control Register The Timer Control Register TCR is used to control the operation of the counter timer Table 288 Timer Control Register TCR address 0x4001 4004 CT32B0 and 0x4001 8004 CT32B1 bit description Bit Symbol Value Description Reset value 0 CEN Counter enable 0 0 The counters are disabled 1 The Timer Counter and Prescale Counter are enabled for counting 1 CRST Counter reset 0 0 Do nothing 1 The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK The counters remain reset until TCR 1 is returned to zero 31 2 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined 16 7 3 Timer Counter registers The 32 bit Timer Counter is incremented when the Prescale Counter reaches its terminal count Unless it is reset before reaching its upper limit the TC will count up through the value OXFFFF FFFF and then wrap back to the
532. roviding a standard timer that is available on Cortex M3 based devices The SysTick timer can be used for e An RTOS tick timer which fires at a programmable rate for example 100 Hz and invokes a SysTick routine A high speed alarm timer using the core clock e A simple counter Software can use this to measure time to completion and time used e An internal clock source control based on missing meeting durations The COUNTFLAG bit field in the control and status register can be used to determine if an action completed within a set duration as part of a dynamic clock management control loop Refer to the Cortex M3 User Guide for details 18 5 Register description The systick timer registers are located on the ARM Cortex M3 private peripheral bus see Figure 2 and are part of the ARM Cortex M3 core peripherals For details see Section 21 5 4 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 336 of 404 NXP Semiconductors U M1 0524 Chapter 18 LPC1315 16 17 45 46 47 System tick timer Table 309 Register overview SysTick timer base address 0xE000 E000 Name SYST_CSR SYST_RVR SYST_CVR SYST_CALIB Access Address Description Reset valuel Reference offset R W 0x010 System Timer Control and status register 0x000 0000 Table 310 R W 0x014 System Timer Reload value register 0 Table 311 R W 0x01
533. rpose digital input output pin A LOW level on this pin during reset starts the ISP command handler A HIGH level during reset starts the USB device enumeration l USB_VBUS Monitors the presence of USB bus power PIOO_4 SCL 20 15 10 I IA 0 PIO0_4 General purpose digital input output pin open drain O SCL l C bus clock input output open drain High current sink only if I2C Fast mode Plus is selected in the I O configuration register PIOO_5 SDA 21 16 1 IA 1 0 PIO0_5 General purpose digital input output pin open drain 1 0 SDA l C bus data input output open drain High current sink only if I2C Fast mode Plus is selected in the I O configuration register PIOO_6 USB_CONNECT 29 22 15 BI 1 PU I O PIO0_6 General purpose digital input output pin SCKO O USB_CONNECT Signal used to switch an external 1 5 KQ resistor under software control Used with the SoftConnect USB feature 1 0 SCKO Serial clock for SSPO PIOO_7 CTS 30 23 16 BI 1 PU I O PIO0_7 General purpose digital input output pin high current output driver CTS Clear To Send input for USART PIO0_8 MISOO 36 27 17 1 PU VO PIO0_8 General purpose digital input output pin CT16BO_MATO 0 MISOO Master In Slave Out for SSPO O CT16B0_MAT0 Match output 0 for 16 bit timer 0 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved
534. rrupt endpoint 1 Isochronous endpoint For OUT endpoints this is the number of bytes that can be received in this buffer For IN endpoints this is the number of bytes that must be transmitted HW decrements this value with the packet size every time when a packet is successfully transferred Note If a short packet is received on an OUT endpoint the active bit will be cleared and the NBytes value indicates the remaining buffer space that is not used Software calculates the received number of bytes by subtracting the remaining NBytes from the programmed value Bits 21 to 6 of the buffer start address If the endpoint type is set to 0 generic endpoint this address is incremented every time a packet has been successfully received transmitted If the endpoint type is set to 1 isochronous endpoint the address is not incremented Remark When receiving a SETUP token for endpoint zero the HW will only read the SETUP bytes Buffer Address offset to know where it has to store the received SETUP bytes The hardware will ignore all other fields In case the SETUP stage contains more than 8 bytes it will only write the first 8 bytes to memory A USB compliant host must never send more than 8 bytes during the SETUP stage All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 150 of 404 NXP Semiconductors UM10524
535. rrupt 3 wake up 0 0 Disabled 1 Enabled 4 PINT4 Pin interrupt 4 wake up 0 0 Disabled 1 Enabled 5 PINT5 Pin interrupt 5 wake up 0 0 Disabled 1 Enabled 6 PINT6 Pin interrupt 6 wake up 0 0 Disabled 1 Enabled 7 PINT7 Pin interrupt 7 wake up 0 0 Disabled 1 Enabled 31 8 Reserved z Start logic 1 interrupt wake up enable register STARTERP1 This register selects which interrupts will wake the part from deep sleep and power down modes Interrupts selected by a one in these registers must be enabled in the NVIC Table 53 The STARTERP1 register enables the WWDT interrupt the BOD interrupt the USB wake up interrupt and the two GPIO group interrupts for wake up All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 29 of 404 NXP Semiconductors U M1 0524 3 5 35 UM10524 Chapter 3 LPC1315 16 17 45 46 47 System control block Table 39 Start logic 1 interrupt wake up enable register STARTERP1 address 0x4004 8214 bit description Bit Symbol Value Description Reset value 11 0 Reserved 12 WWDTINT WWDT interrupt wake up 0 0 Disabled 1 Enabled 13 BODINT Brown Out Detect BOD interrupt wake up 0 0 Disabled 1 Enabled 18 14 Reserved 19 USB_WAKEUP USB need_clock signal wake up 0 0 Disabled 1 Enabled 20 GPIOINTO GPIO GROUPO interrupt wake up 0 0 Disabled 1 Enabled 21 GPIOINT1 GPIO GROUP 1 interrupt w
536. rs 1 hHid Handle to HID function driver 2 pSetup Pointer to setup packet recived from host 3 protocol Protocol mode 0 Boot Protocol 1 Report Protocol Returns The call back should returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_ xxx For other error conditions HID_EpIn_Hdlr ErrorCode_t ErrorCode_t USBD_HID_INIT_PARAM HID_EpIn_Hdlr USBD_HANDLE_T hUsb void data uint32_t event USBD_HANDLE_T hUsb void data uint32_t event Optional Interrupt IN endpoint event handler The application software could provide Interrupt IN endpoint event handler Application which send reports to host on interrupt endpoint should provide an endpoint event handler through this data member This data member is ignored if the interface descriptor hUsbHandle to the USB device stack dataHandle to HID function driver eventType of endpoint event See USBD_EVENT_T for more details Parameters 1 hUsb Handle to the USB device stack 2 data Handle to HID function driver 3 event Type of endpoint event See USBD_EVENT_T for more details Returns The call back should return ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_xxx For other error con
537. rved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 81 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration 7 4 21 I O configuration for pin PIOO_20 Table 76 I O configuration for pin PIOO_20 CT16B1_CAP0 PIO0_20 address 0x4004 4050 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x2 to 0x7 are reserved 0 0x0 PIOO_20 0x1 CT16B1_CAPO 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 00 Inactive no pull down pull up resistor enabled 01 Pull down resistor enabled 10 Pull up resistor enabled 11 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 22 I O configuration for pin PIOO 21 Table 77 I O configuration for pin PlIOO_21 CT16B1_MATO MOSI1 PIO0_21 address 0x4004 4054 bit description
538. s LOW if pinned out 10 Set the corresponding External Match bit output to 1 CT32Bn_MATm pin is HIGH if pinned out 11 Toggle the corresponding External Match bit output 16 7 11 Count Control Register The Count Control Register CTCR is used to select between Timer and Counter mode and in Counter mode to select the pin and edges for counting When Counter Mode is chosen as a mode of operation the CAP input selected by the CTCR bits 3 2 is sampled on every rising edge of the PCLK clock After comparing two consecutive samples of this CAP input one of the following four events is recognized rising edge falling edge either of edges or no changes in the level of the selected CAP input Only if the identified event occurs and the event corresponds to the one selected by bits 1 0 in the CTCR register will the Timer Counter register be incremented Effective processing of the externally supplied clock to the counter has some limitations Since two successive rising edges of the PCLK clock are used to identify only one edge on the CAP selected input the frequency of the CAP input can not exceed one half of the PCLK clock Consequently duration of the HIGH LOWLOW levels on the same CAP input in this case can not be shorter than 1 PCLK All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 319 of 404 NXP Semiconductors U M1 0524
539. s as this data member of the parameter structure Application which like the default handler should set this data member to zero before calling the USBD_DFU_API Init Remark Parameters 1 hUsb Handle to the USB device stack 2 data Pointer to the data which will be passed when callback function is called by the stack 3 event Type of endpoint event See USBD_EVENT_T for more details Returns The call back should returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR _USBD_xxx For other error conditions 11 5 32 USBD_HID_API HID class API functions structure This structure contains pointers to all the function exposed by HID function driver module UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 181 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 197 USBD_HID_API class structure Member Description GetMemSize uint32_t uint32_t USBD_HID_API GetMemSize USBD_HID_INIT_PARAM_T param Function to determine the memory required by the HID function driver module This function is called by application layer before calling pUsbApi gt hid gt Init to allocate memory used by HID function driver module The applicati
540. s cleared by software When a serial interrupt routine is entered the status code in STAT is used to branch to the appropriate service routine For each status code the required software action and details of the following serial transfer are given in tables from Table 261 to Table 267 14 10 1 Master Transmitter mode In the master transmitter mode a number of data bytes are transmitted to a slave receiver see Figure 40 Before the master transmitter mode can be entered I2CON must be initialized as follows Table 260 CONSET used to initialize Master Transmitter mode Bit 7 6 5 4 3 2 1 0 Symbol I2EN STA STO SI AA Value 1 0 0 0 x The 2C rate must also be configured in the SCLL and SCLH registers I2EN must be set to logic 1 to enable the IC block If the AA bit is reset the 1 C block will not acknowledge its own slave address or the General Call address in the event of another device becoming master of the bus In other words if AA is reset the 12C interface cannot enter slave mode STA STO and SI must be reset UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 270 of 404 NXP Semiconductors U M1 0524 UM10524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller The master transmitter mode may now be entered by setting the STA bit The 12C logic will now test the 1 C bus and genera
541. s defined as OXOCHDMhCC where each nibble represents version number of the corresponding component CC 7 0 8bit core version number h 11 8 4bit hardware interface version number M 15 12 4bit MSC class module version number D 19 16 4bit DFU class module version number H 23 20 4bit HID class module version number C 27 24 4bit CDC class module version number H 31 28 4bit reserved 11 5 26 USBD_API_INIT_PARAM USB device stack initialization parameter data structure Table 191 USBD_API_INIT_PARAM class structure Member usb_reg_base mem_base mem_size max_num_ep pado Description uint32_tuint32_t USBD_API_INIT_PARAM usb_reg_base USB device controller s base register address uint32_tuint32_t USBD_API_INIT_PARAM mem_base Base memory location from where the stack can allocate data and buffers Remark The memory address set in this field should be accessible by USB DMA controller Also this value should be aligned on 2048 byte boundary uint32_tuint32_t USBD_API_INIT_PARAM mem_size The size of memory buffer which stack can use Remark The mem_size should be greater than the size returned by USBD_HW_API GetMemSize routine uint8_tuint8_t USBD_API_INIT_PARAM max_num_ep max number of endpoints supported by the USB device controller instance specified by uint8_tuint8_t USBD_API_INIT_PARAM pad0 3 3 USB_Reset_Event USB_CB_TUSB_CB_T USBD_API_INIT_PARAM USB_Reset_Event
542. s document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 350 of 404 NXP Semiconductors U M1 0524 20 6 Operation Chapter 20 LPC1315 16 17 45 46 47 ADC Table 329 A D Trim register TRM address 0x4001 C034 bit description Bit Symbol Description Reset value 3 0 Reserved NA 7 4 ADCOFFS Offset trim bits for ADC operation Initialized by the boot code Can 0 be overwritten by the user 11 3 TRIM Written to by boot code Can not be overwritten by the user These 1111 bits are locked after boot code write 31 12 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined UM10524 20 6 1 20 6 2 20 6 3 20 6 4 Hardware triggered conversion If the BURST bit in the ADCRO is 0 and the START field contains 010 111 the A D converter will start a conversion when a transition occurs on a selected pin or timer match signal Interrupts An interrupt is requested to the interrupt controller when the ADINT bit in the ADSTAT register is one The ADINT bit is one when any of the DONE bits of A D channels that are enabled for interrupts via the ADINTEN register are one Software can use the Interrupt Enable bit in the interrupt controller that corresponds to the ADC to control whether this results in an interrupt The result register for an A D channel that is generating an interrupt must b
543. s will be recognized if ADR O logic 1 Read data byte or 1 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free Read data byte 1 0 0 1 Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if ADR 0 logic 1 A START condition will be transmitted when the bus becomes free 0x90 Previously addressed Read data byte or X 0 0 0 Data byte will be received and NOT ACK with General Call will be returned DATA byte has been Read data byte X 0 0 1 Databyte will be received and ACK will received ACK has be fet rned been returned UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 278 of 404 NXP Semiconductors UM10524 Table 265 Slave Receiver mode continued Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller Status Status of the I2C bus Application software response Code and hardware To FromDAT ToCON STAT STA STO SI 0x98 Previously addressed Readdatabyte or 0 0 0 with General Call DATA byte has been received NOT ACK Read data byte or has been returned Read data byte or Read data byte OxA0 A STOP condition or No STDAT action Repeated START or condition has been received while still No STDAT action addressed as or SLV REC or SLV TRX
544. sable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 7 ADMODE Selects Analog Digital mode 1 0 Analog input mode 1 Digital functional mode 8 FILTR Selects 10 ns input glitch filter 0 0 Filter disabled 1 Filter enabled 9 Reserved 0 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 14 I O configuration for pin TDO PIOO_13 Table 69 I O configuration for pin TDO PIO0_13 AD2 CT32B1_MAT0 TDO_PIO0O_13 address 0x4004 4034 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x4 to 0x7 are reserved 0 0x0 TDO 0x1 PIOO_13 0x2 AD2 0x3 CT32B1_MAT0 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 75 of 404 NXP Semiconductors UM10524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 69 1 O configuration for pin TDO PIO0_13 AD2 CT32B1_MATO TDO_PIO0_13 address 0x4004 4034 bit description Bit Symbol Value Description Reset value 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up re
545. safety critical systems or equipment nor in applications where failure or UM10524 All information provided in this document is subject to legal disclaimers malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not acc
546. se Next action taken by I2C hardware Code and hardware To From DAT To CON STAT STA STO SI AA OxA8 Own SLA R hasbeen Load data byte or X 0 0 0 Last data byte will be transmitted and received ACK has ACK bit will be received been returned Load data byte X 0 0 1 Data byte will be transmitted ACK will be received 0xBO Arbitration lost in Load data byte or X 0 0 0 Last data byte will be transmitted and SLA R W as master ACK bit will be received Own SLA R has been Load data byte x 0 0 1 Data byte will be transmitted ACK bit will received ACK has ha teceived been returned 0xB8 Data byte in DAT has Load data byte or X 0 0 0 Last data byte will be transmitted and been transmitted ACK bit will be received ACK has been Load data byte X 0 0 1 Data byte will be transmitted ACK bit will received be received 0xCO Data byte in DAT has No DAT actionor 0 0 0 0 Switched to not addressed SLV mode no been transmitted recognition of own SLA or General call NOT ACK has been address received No DAT action or 0 0 0 1 Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if ADR 0 logic 1 No DAT action or 1 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free No DAT action 1 0 0 1 Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if ADR 0
547. section Once the escape code is received the ISP command handler waits for a new command Interrupts during ISP The boot block interrupt vectors located in the boot block of the flash are active after any reset All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 356 of 404 NXP Semiconductors U M1 0524 21 8 7 21 8 8 21 8 9 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming Interrupts during IAP The on chip flash memory is not accessible during erase write operations When the user application code starts executing the interrupt vectors from the user flash area are active The user should either disable interrupts or ensure that user interrupt vectors are active in RAM and that the interrupt handlers reside in RAM before making a flash erase write IAP call The IAP code does not use or disable interrupts RAM used by ISP command handler ISP commands use on chip RAM from 0x1000 017C to 0x1000 025B The user could use this area but the contents may be lost upon reset Flash programming commands use the top 32 bytes of on chip RAM The stack is located at RAM top 32 bytes The maximum stack usage is 256 bytes and grows downwards RAM used by IAP command handler Flash programming commands use the top 32 bytes of on chip RAM The maximum stack usage in the user allocated stack space is 128 bytes and
548. served 0 RO 24 DCON_C Device status connect change 0 RWC The Connect Change bit is set when the device s pull up resistor is disconnected because VBus disappeared The bit is reset by writing a one to it 25 DSUS_C Device status suspend change 0 RWC The suspend change bit is set to 1 when the suspend bit toggles The suspend bit can toggle because The device goes in the suspended state The device is disconnected The device receives resume signaling on its upstream port The bit is reset by writing a one to it 26 DRES_C Device status reset change 0 RWC This bit is set when the device received a bus reset On a bus reset the device will automatically go to the default state unconfigured and responding to address 0 The bit is reset by writing a one to it UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 141 of 404 NXP Semiconductors UM10524 Table 152 USB Device Command Status register DEVCMDSTAT address 0x4008 0000 bit description Chapter 10 LPC1345 46 47 USB2 0 device controller Bit Symbol Value Description Reset Access 27 Reserved RO 28 VBUSDEBOUNCED This bit indicates if Vous is detected or not The bit raises RO immediately when Vbus becomes high It drops to zero if Vbus is low for at least 3 ms If this bit is high and the DCon bit is set the HW will enable the pull up
549. set and the Status Register will show the status code For master mode the possible status codes are 0x40 0x48 or 0x38 For slave mode the possible status codes are 0x68 0x78 or OxBO For details refer to Table 262 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 263 of 404 NXP Semiconductors U M1 0524 UM10524 14 8 3 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller n bytes data received A Acknowledge SDA low A Not acknowledge SDA high S START condition P STOP condition E from Master to Slave D from Slave to Master Fig 33 Format of Master Receiver mode After a Repeated START condition 12C may switch to the master transmitter mode n bytes data transmitted A Acknowledge SDA low A Not acknowledge SDA high E From master to slave S START condition C From slave to master P STOP condition SLA Slave Address Sr Repeated START condition Fig 34 A Master Receiver switches to Master Transmitter after sending Repeated START Slave Receiver mode In the slave receiver mode data bytes are received from a master transmitter To initialize the slave receiver mode write any of the Slave Address registers ADRO 3 and write the 12C Control Set register CONSET as shown in Table 258 Table 258 CONSET used to configure Slave mode
550. set_power Input Param0 new system clock in MHz Param1 mode PWR_DEFAULT PWR_CPU_PERFORMANCE PWR_ EFFICIENCY PWR_LOW_CURRENT Param2 current system clock in MHz Result Result0 PWR_CMD_SUCCESS PWR_INVALID_FREQ PWR_INVALID_MODE The following definitions are needed for set_power routine calls set_power mode options define PWR_DEFAULT 0 define PWR_CPU_PERFORMANCE 1 define PWR_EFFICIENCY 2 define PWR_LOW_CURRENT 3 set_power result0 options define PWR_CMD_SUCCESS 0 define PWR_INVALID_FREQ 1 define PWR_INVALID_MODE 2 New system clock The new system clock is the clock rate at which the microcontroller will be running after either a successful execution of a clocking routine call or a similar code provided by the user This operand must be an integer between 1 to 50 MHz inclusive If a value out of this range is supplied set_power returns PWR_INVALID_FREQ and does not change the power control system Mode The input parameter mode Param1 specifies one of four available power settings If an illegal selection is provided set_power returns PWR_INVALID_MODE and does not change the power control system PWR_DEFAULT keeps the device in a baseline power setting similar to its reset state PWR_CPU_PERFORMANCE configures the microcontroller so that it can provide more processing capability to the application CPU performance is 30 better than the default option PWR_EFFICIENCY setting
551. shows pins that are associated with system control block functions Table 4 Pin summary Pin name Pin Pin description direction CLKOUT O Clockout pin PIOO and PIO1 pins Eight pins can be selected as external interrupt pins from all available GPIO pins see Table 35 3 4 Clocking and power control UM10524 See Figure 3 for an overview of the LPC1315 16 1 7 45 46 47 Clock Generation Unit CGU The LPC1315 16 1 7 45 46 47 include three independent oscillators These are the system oscillator the Internal RC oscillator IRC and the Watchdog oscillator Each oscillator can be used for more than one purpose as required in a particular application Following reset the LPC1315 16 17 45 46 47 will operate from the Internal RC oscillator until switched by software This allows systems to operate without an external crystal and the bootloader code to operate at a known frequency The SYSAHBCLKCTRL register gates the system clock to the various peripherals and memories USART and SSP have individual clock dividers to derive peripheral clocks from the main clock The main clock and the clock outputs from the IRC the system oscillator and the watchdog oscillator can be observed directly on the CLKOUT pin All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 11 of 404 NXP Semiconductors U M1 0524 Chapter 3 LPC1315
552. sideration where applicable 15 CMD_LOCKED Command is locked 16 INVALID_ CODE Unlock code is invalid 17 INVALID_BAUD_RATE Invalid baud rate setting 18 INVALID_STOP_BIT Invalid stop bit setting 19 CODE_READ_ PROTECTION __ Code read protection enabled ENABLED 21 14 IAP commands UM10524 For in application programming the IAP routine should be called with a word pointer in register rO pointing to memory RAM containing command code and parameters Result of the IAP command is returned in the result table pointed to by register r1 The user can reuse the command table for result by passing the same pointer in registers rO and r1 The parameter table should be big enough to hold all the results in case the number of results are more than number of parameters Parameter passing is illustrated in the Figure 62 The number of parameters and results vary according to the IAP command The maximum number of parameters is 5 passed to the Copy RAM to FLASH command The maximum number of results is 4 returned by the ReadUID command The command handler sends the status code INVALID COMMAND when an undefined command is received The IAP routine resides at Ox1FFF 1FFO location and it is thumb code The IAP function could be called in the following way using C Define the IAP location entry point Since the Oth bit of the IAP location is set there will be a change to Thumb instruction set when the program counter branches to this address
553. sistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 7 ADMODE Selects Analog Digital mode 1 0 Analog input mode 1 Digital functional mode 8 FILTR Selects 10 ns input glitch filter 0 0 Filter disabled 1 Filter enabled 9 Reserved 0 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 15 I O configuration for pin TRST PIOO_14 Table 70 1 O configuration for pin TRST PIO0_14 AD3 CT32B1_MAT1 TRST_PIO0_14 address 0x4004 4038 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x4 to 0x7 are reserved 0 0x0 TRST 0x1 PIOO_ 14 0x2 AD 0x3 CT32B1_MAT1 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 76 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 70 I O configuration for pin TRST PIOO_14 AD3 CT32B1_MAT1 TRST_PIOO_14 address 0x4004 4038 bit description Bit Symbol Value Description Reset value 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down
554. spikes or drops in the frequency of the output clock The recommended way of changing between divider settings is to power down the PLL adjust the divider settings and then let the PLL start up again Frequency selection The PLL frequency equations use the following parameters also see Figure 3 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 43 of 404 NXP Semiconductors U M1 0524 UM10524 3 10 4 1 3 10 4 2 Chapter 3 LPC1315 16 17 45 46 47 System control block Table 45 PLL frequency parameters Parameter System PLL FCLKIN Frequency of sys_plliclkin input clock to the system PLL from the PLL clock multiplexer see Table 15 and Table 16 FCCO Frequency of the Current Controlled Oscillator CCO 156 to 320 MHz FCLKOUT Frequency of sys_pllclkout P System PLL post divider ratio PSEL bits in PLL control registers see Table 8 and Table 10 M System PLL feedback divider register MSEL bits in the PLL control registers see Table 8 and Table 10 Normal mode In this mode the post divider is enabled giving a 50 duty cycle clock with the following frequency relations 1 Fclkout M x Fclkin FCCO 2 x P To select the appropriate values for M and P it is recommended to follow these steps 1 Specify the input clock frequency Fclkin 2 Calculate M to obtain the desired output
555. st has been completely and successfully executed 1 INVALID_ COMMAND Invalid command 2 SRC_ADDR_ERROR Source address is not on word boundary 3 DST_ADDR_ERROR Destination address is not on a correct boundary 4 SRC_ADDR_NOT_MAPPED Source address is not mapped in the memory map Count value is taken in to consideration where applicable 5 DST_ADDR_NOT_MAPPED Destination address is not mapped in the memory map Count value is taken in to consideration where applicable 6 COUNT_ERROR Byte count is not multiple of 4 or is not a permitted value 7 INVALID_SECTOR Sector number is invalid or end sector number is greater than start sector number SECTOR_NOT_BLANK Sector is not blank SECTOR_NOT_PREPARED_FOR_ Command to prepare sector for write operation WRITE_OPERATION was not executed UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 370 of 404 NXP Semiconductors U M1 0524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming Table 352 ISP Return Codes Summary Return Mnemonic Description Code 10 COMPARE_ERROR Source and destination data not equal 11 BUSY Flash programming hardware interface is busy 12 PARAM_ERROR Insufficient number of parameters or invalid parameter 13 ADDR_ERROR Address is not on word boundary 14 ADDR_NOT_MAPPED Address is not mapped in the memory map Count value is taken in to con
556. success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_ xxx For other error conditions CDC_Ep0_Hadlr ErrorCode_t ErrorCode_t USBD_CDC_INIT_PARAM CDC_Ep0_Hdlr USBD_HANDLE_T hUsb void data uint32_t event USBD_HANDLE_T hUsb void data uwint32_t event Optional user overridable function to replace the default CDC class handler The application software could override the default EPO class handler with their own by providing the handler function address as this data member of the parameter structure Application which like the default handler should set this data member to zero before calling the USBD_CDC_API Init Remark Parameters 1 hUsb Handle to the USB device stack 2 data Pointer to the data which will be passed when callback function is called by the stack 3 event Type of endpoint event See USBD_EVENT_T for more details Returns The call back should returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_ xxx For other error conditions 11 5 29 USBD_CORE_API USBD stack Core API functions structure UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 174 of 404 NXP Semiconductors U M1 0524
557. suspended and the host wakes up the device by supplying Start Of Frame pulses This is generally hooked to pull the user application out of a low power state and back into normal operating mode Remark This event is called from USB_ISR context and hence is time critical Having delays in this callback will cause other system issues USB_CB_TUSB_CB_T USBD_API_INIT_PARAM reserved_sbz Reserved parameter should be set to zero USB_CB_TUSB_CB_T USBD_API_INIT_PARAM USB_SOF_Event Event for USB Start Of Frame detection when enabled This event fires at the start of each USB frame once per millisecond in full speed mode or once per 125 microseconds in high speed mode and is synchronized to the USB bus This event is time critical it is run once per millisecond full speed mode and thus long handlers will significantly degrade device performance This event should only be enabled when needed to reduce device wake ups This event is not normally active it must be manually enabled and disabled via the USB interrupt register Remark This event is not normally active it must be manually enabled and disabled via the USB interrupt register USB_PARAM_CB_TUSB_PARAM_CB_T USBD_API_INIT_PARAM USB_WakeUpCfg Event for remote wake up configuration when enabled This event fires when the USB host request the device to configure itself for remote wake up capability The USB host sends this request to device which report remote wake up capa
558. t 31 8 Reserved user software should not write ones to reserved bits 0 The value read from a reserved bit is not defined This register controls the clock pre scaler for the baud rate generation The reset value of the register keeps the fractional capabilities of USART disabled making sure that USART is fully software and hardware compatible with USARTs not equipped with this feature The USART baud rate can be calculated as 3 PCLK UART il an DivadaVal MulVal Where UART_PCLK is the peripheral clock DLM and DLL are the standard USART baud rate divider registers and DIVADDVAL and MULVAL are USART fractional baud rate generator specific parameters 16 x 256 x UODLM UODLL x The value of MULVAL and DIVADDVAL should comply to the following conditions 1 1 lt MULVAL lt 15 2 0 lt DIVADDVAL lt 14 3 DIVADDVAL lt MULVAL The value of the FDR should not be modified while transmitting receiving data or data may be lost or corrupted If the FDR register value does not comply to these two requests then the fractional divider output is undefined If DIVADDVAL is zero then the fractional divider is disabled and the clock will not be divided UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 221 of 404 NXP Semiconductors U M1 0524 Chapter 12 LPC1315 16 17 45 46 47 USART 12 5 14 1 Baud
559. t USBD_HANDLE_T hUsb uint32_t EPNum uint32_t event_type uint32_t enable USBD_HANDLE_T hUsb uint32_t EPNum uint32_t event_type uint32_t enable 11 5 35 USBD_MSC_API UM10524 MSC class API functions structure This module exposes functions which interact directly with USB device controller hardware All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 197 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 200 USBD_MSC_API class structure Member Description GetMemSize uint32_t uint32_t USBD_MSC_API GetMemSize USBD_MSC_INIT_PARAM_T param Function to determine the memory required by the MSC function driver module This function is called by application layer before calling pUsbApi gt msc gt Init to allocate memory used by MSC function driver module The application should allocate the memory which is accessible by USB controller DMA controller Remark Some memory areas are not accessible by all bus masters Parameters 1 param Structure containing MSC function driver module initialization parameters Returns Returns the required memory size in bytes init ErrorCode_t ErrorCode_t USBD_MSC_API init USBD_HANDLE_T hUsb USBD_MSC_INIT_PARAM_T param Function to initialize MSC function driver module This function is called by application layer to in
560. t description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x2 to 0x7 are reserved 0 0x0 PIOO_4 open drain pin 0x1 12C SCL open drain pin 7 3 Reserved UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 68 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 60 I O configuration for pin PIOO_4 SCL PIO0_4 address 0x4004 4010 bit description Bit Symbol Value Description Reset value 9 8 I2CMODE Selects 12C mode see Section 6 3 8 Select Standard 0 mode I2CMODE 0 default or Standard I O functionality I2CMODE 1 if the pin function is GPIO FUNC 0 0x0 Standard mode Fast mode 12C 0x1 Standard I O functionality 0x2 Fast mode Plus l2C 0x3 Reserved 31 10 Reserved 7 4 6 I O configuration for pin PIOO_5 Table 61 1 O configuration for pin PIOO_5 SDA PIO0_5 address 0x4004 4014 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x2 to 0x7 are reserved 0 0x0 PIO0_5 open drain pin 0x1 12C SDA open drain pin 7 3 Reserved 9 8 I2CMODE Selects 12C mode see Section 6 3 8 Select Standard 0 mode I2CMODE 00 default or Standard I O functionality IZCMODE 01 if the pin function is GPIO FUNC 0 0x0 Standard mode Fast mode 12C 0x1 Standard I
561. t flag will be set Any bit or combination of bits can be removed from this comparison i e forced to compare by writing a 1 to the corresponding bit s in the MASK and MASK_H registers If the RITENCLR bit is low default state a valid comparison ONLY causes the interrupt flag to be set It has no effect on the count sequence Counting continues as usual When the counter reaches OxFFFF FFFF FFFF it rolls over to 0 on the next clock and continues counting If the RITENCLR bit is set to 1 a valid comparison will also cause the counter to be reset to zero Counting will resume from there on the next clock edge Counting can be halted in software by writing a 0 to the RITEN bit Counting will also be halted when the processor is halted for debugging provided the RITENBR bit is set Both the RITEN and RITENBR bits are set on reset The interrupt flag can be cleared in software by writing a 1 to theRITINT bit Software must stop the counter before reloading it with a new value The counter COUNTER COUNTER_H COMPVAL COMPVAL_H registers MASK MASK_H registers and the CTRL register can all be read by software at any time All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 344 of 404 UM10524 Chapter 20 LPC1315 16 17 45 46 47 ADC Rev 1 17 February 2012 User manual 20 1 How to read this chapter The ADC block is ide
562. t input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin All information provided in this document is subject to legal disclaimers reads as 0 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 Reserved 0x1 NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 66 of 404 NXP Semiconductors U M1 0524 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 57 I O configuration for pin PlOO_1 CLKOUT CT32B0_MAT2 USB_FTOGGLE PIO0_1 address 0x4004 4004 bit description Bit Symbol Value Description Reset value 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 3 I O configuration for pin PIOO_ 2 Table 58 I O configuration for pin PlO0O_2 SSEL0 CT16B0_CAPO0 PIOO_2 address 0x4004 4008 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x3 to 0x7 are reserved 0 0x0 PIOO_2 0x1 SSELO 0x2 CT16BO_CAPO 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0
563. t is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 3 of 404 NXP Semiconductors UM10524 UM10524 Chapter 1 LPC1315 16 17 45 46 47 Introductory information Debug options Standard JTAG test interface for BSDL Serial Wire Debug Support for ETM ARM Cortex M3 debug time stamping Digital peripherals Up to 51 General Purpose I O GPIO pins with configurable pull up pull down resistors repeater mode input inverter and pseudo open drain mode Eight pins support programmable glitch filter Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources Two GPIO grouped interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins High current source output driver 20 mA on one pin P0O_7 High current sink driver 20 mA on true open drain pins PO_4 and P0_5 Four general purpose counter timers with a total of up to 8 capture inputs and 13 match outputs Programmable Windowed WatchDog Timer WWDT with a internal low power WatchDog Oscillator WDO Repetitive Interrupt Timer RI Timer Analog peripherals 12 bit ADC with eight input channels and sampling rates of up to 500 kSamples s Serial interfaces USB 2 0 full speed device controller LPC 1345 46 47 with on chip ROM based USB driver library USART with fractional baud rate generation internal FIFO a full modem co
564. t is time to issue a remote wake up turn on the USB clock and enable the USB clock source 3 Force the USB clock on by writing a 1 to bit AP_CLK Table 36 bit 0 in the USBCLKCTRL register All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 154 of 404 NXP Semiconductors U M1 0524 Chapter 10 LPC 1345 46 47 USB2 0 device controller 4 Write a 0 to the DSUS bit in the DSVCMD_STAT register 5 Wait until the USB leaves the suspend state by polling the DSUS bit in the DSVCMD_STAT register DSUS 0 6 Clear the AP_CLK bit Table 36 bit 0 in the USBCLKCTRL to enable automatic USB clock control UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 155 of 404 UM10524 Chapter 11 LPC1345 46 47 USB on chip drivers Rev 1 17 February 2012 User manual 11 1 How to read this chapter 11 2 Introduction The USB on chip drivers are available on parts LPC 1345 46 47 The boot ROM contains a USB driver to simplify the USB application development The USB driver implements the Communication Device Class CDC the Human Interface Device HID and the Mass Storage Device MSC device class The USB on chip drivers support composite device 11 3 USB driver functions UM10524 The USB device
565. t output open drain High current sink only if 2C Fast mode Plus is selected in the I O configuration register PIOO_6 R 29 22 15 BI 1 PU I O PIO0_6 General purpose digital input output pin SCKO R Reserved 1 0 SCKO Serial clock for SSPO PIOO_7 CTS 30 23 16 1 PU VO PIO0_7 General purpose digital input output pin high current output driver CTS Clear To Send input for USART PIO0_8 MISOO 36 27 17 B 1 PU lO PIO0_8 General purpose digital input output pin CT16BO_MATO 0 MISOO Master In Slave Out for SSPO O CT16B0_MAT0 Match output 0 for 16 bit timer 0 PIO0_9 MOSI0 37 28 18 Bl IPU VO PIO0_9 General purpose digital input output pin CT16B0_MAT1 z O MOSIO Master Out Slave In for SSPO SWO O CT16B0_MAT1 Match output 1 for 16 bit timer 0 O SWO Serial wire trace output SWCLK PIOO_10 SCKO 38 29 19 BI PU SWCLK Serial wire clock and test clock TCK for JTAG CT16B0_MAT2 interface O PIO0_10 General purpose digital input output pin O SCKO Serial clock for SSPO O CT16B0_MAT2 Match output 2 for 16 bit timer 0 TDI PIOO_11 ADO 42 32 21 Bl PU I TDI Test Data In for JTAG interface CT32B0_MAT3 1 0 PIO0_11 General purpose digital input output pin l ADO A D converter input 0 O CT32B0_MAT3 Match output 3 for 32 bit timer 0 TMS Test Mode Select for JTAG interface 1 0 PIO_12 General purpose digital input output
566. t period The time out period is the same for master and slave modes and is determined by the SSP bit rate 32 bits at PCLK CPSDVSR x SCR 1 2 RXIM Software should set this bit to enable interrupt when the Rx FIFO is at 0 least half full 3 TXIM Software should set this bit to enable interrupt when the Tx FIFO is at 0 least half empty 31 4 Reserved user software should not write ones to reserved bits The NA value read from a reserved bit is not defined SSP SPI Raw Interrupt Status Register This read only register contains a 1 for each interrupt condition that is asserted regardless of whether or not the interrupt is enabled in the IMSC registers Table 240 SSP SPI Raw Interrupt Status register RIS address 0x4004 0018 SSPO and 0x4005 8018 SSP1 bit description Symbol Description Reset value 0 RORRIS This bit is 1 if another frame was completely received while the 0 RxFIFO was full The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs 1 RTRIS This bit is 1 if the Rx FIFO is not empty and has not been read fora 0 time out period The time out period is the same for master and slave modes and is determined by the SSP bit rate 32 bits at PCLK CPSDVSR x SCR 1 2 RXRIS This bit is 1 if the Rx FIFO is at least half full 0 3 TXRIS This bit is 1 if the Tx FIFO is at least half empty 1 31 4 Reserved user software should not write ones to reserved b
567. t setting for echo command is ON When ON the ISP command handler sends the received serial data back to the host Example A 0 lt CR gt lt LF gt turns echo off 21 13 4 Write to RAM lt start address gt lt number of bytes gt The host should send the data only after receiving the CMD_SUCCESS return code The host should send the check sum after transmitting 20 UU encoded lines The checksum is generated by adding raw data before UU encoding bytes and is reset after transmitting 20 UU encoded lines The length of any UU encoded line should not exceed 61 characters bytes i e it can hold 45 data bytes When the data fits in less than 20 UU encoded lines then the check sum should be of the actual number of bytes sent The ISP command handler compares it with the check sum of the received bytes If the check sum matches the ISP command handler responds with OK lt CR gt lt LF gt to continue further transmission If the check sum does not match the ISP command handler responds with RESEND lt CR gt lt LF gt In response the host should retransmit the bytes UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 364 of 404 NXP Semiconductors U M1 0524 UM10524 21 13 5 21 13 6 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming Table 340 ISP Write to RAM command Command Ww Input Start Address R
568. t to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 274 of 404 NXP Semiconductors U M1 0524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller Table 262 Master Receiver mode Status Status of the I2C bus Application software response Next action taken by I2C hardware Code and hardware To From DAT To CON STAT STA STO SI AA 0x08 A START condition Load SLA R x 0 0 X SLA R will be transmitted ACK bit will be has been transmitted received 0x10 A Repeated START Load SLA R or X 0 0 X As above condition has been Load SLA W X 0 0 X SLA W will be transmitted the I2C block transmitted will be switched to MST TRX mode 0x38 Arbitration lostin NOT No DAT actionor 0 0 0 X 12C bus will be released the 12C block will ACK bit enter slave mode No DAT action 1 0 0 x A START condition will be transmitted when the bus becomes free 0x40 SLA R has been No DAT actionor 0 0 0 0 Data byte will be received NOT ACK bit transmitted ACK has will be returned been received No DAT action 0 0 0 1 Databyte will be received ACK bit will be returned 0x48 SLA R has been No DAT actionor 1 0 0 X Repeated START condition will be transmitted NOT ACK transmitted has been received No DAT actionor 0 1 0 X STOP condition will be transmitted STO flag will be reset No DAT action 1 1 0 X STOP condition followed by a START condition will be transmitted STO flag will be reset 0x50 Data byte
569. t to next in line 3 ERR_USBD_ xxx For other error conditions All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 184 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 198 USBD_HID_INIT_PARAM class structure Member HID_GetPhysDesc Description ErrorCode_t ErrorCode_t USBD_HID_INIT_PARAM HID_GetPhysDesc USBD_HANDLE_T hHid USB_SETUP_PACKET pSetup uint8_t pBuf uint16_t length USBD_HANDLE_T hHid USB_SETUP_PACKET pSetup uint8_t pBuf uintl6 _t length Optional callback function to handle HID_GetPhysDesc request The application software could provide this callback HID_GetPhysDesc handler to handle get physical descriptor requests sent by the host When host requests Physical Descriptor set 0 application should return a special descriptor identifying the number of descriptor sets and their sizes A Get_Descriptor request with the Physical Index equal to 1 should return the first Physical Descriptor set A device could possibly have alternate uses for its items These can be enumerated by issuing subsequent Get_Descriptor requests while incrementing the Descriptor Index A device should return the last descriptor set to requests with an index greater than the last number defined in the HID descriptor Remark Applications which don t have physical descriptor sho
570. te Three Code Read Protection CRP levels can be enabled for flash images updated through USB see Section 21 12 for details The volume label on the MSCD indicates the CRP status All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 357 of 404 NXP Semiconductors UM10524 UM10524 21 9 1 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming Table 331 CRP levels for USB boot images CRP status Volume label No CRP CRP DISABLD Description The user flash can be read or written CRP1 CRP1 ENABLD The user flash content cannot be read but can be updated The flash memory sectors are updated depending on the new firmware image CRP2 CRP2 ENABLD The user flash content cannot be read but can be updated The entire user flash memory is erased before writing the new firmware image CRP3 CRP3 ENABLD The user flash content cannot be read or updated The bootloader always executes the user application if valid Usage note When programming flash images via Flash Magic or Serial Wire Debugger SWD the user code valid signature is automatically inserted by the programming utility When using USB ISP the user code valid signature must be either part of the vector table or the axf or binary file must be post processed to insert the checksum All information provided in this document is subject to legal disclaim
571. te a START condition as soon as the bus becomes free When a START condition is transmitted the serial interrupt flag SI is set and the status code in the status register STAT will be 0x08 This status code is used by the interrupt service routine to enter the appropriate state service routine that loads DAT with the slave address and the data direction bit SLA W The SI bit in CON must then be reset before the serial transfer can continue When the slave address and the direction bit have been transmitted and an acknowledgment bit has been received the serial interrupt flag SI is set again and a number of status codes in STAT are possible There are 0x18 0x20 or 0x38 for the master mode and also 0x68 0x78 or OxBO if the slave mode was enabled AA logic 1 The appropriate action to be taken for each of these status codes is detailed in Table 261 After a Repeated START condition state 0x10 The 12C block may switch to the master receiver mode by loading DAT with SLA R All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 271 of 404 UM10524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller NXP Semiconductors Table 261 Master Transmitter mode Status Status of the I2C bus Application software response Next action taken by I2C hardware Code andinardware TolFromDAT ToCON I2CSTAT STA STO SI AA 0x08
572. ten This address should be a 256 byte boundary Param1 SRC Source RAM address from which data bytes are to be read This address should be a word boundary Param2 Number of bytes to be written Should be 256 512 1024 4096 Param3 System Clock Frequency CCLKk in kHz CMD_SUCCESS SRC_ADDR_ERROR Address not a word boundary DST_ADDR_ERROR Address not on correct boundary SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR Byte count is not 256 512 1024 4096 SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION BUSY None This command is used to program the flash memory The affected sectors should be prepared first by calling Prepare Sector for Write Operation command The affected sectors are automatically protected again once the copy command is successfully executed The boot sector can not be written by this command Also see Section 21 6 for the number of bytes that can be written 21 14 3 Erase Sector s Table 356 IAP Erase Sector s command Command Input Return Code Result Description Erase Sector s Command code 52 decimal Param0 Start Sector Number Param1 End Sector Number should be greater than or equal to start sector number Param2 System Clock Frequency CCLKk in kHz CMD_SUCCESS BUSY SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION INVALID_SECTOR None This command is used to erase a sector or multiple sectors of on chip flash memory The boot sector can not be
573. ter SYSMEMREMAP The system memory remap register selects whether the exception vectors are read from boot ROM flash or SRAM By default the flash memory is mapped to address 0x0000 0000 When the MAP bits in the SYSMEMREMAP register are set to 0x0 or 0x1 the boot ROM or RAM respectively are mapped to the bottom 512 bytes of the memory map addresses 0x0000 0000 to 0x0000 0200 Table 6 System memory remap SYSMEMREMAP address 0x4004 8000 bit description Bit Symbol Value Description Reset value 1 0 MAP System memory remap Value 0x3 is reserved 0x2 0x0 Boot Loader Mode Interrupt vectors are re mapped to Boot ROM 0x1 User RAM Mode Interrupt vectors are re mapped to Static RAM 0x2 User Flash Mode Interrupt vectors are not re mapped and reside in Flash 31 2 Reserved 3 5 2 Peripheral reset control register PRESETCTRL This register allows software to reset specific peripherals A 0 in an assigned bit in this register resets the specified peripheral A 1 negates the reset and allows peripheral operation Remark Before accessing the SSP and 12C peripherals write a 1 to this register to ensure that the reset signals to the SSP and 12C are de asserted UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 14 of 404 NXP Semiconductors U M1 0524 3 5 3 3 5 4 Chapter 3 LPC1315 16 17 45 46 47 System control block Table
574. tered the SI bit will be set For a complete list of status codes refer to tables from Table 261 to Table 266 I2C Data register DAT This register contains the data to be transmitted or the data just received The CPU can read and write to this register only while it is not in the process of shifting a byte when the SI bit is set Data in DAT register remains stable as long as the SI bit is set Data in DAT register is always shifted from right to left the first bit to be transmitted is the MSB bit 7 and after a byte has been received the first bit of received data is located at the MSB of the DAT register Table 247 I2C Data register DAT 0x4000 0008 bit description Bit Symbol Description Reset value 7 0 Data This register holds data values that have been received or areto 0 be transmitted 31 8 Reserved The value read from a reserved bit is not defined All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 257 of 404 NXP Semiconductors U M1 0524 UM10524 14 7 4 14 7 5 14 7 5 1 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller IC Slave Address register 0 ADRO This register is readable and writable and are only used when an 12C interface is set to slave mode In master mode this register has no effect The LSB of the ADR register is the General Call bit When this bit is set the G
575. ters control setting of bits in the CON register that controls operation of the I2C interface Writing a one to a bit of this register causes the corresponding bit in the 12C control register to be set Writing a zero has no effect Table 245 I2C Control Set register CONSET address 0x4000 0000 bit description Bit Symbol 1 0 AA SI STO Description Reset value Reserved User software should not write ones to reserved bits The NA value read from a reserved bit is not defined Assert acknowledge flag 12C interrupt flag STOP flag All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 255 of 404 NXP Semiconductors U M1 0524 UM10524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller Table 245 I2C Control Set register CONSET address 0x4000 0000 bit description Bit Symbol Description Reset value 5 STA START flag 0 6 I2EN 12C interface enable 0 31 7 Reserved The value read from a reserved bit is not defined I2EN 12C Interface Enable When I2EN is 1 the 12C interface is enabled I2EN can be cleared by writing 1 to the I2ENC bit in the CONCLR register When I2EN is 0 the 12C interface is disabled When I2EN is 0 the SDA and SCL input signals are ignored the 12C block is in the not addressed slave state and the STO bit is forced to 0 I2EN should
576. the DLL 0x00 register determines the baud rate of the USART 31 8 Reserved USART Interrupt Enable Register when DLAB 0 The IER is used to enable the various USART interrupt sources Table 208 USART Interrupt Enable Register when DLAB 0 IER address 0x4000 8004 bit description Bit Symbol Value Description Reset value 0 RBRINTEN RBR Interrupt Enable Enables the Receive Data Available 0 interrupt It also controls the Character Receive Time out interrupt 0 Disable the RDA interrupt 1 Enable the RDA interrupt 1 THREINTEN THRE Interrupt Enable Enables the THRE interrupt The 0 status of this interrupt can be read from LSR 5 0 Disable the THRE interrupt 1 Enable the THRE interrupt 2 RLSINTEN Enables the Receive Line Status interrupt The status of 0 this interrupt can be read from LSR 4 1 0 Disable the RLS interrupt 1 Enable the RLS interrupt 3 MSINTEN Enables the Modem Status interrupt The components of 0 this interrupt can be read from the MSR 0 Disable the MS interrupt 1 Enable the MS interrupt All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 206 of 404 NXP Semiconductors U M1 0524 UM10524 12 5 5 Chapter 12 LPC1315 16 17 45 46 47 USART Table 208 USART Interrupt Enable Register when DLAB 0 IER address 0x4000 8004 bit description continued Bit S
577. the SO pin CS remains LOW for the duration of the frame transmission The SI pin remains tri stated during this transmission The off chip serial slave device latches each control bit into its serial shifter on the rising edge of each SK After the last bit is latched by the slave device the control byte is decoded during a one clock wait state and the slave responds by transmitting data back to the SSP SPI Each bit is driven onto SI line on the falling edge of SK The SSP SPI in All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 250 of 404 NXP Semiconductors U M1 0524 UM10524 13 7 3 1 Chapter 13 LPC1315 16 17 45 46 47 SSP SPI turn latches each bit on the rising edge of SK At the end of the frame for single transfers the CS signal is pulled HIGH one clock period after the last bit has been latched in the receive serial shifter that causes the data to be transferred to the receive FIFO Note The off chip slave device can tri state the receive line either on the falling edge of SK after the LSB has been latched by the receive shiftier or when the CS pin goes HIGH For continuous transfers data transmission begins and ends in the same manner as a single transfer However the CS line is continuously asserted held LOW and transmission of data occurs back to back The control byte of the next frame follows directly a
578. the oscillator function and generates an analog clock Fekana The FREQSEL field selects Feikana between 0 5 and 3 4 MHz In the digital part Folkana iS divided to produce the oscillator output clock under the control of the DIVSEL field The output clock frequency can be calculated as wdt_osc_clk Fclkana 2 x 1 DIVSEL Remark Any non zero setting of the FREQSEL field will yield a Feikana value within 40 of the listed frequency value Table 13 Watchdog oscillator control WDTOSCCTRL address 0x4004 8024 bit description Bit Symbol Value Description Reset value 4 0 DIVSEL Select divider for Fclkana 0 wdt_osc_clk Fclkana 2 x 1 DIVSEL 00000 2 x 1 DIVSEL 2 00001 2 x 1 DIVSEL 4 to 11111 2 x 1 DIVSEL 64 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 17 of 404 NXP Semiconductors UM10524 UM10524 3 5 9 Chapter 3 LPC1315 16 17 45 46 47 System control block Table 13 Watchdog oscillator control WDTOSCCTRL address 0x4004 8024 bit description Bit Symbol Value Description 8 5 FREQSEL 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 OxA 0xB OxC 0OxD OxE OxF 31 9 Reset value Select watchdog oscillator analog output frequency 0 Fclkana Value 0x0 is reserved Operation is undefined for this value Startup code should program a non zero value in
579. the state of pins regardless of their direction or alternate functions Masked I O A port s MASK register defines which of its pins should be accessible in its MPORT register Zeroes in MASK enable the corresponding pins to be read from and written to MPORT Ones in MASK force a pin to read as 0 and its output bit to be unaffected by writes to MPORT When a port s MASK register contains all zeros its PORT and MPORT registers operate identically for reading and writing Users of previous NXP devices with similar GPIO blocks should be aware of an incompatibility on the LPC11A1x writing to the SET CLR and NOT registers is not affected by the MASK register On previous devices these registers were masked Applications in which interrupts can result in Masked GPIO operation or in task switching among tasks that do Masked GPIO operation must treat code that uses the Mask register as a protected restricted region This can be done by interrupt disabling or by using a semaphore The simpler way to protect a block of code that uses a MASK register is to disable interrupts before setting the MASK register and re enable them after the last operation that uses the MPORT or MASK register More efficiently software can dedicate a semaphore to the MASK registers and set capture the semaphore controlling exclusive use of the MASK registers before setting the MASK registers and release the semaphore after the last operation that uses the MPORT
580. the transition from master transmitter to slave receiver is made with the correct data in DAT Arbitration and synchronization logic In the master transmitter mode the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the 1 C bus If another device on the bus overrules a logic 1 and pulls the SDA line low arbitration is lost and the 12C block immediately changes from master transmitter to slave receiver The 12C block will continue to output clock pulses on SCL until transmission of the current serial byte is complete Arbitration may also be lost in the master receiver mode Loss of arbitration in this mode can only occur while the 12C block is returning a not acknowledge logic 1 to the bus Arbitration is lost when another device on the bus pulls this signal low Since this can occur only at the end of a serial byte the 12C block generates no further clock pulses Figure 38 shows the arbitration procedure All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 267 of 404 NXP Semiconductors U M1 0524 UM10524 14 9 7 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller 1 1 2 i 7 3 gt SoL ine LPLELE PLL 1 Another device transmits serial data 2 Another device overrules a logic dotted line transmitted this 12C master by pulling the SDA line low Arbitrat
581. tion 342 Table 317 RI Control register CTRL address 0x4006 4008 bit description 342 Table 318 RI Counter register COUNTER address 0x4006 400C bit description 343 Table 319 RI Compare Value MSB register COMPVAL_H address 0x4006 4010 bit description 343 Table 320 RI Mask MSB register MASK_H address 0x4006 4014 bit description 343 Table 321 RI Counter MSB register COUNTER_H address 0x4006 4018 bit description 343 Table 322 ADC pin description 346 Table 323 Register overview ADC base address 0x4001 GOOO seridir RS te aaike mnene eia 346 Table 324 A D Control Register CR address 0x4001 C000 bit description 347 Table 325 A D Global Data Register GDR address 0x4001 C004 bit description 349 Table 326 A D Interrupt Enable Register INTEN address 0x4001 COOC bit description 349 Table 327 A D Data registers DRO to DR7 addresses 0x4001 C010 to 0x4001 C02C bit description 0 0 cee eee 350 Table 328 A D Status Register STAT address 0x4001 C030 bit description 350 Table 329 A D Trim register TRM address 0x4001 C034 bit description 00085 351 Table 330 LPC1315 16 17 45 46 47 flash configurations eee eee eee 353 Table 331 CRP levels for USB boot images 358 Table 332 LPC131
582. to one USB wake up Waking up from Deep sleep and Power down modes on USB activity To allow the LPC1315 16 17 45 46 47 to wake up from Deep sleep or Power down mode on USB activity complete the following steps 1 Set bit AP_CLK in the USBCLKCTRL register Table 36 to 0 default to enable automatic control of the USB need_clock signal 2 Wait until USB activity is suspended by polling the DSUS bit in the DSVCMD_STAT register DSUS 1 3 The USB need_clock signal will be deasserted after another 2 ms Poll the USBCLKST register until the USB need_clock status bit is 0 Table 37 4 Once the USBCLKST register returns 0 enable the USB activity wake up interrupt in the NVIC 30 and clear it 5 Set bit 1 in the USBCLKCTRL register to 1 to trigger the USB activity wake up interrupt on the rising edge of the USB need_clock signal 6 Enable the wake up from Deep sleep or Power down modes on this interrupt by enabling the USB need_clock signal in the STARTERP1 register Table 39 bit 19 7 Enter Deep sleep or Power down modes by writing to the PCON register 8 Execute a WFI instruction The LPC1315 16 1 7 45 46 47 will automatically wake up and resume execution on USB activity Remote wake up To issue a remote wake up when the USB activity is suspended complete the following steps 1 Set bit AP_CLK in the USBCLKCTRL register to 0 Table 36 default to enable automatic control of the USB need_clock signal 2 When i
583. to 0x10FC Word pin registers port 1 ext word 32 bit Table 133 DIRO R W 0x2000 Direction registers port 0 0 word 32 bit Table 134 DIR1 R W 0x2004 Direction registers port 1 0 word 32 bit Table 135 MASKO R W 0x2080 Mask register port 0 0 word 82 bit Table 136 MASK1 R W 0x2084 Mask register port 1 0 word 32 bit Table 137 PINO R W 0x2100 Port pin register port 0 ext word 32 bit Table 138 PIN1 R W 0x2104 Port pin register port 1 ext word 32 bit Table 139 MPINO R W 0x2180 Masked port register port 0 ext word 32 bit Table 140 MPIN1 R W 0x2184 Masked port register port 1 ext word 32 bit Table 141 SETO R W 0x2200 Write Set register for port 0 0 word 82 bit Table 142 Read output bits for port 0 SET1 R W 0x2204 Write Set register for port 1 0 word 82 bit Table 143 Read output bits for port 1 CLRO WO 0x2280 Clear port 0 NA word 32 bit Table 144 CLR1 WO 0x2284 Clear port 1 NA word 32 bit Table 145 NOTO WO 0x2300 Toggle port 0 NA word 32 bit Table 146 NOT1 WO 0x2304 Toggle port 1 NA word 32 bit Table 147 1 ext indicates that the data read after reset depends on the state of the pin which in turn may depend on an external source 9 5 1 GPIO pin interrupts block register description 9 5 1 1 Pin interrupt mode register For each of the 8 pin interrupts selected in the PINTSELn registers see Table 35 one bit in the ISEL register determines whether the interrupt is edge or level sensitive UM10524 All information pro
584. to be 0 The bootloader code checksums the first 8 locations in sector 0 of the flash If the result is 0 then execution control is transferred to the user code If the signature is not valid the auto baud routine synchronizes with the host via the serial port UART If the UART is selected the host should send a Ox3F as a synchronization character and wait for a response The host side serial port settings should be 8 data bits 1 stop bit and no parity The auto baud routine measures the bit time of the received synchronization character in terms of its own frequency and programs the baud rate generator of the serial port It also sends an ASCII string Synchronized lt CR gt lt LF gt to the host In response to this host should send the same string Synchronized lt CR gt lt LF gt The auto baud routine looks at the received characters to verify synchronization If synchronization is verified then OK lt CR gt lt LF gt string is sent to the host Host should respond by sending the crystal frequency in kHz at which the part is running For example if the part is running at 10 MHz the response from the host should be 10000 lt CR gt lt LF gt OK lt CR gt lt LF gt string is sent to the host after receiving the crystal frequency If synchronization is not verified then the auto baud routine waits again for a synchronization character For auto baud to work correctly in case of user invoked ISP the CCLK frequency shoul
585. to clear the interrupt prior to exiting the Interrupt Service Routine The USART RLS interrupt IIR 3 1 011 is the highest priority interrupt and is set whenever any one of four error conditions occur on the USART RX input overrun error OE parity error PE framing error FE and break interrupt BI The USART Rx error condition that set the interrupt can be observed via LSR 4 1 The interrupt is cleared upon a LSR read The USART RDA interrupt IIR 3 1 010 shares the second level priority with the CTI interrupt IIR 3 1 110 The RDA is activated when the USART Rx FIFO reaches the trigger level defined in FCR7 6 and is reset when the USART Rx FIFO depth falls below the trigger level When the RDA interrupt goes active the CPU can read a block of data defined by the trigger level The CTI interrupt IIR 3 1 110 is a second level interrupt and is set when the USART Rx FIFO contains at least one character and no USART Rx FIFO activity has occurred in 3 5 to 4 5 character times Any USART Rx FIFO activity read or write of USART RSR will clear the interrupt This interrupt is intended to flush the USART RBR after a message has been received that is not a multiple of the trigger level size For example if a 105 character message was to be sent and the trigger level was 10 characters the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts depending on the service routine resu
586. to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 289 of 404 NXP Semiconductors U M1 0524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller 6 Write 0x04 to CONSET to set the AA bit 7 Write 0x08 to CONCLR to clear the SI flag 8 Increment Master Transmit buffer pointer 9 Exit 14 11 6 4 State 0x30 Data has been transmitted NOT ACK received A STOP condition will be transmitted 1 Write 0x14 to CONSET to set the STO and AA bits 2 Write 0x08 to CONCLR to clear the SI flag 3 Exit 14 11 6 5 State 0x38 Arbitration has been lost during Slave Address Write or data The bus has been released and not addressed Slave mode is entered A new START condition will be transmitted when the bus is free again 1 Write 0x24 to CONSET to set the STA and AA bits 2 Write 0x08 to CONCLR to clear the SI flag 3 Exit 14 11 7 Master Receive states 14 11 7 1 State 0x40 Previous state was State 08 or State 10 Slave Address Read has been transmitted ACK has been received Data will be received and ACK returned 1 Write 0x04 to CONSET to set the AA bit 2 Write 0x08 to CONCLR to clear the SI flag 3 Exit 14 11 7 2 State 0x48 Slave Address Read has been transmitted NOT ACK has been received A STOP condition will be transmitted 1 Write 0x14 to CONSET to set the STO and AA bits 2 Write 0x08 to CONCLR to clear the SI flag 3 Exit 14 11 7 3 State 0x50 Dat
587. to noise XTALOUT should be left floating UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 111 of 404 NXP Semiconductors U M1 0524 Chapter 8 LPC1315 16 17 45 46 47 Pin configuration Table 109 Pin description LPC1345 46 47 with USB Symbol Description oO Bee 3 eo 2 amp l l I S RESET PIO0_0 4 3 2 B PU I RESET External reset input with 20 ns glitch filter A LOW going pulse as short as 50 ns on this pin resets the device causing I O ports and peripherals to take on their default states and processor execution to begin at address 0 This pin also serves as the debug select input LOW level selects the JTAG boundary scan HIGH level selects the ARM SWD debug mode 1 0 PIO0_0 General purpose digital input output pin PIOO_1 CLKOUT 5 4 3 B KPU O PIO0_1 General purpose digital input output pin A CT32B0_MAT2 LOW level on this pin during reset starts the ISP USB_FTOGGLE command handler or the USB device enumeration O CLKOUT Clockout pin O CT32B0_MAT2 Match output 2 for 32 bit timer 0 O USB_FTOGGLE USB 1 ms Start of Frame signal PIOO_2 SSEL0 13 10 8 B IPU O PIO0_2 General purpose digital input output pin CT16B0_CAP0 VO SSELO Slave select for SSPO CT16B0_CAP0 Capture input 0 for 16 bit timer 0 PIO0_3 USB_VBUS 19 14 9 B PU VO PIO0_3 General pu
588. to one to enable the timer reset when the timer value matches the value of the corresponding match register PWM1 MAT1 J MR1 41 l l i I l l l l PWM2 MAT2 l l l MR2 100 l l T l Ao A d d 0 41 65 100 counter is reset Fig 47 Sample PWM waveforms with a PWM cycle length of 100 selected by MR3 and MAT3 0 enabled as PWM outputs by the PWCON register 15 8 Example timer operation UM10524 Figure 48 shows a timer configured to reset the count and generate an interrupt on match The prescaler is set to 2 and the match register set to 6 At the end of the timer cycle where the match occurs the timer count is reset This gives a full length cycle to the match value The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value Figure 49 shows a timer configured to stop and generate an interrupt on match The prescaler is again set to 2 and the match register set to 6 In the next clock after the timer reaches the match value the timer enable bit in TCR is cleared and the interrupt indicating that a match occurred is generated All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 307 of 404 NXP Semiconductors U M1 0524 Chapter 15 LPC1315 16 17 45 46 47 16 bit counter timers CT16B0 1 prescale counter me Lek 5S I e J o Jo t cou
589. to perform either as PWM output or as match output whose function is controlled by the External Match Register EMR For each timer a maximum of three single edge controlled PWM outputs can be selected on the CT16Bn_MAT 1 0 outputs One additional match register determines the PWM cycle length When a match occurs in any of the other match registers the PWM output is set to HIGH The timer is reset by the match register that is configured to set the PWM cycle length When the timer is reset to zero all currently HIGH match outputs configured as PWM outputs are cleared Table 283 PWM Control Register PWMC address 0x4000 C074 and 0x4001 0074 CT16B1 bit description Bit Symbol Value Description Reset value 0 PWMENO PWM mode enable for channel0 0 0 CT16Bi_MATO is controlled by EMO 1 PWM mode is enabled for CT16Bi_MATO 1 PWMEN1 PWM mode enable for channel1 0 0 CT16Bi_MAT01 is controlled by EM1 1 PWM mode is enabled for CT16Bi_MAT1 2 PWMEN2 PWM mode enable for channel2 0 0 CT16Bi_MAT2 is controlled by EM2 1 PWM mode is enabled for CT16Bi_MAT2 3 PWMENS3 PWM mode enable for channels 0 0 CT16Bi_MATS is controlled by EM3 1 PWM mode is enabled for CT16Bi_MATS3 31 4 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 1
590. to reserved bits NA The value read from a reserved bit is not defined 16 COUNTFLAG Returns 1 if the SysTick timer counted to 0 since the last read of 0 this register 31 17 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined System Timer Reload value register The SYST_RVR register is set to the value that will be loaded into the SysTick timer whenever it counts down to zero This register is loaded by software as part of timer initialization The SYST_CALIB register may be read and used as the value for SYST_RVR register if the CPU is running at the frequency intended for use with the SYST_CALIB value All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 337 of 404 NXP Semiconductors U M1 0524 18 5 3 18 5 4 Chapter 18 LPC1315 16 17 45 46 47 System tick timer Table 311 System Timer Reload value register SYST_RVR 0xE000 E014 bit description Bit Symbol Description Reset value 23 0 RELOAD This is the value that is loaded into the System Tick counter when it 0 counts down to 0 31 24 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined System Timer Current value register The SYST_CVR register returns the current count from the System Tick counter when it is read by so
591. to the reference signature The algorithms to derive the reference signature is given in Figure 63 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 382 of 404 NXP Semiconductors U M1 0524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming int128 signature 0 int128 nextSignature FOR address flashpage 0 TO address flashpage max FOR i 0 TO 126 nextSignature i flashword i XOR signature i 1 nextSignature 1 27 flashword 127 XOR signature 0 XOR signature 2 XOR signature 27 XOR signature 29 signature nextSignature return signature Fig 63 Algorithm for generating a 128 bit signature UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 383 of 404 UM10524 Chapter 22 LPC1315 16 17 45 46 47 Serial Wire Debugger SWD Rev 1 17 February 2012 User manual 22 1 How to read this chapter The debug functionality is identical for all LPC1315 16 1 7 45 46 47 parts 22 2 Features e Supports ARM Serial Wire Debug mode e Trace port provides CPU instruction trace capability Output via a Serial Wire Viewer e Direct debug access to all memories registers and peripherals e No target resources are required for the debugging session e
592. to zero 2 Each PWM output will go HIGH when its match value is reached If no match occurs i e the match value is greater than the PWM cycle length the PWM output remains continuously LOW 3 If a match value larger than the PWM cycle length is written to the match register and the PWM signal is HIGH already then the PWM signal will be cleared with the start of the next PWM cycle UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 321 of 404 NXP Semiconductors U M1 0524 Chapter 16 LPC1315 16 17 45 46 47 32 bit counter timers CT32B0 1 4 If a match register contains the same value as the timer reset value the PWM cycle length then the PWM output will be reset to LOW on the next clock tick after the timer reaches the match value Therefore the PWM output will always consist of a one clock tick wide positive pulse with a period determined by the PWM cycle length i e the timer reload value 5 If a match register is set to zero then the PWM output will go to HIGH the first time the timer goes back to zero and will stay HIGH continuously Note When the match outputs are selected to perform as PWM outputs the timer reset MRnR and timer stop MRnS bits in the Match Control Register MCR must be set to zero except for the match register setting the PWM cycle length For this register set the MRnR bit to one t
593. tuint8_t _USB_OTHER_SPEED_CONFIGURATION bDescriptorType Other_speed_Configuration Type uint16_tuint16_t _USB_OTHER_SPEED_CONFIGURATION wlotalLength Total length of data returned uint8_tuint8_t _USB_OTHER_SPEED_CONFIGURATION bNumInterfaces Number of interfaces supported by this speed configuration uint8_tuint8_t _USB_OTHER_SPEED_CONFIGURATION bConfigurationValue Value to use to select configuration uint8_tuint8_t _USB_OTHER_SPEED_CONFIGURATION IConfiguration Index of string descriptor uint8_tuint8_t _USB_OTHER_SPEED_CONFIGURATION bmAttributes Same as Configuration descriptor uint8_tuint8_t _USB_OTHER_SPEED_CONFIGURATION bMaxPower Same as Configuration descriptor 11 5 22 _USB_SETUP_PACKET Table 187 _USB_SETUP_PACKET class structure Member bmRequestType bRequest wValue wlindex wLength Description REQUEST_TYPEREQUEST_TYPE _USB_SETUP_PACKET bmRequestType This bit mapped field identifies the characteristics of the specific request _BM_T uint8_tuint8_t _USB_SETUP_PACKET bRequest This field specifies the particular request The Type bits in the bmRequestType field modify the meaning of this field USBD_REQUEST WORD_BYTEWORD_BYTE _USB_SETUP_PACKET wValue Used to pass a parameter to the device specific to the request WORD_BYTEWORD_BYTE _USB_SETUP_PACKET wIndex Used to pass a parameter to the device specific to th
594. ubject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 80 of 404 NXP Semiconductors U M1 0524 UM10524 7 4 20 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 74 1 O configuration for pin PIOO_18 RXD CT32B0_MATO PIO0_18 address 0x4004 4048 bit description Bit Symbol Value Description Reset value 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 I O configuration for pin PIOO_19 Table 75 I O configuration for pin PlIOO_19 TXD CT32B0_MAT1 PIO0_19 address 0x4004 404C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x3 to 0x7 are reserved 0 0x0 PIOO_19 0x1 TXD 0x2 CT32BO_MAT1 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Rese
595. uint32_tuint32_t _MSC_CSW dDataResidue bStatus uint8_tuint8_t _MSC_CSW bStatus 11 5 15 _REQUEST_TYPE Table 180 _REQUEST_TYPE class structure Member Description B uint8_tuint8_t _REQUEST_TYPE B byte wide access member BM BM_TBM_T _REQUEST_TYPE BM bitfield structure access member 11 5 16 _USB_COMMON_DESCRIPTOR Table 181 _USB_COMMON_DESCRIPTOR class structure Member Description bLength uint8_tuint8_t _USB_COMMON_DESCRIPTOR bLength Size of this descriptor in bytes bDescriptorType uint8_tuint8_t _USB_COMMON_DESCRIPTOR bDescriptorType Descriptor Type UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 162 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers 11 5 17 _USB_CORE_DESCS_T USB descriptors data structure Table 182 _USB_CORE_DESCS_T class structure Member Description device_desc uint8_t uint8_t _USB_CORE_DESCS_T device_desc Pointer to USB device descriptor string_desc uint8_t uint8_t _USB_CORE_DESCS_T string_desc Pointer to array of USB string descriptors full_speed_desc uint8_t uint8_t _USB_CORE_DESCS_T full_speed_desc Pointer to USB device configuration descriptor when device is operating in full speed mode high_speed_desc uint8_t uint8_t _USB_CORE_DESCS_T high_speed_desc Pointer to USB
596. uintl6_t _HID_REPORT_T len Size of the report descriptor in bytes idle_time uint8_tuint8_t _HID_REPORT_T idle_time This value is used by stack to respond to Set_Idle amp GET_Idle requests for the specified report ID The value of this field specified the rate at which duplicate reports are generated for the specified Report ID For example a device with two input reports could specify an idle rate of 20 milliseconds for report ID 1 and 500 milliseconds for report ID 2 _ pad uint8_tuint8_t _HID_REPORT_T __pad Padding space desc uint8_t uint8_t _HID_REPORT_T desc Report descriptor UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 161 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers 11 5 13 _MSC_CBW Table 178 _MSC_CBW class structure Member Description dSignature uint32_tuint32_t _MSC_CBW dSignature dTag uint32_tuint32_t _MSC_CBW dTag dDataLength uint32_tuint32_t _MSC_CBW dDataLength bmFlags uint8_tuint8_t _MSC_CBW bmFlags bLUN uint8_tuint8_t _MSC_CBW bLUN bCBLength uint8_tuint8_t _MSC_CBW bCBLength CB uint8 _tuint8_t _MSC_CBW CB 16 16 11 5 14 _MSC_CSW Table 179 _MSC_CSW class structure Member Description dSignature uint32_tuint32_t _MSC_CSW dSignature dTag uint32_tuint32_t _MSC_CSW dTag dDataResidue
597. uintl6_t state SendBreak ErrorCode_t ErrorCode_t USBD_CDC_INIT_PARAM SendBreak USBD_HANDLE_T hCDC uintl6_t mstime USBD_HANDLE_T hCDC uintl6_t mstime UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 173 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 193 USBD_CDC_INIT_PARAM class structure Member Description SetLineCode ErrorCode_t ErrorCode_t USBD_CDC_INIT_PARAM SetLineCode USBD_HANDLE_T hCDC CDC_LINE_CODING line_coding USBD_HANDLE_T hCDC CDC_LINE_CODING line_ coding CDC_InterruptEP_Hdlr grrorCode_t ErrorCode_t USBD_CDC_INIT_PARAM CDC_InterruptEP_Hdlr USBD_HANDLE_T hUsb void data uint32_t event USBD_HANDLE_T hUsb void data uint32_t event Optional Communication Device Class specific INTERRUPT IN endpoint handler The application software should provide the INT IN endpoint handler Applications should transfer data depending on the communication protocol type set in descriptors Remark Parameters 1 hUsb Handle to the USB device stack 2 data Pointer to the data which will be passed when callback function is called by the stack 3 event Type of endpoint event See USBD_EVENT_T for more details Returns The call back should returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On
598. uld set this data member to zero before calling the USBD_HID_API Init Parameters 1 hHid Handle to HID function driver 2 pSetup Pointer to setup packet received from host 3 pBuf Pointer to a pointer of data buffer containing physical descriptor data If the physical descriptor is in USB accessible memory area application could just update the pointer or else it should copy the descriptor to the address pointed by this pointer 4 length Amount of data copied to destination buffer or descriptor length Returns The call back should returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_ xxx For other error conditions HID_Setldle ErrorCode_t ErrorCode_t USBD_HID_INIT_PARAM HID_SetIdle USBD_HANDLE_T hHid USB_SETUP_PACKET pSetup uint8_t idleTime USBD_HANDLE_T hHid USB_SETUP_PACKET pSetup uint8_t idleTime Optional callback function to handle HID_ REQUEST_SET_IDLE request The application software could provide this callback to handle HID_ REQUEST_SET_IDLE requests sent by the host This callback is provided to applications to adjust timers associated with various reports which are sent to host over interrupt endpoint The setup packet data Remark Applications which don t send reports on Interrupt endpoint or don t have idle time between reports should set this data
599. umber gt Table 346 Read Part ID J Table 347 Read Boot code version K Table 349 Compare M lt address1 gt lt address2 gt lt number of bytes gt Table 350 ReadUID N Table 351 Unlock lt Unlock code gt Table 337 ISP Unlock command Command U Input Unlock code 2313040 Return Code CMD SUCCESS INVALID_CODE PARAM_ERROR Description This command is used to unlock Flash Write Erase and Go commands Example U 23130 lt CR gt lt LF gt unlocks the Flash Write Erase amp Go commands All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 363 of 404 NXP Semiconductors U M1 0524 Chapter 21 LPC1315 16 17 45 46 47 Flash EEPRPOM programming 21 13 2 Set Baud Rate lt Baud Rate gt lt stop bit gt Table 338 ISP Set Baud Rate command Command B Input Baud Rate 9600 19200 38400 57600 115200 Stop bit 1 2 Return Code CMD SUCCESS INVALID_BAUD_ RATE INVALID_STOP_BIT PARAM_ERROR Description This command is used to change the baud rate The new baud rate is effective after the command handler sends the CMD_SUCCESS return code Example B 57600 1 lt CR gt lt LF gt sets the serial port to baud rate 57600 bps and 1 stop bit 21 13 3 Echo lt setting gt Table 339 ISP Echo command Command A Input Setting ON 1 OFF 0 Return Code CMD SUCCESS PARAM_ERROR Description The defaul
600. uped interrupt port 0 0 Table 128 enable register PORT_ENA1 R W 0x044 GPIO grouped interrupt port 1 0 Table 129 enable register All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 120 of 404 NXP Semiconductors U M1 0524 Chapter 9 LPC1315 16 17 45 46 47 GPIO Table 113 Register overview GPIO GROUP1 interrupt base address 0x4006 0000 Name Access Address Description Reset Reference offset value CTRL R W 0x000 GPIO grouped interrupt control 0 Table 125 register PORT_POLO R W 0x020 GPIO grouped interrupt port 0 OxFFFF Table 126 polarity register FFFF PORT_POL1 R W 0x024 GPIO grouped interrupt port 1 OxFFFF Table 127 polarity register FFFF PORT_ENAO R W 0x040 GPIO grouped interrupt port 0 enable 0 Table 128 register PORT_ENA1 R W 0x044 GPIO grouped interrupt port 1 enable 0 Table 129 register GPIO port addresses can be read and written as bytes halfwords or words Table 114 Register overview GPIO port base address 0x5000 0000 Name Access Address Description Reset Width Reference offset value BO to B31 R W 0x0000 to Ox001F Byte pin registers port 0 pins PIOO_O extl l byte 8 bit Table 130 to PIOO_31 B32 to B63 R W 0x0020 to 0x002F Byte pin registers port 1 ext byte 8 bit Table 131 Wo to W31 R W 0x1000 to 0x107C Word pin registers port 0 ext word 32 bit Table 132 W32 to W63 R W 0x1080
601. ured PIO status 0 user Table 29 dependent PIOPORCAP1 read 0x104 POR captured PIO status 1 user Table 30 dependent BODCTRL read write 0x150 Brown Out Detect 0 Table 31 SYSTCKCAL read write 0x154 System tick counter calibration Table 32 IRQLATENCY read write 0x170 IQR delay Allows trade off between 0x0000 Table 33 interrupt latency and determinism 0010 UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 13 of 404 NXP Semiconductors UM10524 Chapter 3 LPC1315 16 17 45 46 47 System control block Table 5 Register overview SYSCON base address 0x4004 8000 Name Access Address Description Reset Reference offset value NMISRC read write 0x174 NMI Source Control 0 Table 34 PINTSEL read write 0x178 GPIO Pin Interrupt Select register 0 Table 35 USBCLKCTRL read write 0x198 USB clock control Table 36 USBCLKST read 0x19C USB clock status Table 37 STARTERPO read write 0x204 Start logic 0 interrupt wake up enable 0 Table 38 register 0 STARTERP1 read write 0x214 Start logic 1 interrupt wake up enable 0 Table 39 register 1 PDSLEEPCFG read write 0x230 Power down states in deep sleep mode Table 40 PDAWAKECFG read write 0x234 Power down states for wake up from Table 41 deep sleep PDRUNCFG read write 0x238 Power configuration register Table 42 DEVICE_ID read Ox3F8 Device ID part Table 43 dependent 3 5 1 System memory remap regis
602. users to invoke this function in other scenarios which are not handle by current stack In most user applications this function is not called directly Also this function can be used by users who are selectively modifying the USB device stack s standard handlers through callback interface exposed by the stack Parameters 1 hUsb Handle to the USB device stack Returns Nothing void void USBD_CORE_API DataQutStage USBD_HANDLE_T hUsb Function to set EPO state machine in data_out state This function is called by USB stack and the application layer to set the EPO state machine in data_out state This function will read the control data EPO out packets received from USB host into EPOData buffer Remark This interface is provided to users to invoke this function in other scenarios which are not handle by current stack In most user applications this function is not called directly Also this function can be used by users who are selectively modifying the USB device stack s standard handlers through callback interface exposed by the stack Parameters 1 hUsb Handle to the USB device stack Returns Nothing All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 176 of 404 NXP Semiconductors U M1 0524 Chapter 11 LPC1345 46 47 USB on chip drivers Table 194 USBD_CORE_API class structure Member StatusInStage D
603. ute to the grouped interrupt Table 128 GPIO grouped interrupt port 0 enable registers PORT_ENAO addresses 0x4005 C040 GROUPO INT and 0x4006 0040 GROUP 1 INT bit description Bit Symbol Description Reset Access value 31 0 ENAO Enable port 0 pin for group interrupt Bit n corresponds to pin 0 PO_n of port 0 0 the port 0 pin is disabled and does not contribute to the grouped interrupt 1 the port 0 pin is enabled and contributes to the grouped interrupt Table 129 GPIO grouped interrupt port 1 enable registers PORT_ENA1 addresses 0x4005 C044 GROUPO INT and 0x4006 0044 GROUP1 INT bit description Bit Symbol Description Reset Access value 31 0 ENA1 Enable port 1 pin for group interrupt Bit n corresponds to pin 0 P1_n of port 0 0 the port 1 pin is disabled and does not contribute to the grouped interrupt 1 the port 1 pin is enabled and contributes to the grouped interrupt UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 127 of 404 NXP Semiconductors U M1 0524 UM10524 9 5 3 9 5 3 1 9 5 3 2 Chapter 9 LPC1315 16 17 45 46 47 GPIO GPIO port register description GPIO port byte pin registers Each GPIO pin has a byte register in this address range Software typically reads and writes bytes to access individual pins but can read or write halfwords to sense or set t
604. uting Copy RAM to flash or Erase Sector s command Successful execution of the Copy RAM to flash or Erase Sector s command causes relevant sectors to be protected again The boot block can not be prepared by this command To prepare a single sector use the same Start and End sector numbers P 0 0 lt CR gt lt LF gt prepares the flash sector 0 Copy RAM to flash lt Flash address gt lt RAM address gt lt no of bytes gt When writing to the flash the following limitations apply 1 The smallest amount of data that can be written to flash by the copy RAM to flash command is 256 byte equal to one page 2 One page consists of 16 flash words lines and the smallest amount that can be modified per flash write is one flash word one line This limitation follows from the application of ECC to the flash write operation see Section 21 6 3 To avoid write disturbance a mechanism intrinsic to flash memories an erase should be performed after following 16 consecutive writes inside the same page Note that the erase operation then erases the entire sector Remark Once a page has been written to 16 times it is still possible to write to other pages within the same sector without performing a sector erase assuming that those pages have been erased previously All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 20
605. utomatically cleared after auto baud 0 completion 0 Auto baud stop auto baud is not running 1 Auto baud start auto baud is running Auto baud run bit This bit is automatically cleared after auto baud completion 1 MODE Auto baud mode select bit 0 0 Mode 0 1 Mode 1 2 AUTORESTART Start mode 0 0 No restart 1 Restart in case of time out counter restarts at next USART Rx falling edge 7 3 Reserved user software should not write ones to 0 reserved bits The value read from a reserved bit is not defined 8 ABEOINTCLR End of auto baud interrupt clear bit write only 0 accessible 0 Writing a 0 has no impact 1 Writing a 1 will clear the corresponding interrupt in the IIR 9 ABTOINTCLR Auto baud time out interrupt clear bit write only 0 accessible 0 Writing a 0 has no impact 1 Writing a 1 will clear the corresponding interrupt in the IIR 31 10 Reserved user software should not write ones to 0 reserved bits The value read from a reserved bit is not defined Auto baud The USART auto baud function can be used to measure the incoming baud rate based on the AT protocol Hayes command If enabled the auto baud feature will measure the bit time of the receive data stream and set the divisor latch registers DLM and DLL accordingly Auto baud is started by setting the ACR Start bit Auto baud can be stopped by clearing the ACR Start bit The Start bit will clear once auto baud has finished and read
606. utput bit not affected GPIO port pin registers Reading these registers returns the current state of the pins read regardless of direction masking or alternate functions except that pins configured as analog I O always read as Os Writing these registers loads the output bits of the pins written to regardless of the Mask register Table 138 GPIO port 0 pin register PINO address 0x5000 2100 bit description Bit Symbol Description Reset Access value 31 0 PORTO Reads pin states or loads output bits bit O PO_O bit 1 ext R W PO_1 bit 31 PO_31 0 Read pin is low write clear output bit 1 Read pin is high write set output bit Table 139 GPIO port 1 pin register PIN1 address 0x5000 2104 bit description Bit Symbol Description Reset Access value 31 0 PORT1 Reads pin states or loads output bits bit O P1_0 bit 1 ext R W P1_1 bit31 P1_31 0 Read pin is low write clear output bit 1 Read pin is high write set output bit GPIO masked port pin registers These registers are similar to the PORT registers except that the value read is masked by ANDing with the inverted contents of the corresponding MASK register and writing to one of these registers only affects output register bits that are enabled by zeros in the corresponding MASK register Table 140 GPIO masked port 0 pin register MPINO address 0x5000 2180 bit description Bit Symbol Description Reset Access v
607. ve from Slave to Master any number of data bytes and their associated Acknowledge bits this number contained in I2STA corresponds to a defined state of the PC bus 14 10 5 14 10 5 1 14 10 5 2 UM10524 Miscellaneous states There are two STAT codes that do not correspond to a defined 12C hardware state see Table 267 These are discussed below STAT 0xF8 This status code indicates that no relevant information is available because the serial interrupt flag SI is not yet set This occurs between other states and when the 12C block is not involved in a serial transfer STAT 0x00 This status code indicates that a bus error has occurred during an I C serial transfer A bus error is caused when a START or STOP condition occurs at an illegal position in the format frame Examples of such illegal positions are during the serial transfer of an address byte a data byte or an acknowledge bit A bus error may also be caused when external interference disturbs the internal 12C block signals When a bus error occurs SI is set To recover from a bus error the STO flag must be set and SI must be cleared This All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 283 of 404 NXP Semiconductors U M1 0524 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller causes the 12C block to enter the not addressed
608. ve mode When STO is 1 in master mode a STOP condition is transmitted on the I C bus When the bus detects the STOP condition STO is cleared automatically In slave mode setting this bit can recover from an error condition In this case no STOP condition is transmitted to the bus The hardware behaves as if a STOP condition has been received and it switches to not addressed slave receiver mode The STO flag is cleared by hardware automatically SI is the 12C Interrupt Flag This bit is set when the I C state changes However entering state F8 does not set SI since there is nothing for an interrupt service routine to do in that case While SI is set the low period of the serial clock on the SCL line is stretched and the serial transfer is suspended When SCL is HIGH it is unaffected by the state of the SI flag SI must be reset by software by writing a 1 to the SIC bit in the CONCLR register All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 256 of 404 NXP Semiconductors U M1 0524 UM10524 14 7 2 14 7 3 Chapter 14 LPC1315 16 17 45 46 47 I2C bus controller AA is the Assert Acknowledge Flag When set to 1 an acknowledge low level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 The address in the Slave Address Register has been received 2 The
609. vel falling edge interrupt clear register For each of the 8 pin interrupts selected in the PINTSEL registers see Table 35 one bit in the CIENF register sets the corresponding bit in the IENF register depending on the pin interrupt mode configured in the ISEL register e If the pin interrupt mode is edge sensitive PMODE 0 the falling edge interrupt is cleared e lf the pin interrupt mode is level sensitive PMODE 1 the LOW active interrupt is selected Table 121 Pin interrupt active level falling edge interrupt clear register CIENF address 0x4004 C018 bit description Bit Symbol Description Reset Access value 7 0 CENAF Ones written to this address clears bits in the IENF thus NA WO disabling interrupts Bit n clears bit n in the IENF register 0 No operation 1 LOW active interrupt selected or falling edge interrupt disabled 31 8 Reserved Pin interrupt rising edge register This register contains ones for pin interrupts selected in the PINTSEL registers see Table 35 on which a rising edge has been detected Writing ones to this register clears rising edge detection Ones in this register assert an interrupt request for pins that are enabled for rising edge interrupts All edges are detected for all pins selected by the PINTSEL registers regardless of whether they are interrupt enabled All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserv
610. vided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 232 of 404 NXP Semiconductors U M1 0524 Chapter 12 LPC1315 16 17 45 46 47 USART selectable O power rail O pull up pull up resistor resistor resistor MATX PWMx GLK ISO 7816 LPC13xx Optional TXD Logic Level yo Smart Card Translation GPIO Insertion Switch Fig 20 Typical smart card application When the SCIEN bit in the SCICTRL register Table 226 is set as described the USART provides bidirectional serial data on the open drain TXD pin No RXD pin is used when SCIEN is 1 If a clock source is needed as an oscillator source into the Smart Card a timer match or PWM output can be used in cases when a higher frequency clock is needed that is not synchronous with the data bit rate The USART SCLK pin will output synchronously with the data and at the data bit rate and may not be adequate for most asynchronous cards Software must use timers to implement character and block waiting times no hardware support via trigger signals is provided on the LPC1315 16 17 45 46 47 GPIO pins can be used to control the smart card reset and power pins Any power supplied to the card must be externally switched as card power supply requirements often exceed source currents possible on the LPC1315 16 17 45 46 47 As the specific application may accommodate any of the available ISO 7816
611. vided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 121 of 404 NXP Semiconductors U M1 0524 UM10524 9 5 1 2 9 5 1 3 Chapter 9 LPC1315 16 17 45 46 47 GPIO Table 115 Pin interrupt mode register ISEL address 0x4004 C000 bit description Bit Symbol Description Reset Access value 7 0 PMODE Selects the interrupt mode for each pin interrupt Bit n 0 R W configures the pin interrupt selected in PINTSELn 0 Edge sensitive 1 Level sensitive 31 8 Reserved Pin interrupt level rising edge interrupt enable register For each of the 8 pin interrupts selected in the PINTSEL registers see Table 35 one bit in the IENR register enables the interrupt depending on the pin interrupt mode configured in the ISEL register e If the pin interrupt mode is edge sensitive PMODE 0 the rising edge interrupt is enabled e If the pin interrupt mode is level sensitive PMODE 1 the level interrupt is enabled The PINTEN_F register configures the active level HIGH or LOW for this interrupt Table 116 Pin interrupt level rising edge interrupt enable register IENR address 0x4004 C004 bit description Bit Symbol Description Reset Access value 7 0 ENRL Enables the rising edge or level interrupt for each pin 0 R W interrupt Bit n configures the pin interrupt selected in PINTSELn 0 Disable rising edge or level interrupt
612. wake up event from Deep power down and was not a cold reset 3 Clear the deep power down flag in the PCON register Table 48 4 Optional Read the stored data in the general purpose registers Section 4 3 2 5 Set up the PMU for the next Deep power down cycle Remark The RESET pin has no functionality in Deep power down mode 3 10 System PLL USB PLL functional description The LPC1315 16 1 7 45 46 47 uses the system PLL to create the clocks for the core and peripherals An identical PLL is available for the USB Ie g ire_osc_clk 1 FCLKIN nes sys_osc_clk m DDD FCCO pd PSEL lt 1 0 gt PFD A 2 SYSPLLCLKSEL pd bp USBPLLCLKCEL LOCK Le pereor Lock b gt gt gt FCLKOUT L a analog section pd d cd M Ly MSEL lt 4 0 gt 1 System PLL only Fig 5 System PLL block diagram The block diagram of this PLL is shown in Figure 5 The input frequency range is 10 MHz to 25 MHz The input clock is fed directly to the Phase Frequency Detector PFD This block compares the phase and frequency of its inputs and generates a control signal when phase and or frequency do not match The loop filter filters these control signals and drives the current controlled oscillator CCO which generates the main clock and optionally two additional phases The CCO frequency range is 156 MHz to 320 MHz These clocks
613. will be received Write Slave Address with R W bit to DAT Write 0x04 to CONSET to set the AA bit Write 0x08 to CONCLR to clear the SI flag Set up Master Transmit mode data buffer Set up Master Receive mode data buffer Initialize Master data counter Exit Nook WOOD Master Transmitter states State 0x18 Previous state was State 8 or State 10 Slave Address Write has been transmitted ACK has been received The first data byte will be transmitted an ACK bit will be received Load DAT with first data byte from Master Transmit buffer Write 0x04 to CONSET to set the AA bit Write 0x08 to CONCLR to clear the SI flag Increment Master Transmit buffer pointer Exit ar WwW N gt State 0x20 Slave Address Write has been transmitted NOT ACK has been received A STOP condition will be transmitted 1 Write 0x14 to CONSET to set the STO and AA bits 2 Write 0x08 to CONCLR to clear the SI flag 3 Exit State 0x28 Data has been transmitted ACK has been received If the transmitted data was the last data byte then transmit a STOP condition otherwise transmit the next data byte Decrement the Master data counter skip to step 5 if not the last data byte Write 0x14 to CONSET to set the STO and AA bits Write 0x08 to CONCLR to clear the SI flag Exit Load DAT with next data byte from Master Transmit buffer ar O N gt All information provided in this document is subject
614. wledge bits controls the master and slave modes contains interrupt request logic and monitors the I C bus status Control register CONSET and CONCLR The 12C control register contains bits used to control the following I2C block functions start and restart of a serial transfer termination of a serial transfer bit rate address recognition and acknowledgment The contents of the 12C control register may be read as CONSET Writing to CONSET will set bits in the 12C control register that correspond to ones in the value written Conversely writing to CONCLR will clear bits in the 12C control register that correspond to ones in the value written Status decoder and status register The status decoder takes all of the internal status bits and compresses them into a 5 bit code This code is unique for each I C bus status The 5 bit code may be used to generate vector addresses for fast processing of the various service routines Each service routine processes a particular bus status There are 26 possible bus states if all four modes of the 12C block are used The 5 bit status code is latched into the five most significant bits of the status register when the serial interrupt flag is set oy hardware and remains stable until the interrupt flag is cleared by software The three least significant bits of the status register are always zero If the status code is used as a vector to service routines then the routines are displaced by eight address
615. wn resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as 0 LOW on pin reads as 1 9 7 Reserved 0x1 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 Reserved 0 7 4 46 I O configuration for pin PIO1_24 Table 101 I O configuration for pin PIO1_24 CT32B0_MATO PIO1_24 address 0x4004 40C0 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x2 to 0x7 are reserved 0 0x0 PIO1_24 0x1 CT32B0_MATO 4 3 MODE Selects function mode on chip pull up pull down resistor 0x2 control 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 100 of 404 NXP Semiconductors U M1 0524 7 4 47 Chapter 7 LPC1315 16 17 45 46 47 I O configuration Table 101 I O configuration for pin PIO1_24 CT32B0_MATO PIO1_24 address 0x4004 40C0 bit description Bit Symbol Value Description Reset value 6 INV Invert input 0 0
616. x02C Capture Register 0 CRO is loaded with the value of TC when there 0 Table 295 is an event on the CT32B1_CAPO input CR1 RO 0x030 Capture Register 1 CR1 is loaded with the value of TC when there 0 Table 295 is an event on the CT32B1_CAP1 input 0x034 Reserved s 0x038 EMR R W 0x03C External Match Register The EMR controls the match function and 0 Table 296 the external match pins CT32Bn_MAT 3 0 0x040 Reserved 0x06C CTCR R W 0x070 Count Control Register The CTCR selects between Timer and 0 Table 298 Counter mode and in Counter mode selects the signal and edge s for counting PWMC R W 0x074 PWM Control Register The PWMCON enables PWM mode for the 0 Table 299 external match pins CT32Bn_MAT 3 0 1 Reset value reflects the data stored in used bits only It does not include reserved bits content UM10524 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 313 of 404 NXP Semiconductors U M1 0524 16 7 1 Chapter 16 LPC1315 16 17 45 46 47 32 bit counter timers CT32B0 1 Interrupt Register The Interrupt Register consists of four bits for the match interrupts and four bits for the capture interrupts If an interrupt is generated then the corresponding bit in the IR will be HIGH Otherwise the bit will be LOW Writing a logic one to the corresponding IR bit will reset the interrupt Writing a ze
617. y PCLK When it reaches the value stored in the Prescale Register the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK This causes the TC to increment on every PCLK when PR 0 every 2 PCLKs when PR 1 etc Table 275 Prescale counter registers PC address 0x4000 C010 CT16B0 and 0x4001 0010 CT16B1 bit description Bit Symbol Description Reset value 15 0 PC Prescale counter value 0 31 16 Reserved Match Control Register The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter The function of each of the bits is shown in Table 276 Table 276 Match Control Register MCR address 0x4000 C014 CT16B0 and 0x4001 0014 CT16B1 bit description Bit Symbol Value Description Reset value 0 MROI Interrupt on MRO an interrupt is generated when MRO matches the value in the TC 0 1 Enabled 0 Disabled 1 MROR Reset on MRO the TC will be reset if MRO matches it 0 1 Enabled 0 Disabled 2 MROS Stop on MRO the TC and PC will be stopped and TCR O will be set to 0 if MRO matches 0 UM10524 the TC Enabled Disabled All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 17 February 2012 300 of 404 NXP Semiconductors U M1 0524 Chapter 15 LPC1315 16 17 45 46 47 16 bit counter timers CT16B0 1 Table 276 Match Contro
618. ymbol Value Description Reset value 7 4 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined 8 ABEOINTEN Enables the end of auto baud interrupt 0 0 Disable end of auto baud Interrupt Enable end of auto baud Interrupt 9 ABTOINTEN Enables the auto baud time out interrupt 0 0 Disable auto baud time out Interrupt 1 Enable auto baud time out Interrupt 31 10 Reserved user software should not write ones to reserved NA bits The value read from a reserved bit is not defined USART Interrupt Identification Register Read Only IIR provides a status code that denotes the priority and source of a pending interrupt The interrupts are frozen during a IIR access If an interrupt occurs during a IIR access the interrupt is recorded for the next IIR access Table 209 USART Interrupt Identification Register Read only IIR address 0x4004 8008 bit description Bit Symbol Value Description Reset value 0 INTSTATUS Interrupt status Note that IIR 0 is active low The pending 1 interrupt can be determined by evaluating IIR 3 1 O Atleast one interrupt is pending 1 No interrupt is pending 3 1 INTID Interrupt identification IER 3 1 identifies an interrupt 0 corresponding to the USART Rx FIFO All other values of IER 3 1 not listed below are reserved 0x3 1 Receive Line Status RLS 0x2 2a Receive Data Available RDA 0x6 2b Character Time out Indicator
619. zero has no effect Table 252 I2C Control Clear register CONCLR 0x4000 0018 bit description Bit Symbol Description Reset value 1 0 Reserved User software should not write ones to reserved bits The NA value read from a reserved bit is not defined 2 AAC Assert acknowledge Clear bit 3 SIC 12C interrupt Clear bit 0 4 Reserved User software should not write ones to reserved bits The NA value read from a reserved bit is not defined 5 STAC START flag Clear bit 0 6 I2ENC 12C interface Disable bit 0 7 Reserved User software should not write ones to reserved bits The NA value read from a reserved bit is not defined 31 8 Reserved The value read from a reserved bit is not defined AAC is the Assert Acknowledge Clear bit Writing a 1 to this bit clears the AA bit in the CONSET register Writing 0 has no effect SIC is the 12C Interrupt Clear bit Writing a 1 to this bit clears the SI bit in the CONSET register Writing 0 has no effect STAC is the START flag Clear bit Writing a 1 to this bit clears the STA bit in the CONSET register Writing 0 has no effect I2ENC is the 12C Interface Disable bit Writing a 1 to this bit clears the I2EN bit in the CONSET register Writing 0 has no effect I2C Monitor mode control register MMCTRL This register controls the Monitor mode which allows the 12C module to monitor traffic on the 12C bus without actually participating in traffic or interfering with the 12C bus

UM10524 LPC1315/16/17/45/46/47 User manual

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