89HPES32NT8BG2 Datasheet 32-Lane 8-Port PCIe® Gen2
Contents
1. POOCLKN PQle Switch PCle Switch POOCLKP FEOOTF 30 SerDes Output SerDes Input PEOOTNIS 0 E Port 0 Port 0 PEOORP 3 0 gt PEOORN 3 0 gt EX PCle Switch s PEUT HIS SerDes Output PO2CLKN PE02TN 3 0 Port 2 e Switcl PO2CLKP gt SerDes Input Port 2 Saab is ae PCle Switch PEO2RN 3 0 spl SerDes Output H PEDATNI3 0 p PO4CLKN v dune PCle Switch PO4CLKP gt SerDes Input BT PEO4RP 3 0 gt I pEQ6TP 3 0 PCle Switch PEO4RN 3 0 gt L PEO6TNI3 0 tea pedi Bue PEE is Soros Output Port 6 PEOGRN 3 0 08TN 3 0 J Port8 f PCle Switch c PEI2TP 3 0 Hie dori PEO8RP 3 0 Le PETN aen Output Pon 4 PEO8RN B 0 o ee c PTB Nam 5 a wi PERS gt PES32NT8BG2 gt Pemo e ponie Potty PET2RNO gt gt PED0TPI30 mi aat L penati SerDes Output PCle Switch Port 20 SerDes Input PETGRP S O a Port 16 PEI6RN B 0 8 SerDes aa CREE X boire Reference oe tal PEDORPI3 0 zs Resistors Port 20 PE2ORN 9 9 GPIO 0 General Purpose Slave SSMBADDR 2 gt 1 0 SMBus Interface SSMBCLK B SSMBDAT lt JTAG_TCK I H JTAG TDI Master MSMBCLK aa gt m JTAG TDO JTAG Pins SMBus Interf2. IDT Device Overview The 89HPES32NT8BG2 is a member of the IDT family of PCI Express switching solutions The PESS2NT8BG2 is a 32 lane 8 port system interconnect switch optimized for PCI Express Gen2 packet switching in high performance applications supporting multiple simulta neous peer to peer traffic flows Target applications include multi host or intelligent I O based systems where inter domain communication is required such as servers storage communications and embedded systems Features High Performance Non Blocking Switch Architecture 32 lane 8 port PCle switch with flexible port configuration Integrated SerDes supports 5 0 GT s Gen2 and 2 5 GT s Gen1 operation Delivers up to 32 GBps 256 Gbps of switching capacity Supports 128 Bytes to 2 KB maximum payload size Low latency cut through architecture Supports one virtual channel and eight traffic classes Port Configurability Eight x4 switch ports Adjacent x4 ports can be merged to achieve x8 port widths Automatic per port link width negotiation x8 gt x4 gt X2 gt x1 Crosslink support Automatic lane reversal Per lane SerDes configuration e De emphasis Receive equalization Drive strength Innovative Switch Partitioning Feature Supports up to 8 fully independent switch partitions Logically independent switches in the same device Configurable downstream port device numbering Supports dynamic reconfiguration of switc
3. Table 17 PES32NT8BG2 Operating Voltages Industrial Temperature 1 VpgPEA and VppPETA should have no more than 25MV peak peak AC power supply noise superimposed on the 1 0V nominal DC value 2 VppPEHA should have no more than 50MV peak peak AC power supply noise superimposed on the 2 5V nominal DC value Power Up Power Down Sequence During power supply ramp up VppCORE must remain at least 1 0V below Vppl O at all times There are no other power up sequence require ments for the various operating supply voltages The power down sequence can occur in any order 17 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Power Consumption Typical power is measured under the following conditions 25 C Ambient 35 total link usage on all ports typical voltages defined in Table 16 and also listed below Maximum power is measured under the following conditions 70 C Ambient 85 total link usage on all ports maximum voltages defined in Table 16 and also listed below Table 18 PES32NT8BG2 Power Consumption PCle Core Supply c ng dd Sd Transmitter I O Supply Total Number of Active Upp y 9 PPly Supply Lanes per Port Typ Max Typ Max Typ Max Typ Max Typ Max Typ Max 1 0V 1 1V 1 0V 1 1V 2 5V 2 75V 1 0V 1 1V 3 3V 3 465 Power Power X8 x8 x8 x4 x4 mA 2486 3400 1623 1806 230 234 679 729 3 5 Full Swing F Wats 249 374 162 199 058 064 oss oso ooi 002 538
4. 2 The values for this symbol were determined by calculation not by testing EXTCLK LENINS Au x AZ XJ gt Tpw 13b fe GPIO asynchronous input X x Figure 4 GPIO AC Timing Waveform 15 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Reference Timing Signal Symbol Min Max Unit Diagram Edge Reference JTAG JTAG_TCK Tper_16a none 50 0 ns See Figure 5 Thigh_16a 10 0 25 0 ns Tlow_16a JTAG_TMS Tsu_16b JTAG_TCK rising 24 ns JTAGLIDI Thid_16b 10 E ns JTAG TDO Tdo 16c JTAG TCK falling 20 ns Tdz 16c 20 ns JTAG TRST N Tpw 16d none 25 0 ns Table 14 JTAG AC Timing Characteristics The JTAG specification IEEE 1149 1 recommends that JTAG TMS should be held at 1 while the signal applied at JTAG TRST N changes from 0 to 1 Otherwise a race may occur if JTAG_TRST_N is deasserted going from low to high on a rising edge of JIAG_TCK when JTAG_TMS is low because the TAP controller might go to either the Run Test Idle state or stay in the Test Logic Reset state The values for this symbol were determined by calculation not by testing gt Tlow_16a lt Tper_16a Thigh_16a 4 JTAG TCK Thld 16b Tsu 16b p Jor i Thid_i6 b gt Tsu_16b p JTAG_TMS i gt Ge gt Tdo_16c gt Tdz_16c JTAG_TDO Tpw 16d gt JTAG_TRST_N Figure 5 JTAG AC Tim
5. PEO4RN 3 0 PEO4RP 3 0 PEO4TN 3 0 PEOATP 3 0 ojo PEO6RN 3 0 PEO6RP 3 0 PEO6TN 3 0 PEO6TP 3 0 ojo PEO8RN 3 0 PEO8RP 3 0 PEO8TN 3 0 PEO8TP 3 0 ojo PE12RN 3 0 PE12RP 3 0 PE12TN 3 0 PE12TP 3 0 PE16RN 3 0 PE16RP 3 0 PE16TN 3 0 PE16TP 3 0 PE20RN 3 0 PCle PE20RP 3 0 differential PE20TN 3 0 PE20TP 3 0 Serial Link Serial Link Note Unused SerDes pins can be left floating Table 10 Pin Characteristics Part 1 of 2 11 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet F 1 0 Internal Function Pin Name Type Buffer Type Resistor Notes Reference Clocks GCLKN 1 0 HCSL Diff Clock Refer to Table 11 Input SERIE He sj Note Unused port POOCLKN clock pins should be POOCLKP connected to Vss on the board PO2CLKN PO2CLKP PO4CLKN PO4CLKP SMBus MSMBCLK yo LVTTL STI Note When unused these signals must MSMBDAT O STI be pulled up on the board using an external resistor or current source in accordance with the SMBus specifica tion SSMBADDR 2 pull up SSMBCLK yo STI Note When unu
6. PE20TN 3 0 O PCI Express Port 20 Serial Data Transmit Differential PCI Express transmit pairs PE20TP 3 0 for port 20 Table 2 PCI Express Interface Pins 5 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Signal Type Name Description GCLKN 1 0 Global Reference Clock Differential reference clock input pairs This GCLKPT 1 0 clock is used as the reference clock by on chip PLLs to generate the clocks required for the system logic The frequency of the differential reference clock is determined by the GCLKFSEL signal Note Both pairs of the Global Reference Clocks must be connected to and derived from the same clock source Refer to the Overview section of Chapter 2 in the PES32NT8xG2 User Manual for additional details POOCLKN Port Reference Clock Differential reference clock pair associated with POOCLKP port 0 PO2CLKN Port Reference Clock Differential reference clock pair associated with PO2CLKP port 2 PO4CLKN Port Reference Clock Differential reference clock pair associated with PO4CLKP port 4 Table 3 Reference Clock Pins Signal Type Name Description MSMBCLK yo Master SMBus Clock This bidirectional signal is used to synchronize transfers on the master SMBus It is active and generating the clock only when the EEPROM or I O Expanders are being accessed MSMBDAT yo Master SMBus Data This bidirectional signal is used for data on the master SMBus SSMBADDR 2
7. Slave SMBus Address This pin determines the SMBus address to which the slave SMBus interface responds SSMBCLK lO Slave SMBus Clock This bidirectional signal is used to synchronize transfers on the slave SMBus SSMBDAT yo Slave SMBus Data This bidirectional signal is used for data on the slave SMBus Table 4 SMBus Interface Pins 6 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Signal Type Name Description GPIO 0 O General Purpose I O This pin can be configured as a general purpose O pin 1st Alternate function pin name PARTOPERSTN 1st Alternate function pin type Input Output 1st Alternate function Assertion of this signal initiated a partition funda mental reset in the corresponding partition 2nd Alternate function pin name P16LINKUPN 2nd Alternate function pin type Output 2nd Alternate function Port 16 Link Up Status output GPIO 1 1 0 General Purpose I O This pin can be configured as a general purpose I O pin 1st Alternate function pin name PART1PERSTN 1st Alternate function pin type Input Output 1st Alternate function Assertion of this signal initiated a partition funda mental reset in the corresponding partition 2nd Alternate function pin name P16ACTIVEN 2nd Alternate function pin type Output 2nd Alternate function Port 16 Link Active Status Output GPIO 2 1 0 General Purpose I O This pin can be configured as a general purpose
8. 7 19 X8 x8 x8 x4 x4 mA 2486 3400 1396 1553 230 234 353 379 3 5 Half Swing Watts 249 374 140 171 058 O64 035 o42 oof 483 653 Note 1 The above power consumption assumes that all ports are functioning at Gen2 5 0 GT S speeds Power consumption can be reduced by turning off unused ports through software or through boot EEPROM Power savings will occur in VppPEA VppPEHA and VppPETA Power savings can be estimated as directly proportional to the number of unused ports since the power consumption of a turned off port is close to zero For example if 3 ports out of 16 are turned off then the power savings for each of the above three power rails can be calculated quite simply as 3 16 multiplied by the power consumption indicated in the above table Note 2 Using a port in Gen1 mode 2 5GT S results in approximately 18 power savings for each power rail VppPEA VppPEHA and VppPETA 18 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Thermal Considerations This section describes thermal considerations for the PES32NT8BG2 23mm FCBGA484 package The data in Table 19 below contains informa tion that is relevant to the thermal performance of the PES32NT8BG2 switch Symbol Parameter Value Units Conditions Ty max Junction Temperature 125 C Maximum TA max Ambient Temperature 70 C Maximum for commercial rated products 85 C Maximum for industrial r
9. Y N v9824 HOlld Wu 001 0310382 M3IN32 Agog WW Q ec x occ 60 27 60 IF nawa ya q 3Nnino 3ovxOvd 91H 1H suu awa swosaav 9 a 7 ZLsc vgz 80 xv U109 QU MMM ub TE 958 001 OOZ8 v8 80v 3NOHd aF V FX ygy 8 156 vO esor uos Lai YVINONY IWNID30 Ai Pa AdIIOA 49949 J9A S vZ09 Q3lJ03dS SS31Nn NV AG TA S39NvHi3101 258 0077 9S8 00 76 N lt ulugg z 3uBieu eabeyoed unu uiulgg z iuBieu abeyoed euruoN 910N 0G WON NIA ANON n i vid 9303P SYALINITIIN NI 38v SNOISN3AIO T n gt m lt lt TVNOILdO SI XINX09 HIV JO 3dvHS LOVX A008 3OvMOvd NO JYNLVJA YIHLO YO NOLVIN3ONI ONDISVI G3ZIMVIGN AYVA ANI Uno AG Chuna 38 LSAW YINYOO Ql LV Iva STIVH 430105 3Hl JO SNMOWO W lYAHdS JHL A8 O3NH30 Jay 9 WNOlVO AYWAINd ONY SNWId ONIIV3S p NALO ANvWiBd Ol TV 00000000000 00000000000 ini Tva 430105 WAXY V G4YNSVAN SI OISN3 OOOOOOOOOOO0O0O0O0O0O0000000 OOOOO0000000j0 0000000000 wag noma FHL SINISI 0000000000000000000000 ooo0oo0000000000000000000 JZS XIMINW TE 30108 WAAMA HL SINISI OOOODOODOGODOOSOOUUQUO 0000000000000000000000 Olld 0X9 TWE M3O10S 2ISYG FHL SINASI j oo000000000000000000000 oooooo0oo0000000000000000 0000000000000000000000 OOOOOOOOOO00J O00O0OOOOOOO 0000000000000000000000 OOOOOOOOOOOOoOOOOOOOOOO 00000000000 6000 600000000000 00000000000 00000000000 OOOOOOOOOOO0 0000000000000000000000 O
10. 1 0 pin 1st Alternate function pin name PART2PERSTN 1st Alternate function pin type Input Output 1st Alternate function Assertion of this signal initiated a partition funda mental reset in the corresponding partition 2nd Alternate function pin name PALINKUPN 2nd Alternate function pin type Output 2nd Alternate function Port 4 Link Up Status output GPIO 3 1 0 General Purpose I O This pin can be configured as a general purpose O pin 1st Alternate function pin name PART3PERSTN 1st Alternate function pin type Input Output 1st Alternate function Assertion of this signal initiated a partition funda mental reset in the corresponding partition 2nd Alternate function pin name PAACTIVEN 2nd Alternate function pin type Output 2nd Alternate function Port 4 Link Active Status Output GPIO 4 O General Purpose I O This pin can be configured as a general purpose O pin 1st Alternate function pin name FAILOVERO 1st Alternate function pin type Input 1st Alternate function When this signal changes state and the correspond ing failover capability is enabled a failover event is signaled 2nd Alternate function pin name POLINKUPN 2nd Alternate function pin type Output 2nd Alternate function Port 0 Link Up Status output GPIO 5 1 0 General Purpose I O This pin can be configured as a general purpose O pin 1st Alternate function pin name GPEN 1st Alternate function
11. PERSTN A12 PEO4TP2 B16 PEO4TN1 C20 JTAG TRST N A13 Vss B17 PEO4TNO C21 SSMBDAT A14 PO4CLKP B18 Vppl O C22 Vppl O A15 Vss B19 MSMBCLK D1 Vss A16 PE04TP1 B20 JTAG_TMS D2 Vss A17 PEO4TPO B21 SSMBCLK D3 Vss A18 Vppl O B22 JTAG TCK D4 Vss A19 MSMBDAT C1 Vss D5 PEO6RP3 A20 JTAG TDO C2 Vppl O D6 PEO6RN2 A21 CLKMODE1 C3 Vss D7 Vss A22 SSMBADDR2 C4 Vss D8 PEO6RP1 B1 Vss C5 PEO6RN3 D9 Vss B2 Vppl O C6 Vss D10 PEO6RPO B3 PEO6TN3 C7 Vas D11 REFRESPLL B4 PEO6TN2 C8 PEO6RN1 D12 Vgg Table 24 PES32NT8BG2 Signal Pin Out Part 1 of 7 25 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Pin Function Alt Pin Function Alt Pin Function Alt D13 PEO4RP3 E17 PEO4RP1 F21 PEO2TN2 D14 Vss E18 VppPEHA F22 PEO2TP2 D15 PEO4RP2 E19 Vss Gi PEO8TPO D16 Vss E20 Vss G2 PEO8TNO D17 PEO4RN1 E21 PEO2TN3 G3 Vss D18 PEO4RPO E22 PE02TP3 G4 PEO8RN1 D19 Vss F1 Vas G5 PEO8RP1 D20 JTAG TDI F2 Vss G6 VppPEA D21 Vppl O F3 PEO8RNO G7 Vss D22 Vppl O F4 PEO8RPO G8 VppCORE E1 Vss F5 VppPEHA G9 VppCORE E2 Vss F6 VppPEHA G10 Vss E3 Vss F7 VppPEHA G11 VppCORE E4 Vss F8 VppPEA G12 VppCORE E5 VppPEHA F9 VppPETA G13 Vss E6 PEO6RP2 F10 VppPEA G14 VppCORE E7 VppPEA F11 VgpPEA G15 VpgCORE E8 VppPEA F12 VppPETA G16 Vss E9 VppPETA F13 VppPETA G17 VppPE
12. Transaction Layer Transaction Layer Route Table Transaction Layer Data Link Layer Data Link Layer Data Link Layer x x x Multiplexer Demultiplexer Multiplexer Demultiplexer Multiplexer Demultiplexer Phy Phy Phy Phy Phy Phy Phy Phy Phy Phy Phy Phy Logical Logical Logical Logical Logical Logical Logical Logical Logical Logical Logical Logical Layer Layer Layer Layer Layer Layer Layer Layer Layer Layer Layer Layer SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes Port 0 Port 2 Ports 4 6 8 12 16 Port 20 rdi E Figure 1 PES32NT8BG2 Block Diagram Function Number Description NTB ports Up to 8 Each device can be configured to have up to 8 NTB functions and can support up to 8 CPUs roots Mapping table Up to 64 for entire Each device can have up to 64 masters ID for address and ID translations entries device Mapping windows Six 32 bits or three Each NT port has six BARs where each BAR opening an NT window to another domain 64 bits Address translation Direct address and Lookup table translation divides the BAR aperture into up to 24 segments where each segment lookup table trans has independent translation programming and is associ
13. allow performance power savings tuning SerDes power savings e Supports low swing half swing SerDes operation SerDes associated with unused ports are turned off SerDes associated with unused lanes are placed in a low power state Reliability Availability and Serviceability RAS ECRC support AER on all ports SECDED ECC protection on all internal RAMs End to end data path parity protection Checksum Serial EEPROM content protected Ability to generate an interrupt INTx or MSI on link up down transitions Initialization Configuration Supports Root BIOS OS or driver Serial EEPROM or SMBus switch initialization Common switch configurations are supported with pin strap ping no external components Supports in system Serial EEPROM initialization program ming On Die Temperature Sensor Range of 0 to 127 5 degrees Celsius Three programmable temperature thresholds with over and under temperature threshold alarms Automatic recording of maximum high or minimum low temperature 9 General Purpose I O Test and Debug Ability to inject AER errors simplifies in system error handling software validation Oncchip link activity and status outputs available for several ports Per port link activity and status outputs available using external IC I O expander for all remaining ports Supports IEEE 1149 6 AC JTAG and IEEE 1149 1 JTAG 2 of 35 Standards and Compatibility PCI Exp
14. pin type Output 1st Alternate function Hot plug general purpose even output 2nd Alternate function pin name POACTIVEN 2nd Alternate function pin type Output 2nd Alternate function Port 0 Link Active Status Output Table 5 General Purpose I O Pins Part 1 of 2 7 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Signal Type Name Description GPIO 6 yo General Purpose 1 0 This pin can be configured as a general purpose 1 0 pin 1st Alternate function pin name FAILOVER1 1st Alternate function pin type Input 1st Alternate function When this signal changes state and the correspond ing failover capability is enabled a failover event is signaled 2nd Alternate function pin name FAILOVER3 2nd Alternate function pin type Input 2nd Alternate function When this signal changes state and the correspond ing failover capability is enabled a failover event is signaled GPIO 7 1 0 General Purpose 1 0 This pin can be configured as a general purpose I O pin 1st Alternate function pin name FAILOVER2 1st Alternate function pin type Input 1st Alternate function When this signal changes state and the correspond ing failover capability is enabled a failover event is signaled 2nd Alternate function pin name P8BLINKUPN 2nd Alternate function pin type Output 2nd Alternate function Port 8 Link Up Status output GPIO 8 yo General Purpose 1 0 This pin can be configured as a general purpose O pin 1s
15. 0 e mA Vop 1 5V Schmitt Vi 0 3 0 8 0 3 0 8 Trigger 0 5 0 5 Input Vi 0 3 0 8 0 3 0 8 Vin 2 0 Vppl O 2 0 Vppl O t 0 5 0 5 3 3V Output VoL 0 4 0 4 V lo 8mA for Low Voltage JTAG TDO and GPIO pins 3 3V Output Vou 2 4 24 V lop 8mA for High Volt JTAG TDO age and GPIO pins December 17 2013 IDT 89HPES32NT8BG2 Datasheet Geni Gen2 Uni Cond 1 O Type Parameter Description tions Min Typ Max Min Typ Max Capacitance Cn s 8 5 a 8 5 pF Table 20 DC Electrical Characteristics Part 3 of 4 22 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Gen1 Gen2 Unit Condi 1 O Type Parameter Description tions Min Typ Max Min Typ Max Leakage Inputs 10 10 uA Vppl O max IO Eak w o 10 10 pA Vppl O max Pull ups downs IO Eak with 80 80 uA Vppl O max Pull ups downs Table 20 DC Electrical Characteristics Part 4 of 4 1 Minimum Typical and Maximum values meet the requirements under PCI Express Base Specification 2 1 Absolute Maximum Voltage Rating PCle PCle Analog PCle Analog pi Core Supply Transmitter I O Supply Supply High Supply Supply 1 5V 1 5V 4 6V 1 5V 4 6V SMBus Characterization Table 21 PES32NT8BG2 Absolute Maximum Volta
16. 2NT8BG2 Signal Pin Out Part 3 of 7 27 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Pin Function Alt Pin Function Alt Pin Function Alt L15 VppCORE M19 Vas P1 PE12TP1 L16 Vss M20 Vgg P2 PE12TN1 L17 VppPEA M21 PEO2TNO P3 Vss L18 PEO2RPO M22 PEO2TPO P4 Vss L19 PEO2RNO N1 PE12TPO P5 VppPETA L20 Vss N2 PE12TNO P6 VppPETA L21 PEO2TN1 N3 REFRES04 P7 Vas L22 PEO2TP1 N4 PE12RN1 P8 VppCORE M1 Vss N5 PE12RP1 P9 VppCORE M2 Vss N6 VppPEA P10 Vss M3 PE12RNO N7 Vg P11 VppCORE M4 PE12RPO N8 VppCORE P12 VppCORE M5 VppPEA N9 VppCORE P13 Vas M6 VppPEA N10 Vgg P14 VppCORE M7 Vgg N11 VppCORE P15 VppCORE M8 VppCORE N12 VppCORE P16 Vss M9 VppCORE N13 Vss P17 VppPEA M10 Vas N14 VppCORE P18 PEOORP2 M11 VppCORE N15 VppCORE P19 PEOORN2 M12 VppCORE N16 Vgg P20 Vss M13 Vss N17 VppPEA P21 PEOOTN3 M14 VppCORE N18 VppPEA P22 PEOOTP3 M15 VppCORE N19 PEOO0RP3 R1 Vss M16 Vss N20 PEOORN3 R2 Vss M17 VppPEA N21 Vss R3 PE12RN2 M18 VppPEA N22 Vgg R4 PE12RP2 Table 24 PES32NT8BG2 Signal Pin Out Part 4 of 7 28 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Pin Function Alt Pin Function Alt Pin Func
17. A E10 VppPEA F14 VgpPEA G18 VppPEA E11 REFRES03 F15 VppPEA G19 PEO2RP3 E12 VppPETA F16 VppPEA G20 PEO2RN3 E13 NC F17 VgpPEHA G21 Vss E14 Vss F18 VppPEHA G22 Vss E15 VppPEA F19 VgpPEHA H1 PEO8TP1 E16 Vss F20 Vss H2 PEO8TN1 Table 24 PES32NT8BG2 Signal Pin Out Part 2 of 7 26 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Pin Function Alt Pin Function Alt Pin Function Alt H3 REFRES05 J7 Vas K11 VppCORE H4 Vss J8 VppCORE K12 VppCORE H5 VppPEA J9 VppCORE K13 Vss H6 VppPEA J10 Vas K14 VppCORE H7 Vss J11 VppCORE K15 VppCORE H8 VppCORE J12 VppCORE K16 Vgg H9 VppCORE J13 Vss K17 VppPETA H10 Vas J14 VppCORE K18 REFRESO1 H11 VppCORE J15 VppCORE K19 PEO2RP1 H12 VppCORE J16 Vss K20 PEO2RN1 H13 Vss J17 VppPETA K21 Vss H14 VppCORE J18 VppPETA K22 Vgg H15 VppCORE J19 REFRESOO L1 PEOBTP3 H16 Vss J20 NC L2 PEO8TN3 H17 VppPEA J21 PO2CLKN L3 Vss H18 PEO2RP2 J22 PO2CLKP L4 Vss H19 PEO2RN2 K1 PE08TP2 L5 VppPEA H20 Vss K2 PEO8TN2 L6 VppPEA H21 POOCLKN K3 Vss L7 Vss H22 POOCLKP K4 PEO8RN3 L8 VppCORE J1 Vss K5 PEO8RP3 L9 VppCORE J2 Vss K6 VppPETA L10 Vas J3 PEO8RN2 K7 Vss L11 VgpCORE J4 PEO8RP2 K8 VppCORE L12 VppCORE J5 VppPETA K9 VppCORE L13 Vgg J6 VppPETA K10 Vss L14 VppCORE Table 24 PES3
18. G Data Input This is the serial data input to the boundary scan logic or JTAG Controller JTAG_TDO 0 JTAG Data Output This is the serial data shifted out from the boundary scan logic or JTAG Controller When no data is being shifted out this signal is tri stated JTAG_TMS JTAG Mode The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller JTAG_TRST_N JTAG Reset This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller An external pull up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal However for systems running in functional mode one of the following should occur 1 actively drive this signal low with control logic 2 statically drive this signal low with an external pull down on the board Table 8 Test Pins 9 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Signal Type Name Description REFRES 7 0 External Reference Resistor Reference for the corresponding SerDes bias currents and PLL calibration circuitry A 3K Ohm 1 resistor should be connected from this pin to ground and isolated from any source of noise injection Each bit of this signal corresponds to a SerDes quad e g REFRESJ 5 is the reference resistor for SerDes quad 5 REFRESPLL PLL External Reference Resistor Provides a reference for the PLL bias currents and PLL calib
19. OOOOOOOOOOCcOOOOOOOOO 0000000000000000000000 C86 NG v LA ISNY OL WHOINOD SNIONVHTTOL NY SNINOISN3A FH NUAAEANMOSISAEHAISZSESEN 60 22 60 3SV313M VILINI Q3 0Nddv 3iva NOlIdl4i2S3d SNOISIA3H December 17 2013 33 of 35 IDT 89HPES32NT8BG2 Datasheet Revision History October 27 2010 Initial publication of final data sheet November 11 2010 Added ZB silicon on Ordering page January 26 2011 In Table 18 Power Consumption revised IO and Total power numbers in Full Swing section and added Half Swing section Adjusted P value in Table 19 March 9 2011 In Table 10 deleted External pull down from the Notes column for JTAG TRST N March 28 2011 In Tables 16 and 17 added VppPETA to footnote 1 May 20 2011 Removed ZA silicon and added ZC to Order page and codes November 7 2011 Revised values in Table 18 Power Consumption and updated power dissipation value in Table 19 November 29 2011 Added new Tables 22 and 23 SMBus Characterization and Timing March 14 2012 In Table 3 revised description for GCLKN P signals April 16 2013 In Table 20 added 3 3V output voltage parameters under Other I Os category May 16 2013 Added Note after Table 11 In Table 20 added information in the Conditions column for the 3 3V parameters December 17 2013 Added footnote 2 to Table 23 34 of 35 December 17 2013 ID
20. T 89HPES32NT8BG2 Datasheet Ordering Information NN A NNAANA AN AA AAA A Legend A Alpha Character N Numeric Character Product Operating Product Generation Device Package Temp Range Family Voltage Detail Series Revision Blank Commercial Temperature 0 C to 70 C Ambient Industrial Temperature 40 C to 85 C Ambient HL 484 ball FCBGA HLG 484 ball FCBGA Green ZB ZB revision ZC ZC revision G2 PCle Gen 2 32NT8B 32 lane 8 port H 1 0V Core Voltage 89 Serial Switching Product Valid Combinations 89H32NT8BG2ZBHL 484 ball FCBGA package Commercial Temp 89H32NT8BG2ZCHL 484 ball FCBGA package Commercial Temp 89H32NT8BG2ZBHLG 484 ball Green FCBGA package Commercial Temp 89H32NT8BG2ZCHLG 484 ball Green FCBGA package Commercial Temp 89H32NT8BG2ZBHLI 484 ball FCBGA package Industrial Temp 89H32NT8BG2ZCHLI 484 ball FCBGA package Industrial Temp 89H32NT8BG2ZBHLGI 484 ball Green FCBGA package Industrial Temp 89H32NT8BG2ZCHLGI 484 ball Green FCBGA package Industrial Temp CORPORATE HEADQUARTERS for SALES for Tech Support l D 6024 Silver Creek Valley Road 800 345 7015 or 408 284 8200 email ssdhelp eng idt com e San Jose CA 95138 www idt com DISCLAIMER Integrated Device Technology Inc IDT and its subsidiaries reserve the right to modify the products and or specifications described herein at any time and at IDT s sole discretion All inf
21. TKICFGO Y6 Vg AA10 PE16TN3 W3 STK2CFGO YT Vas AA11 Vss W4 Vppl O Y8 PE16RN2 AA12 GCLKN1 W5 PE16RPO Y9 Vss AA13 Vas W6 PE16RN1 Y10 Vss AA14 PE20TNO W7 REFRESO6 Y11 PE16RN3 AA15 PE20TN1 W8 PE16RP2 Y12 Vss AA16 Vgs W9 Vss Y13 PE20RNO AA17 PE20TN2 W10 Vss Y14 Vgg AA18 PE20TN3 W11 PE16RP3 Y15 REFRESO7 AA19 Vas W12 Vss Y16 PE20RN2 AA20 GPIO 03 2 W13 PE20RPO Y17 Vss AA21 GPIO 04 2 W14 PE20RN1 Y18 Vss AA22 GPIO_05 2 W15 Vss Y19 PE20RN3 AB1 SWMODE1 W16 PE20RP2 Y20 GPIO_06 2 AB2_ RSTHALT W17 Vss Y21 GPIO_07 2 AB3_ SWMODE2 W18 VppPEHA Y22 GPIO_08 2 AB4 SWMODE3 W19 PE20RP3 AA1 CLKMODEO AB5 Vppl O W20 Vppl O AA2 GCLKFSEL AB6 PE16TPO Table 24 PES32NT8BG2 Signal Pin Out Part 6 of 7 30 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Pin Function Alt Pin Function Alt Pin Function Alt AB7 PE16TP1 AB13 Vss AB19 Vss AB8 Vss AB14 PE20TPO AB20 GPIO_00 2 AB9 PE16TP2 AB15 PE20TP1 AB21 GPIO 01 2 AB10 PE16TP3 AB16 Vas AB22 GPIO 02 2 AB11 Vss AB17 PE20TP2 AB12 GCLKP1 AB18 PE20TP3 Table 24 PES32NT8BG2 Signal Pin Out Part 7 of 7 31 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet JO 133HS L8Cv 9Sd ON 9NIMVSO v9824 HOlld Ww 00 Agog ww Q ez x oez 20781760 IE Nava 3Nnino 39vxovd 91H TH suu S IvAOMuddv
22. ZiGc vez 80v Kw woo J Mum kou Y O0Z8 v8Z 80v 3NOHd A U FX 3NYld ONILWAS 8 156 v2 esor uos AG avnony avwa 00 000 KA od o0 oL rcc fe E NSRO LLL pL Q3i423dS SS31Nn 2 CERRO Pay Adlon 49939 4901S Z09 S3ONV33101 pra o o O oo0oo0000000 oo0oo0000000 oo0o0o0 ooo o o OOOOO 000000 OOOOOOOOOO0 OOOOOOOO0O0004 OOOOO0O0000007 oo0oo000000000 OOOOOOOOO00 OOOOOOOOOOO OOOOOOOOOOO oo0o000000000 OOOOOOOOOOO OOOOOOOOOOO0 oo0oo000000000 oo0oo0o00000000 ooo0oo0000000 oooo0oo0000000 QOo0n0n00o0n0o0aaoa OO loDOoOoOoOoOoOoOOO OOOOOOOOOOOOO0O0 oooopoo0oo00000000 ooooopo0oo000000000 OO0O0OOOOO0OOOOOOOOOOO OOO0O0O0000 00000000000 O00000000 00000000000 OOO0OO0O0O0O000000000000 O0000000 00000000000 a aatatel OO0O0O0O0C OOOOOOO00O0000 OOOOOOOOOO0O OO0000000000 O a Bv Ww A M n L 4 d N W 1 A r H 4 3 a 8 Y OOOOOO O000000 OOOOOO O00000 0c z 44 60 22 60 3Sv3134 VILINI G3 0Ndav iva NOILdI4OS3Q SNOISIA33 PES32NT8BG2 Package Drawing 484 Pin HL HLG484 December 17 2013 32 of 35 IDT 89HPES32NT8BG2 Datasheet PES32NT8BG2 Package Drawing Page Two Z 40 Z 133HS ONIMVEC 31v9S LON OQ L8Cv 9Sd
23. ace MSMBDAT n r1 JTAG TMS m H JTAG TRST N STK S0JCFG0 gt D System CLKMODE 1 0 gt L y cope Pins RSTHALT gt L Vp 0 PERSTN I VapPEA 4 DD Power Ground 0 SWMODE 3 0 VopPEHA VppPETA Vss Figure 3 PES32NT8BG2 Logic Diagram 13 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures as shown in Tables 16 and 15 Parameter Description Condition Min Typical Max Unit Refclkrreq Input reference clock frequency range 100 125 MHz Tc RISE Rising edge rate Differential 0 6 4 Vins TC FALL Falling edge rate Differential 0 6 4 Vins Vin Differential input high voltage Differential 150 mV Vi Differential input low voltage Differential 150 mV VcRoss Absolute single ended crossing point Single ended 250 550 mV voltage VCROSS DELTA Variation of Vorogg over all rising clock Single ended 140 mV edges Vnp Ring back voltage margin Differential 100 100 mV TerABLE Time before Vpp is allowed Differential 500 ps TPERIOD AVG Average clock period accuracy 300 2800 ppm TPERIOD ABS Absolute period including spread spec 9 847 10 203 ns trum and jitter Tcc JITTER Cycle to cycle jitter 150 ps Vax Absolute maximum input voltage 1 15 V VMIN Abs
24. ansfers to multicast groups Linked list descriptor based operation Flexible addressing modes Linear addressing Constant addressing Quality of Service QoS Port arbitration Round robin Request metering DT proprietary feature that balances bandwidth among Switch ports for maximum system throughput High performance switch core architecture Combined Input Output Queued CIOQ switch architecture with large buffers Clocking Supports 100 MHz and 125 MHz reference clock frequencies Flexible port clocking modes Common clock Non common clock Local port clock with SSC spread spectrum setting and port reference clock input IDT and the IDT logo are registered trademarks of Integrated Device Technology Inc 2013 Integrated Device Technology Inc 1 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Hot Plug and Hot Swap Hot plug controller on all ports Hot plug supported on all downstream switch ports All ports support hot plug using low cost external 1 C 1 0 expanders Configurable presence detect supports card and cable appli cations GPE output pin for hot plug event notification Enables SCI SMI generation for legacy operating system support Hot swap capable I O Power Management Supports DO D3hot and D3 power management states Active State Power Management ASPM Supports LO LOs L1 L2 L3 Ready and L3 link states Configurable LOs and L1 entry timers
25. ated products 15 2 C W Zero air flow OJA effective Effective Thermal Resistance Junction to Ambient 8 5 C W 1 m air flow 74 C W 2 m S air flow 0jB Thermal Resistance Junction to Board 3 1 C W Ojc Thermal Resistance Junction to Case 0 15 C W P Power Dissipation of the Device 7 19 Watts Maximum Table 19 Thermal Specifications for PES32NT8BG2 23x23 mm FCBGA484 Package Note It is important for the reliability of this device in any user environment that the junction temperature not exceed the T jm value specified in Table 19 Consequently the effective junction to ambient thermal resistance Oa for the worst case scenario must be maintained below the value determined by the formula OJA TJ max d Ta max P Given that the values of T maj Ta max and P are known the value of desired 0 4 becomes a known entity to the system designer How to achieve the desired 0 j4 is left up to the board or system designer but in general it can be achieved by adding the effects of jc value provided in Table 19 thermal resistance of the chosen adhesive Ocg that of the heat sink Osa amount of airflow and properties of the circuit board number of layers and size of the board It is strongly recommended that users perform their own thermal analysis for their own board and system design scenarios 19 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet DC Electrical Characteristics Values based on systems running at recommen
26. ated with an entry in a look up table lations Doorbell registers 32 bits Doorbell register is used for event signaling between domains where an outbound doorbell bit sets a corresponding bit at the inbound doorbell in the other domain Message registers 4 inbound and out Message registers allow mailbox message passing between domains message placed in the bound registers of inbound register will be seen at the outbound register at the other domain 32 bits Table 1 Non Transparent Bridge Function Summary SMBus Interface The PES32NT8BG2 contains two SMBus interfaces The slave interface provides full access to the configuration registers in the PES32NT8BG2 allowing every configuration register in the device to be read or written by an external agent The master interface allows the default configuration register values of the PES32NT8BG2 to be overridden following a reset with values programmed in an external serial EEPROM The master interface is also used by an external Hot Plug I O expander 3 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Each of the two SMBus interfaces contain an SMBus clock pin and an SMBus data pin In addition the slave SMBus has the SSMBADDR2 pin As shown in Figure 2 the master and slave SMBuses may only be used in a split configuration In the split configuration the master and slave SMBuses operate as two independent buses thus multi master arbitration is not required The SMBus mas
27. ded supply voltages as shown in Table 16 Note See Table 10 Pin Characteristics for a complete 1 O listing Gent Gen2 Unit cone 1 O Type Parameter Description tions Min Typ Max Min Typ Max Serial Link PCle Transmit VTX DIFFp p Differential peak to peak output 800 1200 800 1200 mV voltage Vrx piFFp pLow Low Drive Differential Peak to 400 1200 400 1200 mV Peak Output Voltage Vrxpe RArio De emphasized differential out 3 4 3 0 3 5 4 0 dB 3 5dB put voltage VIYX DE RATIO De emphasized differential out NA 5 5 6 0 6 5 dB 6 0dB put voltage VrTX DC CM DC Common mode voltage 0 3 6 0 3 6 V VrTX CM ACP RMS AC peak common mode 20 mV output voltage VrX CM DC Abs delta of DC common mode 100 100 mV active idle delta voltage between LO and idle Vrx cM DC ine Abs delta of DC common mode 25 25 mV delta voltage between D and D VTx Idle DiffP Electrical idle diff peak output 20 20 mV RLty piFF Transmitter Differential Return 10 10 dB 0 05 1 25GHz loss 8 dB 1 25 2 5GHz RLty cm Transmitter Common Mode 6 6 dB Return loss ZTX DIFF DC DC Differential TX impedance 80 100 120 120 Q VTX CM ACpp Peak Peak AC Common NA 100 mV VTxX DC CM Transmit Driver DC Common 0 3 6 0 3 6 V Mode Voltage Vrx ncv perecT The amount of voltage change 600 600 mV allowed during Receiver Detec tion ItX SHORT Transmi
28. ge Rating Warning For proper and reliable operation in adherence with this data sheet the device should not exceed the recommended operating voltages in Table 16 The absolute maximum operating voltages in Table 21 are offered to provide guidelines for voltage excursions outside the recommended voltage ranges Device functionality is not guaranteed at these conditions and sustained operation at these values or any exposure to voltages outside the maximum range may adversely affect device functionality and reliability SMBus 2 0 Char Data Symbol Parameter Unit 3V 3 3V 3 6V DC Parameter for SDA Pin Vi Input Low 1 16 1 26 1 35 Vin Input High 1 56 1 67 1 78 V VoL G350uA Output Low 15 15 15 mV loLeo4v 23 24 25 mA lPullup Current Source uA li Leak Input Low Leakage 0 0 0 uA lH Leak Input High Leakage 0 0 0 uA Table 22 SMBus DC Characterization Data Part 1 of 2 23 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet SSS ee SMBus 2 0 Char Data Symbol Parameter Unit 3V 3 3V 3 6V DC Parameter for SCL Pin Vi y Input Low 1 11 1 2 1 31 V Vin V Input High 1 54 1 65 1 76 V li Leak Input Low Leakage 0 0 0 pA lH Leak Input High Leakage 0 0 0 uA Table 22 SMBus DC Characterization Data Part 2 of 2 1 Data at room and hot temperature SMBus G8 3V 10 Symbol Parameter U
29. h partitions Dynamic port reconfiguration downstream upstream non transparent bridge Dynamic migration of ports between partitions Movable upstream port within and between switch partitions Non Transparent Bridging NTB Support Supports up to 8 NT endpoints per switch each endpoint can communicate with other switch partitions or external PCle domains or CPUs 6 BARs per NT Endpoint Bar address translation 32 Lane 8 Port PCle amp Gen2 System Interconnect Switch 89HPES32NT8BG2 Datasheet All BARs support 32 64 bit base and limit address translation Two BARs BAR2 and BAR4 support look up table based address translation 32 inbound and outbound doorbell registers 4 inbound and outbound message registers Supports up to 64 masters Unlimited number of outstanding transactions Multicast Compliant with the PCI SIG multicast Supports 64 multicast groups Supports multicast across non transparent port Multicast overlay mechanism support ECRC regeneration support Integrated Direct Memory Access DMA Controllers Supports up to 2 DMA upstream ports each with 2 DMA chan nels Supports 32 bit and 64 bit memory to memory transfers e Fly by translation provides reduced latency and increased performance over buffered approach Supports arbitrary source and destination address alignment e Supports intra as well as inter partition data transfers using the non transparent endpoint Supports DMA tr
30. ifferential PCI Express receive pairs for PEO2RPT 3 0 port 2 PEO2TN 3 0 O PCI Express Port 2 Serial Data Transmit Differential PCI Express transmit pairs for PEO2TP 9 0 port 2 PEO4RN 9 0 PCI Express Port 4 Serial Data Receive Differential PCI Express receive pairs for PEO4RPT 3 0 port 4 PEO4TN 3 0 O PCI Express Port 4 Serial Data Transmit Differential PCI Express transmit pairs for PEO4TP 3 0 port 4 PEO6RN 3 0 PCI Express Port 6 Serial Data Receive Differential PCI Express receive pairs for PEO6RP 3 0 port 6 PEO6TN 3 0 O PCI Express Port 6 Serial Data Transmit Differential PCI Express transmit pairs for PEO6TP 3 0 port 6 PEO8RN 9 0 PCI Express Port 8 Serial Data Receive Differential PCI Express receive pairs for PEO8RP 3 0 port 8 PEO8TN 3 0 O PCI Express Port 8 Serial Data Transmit Differential PCI Express transmit pairs for PEO8TP 3 0 port 8 PE12RN 3 0 PCI Express Port 12 Serial Data Receive Differential PCI Express receive pairs for PE12RP 3 0 port 12 PE12TN 3 0 O PCI Express Port 12 Serial Data Transmit Differential PCI Express transmit pairs PE12TP 3 0 for port 12 PE16RN 3 0 PCI Express Port 16 Serial Data Receive Differential PCI Express receive pairs for PE16RP 3 0 port 16 PE16TN 3 0 O PCI Express Port 16 Serial Data Transmit Differential PCI Express transmit pairs PE16TP 3 0 for port 16 PE20RN 3 0 PCI Express Port 20 Serial Data Receive Differential PCI Express receive pairs for PE20RP 3 0 port 20
31. ing Waveform 16 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Recommended Operating Temperature Grade Temperature Commercial 0 C to 70 C Ambient Industrial 40 C to 85 C Ambient Table 15 PESS2NT8BG2 Operating Temperatures Recommended Operating Supply Voltages Commercial Temperature Symbol Parameter Minimum Typical Maximum Unit VppCORE Internal logic supply 0 9 1 0 1 1 V Vppl O I O supply except for SerDes 3 125 3 3 3 465 V VppPEA PCI Express Analog Power 0 95 1 0 14 V VppPEHA PCI Express Analog High Power 2 25 2 5 2 75 V VppPETA PCI Express Transmitter Analog Voltage 0 95 1 0 1 1 V Vss Common ground 0 0 0 V Table 16 PES32NT8BG2 Operating Voltages Commercial Temperature 1 VggPEA and VppPETA should have no more than 25MVpeak peak AC power supply noise superimposed on the 1 0V nominal DC value VppPEHA should have no more than 50MVpeak peak AC power supply noise superimposed on the 2 5V nominal DC value Recommended Operating Supply Voltages Industrial Temperature Symbol Parameter Minimum Typical Maximum Unit VppCORE Internal logic supply 0 9 1 0 1 1 V Vppl O I O supply except for SerDes 3 125 3 3 3 465 V VppPEA PCI Express Analog Power 0 95 1 0 1 05 V VppPEHA PCI Express Analog High Power 2 25 2 5 2 75 V VppPETA PCI Express Transmitter Analog Voltage 0 95 1 0 1 1 V Vss Common ground 0 0 0 V
32. le after sending 8 8 ns IDLE an Idle ordered set TTY IDLE TO DIFF Maximum time to transition from valid idle to diff data 8 8 ns DATA TTX SKEW Transmitter data skew between any 2 lanes 1 3 1 3 ns TMIN PULSED Minimum Instantaneous Lone Pulse Width NA 0 9 UI Trx ur DJ DD Transmitter Deterministic Jitter gt 1 5MHz Bandwidth NA 0 15 Ul TRF MISMATCH Rise Fall Time Differential Mismatch NA 0 1 Ul PCle Receive UI Unit Interval 399 88 400 400 12 199 94 200 06 ps TRX EYE with jitter Minimum Receiver Eye Width jitter tolerance 0 4 0 4 Ul Trx EYE MEDIUM ro Max time between jitter median amp max deviation 0 3 Ul MAX JITTER TRX SKEW Lane to lane input skew 20 8 ns TRX HF RMS 1 5 100 MHz RMS jitter common clock NA 3 4 ps TRX HF DJ DD Maximum tolerable DJ by the receiver common clock NA 88 ps TRX LF RMS 10 KHz to 1 5 MHz RMS jitter common clock NA 42 ps TRxX MIN PULSE Minimum receiver instantaneous eye width NA 0 6 UI Table 12 PCle AC Timing Characteristics Part 2 of 2 1 Minimum Typical and Maximum values meet the requirements under PCI Express Base Specification 2 1 Reference Timing Signal Symbol E Min Max Unit Diagram dge Reference GPIO GPIO 8 0 Tpw 13b None 50 ns See Figure 4 Table 13 GPIO AC Timing Characteristics 1 GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous
33. nit Min Max FscL Clock frequency 5 600 KHz Tpur Bus free time between Stop and 3 5 us Start THD STA Start condition hold time 1 us Tsu sta Start condition setup time 1 us Tsu sto Stop condition setup time 1 us THD DAT Data hold time 1 ns Tgy pat Data setup time 1 ns TTIMEOUT Detect clock low time out m 74 7 ms Trow Clock low period 3 7 us Ther Clock high period 3 7 us TF Clock Data fall time 72 2 ns TR Clock Data rise time 68 3 ns TpoR 1okHz Time which a device must be 20 ms operational after power on reset Table 23 SMBus AC Timing Data 1 Data at room and hot temperature 2 T ow and Tyigy are measured at Fac 135 kHz 24 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Package Pinout 484 BGA Signal Pinout for the PES32NT8BG2 The following table lists the pin numbers and signal names for the PES32NT8BG2 device Note Pins labeled NC are No Connection Pin Function Alt Pin Function Alt Pin Function Alt Al Vss B5 Vss c9 Vss A2 Vppl O B6 PEO6TN1 C10 PEO6RNO A3 PEO6TP3 B7 PEO6TNO C11 Vss A4 PEO6TP2 B8 Vss C12 Vgg A5 Vss B9 GCLKNO C13 PEO4RN3 A6 PEOGTP1 B10 Vss C14 Vss A7 PEO6TPO B11 PEO4TN3 C15 PEO4RN2 A8 Vss B12 PEO4TN2 C16 REFRES02 A9 GCLKPO B13 Vss C17 Vss A10 Vss B14 PO4CLKN C18 PEO4RNO All PEO4TP3 B15 Vss C19
34. olute minimum input voltage 0 3 V Duty Cycle Duty cycle 40 60 Rise Fall Matching Single ended rising Refclk edge rate ver 20 Yo sus falling Refclk edge rate Zc pc Clock source output DC impedance 40 60 Q Table 11 Input Clock Requirements 1 The input clock frequency will be either 100 or 125 MHz depending on signal GCLKFSEL Note Refclk jitter compliant to PCle Gen2 Common Clock architecture is adequate for the GCLKN P x and PE x CLKN P pins of this IDT PCle switch This same jitter specification is applicable when interfacing the switch to another IDT switch in a Separate Non Common Clock architecture AC Timing Characteristics Gen 1 Gen 2 Parameter Description 1 1 1 1 1 1 Units Min Typ Max Min Typ Max PCle Transmit UI Unit Interval 399 88 400 400 12 199 94 200 200 06 ps TIX EYE Minimum Tx Eye Width 0 75 0 75 Ul TTX EYE MEDIAN to Maximum time between the jitter median and maxi 0 125 Ul MAX JITTER mum deviation from the median Table 12 PCle AC Timing Characteristics Part 1 of 2 14 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Parameter Description Sm aiii Units Min Typ Max Min Typ Max Trx ise TTx FALL TX Rise Fall Time 20 80 0 125 0 15 UI TTX IDLE MIN Minimum time in idle 20 20 UI TTX IDLE SET TO Maximum time to transition to a valid Id
35. ormation in this document including descriptions of product features and performance is subject to change without notice Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products The information contained herein is provided without representation or warranty of any kind whether express or implied including but not limited to the suitability of IDT s products for any particular purpose an implied warranty of merchantability or non infringement of the intellectual property rights of others This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties IDT s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users Anyone using an IDT product in such a manner does so at their own risk absent an express written agreement by IDT Integrated Device Technology IDT and the IDT logo are registered trademarks of IDT Other trademarks and service marks used herein including protected names logos and designs are the property of IDT or their respective third party owners Copyright 2013 All rights reserved 35 of 35 December 17 2013
36. ration circuitry A 3K Ohm 1 resistor should be connected from this pin to ground and isolated from any source of noise injection VppCORE Core Vpp Power supply for core logic 1 0V Vpol O 1 0 Vpp LVTTL I O buffer power supply 3 3V VppPEA PCI Express Analog Power Serdes analog power supply 1 0V VppPEHA PCI Express Analog High Power Serdes analog power supply 2 5V VppPETA PCI Express Transmitter Analog Voltage Serdes transmitter analog power supply 1 0V Ground Table 9 Power Ground and SerDes Resistor Pins 10 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Pin Characteristics Note Some input pads of the switch do not contain internal pull ups or pull downs Unused SMBus and System inputs should be tied off to appropriate levels This is especially critical for unused control signal inputs which if left floating could adversely affect operation Also floating pins can cause a slight increase in power consumption Unused Serdes Rx and Tx pins should be left floating Finally No Connection pins should not be connected Function Pin Name Type Buffer 1 0 Type Internal Resistor Notes PCI Express Interface PCI Express Interface cont PEOORN 3 0 PCle PEOORP 3 0 differential PEOOTN 3 0 PEOOTP 3 0 ojlo PEO2RN 3 0 PEO2RP 3 0 PEO2TN 3 0 PEO2TP 3 0 o o
37. ress Base Specification 2 1 compliant Implements the following optional PCI Express features Advanced Error Reporting AER on all ports End to End CRC ECRC Access Control Services ACS Device Serial Number Enhanced Capability Sub System ID and Sub System Vendor ID Capability Internal Error Reporting Multicast VGA and ISA enable LOs and L1 ASPM ARI Power Supplies Requires three power supply voltages 1 0V 2 5V and 3 3V Packaged in a 23mm x 23mm 484 ball Flip Chip BGA with 1mm ball spacing Product Description With Non Transparent Bridging functionality and innovative Switch Partitioning feature the PESS2NT8BG2 allows true multi host or multi processor communications in a single device Integrated DMA control lers enable high performance system design by off loading data transfer operations across memories from the processors Each lane is capable of 5 GT s link speed in both directions and is fully compliant with PCI Express Base Specification 2 1 A non transparent bridge NTB is required when two PCI Express domains need to communicate to each other The main function of the NTB block is to initialize and translate addresses and device IDs to allow data exchange across PCI Express domains The major function alities of the NTB block are summarized in Table 1 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Block Diagram 8 Port Switch Core 32 Gen2 PCI Express Lanes Port Arbitration E HN E
38. sed these signals must SSMBDAT lO STi be pulled up on the board using an external resistor or current source in accordance with the SMBus specifica tion General Purpose I O GPIO 8 0 yo LVTTL STI High pull up Unused pins can be left Drive floating Stack Configuration STKOCFGO l LVTTL Input pull down Unused pins can be left STKICFGO floating STK2CFGO STK3CFGO System Pins CLKMODET 1 0 l LVTTL Input pull up Unused pins can be left GCLKFSEL pull down floating PERSTN Schmitt trigger RSTHALT pull down Unused pins can be left SWMODE 3 0 pull down ating EJTAG JTAG JTAG TCK LVTTL STI pull up Unused pins can be left JTAG TDI STI pull up floating JTAG_TDO 0 JTAG TMS STI pull up JTAG_TRST_N STI pull up SerDes Reference Resis REFRES 7 0 Analog Unused pins should be tors REFRESPLL connected to Vss on the board Table 10 Pin Characteristics Part 2 of 2 1 Internal resistor values under typical operating conditions are 92K Q for pull up and 91K Q for pull down 2 All receiver pins set the DC common mode voltage to ground All transmitters must be AC coupled to the media 3 Schmitt Trigger Input STI 12 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Logic Diagram PES32NT8BG2 Gia GCLKN 1 0 gt GCLKP 1 0 Reference Clock erence Clocks GCLKFSEL
39. t Alternate function pin name IOEXPINTN 1st Alternate function pin type Input 1st Alternate function IO expander interrupt 2nd Alternate function pin name PBACTIVEN 2nd Alternate function pin type Output 2nd Alternate function Port 8 Link Active Status Output Table 5 General Purpose I O Pins Part 2 of 2 Signal Type Name Description STKOCFGO Stack 0 Configuration This pin selects the configuration of stack 0 STK1CFGO Stack 1 Configuration This pin selects the configuration of stack 1 STK2CFGO Stack 2 Configuration This pin selects the configuration of stack 2 STK3CFGO Stack 3 Configuration This pin selects the configuration of stack 3 Table 6 Stack Configuration Pins Signal Type Name Description CLKMODET 1 0 Clock Mode These signals determine the port clocking mode used by ports of the device GCLKFSEL Global Clock Frequency Select These signals select the frequency of the GCLKP and GCLKN signals 0x0 100 MHz 0x1 125 MHz Table 7 System Pins Part 1 of 2 8 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Signal Type Name Description PERSTN Fundamental Reset Assertion of this signal resets all logic inside the device RSTHALT Reset Halt When this signal is asserted during a switch fundamental reset sequence the switch remains in a quasi reset state with the Master and Slave SMBuses active This allo
40. ter interface does not support SMBus arbitration As a result the switch s SMBus master must be the only master in the SMBus lines that connect to the serial EEPROM and I O expander slaves Processor Other SR SMBus SMBus witc Master Devices SSMBCLK LL U SSMBDAT 4 MSMBCLK MSMBDAT Hot Plug yo Expander Serial EEPROM Figure 2 Split SMBus Interface Configuration Hot Plug Interface The PES32NT8BG2 supports PCI Express Hot Plug on each downstream port To reduce the number of pins required on the device the PES32NT8BG2 utilizes an external I O expander such as that used on PC motherboards connected to the SMBus master interface Following reset and configuration whenever the state of a Hot Plug output needs to be modified the PES32NT8BG2 generates an SMBus transaction to the 1 0 expander with the new value of all of the outputs Whenever a Hot Plug input changes the I O expander generates an interrupt which is received on the IOEXPINTN input pin alternate function of GPIO of the PES32NT8BG 2 In response to an I O expander interrupt the PES32NT8BG2 generates an SMBus transaction to read the state of all of the Hot Plug inputs from the I O expander General Purpose Input Output The PES32NT8BG 2 provides 9 General Purpose I O GPIO pins that may be individually configured as general purpose inputs general purpose outpu
41. tion Alt R5 VppPETA T9 VppCORE U13 VppPEA R6 VppPETA T10 Vas U14 VppPEA R7 Vss T11 VppCORE U15 VppPETA R8 VppCORE T12 VppCORE U16 VppPEA R9 VppCORE T13 Vas U17 VppPEHA R10 Vss T14 VppCORE U18 PEOORPO R11 VppCORE T15 VppCORE U19 PEOORNO R12 VppCORE T16 Vss U20 Vss R13 Vss T17 VppPETA U21 PEOOTN1 R14 VppCORE T18 VppPETA U22 PEOOTP1 R15 VppCORE T19 PEOORP1 V1 Vppl O R16 Vss T20 PEOORN1 V2 Vppl O R17 VppPETA T21 Vss V3 PE12RN3 R18 VppPETA T22 Vss V4 PE12RP3 R19 Vss U1 PE12TP3 V5 Vss R20 Vss U2 PE12TN3 V6 PE16RP1 R21 PEOOTN2 U3 Vss V7 Vss R22 PEOOTP2 U4 Vas V8 VppPEA T1 PE12TP2 U5 VppPEHA V9 VppPEA T2 PE12TN2 U6 VppPEHA V10 Vas T3 Vss U7 VppPEA V11 VppPETA T4 Vss U8 VppPEA V12 Vss T5 VppPEHA U9 VppPEA V13 VppPEA T6 VppPEHA U10 VppPETA V14 PE20RP1 T7 Vss Uli VppPETA V15 VppPETA T8 VppCORE U12 VppPEA V16 VppPEA Table 24 PES32NT8BG2 Signal Pin Out Part 5 of 7 29 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Pin Function Alt Pin Function Alt Pin Function Alt V17 VppPEHA W21 Vppl O AA3 SWMODEO V18 VggPEHA W22 Vppl O AM Vgs V19 Vss Yi STKOCFGO AA5 Vppl O V20 Vss Y2 STKSCFGO AA6 PE16TNO V21 PEOOTNO Y3 Vss AA7 PE16TN1 V22 PEOOTPO Y4 Vppl O AA8 Vss Wi Vss Y5 PE16RNO AAQ PE16TN2 W2 S
42. ts or alternate functions All GPIO pins are shared with other on chip functions These alternate functions may be enabled via software SMBus slave interface or serial configuration EEPROM 4 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Pin Description The following tables list the functions of the pins provided on the PES32NT8BG2 Some of the functions listed may be multiplexed onto the same pin The active polarity of a signal is defined using a suffix Signals ending with an N are defined as being active or asserted when at a logic zero low level All other signals including clocks buses and select lines will be interpreted as being active or asserted when at a logic one high level Differential signals end with a suffix N or P The differential signal ending in P is the positive portion of the differential pair and the differential signal ending in N is the negative portion of the differential pair Note Pin x of a port refers to a lane For port 0 PEOORN 0 refers to lane 0 PEOORN 1 refers to lane 1 etc Signal Type Name Description PEOORN 3 0 PCI Express Port 0 Serial Data Receive Differential PCI Express receive pairs for PEOORP 3 0 port 0 PEOOTN 3 0 O PCI Express Port 0 Serial Data Transmit Differential PCI Express transmit pairs for PEOOTP 3 0 port 0 PEO2RN 9 0 PCI Express Port 2 Serial Data Receive D
43. tter Short Circuit Current 0 90 90 mA Limit Table 20 DC Electrical Characteristics Part 1 of 4 20 of 35 December 17 2013 IDT 89HPES32NT8BG2 Datasheet Table 20 DC Electrical Characteristics Part 2 of 4 21 of 35 Gen1 Gen2 Unit cone I O Type Parameter Description tions Min Typ Max Min Typ Max Serial Link PCle Receive cont VRX DIFFp p Differential input voltage peak 175 1200 120 1200 mV to peak RLpgx pirr Receiver Differential Return 10 10 dB 0 05 1 25GHz Loss 8 1 25 2 5GHz RLgx cM Receiver Common Mode Return 6 6 dB Loss ZRX DIFF DC Differential input impedance 80 100 120 Refer to return loss spec Q DC ZRX DC DC common mode impedance 40 50 60 40 60 Q ZRX COMM DC Powered down input common 200k 350k 50k Q mode impedance DC ZRX HIGH IMP DC input CM input impedance 50k 50k Q DC POS for V gt 0 during reset or power down ZgxuiguMP DC input CM input impedance 1 0k 1 0k Q DC NEG for V 0 during reset or power down VRX IDLE DET Electrical idle detect threshold 65 175 65 175 mV DIFFp p VRX CM ACp Receiver AC common mode 150 150 mV VRX CM ACp peak voltage PCle REFCLK Cin Input Capacitance 1 5 1 5 pF Other 1 0s LOW Drive lot 2 5 2 5 E mA Voz 0 4v Pup Ii zs mE 55 mA Vou 15V High Drive lo 12 0 12 0 mA Vor 0 4v SUE m 2
44. ws software to read and write registers internal to the device before normal device operation begins The device exits the quasi reset state when the RSTHALT bit is cleared in the SWCTL register by an SMBus master SWMODE 3 0 Switch Mode These configuration pins determine the switch operating mode These pins should be static and not change following the negation of PERSTN 0x0 Single partition Ox1 Single partition with Serial EEPROM initialization Ox2 Single partition with Serial EEPROM Jump 0 initialization 0x3 Single partition with Serial EEPROM Jump 1 initialization 0x4 through 0x7 Reserved 0x8 Single partition with reduced latency Ox9 Single partition with Serial EEPROM initialization and reduced latency OxA Multi partition with Unattached ports OxB Multi partition with Unattached ports and IC Reset OxC Multi partition with Unattached ports and Serial EEPROM initialization OxD Multi partition with Unattached ports with C Reset and Serial EEPROM initial ization OxE Multi partition with Disabled ports OxF Multi partition with Disabled ports and Serial EEPROM initialization Table 7 System Pins Part 2 of 2 Signal Type Name Description JTAG_TCK JTAG Clock This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller JTAG_TCK is independent of the system clock with a nominal 50 duty cycle JTAG_TDI JTA
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