4DSP-FMC230 Guide
Contents
1. Voltage Pins Max Amps Max Watt 3 3V 4 3A 10 W 12V 2 1A 12 W VADJ 4 4A 10 W VIO_B VADJ 2 1 15A 2 3 W Table 4 FMC standard power specification UM023 www 4dsp com 10 UM023 FMC230 User Manual LJE gt r1 4 The power provided by the carrier card can be very noisy Special care is taken with the power supply generation on the FMC card to minimize the effect of power supply noise on clock generation and data conversion Clean 1 8V is derived from 3 3V with linear regulators Clean 3 3V is derived from 12V in two steps for maximum efficiency The first step uses a high efficient switched regulator to generate a 3 8V power rail From this power rail each analog supply is derived with separate low dropout low noise linear regulators The regulators have sufficient copper area to dissipate the heat in combination with proper airflow see section 6 3 Cooling ADP2301 22mA 12V 45mW sven 120mA 1 5V Eff 85 330mA 1 8Vd ADP151 AD9129 263mW 175mA 1 8Va g50mW e 60mA 1 5Va po die ADP1753 66oma 1 8v Consumption 990mW i 5 6W Max 800mA_ Se G i aud L 330m oa ADP151 AD9129 263mW 175mA 1 8V8 g50mWw __60mA 1 5Va 1010mA VADJ 1010mA 3 3V B may be usod when 252. TRST TCK TMS TDI TDO PRSNT_M2C_L A 3P3V gt CPLD ZN T TRST TCK TMS TDI TDO PRSNT_M2C_L Top connector to FMC carrier Figure 3 JTAG Connection 4 3 Main characteristics Analog outputs s voltage range 1 75 Vpp 9 dBm Output impedance impedance Analogue output bandwidth 1 4GHz please refer to AD9129 datasheet for details UM023 www 4dsp com 7 UM023 FMC230 User Manual i OSH r1 4 External sampling clock input Input Level OdBm typical LVTTL level supported Input impedance 50Q Input range Input RF transformer 4 5 MHz to 3000 MHz AC coupled External reference clock input Input Level OdBm typical LVTTL level supported Input impedance 50Q Input range 1MHz to 250MHz AC coupled External clock output 800mVp p into 50Q typical Output Level LVCMOS output available as build option contact 4DSP External Trigger input f LVTLL LVCMOS33 orma Logic 0 gt max 0 8V Logic 1 gt min 2 0V Frequency range Up to 300 MHz Internal sampling clock F R DAC up to 5300MHz Software selectable contact 4DSP for Kate mange frequencies higher frequencies up to 5600MHz Table 2 FMC daughter card main characteristics 4 4 Analog output channels The DAC output circuit is constructed such different build options can be made The default configuration will be a wideband balun ETC1 1 13 MACOM 4 5 to 3000MHZz Please contac
3. LA18_N_CC C23 DACO_P1_DP01_N HA22_N J22 LA18_P_CC C22 DACO_P1_DP01_P HA22_P J21 LA19_N H23 DACO_P1_DP03_N HA23_N K23 LA19_P H22 DACO_P1_DP03_P HA23_P K22 LA20_N G22 DACO_P1_DP02_N LA20_P G21 DACO_P1_DP02_P LA21_N H26 DACO_P1_DP05_N LA21_P H25 DACO_P1_DP05_P LA22_N G25 DACO_P1_DP04_N LA22_P G24 DACO_P1_DP04_P LA23_N D24 DACO_P1_DP06_N LA23_P D23 DACO_P1_DP06_P LA24_N H29 DACO_P1_DP10_N LA24_P H28 DACO_P1_DP10_P LA25_N G28 DACO_P1_DP09_N LA25_P G27 DACO_P1_DP09_P LA26_N D27 DACO_P1_DP07_N LA26_P D26 DACO_P1_DP07_P LA27_N C27 DACO_P1_DP08_N LA27_P C26 DACO_P1_DP08_P LA28_N H32 DACO_P1_DP12_N LA28_P H31 DACO_P1_DP12_P LA29_N G31 DACO_P1_DP11_N LA29_P G30 DACO_P1_DP11_P LA30_N H35 DACO_P1_DP13_N LA30_P H34 DACO_P1_DP13_P LA31_N G34 FMC_TO_CPLD 1 LA31_P G33 FMC_TO_CPLD 0 CLK_DIR B1 LA32_N H38 FMC_TO_CPLD 3 PG_C2M D PG_C2M LA32_P H37 FMC_TO_CPLD 2 PG_M2C F1 PG_M2C LA33_N G37 DC SCH c30 DC SCH LA33_P G36 12C_SDA c31 12C_SDA Table 7 FMC230 Pinout UO DACO_DCO_P D A 0 Output LVDS Clock coming from the 1st D A converter DACO_DCO_N DACO_DCI_P D A 0 Input LVDS Clock going the 1st D A converter DACO_DCI_N DACO_FRM_P D A 0 Input LVDS Frame going the 1st D A converter DACO_FRM_N DACO_PO_P lt 13 0 gt D A 0 Input LVDS Data bus 0 going the 1st D A converter DACO_PO_N lt 13 0 gt
4. UM023 www 4dsp com 19 UM023 FMC230 User Manual Sr r1 4 DACO_P1_P lt 13 0 gt D A 0 Input LVDS Data bus 1 going the ist D A converter DACO_P1_N lt 13 0 gt DAC1_DCO_P D A 1 Output LVDS Clock coming from the 2nd D A converter DAC1_DCO_N DAC1_DCI_P D A 1 Input LVDS Clock going the 2nd D A converter DAC1_DCI_N DAC1_FRM_P D A 1 Input LVDS Frame going the 2nd D A converter DAC1_FRM_N DAC1_P0O_P lt 13 0 gt D A 1 Input LVDS Data bus 0 going the 2nd D A converter DAC1_P0O_N lt 13 0 gt DAC1_P1_P lt 13 0 gt D A 1 Input LVDS Data bus 1 going the 2nd D A converter DAC1_P1_N lt 13 0 gt CLK_TO_FPGA_P i j H uo Output LVDS Clock coming from the clock tree Typically CLK_TO_FPGA_N used for debug and monitoring purposes EXT_TRIGGER_P i j Ta Output LVDS an of the external trigger EXT_TRIGGER_N ower SPI bus to CPLD on the FMC176 CMOS FMC_TO_CPLD 0 SPI Clock FMC_TO_CPLD lt 3 0 gt CONTROL Bidir VIO FMC_TO_CPLD 1 SPI Chip Select low active FMC_TO_CPLD 2 SPI Data In Out FMC_TO_CPLD 3 SPI Alert Interrupt CLK_DIR is not connected CLK2 and CLK_DIR CONTROL Output LVTTL CLk3 are unused PG_C2M STATUS Input LVTTL Power good indicator from carrier to module PG_M2C STATUS Output LVTTL ios good indicator from module to I2C_SCL 12C Input LVTTL IC clock line I2C_SDA 12C Bidir LVTTL 12C data lin
5. DAC1_P1_DP10_N LA07_P H13 DACO_PO_DP04_P HA11_P J12 DAC1_P0_DP08_P HB11_P J30 DAC1_P1_DP10_P LAO8_N G13 DACO_PO_DPO5_N HA12_N F14 DAC1_P0_DPO7_N HB12_N F32 DAC1_P1_DP13_N LA08_P G12 DACO_PO_DPO5_P HA12_P F13 DAC1_P0_DP07_P HB12_P F31 DAC1_P1_DP13_P LA09 N D15 DACO_PO_DP06_N HA13_N E13 DAC1_P0_DP10_N HB13_N E31 DAC1_P1_DP12_N LA09_P D14 DACO_PO_DP06_P HA13_P E12 DAC1_P0_DP10_P HB13_P E30 DAC1_P1_DP12_P LA10_N c15 DACO_PO_DP09_N HA14_N J16 DAC1_P0_DP11_N HB14_N K35 LA10_P c14 DACO_PO_DP09_P HA14_P J15 DAC1_P0_DP11_P HB14_P K34 LA11_N H17 DACO_PO_DP08_N HA15_N F17 DAC1_P0_DP12_N HB15_N J34 LA11_P H16 DACO_PO_DP08_P HA15_P F16 DAC1_P0_DP12_P HB15_P J33 LA12_N G16 DACO_PO_DPO7_N HA16_N E16 DAC1_P0_DP13_N HB16_N F35 LA12_P G15 DACO_PO_DP07_P HA16_P E15 DAC1_P0_DP13_P HB16_P F34 LA13_N D18 DACO_PO_DP10_N HA17_N_CC Ki HB17_N_CC K38 LA13_P D17 DACO_PO_DP10_P HA17_P_CC K16 HB17_P_CC K37 LA14_N c19 DACO_PO_DP13_N HA18_N J19 HB18_N J37 LA14_P c18 DACO_PO_DP13_P HA18_P J18 HB18_P J36 LA15_N H20 DACO_PO_DP12_N HA19_N F20 HB19_N E34 LA15_P H19 DACO_PO_DP12_P HA19_P F19 HB19_P E33 LA16_N G19 DACO_PO_DP11_N HA20_N E19 HB20_N F38 LA16_P G18 DACO_PO_DP11_P HA20_P E18 HB20_P F37 LA17_N_CC D21 DACO_P1_DP00_N HA21_N K20 HB21_N E37 LA17_P_CC D20 DACO_P1_DP00_P HA21_P K19 HB21_P E36 UM023 FMC230 User Manual k r r1 4
6. The registers of the other devices are transparently mapped W P7 P6 P5 P4 P3 P2 P1 PO IRI A6 A5 A41 A3 A2 BWR Ge 8 bit pre selection 8 bit instruction 8 bit register data Figure 10 Write instruction to CPLD registers A1 A0 UM023 www 4dsp com 13 UM023 FMC230 User Manual i OSE r1 4 N_CS souk TY LU UU UU UU UU UU UU UU o la a ee p2 pt Po RW asias 8 bit pre selection 8 bit instruction 8 bit register data a2 SDIO P7 P6 P5 P4 P3 A4 A3 Figure 11 Read instruction to CPLD registers A1 A0 N_CS solo Pree fes es ro ee rare ol vo a e T 8 bit register data 8 bit instruction 8 bit pre selection Figure 12 Write instruction to AD9129 registers A4 A0 N_CS sok YJ YU UU UU UU UU UU UU UU UU LU LU LU LU Lr solo NEE EE TSTST 8 bit pre selection 8 bit instruction 8 bit register data Figure 13 Read instruction to AD9129 registers A4 A0 vo IUUOUUUUOUUUUUOUUUUDOUUUUOOUUUOUU le soo Pree Les Leele Fele abanlaez os o gt 8 bit pre selection 16 bit instruction 8 bit register data L SCLK Figure 14 Write instruction to AD9517 registers A12 A0 nes o o sak U ULU U U LU LU LU U U U U U U L U U ULU L LU L U U UU U U LU UUU L EN ad SIE 8 bit pre selection 16 bit instruction 8 bit register data SDIO P7 P6 P5 P4 P3 P
7. is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system 9 Ordering information UM023 www 4dsp com 16 UM023 FMC230 User Manual ef OSE r1 4 Part Number FMC230 2 1 1 1 Card Type Temperature Range Industrial 40 C to 85 C 1 Commercial 0 C to 70 C 2 Connector Type MMCxX Standard feature 1 SSMC 2 Reserved Standard Feature 1 Mil I 46058c Conformal Coating No Conformal Coating 1 Add Conformal Coating 2 10 Warranty Basic Warranty 1 Year from Date of Shipment 90 Days from Date of Shipment included Extended Warranty 2 Years from Date of Shipment 1 Year from Date of Shipment optional UM023 www 4dsp com 17 UM023 FMC230 User Manual Appendix A LPC HPC pin out a L T a r1 3 e Note that FMC700 is required to use the FMC230 on KC705 AV57 1 HPC Pin FMC230 Signal AV57 1 HPC Pin FMC230 Signal AV57 1 HPC Pin FMC230 Signal CLKO_M2C_N HS CLK TO FPGA N HAOO_N_CC FS DAC1_DCO_N HBOO_N_CC K26 DAC1_P1_DPO5_N CLKO_M2C_P H4 CLK_TO_FPGA_P HAOO_P_CC F4 DAC1_DCO_P HBOO_P_CC K25 DAC1_P1_DPO5_P CLK1_M2C_N G3 EXT_TRIGGER_N HAO1_N_CC E3 DAC1_DCI_N HBO1_N J25 DAC1_P1_DP04_N CLK1_M2C_P G2
8. 2 P1 Po RAW w1 wo Figure 15 Read instruction to AD9517 registers A12 A0 UM023 www 4dsp com 14 UM023 FMC230 User Manual i OSE r1 4 6 Environment 6 1 Temperature Operating temperature e 40 C to 85 C Industrial Storage temperature e 40 to 120 C 6 2 Monitoring The FMC holds an AD7291 device for monitoring several power supply voltages on the board as well as temperature The device can be programmed and read out through the 1 C bus Continuously operating the 1 C bus might interfere with the conversion process resulting in signal distortion It is recommended to program the minimum and maximum limits in the monitoring devices and only read from the devices when the interrupt line is asserted It is recommended that the carrier card and or host software uses the power down features in the case the temperature is too high Parameter Device 1 Formula address 010 1111 GA 00 address 010 1100 GA 01 address 010 0011 GA 10 address 010 0000 GA 11 On chip temperature External VINO 1 8Va DAC VINO 1 External VIN1 1 8Vd DAC VINT 1 External VIN2 1 8Va VIN2 1 External VIN3 1 8Vd VIN3 1 External VIN4 3V3 CLK VIN4 2 External VIN5 3V3 TCXO VIN5 2 External VIN6 VADJ VING 2 External VIN7 1V5 3 3 2 VIN7 Table 6 Temperature and voltage parameters 6 3 Cooling Two different types of cooling will be available for t
9. 30 User Manual Le r1 4 2 General description The FMC230 is a two channel DAC FMC daughter card The card provides two 14 bit up to 5 6GSPS DAC channels which can be clocked by an internal clock source optionally locked to an external reference or an externally supplied sample clock There is one trigger input for customized sampling control The FMC daughter card is mechanically and electrically compliant to FMC standard ANSI VITA 57 1 The FMC has a high pin count connector front panel I O and can be used in a conduction cooled environment The design is based on Analog Devices AD9129 single channel 14 bit 5 6GSPS DAC with DDR LVDS inputs The analog output signals are AC coupled connecting to MMCX coax connectors on the front panel The FMC allows flexible control on sampling frequency through serial communication busses Furthermore the card is equipped with power supply and temperature monitoring and offers several power down modes to switch off unused functions or protect the card from overheating Ref Clock CR Sample Clock K Clock Tree Clock Status amp Control f Clock Output WM Trigger C gt DDR LVDS e Status amp Control S DAC A DDR LVDS Status amp Control DAC s a QO Figure 1 FMC230 block diagram 3 Installation 3 1 Requirements and handling instructions e Prevent electrostatic discharges by observing ESD precautions when handling the card e Do not flex the ca
10. EXT_TRIGGER_P HAO1_P_CC E2 DAC1_DCI_P HBO1_P J24 DAC1_P1_DP04_P CLK2_BIDIR_N K5 N C HA02_N K8 DAC1_FRM_N HBO2_N F23 DAC1_P1_DP03_N CLK2_BIDIR_P K4 N C HA02_P K7 DAC1_FRM_P HBO2_P F22 DAC1_P1_DP03_P CLK3_BIDIR_N J3 N C HA03_N J7 DAC1_P0_DPOO_N HBO3_N E22 DAC1_P1_DP02_N CLK3_BIDIR_P J2 N C HA03_P J6 DAC1_P0_DP00_P HBO3_P E21 DAC1_P1_DP02_P LAOO_N_CC G7 DACO_DCO_N HAO4_N F8 DAC1_P0_DPO1_N HBO4_N F26 DAC1_P1_DP01_N LAQO_P_CC G6 DACO_DCO_P HAO4_P F7 DAC1_P0_DP01_P HBO4_P F25 DAC1_P1_DP01_P LA01_N_CC D9 DACO_DCI_N HAOS_N E7 DAC1_P0_DP02_N HBOS_N E25 DAC1_P1_DPO0_N LAO1_P_CC D8 DACO_DCI_P HAOS_P E6 DAC1_P0_DP02_P HBOS_P E24 DAC1_P1_DP00_P LAO2_N H8 DACO_FRM_N HAQ6_N K11 DAC1_P0_DP04_N HBO6_N_CC K29 DAC1_P1_DP06_N LA02_P H7 DACO_FRM_P HA06_P K10 DAC1_P0_DP04_P HBO6_P_CC K28 DAC1_P1_DP06_P LAO3_N G10 DACO_PO_DPOO_N HAO7_N J10 DAC1_P0_DP03_N HBO7_N J28 DAC1_P1_DP07_N LA03_P G9 DACO_P0_DP00_P HA07_P J9 DAC1_P0_DP03_P HBO7_P J27 DAC1_P1_DP07_P LAO4_N H11 DACO_PO_DP01_N HAO8_N F11 DACL b DPOS N HBO8_N F29 DAC1_P1_DP09_N LA04_P H10 DACO_PO_DP01_P HAO8_P F10 DAC1_P0_DP05_P HBO8_P F28 DAC1_P1_DP09_P LAOS_N D12 DACO_PO_DP02_N HA09_N E10 DACL P DPOS N HBO9_N E28 DAC1_P1_DP08_N LAOS_P D11 DACO_PO_DP02_P HA09_P E9 DAC1_P0_DP06_P HBO9_P E27 DAC1_P1_DP08_P LAO6_N C11 DACO_PO_DP03_N HA10_N K14 DAC1_P0_DPO9_N HB10_N K32 DAC1_P1_DP11_N LA06_P c10 DACO_PO_DP03_P HA10_P K13 DAC1_P0_DP09_P HB10_P K31 DAC1_P1_DP11_P LAO7_N H14 DACO_PO_DP04_N HA11_N J13 DAC1_P0_DPO8_N HB11_N J31
11. External reference Input eee eee eee 9 4 8 External Clock EE nunmmcdinendnnthnmanbawthwudienthaunbaueh EEEE 9 EE GOC EE 9 49 1 PLE ln TE 10 4 10 Power SUPPI gine een rain N ee eee ee eee eee eee eet 10 5 Controlling the FMC Q3O kis vsisascasssese ca cccstacecacensnccncsencnsecassnessceescesanessannesccecerscnteannncsneceeniass 11 541 PARCMMB CMON sccerticecledents steele ee cawicecints eaten eee ee 11 Reen e eee eee me oe ee eee eee ee eer err ry ener ree eee ere 13 GV si GIN E 15 6 1 Temperature eet 15 6 2 Monitoring sse esse eee eee 15 6 3 e sei T 15 6 3 1 Convection e e WEE 15 6 3 2 Conduction cooling sss esse eee 16 SE ys E A E 16 8 Le 16 9 period nnmnnn nnmnnn nnn 16 10 TE 17 Appendix A LPC HPC Dee ee ee ee artes eee ee 18 Appendix B CPLD Register map cssssssssseeeeeeesssssseeeeeeeessssserree resen reenn ereenn 21 UM023 www 4dsp com 3 UM023 FMC230 User Manual k r r1 4 1 Acronyms and related documents 1 1 Acronyms ADC DDR _ DoubleDataRate S DSP FMC LED LVTTL LSB Least Significant Bit s LVDS MGT MSB Most Significant Bit s PCB PCI PCle PLL PMC QDR__ Quadruple Data rate o TTL XMG Table 1 Glossary 1 2 Related Documents e FPGA Mezzanine Card FMC standard ANSI VITA 57 1 2010 e Datasheet AD9129 Rev C Analog Devices e Datasheet AD9517 Rev A Analog Devices e Datasheet AD7291 Rev B Analog Devices e FMC700 User Manual 4DSP UM023 www 4dsp com UM023 FMC2
12. UM023 FMC230 User Manual i OSE r1 4 FMC230 User Manual 4DSP USA Email support 4dsp com This document is the property of 4DSP LLC and may not be copied nor communicated to a third party without the written permission of 4DSP LLC 4DSP LLC 2014 UM023 FMC230 User Manual i OSE r1 4 Revision History 2013 02 05 Corrected pin assignments in Appendix A 1 1 2013 03 22 Updated analog output range in Table 2 and added a FMC700 requirement information for KC705 2013 08 15 Updated analog output bandwidth in Table 2 Added a signal description in Appendix A 2014 01 30 Removed the wrongful reference to analog input gain and over range in chapter 2 UM023 www 4dsp com 2 UM023 FMC230 User Manual i OSE r1 4 Table of Contents 1 Acronyms and related documents sssssssseeeeessssssseeeeeeesssssseereee essere essere eenn d Ti ACrONYM E 4 I Related een 4 2 General description cscesssssssseeeeeessssssseeeeeeessssseeree essere esen eenn nnmnnn ereenn 5 e Jett ee 5 3 1 Requirements and handling Instruccions sese eee 5 Pus s TT LOT 6 e GN Gw lee Te ue 6 4 1 1 BOArGIDIMGNSIONS isc sese 6 412 os 9 921g gt Deere ere an a a eee eer ee eee ee eee 6 4 2 Electrical specifications E 6 421 EEPROM cate otc eea ents 6 le EE 6 4 21 UM r 16 tein thot E EE ental autem 7 4 3 Main CHAT AGISM SINGS E 7 4 4 Analog output Channels sese eee eee 8 45 External trigger Tale 8 4 6 External clock el 9 4 7
13. V Ze ADP151 25mA 3 3V TCXO ass BE 8mW TX3 801 ADP2301 169 mA 12V 406mW 480mA 3 6V G __455mA 3 3v _ 409517 35mW 1 5W Eff 85 Figure 7 Power supply tree Power plane Typical Maximum VADJ 0 2A lva B 3P3V 1 0A 1 1A 12POV 0 2A 0 3A 3P3VAUX Operating 0 1 mA 3 mA 3P3VAUX Standby 0 01 pA 1 pA Table 5 Typical Maximum current drawn from FMC carrier card 5 Controlling the FMC230 5 1 Architecture The data interface of one DAC channel occupies 31 differential pairs on the FMC connector Since one DAC channel is available on the LPC connections there are only 6 signals left on the LPC connections to control the board Therefore the FMC will be controlled from a single SPI interface connecting to an onboard CPLD Xilinx Coolrunner ll XC2C64A QFG Four connections are available between the FMC connector and the CPLD The CPLD acts as a UM023 www 4dsp com 11 UM023 FMC230 User Manual i OSE r1 4 SPI distribution device and level translator and comes factory programmed The two remaining signals on the FMC connector are reserved 3 3V VADJ FMC Connector ADG3304 FMC_TO_CPLDJ 3 0 Signals to AD9517 Signals to AD9129 Figure 8 FMC control interface The FMC is controlled from the carrier hardware through a single SPI communication bus The SPI communication bus is connected to a CPLD which has the following tasks e Distribute SPI access from the carrier hardware alo
14. d for best compatibility with Xilinx development platforms CLKO is connected to a spare clock output of the clock tree CLK1 is connected to the external trigger 4 2 1 EEPROM The FMC card carries a small serial EEPROM M24C02 which is accessible from the carrier card through the ISC bus The EEPROM is powered by 3P3VAUX The standby current is only 0 01uA when SCL and SDA are kept at 3P3VAUX level These signals may also be left floating since pull up resistors are present on the FMC By default the EEPROM is write protected 4 2 1 FMC Connector UM023 www 4dsp com 6 UM023 FMC230 User Manual i OSE r1 4 FMC Top Connector The top connector is the main connector to the FMC carrier board The pin out is defined in the appendix The connector is a HPC connector FMC Bottom Connector The high pin count connector enables FMC card stacking The following connections are available between the top and bottom FMC connector e Unused gigabit data signals DP 4 9 M2C_P N DP 0 9 C2M_P N e All gigabit reference clocks GBTCLK 0 1 _M2C_P N e RESO e 3P3VAUX 3P3V 12POV VADJ e JTAG see section 4 2 1 The bottom connector is not mounted by default 4 2 1 JTAG In a stacked environment the TDI pin will be decoupled from the TDO pin by the PRST_M2C_L signal coming from the bottom connector TRST TCK TMS TDI and TDO are directly connected between top to bottom connector Bottom connector to stacked FMC
15. e Table 8 FMC230 Signal Description UM023 www 4dsp com 20 UM023 FMC230 User Manual ef OSE r1 4 Appendix B CPLD Register map Control register 0 0 for internal reference clock 1 for external reference clock disable internal reference Reserved 0 Release DAC reset 1 Assert DAC reset 0 Release CLK reset AD9517 1 Assert CLK reset AD9517 0 Release CLK sync AD9517 1 Assert CLK sync AD9517 Reserved EEPROM write enable Recommended to write 0 Control register 1 Reserved Reserved Reserved Reserved Reserved Reserved 0 for CLK power enable AD9517 1 for CLK power down AD9517 0 for MONITORING power enable AD7291 rst_l 1 for MONITORING power down AD7291 rst_l Status register REFMON AD9517 LD AD9517 STATUS AD9517 ALERT AD7291 IRQ DAC CPLD revision current b 001 Table 9 CPLD Register Map UM023 www 4dsp com 21
16. he FMC 6 3 1 Convection cooling The air flow provided by the chassis fans the FMC is enclosed in will dissipate the heat generated by the on board components A minimum airflow of 300 LFM is recommended UM023 www 4dsp com 15 UM023 FMC230 User Manual ef SEH r1 4 For standalone operations such as on a Xilinx development kit it is highly recommended to blow air across the FMC and ensure that the temperature of the devices is within the allowed range 4DSP s warranty does not cover boards on which the maximum allowed temperature has been exceeded 6 3 2 Conduction cooling In demanding environments the ambient temperature inside a chassis could be close to the operating temperature defined in this document It is very likely that in these conditions the junction temperature of power consuming devices will exceed the operating conditions recommended by the devices manufacturers mostly 85 C While a low profile heat sink coupled with sufficient air flow might be sufficient to maintain the temperature within operating boundaries some active cooling would yield better results and would certainly help with resuming operations much faster in the case the devices were disabled because of a temperature over range 7 Safety This module presents no hazard to the user 8 EMC This module is designed to operate from within an enclosed host system which is built to provide EMC shielding Operation within the EU EMC guidelines
17. ng the local devices 2x AD9129 D A converters 1x AD9517 Clock Tree e Enable disable internal reference based on a SPI command from the carrier hardware REF_EN e Generate SPI reset for AD9517 CLK N RESET and both AD9129 DAC_RST e Collect local status signals and store them in a register which can be accessed from the carrier hardware e Drive a LED according to the level of the status signals UM023 www 4dsp com 12 UM023 FMC230 User Manual i OSE r1 4 Local Side CPLD FMC Side DACO_N_CS DAC1_N_CS CLK_N_CS FMC_TO_CPLD 0 SCLK FMC_TO_CPLD 1 SCLK SDIO NCS FMC_TO_CPLD 2 S K SDIO REF_EN Ctrl DAC_RST CLK_N_RESET REFMON STATUS 4 FMC_TO_CPLD 3 ALERT AND P N INT LED Le Figure 9 CPLD architecture yY YYY Notes e SDO on the AD9517 and AD9129 devices is not connected SDIO is used bidirectional 3 wire SPI 5 2 SPI Programming The SPI programmable devices on the FMC can be accessed as described in their datasheet but each SPI communication cycle needs to be preceded with a pre selection byte The pre selection byte is used by the CPLD to forward the SPI command to the right destination The pre selection bytes are defined as follows CPLD 0x00 AD9129 1 0x82 AD9129 2 0x83 AD9517 0x84 The CLPD has three internal registers which are described in the Appendix
18. or test en monitoring purposes OUT5 connect to the gigabit transceiver reference clock on the FMC connector as a build option it can be connected to OUT7 OUT6 connects to the clock output on a MMCX connector 4 9 1 PLL design The PLL functionality of the AD9517 is used to operate from an internal sampling clock To enable flexibility in frequency selection while maintaining high performance The default loop filter is designed for a phase detector frequency of 7 68MHZ d loop bandwidth of 10KHz phase margin of 45 deg and a charge pump of 4 8mA Lower phase detector frequencies might be required to achieve the required output clock frequency phase detector frequency equals the VCO tuning step size Whether the loop filter design still works for other configurations should be investigated case by case FMC230 AD9517 1 2300MHz 2650MHz 2457 60MHz 2457 60MHz Table 3 FMC default clock configurations Note Higher DAC clock frequencies fs up to 5600MHz can be achieved using external clock LE cP e e e Ri R2 11 c1 1 00k 2 00k c3 CLK Ge Se 12 330pF c2 150pF CLK Se 9 4 70nF Bypass L k L K AD9517 X 220nF 48 REFIN K Figure 6 Loop filter design 4 10 Power supply Power is supplied to the FMC card through the FMC connector The pin current rating is 2 7A but the overall maximum is limited according to Table 4
19. rd e The FMC daughter card must be installed on a carrier card compliant to the FMC standard e The FMC carrier card must support the high pin count connector 400 pins to support all channels A low pin count connector is supported but may result in limited features e The FMC carrier card may support a VADJ VIO_B voltage of 1 2V to 3 3V e The FMC700 is required in order to use the FMC230 on KC705 UM023 www 4dsp com 5 UM023 FMC230 User Manual hE r r1 4 4 Design 4 1 Physical specifications 4 1 1 Board Dimensions The FMC card complies with the FMC standard known as ANSI VITA 57 1 The card is a single width conduction cooled mezzanine module with region 1 and front panel I O There may be a mechanical conflict with the front rib on a carrier card The stacking height is 10mm and the PCB thickness is 1 6mm 4 1 2 Front panel There are 10 MMCX connectors available from the front panel From top to bottom Analog outputs B D1 and A DO Trigger in TR Clock Input Cl Reference Input RI Clock Output CO Figure 2 Front panel layout 4 2 Electrical specifications The DAC devices use DDR LVDS signals mapped to the regular FMC pins Each channel has two 14 bit wide DDR LVDS busses Control signals operate in LVCMOS mode A VADJ range of 1 2V to 3 3V is supported The voltage on VIO_B pins will follow the voltage on VADJ The CLKx pins are required to be LVDS by the FMC standard CLK2 and CLK3 are not use
20. s one MMCX clock input on the front panel that can serve as sampling reference clock output Refer also to section 4 9 for more information about the clock tree 4 9 Clock tree The FMC offers a clock architecture that combines flexibility and high performance Components have been chosen in order to minimize jitter and phase noise to reduce degradation of the data conversion performance The user may choose to use an external sampling clock or an internal sampling clock The clock tree has a PLL and clock distribution section The PLL ensures locking of the internal VCO clock to an external supplied reference There is an onboard reference which is used in case there is no external reference present The onboard reference is a QuartzCom TX3 801 30 72MHz Filter REF EN d 30 72MHz xe CHE KE co O OUTO Lt DIvie LVPECL gt out gel ou2 no DIvie Q LVPECL PS N ouT3 gt Q ouT4 To FMC rae ee ToGBT m OD outs gt To OUT DIV gt DIV OUT7 Q SERIAL CONTROL PORT lt _ AND SC DIGITAL LOGIC Figure 5 Clock tree UM023 www 4dsp com 9 UM023 FMC230 User Manual te f a r1 4 The AD9517 has four LVPECL outputs OUT2 and OUT3 are used for clocking the DAC devices The other four clock outputs can be either programmed as LVDS or LVCMOS33 These outputs have the ability to enable a programmable delay OUT4 is connected to the FMC connector f
21. t 4DSP for custom configurations O TCI 33 7562 O isec_p eat np a t RB VAAN _ NN 7 1 nF 49A9 A7 DNP G R9 45A9 N NN N NANen 4 E 12 v T9 Figure 4 Wideband balun output option 4 5 External trigger input An external trigger is available on the front panel MMCX connector The trigger signal connects to a buffer NB6N11S before being sent to the carrier card The buffer translates the external LVTTL signal to LVDS and connects to the FMC connector The trigger input is terminated to ground with 4 7kQ UM023 www 4dsp com 8 UM023 FMC230 User Manual i OSE r1 4 4 6 External clock input There is one MMCX clock input on the front panel that can serve as sampling clock input Refer also to section 4 9 for more information about the clock tree Note when internal clock is enabled and there is no need for an external reference it is highly recommended to leave the clock input unconnected to prevent interference with the internal clock 4 7 External reference input There is one MMCX reference input on the front panel that can serve as reference clock input Refer also to section 4 9 for more information about the clock tree Note when internal clock is enabled and there is no need for an external reference it is highly recommended to leave the reference input unconnected to prevent interference with the internal clock 4 8 External clock output There i
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