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USER`S MANUAL

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4. Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 The modules are shipped from the factory with jumpers JAI JA2 and installed NOTE When the module is never required to generate interrupts JAL JA2 and JA3 should all be installed to ensure that a programming bug will not generate a VMEbus interrupt 2 4 4 BGIN BGOUT IACKIN IACKOUT Daisy Chain The Data Bus Arbitration signals BGIN BGOUT are not used by the DIO Module and are hardwired together on the module to allow the Bus Arbitration Daisy Chain to pass through the backplane slot occupied by the DIO Module In each slot of the VMEbus backplane there are set of jumpers which short the IN lines to the lines Since BGIN BGOUT signals are already hardwired on the DIO Module it is not necessary to insert the corresponding jumper on the slot occupied by the DIO Module However the IACKIN IACKOUT signals are used by the DIO Module and thus the backplane jumper for these signals must not be installed in the backplane slot occupied by the DIO Module 2 4 5 Handshake Line H2 Direction umpers The 68230 PI T chips on the DIO Module can be programmed to operate in Modes 0 and refer to the 68230 Manual for mode explanation Data transfers in these modes can be controlled via the four handshake pins on each chip These handshake pins are designed to be used in any of several different programmable protocols a thorough understanding of Modes 0 a
5. the H2 or status bits must be used to negate the interrupt refer to the 68230 Manual for the Direct Method of clearing status bits 3 7 200 290 Manual December 1987 3 3 1 3 PI T Timer Interrupt Enabling 68230 timer interrupts are enabled disabled via PORT C output pin PC4 When PC4 is negated logic T the timer cannot generate VMEbus interrupts When PC4 is asserted logic 0 the timer will generate VMEbus interrupts When the timer interrupts are to be used PORT C pins PC3 TOUT and PC7 TIACK must be programmed to serve the timer interrupt request and acknowledge functions Pin 4 is then used to determine whether timer interrupts are enabled or disabled All interrupt related PORT pins are connected to pull up resistors so that when the module is reset all PORT C lines will be configured as inputs and thus all module interrupts will be disabled During the interrupt service routine the Direct Method must be used for clearing the timer zero detect status bit in order to negate the interrupt refer to the 68230 Manual for information on the Direct Method of clearing the timer When the timer interrupts are not going to be used pin PC4 must be negated logic in order to disable timer interrupts In these cases pin PC3 TOUT be programmed either as a simple timer output or as a general purpose PORT C output line 34 PI T PORT A AND PORT B DATA LINES The lines
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7. 2 200 290 Manual December 1987 Table VMEbus Signal Identification cont d Connector Signal and Mnemonic Pin Number Signal Name and Description BRO BR3 1B 12 15 BUS REQUEST 0 3 Open collector driven signals generated by Requesters These signals indicate that a DTB master in the daisy chain requires access to the bus DS0 1A 13 DATA STROBE 0 Three state driven signal that indicates during byte and word transfers that a data transfer will occur on data buss lines 200 007 DSI 1 12 DATA STROBE 1 Three state driven signal that indicates during byte and word transfers that a data transfer will occur on data bus lines 00 015 DTACK IA 16 DATA TRANSFER ACKNOWLEDGE Open collector driven signal generated by a DTB slave The falling edge of this signal indicates that valid data is available on the data bus during a read cycle or that data has been accepted from the data bus during a write cycle D00 DI5 1A 1 8 DATA BUS bits 0 15 Three state driven bi 1 1 8 directional data lines that provide data path between the DTB master and slave GND 1A 9 11 GROUND 15 17 19 1B 2023 IC 9 2B 2 12 2231 A 3 XVME 200 290 Manual December 1987 Table VMEbus Signal Identification 4 Connector Signal and Mnemonic Pin Number IRQI 1B24 30 IRQ7 LWORD RESERV ED SERCLK SYSCLK Signal Name and Description INTERRUPT ACKNOWLEDGE Open collector or three state dr
8. 5 g peak acceleration 5 to 2000 Hz 0 030 peak to peak displacement 5 0 g peak acceleration 30 g peak acceleration 11 msec duration 50 g peak acceleration 11 msec duration XVME 200 290 Manual December 1987 VMEbus Compliance e Complies with VMEbus Standard Rev 16 08 0 DIB Slave e I 1 to I 7 STAT with programmable interrupt vector Size Single 200 Size Double XVME 290 Base address jumper selectable on boundaries within the VMEbus short I O address space 200 290 Manual December 1987 Chapter 2 INSTALLATION 2 1 INTRODUCTION This chapter explains how to configure the 200 290 DIO Module prior to installation in a VMEbus backplane Included in this chapter is information on module base address selection jumpers module interrupt level selection jumpers the handshake line H2 direction jumpers connector pinouts and a brief outline of the physical installation procedure 2 2 SYSTEM REQUIREMENTS The XVME 200 290 DIO Modules are VMEbus compatible modules To operate they must be properly installed in VMEbus backplane The minimum system requirements for the operation of XVME 200 290 DIO Modules are one of the following A host processor module properly installed on the same backplane as the 200 290 and a controller subsystem module which employs a Data Transfer Bus Arbiter a System Clock driver a System Reset dri
9. IN OUT OUT IN D800H OUT OUT IN OUT OUT OUT DCOOH OUT OUT OUT IN IN IN OUT OUT IN IN OUT 400 XVME 200 290 Manual December 1987 Table 2 2 Base Address Jumper Options Cont d Base Address of JA15 14 JAB JA12 Module 2 4 2 Address Modifier Jumper The DIO Module has one jumper that determines which Address Modifier Codes it will respond to This jumper is labeled as 2 see Figure 2 1 for the jumper location Jumper J2 determines whether the module will respond to supervisory or to non privileged short VMEbus cycles When jumper is in the module will respond to supervisory short bus cycles only When jumper J2 is out the module will respond to both non privileged and supervisory short I O bus cycles Table 2 3 shows the relationship between jumper 2 and the Address Modifiers Table 2 3 Addressing Options Address Modifier that DIO Module will respond to Supervisory Only 2DH Supervisory or 29H Non privileged 2 7 XVME 200 290 Manual December 1987 2 4 3 Interrupt Level Selection umpers The DIO Module can either be configured to generate VMEbus interrupts at levels 1 7 the module interrupt capability can be completely disabled Table 2 4 shows how jumpers JAI JA3 are used to determine the interrupt level status for the DIO Module Table 2 4 Interrupt Level Jumper Positions Interrupt Level Selected None VMEbus Interrupter disabled Level 1
10. Modules are VMEbus compatible boards There 1 one 96 pin bus connector on the rear edge of the board labeled Pl refer to Chapter 2 Figure 2 1 for the location and XVME 290 1 also uses the P2 connector The signals by connector Pl are the standard address data and control signals required for a Pl backplane interface as defined by the VMEbus specification Table 1 identifies and defines the signals carried by the Pl connector Table A 3 shows the pin outs for the P2 connector Table Pl VMEbus Signal Identification Connector and Pin Number Signal Name and Description ACFAIL IB 3 AC FAILURE Open collectors driven signal which indicates that AC input to the power supply is no longer being provided or that the required input voltage levels are not being met IACKIN 1 21 INTERRUPT ACKNOWLEDGE IN Totem pole driven signal IACKIN and IACKOUT signals form daisy chained acknowledge The IACKIN signal indicates to the VME board that an acknowledge cycle is in progress IACKOUT 1A 22 INTERRUPT ACKNOWLEDGE OUT Totem pole driven signal IACKIN IACKOUT signals form daisy chained acknowledge The IACKOUT signal indicates to the next board that an acknowledge cycle is in progress 5 1 23 ADDRESS MODIFIER bits O 5 Three state driven 1B 16 17 lines that provide additional information about the 18 19 address bus such as size cycle type and or DTB 14 master i
11. Port C Alternate function lines and their programmed direction for primary module use Notice that some of the pins retain the possibility of being used as Port C single bit inputs outputs if the module interrupt and timer capabilities not being used ie pins 1 and 3 while others must be dedicated to module control functions ie pins 0 and 1 should always be programmed as outputs to control the direction of the Port A and B data buffers and pins 4 5 6 and 7 are dedicated to timer and port interrupt control 3 5 XVME 200 290 Manual December 1987 7 6 5 4 3 1 0 PCO PIACK PIRQ TINTEN PC3 TOUT PORT PORTA Input Input output output output output output Figure 3 3 Port C Alternate Function Signal Definitions The following is a brief explanation of each PORT C bit Bits and are used to control the direction of the 8 0 data transceivers which are used to buffer the Port A and Port B data lines After start up or reset these bits should be programmed as outputs Bit 2 is used as a timer input line if the 68230 timer function is being utilized If the timer function is not being used this bit could be employed as a general purpose input line Bit 3 is used as a timer output line if the 68230 timer function is being utilized If the timer function is not being used this bit could be employed as a general purpose output line Bit 4 is used as a timer interrupt enable line of the 68230 timer function
12. bits double buffered outputs 2 C bit 0 single buffered output controls the direction of transceiver connected to Port A 3 C bit single buffered output controls the direction of the transceiver connected to Port B 4 Port bit 2 TIN function The prescaler will not be used The signal TIN will be used to decrement the counter 5 Port C bit 3 TOUT function 6 Port C bit 4 single buffered output controls the timer interrupt enable 7 Port C bit 5 PIRQ function 8 Port C bit 6 PIACK function 9 Port C bit 7 TIACK function 10 The handshake pins HLH2 H3 H4 are at a low voltage level when negated and at a high voltage level when asserted 11 is an edge sensitive input HIS is set by an asserted edge of and HI interrupt is enabled 12 H2 is an edge sensitive input and H2S is set by an asserted edge of H2 and H2 interrupt is disabled 13 and H4 set up for interlocked output handshake protocol 14 interrupt is disabled 15 Timer is set up to interrupt after timeout and started 3 12 XVME 200 290 Manual December 1987 16 Vectored interrupts are supported 17 When zero is detected the counter will generate a VMEbus interrupt reload the counter and continue counting 18 HI and timer interrupts are enabled CODE MOVEA L 2 AO base address of 1 MOVE B 0 TCR Disable timer MOVE
13. connected to the pins are labeled PAO PA7 and PBO PB7 refer Figure 1 1 of this manual The PORT and B data lines are indepen dently buffered by 8 bit transceivers The 8 I O lines assigned to each port must all assume the same direction Thus all I O lines in PORT A must assume the same direction and all the data lines PORT B must assume the same direction PORTS A and B may however assume different directions The direction of the 8 bit data transceivers which buffer each port is programmed independent of the direction of the PORT I O lines on the PI T chips The direction of the data transceivers is programmed via the PORT C outputs PCO PCL The state of the PCO and outputs should be programmed to be consistent with the programmed direction of the PI T ports When programming a port for output the direction of the transceiver and the port should be set in the following sequence Set the direction of the data transceiver 2 Set the direction of the PI T Port When programming port for input the direction of the port and transceiver should be set in the following sequence 1 the direction of the PI T Port 2 Set the direction of the data transceiver 3 8 XVME 200 290 Manual December 1987 Table 3 3 shows how pins PCO and affect the direction of the PORT and B data transceivers Remember each PI T chip has its own PORT and B and thus there is a total of 4 lines which a
14. is being utilized This bit can only be used for the timer interrupt function Bit 5 is used as interrupt request line if the 68230 interrupts are enabled This bit can only be used for the port interrupt function Bit 6 is used as a port interrupt acknowledge line if the 68230 port interrupts are enabled This bit can onlv be used for the port interrupt function Bit 7 is used as a timer interrupt acknowledge line if the 68230 timer functions are being utilized This bit can only be used for the timer interrupt function 3 6 200 290 Manual December 1987 During VMEbus reset all three PI T ports A amp C assume an input direction Pull up resistors present on bits PCO and PCI cause the port A and B data line transceivers to assume an input direction Pull up resistors also cause PORT C pins 3 4 and 5 to go high at reset thereby preventing the possibility of unintentional interrupts port or timer After reset PORT C can be configured to conform to the users needs ie Port and B transceiver direction port and timer interrupt control signals and timer I O lines and or single bit general purpose I O Figure 3 2 shows the direction for each PORT C pin as dictated by hardware config uration Some attention should be given to the possibility of generating unintentional interrupts when configuring the direction of the PORT C pins The following procedure is an example of how PORT C could be ini
15. on the XVME 290 2 DIO Module Jumper Connector Locations on the XVME 290 1 DIO Module Memory Map of the XVME 200 and XVME 290 Modules 68230 Register Model Port C Alternate Function Signal Definitions LIST OF TABLES TITLE Digital I O Module Specifications Module Specifications DIO Module Jumper List Base Address Jumper Options Addressing Options Interrupt Level Jumper Positions Handshake Line H2 Direction Jumpers Pin Assignments for Connectors JK1 and JK2 Pin Assignment for P2 XVME 290 1 Only Register Offsets From the Module Base Address Priority of Local Interrupt Sources Port A and B Data Transceiver Direction Control ii PAGE 1 4 2 2 2 3 2 4 200 290 Manual December 1987 Chapter 1 INTRODUCTION 1 1 OVERVIEW The XVME 200 and XVME 290 are Digital I O VMEbus compatible boards also referred to as DIO Modules The XVME 200 is a single high 3U single wide module and the XVME 90 is a double high 6U single wide form factored modules The DIO Module provides VME system with 32 digital TTL channels full VMEbus interrupt capability and port handshake control features The DIO Module utilizes two 68230 Parallel Interface Timer Integrated Circuit devices also referred to as PI T devices to provide and control its parallel interface functions with 16 channels per PI T device In addition the 68230 devices also provide two 240 bit software configurable timers 1 t
16. on the XVME 290 2 DIO Module 2 3 XVME 200 290 Manual December 1987 Figure 2 3 Jumper Connector Locations on the XVME 290 1 DIO Module 2 4 XVME 200 290 Manual December 1987 24 XVME 200 290 Jl and J3 J2 JAIO JAIS JA1 JA3 24 1 DIO MODULE JUMPER LIST Table 2 1 DIO Module Jumper List Determine the direction of handshake line H2 for both of the PI T chips refer to Section 2 4 5 of this manual Determines whether the module will respond to supervisory non privileged short IO VMEbus cycles refer to Section 2 42 of this manual Select module base address on any one of the 64 IK boundaries within the short I O address space refer to Section 2 4 1 of this manual Select the VMEbus interrupt level for the module refer to Section 2 4 3 of this manual Base Address Jumpers The DIO Module can be configured to be addressed at any one of the 64 IK boundaries within the VME Short Address space by using jumpers JAIO through JA15 see Figure 2 1 XVME 200 or Figure 2 2 XVME 290 for the location of the jumpers on the board as shown below 15 Table 2 2 Base Address Jumper Options Base Address of IN IN IN IN IN IN IN IN IN IN IN IN IN 14 JA13 JA12 Module IN IN IN IN IN 0000H IN IN IN IN OUT 0400H IN IN IN OUT IN 0800H IN IN IN OUT OUT OCOOH IN IN OUT IN IN 1000H IN IN OUT IN OUT 1400H IN IN OUT OUT IN 1800H IN
17. properly seated it should be secured to the chassis tightening the two machine screws at the extreme top and bottom of the board 2 15 200 290 Manual December 1987 Chapter 3 MODULE PROGRAMMING 31 INTRODUCTION This chapter will briefly examine the addressing and initialization procedures and constraints required when programming the XVME 200 and XVME 290 DIO Modules In order to demonstrate the correct sequence of initialization for the ports and registers contained in the 68230 PI T chips two programming examples with comments have been incorporated in this chapter For a complete explanation on how to program and maximize the functionality of the 68230 PI T chip refer to the accompanying 68230 Manual 32 MODULE ADDRESSING The XVME 200 and XVME 290 DIO Modules are designed to be addressed within the VMEbus defined 64K short I O address space When the DIO Module is installed in the system it will occupy a byte block of the short address space The base address decoding scheme for the XVME I O modules is such that the starting address for each board resides on IK boundary Thus there are 64 possible locations boundaries in the short I O address space which could be used as the base address for the DIO Module refer to Section 2 4 1 for the list of base addresses and their corresponding jumper configurations The logical registers ports utilized for the transfer of data on the XVME 200 and XVM
18. the 68230 PI T devices on the XVME 200 and XVME 290 Modules The following equates will be used in both examples Interrupt vectors PVCTR EQU Port interrupt vector TVCTR EQU __ Timer interrupt vector Values to preload counter CHIGH EQU 5 High byte CMID EQU 5 Middle byte CLOW EQU __ Low byte 68230 Base Address and Register Offsets BASE200 EQU XVME 200 Module base address jumper selectable 200 00 68230 PUT 1 base address 2 BASE200 40 68230 2 base address PCGR EQU 01 Port general control register PSRR EQU 03 Port service request register PADDR 05 Port A data direction register PBDDR EQU 07 Port B data direction register PCDDR 09 Port C data direction register PIVR EQU 0B Port interrupt vector register PACR EQU 00 Port A control register PBCR EQU 0 Port B control register PADR EQUSII Port A data register PBDR EQU 13 Port B data register PAAR EQU 15 Port A alternate register PBAR EQU 17 Port B alternate register PCDR EQU 19 Port C data register PSR EQU SIB Port status register TCR EQU 21 Timer control register TIVR EQU 23 Timer interrupt vector register CPRH EQU 27 Counter preload register high byte CPRM EQU 29 Counter preload register mid byte CPRL EQU 2B Counter preload register low byte CNTRH EQU F Count register high byte CNTRM EQU 31 Count
19. 00 290 Manual December 1987 Assembly Drawing 4 9 ou pr 1 o U7 200 XVME 200 290 Manual December 1987 Assembly Drawing XVME 290 B 4 8 pee 8 c 555555 19945 OIA 007 3INAX C eino 532814 12 482 59 0310891530 1 389 GND A0S 389 5490 559448 2 301943039 1 71031409 C 5 NI 389 SEOISIS3H 31382510 19 A ZX 312429 XJI 53108 6 83501 1 300338 13A31 XI 2 2 gen 814 3 sour 62 814 8 2 814 1 12 814 82 814 622814 193135 Ted tour 814 4 993 1 1 191 AN 55380609 95 513 tw ase 2814 zu 4198 198 lt 82 914 z 22 919 ww 92 914 62 14 9v 133136 92 914 Lo NOI1U93N 850 91 919 31104 21 014 1353 645 inovoui 22 vid m MO10U3N39 300230 81 514 ess 123135 68908 ETE 91 914 19545 Ci vid 950 11 519 8 912914 91 019 2916 CS tue EVid vuv 61 819 cuo 21 819 91 814 gue 329 81 814 193135 1l3S3u lt 2 AMOSI1AU3dnS 2 52 98191104 86838009
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21. 2 programmable timers 1 timer per chip Several different operating modes can be programmed for the parallel ports and timers to provide a high degree of versatility and flexibility Each 68230 chip has two 8 line I O ports labeled as Port Al and Port Bl for PI T 1 and Port A2 and Port B2 for PI T 2 The third Port on each PI T chip Port C Alternate Function is configured as a group of dedicated control lines for interrupt handling timer operation and data port direction Each of the four ports is independently buffered by its own 8 data transceiver The data transceivers are all bidirectional with their direction being independently controlled by PCO and of the Port D Alternate Function lines on each PIT The 8 data lines within each of the four PI T I O ports Al A2 BL and B2 must always be programmed for the same direction 16 because transceiver data direction is programmed individually for each port and cannot be done on a line by line In order to avoid signal direction contention between PI T Port and its data transceiver the direction of the ports and transceivers must be programmed in the proper order documented in Chapter 2 The DIO Module design allows each of the PI T ports Al Bl A2 or B2 to be individually programmed in either Port Mode 0 or Port Mode 1 refer to the 68230 Manual for a description of Port Modes In addition any of the submodes within Port Modes 0 and 1 may be utilized Th
22. Acromag S THE LEADER INDUSTRIAL XVME 200 XVME 290 32 Channel Digital I O Module USER S MANUAL ACROMAG INCORPORATED Tel 248 295 0885 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Email xembeddedsales acromag com Wixom MI 48393 7037 U S A Copyright 2012 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 965B E Xycom Revision Record Revision Description A Manual Released B Manual Updated Trademark Information Brand or product names are registered trademarks of their respective owners Windows is a registered trademark of Microsoft Corp in the United States and other countries Copyright Information This document is copyrighted by Xycom Incorporated Xycom and shall not be reproduced or copied without expressed written authorization from Xycom The information contained within this document is subject to change without notice Xycom does not guarantee the accuracy of the information and makes no commitment toward keeping it up to date xycom Technical Publications Department 750 North Maple Road Saline MI 48176 1292 aN ae ZU S co RUN XVME 200 290 Manual December 1987 TABLE OF CONTENTS CHAPTER TITLE 1 INTRODUCTION 1 1 Introduction 1 2 Manual Structure 1 3 Module Operational
23. B 8 _ Initialize Port C functions MOVE B 1 B PCDDR AO Port amp B transceivers output PC3 TOUT high 4 high timer interrupts disabled PC7652 inputs MOVE B s 4EPGCR AO Port mode 1 H34 H12 interrupts disabled Handshake pins active high MOVE B 06 PACR AO _ Initialize A Submode H2 edge sensitive input amp H2 interrupts enabled MOVE B 3 32 PBCR AO _ Initialize Port B Submode port handshake function interrupts disabled H3 interrupts enabled MOVE B 18 PSRR AO PC4 C function PCS PIRQ PIRQ function PC6 PIACK PIACK function MOVE B FEPADDR AO A output MOVE B FF PBDDR AO Port B output MOVE B PVCTR PIVR AO Set up port vector 30 PGCR A0 H34 amp 2 interrupts enabled Timer setup PC3 TOUT TOUT function PC7 TIACK TIACK function Counter reloads on zero detect PC2 TIN TIN function t Timer disabled MOVE B A6 TCR AO 3 13 XVME 200 290 Manual December 1987 MOVE B CHIGH CPRH AO Initialize counter preload registers MOVE B CMID CPRM AO MOVE B CLOW CPRL AO MOVE B IVCTR TIVR AO Initialize timer IACK vector BCLR 4 PCDR AO Set PC4 0 to enable timer interrupts BSET O TCR AO Enable timer 3 14 XVME 200 290 Manual December 1987 Appendix A VMEbus CONNECTOR PIN DESCRIPTION The XVME 200 and XVME 290
24. Description 1 4 Module Specifications 2 INSTALLATION 2 1 Introduction 2 2 System Requirements 2 3 XVME 200 290 DIO Module Jumper Connector Locations 2 4 XVME 200 290 DIO Module Jumper List 2 4 1 Base Address Jumpers 2 4 2 Address Modifier Jumper 2 4 3 Interrupt Level Selection Jumpers 2 4 4 BGIN BGOUT IACKIN IACKOUT Daisy Chain 2 4 5 Handshake Line H2 Direction Jumpers 2 5 Connector Pin Assignments 2 5 1 JK1 and JK2 Connectors 2 5 2 P1 and P2 Connectors 2 5 3 P2 Connector XVME 290 1 2 6 Module Installation 3 MODULE PROGRAMMING 3 1 Introduction 3 2 Module Addressing 3 3 Module VMEbus Interrupt Capability 3 3 1 Module VMEbus Interrupt Enabling 3 3 1 1 Port C Alternate Function Initialization 3 3 1 2 PI T Port Interrupt Enabling 3 3 1 3 PI T Timer Interrupt Enabling 3 4 PI T Port A and Port B Data Lines 3 4 1 Port A and B Reset State 3 5 Programming Examples A VMEbus CONNECTOR PIN DESCRIPTION SCHEMATICS AND DIAGRAMS QUICK REFERENCE GUIDE i PAGE BO DD 00 ANN 1 m WO N Q Ur 1 e UO 0 Q 2 2 XVME 200 290 Manual December 1987 FIGURE 1 1 1 2 2 1 2 2 2 3 LIST OF FIGURES TITLE XVME 200 and 290 2 DIO Module Operational Block Diagram XVME 290 1 DIO Module Operational Block Diagram Jumper Connector Locations on the XVME 200 DIO Module Jumper Connector Locations
25. E 290 Modules are all contained within the 68230 PI T devices register locations within the 68230 devices are given specific addresses which are offset from the module base address Table 3 1 lists the offsets specified for the registers used in the 68230 chips 3 1 XVME 2001290 Manual December 1987 Table 3 l Register Offsets From the Module Base Address 68230 PI T Register Offsets from Module Base Address PVT Register Name Port General Control Register 3 Port Service Request Register 3 Port Data Direction Register 7 Pot Data Direction Register 9 Port C Data Direction Register 11 Port Interrupt Vector 13 Port A Control Register 15 Port B Control Register 17 Port A Data Register 19 Port Data Register 2 Port A Alternate Register 23 Port B Alternate Register 25 Port C Data Register 27 Port Status Register 29 Null 31 Null 33 Timer Control Register 35 Timer Interrupt Vector 37 Null 39 Counter Preload High 4 Counter Preload Middle 43 Counter Preload Low 45 Null 47 Count Register High 49 Count Register Middle 51 Count Register Low 53 Timer Status Register 55 Null Null Registers Always 57 Null Read Zero Writing 59 Null To A Null Register 61 Null Has No Effect On 63 Null The Module XVME 200 290 Manual December 1987 A specific register address in one of the 68230 chips can be accessed by simply adding the specific register offset to the module base address For example the offset s
26. I Jumper J3 H2 handshake lines In In Input Out Out Output CAUTION The module is factory shipped with and 73 installed Therefore it will be necessary to remove the jumpers if the PI T H2 lines are to be programmed as outputs Failure to do so will result in signal contention 2 5 CONNECTOR PIN ASSIGNMENTS 2 5 1 and JK2 Connectors The port data lines port handshake lines and timer I O lines are all available to the user at two 50 connectors located on the module front panel refer to Figure 2 1 XVME 200 or Figure 2 2 XVME 290 The connectors are labeled 7 and JK2 The two connectors have identical pinouts and differ only as to which PI T device they interface with Connector carries the signals pertaining to PI T 1 and Connector JK2 carries the signals pertaining to PI T 2 2 9 200 290 Manual December 1987 The XVME 290 Module I O interconnect is done via P2 of the VMEbus backplane 290 through two 50 pin connectors and JK2 mounted in the P2 area 290 2 On the XVME 290 P2 carries all the signals for both PI T 1 and PUT 2 while for the XVME 290 2 carries signals for PIT 1 and JK2 carries signals for PI T 2 NOTE Connectors and JK2 are directly compatible with OPTO 22 24 point subsystems flat cables can be con nected directly from the XVME 200 and XVME 290 2 to the OPTO 22 system without the need for a transition inte
27. IN OUT OUT OUT 1C00H IN OUT IN IN IN 2000H IN OUT IN IN OUT 2400H IN OUT IN OUT IN 2800H IN OUT IN OUT OUT 2 00 OUT OUT IN IN 3000H XVME 200 290 Manual December 1987 Table 2 2 Base Address Jumper Options Cont d Base Address of 15 14 JA13 JA12 JAII JAIO Module IN IN OUT OUT IN OUT 3400H IN IN OUT OUT OUT IN 3800H IN IN OUT OUT OUT OUT 8 00 IN OUT IN IN IN IN 4000H IN OUT IN IN IN OUT 4400H IN OUT IN IN OUT IN 4800H IN OUT IN IN OUT OUT 4 00 IN OUT IN OUT IN IN 5000H IN OUT IN OUT IN OUT 5400H IN OUT IN OUT OUT IN 5800H IN OUT IN OUT OUT OUT 5 IN OUT OUT IN IN IN 6000H IN OUT OUT IN IN OUT 6400H IN OUT OUT IN OUT IN 6800H IN OUT OUT IN OUT OUT 6 00 IN OUT OUT OUT IN IN 7000H IN OUT OUT OUT IN OUT 7400 IN OUT OUT OUT OUT IN 7800H IN OUT OUT OUT OUT OUT 7COOH OUT IN IN IN IN IN 8000H OUT IN IN IN IN OUT 8400H OUT IN IN IN OUT IN 8800H OUT IN IN IN OUT OUT 8 00 IN IN OUT IN IN 9000H OUT IN IN OUT IN OUT 9400H OUT IN IN OUT OUT IN 9800H OUT IN IN OUT OUT OUT 9C00H OUT IN OUT IN IN IN A000H OUT IN OUT IN IN OUT A400H OUT IN OUT IN OUT IN A800H OUT IN OUT IN OUT OUT ACOOH OUT IN OUT OUT IN IN BOOOH OUT IN OUT OUT IN OUT B400H OUT IN OUT OUT OUT IN B800H OUT IN OUT OUT OUT OUT BCOOH OUT OUT IN IN IN IN 000 OUT IN IN IN OUT C400H OUT OUT IN IN OUT IN C800H OUT OUT IN IN OUT OUT CCOOH OUT OUT IN OUT IN IN DOOOH OUT OUT IN OUT IN OUT D400H OUT OUT
28. N s D z 91 6515756 ETN Tor D z 2 NI 2 NI i 2 c8d SES Poor ve 9n Cer zw 34 2 8d lt gt H 2 81N C 2 98d ZED 2 98d lt gt 2 984 ot ELESIbe TTN 2 5899 lt gt 2 58d 2 bad 02 se 2 bad lt gt 91N Cez 2x 34 2 8d Gees 2 8d lt gt 2 28d lt gt Poe ETES 2 18d AN lt gt Cre ener 2 08d sssw en Ces lt E 2 cUd Csg CO 2 Ud 2 2 9 4 554 2 94 Gar lt gt 2 904 2 2 Std ga ued 2 4 lt gt 2 2 bud Ceu 2 9 Cez 4 5 4 2 99 Cr lt gt 2 Ud 194 194 A lt gt 199 2 00d D lt gt 6 066 1 066 1861 Ienuew 062 007 AWAX
29. OW B ROW C Cm ses m rae H4 OUT 1 TMR OUT 1 H2 IN I 1 1 TMR PB6 1 PB5 1 PB3 1 PB2 PBO PA791 PAS 1 PA4 1 PA2 PAI 1 GND H4 OUT 2 TMR OUT 2 H2 IN 2 IN 2 TMR IN 2 PB6 2 PB5 2 PB3 2 PB2 2 2 7 2 5 2 4 2 PA2 2 PAL2 GND o z Z Z B Z Z z z z Z z Z Ooomoooooco 2 2 z gt z 7 XVME 200 290 Manual December 1987 Appendix B BLOCK DIAGRAM ASSEMBLY DRAWING amp SCHEMATICS Block Diagram XVME 200 and XVME 290 2 Port B2 Port vo Le Lines Data Lines Data Lines Handshake Lines PORT Sea 28 B2 X CEIVER X CEIVER X CEIVER BUFFER Bi PA0 PA7 PCO 7 TMR MRIN PI T 2 PIRQ PIACK Port Port A1 Port Timer Port A2 Handshake Lines Data Lines Data Lines Lines CONNECTOR JK2 CONNECTOR JK1 dd PAO PA7 PCO PCI PVT 1 LOGIC VME INTERFACE VMEbus B 1 XVME 200 290 Manual December 1987 Block Diagram XVME 290 1 Port Port Al Port Timer Timer Port A2 Port B2 Port Handshake Lines Data Lines Data Lines Lines VO Lines Data Lines Data Lines Handshake Lines JK2 II rr II TIMER P ESI SIGNAL BUFFER PBO PB7 TMR IN He H3 H2 PVT 1 TMR OUT 0 7 TMR IN TMR OUT VME INTERFACE VMEbus B 2 XVME 2
30. dentification AS 1A 18 ADDRESS STROBE Three state driven signal that indicates a valid address is on the address bus XVME 200 290 Manual December 1987 Signal Mnemonic 01 23 24 BBSY BCLR BERR BGOIN BG3IN BG0OUT BG30UT Table Connector and Pin Number 1A 24 30 1C 15 30 2B 4 11 1 1 182 1B 4 6 8 10 1B 5 7 VMEbus Signal Identification cont d Signal Name and Description ADDRESS BUS bits 1 23 Three state driven address lines that specify a memory address ADDRESS BUS bits 24 31 Three state driven bus expansion address lines BUS BUSY Open collector driven signal generated by the current DTB master to indicate that it is using the bus BUS CLEAR Totem pole driven signal generated by the bus arbitrator to request release by the DTB master if a higher level is requesting the bus BUS ERROR Open collector driven signal generated by a slave It indicates that an unrecoverable error has occurred and the bus cycle must be aborted BUS GRANT 0 3 IN Totem pole driven signals generated by the Arbiter or Requesters Bus Grant In and Out signals form daisy chained bus grant The Bus Grant In signal indicates to this board that it may become the next bus master BUS GRANT 0 3 OUT Totem pole driven signals generated by Requesters These signals indicate that a DTB master in the daisy chain requires access to the bus A
31. ed during the VMEbus IACK cycle Table 3 2 shows the priority of the four local interrupt sources Table 3 2 Priority of Local Interrupt Sources PIT 1 Port Interrupt Highest Priority 2 Port Interrupt PI T 1 Timer Interrupt 2 Timer Interrupt Lowest Priority When the module responds to a VMEbus IACK cycle the IACK vector is acquired from the corresponding PI T vector register refer to the 68230 Manual for location and operation and driven onto the VMEbus Each device produces 5 different vectors 4 from the ports and 1 from the timer Thus ten different VMEbus IACK vectors can be provided by the XVME 200 and XVME 290 Modules The appropriate PI T IACK vector registers must be initialized before interrupts are enabled refer to 68230 Manual 33 1 Module VMEbus Interrupt Enabling As mentioned in the previous section the ports and timer of both PI T devices have the capability of generating VMEbus interrupts The following subsections explain the general procedure for enabling the port and timer interrupts 33 1 1 Port C Alternate Function Initialization Basically the interrupt initialization procedures begin by programming the Port C Alternate function lines on the PI T devices to carry the interrupt control functions The operation of the Port C Alternate function lines is covered in depth in the 68230 Manual however for the sake of clarity Figure 3 3 is included in this manual Figure 3 3 defines the
32. er only in whether their signals interface to or JK2 XVME 200 XVME 290 2 or which P2 pins the signals connect to 290 and the jumper number which controls the direction of H2 which must be distinct 1 5 XVME 200 290 Manual December 1987 14 MODULE SPECIFICATIONS The following is a list of the operational and environmental specifications for the XVME 200 290 DIO Module 1 6 200 290 Manual December 1987 Table l l Digital VO Module Specifications Characteristic Specification Number of Channels 32 Parallel Interface Device 68230 2 per module Input Characteristics Vil 08V max 750 uA 2 0v min lil 325 uA max Output Characteristics Vol 04 Iol 12 mA Power Requirements Board Dimensions Temperature Operating Non Operating Humidity Altitude Operating Non Operating Vibration Operating Non Operating Shock Operating Non Operating Vol 05V Iol 24 mA Voh 24V min Ioh 3 mA Voh 2 0v min loh 15 mA 1 3 A typ 1 5 A max Single height size 150 x 116 7 mm XVME 200 Double height size 160 x 233 4 mm XVME 290 0 to 2 329 to 149 40 to 85 40 to 158 F 5 to 95 RH non condensing Extremely low humidity may require protection against static discharge Sea level to 10 000 ft 3048m Sea level to 50 000 ft 15240m 5 to 2000 Hz 0 015 peak to peak displacement 2
33. ere are 4 buffered handshake lines for each PI T chip which depending on the operation mode selected and the position of jumpers Jl and J3 can be used to provide interlocked handshake pulsed handshake interrupt input independent of data transfer or general purpose single line Each PI T chip also contains its own 24 bit timer capable of signaling event occurrence by generating a periodic interrupt an interrupt after timeout or a square wave output The timer interrupt capability is enabled by using three of the Port C Alternate Function pins programmed to carry the Timer Interrupt functions ie Timer Interrupt enable Timer input and Timer output The module address decode logic allows the user to select via 6 jumpers any one of 64 of the boundaries in the Short I O Address Space to be used as the module base address The PI T Internal Registers are accessible at specific addresses offset from the selected module base address Any of the 7 VMEbus interrupt levels may be selected via 3 jumpers to facilitate interrupt generation and handling from any one of 4 interrupt sources on the module ie P T port interrupts PI T 2 port interrupts 1 timer interrupts and PI T 2 timer interrupts Each of the two chips is capable of producing 5 different IACK vectors one for the timer and four for the ports for a total of ten different IACK vectors per module On the XVME 200 290 the configuration of the PI Ts diff
34. imer per PI T device which can be used to generate periodic interrupts a single interrupt after a specified time period or a square wave The specific features of the DIO Module are listed below Direct compatibility with 22 24 point subsystems of either single or quad density with no transition interface required XVME 290 2 25 Fully buffered TTL outputs and hysteresis on TTL Inputs Software configurable port direction ie ports may be configured to either input or output TTL level data Complete VMEbus interrupt capability 140 interrupts STAT Programmable IACK vector with vector alteration based on the source of the interrupt Port handshake signals are available to coordinate port data transfers TWO software configurable timers The XVME 200 provides 32 digital I O channels plus port handshake and timer control signals through the VMEbus P2 connector The XVME 290 2 places all signals on OPTO 22 compatible connectors JKI and JK2 located in the P2 area 1 1 XVME 200 290 Manual December 1987 12 MANUAL STRUCTURE This manual consists of three chapters which divide the various aspects of module specification and operation into three distinct areas The three chapters develop these aspects in the following progression Chapter One A general description of the XVME 200 290 Digital I O Module including complete functional and environmental specifications VMEbus com plia
35. iven signal from any master processing an interrupt request It is routed via the backplane to slot 1 where it is looped back to become slot 1 IACKIN in order to start the interrupt acknowledge daisy chain INTERRUPT REQUEST 1 7 Open collector driven signals generated by an interrupter which carry prioritized interrupt requests Level seven is the highest priority LONGWORD Three state driven signal indicates that the current transfer is a 32 bit transfer RESERVED Signal line reserved for future VMEbus enhancements This line must not be used A reserved signal which will be used as the clock for a serial communication bus protocol which is still being finalized A reserved signal which will be used transmission line for serial communication bus messages SYSTEM CLOCK A constant 16 MHz clock signal that is independent of processor speed or timing It is used for general system timing use 4 XVME 200 290 Manual December 1987 Signal Mnemonic SYSFAIL SYSRESET WRITE STDBY 45v 12v 12 Table Connector and Pin Number 1C 10 1C 12 1A 14 1 31 1 32 18 32 1 32 2 1 13 32 1 31 1 31 VMEbus Signal Identification con d Signal Name and Description SYSTEM FAIL driven signal that indicates that a failure has occurred in the system It may be generated by any module on the VMEbus SYSTEM RESET Ope
36. n P2 carries all the signals for both PI T I and PI T 2 while the XVME 290 2 version carries the signals for 1 and JK2 carries the signals for PI T 2 CAUTION Never attempt to install or remove any boards before turning off the power to the bus and all related external power supplies Prior to installing a module you should determine and verify all relevant jumper configurations and all connections to external devices or power supplies Please check the jumper configuration against the diagrams and lists in this manual To install a board in the cardcage perform the following steps 1 Make certain that the particular cardcage slot which you are going to use is clear and accessable 2 Center the board on the plastic guides in the slot so that the handle on the front panel is towards the bottom of the cardcage 3 Push the card slowly toward the rear of the chassis until the connectors engage the card should slide freely in the plastic guides 4 Apply straight forward pressure to the handle located on the front panel of the module until the connector is fully engaged and properly seated NOTE It should not be necessary to use excessive pressure or force to engage the connectors If the board does not properly connect with the backplane remove the module and inspect all connectors and guide slots for possible damage obstructions 2 4 XVME 200 290 Manual December 1987 5 Once the board is
37. n collector driven signal which when low will cause the system to be reset WRITE Three state driven signal that specifies the data transfer cycle in progress to be either read or written A high level indicates a read operation a low level indicates a write operation 5 VDC STANDBY This line supplies 5 VDC to devices requiring battery backup 5 VDC POWER Used by system logic circuits 12 VDC POWER Used by system logic circuits 12 VDC POWER Used by system logic circuits 5 200 290 Manual December 1987 BACKPLANE CONNECTOR PI The following table lists the Pl pin assignments by pin number order The connector consists of three rows of pins labeled rows A B and C Table A 2 Pl Pin Assignments Row A Row B Row C Signal Signal Signal Mnemonic Mnemonic Mnemonic BBSY DOS BCLR DO9 DO2 ACFAIL DIO DO3 BGOIN DII DO4 BGOOUT D12 005 BGIIN D13 DO6 BGIOUT D14 007 BG2IN 015 GND BG20UT GND SYSCLK BG3IN SYSFAIL GND BG3OUT BERR DSI BRO SYSRESET DSO LWORD WRITE AM5 GND A23 DTACK A22 GND 21 AS A20 GND A19 IACK A18 IACKIN SERCLK 1 A17 IACKOUT SERDAT 1 16 4 GND 15 A07 IRQ7 A14 A06 IRQ6 A13 A05 IRQ5 12 04 IRQ4 All A03 IRQ3 A10 A02 IRQ2 09 AOI IRQI A08 12v 5 STDBY 12 5 5 5 A N 6 XVME 200 290 Manual December 1987 Table A 3 Pin Assignment for P2 XVME 290 Only ROW A R
38. nal block diagram of the XVME 200 and the XVME 290 2 DIO Modules Figure 1 2 shows an operational block diagram of the XVME 290 1 The 290 2 is identical to the XVME 200 DIO operational block diagram however the JK1 and JK2 connectors are located on the back of the module near the VMEbus P2 connector instead of on the module front panel Por Al Port Timer Timer Port A2 Port B2 Port Handshake Lines Data Lines Data Lines Lines VO Lines Data Lines Data Lines Handshake Lines CONNECTOR JK2 Al PORT E PORT A2 PORT B2 Handshake X CEIVER X CEIVER X CEIVER E CONECTORX r PA0 PA7 PCO PB0 PB7 PCO INTERFACE Figure 1 1 XVME 200 and 290 2 DIO Module Operational Block Diagram 1 3 XVME 200 290 Manual December 1987 Port Port Al Port Timer Timer Port A2 Port B2 Port Handshake Lines Data Lines Data Lines Lines VO Lines Data Lines Data Lines Handshake vii EN Al EN PAO PA7 PCO PBO PB7 PCO PCi PBO PB7 1 2 PIRQ PIACK VMEbus Figure 1 2 XVME 290 1 DIO Module Operational Block Diagram 1 4 XVME 200 200 Manual December 1987 The DIO Module uses two 68230 Parallel Interface Timer devices to provide a total of 32 parallel IO lines 16 lines per chip arranged as four ports two 8 line ports per chip as well as
39. nce information and a block diagram Chapter Two DIO Module installation information covering module specific system requirements jumpers and connector pinouts Chapter Three Details covering functional addressing interrupt enabling and programming considerations requirements The Appendices are designed to provide additional information in terms of the backplane signal pin descriptions a block diagram and assembly drawing and module schematics NOTE In order to fully document the complex vers of XVME 200 290 and the 68230 PI T device a manual kit is being shipped with the 200 290 DIO Module the manual kit is referenced as XYCOM Part 74200 001 This kit consists of two parts a Motorola MC68230 Manual c referenced as XYCOM Part 74200 003 and 200 290 Manual referenced as Part 74200 002 It recommended that the user read completely the 68230 Manual prior to reading further in the 200 290 Manual After becoming familiar with the 68230 and how it is programmed the user should then read the remainder of the XVME 200 200 Manual to become acquainted with module base addressing register access offsets interrupt control handshake control and operational mode programming constraints MC68230 Parallel Interface Timer Manual c Motorola Inc 1983 XVME 200 290 Manual December 1987 13 MODULE OPERATIONAL DESCRIPTION Figure 1 1 shows the operatio
40. nd 1 and their associated submodes presented in the 68230 Manual is necessary in order to fully understand the variety of protocols 2 8 XVME 200 290 Manual December 1987 In these modes the direction of two of the handshake pins H2 and H4 should be programmable However due to constraints in hardware design pin must always be programmed as an output Thus pin H2 may be programmed as either an input or an output depending on what type of handshake protocol is to be used Jumpers and J3 refer to Figure 2 1 XVME 200 or Figure 2 2 XVME 290 for the location of these jumpers are used in conjunction with the programmed direction of pin H2 to determine whether the buffered handshake line H2 will be used as an input or an output Jumper Jl is used to control the direction of PIT 1 H2 line and Jumper J3 is used to control the direction of the PI T 2 H2 line NOTE In order to prevent the possibility of signal contention when using handshake protocol pin H4 of a 68230 chip must always be programmed as an output with the H4 interrupt disabled and the programmed direction of pin H2 must consistent with position of the corresponding jumper 31 or 13 Table 2 5 shows the relationship between the position of jumpers Jl and J3 and the direction of the buffered handshake line H2 for each of the PI T chips Table 2 5 Handshake Line H2 Direction Jumpers PIT 1 PIT 2 Direction of the corresponding Jumper J
41. onnector is designed to mechanically interface with VMEbus defined Pl backplane 2 5 3 P2 Connector XVME 290 1 The P2 connector is a standard VMEbus P2 backplane connector with 96 pins 3 rows The pin outs for the connector P2 are found in Appendix A of this manual The P2 connector is designed to interface with a VMEbus defined P2 backplane The P2 connector has been modified slightly for the 290 see Table 2 7 2 12 XVME 200 290 Manual December 1987 Table 2 7 Pin Assignment for P2 XVME 290 Only c P2A 1 P2A 2 P2A 3 P2A 4 P2A 5 P2A 6 P2A 7 P2A 8 P2A 9 P2A IO P2A I 1 P2A 12 P2A 13 P2A 14 P2A I 5 P2A 16 P2A 17 P2A 18 P2A 19 P2A 20 2 2 1 2 22 2 23 2 24 2 25 2 26 2 27 2 28 2 29 2 30 P2A 3 1 P2A 32 a 4 m 00 dd Z z Z Z Z z ZZ 2 tri tri 4 4 z Z Z Z Z Z 2 2 NN vw 2 13 XVME 200 290 Manual December 1987 2 6 MODULE INSTALLATION XYCOM modules are designed to comply with all physical and electrical VMEbus backplane specifications The XVME 200 DIO Module is a single high single wide VMEbus module and as such only requires the Pl backplane The XVME 290 DIO Module uses the P2 of the VMEbus backplane or through the two 50 pin connectors and JK2 mounted in the P2 area XVME 290 2 In the XVME 290 versio
42. pecified for the Port General Control Register for PI T 42 is 41H and if the module base address is jumpered to 1000H the register can be accessed at 1041H Module Base Address Register Offset PCG Register 2 1000H 41H 1041 The XVME 200 290 are an odd byte only slave and as such the module will not respond to even address single byte accesses However word accesses may be used with the understanding that only the odd byte of the word is used to exchange data If word accesses are used the register offsets listed in Table 3 1 would all be decremented by 1 Figure 3 1 shows a simple map of the IK block of the short I O address space which is occupied by the XVME 200 290 Modules EVEN ODD Base 1 5 40H E 41H D PI T 12 80H 81H Unused 3FEH 3FFH Figure 3 1 Memory Map of the XVME 200 and XVME 290 Modules 3 3 XVME 200 290 Manual December 1987 Figure 3 2 is a model of the registers internal to each 68230 PI T chip Notice that the register model includes a register value after reset for each register as well as register select bits for each register see the NOTE immediately following Figure 3 2 H 7 6 5 4 3 2 1 9 smse smse erame sees 2211 Pnonty Control e e e 6 20001 Number Vector 9egister Pon A A Con
43. re used to control the direction of the four data transceivers refer to the Module Block Diagram Figure 1 1 Table 3 3 PORT A and B Data Transceiver Direction Control PCO output output Data Line Transceiver Direction 7 are OUTPUTS 7 are INPUTS PBO PB7 are OUTPUTS PBO PB7 are INPUTS These directions are the same for both PI T chips CAUTION PIT pins PAO PA7 must all be programmed to assume the same direction this direction must be consistent with PCO as shown in Table 3 3 PI T pins PBO PB7 must all be programmed to assume the same direction this direction must be consistent with 1 as shown in Table 3 3 Failure to observe these conventions will cause signal contention 341 Port A and B Reset State During a VMEbus reset PI T PORTS A B and C all assume an input direction Therefore I O signals PAO PA7 and PBO PB7 all assume an input direction during a reset This means that if the signals are being used in an application as outputs they will have a high reset state Thus active low outputs would have to be used on lines which must be negated on power up or system reset The receivers of these active low outputs should limit their Ig value below 250uA to guarantee that they will be negated upon reset XVME 200 290 Manual December 1987 35 PROGRAMMKNG EXAMPLES The two 68000 CPU code programming examples which follow demonstrate general methods of initialization of
44. register mid byte CNTRL EQUS33 Count register low byte TSR EQU 35 Timer status register ye os 3 10 XVME 200 290 Manual December 1987 Example 7H Basic Set Up PIT 41 Mode 0 Unidirectional 8 bit Mode Submode IO Pin Definable Single Buffered Output or Non Latched Input Goals 1 Port A all bits non latched inputs 2 B all bits single buffered outputs 3 C bit 0 single buffered output controls the direction of the transceiver connected to Port A 4 Port C bit single buffered output controls the direction of the transceiver connected to Port B 5 Port C bit 2 non latched input 6 Port C bit 3 single buffered output high 7 Port C bit 4 single buffered output programmed high to disable timer interrupts 8 C bit 5 PIRQ function 2 Port C bit 6 PIACK function 10 Port C bit 7 non atched input will always read as one 11 The handshake pins HLH2 H3 H4 are at a low voltage level when negated and at a high voltage level when asserted 12 is an edge sensitive status input HIS is set by an asserted edge of 13 H2 is a negated output pin and 2 is always cleared 14 H3 is an edge sensitive status input H3S is set by an asserted edge of 15 is an asserted output pin and H4S is always cleared 16 in
45. rface Table 2 6 shows the pin assignments for Connectors and JK2 the signal direction with respect to the XVME 200 and the XVME 290 2 Modules and the corresponding 22 channel number 2 10 XVME 200 290 Manual December 1987 Table 2 6 Pin Assignments for Connectors JK1 and JK2 JK1 Signal 2 Signal OPTO 22 Channel Signal Direction Not Connected GND H4 OUT 2 OUTPUT GND H2 OUT 2 OUTPUT GND OUT 1 TMR OUT 2 OUTPUT GND GND H2 IN 1 H2 IN 2 INPUT GND H2 IN 1 INPUT GND IN 1 IN 2 INPUT GND GND TMR IN 1 TMR IN 2 INPUT GND GND PB7 1 PB7 2 GND GND PB6 1 PB6 2 GND GND PB5 1 PB5 2 GND GND PB4 1 PB4 2 INPUT or OUTPUT GND GND as a group PB3 1 PB3 2 GND GND PB2 1 PB2 2 GND GND 1 1 1 2 GND GND PBO 1 PBO 2 GND GND PA7 1 PB7 2 GND GND PA6 1 PB6 2 GND GND PA5 1 PB5 2 GND GND PA4 1 PB4 2 INPUT or OUTPUT GND GND as a group PA3 1 PB3 2 GND GND PA2 1 PB2 2 GND GND 1 1 1 2 GND GND 1 PBO 2 GND Not Connected GND NO COON 200 290 Manual December 1987 2 5 2 Pl and P2 Connectors Connectors PI and P2 are mounted at the rear edge of the board see Figure 2 1 The pin connections for 96 pin 3 row connector contains the standard address data and control signals necessary for the operation of VMEbus defined modules The signal definitions and pin outs for the connector are found in Appendix A of this manual The Pl c
46. terrupts are disabled 17 The timer is disabled CODE MOVEA L 4 PI TIBASE AO AO base address of PI T 1 MOVE B 4 FF PCDR AO Initialize Port C control MOVE B 851 B PCDDR AO functions Port A amp B transceivers output PC3 TOUT high PC4 high timer interrupts disabled 7652 inputs MOVE B Port mode 0 H34 H12 interrupts disabled Handshake pins active high MOVE B Initialize Submode 1X H2 negated output HI amp H2 interrupts disabled 3 1 200 290 Manual December 1987 MOVE B 5 Initialize Port B Submode 1X H4 asserted output amp H4 interrupts disabled MOVE B 4 18 PSRR AO 4 Port C function PCS PIRQ PIRQ function PC6 PIACK PIACK function Set Port A amp B direction MOVE B O PADDR AO Port A input mode MOVE B 4 FF PBDDR AO Port B output mode BCLR 0 PCDR AO Port A transceiver input mode MOVE B 0 TCR AO PC2 PC3 amp PC7 Port C function timer disabled After this initialization code is executed PI T 1 Port A data register will reflect the state of PA7 1 through Data written to PIT Port will appear on PB7 1 through Example 2 Basic Set Up 2 Mode Unidirectional 16 bit Mode Submode Pin Definable Double Buffered Output or Non Latched Input Goals Port A and B all
47. tialized to appear as it does in Figure 3 2 Write FFH to the PORT C Data register This ensures that all PORT C pins will be high when the direction of the pins is switched thereby preventing the possibility of unintentional interrupts both port and timer being generated 2 Write IBH to the PORT C Direction register This will configure the direction of PORT as shown in Figure 3 2 with the exception of pin 5 PIRQ which remains an input to ensure that port interrupts will not be generated unintentionally 3 Individual PORT C bits can now be programmed to conform to the user s needs At this point port interrupts could be enabled by merely programming the PC6 PIACK and PCS PIRQ pins to support the interrupt and acknowledge functions 3 3 1 2 PI T Port Interrupt Enabling In order to enable the PI T port interrupt capability PORT C must be programmed so that pins PCS PIRQ and PC6 PIACK serve the port interrupt request and acknowledge functions As such the individual internal enable bits for Hl H2 and H3 determine whether a particular port function will generate a VMEbus interrupt NOTE Handshake line H4 must be programmed as an output and H4 interrupts must always be disabled When H2 interrupts are to be used input pin H2 must be physically jumpered to configure the line for inputs refer to Section 2 4 5 of this manual for H2 jumper definitions During the interrupt service routine the Direct Method of clearing
48. trol Enable Port 8 Port Control H4 Control EJ Register 4 0 1 Data Register Port 8 Data Register Null Unused zero Value betore RESET Current value on pins e Undetermined value Figure 3 2 68230 Register Model NOTE The register select bits values shown in Figure 3 2 are intended for the 68230 chip in a stand alone perspective and are not representative of the addressing logic included on the XVME 200 and XVME 290 DIO Modules All reg isters are accessed on the XVME 200 and 290 Modules by using the offsets shown in Table 3 1 added to the module base address refer to the example on page 3 3 3 4 Timer Control Register Timer Interrup Vector Register Null Counter Preioac Register High Counter Preiosc Register Mid Counter Preloac Register Low Null Count Register High Count Register Count Register Low Timer Status Register Nutty Null Null INCID Null XVME 200 290 Manual December 1987 33 MODULE VMEbus INTERRUPT CAPABILITY Four sources of interrupts exist on the XVME 200 and XVME 290 These the timer and port interrupt sources from both PI T 1 and 2 When enabled each of the four interrupt sources can generate VMEbus interrupts on the level selected by jumpers JALJA3 refer to Section 2 4 3 of this manual The four local interrupt sources are prioritiz
49. ver and a Bus timeout module The XYCOM XVME 010 System Resource Module provides a controller subsystem with the components listed OR host processor module which incorporates an on board controller sub system such as XYCOM s XVME 600 or 601 Pnor to installing XVME 200 290 DIO Modules it will be necessary to configure several jumper options These options are 1 Module base address within the short I O address space 2 Address Modifier codes to which the DIO Module will respond 3 Interrupt level 4 Direction of handshake line H2 on the 68230 PI T chip 23 XVME 200 290 DIO MODULE JUMPER CONNECTOR LOCATIONS The jumpers and connectors relevant to the installation of the XVME 200 DIO Module are shown in Figure 2 1 and the jumpers and connectors relevant to the installation of the XVME 290 2 DIO Module are shown in Figure 2 2 and Figure 2 3 shows the 290 2 1 XVME 200 290 Manual December 1987 JK CONNECTORS COMPONENT SIDE PIN 50 2 PIN 1 FRONT VIEW IE TE TE TE CONNECTOR Figure 2 1 Jumper Connector Locations on the XVME 200 DIO Module 2 2 200 290 Manual December 1987 eo o e o 0 ooo o oo e o oo o JK2 stacked End View on top of JK1 Figure 2 2 Jumper Connector Locations

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