ESSI Programming
Contents
1. Bit No Bit Abbr Value Function 0 IFO Serial Input Flag 0 Valid only in synchronous mode with transmitter 1 disabled and SCO configured as an input see Table 1 1 Data on the SCO pin is seen here 1 IF1 Serial Input Flag 1 Valid only in synchronous mode with transmitter 1 disabled and SC1 configured as an input see Table 1 2 Data on the SC1 pin is seen here 2 TFS Transmit Frame Sync Flag Valid only if at least one transmitter is enabled Always 1 in normal mode 0 No transmit frame sync occurred during the current time slot 1 Transmit frame sync occurred during the current time slot 3 RFS Receive Frame Sync Flag Valid only if the receiver is enabled Always 1 in normal mode 0 No receive frame sync occurred during the current time slot 1 Receive frame sync occurred during the current time slot 4 TUE Transmit Underrun Error Flag 0 Otherwise 1 At least one enabled transmit shift register is empty and a transmit time slot occurred 5 ROE Receive Overrun Error Flag 0 Otherwise 1 Receive shift register is full but the receive data register is still full 6 TDE Transmit Data Register Empty 0 All enabled transmit data registers have been written to the DSP56300 core 1 Enabled transmit data registers are transferred to the transmit shift registers and data is ready for writing to the transmit data register 7 RDF Receive Data Register Full 0 Receive data register is read 1 Receive shift register is transferred t2. 2 1 2 Word Alignment Words less than 24 bits long can be aligned in two ways based on the value of CRA 18 ALC If ALC is set 8 12 and 16 bit words are left aligned to bit 15 If ALC is clear 8 12 and 16 bit words are left aligned to bit 23 Figure 2 3 shows the different options for the word alignment Motorola DSP56300 ESSI Programming 11 Transfer Characteristics Data Registers bit 23 bit 0 8 bit CRA ALC 0 Align to bit 23 12 bit 16 bit bit 15 bit 0 8 bit CRA ALC 1 Align to bit 15 12 bit 16 bit Figure 2 3 Alignment Control 2 1 3 Shift Direction The ESSI presents two options for shift direction Most Significant Bit MSB first or Least Significant Bit LSB first To select shift direction set bit 6 in Control Register B CRB 6 SHFD If SHFD is set the data is shifted into the receive shift register from the SRD pin and out of the transmit shift register to the STD pin with the LSB first If SHFD is clear the data is shifted into the receive shift register from the SRD pin and out of the transmit shift register to the STD pin with the MSB first Figure 2 4 shows how data is shifted for both shift direction options CRB SHFD 0 MSB first TX Data Register Y STD lt 4 TX Shift Register RX Data Register N RX Shift Register SRD CRB SHED 1 LSB first TX Data Register Y TX
3. te Receive Frame Sync Figure 2 5 Synchronous Versus Asynchronous In synchronous mode SCK is an input or an output that all enabled transmitters and the receiver use as the clock signal SC2 is an input or an output that all enabled transmitters and the receiver use as the frame sync signal SCO and SC1 can be used as extra transmitter signals or as flag signals In asynchronous mode SCK is an input or an output that transmitter 0 uses as the clock signal SC2 is an input or an output that all enabled transmitters use as the frame sync signal e SCO is an input or an output that the receiver uses as the clock signal e SCI is an input or an output that the receiver uses as the frame sync signal 1 Transmitters 1 and 2 and Flags O and 1 cannot be used in asynchronous mode Motorola DSP56300 ESSI Programming 13 Synchronization Signals The direction of the SCO SC1 SC2 and SCK pins is determined by the SCD0 SCD1 SCD2 and SCKD bits respectively CRB 2 5 If one of these bits is clear the corresponding pin is an input If one of these bits is set the corresponding pin is an output 2 2 2 Clock Signal When the SCK pin is an output SCKD 1 its rate is controlled by two sets of bits in CRA PSR and PM 7 0 as Figure 2 6 shows Divide Divide Divide Fcore gt by PA by PA by m gt ScK 2 lorg 1 to 256 PSR PM 7 0 1 or 0 0 to FF Figu
4. Ne Ne Ne Ne Load CRA for oad CRB for ESSIO ESSIO Load CRA for Load CRB for ESSI1 ESSI1 Set the bits in the PORC and PCRD registers that correspond to the ESSI pins to be used The following commands set all of the Port C and Port D bits to enable all the ESSIO and ESSI1 pins Motorola DSP56300 ESSI Programming 20 Transfer Methods movep 3F x M_PCRC Enable ESSIO movep 3F x M_PCRD Enable ESSI1 4 Write the first data to the transmit registers The first data word to be transmitted should be present in the transmit data registers before the transmitters are enabled even if DMA is used to transfer data to the transmit register The following commands write the first data to all the transmit data registers for both ESSIs TX datal represents any register or memory location that contains the first data to be transmitted movep TX00_datal x M_TXO00 Write first data to ESSIO TXO reg movep TX01_datal x M_TXO1 Write first data to ESSIO TX1 reg movep TX02_datal x M_TX02 Write first data to ESSIO TX2 reg movep TX10_datal x M_TX10 Write first data to ESSI1 TXO reg movep TX11_datal x M_TX11 Write first data to ESSI1 TX1 reg movep TX12_datal x M_TX12 Write first data to ESSI1 TX2 reg 5 Enable the transmitters and receiver Set the transmitter and receiver enable bits in CRBO and CRB as follows bset 14 x M_CRBO Enable ESSIO TX2 bset 1
5. RX A read only register that accepts data from the receive shift register as it becomes full Transmit Data Registers TX0 TX1 TX2 A write only register that transfers data to the transmit shift registers The ESSI data registers are double buffered for maximum throughput Data to be transmitted is written to a transmit data register When the transmit data register is full the data is automatically transferred to a transmit shift register and then shifted out to the transmit data pin If data is shifted out of the transmit shift register but new data has not been written to the transmit data register and a transmit frame sync occurs a transmit underrun error occurs A receive shift register receives incoming data from the receive data pin When the receive shift register is full the data is automatically transferred to the receive data register If data is shifted into the receive shift register but the previous data has not been read from the receive data register and a receive frame sync occurs a receive overrun error occurs Table 1 5 Control Register A CRA Bit No Bit Abbr Value Function 7 0 PM 7 0 Prescale Modulus Select 0 FF ESSI clock is divided by PM plus 1 10 8 Reserved bits to be written with 0 11 16 12 PSR Prescaler Range 0 ESSI clock is divided by eight 1 ESSI clock is divided by one DC 4 0 Frame Rate Divider Control 00000 11111 In normal mode equa
6. 3 E Bit 6 4 DAM 2 0 A Bit 3 2 DDS 1 0 E Bit 1 0 DSS 1 0 movep SOURCE 1 x M_DSR3 movep TX10 x M_DDR3 movep COUNT 1 x M_DCO3 movep DCR3 x M_DCR3 movep RX1 x M_DSR2 movep DEST x M_DDR2 movep COUNT x M_DCO2 movep DCR2 x M_DCR2 Motorola 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 No No So Ne se se 01 1 1100 01 00 1 0 01 L 1101 00 01 0 1 Load D Load D Load D Load D Load D Load D Load D MA3 Channel enabled Interrupt disabled Transfer mode 1 Channel priority 1 Continuous mode disabled Request source ESSI1 RX 3 D mode disabled Dest address post inc by 1 Source address no update Dest space Y memory Source space X memory Channel enabled Interrupt disabled Transfer mode 1 Channel priority 1 Continuous mode disabled Request source ESSI1 TX 3 D mode disabled Dest address no update Source address Dest space Source spac X memory Y memory source dest counter control A3 A3 A3 Load DMA2 source MA2 dest A2 counter A2 control DSP56300 ESSI Programming post inc by 1 References 2 7 References 1 DSP56300 Family Manual Motorola 1995 Order this document by the order number DSP56300FM AD Or download it from the Motorola Web site at http www mot com SPS DSP documentation DSP56300 html 2 DSP56303 User s Manual Motorola 1996 Order this doc
7. Shift Register gt STD RX Data Register i SRD RX Shift Register Figure 2 4 Shift Direction Motorola DSP56300 ESSI Programming 12 Synchronization Signals 2 2 Synchronization Signals Because the ESSI is a synchronous interface it requires clock and frame sync signals to define when the data changes and when a new frame begins In certain modes the ESSI also has the option of two flag signals to use for device selection This section describes all of these signals 2 2 1 Synchronous Versus Asynchronous The ESSI includes both synchronous and asynchronous modes In synchronous mode the transmitters and receiver use the same clock and frame sync in asynchronous mode the transmitters and receiver use different clocks and frame syncs The ESSI data transfers are synchronized to a clock in both modes The choice of synchronous versus asynchronous mode is determined by the SYN bit CRB 12 Setting SYN puts the ESSI is in synchronous mode clearing SYN puts it in asynchronous mode Figure 2 5 summarizes the operation of the ESSI pins in synchronous and asynchronous modes SYN 1 Synchronous mode SYN 0 Asynchronous mode SCK PS Clock SCK 32 Transmit Clock STD PB Transmit STD M Transmit SRD tt Receive SRD Receive SC2 ma Frame Sync SC2 pat Transmit Frame Sync SC1 e Flag 1 or Transmit 2 SC1 t t gt Receive Clock SCO lt q pe Flag 0 or Transmit 1 SCO 9a
8. illustrate practical programming guidelines 2 3 2 2 gt Transmit Slot Mask Registers cceseeeeeeeeees 17 2 3 2 3 Receive Slot Mask Registers ceceseseeeeeeees 17 2 3 2 4 On Demand Mode 18 2 4 Programming Control Registers uione nesine 2 4 1 Example 1 2 4 2 Example 2 2 5 Initialization 0 0 0 0 20 2 6 Transfer Methods 21 2 6 1 PONG caras 21 2 6 2 Interrupts eee eee 22 2 6 3 DMA 23 27 ReferenceS coooononncionncnonnos 25 D E E v D gt 2 oO 177 op Ww o oS a LO am ep m AA MOTOROLA Motorola Inc 1998 Part 1 ESSI Architecture All DSP56300 devices contain two independent and identical Enhanced Synchronous Serial Interfaces ESSIO and ESSI1 For simplicity this section describes a single generic interface Figure 1 1 shows the ESSI block diagram depicting the pins and registers that control ESSI operation GDB DDB RCLK RX SHIFT REG SRD TCLK TXO SHIFT REG STD TXO Sco mm TX2 SHIFT REG i i Interrupts Clock Frame Sync Generators and Control Logic SC2 SCK AA0678 TX ae SC1 Figure 1 1 ESSI Block Diagram Motorola DSP56300 ESSI Programming ESSI Pins 1 1 ESSI Pins Figure 1 2 depicts the ESSI pins Port C D GPIO Enhanced 4 gt SC0 5C2 PO P2 Synchronous Serial gt SCK P3 Interface Port ESSI t SRD P4 gt F STD P5 Figure 1 2 ESSI
9. pin has many different functions depending on the mode settings which are determined by the SYN and Motorola ESSI Architecture 3 ESSI Registers SCD2 bits in Control Register A CRA Table 1 3 shows the various functions This pin also functions as GPIO pin P2 Table 1 3 SC2 Operation SYN SCD2 Operation 1 Sync 0 Input Transmit and receive frame sync input external 1 Sync 1 Output Transmit and receive frame sync output internal 0 Async 0 Input Transmit frame sync input external 0 Async 1 Output Transmit frame sync output internal Serial Clock Pin SCK Provides the serial bit rate clock for the ESSI This pin has many different functions depending on the mode settings which are determined by the SYN and SCKD bits in Control Register A CRA Table 1 4 shows the various functions This pin also functions as GPIO pin P3 Table 1 4 SCK Operation SYN SCKD Operation 1 Sync 0 Input Transmit and receive clock input external 1 Sync 1 Output Transmit and receive clock output internal 0 Async 0 Input Transmit clock input external 0 Async 1 Output Transmit clock output internal Serial Receive Data Pin SRD Receives data and is always an input This pin also functions as GPIO pin P4 Serial Transmit Data Pin STD Transmits data from transmitter 0 and is always an output This pin also functions as GPIO pin PS 1 2 ESSI Reg
10. the body or other applications intended to support life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and 44 are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer How to reach us USA Europe Locations Not Listed Motorola Literature Distribution P O Box 5405 Denver Colorado 80217 1 800 441 2447 1 303 675 2140 Motorola Fax Back System Mfax TOUCHTONE 602 244 6609 1 800 774 1848 RMFAX0 email sps mot com AA MOTOROLA Asia Pacific Motorola Semiconductors H K Ltd 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po N T Hong Kong 852 26629298 Technical Resource Center 1 800 521 6274 DSP Helpline dsphelp dsp sps mot com Japan Nippon Motorola Ltd SPD Strategic Planning Office141 4 32 1 Nishi Gotanda Shin
11. 1 Control Register B CRB A Bit 23 REIE al RX exception int enabled F Bit 22 TEIE 1 TX exception int enabled A Bit 21 RLIE 1 RX last slot int enabled E Bit 20 LIE 1 TX last slot int enabled P Bit 19 RIE 1 RX int enabled s Bit 18 TIE 1 TX int enabled E Bit 17 RE 0 RX disabled Bit 16 EO 0 TXO disabled Bit 15 TEL 0 TX1 disabled s Bit 14 TE2 0 TX2 disabled s Bit 13 MOD Network mode Bit 12 SYN dl Synchronous mode Bit 11 CKP 0 Clk polarity on rising edge Bit 10 FSP 1 Frame sync polarity negative Bit 9 FSR 0 Frame sync with lst bit Bit 8 7 FSL 10 Bit length frame sync E Bit 6 SHFD Shift LSB first Bit 5 SCKD Internal clock source a Bit 4 SCD2 SC2 pin output Bit 3 SCD1 SC1 pin output E Bit 2 SCDO 1 SCO pin output Bit 1 0 OF 1 0 00 Output flags 2 5 Initialization Perform the following steps to initialize the ESSI properly 1 Reset the ESSI This is accomplished by a hardware or software reset or by putting the ESSI into its individual reset state by clearing the PCR bits as shown here movep 0 x M_PCRC movep S 0 x M_PCRD 2 Program the ESSI control registers r T ESSIO ESSI1 Reset Reset CRA and CRB must be programmed to control the ESSI operation The following commands program the ESSI control registers by moving equates into CRA and CRB for both ESSIs CRAO x M_CRAO CRBO x M_CRBO CRA1 xX M_CRA1 CRB1 x M_CRB1 movep movep movep movep 3 Enable the ESSI pins
12. 5 x M_CRBO Enable ESSIO TX1 bset 16 x M_CRBO Enable ESSIO TXO bset 14 x M_CRB1 Enable ESSI1 TX2 bset 15 x M_CRB1 Enable ESSI1 TX1 bset 16 x M_CRB1 Enable ESSI1 TXO bset 17 x M_CRBO Enable ESSIO RE bset 17 x M_CRB1 Enable ESSI1 RE 2 6 Transfer Methods The ESSI provides three methods for transferring data to or from the data registers polling interrupts and DMA Polling is the easiest method but it demands a large amount of the DSP56300 core s processing power The DSP56300 core cannot be involved in other processing activities while it polls the receive and transmit ready bits Interrupts on the other hand require more code but the Core can process other routines while waiting for the ESSI transfers DMA requires even less core intervention and the setup code is minimal but the DMA channels must be available The following sections describe each transfer method 2 6 1 Polling The SSISR provides bits that notify the core when data is ready to be transferred to or from the ESSI The core can poll these bits to determine when to interact with the ESSI For proper operation the DSP core must write to the transmit buffer only when it is empty and read from the receive data register when it is full SSISR 6 Transmit Data Register Empty TDE determines when to write to the transmit data registers TDE is cleared when the core writes to all enabled transmit data registers TDE is set when this d
13. MOTOROLA AN1764 D Semiconductor Application Note Rev 1 0 DSP56300 Enhanced Synchronous Contents Serial Interface ESSI Programming parti ESSI Architecture 2 1 1 ESSI Pins vi c cecceceeseceeerseesnns By Tina M Redheendran 1 2 ESSI Registers Part II ESSI Programming 11 The Enhanced Synchronous Serial Interface ESSI providesa 24 Transfer Characteristics 11 full duplex serial port for communicating with a variety of ZLI Word Length a 1 gt z gt 2 1 2 Word Alignment 11 serial devices The ESSI comprises independent transmitter 213 Shift Direction 12 and receiver sections and a common ESSI clock generator 22 Sy chroni tion Signals 13 Three transmit shift registers enable it to transmit from three 2 2 1 Synchronous Versus different pins simultaneously It interfaces to TDM networks Asynchronous coccccniconiconicons 13 without additional logic Each DSP56300 family device 2 2 2 Clock Signal 14 includes two ESSIs and thus can accommodate six total ESSI 2 2 3 Frame SYNC 14 transmitters for six channel surround sound applications 2 24 FlagS ssesssssssessesssesnnsnsee 15 2 3 Operation Modes 15 This document consists of two sections The first surveys the 2 3 1 Normal Mode 16 pins and registers that control ESSI operation The second 2 3 2 Network Mode 16 describes how the ESSI operates and includes small segments 2 3 2 1 Time Slot Register 17 of code that
14. Pins e Serial Control Pin 0 SCO Provides many different functions depending on the mode settings which are determined by the SYN TE1 and SCDO bits in Control Register A CRA Table 1 1 shows the various functions This pin also functions as GPIO pin PO Table 1 1 SCO Operation SYN TE1 SCDO Operation 1 Sync 0 Disable 0 Input Flag 0 input 1 Sync 0 Disable 1 Output Flag 0 output 1 Sync 1 Enable Transmitter 1 data always an output 0 Async 0 Input Receive clock input external 0 Async 1 Output Receive clock output internal e Serial Control Pin 1 SC1 Provides many different functions depending on the mode settings which are determined by the SYN TE1 SSC1 and SCDO bits in Control Register A CRA Table 1 2 shows the various functions This pin also functions as GPIO pin P1 Table 1 2 SC1 Operation SYN TE2 SCD1 SSC1 Operation 1 Sync 0 Disable 0 Input 0 Flag Flag 1 input 1 Sync 0 Disable 1 Output 0 Flag Flag 1 output 1 Sync 1 Enable Transmitter 2 data always an output 1 Sync 0 Disable 0 Input 1 TX0 Act Reserved 1 Sync 0 Disable 1 Output 1 TXO Act TXO active 0 Async 0 Input Receive frame sync input external 0 Async 1 Output Receive frame sync output internal e Serial Control Pin 2 SC2 Provides the serial frame sync for the ESSI This
15. TSR DSP56300 ESSI Programming 22 Transfer Methods e Transmit Last Slot Enabled by setting CRB 20 TLIE Triggered in network mode when TLIE is set and the last time slot is beginning Maximum time to service this interrupt must be less than the time to service the number of bits in one time slot e Transmit Data Enabled by setting CRB 18 TIE Triggered when TDE the transmit data register is empty and TIE are set simultaneously Cleared by writing to all enabled TX registers or to TSR Configuring interrupts requires two steps setting up the interrupt routine and enabling the interrupts To set up the interrupt routine place the code to be run during the interrupt at the interrupt starting address The interrupt routines can be short only two opcodes long or long more that two opcodes that requires a jsr instruction Enabling the interrupts involves setting the corresponding bits in CRB and enabling the ESSI interrupts in the Interrupt Priority Register Peripheral IPRP and enabling global interrupts in the Mode Register MR portion of the Status Register SR The following code sets up short interrupt routines to service the ESSIO and ESSI1 transmitter 0 and receiver This code uses equate labels for the location of the ESSI interrupt starting addresses These labels include the interrupt name preceded with I_ and can be found in the intequ asm file TX data represents any register or memory l
16. agawa ku Japan 81 3 5487 8488 Internet htto www motorola dsp com
17. ata is transferred from the transmit data registers into the transmit shift registers Thus when TDE is set the transmit data registers are empty and the core can write to the transmit data registers The following code polls the TDE bit and writes to the transmit registers when this bit is set TX data represents any register or memory location that contains the data to be transmitted Motorola DSP56300 ESSI Programming 21 Transfer Methods clr 6 x M_SSISRO Wait until ESSIO transmit registers ar mpty ovep TX00_data x M_TX00 Write data to ESSIO TXO reg ovep TX01_data x M_TX01 Write data to ESSIO TX1 reg ovep TX02_data x M_TX02 Write data to ESSIO TX2 reg 33 3u clr 6 x M_SSISRI1 Wait until ESSI1 transmit registers ar mpty ovep TX10_data x M_TX10 Write data to ESSI1 TXO reg ovep TX11_data x M_TX11 Write data to ESSI1 TX1 reg ovep TX12_data x M_TX12 Write data to ESSI1 TX2 reg 353 3u SSISR 7 Receive Data Register Full RDF determines when to read from the receive data register RDF is cleared when the core reads data from the receive data register RDF is set when data is transferred from the receive shift register to the receive data register Thus when RDF is set the receive data register is full and the core can read from the receive data register The following code polls the RDF bit and reads from the receive register when this bit is set RX data repr
18. bled Bat 3 MOD 0 Normal mode Bit 12 SYN 0 Asynchronous mode Bit 11 CKP Clk polarity on falling edge Bit 10 FSP 1 Frame sync polarity negative Bit 9 FSR 0 Frame sync with 1st bit Bit 8 7 FSL 11 Word length TX frame sync Bit length RX frame sync 7 Bit 6 SHF 1 Shift LSB first E Bit 5 SCKD 0 External clock source 7 Bit 4 SCD2 0 SC2 pin input Bit 3 SCD1 SC1 pin output Bit 2 SCDO 1 SCO pin output Bit 1 0 OF 1 0 00 Output flags 2 4 2 Example 2 This example programs ESSI1 for network synchronous mode Figure 2 10 shows the basic pinout diagram for this example SC11 is the TXO active signal The comments following the equates describe the other characteristics for this example STD1 SCK1 SC12 SRD1 SC10 SC11 TX Data Clock Frame Sync VY yY lg RX Data Flag 0 TX0 Active gt p Figure 2 10 Network Synchronous Mode Example The following code sets up the equates for CRA and CRB which initialize the ESSI Motorola DSP56300 ESSI Programming 19 Initialization CRAL EQU 505803 ESSI1 Control Register A CRA Bit 22 SSC1 1 SC1 pin TXO active Bit 21 19 WL 2 0 010 16 bits word Bit 18 ALC 0 Left align to bit 23 Bit 16 12 DC 4 0 00101 Number of time slots 6 Bit 11 PSR 1 Fixed prescaler bypassed f Bit 7 0 PM 7 0 00000011 Clock divide 4 r CRB1 EQU SFC357C ESSI
19. ceiver FSL 1 0 00 or 10 when the ESSI is in synchronous mode because the transmitter and receiver share a frame sync signal A bit length frame sync is required in normal mode MOD 0 with a divide ratio of 1 DC 4 0 00000 because this mode provides continuous data transfers Motorola DSP56300 ESSI Programming 14 Operation Modes Table 2 2 Frame Sync Length Frame Sync Length FSL1 FSLO RX TX 0 0 Word Word 0 1 Word Bit 1 0 Bit Bit 1 1 Bit Word Word length frame syncs can be positioned two ways based on the value of CRB 9 FSR If FSR is clear the word length frame sync occurs together with the first bit of the data word in the first time slot If FSR is set the word length frame sync occurs one clock cycle before the first bit in the data word of the first time slot The polarity of the frame sync signals is determined by CRB 10 FSP If FSP is clear the frame sync is positive i e the frame sync goes high to indicate a frame start If FSP is set the frame sync is negative i e the frame sync goes low to indicate a frame start 2 2 4 Flags When the ESSI is in synchronous mode and transmitters 1 and 2 are disabled the SCO and SC1 pins are available for use as flags The following rules apply for the flag signals If SCO is an e input SCDO 0 data on the SCO pin is seen on SSISR O IFO output SCDO 1 data written to OFO CRB O is seen on the SCO pin If SC1 is an i
20. e slot mask registers 2 3 2 1 Time Slot Register The time slot register TSR is a write only null data register that prevents data transmission in the current time slot TSR is similar to a transmit data register However when data is written to the TSR the data is not transmitted Instead all of the enabled transmitters are in the high impedance state for the current time slot The following code writes an arbitrary data word to the time slot registers for ESSIO and ESSI1 to disable transmission during the current time slot movep data x M_TSRO Write data to ESSIO TSRO reg disable TX movep data x M_TSR1 Write data to ESSIO TSR1 reg disable TX 2 3 2 2 Transmit Slot Mask Registers There are two transmit slot mask registers Transmit Slot Mask Register A TSMA and Transmit Slot Mask Register B TSMB Both TSMA and TSMB are 16 bits wide Together they can be regarded as one 32 bit register TSM When bit n of the TSM is set the transmit sequence proceeds normally during time slot n When bit n of the TSM is cleared the transmit data pins of the enabled transmitters are tri stated during time slot n Also when bit n of TSM is cleared the TDE and TUE flags in the SSISR are not set during time slot n Thus transmit interrupts are generated only for enabled time slots The transmit slot mask registers do not conflict with the TSR register Even if a time slot is enabled in the transmit slot mask registers writing to the TSR disabl
21. egister and from the ESSI receive register Table 2 3 shows the four available ESSI DMA request sources The DMA request source bits are used in the DMA Control Register DCR 15 11 Ne Ne Ne Ne Ne Motorola DSP56300 ESSI Programming 23 Transfer Methods Table 2 3 DMA Request Sources DMA Request Source Bits DSR 4 0 Requesting Device 01010 ESSIO Receive Data RDFO 1 01011 ESSIO Transmit Data TDEO 1 01100 ESSI1 Receive Data RDF1 1 01101 ESSI1 Transmit Data TDE1 1 The following code initializes DMA channel 2 to transfer data from x SOURCE to the ESSI1 transmit register Then the code initializes DMA channel 3 to transfer data from the ESSI1 receive register to x DEST COUNT number of transfers are completed and then the DMA channels are disabled The code includes memory moves that program the DMA registers and equate labels that fully describe the DMA control register bit settings DCR2 EQU 8A62C4 DMA Control Register 2 DCR2 E Bit 23 DE Bit 22 DIE E Bit 21 19 DIM 2 0 E Bit 18 17 DPR 1 0 s Bit 16 DCON Bit 15 11 DSR 4 0 E Bit 10 D3D Bit 9 7 DAM 5 3 E Bit 6 4 DAM 2 0 Bit 3 2 DDS 1 0 Bit 1 0 DSS 1 0 DCR3 EQU 8A6A51 DMA Control Register 3 DCR3 E Bit 23 DE Bit 22 DIE 5 Bit 21 19 DTM 2 0 E Bit 18 17 DPR 1 0 E Bit 16 DCON E Bit 15 11 DSR 4 0 E Bit 10 D3D Bit 9 7 DAM 5
22. es the transmitters The following code writes to the transmit slot mask registers for ESSIO and ESSI to disable transmission during all except the first and the fourth time slots To ensure that this code runs properly verify that the DC 4 0 bits are set so that there are at least four time slots per frame movep 0009 x M_TSMAO Load TSMA for ESSIO movep 0000 x M_TSMBO Load TSMB for ESSIO movep 0009 x M_TSMA1 Load TSMA for ESSI1 movep 0000 x M_TSMB1 Load TSMB for ESSI1 2 3 2 3 Receive Slot Mask Registers There are two receive slot mask registers Receive Slot Mask Register A RSMA and Receive Slot Mask Register B RSMB Both RSMA and RSMB are 16 bits wide Together they can be regarded as one 32 bit register RSM When bit n of RSM is set the transmit sequence proceeds normally during time slot n When bit n of RSM is cleared the receive data pins of the enabled transmitters are tri stated during time slot n Also when bit n of RSM is cleared the RDF and ROE flags in the SSISR are not set during time slot n Thus receive interrupts are generated only for enabled time slots The following code writes to the receive slot mask registers so that ESSIO receives only during the first time slot and ESSI1 receives only during the fourth time slot To ensure that this code runs properly verify that the DC 4 0 bits are set so that there are at least four time slots per frame Motoro
23. esents any register or memory location to which received data should be written 2 6 2 jclr 7 x M_SSISRO Wait until ESSIO receive register is full movep x M_RX0 RX0O_data Read data from ESSIO RX reg jclr 7 x M_SSISRI1 Wait until ESSI1 receive register is full movep x M_RX1 RXl_data Read data from ESSI1 RX reg Interrupts The ESSI provides the following six interrupts which are listed from highest to lowest priority e Motorola Receive Data with Exception Enabled by setting CRB 23 REIE Triggered when ROE a receiver overrun error is detected RDF the receive data register is full and REIE are set simultaneously Cleared by reading from SSISR and then from RX Receive Data Enabled by setting CRB 19 RIE Triggered when RDF the receive data register is full and RIE are set simultaneously Cleared by reading from RX Receive Last Slot Enabled by setting CRB 21 RLIE Triggered in network mode when RLIE is set and the last time slot ends Maximum time to service this interrupt must be less than the time to service the number of bits in one time slot Transmit Data with Exception Enabled by setting CRB 22 TEIE Triggered when TUE a transmit underrun error has been detected TDE the transmit data register is empty and TEIE are set simultaneously Cleared by writing to SSISR and then by writing to all enabled TX registers or to
24. frame The DC 4 0 bits in CRA define the divide ratio minus one The divide ratio can be interpreted as the frame length divided by the data length as Figure 2 7 shows This ratio can be between 1 and 32 DC 4 0 00000 to 11111 Frame Length Divide Ratio Frame Length Data Length Frame Sync Signal with word length frame sync EA Data Signal Data lt Data D Data Length rr Figure 2 7 Normal Mode Frame Divider Control 2 3 2 Network Mode The network mode of operation allows more than one time slot per frame Up to 32 data words can be transferred for every frame sync The DC 4 0 bits in CRA define the number of time slots per frame minus one Figure 2 8 illustrates the number of time slots per frame which can be between 2 and 32 DC 4 0 00001 to 11111 DC 4 0 00000 is reserved for on demand mode Frame Sync Signal with word length frame sync Number of Time Slots per Frame N a 4 a a o Data Signal X Data Data Data a D lt Data Data Data x X Data Data lt i Q tt Time Slot 1 Time Slot 2 Time Slot 3 Time Slot N Figure 2 8 Network Mode Frame Divider Control Motorola DSP56300 ESSI Programming 16 Operation Modes Some applications do not require data to be transmitted or received during every time slot There are two types of registers that control which time slots receive and transmit data the time slot register and th
25. gramming This section describes the practical operation of the ESSI covering transfer characteristics synchronization signals operation modes initialization method and transfer methods In some cases segments of code illustrate practical programming guidelines The code in this section uses equate labels for the location of the ESSI registers These labels include the register name preceded with M_ and can be found in the ioequ asm file 2 1 Transfer Characteristics Words transferred by the ESSI are characterized by word length shift direction and word alignment This section describes these characteristics and the programming associated with them 2 1 1 Word Length The ESSI presents six options for the number of bits per word or the word length To choose word length set the WL 2 0 bits in Control Register A CRA 21 19 as shown in Table 2 1 The ESSI transmit and receive data registers are 24 bits long so 32 bits words cannot be completely transmitted or received For 32 bit words two options are available the first 24 bits contain valid data and the last bit is duplicated eight times or the last 24 bits contain valid data and the first bit is duplicated eight times Table 2 1 Word Length WL2 WL1 WLO Number of Bits per Word 0 0 0 8 0 0 1 12 0 1 0 16 0 1 1 24 1 0 0 32 data valid in the first 24 bits 1 0 1 32 data valid in the last 24 bits 1 1 0 Reserved 1 1 1 Reserved
26. his example programs ESSIO for normal asynchronous mode Figure 2 9 shows the basic pinout diagram for this example Recall that in asynchronous mode there are separate clock and frame sync signals for the transmit and receive transfers The comments following the equates describe the other characteristics for this example STDO TX Data gt SCKO lt TX Clock SCO2 lng TX Frame Sync SRDO lag RX Data Sco0 RX Clock p SCO1 RX Frame Sync gt Figure 2 9 Normal Asynchronous Mode Example The following code sets up the equates for CRA and CRB which initialize the ESSI Motorola DSP56300 ESSI Programming 18 Programming Control Registers r CRAO EQU SO1F801 ESSIO Control Register A CRA Bit 22 SSC1 0 scl pin serial I O flag A Bit 21 19 WL 2 0 000 8 bits word Bit 18 ALC 0 Left align to bit 23 A Bit 16 12 DC 4 0 11111 Divide ratio 32 E Bit 11 PSR 1 Fixed prescaler bypassed Bit 7 0 PM 7 0 00000001 Clock divide 2 r CRBO EQU C80DCC ESSIO Control Register B CRB A But 23 REIE 1 RX exception int enabled Bit 22 TEIE 1 TX exception int enabled 7 Bit 21 RLIE 0 RX last slot int disabled z Bit 20 TLIE 0 TX last slot int disabled A Bit 19 RIE 1 RX int enabled s Bit 18 TIE 0 TX int disabled A Bit 17 RE 0 RX disabled Bit 16 TEO 0 TXO disabled A Bit 15 TEL 0 TX1 disabled Bit 14 TE2 0 TX2 disa
27. isters The following registers control ESSI operation Motorola Control Register A CRA One of two registers that control ESSI operation see Table 1 5 Control Register B CRB Second of two registers that control ESSI operation see Table 1 6 Status Register SSISR A read only register that describes the ESSI status and serial flags see Table 1 7 Transmit Slot Mask Register A TSMA and Transmit Slot Mask Register B TSMB Two registers that in network mode determine whether to transmit during a given time slot or to tri state the transmitter TSMA and TSMB together form one register TSM When bit n of TSM is cleared the transmit data pins of the enabled transmitters are tri stated during time slot n When bit n of TSM is set the transmit sequence proceeds normally during time slot n DSP56300 ESSI Programming 4 ESSI Registers Receive Slot Mask Register A RSMA and Receive Slot Mask Register B RSMB Two registers that in network mode determine whether to receive during a given time slot or tri state the receiver RSMA and RSMB together form one register RSM When bit n of RSM is cleared the receive data pin of the receiver is tri stated during time slot n When bit n of RSM is set the receive sequence proceeds normally during time slot n Time Slot Register TSR A write only null data register that in network mode prevents data transmission for the current time slot Receive Data Register
28. la DSP56300 ESSI Programming 17 Programming Control Registers movep 0001 x M_RSMAO movep 0000 x M_RSMBO movep 0008 x M_RSMA1 movep 0000 x M_RSMB1 2 3 2 4 On Demand Mode The on demand mode of operation does not generate a periodic frame sync Thus no time slots are defined in this mode A frame sync is generated only when data is ready to be transmitted i e data is written to a transmit data register The on demand mode is selected if the MOD bit is set and the DC 4 0 bits in CRA are all clear This mode requires that the transmit frame sync be internal output and the receive frame sync be external input for proper operation Because the transmit and receive frame syncs must be opposite only simplex operation receive or transmit but not both is allowed in synchronous mode Duplex operation receive and transmit simultaneously is allowed only in asynchronous mode Transmit underruns are impossible in on demand mode because there are no transmit time slots Thus transmit underruns are disabled Load RSMA for ESSIO Load RSMB for ESSIO Load RSMA for ESSI1 Load RSMB for ESSI1 No Ne Se Ne 2 4 Programming Control Registers This section shows how to program the control registers CRA and CRB to achieve the characteristics described in previous sections of this document Two examples are presented including pinout diagrams and equates describing the control register settings 2 4 1 Example 1 T
29. ls the divide ratio minus 1 00000 In network mode enables on demand mode 00001 11111 In network mode equals the number of time slots per frame minus 1 17 Reserved bits to be written with 0 18 Motorola ALC Alignment Control 0 Align data to bit 23 1 Align data to bit 15 not allowed with 24 and 32 bit word lengths ESSI Architecture 5 ESSI Registers Table 1 5 Control Register A CRA Bit No Bit Abbr Value Function 21 19 WL 2 0 Word Length Control 000 8 bits per word 001 12 bits per word 010 16 bits per word 011 24 bits per word 100 32 bits per word valid in the first 24 bits 101 32 bits per word valid in the last 24 bits 11x Reserved 22 SSCl Select SC1 as TXO active Valid only in synchronous mode with transmitter 2 disabled see Table 1 2 0 SCI is Flag 1 1 SC1 is TXO active Valid only if SC1 is configured as an input drives an external buffer for the transmitter 0 23 Reserved bit to be written with 0 Table 1 6 Control Register B CRB Bit No Bit Abbr Value Function 0 OFO Serial Output Flag 0 Valid only in synchronous mode with transmitter 1 disabled and SCO configured as an output see Table 1 1 Data written to OFO is seen on the SCO pin 1 OF 1 Serial Output Flag 1 Valid only in synchronous mode with transmitter 2 disabled and SC1 configured as an ou
30. nput SCD1 0 data on the SC1 pin is seen on SSISR 1 IF1 e output SCD1 1 data written to OF1 CRB 1 is seen on the SC1 pin The flags can change at the beginning of each frame in normal mode and at the beginning of each time slot in network mode There is one additional option for the SC1 pin In synchronous mode with transmitter 2 disabled the SC1 pin can be programmed as a transmitter 0 active signal When the TXO active pin is high transmitter 0 is active when this pin is low transmitter 0 is not active This signal can enable an external buffer for the transmitter 0 output This option is selected using CRA 22 SSC1 which is valid only in synchronous mode with transmitter 2 disabled If SSC1 is clear SC1 is the flag 0 signal If SSC1 is set SC1 is the transmitter 0 active signal 2 3 Operation Modes Motorola The ESSI has three basic modes of operation normal network and on demand The operation mode is selected by the MOD bit CRB 11 If MOD is clear the ESSI is normal mode If MOD is set the ESSI is in network mode Additionally the on demand mode is selected if MOD is set and the DC 4 0 bits in CRA are all clear The following sections describe each of the operation modes DSP56300 ESSI Programming 15 Operation Modes 2 3 1 Normal Mode The normal mode of operation has one time slot per frame Thus one data word is transferred for every frame sync However the data word does not have to fill the entire
31. o the receive data register and data is ready for reading from the receive data register In addition to the ESSI registers the three following port registers control ESSI GPIO functionality Port C is ESSIO and Port D is ESSI Port Control Register PCRC amp PCRD Control the functionality of the ESSI GPIO signals Each of the five bits in the port control registers controls the functionality of the corresponding port signal pin When a bit is set the corresponding port signal is configured as an ESSI signal When a bit is clear the corresponding port signal is configured as a GPIO Motorola signal ESSI Architecture 9 ESSI Registers Motorola Port Direction Register PRRC amp PRRD Control the direction of the ESSI GPIO signals Each of the five bits in the port direction registers controls the direction of the corresponding port signal pin if the pin is configured as a GPIO signal When a bit is set the corresponding port signal is configured as an output When a bit is clear the corresponding port signal is configured as an input Port Data Register PDRC PDRD Read write data to from the ESSI GPIO signals If a port signal is configured as a GPIO input the corresponding bit reflects the value present on the pin If a port signal is configured as a GPIO output the value written into the corresponding bit is reflected on the pin DSP56300 ESSI Programming 10 Transfer Characteristics Part 2 ESSI Pro
32. ocation that contains the data to be transmitted and RX data represents any register or memory location to which received data should be written org p I_SIOTD movep TX00_data x M_TX00 Write data to ESSIO TXO reg org PS LI SITTD movep TX10_data x M_TX10 Write data to ESSI1 TXO reg org p I_SIORD movep x M_RX0 RX0O_data Read data from ESSIO RX reg org p I_SI1RD movep X M_RX1 RX1_data Read data from ESSI1 RX reg The following code enables the ESSIO and ESSI1 transmit and receive interrupts Instead of the first four commands the interrupt enable bits in CRB can alternatively be set when CRB is initially programmed as in Step 2 of Section 2 5 bset 18 x M_CRBO bset 19 x M_CRBO bset 18 x M_CRB1 Enable ESSIO transmit interrupt Enable ESSIO receive interrupt Enable ESSI1 transmit interrupt bset 19 x M_CRB1 Enable ESSI1 receive interrupt andi S FC mr Unmask interrupts movep S03C x M_IPRP Set ESSI1 and ESSIO interrupt to priority 2 2 6 3 DMA The Direct Memory Access DMA controller is an on chip device that permits data transfers between internal external memory and or internal external I O in any combination without intervention of the core Due to dedicated DMA address and data buses as well as internal memory partitioning a high level of isolation is achieved so that DMA operation does not interfere with or slow down the core operation The DMA can move data to the ESSI transmit r
33. re 2 6 Clock Generation The maximum ESSI clock frequency is Fcorg 4 The PSR 1 and PM 7 0 00 to give Foorp 2 should not be used The minimum ESSI clock frequency is Fcopg 2 8 256 Foorg 4096 The polarity of the clock signal is determined by CRB 11 CKP If CKP is clear the data and the frame sync are clocked out on the rising edge of the transmit clock and latched in on the falling edge of the receive clock If CKP is set the data and the frame sync are clocked out on the falling edge of the transmit clock and latched in on the rising edge of the receive clock When SCK is an input SCKD 0 the internal clock generator is disconnected from the SCK pin and an external clock source can drive this pin 2 2 3 Frame Sync The frame sync signal indicates when a new frame begins In synchronous mode the SC2 pin is the frame sync for the receiver and all enabled transmitters In asynchronous mode SC2 is the frame sync signal for the receiver and SCO is the frame sync signal for transmitter 0 The direction of the frame sync pins is determined by the SCDO or SCD2 bits in CRB If either of these bits is clear the corresponding pin is an input If either of these bits is set the corresponding pin is an output The frame sync is characterized by its length and position The length of the frame sync is specified by the FSL 1 0 bits CRB 7 8 as shown in Table 2 2 The frame sync length must be the same for the transmitter and the re
34. t clock and latched in on the rising edge of the receive clock 12 SYN Synchronous Asynchronous 0 Asynchronous mode 1 Synchronous mode 13 MOD ESSI Mode Select 0 Normal mode 1 Network mode 14 TE2 Transmit 2 Enable Valid only in synchronous mode 0 Transmit 2 disabled 1 Transmit 2 enabled Motorola ESSI Architecture 7 ESSI Registers Table 1 6 Control Register B CRB Continued Bit No Bit Abbr Value Function 15 TE1 Transmit 1 Enable Valid only in synchronous mode Transmit 1 disabled Transmit 1 enabled 16 17 TEO RE Transmit 0 Enable Transmit 0 disabled Transmit 0 enabled Receive Enable Receive disabled Receive enabled 18 19 TIE RIE Transmit Interrupt Enable Interrupt disabled Interrupt enabled Receive Interrupt Enable Interrupt disabled Interrupt enabled 20 21 TLIE RLIE Transmit Last Slot Interrupt Enable Interrupt disabled Interrupt enabled Receive Last Slot Interrupt Enable Interrupt disabled Interrupt enabled 22 23 TEIE REIE Transmit Exception Interrupt Enable Interrupt disabled Interrupt enabled Receive Exception Interrupt Enable Interrupt disabled Interrupt enabled Motorola DSP56300 ESSI Programming ESSI Registers Table 1 7 Status Register SSISR
35. tput see Table 1 2 Data written to OF1 is seen on the SC1 pin 2 SCDO Serial Control Direction 0 Not valid when transmitter 1 is enabled see Table 1 1 0 SCO is an input 1 SCO is an output 3 SCD1 Serial Control Direction 1 Not valid when transmitter 2 is enabled see Table 1 2 0 SC1 is an input 1 SC1 is an output 4 SCD2 Serial Control Direction 2 see Table 1 3 0 SC2 is an input 1 SC2 is an output Motorola DSP56300 ESSI Programming ESSI Registers Table 1 6 Control Register B CRB Continued Bit No Bit Abbr Value Function 5 SCKD Clock Source Direction see Table 1 4 0 SCK is input clock 1 SCK is output clock 6 SHFD Shift Direction 0 Shift MSB first 1 Shift LSB first 8 7 FSL 1 0 Frame Sync Length Receive Transmit 00 Word length Word length 01 Word length Bit length 10 Bit length Bit length 11 Bit length Word length 9 FSR Frame Sync Relative Timing Only valid with word length frame syncs 0 Frame sync begins with first bit of data word 1 Frame sync begins one bit before first bit of data word 10 FSP Frame Sync Polarity 0 Frame sync polarity is positive 1 Frame sync polarity is negative 11 CKP Clock Polarity 0 Data and frame sync are clocked out on the rising edge of the transmit clock and latched in on the falling edge of the receive clock 1 Data and frame sync are clocked out on the falling edge of the transmi
36. ument by the order number DSP56303UM AD Or download it from the Motorola Web site at http www mot com SPS DSP documentation DSP56300 html 3 Download the equate files ioequ asm and intequ asm from the Motorola Web site at http www mot com SPS DSP software other html Motorola DSP56300 ESSI Programming 25 References NOTES Motorola DSP56300 ESSI Programming 26 References NOTES Motorola DSP56300 ESSI Programming 27 OnCE and Mfax are registered trademarks of Motorola Inc Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into
Download Pdf Manuals
Related Search