Digilent Nexys2 Board Reference Manual
Contents
1. PS2 style keyboards use scan codes to communicate key press data Each key is assigned a code that is sent whenever the key is pressed if the key is held down the scan code will be sent repeatedly about once every 100ms When a key is released a FO key up code is sent followed by the scan code of the released key If a key can be shifted to produce a new character like a capital letter then a shift character is sent in addition to the scan code and the host must determine which ASCII character to use Some keys called extended keys send an E0 ahead of the scan code and they may send more than one scan code When an extended key is released an EO FO key up code is sent followed by the scan code Scan codes for most keys are shown in the figure A host device can also send data to the keyboard Below is a short list of some common commands a host might send ED Set Num Lock Caps Lock and Scroll Lock LEDs Keyboard returns FA after receiving ED then host sends a byte to set LED status Bit 0 sets Scroll Lock bit 1 sets Num Lock and Bit 2 sets Caps lock Bits 3 to 7 are ignored EE Echo test Keyboard returns EE after receiving EE F3 Set scan code repeat rate Keyboard returns F3 on receiving FA then host sends second byte to set the repeat rate FE Resend FE directs keyboard to re send most recent scan code FF Reset Resets the keyboard The keyboard can send d2. as an asynchronous SRAM the Cellular RAM automatically refreshes its internal DRAM arrays allowing for a simplified memory controller design similar to any SRAM in the FPGA When operated in synchronous mode continuous transfers of up to 80MHz are possible The external ROM is a 128Mbit Intel TE28F128J3D75 110 StrataFlash device organized as 8Mbytes x 16bits Internally it contains 128 blocks that can be individually erased and it supports 110ns read cycle times with 25ns page mode reads within blocks It has an internal 32 byte write buffer that can be written with 7Ons cycle times and the 32 byte buffer can be transferred to the Flash array in 218us typical Both devices share a common 16 bit data bus and 24 bit address bus The Cellular RAM is byte addressable using the upper byte and lower byte signals MT UB and MT LB but the StrataFlash is configured for 16 byte operations only it is not byte addressable The output enable OE and write enable WE signals are shared by both devices but each device has individual chip enable CE signals Additionally the Cellular RAM has clock MT CLK wait MT WAIT address valid MT ADV and control register enable MT_CRE signals available to the FPGA for use with synchronous transfers and the StrataFlash has Reset RP and status STS signals routed to the FPGA Copyright Digilent Inc Page 13 17 Doc 502 134 Nexys2 Reference Manual A Digilent www digilentinc com VDHL sourc
3. displayed are based on observations taken from actual VGA displays Back porch 928 us 23 200 1 92 us Figure 19 VGA system timings for 640x480 display A VGA controller circuit decodes the output of a horizontal sync counter driven by the pixel clock to generate HS signal timings This counter can be used to locate any pixel location on a given row Likewise the output of a vertical sync counter that increments with each HS pulse can be used to generate VS signal timings and this counter can be used to locate any given row These two continually running counters can be used to form an address into video RAM No time relationship between the onset of the HS pulse and the onset of the VS pulse is specified so the designer can arrange the counters to easily form video RAM addresses or to minimize decoding logic for sync pulse generation o HS Zero Zero CE Ea Set Horizontal Horizontal Vertical Vertical Pixel Counter Synch Counter Synch CLK Reset 64us Reset Detect Figure 20 Schematic for a VGA controller circuit Copyright Digilent Inc Page 12 17 Doc 502 134 Digilent www digilentinc com Nexys2 Reference Manual A Serial Port The Nexys2 contains a two wire serial port based on an ST Microelectronics ST3232 voltage converter The ST3232 converts the signal levels used by RS 232 communications 12 to 3 fora logic 1 and 12V to 3V for a logic 0 to the 3 3V signals used by the FPGA Since only two s
4. the frequency at which current flows through the deflection coils and it must ensure that video data is applied to the electron guns at the correct time Raster video displays define a number of rows that corresponds to the number of horizontal passes the cathode makes over the display area and a number of columns that corresponds to an area on each row that is assigned to one picture element or pixel Typical displays use from 240 to 1200 rows and from 320 to 1600 columns The overall size of a display and the number of rows and columns determines the size of each pixel Video data typically comes froma video refresh memory with one or Copyright Digilent Inc pixel 0 0 pixel 0 639 640 pixels per row are displayed during forward beam trace Retrace no information displayed during this time Display Surface a pixel 479 0 pixel 479 639 Stable current ramp information is displayed during this time 7 Current waveform through horizontal l 3 defletion gt Total horizontal time coil i l Hori tal disblav ti retrace orizontal aisplay time i l lt play lt gt time HS time C Horizontal sync signal ca porch sets retrace frequency t back porch Figure 18 VGA system signals Page 11 17 Doc 502 134 Digilent Nexys2 Reference Manual www digilentinc com more bytes assigned to each pixel location the Nexys2 uses thr
5. 23 Peio Go 2 a eos re fa Mar Fx21022 Bio 2 Poa P1023 An 2 29 exei024 on 2 30 Fx21025 E10 3 rat P1026 Bi 3 rae P1027 cn 3 as Fxeio28 En 3 a4 Peio Fu 3 a5 Px21030 E12 3 36 P2031 F12 3 a7 P1032 Ais 3 3s Fx21033 Bia 3 a0 Fx21034 E13 3 40 Pxe035 Ala 4 Ca Poss ota 4 a2 Fxoi037 Dia 4 as Pxeios8 Bia 4 a4 Peio Ate as Fx21040 B16 4 ras GND 4 a7 FX CLKOUT D9 4 ras o 4 voore J4 so vecexe 5 FX2 CLKIO VCCFX2 SHIELD Copyright Digilent Inc Page 16 17 Doc 502 134 Digilent www digilentinc com Nexys2 Reference Manual A Built in Self Test A demonstration configuration is loaded into the Platform Flash ROM on the Nexys2 board during manufacturing This demo also available on the resource CD and on the Digilent website can serve as a board verification test since it interacts with all devices and ports on the board To configure the FPGA from a bit file stored in Platform Flash set the Mode Jumper to Slave Serial and cycle power or press the FPGA reset button The self test checks the on board memories and then connects the switches to the LEDs the buttons and PS 2 keyboard if attached to the seven segment display and a VGA monitor if attached will show a color pattern If the on board memories pass test PASS will be displayed on the seven segment display otherwise F
6. AIL After the memory test the buttons and switches will drive the LEDs and seven segment display so that all user I O devices can be manually checked lf the self test is not resident in the Platform Flash ROM it can be programmed into the FPGA or reloaded into the ROM using the Adept programming software All Nexys2 boards are 100 tested during the manufacturing process If any device on the Nexys2 board fails test or is not responding properly it is likely that damage occurred during transport or during use Typical damage includes stressed solder joints or contaminants in switches and buttons resulting in intermittent failures Stressed solder joints can be repaired by reheating and reflowing solder and contaminants can be cleaned with off the shelf electronics cleaning products If a board fails test within the warranty period it will be replaced at no cost If a board fails test outside of the warranty period and cannot be easily repaired Digilent can repair the board or offer a discounted replacement Contact Digilent for more details Copyright Digilent Inc Page 17 17 Doc 502 134
7. B power is driving the main power bus care should be taken to ensure no more than 200mA is consumed by the Pmod Further if the jumper is set to VU a voltage source connected to the Pmod can drive the main power bus of the Nexys2 board so care should be taken to avoid connecting conflicting power supplies The Pmod connectors are labeled JA nearest the power jack JB JC and JD nearest the expansion connector Pinouts for the Pmod connectors are provided in the table below More than 30 low cost are available for attachment to these connectors Pmods can either be attached directly or by using a small cable Available Pmods include A D and D A converters motor drivers speaker amplifiers distance measuring devices etc Please see www digilentinc com for more information Resistors for short a circuit protection JA1 JA2 JA3 JAS JA6 JA7 JA8 Spartan 3E FPGA K ESD protection N 3 3V diodes Power supply jumper Figure 23 Nexys2 Pmod connector circuits Table 3 Nexys2 Pmod Connector Pin Assignments Pmod JA Pmod JB Pmod JC Pmod JD JA1 L15 JA7 K13 JB1 M13 JB7 P17 JC1 G15 JC7 H15 JD1 J13 JD7 K14 JA2 K12 JA8 L16 JB2 R18 JB8 R16 JC2 J16 JC8 F14 JD2 M18 JD8 K15 JA3 L17 JAI M14 JB3 R15 JB9 T18 JC3 G13 JC9 G16 JD3 N18 JD9 J15 JA4 M15 JA10 M16 JB4 T17 JB10 U18 JC4 H16 JC10 J12 JD4 P18 JD10 J14 Notes 1 shared with LD3 2 shared with LD3 3 shared with L
8. D3 shared with LD3 Copyright Digilent Inc Page 15 17 Doc 502 134 Nexys2 Reference Manual Expansion connector The Nexys2 board includes a Hirose FX 2 high density 100 pin connector that is suitable for driving peripheral boards with signal rates in excess of 100 MHz Many connector signals are routed to the FPGA as differential pairs and 47 connector pins are tied to ground resulting ina very low noise connection system The self aligning Hirose FX 2 connector can be used for board to board connections or board to cable connections using the mating Hirose FX2 100S 1 27 available from many catalog distributors and directly from Digilent All signals routed from the FPGA to the FX 2 connector include 75 ohm series resistors The table on the right shows all signal connections between the FX 2 connector and the FPGA Signals without corresponding entries in the FPGA column are not directly connected to the FPGA N Digilent www digilentinc com Table 4 Hirose FX2 Connector Pin Assignments A Name FPGA J1B Name FPGA a vecava 1 SHIELD 2 vov fef a s ms bis s TOO ROM Map aseu a 5 Torx e Peor Ba z eo m a Fx2 103 c3 o Poa C4 o Fx2 i05 ee 4 u Po os 4 e Peor cs 4 rag Pos Fr 4 ria Poo Er 4 P15 Peono AB 4 rie Peon c7 4 a Peo Fe 4 e Peo 07 4 rig Peor es 4 C20 Fxei015 Eo Ca Peor co Pea Peio as 2
9. Digilent Nexys2 Board U DIGILE NTI Reference Manual uw ciailentine com Revision July 11 2011 215 E Main Suite D Pullman WA 99163 509 334 6306 Voice and Fax Overview iroj i i Flash SDRAM The Nexys2 circuit board is a complete PL peel Clock 16 MByte 16 MByte ready to use circuit development platform AG ae BAe contgrom SO MHZ Gte gmcron based on a Xilinx Spartan 3E FPGA Its on Data f board high speed USB2 port 16Mbytes of 20 J port port 45 RAM and ROM and several I O devices and F 4 ports make it an ideal platform for digital gt XILINX systems of all kinds including embedded Spartan3E 500 FG320 processor systems based on Xilinx s MicroBlaze The USB2 port provides board foz 8 bit 2 he ha power and a programming interface so the an ppan Nexys2 board can be used with a notebook IBS a Ee ee Hi speed computer to create a truly portable design pore station I O Devices Data Ports Expansion Connectors The Nexys2 brings leading technologies toa e 500K gate Xilinx Spartan 3E FPGA platform that anyone can use to gain digital e USB2 based FPGA configuration and high speed data design experience It can host countless transfers using the free Adept Suite Software FPGA based digital systems and designs e USB powered batteries and or wall plug can also be used can pee Hea beyond the board usngany e 16MB of Micron PSDRAM amp 16MB of Intel Str
10. Inc All rights reserved 12 pages Doc 502 134 Nexys2 Reference Manual A Digilent www digilentinc com Power Input power bus Jack ae LTC1765 9 Main supply 3 3V Switching Batte u ea S 2 5V a Regulator All other _ 18V regualtors _ 1 ay USB l Select Connector Jumper Figure 2 Nexys2 power supply block diagram The input power bus drives a 3 3V voltage regulator Table 1 Nexys2 Power Supplies that supplies all required board current Some devices Supply Amps max typ require 2 5V 1 8V and 1 2V supplies in addition to the IC6 LTC1765 3A 100mA 3 main 3 3V supply and these additional supplies are D 1 1 created by regulators that take their input from the main 3 3V supply The primary supplies are generated by highly efficient switching regulators from Linear Technology These regulators not only use USB power efficiently they also allow the Nexys2 to run from battery packs for extended periods Total board current depends on the FPGA configuration clock frequency and external connections In test circuits with roughly 20K gates routed a 50MHz clock source and all LEDs illuminated about 200mA of current is drawn from the 1 2V supply 50mA from the gt 2 5V supply and 100mA from the 3 3V supply Required Oe HA eee current will increase if larger circuits are configured in eR ae the FPGA and if peripheral boards are attached The ane Eea table above summarizes the power supply par
11. S 2 select jumper 3 3V provided to PS 2 as Pini Data Pin2 Data Pin3 GND R12 200 Q Pin5 Vdd Spartan 3E 5 2 1 3 Pin6 Clock FPGA n A Pin8 Clock P11 O O 6 pin bottom up mini DIN Figure 12 Nexys2 PS 2 circuits Both the mouse and keyboard use a two wire serial bus clock and data to communicate with a host device Both use 11 bit words that include a start stop and odd parity bit but the data packets are organized differently and the keyboard interface allows bi directional data transfers so the host Copyright Digilent Inc Page 7 17 Doc 502 134 Nexys2 Reference Manual JIA Digilent www digilentinc com device can illuminate state LEDs on the keyboard Edge 0 ee Edge 10 Bus timings are shown in the figure The clock and Mj 3 data signals are only driven when data transfers O start bit _ gt Thid g Stop bit occur and otherwise they are held in the idle state at logic 1 The timings define signal Tsu gt requirements for mouse to host communications C Parameter and bi directional keyboard communications A PS 2 interface circuit can be implemented in the FPGA to create a keyboard or mouse interface Clock to data hold time Figure 13 PS 2 signal timings Keyboard The keyboard uses open collector drivers so the keyboard or an attached host device can drive the two wire bus if the host device will not send data to the keyboard then the host can use input only ports
12. The Nexys2 board uses a six layer PCB with the inner layers dedicated to VCC and GND planes The FPGA and the other ICs on the board all have a large complement of bypass capacitors placed as close as possible to each VCC pin The power supply routing and bypass capacitors result in a very clean stable and low noise power supply FPGA and Platform Flash Configuration The FPGA on the Nexys2 board must be configured or programmed by the user before it can perform any functions During configuration a bit file is transferred into memory cells within the FPGA to define the logical functions and circuit interconnects The free ISE WebPack CAD software from Xilinx can be used to create bit files from VHDL Verilog or schematic based source files The FPGA can be programmed in two ways Cypress JTAG Mode directly from a PC using the on board USB port EZ USB header Jumper and from an on board Platform Flash ROM the Flash ROM is also user programmable via the a He Peg gale USB port A jumper on the Nexys2 board USB miniB ite Serial determines which source PC or ROM the connector FPGA will use to load its configuration The Spartan 3E Vdd FPGA will automatically load a configuration FPGA from the Platform Flash ROM at power on if the JTAG configuration Mode jumper is set to Master Parki lt port PROG FPGA serial If the Mode jumper is set to JTAG the Ta ER Li FPGA will await programming fr
13. a a Ua aa Lo eas TE ce Bios iLp iloa bioz gio Loo 4 CREB ADE izeres ikia AE EJH RIBANA CED ALE k14 Figure 7 Nexys2 board I O devices Inputs Slide Switches and Pushbuttons Four pushbuttons and eight slide switches are provided for circuit inputs Pushbutton inputs are normally low and they are driven high only when the pushbutton is pressed Slide switches generate constant high or low inputs depending on their position Pushbutton and slide switch inputs use a Copyright Digilent Inc Page 4 17 Doc 502 134 Nexys2 Reference Manual A Digilent www digilentinc com series resistor for protection against short circuits a short circuit would occur if an FPGA pin assigned to a pushbutton or slide switch was inadvertently defined as an output 3 3V B18 J14 D0 Buttons BTN D18 K15 P2 i LEDs K14 2s ae SN E16 LD4 4 l 2 BIN3 H13 P15 P16 LD5 i F4 E4 2p R4 P4 2 3 3V SWig o w H18 ie a SW2 o wv _ K18 F15 is AN3 Slid a PEE ei hes SW35 0 w K17 Spartan 3E Il I I FPGA l lal ll l SW o w L18 ml CA Sseg SW5 o wv L13 lee CB Display SW6 o w N17 D16 G14 SW7 o w R17 J17 H14 C17 pin numbers for 1200 die Figure 8 Nexys2 I O devices and circuits Outputs LEDs Eight LEDs are provided for circuit outputs LED anodes are driven from the FPGA via 390 ohm resistors so a logic 1 output will illuminate them with 3 4ma of drive curren
14. ameters The Nexys2 board can also receive power from or deliver power to a peripheral board connected to a Pmod connector or to the large 100 pin expansion connector Jumpers near the Pmod connectors and large expansion connector JP1 JP5 can connect the Nexys2 s input power bus to the connector s power pins The Pmod jumpers can be used to route either the input ee k Wa lili i EEEE HHH power bus or regulated 3 3V to the Pmod power pins Ce ra ORN E F while the expansion connector jumper can only make or break a connection with the input power bus USB power is supplied to the USB circuitry directly but to the rest of the board through an electronic switch Q1 in the Nexys2 schematic The on board USB controller turns on switch Q1 only after informing the host PC that Figure 3 Nexys2 power supply jumpers Copyright Digilent Inc Page 2 17 Doc 502 134 Nexys2 Reference Manual A ee more than 100mA will be drawn through the USB cable as required by the USB specification A USB host can supply only 500mA of current at 5 DC When using USB power care must be taken to ensure the Nexys2 board and any attached peripheral boards do not draw more than 500mA or damage to the host may result The Nexys2 board typically consumes about 300mA of USB current leaving about 200mA for peripheral boards If peripheral boards require more current than the USB cable can supply an external power supply should be used
15. asses through the neck of the CRT where two coils of wire produce orthogonal electromagnetic fields Because cathode rays are composed of charged particles electrons they can be deflected by these magnetic fields Current waveforms are passed through the coils to produce magnetic fields that interact with the cathode rays and cause them to transverse the display surface in a raster pattern horizontally from left to right and vertically from top to bottom As the cathode ray moves over the surface of the display the current sent to the electron guns can be increased or decreased to change the brightness of the display at the cathode ray impact point Information is only displayed when the beam is moving in the forward direction left to right and top to bottom and not during the time the beam is reset back to the left or top edge of the display Much of the potential display time is therefore lost in blanking periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass The size of the beams the frequency at which the beam can be traced across the display and the frequency at which the electron beam can be modulated determine the display resolution Modern VGA displays can accommodate different resolutions and a VGA controller circuit dictates the resolution by producing timing signals to control the raster patterns The controller must produce synchronizing pulses at 3 3V or 5V to set
16. ata to the host only when both the data and clock lines are high or idle Since the host is the bus master the keyboard must check to see whether the host is sending data before driving the bus To facilitate this the clock line is used as a clear to send signal If the host pulls the clock line low the keyboard must not send any data until the clock is released The keyboard sends data to the host in 11 bit words that contain a 0 start bit followed by 8 bits of scan code LSB first followed by an odd parity bit and terminated with a 1 stop bit The keyboard generates 11 clock transitions at around 20 830KHz when the data is sent and data is valid on the falling edge of the clock scan codes for most PS 2 keys are shown in the figure below Copyright Digilent Inc Page 8 17 Doc 502 134 Nexys2 Reference Manual A Digilent www digilentinc com ESC F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 76 05 06 04 OC 03 OB 83 OA 01 09 78 07 E075 1 1 2 3 4 5 6 7 amp 8 9 0 _ BackSpace gt OE 16 1E 26 25 2E 36 3D 3E 46 45 4E 55 66 EO 74 TAB Q W E R T Y U O P if 7 yo OD 15 1D 24 2D 2C 35 3C 43 44 4D 54 5B 5D E0 6B Caps Lock A S D F G H J K L fa Enter 58 1C 1B 23 2B 34 33 3B 42 4B 4C 52 5A EO 72 Shift Z X C V B N M lt gt A Shift 12 1Z 22 21 2A 32 31 3A 41 49 4A 59 Ctrl Alt Space Alt Ctrl 14 11 29 EO 11 EO 14 F
17. ataFlash ROM Oral OL Meriva ye al Slo eo mneiOle oul e Xilinx Platform Flash for nonvolatile FPGA configurations 12 pin Peripheral Module Pmod connectors Praen caine i eee can accommodate up to eight low cost icient switch mode power supplies good for battery powered applications Pmods to add features like motor control A D and D A conversion audio circuits anda host 50MHz oscillator plus socket for second oscillator of sensor and actuator interfaces All user e 60 FPGA I O s routed to expansion connectors one high accessible signals on the Nexys2 board are speed Hirose FX2 connector and four 6 pin headers ESD and short circuit protected ensuring a e 8 LEDs 4 digit Seg display 4 buttons 8 slide switches long operating life in any environment Ships in a plastic carry case with USB cable The Nexys2 board is fully compatible with all Figure 1 Nexys2 block diagram and features versions of the Xilinx ISE tools including the free WebPack Now anyone can build real digital systems for less than the price of a textbook Power Supplies The Nexys2 board input power input bus can be driven from a USB cable from a 5VDC 15VDC center positive 2 1mm _ wall plug supply or from a battery pack A shorting block loaded on the oower select jumper selects the power source The USB circuitry is always powered from the USB cable if no USB cable is attached the USB circuitry is left unpowered Copyright Digilent
18. be written using Digilent s in i public API s to access the Nexys2 USB ah oe hi gt are connection Information on using Adept and or the public API s to transfer data can Figure 11 Nexys2 USB circuit be found on the Digilent website The USB port can also provide power to the Nexys2 board if the power select jumper is set to USB The USB specification requires that attached devices draw no more than 100mA until they have requested more current after which up to 500mA may be drawn When first attached to a USB host the Nexys2 board requests 500mA and then activates a transistor switch to connect the USB cable voltage to the main input power bus The Nexys2 board typically draws around 300mA from the USB cable and care should be taken especially when using peripheral boards to ensure that no more than 500mA is drawn PS 2 Port The 6 pin mini DIN connector can accommodate a PS 2 mouse or keyboard Most PS 2 devices can operate from a 3 3V supply but older devices may require a 5VDC supply A three pin jumper on the Nexys2 board immediately adjacent to the PS 2 connector selects whether regulated 3 3V or the main input power bus voltage VU is supplied to the PS 2 connector To send 5V to the PS 2 connector set the PS2 power jumper to Vswt the main input power bus and ensure the board is powered from USB or a 5VDC wall plug supply To send 3 3V to the connector set the jumper to 3 3V 3V3 Vswt PS 2 power 5V provided to P
19. e displayed one for each unique 8 bit pattern A video controller circuit must be created in the P6 FPGA to drive the sync and color signals with the correct timing in order to produce a working display system U4 1KQ P8 GRN1 GRN2 5100 1KQ U5 BLUEO BLUE1 5109 1009 1009 VGA System Timing T4 U3 VGA signal timings are specified published copyrighted and sold by the VESA organization www vesa org The following VGA system Figure 16 VGA pin definitions and Nexys2 circuit timing information is provided as an example of how a VGA monitor might be driven in 640 by 480 mode For more precise information or for information on other VGA frequencies refer to documentation available at the VESA website CRT based VGA displays use amplitude modulated moving electron beams or cathode rays to display information on a phosphor coated screen LCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal thereby changing light MARAE ENE E permittivity through the crystal on a pixel Cathode ray tube by pixel basis Although the following Deflection coils description is limited to CRT displays LCD displays have evolved to use the same signal timings as CRT displays so the ow signals discussion below pertains to both D CRTs and LCDs Color CRT displays use n N three electron beams one for red one for L BSN iaunis blue and one for green to energize the pt 2
20. e code is available in a reference design posted on the Digilent website to illustrate the use of these devices A base system builder file is also available for using these devices with Xilinx s EDK tool and MicroBlaze processor core both available from Xilinx Complete information is available for both devices from the manufacturer websites See table See table Spartan 3E T2 FPGA N7 IC13 only K5 D3 IC14 only l Ss R5 Figure 22 Nexys2 memory circuits Table 2 Memory Address and Data Bus Pin Assignments Address signals Data signals ADDR8 H6 ADDR16 M5 DATAO L1 DATA8 L3 ADDR9Y F1 ADDR17 E2 DATA1 L4 DATA9 L5 ADDRO NA ADDR1 J1 ADDR2 J2 ADDR3 H4 ADDR4 H1 ADDR5 H2 ADDR6 J5 ADDR7 H3 ADDR10 G3 DATA10 M3 ADDR11 G6 DATA11 M6 ADDR12 G5 DATA12 L2 ADDR13 G4 DATA13 N4 ADDR14 F2 DATA14 R3 ADDR15 El DATA15 Ti Copyright Digilent Inc Page 14 17 Doc 502 134 Digilent www digilentinc com Nexys2 Reference Manual A Peripheral Connectors The Nexys2 board provides four two row 6 pin Pmod connectors that together can accommodate up to 8 Pmods The four 12 pin connectors each have 8 data signals two GND pins and two Vdd pins All data signals include short circuit protection resistors and ESD protection Diodes A jumper block adjacent to each Pmod connector can connect the Pmod s Vdd signal to the Nexys2 board s 3 3V supply or to the input power bus VU If the jumper is set to VU and US
21. ee bits per pixel The controller must index into video memory as the beams move across the display and retrieve and apply video data to the display at precisely the time the electron beam is moving across a given pixel A VGA controller circuit must generate the T HS and VS timings signals and coordinate T the delivery of video data based on the pixel lt q 0 y clock The pixel clock defines the time available to display one pixel of information The VS signal defines the refresh frequency of the display or the frequency at which all information on the display is redrawn The minimum refresh frequency is Horiz Sync Vertical Sync Time Clocks Lines Time Parameter Clks a function of the display s phosphor and electron beam intensity with practical refresh frequencies falling in the 50Hz to 120Hz range The number of lines to be Sync pulse 16 7ms 416 800 32 us 800 Display time 15 36ms 384 000 480 25 6 us 640 Pulse width 64 us 1 600 3 84 us Front porch 320 us 8 000 640 ns displayed at a given refresh frequency defines the horizontal retrace frequency For a 640 pixel by 480 row display using a 25MHz pixel clock and 60 1Hz refresh the signal timings shown in the table at right can be derived Timings for sync pulse width and front and back porch intervals porch intervals are the pre and post sync pulse times during which information cannot be
22. he status byte indicate Left and Right button presses a 1 indicates the button is being pressed Mouse status byte m X direction byte m Y direction byte 110 LIRIO0 1 IXS YSIXYIYY P 1 0 X0O X1 X2 X3 X4 X5 X6 X7 P 1 0 YO Y1 Y2 Y3 Y4 Y5 Y6 Y7 P Start bit Stop bit Start bit Stop bit Start bit Stop bit Idle state Idle state Figure 15 Mouse data format Copyright Digilent Inc Page 9 17 Doc 502 134 Nexys2 Reference Manual A pigiiont www digilentinc com VGA Port The Nexys2 board uses 10 FPGA signals to create a VGA port with 8 bit color and the two standard sync signals HS Horizontal Sync and VS Vertical Sync The color signals use resistor divider circuits that work in conjunction with the 75 ohm termination resistance of the VGA display to create eight signal levels on the Pin 1 Red Pin 5 GND Pin 2 Grn Pin 6 Red GND Pin 3 Blue Pin 7 Grn GND Pin 13 HS Pin 8 Blu GND Pin 14 VS Pin 10 Sync GND red and green VGA signals and four on blue Rg REDO aN the human eye is less sensitive to blue levels Spartan 3E REDI 1KQ This circuit shown in figure 13 produces video FPGA Ue RED 100 color signals that proceed in equal increments R8 between OV fully off and 0 7V fully on Using ye CRNO 2K HD DB15 this circuit 256 different colors can b
23. ignals are connected RXD and TXD an FPGA based serial port controller can only use software hand shaking protocols XON XOFF The Nexys2 serial port is useful for many applications and in particular for debugging and working with Xilinx s MicroBlaze embedded processor The two devices connected to either end of a serial cable are known as the Data Terminal Equipment DTE and the Data Communications Equipment DCE The DCE was originally conceived to be a modem but now many devices connect to a computer as a DCE A DTE source device uses a male DB 9 connector and a DCE peripheral device uses a female DB 9 DB 9 connector Two DTE devices can be connected via a serial P9 TIIN T1OUT cable only if lines two and three U6 W RIOUT RIIN RXD and TXD are crossed 100Q producing what is known as a null modem cable A DTE and DCE ST3232 device can be connected with a RS 232 straight through cable The Spartan 3E voltage Nexys2 is configured as a DCE FPGA converter device with the assumption it will most typically be connected to a DTE device like a computer Figure 21 Nexys2 serial port circuit Memory The Nexys2 board has external RAM and ROM devices The external RAM is a 128Mbit Micron M45W8MW16 Cellular RAM pseudo static DRAM device organized as 8Mbytes x 16bits It can operate as a typical asynchronous SRAM with read and write cycle times of 70ns or as a synchronous memory with an 80MHz bus When operated
24. ignals are common to all digits but they can only illuminate the segments of the digit whose corresponding anode signal is asserted Common anode aN ANO AN1 AN2 AN3 yo F N Il ttl LA A a CA CB CC CD CE CF CG DP Four digit Seven Segment Display DP eo ooo ORE canal An un illuminated seven segment display and nine illumination patterns corresponding to decimal digits Individual cathodes Figure 9 Nexys2 seven segment displays A scanning display controller circuit can be used to show a four digit number on this display This circuit drives the anode signals and corresponding cathode patterns of each digit in a repeating continuous succession at an update rate that is faster than the human eye can detect Each digit is illuminated just one quarter of the time but because the eye cannot perceive the darkening of a digit before it is illuminated again the digit appears continuously illuminated If the update or refresh rate is slowed to around 45 hertz most people will begin to see the display flicker In order for each of the four digits to appear bright and continuously illuminated all four digits should be driven once every 1 to 16ms for a refresh frequency of 1KHz to 60Hz For example in a 60Hz refresh scheme the entire display would be refreshed once every 16ms and each digit would be illuminated for 1 4 of the refresh cycle or 4ms The c
25. igure 14 PS 2 keyboard scan codes Mouse The mouse outputs a clock and data signal when it is moved otherwise these signals remain at logic 1 Each time the mouse is moved three 11 bit words are sent from the mouse to the host device Each of the 11 bit words contains a 0 start bit followed by 8 bits of data LSB first followed by an odd parity bit and terminated with a 1 stop bit Thus each data transmission contains 33 bits where bits 0 11 and 22 are 0 start bits and bits 10 21 and 33 are 1 stop bits The three 8 bit data fields contain movement data as shown in the figure above Data is valid at the falling edge of the clock and the clock period is 20 to 30KHz The mouse assumes a relative coordinate system wherein moving the mouse to the right generates a positive number in the X field and moving to the left generates a negative number Likewise moving the mouse up generates a positive number in the Y field and moving down represents a negative number the XS and YS bits in the status byte are the sign bits a 1 indicates a negative number The magnitude of the X and Y numbers represent the rate of mouse movement the larger the number the faster the mouse is moving the XV and YV bits in the status byte are movement overflow indicators a 1 means overflow has occurred If the mouse moves continuously the 33 bit transmissions are repeated every 50ms or so The L and R fields in t
26. ll comme ite phosphor that coats the inner side of the S Oe Zr ae oe LZ display end of a cathode ray tube see oe 4 2 AS Aa illustration Electron beams emanate from T electron guns which are finely pointed High voltage deflection grid gun heated cathodes placed in close proximity Spey eee a Aeaee to a positively charged annular plate called a grid The electrostatic force imposed by the grid pulls rays of energized electrons Griq Electron guns i Red Blue Green R G B signals Figure 17 CRT deflection system Copyright Digilent Inc Page 10 17 Doc 502 134 Nexys2 Reference Manual KX Digilent www digilentinc com from the cathodes and those rays are fed by the current that flows into the cathodes These particle rays are initially accelerated towards the grid but they soon fall under the influence of the much larger electrostatic force that results from the entire phosphor coated display surface of the CRT being charged to 20kV or more The rays are focused to a fine beam as they pass through the center of the grids and then they accelerate to impact on the phosphor coated display surface The phosphor surface glows brightly at the impact point and it continues to glow for several hundred microseconds after the beam is removed The larger the current fed into the cathode the brighter the phosphor will glow Between the grid and the display surface the beam p
27. ly configured For further information on uu i i using Adept please see the Adept documentation tyr vi LEE a LEN d available at the Digilent website ans meee rs The Nexys2 board can also be programmed using Xilinx s IMPACT software by connecting a suitable programming cable to the JTAG header Digilent s JTAG3 cable or any other Xilinx cable may be used w AE cad B ime A demonstration configuration is loaded into the E Platform Flash on the Nexys2 board during DIGILENT manufacturing That configuration also available oy A am on the Digilent webpage can be used to check all of the devices and circuits on the Nexys2 board Clocks The Nexys2 board includes a 50MHz oscillator and a socket for a second oscillator Clock signals from the oscillators connect to global clock input pins on the FPGA so they can drive the clock synthesizer blocks available in FPGA The clock synthesizers called DLLs or delay locked loops provide clock management capabilities that include doubling or quadrupling the input frequency dividing the input frequency by any integer multiple and defining precise phase and delay relationships between various clock signals B8 Spartan 3E FPGA U9 User I O Figure 6 Nexys2 clocks The Nexys2 board includes several input devices output devices and data ports allowing many designs to be implemented without the need for any other components Eopyright 2ujiz mate on s
28. om the PC via port BTNR the USB cable DENE LED Digilent s freely available PC based Adept software can be used to configure the FPGA Figure 4 Nexys2 programming circuits and Platform Flash with any suitable file stored on the computer Adept uses the USB cable to transfer a selected bit file from the PC to the FPGA or Platform Flash ROM After the FPGA is configured it will remain so until it is reset by a power cycle event or by the FPGA reset button BTNR being pressed The Platform Flash ROM will retain a bit file until it is reprogrammed regardless of power cycle events To program the Nexys2 board using Adept attach the USB cable to the board if USB power will not be used attach a suitable power supply to the power jack or battery connector on the board and set the power switch to wall or bat Start the Adept software and wait for the FPGA and the Platform Flash ROM to be recognized Use the browse function to associate the desired bit file with the FPGA and or the desired mcs file with the Platform Flash ROM Right click on the device to be programmed and select the program function The configuration file will be sent to the FPGA or Platform Flash and the software will indicate whether programming was successful The configuration Copyright Digilent Inc Page 3 17 Doc 502 134 Nexys2 Reference Manual A Digilent www digilentinc com done LED will illuminate after the FPGA has been successful
29. ontroller must drive the cathodes with the correct pattern when the corresponding anode signal is driven To illustrate the process if ANO is asserted while CB and CC are asserted then a 1 will be displayed in digit position 1 Then if AN1 is asserted while CA CB and CC are asserted then a 7 will be displayed in digit position 2 If ANO and CB CC are driven for 4ms and then A1 and CA CB CC are driven for 4ms in an endless succession the display will show 17 in the first two digits An example timing diagram for a four digit controller is provided Copyright Digilent Inc Refresh period ims to 16ms Digit period Refresh 4 AN1 AN2 ne AN3 w i AN4 Cathodes Figure 10 Seven segment display timing diagram Page 6 17 Doc 502 134 Nexys2 Reference Manual A Digilent www digilentinc com USB Port The Nexys2 includes a high speed USB2 port based on a Cypress CY7C68013A USB Control 10 0 lt See schematic controller The USB port can be used to FIFO DATA 7 0 lt See schematic program the on board Xilinx devices to perform user data transfers at up to CYPRESS TMS gt Spartan 3E 38Mbytes sec and to provide power to the 68013A TCK gt FPGA board Programming is accomplished with TDO gt Digilent s free Adept Suite Software User TDI lt data transfers can also be accomplished USB ON using the Adept software or custom user software can
30. t A ninth LED is provided as a power on LED and a tenth LED indicates FPGA programming status Note that LEDs 4 7 have different pin assignments due to pinout differences between the 500 and the 1200 die Outputs Seven Segment Display The Nexys2 board contains a four digit common anode seven segment LED display Each of the four digits is composed of seven segments arranged in a figure 8 pattern with an LED embedded in each segment Segment LEDs can be individually illuminated so any one of 128 patterns can be displayed on a digit by illuminating certain LED segments and leaving the others dark Of these 128 possible patterns the ten corresponding to the decimal digits are the most useful Copyright Digilent Inc Page 5 17 Doc 502 134 Nexys2 Reference Manual KX Digilent www digilentinc com The anodes of the seven LEDs forming each digit are tied together into one common anode circuit node but the LED cathodes remain separate The common anode signals are available as four digit enable input signals to the 4 digit display The cathodes of similar segments on all four displays are connected into seven circuit nodes labeled CA through CG so for example the four D cathodes from the four digits are grouped together into a single circuit node called CD These seven cathode signals are available as inputs to the 4 digit display This signal connection scheme creates a multiplexed display where the cathode s
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