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GPIB-1014DP User Manual

1. SRQI amp SRQI IE REMC amp REMC IE CO amp CO IE LOKC amp LOKC IE ADSC amp ADSC IE National Instruments Corporation 4 15 GPIB 1014DP User Manual Register Bit Descriptions Bit Tw 6r 6w GPIB 1014DP User Manual Mnemonic SRQI SRQI IE Description Notes CPT CPT IE APT APT IE DET DET IE ERR ERR IE END RX END IE DEC DEC IE DO DO IE DI DI IE SRQI SRQI IE REMC REMC IE CO CO IE LOKC LOKC IE ADSC ADSC IE Reserved Bit Section Four Command Pass Through Bit Enable Interrupt on Command Pass Through Bit Address Pass Through Bit Enable Interrupt on Address Pass Through Bit Device Execute Trigger Bit Enable Interrupt on Device Execute Trigger Bit Error Bit Enable Interrupt on Error Bit End Received Bit Enable Interrupt on End Received Bit Device Clear Bit Enable Interrupt on Device Clear Bit Data Out Bit Enable Interrupt on Data Out Bit Data In Bit Enable Interrupt on Data In Bit Service Request Input Bit Enable Interrupt on Service Request Input Bit Remote Change Bit Enable Interrupt on Remote Change Bit Command Output Bit Enable Interrupt on Command Output Bit Lockout Change Bit Enable Interrupt on Lockout Change Bit Address Status Change Bit Enable Interrupt on Address Status Change Bit Write zero to this bit Service Request Input Bit Service Request Input Interrupt Enable Bit SRQI is set when CIC amp
2. HLDE HLDA Data Receiving Mode 0 0 Normal handshake 0 1 RFD holdoff on All Data 1 0 RFD holdoff on END 1 1 Continuous In Normal Handshake mode the local message rdy is generated when data is received from the GPIB When the received data is read from the DIR rdy is generated in Acceptor Not Ready State ANRS the RFD message is transmitted and the GPIB handshake continues In RFD Holdoff on All Data HLDA mode RFD is not sent true after data is received until the Finish Handshake FH auxiliary command is issued Unlike Normal Handshake mode the RFD HLDA mode does not generate the rdy message even if the received data is read through the DIR that is the GPIB RFD message is not generated In RFD Holdoff on End mode operation is the same as the RFD HLDA but only when the end of the data block EOS or END message is detected that is the END message is received or if REOS is set the EOS character received Handshake holdoff is released by the FH auxiliary command In continuous mode the rdy message is generated when in ANRS until the end of the data block is detected A Holdoff is generated at the end of a data block The FH auxiliary command must be issued to release the Holdoff The continuous mode is useful for monitoring the data block transfer without actually participating in the transfer no data reception In continuous mode the DI bit ISR1 0 r is not set by the reception of a data byte 4 42 National Ins
3. The address space required by the GPIB 1014DP consists of one block of 32 consecutive byte addresses The GPIB 1014DP responds only to AM codes that indicate short 16 bit addressing See Access Mode previously in this section The GPIB 1014DP decodes the 11 most significant address bits A05 through A15 as the base address Address line A04 selects between Port A A05 0 and Port B A05 1 The Talker Listener Controller TLC of each port internally decodes the Register Select signals which are address bits AO1 through A03 The GPIB 1014DP base address is selected with the jumper array labeled W4 on the board There is one jumper for each of the address lines A15 through A5 Place the jumper on the side labeled 0 to select a logical zero for the corresponding address bit Place the jumper on the side labeled 1 to select a logical one Figure 3 3 shows the configuration for base address default setting 1000 hex National Instruments Corporation 3 3 GPIB 1014DP User Manual Configuration and Installation Section Three Figure 3 3 Configuration for VMEbus Base Address 1000 hex default setting VMEbus Interrupt Configuration The GPIB 1014DP contains circuitry that permits each port to request service by driving one of the VMEbus interrupt request lines Each GPIB port responds to an interrupt acknowledge cycle of correct priority by providing an 8 bit vector status byte that
4. 0 Clear Parallel Poll Flag 0 Set Parallel Poll Flag Take Control Asynchronously Pulsed Take Control Synchronously Take Control Synchronously on End continues GPIB 1014DP User Manual 4 30 National Instruments Corporation Section Four Register Descriptions Table 4 4 Auxiliary Command Summary continued Function Code COM4 COM0 4321 0 Hex Code Auxiliary Command Go To Standby Listen Listen in Continuous Mode Local Unlisten 11101 Execute Parallel Poll Set IFC 11110 10110 Clear IFC Set REN Clear REN 10100 Disable System Control CNT 2 0 set to 000 binary Represents all eight bits of the Auxiliary Mode Register National Instruments Corporation 4 31 GPIB 1014DP User Manual Register Descriptions Section Four Table 4 5 shows the functions that are executed when the AUXMR Control Code CNT 2 0 is loaded with 000 binary and the Command Code COM 4 0 is loaded Table 4 5 Auxiliary Commands Detailed Description Command Code COM4 COM0 43210 Description Immediate Execute Pon This command generates a local pon message that places the following GPIB interface functions into these idle states AIDS Acceptor Idle State CIDS Controller Idle State LIDS Listener Idle State LOCS Local State LPIS Listener Primary Idle State NPRS Negative Poll Response State PPIS Parallel Poll Idle State PUCS Parallel Poll to Unaddressed to Configure State SIDS Source Idle State SIIS
5. 1 0000 AVX SATOSEG73ZAA CAP 047UF 50V 80 20 CER AX 56 c34 715079 01 1 0000 AVX SA105E4732AA CAP OG7UF SOV 80 20 CER AX 57 C35 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 58 c36 715079 01 1 0000 AVX SA105E4732AA CAP O47UF 50V 80 20 CER AX 59 37 715079 01 1 0000 AVX SA105E473ZAA CAP 047UF 50V 80 20 CER AX 60 C38 715079 01 1 0900 AVX SA105E4732AA CAP O47UF 50V 80 20 CER AX amp 1 C39 715079 01 1 0000 AVX SA105E4732AA CAP O47UF 50V 80 20 CER AX 62 C40 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 63 c41 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20X CER AX 64 cuz 715079 01 1 0000 l AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 65 c43 715079 01 1 0000 AVX SA105E4732AA CAP O47UF 50V 80 20 CER AX 66 chh 715079 01 1 0000 AVX SATOSEZZ3ZAA CAP 047UF 50V 80 20 CER AX 67 C45 715079 01 1 0000 AVX SA105E4732AA CAP OG7UF 50V 80 20 CER AX 68 246 715079 01 1 0000 AVX SA105E4732AA CAP OS7UF 50V 80 20 CER AX 69 C47 715079 01 1 0000 AVX SA105E4732AA CAP O47UF 50V 80 20 CER AX 70 C48 715034 01 1 0000 CMO amp FD121J08 CAP 120PF 100v 52 MICA ROL 71 301 730001 01 1 0000 NSC 1N4148 DIODE 1N4 148 SWITCHING 72 GPIB 1014DP User Manual B4 National Instruments Corporation Appendix B i Parts List and Schematic Diagrams RE e e e dede e dede Ie e Ae E eee eode RRR ERE e je e e e EA dede cle Ae De de dee DE IE eee e ie ede e edere de e
6. Acceptor Not Ready State Affirmative Poll Response State Address Pass Through Bit Enable Interrupt on Address Pass Through Bit Address Register Select Bit Address Strobe Attention Attention Bit Auxiliary Mode Register Auxiliary Register A Auxiliary Register B Auxiliary Register E Acceptor Wait for New Cycle State Bus Busy Bus Clear Bus Error Bus Grant In Lines Bus Grant Out Lines Binary Bit Block Transfer Bus Request Lines F 2 National Instruments Corporation Appendix F Mnemonic Type C C F CACS ST CADS ST CAWS ST CDOR R CDO 7 0 B CIC B CIDS ST CLK 3 0 B CNT B CNT 2 0 B CO B CO IE B COM 4 0 B CPPS ST CPT B CPT ENABLE B CPT IE B CPTR R CPT 7 0 B CPWS ST CS LS CSBS ST CSHS ST CSNS ST CSRS ST CSWS ST CTRS ST D D 00 07 VBS D08 O VBO D 16 31 VBS DAB RM DAC RM dacr LM DAV RM DC F DCAS ST DCIS ST DCL RM DEC B DEC IE B DEC RX B DEN LS DET B National Instruments Corporation Mnemonics Key Definition Controller Controller Active State C function Controller Addressed State Controller Active Wait State Control Data Out Register Control Data Out Bits 7 through 0 Controller In Charge Bit Controller Idle State Clock Bits 3 through 0 Continue Bit Control Code Bits 2 through 0 Command Out Enable Interrupt on Command Output Bit Command Code Bits 4 through 0 Controller Parallel Poll State Command Pass Through Bit Command Pass Through Enable
7. DI DO ERR ENDRX CO DT1 DL1 NATN MODE1 TRM ICR PPR AUXRA AUXRB AUXRE IEPON FH SEOI GTS TCA TCS TCSE LTN LTNC LUN SIFC CIFC SREN CREN TCT UNL UNT SELO SEL1 MA SC National Instruments Corporation C 3 001 octal 002 004 020 010 0100 0 40 0100 001 060 040 0140 0200 0240 0300 000 003 006 020 021 022 032 023 033 034 036 026 037 027 011 077 0137 0200 011 Sample Programs ISR1 Bits Data in Data out Error END received ISR2 Bits Command out ADR Bits Disable Talker Disable Listener ADSR Bits Not ATN ADMR Bits Address Mode 1 GPIB 1014DP functions for T R2 and T R3 AUXMR Hidden Registers Internal Counter Register Parallel Poll Register Auxiliary Register A Auxiliary Register B Auxiliary Register E AUXMR Commands Immediate execute power on Finish release handshake Send END Go to standby Take control asynchronously Take control synchronously Take control synchronously on END Listen Listen continuously Unlisten Set IFC Clear IFC Set REN Clear REN GPIB Commands Take control Universal unlisten Universal untalk User Specified Constants Select ADRO Select ADR1 GPIB address of GPIB 1014DP System Controller set to 0 if not System Controller GPIB 1014DP User Manual Sample Programs Appendix C Program Variables Buffers
8. To achieve the high data transfer rate that the GPIB was designed for the physical distance between devices and the number of devices on the bus are limited The following restrictions are typical e A maximum separation of four meters between any two devices and an average separation of two meters over the entire bus e A maximum total cable length of 20 m e No more than 15 devices connected to each bus with at least two thirds powered on Bus extenders are available from National Instruments and other manufacturers for use when these limits must be exceeded GPIB 1014DP User Manual E 6 National Instruments Corporation Appendix E Operation of the GPIB Related Document For more information on topics covered in this section consult the following manuals e ANSI IEEE Std 488 1978 IEEE Standard Digital Interface for Programmable Instrumentation e ANSI IEEE Std 488 1 1987 IEEE Standard Digital Interface for Programmable Instrumentation e ANSI IEEE Std 488 2 1987 IEEE Standard Codes Formats Protocols and Common Commands National Instruments Corporation E 7 GPIB 1014DP User Manual Appendix F Mnemonics Key This appendix contains a mnemonics key that defines the mnemonics abbreviations used throughout this manual for functions remote messages local messages states bits registers integrated circuits system functions and VMEbus operations and signals The mnemonic types in the key that follows are
9. AUXRE Other registers are configured as described The GPIB 1014DP interface functions are reset to idle and are enabled C 5 GPIB 1014DP User Manual Sample Programs Appendix C 68000 Code Comments INIT movb IEPON AUXMR Initialize and Enable TLC Functions movb 0 IMR1 L Disable TLC interrupts movb 0 IMR2 L isto ISR1 L Clear status bits by reading registers isto ISR2 L movb MODE1 TRM ADMR L Set address mode Talker Listener inactive and proper T R signal mode movb MA SEL0 ADR L Set GPIB address mode 1 primary only with Talker Listener enabled movb DT1 DL1 SEL1 ADR L Disable secondary address recognition movb ICR 8 AUXMR L Set clock divider for 8MHz low speed rts GPIB 1014DP User Manual C 6 National Instruments Corporation Appendix C 68000 Code Sample Programs INTERFACE CLEAR IFC Summary Initialize the interface function of other GPIB devices Assumptions on entry GPIB 1014DP has been initialized Actions Assert GPIB IFC Wait at least 100 microseconds Unassert IFC Status on return GPIB 1014DP is Active Controller Interface functions of other GPIB devices are reset to their idle states Comments IFC1 National Instruments Corporation link a6 4 movl d1 a6 4 movb SIFC AUXMR movb 50 d1 subb 1 d1 bne IFC1 movb CIFC AUXMR movl a6 4 d1 unlk a6 rts Link Save di Set the IFC signal W
10. Bus Slave Compliance Levels D08 O A16 ADO Interrupter Compliance Levels D08 O ROAK Il through I7 National Instruments Corporation 8 bit data path to TLC Responds to 16 bit short I O addresses when specified on the address modifier lines Accommodates Address Only cycles Provides an 8 bit status ID byte on DOO through D07 Releases its interrupt request line when the interrupt handler acknowledges the interrupt Full support of all seven interrupt priority levels and interrupt acknowledge daisy chain 2 13 GPIB 1014DP User Manual Section Three Configuration and Installation This section describes the configuration and installation of the GPIB 1014DP Configuration Before installing the GPIB 1014DP in the VMEbus backplane the following options must be configured with hardware jumpers or switches that are located on the GPIB 1014DP interface board Access Mode W2 VMEbus Base Address W4 VMEbus Interrupts VMEbus Interrupt Priority Code U27 VMEbus Interrupt Line Port A W1 and Port B W3 Interrupt Status ID Vector Port A U45 and Port B U34 National Instruments Corporation 3 1 GPIB 1014DP User Manual Configuration and Installation Section Three Figure 3 1 shows the locations of the GPIB 1014DP configuration jumpers and switches VMEbus Interrupt Priority Code Selection F245 7 Access E Feo Mode Selection F38 mi m 2 db F74 G r HEr o DEST EFE
11. Control Data Out CDOR Interrupt Status 1 ISR1 Interrupt Mask 1 IMR Interrupt Status 2 ISR2 Interrupt Mask 2 IMR2 Serial Poll Status SPSR Serial Poll Mode SPMR Address Status ADSR Address Mode ADMR Command Pass Through CPTR Auxiliary Mode AUXMR Address 0 ADRO Address ADR Address 1 ADRI R W R W R W R W R W R W R W R W End of String EOSR National Instruments Corporation 2 3 GPIB 1014DP User Manual General Description Section Two VMEbus Slave Data As discussed previously the GPIB 1014DP can function as a VMEbus slave decoding memory addresses and commands from a VMEbus master It is designed to accommodate address pipelining as well as Address Only ADO cycles All data is transferred to and from the VMEbus with lines DOO through D07 In VMEbus terminology the slave module of the board is designated as A16 D08 0 The board does not implement Unaligned Transfer UAT Block Transfer BLT and Read Modify Write RMW cycles Interrupter Interrupt events that originate from each TLC are as follows e GPIB Data In DI e GPIB Data Out DO END message received END RX e GPIB Command Out CO Remote mode change REMC e GPIB handshake error ERR e Lockout change LOKC Address Status Change ADSC e Secondary Address received APT Service Request received SRQI Trigger command received DET e Device Clear received DEC RX e Unrecognized Comma
12. SRQ amp RQS amp DAV becomes true SRQI is cleared by pon Read ISR2 Notes CIC SRQ RQS DAV GPIB Controller In Charge GPIB Service Request message GPIB Request Service message GPIB Data Valid message 4 16 National Instruments Corporation Section Four Bit 5r Sw 4r 4w 3r 3w Mnemonic LOK DMAO REM DMAI CO CO IE Register Bit Descriptions Description pon power on reset Read ISR2 Bitis cleared immediately after it is read The SRQI bit indicates that a GPIB Service Request SRQ message has been received while the TLC Controller function is active CIC 1 Lockout Bit LOK is used along with the REM bit to indicate the status of the TLC GPIB Remote Local RL function If set the LOK bit indicates that the TLC is in Local With Lockout State LWLS or Remote With Lockout State RWLS LOK is a non interrupt bit DMA Out Enable Bit The DMA feature is not implemented Do not set this bit Remote Bit This bit is true whenever the TLC GPIB RL function is in one of two states Remote State REMS or Remote With Lockout State RWLS The TLC RL function enters one of these states when the System Controller has asserted the Remote Enable line REN and the Controller In Charge addresses the TLC as a Listener DMA Input Enable Bit The DMA feature is not implemented Do not set this bit Command Out Bit Command Out Interrupt Enable Bit CO is set when CACS a
13. Send END or EOS Dual primary addressing Complete Extended Talker capability Basic Extended Talker Serial Poll Talk Only mode Unaddressed on MSA LPAS Send END or EOS Dual primary addressing continues 2 10 National Instruments Corporation Section Two General Description Table 2 3 GPIB 1014DP IEEE 488 Interface Capabilities continued Complete Listener capability Basic Listener Listen Only mode Unaddressed on MTA Detect END or EOS Dual extended addressing with software assist Complete Extended Listener capability Basic Listener Listen Only mode Unaddressed on MSA TPAS Detect END or EOS Dual extended addressing with software assist Complete Remote Local capability with software interpretation Remote Parallel Poll configuration Local Parallel Poll configuration with software assist Complete Device Clear capability with software interpretation Complete Device Trigger capability with software interpretation Complete Service Request capability continues National Instruments Corporation 2 11 GPIB 1014DP User Manual General Description Section Two Table 2 3 GPIB 1014DP IEEE 488 Interface Capabilities continued Complete Controller capability System Controller Send IFC and take charge Send REN Respond to SRQ Send interface messages Receive control Pass control Pass Control to Self Parallel Poll Take control synchronously Tri state bus drivers with automatic switch to
14. becomes true DO is cleared by Read ISR1 TACS SGNS Notes TACS GPIB Talker Active State SGNS GPIB Source Generate State Read ISR1 Bitis cleared immediately after it is read The DO bit indicates that the TLC is ready to accept another data byte from the VMEbus for transmission onto the GPIB when the TLC is the GPIB Talker The DO bit is cleared when a byte is written to the CDOR and also when the TLC ceases to be the Active Talker Data In Bit Data In Interrupt Enable Bit DI is set by LACS amp ACDS amp Continuous Mode National Instruments Corporation 4 13 GPIB 1014DP User Manual Register Bit Descriptions Bit Mnemonic GPIB 1014DP User Manual Section Four Description DI is cleared by pon Read ISR1 Finish Handshake amp Holdoff Mode Read DIR Notes LACS GPIB Listener Active State ACDS GPIB Accept Data State Continuous Mode Listen In Continuous Mode auxiliary command in effect pon power on reset Read ISRI Bit is cleared immediately after it is read Finish Handshake Finish Handshake auxiliary command issued Holdoff Mode RED holdoff state Read DIR Read Data In Register The DI bit indicates that the TLC as a GPIB Listener has accepted a data byte from the GPIB Talker 4 14 National Instruments Corporation Section Four Register Bit Descriptions Interrupt Status Register 2 ISR2 VMEbus Address Base Address 5 hex Port A Base Address 15 hex
15. compatible with VMEbus systems Compare the signals listed in Table 3 1 to those used by the VMEbus system in which the GPIB 1014DP will be installed to ensure that the GPIB 1014DP provides all the necessary signals needed by the VMEbus system and vice versa Table 3 1 GPIB 1014DP Pin Assignment on VMEbus Connector P1 Signal Used Signal Not Used Signal Used Signal Not Used Al GND AS GND IACK IACKIN IACKOUT AM4 A07 A06 A05 A04 A03 A02 A01 5V continues GPIB 1014DP User Manual 3 8 National Instruments Corporation Section Three Configuration and Installation Table 3 1 GPIB 1014DP Pin Assignment on VMEbus Connector P1 continued Signal Used Signal Not Used Signal Used Signal Not Used Bl BBSY BCLR ACFAIL BGOIN BGOOUT SERCLK BGIIN SERDAT BGIOUT BG2IN BG20UT BG3IN BG30UT BRO BR1 BR2 BR3 5V STDBY DIS GND SYSFAIL BERR SYSRESET LWORD AMS National Instruments Corporation 3 9 GPIB 1014DP User Manual Configuration and Installation Section Three Table 3 2 GPIB 1014DP Pin Assignment on VMEbus Connector P2 Signal Signal Signal Used Not Used Signal Used Not Used Notes MAIS MA13 MAII MAO9 MA07 MAOS User I O User I O DIOSB DIO6B DIO7B DIO8B RENB GND GND GND NNNNNNNNNNNNL C9 C9 C9 CO O9 O LI LI WW WwW continues GPIB 1014DP User Manual 3 10 National Instruments Corporation Section Three Configur
16. equipment and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used National Instruments products are NOT intended to be a substitute for any form of established process procedure or equipment used to monitor or safeguard human health and safety in medical or clinical treatment Preface Introduction to the GPIB 1014DP The GPIB 1014DP is a double height circuit board that interfaces the VMEbus to the IEEE 488 General Purpose Interface Bus GPIB providing two separate full function GPIB parts The GPIB 1014DP provides a means to implement VMEbus test and measurement systems with standard interconnecting cables Organization of the Manual This manual describes the mechanical and electrical aspects of the GPIB 1014DP and contains information concerning its operation and programming The manual is divided into the following sections and appendices e Section One General Information describes the GPIB 1014DP lists the contents of your GPIB 1014DP kit and explains how to unpack the GPIB 1014DP kit Section Two General Description contains the physical and electrical specifications for the GPIB 1014DP and describes the characteristics of key interface board components Section Three Configuration and Installation describes the steps needed to configure the GPIB 1014DP hardware and to verify that it is func
17. even cmdbuf 100 Command buffer for interface messages cmdct word 0 Number of commands to be sent datbuf 100 Data buffer for device dependent messages count word 0 Current number of commands transferred datct word 0 Number of data bytes to be sent cic byte O Controller In Charge flag non zero if CIC ola byte 0 Listen address passed to WRITE sre byte 0 REN flag zero to not set REN non zero to set REN tctadr byte 0 TCT address of new Active Controller vseoi byte 0 SEOI flag zero to not send non zero to send END message with last DSEND byte GPIB 1014DP User Manual C 4 National Instruments Corporation Appendix C National Instruments Corporation Sample Programs KKK KKK KK k k k k k k INITIALIZE INIT KKK KKK KK k k k k KKK Summary nitialize the GPIB 1014DP hardware Assumptions on entry User specified constants MA and SC have been initialized Mode 1 primary addressing is used Low speed timing is used Interrupts are not used Status byte will be set elsewhere Remote Parallel Poll configuration will be used Actions Pulse IEPON to put hardware in known reset state Disable interrupts and clear status Set hardware registers to desired values Status on return The following registers are cleared ISR1 2 IMR1 2 SPMR SPSR PPR AUXRA
18. 2 5 interrupter logic 6 3 to 6 4 programming considerations 5 7 to 5 8 INV Invert Bit 4 43 ISRI See Interrupt Status Register 1 ISR1 ISR2 See Interrupt Status Register 2 ISR2 ISS Individual Status Select Bit 4 43 J jumpers and switches interrupt status ID vector selection 3 6 to 3 7 parts locator diagram 3 2 for Supervisor or Non privileged access 3 3 VMEbus base address 3 4 VMEbus interrupt configuration 3 4 to 3 6 VMEbus interrupt line selection 3 4 to 3 5 VMEbus interrupt priority code selection 3 5 to 3 6 GPIB 1014DP User Manual 1 6 National Instruments Corporation Index L LA Listener Active Bit 4 22 lines See signals and lines Listen command codes for 4 31 description 4 35 Listen in Continuous Mode command codes for 4 31 description 4 35 LLO Local Lockout command 4 27 Local Unlisten command codes for 4 31 description 4 36 LOK Lockout Bit 4 17 LOKC Lockout Change Bit 4 18 LOKC IE Lockout Change Interrupt Enable Bit 4 18 lon Listen Only Bit 4 23 LPAS Listener Primary Addressed State Bit 4 21 M messages multiline interface command messages D 1 to D 3 types of E 1 uPD7210 interface registers illustration 4 5 MJMN Major Minor Bit 4 22 MLA My Listen Address command 4 27 mnemonics for registers alphabetical list with definitions F 1 to F 9 clues to understanding 4 3 MSA PPD My Secondary Address or Parallel Poll Disable command 4 27 MSA PPE My Seco
19. 4 44 Auxiliary Register E AUXRE 4 45 National Instruments Corporation LI GPIB 1014DP User Manual Index B base address VMEbus 3 3 to 3 4 BIN Binary Bit 4 41 bus signals See VMEbus C cabling 3 12 capability codes for GPIB 1014DP 2 10 to 2 12 CDO 7 0 Command Data Out Bits 7 through 0 4 8 CDOR See Command Data Out Register CDOR Chip Reset command codes for 4 30 description 4 32 to 4 33 CIC Controller In Charge Bit 4 21 Clear IFC command codes for 4 31 description 4 36 Clear Parallel Poll Flag command codes for 4 30 description 4 34 Clear REN command codes for 4 31 description 4 36 CLK 3 0 Clock Bits 3 through 0 4 38 clock and reset circuitry definition 2 10 operation 6 3 CNT 2 0 Control Code Bits 2 through 0 4 29 to 4 30 CO Command Out Bit 4 17 CO IE Command Out Interrupt Enable Bit 4 17 COMMAND CMD sample program C 18 Command Data Out Register CDOR 4 8 Command Pass Through Register CPTR 4 26 to 4 28 COMMAND SEND CSEND sample program C 17 commands auxiliary command summary detailed description 4 32 to 4 36 table of 4 30 to 4 31 commands or command messages E 1 multiline GPIB commands table D 2 to D 3 4 26 to 4 28 configuration interrupt status ID vector selection 3 6 to 3 7 jumpers and switches illustration 3 2 requirements E 6 Supervisor or Supervisor and User access 3 3 VMEbus base address 3 3 to 3 4 VMEbus interrupt 3 4 to 3
20. 6 GPIB 1014DP User Manual r2 National Instruments Corporation Index Controller function becoming controller in charge CIC and active controller 5 2 to 5 3 Controller In Charge CIC and System Controller E 2 going from active to idle 5 4 going from active to standby 5 3 going from standby to active 5 4 operation of E 1 to E 2 sending remote multiline messages commands 5 3 CPT Command Pass Through Bit 4 9 to 4 10 CPT 7 0 Command Pass Through Bits 7 through 0 4 26 CPT ENABLE Command Pass Through Enable Bit 4 44 CPT IE Command Pass Through Interrupt Enable Bit 4 9 to 4 10 CPTR See Command Pass Through Register CPTR D Data In Register DIR 4 7 data lines E 2 data or data messages E 1 DATA SEND DSEND sample program C 13 to C 14 data transfer features 2 5 DAV data valid signal E 3 DCL Device Clear command 4 27 DEC Device Clear Bit 4 12 DEC IE Device Clear Interrupt Enable Bit 4 12 DET Device Execute Trigger Bit 4 11 DET IE Device Execute Trigger Interrupt Enable Bit 4 11 DHDC DAC Holdoff on DCAS Bit 4 45 DHDT DAC Holdoff on DTAS Bit 4 45 DI Data In Bit 4 13 to 4 14 DI 7 0 Data In Bits 7 through 0 4 7 DI IE Data In Interrupt Enable Bit 4 13 to 4 14 DIR See Data In Register DIR Disable System Control command codes for 4 31 description 4 36 DL Disable Listener Bit 4 47 DLO Disable Listener 0 Bit 4 46 DL1 Disable Listener 1 Bit 4 48 DMAI DMA Input Enabl
21. 742410 01 2 0000 SCHR 21100 138 SCREW 2 5 X 10MM FLSTRHD ZPS 2 03 740000 01 4 0000 740000 01 NUT 2 56 HEX ZPS 3 04 zidiros t 2 0000 SCHR 21100 429 SCREW 2 5 X BMM RSD CSKHD ZPS 4 05 742412 01 2 0000 SCHR 21100 379 SCREW 2 5 X 11MM CAPTIVE NPS 5 06 745176 01 2 0000 SCHR 21100 662 SLEEVE 5 9 X 3 3 DIA SS 6 07 180188 01 2 0000 NI 180188 01 EMI SHIELD CONN CHAMP 7 08 180273 11 1 0000 PANEL 6U HT MOD GPIB 1014DP 8 09 189187 01 4 0000 NI 180187 01 JACKSOCKET CHAMP METRIC LONG 9 10 745100 01 4 0000 ZIER 741 ANGLE BKT 4 40 THD HOLE 10 11 740407 01 8 0000 740407 01 WASHER 4 LOCK INT TH SS 1 12 740912 01 4 0000 740912 01 SCREW 4 40x5 16 PNH SS 12 13 740406 01 4 0000 740406 01 WASHER 10 LOCK SPLIT 2PS 3 14 745096 01 2 0000 SCHR 20809 295 HANDLE 4HP GRAY 14 15 740001 01 4 0000 740001 01 NUT 4 40 HEX ZPS 15 16 745047 01 0 0000 LOCTITE 242 LOCTITE 16 17 742413 01 4 0000 SCHR 21100 140 SCREW CHEESE HD M2 5x8 2PS 17 18 760014 02 14 0000 AMP 531220 3 CONN MINI JUMP 2 POS SHORT 18 19 745108 01 4 0000 SCHR 60807 181 PWB HOLDER DIE CAST 19 20 180799 01 1 0000 NI 180799 01 LABEL LOGO NI 20 21 181058 01 1 0000 NIC 181058 01 LABEL GPIB 1034DP 21 22 740206 01 4 0000 740206 01 WASHER 2 FLAT NYLON 22 GPIB 1014DP User Manual B 2 National Instruments Corporation Appendix B Parts List and Schematic Diagrams AEE BE BEIE IE A IE IE IO IE E EE WE E E DE IE SELES o CR EERE RAERERRERSERERERERERE REC CR ERE EN RA
22. B Base address B Base address D Base address D Base address F Base address 1H Base address 1H Base address 1H Base address 1D Base address 1D Base address 1H Write only Write only Write only Read only Write only Address Register 1 Read only End Of String Register Base address F Base address 1H Write only Register Sizes All program registers on the GPIB 1014DP are 8 bit registers Register Description Format The remainder of this section discusses each of the GPIB 1014DP registers in the order shown in Table 4 1 Each register group is introduced followed by a detailed bit description of each register The individual register description gives the address type word size and bit map of the register followed by a description of each bit The register bit map shows a diagram of the register with the most significant bit bit 7 shown on the left and the least significant bit bit 0 shown on the right A rectangle is used to represent each bit Each bit is labeled with a name inside its rectangle An asterisk after the bit name indicates that the signal is active low An asterisk is equivalent to an overbar In many of the registers several bits are labeled with an X indicating don t care bits When a register is read these bits may appear set or cleared but should be ignored because they have no significance When a register is written to these bit locations should be
23. BIT BIN COUNTER 113 u31 700234 01 1 0000 TI SN74S02N 1C S02 2 INP_NOR 114 u32 700222 01 1 0000 TI SN74S00N 1C S00 2 INP NAND 115 u33 700013 01 1 0000 Tl SN74LS74AN IC LS74 FLIP FLOP 116 U34 720004 01 1 0000 AMP 2 435668 8 DIPSWITCH 8 POS SPST 117 u35 700643 01 1 0000 SIG N74F244N IC F244 OCTAL BUFER LINE DRIVE 118 u36 700200 01 1 0000 NEC UPD7210 1C 7210 GP1B INTFC CNTRLR 119 u37 760200 01 1 0000 NEC UPD7210 1C 7210 GPIB INTFC CNTRLR 120 138 700540 01 1 0000 SIG N74F85N i IC F85 4 BIT MAGNITUDE COMP 121 2139 700706 01 1 0000 TI SN74FZGN IC F74 FLIP FLOP 122 GPIB 1 014DP User Manual B 6 National Instruments Corporation Appendix B B E E E E T A e T E E E E TER CIN E E SC C de Ree Red ede de ede ode RR d e eee de dee deed dede de dede Ye e Re diel CR I IURE RR rere CET I CREW RON OR CEA ENERO Re ER ITEM NO NI PART NO u40 uam u42 u43 Usa U4S u46 u47 u48 woi wo2 W03 wos National Instruments Corporation 700182 01 700905 01 700706 01 700706 01 700287 01 720004 01 700643 01 700706 01 700004 01 760144 72 760013 03 760144 72 760013 11 QTY REQD 1 0000 1 0000 1 0000 1 0000 1 0000 1 0000 1 0000 1 0000 1 0000 0 1944 1 0000 0 1944 3 0000 MFR TI DAL SEMI TI TI TI AMP SIG TI TI SAMT BERG SAMT BERG MFR PART SN74LS21N DS1013M 25 SN7GF7QN SN74F74N SN74LS19AN 2 435668 8 N74F24
24. Bit Enable Interrupt on Command Pass Through Bit Command Pass Through Register Command Pass Through Bits 7 through 0 Controller Parallel Poll Wait State Chip Select Signal Controller Standby State Controller Standby Hold State Controller Service Not Requested State Controller Service Requested State Controller Synchronous Wait State Controller Transfer State C function Data Lines 0 through 7 Single Odd Byte Transfers Data Lines 16 through 31 Data Byte Data Accepted DAC holdoff release Data Valid Device Clear Device Clear Active State Device Clear Idle State Device Clear Device Clear Bit Enable Interrupt on Device Clear Bit Device Clear Received Data Enable Device Execute Trigger Bit F 3 GPIB 1014P User Manual Mnemonics Key Mnemonic Type DET IE B DHDC B DHDT B DI B DI 7 0 B DI IE B DIO 1 8 GS DIR R DL B DLO B DLI B DMA SF DMAI B DMAO B DO B DO IE B DSO VBS DT F DT B DTO B DTI B DTACK VBS DTAS ST DTIS ST E END RM END IE B END RX B EOI B EOI RM EOI OE LM EOS RM EOS 7 0 B EOSR R ERR B ERR RM ERR IE B EV LS F FH LM G GET RM GND VBS GPIB 1014P User Manual Appendix F Definition Enable Interrupt on Device Execute Trigger Bit DAC Holdoff on DCAS Data Accepted Holdoff on Device Trigger Active State Bit Data In Bit Data In Bits 7 through 0 Enable Interrupt on Data In Bit GPIB Data Lines 1 through 8 Data In Register Disable Listener Bit Disable Listener
25. Clearing lon does not by itself take the TLC out of Listener Active state LACS It is also necessary to execute the Chip Reset or Immediate Execute pon auxiliary command Transmit Receive Mode Bits 1 through 0 TRMI and TRMO control the function of the TLC T R2 and T R3 output pins in the following manner TRM1 TRMO T R2 T R3 0 0 EOI OE TRIG 0 1 CIC TRIG 1 0 CIC EOI OE 1 1 CIC PE National Instruments Corporation 4 23 GPIB 1014DP User Manual Register Bit Descriptions Bit Mnemonic 3 2w 0 1 0w ADM I 0 GPIB 1014DP User Manual Section Four Description Key EOI OE GPIB EOI signal output enable CIC Controller In Charge TRIG Trigger PE Pull up Enable For proper operation set both TRM1 and TRMO which selects T R2 CIC and T R3 PE Reserved Bits Write zeros to these bits Address Mode Bits 1 through 0 These bits state the addressing mode currently in effect that is the manner in which the information in ADRO and ADRI is interpreted see Address Register 0 and Address Register 1 later in this section If both bits are zero then the TLC does not respond to GPIB address commands Instead the ton and lon bits are used to program the Talker and Listener functions respectively The ton and lon bits must be cleared if mode 1 2 or 3 addressing is selected and the AMD 1 0 bits must be cleared if either of the bits ton or lon are set Mode ADMI ADMO Title 0 0 0 ton lon 1 0 1 Normal dual addressi
26. GPIB interface functions for communicating with other GPIB devices and device functions for communicating with the central processor and memory Expressed in VMEbus terminology the GPIB 1014DP is an interface to the outside world Figure 2 1 and Figure 2 2 show typical applications for the GPIB 1014DP In Figure 2 1 the GPIB 1014DP is used to interface an assortment of test instruments to a VMEbus computer system which then functions as an intelligent System Controller This is the traditional role of the GPIB In Figure 2 2 the GPIB 1014DP is used along with other National Instruments interface boards to connect a VMEbus computer to other processors in order to transfer information or to perform other communication functions Since the GPIB 1014DP provides true independent GPIB interfaces a typical application might be a combination of the two Port A could be used to interface the VMEbus computer system to an assortment of test and measurement instruments while Port B is used to link the VMEbus system to other computer systems GPIB 1014DP User Manual 2 6 National Instruments Corporation Section Two VMEbus Computer with GPIB 1014DP Able to Talk Listen and Control Device C Digital Voltmeter Able to Talk and Listen General Description Device A Frequency Counter Able to Talk Device B Printer Able to Listen Data Lines DIO1 DIO8 Handshake Lines DAV Data Valid NRFD Not Ready for Data NDA
27. MS 53 02 MS 53 02 Austin TX 78730 5039 512 794 5678
28. Oo B A W D GPIB 1014DP User Manual B 13 O National Instruments Corporation Appendix C Sample Programs This appendix contains listings of routines in 68000 assembly language code that implement the essential elements of these major utility functions The example code is shown for Port A only Initialize the GPIB 1014DP interface INIT Initialize the interface functions of the GPIB devices IFC Set or clear the GPIB REN line REN Accept data bytes from a Talker RCV Address Talker and read device dependent messages READ Send data bytes to Listeners DSEND Address Listener and write device dependent messages WRITE Send command bytes to Listeners CSEND Write interface messages CMD Pass GPIB control to another device PASSC Assumptions regarding the state of the GPIB 1014DP appear at the beginning of each routine and must be adhered to for proper error free operation The following characteristics of the code must be considered The GPIB 1014DP base address is FF1000 hex Normal non extended GPIB addressing is used Time out on subroutine calls is not implemented Register values are not saved on subroutine calls Program interrupt is not used status checking is by register polling Constants and variables listed in the User Specified Constants section of the listings must be initialized to correct values In operands containing expressions is used in place of logical OR for convenie
29. Port B Attributes Read Only Bits are cleared when read Interrupt Mask Register 2 IMR2 VMEbus Address Base Address 5 hex Port A Base Address 15 hex Port B Attributes Write Only 7 6 5 4 3 2 1 0 R ADSC 0 Skate DMAO_ _DMAI CONE_ TOKCIE REMC IE ADSC TE W ISR2 consists of six interrupt status bits and two TLC internal status bits IMR2 consists of five interrupt enable bits and two TLC internal control bits If the Interrupt Enable bit is true when the corresponding status condition or event occurs a hardware interrupt request is generated Bits in ISR2 are set and cleared regardless of the status of the bits in IMR2 If a condition occurs which requires the TLC to set or clear a bit or bits in ISR2 at the same time ISR2 is being read the TLC holds off setting or clearing the bit or bits until the read is finished Bit Mnemonic Description Tr INT Interrupt Bit This bit is the logical OR of all the enabled interrupt status bits in both ISRI and ISR2 each one ANDed with its interrupt enable bit refer below There is no corresponding mask bit for INT If the INT 1 the INT output pin of the TLC signal GPIB IR is asserted Note Program the INT output pin of the TLC to be active high see description of AUXRB INT is set by CPT amp CPT IE APT amp APT IE DET amp DET IE ERR amp ERR IE END RX amp END IE DEC amp DEC IE DO amp DO IE DI amp DI IE
30. TPAS bit in the ADSR is set If the TLC receives its secondary GPIB talk address before receiving another GPIB Primary Command Group PCG message that is not its MTA the TA bit in the ADSR the ADSC bit in the ISR2 and the DO bit in the ISR1 are set If the TLC has received its primary GPIB listen address the Listener Primary Addressed State LPAS bit in the ADSR is set If the TLC receives its secondary GPIB listen address before receiving another GPIB Primary Command Group PCG message that is not its MLA the LA bit in the ADSR is set the ADSC bit in ISR2 is set and the DI bit in ISR1 is set when the first GPIB data byte is received The Major Minor MJMN bit in the ADSR indicates whether the address status refers to the major or minor address Address Mode 3 Address Mode 3 like Address Mode 2 is used to implement Extended GPIB Talk and Listen address recognition However unlike Address Mode 2 Address Mode 3 provides for both major and minor primary addresses and your program must identify the secondary address by reading the CPTR Proper operation using Address Mode 3 is listed as follows 1 During initialization of the TLC enable Address Mode 3 and optionally set the APT IE bit in IMRI to enable an interrupt request on receipt of a secondary GPIB address Write the TLC major GPIB primary address to ADRO and the TLC minor GPIB primary address to ADRI 2 Receipt of the TLC major or minor primary GPIB Talk Address MTA or major
31. Take Control Synchronously on End command codes for 4 30 description 4 35 Talker Listener Controller TLC See also Controller function addressed implementation Address Mode 1 5 5 Address Mode 2 5 5 to 5 6 Address Mode 3 5 6 to 5 7 definition 2 10 GPIB interface 6 4 to 6 5 initialization of 5 1 interrupt events originating from 2 4 operation of E 1 to E 2 overview 5 5 programmed implementation 5 5 sending receiving messages 5 7 VMEbus slave addressing 2 2 to 2 3 National Instruments Corporation I 11 GPIB 1014DP User Manual Index TCT Take Control command 4 27 test and troubleshooting See troubleshooting test procedures theory of operation address decoding 6 2 clock and reset circuitry 6 3 GPIB interface 6 4 to 6 5 interrupter logic 6 3 to 6 4 test and troubleshooting 6 6 timing control logic 6 3 VMEbus interface 6 1 to 6 2 timing control logic 6 3 timing state machine definition 2 10 TLC See Talker Listener Controller TLC ton Talk Only Bit 4 23 TPAS Talker Primary Addressed State Bit 4 22 transceivers for GPIB 1014DP 2 2 TRI Three State Timing Bit 4 44 Trigger command codes for 4 30 description 4 33 TRM 1 0 Transmit Receive Mode Bits 1 through 0 4 23 to 4 25 troubleshooting test procedures hardware installation tests 7 2 to 7 3 interpreting test procedures 7 1 overview 6 6 7 1 verification of GPIB 1014DP before installation 3 11 U U Parallel Poll Unconfigure Bit
32. address data status and control lines used on the VMEbus plus other logic circuitry that converts internal signals to bus compatible signals Recognizes when the VMEbus master addresses one of the GPIB 1014DP registers and generates the appropriate strobe to effect the data transfer 2 9 GPIB 1014DP User Manual General Description e Clock and Reset Circuitry e Timing State Machine e Interrupter GPIB TLC NEC uPD7210 Section Two Monitors the VMEbus utility signals to generate the 8 MHZ clock used by the TLC and to detect System Reset Controls the timing of accesses to the GPIB 1014DP from the VMEbus Implements the correct VMEbus priority interrupt protocol allowing the GPIB 1014DP to request and respond to an interrupt acknowledge cycle All interrupt conditions are also detectable by polling Implements many of the GPIB interface functions either independently or with assistance of or interpretation by the controlling program Together with special transceivers the TLC forms the GPIB interface side of the GPIB 1014DP Table 2 3 lists the capabilities of the GPIB 1014DP in terms of the IEEE 488 standard codes Table 2 3 GPIB 1014DP IEEE 488 Interface Capabilities Complete Source Handshake capability GPIB 1014DP User Manual Complete Acceptor Handshake capability DAC and RFD Holdoff on certain events Complete Talker capability Basic Talker Serial Poll Talk Only mode Unaddressed on MLA
33. addressing extended mode TPAS 1 indicates that the secondary address being received as the next GPIB command message may represent the TLC extended secondary GPIB Talk address Listener Active Bit LA is set whenever the TLC has been addressed or programmed as a GPIB Listener that is the TLC is in the Listener Active State LACS or the Listener Addressed State LADS The TLC can be addressed to listen either by sending its own listen or extended listen address while it is Controller In Charge CIC or by receiving its listen address from an external CIC It can also be programmed to listen using the lon bit in the Address Mode Register ADMR If the TLC is addressed to Listen it is automatically unaddressed to Talk LA is cleared by pon or by issuing the Chip Reset auxiliary command Talker Active Bit TA is set whenever the TLC has been addressed or programmed as the GPIB Talker that is the TLC is in the Talker Active State TACS the Talker Addressed State TADS or the Serial Poll Active State SPAS The TLC can be addressed to talk either by sending its own talk or extended talk address while it is CIC or by receiving its talk address from an external CIC It can also be programmed to talk using the ton bit in the Address Mode Register ADMR If the TLC is addressed to talk it is automatically unaddressed to listen TA is cleared by pon or by issuing the Chip Reset auxiliary command Major Minor Bit The MJMN bit is us
34. e de RARA e e e e de ITEM NO NI PART NO QTY REQD MFR MFR PART PRODUCT DESCRIPTION J01 180168 01 1 0000 NI 180168 01 CONN CHAMP 24 RA 73 J02 180168 01 1 0000 NI 180168 01 CONN CHAMP 24 PIN DISASSEMBLED 74 P01 760208 96 1 0000 PAN 100 096 033 CONN DIN 3X32POS RTANG CLASSII 75 p02 760208 96 1 0000 PAN 100 096 033 CONN DIN 3X32POS RTANG CLASSII 76 RO1 711141 01 1 0000 RCO7GF8225 RES 78 2 1 44 5 CF 7 R02 711117 01 1 0000 AB 1104472 RESNET 9X4 7K 2 10 S1P 78 R03 711009 01 1 0000 MOUS 29AB250 1K RES 1K 1 4W 5 CF 79 RO4 711117 01 1 0000 AB 1104472 RESNET 9X4 7K 2 10 SIP 80 ROS 711141 01 1 0000 RCO7GF822J RES 8 2K 1 44 5X CF 81 ROG 711162 01 1 0000 7 AB RNK7320F RES 732 1 4W 1 82 R07 711117 01 1 0000 AB 1104472 RESNET 9X4 7K 2X 10 SIP 83 vol 700562 01 1 0000 TI SN74F245N IC F245 TRANSCEIVER 84 u02 700740 01 1 0000 TI SN74F20N 1C F20 DUAL 4INPUT NAND 85 u03 700646 01 1 0000 SIG N74F38N IC F38 QUAD 2 INPUT NAND 3 ST 86 U04 700176 01 1 0000 TI SN74LS240N 1C LS240 BUFFER DRIVER 87 UOS 700173 01 1 0000 AMD AM25LS2521PC IC L 2521 8 B1T EQUAL TO CMPTR 88 uo6 700490 01 1 0000 TI SN74ALS244AN IC ALS264 0CT BUF amp LINE DR 3 ST 89 u07 700173 01 1 0000 AMO AM25LS2521PC 1C LS2521 8 BIT EQUAL TO CMPTR 90 uos 700740 01 1 0000 TI SN74F20N IC F20 DUAL 4INPUT NAND 91 u09 700003 01 1 0000 TI SN74LSO4N IC LS04 INVERTER 92 410 700013 01 1 0000 TI SN74LS74AN iaia 93 u11 700106 01 1 0000 NS DS75160AN i 1C 75160 GPIB DATA BUS XCVR 94 u12 70
35. ola The data to be sent is placed in datbuf The variable datct contains the number of bytes to send Actions Set up cmdbuf and cmdct and call CMD to address the GPIB 1014DP as Talker to address the Listener and to unaddress all other devices Go to standby and unassert ATN Transfer the contents of datct to the dO register Load a0 register with the address of datbuf Call DSEND to write the data When the last byte has been sent take control Call CMD to unaddress all devices Status on return The GPIB 1014DP is Active Controller All GPIB devices are unaddressed C 15 GPIB 1014DP User Manual Sample Programs Appendix C 68000 Code Comments WRITE movw 4 cmdct L Put Untalk Unlisten MTA and OLA movb UNT cmdbuf L commands in the buffer movb UNL cmdbuf L 1 movb MA 100 cmdbuf L 2 movb ola cmdbuf L 3 bsr CMD Call CMD to address GPIB devices movb GTS AUXMR L Go to standby and drop ATN movw datct d0 Preset dO register with byte count movl datbuf a0 Preset a0 register with address of buffer bsr DSEND Source Handshake Data will write data WRITE1 btst DO ISR1 L Wait until last byte has been sent beq WRITE1 movb TCA AUXMR L Then take control subw 2 cmdct L Prepare to unaddress all Talkers and Listeners bsr CMD rts GPIB 1014DP User Manual C 16 National Instruments Corporation Appendix C
36. on RFD or DAC Trigger Note Trigger cannot be used with the GPIB 1014DP The Trigger command generates a high pulse on the TRIG pin T R3 pin when TRM1 0 of the TLC The Trigger command performs the same function as if the DET Device Trigger bit ISR1 5 r were set The DET bit is not set by issuing the Trigger command Return to Local rtl Return to Local rtl The two Return to Local commands implement the rtl message as defined by IEEE 488 When COM3 is zero the message is generated in the form of a pulse When COM3 is one the rtl command is set in the standard manner Send EOI SEOI The Send EOI command causes the GPIB End Or Identify EOD line to go true with the next byte transmitted The EOI line is then cleared upon completion of the Handshake for that byte The TLC recognizes the Send EOI command only if TA 1 that is the TLC is addressed as the GPIB Talker continues National Instruments Corporation 4 33 GPIB 1014DP User Manual Register Descriptions Section Four Table 4 5 Auxiliary Commands Detailed Description continues Command Code COM4 COM0 43210 Description Non Valid Secondary Command or Address The Non Valid command releases the GPIB DAC message held off by the Address Pass Through APT The TLC is permitted to operate as if an Other Secondary Address OSA message has been received Valid Secondary Command or Address The Valid command releases the GPIB DAC message held
37. open Collector drivers during Parallel Poll Each GPIB 1014DP port has complete Source and Acceptor Handshake capability The port can operate as a basic Talker or Extended Talker and can respond to a Serial Poll It can be placed in a Talk Only mode and it is unaddressed to talk when it receives its listen address The interface can operate as a basic Listener or Extended Listener It can be placed in a Listen Only mode and it is unaddressed to listen when it receives its talk address The port has full capabilities for requesting service from another Controller It can be placed in local mode but the interpretation of remote versus local mode is software dependent The interface has full Parallel Poll capability although local configuration requires software assistance It also has Device Clear and Trigger capability but the interpretation is software dependent All Controller functions as specified by the IEEE 488 standard are included in the GPIB 1014DP These include the capability to Be System Controller Initialize the interface Send Remote Enable Respond to Service Request Send multiline command messages Receive control Pass control Conduct a Parallel Poll Take control synchronously or asynchronously GPIB 1014DP User Manual 2 12 National Instruments Corporation Section Two General Description Table 2 4 indicates the GPIB 1014DP IEEE 1014 compliance levels Table 2 4 GPIB 1014DP IEEE 1014 Compliance Levels
38. or LPAS bit was set The GPIB DAC message to be sent true and the handshake to be finished Until a GPIB Primary Command Group PCG message is received that is as long as the subsequent messages are secondary addresses the APT bit is set and a DAC holdoff is in effect each time a GPIB secondary address is received In this way the GPIB CIC can address several devices having the same primary address without repeating the primary address each time If a PCG message is received before a secondary address is received the TPAS and LPAS bits are cleared Sending Receiving Messages When the GPIB port is a GPIB Talker or Listener data device dependent messages can be sent or received To send data wait until the port has been programmed or addressed to talk and the CDOR is empty When this occurs the DO bit in the ISR1 is set indicating that it is safe to write a byte to the CDOR The DO bit is set again once the byte has been received by all GPIB Listeners To receive data wait until the port has been programmed or addressed to listen and the DIR is full When this occurs the DI bit in the ISRI is set indicating that the GPIB Talker has written a byte to the DIR Once that byte has been read the DI bit will be set again when a new byte is received from the GPIB Talker Determining when the CDOR is empty or the DIR is full can be done by polling the ISR1 until the DO or DI status first appears or by allowing a program interrupt to o
39. read Send HLDA Restore d2 Restore d1 Unlink Return National Instruments Corporation Appendix C National Instruments Corporation Sample Programs KKK ko k KK READ Summary Called to read device dependent data messages when the GPIB 1014DP is Controller In Charge RCV is called when the GPIB 1014DP is Idle Controller Assumptions on entry GPIB 1014DP is Controller In Charge The Talker address is placed in first location of cmdbuf The variable cmdct is set to 1 The buffer datbuf is free to place incoming data The number of bytes to read is placed in datct Actions Set up cmdbuf and cmdct and call CMD to address the Talker and unaddress all other devices Program the GPIB 1014DP to listen Go to standby and unassert ATN Transfer the contents of datct to the dO register Load the a0 register with the address of datbuf Call RCV to receive the data Call CMD to unaddress all devices Program the GPIB 1014DP to unlisten Status on return GPIB 1014DP is Active Controller Acceptor handshake is held off at NRFD All GPIB devices are unaddressed C 11 GPIB 1014DP User Manual Sample Programs 68000 Code Appendix C Comments READ movb movb movb addw bsr movb movb movw movl bsr movb READ1 bne subw bsr movb rts cmdbuf L cmdbuf L 2 Put Untalk and Unlisten commands before UNT cmdbuf L UNL cmdbuf L 1 2 cmdct L CMD LTN AUX
40. 0 Bit Disable Listener Bit Direct Memory Access DMA Input Enable Bit DMA Out Enable Bit Data Out Bit Enable Interrupt on Data Out Bit Data Strobe Zero Device Trigger Disable Talker Bit Disable Talker 0 Bit Disable Talker 1 Bit Data Transfer Acknowledge Device Trigger Active State Device Trigger Idle State End Enable Interrupt on End Received Bit End Received Bit End or Identify Bit End or Identify GPIB EOI Signal Output Enable End of String End of String Bits 7 through 0 End of String Register Error Bit Error Enable Interrupt on Error Bit Enable Vector Finish Handshake Group Execute Trigger Ground F 4 National Instruments Corporation Appendix F Mnemonic Type GTL RM gts LM H HLDA B HLDE B I IA 1 3 LS IACK VBS IACKIN VBS IACKOUT VBS IB 1 3 LS ICR R IDTACK LS IDY RM IFC RM IMRI R IMR2 R INT B INTA LS INTB LS INV B IR LM IRQ VBS ISRI R ISR2 R ISS B ist LM L L F LA B LACS ST LADS ST LAG RM LD 0 7 LS LDTACK LS LE F LIDS ST LLO RM LMR B LOCS ST LOK B LOKC B LOKC IE B National Instruments Corporation Mnemonics Key Definition Go To Local Go to Standby Holdoff on All Bit Holdoff on End Bit Interrupt Priority Code Bits Interrupt Acknowledge Signal Interrupt Acknowledge In Interrupt Acknowledge Out Interrupt Priority Code Bits Internal Counter Register Interrupt DTACK Identify Interface Clear Interrupt Mask Register 1 Interru
41. 0107 01 1 0000 NS DS75162AN 1C 75162 GPIB CNTRL BUS XCVR i 95 U13 700106 01 1 0000 NS DS75160AN eee OMA BUS XCVR 96 u14 700107 01 1 0000 NS DS75162AN 1C 75162 GPIB CNTRL BUS XCVR 97 National Instruments Corporation B 5 GPIB 1014DP User Manual Parts List and Schematic Diagrams Appendix B IERI RICER RIE RION IIC US ede e dee deg de efe eee e ed e e dede ede e edd Ie Y ede CR IO d ede I e IIC CIRO II e OR e Y RE EY RICICIOIEI dE d Y eee RR IIC TRE ITEM NO NI PART NO QTY REOD MFR MFR PART PRODUCT DESCRIPTION U15 700540 01 1 0000 S1G N74F85N 1C F85 4 B1T MAGNITUDE COMP 98 U16 700706 01 1 0000 TI SN74F74N IC F74 FLIP FLOP 99 017 700004 01 1 0000 TI SN74LSOBN IC LS08 2 INP AND 100 u18 701010 01 1 0000 TI SN74F10N IC F10 THREE INPUT NAND GATE 101 u19 700706 01 1 0000 mo SNT amp FTAN IC F746 FLIP FLOP 102 u20 790440 01 1 0000 MOT MC74FOGN IC FO4 HEX INVERTER 103 u21 700418 01 1 0000 TI SN74F32N IC F32 QUAD 2 INPUT OR 104 u22 700009 01 1 0000 Ti SN74LS27N IC LS27 3 INP NOR 105 U23 700008 01 1 0000 TI SN74LS20N 1C LS20 4 INP NAND 106 U24 700418 01 1 0000 TI SN74F32N IC F32 QUAD 2 INPUT OR 107 u25 700418 01 1 0000 TI SN74F32N IC F32 QUAD 2 INPUT OR 108 U26 700013 01 1 0000 TI SN74LS7GAN IC LS74 FLIP FLOP 109 U27 720002 01 1 0000 AMP 2 435668 5 DIPSWITCH 6 POS SPST 110 u28 700706 01 1 0000 TI SN74F74N IC F74 FLIP FLOP 111 29 700182 01 1 0000 TI SN74LS21N 1C LS21 4 INP AND 112 u30 701072 01 1 0000 SIG N74F393N IC F393 DUAL 4
42. 1 0 CNT2 CNTI CNTO COM4 COM3 COM2 COMI COMO W The AUXMR is used to issue auxiliary commands It is also used to program the five hidden registers Auxiliary Register A AUXRA Auxiliary Register B AUXRB Parallel Poll Register PPR Auxiliary Register E AUXRE Internal Counter Register ICR Table 4 4 shows the control and command codes used Bit Mnemonic Description 7 5w CNT 2 0 Control Code Bits 2 through 0 These bits specify the control code that is the manner in which the information in bits COM 4 0 is to be used If CNT 2 0 are all zero then the special command selected by COM 4 0 is executed otherwise the hidden register selected by CNT 2 0 is loaded with the data from COM 4 0 O National Instruments Corporation 4 29 GPIB 1014DP User Manual Register Bit Descriptions Section Four Bit Mnemonic Description 4 0w COM 4 0 Command Code bits 4 through 0 These bits specify the command code of the special function if the control code is 000 Table 4 4 is a summary of the implemented special functions Table 4 5 explains the details of each special function If the control code is not 000 then these bits are written to one of the hidden registers indicated by the control code in CNT 2 0 Table 4 4 Auxiliary Command Summary Function Code COM4 COM0 4321 0 Hex Cad Auxiliary Command 00110 Send EOI 00 1 1 1 Non Valid Secondary Command or Address O 1 11 1l Valid Secondary Command or Address 0 1
43. 1 and ISR2 bits For one of these conditions to drive the selected IRQ line the following criteria must be satisfied e The interrupt condition must be true e The interrupt condition must be enabled bits in IMRI and IMR2 e The uPD7210 interrupt signal must be programmed to be active high see Auxiliary Register B in Section Four After an interrupt is generated the operating system will ask the interrupting source for a Status ID byte so that it can branch to the appropriate interrupt handler The status of the TLC interrupt is then found by reading the appropriate TLC status registers The status bits in ISR1 or ISR2 are all automatically cleared when the register is read even if the conditions are still true If two conditions are true at the same time that is more than one bit in ISRI or ISR2 is set software copy of the register must be maintained if the program is going to analyze the conditions one at a time GPIB 1014DP User Manual 5 8 National Instruments Corporation Section Five Programming Considerations Serial Polls Conducting Serial Polls The TLC as CIC serially polls other devices as described in the IEEE 488 specification From the programming point of view the TLC must first become Active Controller to send the addressing and enabling commands to the device being polled make itself a GPIB Listener by issuing the Listen auxiliary command and then go to standby with the Go To Standby auxiliary command in or
44. 4 18 National Instruments Corporation Section Four Register Bit Descriptions Bit Mnemonic Description Notes TA Talker Active bit ADSR 1 r LA Listener Active bit ADSR 2 r CIC Controller In Charge bit ADSR 7 r MJMN Major Minor bit ADSR 0 r lon Listen Only bit ADMR 6 w ton Talk Only bit ADMR 7 w pon power on reset Read ISR2 Bit is cleared immediately after it is read ADSC is set whenever there is a change in one of the four bits TA LA CIC MJMN of the Address Status Register ADSR National Instruments Corporation 4 19 GPIB 1014DP User Manual Register Bit Descriptions Section Four Serial Poll Status Register SPSR VMEbus Address Base Address 7 hex Port A Base Address 17 hex Port B Attributes Read Only Serial Poll Mode Register SPMR VMEbus Address Base Address 7 hex Port A Base Address 17 hex Port B Attributes Write Only 7 6 5 4 3 2 1 0 R W Bit Mnemonic Description Tr S8 Serial Poll Status Bit 8 Tw 5 Or S 6 1 Serial Poll Status Bits 6 through 1 5 Ow Cleared by Power On Reset pon and by issuing the Chip Reset auxiliary command These bits are used for sending device or system dependent status information over the GPIB when the TLC is serial polled When the TLC is addressed as the GPIB Talker and receives the GPIB multiline Serial Poll Enable SPE command message it transmits a byte of status information SPMR 7 0 to the Controller In Charge after
45. 4 39 UNL Unlisten command 4 27 unpacking the GPIB 1014DP 1 3 UNT Untalk command 4 27 V Valid Secondary Command or Address command codes for 4 30 description 4 34 verification of system compatibility 3 8 to 3 11 testing 3 11 VMEbus base address configuration 3 3 to 3 4 control signals 6 1 to 6 2 data lines 6 1 definition 2 9 interrupt configuration 3 4 to 3 6 modules not provided 2 5 GPIB 1014DP User Manual I 12 National Instruments Corporation signals chart 2 1 to 2 2 slave addressing 2 2 to 2 3 slave data 2 4 W WRITE sample program C 15 to C 16 X X Don t Care Bit 4 46 XEOS Transmit END with EOS Bit 4 41 National Instruments Corporation 1 13 Index GPIB 1014DP User Manual Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products This information helps us provide quality products to meet your needs Title GPIB 1014DP User Manual Edition Date November 1993 Part Number 370946A 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for your help Name Title Company Address Phone Mail to Technical Publications Fax to Technical Publications National Instruments Corporation National Instruments Corporation 6504 Bridge Point Parkway
46. 4 8 Interrupt Status Register 1 CIS RU iicet cia 4 9 Interrupt Mask Register 1 IMRI eren 4 9 National Instruments Corporation vii GPIB 1014DP User Manual Contents Interrupt Status Register 2 ISR2 1 nuce ettet da geo Pope tici ed 4 15 Interrupt Mask Register 2 IM R2 ua jegen sa teaser ue sieasaasl gue fepe eo ce ae colat ad 4 15 Serial Poll Status Register SPSR sicilia 4 20 Serial Poll Mode Register SPMR irpini 4 20 Address Status Register ADSR cui iaia 4 2 Address Mode Register ADMR c cccssscssesececesececssccecssccecsscceescceesceeensees 4 23 Command Pass Through Register CPTR eee 4 26 Auxiliary Mode Register AUXMR onice 4 29 Hidden CBIR ETS acs Seas ttn saam tpe IONS Su RI ideo Ini en tenu Me LM a 4 37 Internal Counter Register ICR iioii quide ea tenn eve ien ed gd 4 38 Parallel Poll Begister PPR ostili etus eee gea a ve dadas 4 39 Auxiliary Register A AUXRA Lirio eil 4 41 Auxiliary Register B CAUXRDB 5 soia aa bp irn eee aes 4 43 Auxiliary Register E AUXRE itti lina detto eee gea donis 4 45 Address Resister0 ADRO Licodia orari 4 46 Address Register ADR siscceesssiasissdescasdeaacgusayecesanecduatssobenechaunentuaee ead veo erae d bu 4 47 Address Register 1 ADRI ore iaia 4 48 End Of String Register EOSR iaia ela alari 4 49 Section Five Programming Considerations seen 5 1 LENA to MEM 5 1 A GPIB 1014DP Port as GPIB Controller eee la
47. 4N SN74F76N SN74LSO8N TSW 136 07 S D 65500 103 TSW 136 07 5 D 65500 111 Parts List and Schematic Diagrams PRODUCT DESCRIPTION 1C LS21 4 INP AND 123 1C 051013M DDL 25NS 3 IN 1 124 1C F74 FLIP FLOP 125 IC F74 FLIP FLOP 126 IC LS19 HEX ST INVERTER 127 DIPSWITCH 8 POS SPST 128 1C F244 0CTAL BUFER LINE DRIVE 129 1C F74 FLIP FLOP 130 1C LS08 2 INP AND 131 CONN BRGSTK HOR 2X36 STRT 132 HEADER SGL ROW STR 1 CTR 3POS 133 CONN BRGSTK HDR 2X36 STRT 134 CONN ERGSTK HDR SGL 1CTR 11PO 135 GPIB 1014DP User Manual PMD 4251 dOFIOI SIdO 6g UOMDIOdIOI STUZUNASU JDUONDN Pensesay SIUCTY TTY dado SINSWNALSNI TWNOLILON 6861 1HOIBNAdU29 T0 T722081 uoTSSTuas4 usiiT4m ANGUITA SUSAT 40 ATES JO a4032 j0u w SUI JOJ TSPQ OU3 Se ap OM aaor 2007 RED des JO STOUM UT PSTdOI 40 PASNPOJdSI IQ 30 ddr TOT BIA9 ZA T UDRLRTONULI M teer teet amp zl a WUBNSUIG OILIUWJHOS m TO Q3ISTISdS 3SIMB3HLO SS37Nn S310N xp 1350 UI BIB Li Rib nisl Ld DT ELI iip iis Britt ji Lakes Li Af T0o T Zze08T r li s r r E s s pe iii SUDIO IRDWNIS pup 151 SUDA o gapusidy jonuowp 4251 AQPIOI gIdO rg UOTD40d407 SIURUNUISU OUOTION mi do E RA RD 5 EA 53833853 m ies So DO N 1 ra O b SUDABDIC INDUNIS pup IST SUDA g mpuaddy Parts List and Schematic Diagrams Appendix B 01 1 N avi o 2 CD P b jO k
48. 68000 Code Sample Programs ok ck ok ko KK Ck Ck KK KK KK KK k k k k k kk OK COMMAND SEND CSEND kK ck ck Ck ck Ck Ck Ck Ck Ck Ck Ck KK ok ko k k ok k k kk OK Summary Called by CMD to send interface command messages Assumptions on entry The GPIB 1014DP is Active Controller The dO register contains the number of bytes to send The a0 register contains the address oc cmdbuf Actions Initialize a count variable Wait until the CDOR is empty Write a byte and increment the counter Check for a GPIB error Loop until all bytes are transferred On an error set dO to 1 Status on return dO register contains number of bytes sent or 1 if an error occurred Comments CSEND CSEND 1 CSEND2 CSEND3 cliw count L btst CO ISR2 L beq CSEND1 cmpw count d0 beq CSEND3 addw 1 count L movb a0 CDOR L btst ERR ISR1 bne CSEND2 addi 1 a0 bra CSEND1 movw 1 d0 rts National Instruments Corporation Initialize count variable Wait till CDOR is empty Have all commands been sent Yes No Increment counter and write the next command If there are no Listeners return 1 in dO register GPIB 1014DP User Manual Sample Programs 68000 Code CMD movb TCA AUXMR L movl movw bsr rts GPIB 1014DP User Manual Appendix C kK ok KR KK KKK k ok k k kk COMMAND CMD ok ok ok ko KK k k k k k k k Summary Send GPIB interface or comm
49. 7 FS 3C 074 60 lt MLA28 GS 3D 075 61 MLA29 RS 3E 076 62 gt MLA30 US 3F 077 63 gt UNL MSA My Secondary Address Group Execute Trigger MTA My Talk Address Go To Local Local Lockout PPC Parallel Poll Configure PPD Parallel Poll Disable My Listen Address D 2 National Instruments Corporation Appendix D PPE PPU SDC SPD Multiline Interface Command Messages Multiline Interface Messages Oct Dec ASCII 100 64 101 65 A 102 66 B 103 67 C 104 68 D 105 69 E 106 70 F 107 71 G 110 72 H 111 73 I 112 74 J 113 75 K 114 76 L 115 71 M 116 78 N 117 79 O 120 80 P 121 81 Q 122 82 R 123 83 S 124 84 T 125 85 U 126 86 V 127 87 W 130 88 X 131 89 Y 132 90 Z 133 91 134 92 135 93 136 94 137 95 _ Parallel Poll Enable Parallel Poll Unconfigure Selected Device Clear Serial Poll Disable National Instruments Corporation Msg MTAO MTAI MTA2 MTA3 MTA4 MTAS MTA6 MTA7 MTA8 MTA9 MTA10 MTAII MTA12 MTA13 MTA14 MTA15 MTAI6 MTA17 MTA18 MTA19 MTA20 MTA2I MTA22 MTA23 MTA24 MTA25 MTA26 MTA27 MTA28 MTA29 MTA30 UNT D 3 Hex 60 140 61 141 62 142 98 63 143 99 64 144 100 65 145 101 66 146 102 67 147 103 68 150 104 69 151 105 152 153 154 155 156 6F157 111 70 160 112 71161 113 72162 114 73163 115 74164 116 75165 117 76166 118 77167 119 78 170 120 79171 121 7A 172 7B 173 7C 174 7D 175 7E 176 7F177 127 SPE TCT UNL UNT Oct Dec A
50. 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 41 ci9 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 42 C20 715079 01 1 0000 AVX SA105E4732AA CAP O47UF 50V 80 20 CER AX 43 221 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 44 c22 715079 01 1 0000 AVX SA10SE473ZAA CAP O47UF 50V 80 20x CER AX 45 223 715079 01 1 0000 AVX SA105E4732AA CAP L047UF 50V 80 20 CER AX 46 224 715079 01 1 0000 AVX SA105E4732AA CAP O47UF SOV 80 205 CER AX 47 National Instruments Corporation B 3 GPIB 1014DP User Manual Parts List and Schematic Diagrams Appendix B OCDE OI WE DE E E AE HE IE ME IE IE EE E TE E IE AE IE CUR SER HIR RR de KE IER CREDE CC E HIC III III E e WE AE AE E Ae S E E E E A BE B IDEE HER RR ITEM NO NI PART NO QTY REQD MFR MFR PART PROOUCT DESCRIPTION C25 715079 01 1 0000 AVX SATOSETIZAA CAP 047UF 50V 80 20 CER AX 48 c26 715079 01 1 0000 AVX SA105E4732AA CAP O47UF 50V 80 20 CER AX 49 c27 715079 01 1 0000 AVX SA105E4732AA CAP O47UF 50V 80 20 CER AX 50 C28 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 54 29 715079 01 1 0000 AVX SA105E4732AA CAP 047UF SOV B0 20 CER AX 52 C30 715079 01 1 0000 AVX SA105E4732AA CAP 047UF SOV 80 20 CER AX 53 c31 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 54 c32 715079 01 1 0000 AVX SA105E4732AA CAP 047UF SOV B0 20M CER AX 55 233 715079 01
51. ADMR 31 Address Mode 1 B 1B AUXMR 0 Immediate execute pon B 1B AUXMR 1E set IFC B 1B AUXMR 16 clear IFC 9 19 ADSR 80 CIC 3 15 ISR2 9 CO ADSC B IB AUXMR 10 go to standby 9 19 ADSR C0 CIC ATN National Instruments Corporation 7 3 GPIB 1014DP User Manual Appendix A Specifications IEEE 488 Bus Transfer Rate Up to 80 kbytes sec Power Requirement 5 VDC 1 1 A typical 2 0 A maximum Physical Board dimensions 6 299 by 9 187 in 160 by 233 35 mm Input output connectors IEEE 488 standard 24 pin Operating Environment Component temperature 0 to 70 C Relative humidity 10 to 90 noncondensing Storage Environment Temperature 62 to 71 C Relative humidity 0 to 100 noncondensing National Instruments Corporation A 1 GPIB 1014DP User Manual Appendix B Parts List and Schematic Diagrams This appendix contains the parts list and schematic diagrams for the GPIB 1014DP National Instruments Corporation B 1 GPIB 1014DP User Manual Parts List and Schematic Diagrams Appendix B IC DE DE e eee e e IE DI DERE de de IE ede gei dee dede de e de de TE e e e dee dee fe de e ee e e 3X Fe T Vt le de e dee eec Yee e e e Te VR OR RC de ed Re ee do e e dede de d e fe e Ye Pede Hee dee ecd e de END PRODUCT PRODUCT DESCRIPTION REVISION LEVEL 180270 01E CCA GPIB 1014DP E trem NO NI PART NO QTY REOD MFR MFR PART PRODUCT DESCRIPTION 01 180272 01 1 0000 NI 180272 01 PWB GPIB 1014DP 1 02
52. Base Address D hex Port A Base Address 1D hex Port B Attributes Write Only Internal to TLC 7 6 5 4 3 2 1 0 W The Address Register ADR is used to load the internal registers ADRO and ADR1 Both ADRO and ADRI must be loaded for all addressing modes Bit Mnemonic Description Tw ARS Address Register Select Bit ARS is 0 or 1 to select whether the seven lower order bits of ADR must be loaded into internal registers ADRO or ADR1 respectively 6w DT Disable Talker Bit DT must be set if recognition of the GPIB talk address formed from AD 5 1 ADR 4 0 w is not to be enabled 5w DL Disable Listener Bit DL must be set if recognition of the GPIB Listen address formed from AD 5 1 is not to be enabled 4 Ow AD 5 1 Address Bit These bits specify the five low order bits of the GPIB address that is to be recognized by the TLC The corresponding GPIB Talk address is formed by adding octal 100 to AD 5 1 while the corresponding GPIB listen address is formed by adding octal 40 The value written to AD 5 1 must not be all ones otherwise the corresponding talk and listen addresses would conflict with the GPIB Untalk UNT and Unlisten UNL commands National Instruments Corporation 4 47 GPIB 1014DP User Manual Register Descriptions Section Four Address Register 1 ADR1 VMEbus Address Base Address F hex Port A Base Address 1F hex Port B Attributes Read Only Address Register 1 ADR1 indi
53. C Not Data Accepted Management Lines IFC Interface Clear ATN Attention SRQ Service Request REN Remote Enable EOI End or Identify Figure 2 1 GPIB 1014DP with a VMEbus Computer National Instruments Corporation GPIB 1014DP User Manual General Description Section Two R amp D Lab BH o el EB BEE VMEbus Computer with IBM PC with GPIB PC GPIB 1014DP IEEE 488 Interface IEEE 488 Interface Microprocessor Work Station GPIB 100 Bus Extender Up to 300 Meters RS 422 Computer Center l GPIB 100 Bus Extender Production amp Testing PDP 11 44 with GPIB11 2 S 100 Computer IEEE 488 Interface GPIB 696P IEEE 488 Interface Figure 2 2 GPIB 1014DP in a Multiprocessor Application GPIB 1014DP User Manual 2 8 National Instruments Corporation Section Two General Description Figure 2 3 is a block diagram of the GPIB 1014DP AMS AMO A15 A01 Bus Address Decoding WRITE Timing and Data Direction DTACK Control DS1 DS0 D07 D00 IRQI IRQ7 Interrupt Logic IACKOUT GPIB uPD7210 Transceivers TLC Controller Select n E 9 o d System Controller Select Figure 2 3 GPIB 1014DP Block Diagram The interface consists of these major components which are discussed in greater detail in Section Six e VMEbus Interface e Address Decoder National Instruments Corporation Consists of the buffers drivers and transceivers for the
54. CIDS The transition of the TLC interface function is not guaranteed if the local messages rpp and Go To Standby gts are issued simultaneously when the TLC is in Controller Active State CACS and Source Transfer State STRS or Source Delay State SDYS Set IFC Clear IFC These commands generate the local message request system control rsc and set Interface Clear IFC to the value of COM3 These commands should only be issued if the GPIB 1014DP is the System Controller SC In order to meet IEEE 488 requirements you must not issue the Clear IFC command until IFC has been held true for at least 100 usec Set REN Clear REN These commands generate the local message rsc and set REN to the value in COM3 These commands should only be issued if the GPIB 1014DP is the System Controller SC In order to meet IEEE 488 requirements you must not issue the Set REN command until REN has been held false for at least 100 usec Disable System Control The Disable System Control command clears the local message rsc GPIB 1014DP User Manual 4 36 National Instruments Corporation Section Four Register Descriptions Hidden Registers The hidden registers are loaded through the Auxiliary Mode Register AUXMR AUXMR 7 5 is loaded with the hidden register number and AUXMR 4 0 is loaded with the data to be transferred to the hidden register The hidden registers cannot be read and in some cases the contents can only be set that is t
55. GPIB 1014DP User Manual November 1993 Edition Part Number 370946A 01 Copyright 1984 1995 National Instruments Corporation All Rights Reserved National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin TX 78730 5039 512 794 0100 Technical support fax 800 328 2203 512 794 5678 Branch Offices Australia 03 879 9422 Austria 0662 435986 Belgium 02 757 00 20 Canada Ontario 519 622 9310 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 24 Germany 089 741 31 30 Italy 02 48301892 Japan 03 3788 1921 Mexico 95 800 010 0793 Netherlands 03480 33466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 20 51 51 Taiwan 02 377 1200 U K 0635 523545 Limited Warranty The GPIB 1014DP is warranted against defects in materials and workmanship for a period of two years from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty
56. GPIB Talk or Listen address using the CO bit and the CDOR When another device on the GPIB is acting as Controller the TLC is addressed with GPIB command messages to become a Talker or Listener Address Mode 1 If the TLC ADMR has been configured for Address Mode 1 the TLC responds to the reception of two primary GPIB addresses major and minor Upon receipt of its major or minor MTA or its major or minor MLA from the GPIB Active Controller the TLC is addressed as Talker or Listener If the TLC has received its GPIB Talk Address the TA bit in the ADSR is set the ADSC bit in ISR2 is set and the DO bit in ISR1 is set If the TLC has received its GPIB Listen address the LA bit in the ADSR is set the ADSC bit in ISR2 is set and the DI bit in ISR1 is set when the first GPIB data byte is received National Instruments Corporation 5 5 GPIB 1014DP User Manual Programming Considerations Section Five Address Mode 2 Address Mode 2 is used when Talker Extended TE or Listener Extended LE functions are to be used TE and LE functions require receipt of two addresses primary and secondary before setting TA or LA The TLC GPIB primary address is specified by the byte written to ADRO The secondary address is specified by the byte written to ADR1 Upon receipt of both the primary and secondary GPIB addresses the TLC becomes an addressed Talker or Listener If the TLC has received its primary GPIB talk address the Talker Primary Addressed State
57. Interrupt Enable Bit DEC is set by DCAS DEC is cleared by pon Read ISR1 Notes DCAS GPIB Device Clear Active State pon power on reset Read ISRI Bitis cleared immediately after it is read The DEC bit indicates that the GPIB Device Clear DCL command has been received or that the GPIB Selected Device Clear SDC command has been received while the TLC was a GPIB Listener the TLC is in DCAS Error Bit Error Interrupt Enable Bit ERR is set by TACS amp SDYS amp DAC amp RFD SIDS amp Write CDOR SDYS SIDS 4 12 National Instruments Corporation Section Four Bit lr lw Or Ow Mnemonic DO DO IE DI DI IE Register Bit Descriptions Description ERR is cleared by pon Read ISR1 Notes TACS GPIB Talker Active State SDYS GPIB Source Delay State DAC GPIB Data Accepted message RED GPIB Ready For Data message SIDS GPIB Source Idle State Write CDOR Bit is set immediately after writing to the Command Data Out Register SDYS gt SIDS Transition from GPIB Source Delay State to Source Idle State pon power on reset Read ISRI Bit is cleared immediately after it is read The ERR bit indicates that the contents of the CDOR have been lost ERR is set when data is sent over the GPIB without a specified Listener or when a byte is written to the CDOR during SIDS or during the SDYS to SIDS transition Data Out Bit Data Out Interrupt Enable Bit DO is set as TACS amp SGNS
58. MR L GTS AUXMR L datct d0 datbuf a0 RCV TCS AUXMR L btst NATN ADSR READ1 1 cmdct CMD LUN AUXMR L GPIB 1014DP User Manual Talker address in the buffer Command routine will address the Talker Program GPIB 1014DP to be a Listener so it can take control synchronously later then go to standby and drop ATN Take control Preset dO register with byte count Preset a0 register with buffer address Receive routine will read data Wait for ATN indefinitely Prepare to unaddress all Talkers and Listeners using CMD Send Local Unlisten command National Instruments Corporation Appendix C National Instruments Corporation Sample Programs ok ok KK KK k k k k k KK KKK OK DATA SEND DSEND KKK ok ko KK k k k k k k k k k k X Summary Called by WRITE to transmit data messages if the GPIB 1014DP is Controller In Charge Called directly from the main program if the GPIB 1014DP is not CIC Assumptions on entry The GPIB 1014DP is Standby or Idle Controller GPIB 1014DP is or will be addressed to talk If the GPIB 1014DP is Idle Controller the current CIC will go to standby The dO register contains the byte count The a0 register contains the address of the data buffer The user specified variable veoi has been set properly Actions Copy byte count to d1 Wait until the CDOR is empty Decrement d1 If last byte assert EOI if in us
59. National Instruments believes that the information in this manual is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable c
60. P User Manual Section Five Programming Considerations This section explains important considerations for programming the GPIB 1014DP Initialization On power up pon the VMEbus system typically issues a system reset SYSRESET that drives the GPIB 1014DP RESET signal active and initializes the following circuitry e Timing State Machine e Interrupter Each uPD7210 TLC The NEC uPD7210 Talker Listener Controller TLC integrated circuits are initialized as follows e The local message pon is set and the interface functions are placed in their idle states SIDS AIDS TIDS SPIS TPIS LIDS LPIS NPRS LOCS PPIS PUCS CIDS SRIS SIIS e All bits of the Serial Poll Mode Register SPMR are cleared End Or Identify EOD bit is cleared e All bits of the Auxiliary Registers A B and E AUXRA AUXRB and AUXRE are cleared e The Parallel Poll Flag and Request System Control RSC local message are cleared e The Internal Counter Register ICR is set to a count of eight e The Transmit Receive Mode 0 TRMO and Transmit Receive Mode 1 TRM1 bits in the Address Mode Register ADMR are cleared All other TLC register contents should be considered as undefined while the RESET is asserted and after RESET has been cleared All Auxiliary Mode Register AUXMR commands are cleared and cannot be executed All other TLC registers can be programmed while the TLC internal signal pon is set When pon is released or cleared by i
61. PIB Address Bits 5 0 through 1 0 4 46 AD5 1 Address Bit 4 47 AD 5 1 1 1 Mode 2 Secondary TLC GPIB Address Bits 5 1 through 1 1 4 48 address decoding 6 2 VMEbus address lines 6 2 VMEbus base address configuration 3 3 to 3 4 VMEbus slave addressing 2 2 to 2 3 address decoder definition 2 9 Address Mode Register ADMR 4 23 to 4 25 Address Register ADR 4 47 Address Register 0 ADRO 4 46 Address Register 1 ADR1 4 48 Address Status Register ADSR 4 21 to 4 22 addressed implementation of Talker and Listener 5 5 to 5 6 ADM 1 0 Address Mode Bits 1 through 0 4 24 to 4 25 ADMR See Address Mode Register ADMR ADR See Address Register ADR ADRO See Address Register 0 ADRO ADRI See Address Register 1 ADRI ADSC Addressed Status Change Bit 4 18 to 4 19 ADSC IE Addressed Status Change Interrupt Enable Bit 4 18 to 4 19 ADSR See Address Status Register ADSR AH Acceptor Handshake 4 7 ANSI IEEE Standard for a Versatile Backplane Bus VMEbus 1 1 APT Address Pass Through Bit 4 10 to 4 11 APT IE Address Pass Through Interrupt Enable Bit 4 10 to 4 11 ARS Address Register Select Bit 4 47 ATN Attention Bit 4 21 ATN attention line E 3 auxiliary command summary detailed description 4 32 to 4 36 table of 4 30 to 4 31 Auxiliary Mode Register AUXMR command summary table 4 30 to 4 31 overview 4 29 to 4 30 Auxiliary Register A AUXRA 4 41 to 4 42 Auxiliary Register B AUXRB 4 43 to
62. RER ERE ERE IR e ECHO ERENT NER ERE HORROR ERO EE RECEN OR ITEM NO NI PART NO QTY REQD MFR MFR PART PRODUCT DESCRIPTION 23 742420 01 4 0000 742420 01 SCREW 2 56x7 16 PH PHLPS SS 23 cot 715062 01 1 0000 SPG 1990106x0016CE2 CAP 10UF 16V 20X TANT RDL 24 coz 715062 01 1 0000 SPG 199D106X0016CE2 CAP 10UF 16V 20 TANT RDL 25 co3 715079 01 1 0000 AVX SA105E4732AA l CAP 047UF 50V 80 20 CER AX 26 c04 715079 01 1 0000 AVX SA105E4732AA CAP 047 50V 80 20 CER AX 27 cos 715079 01 1 0000 AVX SA105E4732AA CAP m 50V 80 20 CER AX 28 C06 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 cen Ax 29 co7 715079 01 1 0000 AVX SA105E4732AA CAP 047UF SOV 80 20 CER AX 30 cos 715079 01 1 0000 AVX SA105E4732AA CAP O47UF 50V 80 20 CER AX 31 coo 715079 01 1 0000 AVX SA105E4722AA CAP 047UF 50V 80 20 CER AX 32 c10 715079 01 1 0000 AVX SA105E473ZAA CAP 067UF 50V 80 20 CER AX 33 cti 715079 01 1 0000 AVX SA105E473ZAA CAP O47UF SOV 80 20 CER AX 34 ci2 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 35 ci3 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 36 Cis 715079 01 1 0000 AVX SA105E4732AA CAP 047UF 50V 80 20 CER AX 37 c15 715079 01 1 0000 AVX SA105E473ZAA l CAP 047UF 50V 80 20 CER AX 38 c16 715079 01 1 0000 AVX SA105E473ZAA CAP 047UF 50V 80 20 CER AX 39 c17 715079 01 1 0000 AVX SA105E4732AA CAP 047UF sov amp 0 20 CER AX 40 c18
63. SCII Msg 96 E MSAO PPE 97 a MSA1 PPE b MSA2 PPE c MSA3 PPE d MSA4 PPE e MSAS PPE f MSA6 PPE g MSA7 PPE h MSA8 PPE i MSA9 PPE 106 j MSA10 PPE 107 k MSA11 PPE 108 l MSA12 PPE 109 m MSA13 PPE 110 n MSA14 PPE o MSA15 PPE p MSA16 PPD q MSA17 PPD r MSA18 PPD S MSA19 PPD t MSA20 PPD u MSA21 PPD V MSA22 PPD W MSA23 PPD x MSA24 PPD y MSA25 PPD 122 Z MSA26 PPD 123 MSA27 PPD 124 MSA28 PPD 125 MSA29 PPD 126 MSA30 PPD DEL Serial Poll Enable Take Control Unlisten Untalk GPIB 1014DP User Manual Appendix E Operation of the GPIB Communication among interconnected GPIB devices is achieved by passing messages through the interface system Types of Messages The GPIB carries device dependent messages and interface messages e Device dependent messages often called data or data messages contain device specific information such as programming instructions measurement results machine status and data files e Interface messages manage the bus itself They are usually called commands or command messages Interface messages perform such tasks as initializing the bus addressing and unaddressing devices and setting device modes for remote or local programming The term command as used here should not be confused with some device instructions which can also be called commands Such device specific instructions are actually data messages Talkers Listeners and Controllers A Talker sends data messages to one or more Lis
64. System Control Interface Clear Idle State SPIS Serial Poll Idle State SRIS System Control Remote Enable Idle State TIDS Talker Idle State TPIS Talker Primary Idle State If the command is sent while a pon message is already active by either an external reset pulse or the Chip Reset auxiliary command the local pon message becomes false Chip Reset The Chip Reset command resets the TLC in the same way as an external reset pulse The System Controller bit is also cleared The TLC is reset to the following conditions e The local pon message is set and the interface functions are placed in their idle states AII bits of the SPMR are cleared The EOI bit is cleared All bits of the AUXRA AUXRB and AUXRE are cleared The Parallel Poll Flag and RSC local message are cleared continues GPIB 1014DP User Manual 4 32 National Instruments Corporation Section Four Register Descriptions Table 4 5 Auxiliary Commands Detailed Description continues Command Code COM4 COM0 43210 Description e The contents of the ICR is set to eight F3 set to 1 F2 FI and FO set to 0 e The TRMO bit and the TRM1 bit are cleared The interface functions are held in their idle states until released by an Immediate Execute pon command Between these commands the TLC writable bits may be programmed to their desired states Finish Handshake FH The Finish Handshake command finishes a GPIB Handshake that was stopped because of a Holdoff
65. abbreviated to mean the following Bit Function Integrated Circuit GPIB Signal Local Message Local Signal Register Remote Message System Function State VMEbus Operation VMEbus Signal National Instruments Corporation GPIB 1014P User Manual Mnemonics Key Mnemonic Type A A 01 31 VBS ACDS ST ACFAIL VBS ACG RM ACRS ST ACT B AD 5 1 B AD 5 0 1 0 B AD 5 1 1 1 B ADCS B ADCS IE B ADM 1 0 B ADMR R ADO VBO ADR R ADRO R ADRI R ADSC B ADSC IE B ADSR R AH ST AIDS ST AM 0 5 VBS ANRS ST APRS ST APT B APT IE B ARS B AS VBS ATN ST ATN B AUXMR R AUXRA R AUXRB R AUXRE R AWNS ST B BBSY VBS BCLR VBS BERR VBS BG 0 3 IN VBS BG 0 3JOUT VBS BIN B BLT VBO BR 0 3 VBS GPIB 1014P User Manual Appendix F Definition Address Lines 1 through 31 Acceptor Data State AH function Power Fail Signal Addressed Command Group Acceptor Ready State Channel Active Bit Talker Listener Controller TLC GPIB Address Bits 5 through 1 Mode 2 Primary TLC GPIB Address Bits 5 through 1 Mode 2 Secondary TLC GPIB Address Bits 5 through 1 Addressed Status Change Bit Enable Interrupt on Addressed Status Change Bit Address Mode Bits 1 through 0 Address Mode Register Address Only Cycle Address Register Address Register 0 Address Register 1 Address Status Change Address Status Change Interrupt Enable Bit Address Status Register Acceptor Handshake Acceptor Idle State Address Modifier Lines
66. able Not Active State Service Request Service Request Input Bit Enable Interrupt on Service Request Input Bit Service Request State Status Byte Source Transfer State Start Cycle Signal Source Wait for New Cycle State System Clock System Fail System Reset Talker Talker Active Bit Talker Active State T function Talker Addressed State Talk Address Group Take Control Asynchronously Take Control Synchronously Take Control Synchronously on End Take Control Terminate DMA Extended Talk Talker Idle State Talker Listener Controller GPIB Adapter TLC Chip Reset TLC Write Talker Only Bit Talker Only Talker Primary Addressed State Bit Talker Primary Addressed State F 8 National Instruments Corporation Appendix F Mnemonic Type TPIS ST TRI B TRIG LM TRM 1 0 B U U B UAT VBO UCG RM UDPCF LM UNL RM UNT RM V V 0 7 LS W WR LS WRITE VBS X XEOS B O National Instruments Corporation Mnemonics Key Definition Talker Primary Idle State Three State Timing Bit Trigger Transmit Receive Mode Bits 1 through 0 Unconfigure Bit Unaligned Transfer Universal Command Group Undefined Primary Command Function Unlisten command Untalk command Interrupt Vector Bits TLC Write Signal Read Write Line Transmit End with End Of String Bit F 9 GPIB 1014P User Manual Index A abbreviations used in the manual vi access mode configuration 3 3 AD 5 0 1 0 Mode 2 Primary G
67. additional 25 nsec before asserting IACKOUT or responding with a STATUS ID byte This additional delay assures that the output of the flip flop will be stable before the logic selects to either pass the interrupt of the comparison or respond with a status byte If the output of the flip flop is latched true the interrupter is set to respond with a STATUS ID byte The interrupter waits for IACKIN and DSO to become true as well as for the signal AS that has been delayed 50 nsec and makes certain that the VME signal DTACK has been released At this time an enable vector signal EVA or EVB is latched in order to enable the data bus transceiver for the entire transfer cycle The complement EVA or EVB enables an F244 to drive the VME data bus with a STATUS ID byte which you determine by setting onboard switches as described in Interrupt Status ID Byte in Section Three EVA or EVB then signals the DTACK Asset Release circuitry via ITACK to drive DTACK true ITACK is delayed by a 25 nsec delay line to allow for data setup on the VMEbus The enable vector signal is held true until the interrupt handler releases DSO The rise of EVA or EVB releases the appropriate IRQ line Therefore the GPIB 1014DP is a Release On AcKnowledge ROAK interrupter Note Even though the VMEbus interrupt request line is no longer driven the TLC INT line remains asserted until it is cleared in the interrupt service routine by reading the appropriate interr
68. ait at least 100 microseconds 18 clock cycles Clear IFC Restore d1 C 7 GPIB 1014DP User Manual Sample Programs 68000 Code REN tstb sre L beq RENI movb SREN AUXMR L bra REN2 REN1 movb CREN AUXMR L REN2 rts GPIB 1014DP User Manual Appendix C REMOTE ENABLE REN Summary Set or clear GPIB Remote Enable signal Assumptions on entry User specified sre is non zero if REN is to be asserted and is zero if REN is to be unasserted GPIB 1014DP is System Controller and Active Controller Actions Check sre flag if non zero true send REN else send clear REN Status on return REN is asserted or unasserted Comments Turn on the REN signal if sre is non zero Else turn off REN if sre is zero C 8 National Instruments Corporation Appendix C National Instruments Corporation Sample Programs okok ok KKK k k k k k KKK RECEIVE RCV RK KKK k k k k k k k k k k Summary Called by READ to receive data if GPIB 1014DP is Controller In Charge Called directly from main program to receive data if GPIB 1014DP is Idle Controller Assumptions on entry GPIB 1014DP is Standby or Idle Controller GPIB 1014DP is or will be addressed to listen The GPIB Talker has been or will be addressed The Talker will send END with last byte if the number of bytes sent is less than the byte count The dO register contains the byte count The a0 register conta
69. and messages Assumptions on entry The GPIB 1014DP is Controller In Charge The commands to be sent are in cmdbuf The variable cmdct contains the number of commands to be sent which must be less than 256 Interruption of any data transfer in progress is acceptable Actions ssue TCA command to assert ATN in case the GPIB 1014DP is at standby Load the dO register with the address of cmdbuf Load a0 with the number of commands Call CSEND to transmit the bytes Status on return GPIB 1014DP is Active Controller GPIB devices are programmed as implied by command bytes Comments Take control in case at standby cmdbuf a0 Set up registers for CSEND call cmdct d0 CSEND C 18 National Instruments Corporation Appendix C 68000 Code Sample Programs PASS CONTROL PASSC Summary Passes GPIB Controller In Charge status to another device Assumptions on entry The GPIB 1014DP is Controller In Charge The primary GPIB address of the new controller is placed in tctadr Actions Send TCA command to take control in case the GPIB 1014DP is at standby Set up the command buffer and command count Call CMD to send the command bytes Status on return The GPIB 1014DP is Idle Controller Comments movb TCA AUXMR L movb UNT cmdbuf L movb UNL cmdbuf L 1 movb tctadr cmdbuf L 2 movb TCT cmdbuf L 3 movw 4 cmdct bsr CMD rts National Instruments Corporation Take contro
70. ands and by Listeners when receiving data messages NDAC not data accepted NDAC indicates when a device has or has not accepted a message byte The line is driven by all devices when receiving commands and by Listeners when receiving data messages GPIB 1014DP User Manual E 2 National Instruments Corporation Appendix E Operation of the GPIB DAV data valid DAV tells when the signals on the data lines are stable valid and can be accepted safely by devices The Controller drives DAV when sending commands and the Talker drives it when sending data messages Interface Management Lines Five lines are used to manage the flow of information across the interface ATN attention The Controller drives ATN true when it uses the data lines to send commands and false when it allows a Talker to send data messages IFC interface clear The System Controller drives the IFC line to initialize the bus and become CIC REN remote enable The System Controller drives the REN line which is used to place devices in remote or local program mode SRQ service request Any device can drive the SRQ line to asynchronously request service from the Controller EOI end or identify The EOI line has two purposes The Talker uses the EOI line to mark the end of a message string The Controller uses the EOI line to tell devices to identify their response in a parallel poll Physical and Electrical Characteristics Devices are usually connected
71. at from the second step UNL for each additional device The same procedure should be followed to disable polling with PPD for example when changing responses during reconfiguration Responding To a Parallel Poll Before the port can be polled by the CIC the TLC must be configured either locally by your program at initialization time or remotely by the CIC Configuration involves the following e Enabling the TLC to participate in polls e Selecting the sense or polarity of the response Selecting the GPIB data line on which the response will be asserted when the CIC issues the IDY message With remote configuration PP1 the TLC interprets the configuration commands received from the CIC without any software assistance or interpretation from your program With local configuration PP2 the three actions listed must be explicitly handled in the software by writing the appropriate values to the U S and P3 to P1 bits of the PPR Refer to the PPR description in Section Four for more information Once the PPR is configured all that remains for your program is determining the source and value of the local individual status ist message If the ISS bit in the AUXRB is zero ist is set and cleared via the Set and Clear Parallel Poll auxiliary commands If ISS is one ist is set if the TLC s Service Request function is in the Service Request State SRQS and the TLC is asserting the GPIB SRQ signal line and cleared otherwise Consequently s
72. ation and Installation Table 3 2 GPIB 1014DP Pin Assignment on VMEbus Connector P2 continued Signal Signal Signal Used Not Used Signal Used Not Used Notes User I O User I O User I O DIO1B DI02B DIO3B DI04B EOIB DAVB NRFDB NDACB NNNNYNNNNNNYNN WW WW WW WWW WW C9 Notes Can be used to set base address of GPIB 1014DP GPIB signals Port A used for GPIB I O via P2 GPIB signals Port B used for GPIB I O via P2 Reserved Verification Testing A verification test can be run to ensure that the board has not been damaged during shipment and also to ensure that the board has been configured correctly This requires an interactive control program or an equivalent mechanism such as front panel control switches or front panel emulator that provides a way to load and read memory and I O addresses The tests presented in Section Seven of this manual consist of a series of steps written in a pseudo processor independent language with instructions The steps generally involve writing data to specific GPIB 1014DP device registers followed by reading other GPIB 1014DP registers to verify that the programming is correct These tests exercise virtually all of the major functions of the GPIB 1014DP including I O communications and GPIB communications All functions except GPIB communications can be performed as stand alone operations that is without another GPIB device To completely check the GPIB functions you mus
73. block transfer End message END bit equal to one is generated at CSBS The tcs message is cleared when the TLC enters CACS Listen The listen command generates the local message Itn in the form of a pulse Listen in Continuous Mode The Listen in Continuous Mode command generates the local message Itn in the form of a pulse and places the TLC in continuous mode In continuous mode the local message rdy is issued when the Acceptor Not Ready State ANRS is initiated unless data block transfer end is detected END RX bit equals one When END is detected the TLC is placed in the RFD Holdoff state preventing generation of the rdy message In continuous mode the DI bit is not set when a data byte is received The continuous mode caused by the Listen in Continuous Mode command is released when the Listen auxiliary command is issued or the TLC enters the Listener Idle State LIDS continues National Instruments Corporation 4 35 GPIB 1014DP User Manual Register Descriptions Section Four Table 4 5 Auxiliary Commands Detailed Description continued Command Code COM4 COM0 43210 Description Local Unlisten The Local Unlisten command generates the local message lun in the form of a pulse Execute Parallel Poll The Execute Parallel Poll command sets the local message Request Parallel Poll rpp The rpp message is cleared when the TLC enters either Controller Parallel Poll State CPPS or Controller Idle State
74. cal message is cleared A program can determine that the Parallel Poll operation is complete based on the condition of CO CO 1 when the poll is complete The response can be obtained by reading the contents of the CPTR The response is held in the CPTR until a GPIB command is transmitted or the TLC Controller function becomes inactive In response to IDY each device participating in the Parallel Poll drives one and only one GPIB DIO line its Parallel Poll response or PPRn active true or passive false while it drives the other lines passive false Since there are eight data lines and for each line there can be one response true or false for each device 2 lines device there are 16 possible responses The line that a device uses and how that device drives the line depends on how it was configured and whether its local individual status message ist is one or zero Thus each device on the GPIB can be configured to drive its assigned DIO line true if ist 1 and to drive the DIO line false if ist 0 or it can be configured to do exactly the opposite that is to drive the DIO line true if ist 0 and false if ist 1 The meaning of the value of ist whether one or zero is system dependent or device dependent Because the data lines are driven Open Collector during Parallel Polls more than one device can respond on each line The device or devices asserting the line true overrides any device asserting the line false The Controller must know in a
75. cates the status of the GPIB address and enable bits for the secondary address of the TLC if mode 2 addressing is used or the minor primary address of the TLC if dual primary addressing is used modes 1 and 3 If mode 1 addressing is used and only a single primary address is needed both the talk and listen addresses disable in this register If mode 2 addressing is used the talk and listen disable bits in this register must match those in ADRO Bit Mnemonic Description Tr EOI End or Identify Bit EOI indicates the value of the GPIB EOI line latched when a data byte is received by the TLC GPIB Acceptor Handshake AH function If EOI 1 the EOI line was asserted with the received byte EOI is cleared by pon or by using the Chip Reset auxiliary command 6r DTI Disable Talker 1 Bit If DTI is set the mode 2 secondary or mode 1 and 3 minor Talker is not enabled that is the TLC does not respond to a secondary address or minor primary talk address formed from bits AD 5 1 1 1 If DTI is cleared DTI 0 and the TLC received its primary talk address that is is in TPAS the secondary address is checked 5r DLI Disable Listener 1 Bit If DL1 1 the mode 2 secondary or mode 1 and 3 minor listen function is not enabled that is the TLC cannot be addressed to listen at the address specified by AD 5 1 1 1 If DL1 is cleared DL1 0 and the TLC received its primary listen address that is is in LPAS the secondary address is
76. cation illustration 2 8 optional equipment 1 3 parts list and schematic diagrams B 1 to B 7 theory of operation 6 1 to 6 6 with VMEbus computer illustration 2 7 GPIB TLC See Talker Listener Controller TLC GTL Go To Local command 4 26 GPIB 1014DP User Manual 1 4 National Instruments Corporation Index H handshake lines E 2 to E 3 hidden registers Address Register ADR 4 47 Address Register 0 ADRO 4 46 Address Register 1 ADR1 4 48 Auxiliary Register A AUXRA 4 41 to 4 42 Auxiliary Register B AUXRB 4 43 to 4 44 Auxiliary Register E AUXRE 4 45 End of String Register EOSR 4 49 Internal Counter Register ICR 4 38 Parallel Poll Register PPR 4 39 to 4 40 HLDA Holdoff on All Bit 4 42 HLDE Holdoff on END Bit 4 42 I ICR See Internal Counter Register ICR IEEE 488 standard 1 1 GPIB 1014DP capabilities 2 10 to 2 12 IEEE 1014 standard 1 1 GPIB 1014DP compliance levels 2 13 IFC interface clear line E 3 Immediate Execute Pon command codes for 4 30 description 4 32 IMRI See Interrupt Mask Register 1 IMRI initialization of GPIB 1014DP 5 1 to 5 2 INITIALIZE INIT sample program C 5 to C 6 installation cabling 3 12 hardware installation tests 7 2 to 7 3 prerequisites for 3 1 unpacking the GPIB 1014DP 1 3 verification of system compatibility 3 8 to 3 11 verification testing 3 11 INT Interrupt Bit 4 15 to 4 16 INTERFACE CLEAR IFC sample program C 7 interface managem
77. ccur on the respective event Remember however that the status bits and interrupt signals are cleared when the ISR1 is read so the absence of a true DO or DI status does not indicate that the CDOR is still full or that the DIR is still empty National Instruments Corporation 5 7 GPIB 1014DP User Manual Programming Considerations Section Five Sending Receiving END or EOS The GPIB END message is sent by issuing the Send EOI auxiliary command just before writing the last data byte to the CDOR The GPIB EOS message is sent simply by making the last byte written to the CDOR the End Of String EOS code The END status bit or interrupt is used to inform the program of the receipt of an END or EOS message Interrupts The interrupt circuitry of the GPIB 1014DP allows the board to interrupt the CPU to request service Prior to use the following three characteristics of the interrupter must be set see Interrupt Request Line Selection in Section Three for details e The interrupt request IRQ line is selected via a hardware jumper e The interrupt priority is determined by three switches e The encoded value of the switches must match the interrupt request line A Status ID byte is set by an 8 switch DIP This byte is used by the operating system to determine the appropriate interrupt handler The uPD7210 TLC is the only source of interrupts on each port The TLC generates interrupts on any of the 13 conditions specified by the ISR
78. cepted signal By programming the TLC to Listen or not Listen via the ADMR NDAC can be asserted or not asserted respectively DIO1 is the GPIB Data Input Output bit 1 LSB By programming the TLC as active GPIB Controller and sending command bytes using the CO bit the CDOR DIO1 can be asserted and unasserted for testing GPIB 1014DP User Manual 6 6 National Instruments Corporation Section Seven GPIB 1014DP Diagnostic and Troubleshooting Test Procedures This section contains test procedures for determining if the GPIB 1014DP is installed and operating correctly The tests are similar to those used by National Instruments to verify correct hardware functioning This method programs specific internal functions by writing to one or more registers then reading other registers to confirm that the functions were implemented A user must have available an appropriate mechanism for writing to and reading from memory locations A program such as an interactive control program console emulator monitor or program debugger is ideal for this purpose Interpreting Test Procedures The following test procedures are written in the form of simple equations The left side of the equation contains the hexadecimal address offset from the GPIB 1014DP base address and mnemonic for the register The right side of the equation contains a hex value Converting the hex value to binary results in a representation of the bit pattern in the register For exa
79. checked 4 Or AD 5 1 1 1 Mode 2 Secondary TLC GPIB Address Bits 5 1 through 1 1 These are the lower five bits of the TLC secondary or minor address The secondary address is formed by adding hex AO to bits AD 5 1 1 1 The minor talk address is formed by adding hex 40 to AD 5 1 1 1 while the listen address is formed by adding a hex 20 GPIB 1014DP User Manual 4 48 National Instruments Corporation Section Four Register Descriptions End Of String Register EOSR VMEbus Address Base Address F hex Port A Base Address 1F hex Port B Attributes Write Only 7 6 5 4 3 2 1 0 EOS7 EOS6 EOS5 EOS4 EOS3 EOS2 EOS1 EOSO W The End of String Register EOSR holds the byte used by the TLC to detect the end of a GPIB data block transfer A 7 or 8 bit byte ASCII or binary can be placed in the EOSR to be used in detecting the end of a block of data The length of the EOS byte to be used in the comparison is selected by the BIN bit in AUXRA AUXRA 4 w If the TLC is a Listener and bit REOS of AUXRA is set the END bit is set in ISR1 whenever the byte in the DIR matches the EOSR If the TLC is a Talker and the data is being transmitted and XEOS bit of AUXRA is set the END message GPIB EOI line asserted low is sent along with the data byte whenever the contents of the CDOR matches the EOSR Bit Mnemonic Description 7 0w EOS 7 0 End of String Bits 7 through 0 National Instruments Corporation 4 49 GPIB 1014D
80. cleared Terminology The terms set set true and set to one are synonymous The terms clear set false set to zero and clear to zero are synonymous The meanings of preset and reset are determined by the context in which they are used Bit signatures are written in uppercase letters GPIB 1014DP User Manual 4 2 National Instruments Corporation Section Four Register Bit Descriptions The term addressed means the interface has been configured to perform a function from the GPIB side while the term programmed means that it has been configured from the VMEbus side This distinction is important to make because many functions such as making the interface a Talker or Listener can be activated from either side Where it is necessary to specify a particular bit of a register the bit position appears as a decimal number in square brackets after the mnemonic for example ISR1 1 indicates the DI bit of Interrupt Status Register 1 A minus sign is used to indicate logical negation An ampersand amp represents AND and a plus sign represents OR in logical expressions All numbers except register offsets are decimal unless specified otherwise Register offsets are given in hexadecimal Uppercase mnemonics are used for control status data registers register contents and interface functions as well as GPIB remote messages commands and logic states as defined in the IEEE 488 standard After a mnemonic of a name has be
81. cteristics The following paragraphs describe both modules on the GPIB 1014DP slave and interrupter Table 2 3 later in this section summarizes the capabilities of these modules VMEbus Slave A ddressing The GPIB 1014DP occupies 32 bytes of consecutive memory addresses located in the A 16 short Input Output I O space These addresses are used to access the two GPIB Talker Listener Controller TLC integrated circuits As a VMEbus slave it only responds when the address modifier AM lines specify a short supervisory access AM code 2D or a short non privileged access AM code 29 An onboard jumper allows selection of privileged or non privileged access to the board GPIB 1014DP User Manual 2 2 National Instruments Corporation Section Two General Description The board responds to 16 bit addresses It compares address lines A05 through A15 with its hardware programmable base address see Base Address in Section Three to generate its board select signal Address line A04 is used to select between GPIB Port A A04 0 and Port B A04 1 The TLCs decode the remaining address lines A01 through A03 and the data strobe DSO into eight memory mapped interface register addresses per port The GPIB TLC uPD7210 interface registers are addressed relative to the base address of the board as shown in Table 2 2 Table 2 2 uPD7210 Internal GPIB Interface Registers Address base hexoffset Register Port A Port B Data In DIR
82. cycles refer to ANSI IEEE Std 1014 1987 IEEE Standard for a Versatile Backplane Bus VMEbus An LS74A D type flip flop and an LS393 dual 4 bit counter implement a state machine to control the timing during Read Write cycles The timing control begins when STRT becomes true If the VMEbus signal WRITE is false indicating a read cycle either the TLC RDA or the RDB signal is driven true and the data bus drivers are enabled immediately The state machine then uses the VMEbus utility SYSCLK to count a minimum delay of 250 nsec which corresponds to the read access time of the TLC At this time the local signal LDTACK becomes true signaling the DTACK assert release circuitry to drive the VMEbus signal DTACK low This indicates that valid data is present on the data bus The data remains valid until DSO is released at which time the signals DEN and LDTACK go high The DTACK assert release circuitry releases DTACK once it sees that the bus driver has been released DEN is high and that DS1 is high The state machine then delays for a recovery time of 250 nsec The timing control for a write operation is similar to a read operation When STRT and the VMEbus signal WRITE are true either the TLC WRA or the WRB signal is driven true and the data bus receivers are enabled immediately The state machine counts a data setup time of 250 nsec before driving the WR signal false and asserting LDTACK thus asserting DTACK Data is latched into th
83. d only registers are placed on the IEEE 1014 bus in a minimum access time after TLC CS and RD are both true Most of the TLC GPIB interface functions can be implemented or activated from either side that is the TLC can be programmed to do these functions by the VMEbus master or it can be addressed to do them by the GPIB Controller In terms of the IEEE 488 standard the distinction between these two modes of operation is generally the same as that between local and remote interface messages respectively The ADSR is the primary register for monitoring the current status of the TLC that is to determine if it is a GPIB Talker GPIB Listener GPIB Active Controller or in GPIB remote or local mode The CPTR provides a means to read the GPIB data bus directly and is used to recognize interface messages that are not automatically decoded and implemented by the TLC The Address Register ADR is used to program two address registers ADRO and ADRI which contain the GPIB addresses recognized by the TLC and Talker and Listener disabling bits The manner in which the TLC uses these registers depends on the address mode established in the ADMR A bit in ADRI indicates if END was set on the last byte received IMRI and IMR2 are interrupt mask registers for enabling and disabling the interrupt from the TLC on the occurrence of 13 specific GPIB conditions or events The status of these conditions can be read from the ISR1 and ISR2 registers The status b
84. d pass through feature is enabled by the CPT ENABLE bit AUXRB 0 w Any GPIB command message not decoded by the TLC is treated as an undefined command for example the Go To Local command GTL However any addressed command is automatically ignored when the TLC is not addressed Undefined commands are read using the CPTR The TLC holds off the GPIB Acceptor Handshake in the Accept Data State ACDS until the Valid auxiliary command function code octal 017 is written to the AUXMR If the CPT feature is not enabled undefined commands are simply ignored Address Pass Through Bit Address Pass Through Interrupt Enable Bit APT is set by ADMI amp ADMO amp TPAS LPAS amp SCG amp ACDS APT is cleared by pon Read ISR1 4 10 National Instruments Corporation Section Four Bit 5r Sw 4r 4w Mnemonic DET DET IE END RX END IE Register Bit Descriptions Description Notes ADMI Address Mode Register bit 1 ADMR 1 w ADMO Address Mode Register bit 0 ADMR 0 w TPAS GPIB Talker Primary Addressed State LPAS GPIB Listener Primary Addressed State SCG GPIB Secondary Command Group ACDS GPIB Accept Data State pon power on reset Read ISR1 Bitis cleared immediately after it is read The APT bit indicates that a secondary GPIB address has been received and is available in the CPTR for inspection Note The application program must check this bit when using TLC address mode 3 When APT is set
85. der to read the status byte Responding to a Serial Poll The CIC can conduct Serial Polls to determine which device is asserting the GPIB SRQ signal to request service Before requesting the service the recommended practice is to wait until the PEND bit in the SPSR is zero indicating that the TLC is not presently in the middle of a Serial Poll SPAS 0 If PEND 0 write the desired Status Byte STB into the SPMR with the rsv bit set At that time PEND sets and remains set until the Serial Poll completes Once rsv is set the TLC waits until any current Serial Poll is complete and then asserts the GPIB SRQ signal In response to that signal the CIC starts the poll addressing the TLC to talk When the CIC unasserts ATN the TLC unasserts SRQ and transfers the STB message onto the GPIB data bus with DIO7 the RQS signal asserted While the Serial Poll is in progress SPAS 1 the CIC normally reads the STB only once however it can read it any number of times provided that it asserts ATN between each one byte read RQS is set only during the first read After the first read rsv also is cleared PEND is cleared when the CIC asserts ATN to terminate the poll The GPIB EOI line is asserted along with the status byte that is the END message is sent during the serial poll if bit B1 of the AUXRB is set National Instruments Corporation 5 9 GPIB 1014DP User Manual Programming Considerations Section Five Parallel Polls Parallel Pol
86. dvance whether a true response means the local ist message of the device is one or zero To do this the device must be configured to respond in the desired way Two methods can be used to accomplish this GPIB 1014DP User Manual 5 10 National Instruments Corporation Section Five Programming Considerations e Local configuration Parallel Poll function subset PP2 involves assigning a response line and sense from the device side in a manner similar to assigning the device GPIB address Thus one device might be assigned to respond with remote message PPR1 driving DIO1 while a second device might be assigned to respond with the remote message PPR3 driving DIO3 both positive that is true response if ist 1 Local configuration is static in that it does not change after the system is integrated that is hardware configured and installed e Remote configuration Parallel Poll function subset PP1 involves the dynamic assigning of the response line and sense to devices on the GPIB This is accomplished using Parallel Poll Enable PPE and Parallel Poll Disable PPD commands which are issued by the Active Controller The sequence for remotely configuring devices on the GPIB is as follows 1 Become Active Controller Send the GPIB UNL message to unaddress all GPIB Listeners Send the listen address of the first device to be configured Pr 9 Send the GPIB PPC message to all devices followed by the PPE message for that device 5 Repe
87. e Write a byte Check for a GPIB error Loop until all bytes are transferred On an error set d0 to 1 Status on return The dO register contains the number of bytes transferred or a 1 to indicate an error C 13 GPIB 1014DP User Manual Sample Programs DSEND1 movb ISR1 L d2 btst DO ERR d2 beq DSEND1 btst ERR d2 bne DSEND3 subl 1 d1 bmi DSEND4 bne DSEND2 cmpb 0 vseoi L beq DSEND2 movb SEOI AUXMR L DSEND2 movb a0 CDOR L bra DSEND1 movb DMAO IMR2 DSEND3 movl 1 d0 DSEND4 movl a6 8 d2 movl a6 4 d1 unlk a6 GPIB 1014DP User Manual Appendix C Comments Link Save d1 Save d12 Copy byte count Wait for CDOR or ERR Look for error dec byte counter Have all bytes been sent No Is this last byte Yes EOI in use No Send EOI with last byte Next byte Enable DMA to the CDOR Return 1 indicating error Restore d2 Restore d1 Unlink Return C 14 National Instruments Corporation Appendix C National Instruments Corporation Sample Programs kK KR Kk k KK WRITE kK Kk Kk k k KK Summary Called to send device dependent data messages when the GPIB 1014DP is Controller In Charge DSEND is called when the interface is Idle Controller Assumptions on entry GPIB 1014DP is CIC One Listener is addressed and its address is placed in the variable
88. e 4 2 Writing to the Hidden Registers eese nennen 4 6 Figure E 1 GPIB Connector and the Signal Assignment i E 4 Figure E 2 Linear Configuration ulisse E 5 Ligure E 3 Star C onfi s rati on noon t Def oe uh palla Diana E 6 Tables Table 2 1 GPIB 1014 DP Signals ucraina 2 1 Table 2 2 uPD7210 Internal GPIB Interface Registers i 2 3 Table 2 3 GPIB 1014DP IEEE 488 Interface Capabilities eene 2 10 Table 2 4 GPIB 1014DP IEEE 1014 Interrupter Compliance Levels 2 13 Table 3 1 GPIB 1014DP Pin Assignment on VMEbus Connector Pl 3 8 Table 3 2 GPIB 1014DP Pin Assignment on VMEbus Connector P2 3 10 Table 4 1 GPIB 1014DP Register Map casais suas reiterata aves eene Rte eques 4 1 Table 4 2 Clues to Understanding Mnemonics essere 4 3 Table 4 3 Multiline GPIB Commands Recognized by the UPD7210 esses 4 26 Table 4 4 Auxiliary Command Summary esses ener nennen nennen 4 30 Table 4 5 Auxiliary Commands Detail Description eene en 4 32 GPIB 1014DP User Manual x National Instruments Corporation Section One General Information The GPIB 1014DP consists of two IEEE 488 interfaces for the VMEbus on a single VME card This interface permits IEEE 488 compatible engineering scientific or medical instruments to be controlled fr
89. e Bit 4 17 DMAO DMA Out Enable Bit 4 17 DO Data Out Bit 4 13 DO IE Data Out Interrupt Enable Bit 4 13 documentation abbreviations used in the manual vi related documents E 7 vi don t care bits definition 4 2 DT Disable Talker Bit 4 47 DTO Disable Talker 0 Bit 4 46 DT1 Disable Talker 1 Bit 4 48 National Instruments Corporation L3 GPIB 1014DP User Manual Index E electrical characteristics See physical and electrical characteristics END IE End Received Interrupt Enable Bit 4 11 to 4 12 End of String Register EOSR 4 49 END or EOS sending receiving 5 7 END RX End Received Bit 4 11 to 4 12 EOI End or Identify Bit 4 48 EOI End or Identify line E 3 EOS 7 0 End of String Bits 7 through 0 4 49 EOSR See End of String Register EOSR ERR Error Bit 4 12 to 4 13 ERR IE Error Interrupt Enable Bit 4 12 to 4 13 Execute Parallel Poll command codes for 4 31 description 4 36 F features of GPIB 1014DP 1 1 Finish Handshake FH command 4 7 codes for 4 30 description 4 33 G GET Group Execute Trigger command 4 27 Go To Standby command codes for 4 31 description 4 34 GPIB Controller See Controller function GPIB 1014DP block diagram 2 9 capabilities 2 10 to 2 12 contents of kit 1 3 definition v features of 1 1 functional description 2 6 to 2 12 IEEE 1014 compliance levels 2 13 illustration 1 2 major components of 2 9 to 2 10 in multiprocessor appli
90. e GPIB interface board and its software your personal computer plays all three roles e Controller to manage the GPIB e Talker to send data e Listener to receive data The Controller In Charge and System Controller Although there can be multiple Controllers on the GPIB only one Controller at a time is active or Controller In Charge CIC Active control can be passed from the current CIC to an idle Controller Only one device on the bus the System Controller can make itself the CIC The GPIB interface board is usually the System Controller GPIB Signals and Lines The interface system consists of 16 signal lines and eight ground return or shield drain lines The 16 signal lines are divided into the following three groups e Eight data lines e Three handshake lines e Five interface management lines Data Lines The eight data lines DIO1 through DIOS carry both data and command messages All commands and most data use the 7 bit ASCII or ISO code set in which case the eighth bit DIOS is unused or used for parity Handshake Lines Three lines asynchronously control the transfer of message bytes among devices The process is called a three wire interlocked handshake and it guarantees that message bytes on the data lines are sent and received without transmission error NRFD not ready for data NRFD indicates when a device is ready or not ready to receive a message byte The line is driven by all devices when receiving comm
91. e TLC on the trailing edge of the WR signal The DTACK signal remains asserted until the bus master releases DSO and DS1 and the F245 releases the VME data bus After a recovery time of 250 nsec the state machine is ready to begin the next operation Accesses to the GPIB 1014DP during this recovery time are recognized but are delayed until the recovery time has elapsed Interrupter Logic The interrupter circuitry permits the GPIB 1014DP to request service The circuitry consists of four flip flops two F85 4 bit magnitude comparators two 25 nsec digital delay gates and some miscellaneous gates National Instruments Corporation 6 3 GPIB 1014DP User Manual Theory of Operation Section Six When a TLC drives its INT line the interrupter immediately pulls one of the interrupt request lines low see VMEbus Interrupt Request Line in Section Three An F85 comparator compares the address lines A01 through A03 with the priority you selected on U27 and sets the A B output high if there is a match during an interrupt acknowledge cycle The interrupt circuitry is duplicated for each port If Port A and Port B use the same priority code Port A will be serviced first Note The priority you select must match the interrupt request line see Interrupt Request Priority in Section Three The VME signal AS is delayed 25 nsec to allow the comparator output to stabilize This delayed signal then clocks the result of the comparison AS is delayed an
92. e addresses assures that the proper address will be present at the TLC for internal decoding when addresses are pipelined Address Decoding The GPIB 1014DP occupies a 32 byte space you determine the base address by setting the jumpers at W4 see Section Three Configuration and Installation The GPIB 1014DP only responds if the address modifier codes indicate 16 bit addressing This code is either 29 or 2D depending on whether you choose supervisory or non privileged access An onboard jumper selects the access mode see Access Mode in Section Three An F20 NAND gate an S02 NOR gate and two LS2521 8 bit comparators decode the GPIB 1014DP base address and address modifier codes When the base address is matched the address modifier codes indicate 16 bit addressing AMO through AMS 29 or 2D and LWORD and IACK are both high then both LS2521 outputs become true and the D input of flip flop U24 becomes high If one of these conditions is not met then the D input is low The signal AS 25 clocks the result of the decoding circuitry AS 25 is the address strobe signal delayed 25 nsec The delay assures that the decoding has been completed and the result is valid The clocked output signal is labeled MCYC If MCYC is false the GPIB 1014DP is prevented from taking any action until a new address cycle begins If MCYC is true the GPIB 1014DP is able to respond if DSO goes low DS1 is not monitored for the purpose of distinguishing 16 bit trans
93. e certain the VME data bus has been released before beginning a data transfer FTTL gates drive IRQ1 through IRQ7 DTACK and IACKOUT The DTACK and IRQ drivers have open collector outputs The GPIB 1014DP does not drive the other control signals National Instruments Corporation 6 1 GPIB 1014DP User Manual Theory of Operation Section Six Two onboard signals LDTACK and IDTACK determine the control of DTACK The Read Write State Machine drives LDTACK which is used during read and write cycles while the interrupter circuitry controls IDTACK which is used during Status ID cycles DTACK is asserted when either of these signals is true DTACK is released when both LDTACK and IDTACK are false and DSO and DS1 are both high Since the GPIB 1014DP does not request control of the bus the VMEbus daisy chain bus grant signals BGOIN through BG3IN are connected directly to the corresponding BGOOUT through BG30UT lines Address Lines Two LS2521 comparators receive VMEbus address lines A05 through A15 and the address modifier lines AM4 AM3 AMI and AMO for decoding An FTTL gate receives AMS AM2 and LWORD which are also used in decoding An ALS244 buffer receives address lines A01 through A04 These addresses are latched when AS goes high provided the GPIB 1014DP is not active in a data transfer cycle by holding MDTACK low The GPIB 1014DP holds MDTACK true while it is driving the VMEbus signal DTACK Latching thes
94. e lines E 2 DAV data valid E 3 NDAC not data accepted E 2 NRED not ready for data E 2 interface management lines E 3 ATN attention E 3 EOI end or identify E 3 IFC interface clear E 3 REN remote enable E 3 SRQ service request E 3 VMEbus signals chart of 2 1 to 2 2 operation 6 1 to 6 2 slave addressing VMEbus 2 2 to 2 3 slave data VMEbus 2 4 SPD Serial Poll Disable command 4 27 GPIB 1014DP User Manual I 10 National Instruments Corporation Index SPE Serial Poll Enable command 4 27 specifications electrical characteristics 2 1 to 2 2 IEEE 488 bus transfer rate A 1 operating environment A 1 physical characteristics A 1 2 1 power requirement A 1 storage environment A 1 SPEOI Send Serial Poll EOI Bit 4 44 SPMR See Serial Poll Mode Register SPMR SPMS Serial Poll Mode State Bit 4 21 SPSR See Serial Poll Status Register SPSR SRQ service request line E 3 SRQI Service Request Input Bit 4 16 to 4 17 SRQI IE Service Request Input Interrupt Enable Bit 4 16 to 4 17 standards for GPIB 1 1 storage environment A 1 Supervisor or Supervisor and User access configuration 3 3 switches See jumpers and switches system reset clock and reset circuitry 6 3 during initialization 5 1 to 5 2 T TA Talker Active Bit 4 22 Take Control Asynchronously Pulsed command codes for 4 30 description 4 34 Take Control Synchronously command codes for 4 30 description 4 35
95. ed to determine whether the information in the other ADSR bits applies to the TLC major or minor Talker Listener function MJMN is set to 1 when the TLC GPIB minor Talk address or minor Listen address is received MJMN is cleared on receipt of the TLC major Talk or major Listen address Note Only one Talker Listener can be active at any one time Thus the MJMN bit indicates which if either of the TLC Talker Listener functions is addressed or active MJMN is always zero unless a dual primary addressing mode Mode 1 or Mode 3 is enabled see Address Mode Register later in this section 4 22 National Instruments Corporation Section Four Register Bit Descriptions Address Mode Register ADMR VMEbus Address Attributes Base Address 9 hex Port A Base Address 19 hex Port B Write Only 7 6 5 4 3 2 1 0 W Bit Tw 6w 5 Aw Mnemonic ton lon TRM 1 0 Description Talk Only Bit Setting ton programs the TLC to be a GPIB Talker If ton is set the lon ADM1 and ADMO bits must be cleared This method must be used in place of the addressing method when the TLC will be only a Talker Note Clearing ton does not by itself take the TLC out of GPIB Talker Active state TACS It is also necessary to execute the Chip Reset or Immediate Execute pon auxiliary command Listen Only Bit Setting lon programs the TLC to be a GPIB Listener If lon is set ton ADM1 and ADMO should be cleared Note
96. en defined the mnemonic is used thereafter Appendix F contains a list of all mnemonics used in this manual along with their type and name Mnemonics are assigned to messages states registers bits functions and integrated circuits Most mnemonics contain a clue to their meaning Table 4 2 contains a list of clues to look for Table 4 2 Clues to Understanding Mnemonics Mnemonic Probably Stands For Ends in IE Interrupt enable bit Ends in EN Enable bit 4 letters Interface function as defined in the ends in S IEEE 488 standard Ends in R RO R1 R2 GPIB program register 3 letters uppercase Remote GPIB message 3 letters lowercase Local GPIB message National Instruments Corporation 4 3 GPIB 1014DP User Manual Register Bit Descriptions Section Four Interface Registers All program registers for each port are GPIB interface registers eight are read only eight are write only and five are hidden or indirectly accessible All are located within the NEC uPD7210 Talker Listener Controller TLC integrated circuit Each of the 32 interface registers is addressed relative to the GPIB 1014DP VMEbus base address which is set with jumper switches refer to Base Address in Section Three Figure 4 1 shows the uPD7210 Interface registers the bit mnemonics of each its read write accessibility and its relative address Figure 4 2 shows the hidden GPIB interface registers and illustrates the method of writing to those registe
97. ent lines E 3 interface registers Address Mode Register ADMR 4 23 to 4 25 Address Status Register ADSR 4 21 to 4 22 Auxiliary Mode Register AUXMR 4 29 to 4 36 Command Data Out Register CDOR 4 8 Command Pass Through Register CPTR 4 26 to 4 28 Data In Register DIR 4 7 hidden registers Address Register ADR 4 47 National Instruments Corporation L5 GPIB 1014DP User Manual Index Address Register 0 ADRO 4 46 Address Register 1 ADR1 4 48 Auxiliary Register A AUXRA 4 41 to 4 42 Auxiliary Register B AUXRB 4 43 to 4 44 Auxiliary Register E AUXRE 4 45 End of String Register EOSR 4 49 Internal Counter Register ICR 4 38 overview 4 37 Parallel Poll Register PPR 4 39 to 4 40 Interrupt Mask Register 1 IMR1 4 9 to 4 14 Interrupt Status Register 1 ISR1 4 9 to 4 14 Interrupt Status Register 2 ISR2 4 15 to 4 19 uPD7210 interface registers illustration 4 5 overview 4 4 Serial Poll Mode Register SPMR 4 20 Serial Poll Status Register SPSR 4 20 writing to hidden registers 4 6 Internal Counter Register ICR 4 38 interrupt configuration VMEbus interrupt priority code 3 5 to 3 6 interrupt request line selection 3 4 to 3 5 overview 3 4 Interrupt Mask Register 1 IMR1 4 9 to 4 14 interrupt status ID vector selection configuring 3 6 to 3 7 Interrupt Status Register 1 ISR1 4 9 to 4 14 Interrupt Status Register 2 ISR2 4 15 to 4 19 interrupter definition 2 10 description of 2 4 to
98. etting ISS ties the Parallel Poll function to the Service Request function and also to the Serial Poll process The particular response sent by the port during a Parallel Poll is determined by the value of ist and the configuration of the port The value of ist and the actual configuration must be decided by the GPIB system integrator The response can be changed dynamically during program execution by changing the value of ist and when remote configuration is used by reconfiguration National Instruments Corporation 5 11 GPIB 1014DP User Manual Section Six Theory of Operation This section discusses the major elements of the GPIB 1014DP in detail with references to signals and circuits shown in the schematic diagrams in Appendix B However a brief description of the GPIB 1014DP interface with a functional block diagram is provided in Section Two see Figure 2 4 Signal names in the following discussion are referenced in terms of logic value true or false and asserted or not asserted and also in terms of logic level TTL high or low Both positive and negative logic symbols are used in the schematic diagram The terms clear negate unassert reset and set false are synonymous as are set assert and set true Since in the circuit implementation some positive true signals are derived from the inverted output of flip flops these terms are not synonymous with the device signals CLR clear and PR preset Much of the circuitry fo
99. fers from 8 bit transfers so the GPIB 1014DP responds to BYTE 0 1 or BYTE 2 3 accesses The upper byte is not used during a write cycle and returns a hex value of FF during a read cycle When the master releases AS MCYC is cleared and the GPIB 1014DP is ready for a new data transfer cycle GPIB 1014DP User Manual 6 2 National Instruments Corporation Section Six Theory of Operation Clock and Reset Circuitry An LS240 receives the 16 MHz utility SYSCLK provided on the VMEbus The Read Write State Machine uses the 16 MHz clock to control the timing of the signal DTACK and the TLC inputs RDA RDB WRA and WRB see Timing Control Logic This clock is divided to 8 MHz for the CLOCK signal used by each TLC The VMEbus signal SYSRESET initializes two TLCs the interrupter and the timing control circuitry Timing Control Logic When the GPIB 1014DP is addressed see Address Decoding in this section AS 25 clocks the local signal MCYC true If another module is asserting DTACK when MCYC becomes true that is the address is pipelined to the GPIB 1014DP the GPIB 1014DP waits for DTACK to be released and for DSO to be asserted The GPIB 1014DP then asserts STRT after delaying a minimum of 85 nsec in order to meet the TLC address set up time If DSO is never asserted the cycle is an Address Only ADO cycle In this case MCYC is cleared when AS goes high and the GPIB 1014DP takes no further action For more information on ADO
100. g these two messages MTA and TCT automatically becomes CIC when ATN is dropped The exact sequence of events is as follows 1 The TLC receives the My Talk Address MTA The TLC then enters into Talker Addressed State TADS This operation can be transparent to a program The Talker Active TA bit in the Address Status Register ADSR is set when the TLC receives its GPIB talk address 2 The TLC receives the GPIB TCT message GPIB 1014DP User Manual 5 2 National Instruments Corporation Section Five Programming Considerations Note Normally a program does not have to read or respond to the TCT command message but it can read the TCT message in the Command Pass Through Register CPTR in response to the assertion of the CPT status bit in Interrupt Status Register 1 ISR1 assuming that the CPT ENABLE bit of AUXRB has been previously set 3 The current Active Controller sees the completed handshake goes to idle and unasserts ATN 4 As soon as the ATN line on the GPIB is unasserted the TLC automatically becomes CIC and asserts ATN As soon as the TLC becomes CIC the CIC bit in the ADSR and the Command Output CO bit in Interrupt Status Register 2 ISR2 are set Using these two bits the program can unambiguously determine that the TLC is the GPIB Active Controller and can send remote messages Sending Remote Multiline Messages Commands A GPIB 1014DP port sends commands as Active Controller simply by writing to the C
101. h PPR 0 and by ist If U 1 the TLC does not participate in a Parallel Poll The U bit is equivalent to the local message lpe local poll enable active low When U 0 S and P3 1 mean the same as the bit of the same name in the PPE message and the I O write operation to the PPR is the same as the receipt of the PPE message from the GPIB Controller When U 1 S and P3 1 do not carry any meaning but they must be cleared National Instruments Corporation 4 39 GPIB 1014DP User Manual Register Descriptions Section Four Bit Mnemonic Description 3w S Status Bit Polarity Bit The S bit is used to indicate the polarity of the TLC local ist individual status message If S 1 the status is in phase meaning that if during a Parallel Poll response S ist 1 and U 0 the TLC responds to the Parallel Poll by driving one of the eight GPIB DIO lines low thus asserting it to a logic one If S 1 and ist 0 the TLC does not drive the DIO line If S 0 the status is in reverse phase meaning that if during a Parallel Poll ist 0 and U is 0 the TLC responds to the Parallel Poll by driving one of the eight GPIB DIO lines low If S 0 and ist 1 the TLC does not drive the DIO line Refer to the description of AUXRB and the Set Clear auxiliary commands for more information 2 0w P 3 1 Parallel Poll Response Bits 3 through 1 PPR bits 3 through 1 designated P 3 1 contain an encoded version of the Parallel Poll Response P 3 1 indicate wh
102. he TLC is a Talker or Active Controller and low when it is a Listener Controlling the direction of the ATN and SRQ signals T R2 is high when the TLC is Controller In Charge CIC and low otherwise T R3 is high when the three state driver mode is active and low when the open collector mode is active When the GPIB 1014DP is parallel polled the transceiver switches to open collector mode SC is set whenever the System Controller Select logic senses that the TLC has received the Set IFC auxiliary command SC is cleared when the TLC receives the Release System Control auxiliary command SC controls the direction of the IFC and REN signals driving the GPIB when SC is high and receiving from the GPIB when it is low National Instruments Corporation 6 5 GPIB 1014DP User Manual Theory of Operation Section Six Test and Troubleshooting The GPIB 1014DP is designed to aid acceptance testing and troubleshooting of either hardware failures or software bugs The hardware provides several features that enable stand alone testing The NDAC and DIO1 bits can be used to determine if the output signals of the TLC the 75160A and the 75162A are functioning properly Since most failures including problems with short or open circuits on the PWB prevent the TLC from working at all this test gives limited assurance that the TLC and its associated circuitry are working and that the output signals can be manipulated properly NDAC is the GPIB Not Data Ac
103. he GPIB handshake without setting the Data In DI bit Then issue gts When Holdoff occurs the TLC can take control synchronously This means that the Talker must finish its transmission with the END or EOS message It can then take control synchronously when necessary Note The Take Control Synchronously on End tcse auxiliary command can be issued after gts thereby causing the TLC to automatically take control synchronously on holdoff National Instruments Corporation 5 3 GPIB 1014DP User Manual Programming Considerations Section Five Going from Standby to Active Controller The manner in which the TLC resumes GPIB Active Control depends on how it went to standby Consider the three cases Case 1 The TLC as a Talker takes control upon receipt of the Take Control Asynchronously auxiliary command Do not issue the Take Control Asynchronously auxiliary command until there are no more bytes to send and the DO bit is set Case 2 The TLC as a Listener takes control upon receipt of the Take Control Synchronously auxiliary command If programmed I O is used the Take Control Synchronously auxiliary command should be issued between seeing a DI status bit and reading the last byte from the DIR Case 3 The TLC as neither Talker nor Listener takes control synchronously with the Take Control Synchronously auxiliary command after detecting the END RX bit set in ISRI This indicates that a holdoff is in progress When the Take Contro
104. hey can be cleared or reset to initialized conditions only by issuing the Chip Reset auxiliary command or by a pon Figure 4 2 earlier in this section shows the five hidden registers and illustrates how they are loaded with data from the AUXMR National Instruments Corporation 4 37 GPIB 1014DP User Manual Register Descriptions Section Four Internal Counter Register ICR VMEbus Address Base Address B hex Port A Base Address 1B hex Port B AUXMR Control Code 001 Binary Bits 7 5 Attributes Write Only Accessed through AUXMR 4 3 2 1 0 gt Tas Tee Tee as W Bit Mnemonic Description 4w 0 Reserved Bit Write zero to this bit 3 0w CLK 3 0 Clock Bits 3 though 0 The contents of the ICR are used to divide internal counters that generate TLC state change delay times used by the IEEE 488 specification The most familiar of these times T1 is the minimum delay between placing the data or command bytes on the GPIB DIO lines and asserting DAV These delay times vary depending on the type of transfer in progress and the value of the AUXRB bit TRI For proper operation ICR should be set to eight because the TLC is clocked at 8 MHz GPIB 1014DP User Manual 4 38 National Instruments Corporation Section Four Register Descriptions Parallel Poll Register PPR VMEbus Address Base Address B hex Port A Base Address 1B hex Port B AUXMR Control Code 011 Binary Bits 7 5 Attributes Write On
105. his interrupt vector consists of eight bits labeled VO through V7 as shown in Figures 3 6a and 3 6b Bit V7 corresponds to the most significant bit while VO corresponds to the least significant Press the side labeled 0 to select a logical zero for the corresponding address bit Press the side labeled 1 to select a logical one Figure 3 6 shows the configuration for a status ID byte value 1A hex GPIB 1014DP User Manual 3 6 National Instruments Corporation Section Three Configuration and Installation This side down for logic 0 This side down for logic 1 12345678 o U34 a Status ID Byte 1A hex for Port B This side down for logic 0 This side down for logic 1 gt 12345678 0 b Status ID Byte 1A hex for Port A Figure 3 6 Status ID Byte 1A hex O National Instruments Corporation 3 7 GPIB 1014DP User Manual Configuration and Installation Section Three Installation The GPIB 1014DP is a double height board that interfaces to the VMEbus P1 and P2 connectors and is provided with a double height metal front cover plate with two GPIB connectors The top connector J1 is referred to as Port A while the lower connector J2 is Port B The following paragraphs describe the GPIB 1014DP interface to the VMEbus backplane and to the IEEE 488 bus Verification of System Compatibility The GPIB 1014DP monitors and drives those signals required by the IEEE 1014 Standard and is
106. his register and is not destroyed by a read of the DIR which is located at the same address When a byte is written to the CDOR the TLC GPIB Source Handshake SH function is initiated and the byte is transferred to the GPIB Bit Mnemonic Description 7 Ow CDO 7 0 Command Data Out Bits 7 through 0 GPIB 1014DP User Manual 4 8 National Instruments Corporation Section Four Register Bit Descriptions Interrupt Status Register 1 ISR1 VMEbus Address Base Address 3 hex Port A Base Address 13 hex Port B Attributes Read Only Bits are cleared when read Interrupt Mask Register 1 IMR1 VMEbus Address Base Address 3 hex Port A Base Address 13 hex Port B Attributes Write Only T 6 5 4 3 2 1 0 R C cer ae Der p ENDRX D amp c ERR 30 D ISRI is composed of eight interrupt status bits IMR1 is composed of eight interrupt enable bits which directly correspond to the interrupt status bits in ISR1 As a result ISR1 and IMRI service eight possible interrupt conditions where each condition has an interrupt status bit and an interrupt enable bit associated with it If the Interrupt Enable bit is true when the corresponding status condition or event occurs a hardware interrupt request is generated Bits in ISR1 are set and cleared by the TLC regardless of the status of the interrupt enable bits in IMRI If an interrupt condition occurs at the same time ISR1 is being read the TLC holds off setting the corresp
107. ia ai ei aste OR M ROM OS US 6 1 nume NE E HX dee 6 2 GPIB 1014DP User Manual viii National Instruments Corporation Contents Address Decoding 5 usen RO ia uso REAR IA Od et ne a dde 6 2 ire duni mici TP 6 3 Timing Control LOGIC ies et ttn E A ERN NEVER eA V PS FUNT URP ae AN eae 6 3 Interrupt E0910 505 tet top t Dn poU Ee tts i 6 3 GPIB Interf CO c 6 4 T stand Troubleshooting oos Ron 6 6 Section Seven GPIB 1014DP Diagnostic and Troubleshooting Test Procedures 7 1 Interpreting Test PEOCGHUIGS eet e titu e et een epe oes Sus ada 7 1 GPIB 1014DP Hardware Installation Tests essere 7 2 Appendix A Specifications ei PT TT A 1 Appendix B Parts List and Schematic Diagrams iii B 1 Appendix C Sample Programs 22b eaae iot ade Um arb unite tiens itta C 1 Appendix D Multiline Interface Command Messages sees D 1 Appendix E Operation of the GPIB ulivi E 1 pes Oil MICS SAGES LH HT E 1 Talkers Listeners and Controllers iii E 1 The Controller In Charge and System Controller ii E 2 GPIB Sicnals and CINES salare lalla ao E 2 Data anes c E E 2 Handshake Lines 2 einen rie Meteo iii peli E 2 NRED not ready for data ustedes ee tive oct pP eser ito E 2 NDAC not data accepted itas teste im esiti teases E 2 DAN data valid RT E 3 Interface Management Lines
108. ich of the eight DIO lines is asserted during a Parallel Poll equal to N 1 The GPIB 1014DP normally drives the GPIB DIO lines using three state drivers During Parallel Poll responses however the drivers automatically convert to Open Collector mode as required by IEEE 488 For example if P 3 1 010 binary GPIB DIO line DIO3 is driven low asserted if the GPIB 1014DP is parallel polled and S ist Some examples of configuring the Parallel Poll Register are as follows Written to the AUXMR 7 6 54 32 1 0 Result O 1 1 10000 Unconfigures PPR 01 100000 0 00 00 is written to the PPR GPIB 1014DP participates in a Parallel Poll asserting the DIO1 line if ist is 0 Otherwise the GPIB 1014DP does not participate O 1 1 O 1 00 I 0100 1 is written to the PPR GPIB 1014DP participates in a Parallel Poll asserting the DIO2 line if ist is 1 Otherwise the GPIB 1014DP does not participate GPIB 1014DP User Manual 4 40 National Instruments Corporation Section Four Register Descriptions Auxiliary Register A AUXRA VMEbus Address AUXMR Control Code Attributes Base Address B hex Port A Base Address 1B hex Port B 100 Binary Bits 7 5 Write Only Accessed through AUXMR 4 3 2 1 0 W Writing to Auxiliary Register A AUXRA is done via the AUXMR Writing the binary value 100 into the Control Code CNT 2 0 and a bit pattern into the Command Code portion COM 4 0 of the AUXMR causes the Command C
109. ins the address of the data buffer The user specified variable cic is set properly Actions Release any holdoff in progress Set up handshake holdoffs as r ired by Controller status cic Wait for GPIB END message or byte count If END set dO register to number of bytes received Holdoff handshake Status on return a NRFD handshake holdoff is in effect The number of bytes transferred is in bx bc C 9 GPIB 1014DP User Manual Sample Programs RCV1 RCV2 RCV3 RCV5 RCV6 68000 Code link movi movl movb tst beq movb bra movb clr movb btst beq btst bne movb addw cmpw bne bra movb movw movb movl movl unlk rts a6 4 d1 a6 4 d2 a6 8 FH AUXMR L b cic L RCV1 Comments Save d1 Appendix C Release any handshake holdoff in progress Is GPIB 1014DP Controller In Charge Save d2 AUXRA 0202 AUXMR L Yes Set HLDE and BIN in AUXRA RCV2 AUXRA AUXMR L di ISR1 L d2 END DI d2 RCV3 END d2 RCV5 DIR a0 1 d1 d0 d1 RCV3 RCV6 DIR a0 d1 d0 AUXRA 1 AUXMR L a6 8 d2 a6 4 d1 a6 GPIB 1014DP User Manual No Clear any HLDE or HLDA in effect Clear byte counter Read status Wait for GPIB END or DI Look for END Read byte More bytes to read Yes continue No exit END read last byte Record bytes
110. is used to locate the appropriate interrupt service routine The following paragraphs explain the actions that must be performed to configure the interrupt request line the interrupt priority and the status ID byte or interrupt vector of each port Interrupt Request Line Selection The VMEbus provides seven interrupt request lines IRQ1 to IRQ7 Each of the two GPIB ports can be configured to drive any one of these seven lines The jumpers shown in Figure 3 4 are used to connect the interrupt request from each port to a VMEbus interrupt request line The jumpers are placed on the pins that correspond to the desired interrupt request line for each port Note The interrupt priority code must be set to correspond to the interrupt request line Figure 3 4a shows both jumpers configured to select interrupt request line IRQ2 while Figure 3 4b shows the configuration changed to select IRQ4 for Port B The default setting for the GPIB 1014DP is IRQ2 for both ports GPIB 1014DP User Manual 3 4 National Instruments Corporation Section Three Configuration and Installation a Select Interrupt Request Line Configured to IRQ2 for both ports Default Setting a 7 b Select Interrupt Request Line Configured to IRQ2 for Port A and to IRQ4 for Port B Figure 3 4 VMEbus Interrupt Line Selection Note An asterisk implies that the signal is act
111. it 4 18 REMC IE Remote Change Interrupt Enable Bit 4 18 REMOTE ENABLE REN sample program C 8 REN remote enable line E 3 REOS END on EOS Received Bit 4 41 reset See system reset Return to Local rtl command codes for 4 30 description 4 33 RED Holdoff mode 4 7 4 42 RFD Ready for Data message 4 7 rsv Request Service Bit 4 20 S S Status Bit Polarity Bit 4 40 S8 Serial Poll Status Byte 4 20 sample programs 68000 code C 2 to C 4 COMMAND CMD C 18 COMMAND SEND CSEND C 17 National Instruments Corporation r9 Index GPIB 1014DP User Manual Index DATA SEND DSEND C 13 to C 14 INITIALIZE INIT C 5 to C 6 INTERFACE CLEAR IFC C 7 overview C 1 PASS CONTROL PASSC C 19 READ C 11 to C 12 RECEIVE RCV C 9 to C 10 REMOTE ENABLE REN C 8 WRITE C 15 to C 16 schematic diagrams B 1 to B 7 SDC Selected Device Clear command 4 26 Send EOI SEON command codes for 4 30 description 4 33 sending receiving messages 5 7 Serial Poll Mode Register SPMR 4 20 Serial Poll Status Register SPSR 4 20 serial polls conducting 5 8 responding to 5 8 Set IFC command codes for 4 31 description 4 36 Set Parallel Poll Flag command codes for 4 30 description 4 34 Set REN command codes for 4 31 description 4 36 SH Source Handshake 4 8 signals and lines data lines E 2 GPIB connector and signal assignment illustration E 4 GPIB 1014DP pin assignment on VMEbus connector P1 3 8 to 3 11 handshak
112. it Remote With Lockout State Status Bit Polarity Sense Bit Serial Poll Status Bits 8 and 6 through 1 System Control Active State Secondary Command Group Selected Device Clear Source Delay State Send EOI Serial Clock Serial Data Source Generate State Source Handshake System Control Interface Clear Active State Send Interface Clear Source Idle State System Control Interface Clear Idle State System Control Interface Clear Not Active State Source Idle Wait State F 7 GPIB 1014P User Manual Mnemonics Key Mnemonic Type SNAS ST SP F SPAS ST SPD RM SPE RM SPEOI B SPIS ST SPMR R SPMS B SPMS ST SPSR R SR F SRAS ST sre LM SRIS ST SRNS ST SRQ RM SRQI B SRQI IE B SRQS ST STB RM STRS ST STRT LS SWNS ST SYSCLK VBS SYSFAIL VBS SYSRESET VBS T T F TA B TACS ST TADS ST TAG RM tca LM tcs LM tcse LM TCT TM TDMA SX TE F TIDS ST TLC IC TLC CS LS TLC WR LS ton B ton LM TPAS B TPAS ST GPIB 1014P User Manual Appendix F Definition System Control Not Active State Serial Poll scanning flags Serial Poll Active State T function Serial Poll Disable Serial Poll Enable Send Serial Poll End Or Indentify Bit Serial Poll Idle State Serial Poll Mode Register Serial Poll Mode State Bit Serial Poll Mode State Serial Poll Status Register Service Request System Control Remote Enable Active State Send Remote Enable System Control Remote Enable Idle State System Control Remote En
113. its in these registers function independently of the corresponding mask bits that is they are set and cleared regardless of whether an interrupt request is enabled for the condition An important fact to remember is that ISRI and ISR2 are always cleared when read even if the condition which caused the bit to be initially set remains true Data to and from the GPIB is pipelined through the CDOR and DIR respectively An 8 MHz clock is used as the CLOCK input to the TLC For proper GPIB timing the internal counter register must be programmed to eight The AUXMR is used to issue special commands to the TLC and write to the five hidden registers The Parallel Poll Register PPR locally configures the TLC for polling Auxiliary Registers A B and E AUXRA B E provide a means to control a variety of diverse functions such as enabling handshake holdoffs transmitting END when the EOS byte is sent setting the END RX bit when EOS is received and enabling high speed transfers Two special purpose transceivers a 75160 for the data signals and a 75162 for the handshake and interface management signals interface the TLC to the GPIB Three signals from the TLC T R1 through T R3 and the SC signal from the System Controller Select logic control signal direction of these two transceivers The System Controller select logic provides an SC signal for each port SCA and SCB Controlling the direction of the data handshake and EOI signals T R1 is high when t
114. ive low Interrupt Priority Code An interrupt priority code is used to identify an interrupt acknowledge cycle intended for a GPIB 1014DP port Three bits IA1 through IA3 represent the interrupt priority code for Port A while bits IB1 through IB3 represent the interrupt priority code for Port B The encoded value of these three bits must correspond to the interrupt request line used 1 through 7 by the port I1 is the least significant bit Six switches located at U27 set these bits Press the side labeled 0 to select a logical zero for the corresponding address bit Press the side labeled 1 to select a logical one Figure 3 5a shows the switch configuration for using IRQ2 on both ports while Figure 3 5b shows the switch configuration for using IRQ4 on Port B and IRQ2 on Port A The default setting for Port B and Port A is IRQ2 National Instruments Corporation 3 5 GPIB 1014DP User Manual Configuration and Installation Section Three This side down for logic 0 This side down for logic 1 123456 0 a Port B using IRQ2 Port A using IRQ2 Default Setting This side down for logic 0 This side down for logic 1 e 123456 b Port B using IRQ4 Port A using IRQ2 Figure 3 5 VMEbus Interrupt Priority Code Selection Interrupt Status ID Vector Selection Switches located at U34 and U45 configure the interrupt status ID vector which is provided by each port during an interrupt acknowledge cycle T
115. l Synchronously auxiliary command is used the TLC takes control of the GPIB only at the end of a data transfer This implies that one transfer must follow or be in progress when the Take Control Synchronously auxiliary command is issued If this is not the case the Take Control Asynchronously auxiliary command must be used Of course the Take Control Asynchronously auxiliary command may be used in place of the Take Control Synchronously auxiliary command when the possibility of disrupting an in progress GPIB handshake before all GPIB Listeners have accepted the data byte is acceptable In Cases 2 and 3 the END IE bit in IMRI can also be set to indicate to the program that the TLC functioning as a GPIB Listener has received its last byte In all cases a CO status indicates that the GPIB 1014DP is now Active Controller Going from Active to Idle Controller Going from Active to Idle GPIB Controller also known as passing control requires that the TLC be the Active Controller initially in order to send the necessary GPIB command messages After the TLC has become the GPIB Active Controller it must complete the following procedures to pass control 1 Write the GPIB Talk address of the device being passed control to the CDOR 2 In response to the next CO status write the GPIB TCT message to the CDOR 3 As soon as the TCT command message is accepted by all devices on the GPIB the TLC automatically unasserts ATN and the new Controller as
116. l in case at standby Set up the command buffer The GPIB 1014DP automatically releases control when TCT is sent C 19 GPIB 1014DP User Manual Appendix D Multiline Interface Command Messages The following tables are multiline interface messages sent and received with ATN TRUE National Instruments Corporation D 1 GPIB 1014DP User Manual Multiline Interface Command Messages Appendix D Message Definitions DCL GET GTL LLO MLA GPIB 1014DP User Manual Oct Dec 000 0 001 1 002 2 003 3 004 4 005 5 006 6 007 7 010 8 011 9 012 10 013 11 014 12 015 13 016 14 017 15 020 16 021 17 022 18 023 19 024 20 025 21 026 22 027 23 030 24 031 25 032 26 033 27 034 28 035 29 036 30 037 31 Device Clear Multiline Interface Messages ASCII Msg Hex Oct Dec ASCII Msg NUL 20 040 32 SP MLAO SOH GTL 21 041 33 MLA1 STX 22 042 34 MLA2 ETX 23 043 35 MLA3 EOT SDC 24 044 36 MLA4 ENQ PPC 25 045 37 MLAS ACK 26 046 38 amp MLA6 BEL 27 047 39 MLA7 BS GET 28 050 40 MLAS8 HT TCT 20 051 41 MLA9 LF 2A 052 42 ni MLA10 VT 2B 053 43 MLA11 FF 2C 054 44 MLA12 CR 2D 055 45 MLA13 SO 2E 056 46 MLA14 SI 2F 057 47 MLAI5 DLE 30 060 48 0 MLA16 DCI LLO 31 061 49 1 MLA17 DC2 32 062 50 2 MLA18 DC3 33 063 SI 3 MLA19 DC4 DCL 34 064 n2 4 MLA20 NAK PPU 35 065 53 5 MLA2I SYN 36 066 54 6 MLA22 ETB 37 067 55 7 MLA23 CAN SPE 38 070 56 8 MLA24 EM SPD 39 071 57 9 MLA25 SUB 3A 072 58 MLA26 ESC 3B 073 59 MLA2
117. ld always be clear and should never be set INV 0 INT pin is active high INV 1 INT pin is active low National Instruments Corporation 4 43 GPIB 1014DP User Manual Register Descriptions Bit Mnemonic 2w TRI lw SPEOI Section Four Description Three State Timing Bit The TRI bit determines the TLC GPIB Source Handshake Timing T1 as defined in the IEEE 488 specifications TRI can be set to enable high speed data transfers when three state GPIB drivers are used The GPIB 1014DP uses three state GPIB drivers except during Parallel Poll responses in which case the GPIB drivers automatically switch to Open Collector Setting TRI enables timing during the GPIB Source Handshake function after transmission of the first byte Clearing TRI sets the T1 timing to low speed in all cases Send Serial Poll EOI Bit The SPEOI bit permits or prohibits the transmission of the END message in Serial Poll Active State SPAS If SPEOI is set EOI is sent true when the TLC is in SPAS otherwise EOI is sent false in SPAS Ow CPT ENABLE Command Pass Through Enable Bit GPIB 1014DP User Manual The CPT ENABLE bit permits or prohibits the detection of undefined GPIB commands and permits or prohibits the setting of the CPT bit ISR1 7 r on receipt of an undefined command When CPT ENABLE is set and an undefined command has been received the DAC message is held and the Handshake stops until the Valid auxiliary command is issued The undefi
118. ls are used by the GPIB Active Controller to check the status of several devices simultaneously The meaning of the status returned by the devices being polled is device dependent There are two general ways in which Parallel Polls are useful When the GPIB Controller sees SRQ asserted in a system with several devices it can quickly determine which one needs to be serially polled usually using only one Parallel Poll e Insystems in which the Controller response time requirement to service a device is low and the number of devices is small Parallel Polls can replace Serial Polls entirely provided that the Controller polls frequently Although the Controller can obtain a Parallel Poll response quickly and at any time there can be considerable front end overhead during initialization to configure the devices to respond appropriately This is contrasted with Serial Polls where the overhead in the form of addressing and enabling command messages occurs with each poll Conducting a Parallel Poll The TLC as Active Controller has the capability to conduct a Parallel Poll When the Execute Parallel Poll auxiliary command is issued and the TLC internal local message rpp is set the Parallel Poll is executed that is the GPIB message IDY is sent true as soon as the TLC Controller interface function is placed in the proper state CAWS or CACS The Parallel Poll Response PPR is automatically read from the GPIB DIO lines into the CPTR and the rpp lo
119. lso treated as undefined In such a case when an undefined GPIB message is encountered it is held in the CPTR and the TLC Acceptor Handshake function is held off in ACDS until the Valid auxiliary command is written to the AUXMR The CPTR is also used to inspect secondary addresses when mode 3 addressing is used The TLC Acceptor Handshake function is held off in ACDS until the Valid or Non Valid auxiliary command is written to the AUXMR Table 4 3 Multiline GPIB Commands Recognized by the uPD7210 Parallel Poll Configure continues 4 26 National Instruments Corporation Section Four Register Bit Descriptions Table 4 3 Multiline GPIB Commands Recognized by the uPD7210 continued MSA PPE My Secondary Address or Parallel Poll Enable MSA PPD My Secondary Address or Parallel Poll Disable National Instruments Corporation 4 27 GPIB 1014DP User Manual Register Bit Descriptions Section Four The CPTR is read during a TLC initiated Parallel Poll operation to fetch the Parallel Poll response The PPR message is latched into the CPTR when CPPS is set until CIDS is set or until a command byte is sent over the GPIB GPIB 1014DP User Manual 4 28 National Instruments Corporation Section Four Register Bit Descriptions Auxiliary Mode Register AUXMR VMEbus Address Base Address B hex Port A Base Address 1B hex Port B Attributes Write Only Permits Access to Hidden Registers 7 6 5 4 3 2
120. ly Accessed through AUXMR 4 3 2 1 0 W Writing to the Parallel Poll Register is done via the AUXMR Writing the binary value 011 into the Control Code CNT 2 0 and a bit pattern into the command code portion COM 4 0 of the AUXMR causes the command code to be written to the Parallel Poll Register PPR When COM 4 0 is written to the PPR the bits are named as shown above This 5 bit command code determines the manner in which the TLC responds to a Parallel Poll When using the remote Parallel Poll Configure IEEE 488 capability code PP1 do not write to the PPR The TLC implements remote configuration fully and automatically without software assistance The hardware recognizes interprets and responds to Parallel Poll Configure PPC Parallel Poll Enable PPE Parallel Poll Disable PPD and Identify IDY messages The user need only set or clear the individual status ist message using Set Clear Parallel Poll Flag auxiliary commands according to pre established system protocol convention Writing to the PPR after it is remotely configured will corrupt the configuration When using the local PPC capability code PP2 a valid PPE or PPD message should be written to the PPR in advance of the poll Bit Mnemonic Description 4w U Parallel Poll Unconfigure Bit The U bit determines whether or not the TLC participates in a Parallel Poll If U 0 the TLC participates in Parallel Polls and responds in the manner defined by PPR 3 throug
121. lysical Ehatacicn Stes or E tede ll ELLI ae 2 1 Electrical Characteristics ian 2 1 VMEb s Charaete FISEOS ente os a OS ana 2 2 VMEbus Slave Addressimg iy dac eet a rari iaia 2 2 VMEbus Sl ve Datar ironie e ati array aE 2 4 iicet 2 4 VMEbus Modules Not Provided eese 2 5 Diagnostic Aids iiio literati e EN IRR UR en rari 2 5 Data Transfer Features arie 2 5 GPIB 1014DP Functional Description eene 2 6 Section Three Configuration and Installation sees 3 1 Configuration FEE 3 1 Access Mode as omitti edo tesa ene lello iii ai 3 3 VMEBbus BaseAddressco cilea ae 3 3 VMEbus Interrupt Configuration iaia aiar 3 4 Interrupt Request Line Selection Leisten tee tereti oed 3 4 b tettupt Priority C Ode o eiue on REL hc d Qoo a aa 3 5 Interrupt Status ID Vector Selection iaia 3 6 INFERI idunt lus tei dua 3 8 Verification of System Compatibility esee 3 8 N enfication Testing sooo uid d tetto t Qu nied wa sac a ee nha 3 11 GS AD NN aL oen eaa i iuto s Ps ces QU eR A Kn cO cic 3 12 Section Four Register Bit Descriptions ues A ee e Cab ae eed 4 1 Resister Map ouod eade sees ese E eed ace eae LUE 4 KOSISIQr 47S lie 4 2 Register Description Hormal rrc sean 4 2 JOLIE 4 2 Intertace Registers e NEP c cc 4 4 Data In Resister DIR uio petet oil tea ea 4 7 Command Data Out Register CDOR seen
122. mp SGNS becomes true CO is cleared by Read ISR2 CACS SGNS Notes CACS GPIB Controller Active State SGNS GPIB Source Generate State Read ISR2 Bitis cleared immediately after it is read CO 1 indicates CDOR is empty and that another command can be written to it for transmission to the GPIB without overwriting a previous command National Instruments Corporation 4 17 GPIB 1014DP User Manual Register Bit Descriptions Bit Mnemonic 2w LOKC 2r LOKC IE lw REMC Ir REMC IE Or ADSC Ow ADSC IE GPIB 1014DP User Manual Section Four Description Lockout Change Bit Lockout Change Interrupt Enable Bit LOKC is set by any change in LOK LOKC is cleared by pon Read ISR2 Notes LOK ISR2 5 r pon power on reset Read ISR2 Bit is cleared immediately after it is read LOKC is set whenever there is a change in the LOK bit ISR2 5 r REMS RELS Remote Change Bit Remote Change Interrupt Enable Bit REMC is set by any change in REM REMC is cleared by pon Read ISR2 Notes REM ISR2 4 r pon power on reset Read ISR2 Bit is cleared immediately after it is read REMC is set whenever there is a change in the REM bit ISR2 4 r REMS RELS Addressed Status Change Bit Addressed Status Change Interrupt Enable Bit ADSC is set by any change in TA any change in LA any change in CIC any change in MJMN amp lon ton ADSC is cleared by pon Read ISR2
123. mple a hex value of FF corresponds to a bit pattern of 11111111 40 hex corresponds to a bit pattern of 01000000 The tests should be performed for both ports Equations not followed by a question mark are instructions to the user to load the value shown into the designated register Equations followed by a question mark are instructions to the user to read the register and verify that the value in the register is the one indicated The column to the left of each test step contains the relative register address Comments written to the right of each test step briefly describe the action taken and sometimes suggest the purpose The test procedures are designed to check the most elemental levels of functioning first and then progress to tests of higher complexity For this reason users are advised to perform the tests in the order given The tests should be performed without connecting the GPIB 1014DP to another GPIB device All GPIB cables should be removed If the GPIB 1014DP does not perform as described in the test procedures carefully perform the following steps 1 Verify that the test instructions have been followed correctly and all cables are disconnected 2 Examine any read and write routines being used in connection with the checkout procedure for errors 3 Recheck the jumper settings described in Section Three After these items have been carefully checked if the interface is still not functioning properly gather togethe
124. nce An arithmetic addition yields the same result for the instances here National Instruments Corporation C 1 GPIB 1014DP User Manual Sample Programs BASE DIR CDOR ISR1 IMR1 ISR2 IMR2 SPSR SPMR ADSR ADMR CPTR AUXMR ADRO ADR ADR1 EOSR 68000 Code OxFF1000 BASE 0x1 BASE 0x1 BASE 0x3 BASE 0x3 BASE 0x5 BASE 0x5 BASE 0x7 BASE 0x7 BASE 0x9 BASE 0x9 BASE 0xB BASE 0xB BASE 0xD BASE 0xD BASE OxF BASE OxF GPIB 1014DP User Manual GPIB 1014DP Sample Functions for Driver INIT Initialize the GPIB 1014DP IFC Send Interface Clear REN Set Clear Remote Enable RCV Receive READ Read Data DSEND Data Send WRITE Write Data CSEND Command Send CMD Write Commands PASSC Pass Control Base address of GPIB 1014DP interface Data In Register read Control Data Out Register write Interrupt Status Register 1 read Interrupt Mask Register 1 write Interrupt Status Register 2 read Interrupt Mask Register 2 write Serial Poll Status Register read Serial Poll Mask Register write Address Status Register read Address Mode Register write Command Pass Thru Register read Auxiliary Mode Register write Address Register O read Address Register write Address Register 1 read End Of String Register write Appendix C C 2 National Instruments Corporation Appendix C
125. nd received CPT All 13 interrupt events are wire ORed in the TLC to a single signal designated INT on the NEC HPD7210 When one of these events occurs INT goes high and one of the interrupt request lines IRQ1 through IRQ7 is driven low You select the interrupt request line by means of an onboard jumper You set the interrupt priority via three hardware switches U27 The encoded value of the priority must match the level of the interrupt request line The INT pin and associated board setting are independent for each port See Interrupt Request Line Selection in Section Three for more information on setting the interrupt level GPIB 1014DP User Manual 2 4 National Instruments Corporation Section Two General Description The onboard hardware implements the VMEbus interrupt acknowledge protocol The interrupter drives the VMEbus with an 8 bit Status ID byte vector during an interrupt acknowledge cycle The Status ID bytes are set by onboard 8 position Dual In line Package DIP switches U34 and U45 After the interrupt handler reads the Status ID byte from the data bus it releases the data strobe DSO to high Upon seeing DSO high the interrupter releases the data bus and the interrupt request line This implies that the GPIB 1014DP interrupter is a Release On Acknowledge ROAK interrupter Note Even though the interrupt request line is no longer driven the TLC Interrupt INT line remains asserted until it is cleared in the inter
126. ndary Address or Parallel Poll Enable command 4 27 MTA My Talk Address command 4 27 multiline GPIB commands table D 2 to D 3 4 26 to 4 28 N NDAC not data accepted signal E 2 Non Valid Secondary Command or Address command codes for 4 30 description 4 34 NRED not ready for data signal E 2 O operating environment A 1 optional equipment for GPIB 1014DP 1 3 National Instruments Corporation L7 GPIB 1014DP User Manual Index P P 3 1 Parallel Poll Response Bits 3 through 1 4 40 Parallel Poll Register PPR 4 39 to 4 40 parallel polls conducting 5 9 to 5 10 overview 5 9 responding to 5 10 parts list and schematic diagrams B 1 to B 7 PASS CONTROL PASSC sample program C 19 PEND Pending Bit 4 20 physical and electrical characteristics description of E 3 2 1 GPIB connector and signal assignment illustration E 4 linear configuration illustration E 5 specifications A 1 star configuration illustration E 5 pin assignments See signals power requirement A 1 PPC Parallel Poll Configure command 4 26 PPR See Parallel Poll Register PPR PPU Parallel Poll Unconfigure command 4 27 programming Controller function becoming controller in charge CIC and active controller 5 2 to 5 3 going from active to idle 5 4 going from active to standby 5 3 going from standby to active 5 4 sending remote multiline messages commands 5 3 initialization 5 1 to 5 2 interrupts 5 7 to 5 8 parallel
127. ned command can be read from the CPTR and processed by the software 4 44 National Instruments Corporation Section Four Register Descriptions Auxiliary Register E AUXRE VMEbus Address Base Address B hex Port A Base Address 1B hex Port B AUXMR Control Code 110 Binary Bits 7 5 Attributes Write Only Accessed through AUXMR 4 3 2 1 0 W Writing to Auxiliary Register E AUXRE is done via the AUXMR Writing the binary value 110 into the Control Code CNT 2 0 and a bit pattern into the lower five bits COM 4 0 of the AUXMR causes the two lowest order bits to be written to AUXRE The 2 bit code DHDC and DHDT determines how the TLC uses DAC Holdoff Bit Mnemonic Description 4 2w 0 Reserved Bits Write zeros to these bits lw DHDC DAC Holdoff on DCAS Bit Setting DHDC enables DAC holdoff when the TLC enters Device Clear Active State DCAS Clearing DHDC disables DAC Holdoff on DCAS Issuing the Finish Handshake auxiliary command releases the Holdoff Ow DHDT DAC Holdoff on DTAS Bit Setting DHDT enables DAC holdoff when the TLC enters Device Trigger Active State DTAS Clearing DHDT disables DAC Holdoff on DTAS Issuing the Finish Handshake auxiliary command releases the Holdoff National Instruments Corporation 4 45 GPIB 1014DP User Manual Register Descriptions Section Four Address Register 0 ADRO VMEbus Address Base Address D hex Port A Base Address 1D hex Port B Attribu
128. ng 2 1 0 Extended single addressing 3 1 1 Extended dual addressing In mode 1 ADRO and ADRI contain the major and minor addresses respectively for dual primary GPIB address applications that is the TLC responds to two GPIB addresses a major address and a minor address The MJMN bit in the ADSR indicates which address was received In applications where the TLC needs to respond to only one address the major Talker and Listener function is used and the minor Talker and Listener function should be disabled The minor Talker and Listener function can be disabled by setting the Disable Talker DT and Disable Listener DL bits in ADRI set ADR and ADRI In mode 2 ADM1 1 ADMO 0 the TLC recognizes two sequential GPIB address bytes a primary followed by a secondary Both GPIB address bytes must be received in order to enable the TLC to talk or listen In this manner mode 2 addressing uses the Extended Talker and Extended Listener functions as defined in IEEE 488 without requiring computer program intervention In mode 2 ADRO and ADRI contain the TLC primary and secondary GPIB addresses respectively 4 24 National Instruments Corporation Section Four Bit Mnemonic Register Bit Descriptions Description In mode 3 ADM1 1 ADMO 1 the TLC handles addressing just as it does in mode 1 except that each major or minor GPIB primary address must be followed by a secondary address All secondary GPIB addresses must be verified b
129. nic represents a bit register function remote message local message state VMEbus operation or VMEbus signal e Index alphabetically lists topics covered in this manual including the page where the topic can be found Abbreviations Used in This Manual The following abbreviations are used in the text of this manual lt is less than or equal to 2 is greater than or equal to A ampere C Celcius d degree hex hexadecimal in inch kbytes 1000 bytes m meters Mbyte million bytes mm millimeter MHz megahertz usec microsecond nsec nanosecond sec second V volt VDC volts direct current Related Documents The following manuals provide information that may be helpful as you read this manual e ANSI IEEE Std 488 1978 IEEE Standard Digital Interface for Programmable Instrumentation e ANSI IEEE Std 1014 1987 IEEE Standard for a Versatile Backplane Bus VMEbus e HPD7210 GPIB IFC User Manual e uPD7210 Intelligent GPIB Interface Controller Engineering Data Sheet e How to Interface a Microcomputer System to a GPIB amp The NEC uPD7210 TLC GPIB 1014DP User Manual vi National Instruments Corporation Contents Section One General Information i 1 1 What Your Kit Should Contain e 1 3 Optional Eg ipment ariana aRaieaa cas serae lees DIAS AS ASS ust LADA ad 1 3 Upea ca Pi ner UE da cd dubie Med E AN 1 3 Section Two General Description onsite eons pr cm lop a A eto uns 2 1 P
130. nse State Not Ready for Data Null byte Other Secondary Address Other Talk Address Parallel Poll Response Bits 3 through 1 Parallel Poll Addressed to Configure State Primary Command Group Pull up Enable Pending Bit Power Off Power On Parallel Poll scan all status flags Parallel Poll Active State Parallel Poll Configure Parallel Poll Disable Parallel Poll Enable F 6 National Instruments Corporation Appendix F Mnemonic Type PPIS ST PPR RM PPSS ST PPU RM PUCS ST R RD LS rdy LM REM B REMC B REMC IE B REMS ST REN RM REOS B RESET LS RFD RM RL F RMW VBO ROAK VBO rpp LM RQS RM rsc LM TSV B TSV LM rtl LM RWD B RWLS ST S S B S8 S 6 1 B SACS ST SCG RM SDC RM SDYS ST SEOI B SERCLK VBS SERDAT VBS SGNS ST SH F SIAS ST sic LM SIDS ST SIIS ST SINS ST SIWS ST National Instruments Corporation Mnemonics Key Definition Parallel Poll Idle State Parallel Poll Response Parallel Poll Standby Active Parallel Poll Unconfigure Parallel Poll Unaddressed to Configure State TLC Read Signal Ready for next message Remote Bit Remote Change Bit Enable Interrupt on Remote Change Bit Remote State Remote Enable End on End Of String Received Bit Local Reset Signal Ready For Data Remote Local Read Modify Write Release on Register Access Request Parallel Poll Request Service Request System Control Request Service Bit Request Service Return To Local Release When Done B
131. ode to be written to AUXRA When the data is written to AUXRA the bits are denoted by the mnemonics shown above This 5 bit code controls the data transfer messages Holdoff and EOS END Bit 4w 3w 2w Mnemonic BIN XEOS REOS Description Binary Bit The BIN bit selects the length of the EOS message Setting BIN causes the End of String Register EOSR to be treated as a full 8 bit byte When BIN 0 the EOSR is treated as a 7 bit register for ASCII characters and only a 7 bit comparison is done with the data on the GPIB Transmit END with EOS Bit The XEOS bit permits or prohibits automatic transmission of the GPIB END message at the same time as the EOS message when the TLC is in Talker Active State TACS If XEOS is set and the byte in the CDOR matches the contents of the EOSR the EOI line is sent true along with the data END on EOS Received Bit The REOS bit permits or prohibits setting the END bit ISR1 4 r at reception of the EOS message when the TLC is in Listener Active State LACS If REOS is set and the byte in the DIR matches the byte in the EOSR the END bit ISR1 4 r is set National Instruments Corporation 4 4 GPIB 1014DP User Manual Register Descriptions Bit 1 Ow GPIB 1014DP User Manual Mnemonic HLDE HLDA Section Four Description Holdoff on END Bit Holdoff on All Bit HLDE and HLDA together determine the GPIB data receiving mode The four possible modes are as follows
132. off by APT and allows the TLC to function as if a My Secondary Address MSA message had been received The DAC message is released at the time of Command Pass Through CPT DAC is also if DCAS or DTAS is in Holdoff state Clear Parallel Poll Flag Set Parallel Poll Flag These commands set the Parallel Poll Flag to the value of COM3 The value of the Parallel Poll Flag is used as the local message ist when bit four of Auxiliary Register B is zero The value of SRQS is used as the ist when ISS 1 Go To Standby The Go To Standby command sets the local message gts if the TLC is in Controller Active State CACS or when it enters CACS When the TLC leaves CACS gts is cleared Take Control Asynchronously The Take Control Asynchronously command pulses the local message tca continues GPIB 1014DP User Manual 4 34 National Instruments Corporation Section Four Register Descriptions Table 4 5 Auxiliary Commands Detailed Description continues Command Code COM4 COM0 43210 Description Take Control Synchronously The Take Control Synchronously command sets the local message tcs The local message tcs is effective only when the TLC is in Controller Standby State CSBS or Controller Synchronous Wait State CSWS The local message tcs is cleared when the TLC enters Controller Active State CACS Take Control Synchronously on END The Take Control Synchronously on END command sets the local message tcs when the data
133. om a VMEbus based computer The GPIB 1014DP has the following features Complete IEEE 488 Talker Listener Controller TLC capability using the NEC uPD7210 GPIB TLC chip for each port Polled or interrupt driven transfers Transfer rates up to 80 kbytes sec User configurable parameters Base Address Interrupt Request Line Interrupt Status ID byte Supervisor or User Access IEEE 1014 VMEbus standard compliance Comprehensive software support Compatible with software written for the GPIB 1014P The GPIB 1014DP conforms to all requirements and conventions specified in ANSI IEEE Std 1014 1987 IEEE Standard for a Versatile Backplane Bus VMEbus Hereafter the General Purpose Interface Bus is referred to as the GPIB the GPIB standard is referred to as the JEEE 488 standard and the ANSI IEEE Std 1014 1987 is referred to as the JEEE 1014 standard National Instruments Corporation 1 1 GPIB 1014DP User Manual General Information Section One Figure 1 1 shows the GPIB 1014DP interface board Figure 1 1 GPIB 1014DP Interface Board The GPIB 1014DP interface kit includes hardware and programming examples to implement common GPIB functions Optional cables are supplied for interconnection with other devices on the GPIB GPIB 1014DP User Manual 1 2 National Instruments Corporation Section One General Information What Your Kit Should Contain Your GPIB 1014DP kit should contain the following components Kit Com
134. ommand Data Out Register CDOR in response to the CO status bit in ISR2 The TLC recognizes any commands applicable to itself such as its own talk or listen address To make the TLC a Listener write its listen address to the CDOR Going from Active to Standby Controller If the TLC is GPIB Active Controller the Controller Standby State CSBS is entered upon reception of the Go To Standby auxiliary command The ATN line is unasserted as soon as the TLC enters CSBS Even though the TLC GPIB Controller state machine is in standby the CIC bit in the ADSR is still set Do not issue the Go To Standby auxiliary command unless the CO bit in ISR2 is set There are three cases to consider when going to standby Case 1 The TLC becomes the GPIB Talker when ATN is unasserted To do this wait for CO to be set send the TLC GPIB Talk Address MTA wait for CO to be set again and then issue the Go To Standby auxiliary command Case 2 The TLC becomes a GPIB Listener when ATN is unasserted To do this wait for CO to be set issue the TLC GPIB Listen Address MLA wait for CO to be set again and then issue the Go To Standby auxiliary command Case 3 The TLC is neither GPIB Talker nor Listener In this case issue the Listen in Continuous Mode auxiliary command or set the Holdoff on End HLDE and Holdoff on All HLDA bits in AUXRA before going to standby This puts the TLC in the continuous mode Once this mode is enabled the TLC participates in t
135. on Bit ATN is a status bit which indicates the current level of the GPIB ATN signal If ATN is 0 the GPIB ATN signal is asserted 5r SPMS Serial Poll Mode State Bit If SPMS 1 the TLC GPIB Talker T or Talker Extended TE function is enabled to participate in a serial poll SPMS is set when the TLC has been addressed as a GPIB Talker and the GPIB Active Controller has issued the GPIB Serial Poll Enable SPE command message SPMS is cleared when the GPIB Serial Poll Disable SPD command is received by power on reset or by issuing the Chip Reset auxiliary command 4r LPAS Listener Primary Addressed State Bit The LPAS bit is used when the TLC is configured for extended GPIB addressing and when set indicates that the TLC has received its primary listen address In Mode 3 addressing see Address Mode Register Description LPAS 1 indicates that the secondary address being received on the next GPIB command may represent the TLC Extended Secondary GPIB Listen address LPAS is cleared by pon or by issuing the Chip Reset auxiliary command National Instruments Corporation 4 21 GPIB 1014DP User Manual Register Bit Descriptions Bit Mnemonic 3r TPAS 2r LA lr TA Or MJMN GPIB 1014DP User Manual Section Four Description Talker Primary Addressed State Bit TPAS is used when the TLC is configured for extended GPIB addressing and when set indicates that the TLC has received its primary GPIB Talk address In Mode 3
136. onding status bit until the read has finished Bit Mnemonic Description Tr CPT Command Pass Through Bit Tw CPT IE Command Pass Through Interrupt Enable Bit CPT is set on UCG ACG amp TADS LADS amp undefined amp ACDS amp CPT ENABLE UDPCF amp SCG amp ACDS amp CPT ENABLE CPT is cleared by pon Read ISR1 Notes UCG GPIB Universal Command Group message ACG GPIB Addressed Command Group message TADS GPIB Talker Addressed State LADS GPIB Listener Addressed State National Instruments Corporation 4 9 GPIB 1014DP User Manual Register Bit Descriptions Bit Mnemonic 6r APT 6w APT IE GPIB 1014DP User Manual Section Four Description defined GPIB command automatically recognized and executed by TLC undefined GPIB command not automatically recognized and executed by TLC ACDS GPIB Accept Data State CPT ENABLE AUXRB 0 w UDPCF Undefined primary command function see below SCG GPIB Secondary Command Group message pon power on reset TAG GPIB Talk Address Group message LAG GPIB Listen Address Group message Read ISRI Bit is cleared immediately after it is read UDPCF is set on UCG ACG amp TADS LADS amp undefined amp ACDS amp CPT ENABLE UDPCF is cleared on UCG ACG amp defined TAG LAG amp ACDS CPT ENABLE pon The CPT bit flags the occurrence of a GPIB command not recognized by the TLC and all following GPIB secondary commands when the Comman
137. ons Physical Characteristics The GPIB 1014DP measures 160 by 233 35 mm and is supplied with two standard 24 pin GPIB connectors mounted on the front panel The card is supplied with a double height metal front panel 0 8 in width Two DIN 41612 96 pin connectors connect the GPIB 1014DP to the VMEbus backplane Electrical Characteristics All integrated circuit drivers and receivers used on the GPIB 1014DP meet the requirements of the VMEbus Specification and the IEEE 1014 standard Table 2 1 contains a list of the VMEbus signals used by the GPIB 1014DP and the device used to interface to each signal Note The asterisk after the bus signal indicates the signal is active low Table 2 1 GPIB 1014DP Signals Driver Device Receiver Device Bus Signals Part Number Part Number D00 through D07 F245 F245 A15 through AOS Do 1 92521 AM4 AM3 AMO AM1 IACK fi LS2521 DS0 WRITE IACKIN LS240 SYSRESET SYSCLK continues National Instruments Corporation 2 1 GPIB 1014DP User Manual General Description Section Two Table 2 1 GPIB 1014DP Signals continued Driver Device Receiver Device Bus Signals Part Number Part Number AOL through A04 Fei aL 5244 The GPIB transceivers meet the requirements of the IEEE 488 standard The components used are as follows Transceivers Component Designation Data Transceivers 75160 Control Transceivers 75162 Note Current load is typically 1 1 A 2 0 A maximum VMEbus Chara
138. ontrol The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this book may not be copied photocopied reproduced or translated in whole or in part without the prior written consent of National Instruments Corporation Trademarks Product names listed are trademarks of their respective manufacturers Company names listed are trademarks or trade names of their respective companies WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure or by errors on the part of the user or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel and all traditional medical safeguards
139. or minor primary GPIB Listen Address MLA sets TPAS or LPAS indicating that the primary address has been received 3 Ifthe next GPIB command following the primary address is a secondary address the APT bit is set and a DAC handshake holdoff is activated the GPIB DAC message is held false 4 Inresponse to APT the program must e Determine whether the command just received is a listen talk major or minor address by reading the LPAS TPAS and MJMN bits of the ADSR e Read the secondary address in the CPTR and determine whether or not it is the address of the TLC 5 Ifit is not the TLC address issue the Non Valid auxiliary command If it is the TLC address issue the Valid auxiliary command GPIB 1014DP User Manual 5 6 National Instruments Corporation Section Five Programming Considerations 6 When the Valid auxiliary command is issued the TLC assumes that the My Secondary Address MSA message has been received which causes e The LA bit to be set and the TA bit to be cleared LADS TIDS 1 if LPAS was set or the TA bit to be set and the LA bit to be cleared TADS LIDS 1 if TPAS was set e The GPIB DAC message to be sent true and the GPIB handshake to be finished 7 When the Non Valid auxiliary command is issued the TLC assumes that the Other Secondary Address OSA message has been received which causes e The TLC Talker or Listener function to go to its idle state TIDS 1 or LIDS 1 if the either the TPAS
140. ormation is separately latched by this register and is not destroyed by a write to the Command Data Out Register CDOR which locates at the same address The GPIB Ready For Data RFD message is held false until the byte is removed from the DIR by an I O read from a VMEbus master The Acceptor Handshake AH completes automatically after the byte has been read In RFD Holdoff mode refer to Auxiliary Register A later in this section the GPIB Handshake is not finished until the Finish Handshake FH auxiliary command is issued telling the TLC to release the Holdoff By using the RFD Holdoff mode the same byte can be read several times or a GPIB Talker that is ready to provide more data can be held off until the program is ready to proceed DIO is the least significant bit of the data byte and corresponds to GPIB DIO1 DI7 is the most significant bit of the data byte and corresponds to GPIB DIOS Bit Mnemonic Description 7 Or DI 7 0 Data In Bits 7 through 0 National Instruments Corporation 4 7 GPIB 1014DP User Manual Register Bit Descriptions Section Four Command Data Out Register CDOR VMEbus Address Base Address 1 hex Port A Base Address 11 hex Port B Attributes Write Only 7 6 5 4 3 2 1 0 CDO7 CDO6 CDOS CDO4 CDO3 CDO2 CDOI CDOO W The Command Data Out Register CDOR is used to move data from the VMEbus to the GPIB when the TLC is the GPIB Talker or the Active Controller Outgoing data is separately latched by t
141. polls 5 9 to 5 10 sample programs 68000 code C 2 to C 4 COMMAND CMD C 18 COMMAND SEND CSEND C 17 DATA SEND DSEND C 13 to C 14 INITIALIZE INIT C 5 to C 6 INTERFACE CLEAR IFC C 7 overview C 1 PASS CONTROL PASSC C 19 READ C 11 to C 12 RECEIVE RCV C 9 to C 10 REMOTE ENABLE REN C 8 WRITE C 15 to C 16 sending receiving messages 5 7 serial polls 5 8 Talker and Listener addressed implementation 5 5 to 5 6 overview 5 5 programmed implementation 5 5 GPIB 1014DP User Manual 1 8 National Instruments Corporation R READ sample program C 11 to C 12 RECEIVE RCV sample program C 9 to C 10 registers format for description of 4 2 GPIB TLC interface registers chart 2 3 interface registers Address Mode Register ADMR 4 23 to 4 25 Address Status Register ADSR 4 21 to 4 22 Auxiliary Mode Register AUXMR 4 29 to 4 36 Command Data Out Register CDOR 4 8 Command Pass Through Register CPTR 4 26 to 4 28 Data In Register DIR 4 7 hidden registers 4 37 to 4 45 Interrupt Mask Register 1 IMR1 4 9 to 4 14 Interrupt Status Register 1 ISR1 4 9 to 4 14 Interrupt Status Register 2 ISR2 4 15 to 4 19 uPD7210 interface registers illustration 4 5 overview 4 4 Serial Poll Mode Register SPMR 4 20 Serial Poll Status Register SPSR 4 20 writing to hidden registers 4 6 mnemonics for 4 3 register map 4 1 to 4 2 size of 4 2 terminology related to 4 2 to 4 3 REM Remote Bit 4 17 REMC Remote Change B
142. ponent Part Number GPIB 1014DP board 776093 01 GPIB 1014DP User Manual 320049 01 Optional Equipment Equipment Part Number Single Shielded Cables GPIB Type X1 Cable 1 m 763001 01 GPIB Type X1 Cable 2 m 763001 02 GPIB Type X1 Cable 4 m 763001 03 Unpacking Follow these steps when unpacking your GPIB 1014DP 1 Verify that the pieces contained in the package you received match the kit parts list given previously in this section Do not remove the board from its plastic bag at this point 2 Your GPIB 1014DP board is shipped packaged in an antistatic plastic bag to prevent electrostatic damage to the board Several components on the board can be damaged by electrostatic discharge To avoid such damage in handling the board touch the plastic bag to a metal part of your VMEbus computer chassis before removing the board from the bag 3 Remove the board from the bag and inspect the board for loose components or any other sign of damage Notify National Instruments if the board appears damaged in any way DO NOT install a damaged board into your computer National Instruments Corporation 1 3 GPIB 1014DP User Manual Section Two General Description This section contains the physical and electrical specifications for the GPIB 1014DP and describes the characteristics of key interface board components including a functional block diagram as well as illustrations of applications in test and measurement configurati
143. pt Mask Register 2 Interrupt Bit TLC Interrupt Request Line A TLC Interrupt Request Line B Invert Bit Interrupt Request Interrupt Request Interrupt Status Register 1 Interrupt Status Register 2 Individual Status Select Bit Individual Status Listener Listener Active Bit Listener Active State L function Listener Addressed State L function Listener Address Group Local Data Bus Local DTACK Listener Extended Listener Idle State Local Lockout Local Master Reset Bit Local State Lockout Bit Lockout Change Bit Enable Interrupt on Lockout Change Bit F 5 GPIB 1014P User Manual Mnemonics Key Mnemonic Type lon B lon LM LPAS B LPAS ST Ipe LM Ipe LM LPIS ST Itn LM lun LM LWLS ST LWORD VBS M MAKOUT LS MCYC LS MDTACK LS MJMN B MLA RM MSA RM MTA RM N nba LM NDAC RM NPRS ST NRFD RM NUL RM O OSA RM OTA RM P P 3 1 B PACS ST PCG RM PE LM PEND B pof LM pon LM PP F PPAS ST PPC RM PPD RM PPE RM GPIB 1014P User Manual Appendix F Definition Listen Only Bit Listen Only Listener Primary Addressed State Bit Listener Primary Addressed State Local Poll Enabled Local Poll Enabled Active Low Listener Primary Idle State Listen Local Unlisten Local With Lockout State Low Word Internal IACKOUT From A to B My Cycle DMA Acknowledge Major Minor Bit My Listen Address My Secondary Address My Talk Address New Byte Available Not Data Accepted Negative Poll Respo
144. r each port is symmetric and the description of the operation is applicable to each VMEbus Interface Low power Schottky Transistor Transistor Logic LSTTL Advance Low power Schottky Transistor Transistor Logic ALSTTL or Fast Transistor Transistor Logic FTTL logic devices buffer address data control and status signals to or from the VMEbus All drivers drive the proper amount of current as required by the VMEbus specification and all receivers meet the bus loading limits as called out by the VMEbus specification Data Lines An F245 octal bus transceiver connects VMEbus data lines DOO through D07 to the GPIB 1014DP During interrupter Status ID cycles or read cycles to the GPIB 1014DP the F245 is directed to allow the GPIB 1014DP to drive the data bus During write cycles the direction of the F245 is reversed to allow the Talker Listener Controller TLC registers to receive data from the VME data bus The F245 transceiver is enabled when either the EVA the EVB or the STB signal is high The EVA or the EVB signal is asserted to allow the interrupter to drive the data bus with a Status ID byte while the STB signal is asserted to enable the F245 during a data transfer cycle Control Signals Note An asterisk implies that the signal is active low IB 1014DP receives the VMEbus control signals WRITE DTACK DSO IACKIN and WRITE with LS240 buffers while an ALS244 buffer receives DS1 and AS The slave monitors DTACK to mak
145. r the information concerning what the GPIB 1014DP is and is not doing with regard to the expected results and contact National Instruments National Instruments Corporation 7 1 GPIB 1014DP User Manual Diagnostics and Troubleshooting Section Seven GPIB 1014DP Hardware Installation Tests 1 Initialize TLC Port A Port B B 1B AUXMR 2 B 1B AUXMR 0 Chip Reset Immediate execute pon 2 Send Chip Reset then read registers and compare to reset values Port A Port B B 1B AUXMR 2 3 13 ISR1 0 5 15 ISR2 0 7 17 SPSR 0 9 19 ADSR 40 B 1B CPTR 09 3 Test ton DO ERR CPTR TA Port A PortB B IB AUXMR 2 9 19 ADMR 80 B IB AUXMR 0 9 19 ADSR 429 3 13 ISR1 2 2 1 11 CDOR 51 B 1B CPTR 51 3 13 ISR1 26 3 13 ISR1 20 B 1B AUXMR 2 9 19 ADMR 0 B 1B AUXMR 0 9 19 ADSR 40 4 Check lon LA Port A Port B B 1B AUXMR 2 3 13 IMRI 0 5 15 IMR2 0 9 19 ADMR 40 B 1B AUXMR 0 9 19 ADSR 44 B 1B AUXMR 2 9 19 ADSR 40 GPIB 1014DP User Manual Chip Reset Chip Reset ton Immediate execute pon TA DO write data byte verify DO ERR bits cleared when read Chip Reset disable ton Immediate execute pon not TA Chip Reset no interrupts no interrupts lon Immediate execute pon LA Chip Reset not LA 7 2 National Instruments Corporation Section Seven Diagnostics and Troubleshooting 5 Test ATN CIC CO Port A Port B B 1B AUXMR 2 Chip Reset 9 19
146. ra 5 2 Becoming Controller In Charge CIC and Active Controller 5 2 Sending Remote Multiline Messages Commands esses 5 3 Going from Active to Standby Controller eee 5 3 Going from Standby to Active Controller eee 5 4 Going from Active to Idle Controller 5 4 A GPIB 1014DP Port as GPIB Talker and Listener eee 5 5 Programmed Implementation of Talker and Listener sess 5 5 Addressed Implementation of the Talker and Listener sss 5 5 Address Mode 1 eee eit tec oe Set pee eet 5 5 Addr ss Mod 2 eie cot Mn intone Oca catene dra etit toti eade 5 5 Address Mode 3 ehe eee dle eie gt nani 5 6 Seftiding Receivimg Messinese liacle 5 7 Sending Receiving END or EOS c cccssccssssccesssscsessssesseccesneceecnaecssenecesseccesneces 5 7 Interrupts i oett bruce t our lin bi ilo clearance 5 7 periolPolls als Em 5 8 Conducting Serial Polls urea 5 8 Responding to a Serial Poll iio nilo 5 8 Parallel Polls iod aee td pta cal avec tito tet ee eed lai eee ee 5 9 Conducting a Parallel Poll aie ot eoo boten o lis em editus 5 0 Responding To a Parallel Poll nei 5 10 Section Six Theory of OpOEALIOB uos iio er e soleil oto ond iin 6 1 MVINDEDUS IB EEHER ossis ss ga ai Doe iii ii o pua b shed a ace iO e tap ts 6 1 Data Lines c alal area ames Wile keaton M 6 1 Contrel Sisnalsu aero
147. register in bits Table 4 1 GPIB 1014DP Register Map Register Name Address Hex Port A Port B GPIB Interface Register Group Data In Register Command Data Out Register Interrupt Status Register 1 Interrupt Mask Register 1 Interrupt Status Register 2 Interrupt Mask Register 2 Serial Poll Status Register Serial Poll Mode Register Address Status Register Address Mode Register Command Pass Through Register Auxiliary Mode Register Hidden Registers Internal Counter Register Parallel Poll Register National Instruments Corporation Base Base address 1 address 1 address 3 address 3 address 5 address 5 address 7 address 7 address 9 address 9 address B address B address B address B 4 1 address address address address address address address address address address address address address address Read only Write only Read only Write only Read only Write only Read only Write only Read only Write only Read only Write only Write only Write only continues GPIB 1014DP User Manual Register Bit Descriptions Section Four Table 4 1 GPIB 1014DP Register Map continued Address Hex Port B Register Name Port A Hidden Registers continued Auxiliary Register A Auxiliary Register B Auxiliary Register E Address Register 0 Address Register Base address B Base address
148. rs via the Auxiliary Mode Register A detailed function description of all 32 interface registers is provided in the paragraphs following the figures GPIB 1014DP User Manual 4 4 National Instruments Corporation Section Four Register Bit Descriptions Contents of Read Register Bit Bit Bit Bit gt 4 3 2 Contents of Write Register Address Offset hex o AP opr oer oer po pe eee bo or To ssane pwso pwn corporc iene anse on io meon reso o 0 Janus ooo Note X indicates a don t care bit Figure 4 1 uPD7210 Interface Registers O National Instruments Corporation 4 5 GPIB 1014DP User Manual Register Bit Descriptions Section Four amp Control Code p lt Command Code pp EEE ES E ES W When CNT2 CNTO is ICR is loaded with EEE O 0 1 o qe ae ar ax PPR is loaded with SSS SSS ESS ESSES AUXRA is loaded with ess pe a eS AUXRB is loaded with EEE Es ai ea ea AUXRE is loaded with a Ss re ae eee Do Dir DADC Figure 4 2 Writing to the Hidden Registers GPIB 1014DP User Manual 4 6 National Instruments Corporation Section Four Register Bit Descriptions Data In Register DIR VMEbus Address Base Address 1 hex Port A Base Address 11 hex Port B Attributes Read Only 7 6 5 4 3 2 1 0 R id The Data In Register DIR is used to move data from the GPIB to the VMEbus when the interface is a Listener Incoming inf
149. rupt service routine by reading the appropriate status register ISR1 or ISR2 Clearing the TLC INT line in the interrupt routine enables further interrupts from the GPIB 1014DP VMEbus Modules Not Provided Because the GPIB 1014DP is not designed to be VMEbus Controller it does not have the following modules e Master e Bus Timer e Arbiter e Interrupt Handler e TACK Daisy Chain Driver e System Clock Driver Serial Clock Driver e Power Monitor Diagnostic Aids The GPIB 1014DP is designed to allow stand alone verification of I O functions See Section Seven GPIB 1014DP Diagnostic and Troubleshooting Test Procedures for details Data Transfer Features The GPIB 1014DP can be used to transfer data to and from the GPIB using programmed I O Typical transfer rates range from 10 to 80 kbytes sec The actual transfer rate for any particular GPIB system is a function of several factors including the following Response time of the GPIB devices involved e Microprocessor speed and operating system and application program overhead e Interrupt service response time National Instruments Corporation 2 5 GPIB 1014DP User Manual General Description Section Two GPIB 1014DP Functional Description In the simplest terms the GPIB 1014DP can be thought of as a bus translator converting messages and signals present on the VMEbus into appropriate GPIB messages and signals Expressed in GPIB terminology a GPIB 1014DP port implements
150. s between these two modes Becoming Controller In Charge CIC and Active Controller The TLC can become CIC either by being the System Controller and taking control by issuing the Set IFC auxiliary command or by being passed control of the GPIB from the current Active Controller To take control issue the Set IFC auxiliary command wait for a minimum of 100 usec and then issue the Clear IFC auxiliary command The ensuing GPIB IFC message initializes the GPIB interface functions of all devices on the bus As soon as any existing CIC goes to idle dropping ATN if it was active the TLC becomes CIC and Active Controller and asserts the GPIB ATN line In addition to asserting IFC the Set IFC auxiliary command also causes the GPIB transceivers for IFC and REN to be configured as GPIB line drivers thus allowing the IFC and REN lines from the port to be driven to the GPIB The transceivers remain configured as drivers until a system reset is received or the Disable System control auxiliary command is issued which causes the transceivers to be reconfigured as receivers If the GPIB 1014DP is not the System Controller the initialization sequence should include issuing the Disable System Control auxiliary command to ensure that the transceivers are configured as receivers Another Active Controller passes control to the GPIB 1014DP port by sending the TLC GPIB talk address MTA followed by the GPIB Take Control TCT message The TLC upon receivin
151. serts ATN GPIB 1014DP User Manual 5 4 National Instruments Corporation Section Five Programming Considerations A GPIB 1014DP Port as GPIB Talker and Listener The TLC may be either GPIB Talker or Listener but not both simultaneously Either function is deactivated automatically if the other is activated The TA LA and ATN bits in the ADSR together indicate the specific state of the TLC ATN TA LA 0 1 0 Addressed Talker cannot send data 1 1 0 Active Talker can send data 0 0 1 Addressed Listener cannot receive data 1 0 1 Active Listener can receive data The status bits Address Status Change ADSC Command Output CO Address Pass Through APT Data Out DO and Data In DI are used to prompt the program possibly with an interrupt request when a change of state occurs The following paragraphs discuss several aspects of data transfers Programmed Implementation of Talker and Listener When there is no Controller in the GPIB system the ton and lon address modes refer to the description of the ADMR are used to activate the TLC GPIB Talker and Listener functions If used ton or lon should be set during TLC initialization When the TLC is GPIB Active Controller the Listen and Local Unlisten programmed auxiliary commands are used to activate and de activate the TLC GPIB Listener function Addressed Implementation of the Talker and Listener The TLC when GPIB Active Controller can address itself by sending its own
152. ssi 7 35 css CE ES e VMEbus DS aaa Interi Line RISAIE B Lsz93 HE F10 Selection TREZE dObTOT ALdo 68617 O LHITHAdOI duUoo SINTNNULSNI TYNOILYN dt res 0 nN33 0 02Z208TASSY cn 99 8b ecra VMEbus Base H Address Reje Configuration Qi 8 SUITOMP a Interrupt Status ID AD 75162 Vector Selection Figure 3 1 GPIB 1014DP Parts Locator Diagram GPIB 1014DP User Manual 3 2 National Instruments Corporation Section Three Configuration and Installation Access Mode The GPIB 1014DP can be configured to allow Supervisor privileged or Supervisor and User non privileged access using hardware jumper W2 as shown in Figure 3 2 To configure the board for privileged access only place the jumper on the side labeled S as shown in Figure 3 2a To configure the board for non privileged access place the jumper on the side labeled NP as shown in Figure 3 2b The default setting for the GPIB 1014DP is for non privileged access In the Supervisor mode the GPIB 1014DP only responds to Address Modifier AM code 2D In the Non privileged mode the board responds to AM codes 2D or 29 Refer to ANSI IEEE Std 1014 1987 IEEE Standard for a Versatile Backplane Bus VMEbus for more information on Supervisor and Non privileged modes a Supervisor only b Supervisor and User Privileged Non Privileged Figure 3 2 Access Selection VMEbus Base Address
153. ssuing an Immediate Execute pon auxiliary command to the TLC the interface functions are released from the pon state and the auxiliary commands can be executed A typical programmed initialization sequence for a GPIB 1014DP port might include the following steps 1 Set pon by issuing the Chip Reset auxiliary command to place the GPIB 1014DP in a known quiescent state 2 Set or clear the desired interrupt enable bits in Interrupt Mask Register 1 IMR1 and Interrupt Mask Register 2 IMR2 of the TLC National Instruments Corporation 5 1 GPIB 1014DP User Manual Programming Considerations Section Five 3 Load the TLC primary GPIB address in Address Register 0 ADRO and Address Register 1 ADRI 4 Enable or disable the GPIB Talker and Listener functions and addressing mode using the ADMR 5 Load the Serial Poll response in the SPMR 6 Load the Parallel Poll response in the Parallel Poll Register PPR if local configuration is used If using remote configuration clear the PPR 7 Clear power on pon by issuing the Immediate Execute pon auxiliary command to the TLC to bring TLC on line 8 Execute the desired TLC auxiliary commands A GPIB 1014DP Port as GPIB Controller The GPIB 1014DP Controller function of each port is generally in one of two modes idle or in charge When in charge the Controller function is either active asserting ATN or standby not asserting ATN The following paragraphs discuss the various transition
154. t use a bus tester or analyzer such as National Instruments GPIB 400 or GPIB 410 that can monitor and control GPIB signal lines emulate GPIB Talker Listener and Controller devices and single step through the Source and Acceptor Handshakes National Instruments Corporation 3 1 GPIB 1014DP User Manual Configuration and Installation Section Three Cabling Optional cables are available to connect the GPIB ports of the GPIB 1014DP to other GPIB devices Connect the cable to the GPIB 1014DP Port A at the standard GPIB connector labeled J1 at the top of the interface board Connect the cable to the GPIB 1014DP Port B at the standard GPIB connector labeled J2 at the bottom of the interface board The GPIB connector protrudes through the metal front cover plate Figure 3 7 shows the signals present on a GPIB cable connector DIOS DIO6 DIO7 DIO8 REN GND TW PAIR W DAV GND TW PAIR W NRFD GND TW PAIR W NDAC GND TW PAIR W IFC GND TW PAIR W SRQ GND TW PAIR W ATN SIGNAL GROUND Figure 3 7 GPIB Cable Connector GPIB 1014DP User Manual 3 12 National Instruments Corporation Section Four Register Bit Descriptions This section presents detailed information on the use of the GPIB 1014DP Talker Listener Controller registers Register Map The register map for the GPIB 1014DP is shown in Table 4 1 This table gives the register name the register address the type of the register and the size of the
155. teners The Controller manages the flow of information on the GPIB by sending commands to all devices Devices can be Listeners Talkers and or Controllers A digital voltmeter for example is a Talker and may be a Listener as well The GPIB is a bus like an ordinary computer bus except that the computer has its circuit cards interconnected via a backplane bus whereas the GPIB has standalone devices interconnected via a cable bus The role of the GPIB Controller can also be compared to the role of the CPU of a computer but a better analogy is to the switching center of a city telephone system The switching center Controller monitors the communications network GPIB When the center Controller notices that a party device wants to make a call send a data message it connects the caller Talker to the receiver Listener The Controller addresses a Talker and a Listener before the Talker can send its message to the Listener After the message is transmitted the Controller may unaddress both devices Some bus configurations do not require a Controller For example one device may always be a Talker called a Talk only device and there may be one or more Listen only devices A Controller is necessary when the active or addressed Talker or Listener must be changed The Controller function is usually handled by a computer National Instruments Corporation E 1 GPIB 1014DP User Manual Operation of the GPIB Appendix E With th
156. tes Read Only ADRO reflects the internal GPIB address status of the TLC as configured using the ADMR In addressing Mode 2 ADRO indicates the address and enable bits for the primary GPIB address of the TLC In dual primary addressing Modes and 3 ADRO indicates the TLC major primary GPIB address Refer to description of ADMR for information on addressing modes Bit Mnemonic Description Tr X Don t Care Bit Reads as a zero or one 6r DTO Disable Talker 0 If DTO is set it indicates that the mode 2 primary or mode 1 and 3 major Talker is not enabled that is the TLC does not respond to a GPIB talk address matching AD 5 0 1 0 If DTO 0 the TLC responds to a GPIB talk address matching bits AD 5 0 1 0 Sr DLO Disable Listener 0 Bit If DLO is set it indicates that the mode 2 primary or mode 1 and 3 major Listener is not enabled that is the TLC does not respond to a GPIB Listen address matching bits AD 5 0 1 0 If DLO 0 the TLC responds to a GPIB listen address matching bits AD 5 0 1 0 4 0r AD 5 0 1 0 Mode 2 Primary GPIB Address Bits 5 0 through 1 0 These are the lower five bits of the TLC GPIB primary or major address The primary talk address is formed by adding octal 100 to AD5 0 through AD1 0 while the listen address is formed by adding octal 40 GPIB 1014DP User Manual 4 46 National Instruments Corporation Section Four Register Descriptions Address Register ADR VMEbus I O Address
157. the Controller goes to Standby and becomes an active Listener 6r PEND Pending Bit PEND is set when rsv 1 and cleared when Negative Poll Response States NPRS amp Request Service rsv 1 Reading the PEND status bit can confirm that a request was accepted and that the Status Byte STB was transmitted PEND 0 6w rsv Request Service Bit The rsv bit is used for generating the GPIB local request service message When rsv is set and the GPIB Active Controller is not serially polling the TLC the TLC enters the Service Request State SRQS and asserts the GPIB SRQ signal When the Active Controller reads the STB during the poll the TLC clears rsv at the Affirmative Poll Response State APRS The rsv bit is also cleared by power on reset LMR CFG2 1 w and by issuing the Chip Reset auxiliary command GPIB 1014DP User Manual 4 20 National Instruments Corporation Section Four Register Bit Descriptions Address Status Register ADSR VMEbus Address Base Address 9 hex Port A Base Address 19 hex Port B Attributes Read Only 7 6 5 4 3 2 1 0 R The ADSR contains information that can be used to monitor the TLC GPIB address status Bit Mnemonic Description Tr CIC Controller In Charge Bit CIC CIDS CADS CIC indicates that the TLC GPIB Controller function is in an active or standby state with ATN on or off respectively The Controller function is in an idle state with ATN off if CIC 0 6r ATN Attenti
158. the DAC message is held and the GPIB handshake stops until either the Valid or Non Valid auxiliary command is issued The secondary address can be read from the CPTR Device Execute Trigger Bit Device Execute Trigger Interrupt Enable Bit DET is set by DTAS DET is cleared by pon Read ISR1 Notes DTAS GPIB Device Trigger Active State pon power on reset Read ISR1 Bitis cleared immediately after it is read The DET bit indicates that the GPIB Device Execute Trigger DET command has been received while the TLC was a GPIB Listener the TLC has been in DTAS End Received Bit End Received Interrupt Enable Bit END RX is set by LACS amp EOI EOS amp REOS amp ACDS National Instruments Corporation 4 11 GPIB 1014DP User Manual Register Bit Descriptions Bit Mnemonic 3r DEC 3w DEC IE 2r ERR 2w ERR IE GPIB 1014DP User Manual Section Four Description END RX is cleared by pon Read ISR1 Notes LACS GPIB Listener Active State EOI GPIB End Or Identify Signal EOS GPIB End Of String message REOS Reception Of GPIB EOS allowed AUXRA 2 w ACDS GPIB Accept Data State pon power on reset Read ISR1 Bitis cleared immediately after it is read The END RX bit is set when the TLC is a Listener and the GPIB uniline message END is received with a data byte from the GPIB Talker or the data byte in the DIR matches the contents of the End Of String Register EOSR Device Clear Bit Device Clear
159. tioning properly Section Four Register Bit Descriptions contains detailed descriptions of the GPIB Interface registers of the NEC uPD7210 LSI GPIB Talker Listener Controller as well as summary tables for easy reference Section Five Programming Considerations explains important considerations for programming the GPIB 1014DP e Section Six Theory of Operation contains a functional overview of the GPIB 1014DP board and explains the operation of each functional block making up the GPIB 1014DP Section Seven GPIB 1014DP Diagnostic and Troubleshooting Test Procedures contains test procedures for determining if the GPIB 1014DP is installed and operating correctly e Appendix A Specifications lists the specifications of the GPIB 1014DP e Appendix B Parts List and Schematic Diagrams contains a parts list and detailed schematic diagrams e Appendix C Sample Programs provides sample programs in 68000 Assembly Language code for implementing the most commonly used GPIB functions Line by line comments provide an explanation of each function National Instruments Corporation v GPIB 1014DP User Manual Preface e Appendix D Multiline Interface Command Messages contains a listing of the multiline GPIB interface messages e Appendix E Operation of the GPIB describes the operation of the GPIB e Appendix F Mnemonics Key contains an alphabetical listing of all mnemonics used in this manual and indicates whether the mnemo
160. truments Corporation Section Four Register Descriptions Auxiliary Register B AUXRB VMEbus Address Base Address B hex Port A Base Address 1B hex Port B AUXMR Control Code 101 Binary Bits 7 5 Attributes Write Only Accessed through AUXMR 4 3 2 1 0 CPT INV W Writing to Auxiliary Register B AUXRB is done via the AUXMR Writing the value 101 into the Control Code CNT 2 0 and a bit pattern into the Command Code portion COM 4 0 of the AUXMR causes the Command Code to be written to AUXRB When the data is written to AUXRB the bits are denoted as shown in the register bit map above This 5 bit code affects several interface functions as described in the following paragraphs Bit Mnemonic Description 4w ISS Individual Status Select Bit The ISS bit determines the value of the TLC ist message When ISS 1 ist becomes the same value as the TLC Service Request State SRQS The TLC is asserting the GPIB SRQ message when it is in SRQS When ISS 0 ist takes on the value of the TLC Parallel Poll Flag The Parallel Poll Flag is set and cleared using the Set Parallel Poll Flag and Clear Parallel Poll Flag auxiliary commands 3w INV Invert Bit The INV bit affects the polarity of the TLC INT pin Setting INV causes the polarity of the Interrupt INT pin on the TLC to be active low As implemented on the GPIB 1014DP configuring the INT pin to active low results in interrupt request errors Consequently INV shou
161. umana era rin E 3 ATN attention iaia ea E 3 IFG nterface clear aria aa E 3 REN remote enable usi abili ilo alia E 3 SRO Service reg est ennn Garda aMeeu aste a edades E 3 EOL end OF identity oce deae deae Coenen a ae E 3 Physical and Electrical Characteristics flirt cada E 3 Confisuraton Requitements oe se Bde bili oso lucidi ieri E 6 Related Document rele elia E 7 GPIB 1014DP User Manual ix National Instruments Corporation Contents Appendix F Minemonies korean eds oe eee F 1 Index lorelai RU Rees I 1 Figures Figure 1 1 GPIB 1014DP Interface Board i 1 2 Figure 2 1 GPIB 1014DP with a VMEbus Computer 2 7 Figure 2 2 GPIB 1014DP in a Multiprocessor Application i 2 8 Figure 2 3 GPIB 1014DP Block Diagram eene nennen 2 9 Figure 3 1 GPIB 1014DP Parts Locator Diagram era 3 2 Figure 3 2 ACCESS Selection soi AE aa e dad lebe near a audes 3 3 Figure 3 3 Configuration for VMEbus Base Address 1000 hex default setting 3 4 Figure 3 4 VMEbus Interrupt Line Selection uie pz Cp ce de liceali 3 5 Figure 3 5 VMEbus Interrupt Priority Code Selection esee 3 6 Figure 3 6 Status ID Byte T excoriata 3 7 Figure 327 GPIB able Connector gras cor culta band te pei ter Gosia rset pulstev pec ds coos read 3 12 Figure 4 1 uPD7210 Interface Registers assis ie lei leer eeu 4 5 Figur
162. upt status register ISR1 or ISR2 The appropriate interrupt status register must be read to enable further interrupts from the GPIB 1014DP The DTACK assert release circuitry releases DTACK after the F245 ceases driving the data bus DEN 1 IDTACK is high and DS1 is released If the address lines A01 through A03 do not match the indicated priority of either GPIB 1014DP port IACKOUT will be asserted After IACKIN and the delayed AS are received high the VMEbus signal IACKOUT is driven low IACKOUT is released within 30 nsec of AS being released GPIB Interface Each port of the GPIB 1014DP is interfaced to the GPIB using an NEC uPD7210 Talker Listener Controller TLC large scale integrated circuit The TLC contains most of the logic circuitry needed to program control and monitor the GPIB interface functions that are implemented by each port Access to these functions is through eight read only registers and 13 write only registers five of which are indirectly addressed These registers occupy a block of 16 memory addresses eight consecutive odd addresses for each port GPIB 1014DP User Manual 6 4 National Instruments Corporation Section Six Theory of Operation The TLC is enabled during the TLC CS pulse and the IEEE 1014 bus address signals A1 through A3 are decoded internally to access the appropriate register Data on the IEEE 1014 bus are strobed into write only registers at the trailing edge of WR Data in the rea
163. with a cable assembly consisting of a shielded 24 conductor cable with both a plug and receptacle connector at each end This design allows devices to be linked in either a linear or a star configuration or a combination of the two See Figures E 1 E 2 and E 3 The standard connector is the Amphenol or Cinch Series 57 Microribbon or Amp Champ type An adapter cable using a non standard cable and or connector is used for special interconnection applications The GPIB uses negative logic with standard TTL logic level When DAV is true for example it is a TTL low level 0 8V and when DAV is false it is a TTL high level gt 2 0V National Instruments Corporation E 3 GPIB 1014DP User Manual Operation of the GPIB DIO1 DIO2 DIO3 DIO4 EOI DAV NRFD NDAC IFC SRQ ATN SHIELD 3 alo NI alo r 4 Do fp fino Ip Ja Fo Ja Ja a WIN O OJON o Joy E Appendix E DIO5 DIO6 DIO7 DIO8 REN GND TW PAIR W DAV GND TW PAIR W NRFD GND TW PAIR W NDAC GND TW PAIR W IFC GND TW PAIR W SRQ GND TW PAIR W ATN SIGNAL GROUND Figure E 1 GPIB Connector and the Signal Assignment GPIB 1014DP User Manual National Instruments Corporation Appendix E Operation of the GPIB Figure E 2 Linear Configuration National Instruments Corporation E 5 GPIB 1014DP User Manual Operation of the GPIB Appendix E Figure E 3 Star Configuration Configuration Requirements
164. y computer program when mode 3 is used When the TLC is in Talker Primary Addressed State TPAS or Listener Primary Addressed State LPAS and a secondary address byte is on the GPIB DIO lines the APT bit of ISR2 is set and the secondary GPIB address may be inspected in the CPTR The TLC Acceptor Handshake is held up in the Accept Data State ACDS until the Valid or Non Valid auxiliary command is written to the AUXMR signaling a valid or invalid secondary address respectively to the TLC ADMO and ADMI must be cleared when either of the two programmable bits ton or lon is set National Instruments Corporation 4 25 GPIB 1014DP User Manual Register Bit Descriptions Section Four Command Pass Through Register CPTR VMEbus Address Base Address B hex Port A Base Address 1B hex Port B Attributes Read Only 7 6 5 4 3 2 1 0 R CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPTI CPTO Bit Mnemonic 7 0r CPT 7 0 GPIB 1014DP User Manual Description Command Pass Through Bits 7 through 0 These bits are used to transfer undefined multiline GPIB command messages from the GPIB DIO lines to the computer When the CPT feature is enabled CPT ENABLE 1 AUXRB 0 w any GPIB Primary Command Group PCG message not decoded by the TLC is treated as an undefined command The multiline GPIB commands recognized by the uPD7210 are listed in Table 4 3 All GPIB Secondary Command Group SCG messages following an undefined GPIB PCG message are a

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