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IOS-409 User`s Manual

1. I O Noise and Grounding Considerations PROGRAMMING INFORMATION ADDRESS MAP Srce INR MEIN Control Reglster side ettet E E sepas Input Output Channel Registers Direction Control Registers Interrupt Enable Interrupt Type Configuration Register Interrupt Status Interrupt Polarity Interrupt Vector IOS Identification IOS 409 PROGRAMMING CONSIDERATIONS I O Handshake Operation Programming THEORY OF FIELD INPUT OUTPUT 19 EIA RS485 AND RS422 SERIAL INTERFACE SERVICE AND SERVICE AND REPAIR ASSISTANCE 2 0 3 0 4 0 5 0 PRELIMINARY SERVICE PROCEDURE 6 0 1 am e ie e
2. THE LEADER IN INDUSTRIAL 1 105 409 24 Channel Differential Digital I O Board USER S MANUAL ACROMAG INCORPORATED Tel 248 295 0310 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Wixom MI 48393 7037 U S A solutions acromag com Copyright 2009 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 844 11 007 SERIES IOS 409 I O SERVER MODULE The information contained in this manual is subject to change without notice Acromag Inc makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag Inc assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc Table of Contents Pa 1 0 GENERAL KEY IOSJ09 FEATURES une xr pee ER AO SERVER MODULE SOFTWARE LIBRARY PREPARATION FOR UNPACKING AND BOARD lE IOS Field Connector 2
3. a errr eer 1 ENVIRONMENTAL oos 1 EIA RS485 RS422 85 1 DRAWINGS Pa 05 409 BLOCK 1 05 409 EXAMPLE CONNECTIONS 1 05 409 TERMINATION RESISTOR LOCATION 1 IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures designing any type of control or monitoring system This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall system design It is agreed between the Buyer and Acromag that this is the Buyer s responsibility 24 CHANNEL DIFFERENTIAL DIGITAL I O MODULE 1 0 GENERAL INFORMATION The I O Server Module IOS Series IOS 409 module is a 24 channel differential digital input output board with interrupts This model allows channels to be programmed as input or output on a bit basis in any combination up to 24 channels All channels can be programmed to generate Change Of State COS Low or High level transition interrupts Each channel uses a robust RS485 RS422 transceiver which permits half duplex bi directional data transfer one direction at a time The use of differential data transmission allows reliable transmission of data at high rates over up to 4000 meter distanc
4. occurs at the corresponding input channel i e any state transition low to high or high to low The Interrupt Type Configuration register at the carrier s base address offset OE is used to control channels 00 through 07 For example channel 00 is controlled via data bit O as seen in the table below Registers for Channels 15 to 08 and Channels 23 to 16 are accessed similarly at offsets OF and 10 hex respectively Interrupt Type COS or H L Configuration Register MSB LSB Data Data Bit 00 Data Bit 06 Data Bit 01 Data Bit 02 Data Bit 03 Data Bit 04 Data Bit 05 Bit 07 Channel read or write operations use 8 bit or 16 bit data transfers The upper 8 bits of register C are Not Used and will always read low 0 s for D16 accesses Note that interrupts will not occur unless they are enabled All bits are set to 0 following a reset which means that if enabled the inputs will cause interrupts for the levels specified by the digital input channel Interrupt Polarity Register SERIES IOS 409 I O SERVER MODULE 24 CHANNEL DIFFERENTIAL DIGITAL I O MODULE Interrupt Status Registers Read Write Base 12 13 14 Cho7 06 Ch05 Cho4 Ch03 Cho2 Cho1 Choo The Interrupt Status Register reflects the status of each of The upper 8 bits of register C are Not Used and will always the interrupting channels A 1 bit indicates that an interrupt is read low 0 s for D16 accesses All bi
5. Register bit and the interrupting channel s must remain disabled until the interrupt stimulus has been removed After removal of the input stimulus the channel s may be cleared and re enabled 3 Re enable the interrupting channel s by writing a 1 to the appropriate bits in the Interrupt Enable Register General Sequence of Events for Processing an Interrupt 1 The 05 409 asserts the Interrupt Request 0 Line INTREQO in response to an interrupt condition at one or more inputs 2 A generated interrupt is recognized by the carrier board and is 24 CHANNEL DIFFERENTIAL DIGITAL I O MODULE recorded in the carrier board s Interrupt Pending Register and passed to the PCI bus by driving interrupt request signal INTA active 3 The host processor uses the PCI interrupt to locate an interrupt service routine to process interrupts from the carrier board 4 The carrier board interrupt service routine examines the carrier board s Interrupt Pending Register and invokes IOS module interrupt service routines to service individual IOS modules 3 The carrier board interrupt service routine accesses the interrupt space of the IOS module selected to be serviced Note that the interrupt space accessed must correspond to the interrupt request signal driven by the IOS module 4 The carrier board will assert the INTSEL signal to the appropriate IOS module together with carrier board generated address bit A1 to select which interrupt request is
6. being processed A1 low corresponds to INTREQO A1 high corresponds to INTREQ1 5 The IOS module receives an active INTSEL signal from the carrier and supplies its interrupt vector to the host processor during this interrupt acknowledge cycle An IOS module designed to release its interrupt request on acknowledge will release its interrupt request upon receiving an active INTSEL signal from the carrier If the IOS module is designed to release it s interrupt request on register access the interrupt service routine must also access the required register to clear the interrupt request 6 If the IOS module interrupt stimulus has been removed and no other IOS modules have interrupts pending the interrupt cycle is completed i e the carrier board negates its interrupt request 4 0 THEORY OF OPERATION This section describes the basic functionality of the circuitry used on the board Refer to the IOS 409 Block Diagram as review this material FIELD INPUT OUTPUT SIGNALS The field I O interface to the IOS module is provided through connector P2 refer to Table 2 1 These pins are tied to the inputs and outputs of EIA RS485 RS422 line transceivers Signals received are converted from the required EIA RS485 RS422 voltages signals to the TTL levels required by the Field Programmable Gate Array FPGA Likewise TTL signals are converted to the EIA RS485 RS422 voltages for data output transmission The Field Programmabl
7. bits to always read high 1 s The IOS will respond to addresses that are Not Used with an active IOS module acknowledge ACK Data read at Not Used addresses will be driven low The base address for the IOS module I O space see your carrier board instructions must be added to the addresses shown in Table 3 1 to properly access the I O space Accesses can be performed on an 8 bit DOS EO or 16 bit 016 word basis SERIES IOS 409 I O SERVER MODULE Control Register Write Base 00H This read write register is used to issue a software reset Bit 0 when set to a logic high will perform a software reset When read this register will return random values Input Output Channel Registers Read Write Base 02 03 04 Twenty four possible input output channels numbered 0 through 23 may be individually accessed via these registers The Input Output Channel registers are used to monitor read or set write channels 0 through 23 Channels 7 to 0 are accessed at the carrier base address 02 via data bits 7 to 0 Channels 15 to 8 are accessed at the carrier base address 03 via data bits 15 to 8 Channels 23 to 16 are accessed at carrier base address 04 via data bits 7 to O The table below shows all channels and their corresponding I O data bit Input Output Channel 7 to 0 Register Data Data Data Data Data Bit Bit Bit Bit Bit Bit Bit Bit 07 06 05 04 03 02 01 00 Input Output Channel 15 to 8 Register Data Data D
8. motors Electrostatic Discharge Immunity ESD Complies with IEC1000 4 2 Level 1 2KV direct contact discharge at field input output terminals and European Norm EN50082 1 Surge Immunity Not required for signal I O per European Norm EN50082 1 Electric Fast Transient Immunity EF T i eot Complies with 1000 4 4 Level 2 0 5KV at field input and output terminals and European Norm EN50082 1 Radiated Emissions Meets or exceeds European Norm EN50081 1 for class A equipment Warning This is a class A product In a domestic environment this product may cause radio interference in which the user may be required to take adequate measures 10 24 independent non isolated EIA RS485 RS422 serial ports with a common signal return connection 250K bits sec Maximum 4000 feet Maximum Use of a signal repeater can extend transmission distances beyond this limit 1200 Termination Resistors installed in sockets on board at network end points only see IOS 409 Termination Resistor Location 5V Maximum 1 5V Minimum with 27Q load 3V Maximum 250mA Maximum 250ns Minimum 800ns Typical 2000ns Maximum Rpirr 540 100pF 70mV 0 500nS minimum to 2250nS maximum depending on when the input transition occurs with respect to the 8MHz clock Measured from input transition to INTREQO line assertion TRANSCEIVER
9. 1 NE a a m a e 5 2 S k 5 gt gt z 2 2 m i FPGA FPGA THE 5 485 STANDARD ALLOWS UP TO 32 DRIVER RECEIVERS TO BE CONNECTED TO A SINGLE BUS THE BUS IS A HALF DUPLEX BI DIRECTIONAL BUS BUT ONLY ONE DRIVER SHOULD BE ACTIVE AT A TIME TERMINATION SHOULD BE USED AND ONLY LOCATED AT THE TWO EXTREME ENDS OF THE BUS NOT AT EACH NODE THE PURPOSE OF THE TERMINATION IS TO PREVENT ADVERSE TRANSMISSION LINE REFLECTIONS TO MINIMIZE POWER DISSIPATION THE TERMINATION RESISTORS CAN BE LEFT OFF THIS IS POSSIBLE IF THE CABLE IS SHORT AND THE DATA RATE IS LOW IT IS ALSO POSSIBLE TO MINIMIZE POWER DISSIPATION BY USING AN RC TERMINATION IN PLACE OF THE RESISTOR TERMINATION TO MINIMIZE TRANSMISSION LINE PROBLEMS ALL NODES CONNECTED TO THE CABLE MUST USE MINIMUM STUB LENGHT CONNECTIONS IDEALLY ALL NODES SHOULD BE CONNECTED IN A DAISY CHAIN FASHION TO MINIMIZE HIGH LEVEL OF EMI THE GROUND WIRE ON PIN 50 MUST BE USED TO PROVIDE A PATH FOR INDUCED COMMON MODE NOISE AND CURRENTS THE GROUND PROVIDES LOW IMPEDANCE PATH TO REDUCE EMMISSIONS FINGOW H3AW3S 60 50 SAIYAS FINGOW IVLIOIO TIVI LN3gd3adadld TSANNVHO Ve 6 105 409 TERMINATION SIP RESISTOR LOCATION DRAWING 120 OHM RESISTOR SIPS ARE GROUPS OF FOUR R13 R12 R10 ISOLATED RESISTORS 8 PINS PIN 1 POSITION IS IDENTIFIED BY A DOT MODEL 105 409 COMPONENT SIDE PARTIAL VIEW RESISTOR IDENTIFICATION TERMINATION IP VALUE CHANNE
10. 409 I O Space Address Hex Memory HIGH Base 0 10 Y 7F HIGH Byte D15 LOW Byte D07 DOO Control Register Input Output Channel Reg B CH15 lt gt CH08 Not Used Direction Control Register B CH15 8 Not Used R W Interrupt Enable Register B 5 CH08 Not Used R W Interrupt Type Register B 5 CH08 Not Used R W Interrupt Status Register B 5 8 Not Used R W Interrupt Polarity Register B CH15 lt gt CH08 NOT USED Notes Table 3 1 1 Input Output Channel Reg A CHO7 lt gt Input Output Channel Reg C CH23 lt gt CHI16 Direction Control Register A CHO7 lt gt Direction Control Register C CH23 lt gt CH16 R W Interrupt Enable Register A CHO7 lt gt R W Interrupt Enable Register C CH23 lt gt CHI16 R W Interrupt Type Register A CHO7 R W Interrupt Type Register C CH23 lt gt CHI16 R W Interrupt Status Register A CHO7 R W Interrupt Status Register C CH23 lt gt CHI16 R W Interrupt Polarity Register A 7 lt gt R W Interrupt Polarity Register C CH23 lt gt CH16 R W Interrupt Vector Register LOW Base gt The upper 8 bits even byte of this register are not driven upon on interrupt select cycle Pullups on the carrier board data bus will cause these
11. 80 3 or equivalent This provides excellent connection integrity and utilizes gold plating in the mating area The field and logic side connectors are keyed to avoid incorrect assembly P2 pin assignments are unique to each IOS model see Table 2 1 and normally correspond to the pin numbers of the field I O interface connector on the carrier board you should verify this for your carrier board When reading Table 2 1 note that channel designations are abbreviated to save space For example channel 0 is abbreviated as 1 000 and 00 for the and connections respectively Table 2 1 105 409 Field I O Pin Connections P2 Pin Description Number Pin Description Number 6 oos 8 9 SERIES IOS 409 I O SERVER MODULE Noise and Grounding Considerations 05 409 is non isolated between the logic and field I O grounds since output common is electrically connected to the IOS module ground Consequently the field I O connections are isolated from the carrier board and backplane Two ounce copper ground plane foil has been employed in the design of this model to help minimize the effects of ground bounce impedance drops and switching transients However care should be taken designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections To minimize high levels of EMI the signal ground connection at the fie
12. For example 05 409 has channels 0 to 15 configured as outputs Channel 16 is configured as input handshake signal Ready For Data Channel 17 is configured as output handshake signal Output Data Valid The 05 409 has channels 0 to 15 configured as inputs Channel 16 is configured as output handshake signal Ready For Data Channel 17 is configured as input handshake signal Input Data Valid 24 CHANNEL DIFFERENTIAL DIGITAL I O MODULE The following step by step sequence gives an example of how data could be transferred from IOS 409A to IOS module IOS 409B 1 105 409 drives channel 16 Ready For Data signal to an active high state This indicates to the IOS 409A that the IOS 409B is ready to receive data The 05 409 drives channel 17 Output Data Valid inactive to a high state 2 OS 409A receives channel 16 Ready For Data signal as active high This indicates to the IOS 409A that the IOS 409B is ready to receive new data 105 409 drives valid data on channels 0 to 15 and drives channel 17 Output Data Valid active to a low state 4 OS 409B receives channel 17 Input Data Valid active low IOS 409B drives channel 16 Ready For Data low indicating that input register is full and is not ready for new data 5 OS 409B reads the new data from it s input register and then drives channel 16 Ready For Data high Steps 1 5 would be repeated to transfer additional data In addition channel 17 co
13. INT 001 s vo PRI P gt NOTE TERMINATION RESISTOR RT SIPS ARE MOUNTED IN SOCKETS AND MAY BE REMOVED IF REQUIRED See SIP Resistor Locotion Drawing 5 485 5 422 TRANSCEIVERS 000 1 000 2 RT Ry J NPUT OUTPUT BUS 002 002 RT TH 1 023 IT i gt COMMON PIN 5 IS SIGNAL COMMON BUS Cieero 05 409 BLOCK DIAGRAM FIELD PROGRAMMABLE LOGIC ARRAY LOGIC INTERFACE INPUT OUTPUT DIRECTION CHANNEL REGISTERS CONTROL REGISTERS ADDRESS BUS d Eres CONTROL REGISTERS E CONTROL BUS INTERRUPT j TYPE REGISTERS ACKNOWLEBGE INTERRUPT ADDRESS DECODING j POLARITY REGISTERS NTERRUPT AND IP BUS INTERFACE LOGIC eee INTERRUPT STATUS REGISTERS FPGA INTERRUPT ID PROM CONFIGURATION ECTOR REGISTER EMORY T X DATA BUS D15 D 15V SUPPLY NON SUPPLY FILTERING COMMON P GND FINGOW H3AW3S 60 50 SAIYAS FINGOW IVLIOIO TIVI LN3gd3adadld TSANNVHO Ve g RS485 HALF DUPLEX MULTIPOINT NETWORK UNIT 1 UNIT N lt 33 LRT LRT Dr 0 I O CHANNEL m N I O CHANNEL E gt gt FS 9 gt 4 i 4 DIRECTION DIRECTION FPGA 5 5 lt gt UNT 2 UNIT N
14. LS RB 120 OHM R9 120 OHM R10 05 409 PARTIAL VIEW R10 120 OHM 8 9 10 11 13 14 15 19 12 16 17 18 20 21 22 25 NOTES CONCERNING RESISTOR PLACEMENT AND REMOVAL TERMINATION RESISTORS SHOULD ONLY BE USED AT THE TWO EXTREME ENDS OF THE BUS AND NOT AT EACH NODE THE SIP TERMINATION RESISTORS OF THE 105 409 ARE MOUNTED IN SOCKETS AND CAN BE REMOVED IF REQUIRED FINGOW H3AW3S 60 50 SAIYAS FINGOW IVLIOIO WILNSYSsssIC TSANNVHO Ve
15. OS MODULE Win32 DRIVER SOFTWARE Acromag provides a software product sold separately to facilitate the development of Windows Embedded Standard applications interfacing with I O Server Modules installed on Acromag Industrial I O Server systems This software Model IOSSW DEV WIN consists of a low level driver and Windows 32 Dynamic Link Libraries DLLS that are compatible with a number of programming environments including Visual C Visual Basic NET Borland Builder and others The DLL functions provide a high level interface to the IOS carrier and modules eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers IOS MODULE LINUX SOFTWARE Acromag provides a software product sold separately consisting of Linux amp software This software Model IOSSW API LNX is composed of Linux libraries designed to support applications accessing I O Server Modules installed on Acromag Industrial Server systems The software is implemented as library of C functions which link with existing user code 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep th
16. ata Data Data Data Bit Bit Bit Bit Bit Bit Bit Bit 15 14 13 12 11 10 09 08 Input Output Channel 23 to 16 Register Data Data Data Data Data Data Bit Bit Bit Bit Bit Bit 06 05 04 03 02 01 Data Data Data Data Data Data Bit 00 Data Bit 07 Channel read write operations use 8 bit or 16 bit data transfers with the lower ordered bits corresponding to the lower numbered channels for the register of interest All input output channels are configured as inputs on a power on or software reset The unused upper 8 bits of register C are Not Used and will always read low 0 s for D16 accesses Direction Control Registers Read Write Base 06 07 08 The data direction input or output of the 24 differential channels is selected via these registers The data direction of each channel can be independently set on a bit by bit basis Setting a bit high configures the corresponding channel data direction for output Setting the control bit low configures the corresponding channel data direction for input The default power up state of these registers is logic low Thus all channels are configured as inputs on system reset or power up The unused upper byte of register C is Not Used and will always read low 05 Interrupt Enable Registers Read Write Base 0A OB OC The Interrupt Enable Registers provide a mask bit for each of the 24 channels A 0 bit will prevent the corresponding input channel from gene
17. cessing Change of State Interrupts 1 Clear the interrupting channel s by writing a 1 to the appropriate bits in the 05 409 Interrupt Status Register Programming Example for Level Polarity Match Interrupts 1 Select channel Polarity Match Interrupts by writing a 0 to each channel s respective bit in the Interrupt Type Register Note that Change Of State interrupts specified with 1 may be mixed with Polarity Match Interrupts specified with O 3 Select the desired polarity High Low level for interrupts by writing a 0 Low or 1 High level to each channel s respective bit in the Interrupt Polarity Register 4 Enable individual input channel interrupts by writing a 1 to each channel s respective bit in the Interrupt Enable Register 5 Clear pending interrupts by writing a 1 to each channel s respective bit in the Interrupt Status Register Interrupts can now be generated by matching the input level with the selected polarity for programmed interrupt channels Processing Level Polarity Match Interrupts 1 Disable the interrupting channel s by writing a O to the appropriate bits in the IOS 409 Interrupt Enable Register 2 After the interrupt stimulus has been removed clear the interrupting channel s by writing a 1 to the appropriate bits in the 05 409 Interrupt Status Register If the input stimulus is still applied this will not clear the Interrupt Status
18. culating this bandwidth The total response time is the sum of the input buffer response time plus the interrupt logic circuit response time and this time must pass before another interrupt condition will be recognized The Interrupt Input Response Time is specified in section 6 SERIES IOS 409 I O SERVER MODULE Interrupt Programming Example 1 Clear the Interrupt Enable Bits in the Carrier Board Status Register by writing a O to bit 2 and bit 3 2 Perform Specific IOS 409 Module Programming see the Change of State or Level Polarity Match programming examples that follow as required for your application 3 Write a 1 to bit 2 of the Carrier Status Control Register Module Interrupt Enable bit to enable IOS module interrupts to the PCI bus Programming Example for Change of State Interrupts 1 Select channel Change of State interrupts by writing a 1 to each channel s respective bit in the Interrupt Type Register Note that Change Of State interrupts specified with 1 may be mixed with polarity match interrupts specified with O 3 Enable individual input channel interrupts by writing a 1 to each channel s respective bit in the Interrupt Enable Register 4 Clear pending interrupts by writing a 1 to each channel s respective bit in the Interrupt Status Register Change of State Interrupts may now be generated by the input channels programmed above for any Change Of State transition Pro
19. e Gate Array provides the necessary interface to the RS485 RS422 transceivers for control of data output or input and monitoring of input signals for generation of interrupts if enabled The field I O interface to the carrier board is provided through connector P2 refer to Table 2 1 Field I O points are NON ISOLATED This means that the field return and logic common have a direct electrical connection to each other As such care must be taken to avoid ground loops see Section 2 for connection recommendations Ignoring this effect may cause operational errors and with extreme abuse possible circuit damage Interrupt Operation Digital input channels of this model can be configured to generate interrupts for Change Of State COS and input level polarity match conditions at enabled inputs An 8 bit interrupt SERIES IOS 409 I O SERVER MODULE 24 CHANNEL DIFFERENTIAL DIGITAL I O MODULE service routine vector is provided during interrupt acknowledge cycles on data lines DO D7 The interrupt release mechanism PRELIMINARY SERVICE PROCEDURE employed is RORA Release On Register Access Before beginning repair be sure that all of the procedures in Fail Safe Operation Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier board to verify that it is The 05 409 operation is considered Fail safe That is the correctly configured Replacement of the module with one that is input output chan
20. e carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected for evidence of mishandling prior to applying power V CAUTION SENSITIVE ELECTRONIC DEVICES DO NOT SHH OR STORE NEAR BTRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS The board utilizes static sensitive components and should only be handled at a static safe workstation 24 CHANNEL DIFFERENTIAL DIGITAL I O MODULE BOARD CONFIGURATION Power should be removed from the board when installing 105 modules cables termination panels and field wiring Refer to the following discussion for configuration and assembly instructions Model 05 409 I O Boards have no jumpers or switches to configure interrupts are configured through software commands CONNECTORS lOS Field I O Connector P2 P2 provides the field I O interface connector for mating IOS modules to the carrier board P2 is a 50 pin female receptacle header AMP 173279 3 or equivalent which mates to the male connector of the carrier board 1732
21. el Configuration ie e caelo 4 030 in 102 36 mm PP 1 930 49 02 Board Thickness 0 062 in 1 59 mm Height 0 500 in 12 7 mm Data Cable Length Power Configured as Output with Termination Resistors Installed 5 Volts 59 600mA Typical 800mA Maximum Termination Resistors Configured as Input 5 Volts 59 20mA Typical 30mA Maximum 12 Volts 5 from 1 Not Used Differential Output Voltage Maximum Vcc Rise Time 100m seconds Common Mode Output ENVIRONMENTAL MOltagQu tao Output Short Circuit Current Operating Temperature 40 C to 85 Relative Humidity 5 95 Non Condensing Rise Fall Storage Temperature 55 to 125 C Non Isolated Logic and field commons have a direct electrical connection Input Hysteresis Resistance to RFlI Designed to comply with IEC1000 4 3 Level 3 10V m at Interrupt Input Response frequencies o f 27MHz to iq m 500MHz and European Norm EN50082 1 Electromagnetic Interference Immunity EMI No digital upset under the influence of EMI from switching solenoids commutator motors and drill
22. ement loopback output control e Long Distance Data Transmission Data transmission with up to 32 nodes and up to 4000 feet is possible Robust RS485 RS422 Transceivers The 05 409 is designed for electrically harsh environments All differential I O channels are protected against electrostatic discharge ESD electrical fast transient EFT and electromagnetic interference EMI e Programmable Change of State Level Interrupts Interrupts are software programmable for any bit Change Of State or Level on an individual channel basis e Socketed Termination Resistors The network termination resistors are installed in sockets on the board and may be easily inserted or removed as required Configuration Jumpers or Switches All configuration is performed through software commands with no internal jumpers to configure or switches to set e Power Up amp System Reset is Failsafe For safety all channels are configured as input upon power up and after a system reset SERIES IOS 409 I O SERVER MODULE e Output Channels With Read Back The differential output channel registers can be read back to verify programmed logic levels e Conduction Cooled Module 1 0 modules employ advanced thermal technologies A thermal pad and module cover wicks heat away from the module and transfers the energy to a heat spreading friction plate Heat moves to the enclosure walls where it is dissipated by the external cooling fins I
23. es and through noisy environments Differential transmission nullifies the effects of ground shifts and noise signals which appear as common mode voltages on the line The 05 409 model temperature range is 40 C to 85 C Four units mounted on a carrier board provide up to 96 I O points per 6U VMEbus system slot Since each channel can be independently programmed as an input or output loopback monitoring is possible A channel programmed as an input can be used to monitor another channel programmed as an output The 05 409 utilizes state of the art Surface Mounted Technology SMT to achieve its high channel density and is an ideal choice for a wide range of industrial control and monitor applications that require high density high reliability and high performance at a low cost Important Note The following IOS model are accessories to the IOS Server Models IOS 7200 IOS 7200 WIN IOS 7400 and IOS 7400 WIN which are cULus Listed This equipment is suitable for use in Class Division 2 Groups A B C and D or non hazardous locations only KEY 5 409 FEATURES e High Channel Count Interfaces with up to 24 input output points Four units mounted on a carrier board provide up to 96 input and or output channels in a single system slot Input and output channels may be intermixed in any combination The input circuitry of a single channel can also be used to monitor the output state of a different channel to efficiently impl
24. ld I O port pin 50 should be used to provide a path for induced common mode noise and currents The ground path provides a low impedance path to reduce emissions EIA RS485 RS422 communication distances are generally limited to less than 4000 feet To minimize transmission line problems all nodes connected to the cable must use minimum stub length connections The optimal configuration for the RS485 RS422 bus is a daisy chain connection from node 1 to node 2 to node 3 to node n The bus must form a single continuous path and the nodes in the middle of the bus must not be at the ends of long branches spokes or stubs See 05 409 Example I O Connections for example connection and termination practices Transmission line signal reflections can be minimized with proper termination The EIA RS485 RS422 standard allows up to 32 driver receivers to be connected to a single bus Termination resistors should only be used at the two extreme ends of the bus and not at each of the nodes of the bus 3 0 PROGRAMMING INFORMATION ADDRESS MAPS This board is addressable in the I O Server Module space to control the data transfer and steering logic of the 24 EIA RS485 RS422 serial ports The I O space may be as large as 64 16 bit words 128 bytes using address lines A1 A6 but the IOS 409 only uses a portion of this space The I O space address map for the IOS 409 is shown in Table 3 1 24 CHANNEL DIFFERENTIAL DIGITAL I O MODULE Table 3 1 05
25. nels are always configured as input upon power known to work correctly is a good technique to isolate a faulty up reset and a system software reset This is done for safety module reasons to ensure reliable control of the output state under all conditions CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS EIA RS485 AND RS422 SERIAL INTERFACE Acromag s Applications Engineers can provide further technical assistance if required When needed complete repair The EIA RS485 and RS422 interface specifies a balanced services are also available from Acromag driver with balanced receivers Balanced data transmission refers to the fact that two conductors are switched per signal and the logical state of the data is referenced by the difference in potential between the two conductors not with respect to signal ground The differential method of data transmission makes EIA RS485 and RS422 ideal for noisy environments since it minimizes the effects of coupled noise and ground potential differences That is since these effects are seen as common mode voltages common to both lines not differential they are rejected by the receivers The EIA RS422 standard defines a bus with a single driver and multiple receivers The EIA RS485 standard defines a bi directional terminated driver and receiver configuration Half duplex operation is provided by the sharing of a single data path for transmit and receive The maximum data t
26. ransmission cable length is generally limited to 4000 feet without a signal repeater installed With respect to EIA RS485 and RS422 logic states are represented by differential voltages from 1 5 to 5V The polarity of the differential voltage determines the logical state A logic 0 is represented by a negative differential voltage between the terminals measured A to or to A logic 1 is represented by a positive differential voltage between the terminals measured A to B or to The line receivers convert these signals to the conventional TTL level 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be easily damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair SERIES IOS 409 I O SERVER MODULE 24 CHANNEL DIFFERENTIAL DIGITAL I O MODULE 6 0 SPECIFICATIONS PHYSICAL EIA RS485 TRANSCEIVERS Physical Configuration Single I O Server Module Chann
27. rating an external interrupt A 1 bit will allow 24 CHANNEL DIFFERENTIAL DIGITAL I O MODULE the corresponding input channel to generate an interrupt Only those channels configured as inputs can generate interrupts The Interrupt Enable register at the carrier s base address offset OA is used to control channels 00 through 07 For example channel 00 is controlled via data bit O as seen in the table below Registers for Channels 15 to 08 and Channels 23 to 16 are accessed similarly at offsets OB and OC hex respectively Interrupt Enable Register MSB Data LSB Data Data Bit Bit Bit Bit Bit Bit Bit Bit 07 06 05 04 03 02 01 00 Channel read operations use 8 bit or 16 bit data transfers The upper 8 bits of register C are Not Used and will always read low 0 s for D16 accesses Data Data Data Data Data All input channel interrupts are disabled set to O following a power on or software reset Interrupt Type COS or H L Configuration Registers Read Write Base OE OF 10 The Interrupt Type Configuration Registers determine the type of input channel transition that will generate an interrupt for each of the 24 possible interrupting channels A 0 bit selects interrupt on level An interrupt will be generated when the input channel level specified by the Interrupt Polarity Register occurs i e Low or High level transition interrupt A 1 bit means the interrupt will occur when a Change Of State COS
28. se address offset 16 is used to control channels 00 through 07 For example 08 i Acromag ID Code channel 00 is controlled via data bit O as seen in the table below iOS Model Gode Registers for Channels 15 to 8 and Channels 23 to 16 are EL 0 Not Used accessed similarly at offsets 17 and 18 hex respectively Revision 0E 00 Reserved 10 Not Used o 12 00 Not Used 14 OC Total Number of ID PROM Bytes 16 Be Interrupt Polarity Register MSB LSB Data Data Data Data Data Data Data Data Bit Bit Bit Bit Bit Bit Bit Bit SERIES IOS 409 I O SERVER MODULE 18t03bE y Not Used Notes Table 3 2 1 The IOS model number is represented by a two digit code within the ID space the IOS 409 model is represented by 20 Hex IOS 409 PROGRAMMING CONSIDERATIONS To make programming and communicating with the board easier Acromag provides you with the I O Server Module Software Library diskette The functions provided are written in the programming language and can be linked into your application Refer to the README TXT file in the root directory and the INFO409 TXT file in the 405 409 subdirectory on the diskette for details Acromag also provides a software diskette of IOS module Object Linking and Embedding OLE drivers for Windows 956 and Windows NT compatible application programs Model IOSSW OLE PCI MSDOS format This software provides indi
29. sing always read low 0 s for D16 accesses All bits are set to 0 only the odd addresses in a 64 byte block on the Big Endian following a reset which means that all interrupts are cleared VMEbus Even addresses are used on the Little Endian PC ISA or PCI buses Interrupt Polarity Registers Read Write Base 16 17 18 The 05 409 ID Space contents are shown in Table 3 2 The Interrupt Polarity Register determines the level that will Note that the base address for the IOS module ID space see cause a channel interrupt to occur for each of the channels your carrier board instructions must be added to the addresses enabled for level interrupts A 0 bit specifies that an interrupt shown to properly access the ID information Execution of an ID will occur when the corresponding input channel is low i e a 0 Space Read operation requires 0 wait states in the digital input channel data register A 1 bit means that an interrupt will occur when the input channel is high i e a 1 in the Table 3 2 105 409 ID Space Identification ID digital input channel data register Note that no interrupts will Hex Offset occur unless they are enabled by the Interrupt Enable Register From ID Numeric Further the Interrupt Polarity Register will have no effect if the Base Change of State COS interrupt type is configured by the Address Interrupt Type Configuration Register The Interrupt Polarity register at the carriers ba
30. terrupt prioritization E 07 06 0 o2 01 00 The Interrupt Status register at the carrier s base address offset 12 is used to monitor pending interrupts corresponding to Interrupts are released on register access to the Interrupt channels 00 through 07 For example channel 00 is monitored Status register Issue of a software or hardware reset will clear via data bit 0 as seen in the table below Registers for Channels the contents of this register to 0 15 to 08 and Channels 23 to 16 are accessed similarly at offsets 13 and 14 hex respectively IOS Identification Space Read Only 32 evenbyte addresses Each IOS module contains identification ID information that resides in the ID space per the IOS module specification This area of memory contains 32 bytes of information at most Both fixed and variable information may be present within the ID space Fixed information includes the IOS identifier model Interrupt Status Register MSB LSB Data Data Data Data Data Data Data Data Bit Bit Bit Bit Bit Bit Bit Bit 07 06 05 04 03 02 01 00 edat number and manufacturer s identification codes Variable Ch07 Ch06 5 ChO3 Ch02 Choo information includes unique information required for the module The 05 409 ID Space does not contain any variable e g unique The unused upper 8 bits of register are Not Used and will calibration information ID Space bytes are addressed u
31. ts are set to 0 following a pending for the corresponding channel A channel that does not reset which means that the inputs will cause interrupts when they have interrupts enabled will never set its interrupt status flag A are below TTL threshold provided they are enabled for interrupt channel s interrupt be cleared by writing 1 to its bit on level position in the Interrupt Status Register writing a 1 acts as a reset signal to clear the set state This is known as the Release Interrupt Vector Register Read Write Base 1A On Register Access RORA method as defined in the VME system architecture specification However if the condition which The Interrupt Vector Register maintains an 8 bit interrupt caused the interrupt to occur remains the interrupt will be pointer for all channels configured as input channels The Vector generated again unless disabled via the Interrupt Enable Register can be written with an 8 bit interrupt vector This vector Register In addition an interrupt will be generated if any of the is provided to the carrier and system bus upon an active INTSEL channels enabled for interrupt have an interrupt pending i e one cycle Reading or writing to this register is possible via 16 bit or that has not been cleared Writing 0 to a bit location has no 8 bit data transfers effect that is a pending interrupt will remain pending Interrupt Vector Register EE de ue system software must handle in
32. uld be programmed at the IOS 409B to generate an interrupt upon a change of state to logic low The interrupt service routine could set channel 16 low and read the input data register After the data is read the interrupt service routine could set channel 16 high to inform IOS 409A it is ready for new data Programming Interrupts Digital input channels can be programmed to generate interrupts for the following conditions e Change of State COS at selected input channels e Input level polarity match at selected input channels Interrupts generated by the IOS 409 use interrupt request line INTREQO Interrupt Request O The interrupt release mechanism employed is the Release On Register Access RORA type This means that the interrupter will release the I O Server Module interrupt request line INTREQO after all pending interrupts have been cleared by writing a 1 to the appropriate bit positions in the input channel Interrupt Status Register The Interrupt Vector Register contains a pointer vector to an interrupt handling routine One interrupt handling routine must be used to service all possible channel interrupts When using interrupts input channel bandwidth should be limited to reduce the possibility of missing channel interrupts For a given input channel this could happen if multiple changes occur before the channel s interrupt is serviced The response time of the input channels should also be considered when cal
33. vidual drivers that allow all IOS modules and the APC8620 carrier to be easily integrated into Windows application programs such as Visual C Visual Basic Borland Delphi amp Microsoft Office 97 applications and others The OLE controls provide a high level interface to IOS modules eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers all the complicated details of programming are handled by the OLE controls These functions are intended for use in conjunction with an Acromag personal computer carrier and consist of a carrier OLE control and an OLE control for each Acromag IOS module as well as a generic OLE control for non Acromag IOS modules I O Handshake Operation 05 409 has 24 channels that can be independently configured as input or output ports With independent configuration of channels the 05 409 can be used to move data in either direction on a word by word basis The data word size can be any number of user defined bits up to the 24 channels minus the number of handshake channels used Channels not used to move data can be defined as handshake signals The handshake channels can consist of status input lines and control output lines There are a number of different handshake protocols available For example two directly connected IOS 409 modules could transfer 16 bit data from IOS 409A to 05 409 The IOS 409B will acknowledge the transfer

IOS-409 User`s Manual

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