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Transmit pre-arbitration scheme for a can device and a can device

1. 2 PROGRAM BUS i 24 32K BYTES SFR BUS ROM EPROM go ded 1 26 1024 BYTES BUS DATA RAM 27 EXTERNAL F51 ADDRESS e Sk DATABUS MEMORY MMR BUS i T INTERFACE 4 2 er E 53 8 TIMER T ELM Ea x WATCHDOG 1 7 2 08 Lu 0 5 Patent 21 2003 Sheet 1 of 7 US 6 510 479 B1 STANDARD IFS Idle DEL 7 bits 36 Data Field 0 1 8 Bytes 0 8 64 bits EXTENDED RemoteTransmitRequest ORR SubstituteRemoteRequest ID Extension r1 10 reserved bits DLC DataLengthCode 0 1 8 IFS InterFrameSpace FIG 1 CAN bus 8 8 Byte 4 8 Byte CAL Message B baa ae ee ee 0 5 Patent 21 2003 Sheet 2 of 7 US 6 510 479 B1 CORE DATA BUS XA CPU CORE 22 PROGRAM BUS S2KBYTES ROM EPROM ge ur 7 DAT i og 1024BYTES BUS DATA RAM UARTO 27 XRAM 28 36 SPI 99 EXTERMAL ADDRESS DATABUS MEMORY MMR BUS r P INTERFACE 53 32 TIMER 1 54 i TIMER 2 WATCHDOG TIMER Tx r 0 5 Patent 21 2003 Sheet 3 of 7 US 6 510 479 B1 MMRs Address Offset Message Object Registers n 0 31 O0 0nunanonino0000b nOh Message n Match ID High 00 Message n Butler Location 000000 Message n Buffer Size Message n Fragmentation Count C
2. collectively be considered to constitute a CAN CAL module 77 and will be referred to as such at various times through out the following description Further the particular logic elements within the CAN CAL module 77 that perform message management and message handling functions will sometimes be referred to as the message management engine and the message handler respectively at various times throughout the following description Other nomen clature will be defined as it introduced throughout the following description As previously mentioned the XA C3 microcontroller 20 automatically implements in hardware many message man agement and other functions that were previously only implemented in software running on the host CPU or not implemented at all including transparent automatic re assembly of up to 32 concurrent interleaved multi frame fragmented CAL messages For each application that is installed to run on the host CPU 1 the XA CPU Core 22 the user software programmer must set up the hard 05 6 510 479 1 7 ware for performing these functions by programming certain ones of the MMRs and SFRs in the manner set forth in the XA C3 Functional Specification and XA C3 CAN Transport Layer Controller User Manual The register programming procedures that are most relevant to an understanding of the present invention are described below followed by a description of the various message man
3. Although the persent invention has been described in detail hereinabove in the context of a specific perferred embodiment implementation it should be clearly under 05 6 510 479 1 19 stood that many variation modification and or alternative embodiments implementations of the basic inventive con cepts taught herein which may appear to those skilled in the pertinent art will still fall within the spirit and scope of the present invention as defined in the appended claims What is claimed is 1 A CAN device that supports a plurality of message objects comprising at least one object specific control register associated with each message object wherein the at least one object specific control register associated with each message object is programmable for the purpose of enabling or disabling the associated message object as a transmit or receive message object thereby providing a user with the capability to concurrently stage two or more trans mit messages for attempted transmission over a CAN bus coupled to the CAN device according to a gov erning CAN protocol and a CAN CAL module that processes both receive and transmit messages the CAN CAL module including a transmit pre arbitration engine that determines which of two or more transmit messages concurrently staged for attempted transmission over the CAN bus has priority wherein the message determined to have pri ority comprises a winning message and the message obje
4. 1 If the Tx Message Complete interrupt is enabled for the transmit message the user application would write the next transmit message to the designated transmit message buffer upon receipt of the Tx Message Complete interrupt Once the interrupt flag is set it is known for certain that the pending transmit message has already been transmit ted 2 Wait until the EN bit of the MnCTL register of the associated Transmit Message Object clears before writing to the associated transmit message buffer This can be accomplished by polling the bit of MnCTL register of the associated Transmit Message Object 3 Clear the EN bit of the MnCTL register of the associated Transmit Message Object while that Transmit Message Object is still in Tx Pre Arbitration In the first two cases above the pending transmit message will be transmitted completely before the next transmit 5 10 15 20 25 30 35 40 45 50 55 60 65 14 message gets transmitted For the third case above the transmit message will not be transmitted Instead a transmit message with new content will enter Tx Pre Arbitration There is an additional mechanism that prevents corruption of a message that is being transmitted In particular if a transmission is ongoing for a Transmit Message Object the user will be prevented from clearing the EN bit in the MnCTL register associated with that particular Transmit Message Obj
5. 215 38 a7 20 0 5 Patent 21 2003 Sheet 6 of 7 US 6 510 479 B1 Object n Match ID Field MnMIDH and MnMIDL Mid28 Mid8 Midi7 Midi0 Mid9 Mid2 Midi Mido MIDE Object n Mask Field MnMSKH and MnMSKL Msk28 5 8 Msk17 Mski0 Msk9 Msk2 Mskl Screener ID Field assembled from incoming bit stream Object n Match ID Field MnMIDH and MnMIDL Mid28 Midi8 Mid9 Mid2 Midt Midd MIDE Object n Mask Field MnMSKH and MnMSKL Msk28 Mski8 Msk17 Msk10 Msk9 Msk2 Mskl Screener ID Field assembled from incoming bit stream IDE FIG 10 U S Patent Jan 21 2003 Sheet 7 of 7 US 6 510 479 B1 DIRECTION OF INCREASING ADDRESS DIRECTION OF INCREASING ADDRESS Framelnfo Data Byte 1 Data Byte 2 Data Byte DLC Framelnfo next Data Byte 1 next Data Byte 2 next FIG 12 05 6 510 479 1 1 TRANSMIT PRE ARBITRATION SCHEME FOR A CAN DEVICE AND A CAN DEVICE THAT IMPLEMENTS THIS SCHEME This application claims the full benefit and priority of U S Provisional Application Ser No 60 154 022 filed on Sep 15 1999 the disclosure of which is fully incorporated herein for all purposes BACKGROUND OF THE INVENTION The present invention relates generally to the field of data communications and more particularly to the field of serial communications bus controllers and microc
6. 60 65 2 is believed that the XA C3 is the first chip that features hardware CAL support The XA C3 is a CMOS 16 bit CAL CAN 2 0B micro controller that incorporates a number of different inventions including the present invention These inventions include novel techniques and hardware for filtering buffering handling and processing CAL CAN messages including the automatic assembly of multi frame fragmented mes sages with minimal CPU intervention as well as for man aging the storage and retrieval of the message data and the memory resources utilized therefor The present invention relates to a CAN microcontroller that supports a plurality e g 32 of message objects each one of which is assigned a respective message buffer within an on chip and or off chip portion of the overall data memory space of the CAN microcontroller The location and size of each of the message buffers can be reconfigured by the user programmer by simple programming of memory mapped registers provided for this purpose The message buffers are used to store incoming receive messages and to stage outgoing transmit messages With the XA C3 micro controller that constitutes a presently preferred implemen tation of the present invention Direct Memory Access DMA is employed to enable the XA C3 CAN module to directly access any of the 32 message buffers without interrupting the processor core This message storage scheme provides a great deal of f
7. CAN CAL module 7 The CAN device as set forth in claim 1 wherein the CAN CAL module further includes a transmit engine that attempts to transmit the winning message over the CAN bus according to a CAN bus arbitration priority scheme established by the governing CAN protocol and the transmit pre arbitration engine determines priority between the two or more transmit messages concur rently staged for attempted transmission over the CAN bus according to the CAN bus arbitration priority scheme established by the governing CAN protocol 20 25 30 35 50 55 60 65 20 8 The CAN device as set forth in claim 7 wherein the CAN bus arbitration priority scheme comprises examining CAN arbitration field contained in a header portion of each of the two or more transmit messages concurrently staged for attempted transmission over the CAN bus and then selecting the transmit message having a highest assigned priority according to the governing CAN protocol as the winning message 9 The CAN device as set forth in claim 1 wherein the message objects are uniquely numbered and in the event that more than one of the two or more transmit messages concurrently staged for attempted transmis sion over the CAN bus are determined to have the same priority the transmit pre arbitration engine designates the transmit message associated with the lowest numbered message object as the winning message 10 The CAN device as set f
8. CAN bus by selecting the transmit message associated with a highest numbered message object as the winning message wherein the message objects are uniquely numbered 17 The CAN device as set forth in claim 15 wherein the two or more pre arbitration schemes include a first pre arbitration scheme whereby the transmit pre arbitration engine determines priority between the two or more transmit messages concurrently staged for attempted transmission over the CAN bus according to CAN bus arbitration priority scheme established by the governing CAN protocol and a first pre arbitration scheme whereby the transmit pre arbitration engine determines priority between the two or more transmit messages concurrently staged for attempted transmission over the CAN bus by selecting the transmit message associated with a lowest numbered message object as the winning message wherein the message objects are uniquely numbered 18 The CAN device as set forth in claim 1 wherein the CAN CAL module further includes a transmit engine that attempts to transmit the winning message over the CAN bus according to a CAN bus arbitration priority scheme established by the governing CAN protocol and if the winning message is not granted access to the CAN bus according to the CAN bus arbitration priority scheme the transmit pre arbitration engine is reset to repeat the pre arbitration priority determination pro cess 19 The CAN device as set forth in cl
9. receive messages concurrently 26 In a CAN device that supports a plurality of message objects a method comprising enabling two or more message objects as transmit mes sage objects concurrently staging two or more transmit messages asso ciated with respective ones of the two or more enabled transmit message objects for attempted transmission over a CAN bus coupled to the CAN device and performing a pre arbitration process to determine which of the two or more concurrently staged transmit mes sages has priority wherein the message determined to have priority comprises a winning message and the message object associated with the winning message comprises a winning message object 27 The method as set forth in claim 26 wherein the pre arbitration process is a selected one of at least two pre arbitration schemes 28 The method as set forth in claim 27 wherein the two or more pre arbitration schemes include a first pre arbitration scheme whereby priority is deter mined according to a CAN bus arbitration priority scheme established by the governing CAN protocol and second pre arbitration scheme whereby priority is deter mined by selecting the transmit message associated with a highest numbered message object as the winning message wherein the message objects are uniquely numbered 29 The method as set forth in claim 27 wherein the two or more pre arbitration schemes include first pre arbitration scheme whe
10. 3 microcontroller FIG 4 is a table listing all of the Memory Mapped Registers MMRs provided by the XA C3 microcontroller FIG 5 is a diagram illustrating the mapping of the overall data memory space of the XA C3 microcontroller FIG 6 is a diagram illustrating the MMR space contained within the overall data memory space of the XA C3 micro controller FIG 7 is a diagram illustrating formation of the base address of the on chip XRAM of the XA C3 microcontroller with an object n message buffer mapped into off chip data memory FIG 8 is a diagram illustrating formation of the base address of the on chip XRAM of the XA C3 microcontroller with an object n message buffer mapped into the on chip XRAM FIG 9 is a diagram illustrating the Screener ID Field for a Standard CAN Frame FIG 10 is a diagram illustrating the Screener ID Field for an Extended CAN Frame FIG 11 is a diagram illustrating the message storage format for fragmented CAL messages and FIG 12 is a diagram illustrating the message storage format for fragmented CAN messages DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention is described below in the context of a particular implementation thereof 1 in the context of the XA C3 microcontroller manufactured by Philips Semicon ductors Of course it should be clearly understood that the present invention is not limited to this particular implementation as any one or more of the various
11. AN bus must compete with all other transmitting devices on the network for access to the CAN bus at any given time It will be appreciated that access onto the CAN bus is governed by the arbitration process inherent in the governing CAN protocol and thus need not be described herein As was also previously described if the winning Transmit Message Object loses arbitration on the CAN bus the transmit pre arbitration process is gets reset and starts over This ensures that the XA CAN CAL module 77 transmit pre arbitration is always based on up to date information Thus if the software e g CAN application running on the XA CPU Core 22 enables new messages for transmission or disables a previously pending transmit message the transmit pre arbitration engine will detect this change prior to initi ating a new transmit cycle It will be appreciated that the XA CAN CAL module 77 has the unique capability of allowing transmit pre arbitration of pending transmit messages and input acceptance filtering of receive messages to be handled concurrently using the same logic module and the same state machine within the CAN CAL module 77 This capability improves system performance and minimizes the required die area The two different transmit pre arbitration schemes or policies that are supported as options by the XA CAN CAL module 77 are as follows The first optional scheme per forms transmit pre arbitration based upon the same priority scheme tha
12. IC Registers MCR RO 00 MER RO Byte Word Frame Error Enable Register CCB Registers Wr Brea RW 00h 2n Timing Reg high RW 00h RW 2n Error Warning Limit Register LER 106 0 2 0 Error Code Capture Register AR 10 ByeWod _ 27 Arbitration Lost Capture Reg Registers Legend RAN Read amp Write RO Read Only WO Write Only R C Read amp Clear W Writable only during F 4 CAN Reset mode x undefined after reset 0 5 Patent 21 2003 Sheet 4 of 7 US 6 510 479 B1 Data Memory Segment 0 OOFFFFh LLLLLLLL Off Chip AK Bytes MMR Space CTT TTT MMR Base Address Off Chip XRAM Base Address Off Chip Data Memory Scratch Pad 1 0000000 5 MMR Space 512 Bytes Object Registers Offset FIG 6 Offset 000h 0 5 Patent 21 2003 Sheet 5 of 7 US 6 510 479 B1 Segment xy in Data Memory Space xyFFFFh Object nf Object n Message Buffer 423 416 215 40 Buffer size r lt MBXSR 7 0 MnBLR ee XRAM 512 Bytes a23 216215 a8 a a0 Darm uw Segment xy in Data Memory Space XyFFFFh 403 2416 415 20 es eee MBXSR 7 0 MnBLR Object n Message Buffer proe MEL NW NNNM xy0000h FIG 8 Object if XRAM Buffer size 512 Bytes 323 216
13. US006510479B1 a United States Patent Hao US 6 510 479 B1 Jan 21 2003 10 Patent No 45 Date of Patent MT 55 PORTS 0 3 54 TRANSMIT PRE ARBITRATION SCHEME Primary Examiner Sumati Lefkowitz FOR A CAN DEVICE AND A CAN DEVICE Assistant Examiner Christopher E Lee THAT IMPLEMENTS THIS SCHEME 57 ABSTRACT 75 Inventor Hong Bin Hao San Jose CA US In CAN device e g CAN microcontroller that supports 73 Assignee Koninklijke Philips Electronics N V a plurality of message objects a method that includes Eindhoven NL concurrently staging two or more transmit messages asso Notice Subject to any disclaimer the term of this ciated with respective ones of two or more enabled transmit patent is extended or adjusted under 35 message objects for attempted transmission over a CAN bus U S C 154 b by 255 days coupled to the CAN device and performing a pre arbitration process to determine which of the two or more concurrently 21 Appl No 09 630 642 staged transmit messages has priority The message deter 22 Filed Aug 1 2000 mined to have priority is deemed a winning message and the message object associated with the winning message is Related U S Application Data deemed a winning message object In a presently preferred 60 Provisional application No 60 154 022 filed on Sep 15 embodiment the pre arbitration process is a selected one of 1999 at least two pre arbitration schemes inclu
14. agement and other functions that are automatically performed by the CAN module 77 during operation of the XA C3 microcon troller 20 after it has been properly set up by the user Following these sections a more detailed description of the particular invention to which this application is directed is provided Set up Programming Procedures As an initial matter the user must map the overall XA C3 data memory space as illustrated in FIG 5 In particular subject to certain constraints the user must specify the starting or base address of the XRAM 28 and the starting or base address of the MMRs 40 The base address of the MMRs 40 can be specified by appropriately programming Special Function Registers SFRs MRBL and MRBH The base address of the XRAM 28 can be specified by appro priately programming the MMRs designated MBXSR and XRAMB see FIG 4 The user can place the 4 KByte space reserved for MMRs 40 anywhere within the entire 16 Mbyte data memory space supported by the XA architecture other than at the very bottom of the memory space 1 the first 1 KByte portion starting address of 000000h where it would conflict with the on chip Data RAM 26 that serves as the internal or scratch pad memory The 4 KBytes of MMR space will always start at a 4K boundary The reset values for MRBH and MRBL are OFh and FOh respectively Therefore after reset the MMR space is mapped to the uppermost 4K Bytes of Data Segment OFh bu
15. aim 5 wherein the CAN CAL module further includes a transmit engine that invokes the DMA engine to retrieve the winning message from the message buffer associated with the winning mes sage object and then attempts to transmit the winning message over the CAN bus according to a CAN bus arbi tration priority scheme established by the governing CAN protocol 20 The CAN device as set forth in claim 19 wherein if the winning message is not granted access to the CAN bus according to the CAN bus arbitration priority scheme the transmit pre arbitration engine is reset to repeat the pre arbitration priority determination process 21 The CAN device as set forth in claim 15 further comprising a global control register that is programmable for the purpose of permitting a user to select one of the at least two pre arbitration schemes 22 The CAN device as set forth in claim 2 wherein the CAN device comprises a CAN microcontroller 23 The CAN device as set forth in claim 22 further comprising a processor core that runs CAN applications 24 The CAN device as set forth in claim 23 further comprising a DMA engine that enables the CAN CAL 15 20 35 40 45 55 60 65 22 module to directly access the message buffers without interrupting the processor core 25 The CAN device as set forth in claim 1 wherein the CAN CAL module performs transmit pre arbitration of pending transmit messages and input acceptance filtering of
16. ansfer each accepted CAN Frame from the 13 byte pre buffer to the appropriate message buffer e g in the XRAM 28 one word at a time starting from the address pointed to by the contents of the MBXSR and MnBLR registers Every time the DMA engine 38 transfers a byte or a word it has to request the bus In this regard the MIF unit 30 arbitrates between accesses from the XA CPU Core 22 and from the DMA engine 38 In general bus arbitration is done on an alternate policy After a DMA bus access the XA CPU Core 22 will be granted bus access if requested After an XA CPU bus access the DMA engine 38 will be granted bus access if requested However a burst access by the XA CPU Core 22 cannot be interrupted by a DMA bus access Once bus access is granted by the MIF unit 30 the DMA engine 38 will write data from the 13 byte pre buffer to the appropriate message buffer location The DMA engine 38 will keep requesting the bus writing message data sequen tially to the appropriate message buffer location until the whole accepted CAN Frame is transferred After the DMA engine 38 has successfully transferred an accepted CAN Frame to the appropriate message buffer location the con tents of the message buffer will depend upon whether the message that the CAN Frame belongs to is a non fragmented single frame message or a fragmented message Each case is described below Non Fragmented Message Assembly For Message Objects that have bee
17. ansmit message data from the location in the message buffer cur rently pointed to by the address pointer logic and the DMA engine 38 will sequentially write the retrieved transmit message data to the CCB 42 It is noted that when preparing a message for transmission the user application must not include the CAN ID and Frame Information fields in the transmit message data written into the designated message buffer since the Transmit Tx logic will retrieve this information directly from the appropriate MnMIDH MNMIDL and MnMSKH registers The XA C3 microcontroller 20 does not handle the trans mission of fragmented messages in hardware It is the user s responsibility to write each CAN Frame of a fragmented message to the appropriate message buffer enable the asso ciated Transmit Message Object for transmission and wait for a completion before writing the next CAN Frame of that fragmented message to the appropriate message buffer The user application must therefore transmit multiple CAN Frames one at a time until the whole multi frame frag mented transmit message is successfully transmitted However by using multiple Transmit Message Objects whose object numbers increase sequentially and whose CAN IDs have been configured identically several CAN Frames of a fragmented transmit message can be queued up and enabled and then transmitted in order To avoid data corruption when transmitting messages there are three possible approaches
18. ansmit Pre Arbitration Screener ID A 30 bit field extracted from the incoming message which is then used in Acceptance Filtering The 05 6 510 479 1 5 Screener ID includes the CAN Arbitration ID and the IDE bit and can include up to 2 Data Bytes These 30 extracted bits are the information qualified by Acceptance Filtering Match ID A 30 bit field pre specified by the user to which the incoming Screener ID is compared Individual Match IDs for each of 32 Message Objects are programmed by the user into designated Memory Mapped Registers MMRs Mask A 29 bit field pre specified by the user which can override Mask a Match ID comparison at any particular bit or combination of bits in an Acceptance Filter Individual Masks one for each Message Object are programmed by the user in designated MMRs Individual Mask patterns assure that single Receive Objects can Screen for multiple acknowledged CAL CAN Frames and thus minimize the number of Receive Objects that must be dedicated to such lower priority Frames This ability to Mask individual Message Objects is an important new CAL feature CAL CAN Application layer A generic term for any high level protocol which extends the capabilities of CAN while employing the CAN physical layer and the CAN frame format and which adheres to the CAN specifica tion Among other things CALs permit transmission of Messages which exceed the 8 byte data limit inherent to CAN Frames This is ac
19. any enabled one of the 32 Message Objects that has been designated a Receive Mes sage Object If there is a match between the received CAN Frame and more than one Message Object then the received CAN Frame will be deemed to have matched the Message Object with the lowest object number n Acceptance Filtering is performed as follows by the XA C3 microcontroller 20 1 A Screener ID field is extracted from the incoming received CAN Frame In this regard the Screener ID field that is assembled from the incoming bit stream is different for Standard and Extended CAN Frames In particular as is illustrated in FIG 9 the Screener ID field for a Standard CAN Frame is 28 bits consisting of 11 CAN ID bits extracted from the header of the received CAN Frame 2x8 16 bits from the first and second data bytes Data Byte I and Data Byte 2 of the received CAN Frame the IDE bit Thus the user is required to set the and Msk bits in the Mask Field MnMSKL register for Standard CAN Frame Message Objects i e to don t care In addition in many applications based on Standard CAN Frames either Data Byte 1 Data Byte 2 or both do not participate in Acceptance Filtering In those applications the user must also mask out the unused Data 10 15 20 25 30 35 40 45 50 55 60 65 10 Byte s The IDE bit is not maskable As is illustrated in FIG 10 the Screener ID field for an Extended CAN Frame is 30 bits co
20. aspects and features of the present invention disclosed herein can be utilized either individually or any combination thereof and in any desired application e g in a stand alone CAN controller device or as part of any other microcontroller or system following terms used herein in the context of describ ing the preferred embodiment of the present invention 1 the XA C3 microcontroller are defined as follows Standard CAN Frame The format of a Standard CAN Frame is depicted in FIG 1 Extended CAN Frame The format of an Extended CAN Frame is also depicted in FIG 1 Acceptance Filtering The process a CAN device imple ments in order to determine if a CAN frame should be accepted or ignored and if accepted to store that frame in pre assigned Message Object Message Object A Receive RAM buffer of pre specified size up to 256 bytes for CAL messages and associated with a particular Acceptance Filter or a Transmit RAM buffer which the User preloads with all necessary data to transmit a complete CAN Data Frame Message Object can be considered to be a communication channel over which a complete message or a succession of messages can be transmitted CAN Arbitration ID An 11 bit Standard CAN 2 0 Frame or 29 bit Extended CAN 2 0B Frame identifier field placed in the CAN Frame Header This ID field is used to arbitrate Frame access to the CAN bus Also used in Acceptance Filtering for CAN Frame reception and Tr
21. complished by dividing each message into multiple packets with each packet being transmitted as a single CAN Frame consisting of a maxi mum of 8 data bytes Such messages are commonly referred to as segmented or fragmented messages The individual CAN Frames constituting a complete fragmented message are not typically transmitted in a contiguous fashion but rather the individual CAN Frames of different unrelated messages are interleaved on the CAN bus as is illustrated in FIG 2 Fragmented Message A lengthy message in excess of 8 bytes divided into data packets and transmitted using a sequence of individual CAN Frames The specific ways that sequences of CAN Frames construct these lengthy messages is defined within the context of a specific CAL The XA C3 microcontroller automatically re assembles these packets into the original lengthy message in hard ware and reports via an interrupt when the completed re assembled message is available as an associated Receive Message Object Message Buffer A block of locations in XA Data memory where incoming received messages are stored or where outgoing transmit messages are staged MMR Memory Mapped Register An on chip command control status register whose address is mapped into XA Data memory space and is accessed as Data memory by the XA processor With the XA C3 microcontroller a set of eight dedicated MMRs are associated with each Mes sage Object Additionally ther
22. ct associated with the winning message comprises a winning message object 2 The CAN device as set forth in claim 1 further comprising a plurality of message buffers associated with respective ones of the message objects for storage of trans mit or receive messages associated with the respective ones of the message objects 3 The CAN device as set forth in claim 2 wherein each of the message buffers has a size and a location that are programmable 4 The CAN device as set forth in claim 2 further comprising a plurality of individual message object registers associated with each of the message objects that contain fields of command control information that facilitate con figuration and setup of the associated message object the plurality of individual message object registers associated with each message object including at least one buffer size register that contains a message buffer size field that enables the size of the message buffer associated with the associated message object to be programmed and at least one buffer location register that contains a mes sage buffer location field that enables the location of the message buffer associated with the associated message object to be programmed 5 The CAN device as set forth in claim 2 further comprising a DMA engine that enables the CAN CAL module to directly access the message buffers 6 The CAN device as set forth in claim 5 wherein the DMA engine is contained within the
23. devices such as SRAM DRAM flash ROM and EPROM memory devices via an external address data bus 32 via an internal Core Data bus 34 and via an internal MMR bus 36 a DMA engine 38 that provides 32 CAL DMA Channels a plurality of on chip Memory Mapped Registers MMRs 40 that are mapped to the overall XA C3 data memory space a 4K Byte portion of the overall XA C3 data memory space is reserved for MMRs These MMRs include 32 Message Object or Address Pointers and 32 ID Screeners or Match IDs corre sponding to the 32 CAL Message Objects A complete listing of all MMRs is provided in the Table depicted in FIG 5 a 2 0 B CAN DLL Core 42 that is the CAN Controller Core from the Philips SJA1000 CAN 2 0A B Data Link Layer CDLL device hereinafter referred to as the CAN Core Block CCB and an array of standard microcontroller peripherals that are bi directionally coupled to the XA CPU Core 22 via a Special Function Register SFR bus 43 These stan dard microcontroller peripherals include Universal Asynchronous Receiver Transmitter UART 49 an SPI serial interface port 51 three standard timers counters with toggle output capability namely Timer 0 amp Timer 1 included in Timer block 53 and Timer 2 included in Timer block 54 a Watchdog Timer 55 and four 8 bit I O ports namely Ports 0 3 included in block 61 each of which has 4 programmable output configurations The DMA engine 38 the MMRs 40 and the CCB 42
24. diment the pre arbitration process is a selected one of at least two pre arbitration schemes including a first pre arbitration scheme whereby priority is determined according to a CAN bus arbitration priority scheme established by the governing CAN protocol and a second pre arbitration scheme whereby priority is determined by selecting the transmit message associated with the highest numbered or alternatively lowest numbered message object as the winning message In the event that more than one of the two or more concurrently staged transmit messages are determined to have the same priority the transmit message associated with the highest 05 6 510 479 1 3 numbered message object is designated as the winning message The method further includes attempting to transmit the winning message over the CAN bus If the winning message is not granted access to the CAN bus the pre arbitration priority determination process is repeated In another of its aspects the present invention encom passes CAN device e g a CAN microcontroller that implements the above described method of the present invention In a presently preferred embodiment the CAN microcontroller includes a plurality of message buffers asso ciated with respective ones of the message objects a pro cessor core for running CAN applications a CAN CAL module for processing transmit and receive messages at least one object specific control register associated with eac
25. ding a first pre 51 G06F 13 14 arbitration scheme whereby priority is determined according 52 US CL c 710 240 710 116 710 305 o CAN s d uel scheme by the 58 Field of Search 709 229 713 502 8vermins protocol ang a Second 370 300 700 1 23 710 240 116 305 scheme whereby priority is determined by selecting the transmit message associated with the highest numbered or 56 References Cited alternatively lowest numbered message object as the win U S PATENT DOCUMENTS ning message In the event that more than one of the two Or more concurrently staged transmit messages are determined 5 179 708 1 1993 Gyllstrom et al 395 725 to have the same priority the transmit message associated 5 323385 A 6 1994 Jurewicz et al 370 300 with the highest numbered message object is designated as 5 506 966 A 4 1996 Ban 395 250 he winnie messase The method turtberiuetudesatf rot 6 304 908 10 2001 Kalajan 2 700 229 AS Wmang message 2 6 357 014 3 2002 Correia 1 713 502 ing to transmit the winning message over the CAN bus If FOREIGN PATENT DOCUMENTS the winning message is not granted access to the CAN bus the pre arbitration priority determination process is EP 0378195 A2 1990 06 5 06 repeated WO 8806317 8 1988 G06F 9 46 cited by examiner 35 Claims 7 Drawing Sheets ECC Mem c tA T ad
26. dware assembly of fragmented OSEK and CANopen messages These and other particulars can be found in the XA C3 CAN Transport Layer Controller User Manual that is part of the parent Provisional Application Serial No 60 154 022 the disclosure of which has been fully incorporated herein for all purposes Transmit Message Objects and the Transmit Process In order to transmit a message the XA application pro gram must first assemble the complete message and store it in the designated message buffer for the appropriate Trans mit Message Object n The message header CAN ID and Frame Information must be written into the MnMIDH MnMIDL and MnMSKH registers associated with that Transmit Message Object n After these steps are completed the XA application is ready to transmit the message To initiate a transmission the object enable bit OBJ EN bit of the MnCTL register associated with that Transmit Message Object n must be set except when transmitting an Auto Acknowledge Frame in CANopen This will allow this ready to transmit message to participate in the pre arbitration process In this connection if more than one message is ready to be transmitted 1 if more than one Transmit Message Object is enabled a Tx Pre Arbitration process will be performed to determine which enabled Transmit Message Object will be selected for transmission There are two Tx Pre Arbitration policies which the user can choose between by setting or clearing th
27. e Object A Rx Message Object can be associated either with a unique CAN ID or with a set of CAN IDs which share certain ID bit fields As previously mentioned each Message Object has its own reserved block of data 10 15 20 25 30 35 40 45 50 55 60 65 8 memory space up to 256 Bytes which is referred to as that Message Object s message buffer As will be seen both the size and the base address of each Message Object s message buffer is programmable As previously mentioned each Message Object is asso ciated with a set of eight MMRs 40 dedicated to that Message Object Some of these registers function differently for Tx Message Objects than they do for Rx Message Objects These eight MMRs 40 are designated Message Object Registers see FIG 4 names of these eight MMRs 40 are 1 MnMIDH Message n Match ID High 2 MnMIDL Message n Match ID Low 3 MnMSKH Message n Mask High 4 MnMSKL Message n Mask Low 5 MnCTL Message n Control 6 MnBLR Message n Buffer Location Register MnBSZ Message n Buffer Size 8 MnFCR Message n Fragment Count Register where n ranges from 0 to 31 i e corresponding to 32 independent Message Objects In general the user defines or sets up a Message Object by configuring programming some or all of the eight MMRs dedicated to that Message Object as will be described below Additionally as will be described below the user must configure program
28. e Object n In this manner the MnBLR register 05 6 510 479 1 17 for each message buffer serves as an address pointer These address pointer fields are also readable at any time by the processor under software control The above described approach to message storage also provides an extremely quick and efficient means of freeing up a message buffer when a message completes or when a message buffer is fill The software can respond to a message complete interrupt or a buffer full interrupt by simply repositioning the message buffer space for that par ticular Message Object to somewhere else in the message buffer memory space This is accomplished by performing a single write operation to modify the buffer base address specified in the appropriate MnBLR register i e address pointer This is essentially the extent of a very short interrupt handling routine These interrupts must be handled quickly because the message buffer must be freed up for subsequent message reception Interrupt response is particu larly critical if many completed messages are stacked up and need to be dealt with at once Once this buffer repositioning is accomplished the hardware is immediately ready to receive a new message over that Message Object channel or the continuation of the current message in the case of a buffer full interrupt The memory space that was previously designated as the message buffer for that Message Object n still contains the
29. e Pre__Arb bit in the GCTL register After a Tx Message Complete interrupt is generated in response to a determination being made by the message 05 6 510 479 1 13 handler that a completed message has been successfully transmitted the Tx Pre Arbitration process is reset and begins again Also if the winning Transmit Message Object subsequently loses arbitration on the CAN bus the Tx Pre Arbitration process gets reset and begins again If there is only one Transmit Message Object whose EN bit is set it will be selected regardless of the Tx Pre Arbitration policy selected Once an enabled Transmit Message Object has been selected for transmission the DMA engine 38 will begin retrieving the transmit message data from the message buffer associated with that Transmit Message Object and will begin transferring the retrieved transmit message data to the CCB 42 for transmission The same DMA engine and address pointer logic is used for message retrieval of trans mit messages as is used for message storage of receive messages as described previously Further message buffer location and size information is specified in the same way as described previously In short when a transmit message is retrieved it will be written by the DMA engine 38 to the CCB 42 sequentially During this process the DMA engine 38 will keep requesting the bus when bus access is granted the DMA engine 38 will sequentially read the tr
30. e are several MMRs whose bits control global parameters that apply to all Message Objects With reference now to FIG 3 there can be seen a high level block diagram of the XA C3 microcontroller 20 The XA C3 microcontroller 20 includes the following func tional blocks that are fabricated on a single integrated circuit IC chip packaged in a 44 pin PLCC or a 44 pin package an XA CPU Core 22 that is currently implemented as a 16 bit fully static CPU with 24 bit program and data address range that is upwardly compatible with the 80C51 architecture and that has an operating fre quency of up to 30 MHz 10 15 20 25 30 35 40 45 50 55 60 65 6 a program or code memory 24 that is currently imple mented as a 32K ROM EPROM and that is bi directionally coupled to the XA CPU Core 22 via an internal Program bus 25 A map of the code memory space is depicted in FIG 4 a Data RAM 26 internal or scratch pad data memory that is currently implemented as a 1024 Byte portion of the overall XA C3 data memory space and that is bi directionally coupled to the XA CPU Core 22 via an internal DATA bus 27 an on chip message buffer RAM or XRAM 28 that is currently implemented as a 512 Byte portion of the overall XA C3 data memory space which may contain part or all of the CAN CAL Transmit amp Receive Object message buffers a Memory Interface MIF unit 30 that provides interfaces to generic memory
31. ect CAN CAL Related Interrupts The CAN CAL module 77 of the XA C3 microcontroller 20 is presently configured to generate the following five different Event interrupts to the XA CPU Core 22 1 Rx Message Complete 2 Tx Message Complete 3 Rx Buffer Full 4 Message Error 5 Frame Error For single frame messages the Message Complete con dition occurs at the end of the single frame For multi frame fragmented messages the Message Complete condition occurs after the last frame is received and stored Since the XA C3 microcontroller 20 hardware does not recognize or handle fragmentation for transmit messages the Tx Message Complete condition will always be generated at the end of each successfully transmitted frame As previously mentioned there is a control bit associated with each Message Object indicating whether a Message Complete condition should generate an interrupt or just set a Message Complete Status Flag for polling without generating an interrupt This is the INT EN bit in the MnCTL register associated with each Message Object n There are two 16 bit MMRs 40 MCPLH and MCPLL which contain the Message Complete Status Flags for all 32 Message Objects When a Message Complete Tx or Rx condition is detected for a particular Message Object the corresponding bit in the MCPLH or MCPLL register will be set This will occur regardless of whether the INT EN bit is set for that particular Message Object in its assoc
32. eld that enables the location of the message buffer associated with the associated message object to be programmed Preferably the CAN CAL module further includes transmit engine that invokes the DMA engine to retrieve the winning message from the message buffer associated with the winning message object and then attempts to transmit the winning message over the CAN bus according to the CAN bus arbitration priority scheme established by the governing CAN protocol If the winning message is not granted access to the CAN bus according to the CAN bus arbitration priority scheme the transmit pre arbitration engine is reset to repeat the pre arbitration priority determi nation process The global control register is programmable for the purpose of permitting a user to select one of the at least two pre arbitration schemes BRIEF DESCRIPTION OF THE DRAWINGS These and various other aspects features and advantages of the present invention will be readily understood with reference to the following detailed description of the inven tion read in conjunction with the accompanying drawings in which FIG 1 is a diagram illustrating the format of a Standard CAN Frame and the format of an Extended CAN Frame FIG 2 is a diagram illustrating the interleaving of CAN Data Frames of different unrelated messages 10 15 20 25 30 35 40 45 50 55 60 65 4 FIG 3 is a high level functional block diagram of the XA C
33. er for that Message Object set to 17 masking of the 11 29 bit CAN ID field is disallowed As such the CAN ID of the accepted CAN Frame is known unambiguously and is contained in the MnMIDH and MnMIDL registers associated with the Message Object that has been deemed to constitute a match Therefore there is no need to write the CAN ID of the accepted CAN Frame into the MnMIDH and MnMIDL registers associated with the Message Object that has been deemed to constitute a match As subsequent CAN Frames of a fragmented message are received the new data bytes are appended to the end of the previously received and stored data bytes This process continues until a complete multi frame message has been received and stored in the appropriate message buffer Under CAL protocols DeviceNet CANopen and OSEK if a Message Object is an enabled Receive Message Object and its associated MnCTL register has its FRAG bit set to 1 i e automatic fragmented message assembly is enabled for that particular Receive Message Object then the first data byte Data Byte 1 of each received CAN Frame that matches that particular Receive Message Object will be used to encode fragmentation information only and thus will not be stored in the message buffer for that particular Receive Message Object Thus message storage for such enabled Receive Message Objects will start with the second data byte Data Byte 2 and proceed in the previously descr
34. ge over the CAN message associated with the highest numbered mes pung 5 bus and sage object as the winning message MK 34 The method as set forth in claim 26 wherein if the winning message is not granted access to the CAN the message objects are uniquely numbered and bus repeating the pre arbitration priority determination in the event that more than one of the two or more process concurrently staged transmit messages are determined 10 to have the same priority designating the transmit
35. ges concur rently staged for attempted transmission over the CAN bus by selecting the transmit message associated with the lowest numbered message object as the winning message 14 The CAN device as set forth in claim 1 wherein the message objects are uniquely numbered and the transmit pre arbitration engine determines priority between the two or more transmit messages concur rently staged for attempted transmission over the CAN bus by selecting the transmit message associated with the highest numbered message object as the winning message 15 The CAN device as set forth in claim 1 wherein the transmit pre arbitration engine determines priority between the two or more transmit messages concurrently staged for attempted transmission over the CAN bus according to a selected one of at least two pre arbitration schemes 16 The CAN device as set forth in claim 15 wherein the two or more pre arbitration schemes include 05 6 510 479 1 21 first pre arbitration scheme whereby the transmit pre arbitration engine determines priority between the two or more transmit messages concurrently staged for attempted transmission over the CAN bus according to CAN bus arbitration priority scheme established by the governing CAN protocol and second pre arbitration scheme whereby the transmit pre arbitration engine determines priority between the two or more transmit messages concurrently staged for attempted transmission over the
36. h message object at least one global control register and a DMA engine that enables the CAN CAL module to directly access the message buffers without interrupting the processor core at least one object specific control register associated with each message object is programmable for the purpose of enabling or disabling the associated message object as a transmit or receive message object thereby providing a user with the capability to concurrently stage two or more transmit messages for attempted transmission over a CAN bus coupled to the CAN microcontroller according to a governing CAN protocol The CAN CAL module includes a transmit pre arbitration engine that determines which of the two or more transmit messages concurrently staged for attempted transmission over the CAN bus has priority Preferably each of the message buffers has a size and a location that are program mable In this regard the CAN microcontroller preferably further includes a plurality of individual message object registers associated with each of the message objects that contain fields of command control information that facilitate configuration and setup of the associated message object including at least one buffer size register that contains a message buffer size field that enables the size of the message buffer associated with the associated message object to be programmed and at least one buffer location register that contains a message buffer location fi
37. h particular Message Object n by programming the MnBSZ register associated with that Mes sage Object n The top location of the message buffer for each Message Object n is determined by the size of that message buffer as specified in the corresponding MnBSZ register The user can configure program the MnCTL register associated with each particular Message Object n in order to enable or disable that Message Object n in order to define or designate that Message Object n as a Tx or Rx Message Object in order to enable or disable automatic hardware assembly of fragmented Rx messages 1 automatic frag mented message handling for that Message Object n in order to enable or disable automatic generation of a 05 6 510 479 1 9 Message Complete Interrupt for that Message Object n and in order to enable or not enable that Message Object n for Remote Transmit Request RTR handling In CANopen and OSEK systems the user must also initialize the MnFCR register associated with each Message Object n As previously mentioned on set up the user must con figure program the global GCTL register whose bits control global parameters that apply to all Message Objects In particular the user can configure program the GCTL register in order to specify the high level CAL protocol if any being used e g DeviceNet CANopen or OSEK in order to enable or disable automatic acknowledgment of CANopen Frames CANopen auto acknowledge and
38. iated MnCTL register or whether Message Complete Status Flags have already been set for any other Message Objects In addition to these 32 Message Complete Status Flags there is a Tx Message Complete Interrupt Flag and an Rx Message Complete Interrupt Flag corresponding to bits 1 and 0 respectively of an MMR 40 designated CANINTFLG which will generate the actual Event inter rupt requests to the XA CPU Core 22 When an End of Message condition occurs at the same moment that the Message Complete Status Flag is set the appropriate Tx or Rx Message Complete Interrupt flip flop will be set pro vided that INT EN 1 for the associated Message Object and provided that the interrupt is not already set and pend ing Further details regarding the generation of interrupts and the associated registers can be found in the XA C3 Func tional Specification and in the XA C3 CAN Transport Layer Controller User Manual both of which are part of the parent Provisional Application Serial No 60 154 022 the disclo sure of which has been fully incorporated herein for all purposes Message Buffers As was previously described in detail hereinabove the XA C3 microcontroller 20 supports up to 32 separate and independent Message Objects each of which is set up or 05 6 510 479 1 15 defined by virtue of the user programmer configuring programming some or all of the eight MMRs 40 dedicated to that Message Object In the XA C3 microcontro
39. ibed manner until a complete multi frame message has been received and stored in the appropriate message buffer This message storage format is illustrated in FIG 11 The message handler hardware will use the fragmentation infor mation contained in Data Byte 1 of each CAN Frame to facilitate this process Under the CAN protocol if a Message Object is an enabled Receive Message Object and its associated MnCTL register has its FRAG bit set to 1 1 automatic frag mented message assembly is enabled for that particular Receive Message Object then the CAN Frames that match that particular Receive Message Object will be stored sequentially in the message buffer for that particular Receive Message Object using the format shown in FIG 12 When writing message data into a message buffer asso ciated with a Message Object n the DMA engine 38 will generate addresses automatically starting from the base 10 15 20 25 45 50 55 60 65 12 address of that message buffer as specified in the MnBLR register associated with that Message Object n Since the size of that message buffer is specified in the MNBSZ register associated with that Message Object n the DMA engine 38 can determine when it has reached the top location of that message buffer If the DMA engine 38 determines that it has reached the top location of that message buffer and that the message being written into that message buffer has not been completel
40. in order to specify which of two transmit Tx pre arbitration schemes policies is to be utilized ie either Tx pre arbitration based on CAN ID with the object number being used as a secondary tie breaker or Tx pre arbitration based on object number only Receive Message Objects and the Receive Process During reception 1 when an incoming CAN Frame is being received by the XA C3 microcontroller 20 the CAN CAL module 77 will store the incoming CAN Frame in a temporary 13 Byte buffer and determine whether a complete error free CAN frame has been successfully received If it is determined that a complete error free CAN Frame has been successfully received then the CAN CAL module 77 will initiate Acceptance Filtering in order to determine whether to accept and store that CAN Frame or to ignore discard that CAN Frame Acceptance Filtering In general because the XA C3 microcontroller 20 pro vides the user with the ability to program separate Match ID and Mask fields for each of the 32 independent Message Objects on an object by object basis as described previously the Acceptance Filtering process performed by the XA C3 microcontroller 20 can be characterized as a match and mask technique The basic objective of this Acceptance Filtering process is to determine whether a Screener ID field of the received CAN Frame excluding the don t care bits masked by the Mask field for each Message Object matches the Match ID of
41. lexibility to the user as the user is free to use as much or as little message storage area as an application requires and is also free to position the message buffers wherever it is most convenient This message storage scheme is a key element of the unique message management capabilities of the XA C3 CAN microcontroller as this scheme enables the XA C3 CAN CAL module to concurrently assemble many up to 32 incoming fragmented messages of varying lengths and at the same time stage multiple outgoing messages for transmission Since incoming message assembly is handled entirely in hardware the processor is free to perform other tasks typically until a complete message is received and ready for processing SUMMARY OF THE INVENTION The present invention encompasses in one of its aspects a method implemented in a CAN device e g a microcontroller that supports a plurality of message objects that includes concurrently staging two or more transmit messages associated with respective ones of two or more enabled transmit message objects for attempted transmission over a CAN bus coupled to the CAN device and performing a pre arbitration process to determine which of the two or more concurrently staged transmit messages has priority The message determined to have priority is deemed a winning message and the message object associated with the winning message is deemed a winning message object In a presently preferred embo
42. ller 20 each of the 32 Message Objects is assigned its own block of address space in data memory which serves as its message buffer for data storage The size and location of each message buffer is programmable and thus reconfigurable on the fly by the user programmer The message buffers can be positioned in any desired location within the overall data memory space addressable by the XA C3 microcon troller 20 which is presently configured to be a 16 Mbyte overall memory space These message buffers can be located in the XRAM 28 and or in any off chip portion of the overall data memory space The location of the message buffer associated with each Message Object n is established by programming the MMR 40 designated MnBLR associated with that Message Object 1 by programming the Message n Buffer Location Reg ister The size of the message buffer associated with each Message Object is established by programming the MMR 40 designated MnBSZ associated with that Message Object i e by programming the Message n Buffer SiZe Register In the XA C3 microcontroller 20 allowable buffer sizes are 2 4 8 16 32 64 128 or 256 bytes Users can select the size of each message buffer based on the anticipated length of the incoming message or they can conserve memory by delib erately specifying smaller buffers at the expense of increased processor intervention to handle more frequent buffer full conditions In the XA C3 microcontroller 20 Di
43. n set up with automatic fragmented message handling disabled not enabled i e the FRAG bit in the MnCTL register for that Message Object is set to 0 the complete CAN ID of the accepted CAN Frame which is either 11 or 29 bits depending on 05 6 510 479 1 11 whether the accepted CAN Frame is a Standard or Extended CAN Frame is written into the MnMIDH and MnMIDL registers associated with the Message Object that has been deemed to constitute a match once the DMA engine 38 has successfully transferred the accepted CAN Frame to the message buffer associated with that Message Object This will permit the user application to see the exact CAN ID which resulted in the match even if a portion of the CAN ID was masked for Acceptance Filtering As a result of this mechanism the contents of the MnMIDH and MnMIDL registers can change every time an incoming CAN Frame is accepted Since the incoming CAN Frame must pass through the Acceptance Filter before it can be accepted only the bits that are masked out will change Therefore the criteria for match and mask Acceptance Filtering will not change as a result of the contents of the MnMIDH and MnMIDL registers being changed in response to an accepted incoming CAN Frame being transferred to the appropriate message buffer Fragmented Message Assembly For Message Objects that have been set up with automatic fagmented message handling enabled 1 with the FRAG bit in the MnCTL regist
44. nsisting of 29 CAN ID bits extracted from the header of the incoming CAN Frame the IDE bit Again the IDE bit is not maskable 2 The assembled Screener ID field of the received CAN Frame is then sequentially compared to the corresponding Match ID values specified in the MnMIDH and MnMIDL registers for all currently enabled Receive Message Objects Of course any bits in the Screener ID field that are masked by a particular Message Object are not included in the comparison That is if there is a 1 in a bit position of the Mask field specified in the MnMSKH and MnMSKL registers for a particular Message Object then the corresponding bit position in the Match ID field for that particular Message Object becomes a don t i e always yields a match with the corresponding bit of the Screener ID of the received CAN Frame 3 If the above comparison process yields a match with more than one Message Object then the received CAN Frame will be deemed to have matched the Message Object having the lowest object number n Message Storage Each incoming received CAN Frame that passes Accep tance Filtering will be automatically stored via the DMA engine 38 into the message buffer for the Receive Message Object that particular CAN Frame was found to have matched In an exemplary implementation the message buffers for all Message Objects are contained in the XRAM 28 Message Assembly In general the DMA engine 38 will tr
45. odule 77 provides the user programmer with the unique ability to enable multiple up to 32 ones of the Message Objects as Transmit Message Objects thereby enabling multiple up to 32 messages to be staged for transmit at once In accordance with the present invention the XA CAN CAL module 77 includes logic transmit pre arbitration engine for automatically determining which of multiple pending Transmit Message Objects has the highest priority prior to an attempt to transmit any of the messages over the CAN bus The scheme employed for making this determination is termed a transmit pre arbitration scheme As was described previously the XA C3 microcontroller 20 provides the user programmer 10 15 20 25 30 35 45 50 55 60 65 18 with the ability to select between two different transmit pre arbitration schemes or policies by setting or clearing the Arb bit in the GCTL register It will be appreciated that once priority is determined the DMA engine 38 will then retrieve the message stored in the message buffer associated with the Transmit Message Object that has been determined to have the highest priority accord ing to the selected transmit pre arbitration scheme 1 the winning Transmit Message Object and will then transfer the retrieved transmit message data to the CCB 42 for transmission over the CAN bus Obviously each transmit message frame selected for transmission over the C
46. ontrollers that incorporate the same CAN Control Area Network is an industry standard two wire serial communications bus that is widely used in automotive and industrial control applications as well as in medical devices avionics office automation equipment consumer appliances and many other products and appli cations CAN controllers are currently available either as stand alone devices adapted to interface with a microcon troller or as circuitry integrated into or modules embedded in a microcontroller chip Since 1986 CAN users software programmers have developed numerous high level CAN Application Layers CALs which extend the capabilities of the CAN while employing the CAN physical layer and the CAN frame format and adhering to the CAN specification CALs have heretofore been implemented primarily in software with very little hardware CAL support Consequently CALs have heretofore required a great deal of host CPU intervention thereby increasing the processing overhead and diminishing the performance of the host CPU Thus there is a need in the art for a CAN hardware implementation of CAL functions normally implemented in software in order to offload these tasks from the host CPU to the CAN hardware thereby enabling a great savings in host CPU processing resources and a commensurate improvement in host CPU performance One of the most demanding and CPU resource intensive CAL functions is message management which entails
47. orth in claim 1 wherein the message objects are uniquely numbered and in the event that more than one of the two or more transmit messages concurrently staged for attempted transmis sion over the CAN bus are determined to have the same priority the transmit pre arbitration engine designates the transmit message associated with the highest numbered message object as the winning message 11 The CAN device as set forth in claim 8 wherein the message objects are uniquely numbered and in the event that more than one of the two or more transmit messages concurrently staged for attempted transmis sion over the CAN bus are determined to have the same assigned priority the transmit pre arbitration engine designates the transmit message associated with the lowest numbered message object as the winning mes sage 12 The CAN device as set forth in claim 8 wherein the message objects are uniquely numbered and in the event that more than one of the two or more transmit messages concurrently staged for attempted transmis sion over the CAN bus are determined to have the same assigned priority the transmit pre arbitration engine designates the transmit message associated with the highest numbered message object as the winning mes sage 13 The CAN device as set forth in claim 1 wherein the message objects are uniquely numbered and the transmit pre arbitration engine determines priority between the two or more transmit messa
48. previously received message data but this space now becomes just part of the long term data memory space The message information stored in this long term data memory space can then be processed by the software at its leisure This same buffer repositioning technique can be employed for Transmit Messages to facilitate fragmentation Unlike the receive case the XA C3 CAN CAL Module 77 does not automatically assemble fragmented outgoing mes sages It is incumbent upon the software to load a new message frame each time the previous frame is transmitted Using the XA C3 microcontroller 20 message storage scheme however the software can construct an entire fragmented message prior to enabling transmission As each frame is transmitted the processor XA CPU Core 22 only needs to reposition the buffer again using a single write operation to point to the location of the next frame This is much faster than competing devices which require the processor to move up to 13 bytes of data from memory to a dedicated transmit buffer It will be appreciated that with the above described mes sage buffer scheme of the present invention each message buffer can be regarded as a separate FIFO having an inde pendently programmable buffer length which provides a revolutionary approach to storing sequential messages of varying lengths without any CPU intervention Present Invention As was described in detail hereinabove the XA CAN CAL m
49. reby priority is deter mined according to a CAN bus arbitration priority scheme established by the governing CAN protocol and second pre arbitration scheme whereby priority is deter mined by selecting the transmit message associated with a lowest numbered message object as the winning message wherein the message objects are uniquely numbered 30 The method as set forth in claim 26 wherein priority is determined according to a CAN bus arbitration priority scheme established by the governing CAN protocol 31 The method as set forth in claim 26 wherein priority is determined by selecting the transmit message associated with a lowest numbered message object as the winning message wherein the message objects are uniquely num bered 32 The method as set forth in claim 26 wherein priority is determined by selecting the transmit message associated with a highest numbered message object as the winning message wherein the message objects are uniquely num bered 05 6 510 479 1 23 24 33 method as set forth in claim 26 wherein message associated with the lowest numbered message the message objects are uniquely numbered and object as the winning message in the event that more than one of the two or more 35 The method as set forth in claim 26 further compris concurrently staged transmit messages are determined ing to have the same priority designating the transmit 5 attempting to transmit the winning messa
50. rect Memory Access DMA i e the DMA engine 38 is used to enable the XA C3 CAN CAL module 77 to directly access the 32 message buffers without interrupting the XA C3 processor CPU core 22 The XA C3 CAN CAL module 77 uses the values pro grammed into the buffer size registers MnBSZ to reserve the designated number of bytes of storage for each Message Object n For Receive Message Objects this field is also used by logic in the XA C3 CAN CAL module 77 to calculate the total number of bytes that have actually been stored in the message buffers and to identify when a buffer full condition is reached Each time a byte of data is stored in a message buffer associated with a Message Object n the XA C3 CAN CAL module 77 concurrently accesses the MnBSZ and MNBLR registers associated with that Message Object Logic incorporated within the XA C3 CAN CAL module 77 decodes the buffer size for that Message Object and compares the decoded buffer size to the address pointer to determine current byte count and avail able space left in that Message Object s message buffer The present implementation of the XA C3 microcontrol ler 20 requires that all of the 32 message buffers reside within the same 64 Kbyte memory segment or page The user may position the message buffers within any of the 256 pages in the overall XA C3 data memory space 1 256x64 Kbytes 16 Mbytes Programming the locations of the mes sage buffers is accomplished in two
51. s stored in the global Message Buffer Segment Register i e the MBXSR register and the 16 LSBs stored in the MnBLR register for that message buffer to form a complete 24 bit message buffer address The DMA engine 38 then passes this address to the Memory Interface MIF unit 30 along with a flag indicating that the DMA engine 38 requires access to the memory As soon as the current set of XA C3 processor memory accesses are completed the MIF unit 30 will initiate a memory read or write to the address provided by the DMA engine 38 and then permit the DMA engine 38 to perform the required data transfer to from the desired mes sage buffer DMA accesses are typically done two bytes at a time 1 as a 16 bit operation However 8 bit operations are employed when there is only a single byte to be transferred As soon as the requested DMA operation is completed the DMA engine 38 increments the 16 bit address value stored in the MNBLR register associated with that message buffer by one or two depending upon whether a one byte or two byte access was performed and writes this value back into the MnBLR register for that message buffer Thus the MnBLR registers along with the associated increment logic within the DMA engine 38 effectively function as a set of 32 binary counters Thus at any given time each MnBLR register contains the address which will be used for the next data access to the message buffer associated with the Messag
52. steps The first step is to program the page number in which all of the message buffers reside into the MMR 40 designated as the MBXSR register which is one of the CCB Registers depicted in FIG 4 As was previously described the con tents of this register are subsequently used as the eight MSBs of address for all DMA accesses to any of the message buffers This register also establishes the memory page in which the XRAM 28 resides The second step is to program the base address 16 bits for each individual message buffer into the MnBLR asso 5 10 15 20 25 30 35 40 45 50 55 60 65 16 ciated with that message buffer These 16 bit address values initially specified by the user programmer constitute the base addresses of the 32 respective message buffers within the 64 Kbyte memory page specified in the MBXSR register for all message buffers It should be noted that the message buffers can be placed apart from one another as there is no requirement that the message buffer space be continuous i e that the message buffers reside in physically contiguous locations within the data memory space Further it should also be noted that some or all of the message buffers can be placed in off chip memory and others in the on chip XRAM 28 In the XA C3 microcontroller 20 it is required that each message buffer start at a binary boundary for its size 1 the 8 LSBs must be zero for a 256 byte message buffer
53. t access to the MMRs 40 is disabled The first 512 Bytes offset 000h 1FFh of MMR space are the Message Object Registers eight per Message Object for objects n20 31 as is shown in FIG 6 The base address of the XRAM 28 is determined by the contents of the MMRs designated MBXSR and XRAMB as is shown in FIGS 7 and 8 As previously mentioned the 512 Byte XRAM 28 is where some or all of the 32 Rx Tx message buffers corresponding to Message Objects 0 31 reside The message buffers can be extended off chip to a maximum of 8 KBytes This off chip expansion capability can accommodate up to thirty two 256 Byte message buffers Since the uppermost 8 bits of all message buffer addresses are formed by the contents of the MBXSR register the XRAM 28 and all 32 message buffers must reside in the same 64K Byte data memory segment Since the XA C3 microcontroller 20 only provides address lines 0 19 for accessing external memory all external memory addresses must be within the lowest 1 MByte of address space Therefore if there is external memory in the system into which any of the 32 message buffers will be mapped then all 32 message buffers and the XRAM 28 must also be mapped entirely into that same 64K Byte segment which must be below the 1 MByte address limit After the memory space has been mapped the user can set up or define up to 32 separate Message Objects each of which can be either a Transmit Tx or a Receive Rx Messag
54. t is used to determine access to the actual CAN bus More particularly in accordance with this first optional scheme priority is determined by examining the bit pattern in the CAN arbitration field contained in the header portion of each of the multiple transmit messages that are pending staged for transmission and then selecting the transmit message having the highest assigned priority as defined by the governing CAN protocol It will be appreciated that the CAN arbitration ID is an 11 or 29 bit field contained in the header portion of each transmit message In the event that two or more pending transmit messages share the identical CAN arbitration ID the Message Object number 1 to 32 is used as a secondary tie breaker e g the co winner transmit message associated with the enabled Transmit Message Object having the lowest or highest object num ber will be deemed the winner By using this first optional scheme the user can ensure that the XA CAN CAL module 77 wil attempt to transmit the message which has the highest likelihood of ultimately winning access onto the CAN bus self The second optional scheme performs trans mit pre arbitration based upon the Message Object number alone This option provides the user or software with a mechanism for overriding the inherent priority encoded into the messages themselves which effectively dictates the order in which transmit messages will attempt to gain access to the CAN bus
55. the 7 LSBs must be zero for a 128 byte message buffer etc DMA access to each of the message buffers is achieved by using the 8 bits stored in the MBXSR register as the 8 MSBs of the address of that message buffer and the 16 bits stored in the MnBLR register for that message buffer as the 16 LSBs of the address of that message buffer The base address initially programmed by the user into the MnBLR register for that message buffer is the address of the first bottom location of that message buffer When the first frame of a new receive message arrives the CAN CAL module 77 hardware writes a semaphore code into this bottom location before beginning to store actual data bytes starting at the next location in that message buffer At the end of the new receive message or when a buffer full condition is detected the CAN CAL module 77 hardware computes the total number of bytes actually stored in that message buffer and writes this value into the bottom location of that message buffer The processor i e the XA CPU Core 22 can then read this value and determine precisely how many additional bytes must be read and processed Each time a new byte of data must be written to for receive messages or retrieve from for transmit messages a message buffer the DMA engine 38 reads the MnBLR register for that message buffer in order to retrieve the current address pointer for the associated Message Object The DMA engine 38 concatenates the 8 MSB
56. the global GCTL register whose bits control global parameters that apply to all Message Objects In particular the user can specify the Match ID value for each Message Object to be compared against the Screener IDs extracted from incoming CAN Frames for Acceptance Filtering The Match ID value for each Message Object n is specified in the MnMIDH and MnMIDL registers associated with that Message Object n The user can mask any Screener ID bits which are not intended to be used in Acceptance Filtering on an object by object basis by writing a logic 17 in the desired to be masked bit position s in the appro priate MnMSKH and or MNMSKL registers associated with each particular Message Object n The user is responsible on set up for assigning a unique message buffer location for each Message Object n In particular the user can specify the least significant 16 bits of the base address of the message buffer for each particular Message Object n by programming the MnBLR register associated with that Message Object n upper 8 bits of the 24 bit address for all Message Objects are specified by the contents of the MBXSR register as previously discussed so that the message buffers for all Message Objects reside within the same 64 KByte memory segment The user is also responsible on set up for specifying the size of the message buffer for each Message Object n In particular the user can specify the size of the message buffer for eac
57. the handling storage and processing of incoming CAL CAN messages received over the CAN serial communications bus and or outgoing CAL CAN messages transmitted over the CAN serial com munications bus CAL protocols such as DeviceNet CANopen and OSEK deliver long messages distributed over many CAN frames which methodology is sometimes referred to as fragmented or segmented messaging The process of assembling such fragmented multi frame mes sages has heretofore required a great deal of host CPU intervention In particular CAL software running on the host CPU actively monitors and manages the buffering and processing of the message data in order to facilitate the assembly of the message fragments or segments into com plete messages Based on the above and foregoing it can be appreciated that there presently exists a need in the art for a hardware implementation of CAL functions normally implemented in software in order to offload these tasks from the host CPU thereby enabling a great savings in host CPU processing resources and a commensurate improvement in host CPU performance assignee of the present invention has recently devel oped a new microcontroller product designated XA C3 that fulfills this need in the art The XA C3 is the newest member of the Philips XA eXtended Architecture family of high performance 16 bit single chip microcontrollers It 10 15 20 25 35 40 45 50 55
58. y transferred yet the DMA engine 38 will wrap around by generating addresses starting from the base address of that message buffer again Some time before this happens a warning interrupt will be generated so that the user application can take the necessary action to prevent data loss message handler will keep track of the current address location of the message buffer being written to by the DMA engine 38 and the number of bytes of each CAL message as it is being assembled in the designated message buffer After an End of Message for a CAL message is decoded the message handler will finish moving the com plete CAL message and the Byte Count into the designated message buffer via the DMA engine 38 and then generate an interrupt to the XA CPU Core 22 indicating that a complete message has been received Since Data Byte 1 of each CAN Frame contains the fragmentation information it will never be stored in the designated message buffer for that CAN Frame Thus up to seven data bytes of each CAN Frame will be stored After the entire message has been stored the designated message buffer will contain all of the actual informational data bytes received exclusive of fragmentation information bytes plus the Byte Count at location 00 which will contain the total number of informational data bytes stored It is noted that there are several specific user set up programming procedures that must be followed when invok ing automatic har

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