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Errata Sheet

1. C Infineon Errata Sheet V 1 0 2004 09 Device C508 4E Marking Step Step ES AB Step AB Package P MQFP 64 This Errata Sheet describes the deviations from the current user documentation The module oriented classification and numbering system uses an ascending sequence over several derivatives including already solved deviations So gaps inside this enumeration can occur Current Documentation e C508 User s Manual May 2001 e C508 Data Sheet May 2001 e Instruction Set Manual 07 2000 Note Devices marked with EES or ES are engineering samples which may not be completely tested in all functional and electrical characteristics therefore they should be used for evaluation only The specific test conditions for EES and ES are documented in a separate Status Sheet Contents SEGUON heir wea eae ke ae E oe eee ee ie eee ere deere Page History List Change Summary 2 0 000 eee eee eee 2 Functional Deviations 00 000 eee 4 Deviations from Electrical and Timing Specification 8 Application Hints 26 65 cscs cee dew eee sesew ees Gates ees Seabees ee be ee ewe 8 Errata Sheet C508 4E Step ES AB AB 1 8 K Yang V 1 0 2004 09 Infineon Errata Sheet History List Change Summary 1 History List Change Summary since last CPU Step ES AA AA Table 1 Functional Deviations Functional Short Descrip
2. ADC 1 The upper limit for fapc is increased from 2 MHz to 5 MHz The ADC conversion clock fapc is to be adjusted such that the resulting fapc is less than or equal to 5 MHz instead of 2 MHz as currently specified Workaround None This new upper limit will be included in future documentation updates ADC 2 A D Converter Clock Prescaler Ratio is not as defined in documentation The prescaler ratio for the A D Conversion clock is not as defined on the User s Manual page 6 126 The effective prescaler ratio is shown as follows ADCL1 ADCLO Prescaler Ratio 0 0 Divide by 4 0 1 Divide by 4 1 0 Divide by 8 1 1 Divide by 8 Workaround None INT 1 Contents of SFR EINT cannot be read correctly Reading of SFR EINT address FB causes data corruption in the register It is not recommended to read the contents of EINT register Workaround SFR EINT holds the interrupt edge flags and the rising falling edge control flags for external interrupts 7 to 9 If it is necessary for the application to read this register then the application software can declare a shadow register to SFR EINT This shadow register must be updated each time SFR EINT is written To retrieve the contents of SFR EINT the shadow register is read instead Errata Sheet C508 4E Step ES AB AB 4 8 K Yang V 1 0 2004 09 Infineon Errata Sheet Functional Deviations INT 2 SFR EINT does not support all addressing modes Writi
3. of COUTS 0 When COUTXI is set no inversion at the compare outputs When COUTXI is cleared the output signal of Compare Timer 2 which is wired to the compare outputs COUTx x 0 2 in burst or block commutation mode is inverted Workaround None Errata Sheet C508 4E Step ES AB AB 6 8 K Yang V 1 0 2004 09 Infineon Errata Sheet Functional Deviations CCU 3 CCU 4 The Phase Delay Timer is no longer a feature of the Capture Compare Unit of the C508 The phase delay timer of the CCU is no longer a feature of the C508 Previous items relating to the phase delay timer are to be ignored The C508 User s Manual and Data Sheet will be updated and excludes the phase delay timer Bit 6 of SFR COTRAP is now a reserved bit and must remain cleared always Writing a 1 to this bit is prohibited Workaround None EH 1 In Emulation Mode the device may not work properly with the Emulator at the crystal frequency higher than 8 MHz In Emulation Mode the device may not work properly with Emulator for the crystal frequency range greater than 8 MHz This commonly results to missing some interrupt responses from the Emulator It should be noted that this would not affect the functions of C508 device for full speed 10 MHz operation in Normal Mode Workaround Use crystal frequency less than or equal to 8 MHz for Emulation Mode Errata Sheet C508 4E Step ES AB AB 7 8 K Yang V 1 0 2004 09 In
4. e Mode the WDT can be refreshed and Timer 0 1or 2 can be started immediately to synchronize the WDT In the interrupt service routine of Timer 0 1 or 2 the WDT must be refreshed If required Idle Mode could be entered once again Errata Sheet C508 4E Step ES AB AB 5 8 K Yang V 1 0 2004 09 Infineon Errata Sheet Functional Deviations CCU 1 The PWM is Output on CCx pins instead of COUTx during the Rotate Left 0 Phase Shift mode In the Block Commutation mode the Rotate Left at 0 Phase Shift Mode User s Manual page 6 97 can be selected by the three control bits BCM1 1 BCMO 0 and BCTSEL 1 During this 0 phase shift mode the PWM signal is output on CCx pins instead of COUTxX pins if the modulation mode is selected Workaround None CCU 2 The CT1 output signal inversion in burst and block commutation is also controlled by the initial value of COUT3 The function description for the control bit COUTXI in SFR COINI on page 6 75 of User s Manual is true only if the initial value of COUT3 is set to 1 The complete function description should be Bit Function COUTXI Compare Timer 1 output signal inversion in burst and block commutation Initial value of COUTS 1 When COUTXI is set the output signal of Compare Timer 2 which is wired to the compare outputs COUTx x 0 2 in burst or block commutation mode is inverted When COUTXI is cleared no inversion at the compare outputs Initial value
5. fineon Errata Sheet Deviations from Electrical and Timing Specification 3 Deviations from Electrical and Timing Specification No deviations from the Electrical and Timing Specification are known in this step 4 Application Hints No application hints for this step Application Support Group Singapore Errata Sheet C508 4E Step ES AB AB 8 8 K Yang V 1 0 2004 09
6. ng data to SFR EINT address FBy can only be done by using Immediate Addressing Mode or Register Addressing Mode Workaround In order to set the interrupt rising falling edge control flags of SFR EINT for external interrupts 7 to 9 the Immediate Addressing Mode or Register Addressing Mode should be used For example Using Immediate Addressing Mode MOV EINT data Using Register Addressing Mode OV A data OV EINT A If Direct Addressing Mode has to be used it is suggested as below OV direct data where direct is the memory address OV A direct OV EINT A WDT 1 Watchdog Timer is not halted in Idle Mode The Watchdog Timer WDT is not halted in the Idle Mode as defined However during the Idle Mode an overflow condition of the WDT does not initiate an internal reset In such a case the WDT starts a new count sequence Workaround 1 Do not use the Watchdog Timer function in combination with the Idle Mode 2 Incase of WDT is running before entry into idle mode to avoid a WDT initiated reset upon exit of the Idle Mode the following methods can be used a The WDT is refreshed immediately upon exit from Idle Mode b A timed interrupt can be used to exit the Idle Mode before the WDT reaches the counter state 7FFC This can be achieved by using Timer 0 1 or 2 This timer can be programmed to generate an interrupt at a WDT counter state prior to overflow for e g at 7FOO Prior to entering Idl
7. tion Fixed in Change Deviation Step ADC 1 The upper limit for fagc is increased from 2 MHz to 5 MHz ADC 2 A D Converter Clock Prescaler Ratio is not as defined in documentation INT 1 Contents of SFR EINT cannot be read correctly INT 2 SFR EINT does not support all addressing modes WDT 1 Watchdog Timer is not halted in the Idle Mode WDT 2 Typing Error on the Reset Value of Watchdog Timer Updated Doc CCU 1 The PWM is Output on CCx pins instead of COUTx during the Rotate Left 0 Phase Shift Mode CCU 2 The CT1 output signal inversion in burst and block commutation is also controlled by the initial value of COUT3 CCU 3 The Phase Delay Timer is no longer a feature of the CCU 4 Capture Compare Unit of the C508 EH 1 In Emulation Mode the device may not work prop erly with the Emulator at the crystal frequency higher than 8 MHz OTP 1 OTP module may fail under special conditions lead AB ing to undefined operation Table 2 AC DC Deviations AC DC Short Description Fixed Change Deviation in Step None Errata Sheet C508 4E Step ES AB AB 2 8 K Yang V 1 0 2004 09 C Infineon technologies Errata Sheet History List Change Summary Table 3 Application Hints Application Short Description Fixed Change Hint in Step None Errata Sheet C508 4E Step ES AB AB 3 8 K Yang V 1 0 2004 09 Infineon Errata Sheet Functional Deviations 2 Functional Deviations

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