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1. Signal Direction Description EP_DATAOUT 15 0 Output Wire values output sent from host ep_addr 8 h21 okwireOut wire0ut21 ok1Cok1 ok2 ok2 ep_datain ep21data okwireIn wire0ut03 ok1Cok1 ok2 ok2 ep_addr 8 h03 ep_dataout ep03data okTriggerOut wireOut21 okwireOut port map okl gt okl ok2 gt ok2 ep_addr gt x 21 ep_datain gt ep21data Clock to which the trigger is synchronized wire0ut03 okwireIn port map okl gt okl ok2 gt ok2 ep_addr gt x 03 ep_dataout gt ep03data okTriggerln signal Direction Description okTriggerout trigout6A ok1 ok1 ok2 ok2 ep_clk clk2 ep_addr 8 h6a ep_trigger ep6Atrig Independent triggers to host EP_CLK Input Clock to which the trigger should synchronize EP_TRIGGER 15 0 Output Independent triggers from host okTriggerIn trigin53 ok1Cok1 ok2 ok2 ep_clk c1k2 ep_addr 8 h53 ep_trigger ep53trig trigOut6A okTrigger0ut port map ok1 gt ok1 ok2 gt ok2 ep_addr gt x 6a ep_clk gt clk2 ep_trigger gt ep6Atrig trigin53 okTriggerIn port map okl gt okl ok2 gt ok2 ep_addr gt x 53 ep_clk gt clk2 ep_trigger gt ep53trig okPipeln l okPipeOut Signal Direction Description Signal Direction Description EP_DATAOUT 15 0 Output Pipe data output EP_WRITE Output Acti
2. www opalkelly com FrontPanel User s Manual Activating a Triggerln is a very fast operation and can operate at over 1 000 times per second Only one trigger is written per call Updating TriggerOuts is similar to reading all WireOuts all TriggerOuts are read simultaneously Measured Performance API Call Calls per second UpdateWirelns 1000 UpdateWireOuts 800 ActivateTriggerln 1600 UpdateTriggerQuts Pipes Bulk Transfers Pipes are the fastest way to transmit or receive bulk data Due to overhead performance is best with long transfers Each time you perform a pipe transfer several layers of setup are required including those at the firmware level API level and operating system level Therefore it is best to design around using long transfers if possible This generally means using large buffer sizes on the FPGA and relying on external memory when possible Low latency high bandwidth transfers present a special challenge to any protocol and USB and therefore FrontPanel is no different In this case the two goals are at odds trying to perform many operations and still achieve high bandwidth The problem is that the overhead associated with setting up each transfer cuts into the time available to perform the data transfer It is important to note that Windows Linux and Mac OS X are not real time operating systems They are complex systems that may have many other processes taking higher priority at any given time T
3. The okTriggerSound does not physically appear on a virtual panel Instead it is attached to the panel and is activated when a trigger out is activated Upon activation it rings the system bell as a brief audible notification of a trigger out event An optional WAV file may be specified that will play instead of the system bell Element Type Description o U HEX BYTE Endpoint address for the corresponding Trigger In bit NUMBER Bit to which this component addresses O LSB 15 MSB TEXT Label text shown in the FrontPanel component list OP TIONAL FILENAME _ Filename of a WAV file to be played upon triggering OP TIONAL XML Example lt object class okTriggersound gt lt endpoint gt 0x63 lt endpoint gt lt bit gt 3 lt b1t gt lt label gt Transfer complete trigger lt label gt lt soundfile gt c windows Media chimes wav lt soundfile gt lt object gt okTriggerLog Trigger Out okTriggerLog displays specified Trigger Out events along with a user specified text message in list form Each trigger item within the list is stamped with the time hh mm ss of the occurrance Element Type Description 222222222 POSITION Position of the top left corner SIZE trigger XML Adds a message to be entered in the log when a trigger event occurs The XML contains the endpoint bit and message tags as shown in the example below XML Example lt object class okTriggerLog gt lt
4. This sample is designed to work with the XEM3001 The Counters sample is a bit more complicated than the previous example It includes a few more FrontPanel components and also adds a few Trigger endpoints More importantly though it adds more hardware in the form of HDL so you can see how FrontPanel integrates with HDL in a slightly more complicated setup The FrontPanel virtual interface for this sample is shown below Counters Example Counter 1 Controls Cha 7 4 x 3 0 Counter 2 Controls Crea 3 Y Autocount y17 4 y 3 0 Hardware Description The hardware for the Counters sample has two counters the okHostInterface a single Wire In endpoint three Wire Out endpoints and a Trigger In endpoint The hardware also routes to the LEDs on the XEM3001 www opalkelly com 79 FrontPanel User s Manual Counter 1 The first counter is an 8 bit up counter with enable synchronous reset and disable The enable signal is generated by a separate 24 bit counter to make the count progression slower The Ver ilog HDL for this counter and its clock divider counter is shown here always posedge clk1 begin div1 lt divl 1 if divl1 24 h000000 begin div1 lt 24 h400000 clkidiv lt 1 b1 end else begin clkldiv lt 1 b0 end if clkldiv 1 b1 begin if resetl 1 b1 countl lt 8 h00 else if disablel 1 b0 countl lt counti 1 end end From the descri
5. COUMEE 72 sh acre A dat hho esas id Gaea eaten at doe 80 Endpoints sour ar bogie oe Godse AP eee ss 81 MS O been daca ED EEE 81 Nido ols ius D 0X4O sico ee ree ee eee eee 81 Wire Out 0 20 0x21 and 0x22 caro is ii dane 81 FrontPanel Components 00000 cece eee eee eens 82 Panel 1 Counters EXaMple vai cari a eii 82 Panel 2 PUSMDUTONS 2 04404 aaa pol is a ao 82 Quick Reference Endpoints oo oooooooomoo ooo 83 Quick Reference Components occcocoooo eee eeee 84 FrontPanel User s Manual An Introduction to FrontPanel FrontPanel is a software platform designed to make using Opal Kelly FPGA experimenta tion boards easier more productive more powerful and more configurable Most importantly FrontPanel provides the basic functionality required to configure the hardware including the FPGA and peripherals on board After FPGA configuration the USB interface switches from a high speed download port to active communication with FrontPanel allowing you to interface and control your FPGA design from within a single application By virtualizing many common controls found on typical evaluation or prototyping boards FrontPanel enables far greater flexibility and capability than pure hardware based approaches Terminology Collectively FrontPanel describes several components that make up the FrontPanel environ ment FrontPanel HDL HDL modules you design into your FPGA hardware that
6. The 24 bit color of the LED as RRGGBB endpoint The endpoint address expressed in hexadecimal for this LED s Wire Out endpoint The specific bit on the endpoint address that this LED monitors Other Samples The standard FrontPanel installation includes other samples including samples which illustrate use of the C and Python programmer s interfaces A summary of these samples is shown below They are placed in the installation directory in the Samples folder 76 www opalkelly com gt gt gt FrontPanel User s Manual Sample_ FrontPanel C Python Java Description First JZ Avery simple FrontPanel only project to get started quickly Displays two independent counters with controls for each Since it is implemented Saunier dd e in FrontPanel C and Python it is a good start for those wanting to learn the APIs This sample is a showcase of the FrontPanel Controls Y components available Connects to Pipeln and PipeOut modules on PipeTest Y the FPGA to test transfer rates Block sizes can be set by the user A command line sample based on the Open DES Y Y v Y Cores org triple DES encryption and decryp tion core www opalkelly com 7T FrontPanel User s Manual 78 www opalkelly com FrontPanel User s Manual Appendix B The Counters Sample This sample is a bit more complicated than the simple example and showcases a few more features of FrontPanel and the XEM3001
7. all 16 bits of a Wire Out It appropriately selects the proper number of bits for smaller ranges Element Type Description OOOO Either HORIZONTAL or VERTICAL fst NOMBER This on he endpoint the SB othe splay XML Example lt object class okGauge gt lt position gt 120 235 lt position gt lt size gt 150 15 lt size gt lt style gt HORIZONTAL lt style gt lt range gt 65535 lt range gt lt endpoint gt 0x33 lt endpoint gt lt bit gt 0 lt bit gt lt object gt okTriggerButton Trigger In The okTriggerButton appears identical to the okPushbutton but connects to a Trigger In endpoint The trigger is activated when the button is pushed rather than when the button is released You may wish to denote that a particular button is a trigger by surrounding the label with hyphens In the example below the button label is Reset to make the button appear different from an okPushbutton Element Type Description OOOO e Text feberen town sie baton nome ett which tis component addresses O LSB 5 M58 XML Example lt object class okTriggerButton gt lt label gt Reset lt label gt lt position gt 20 110 lt position gt lt size gt 60 20 lt size gt lt endpoint gt 0x40 lt endpoint gt lt bit gt 0 lt bit gt lt tooltip gt Reset Counter 2 lt tooltip gt lt object gt www opalkelly com FrontPanel User s Manual okTriggerSound Trigger Out
8. donetrigger gt lt object gt okPLL22150 This component provides an XML method to program the on board PLL When provided with a label parameter this component becomes a pushbutton on the panel GUI When that button is pressed the PLL is configured with the given parameters This allows you to specify multiple PLL configuration and provide multiple buttons to access them without going through the PLL dialog A convenient tooltip lists the VCO and output frequencies for the configuration When the component does not have the label parameter this configuration is loaded to the PLL when the profile is loaded It is not stored to EEPROM and the component does not create a GUI button The only way to reconfigure the PLL even after a new FPGA configuration file is loaded is to reload the profile Note that this element is ignored if the target device does not have a CY22150 PLL www opalkelly com 59 FrontPanel User s Manual 60 Eement Type Descrip Y labe TEXT Label text shown inside the button OPTIONAL p NUMBER VCO P multiple 6 2055 CS fq NUMBER VCO O divider 2 172 SSS divider1 NUMBER Divider 1 N value 4 127 divider2 The parameter source is a string that represents the source of the divider ref The reference 48 MHz is used vco The VCO frequency 48 P Q is used outputO STRING This string is either on or off and turns the output on or output of
9. e Opal Kelly FrontPanel A new way to control and observe FPGA designs through virtual instruments on your PC Opal Kelly s FrontPanel software is designed to provide controllability and observability for FPGA de signs It s unique design allows users to describe their own control panels using industry standard XML descriptions of components such as LEDs hex displays push buttons toggle buttons triggers and so on The components then connect to endpoints within the user s FPGA design Once connected the interface details are transparent FrontPanel handles all interaction between the virtual controls and the FPGA internals In the end FrontPanel eliminates the time and effort of interfacing to a design and greatly assists in the external controllability and observability of that design Software documentation samples and related materials are Copyright O 2005 2007 Opal Kelly Incorporated Opal Kelly Incorporated 3442 SE Ironwood Ave Hillsboro OR 97123 http www opalkelly com All rights reserved Unauthorized duplication in whole or part of this document by any means except for brief excerpts in published reviews is prohibited without the express written permission of Opal Kelly Incorporated Opal Kelly the Opal Kelly Logo and FrontPanel are trademarks of Opal Kelly Incorporated Linux is a registered trademark of Linus Torvalds Microsoft and Windows are both registered trademarks of Microsoft Corporation All ot
10. 0x02 The expected result the unsigned sum of the two numbers is also computed At approximately time 0 ps these numbers are generated The UpdateWirelns call is performed but the inputs do not propagate to the design until time 780 ns as seen at the first cursor The design immediately places the result 0x93A5 on WireOut 0x21 This value is not read out by the simulation until UpdateWireOuts has completed at time 1670 ns the second cursor The third cursor shows when the second iteration of inputs have propagated to the design after the second UpdateWirelns call www opalkelly com FrontPanel User s Manual Simulation Accuracy Back to back wire updates such as the ones seen in this simulation do not in fact occur this quickly The bandwidth constraints on USB and other operating system issues will cause them to happen much slower In the interest of simulation speed however we have accelerated the response time of some of the host simulation actions The user may at his or her discretion place additional delays within the simulation in order to better model the speed of the real host interface In most cases this will not be necessary Example DES Tester A more thorough example of the capabilities of the Host Simulation Library including Pipeln and PipeOut transfers is included with the DES sample A step by step review of the setup and ex ecution of this sample has been included in Part IV of our online FrontPanel
11. 260 lt position gt lt size gt 100 55 lt size gt lt keys gt lt KeyButton keycode KEY_UP gt lt endpoint gt 0x00 lt endpoint gt lt bit gt 0 lt bit gt lt KeyButton gt lt KeyToggle keycode KEY_DOWN gt lt endpoint gt 0x00 lt endpoint gt lt bit gt 1 lt bit gt lt KeyButton gt lt KeyTrigger keycode KEY_A gt lt endpoint gt 0x40 lt endpoint gt lt bit gt 1 lt bit gt lt KeyTrigger gt lt KeyTrigger keycode KEY_A gt lt up gt lt endpoint gt 0x40 lt endpoint gt lt bit gt 1 lt bit gt lt KeyTrigger gt lt keys gt lt object gt www opalkelly com 63 FrontPanel User s Manual 64 www opalkelly com FrontPanel User s Manual FrontPanel Host Simulation Hardware simulation is a valuable tool used to reduce design cycles and quickly debug a hard ware design While debug outputs to real instruments logic analyzers and oscilloscopes as well as the virtual instruments supported by FrontPanel can help in the controllability and observability of a design nothing can match the flexibility offered by simulation Unfortunately full system simulation is often difficult to attain Simulation models of external hardware are often not available More importantly integration of the hardware simulation with software can be difficult The FrontPanel API provides a simple capable and convenient communication interface be tween the hardware design residing within the FPGA and a user ap
12. Trigger IN ose ea eee Sas ae eee a eee ead oe 61 FrontPanel Host Simulati0N o oooooooooooo 65 System SimulationiMOgGel is a sra ia rr oa Goats ce 65 Simulation Requirements 000 000 eee eee ees 66 Configuring AcWwenDL ss sacih enced bait eraris rara 66 Configuring ModelSiM s ressrrasserr sr io ea 66 Adding Host Simulation to a Test Fixture ananuna anaana 67 Example Test FIXtUrGS denisror prior a a be 67 ROS aaa 67 simulating PIPES 4222 5pco rara er 67 Simulation in Aldec ActiveHDL 2 0000 0c ees 68 Design Workspace Setup ococoooooococonr rika iaiia 68 Example FifSt sion sacada 69 Required PICS casinos adas oros 69 Perform the Simulation sac 69 Analyzing the Results ooo ocrcrrr ir rr OR ERALA pea 70 Simulan Accra casita das 71 Example DES Tester ociosas nie ir T1 Appendix A A Simple Example n n nnna anaana 73 Toplevel Descrip ria A 74 TATUNG a st ap Sena a cheek peo Babar Swaine E 74 FrontPanel Interface Modules 00000 cece 75 FrontPanel XML Description 0000 cee eee eee 15 OK PMS tia iS a odar 75 OKTOGGIEBUNOR 2 2 c 0ce Sead e Sasi o aid ed ee aii 76 AE ia ee ete aie eee etait can oe ie ean ee 76 Other Samples roco erori 286408004 Hhees eG oe beta eae teaeeRee ere 76 Appendix B The Counters Sample 2 00 2005 79 Hardware DESCH PHNOM chat ida da id Bie dudes anda 79 SN A eae dee e dir dreds ede aie tend beg a eee d 80
13. a 31 Endpoint TYPES ss cri a AA Ai ci 32 Endpoint Addresses 0000 eee 33 OKVVINGHN caiste inapelable dias 39 OKVWIFSQUE 0050 2569 ds A EeeES E 33 A O o 34 Nte lo LO Ul iera o ELO O a ake bata he trade artsy Gk bet Sia 34 OK IPCI 4 4 sda sis wastes ache ene Ge ee a a Sia ae 34 OKPIPCOUL scenas ntr Ge eee deceit etene A a 35 OKBI PIPEN 220 diaria duds a Bnd dns aden in acinar 36 OKBTPIPGOUl cis aden t ened rias aca 37 OKBUNGKCEPIDEIN s 62 52 3200 renni bandas rl ie 38 okBufferedPipeOut 0 000 eee 39 Using the FrontPanel Application o o oooooooo 41 selecting the Active Device eo 0rcoosorpsrcrrrrar dr ora 42 Device Identifier SIND ooo ia a E 42 FPGA Configuration Downl02d oocoocccoocco eee 42 Drag ana Dips cua criada ee eens eee sb 42 PLL GonfigurationiC22 Desi scores abbr rei 42 VCO SGUD uqe ds 43 Divide id corrosivos oa 43 OUD ui ias ana 43 EEPROM REG 5 044 4 206 4 22 eedecninde riera 43 EEPROM Wiles puz s ce acca ban Ia a agen nee 44 ADD iecrt tanto eeta Rad setene OA 44 Example PLL Configurations 2264 96 dan cars da od 44 PLL Configuration CY 22393 i0020 lt 000080nd0eeonceonseeentd gd aearne 44 Loading a FrontPanel Profile c ic0 aca0anse0deectaneavatanaudavaae 45 Drag and DOP in22655 San neereesnnenereedchaetos ad iehouesees 45 PrelerencES siria ricas 45 Wire Update Rate o 04 0 0 44 4 0 e6 40 0de 4 dodo daeaa deed dean bavgadi 45 Configure PLL Before FPGA Do
14. a corresponding value When that text item is selected the Wire In is updated with the value Element Type Description OOOO U 0 NUMBER Bit to which this component addresses O LSB 15 MSB options This field is further broken down into item tags as shown in the example below Each item tag is inserted in order into the combobox Each item tag has a value property which specifies the Wire In value to be used for each item selection www opalkelly com 53 FrontPanel User s Manual 54 XML Example lt object class okCombobox gt lt position gt 180 160 lt position gt lt size gt 100 1 lt s1ize gt lt options gt lt item value 0 gt Test mode lt item gt lt item value 1 gt Standard mode lt item gt lt item value 2 gt Block floating point mode lt item gt lt options gt lt endpoint gt 0x01 lt endpoint gt lt bit gt 1 lt bit gt lt object gt okLED Wire Out This component implements a simple on off indicator analagous to a physical LED It is attached to a specified bit on a specified Wire Out endpoint and monitors the status of that bit Both the style round or square and color a 24 bit RGB value may be specified The LED is on when the Wire Out is asserted logic 1 and off when the Wire Out is deasserted logic 0 When on the LED is displayed in the specified color When off the LED is darkened Element Type Description o POSITION Position of the top
15. be asserted www opalkelly com 81 FrontPanel User s Manual FrontPanel Components The user interface for the Counters sample includes two panels The first panel contains five but tons four hex displays eight LEDs and a check box There are also two cosmetic components called okStaticBox which are used to group the components visually The second panel simply contains four LEDs used to display the state of the pushbuttons Panel 1 Counters Example The active FrontPanel components are listed below with their corresponding endpoints Component___ Label___ Endpoint Bit okPushbutton__ Reset oxoo o okTriggerButton Reset 0x40 o okTriggerButton okTriggerButton okToggleCheck okHex okHex wo oo ooo _ t okHex okHex woa loar p oKLED OKLED OKLED o fow p Note that the okLED and two of the okHex components share endpoint 0x20 FrontPanel allows this and will update both components when Wire Out endpoints change Itis also possible to map two components to input endpoints Panel 2 Pushbuttons The second panel is not automatically opened when the Conters XFP file is loaded You can open it by pressing the number 2 on your keyboard or navigating to View Pushbuttons at the top of the FrontPanel window This displays a small window with the following compo nents Component Label Endpoint Bivmask xeo o fo fo 8 amp 2 wwwopakdyceom gt Wire values input to be sent to host
16. gt lt label gt Transfer complete trigger lt label gt lt soundfile gt c windows Media chimes wav lt soundfile gt lt object gt Trigger Out okTriggerLog lt object class okTriggerLog gt lt position gt 5 290 lt position gt lt size gt 350 100 lt size gt lt trigger gt lt endpoint gt 0x60 lt endpoint gt lt bit gt 1 lt bit gt lt message gt Your laundry is done lt message gt lt trigger gt lt trigger gt lt endpoint gt 0x61 lt endpoint gt lt bit gt 0 lt bit gt lt message gt Elvis the cat has left the building lt message gt lt trigger gt lt object gt Trigger Out okTriggerMessage Trigger Out lt object class okTriggermessage gt lt position gt 120 225 lt position gt lt size gt 220 20 lt size gt lt style gt DOUBLE_BORDER ALIGN_CENTER lt style gt lt trigger gt lt endpoint gt 0x60 lt endpoint gt lt bit gt 0 lt bit gt lt message gt Test trigger has just gone off lt message gt lt background gt ff0000 lt background gt lt foreground gt ffffff lt foreground gt lt delay gt 0 25 lt delay gt lt trigger gt lt trigger gt lt endpoint gt 0x60 lt endpoint gt lt bit gt 1 lt bit gt lt message gt Your laundry is done lt message gt lt background gt ffffff lt background gt lt foreground gt cc0000 lt foreground gt lt trigger gt lt object gt
17. gt ok2 ep_addr gt x 53 ep_clk gt clk2 ep_trigger gt ep53trig okTriggerOut The target may trigger the host using this module EP_TRIGGER 15 0 contains 16 independent trigger signals which are monitored with respect to EP_CLK If EP_TRIGGER x is asserted for the rising edge of EP_CLK then that trigger will be set The next time the host checks trigger values the triggers will be cleared Signa Direction pesen Verilog Instantiation okTriggerout trigOut6A ti_clk ticlk ti_control ti_control ti_data tidata ep_addr 8 h6a ep_clk clk2 ep_trigger ep6Atrig VHDL Instantiation trigOut6A okTriggerOut port map ok1 gt okl ok2 gt ok2 ep_addr gt x 6a ep_clk gt clk2 ep_trigger gt ep6Atrig okPipeln The okPipeln module provides a way to move synchronous multi byte data from the host to the target As usual the host is the master and therefore the target must accept data as it is moved through this pipe up to 48 MHz The EP_WRITE signal is an active high signal which is as serted when data is to be accepted by the target on EP_DATAOUT 15 0 It is possible that EP_WRITE be asserted for several consecutive cycles without deasserting In such a case EP_DATAOUT 15 0 will be changing every clock www opalkelly com FrontPanel User s Manual This somewhat simple Pipe In implementation requires that the target interface be very respon sive to incoming pipe da
18. gt 16777215 lt maxvalue gt lt value gt 49837 lt value gt lt endpoint gt 0x03 lt endpoint gt lt bit gt 0 lt bit gt lt object gt okCombobox Wire In lt object class okCombobox gt lt position gt 180 160 lt position gt lt size gt 100 1 lt size gt lt options gt lt item value 0 gt Test mode lt item gt lt item value 1 gt Standard mode lt item gt lt item value 2 gt Block floating point mode lt item gt lt options gt lt endpoint gt 0x01 lt endpoint gt lt bit gt 1 lt bit gt lt object gt okKeyPanel Wire In Trigger In lt object class okKeyPanel gt lt label gt Key Panel A lt label gt lt color gt b0f0b0 lt color gt lt position gt 5 260 lt position gt lt size gt 100 55 lt size gt lt keys gt lt KeyButton keycode KEY_UP gt lt endpoint gt 0x00 lt endpoint gt lt bit gt 0 lt bit gt lt KeyButton gt lt KeyToggle keycode KEY_DOWN gt lt endpoint gt 0x00 lt endpoint gt lt bit gt 1 lt bit gt lt KeyButton gt lt KeyTrigger keycode KEY_A gt lt endpoint gt 0x40 lt endpoint gt lt bit gt 1 lt bit gt lt KeyTrigger gt lt KeyTrigger keycode kKEY_A gt lt up gt lt endpoint gt 0x40 lt endpoint gt lt bit gt 1 lt bit gt lt KeyTrigger gt lt keys gt lt object gt lt object class okLED gt lt position gt 135 50 lt position gt lt size gt 25 25 lt size gt lt label gt 1 lt labe
19. left corner SIZE TEXT Label text The optional align property can be left right top bottom and specifies the text alignment relative to the LED eo TEXT Tooltip text HEX BYTE Endpoint address for the corresponding Wire Out bit NUMBER Bit to which this component addresses 0 LSB 15 MSB color COLOR The LED or color The off color is automatically com puted as a darker version of this color style STYLE ROUND Displays a round LED SQUARE Displays a square LED XML Example lt object class okLED gt lt position gt 135 50 lt position gt lt size gt 25 25 lt size gt lt label align top gt 1 lt label gt lt style gt SQUARE lt sty1e gt lt color gt 00ff00 lt color gt lt endpoint gt 0x20 lt endpoint gt lt bit gt 1 lt bit gt lt object gt okHex Wire Out The okHex component displays four bits of a Wire Out endpoint as a hexadecimal digit Multiple okHex components may be attached to the same Wire Out endpoint For example to display an entire byte in hex you could display two okHex components side by side Attach the left compo nent to bit 4 and the right component to bit 0 www opalkelly com FrontPanel User s Manual Element Type Description Y oper Text alte som ise i ut HEX BYTE Endpoint address for the corresponding Wire Out NUMBER Least significant bit to which this component addresses The hex value comes from the specified bi
20. level introduction to the API s organization and use Samples Often the best way to learn how to apply a programming interface is to see examples of its ap plication Please see the samples included with FrontPanel for these examples www opalkelly com 17 FrontPanel User s Manual Organization The FrontPanel API is provided as a dynamically linked library that you include with your applica tion The interface to the DLL is C but a C wrapper is provided to make the entire DLL appear as if it were a native C class in your application The library contains a small number of classes which you then instantiate within your code The details of the USB connection between the FPGA and your PC disappear within the neat con fines of the API These classes are shown in the table below in further detailed in what follows okCPLL22150 This is a container class providing methods and structure used to config ure the Cypress 22150 PLL on the XEM3001 An instance of this class can be created and used to program the on board PLL or the class can be generated from the EEPROM settings okCPLL22393 This is a container class providing methods and structure used to config ure the Cypress 22150 PLL on the XEM3001 An instance of this class can be created and used to program the on board PLL or the class can be generated from the EEPROM settings okCUsbFrontPanel This is the base class used to find configure and communicate with a FrontPane
21. position gt 5 290 lt position gt lt size gt 350 100 lt size gt lt trigger gt lt endpoint gt 0x60 lt endpoint gt lt bit gt 1 lt bit gt lt message gt Your laundry is done lt message gt lt trigger gt lt trigger gt lt endpoint gt 0x61 lt endpoint gt lt bit gt 0 lt bit gt lt message gt Elvis the cat has left the building lt message gt lt trigger gt lt object gt okTriggerMessage Trigger Out okTriggerMessage displays a brief text message similar to an okStaticText display when a par ticular trigger occurs Similar to okTriggerLog you can setup a variety of messages to be dis played in the same area when any of a number of trigger outs occur www opalkelly com 57 FrontPanel User s Manual 58 Element Type Description 22222222 POSITION Position of the top left corner SIZE style STYLE Acceptable border styles are none means no border SIMPLE_BORDER RAISED_BORDER SUNKEN_BORDER Acceptable text styles are ALIGN_LEFT default ALIGN_RIGHT ALIGN_CENTER trigger XML Adds a message to be displayed when a trigger event occurs The XML contains endpoint bit delay and message tags as shown in the example below The delay parameter specifies an optional delay in seconds after which the message will disappear XML Example lt object class okTriggerMessage gt lt position gt 5 290 lt position gt lt size gt 200 20 lt size gt lt s
22. the next digit on the right Element Type Description Cd will span multiple consecutive endpoints as necessary XML Example lt object class okDigitEntry gt lt position gt 5 215 lt position gt lt size gt 200 30 lt size gt lt tooltip gt Sets the integer divider lt tooltip gt lt minvalue gt 0 lt minvalue gt lt maxvalue gt 16777215 lt maxvalue gt lt value gt 49837 lt value gt lt endpoint gt 0x07 lt endpoint gt lt bit gt 0 lt bit gt lt object gt 52 www opalkelly com FrontPanel User s Manual okSlider Wire In Element Type Description OOOO fees Text I event sronto fit NOMBER ito wich is component adresse 0 L 38 TENE style STYLE VERTICAL Displays the slider vertically HORIZONTAL Displays the silder horizontally SHOWLABELS Show min max value labels XML Example lt object class okslider gt lt position gt 310 5 lt position gt lt size gt 25 100 lt size gt lt label gt Hi lt label gt lt tooltip gt 4 bit vertical slider lt tooltip gt lt style gt VERTICAL SHOWLABELS lt sty1e gt lt minvalue gt 0 lt minvalue gt lt maxvalue gt 15 lt maxvalue gt lt value gt 3 lt value gt lt endpoint gt 0x04 lt endpoint gt lt bit gt 4 lt bit gt lt object gt okCombobox Wire In The okCombobox allows you to relate numerical values on a Wire In endpoint to text selections in a traditional combobox You specify the text items and
23. xem ConfigureFPGA c Xcounters bit xem ActivateTriggerin 0x40 0 Java API The Java API is built as an extension library to be used with Sun s compiled Java language It it built on top of the JNI Java Native Interface The API is distributed as a shared library and a Java archive JAR file Required Files There are only two required files for the Java API the shared library and the Java archive e okjFrontPanel dll Windows e okjFrontPanel so Linux e libokjFrontPanel jnilib Mac OS X e okjFrontPanel jar Under Windows you can keep the DLL in the directory where you run java Under Linux the shared object should be placed within your java class path For example under the SuSE 9 2 Linux distribution you would copy the file to usr lib jre lib i386 Example Usage Within a Java source that uses the Java FrontPanel API you need to import the FrontPanel classes using the following line 24 www opalkelly com FrontPanel User s Manual import com opalkelly frontpanel To actually load the FrontPanel library into Java you will also need to make the following System call before using any FrontPanel API objects System loadLibrary okjFrontPanel Compiling a Java application for use with the Java API can be done on the command line using javac with the classpath argument to specify the Java API JAR as shown below javac classpath okjFrontPanel jar MyClass java Likewise when running
24. 00 feremers dB o fesomers raras Isochronous Transfers FrontPanel does not support USB isochronous transfers It is true that isochronous transfers can negotiate for guaranteed bandwidth on the USB which can be very helpful when trying to build a system that must deliver certain performance to the end user However this guarantee comes at a significant price isochronous transfers do not provide the same level of error detection and error correction that the more reliable USB bulk transfers provide Furthermore the guarantee is only for bus bandwidth and says nothing about the operating system s capabilities If an error occurs during the transmission of a bulk transfer the host will request that the missing packet be repeated The host will also properly reconstitute the transmission so that everything is properly sequenced With isochronous transfers the bandwidth and latency requirements trump delivery accuracy Therefore it is possible that some data may be lost in this pursuit Isochronous transfers were created for things such as multimedia content that requires on time delivery But if the host is too busy or something interrupts the transfer a few missing frames of video or a few milliseconds of audio are considered expendable www opalkelly com FrontPanel User s Manual Application Programmer s Interface The FrontPanel application provides a turnkey method to make basic user interaction available to your FPGA har
25. 0000 Enable 4 Source DIVICLK DIVIN Frequency 50 000000 C Enable 5 Source DIVICLK DIVIN v Frequency 50 000000 C Enable 6 Source DIVICLK DIVIN Frequency 50 000000 C Enable aaa Erro As you make changes in the PLL Configuration Dialog the output frequencies are automatically updated to indicate how the outputs will behave with the current selections Details of the PLL configuration are available in Cypress documentation for the CY22150 A brief description of the parameters follows VCO Setup The CY22150 contains a single PLL which is used as the source to a divider network which then produces the signals at the output Because of this all outputs are referenced from the same PLL The VCO frequency is produced by dividing the reference frequency fixed at 48 MHz for the XEM3001 by Q and multiplying by P Cypress specifies that the VCO frequency should be kept between 250 kHz and 400 MHz for reliable operation The valid range for P is 8 to 2055 The valid range for Q is 2 to 129 Divider 1 and 2 Two divide by N blocks are available DIV1N and DIV2N each with a range from 4 to 127 The source for each divider can either be the VCO or the input reference The divider outputs are then used to generate the resulting output signal Outputs Each of the six outputs can have a different source as indicated by the combobox The choice of this source directly determines the clock frequency f
26. 01v1 deep asynchronous block RAM FIFO Because the FIFO is asynchronous the two ports can run with different clocks TI_CLK for the target interface side and EP_CLK for the user logic side The buffered pipes are provided as one way to cross the clock boundary between the host in terface and your design s clock if they differ Another simpler method would be to use a double buffered technique Some negotiation will be required between the host buffered pipe and user design to assure that FIFO overruns and underruns do not occur This would typically be done with wires or triggers to indicate to the host when the FIFO can accept additional data The FIFO used in this module is based on the Xilinx asynchronous FIFO presented in XAPP131 It has been slightly modified to accommodate the larger BRAM size of the Spartan 3 Please refer to the original application note for detailed FIFO usage and timing information Signa Deetion Description OOOO U EP_READ Input When asserted advances the FIFO read pointer to the next datum The next datum will be available during the following clock cycle EP_DATAOUT 15 0 Output Pipe data output EP_FULL Output Asserted when the endpoint FIFO is full EP_EMPTY Output Asserted when the endpoint FIFO is empty EP_STATUST 3 0 Output Indicates the fullness of the FIFO in 16 levels 1 16 full 1 8 full and so on Verilog Instantiation okBufferedPipeIn pipeIn87 ok1 ok1 ok2 ok2 ep_add
27. C Note that this counts all FrontPanel devices and also queries information about each device which can be retrieved using the Get DeviceListXXX methods below GetDeviceListModel Retrieves the board model of a connected device GetDeviceListSerial Retrieves the serial number of a connected devicce OpenBySerial Opens a device with matching serial number for communication GetDeviceMinorVersion Retrieves the current firmware minor version GetDeviceMajorVersion Retrieves the current firmware major version GetSerialNumber Returns a 10 digit serial number unique to each device This serial number may be used to select a specific device on the USB bus The serial number is set at the factory and is not user modifiable Device Configuration Once an available device has been opened these methods allow you to configure it s available features such as PLL settings and EEPROM parameters and to download configuration data to the FPGA GetDevicelD Returns a device identification string stored in the device Unlike the serial number this string may be changed by the user using the API or the FrontPanel application It is not guaranteed to be unique SetDevicelD Allows the user to set the device ID LoadDefaultPLLConfiguration Configures the PLL with settings stored in EEPROM GetPLLxxxConfiguration Retrieves the current on board PLL configuration xxx is either 22150 or 22393 SetPLLxxxConfiguration Sets the on board PLL to a g
28. Four things happen when you configure the device 1 The on board PLL is configured with the parameters stored in EEPROM 2 The FPGA is reset and a programming sequence is initiated 3 The configuration data is downloaded to the FPGA 4 The FPGA is checked to verify that the configuration was successful DONE is asserted Once complete the FPGA is now configured and running with the new design Drag and Drop As an alternative to clicking the download icon and using a file selector to choose the configura tion file you can simply drag a Xilinx bitfile onto the icon and release it FrontPanel then pro ceeds as if you had just chosen the file in the file selector PLL Configuration CY22150 su SU 42 The on board PLL is available to the USB microcontroller as an 1 C peripheral Through FrontPanel you can configure the PLL using the PLL Configuration Dialog which is opened by clicking on the icon to the left When you do so the current PLL configuration is read and the following dialog appears www opalkelly com FrontPanel User s Manual PLL Configuration Cypress CY 22150 VCO Setup Reference MHz 48 000000 P 400 Q 48 s VCO Frequency MHz 400 000000 Divider 1 Divider 2 Source OREF VCO Source OREF VCO DIVIN 8 s DIV2N 127 s Dutputs 1 Source REF v Frequency 48 000000 Enable 2 Source DIVICLK DIVIN Frequency 50 000000 Enable 3 Source DIVICLK DIVIN v Frequency 50 00
29. Host Interface core component provided as a pre synthesized module as well as the necessary IOB components to connect to the host interface pins of the FPGA okHostlnterface This module must be instantiated in any design that makes use of FrontPanel virtual interface components The following signals need to be connected directly to pins on the FPGA which go to the USB microcontroller on the XEM For a listing of the pin locations for a particular XEM product please see the user s manual for that device Signal Direction Description o HI_IN 7 0 Host interface input signals HI_OUTI 1 0 Output Host interface output signals HI_INOUT 15 0 In Out Host interface bidirectional signals www opalkelly com 31 FrontPanel User s Manual The remaining ports of the okHostInterface are connected to a shared bus inside your design These signals are collectively referred to as the target interface bus Each endpoint must con nect to these signals for proper operation Signal ____ Direction Description o OK1 30 0 Output Control signals to the target endpoints OK2 16 0 Control signals from the target endpoints TI_CLK Output Buffered copy of the host interface clock 48 MHz This signal does not need to be connected to the target end points because it is replicated within OK1 Instantiation of the okHostInterface is simple in either VHDL or Verilog Use the templates below in your toplevel HDL design A more detailed li
30. OOwire and ep20wire for clarity FrontPanel XML Description The user s interface shown at the beginning of this example is described in XML and shown below Only one instance of the okToggleButton and one instance of the okLED are shown for brevity The others instances are similar with the exception of their position tag and endpoint bit lt xml version 1 0 encoding IS0 8859 1 gt ES First FrontPanel Example Copyright c 2004 Opal Kelly Incorporated gt lt resource version 2 3 0 1 gt lt object class okPanel name panel1 gt lt title gt First FrontPanel Example lt title gt lt size gt 180 70 lt s1ize gt lt object class okToggleButton gt lt label gt 1 lt label gt lt position gt 10 10 lt position gt lt size gt 20 20 lt size gt lt endpoint gt 0x00 lt endpoint gt lt bit gt 0 lt bit gt lt object gt other okToggleButton objects removed lt LEDS gt lt object class 0kLED gt lt position gt 48 40 lt position gt lt size gt 25 25 lt size gt lt label gt 1 lt label gt lt style gt SQUARE lt sty1e gt lt color gt 00ff00 lt color gt lt endpoint gt 0x20 lt endpoint gt lt bit gt 0 lt bit gt lt object gt other okLED objects removed lt object gt lt resource gt Each FrontPanel XML description must contain the lt xml gt tag shown at the top as well as the lt resource gt and lt resource gt tag
31. SB Device interaction lt cocrsrrossorisr o ree 18 Device COnNgUralion sisas negada E 19 FPGA Commu nicati n pea ion irradian dei 19 Communicating with Multiple Devices 0 0 00 20 Querying Attached Devices 0 00 cece eens 20 Connecting to a Specific DEVICE 6 osais sis da 20 API COMMUNICATION 2 2 0 02 20622 24 26 2 8 apie rd 21 WINES anida asa de iat ee a e we aw Ga snes heehee 21 PPP een hbbes esd eestor eaSenever ate 21 RIDOS Sa O OE aa are ee sues 22 BlocieThrotlediPIDES eoisiorsbiotian riada 22 Example USIO viu isa aaa ara ada ci ea a 22 Regarding Device Ownership 02 0 600 5002 beeen eee enna eee bees 23 EY UNOR A dlavadce E sata arena TET E E E T 23 Required FICS u 4 304 0220 r2a oneiad er toorgnand ea e e 23 Example USIO L ssvditsnass cud ddan seed aaeeadsavaccaiawteuar as 24 PAV AP le hsm eo es sds dy sce ate Gna AG AE an Ganon re a OE ny eas 24 Required FOSA 24 Example USIGO secure rr A EA 24 Frontranel DEL sara rana Ian ac 25 Example Usage C coimas 26 Example Usage Matlab sici n parana pad 27 Metta APIS t neremrea enant eh ee btn ai aE E oi a cantidad 28 DLL Meader Fleur ada dadas 28 SUPPO SAUS O eee 28 ADLE Modules costs add rr i n ea 29 Building FPGA Projects with FrontPanel HDL Modules 29 XEMSOOTVIT NOIE e toi E ra it aio 30 FPGA Resource Requirements oooccoocooocco eee eens 31 The NOSIMO IE tc di on 31 OKHOStIMterface civic aaa ae
32. UpdateWirelns Updates all wire in values to FPGA simultaneously with the values held internally to the API UpdateWireOuts Simultaneously retrieves all wire out values from FPGA and stores the values internally UpdateTriggerOuts Retrieves all trigger out values from FPGA and records which end points have triggered since the last query SetWirelnValue Sets a wire in endpoint value Requires a subsequent call to Up dateWirelns GetWireOutValue Retrieves a wire out endpoint value Requires a previous call to UpdateWireOuts since a previous call to UpdateTriggerOuts Writes data byte array to a pipe in Reads data byte array from a pipe out WriteToBlockPipeln Writes data to a block throttled pipe in ReadFromBlockPipeOut Reads data from a block throttled pipe out Communicating with Multiple Devices In most cases your software will communicate with a single device attached to the USB How ever some applications require simultaneous communication with two or more devices Multiple device communication is fully supported by the driver and API but will require special consider ation when initializing the communication Querying Attached Devices You can call the method GetDeviceCount to determine the number of supported devices at tached to the bus before opening a specific a specific device The GetDeviceCount method also queries the device serial numbers board types and device ID strings of all the attached dev
33. a number spanning more than 256 would map to multiple endpoints Endpoints In FrontPanel an endpoint is either a Wire Trigger or Pipe and is either directed in or out of your design By way of definition the endpoint will always be labelled from the perspective of the device FPGA so an In endpoint moves data into the design while an Out endpoint moves data out of the design All of the endpoints in a design are instantiated from Opal Kelly modules and share a common connection to the Host Interface which provides the connection to the PC through the USB interface on the XEM board www opalkelly com 11 FrontPanel User s Manual The figure below shows the block diagram of an example FPGA design The okHostInterface is instantiated once and connects to the external FPGA pins as well as a bus shared by all endpoint HDL modules This bus provides the communications channel for the endpoints to and from the Host Interface okHostInterface Configuration okWireln 0x06 okWireln 0x07 okTriggerln 0x52 okWireOut 0x23 Status Information okWireOut 0x24 State Machine Done Load Data State Machine Start okTriggerOut 0x60 okPipeln 0x80 Each instance of an endpoint has an associated address shown in parentheses so it may be accessed independent of other endpoints In this example two Wire In endpoints setup the configuration for the design and two Wire Out endpoints re
34. ads on the target side occur at the host s whim Therefore data must be provided whenever EP_READ is asserted This simple implementation of a Pipe Out endpoint requires that the target interface be somewhat responsive to host read requests If the target is able to keep up with the throughput but needs to handle data in a block fashion coupling the okPipeOut with a FIFO from the Xilinx CORE generator is a good solution Alternatively an okBTPipeOut can be used The timing diagram below indicates how the user HDL needs to respond to EP_READ with EP_DATAIN valid data When EP_READ is asserted for the rising edge of TI_CLK user HDL must respond with valid EP_DATAIN on the next clock edge subject to setup and hold times ap propriate for T and T in the Spartan 3 CLB timing documentation Of course these times are also subject to the particular routing and logic in your HDL implementation Note that the transfer sends 4 words in this example Although contrived it is important to note that EP_READ may deassert during the transfer This will generally happen with longer transfers gt 256 words www opalkelly com 35 FrontPanel User s Manual 1 2 3 4 5 6 7 8 9 10 11 TLCLK PASTA L EP_READ K EP_DATAIN gt AAA Signal Direction Description EP_ADDRI7 0 Endpoint address EP_DATAIN 15 0 Pipe data input EP_READ Output Active high read signal Data mus
35. ator www opalkelly com 69 FrontPanel User s Manual 70 Tu wave default DER File Edit view Insert Format Tools Window SHS BA rA aaa k E FrontPanel Control Simulation E FIRST_ZTESTIM E FIRST_TEST 12 Er FIRST_TEST exp E FIRST_ZTEST sum First _____ E FIRST_TEST dut ep01 wire E FIRST_TEST dut ep02wire E FIRST_TEST dut ep21 wire First UpdateWirelns take effect First UpdatewWireDuts take effect Second UpdateWirelns take effect al 0 ps to 8473500 ps Now 8 070 ns Delta 3 Analyzing the Results The important simulus from First_tf v comes from the following Verilog statements for k 0 k lt 5 k k 1 begin Set the two ADDER inputs to random 16 bit values rl random 65536 r2 random 65536 exp rl r2 SetwireIns 8 h01 r1 16 hffff FRONTPANEL API SetwireIns 8 h02 r2 16 hfffFf FRONTPANEL API UpdatewireIns FRONTPANEL API The ADDER result will be ready UpdatewireOuts to get it Updatewire0uts FRONTPANEL API sum Getwire0utvalue 8 h21 FRONTPANEL API if exp sum display SUCCESS Expected 0x 04h Received 0x 04h exp sum else display FAILURE Expected 0x 04h Received 0x 04h exp sum This code is iterated 5 times to simulate 5 different Wireln inputs Each time two random 16 bit numbers are generated and sent as Wireln 0x01 and Wireln
36. be data that can be ma nipulated by any XML supporting editor and in a platform agnostic way At its core XML is just a text file containing tags which correspond to nodes of a tree Each node can have properties and values FrontPanel interfaces are described using XML tags so they can be read and written with any standard text editor This means that adding components to your virtual I O board is as easy as adding a few lines to a text file It also means that as FrontPanel grows in its capabilities the interface descriptions will be forward and backward compatible As additional functionality is added to FrontPanel you will be able to take advantage of it by simply adding to your current projects HDL Endpoints On the FPGA side of the interface Endpoints are used to connect FrontPanel components to signals in your design These endpoints work just like any external pin You simply connect the signals you want to control or observe to the endpoint ports Then connect the endpoint mod ules to a shared bus and place a Host Interface module on that same shared bus The Host In terface along with FrontPanel software and drivers take care of the rest Signals within the FPGA are immediately visible within FrontPanel and FrontPanel can now control any input endpoints you ve connected Additional endpoints can be added at any time simply by instantiating additional endpoint mod ules The modules are designed to consume very littl
37. ble outputs to FrontPanel To reduce the number of endpoints we have chosen to share them among the counters Wire In 0x00 The only Wire In endpoint is used to carry the RESET1 DISABLE1 and AUTOCOUNT2 signals These are wires because we want them to have a static state rather than one shot signals Signal Bit s Description RESET1 En When asserted Counter 1 holds the value 0x00 and does not count DISABLE1 When asserted Counter 2 holds its value and does not count AUTOCOUNT2 Configures counter 2 to autocount fUnsed tS S S Trigger In 0x40 The only Trigger In endpoint is used for the Counter 2 inputs These are triggers because we want single events one shots to occur such as a count up event Note that RESET2 behaves the same as RESET1 but we want to have RESET2 behave as a one shot event so that the user cannot hold RESET2 asserted Therefore we attach this one to a Trigger Signal Bitfe Description Y PRESET o When asserted Counter 2 resets to 0x00 and does not count fonsed Pisa Wire Out 0x20 0x21 and 0x22 These wires provide observables for FrontPanel They are connected as follows Endpoint Signal Description_ 22222 Wire Out 0x20 COUNT1 7 0 Counter 1 value Wire Out 0x21 COUNT2 7 0 Counter 2 value Wire Out 0x22 BUTTON 3 0 The lower four bits of this wire bundle contain the status of the on board pushbuttons If a button is pressed the corresponding wire will
38. checks for a valid EP_READY signal and PostReadyDelay simulates a delay after EP_READY is asserted before the next block of data is piped An example setup for these requirements is shown here parameter BlockDelayStates 5 REQUIRED of clocks between blocks of pipe data parameter ReadyCheckDelay 5 REQUIRED of clocks before block transfer before host interface checks for ready 0 255 parameter PostReadyDelay 5 REQUIRED of clocks after ready is asserted and check that the block transfer begins 0 255 A parameter pipeInsize 16383 REQUIRED byte must be even length of default PipeIn Integer 0 2A32 parameter pipeOutSize 16383 REQUIRED byte must be even length of default PipeOut Integer 0 2A32 reg 7 0 pipeIn 0 pipeInsize 1 reg 7 0 pipeout 0 pipeoutsize 1 After a call to ReadFromPipeOut or ReadFromBlockPipeOut the received data will be in the byte wide register array pipeOut arranged as it would be after a call to the C method Simi larly before a call to WriteToPipeln or WriteToBlockPipetn the transmitted data should be setup in the byte wide register array pipeIn More pipe data arrays may be added as needed by copying and modifying the default pipe functions Simulation in Aldec ActiveHDL The process of setting up the simulation test fixture and calling host interface functions is identi cal for ActiveHDL The only differences are limited to the configuration of the tool
39. crocontroller This is the entry point for FrontPanel into your design The endpoints connect to a shared control bus on the host interface This internal bus is used to shuttle the endpoint connections to and from the host interface Several endpoints may be connected to this shared bus FrontPanel uses endpoint addresses to select which endpoint it is communicating with so each endpoint must have its own unique address to work properly Building FPGA Projects with FrontPanel HDL Modules The FrontPanel HDL Modules are provided as pre synthesized files which get included in your design flow The following table lists these files and describes it s content By default these files are installed at C Program Files Opal Kelly FrontPanel FrontPanelHDL In this directory are several subdirectories that contain HDL modules built for different Xilinx ISE versions If you are using an XEM3001v1 8 bit board choose a v1 directory Otherwise choose a v2 directory www opalkelly com 29 FrontPanel User s Manual Filename Description OOOO okTriggerOut ngc Pre synthesized Xilinx module for the Trigger Out endpoint okPipeln ngc Pre synthesized Xilinx module for the Pipe In endpoint okPipeOut ngc Pre synthesized Xilinx module for the Pipe Out endpoint okBTPipeln ngc Pre synthesized Xilinx module for the Block Throttled Pipe In endpoint okBTPipeOut ngc Pre synthesized Xilinx module for the Block Throttled Pipe Out endpoint T
40. d the PLL settings required to generate that output If more than one frequency is required for the FPGA remember that the PLL only has a single VCO so the outputs must be generated from a single source and possibly multiple divider values Output vco DIV1N Frequency Frequency 100 MHz 400 MHz DIV1CLK DIV1N 80 MHz 240 MHz DIV1CLK 3 e666 Mine 400 as a00wriz fe DIVICLK DIVIN sowie 400 48 200 whiz fs DIVICLK DIVIN Of course many other configurations are possible including those with multiple output frequen cies Please see the specific PLL datasheet for more information PLL Configuration CY22393 The XEM3010 product includes a Cypress CY22393 PLL which has a multi PLL configuration and is therefore more capable than the CY22150 Configuration for the Cypress CY22393 is also available through the FrontPanel API and the FrontPanel Application Please refer to the Cy press datasheet for parameter details on the CY22393 44 www opalkelly com FrontPanel User s Manual Loading a FrontPanel Profile A FrontPanel Profile is an XML file with the extension XFP A new profile may be loaded at any time but only one profile is available at any time That is the previous profile is unloaded before loading in the new one You can load a new profile by clicking on the button shown at the left A file selector dialog will open asking you to select a profile E Opal Kelly FrontPanel When a selection is confi
41. dware but it is not suitable for all applications particularly those which require further data processing on the PC side of the interface or when data transfer between the PC and FPGA is required In these cases a custom software application is usually a better fit To this end Opal Kelly provides the FrontPanel Application Programmer s Interface API a cross platform interface to the underlying USB driver layer The FrontPanel API contains methods which communicate via the USB to the microcontroller on the XEM but the methods have been specifically designed to interface with FPGA hardware in a manner which is consistent with most hardware designs The API provides methods to interface directly with the FrontPanel HDL modules such as wires triggers and pipes Because of this abstraction some flexibility in the USB interface is sacrificed for a dramatically reduced develop ment cycle and learning curve for connecting your FPGA hardware to your custom software The library is written in C and is provided as a dynamically linked ibrary However Python and Java versions of the API are also available and can make FPGA development even faster A de tailed API reference is available in HTML format or Compiled HTML under Windows Because the Python and Java APIs are generated automatically from the C API most of the methods are identical and you can use the same API reference for all languages This section of the manual provides a higher
42. e FPGA resources so the effect on your design is minimal www opalkelly com 9 FrontPanel User s Manual 10 www opalkelly com FrontPanel User s Manual Designing with FrontPanel FrontPanel s main purpose is to move data between your PC and your FPGA in order to pro vide a convenient and effective way for you to work with the design FrontPanel was designed to interface simply and easily with new and existing FPGA designs in a way which is powerful enough to apply to a large number of interface methods yet simple enough to apply to a design in minutes More importantly FrontPanel attempts to make the specific implementation of the physical interface that is the USB interface disappear so that those details don t get in the way of your work FrontPanel introduces the concept of endpoints to your FPGA design An endpoint is a bundle of interconnect internal to your design that transports data to or from the PC in some fashion In many cases the endpoint can be created from an existing signal in your design which you want to observe in FrontPanel In other cases you will create an endpoint to perform a specific data transfer Components are the corresponding PC side interface to an endpoint in the FPGA Compo nents may correspond to a single bit on an endpoint or to several endpoints For example an okTriggerButton activates a single bit on a Trigger In endpoint In contrast a field that allows you to enter or display
43. eEmpty ep_status pipeStatus okBufferedPipe0ut pipe0utA3 ok1 ok1 ok2 ok2 ep_clk clk2 ep_addr 8 ha3 ep_datain pipeData ep_write pipewrite ep_full pipeFull ep_empty pipeEmpty ep_status pipeStatus pipeoutA3 okBufferedPipeIn port map okl gt okl ok2 gt ok2 ep_addr gt x 9c ep_clk gt clk2 ep_dataout gt pipeData ep_read gt pipeRead ep_full gt pipeFull ep_empty gt pipeEmpty ep_status gt pipeStatus okHostinterface Signal Direction Description HI_IN 7 0 Input Host interface inputs HI_OUT 1 0 Output Host interface outputs HI_INOUT 15 0 In Out Bidirectional host interface signals TI_CLK Output Buffered host interface clock signal OK1 30 0 Out Control signals to endpoint modules OK2 16 0 In Control signals from endpoint modules ti_clk ticlk okHostInterface hostIF hi_in hi_in hi_out hi_out hi_inout hi_inout ok1 0k1 ok2 0k2 hostIF okHostInterface port map hi_in gt hi_in hi_out gt hi_out hi_inout gt hi_inout ti_clk gt ticlk okl gt ok1 ok2 gt ok2 pipeouta3 okBufferedPipeOut port map okl gt okl ok2 gt ok2 ep_addr gt x A3 ep_clk gt clk2 ep_datain gt pipeData ep_write gt pipewrite ep_full gt pipeFull ep_empty gt pipeEmpty ep_status gt pipeStatus okPushbutton lt object class okPushbutton gt lt label gt Disable lt
44. es and so on These devices are not synchronous to the design and they usu ally convey the current state of some internal signal in the case of Wire Outs Wires are updated periodically using a polling mechanism The rate of update is determined by how fast the PC can poll the FPGA In FrontPanel this value is user configurable Even at the highest update rate 25 millisecond period very little USB bandwidth is consumed so you should not notice any performance penalty Because some FrontPanel components may convey the state of several wires and in order to avoid multiple transfers over the USB all wires are captured and updated simultaneously That is not to say they are synchronous but that they are all updated at the same time Therefore all 64 Wire Ins or Wire Outs are transferred together Triggers Pipes Triggers are synchronous connections between the PC and an HDL endpoint A Trigger In is an input to the target A Trigger Out is an output from the target Triggers are used to initiate or signal a single event such as the start or end of a state machine As an input to the HDL a Trigger In creates a signal that is asserted for a single clock cycle The synchronization clock is determined by the user and the HDL module takes care of crossing the clock domains properly As an output from the HDL a Trigger Out triggers the PC when a signal s rising edge is detected The rising edge is actually determined by the signa
45. f The parameter source is a string that represents the asi source for the output outputs ref Use the reference 48 MHz div1byn Use divider 1 source divided by divider 1 N div1by2 Use divider 1 source divided by 2 div1by3 Use divider 1 source divided by 3 div2byn Use divider 2 source divided by divider 2 N div2by2 Use divider 2 source divided by 2 div2by4 Use divider 2 source divided by 4 XML Example lt object class okPLL22150 gt lt label gt PLL1 Configuration lt label gt lt position gt 170 5 lt position gt lt size gt 100 15 lt size gt lt p gt 400 lt p gt lt q gt 48 gt lt q gt lt dividerl source vco gt 8 lt dividerl gt lt outputO source divibyn gt on lt output0 gt lt object gt okPLL22393 This component provides an XML method to program the on board PLL When provided with a label parameter this component becomes a pushbutton on the panel GUI When that button is pressed the PLL is configured with the given parameters This allows you to specify multiple PLL configuration and provide multiple buttons to access them without going through the PLL dialog A convenient tooltip lists the VCO and output frequencies for the configuration When the component does not have the label parameter this configuration is loaded to the PLL when the profile is loaded Itis not stored to EEPROM and the component does not crea
46. ffered pipe and user design to assure that FIFO overruns and underruns do not occur This would typically be done with wires or triggers to indicate to the host when data is available from the FIFO The FIFO used in this module is based on the Xilinx asynchronous FIFO presented in XAPP131 It has been slightly modified to accommodate the larger BRAM size of the Spartan 3 Please refer to the original application note for detailed FIFO usage and timing information Signa Deetion Description OOOO U EP_WRITE Input When asserted writes the data on EP_DATAIN to the FIFO and advances the write pointer to the next datum EP_DATAIN 15 0 Pipe data input EP_FULL Output Asserted when the endpoint FIFO is full EP_EMPTY Output Asserted when the endpoint FIFO is empty EP_STATUST 3 0 Output Indicates the fullness of the FIFO in 16 levels 1 16 full 1 8 full and so on Verilog Instantiation okBufferedPipeOut pipe0uta9 ok1 ok1 ok2 Cok2 ep_addr 8 ha9 ep_clk clk2 ep_reset reset ep_write pipewrite ep_datain pipeData ep_full pipeFull ep_empty pipeEmpty ep_status pipestatus VHDL Instantiation pipeouta9 okBufferedPipeOut port map ok1 gt ok1 ok2 gt ok2 ep_addr gt x a9 ep_clk gt clk2 ep_reset gt reset ep_write gt pipewrite ep_datain gt pipeData ep_full gt pipeFull ep_empty gt pipeEmpty ep_status gt pipeStatus www opalkelly com 39 FrontPanel U
47. fore meth ods have been provided in the DLL for creating and destroying the objects such as okCPLL22150 and okCUsbFrontPanel An object must be created before its methods can be called An object should also be destructed when you are done using it OkUSBFRONTPANEL_HANDLE xem xem okUsbFrontPanel_Construct Use the xem object okUsbFrontPanel_Destruct xem Calling Methods Each DLL method that acts on an object has an additional required argument that indicates which object is being acted upon In C this additional argument is implied by the object oriented nature of the language In the DLL this argument must be explicitly provided C Wrapper Also included in the okFrontPanel cpp file is a C wrapper for the DLL This provides a full C object class so that you do not have to call the C style DLL methods from your C applica tion Most of the samples are written using this C wrapper www opalkelly com FrontPanel User s Manual OKUSBFRONTPANEL_HANDLE xem okPLL22150_HANDLE pll Construct XEM and PLL objects xem okUsbFrontPanel_Construct pll okPLL22150_ConstructQ Setup the PLL okPLL22150_SetvcoParameters p11 400 48 okPLL22150_setDiv1 p11 DivSrc_vco 8 okPLL22150_SetoutputSource p11 0 ClkSrc_Div1ByN okPLL22150_setoutputEnable p11 O true Configure the XEM PLL okUsbFrontPanel_OpenBySerial xem NULL okUsbFrontPanel_SetPLLConfiguration xem p11 Fin
48. he Host Interface is actually broken into two components a core component which is pre synthesized and a wrapper component in okLibrary v or okLibrary vhd which includes the core component as well as IOBs required for the connections to FPGA pins When you start a new design you should copy okLibary v or okLibrary vhd into the directory with your other sources and add them to your project This file will be synthesized just like your other modules except that the HDL is mostly just a placeholder for the modules that have been pre synthesized When properly added to a project Project Navigator will list the source follows similar to what is shown below Sources in Project E Counters 9 xc3s200 4pq208 Y Counters Source Counters v 4 ASource Counters ucf Y okEndpoint Triggerln Wilimd ok Library v Y okEndpoint TriggerOut 1 WXilimc wok Library v Y okEndpointWireln Xilinx ok Library v Y okEndpointWireOut Xiliroe ok Library v Y okHostinterface Xilinx ok Library v Y okHostinterfaceCore Xilira okLibrary v j Eg Module View ta Snapshot View A Library View You should also copy the pre synthesized files ngc that you use into your project directory You won t need to copy module files that you are not using The ngc files will then be used by the Xilinx tools during the Translate step in order to completely build the FPGA configuration file XEM3001
49. he host interface model VHDL For VHDL simulation a corresponding okHostCalls is not necessary Instead these routines are actually included in dut tf vhd Note that dut _ tf vhd is significantly longer than dut tf v Reset In a live FPGA design the FPGA automatically performs a reset of all logic within the fabric after configuration This assures that the entire design start in a known state which is established by the design In a simulation environment this reset signal is not always simulated and some signals may start in an unknown state The FrontPanelReset call will reset the host interface functions and as sure that the simulation starts off in a known state It is therefore recommended that your simula tion issue a call Reset at the beginning of the simulation Simulating Pipes Pipe transfer calls utilize global array variables in the test fixture to store the data that will be transmitted or received These global variables must be declared within the user s testbench if www opalkelly com 67 FrontPanel User s Manual any pipe functionality is to be simulated In addition the three parameters BlockDelayStates ReadyCheckDelay and PostReadyDelay determine how many clock periods exist between various pipe functions to help simulate possible delays that may occur in actual hardware BlockDelayStates adds delay between transfers of blocks of data ReadyCheckDelay simulates a lag in clocks before a Block Pipe module
50. her trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed Revision History 20040901 20040920 20041114 20041201 20050131 20050223 20050305 20050313 20050328 20050423 20050507 20050613 20050620 20050927 20060703 20060822 20060913 20061230 20070126 Contents An Introduction to FrontPanel 0000 cee eee 7 Te MINO Yuca cio las dada T Basic Functionally isere iio eE RARD 8 Peripheral Configuration 06 654 40s00008s noc a ee eee 8 Flexibility Outside the Design k occpooncrrocoron dee ebad wees ees 8 ContolablYiss didas ores Sowers SE ET 8 OBSADY si 0ccncecinrearracaain rev rre 9 XML and FrontPanel Components 20 20 0c e ee eee eee 9 HOLEndpomts ss cnassd ctagnees haan note ais 9 Designing with FrontPanel occ ccroouodorotr e 11 AA A 11 WV INES a asias dede aia ii iia 12 WMHIdEiS oiga o to 13 PIPES 3 000 dra tod a 13 Block Throttled PIPES cocine ds ia i 14 COMPONEGIS vinagre ca ora ad ara 14 Penenmance Notes lo arribado di 14 Wires and Triggers eo cia e dede 14 Pipes Bulk TransfefS sssi crerrersirirs ke tnni Esan n nin aE 15 Block Throttled Pipes Bulk Transfers nananana anaa 16 isochronous INANSICNS arca A die woke koe 16 Application Programmer s Interface ooooooooo 17 A A A 17 OTGANIZAON cciccoicberrerecne IA AA AAA 18 The okCUsbFrontPanel ClaSS usos dana cria 18 U
51. herefore it is often the case that simple operations like moving a window dramati cally reduce transfer bandwidth This should be a consideration when designing the buffering for any bandwidth dependent application NOTE Pipes in FrontPanel 3 are actually a subset of Block Throttled Pipes where the EP _ READY signal is always asserted thus disabling any throttling Also block sizes are always 1024 bytes except for the last block which may be smaller to account for the total length of the transfer Block sizes are 64 bytes when the device is enumerated at full speed Measured Performance 1 0 MB 36 5 MB s 36 7 MB s 4 0 MB 37 9MB s 37 9MB s 8 0 MB 38 2 MB s 38 1 MB s 64 0 kB 20 8 MB s 23 2 MB s 256 kB 31 8 MB s 32 7 MB s www opalkelly com 15 FrontPanel User s Manual 16 Block Throttled Pipes Bulk Transfers Block Throttled Pipes are available only in FrontPanel 3 They provide equivalent performance to the standard pipe except that the FPGA can throttle the data transfer at the block level The block is programmable by the user with highest performance achieved at the largest 1 024 byte block size BTPipes are an excellent way to achieve high performance with smaller buffer sizes because the FPGA can negotiate the transfer at a low level without incurring the significant overhead of set ting up a new transfer for each small buffer block Measured Performance All measurements taken with a 8 MB transfer length 6
52. ia E DO D1 D2 Dn 2 Dn 1 Signal Direction Description EP_ADDR 7 0 Endpoint address EP_DATAIN 15 0 Pipe data input EP_READ Output Active high read signal Data must be provided in the cycle following as assertion of this signal EP_BLOCKSTROBE Output Active high block strobe This is asserted for one cycle just before a block of data is read EP_READY Input Active high ready signal Logic should assert this sig nal when it is prepared to transmit a full block of data Verilog Instantiation okBTPipeOut pipe0utA3 ok1C ok1 ok2 ok2 ep_addr 8 ha3 ep_datain epA3pipe ep_read epA3read ep_blockstrobe epa3strobe ep_ready epA3ready VHDL Instantiation pipeOutA3 okBTPipeOut port map ok1 gt okl ok2 gt ok2 ep_addr gt x a3 ep_datain gt epA3pipe ep_read gt epA3read ep_blockstrobe gt epA3strobe ep_ready gt epA3ready www opalkelly com 37 FrontPanel User s Manual 38 okBufferedPipeln DEPRECATION NOTICE The okBufferedPipeln has been deprecated in FrontPanel 3 Now that Xilinx includes the FIFO Core Generator with ISE WebPack for free the okBufferedPipes are no longer required to fill the void In all cases an okPipe coupled to a FIFO Core is the preferred choice The okBufferedPipeln is a special implementation of a Pipe In which includes a FIFO to simplify dataflow between the target and host The FIFO is implemented as a 2047 word 2047 byte for XEM30
53. ices This information can then be accessed by calling the methods GetDeviceListSerial GetDeviceListModel and GetDeviceListID respectively Connecting to a Specific Device It is expected that you would identify a specific board using the serial number factory assigned and not user mutable or using the device ID string user configurable via FrontPanel A typical process for openening multiple devices would then be 1 Create two instances call them x and y of the okCUsbFrontPanel 2 Call x GetDeviceCount to verify that two boards are connected and to query the serial numbers and other device information 20 www opalkelly com FrontPanel User s Manual 3 Call serX x GetDeviceListSerial 0 to get the first device s serial number 4 Call serY x GetDeviceListSerial 1 to get the second device s serial number 5 Call x OpenBySerial serX to open the first device 6 Call y OpenBySerial serY to open the second device Using this procedure you would then have two instances which point to the two devices in your system They have also been clearly associated with the specific hardware you specified so there is no ambiguity API Communication The three endpoint types Wire Trigger Pipe provide a means by which the PC and FPGA communicate Each type is suited to a specific type of data transfer and has its own associated usage and rules Wires Recall that a wire is used to communicate asynchronous signal state bet
54. id clock is available when the FPGA comes out of the configuration state Sometimes however you may want to keep the current PLL set tings in effect and not update the EEPROM www opalkelly com 45 FrontPanel User s Manual Show Panels in Taskbar When unchecked each FrontPanel panel is displayed in a toolbox window which does not reg ister with the taskbar When checked these panels will register with the taskbar so that you can easily select a particular panel Enable Asynchronous Transfers Asynchronous transfers allow USB transfer requests to be queued and sequenced by the oper ating system This decreases software overhead and increases overall throughput However many Windows 2000 based machines have problems with asynchronous transfers and may not communicate with the FPGA properly when this feature is enabled You may find that you need to disable asynchronous transfers before any FPGA communication Otherwise the communication link may become tainted and will not work Therefore if you experience problems with Windows 2000 and FrontPanel communication we advise that you dis able asynchronous transfers before communicating with your board From within your own software there is an API method to control this feature 46 www opalkelly com XML FrontPanel User s Manual Component XML FrontPanel user interfaces panels are constructed from components graphical devices that interface to y
55. ignal the host with a one shot or other single event indicator Triggers are read and updated in a manner similar to Wires All Trigger Ins are transferred to the FPGA at the same time and all Trigger Outs are transferred from the FPGA at the same time However due to common usage differences Trigger Ins are not transferred immediately with the call to ActivateTriggerln Trigger Out information is read from the FPGA using the call UpdateTriggerOuts Subsequent calls to IsTriggered then return true if the trigger has been activated since the last call to Upda teTriggerOuts www opalkelly com 21 FrontPanel User s Manual Pipes Pipe communication is the synchronous communication of one or more bytes of data In both Pipe In and Pipe Out cases the host is the master Therefore the FPGA must be able to accept or provide data on any time Wires Triggers and Buffered Pipes can make things a little more negotiable When data is written by the host to a Pipe In endpoint using WriteToPipeln the USB driver will packetize the data as necessary for the USB protocol Once the transfer has started it will continue to completion so the FPGA must be prepared to accept all of the data When data is read by the host from a Pipe Out endpoint using ReadFromPipeOut the USB driver will again packetize the data as necessary The transfer will proceed from start to comple tion so the FPGA must be prepared to provide da
56. ire In component and behaves much like the okToggleButton except that graphically it appears as a checkbox with the label text on the right When un checked the corresponding wire is unasserted logic 0 When checked the corresponding wire is asserted logic 1 Element Type Description o POSITION Position of the top left corner Size in pixels If no size is specified the component is automatically sized CI Tet AI BR NOWGER ett which tis component addresses 085 T5 M5E www opalkelly com 51 FrontPanel User s Manual XML Example lt object class okTogglecheck gt lt label gt Autocount lt label gt lt position gt 20 135 lt position gt lt endpoint gt 0x00 lt endpoint gt lt bit gt 2 lt bit gt lt tooltip gt Enable autocount lt tooltip gt lt object gt okDigitEntry Wire In This component allows a more flexible way to convey numerical information to your design The okDigitEntry attaches to one or more Wire In endpoints and allows the user to enter a numeri cal value using the mouse and or keyboard The bounds on the value are set in the component properties The okDigitEntry component is designed to allow fast entry through either the mouse or key board Using the mouse you can hover over any digit and change its value using the scrollwheel Likewise by pressing a number on the keyboard when a digit is highlighted that particular digit is changed and the highlight moves to
57. ished with the PLL okPLL22150_Destruct p11 Use the xem object okUsbFrontPanel_Destruct xem Example Usage Matlab Matlab provides a convenient way to extend its own capabilities by calling user provided DLL functions This is done using a few native Matlab calls loadlibrary calllib libisloaded libfunc tions libfunctionsview For example to load the FrontPanel DLL into Matlab for use the following syntax can be used if libisloaded okFrontPanel loadlibrary okFrontPanel okFrontPanelDLL h end You can view the calling conventions and conversions Matlab has applied to the DLL methods by calling the command libfunctionsview okFrontPanel An example way to call the DLL Create a device structure xid ptr 0 xid serial xid deviceID xid major 0 xid minor 0 Construct an XEM3001v2 and open the first device xid ptr calllibC okFrontPanel okUsbxXEM3001v2_Construct ret x calllib okFrontPanel okUsbFrontPanel_Open xid ptr 0 xid major x calllibC okFrontPanel okusbFrontPanel_GetDeviceMajorversion xid ptr xid minor x calllib okFrontPanel okUsbFrontPanel_GetDeviceMinorversion xid ptr Do xid serial calllib okFrontPanel okUsbFrontPanel_GetSerialNumber xid ptr Eo xid deviceID calllibC okFrontPanel okUsbFrontPanel_GetDeviceID xid ptr p www opal
58. ith an attribute which defines what type of component it is Case Sensitivity All XML component types and value names are currently case sensitive That is okPushButton is not a valid component name but okPushbutton is 48 www opalkelly com FrontPanel User s Manual Element Data Types All FrontPanel components have sub elements which specify certain properties of the compo nent These sub elements are listed with each component and take a certain data type as their value The various data types available along with an example and description are shown in the table below Type Example Description Cd POSITION 50 75 Position represented as x y in pixels SIZE 40 80 Size represented as width height in pixels Many controls will accept 1 as a width and or height and automatically compute the best value TEXT Hello World A text string No quotes are necessary HEX BYTE An 8 bit hexadecimal number The leading Ox is required NUMBER Numeral range is determined by object type COLOR 2040A3 24 bit hexadecimal HTML color format RRGGBB The STYLE type is object dependent and contains one or more styles which can be or ed together using the pipe symbol Component Types The following figure shows most of the FrontPanel components available Some components do not have a corresponding GUI representation This image is taken from the Controls Sample okLED okTriggerB
59. iven configuration xxx is either 22150 or 22393 GetEepromPLLxxxConfiguration Retrieves the PLL configuration stored in the on board EE PROM xxx is either 22150 or 22393 SetEepromPLLxxxConfiguration Programs the on board EEPROM with a PLL configuration for later retrieval xxx is either 22150 or 22393 ConfigureFPGA Downloads a Xilinx configuration bitfile to the FPGA ConfigureFPGAFromMemory Similar to above but with the configuration file contents in memory FPGA Communication Once the FPGA has been configured communication between the application and the FPGA hardware is done through these methods The FPGA is connected directly to the USB microcontroller on the XEM These methods communicate through that connection and require that an instance of the HDL module okHostinterface be installed in the FPGA configuration A brief description of the API methods is in the table below The way the API and FrontPanel HDL modules communicate is described in more detail later www opalkelly com 19 FrontPanel User s Manual Method Description 222222222222 IsFrontPanelEnabled Checks to see that an instance of the okHostInterface is installed in the FPGA configuration IsFrontPanel3Supported Returns true if the firmware on the device supports FrontPanel 3 ResetFPGA Sends a reset signal through the host interface This is used to reset the host interface or any endpoints It can also be used to reset user hardware
60. just before a block of data is written EP_READY Input Active high ready signal Logic should assert this sig nal when it is prepared to receive a full block of data 36 www opalkelly com FrontPanel User s Manual Verilog Instantiation OkBTPipeIn pipeIn9C ok1 ok1 ok2 ok2 ep_addr 8 h9c ep_dataout ep9Cpipe ep_write ep9Cwrite ep_blockstrobe ep9cstrobe ep_ready ep9cready VHDL Instantiation pipeIn9c okBTPipeIn port map ok1 gt ok1 ok2 gt ok2 ep_addr gt x 9c ep_dataout gt ep9Cpipe ep_write gt ep9cwrite ep_blockstrobe gt ep9Cstrobe ep_ready gt ep9cready okBTPipeOut The Block Throttled Pipe Out module is similar to the okPipeOut module but adds two signals EP_BLOCKSTROBE and EP_READY to handle block level negotiation for data transfer The host is still master but the FPGA controls EP_READY When EP_READY is asserted the host is free to read a full block of data When EP_READY is deasserted the host will not read from the module EP_READY could for example be tied to a level indicator on a FIFO When the FIFO has a full block of data available it will assert EP_READY signifying that a full block may be read from the FIFO 1 2 3 4 5 6 7 8 9 10 11 12 13 TLOLK r LS EP_READY Beet eee eeS EEL eREEeEe EP_BLOCKSTROBE N iN P N Tclk gt EP_READ YA EP_DATAIN pra
61. k1 wire 16 0 ok2 Endpoint connections wire 15 0 ep00wire wire 15 0 ep20wire assign led assign ep20wire ep00wire 12 b0000 button Instantiate the okHostInterface and connect endpoints to the target interface okHostInterface okHI hi_inChi_in hi_out hi_out hi_inoutC hi_inout ti_clk ti_clk ok1Cok1 ok2 0k2 okwireIn ep00 0k1 ok1 ok2 ok2 ep_addr 8 h00 ep_dataout ep00wire okwireOut ep20 0k1 ok1 ok2 ok2 ep_addr 8 h20 ep_datain ep20wire endmodule Listed inside the module definition are several wires Most of these are for the FrontPanel host interface The two other busses LED 7 0 and BUTTON 3 0 connect to the LEDs and pushbut tons on the XEM3001 Their specific pin locations are constrained in First ucf Target Logic The logic description for this example is very simple and only consists of two lines of HDL con necting the Wire In endpoint to the physical LEDs and the Wire Out endpoint to the physical pushbuttons assign led epOOwire assign ep20wire 12 b0000 button The LEDs are attached to endpoint 0x00 and the pushbuttons are attached to endpoint 0x20 www opalkelly com FrontPanel User s Manual FrontPanel Interface Modules This design contains three FrontPanel interface modules okHostInterface okWireln and okWir eOut Their instantiation is pretty straightforward We have chosen to call the endpoint wires ep
62. kelly com 21 FrontPanel User s Manual Matlab API While the above example shows how to use the FrontPanel DLL from within Matlab we have al ready provided a more thorough version of this API for your usage It is provided as a fully func tioning sample of the DLL usage from within Matlab and utilizes Matlab s object oriented structure to provide an API that is very similar to the C API in usage DLL Header File Due to a bug in Matlab s DLL usage a slightly modified DLL header file must be used when accessing the API through Matlab This revised header defines the HANDLE objects as unsigned long rather than void If the revised header file is not used memory leaks will occur in Matlab Support Status Please note that the Matlab API is not officially supported by Opal Kelly While it is not officially supported we would like to keep it up to date Please contact us via email if you have any sug gested changes to the Matlab API 28 www opalkelly com FrontPanel User s Manual HDL Modules The use of FrontPanel components to control and observe pieces of your FPGA design requires the instantiation of one or more modules in your toplevel HDL These modules can quickly and easily be added into an existing or new design and take care of all the dirty work of communicat ing with the FrontPanel software The host interface is the block which connects directly to pins on the FPGA which are connected on the XEM board to the USB mi
63. l s state from one clock cycle to the next and does not detect glitches It should be noted that because FrontPanel polls the FPGA periodically it can only detect independent trigger outs between polls That is once a Trigger Out is set it remains set until the next poll clears it Pipes are synchronous connections between FrontPanel and an HDL endpoint Unlike Triggers which convey a single event however Pipes are designed to transmit a series of bytes to or from the endpoint They are most commonly used to download or upload memory contents but may also be used to stream data to or from the device From the HDL point of view a Pipe is always a master That is the PC and therefore the HDL module that implements the Pipe controls the transaction for both Pipe Ins and Pipe Outs In addition the Pipe transactions must be performed at the endpoint s clock rate 48 MHz To suc cessfully cross this clock boundary a buffered FIFO arrangement is suggested okBuffered Pipes provide built in asynchronous FIFOs Although access to the Pipe is always from a slave point of view use of Triggers provides an ef fective negotiation method to synchronize the transfer of blocks of data Pipe transfer rates will vary depending on host hardware Our tests indicate transfer rates to the FPGA are around 39 MB s and transfer rates from the FPGA are about 39 MB s For more detail see Performance Notes below FrontPanel 3 Note Firmware supp
64. l enabled device The methods in the API are organized into four main groups USB Device Interaction Device Configuration FPGA Communication and Event Handling The okCUsbFrontPanel Class This class is the workhorse of the FrontPanel API It s methods are organized into three main groups USB Device Interaction Device Configuration and FPGA Communication In a typical application your software will perform the following steps 1 Create an instance of okCUsbFrontPanel 2 Using the USB Device Interaction methods find an appropriate XEM with which to com municate and open that device 3 Configure the XEM PLL Download a configuration file to the FPGA using ConfigureFPGA Perform any application specific communication with the FPGA using the FPGA Commu nication methods USB Device Interaction As much as the API encapsulates the underlying details of the USB interface the fact remains that the XEM is a USB device and therefore must play by the rules These methods provide a means to iterate all attached XEM devices query certain information about each one and ulti mately open a particular device for communication These methods are summarized in the fol lowing table For brevity arguments have been removed Please see the API reference manual for more details 18 www opalkelly com FrontPanel User s Manual Method Description S O GetDeviceCount Returns the number of FrontPanel devices attached to the P
65. l gt lt style gt SQUARE lt sty1e gt lt color gt 00ff00 lt color gt lt endpoint gt 0x20 lt endpoint gt lt bit gt 1 lt bit gt lt object gt okHex Wire Out lt object class okHex gt lt label gt x 3 0 lt label gt lt position gt 217 22 lt position gt lt size gt 35 50 lt size gt lt endpoint gt 0x20 lt endpoint gt lt bit gt 0 lt bit gt lt tooltip gt Counter 1 low nibble lt tooltip gt lt object gt okDigitDisplay Wire Out lt object class okDigitDisplay gt lt position gt 5 215 lt position gt lt size gt 200 30 lt size gt lt maxvalue gt 65535 lt maxvalue gt lt endpoint gt 0x23 lt endpoint gt lt bit gt 0 lt bit gt lt object gt okGauge Wire Out lt object class okGauge gt lt position gt 120 235 lt position gt lt size gt 150 15 lt size gt lt style gt HORIZONTAL lt style gt lt range gt 65535 lt range gt lt endpoint gt 0x33 lt endpoint gt lt bit gt 0 lt bit gt lt object gt okTriggerButton lt object class okTriggerButton gt lt label gt Reset lt label gt lt position gt 20 110 lt position gt lt size gt 60 20 lt size gt lt endpoint gt 0x40 lt endpoint gt lt bit gt 0 lt bit gt lt tooltip gt Reset Counter 2 lt tooltip gt lt object gt Trigger In okTriggerSound lt object class okTriggersound gt lt endpoint gt 0x63 lt endpoint gt lt bit gt 3 lt bit
66. label gt lt position gt 90 25 lt position gt lt size gt 60 20 lt size gt lt endpoint gt 0x00 lt endpoint gt lt bit gt 1 lt bit gt lt tooltip gt Momentarily disable counter 1 lt tooltip gt lt object gt Wire In Wire In okToggleButton lt object class okToggleButton gt lt label gt 1 lt label gt lt position gt 10 10 lt position gt lt size gt 20 20 lt size gt lt endpoint gt 0x00 lt endpoint gt lt bit gt 0 lt bit gt lt object gt okToggleCheck lt object class okTogglecheck gt lt label gt Autocount lt label gt lt position gt 20 135 lt position gt lt endpoint gt 0x00 lt endpoint gt lt bit gt 2 lt bit gt lt tooltip gt Enable autocount lt tooltip gt lt object gt okSlider lt object class okSlider gt lt position gt 310 5 lt position gt lt size gt 25 100 lt size gt lt label gt Hi lt label gt lt tooltip gt 4 bit vertical slider lt tooltip gt lt style gt VERTICAL SHOWLABELS lt style gt lt minvalue gt 0 lt minvalue gt lt maxvalue gt 15 lt maxvalue gt lt value gt 3 lt value gt lt object gt Wire In Wire In okDigitEntry lt object class okDigitEntry gt lt position gt 5 215 lt position gt lt size gt 200 30 lt size gt lt label gt Divider lt label gt lt tooltip gt Sets the integer divider lt tooltip gt lt minvalue gt 0 lt minvalue gt lt maxvalue
67. lay status information back to the PC The Trigger In endpoint is used to initiate a state machine and a Trigger Out endpoint is used to indicate the completion of the state machine A Pipe In endpoint is used to load data into a memory within the design The three types of endpoints are summarized in the table below and described in more detail after Endpoint Sync Async Wire In Asynchronous Transfers a signal state into the design Examples virtual pushbutton or switch Wire Out Asynchronous Transfers a signal state out of the design Examples virtual LED or hex display Trigger In Synchronous Generates one shot signal destined for a particular clock Example pushbutton to start a state machine Trigger Out Synchronous Informs the PC that a particular event has occurred Example Done signal from a state machine pops up a window to the user or starts a data transfer Pipe In Synchronous Multi byte synchronous transfer into the design Example Memory download streaming data Pipe Out Synchronous Multi byte synchronous transfer out of the design Example Memory upload read results of a computation Wires A Wire is an asynchronous connection between the PC and an HDL endpoint A Wire In is an input to the target A Wire Out is an output from the target 12 www opalkelly com FrontPanel User s Manual Wires are designed to fill the position of devices such as LEDs hexadecimal displays pushbut tons DIP switch
68. ls conversion to differ ent versions of ModelSim can be done using the refresh command within ModelSim as well as Aldec ActiveHDL 7 1 and higher Configuring ActiveHDL Launch ActiveHDL 7 1 and follow the steps below Launch the Library Manager View Library Manager On the top menu select Library Attach Library Navigate to the Opal Kelly ActiveHDL simulation library in the FrontPanel installation di rectory and select the lib file to install the library okFPsim _ ver is the Verilog library okFPsim is the VHDL library 4 Repeat Step 3 for the other library Configuring ModelSim A small change to the ModelSim configuration file modelsim ini will allow you to access the Host Simulation Library from within any project and therefore not have to copy the library to each project s simulation directory The configuration file is by default located at the following path C Modeltech_xe_starter modelsim ini Open this file in a text editor The file is read only so you may want to make a copy of the file and edit the copy Add the following link to the Verilog Section note that this should all be ona single line okFPsim_ver c Program Files Opal Kelly FrontPanel FrontPanelHDL ModelSimxE61e okFPsim_ver okFPsim c Program Files Opal Kelly FrontPanel FrontPanelHDL ModelSimxE61e okFPsim Whenever ModelSim is started it will include this library and the models should be accessible from your simulatio
69. makes your design FrontPanel Enabled and allows it to communicate with the PC FrontPanel Firmware Firmware running on the USB microcontroller that provides the conduit for FPGA PC communication FrontPanel API A complete programmer s interface allowing you to design custom PC applications that communicate with your FrontPanel Enabled hardware e FrontPanel Application A flexible software application providing virtual instrumentation to your hardware such as LEDs hex displays numeric entry pushbuttons and so on www opalkelly com 7 FrontPanel User s Manual Basic Functionality FrontPanel is most importantly support software for Opal Kelly s FPGA experimentation mod ules In that role FrontPanel allows you to quickly and easily download FPGA configuration files via USB to a target device Once the configuration file is downloaded the device now takes on that design s personality and is ready for use If desired FrontPanel s role is now complete Peripheral Configuration Opal Kelly XEM devices contain additional peripherals to integrate FPGAs into your projects PLLs audio CODECs Flash memory and other peripherals can benefit from the simple single source configuration that FrontPanel offers PLL outputs are independently configurable through easy to use setup dialogs Flash memory can be programmed cleared and reprogrammed in a variety of ways and audio CODECs can be setup for diffe
70. mple of a hidden component would be one that makes a sound in response to a Trigger Out Performance Notes 14 Opal Kelly s FrontPanel consists of HDL modules within the FPGA firmware on the USB microcontroller and an API on the PC that have been optimized for both performance and a clean abstraction Our latest FrontPanel 3 release has improved performance significantly while offering several features that customers have requested Achieving the highest level of performance for your particular application requires an understand ing of the components being used and how certain things affect performance By following a few simple strategies and applying these notes your application will be a top USB performer and still benefit from the ease of use and flexible abstraction that only FrontPanel provides Measured Performance Measured performance figures in this section were taken on an Athlon 64 X2 4800 machine running Windows XP SP2 USB performance can vary significantly depending on a number of factors including the motherboard make and model specific driver versions installed and ma chine load Wires and Triggers Wires and triggers provide the most basic form of communication between the FPGA and the PC From a performance perspective wires can be read or written several hundred times per second All Wirelns are read simultaneously regardless of which ones you are interested in Similarly all WireOuts are written simultaneously
71. n project 66 wwwopalkelly com FrontPanel User s Manual Adding Host Simulation to a Test Fixture A test fixture which simulates the FrontPanel Host requires the following three components 1 Instantiation of the device under test DUT This is required in any test fixture 2 A behavioral block which calls the Host Simulation Library to mimic the FrontPanel API 3 Include okHostCalls v This file contains the tasks which simulate the various host API functions The last two items are specific to FrontPanel Host Simulation The table below lists the FrontPanel API calls that are available within the Host Simulation Library In most cases the parameters are identical to the corresponding FrontPanel API calls SetWirelns GetWireOutValue ActivateTriggerln IsTriggered WriteToPipeln ReadFromPipeOut WriteToBlockPipeln ReadFromBlockPipeOut UpdateWirelns UpdateWireOuts UpdateTriggerOuts FrontPanelReset Example Test Fixtures The Simulation subdirectory in the FrontPanel installation location contains sample test fixture templates for simulation They show the general flow and structure of a test fixture that includes the FrontPanel host interface simulation model These templates should be the starting point for your own simulation test fixtures Verilog For Verilog simulation dut _ tf v your device under test test fixture is used together with okHostCalls v The latter includes the necessary code to communicate with t
72. n the first available device xem gt OpenBySerial Configure the PLL using the stored EEPROM settings xem gt LoadDefaultPLLConfiguration Download a configuration file to the FPGA xem gt ConfigureFPGAC mybitfile bit Set a value on WireIn endpoint 0x00 SetwireInvalue 0x00 0x37 UpdatewireInsQ Activate TriggerIn 0x40 0 clears address pointers ActivateTriggerIn 0x40 0 Send 1024 bytes to PipeIn 0x80 writeToPipeIn 0x80 1024 buf Read 1024 from Pipeout OxA0 ReadFromPipeout OxA0 1024 buf Read the result from wireOut endpoint 0x20 Updatewi reouts result Getwire0utvalue 0x20 Regarding Device Ownership In general once an instance of okCUsbFrontPanel has been opened that instance owns the device That means that while the API will allow you to create another instance and communi cate with the same device there are likely going to be problems with doing so In situations where you must have multiple threads or processes communicating with the same device it is better to have a single owner of the device instance and route all calls through that owner The exception to this is GetDeviceCount and the associated calls You can call this method at any time even before opening a device to determine the number of attached FrontPanel devices and retrieve their model numbers and serial numbers You may not retrieve the Device ID string without opening
73. nd stored www opalkelly com FrontPanel User s Manual In both cases an optional Start Trigger and optional Done Trigger are available The Start Trig ger will be activated just before the transfer initiates The Done Trigger is activated after the transfer completes These triggers can be used as notification events within your hardware Element Type Description Y lee TEXT Label text shown inside the buton endpoint HEX BYTE Endpoint address for the corresponding Pipe In or Pipe Out filename TEXT Optional filename to read or write If not provided the user will be prompted length NUMBER For Pipe Out transfers the length in bytes to read from the Pipe Out and store in the file append If present an output file will be appended if it already ex ists starttrigger Describes the parameters of an optional Start Trigger end point and bit donetrigger Describes the parameters of an optional Done Trigger end point and bit XML Example lt object class okFilePipe gt lt label gt Pipe Out lt label gt lt position gt 20 53 lt position gt lt size gt 60 20 lt size gt lt endpoint gt 0xa0 lt endpoint gt lt length gt 5000 lt 1ength gt lt tooltip gt Read a file from Pipe OxA0 lt tooltip gt lt append gt lt starttrigger gt lt endpoint gt 0x40 lt endpoint gt lt bit gt 0 lt bit gt lt starttrigger gt lt donetrigger gt lt endpoint gt 0x40 lt endpoint gt lt bit gt 1 lt bit gt lt
74. nt that does maintain its state see the okToggleButton Element Type Description 22222222 POSITION Position of the top left corner SIZE ee Text svete town ie e ton bE NOWGER ett which tis component adresses 0 85 T5 M5E 50 www opalkelly com FrontPanel User s Manual XML Example lt object class okPushbutton gt lt label gt Disable lt label gt lt position gt 90 25 lt position gt lt size gt 60 20 lt size gt lt endpoint gt 0x00 lt endpoint gt lt bit gt 1 lt bit gt lt tooltip gt Momentarily disable counter 1 lt tooltip gt lt object gt okToggleButton Wire In The okToggleButton is similar to the okPushbutton in that it connects to a Wire In endpoint In contrast to the okPushbutton however this component maintains its state just as a physical toggle switch would When unpressed the corresponding wire is deasserted logic 0 When pressed the corresponding wire is asserted logic 1 Note This component is not presently available under OS X Element ype Deseription SCS CT ee Text I abet sown ie e ton bE NOWGER Bitto whin tis component atdresses 0 LS5 T5 M5E XML Example lt object class okToggleButton gt lt label gt 1 lt label gt lt position gt 10 10 lt position gt lt size gt 20 20 lt size gt lt endpoint gt 0x00 lt endpoint gt lt bit gt 0 lt bit gt lt object gt okToggleCheck Wire In The okToggleCheck attaches to a W
75. of the Host Simulation Library NOTE Both samples are provided only for ModelSim but should translate to ActiveHDL in a straightforward manner Required Files The following table lists the files required for the First simulation along with a brief description Filename Description 222222222 This is the unmodified source file from the First project Simulation first do This files contains the ModelSim commands to setup compile and run the simulation Simulation First_tf v This is the Verilog test fixture for the First simulation Simulation okHostCalls v This file contains the Host Simulation Library calls This has been copied from the installation directory The file okHostCalls v has been copied from the FrontPanel installation directory to the simula tion directory By default it is installed at the following location C Program Files Opal Kelly FrontPanel FrontPanelHDL Simulation Perform the Simulation For this example the simulation is performed from a series of commands already setup in the first do file To run the simulation perform these steps Start ModelSim 2 Atthe command prompt change your working directory to the First Simulation directory cd c mysimulations First 3 Perform the simulation by entering at the command prompt do first do The simulation should run to completion By selecting the Wave window you should see some thing like this assuming ModelSim as the simul
76. or that output Each output can then be independently enabled or disabled using the checkboxes to the right EEPROM Read The XEM stores the microcontroller bootcode in a small serial EEPROM which is also used to store a single set of PLL parameters These parameters are loaded before each FPGA configu ration so that valid clock signals are presented to the FPGA when it comes out of configuration The PLL Configuration Dialog allows you to read and write this section of EEPROM by using the buttons at the lower left When you click the button labelled EEPROM Read the stored PLL configuration is read from the EEPROM and the PLL Configuration Dialog is updated to represent these values The PLL is not re configured yet To configure the PLL with these values you must press Apply www opalkelly com 43 FrontPanel User s Manual EEPROM Write The current configuration represented in the PLL Configuration Dialog not the current PLL con figuration is written to the EEPROM when you press this button The next time a configuration file is downloaded to the FPGA this configuration will be loaded into the PLL Apply Any time you change a setting in the PLL Configuration Dialog or load the EEPROM settings the values change in the dialog but do not affect the actual PLL on board To make the changes take effect you must press the Apply button Example PLL Configurations The table below lists several example frequencies an
77. orting FrontPanel 1 4 1 and earlier was limited to approximately 32MB s to the FPGA and 19 MB s from the FPGA www opalkelly com 13 FrontPanel User s Manual Block Throttled Pipes Block Throttled Pipes or BTPipes are very similar to standard Pipes with one important distinc tion BTPipes provide a way for the FPGA to throttle transfer through the pipe at a block level The block size is programmable from 1 to 512 words 2 to 1024 bytes The FPGA throttles data through the BTPipe by asserting or deasserting a READY signal to the USB microcontroller This allows the FPGA to halt data transfer until data is available or ready to be processed BTPipes provide the same transfer rates as standard pipes but the throttling allows them to be used in a wider array of applications and can generally increase performance by reducing the overhead that would otherwise be required to negotiate the transfer at a higher level FrontPanel 3 Note BTPipes are only available using firmware supporting FrontPanel 3 Full Speed USB Note On full speed USB busses the block size is limited to 1 to 32 words 2 to 64 bytes Components Components represent the other half of the interface each connecting to an appropriate endpoint or multiple endpoints within the design Most components have a graphical representation within FrontPanel such as a pushbutton virtual LED or numerical display Some components howev er are hidden from view An exa
78. our design or serve some decorative function The interfaces are described in FrontPanel profiles which are written in a text file format known as XML The XML profile con tains structure which defines where each component exists on a panel as well as the connections that component has to your FPGA design FrontPanel XML files end with the extension XFP XML stands for eXtensible Markup Language and is used in documents containing structured information The syntax for XML is defined at http www w3 org TR WD xml For its part XML does not define the content but rather how the content is organized FrontPanel uses XML because the standard is well known and there are many tools available to read write edit and parse the content It is also easily human readable so you can read and write FrontPanel profiles in a text editor with ease A complete tutorial of XML is beyond the scope of this text What is provided here is a basic tuto rial of the aspects of XML required to compose FrontPanel profiles Please refer to the enormous on line resources available for a complete understanding of XML its applications and the tools available for working with XML Basic Structure for FrontPanel The basic FrontPanel XFP file has the following structure www opalkelly com 47 FrontPanel User s Manual lt xml version 1 0 encoding I1S0 8859 1 gt lt A basic FrontPanel Example gt lt resource version 2 3 0 1 gt l
79. p gt tag within the XML the KeyTrigger can map to the upstroke By defining both the upstroke and downstroke to the same key triggers can be sent on each end of a keypress Element Type Description 222222222 POSITION Position of the top left corner SIZE label TEXT Label text COLOR Sets the component s active color keys XML XML describing the key mapping from keyboard events to HDL endpoints See the table below for more details The following table describes the nodes of the lt key gt XML element within the component de scription This mapping is used to associate a keyboard event with an HDL endpoint Element Type Description 22222222 KeyButton XML Defines a KeyButton behavior on the provided keycode to the associated Wire In endpoint The keycode property defines the mapped key KeyToggle XML Defines a KeyTrigger behavior on the provided keycode to the associated Wire In endpoint The keycode property defines the mapped key KeyTrigger XML Defines a KeyTrigger behavior on the provided keycode to the associated Trigger In endpoint The keycode property defines the mapped key The table below lists the recognized keycodes kev SPACE en HOME kev saer AN SSCS kev contro kev peonon SOS 62 www opalkelly com FrontPanel User s Manual XML Example lt object class okkKeyPanel gt lt label gt Key Panel A lt label gt lt color gt b0f0b0 lt color gt lt position gt 5
80. pful for setting up FrontPanel profiles or writing the HDL for your project At the bottom is a status bar which displays the current FrontPanel status The icon at the right of the status bar indicates if the current FPGA design is FrontPanel enabled If the current design has an instance of okHostinterface the icon will be in color If no instance is detected the icon is displayed in grayscale Selecting the Active Device As XEM devices are added and removed from the USB the Active devices combobox will be updated You may select any one of these devices for each instance of FrontPanel The select ed device then becomes the target for any FPGA download and PLL configuration operations In addition any loaded FrontPanel profiles will communicate with this target device Device Identifier String Each XEM device contains an identifier string stored in the on board EEPROM This identifier string is displayed in brackets in the Available Devices list so that you know which device is cur rently selected You can change the device identifier string at any time by navigating to FrontPanel Set Device ID FPGA Configuration Download gt lt S To download an FPGA configuration file to the current target device simply click on the icon shown to the left A file selector dialog will appear from which you can choose the Xilinx bitfile to download If you accept the file the download will proceed immediately
81. plication running on a PC host The Opal Kelly FrontPanel Host Simulation Libraries allows simulation of this PC host within a hardware simulation System Simulation Model The block diagram below illustrates the system simulation model for the Host Simulation Librar ies The FPGA design encompasses the user s HDL design as well as the okHostInterface module and endpoint modules such as okWireln and okPipeOut In a live system the ok HostInterface communicates with the USB microcontroller on the FPGA board which in turn communicates with the PC and software API In the simulation system the okHostInterface is replaced by a simulation model which communicates with a simulation model for the Host The user s simulation test fixture executes host directives as if they were software API calls www opalkelly com 65 FrontPanel User s Manual Complete FPGA Design okHostInterface mes okWireOut User s HDL okTriggerln okPipeln ModelSim Host j ss The goal of this type of simulation model is to simulate the complete FPGA design without hav ing to make changes specific to the simulation model In reality many designs will require some modification but in this case the host can be simulated as realistically as possible Simulation Requirements The Opal Kelly FrontPanel Host Simulation Library has been precompiled for use with ModelSim XE III 6 1e Starter Edition the version packaged with the Xilinx ISE too
82. ption we gather that when RESET is asserted the counter will hold the value 0x00 When DISABLE1 is asserted the counter holds its current value Otherwise the counter will increment each time the clock divider counter expires Note that this counter operates on CLK1 which is mapped to LCLK1 on the PLL Counter 2 The second counter operates on CLK2 which is mapped to LCLK2 on the PLL Using the PLL Configuration Dialog we will be able to observe the effects of changing the PLL frequencies on the two counters The Verilog HDL for this counter and its own divider is listed below This counter will count up when UP2 is asserted count down when DOWN2 is asserted and automatically count up when AUTOCOUNTZ2 is asserted Note that UP2 and DOWN2 must be asserted for exactly one CLK2 cycle for the counter to count only one This is why we have the Trigger endpoints always posedge clk2 begin div2 lt div2 1 if div2 24 h000000 begin div2 lt 24 h100000 clk2div lt 1 b1 end else begin clk2div lt 1 b0 end if reset2 1 b1 count2 lt 8 h00 else if up2 1 b1 count2 lt count2 1 else if down2 1 b1 count2 lt count2 1 else if Cautocount2 1 b1 amp amp clk2div 1 b1 count2 lt count2 1 end 80 www opalkelly com FrontPanel User s Manual Endpoints This sample uses several endpoints to provide controllable inputs to the hardware and observ a
83. r 8 h87 ep_clk c1k2 ep_reset reset ep_read pipeRead ep_dataout pipeData ep_full pipeFull ep_empty pipeEmpty ep_status pipestatus VHDL Instantiation pipeIn87 okBufferedPipeIn port map ok1 gt ok1 ok2 gt ok2 ep_addr gt x 87 ep_clk gt clk2 ep_reset gt reset ep_read gt pipeRead ep_dataout gt pipeData ep_full gt pipeFull ep_empty gt pipeEmpty ep_status gt pipeStatus www opalkelly com FrontPanel User s Manual okBufferedPipeOut DEPRECATION NOTICE The okBufferedPipeln has been deprecated in FrontPanel 3 Now that Xilinx includes the FIFO Core Generator with ISE WebPack for free the okBufferedPipes are no longer required to fill the void In all cases an okPipe coupled to a FIFO Core is the preferred choice The okBufferedPipeOut is a special implementation of a Pipe Out which includes a FIFO to sim plify dataflow between the target and host The FIFO is implemented as a 2047 word 2047 byte for XEM3001v1 deep asynchronous block RAM FIFO Because the FIFO is asynchronous the two ports can run with different clocks TI_CLK for the target interface side and EP_CLK for the user logic side The buffered pipes are provided as one way to cross the clock boundary between the host in terface and your design s clock if they differ Another simpler method would be to use a double buffered technique Some negotiation will be required between the host bu
84. re the use of this file okFrontPanelDLL h This header file contains the FrontPanel DLL entrypoints corresponding to the stub functions in okFrontPanelDLL c www opalkelly com 25 FrontPanel User s Manual 26 In most cases each class method has a corresponding DLL entrypoint This makes it easy to re fer to the standard API documentation for calling information One notable difference is that most DLL entrypoints require a pointer argument This pointer is actually the pointer to the allocated C class object Note however that this object is allocated and deallocated using DLL entry points and therefore the DLL does NOT require C and can be used in any C application Example Usage C When using the DLL in a compiled C application you will need to compile and link the okFrontPanelDLL cpp file with your application This file provides the stub functions that will load and call the DLL from your application You will also need to include the file okFrontPanelDLL h in each source file that calls the DLL Initialization Before calling functions within the DLL you need to load the DLL library This is done with the following call Initialize the DLL and load all entrypoints if FALSE okFrontPanelDLL_LoadLib printfC ERROR FrontPanel DLL could not be initialized n Constructing and Destructing Objects The FrontPanel API is an object oriented library but the DLL is strictly C style There
85. rent configurations Flexibility Outside the Design FPGAs and other programmable logic devices have allowed engineers the unique opportunity to construct complete hardware designs within the confines of a logic device Unfortunately this means that many of the tools engineers typically employ to debug such designs such as oscil loscopes LEDs switches and buttons are limited to viewing signals brought out to the external pins of the device FrontPanel takes these ideas closer to the realm of flexible logic devices and makes them likewise flexible In the end however FrontPanel provides controllability and observability to your designs reducing development time and putting a new face on your proto types FrontPanel Software on PC FPGA FrontPanel Example EN User Design Host Interface lt Endpoint Wire Out Endpoint Wire Out USB uController USB Cable lt object class pushbutton gt lt label gt Start lt label gt Endpoint Wire In lt position gt 10 10 lt position gt lt size gt 80 20 lt size gt lt endpoint gt 0x08 lt endpoint gt lt pit gt 3 lt bit gt lt object gt Endpoint Verilog or VHDL okWireIn startEP ep_addr 8 h08 ep_data buttonwire Controllability Any prototype or experiment invariably requires some level of control Typically devices such as pushbuttons DIP switche
86. rmed the profile is loaded and the first panel is displayed If there are more panels in the profile they will not be displayed However an entry is made in the View menu for each panel in the profile To open another panel simply select eM j that panel s label from the menu Recover otatus F Drag and Drop As an alternative to opening the file dialog to load a new panel you can drag an XFP file and drop it on the button This will load the profile and open the first panel just like opening the file through the file selector Preferences The Preferences dialog shown below can be shown by navigating under the FrontPanel menu FrontPanel Preferences FrontPanel Preferences FrontPanel Preferences Wire Update Rate O Slow 200 ms O Medium 100 ms Fast 25 ms FPGA Configuration Options Configure PLL before FPGA download Application Settings C Show Panels in Taskbar Enable asynchronous transfers Wire Update Rate Wire Out enpoints are updated using timed polling by the FrontPanel software This update rate is determined by your design s needs how quickly you need to see wire changes as well as the performance of your PC On an Athlon 2100 even the fastest update rate places minimal lt 2 load on the CPU Configure PLL Before FPGA Download This option determines whether an FPGA download configures the PLL prior to download In most cases this is the desired behavior so that a val
87. s rotary devices or keypads are used With most prototype systems however what is provided is nearly never enough you can always use one more button or switch to select a different mode Typically the problem is solved by rebuilding the design with a differ ent mode or multiplexing the use of the available inputs 8 www opalkelly com FrontPanel User s Manual FrontPanel offers another solution With a simple change in a couple files new virtual buttons and switches can be added quickly and connected to the proper points in your design Observability Prototypes also require some level of observability usually offered in the form of LEDs hexa decimal displays and LCDs or sampled externally by oscilloscopes and logic analyzers Again however there is the problem of limited resources in the typical prototype system Only so many LEDs and displays are present on an I O board so the problem is remedied by adding more I O boards or multiplexing the use of the current lot FrontPanel s flexibility means you can display all sorts of information in real time about the state of any number of signals in your design It s like having an I O board that allows you to add and remove components at will without taking up valuable pins on the FPGA XML and FrontPanel Components XML is the eXtensible Markup Language used in the latest generation of software applications and other forms of markup such as XHTML It is simply a way to descri
88. s as they are required by the FrontPanel XML parser okPanel The first object specified is the okPanel object which has a name property with value panel1 FrontPanel looks for these properties when loading a profile They must be sequenced panel1 panel2 and so on The okPanel object also has two child nodes serving as parameters for the okPanel as listed in the table below www opalkelly com 75 FrontPanel User s Manual This is the title of the dialog window created when you view this panel The size of the dialog in pixels Width Height The okPanel object also has two child nodes which are FrontPanel components okToggleButton and okLED Because they are children of the okPanel object they will appear on this particular panel okToggleButton The toggle button is described with child nodes as indicated in the table below label This is a label that wil be placed inside the toggle button endpoint The endpoint address expressed in hexadecimal for this toggle button s Wire In endpoint The specific bit on the endpoint address that this toggle button controls okLED The LED is described with child nodes as indicated in the table below label This is a label that will be placed below the LED The position of the top left corner of the component in pixels X Y The size of the component in pixels specified as Width Height This size includes the LED and its label LED style SQUARE or ROUND
89. see above and in the setup of the design workspace Design Workspace Setup Follow the steps below to properly setup your ActiveHDL design workspace for use with the FrontPanel HDL Simulation libraries 1 Create an empty design in ActiveHDL The design name and location are not important 2 Inthe Design Browser double click on Add New File then Add Existing File then select the file you want to add to the simulation First add the Xilinx g1b1 v file from the Xilnx ISE installation directory in verilog src 3 From the top menu select Design Settings Then select General Verilog Add okfpsim verand ovi unisim to the Verilog libraries 4 In the Design Browser click on one of the Verilog files and select Compile All with File Reorder 5 Expand the local library in the Design Browser it will have your design name Select your top level source and glb1 Right click on one of them and select Set as Top Lev el This will create a multiple top level 6 From the top menu select Simulation Initialize Simulation You are now free to create a new waveform and continue with your simulations 68 www opalkelly com FrontPanel User s Manual Example First Two simulation examples are included with FrontPanel to help get you started The first example runs a very simple simulation on the First project that we included in the Getting Started guide The second example is an in depth simulation which exercises more
90. ser s Manual 40 www opalkelly com FrontPanel User s Manual Using the FrontPanel Application FrontPanel provides essential functionality to make using XEM devices easy and intuitive This functionality includes downloading FPGA configuration files and configuring the on board periph erals for use in a design but it also extends to loading FrontPanel profiles to control and inter face to your design The FrontPanel interface has a simple presentation as shown below Opal Kelly FrontPanel FrontPanel View Debug Help nn Available devices ny XEM3001 0 Opal Kelly XEM3001 v Type Label Endpoint Address it Enable okPushbutton Reset Wire In 0x00 okPushbutton Disable Wire In 0x00 okLED rd Wire Out 0x00 okLED 6 Wire Out 0x00 okLED 5 Wire Out 0x00 OKLED 4 Wire Out 0x00 3 Wire Out 0x00 c00o00oolu OKLED FrontPanel profile loaded successfully Available XEM devices are shown to the right The device choices are automatically updated as USB devices are added and removed from the bus The icons to the left allow you to download an FPGA configuration configure the on board PLL and load a FrontPanel profile respectively If no XEM device is available downloading and PLL configuration will not be allowed and their icons will be disabled www opalkelly com 41 FrontPanel User s Manual In the lower section of the window a Component List displays the currently registered FrontPanel components This list may be hel
91. ses Endpoints attach to the host interface on a shared bus To properly route signals between the host PC and target endpoints each endpoint must be assigned a unique 8 bit address For performance reasons to minimize USB transactions each endpoint type has been assigned an address range as indicated in the table above When assigning addresses to your endpoints be sure to follow these ranges The endpoint address is assigned in HDL through an additional 8 bit input port on the endpoint instance Example instantiation for each endpoint type are shown in the sections below okWireln In addition to the target interface pins the okWireln adds a single 16 bit output bus called EP _ DATAOUT 15 0 The pins of this bus are connected to your design as wires and act as asyn chronous connections from FrontPanel components to your HDL When FrontPanel updates the Wire Ins it writes new values to the wires then updates them all at the same time Therefore although the wires are asynchronous endpoints they are all updated at the same time on the host interface clock Signal Direction Description o EP_DATAOUT 15 0 Output Wire values output sent from host Verilog Instantiation okwireIn wire03 ok1 gt ok1 ok2 gt ok2 ep_addr 8 h03 ep_dataout ep03data VHDL Instantiation wire03 okwireIn port map ok1 gt ok1 ok2 gt ok2 ep_addr gt x 03 ep_dataout gt ep03data okWireOut An okWireOu
92. sting can be found later in this manual as one of the examples Verilog Instantiation okHostinterface hostIF hi_inChi_in hi_out hi_out hi_inout hi_inout ti_clk ticlk ok1 ok1 ok2 ok2 VHDL Instantiation OkHI okHostInterface port map hi_in gt hi_in hi_out gt hi_out hi_inout gt hi_inout ti_clk gt ticlk ok1 gt ok1 ok2 gt ok2 Endpoint Types 32 FrontPanel supports three basic types of endpoints Wire Trigger and Pipe Each can either be an input from host to target or output from target to host Each endpoint type has a certain address range which must be used for proper operation The address is specified at the instan tiation of the endpoint module in your design Endpoints are instantiated in your HDL design and connected to the okHostInterface target ports Each endpoint also has one or more ports which are connected to various signals in your design depending on the endpoint module Each endpoint is connected to 48 target interface pins on the okHostInterface module The direction is from the perspective of the endpoint module Signal Direction Description OK1 30 0 Interface control HI to target OK2 16 0 Output Interface control Target to Hl www opalkelly com FrontPanel User s Manual These signals are present in every endpoint In the signal tables for the independent endpoints below we have left out these common signals Endpoint Addres
93. t and its three neighbors to the left For example if bit 2 the hex value will be taken from bits 5 2 COLOR Sets the numeral color XML Example lt object class okHex gt lt label gt x 3 0 lt label gt lt position gt 217 22 lt position gt lt size gt 35 50 lt size gt lt endpoint gt 0x20 lt endpoint gt lt bit gt 0 lt bit gt lt tooltip gt Counter 1 Clow nibble lt tooltip gt lt object gt okDigitDisplay Wire Out This component allows a flexible way to display numerical information to your design The ok DigitDisplay is simply a read only Wire Out version of the okDigitEntry Just like the okDigitEn try its endpoint attachment can span multiple Wire Out endpoints as necessary according to the maxvalue setting Element Type Description 2222222222 Mabel TEXT Labeltext shown inside the buton play will span multiple consecutive endpoints as necessary XML Example lt object class okDigitDisplay gt lt position gt 5 215 lt position gt lt size gt 200 30 lt s1ze gt lt maxvalue gt 65535 lt maxvalue gt lt radix gt 16 lt radix gt lt endpoint gt 0x20 lt endpoint gt lt bit gt 0 lt bit gt lt object gt www opalkelly com 55 FrontPanel User s Manual 56 okGauge Wire Out The okGauge component is used to display a bar type indicator horizontally or vertically on the panel It connects to a Wire Out endpoint and allows a maximum range of 65535
94. t be provided in the cycle following as assertion of this signal Verilog Instantiation okPipeOut pipe0utA3 ok1 gt ok1 ok2 gt ok2 ep_addr 8 ha3 ep_datain epA3pipe ep_read epA3read VHDL Instantiation pipeOutA3 okPipeOut port map ok gt ok1 ok2 gt ok2 ep_addr gt x a3 ep_datain gt epA3pipe ep_read gt epA3read okBTPipeln The Block Throttled Pipe In module is similar to the okPipeln module but adds two signals EP_BLOCKSTROBE and EP_READY to handle block level negotiation for data transfer The host is still master but the FPGA controls EP_READY When EP_READY is asserted the host is free to transmit a full block of data When EP_READY is deasserted the host will not transmit to the module EP_READY could for example be tied to a level indicator on a FIFO When the FIFO has a full block of space available it will assert EP_READY signifying that it can accept a full block trans fer 1 2 3 4 5 6 7 8 9 10 11 12 13 TLCLK N S l l EP_READY _ AY T EP_BLOCKSTROBE Ep WRITE EP_DATACUT I MINI o OC A Signal Direction Description EP_ADDRI7 0 Endpoint address EP_DATAOUT 15 0 Output Pipe data output EP_WRITE Output Active high write signal Data should be captured when this signal is asserted EP_BLOCKSTROBE Output Active high block strobe This is asserted for one cycle
95. t module adds a single 16 bit input bus called EP_DATAIN 15 0 Signals on these pins are read whenever FrontPanel updates the state of its wire values In fact all wires are cap tured simultaneously synchronous to the host interface clock and read out sequentially Signal Direction Description EP_DATAIN 15 0 Wire values input to be sent to host Verilog Instantiation okwire0ut wire21 ok1 gt ok1 ok2 gt ok2 ep_addr 8 h21 ep_datain ep21data VHDL Instantiation wire21 okwireOut port map ok1 gt ok1 ok2 gt ok2 ep_addr gt x 21 ep_datain gt ep21data www opalkelly com 33 FrontPanel User s Manual 34 okTriggerln The okTriggerIn provides EP_CLK and EP_TRIGGER 15 0 as interface signals The Trigger In endpoint produces a single cycle trigger pulse on any of EP_TRIGGER 15 0 which is synchro nized to the clock signal EP_CLK Therefore the single cycle does not necessarily have to be a single host interface cycle Rather the module takes care of crossing the clock boundary prop erly Signal Direction Description EP_ADDR 7 0 Endpoint address EP_CLK Clock to which the trigger should synchronize EP_TRIGGER 15 0 Output Independent triggers from host Verilog Instantiation okTriggerIn trigIn53 ok1 gt ok1 ok2 gt ok2 ep_addr 8 h53 ep_clk clk2 ep_trigger ep53trig VHDL Instantiation trigIn53 okTriggerIn port map ok1 gt ok1 ok2
96. t object class okPanel name panel1 gt lt title gt Main Panel Title lt title gt lt size gt 180 70 lt s1ize gt Main Panel component XML will go here lt object gt lt resource gt This simple example defines a single panel Note the first line starting with lt xml gt and the lt re source version 2 3 0 1 gt lt resource gt are required content in any FrontPanel profile Comments Comments in XML can appear anywhere outside of normal markup They have the form as shown below Note that the string is not allowed within a comment and that the comment must end with exactly two hyphen characters and the gt character lt This is some comment text gt lt This text is NOT allowed because it is incorrectly terminated gt Start Tags and End Tags The start and end tags enclose an XML element In the listing below the XML element is an object and its content is defined between the first line Start Tag and last line End Tag This particular element contains a child element label which also has as a requirement a Start Tag and an End Tag lt object class okStaticText gt lt label gt Hello there lt label gt lt object gt The object element in the above example contains one attribute class which is set to okStat icText In FrontPanel all of the graphical components are object elements w
97. t pipe0uta3 ok1 ok1 ok2 ok2 ep_addr 8 ha3 ep_datain pipeData ep_read pipeRead ep_blockstrobe pipestrobe ep_ready pipeReady okBufferedPipeln pipeIn9c okBTPipeIn port map okl gt ok1 ok2 gt ok2 ep_addr gt x 9C ep_dataout gt pipeData ep_write gt pipewrite ep_blockstrobe gt pipeStrobe ep_ready gt pipeReady pipe0utA3 okBTPipeOut port map okl gt okl ok2 gt ok2 ep_addr gt x A3 ep_datain gt pipeData ep_read gt pipeRead ep_blockstrobe gt pipeStrobe ep_ready gt pipeReady okBufferedPipeOut full 1 8 full and so on Signal Direction Description Signal Direction Description S O EP_CLK Input Endpoint clock EP_CLK Input Endpoint clock EP_DATAOUT 15 0 Output Pipe data output EP_DATAIN 15 0 EP_READ Output When asserted advances the read pointer to the next FIFO word advances to the next FIFO word EP_FULL Output Asserted when the endpoint FIFO is full EP_EMPTY Output Asserted when the endpoint FIFO is empty EP_EMPTY Asserted when the endpoint FIFO is empty EP_STATUST 3 0 Output Indicates the fullness of the FIFO in 16 levels 1 16 EP_STATUS 3 0 Indicates the fullness of the FIFO in 16 levels 1 16 full 1 8 full and so on ep_addr 8 h9c ep_full pipeFull okBufferedPipeIn pipe0ut9c ok1 ok1 ok2 ok2 ep_clk clk2 ep_dataout pipeData ep_read pipeRead ep_empty pip
98. t position gt 170 5 lt position gt lt size gt 100 15 lt size gt lt p110 p 400 q 48 gt lt p111 p 397 q 43 gt lt outputO source p110_0 divider 8 gt on lt output0 gt lt output1 source p111_180 divider 16 gt on lt output0 gt lt object gt okKeyPanel Wire In Trigger In The okKeyPanel component allows keyboard input to be captured and mapped to selected Wire In and Trigger In endpoints Multiple okKeyPanels may be instantiated on the same okPanel al lowing the same keyboard events to map to different behaviors depending on which okKeyPanel is active The okKeyPanel appears on a panel as a simple box with a text label within When the mouse is over the component it changes color to indicate that it is active When active keyboard events are captured and mapped to HDL endpoints according to the XML description Three behaviors are available KeyButton KeyToggle and KeyTrigger KeyButton The KeyButton works like a pushbutton The Wire In is asserted when the key is pressed and deasserted when the key is released www opalkelly com 61 FrontPanel User s Manual KeyToggle The KeyButton is like a toggle button On the key downstroke the Wire In is toggled Nothing happens on the upstroke KeyTrigger The KeyTrigger activates a Trigger In when the keyboard event occurs By default the keyboard event is defined as the key downstroke However with the optional lt u
99. ta If the target is able to keep up with the throughput but needs to handle data in a block fashion coupling the okPipeln with a FIFO from the Xilinx CORE genera tor is a good solution Alternatively an okBTPipeln can be used The timing diagram below indicates how data is presented by the okPipeln to user HDL EP_ DATAOUT contains valid data for any clock cycle where EP_WRITE is asserted during the rising edge of TI_CLK Note that the transfer sends 4 words in this example Although contrived it is important to note that EP_WRITE may deassert during the transfer This will generally happen with longer transfers gt 256 words 1 2 3 4 5 6 7 8 9 10 11 12 13 nek LI LI LIIN LP O LP LS LS 1 EP_WRITE N EP_DATACUT MD o A A Signal Direction Description EP_ADDR 7 0 Endpoint address EP_DATAOUT 15 0 Output Pipe data output EP_WRITE Output Active high write signal Data should be captured when this signal is asserted Verilog Instantiation okPipeIn pipeIn9c okl gt ok1 ok2 gt ok2 ep_addr 8 h9c ep_dataout ep9Cpipe ep_write ep9cwrite VHDL Instantiation pipeIn9c okPipeIn port map ok1 gt ok ok2 gt ok2 ep_addr gt x 9c ep_dataout gt ep9Cpipe ep_write gt ep9Cwrite okPipeOut The okPipeOut module implements a simple version of the Pipe Out endpoint to move synchro nous multi byte data from the target to the host Because the host is master all re
100. ta to the Pipe Out as requested Byte Order Pipe data is transferred over the USB in 8 bit words but transferred to the FPGA in 16 bit words Therefore on the FPGA side HDL the Pipe interface has a 16 bit word width but on the PC side API the Pipe interface has an 8 bit word width When writing to Pipe Ins the first byte written is transferred over the lower order bits of the data bus 7 0 The second byte written is transferred over the higher order bits of the data bus 15 8 Similarly when reading from Pipe Outs the lower order bits are the first byte read and the higher order bits are the second byte read Block Throttled Pipes Block Throttled Pipe communication is identical to Pipe communication with the additional speci fication of a block size The FPGA sends or receives data in blocks sized 2 4 6 1024 as specified by the arguments to the call Block sizes are restricted to 64 bytes or less when using the device at full speed Because the FPGA has the opportunity to stall the transfer by deasserting EP_READY the call may fail with a timeout Example Usage 22 Below is a short code snippet that illustrates how the API might be used in a C application More useful and detailed examples can be found in the Samples folder of the FrontPanel instal lation www opalkelly com FrontPanel User s Manual Create an instance of the okCUsbFrontPanel okcusbFrontPanel xem new okCUsbFrontPanel Ope
101. te a GUI button The only way to reconfigure the PLL even after a new FPGA configuration file is loaded is to reload the profile Note that this element is ignored if the target device does not have a CY22393 PLL Also note that the convention here is to label PLLs and outputs as 0 indexed 0 1 2 rather than in dexed from 1 as the Cypress documentation does www opalkelly com FrontPanel User s Manual Element LN CTS labe TEXT Label text shown inside the button OPTIONAL none This parameter has no content but does have the following properties P Specifies the P multiplier for the PLL 6 2053 Q Specifies the Q divider for the PLL 2 257 output0 STRING This string is either on or off and turns the output on or output1 off ee The property source is a string that represents the source output4 for the output ref Use the reference 48 MHz pll0_0 PLL ouput O with 0 phase shift pll0_ 180 PLL ouput O with 180 phase shift plI1_0 PLL ouput 1 with 0 phase shift oll1_ 180 PLL ouput 1 with 180 phase shift pll2_0 PLL ouput 2 with 0 phase shift pll2_ 180 PLL ouput 2 with 180 phase shift The property divider specifies the integer divider for the output 1 127 for outputs 0 3 and 2 3 4 for output 4 XML Example lt object class o0kPLL22393 gt lt label gt PLL1 Configuration lt label gt l
102. the application you need to add the Java API JAR to the classpath java classpath okjFrontPanel jar MyClass A thorough example of the Java API is included in the DESTester application Shown below is the Python example above transformed into Java import com opalkelly frontpanel public class JavaAPITest public void TestMethod xem new okFrontPanel pll new okPLL221500 xem GetEepromPLL22150configuration p11 xem SetPLL22150Configuration p11 System out println PLL Output pl1l GetoutputFrequency 0 MHz xem ConfigureFPGA c counters bit xem ActivateTriggerin short 0x40 short 0 FrontPanel DLL On the Windows platform a dynamically linked library DLL is available This DLL makes it pos sible to call the FrontPanel API from other programming languages such as VisualBasic as well as from many third party software applications such as LabVIEW and Matlab It also means that you don t need to have a precompiled API library specific to your compiler The FrontPanel DLL is provided as three files listed in the table below Filename Description okFrontPanel dll The FrontPanel DLL binary This file needs to be located with your ap plication executable or for third party software in the appropriate DLL location okFrontPanelDLL cpp This file contains the FrontPanel DLL stub functions for use within a C application that will call the DLL Many applications will not requi
103. the device and that implies owning the device Python API The Python API is built as an import library to be used with the Python interpreted programming language Python is a powerful extensible language with a clear syntax making it ripe for the FrontPanel API add on The Python API is built using the C API as a foundation so the simi larities are pervasive The Python API is compiled for each supported platform into a shared object file DLL under Windows or so under Linux and distributed along with a couple Python files that define the package The Python interpreter can access the API methods through this shared object and Python package Required Files The Python API distribution includes four files as listed below www opalkelly com 23 FrontPanel User s Manual e init__ py e __version__ py e ok py e _ok dll Windows e _ok so Linux Mac OS X These four files need to be in the current working directory where Python is started Alterna tively they may be added to the Python site packages directory within your Python distribution Refer to the Python manual to see how this is done Example Usage Using the API from Python is quite easy and can be done scripted or interactively Below is an example interaction with the Counters sample project import ok xem ok FrontPanel O pll ok PLL221500 xem GetEepromPLL22150cConfiguration p11 xem SetPLL22150Configuration p11 p11 GetoutputFrequency 0 0
104. tutorial www opalkelly com 71 FrontPanel User s Manual 72 www opalkelly com FrontPanel User s Manual Appendix A A Simple Example This basic example quickly introduces the basic concepts of the Wire In and Wire Out endpoints by linking real and virtual pushbut tons to real and virtual LEDs The XML and HDL descriptions are short and concise making this example a great place to start with FrontPanel This sample is designed to work with the XEM3001 The First FrontPanel sample contains the following files File Description S First xfp FrontPanel profile text readable XML first bit Xilinx configuration file produced from ISE Verilog First ise Xilinx ISE Navigator project file Verilog First v Verilog description of the project s toplevel Verilog First ucf Xilinx constraints file containing pin location constraints When the profile is loaded into FrontPanel it creates a user interface that looks like this First FrontPanel Example El QUEUE DE E E EIA www opalkelly com 73 FrontPanel User s Manual Toplevel Description 74 The file Firstv contains the Verilog description of the project including all pins which are physi cally connected to the FPGA It s entire contents are listed below module toplevel input wire 7 0 hi_in input wire 1 0 hi_out inout wire 15 0 hi_inout output wire 7 0 led input wire 3 0 button Target interface bus wire ti_clk wire 30 0 o
105. tyle gt RAISED_BORDER ALIGN_CENTER lt sty1e gt lt trigger gt lt endpoint gt 0x60 lt endpoint gt lt bit gt 1 lt bit gt lt message gt Your laundry is done lt message gt lt delay gt 0 5 lt delay gt lt background gt ff0000 lt background gt lt foreground gt ffffff lt foreground gt lt trigger gt lt trigger gt lt endpoint gt 0x61 lt endpoint gt lt bit gt 0 lt bit gt lt message gt Elvis the cat has left the building lt message gt lt trigger gt lt object gt okFilePipe Pipe In Pipe Out Trigger In This component provides simple binary file transfer capability through the use of Pipe In or Pipe Outs The type In or Out is automatically determined by the endpoint address The component appears as a pushbutton on your panel that can be clicked to initiate the transfer If no filename is provided the user will be prompted with a File Dialog to select an appropriate input or output file If a filename is provided for Pipe In but the file does not exist the user will also be prompted In the case of a Pipe In the filename parameter provides an input file The entire contents of the file are transferred to the Pipe In The transfer proceeds in chunks of 64kB until the entire file has been transferred In the case of a Pipe Out a length parameter must be provided to tell FrontPanel how many bytes to read from the FPGA The transfer proceeds in chunks of 64kB until the full length has been read a
106. utton okStaticBox FrontPanel Example 1 okStaticText z L gt okPushbutton EE ATA O 7 4 3 0 okToggleButton Togale Check okSlider okToggleCheck EP22 7 4 EP22 3 0 okPanel okDigitEntry okHex www opalkelly com 49 FrontPanel User s Manual okStaticText This is a simple control to display static text within a panel Element Type Description 222222222 POSITION Position of the top left corner SIZE label TEXT Label text XML Example lt object class okStaticText gt lt label gt Disable lt label gt lt position gt 90 25 lt position gt lt size gt 60 20 lt size gt lt object gt okStaticBox This is a simple control to display static text within a panel It also displays a box which is helpful to distinguish parts of a control panel Element type Description SSS CET TEXT _ labeltex SSCS XML Example lt object class okStaticBox gt lt label gt Disable lt label gt lt position gt 90 25 lt position gt lt size gt 60 20 lt size gt lt object gt okPushbutton Wire In This component models a physical pushbutton and connects to a Wire In endpoint By default the pushbutton is unpressed and the corresponding wire is deasserted logic 0 When pressed the corresponding wire is asserted logic 1 The pushbutton does not hold its state that is to maintain a logic 1 you have to hold the pushbutton in its pressed state For an alternative compone
107. v1 Note 30 The first PCB revision of the XEM3001 date code 20040301 had an 8 bit host interface All newer implementations have a 16 bit interface For the purposes of this section the only things which change are the HI_DATA TI_DATA busses as well as the widths of the endpoint connec tions such as EP_DATAIN and EP_DATAOUT For the XEM3001v1 simply substitute an 8 bit bus in those places www opalkelly com FrontPanel User s Manual FPGA Resource Requirements The FrontPanel enabling modules have been designed to consume as few resources as possible within the FPGA The resource requirements for each block are listed in the tables below Keep in mind that these are requirements for an endpoint with all bits used In many cases the place and route tools will optimize and remove unused components e la LUTs RAMs Host Interface 32 33 49 ja jo wen m he m p b weon 7 fs b b Jo riggerin f sz a o o _ Trogerou i8 far is fe o ien po fe o jo b Peou h fo b b b The Host Interface The host interface is the gateway for FrontPanel to control and observe your design It contains relatively simple logic that lets the USB microcontroller on the XEM board communicate with the various endpoints within the design Exactly one host interface must be instantiated in any design which uses the FrontPanel components The Host Interface component is the only block which is synthesized with your design It con tains a
108. ve high write signal Data should be captured EP_READ Active high read signal Data must be provided in the when this signal is asserted cycle following as assertion of this signal ep_addr 8 h9c pipeIn9c okPipeIn port map okl gt okl ok2 gt ok2 ep_addr gt x 9C ep_dataout gt pipeData ep_write gt pipewrite okPipeIn pipeIn9c ok1 ok1 ep_dataout pipeData ep_write pipewrite 0k2 0k2 okPipe0ut pipeoutA3 ok1 ok1 ok2 ok2 ep_addr 8 ha3 ep_datain pipeData ep_read piperead pipe0utA3 okPipeOut port map okl gt okl ok2 gt ok2 ep_addr gt x A3 ep_datain gt pipeData ep_read gt pipeRead okBTPipeln okBTPipeOut Signal Direction Description Active high write signal Data should be captured when this signal is asserted Signal Direction Description EP_DATAIN 15 0 Input Pipe data input EP_READ Output Active high read signal Data must be provided in the cycle following as assertion of this signal Active high block strobe EP_BLOCKSTROBE Output Active high block strobe EP_READY Active high ready signal EP_READY Input Active high ready signal ep_addr 8 h9c okBTPipeIn pipeIn9c ok1 ok1 ep_dataout pipeData ep_write pipewrite ep_blockstrobe pipestrobe ep_ready pipeReady 0k2 0k2 okBTPipe0u
109. ween the host PC and the target FPGA The okHostInterface supports up to 32 Wire In endpoints and 32 Wire Out endpoints connected to it To save bandwidth all Wire In or Wire Out endpoints are updated at the same time and written or read by the host in one block All Wire In to FPGA endpoints are updated by the host at the same time with the call Up dateWirelns Prior to this call the application sets new Wire In values using the API method SetWirelnValue The SetWirelnValue simply updates the wire values in a data structure inter nal to the API UpdateWirelns then transfers these values to the FPGA All Wire Out from FPGA endpoints are likewise read by the host at the same time with a call to UpdateWireOuts This call reads all 32 Wire Out endpoints and stores their values in an inter nal data structure The specific endpoint values can then be read out using GetWireOutValue Note UpdateWirelns and UpdateWireOuts also latch all wire endpoint data at the same time Therefore the data available on Wire Out endpoints are all captured synchronously with the tar get interface clock Similarly the data availble to Wire In endpoints is all latched synchronously with the target interface clock Triggers Triggers are used to communicate a singular event between the host and target A Trigger In provides a way for the host to convey a one shot on an arbitrary FPGA clock A Trigger Out provides a way for the FPGA to s
110. wnload 2 20000002 45 show Panels in Taskbal caco rie 46 Enable Asynchronous Transfers imac a advan Sauce ak ewe 46 Component XML 0 cece eee eee eee eee eee 47 AME acia ala rara de staan tsk AAS a aetna ahd 47 Basie Structure for FrontPanel cocoa a Rad 47 COMMENIS s566s5440 pide O04 o Sea RED eee eats 48 Start Tags and End TagS s ninia el dt da 48 Case SOnsSitVIY s c a did ad Ria a te 48 Element Data DES dias 49 Component TYPES ecseri otara ri nea ioe a Ses ESET HOE a swe d 49 ORSAI ara a A A a a aecant 50 OKSIAUCBOM 425426002 careta a ia 50 okPUSsAGUtON Wire lost dd 50 okToggleButton Wire In scccscscaeeau get aedereeeesaees a ae 51 kToggleCheck Wire IN cnisnraiacd ari tetas itera ok Soars ad 51 OK DIGI Nt Y Wire A camara odia dae 52 OKSIOEr Wie listas eater aes wats tesa has Res Santee ee 53 okCombobox Wire IM rast essrer iscr ccc eee nee 53 KUED WIE QUI a sir ee 54 kHex Wire QU 2s02 chet apa sate a lia eee eae 54 okDigitDisplay Wire QU o 22215252422 idad abridor 55 OkGauge Wire OUL s 2cavccasacraee wa a o 56 okTriggerButton Trigger In aasa anaana 56 okTriggerSound Trigger Out ocviconiin Dra dvb ew ace Res 57 okTriggerLog Trigger Out a na aaa aaa a a aa 57 okTriggerMessage Trigger Out Vesigiacisiasan daba 57 okFilePipe Pipe In Pipe Out Trigger IN 262 2068 eek eee eee ee 58 OkPLE Z SM tiara idas 59 OKPLL2Z2093 2 6 2 2 t20d 5 claridad a ira 60 okKeyPanel Wire In

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