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uPD78054, 78054Y SUBSERIES 8-BIT SINGLE

1. j A m B D ml la 1 TR N iQ g 4 dt tQ TU Lu k a sas ERE TS qo 2 screw e b Hi iA u 2 6 A GFE NZ a 2 1 1 f Fen 6 aci loc CAE a F iO ED 4 iO 2 K L W 2 1JJJ LLLM X Y 9 f ju r t i i if s hid Bey Z Pl Protrusion 4 places k n I ITEM MILLIMETERS INCHES ITEM MILLIMETERS INCHES A 18 0 0 709 a 0 5x19 9 540 10 0 020 0 748 0 374 0 004 B 11 77 0 463 b 0 25 0 010 C 0 5x19 9 5 0 020x0 748 0 374 95 3 90 209 D 0 5 0 020 d 5 3 90 209 0 5 19 9 5 0 020x0 748 0 374 e 01 3 60 051 F 11 77 0 463 f 3 55 00 140 G 18 0 0 709 g 00 3 90 012 H 0 5 0 020 h 1 85 0 2 0 073 0 008 1 1 58 0 062 i 3 5 0 138 J 1 2 0 047 i 2 0 0 079 K 7 64 0 301 k 3 0 0 118 L 1 2 0 047 0 25 0 010 1 58 0 062 14 0 0 551 1 58 0 062 n 1 4 0 2 0 055 0 008 1 2 0 047 1 4 0 2 0 055 0 008
2. 22 1 External Device Expansion Functions l U U u nnns 22 2 External Device Expansion Function Control Register 22 3 External Device Expansion Function Timing J J 22 4 Example of Connection with Memory u u u u CHAPTER 23 STANDBY FUNCTION u u uu uu u u u 22 23 4 Standby Function and Configuration 23 1 1 Standby functiori ree retener e sevens ese 23 1 2 Standby function control register 23 2 Standby Function Operations l U u uu u uu u u 23 2 1 p Rut 23 2 2 S9TOP ImOQO 6 1o CHAPTER 24 RESET 24 1 Reset Function CHAPTER 25 ROM 0 4 uu u u ROM Correction Functions ROM Correction Configuration
3. 270 14 4 A D Converter Input Select Register 271 14 5 External Interrupt Mode Register 1 272 14 6 A D Converter Basic Operation eene enne nnne nennen entente rns 274 14 7 Relations between Analog Input Voltage and A D Conversion Result 275 14 8 A D Conversion by Hardware Start sss enne 276 14 9 A D Conversion by Software Start nennen neret enn nnne nennen rs 277 14 10 Example of Method of Reducing Current Dissipation in Standby Mode 278 14 11 Analog Input Pin DISDOSITIOD icio tette e ae rre Ye erg 279 14 12 A D Conversion End Interrupt Request Generation Timing 280 14 13 Handling of AVpb Pim tte atts reet ie e tient 280 15 1 D A Converter Block 11000 enne 282 15 2 D A Converter Mode Register Format esssssssssseeeeeneneee nennen nnne nennen nnne nnn 284 15 3 Use Example of Buffer 286 16 1 Serial Bus Interface SBI System Configuration Example sse 289 16 2 Serial Interface Channel 0 Block Diagram 2 291 16 3 Timer Clock Select Register 3 Format u
4. 18 3 Serial Interface Channel 1 Control Registers 18 4 Serial Interface Channel 1 Operations cesses u u 18 441 Operation stop mode ee id e bete 18 4 2 3 serial I O mode operation a 18 4 3 3 wire serial I O mode operation with automatic transmit receive function CHAPTER 19 SERIAL INTERFACE CHANNEL 2 u u 19 1 Serial Interface Channel 2 2 4 nennen nnn 19 2 Serial Interface Channel 2 Configuration l u u 19 3 Serial Interface Channel 2 Control Registers 19 4 Serial Interface Channel 2 Operation 19 421 Op ration Stop Image eere ege ehe unquy Oni RM 19 4 2 Asynchronous serial interface UART 19 4 8 3 wire serial ModE riiintean r a aea Ta aeae aiaa nennen 19 4 4 Limitations when UART mode is used I CHAPTER 20 REAL TIME OUTPUT PORT 2 1 2 1 1 20 1 Real Time Output Port Functions U U u u uu u u 20 2 Real Time Output Port Configu
5. Internal clock Note2 SI2 SO2 CMOS output SO2 CMOS output 5 2 output 3 Asynchronous Serial Interface Mode Other than above CSIM2 CSIE2 CSIM22 Shift Clock Setting prohibited 70 512 P71 SO2 RxD Pin TxD Pin Functions Functions P72 SCK2 ASCK Pin Functions 0 0 External clock Internal clock P70 TxD CMOS output ASCK input P72 External clock Internal clock External clock Internal clock ASCK input P72 TxD CMOS output ASCK input Notes 1 Can be used freely as port function Other than above Setting prohibited 2 Can be used as P70 CMOS input output when only transmitter is used Remark x Don t care PMxx Port mode register Pxx Port output latch 446 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 3 Asynchronous serial interface status register ASIS This is a register which displays the type of error when a reception error is generated in the asynchronous serial interface mode ASIS is read with a 8 bit memory manipulation instruction In 3 wire serial mode the contents of the ASIS are undefined RESET input sets ASIS to 00H Figure 19 5 Asynchronous Serial Interface Status Register Format Symbol 7 6 Address After Reset R W 5 4 3 2 1 0
6. U u u u uuu uu u ROM Correction Control Registers u u uu u ROM Correction Application l u u u uu ROM Correction Example Program Execution Flow eene Cautions on ROM Correction U u u uu uu u 25 1 25 2 25 3 25 4 25 5 25 6 25 7 CHAPTER 26 UPD78P054 78 058 1 5 26 1 Memory Size Switching Register uPD78P054 Memory Size Switching Register uPD78P058 Internal Expansion RAM Size Switching Register reote rea u 26 2 26 3 26 4 26 5 26 6 26 7 26 4 1 Operating MOCES n 26 4 2 PROM write procedure ssessssseesesseee e ennemis S n nenne nennen 26 4 58 PROM reading procedure nennen nennen ennne Erasure Procedure uPD78P054KK T and 78PO58KK T Only Opaque Film Masking the Window uPD78P054KK T and 78P058KK T Only Screening of One Time PROM Versions l CHAPTER
7. P26 SO0 SB1 Individually connect to Vpp or Vss via a Input Output P27 SCKO resistor P30 TOO P31 TO1 P32 TO2 P33 TI1 P34 TI2 P35 PCL P36 BUZ P37 P40 ADO to P47 AD7 Input Output Individually connect to Voo via a resistor Individually connect to or Vss via a P50 A8 to P57 A15 Input output resistor CHAPTER 3 PIN FUNCTION uPD78054 Subseries 72 Table 3 1 Pin Input Output Circuit Types 2 2 Input Output Circuit Type P60 to P63 Mask ROM version P60 to P63 PROM version Input Output Input output Recommended Connection of Unused Pins Individually connect to Voo via a resistor P64 RD P65 WR P66 WAIT P67 ASTB P70 SI2 RxD P71 SO2 TxD P72 SCK2 ASCK P120 RTPO to P127 RTP7 Input output Individually connect to Voo or Vss via a resistor P130 ANOO P131 ANO1 Input output Individually connect to Vss via a resistor RESET Input XT2 AVREFO AVREF1 AVop AVss IC Mask ROM version Ver PROM version Leave open Connect to Vss Connect to Connect to Vss Directly connect to Vss CHAPTER 3 PIN FUNCTION uPD78054 Subseries Figure 3 1 Pin Input Output Circuit of List 1 2 Schmitt Triggered Input with Hysteresis Characteristics pullup Vpp enable output disable 7
8. 219 x 1 fx 104 9 ms Main system clock frequency fx or fx 2 220 x 1 fx 209 7 ms 3 MCS Bit 0 of oscillation mode selection register OSMS 4 TCL20 to TCL22 Bits O to 2 of timer clock select register 2 TCL2 5 Figures in parentheses apply to operation with fx 5 0 MHz 254 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12 1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI Clocks selected with the timer clock select register 0 TCLO are output from the PCL P35 pin Follow the procedure below to output clock pulses 1 Select the clock pulse output frequency with clock pulse output disabled with bits 0 to TCLOO to 03 of TCLO 2 Set the P35 output latch to 0 3 Set bit 5 PM35 of port mode register 3 PM3 to 0 set to output mode 4 Set bit 7 CLOE of timer clock select register 0 TCLO to 1 Caution Clock output cannot be used when setting P35 output latch to 1 Remark When clock output enable disable is switched the clock output control circuit does not output pulses with small widths See the portions marked with in Figure 12 1 Figure 12 1 Remote Controlled Output Application Example PCL P35 Pin Output 255 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12 2 Clock Output Control Circuit
9. Si1 P20 Match ADTIO ADTI4 SO1 gt 4 e Roig PM23 0 2 e shake BUSY P24 ARLD 1o44 INTCSH Serial Clock Counter write gt Clear SCK1 c fo 2 fed28 P22 R E i Ta 5 LT PM22 P22 Output Latch TCL TCL TCL TCL 37 36 35 34 Timer Clock Select Register 3 Internal Bus 395 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 1 2 3 396 Serial I O shift register 1 SIO1 This is an 8 bit register to carry out parallel serial conversion and to carry out serial transmission reception shift operation in synchronization with the serial clock 5101 is set with an 8 bit memory manipulation instruction When the value in bit 7 CSIE1 of serial operating mode register 1 CSIM1 is 1 writing data to SIO1 starts serial operation In transmission data written to SIO1 is output to the serial output SO1 In reception data is read from the serial input SI1 to SIO1 RESET input makes SIO1 undefined Caution Do not write data to SIO1 while the automatic transmit receive function is activated Automatic data transmit receive address pointer ADTP This register stores value of the number of transmit data bytes 1 while the automatic transmit receive function is activated As data is transferred received it is
10. DAM5 DAM4 DACE 1 DACEO D A Converter Mode Register 5 Internal Bus 282 CHAPTER 15 D A CONVERTER 1 D A conversion value set register 0 1 DACSO DACS1 DACSO and DACS 1 are registers that set the values to determine analog voltage output to the ANOO and ANO1 pins respectively DACSO and DACS are set with 8 bit memory manipulation instructions RESET input sets these registers to Analog voltage output to the ANOO and ANO 1 pins is determined by the following expression DACSn 256 ANOn output voltage AVREr1 where n 0 1 Cautions 1 Inthe real time output mode when data that are set in DACSO and DACS 1 are read before an output trigger is generated the previous data are read rather than the set data 2 In the real time output mode data should be set to DACSO and DACS 1 after an output trigger and before the next output trigger 283 CHAPTER 15 D A CONVERTER 15 3 D A Converter Control Registers The D A converter mode register DAM controls the D A converter This register sets D A converter operation enable stop The DAM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to Figure 15 2 D A Converter Mode Register Format After Symbol 7 lt gt lt 0 Address Reset R W DACE0 D A Converter Channel 0 Control D A conversion stop D A conversion enable DACE1 D A Converter Channel 1 Control
11. R W SVAM SVA Bit to be Used as Slave Address 0 Bits 0 to 7 1 Bits 1 to 7 R W E INTCSIO Interrupt Factor SelectionNete 2 CSIIFO is set upon termination of serial interface channel 0 transfer CSIIFO is set upon bus release detection or termination of serial interface channel 0 transfer R 27 Pin LevelNetes 0 Low level 1 High level Notes 1 Bit 6 CLD is a read only bit 2 When using wake up function in the SBI mode set SIC to 0 3 When CSIEO 0 CLD becomes 0 Caution Be sure to set bits 0 to 3 to 0 Remark SVA Slave address register CSIIFO Interrupt request flag corresponding to INTCSIO CSIEO Bit 7 of serial operating mode register 0 CSIMO 318 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 4 Various signals Figures 16 20 to 16 25 show various signals and flag operations in SBI Table 16 3 lists various signals in SBI Figure 16 20 RELT CMDT RELD and CMDD Operations Master Slave address write to SIO0 Transfer Start Instruction SIO0 A SCKO RELT P 1 I ys X RELD Y CMDD E Figure 16 21 RELT and CMDD Operations Slave Write FFH to SIOO Transfer start instruction Transfer start instruction sion SS ea E SCKO 2 7 Slave address 5 0 SB1 RELD 319 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 320 Figure 16 22 ACKT Operatio
12. 132 6 3 Port Gonfigurationci u aq uum oa apa 134 6 4 Pull up Resistor of Port 6 144 6 5 Port Mode Register and Output Latch Settings when Using Dual Functions 151 6 6 Comparison between Mask ROM Version and PROM 157 7 1 Clock Generator Configuration u 159 7 2 Relationship between CPU Clock and Minimum Instruction Execution 163 7 3 Maximum Time Required for CPU Clock Switchover 40 172 8 1 Timer Event Counter Operations 176 8 2 16 Bit Timer Event Counter Interval Times T 177 8 3 16 Bit Timer Event Counter Square Wave Output Ranges 178 8 4 16 Bit Timer Event Counter Configuration sess 179 8 5 INTPO TIOO Pin Valid Edge and CROO Capture Trigger Valid Edge 181 8 6 16 Bit Timer Event Counter Interval Times T 193 8 7 16 Bit Timer Event Count Square Wave Output Ranges 2 2 2024 00 207 9 1 8 Bit Timer Event Counters 1 and 2 Interval 216 9 2 8 Bit Timer Event Counters 1 and 2 Squar
13. 247 11 2 Interval Times nie fite aed ete 248 11 3 Watchdog Timer Configuration 249 11 4 Watchdog Timer Runaway Detection Times u 253 11 5 Interval Timer 254 12 1 Clock Output Control Circuit Configuration nennen 256 13 1 Buzzer Output Control Circuit Configuration a 261 14 1 A D Converter Configuration u u h nia s ninas 265 15 1 D A Convert r Configurations ln 282 16 1 Differences between Channels 0 1 and 2 n nennen nennen nennen nennen 287 16 2 Serial Interface Channel 0 Configuration sesssssseseeeeeeeeenene ennemi 290 16 3 Various Signals in SBI Mode u a ett ere tee cote ec dte Due e ce ds 323 17 1 Differences between Channels 0 1 and 2 nennen nennen nennen nena 341 17 2 Serial Interface Channel 0 Configuration sesssssssseseeeeeeeenenen nennen enne 344 17 8 Serial Interface Channel 0 Interrupt Request Signal Generation 347 17 4 Signals in IC Bus Mode a r a a na e a a aaa E a 376 18 1 Serial Interface Channel 1 Configuration 394 18 2 Interval Timing Through CPU Processing when the internal clock is operating 436 18 3 Interv
14. IVIHIS 91 H3ldVHO 6c Figure 16 29 Data Transmission from Master Device to Slave Device Master Device Processing Transmitter Program Processing Hardware Operation Transfer Line SCKO Pin SBO SB1 Pin Slave Device Processing Receiver 9 C C Eiaon e Nea Gal Tarte seuesqns 608 047 0 13NNVHO 1VIH3S 9L H3ldVHO oee Figure 16 30 Data Transmission from Slave Device to Master Device Master Device Processing Receiver Program Processing Vaso eroe data processing i SCKO 510 Serial Hardware Operation Sip Serial Reception Reception Transfer Line SCKO Pin SBO SB1 Pin BUSY READY Slave Device processing Transmitter seuesqns 508 0 17 0 14 1VIH3S 91 HaldVHO CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 9 Transfer start Serial transfer is started by setting transfer data to the serial I O shift register 0 SIOO when the following two conditions are satisfied Serial interface channel 0 operation control bit CSIEO 1 Internal serial clock is stopped or SCKO is at high level after 8 bit serial transfer Cautions 1 If CSIEO is set to 1 after data write to SIOO transfer does not start 2 Because the N ch open drain output must be high impedance state for data reception write FFH to SIOO in advance However when the
15. Remark MCS Oscillation mode selection register bit 0 459 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 ii Generation of baud rate transmit receive clock by means of external clock from ASCK pin The transmit receive clock is generated by scaling the clock input from the ASCK pin The baud rate generated from the clock input from the ASCK pin is obtained with the following expression fasck 4 Baud rate where fasck Frequency of clock input to ASCK pin k Value set in MDLO to MDL3 0 lt k x 14 Table 19 6 Relation between ASCK Pin Input Frequency and Baud Rate When BRGC is set to 00H 460 Baud Rate bps ASCK Pin Input Frequency 2 4 kHz 3 52 kHz 4 8 kHz 9 6 kHz 19 2 kHz 38 4 kHz 76 8 kHz 153 6 kHz 307 2 kHz 614 4 kHz 1000 0 kHz 1228 8 kHz CHAPTER 19 SERIAL INTERFACE CHANNEL 2 2 Communication operation a Data format The transmit receive data format is as shown in Figure 19 7 Figure 19 7 Asynchronous Serial Interface Transmit Receive Data Format One Data Frame gt C _ Character Bits 2 l One data frame consists of the following bits Start bits 1 bit Character bits 7 bits 8 bits e Parity bits Even parity odd parity O parity no parity Stop bit s 1 bit 2 bits The character bit length parity and stop bit length for each data f
16. 12 1 Clock Output Control Circuit Functions l l u u u u 12 2 Clock Output Control Circuit Configuration 12 3 Clock Output Function Control Registers J l l u u 1 20 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT J J 261 13 1 Buzzer Output Control Circuit Functions seen 261 13 2 Buzzer Output Control Circuit Configuration a 261 13 3 Buzzer Output Function Control Registers 40 262 CHAPTER 14 A D 265 14 1 A D Converter Functions 12 22 u u u u 265 14 2 A D Converter Configuration U uu uu u u u 265 14 3 A D Converter Control Registers U u u u u J 269 14 4 A D Converter Operations U u u uu u u u u u T 273 14 4 1 Basic operations of A D converter 273 14 4 2 Input voltage and conversion results a 275 14 4 3 A D converter operating 276 14 5 A D Converter Qaulllghgu ll I ete 278 CHAP
17. AX AX laddr16 E AX lt addr16 laddr16 AX E addr16 AX rp AX rp 8 bit A byte A CY A byte saddr byte saddr CY lt saddr byte lt saddr A saddr A laddr 6 A CY A addr16 HL A CY lt A HL byte A HL byte A HL B A CY A HL A CY amp A HL A HL C A CY lt HL C operation A byte A CY A byte CY saddr byte saddr CY lt saddr byte CY A CYc A r 4OCY r CY r A A CY A saddr CY A laddr 6 NIM O N N NIN A CY A addr16 CY HL A CY A HL CY HL byte A CY A HL byte CY HL B A CY HL CY AJAJAJ jO OC Oo O N hw HL C HL C CY Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed 3 Only when rp BC DE or HL 4 Except r A Remarks 1 One instruction clock cycle is one cycle of the CPU clock
18. I N N O N I ININ IN lt A addr16 A lt HL lt A HL byte A lt HL B OO O RHR oO O Oo l Oo Oo oo O N 9 N A lt HL byte byte CY 1 2 When an area except the internal high speed RAM area is accessed 3 Except r A When the internal high speed RAM area is accessed or instruction with no data access Remarks 1 One instruction clock cycle is one cycle of the CPU clock fceu selected by the processor clock control register PCC 2 This clock cycle applies to internal ROM program 3 n is the number of waits when external memory expansion area is read from 566 27 INSTRUCTION SET Instruction Group Mnemonic Operands A byte Operation A A v byte saddr byte saddr saddr v byte A r AcAvr rr v A saddr A A v saddr A laddr 6 lt A v addr16 HL lt A v HL byte A HL byte A HL B amp A v HL A A v HL B A HL C A A v HL 8 bit operation A byte A lt v byte saddr byte saddr saddr v byte A r AcAvr rervA A saddr A saddr
19. Other than above Setting prohibited Remarks 1 fx Main system clock oscillation frequency 2 MCS Oscillation mode selection register OSMS bit 0 3 TCL10 to TCL13 Bits 0 to 3 of timer clock select register 1 TCL1 4 Values in parentheses when operated at fx 5 0 MHz 229 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 AND 2 Table 9 7 8 Bit Timer Event Counter 2 Interval Time Minimum Interval Time Maximum Interval Time Resolution TCL16 TCL15 TCL14 TI2 input cycle 28 x TI2 input cycle TI2 input edge cycle TI2 input cycle 28 x TI2 input cycle TI2 input edge cycle 2 x 1 fx 2 x 1 fx 29 x 1 fx 210 x 1 fx 2 x 1 fx 2 x 1 fx 400 ns 800 ns 102 4 us 204 8 us 400 ns 800 ns 22 x 1 fx 23 x 1 fx 210 x 1 fx 211 x 1 fx 22 x 1 fx 23 x 1 fx 800ns 1 6 204 8 us 409 6 us 800ns 1 6 us 23 x 1 fx 24 x 1 fx 211 x 1 fx 212 x 1 fx 23 x 1 fx 24 x 1 fx 1 6 us 3 2 us 409 6 us 819 2 us 1 6 us 8 2 us 24 x 1 fx 25 x 1 fx 212 x 1 fx 213 x 1 fx 24 x 1 fx 2 x 1 fx 8 2 us 6 4 us 819 2 us 1 64 ms 3 2 us 6 4 us 25 x 1 fx 26 x 1 fx 213 x 1 fx 214 x 1 fx 25 x 1 fx 26 x 1 fx 6 4 us 128 1 64 ms 3 28 ms 6 4us 12 8 us 26 x 1 fx 27 x 1 fx 214 x 1 fx 215 x 1 fx 26 x 1 fx 27 x 1 fx 12 8 25 6 8 28 ms 6 55 ms 12 8 us 25 6 us 27 x 1 fx 28 x 1 fx 215 x 1 fx 218 x 1 fx 27 x 1 fx 28 x 1 fx 25 6 us 51 2 us 6 55 ms 1
20. Remark SVA Slave address register CSIIFO Interrupt request flag corresponding to INTCSIO CSIEO Bit 7 of serial operating mode register 0 CSIMO 375 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 4 Various signals A list of signals in the 12 bus mode is given in Table 17 4 Table 17 4 Signals in 2 Bus Mode Signal name Description Start condition Definition SDAO SDA1 falling edge when SCL is highNote 1 Function Indicates that serial communication starts and subsequent data are address data Signaled by Master Signaled when is set Affected flag s CMDD is set Stop condition Definition SDAO SDA1 rising edge when SCL is highNote 1 Function Indicates end of serial transmission Signaled by Master Signaled when is set Affected flag s RELD is set and CMDD is cleared Acknowledge signal ACK Definition Low level of SDAO SDA1 pin during one SCL clock cycle after serial reception Function Indicates completion of reception of 1 byte Signaled by Master or slave Signaled when ACKT is set with 1 Affected flag s ACKD is set Wait WAIT Definition Low level signal output to SCL Function Indicates state in which serial reception is not possible Signaled by Slave Signaled when WAT1 1x Affected flag s None Serial Clock SCL Definition Synchronization clock for output of various signals Funct
21. i Special Function Registers SFRs 256 x 8 bits General Registers 32 x 8 bits Internal High speed RAM 1024 x 8 bits FB00H FAFFH Reserved FAE0H FADFH 9FFFH Internal Buffer RAM 32 x 8 bits Program Area Data memory FABFH 1000H space FA80H Reserved A FA7FH CALLF Entry Area 0800H External Memory 07 23168 x 8 bits Program Area Program memory 0080H 007 A000H CALLT Table Area Internal ROM 40960 x 8 bits Vector Table Area Y Y 0000H 0000H CHAPTER 5 CPU ARCHITECTURE Figure 5 6 Memory Map uPD78056 78056Y Data memory space Special Function Registers SFRs 256 x 8 bits General Registers 32 x 8 bits Internal High speed RAM 1024 x 8 bits Reserved FADFH BFFFH Internal Buffer RAM 32 x 8 bits Program Area FACOH FABER 1000H eserve FA80H OBREN FA7FH CALLF Entry Area 0800H External Memory 07FFH 14976 x 8 bits Program Area Program memory 0080H ard 007FH C000H adis CALLT Table Area Internal ROM SEEN 49152 x 8 bits Vector Table Area 0000H 0000H 96 CHAPTER 5 CPU ARCHITECTURE Figure 5 7 Memory Map uPD78058 78058Y Special Function Registers SFRs 256 x 8 bits General Registers 32 x 8 bits Internal High speed RAM 1024 x 8 bits FBOOH
22. Correction branch request signal BR 7FDH ORENn CORSTn Correction control register Internal bus 0 1 537 CHAPTER 25 ROM CORRECTION 1 Correction address registers 0 and 1 CORADO CORAD1 These registers set the start address correction address of the instruction s to be corrected in the mask ROM The ROM correction corrects two places max of the program Addresses are set to two registers CORADO and CORAD1 If only one place needs to be corrected set the address to either of the registers CORADO CORAD are set with a 16 bit memory manipulation instruction RESET input sets CORADO and CORAD1 to 0000H Figure 25 2 Correction Address Registers 0 and 1 Format Symbol 15 0 Address State R W after reset Cautions 1 Setthe CORADO and CORAD1 when bit 1 CORENO and bit 3 COREN1 of the correction control register CORCN see Figure 25 3 are 0 2 Only addresses where operation codes are stored can be set in CORADO and CORAD1 3 Do not set the following addresses to CORADO and CORAD1 Address value in table area of table reference instruction CALLT instruction 0040H to 007FH Address value in vector table area 0000H to 003FH 2 Comparator The comparator always compares the correction address value set in correction address registers 0 and 1 CORADO CORAD 1 with the fetch address value When bit 1 CORENO or bit 3 COREN1 of the correction control
23. 2 bus mode transmit 0 0 1 An interrupt request signal is generated each time 8 serial clocks are counted 8 clock wait Normally during transmission the settings WAT21 WATO 1 0 are not used They are used only when wanting to coordinate receive time and processing systematically using software ACK information is generated by the receiving side thus should be set to 0 disable An interrupt request signal is generated each time 9 serial clocks are counted 9 clock wait ACK information is generated by the receiving side thus should be set to 0 disable Other than abov Setting prohibited 12 bus mode receive 1 0 1 An interrupt request signal is generated each time 8 serial clocks are counted 8 clock wait ACK information is output by manipulating ACKT by software after an interrupt is generated An interrupt request signal is generated each time 9 serial clocks are counted 9 clock wait To automatically generate ACK information preset ACKE to 1 before transfer start However in the case of the master set to 0 disable before receiving the last data After address is received if the values of the serial I O shift register 0 6100 and the slave address register SVA match and if the stop condition is detected an interrupt request signal is generated To automatically generate ACK information preset ACKE to 1 enable before transfer start
24. 550 26 5 Value Set to the Internal Expansion RAM Size Switching Register 551 26 6 PROM Programming Operating Modes essssssseeeeeeeeeeenenenneenren nennen nnne 552 27 1 Operand Identifiers and Description 562 A 1 Major differences between uPD78054 78054Y Subseries and uPD78058F 78058FY S bseri amp s tegunt n tene 578 B 1 OS forIBM PG iiit ata ERR TE ce LE HER eee e HEC u e e ds 589 B 2 Upgrading Former In circuit Emulators for 78K 0 Series to IE 78001 R A 589 35 36 CHAPTER 1 GENERAL uPD78054 Subseries 1 1 Features O OOO On chip high capacity ROM and RAM Program Memory Data Memory Part Number ROM Internal High Speed RAM Internal Buffer RAM Internal Expansion RAM uPD78052 16 Kbytes 512 bytes 32 bytes uPD78053 24 Kbytes 1024 bytes uPD78054 32 Kbytes uPD78P054 32 KbytesNote 1024 bytesNotet uPD78055 40 Kbytes 1024 bytes uPD78056 48 Kbytes uPD78058 60 Kbytes 1024 bytes uPD78P058 60 KbytesNotet 1024 bytesNete 1024 bytesNote2 Notes 1 The capacities of internal PROM and internal high speed RAM can be changed by means of the memory size switching register IMS 2 The capacity of internal high speed RAM can be changed by means of the internal expansion RAM size switchi
25. Other than above Setting prohibited Remark BSYE Bit 7 of serial bus interface control register SBIC ACKE Bit 5 of serial bus interface control register SBIC 347 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 17 3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0 Timer clock select register 3 TCL3 Serial operating mode register 0 CSIMO Serial bus interface control register SBIC Interrupt timing specify register SINT 1 Timer clock select register 3 TCL3 This register sets the serial clock of serial interface channel 0 TCL3 is set with an 8 bit memory manipulation instruction RESET input sets TCL3 to 88H 348 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries Symbol 7 6 5 TCL32 TCL31 Figure 17 3 Timer Clock Select Register 3 Format 4 3 2 1 0 L34 TCL33 TCL32 TCL31 TCL30 TCL30 Serial Interface Channel 0 Serial Clock Selection Address TCL37 TCL36 TCL35 TC 4 After Reset R W 88H R W 25 Serial Clock 2 Bus Mode Serial Clock in 2 Wire or 3 Wire Serial I O Mode MCS 1 Setting prohibited MCS 0 fx 28 78 1 kHz MCS 1 Setting prohibited MCS 0 522 1 25 MHz fxx 28 fx 28 78 1 kHz fx 27 39 1 kHz 522 1 25 MHz fx 23 625 kHz fxw 2 fx 27 39 1 kHz fx 28 19 5 kHz
26. Single chip mode Port mode 256 byte Port mode mode P64 RD buo Port mode mu Memory mode P65 WR expansion ADO AD7 mode 16 Kbyte P66 WAIT mode Port mode P67 ASTB Full Note address A14 A15 mode Setting prohibited No wait Wait one wait state insertion Setting prohibited Wait control by external wait pin Note The full address mode allows external expansion for all areas of the 64 Kbyte address space except the internal ROM RAM SFR and use prohibited areas Remarks 1 P60 to P63 pins enter the port mode in both the single chip and memory expansion mode 2 Besides setting port 4 input output MM also sets the wait count and external expansion area 154 CHAPTER 6 PORT FUNCTIONS 4 Key return mode register KRM This register sets enabling disabling of standby function release by a key return signal falling edge detection of port 4 KRM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets KRM to 02H Figure 6 22 Key Return Mode Register Format After Symbol 7 6 5 4 3 2 1 0 Address Reset R W ewe o o o o mw nw KRIF Key Return Signal Detection Flag 0 Not Detected 1 Detected Falling edge detection of port 4 Standby Mode Control by Key Return Signal 0 Standby mode release enabled 1 Standby mode release disabled
27. a Overrun Error Flag 0 1 Overrun error not generated Overrun error generatedNote 1 When next receive operation is completed before data from receive buffer register is read Framing Error Flag Framing error not generated Framing error generatedNete 2 When stop bit is not detected Parity error not generated Parity error generated When transmit data parity does not match Notes 1 Thereceive buffer register RXB must be read when an overrun error is generated Overrun errors will continue to be generated until RXB is read 2 Even if the stop bit length has been set as 2 bits by bit 2 SL of the asynchronous serial interface mode register ASIM only single stop bit detection is performed during reception 447 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 4 Baud rate generator control register BRGC This register sets the serial clock for serial interface channel 2 BRGC is set with an 8 bit memory manipulation instruction RESET input sets BRGC to 00H Figure 19 6 Baud Rate Generator Control Register Format 1 2 Symbol 7 6 5 4 3 Address After Reset R W 2 1 0 BRGC TPS3 52 TPS1 50 MDL3 MDL2 MDL1 MDLO FF73H 00H R W MDLO Baud Rate Generator Input Clock Selection k fsck 16 fsc 17 18 19 fsck 20 fsck 21 fsck 22 fsck 23 fsck 24 fsck 25 fsck 26 fsck 27 fsck 28 fsck 29 fsck
28. with automatic transmit receive function 3 wire UART uPD780034Y 8K to 32K UART 3 wire 12 bus supports multi master uPD78018FY 8K to 60K 3 wire 2 wire I C 3 wire with automatic transmit receive function uPD78014Y 8K to 32K 3 wire 2 wire I C 3 wire with automatic transmit receive function uPD78002Y 8K to 16K 3 wire 2 wire SBI I2C 780308 48K to 60K 3 wire 2 wire I C 3 wire time division UART 3 wire uPD78064Y 16K to 32K 3 wire 2 wire I C 3 wire UART uPD780024Y Remark The functions except serial interface are common with subseries without Y 55 CHAPTER 2 OUTLINE uPD78054Y Subseries 2 7 Block Diagram 0 00 00 TIO1 INTP1 PO1 TO1 P31 1 TO2 P32 TI2 P34 510 5 0 50 0 25 SOQ SB1 SDAt P26 SCKO SCL P27 SI1 P20 SO1 P21 SCK1 P22 STB P23 BUSY P24 SI2 RxD P70 SO2 TxD P71 SCK2 ASCK P72 ANIO P10 ANI7 P17 AVop AVss AVntro ANOO P130 131 AVss AVnert INTPO POO INTP6 P06 BUZ P36 PCL P35 16 bit TIMER EVENT COUNTER 8 bit TIMER EVENT COUNTER 1 8 bit TIMER EVENT COUNTER 2 WATCHDOG TIMER WATCH TIMER SERIAL INTERFACE 0 SERIAL INTERFACE 1 SERIAL INTERFACE 2 A D CONVERTER D A CONVERTER INTERRUPT CONTROL BUZZER OUTPUT CLOCK OUTPUT PORT 0 PORT 1 POR 1 POR 1
29. 139 2 us 0 5 fsck 142 4 us 1 5 fsck 164 8 us O 5 fsck 168 0 us 1 5 fsck 190 4 us 0 5 fsck 193 6 us 1 5 fsck 216 0 us 0 5 219 2 us 1 5 fsck 241 6 us 0 5 fsck 244 8 1 5 fsck 267 2 us O 5 fsck 270 4 us 1 5 fsck 292 8 us 0 5 fscK 296 0 us 1 5 fsck 318 4 us 0 5 fsck 321 6 us 1 5 fsck 344 0 us 0 5 fsck 347 2 us 1 5 fsck 369 6 us 0 5 fsck 372 8 us 1 5 fsck 395 2 us 0 5 fsck 398 4 us 1 5 fsck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 420 8 us 0 5 fsck Notes 1 The interval is dependent only on CPU processing 2 Cautions Remarks 424 0 us 1 5 fsck The data transfer interval includes an error The data transfer minimum and maximum intervals are found from the following expressions n Value set in ADTIO to ADTI4 However if a minimum which is calculated by the following expressions is smaller than 2 fsck the minimum interval time is 2 fsck 6 Minimum n 1 x 28 0 5 fxx fxx fsck 6 Maximum n 1 x 2 36 LES fxx fxx fsck 1 Do not write data to ADTI during operation of automatic data transmit receive function 2 Bits 5 and 6 must be set to zero 3 To control the data transfer interval by means of automatic transmission reception with ADTI busy control refer to 18 4 3 4 a Busy control option is dis
30. Paragraph 2 Memory size switching register IMS was added in section 19 2 CHAPTER 19 External Device Expansion Function Embedded software were added APPENDIX Embedded Software LPD78055 and 78P058 were added as new devices LPD78054Y subseries devices were added Throughout the manual Pin I O circuits and unused pin connections were changed CHAPTER 3 Pin Function uPD78054 Subseries Caution on oscillation mode switching was added Parts of list of maximum required time for switching CPU clock types were corrected CHAPTER 7 Clock Generator Available frequencies for 16 bit timer register count clock were changed CHAPTER 8 16 bit Timer Event Counter Caution on pulse width measurement operations was added Timing chart for one shot pulse output operation was corrected Section 15 4 Operations of D A Converter was added Section 15 5 Cautions Related to D A Converter was added CHAPTER 15 D A Converter Condition under which acknowledge detection flag ACKD is cleared was changed Timing chart for RELD and CMDD operations slave was corrected CHAPTER 16 Serial Interface Channel 0 uPD78054 Subseries Description on automatic transmit receive interval time was corrected CHAPTER 18 Serial Interface Channel 1 List of operation mode settings was corrected CHAPTER 19 Serial Interface Channel 2 Flowchart for non maskabl
31. Real time Output port Mode Register RTPM Output Latch P127 P120 478 CHAPTER 20 REAL TIME OUTPUT PORT 1 Real time output buffer register RTBL RTBH Addresses of RTBL and RTBH are mapped individually in the Special function register SFR area as shown in Figure 20 2 When specifying 4 bits x 2 channels as the operating mode data are set individually in RTBL and RTBH When specifying 8 bits x 1 channel as the operating mode data are set to both RTBL and RTBH by writing 8 bit data to either RTBL or RTBH Table 20 2 shows operations during manipulation of RTBL and RTBH Figure 20 2 Real time Output Buffer Register Configuration Higher Lower 4 Bits 4 Bits Table 20 2 Operation in Real time Output Buffer Register Manipulation Register to be In Read Note In Write Note2 Manipulated Higher 4 Bits Lower 4 Bits Higher 4 Bits Lower 4 Bits Operating Mode Invalid RTBL 4 Bits x 2 Channels RTBH Invalid RTBH RTBL 8 Bits x 1 Channel RTBH RTBL Notes 1 Only the bits set in the real time output port mode can be read When a bit set in the port mode is read 0 is read 2 After setting data in the real time output port output data should be set in RTBL and RTBH by the time a real time output trigger is generated 479 CHAPTER 20 REAL TIME OUTPUT PORT 20 3 Real Time Output Port Control Registers The following three registers co
32. SCK0 P27 O 339 340 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries The uPD78054Y subseries incorporates three channels of serial interfaces Differences between channels 0 1 and 2 are as follows Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1 Refer to CHAPTER 19 SERIAL INTERFACE CHANNEL 2 for details of the serial interface channel 2 Table 17 1 Differences between Channels 0 1 and 2 Serial Transfer Mode Clock selection Channel 0 fxx 2 fxx 22 fxx 23 fxx 24 fxx 25 26 fxx 27 fxx 28 external clock TO2 output Channel 1 fxx 2 fxx 22 fxx 23 fxx 24 fxx 25 26 27 fxx 28 external clock TO2 output Channel 2 Baud rate generator output 3 wire serial I O Transfer method MSB LSB switchable as the start bit MSB LSB switchable as the start bit Automatic transmit receive function MSB LSB switchable as the start bit Transfer end flag Serial transfer end interrupt request flag CSIIFO Serial transfer end interrupt request flag CSIIF1 Serial transfer end interrupt request flag SRIF 2 bus Inter IC Bus 2 wire serial I O Use possible UART Asynchronous serial interface None None Use possible 341 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 17 1 Serial Interface Channel 0 Functions Serial int
33. Simultaneously generated high priority interrupt requests Interrupt request reserve No Yes Interrupt request reserve No Yes Interrupt request reserve Vectored interrupt servicing Flag to control acknowledgment of maskable interrupt request 1 enable 0 disable Flag to indicate the priority of interrupt currently being serviced 0 servicing interrupt of high priority 1 2 not acknowledging interrupt request or servicing interrupt of low priority 501 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21 14 Interrupt Request Acknowledge Timing Minimum Time 6 Clocks 2 PSW PC Save CPU Processing Instruction Instruction Jump to Interrupt ervicing Interrupt Servicing Program x x PR 1 8 Clocks x x PR 0 7 Clocks Remark 1 clock LO fcpu CPU clock fcPu Figure 21 15 Interrupt Request Acknowledge Timing Maximum Time 25 Clocks 6 Clocks 3 I PSW and PC Save CPU Processing Instruction Divide Instruction Jump to Interrupt ervicing Interrupt Servicing Program x x PR 1 gt 33 Clocks x x PR 0 32 Clocks Remark 1 clock fcpu CPU clock CPU 502 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21 4 3 Software interrupt request acknowledge operation A software interrupt request is acknowledged by BRK instruction execution Software interrupt cannot be dis
34. a 516 22 3 Memory Size Switching Register Format u 517 22 4 Instruction Fetch from External 519 22 5 External Memory Read 0 520 22 6 External Memory Write 521 22 7 External Memory Read Modify Write 522 22 8 Connection Example of uPD78054 and Memory sse ennemi 523 23 1 Oscillation Stabilization Time Select Register 526 23 2 HALT Mode Clear upon Interrupt Request Generation a 528 31 LIST OF FIGURES 8 8 Figure No Title Page 23 3 HALT Mode Release by RESET Input terere 529 23 4 STOP Mode Release by Interrupt Request Generation 531 23 5 Release by STOP Mode RESET Input scsccscsccsssessssescesescesescesessesesceneseseseseesesessesesseseeses 532 24 1 Block Diagram oft Reset FU FCtIOn sei cete t GE Ree ted 533 24 2 Timing of Reset Input by RESET Input I aasan 534 24 3 Timing of Reset due to Watchdog Timer Overflow 534 24 4 Timing of Reset Input in STOP Mode by RESET Input ccccccccscessssssscscecesssesceceseseseseeteseseseseeenes 534 25 1 Block Diagram of ROM Correction u idco cere eco th et Pre ete et a et 537 25 2 Correction Address Registers 0 and 1 Format 538 25 3 Correction Control Regis
35. addr16 Conditional addr16 granch addr16 addr16 N Ml MMM MN O N INI Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed Remarks 1 One instruction clock cycle is one cycle of the CPU clock fceu selected by the processor clock control register PCC 2 This clock cycle applies to internal ROM program 570 27 INSTRUCTION SET Instruction Group Mnemonic Operands saddr bit addr16 Operation PC lt PC 3 jdisp8 if saddr bit 1 sfr bit addr16 PC lt PC 4 jdisp8 if sfr bit 1 A bit addr16 PC lt PC 3 jdisp8 if A bit 1 PSW bit addr16 PC lt PC 3 jdisp8 if PSW bit 1 HL bit addr16 PC lt PC 3 jdisp8 if HL bit 1 saddr bit addr16 PC lt PC 4 jdisp8 if saddr bit 0 sfr bit addr16 PC PC 4 jdisp8 if sfr bit 0 A bit addr16 PC lt PC 3 jdisp8 if A bit 0 PSW bit addr16 PC PC 4 jdisp8 if PSW bit 0 HL bit addr16 w AJJAJ O CO PC lt PC 3 jdisp8 if HL bit 0 Conditional branch saddr bit addr16 PC lt PC 4 jdisp8 if saddr bit 1 then reset saddr bit sfr bit addr16 PC PC 4 jdisp8 if sfr bit 1 then reset sfr bit
36. g LPD78058 78058Y 78P058 78 058 Memory map when internal ROM PROM size is 60 Kbytes FFFFH FF00H FEFFH FB00H FAFFH FADFH FACOH FABFH F800H F7FFH F400H F3FFH FOOOH EFFFH 0000H Internal High Speed RAM Reserved Internal Buffer RAM Reserved Internal Expansion RAM Reserved Single chip mode When the internal ROM PROM size is 60 Kbytes the area from F000H to F3FFH cannot be used F000H to F3FFH can be used as external memory by setting the internal ROM PROM size to less than 56 Kbytes by the memory size switching register IMS 515 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22 2 External Device Expansion Function Control Register The external device expansion function is controlled by the memory expansion mode register MM and memory size switching register IMS 1 Memory expansion mode register MM MM sets the wait count and external expansion area and also sets the input output of port 4 MM is set with an 1 bit memory or 8 bit memory manipulation instruction RESET input sets this register to 10H Figure 22 2 Memory Expansion Mode Register Format When Symbol 7 6 5 Address Reset R W 4 3 2 1 0 Single chip P40 P47 P50 P57 P64 P67 Pin state Memory Expansion Mode Selection P40 P47 P50 P53 P54 P55 P56 P57 P64 P67 Port Input mode Single chip mode Port mode Output 25
37. Error Check Control of Automatic Transmit Receive Function 0 1 Error check disable Error check enable only when BUSY1 1 ARLD Operating Mode Selection of Automatic Transmit Receive Function Single operating mode Repetitive operating mode Receive Control of Automatic Transmit Receive Function Receive disable Receive enable Notes 1 Bits 3 and 4 TRF and ERR are Read Only bits 2 The termination of automatic transmission reception should be discriminated by using TRF not CSIIF1 Interrupt request flag Caution When external clock input is selected with bit 1 CSIM11 of the serial operating mode register 1 CSIM1 set to 0 set STRB and BUSY1 of ADTC to 0 0 handshake control cannot be executed when the external clock is input Remark x Don t care 411 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 c Automatic data transmit receive interval specify register ADTI This register sets the automatic data transmit receive function data transfer interval ADTI is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ADTI to 00H 412 5 4 3 2 1 0 ADTI ADTI7 o ADTI3 ADTI2 ADTI1 ADTIO FF6BH Address After Reset R W 00H R W ADTI7 Data Transfer Interval Control No control of interval by ADT Note 1 0 1 ADTIS Control of interval by ADTI ADTIO to ADTIA Data Transfer Interval Specification fxx 5 0 MHz Operation
38. MCS 1 fx 2 39 1 kHz fx 2 19 5 kHz 32 768 kHz Buzzer Output Frequency Selection TCL26 MCS 1 Buzzer output disable fxx 2 fx 2 9 8 kHz fx 2 4 9 kHz fxx 2 fx 2 4 9 kHz fx 2 2 4 kHz fxx 2 fx 2 2 4 kHz fx 2 1 2 kHz Setting prohibited Caution When rewriting TCL2 to other data stop the timer operation beforehand Remarks 1 fxx Main system clock frequency fx or 5 2 2 fx Main system clock oscillation frequency 3 fxr Subsystem clock oscillation frequency 4 x Don t care 5 MCS Bit 0 of oscillation mode selection register OSMS 6 Figures in parentheses apply to operation with fx 5 0 MHz or fxr 32 768 kHz 244 CHAPTER 10 WATCH TIMER 2 Watch timer mode control register TMC2 This register sets the watch timer operating mode watch flag set time and prescaler interval time and enables disables prescaler and 5 bit counter operations TMC2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TMC2 to 00H Figure 10 3 Watch Timer Mode Control Register Format After Symbol 7 Address R W TMC20 Watch Operating Mode Selection Normal operating mode flag set at fw 2 Fast feed operating mode flag set at fw 2 TMC21 Prescaler Operation Control Clear after operation stop Operation enable Watch Flag Set Time Selection
39. Transmit data 5 T5 Transmit data 6 T6 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 d Automatic transmission reception suspending and restart Automatic transmission reception can be temporarily suspended by setting bit 7 CSIE1 of the serial operating mode register 1 CSIM1 to 0 If during 8 bit data transfer the transmission reception is not suspended if bit 7 CSIE1 is set to 0 It is suspended upon completion of 8 bit data transfer When suspended bit 3 TRF of the automatic data transmit receive control register ADTC is set to 0 after transfer of the 8th bit and all the port pins used with the serial interface pins for dual function P20 11 21 501 P22 SCK1 P23 STB and P24 BUSY are set to the port mode During restart of transmission reception remaining data can be transferred by setting CSIE1 to 1 and writing any data to the serial I O shift register 1 SIO1 Cautions 1 Ifthe HALT instruction is executed during automatic transmission reception transfer is suspended and the HALT mode is set if during 8 bit data transfer When the HALT mode is cleared automatic transmission reception is restarted from the suspended point 2 When suspending automatic transmission reception do not change the operating mode to 3 wire serial I O mode while TRF 1 Figure 18 17 Automatic Transmission Reception Suspension and Restart CSIE1 0 Suspended Command Suspend Restart Command CSIE1 1 Wri
40. Write transmit data in buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Software Execution Set the transmission reception operation interval time in ADTI Write any data to SIO1 Start trigger Write transmit data from buffer RAM to SIO1 Transmission reception Decrement pointer value operation Hardware Execution Write receive data from SIO1 to buffer RAM Pointer value 0 Software Execution End ADTP Automatic data transmit receive address pointer ADTI Automatic data transmit receive interval specify register SIO1 Serial I O shift register 1 TRF Bit 3 of automatic data transmit receive control register ADTC 418 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6 byte transmission reception ARLD 0 RE 1 in basic transmit receive mode buffer RAM operates as follows i Before transmission reception Refer to Figure 18 10 a After any data has been written to serial I O shift register 1 SIO1 start trigger this data is not transferred transmit data 1 T1 is transferred from the buffer RAM to SIO1 When transmission of the first byte is completed the receive data 1 R1 is transferred from 5101 to the buffer RAM and automatic data transmit receive address pointer ADTP is decremented Then transmit data 2 T2 is transferred from the buffer RAM to SIO1 ii 4th byte transmission rec
41. cancer tnter tnn 339 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 341 17 1 Serial Interface Channel 0 Functions U u J 342 17 2 Serial Interface Channel 0 Configuration l u 344 17 3 Serial Interface Channel 0 Control Registers 348 17 4 Serial Interface Channel 0 Operations u u u u u 356 17 4 1 Operation Stop MOE u U UU AQ L U upi uu Su G Gitu u entes 356 17 4 2 3 wire serial I O mode operation L 357 17 4 3 2 serial mode operation u 361 17344 FO tdem tee tates des 367 17 4 5 Cautions on use of I C bus mode nennen enne nnn nnne trennt rn nnns nn nnns 385 17 4 6 Restrictions in IPC bus mode I a nnne nnns 388 17 47 SCKO SCL P27 pin output manipulation ssec 390 21 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 J u u 18 1 Serial Interface Channel 1 Functions U eene nenne nnne nnn 18 2 Serial Interface Channel 1 Configuration
42. fxx 2 fx 2 9 8 kHz 4 9 kHz fxx 2 fx 2 2 4 kHz 1 2 kHz Setting prohibited 8 Bit Timer Register 2 Count Clock Selection 2 falling edge TI2 rising edge fxx 2 fx 2 2 5 MHz 1 25 MHz fxx 2 fx 2 1 25 MHz 625 kHz fxx 2 fx 2 625 kHz 813 kHz fxx 2 fx 2 813 kHz 156 kHz fxx 2 25 156 kHz 78 1 2 fxx 2 fx 2 78 1 kHz 39 1 kHz fxx 2 fx 2 39 1 kHz 19 5 kHz 28 fx 28 19 5 kHz 9 8 kHz fxx 2 fx 2 9 8 kHz 4 9 kHz fxx 2 fx 2 2 4 kHz 1 2 kHz Other than above Setting prohibited Caution When rewriting TCL1 to other data stop the timer operation beforehand Remarks 1 Main system clock frequency or fx 2 2 fx Main system clock oscillation frequency 3 TM 8 bit timer register 1 input pin 4 8 bit timer register 2 input pin 5 MCS Oscillation mode selection register OSMS bit 0 6 Figures in parentheses apply to operation with fx 2 5 0 MHz 224 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 AND 2 2 8 bit timer mode control register TMC1 This register enables stops operation of 8 bit timer registers 1 and 2 and sets the operating mode of 8 bit timer register 1 and 2 1 is set with a 1 bit or 8 bit memory manipulation
43. 01 osProsP ETOCO4LVSO LVRO TOCOt TOEO 16 Bit Timer Output L T 1 03 02 01 OVFO 16 Bit Timer Mode TCLO6 TCL05 TCLO4 Timer Clock Selection CRC02 Control Register Control Register Register 0 Internal Bus 2 Notes 1 Edge detection circuit 2 The configuration of the 16 bit timer event counter output control circuit is shown in Figure 8 2 179 CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 2 16 Bit Timer Event Counter Output Control Circuit Block Diagram PWM Pulse Output Control Circuit Selector Selector Edge Detection Circuit TI00 P00 INTP0 One Shot Pulse Output Control Circuit P30 Output ES11 Latch PM30 External Interrupt 16 Bit Timer Output 16 Bit Timer Mode Port Mode Mode Register 0 Control Register Control Register Register 3 Y Y Internal Bus Remark The circuitry enclosed by the dotted line is the output control circuit 180 CHAPTER 8 16 BIT TIMER EVENT COUNTER 1 Capture compare register 00 CROO 0 is 16 bit register which has the functions of both a capture register and a compare register Whether it is used as a capture register or as a compare register is set by bit O CRCOO of capture compare control register 0 CRCO When 00 is used as a compare register the value se
44. 547 CHAPTER 26 uPD78P054 78P058 Notes 1 The internal ROM and internal high speed RAM capacities are set as follows by RESET input Internal PROM 32K bytes uPD78P054 60K bytes uPD78P058 Internal high speed RAM 1024 bytes 2 The internal expansion RAM is set to 1024 bytes by RESET input Caution The noise immunity and noise radiation differ between PROM versions and mask ROM versions When considering replacement of PROM versions with mask ROM versions in the stage between test production and mass production evaluate thoroughly with CS products not ES products of the mask ROM versions Remarks 1 The uPD78P054 is a PROM model corresponding to the 078052 78053 and 78054 The uPD78P058 is a PROM model corresponding to the 078055 78056 and 78058 2 Only the uPD78058 and 78P058 are provided with an internal expansion RAM size switching register Table 26 2 Differences between uPD78P054 and 78P058 078 054 78 058 Internal PROM 32 Kbytes 60 Kbytes Internal expansion RAM Not provided 1024 bytes Internal expansion RAM Not provided Provided size switching register 548 CHAPTER 26 uPD78P054 78P058 26 1 Memory Size Switching Register uPD78P054 The uPD78P054 allows users to define its internal ROM and high speed RAM sizes using the memory size switching register IMS so thatthe same memory mapping as that of a mask ROM version with a different size internal ROM and high
45. 80 pin plastic TQFP Fine pitch 12 x 12 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic TQFP Fine pitch 12 x 12 mm 80 pin ceramic WQFN 14 x 14 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic TQFP Fine pitch 12 x 12 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic TQFP Fine pitch 12 x 12 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic TQFP Fine pitch 12 x 12 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin ceramic WQFN 14 x 14 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm 1 4 mm 1 4 mm 2 7 mm 1 4 mm 1 4 mm 1 4 mm 1 4 mm 1 4 mm 2 7 mm 2 7 mm 2 7 mm Standard Standard Standard Standard Standard Standard Standard Standard Standard Not applicable for function evalution Standard Standard Standard Standard Standard Standard Standard Not applicable for function evalution Special Special Special Cautions 1 The uPD78P054GC is available in two packages For the package that can be supplied consult NEC 2 The uPD78054KK T and 78P058KK T should be used only for experiment or function evaluation because they are not intended for use in equipment that will be mass produced and require high relia
46. ADTI2 ADTI1 MinimumNete 2 18 4 us 0 5 fsck MaximumNete 2 20 0 us 1 5 fsck 31 2 us 0 5 fsck 32 8 us 1 5 fsck 44 0 us 0 5 fsck 45 6 us 1 5 fsck 56 8 us 0 5 fsck 58 4 us 1 5 fsck 69 6 us 0 5 fsck 71 2 5 1 5 fsck 82 4 us 0 5 fsck 84 0 us 1 5 fsck 95 2 us 0 5 fsck 96 8 us 1 5 fsck 108 0 s 0 5 fsck 109 6 us 1 5 fsck 120 8 us 0 5 fsck 122 4 5 1 5 fsck 133 6 us 0 5 fsck 135 2 us 1 5 fsck 146 4 us 0 5 fsck 148 0 us 1 5 fsck 159 2 us 0 5 fsck 160 8 us 1 5 fsck 172 0 us 0 5 fsck 173 6 us 1 5 fsck 184 8 us 0 5 fsck 186 4 us 1 5 fsck 197 6 us 0 5 fsck 199 2 us 1 5 fsck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Notes 1 2 Cautions Remarks 210 4 us 0 5 fsck 212 0 us 1 5 fsck The interval is dependent only on CPU processing The data transfer interval includes an error The data transfer minimum and maximum intervals are found from the following expressions n Value set in ADTIO to ADTI4 However if a minimum which is calculated by the following expressions is smaller than 2 fsck the minimum interval time is 2 fsck 26 28 fxx i fxx 1 5 fsck 0 5 Maximum 1 x 26 36 fsck fxx fxx Minimum n 1 x 1 Do not write data to ADTI during operation of automatic data transmit receive
47. Control mode These ports function as A D converter analog input pins ANIO to ANI7 The on chip pull up resistor is automatically disabled when the pins specified for analog input 4 2 3 P20 to P27 Port 2 These are 8 bit input output ports Besides serving as input output ports they function as data input output to from the serial interface clock input output automatic transmit receive busy input and strobe output functions The following operating modes can be specified in 1 bit units 1 2 Port mode These ports function as 8 bit input output ports They can be specified in 1 bit units as input or output ports with port mode register 2 PM2 When they are used as input ports on chip pull up resistors can be used to them by defining the pull up resistor option register L PUOL Control mode These ports function as serial interface data input output clock input output automatic transmit receive busy input and strobe output functions 10 SH SOO 501 SBO SB1 SDAO SDA1 Serial interface serial data input output pins b SCKO SCK1 SCL Serial interface serial clock input output pins c BUSY Serial interface automatic transmit receive busy input pins d STB Serial interface automatic transmit receive strobe output pins Caution When this port is used as a serial interface the I O and output latches must be set according to the function the user requires For the setting refer to Figure 17 4 Se
48. Function The memory mapped special function register SFR is addressed with 8 bit immediate data in an instruction word This addressing is applied to the 240 byte spaces FFOOH to FFCFH and FFEOH to FFFFH However the SFR mapped at FFOOH to FF1FH can be accessed with short direct addressing Operand format sfr Special function register name sfrp 16 bit manipulatable special function register name even address only Description example MOV PMO A when selecting PMO FF20H as sfr Operation code 11110110 OP code 00100000 20H sfr offset Illustration OP code sfr offset SFR Effective Address 125 CHAPTER 5 CPU ARCHITECTURE 5 4 6 Register indirect addressing Function This addressing addresses the memory with the contents of a register pair specified as an operand The register pair to be accessed is specified by the register bank select flags RBSO and RBS1 and register pair specify code in an instruction code This addressing can be carried out for all the memory spaces Operand format Description example MOV A DE when selecting DE as register pair Operation code 10000101 Illustration Memory address specified by register pair DE Contents of addressed memory are transferred 7 126 CHAPTER 5 CPU ARCHITECTURE 5 4 7 Based addressing Function This addressing addresses the memory by adding 8 bit immediate data to th
49. MEMO 482 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21 1 Interrupt Function Types The following three types of interrupt functions are used 1 2 3 Non maskable interrupt This interrupt is acknowledged unconditionally even in the interrupt disabled status It does not undergo interrupt priority control and is given top priority over all other interrupt requests It generates a standby release signal Non maskable interrupt includes one interrupt request source from watchdog timer Maskable interrupts These interrupts undergo mask control Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag register PROL PROH PR1L Multiple high priority interrupts can be applied to low priority interrupts If two or more interrupts with the same priority are simultaneously generated each interrupts has a predetermined priority see Table 21 1 A standby release signal is generated Maskable interrupt includes 7 external interrupt request sources and 13 internal interrupt request sources Software interrupt This is a vectored interrupt that occurs when the BRK instruction is executed It is acknowledged even in a disabled state The software interrupt does not undergo interrupt priority control 483 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21 2 Interrupt Sources and Configuration Interrupt sources includes total of 22 non maskb
50. Pin Name nputioutput Function After Reset Alternate Function Input only INTPO TIOO in 1 bit units Input output mode can be specified INTP1 TIO1 Po 8 bit input output port on chip pull up resistor can be used Pos by software P07Note1 Input only P10 to P17 Port 1 P00 P01 P02 P03 Port 0 When used as an input port an P04 P05 P06 8 bit input output port Input output mode can be specified in 1 bit units ANIO to ANI7 When used as input port an on chip pull up resistor can be used by softwareNote2 Port 2 8 bit input output port Input output mode can be specified in1 bit units When used as an input port an on chip pull up resistor can be used by SIO SBO SDAO software SOO SB1 SDA1 SCKO SCL Notes 1 Whenthe PO7 XT1 pinis used as an input port set the bit 6 FRC ofthe processor clock control register PCC to 1 do not use the feedback resistor internal to the subsystem clock oscillator 2 When pins P10 ANIO to P17 ANI7 are used as an analog input of the A D converter set port 1 to input mode The on chip pull up resistor will automatically be disabled 75 CHAPTER 4 PIN FUNCTION uPD78054Y Subseries 1 Port pins 2 3 Pin Name Input Output Function Port 3 8 bit input output port Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software After Reset Altern
51. u 238 Event Counter Operation Timing nennen nnne nennen nennt 239 Timing after Compare Register Change during Timer Count Operation 239 Watch Timer Block uoce ede c e ng 243 Timer Clock Select Register 2 Formatl 244 Watch Timer Mode Control Register Format 245 Watchdog Timer Block 249 Timer Clock Select Register 2 Format nennen ennemis 251 Watchdog Timer Mode Register Format 252 27 LIST OF FIGURES 4 8 Figure No Title Page 12 1 Remote Controlled Output Application Example seseeeneeeeeennenenneen 255 12 2 Clock Output Control Circuit Block Diagram sessi 256 12 3 Timer Clock Select Register 0 Format u nennen 258 12 4 Port Mode Register 3 Format ir ERR te e SERERE GRE 259 13 1 Buzzer Output Control Circuit Block Diagram seen eene 261 13 2 Timer Clock Select Register 2 Format essere neret nnn nnne ns 263 13 3 Port Mode Regist r Foermat uu ore v a ie rep i bu aee inus 264 14 1 A D Converter Block Diagram 266 14 2 Handling of 268 14 3 A D Converter Mode Register
52. 21 5 1 Registers controlling the test function The test function is controlled by the following three registers Interrupt request flag register 1L IF1L Interrupt mask flag register 1L MK1L Key return mode register KRM The names of the test input flags and test mask flags corresponding to the test input signals are listed in Table 21 6 Table 21 6 Flags Corresponding to Test Input Signals Test input signal name Test input flag Test mask flag INTWT WTIF WTMK INTPT4 KRIF KRMK 507 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 1 Interrupt request flag register 1L IF1L It indicates whether a watch timer overflow is detected or not It is set by a 1 bit memory manipulation instruction and 8 bit memory manipulation instruction It is set to 00H by the RESET signal input Figure 21 19 Format of Interrupt Request Flag Register 1L When Symbol lt gt 6 5 4 3 lt 2 lt i gt lt Address IFL wnE o o o apie TMIF2 TMIFi FFE2H 00H R W Not detected WTIF Watch timer overflow detection flag 0 1 Detected Caution Be sure to set bits 3 through 6 to 0 2 Interrupt mask flag register 1L MK1L Itis used to set the standby mode enable disable at the time the standby mode is released by the watch timer It is set by a 1 bit memory manipulation instruction and 8 bit memory manipulation instruction It is set to FFH by the RESET signal input Figure 21 20 Forma
53. 7 4 1 Main system clock oscillator U 7 4 2 Subsystem clock OSCilator 2 0 L u Gu u 72453 Ite ede e eate 7 44 When no subsystem clocks are 7 5 Clock Generator Operations J 7 5 1 Main system clock 7 5 2 Subsystem clock operations u 7 6 Changing System Clock and CPU Clock Settings 7 6 1 Time required for switchover between system clock and CPU clock 7 6 2 System clock and CPU clock switching CHAPTER 8 16 TIMER EVENT COUNTER u u uu uuu u 8 1 Outline of Timers Incorporated in the uPD78054 78054Y Subseries 8 2 16 Bit Timer Event Counter Functions u u u u 8 3 16 Bit Timer Event Counter Configuration l u u u u 8 4 16 Bit Timer Event Counter Control Registers l u u 8 5 16 Bit Timer Event Counter 8 5 1 Interval timer Operations o uuu uN eie th e
54. APPENDIX DEVELOPMENT TOOLS Figure B 3 EV 9200GC 80 Footprint For Reference Only Based on EV 9200GC 80 2 Pad drawing in mm G a J VU K i Bi JL bd m A EV 9200GC 80 P1E ITEM MILLIMETERS INCHES A 19 7 0 776 B 15 0 0 591 C 0 65 0 02 x 19 12 35 0 05 0 026 0 201 x 0 748 0 486 000 D 1 0 6550 02 x 19 12 35 0 05 0 026990 x 0 748 0 486 0 003 E 15 0 0 591 F 19 7 0 776 G 6 0 0 05 0 236 0203 H 6 0 0 05 0 236 0203 0 35 0 02 0 014 0001 J 2 36 0 03 0 093290 K 2 3 90 091 L 1 57 0 03 0 062 250 Caution Dimensions of mount pad for EV 9200 and that for target device QFP may be different in some parts For the recommended mount pad dimensions for QFP refer to SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL C10535E 591 APPENDIX DEVELOPMENT TOOLS Drawing of Conversion Adapter TGK 080S8DW Figure B 4 TGK 080SDW Drawing For Reference unit mm TGK 080SDW 805 TOSOCKETO80SDW Package dimension unit mm
55. CHAPTER 14 A D CONVERTER 3 Noise countermeasures 4 5 In order to maintain 8 bit resolution attention must be paid to noise on pins AVrero and ANIO to ANI7 Since the effect increases in proportion to the output impedance of the analog input source it is recommended that a capacitor be connected externally as shown in Figure 14 11 in order to reduce noise Figure 14 11 Analog Input Pin Disposition If there is possibility that noise whose level is AVnero or higher or AVss or lower may enter clamp with a diode with a small Vr 0 3 V or less Reference Voltage Input 7 AVREFo ANIO ANI7 C 100 1000 pF A Vpp AVpp AVss Vss ZZ Pins ANI0 P10 to ANI7 P17 The analog input pins ANI0 to ANI7 also function as input output port PORT1 pins When A D conversion is performed with any of pins ANI0 to ANI7 selected be sure not to execute an input instruction to PORT1 while conversion is in progress as this may reduce the conversion resolution Also if digital pulses are applied to a pin adjacent to the pin in the process of A D conversion the expected A D conversion value may not be obtainable due to coupling noise Therefore avoid applying pulses to pins adjacent to the pin undergoing A D conversion AVnero pin input impedance A series resistor string of approximately 10 is connected between the AVrero pin and the AVss pin Therefore if the output impedance of the reference vol
56. CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21 10 Flowchart of Generation from Non Maskable Interrupt Request to Acknowledgment WDTM4 with watchdog timer mode selected Interval timer Overflow in WDT WDTM3 0 with non maskable interrupt request selected Reset processing Interrupt request generation WDT interrupt servicing Interrupt request held pending Interrupt control register unaccessed Yes Interrupt Service start WDTM Watchdog timer mode register WDT Watchdog timer Figure 21 11 Non Maskable Interrupt Request Acknowledge Timing a sS F The interrupt request generated during this period is acknowledged at the timing of T TMIF4 Watchdog timer interrupt request flag 498 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21 12 Non Maskable Interrupt Request Acknowledge Operation a lf a new non maskable interrupt request is generated during non maskable interrupt servicing program execution Main Routine NMI Request 1 is executed NMI Request 1 Request 2 NMI Request 2 is reserved 1 Instruction Execution Reserved NMI Request 2 is processed b If two non maskable interrupt requests generated during non maskable interrupt servicing program execution Main Routine NMI NMI Request 1 is executed Request 2 NMI Request 2 is reserv
57. Caution When only either one of the D A converter channels is used with AVreri lt the other pins that are not used as analog outputs must be set as follows Set PM13x bit of the port mode register 13 PM13 to 1 input mode and connect the pin to Vss Set PM13x bit of the port mode register 13 PM13 to 0 output mode and the output latch to 0 to output low level from the pin 3 2 11 AVREFo A D converter reference voltage input pin When A D converter is not used connect this pin to Vss 3 2 12 AVREF1 D A converter reference voltage input pin When D A converter is not used connect this pin to Vop 69 CHAPTER 3 PIN FUNCTION uPD78054 Subseries 3 2 13 AVpp Analog power supply pin of A D converter Always use the same voltage as that of the Vpp pin even when A D converter is not used 3 2 14 AVss This is a ground voltage pin of A D converter and D A converter Always use the same voltage as that of the Vss pin even when neither A D nor D A converter is used 3 2 15 RESET This is a low level active system reset input pin 3 2 16 X1 and X2 Crystal resonator connect pins for main system clock oscillation For external clock supply input it to X1 and its inverted signal to X2 3 2 17 XT1 and XT2 Crystal resonator connect pins for subsystem clock oscillation For external clock supply input it to XT1 and its inverted signal to XT2 3 2 18 Positive power supply pin 3 2 19 Vss Ground potential pi
58. P10 to P17 ESSE WRem ME PM10 PM17 e T cu PUO Pull up resistor option register PM Port mode register RD Port 1 read signal WR Port 1 write signal 136 CHAPTER 6 PORT FUNCTIONS 6 2 3 Port 2 uPD78054 Subseries Port 2 is an 8 bit input output port with output latch P20 to P27 pins can specify the input mode output mode in 1 bit units with the port mode register 2 PM2 When P20 to P27 pins are used as input ports an on chip pull up resistor can be used to them in 8 bit units with a pull up resistor option register L PUOL Alternate functions include serial interface data input output clock input output automatic transmit receive busy input and strobe output RESET input sets port 2 to input mode Figures 6 5 and 6 6 show block diagrams of port 2 Cautions 1 When used as a serial interface set the input output and output latch according to its functions For the setting method refer to Figure 16 4 Serial Operating Mode Register 0 Format and Figure 18 3 Serial Operating Mode Register 1 Format 2 When reading the pin state in SBI mode set PM2n bit of PM2 to 1 n 5 6 Refer to the description of 10 Discrimination of slave busy state in section 16 4 3 SBI Mode Operation Figure 6 5 P20 P21 P23 to P26 Block Diagram Vpp WRPFPuo RD e 5 s ids P20 SI1 5 Output Latch E P20 P21 P23 P26 l 25 510
59. POR 1 A POR 1 1 CONTROL 78K 0 CPU CORE BOM RAM Voo Vss IC Ver POR 1 12 13 REAL TIME OUTPUT PORT EXTERNAL ACCESS SYSTEM CONTROL Remarks 1 The internal ROM and RAM capacities depend on the product 56 2 Pin connection in parentheses is intended for the 78 058 01 06 P07 P10 P17 P20 P27 P30 P37 P40 P47 P50 P57 P60 P67 P70 P72 P120 P127 P130 P131 RTPO P120 RTP7 P127 ADO P40 AD7 P47 A8 P50 A15 P57 RD P64 WR P65 WAIT P66 ASTB P67 RESET 1 2 XT1 P07 XT2 CHAPTER 2 OUTLINE uPD78054Y Subseries 2 8 Outline of Function Part Number Internal memory uPD78052Y uPD78053Y uPD78054Y uPD78055Y uPD78056Y uPD78058Y Mask ROM PROM 16 Kbytes 24 Kbytes 32 Kbytes 40 Kbytes 48 Kbytes 60 Kbytes 60 Kbytes Note 1 High speed RAM 512bytes 1024 bytes 1024 bytes Note 1 Buffer RAM 32 bytes Expansion RAM None 1024 bytes 1024 bytes Note 2 Memory space 64 Kbytes General register 8 bits x 8 x 4 banks Minimum instruction With main system clock selected 0 4 us 0 8 us 1 6 us 3 2 us 6 4 us 12 8 us 5 0 MHz execution time With subsystem clock selected 122 us 32 768 kHz Instruction set 16 bit op
60. Portimode regiStery9r s uenerit ide TR eed 150 188 227 259 264 PM5 Port mode register 5 uu u 150 PM6 Port mode register B ie e ede er dr p epee ied edd orn guit dre ee 150 7 Port mode register Z u u e sala 150 12 Port mode register 12 cere edid E E 150 480 13 Port mode register A teeta 150 596 APPENDIX D REGISTER INDEX PROH Priority specify flag register 491 PROL Priority specify flag register OL l U UU nennen nnne nennen nennen nennen nnne 491 PR1L Priority specify flag register 1L reete tret p re ie s q ER 491 PSW Program statis WOLF ou cin Eg ad ee tet t P oe sce te 109 496 PUOH Pull up resistor option register 153 PUOL Pull up resistor option register 153 R RTBH Real time output buffer register 479 RTBL Real time output buffer register L u U u u 479 RTPC Real time output port control register 481 RTPM Real time output port mode register nnne nnnm 480 RXB Receive buffer register a uu i apa dee Ene EOD e cre a dla adve 443 RXS Receive slift register t e am pei eae e ieee 443
61. WR WAIT ASTB 16K byte expansion mode Address data Address WR WAIT ASTB Full address mode Caution Address data Address RD WR WAIT ASTB When the external wait function is not used the WAIT pin can be used as a port in all modes 511 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Memory maps when using the external device expansion function are as follows 512 a Memory map of uPD78P054 78 058 78P058Y when the uPD78052 78052Y and internal PROM are 16 Kbytes FFFFH FF00H FEFFH FD00H FCFFH FAE0H FADFH FA80H FA7FH 8000H 7FFFH 5000H 4FFFH 4100H 40FFH 4000H 3FFFH 0000H Figure 22 1 Memory Map when Using External Device Expansion Function 1 4 Internal High Speed RAM Reserved Internal Buffer RAM Reserved Full Address Mode when MM2 MMO 111 16 Kbyte Expansion Mode when 2 0 101 4 Kbyte Expansion Mode when 2 0 100 256 byte Expansion Mode when 2 0 011 Single chip Mode b Memory map of uPD78P054 78P058 78P058Y when the uPD78053 78053Y and internal PROM are 24 Kbytes FFFFH FF00H FEFFH FB00H FAFFH FADFH FACOH FABFH FA80H FA7FH A000H 9FFFH 7000H 6FFFH 6100H 60FFH 6000H 5FFFH 0000H Internal High Speed RAM Reserved Internal Buffer RAM Reserved Full Address M
62. fx 23 625 kHz fx 24 313 kHz fxw 28 fx 28 19 5 kHz fx 29 9 77 kHz fx 24 313 kHz fx 25 156 kHz fxx 29 fx 29 9 77 kHz fx 210 4 88 kHz fx 25 156 kHz fx 26 78 1 kHz fxx 210 210 4 88 kHz fx 211 2 44 kHz fx 26 78 1 kHz fx 27 39 1 kHz fxx 211 5 21 2 44 kHz fx 212 1 22 kHz 27 39 1 kHz fx 28 19 5 kHz fxx 212 212 1 22 kHz fx 213 0 61 kHz fx 28 19 5 kHz fx 29 9 8 kHz Setting prohibited bo 2 Serial Interface Channel 1 Serial Clock Selection MCS 1 Setting prohibited fx 22 1 25 MHz fxx 22 fx 22 1 25 MHz fx 23 625 kHz fxw 23 fx 23 625 kHz fx 24 313 kHz fxx 24 fx 24 313 kHz fx 25 156 kHz 25 fx 25 156 kHz fx 26 78 1 kHz 26 fx 28 78 1 kHz fx 27 39 1 kHz fxw 2 fx 27 39 1 kHz fx 28 19 5 kHz fxx 28 5 28 19 5 kHz fx 29 9 8 kHz Other than above Setting prohibited Caution When rewriting TCL3 to other data stop the serial transfer operation beforehand Remarks 1 2 3 4 fx Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency MCS Oscillation mode selection register OSMS bit 0 Figures in parentheses apply to operation with fx 2 5 0 MHz 349 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Su
63. w 77 Vpop RD 34 sa lt medium breakdown input buffer D gt CHAPTER 5 CPU ARCHITECTURE 5 1 Memory Spaces Each product of the uPD78054 and 78054Y Subseries can access the memory space of 64 Kbytes Figures 5 1 to 5 8 show memory maps Figure 5 1 Memory Map uPD78052 78052Y Special Function Registers SFRs 256 x 8 bits General Registers 32 x 8 bits Internal High speed RAM 512 x 8 bits FD00H FCFFH Reserved FAE0H FADFH 3FFFH Internal Buffer RAM 32 x 8 bits Program Area Data memory FABFH d 1000H eserve ad FA7FH CALLF Entry Area 0800H External Memory 07 47744 x 8 bits Program Area Program memory 0080H 5 007 4000 SREE CALLT Table Area Internal ROM 16384 8 bits Vector Table Area Y Y 0000H 0000H 91 CHAPTER 5 CPU ARCHITECTURE Figure 5 2 Memory Map uPD78053 78053Y A Special Function Registers SFRs 256 x 8 bits General Registers 32 x 8 bits Internal High speed RAM 1024 x 8 bits FBOOH FAFFH Reserved FAEOH FADFH 5FFFH Internal Buffer RAM 32 x 8 bits Program Area FACOH Data memory FABFH 1000H Reserved Space FA80H FA7FH CALLF Entry Area 0800H External Memory 07 39552 x 8 bits Program Area Program memory 0080H nons 007FH 6000H SERE CALLT Table Area Internal ROM
64. 8 78056GK xxx BE9 78056YGC xxx 8BT 78058 8 78058GK xxx BE9 78058 8 HPD78P058GC 8BT 78P058YGC 8BT uUPD78052GC A xxx 3B9 78053GC A xxx 3B9 78054GC A xxx 3B9 The application circuits and their parameters are for reference only and are not intended for use in actual design ins Purchase of I C components conveys a license under the Philips I C Patent Rights to use these components in an 2 system provided that the system conforms to the I C Standard Specification as defined by Philips The information in this document is subject to change without notice No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation NEC Corporation assumes no responsibility for any errors which may appear in this document NEC Corporation does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Corporation or others While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices the possibility of defects cannot be eliminated entirely To minimize risks of damage or injury t
65. 8 bit timer register 2 TM2 output Clock specified with bits 4 to 7 of timer clock select register 3 TCL3 Serial Interface Channel 1 Operating Mode Selection 3 wire serial I O mode 0 1 0 MSB SI1 P20 SO1 1 LSB Input CMOS output If the external clock input has been selected with CSIM1 1 set to 0 set bit 1 BUSY1 and bit 2 STRB of the automatic data transmit receive control register ADTC to 0 0 Remark x Don t care Shift Register 1 CSIE1 CSIM11 PM20 P20 21 P21 PM22 P22 Operation Note 1 Note 1 Note 1 Note 1 Note 1 Operation x x x x x stop 3 wire serial I O mode with automatic transmit receive function Note SCK1 P22 Pin Function SI1 P20 Pin Function SO1 P21 Pin Function Serial Clock Counter Operation Control P20 CMOS input output P21 CMOS input output P22 CMOS input output SCK1 Input Note 2 Note 2 1 x Operation enable Count operation 511 Note 2 Input SO1 CMOS output SCK1 CMOS output Notes 1 Can be used freely as port function 2 Can be used as P20 CMOS input output when only transmitter is used clear bit 7 RE of ADTC to 0 Remark x Don t care PMxx Port mode register Pxx Port output latch 406 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 2 Communication operation The 3 wire serial I O mode is used for data transmission reception in 8 bit units B
66. CY sfr bit CY lt CY sfr bit CY A bit CY CY A bit CY PSW bit CY CY PSW bit CY HL bit CY CY A HL bit CY saddr bit CY lt CY v saddr bit CY sfr bit CY lt v sfr bit CY A bit CY amp CY v Abit CY PSW bit lt CY v PSW bit CY HL bit CY CY v HL bit Bit manipulate CY saddr bit CY lt CY saddr bit CY sfr bit CY lt CY lt sfr bit CY A bit CY amp CY v Abit CY PSW bit CY CY v PSW bit CY HL bit CY lt CY HL bit saddr bit saddr bit 1 sfr bit sfr bit 1 A bit A bit 1 PSW bit PSW bit 1 HL bit HL bit lt 1 saddr bit saddr bit 0 sfr bit sfr bit 0 A bit A bit 0 PSW bit PSW bit 0 HL bit mimmj cj nmj rnj nmj rnmj cj nmi nm coi nmj coj co nmi coj nmj coj coj nmi coi nm co c HL bit 0 CY 1 CY 0 Notes 1 When the internal high speed RAM area is accessed or instruction with no data access CY CY 2 When an area except the internal high speed RAM area is accessed Remarks 1 One instruction clock cycle is one cycle of the CPU clock fcPu selected by the processor clock control register PCC 2 This clock cycle applies to internal ROM program 3 n is the number of waits when external me
67. INTP1 is set Any of three edge specifications can be selected rising falling or both edges as the valid edges for the TI00 P00 pin and the TIO1 PO1 pin by means of bits 2 and 3 ES10 and ES11 and bits 4 and 5 ES20 and ES21 of INTMO respectively For 00 00 pin valid edge detection sampling is performed at the interval selected by means of the sampling clock selection register SCS and a capture operation is only performed when a valid level is detected twice thus eliminating noise with a short pulse width Figure 8 20 Control Register Settings for Two Pulse Width Measurements with Free Running Counter a 16 bit timer mode control register TMCO 03 02 01 OVFO b Capture compare control register 0 CRCO Free Running Mode CRC02 CRCO1 CRCOO SE CROO set as capture register Captured in CROO on invalid edge of 00 00 Pin CR01 set as capture register Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement See the description of the respective control registers for details 199 CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 21 Timing of Pulse Width Measurement Operation with Free Running Counter with Both Edges Specified V V TMO Count Value D3 xt INTP1 OVFO 01 Pin Input
68. In this example the SDAO P25 pin is used as a serial data input output pin When the SDA1 P26 is used take P2 5 and PM2 5 in the program example below as P2 6 and PM2 6 For the timing of each signal when this program is executed refer to Figure 17 22 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries Example of program releasing serial transfer status SET1 SET1 SET1 CLR1 SET1 SET1 CLR1 CLR1 CLR1 1 2 3 d 5 6 lt 7 gt lt 8 gt lt 9 gt P2 5 lt gt PM2 5 lt 2 gt PM2 7 lt 3 gt CSIEO lt 4 gt CSIEO lt 5 gt lt 6 gt PM2 7 lt 7 gt 2 5 lt 8 gt PM2 5 lt 9 gt This instruction prevents the SDAO pin from outputting a low level when the 12 bus mode is restored by instruction 5 The output of the SDAO pin goes into a high impedance state This instruction sets the P25 SDAO pin in the input mode to protect the SDAO line from adverse influence when the port mode is set by instruction 4 The P25 pin is set in the input mode when instruction 2 is executed This instruction sets the P27 SCL pin in the input mode to protect the SCL line from adverse influence when the port mode is set by instruction 4 The P27 pin is set in the input mode when instruction 3 is executed This instruction changes the mode from 12 bus mode to port mode This instruction restores the 2 bus mode from the port mode This in
69. Interrupt Request Acknowledge Interval Time Interval Time Interval Time Remark Interval time N 1 x t N 0000H to FFFFH Caution Even if the 16 bit timer event counter mode is used when the TM1 count value matches the CR10 value interrupt request INTTM1 is generated and the F F of 8 bit timer event counter output control circuit 1 is inverted Thus when using 8 bit timer event counter as 16 bit interval timer set the INTTM1 mask flag TMMK1 to 1 to disable INTTM1 acknowledgment When reading the 16 bit timer register TMS count value use the 16 bit memory manipulation instruction CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 AND 2 Table 9 9 Interval Times when 2 Channel 8 Bit Timer Event Counters TM1 and TM2 are Used as 16 Bit Timer Event Counter Minimum Interval Time Maximum Interval Time Resolution TCL12 TCL11 TCL10 TI1 input cycle 28 x TH input cycle input edge cycle TI1 input cycle 28 x TH input cycle input edge cycle 2 x 1 22 x 1 fx 217 x 4 fx 218 x 1 fx 2 x 1 fx 2 x 1 fx 400 ns 800 ns 26 2 ms 52 4 ms 400 ns 800 ns 2 x 1 fx 23 x 1 fx 218 x 1 fx 219 x 1 fx 22 x 1 fx 23 x 1 fx 800 ns 1 6 52 4 104 9 ms 800 ns 1 6 us 23 x 1 fx 24 x 1 fx 219 x 4 fx 220 x 1 fx 23 x 1 fx 24 x 1 fx 1 6 us 3 2 us 104 9 ms 209 7 ms 1 6 us 3 2 us 24 x 1 fx 25 x 1 fx 220 x 1 fx 221 x 1 fx 24 x 1 fx 25 x 1 fx 8 2
70. P25 Output Latc h V Serial Bus Interface Control Register CLRSET D Q A Serial I O Shift Register 0 SIOO Bus Release Command Acknowledge Busy Acknowledge Output Circuit Detector P26 Output Latch Interrupt Request Signal INTCSIO CLD SCKO P27 gt 27 2 Output Control az P27 Output Latch Serial Clock 1 CSIMOO CSIMOO CSIMO1 CSIMO1 Interrupt Timing Specify Register Generator fxx 2 fxx 28 CL33 TCL32 TCL31 TCL30 Timer Clock Select Register 3 Internal Bus Remark Output Control performs selection between CMOS output and N ch open drain output 291 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 1 2 292 Serial I O shift register 0 SIOO This is an 8 bit register to carry out parallel serial conversion and to carry out serial transmission reception shift operation in synchronization with the serial clock SIOO is set with an 8 bit memory manipulation instruction When bit 7 CSIEO of serial operating mode register 0 CSIMO is 1 writing data to SIOO starts serial operation In transmission data written to SIOO is output to the serial output SOO or serial data bus SBO SB1 In reception data is read from the serial input SIO or SBO SB1 to SIOO Note
71. Q 5100 Transfer Start SCKO 5 0 SB1 ACKD b When ACK signal is output after 9th clock of SCKO Transfer Start i Instruction nunan X Transfer Start SCKO 6 7 8 9 seose X b2 X r 7 ACKD v OY P c Clear timing when transfer start is instructed in BUSY Transfer Start Instruction 5 0 SB1 ACKD Figure 16 25 BSYE Operation SCK0 6 7 8 9 SB0 SB1 D2 X D X po ACK BUSY When BSYE 1 at this point lt gt If reset during this period and BSYE 0 at the falling edge of SCK0 322 EE Signal Name Bus release signal REL Output Device Definition SBO SB1 rising edge when SCKO 1 Table 16 3 Various Signals in SBI Mode 1 2 Timing Chart SCKO H SB0 SB1 Output Condition RELT set Effects on Flag RELD set CMDD clear Meaning of Signal CMD signal is output to indicate that transmit data is an address Command signal CMD Master SBO SB1 falling edge when SCKO 1 SCKO H SB0 SB1 CMDT set CMDD set i Transmit data is an address after REL signal output ii REL signal is not output and trans mit data is an command Acknowledge signal ACK Low level signal to be output to SBO SB1 during one clock period of SCKO after completion of serial reception Busy signal BUSY Synchronous BUSY signal Low leve
72. S SAR Successive approximation register 0 u u nene 267 SBIC Serial bus interface control register 298 304 316 335 352 358 363 373 SCS Sampling clock select register u 190 494 SFR Spe cial t riction reglster 114 SINT Interrupt timing specify register 300 318 336 354 364 375 SIO0 Serial I O shift register O E E L E E TE 292 346 SIO1 Serial I O shift register Tulus edn a i a e 396 SVA Slave address register cd eet eter d n e re I e 292 346 Serial operating mode register 0 CSIMO 296 302 315 334 350 357 362 372 Serial operating mode register 1 CSIM1 u 396 399 409 Serial operating mode register 2 CSIM2 444 452 454 467 T TCLO Timer clock select register 0 182 257 TCL1 Timer clock Select T egister u u oiii pente reu eei tn ete Dee 223 TCL2 Timer clock select register 2 242 250 262 TCL3 Timer clock select register 3 2 10000 294 348 397 TMO 16 bit timer register TM1 8 bit timer register 1 TM2 8 bit timer register 2 TMCO 16 bit timer mode control 184 TMC1 8 bit timer mode con
73. SRIF SBI serial bus interface 2 wire serial I O Use possible UART Asynchronous serial interface None None Use possible 287 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 16 1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes Operation stop mode e 3 wire serial I O mode SBI serial bus interface mode 2 wire serial I O mode 1 2 3 288 Caution Do not switch the operation mode 3 wire serial I O 2 wire serial I O SBI of serial interface channel 0 Switch the operation mode after stopping the serial operation Operation stop mode This mode is used when serial transfer is not carried out Power consumption can be reduced 3 wire serial mode MSB LSB first selectable This mode is used for 8 bit data transfer using three lines one each for serial clock SCKO serial output SOO and serial input SIO This mode enables simultaneous transmission reception and therefore reduces the data transfer processing time The start bit of transferred 8 bit data is switchable between MSB and LSB so that devices can be connected regardless of their start bit recognition This mode should be used when connecting with peripheral I O devices or display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X XL 78K and 17K series SBI serial bus
74. Table 8 6 16 Bit Timer Event Counter Interval Times Minimum Interval Time Maximum Interval Time Resolution MCS 1 MCS 0 2 x TIOO input cycle MCS 1 216 x TIOO MCS 0 input cycle MCS 1 TIOO input MCS 0 edge cycle Setting prohibited 2 x 1 fx 400 ns Setting prohibited 216 x 1 fx 13 1 ms Setting prohibited 1 fx 200 ns 2 x 1 fx 400 ns 22 x 1 fx 800 ns 216 x 1 fx 13 1 ms 217 x 1 fx 26 2 ms 1 fx 200 ns 2 x 1 fx 400 ns 22 x 1 fx 800 ns 23 x 1 fx 1 6 us 217 x 1 fx 26 2 ms 218 x 1 fx 52 4 ms 2 x 1 fx 400 ns 22 x 1 fx 800 ns 23 x 1 fx 1 6 us 24 x 1 fx 3 2 us 218 x 1 fx 52 4 ms 219 x 1 fx 104 9 ms 22 x 1 fx 800 ns 23 x 1 fx 1 6 us 1 1 216 x watch timer output cycle 2 x watch timer output cycle Watch timer output edge cycle Other than above Setting prohibited Remarks 1 fx Main system clock oscillation frequency 2 MCS Bit 0 of oscillation mode selection register OSMS 3 04 to TCLO6 Bits 4 to 6 of timer clock select register 0 TCLO 4 Figures in parentheses apply to operation with fx 2 5 0 MHz 8 5 2 PWM output operations Setting the 16 bit timer mode control register TMCO capture compare control register 0 CRCO and the 16 bit timer output control register TOCO as shown in Figure 8 13 allows operation as PWM output
75. u 319 16 22 AGKT Operation tad i tette td e pa pede oe ee aW eum ER 320 16 23 SACER IMEEM E 321 16 24 ACKD Operations einen cede ees Ae ee etn ei eve cree ded 322 16 25 BSYE Operation kus uite eere debo tee teet 322 16 26 Pin Configuration tende e ate ete dev t 325 16 27 Address Transmission from Master Device to Slave Device WUP 1 327 16 28 Command Transmission from Master Device to Slave Device 328 16 29 Data Transmission from Master Device to Slave Device 329 16 30 Data Transmission from Slave Device to Master Device 330 16 31 Serial Bus Configuration Example Using 2 Wire Serial I O Mode 333 16 32 2 Wire Serial Mode Timings nennen nennen nennen nennen nennen 337 16 33 0 L Saul a musauti us 338 16 34 SCK0 P27 Pin Configiirallori eccentric 339 17 1 Serial Bus Configuration Example Using Bus cccccccsccsessesceseeeeeseeeeseeecseeeeseeecseseesesaeseeateees 343 17 2 Serial Interface Channel 0 Block 345 17 3 Timer
76. 1 External reset input with RESET pin 2 Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences In both cases program execution starts at the address at 0000H and 0001H by RESET input When a low level is input to the RESET pin or the watchdog timer overflows a reset is applied and each hardware is set to the status as shown in Table 24 1 Each pin has high impedance during reset input or during oscillation stabilization time just after reset clear When high level is input to the RESET input the reset is cleared and program execution starts after the lapse of oscillation stabilization time 217 fx The reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time 217 fx see Figure 24 2 to 24 4 Cautions 1 For an external reset input a low level for 10 us or more to the RESET pin 2 During reset input main system clock oscillation remains stopped but subsystem clock oscillation continues 3 When the STOP mode is cleared by reset the STOP mode contents are held during reset input However the port pin becomes high impedance Figure 24 1 Block Diagram of Reset Function med Reset Reset Control Circuit Signal Over flow Interrupt Count Clock Watchdog Timer gt Function Stop 533 CHAPTER 24 RESET FUNCTION Fig
77. 18 21 Operation Timings when Using Busy amp Strobe Control Option BUSYO 0 433 18 22 Operation Timing of the Bit Slippage Detection Function Through the Busy Slgnal when 5 0 1 iE t ete Eee ee u m ed Uc supa 434 18 23 Automatic Data Transmit Receive Interval 435 18 24 Operation Timing with Automatic Data Transmit Receive Function Performed by qe P 436 19 1 Serial Interface Channel 2 Block 441 19 2 Baud Rate Generator Block Diagram sess 442 19 3 Serial Operating Mode Register 2 Format sss nennen 444 19 4 Asynchronous Serial Interface Mode Register 445 19 5 Asynchronous Serial Interface Status Register Format 447 19 6 Baud Rate Generator Control Register Format nennen 448 19 7 Asynchronous Serial Interface Transmit Receive Data 461 19 8 Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing 463 19 9 Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing 464 19 10 Receive Error iet EI maa EGRE ED RE EP ERRARE 465 19 11 The State of Receive Buffer Register RXB and Whether the Receive Completion Interrupt Request INTSR is Generated u
78. 21 8 Noise Eliminator Input Output Timing during rising edge detection 495 21 9 Program Status Word Configuration esses nennen nennen nee 496 21 10 Flowchart of Generation from Non Maskable Interrupt Request to Acknowledgment 498 21 11 Non Maskable Interrupt Request Acknowledge Timing een 498 21 12 Non Maskable Interrupt Request Acknowledge Operation seen 499 21 13 Interrupt Request Acknowledge Processing 501 21 14 Interrupt Request Acknowledge Timing Minimum 502 21 15 Interrupt Request Acknowledge Timing Maximum Time 1 502 21 16 Multiple Interrupt enne nennen ennemi 504 21 17 lnterrupt Request Hold eem oe OR REOR e i ERES 506 21 18 Basic Configuration of Test Function L 507 21 19 Format of Interrupt Request Flag Register 11 508 21 20 Format of Interrupt Mask Flag Register 1L 508 21 21 Key Return Mode Register Formal uu nnne nennen nennen 509 22 1 Memory Map when Using External Device Expansion Function 512 22 2 Memory Expansion Mode Register Format
79. 24576 x 8 bits Vector Table Area Y Y 0000H 0000H 92 CHAPTER 5 CPU ARCHITECTURE Figure 5 3 Memory Map uPD78054 78054Y A Special Function Registers SFRs 256 x 8 bits General Registers 32 x 8 bits Internal High speed RAM 1024 x 8 bits FBOOH FAFFH Reserved FAEOH FADFH 7FFFH Internal Buffer RAM 32 x 8 bits Program Area FACOH Data memory FABFH 1000H space Reserved OFFFH FA7FH CALLF Entry Area 0800H External Memory 07FFH 31360 x 8 bits Program Area Program memory H space 7 8000 CALLT Table Area Internal ROM ut 32768 x 8 bits Vector Table Area Y Y 0000H 0000H CHAPTER 5 CPU ARCHITECTURE Figure 5 4 Memory Map uPD78P054 Data memory space Special Function Registers SFRs 256 x 8 bits General Registers 32 x 8 bits Internal High speed RAM Program memory Space 1024 x 8 bits FBOOH FAFFH Reserved FAEOH FADFH 7FFFH Internal Buffer RAM 32 x 8 bits Program Area FACOH 1000H eserve FA80H OFFFH FA7FH CALLF Entry Area 0800H External Memory 07FFH 31360 x 8 bits Program Area 0080H 007 7FFFH CALLT Table Area Internal PROM 32768 8 bits BUSH Vector Table Area 0000H 0000H 94 CHAPTER 5 CPU ARCHITECTURE Figure 5 5 Memory Map uPD78055 78055Y
80. 5 22 General registers ER ROREM HAT U D RR RR 112 5 2 3 Special Function Register SFR u u asan agama nnne nnn 114 5 3 Instruction Address Addressing 118 5 3 1 Re elative addresSIng _ ide c e tee aha tette REL a sieved e e E TR 118 5 3 2 Immediate acddressing uuu ice eo pae e p eate 119 18 5 3 3 Table indirect addressing 2 42242 4 e 5 3 4 Register addressing et dpe antes 5 4 Operand Address Addressing u u u u 5 4 1 Implied addressing etm cde eed te er re ua qa 5 4 2 Fiegister addressliQ usc ae cec d e E etd e e 5 4 8 Directaddressing y u n RD eae o e Ee a eR i de 5 4 4 Shortdirect addressirig oue deer rhe ee o enti 5 4 5 Special Function Register SFR addressing 5 4 6 Register indirect addressing 1 U 5 4 7 ioi Ho huku al E uuu usata has 5 4 8 Based indexed addressing U u u 54 9 Stack addresSSiNg y uiid edite tid ced tcd kh ade teret aet CHAPTER 6 PORT FUNCTIONS inniti cete W cernes 6 1 Port F nctlons i 6 2 Port Gonfigurallon DELI DIEA uu a
81. 6 2 1 POL a tfe te mit ein i Pete UU feto du uet eee as 6 2 2 EEG S EE 6 2 3 Port 2 uPD78054 S bseries eite t rrt et 6 2 4 Port 2 uPB 79054Y Su bse ries x nb e eed eene 6 2 5 POM ix ana aan ine 6 2 6 SSES susu RARUS URN aaa a s ua ERRARE 6 2 7 Ad e EE OE CD 6 2 8 Men LP 6 2 9 pac 6 2 10 POM ote bie IR en Mah u D eed diee es icem t 6 2 11 Pott 195 EEE te E eral tdt dibus 6 3 Port Function Control Registers u uu u 6 4 Port Function Operations u u u u 6 4 1 Writing to input output 6 4 2 Reading from input o utp tiport u au u a ara a aa 6 4 3 Operations on input output 6 5 Selection of Mask Option u u u uu u CHAPTER 7 CLOCK GENERATQOR nene anat snas u u u u asas seen J 7 1 Clock Generator Functions u uuu u u u 7 2 Clock Generator Configuration uuu uu u 7 3 Clock Generator Control Register u u u 7 4 System Clock Oscillator l
82. A laddr 6 o mi rnm nmio nmqj rnij rnmtjrn lt A addr16 HL A A x HL A lt A v HL byte A HL byte A HL B A lt A v HL B A HL C A A v HL C Notes 1 When the internal high speed RAM area is accessed or instruction with no data access A byte A byte saddr byte saddr byte o m rnmj rnmijico nmij rni rnm i r N 9 5 OO j OO O ojojoj O Oj o o O 2 When an area except the internal high speed RAM area is accessed 3 Except r A Remarks 1 2 3 n is the number of waits when external memory expansion area is read from One instruction clock cycle is one cycle of the CPU clock fcPu selected by the processor clock control register PCC This clock cycle applies to internal ROM program 567 CHAPTER 27 INSTRUCTION SET Instruction Group Mnemonic Operands Operation AX CY AX word CY lt AX word AX word Ax X AX Quotient C Remainder AX C 4 rer i saddr saddr 1 rer 1 saddr saddr 1 Increment decrement rp rp 1 rp lt 1 CY A lt Ao 1 lt Am x 1 time CY Ao lt Am 1 lt Am x 1 time CY l
83. A bit addr16 PC amp PC 3 jdisp8 if A bit 1 then reset A bit PSW bit addr16 PC PC 4 jdisp8 if PSW bit 1 then reset PSW bit HL bit addr16 PC lt PC 3 jdisp8 if HL bit 1 then reset HL bit B addr16 B lt B 1 then PC PC 2 jdisp8 if B z 0 C addr16 C C 1 then PC PC 2 jdisp8 if C z 0 saddr addr16 saddr saddr 1 then PC lt PC 3 jdisp8 if saddr 0 RBn RBS1 0 lt n No Operation IE 1 Enable Interrupt IE O Disable Interrupt Set HALT Mode Set STOP Mode Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed Remarks 1 One instruction clock cycle is one cycle of the CPU clock fceu selected by the processor clock control register PCC 2 This clock cycle applies to internal ROM program 3 n is the number of waits when external memory expansion area is read from 4 m is the number of waits when external memory expansion area is written to 571 CHAPTER 27 INSTRUCTION SET 27 8 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4 PUSH POP DBNZ 572 27 INSTRUCTION SET Second Operand First Op
84. ADTI 4 Write any value to the serial I O shift register 1 5101 transfer start trigger Caution Writing any value to SIO1 orders the start of automatic transmit receive operation and the written value has no meaning The following operations are automatically carried out when a and b are carried out Afterthe buffer RAM data specified with ADTP is transferred to SIO1 transmission is carried out start of automatic transmission reception The received data is written to the buffer RAM address specified with ADTP ADTP is decremented and the next data transmission reception is carried out Data transmission reception continues until the ADTP decremental output becomes 00H and address FACOH data is output end of automatic transmission reception When automatic transmission reception is terminated bit 3 TRF of ADTC is cleared to 0 416 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 3 Communication operation a SCK1 501 SH CSIIF1 TRF Basic transmission reception mode This transmission reception mode is the same as the 3 wire serial I O mode in which specified number of data are transmitted received in 8 bit units Serial transfer is started when any data is written to the serial I O shift register 1 SIO1 while bit 7 CSIE1 of the serial operating mode register 1 CSIM1 is set to 1 The interrupt request flag CSIIF1 is set upon completion of transmission of the last byte However judge th
85. CRC02 CRC01 CRC00 Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with the external event CROO set as compare register counter See the description of the respective control registers for details 204 CHAPTER 8 16 TIMER EVENT COUNTER Figure 8 27 External Event Counter Configuration Diagram 16 Bit Capture Compare Register 00 CROO 7 16 Bit Time gt 00 rR egister TM0 gt INTPO 16 Bit Capture Compare Register 01 CRO1 Internal Bus Figure 8 28 External Event Counter Operation Timings with Rising Edge Specified psp T esee EE Tr de d TMO Count Value Xooooyoooryooozyooos ooo yooos 0 X N T X ooo yoooz X00057 INTTMO Caution When reading the external event counter count value TMO should be read 205 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 5 6 Square wave output operation Operates as square wave output with any selected frequency at intervals of the count value preset to the 16 bit capture compare register 00 CROO The TOO P30 pin output status is reversed at intervals of the count value preset to CROO by setting bit 0 TOEO and bit 1 TOC01 of the 16 bit timer output control register to 1 This enables a square wave with any selected frequency to be output 206 Figure 8 29 Control Register Se
86. Control Register Settings for PWM Output 2 2 44 0 194 8 14 Example of D A Converter Configuration with PWM Output eene 195 8 15 TV Tuner Application Circuit Example 0 44 4 01000 ns 195 8 16 Control Register Settings for PPG Output Operation sse 196 8 17 Control Register Settings for Pulse Width Measurement with Free Running Counter and One Capture Register iiid Ro d eie tiores ide PR xD b ap S Re SOR UR ete Rag 197 8 18 Configuration Diagram for Pulse Width Measurement by Free Running Counter 198 8 19 Timing of Pulse Width Measurement Operation by Free Running Counter and One Capture Register with Both Edges 198 8 20 Control Register Settings for Two Pulse Width Measurements with Free Running Counter 199 8 21 Timing of Pulse Width Measurement Operation with Free Running Counter with Both Edges eerte PERIERE UFU ERR 200 8 22 Control Register Settings for Pulse Width Measurement with Free Running Counter and 26 Two Capture Registers 4 Q a L IR e e ERE POR qusa ats 201 Figure No LIST OF FIGURES 3 8 8 23 8 24 8 25 8 26 8 27 8 28 8 29 8 30 8 31 8 32 8 33 8 34 8 35 8 36 8 37 8 38 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 9 10 9 11 9 12 9 13 9 14 9 15 9 16
87. FAFFH Reserved FAEOH FADFH EFFFH Internal Buffer RAM 32 x 8 bits Program Area FACOH Data memory FABFH z d 1000H eserve space F800H OFFFH F7FFH CALLF Entry Area Internal Expansion RAM 0800H 1024 x 8 bits 07FFH F400H Program Area F3FFH Reserved 0080H FOOOH DEN CALLT Table Area Program Internal ROM memory 61440 x 8 bits Space Vector Table Area Y 0000H 0000H Note When internal ROM size is 60K bytes the area FOOOH to F3FFH cannot be used F000H to F3FFH can be used as external memory by setting the internal ROM size to less than 56K bytes by the memory size switching register IMS 97 CHAPTER 5 CPU ARCHITECTURE Figure 5 8 Memory Map uPD78P058 u PD78P058Y Special Function Registers SFRs 256 x 8 bits General Registers 32 x 8 bits Internal High speed RAM 1024 x 8 bits FBOOH FAFFH Reserved FAEOH FADFH EFFFH Internal Buffer RAM 32 x 8 bits Program Area FACOH Data memory FABFH 1000H space F800H Reserved OFFFH F7FFH CALLF Entry Area Internal Expansion RAM 0800H 1024 x 8 bits 07FFH Program Area F400H F3FFH Reserved 0080H F000H 007 ERER CALLT Table Area Program 0040H Internal PROM memory 61440 x 8 bits 003FH space Vector Table Area Y 0000H 0000H Note When internal PROM size is 60K bytes the area FOOOH to F3FFH cannot be used F000H to F3FFH can be used as external memory by setting the internal
88. Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if
89. In the SBI mode clear WUP to 0 before stopping CSIE lt 0 the operation of serial interface channel 0 otherwise P25 is fixed to high level and may not be able to be used as a normal port 297 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 3 Serial bus interface control register SBIC This register sets serial bus interface operation and displays statuses SBIC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SBIC to 00H Figure 16 5 Serial Bus Interface Control Register Format 1 2 Symbol 7 2 gt lt gt 0 Address After Reset R W SBIC BSYE ACKD mmm DIRELD CMDT RELT FF61H 00H R WNote R W Used for bus release signal output When RELT 1 SOO latch is set to 1 After SOO latch setting automatically cleared to 0 Also cleared to 0 when CSIEO 0 R W Used for command signal output When CMDT 1 SOO latch is cleared to 0 After SOO latch clearance automatically cleared to 0 Also cleared to 0 when CSIEO 0 RELD Bus Release Detection Clear Conditions RELD 0 Set Conditions RELD 1 When transfer start instruction is executed If SIOO and SVA values do not match in address reception When bus release signal REL is detected When CSIEO 0 When RESET input is applied CMDD Command Detection Clear Conditions CMDD 0 Set Conditions CMDD 1 When transfer start instruction is executed When bus release sig
90. Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing 503 21 5 Test Input Factors aH pete t T E aqa ec tie bus ua te Pep tvi 507 21 6 Flags Corresponding to Test Input Signals a 507 22 1 Pin Functions in External Memory Expansion 511 22 2 State of Ports 4 to 6 Pins in External Memory Expansion 511 22 3 Values when the Memory Size Switching Register is Reset 517 23 1 HALT Mode Operating Status 0 0 UL L L L n m u D asua au sisa 527 23 2 Operation after HALT Mode Release nennen ennt 529 23 3 STOP Mode Operating Status u aa 530 23 4 Operation after STOP Mode Release 1 532 24 1 Hardware Stat s aflerResetu u L a l Rp ete rode een ee 535 25 1 ROM Correction Configuration essen nennen nennen nnne nnn 537 26 1 Differences between uPD78P054 78P058 and Mask ROM Versions 547 26 2 Differences between uPD78P054 and 78P058 sse nene 548 26 3 Examples of Memory Size Switching Register Settings 78 54 549 26 4 Examples of Memory Size Switching Register Settings uPD78P058
91. PM13 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register H PUOH 2 Control mode These ports allow D A converter analog output ANOO and ANO1 Caution When only either one of the D A converter channels is used with AVreri lt Vpp the other pins that are not used as analog outputs must be set as follows Set PM13x bit of the port mode register 13 PM13 to 1 input mode and connect the pin to Vss Set PM13x bit of the port mode register 13 PM13 to 0 output mode and the output latch to 0 to output low level from the pin 4 2 11 AVREFo A D converter reference voltage input pin When A D converter is not used connect this pin to Vss 4 2 12 AVREF1 D A converter reference voltage input pin When D A converter is not used connect this pin to 4 2 13 AVpp Analog power supply pin of A D converter Always use the same voltage as that of the Vpp pin even when A D converter is not used 4 2 14 AVss This is a ground voltage pin of A D converter and D A converter Always use the same voltage as that of the Vss pin even when neither A D nor D A converter is used 4 2 15 RESET This is a low level active system reset input pin 85 CHAPTER 4 PIN FUNCTION uPD78054Y Subseries 4 2 16 X1 and X2 Crystal resonator connect pins for main system clock oscillation For external clock supply input it to X1 and its inverted signal to X2 4 2 17 XT1
92. Register setting The 3 wire serial I O mode with automatic transmit receive function is set with the serial operating mode register 1 CSIM1 the automatic data transmit receive control register ADTC and the automatic data transmit receive interval specify register ADTI a Serial operating mode register 1 CSIM1 CSIM1 is set with 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM1 to 00H 409 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Symbol 27 6 5 4 3 2 1 0 Address After Reset R W cam CSIM11 CSIM10 Serial Interface Channel 1 Clock Selection Clock externally input to SCK1 pinNote 1 8 bit timer register 2 TM2 output Clock specified with bits 4 to 7 of timer clock select register 3 TCL3 Serial Interface Channel 1 Operating Mode Selection 0 3 wire serial I O mode 1 3 wire serial I O mode with automatic transmit receive function Din Start Bit SH Pin Function SO 1 Pin Function 0 MSB SH P20 SO1 1 LSB Input CMOS output Note 2 x CSIE1 CSIM11 PM20 P20 PM21 P21 PM22 P22 Note 2 Note 2 Note 2 Note 2 x x x x Shift Register 1 Operation Operation stop Serial Clock Counter Operation Control SI1 P20 Pin Function P20 CMOS input output SO1 P21 Pin Function P21 CMOS input output SCK1 P22 Pin Function P22 CMOS input output Note 3 1 Note 3 x Operation enable Count opera
93. SCKO SCL P27 Pin Configuration Manipulated by bit manipulation instruction SCKO SCL P27 O D To internal logic 27 output latch 4 C SCKO 1 while transfer is stopped pus serial nd CSIEO 1 and CSIMO1 CSIMOO are 1 0 or 1 1 respectively controller 2 In 2 bus mode The output level of the SCKO SCL P27 pin is manipulated by the CLC bit of the interrupt timing specify register SINT 1 Setthe serial operating mode register 0 CSIMO SCL pin is set in the output mode and serial operation is enabled Set 1 to the P27 output latch SCL 0 while serial transfer is stopped 2 Manipulate the CLC bit of SINT by executing the bit manipulation instruction Figure 17 28 SCKO SCL P27 Pin Configuration Set 1 SCKO SCL P27 O gt To internal logic P27 output latch M CH ScL et From serial clock controller CSIEO 1 and CSIMO1 and CSIMOO are 1 0 or 1 1 respectively Note The level of the SCL signal is in accordance with the contents of the logic circuits shown in Figure 17 29 390 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries Figure 17 29 Logic Circuit of SCL Signal CLC manipulated by bit manipulation instruction SCL Wait request signal Serial clock low while transfer is stopped Remarks 1 This figure indicates the relation of the signals and does not indicate the internal circuit 2 CLC Bit 3 of interrupt timing spe
94. SCKO to SCK1 SCL SDAO SDA1 510 SI SO0 SO1 STB TH TI2 TIOO to TIO1 TOO to TO2 TxD Vpp VPP Vss WAIT wR X1 X2 XT1 XT2 Programmable Clock Reset Read Strobe Real Time Output Port Receive Data Serial Bus Serial Clock Serial Clock Serial Data Serial Input Serial Output Strobe Timer Input Timer Input Timer Output Transmit Data Power Supply Programming Power Supply Ground Wait Write Strobe Crystal Main System Clock Crystal Subsystem Clock CHAPTER 2 OUTLINE uPD78054Y Subseries 2 PROM programming mode 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm uPD78P058YGC 8BT 80 pin ceramic WQFN 14 x 14 mm uPD78P058YKK T a n a SOS OS OQOOOOOOOOOOOOOQOcOOOoOQO en quts o PGM lt O 1 O RESET D4 O 2 O O 3 O O Vss 4 O O 5 O L O 6 5 L 7 O 8 O O 9 O O O D7 O O D6 O O D5 940 O D4 O O D3 O O D2 O O D1 O O DO m 1 lt lt lt lt lt gt 3 Cautions 1 L Connect individually to Vss via a pull down resistor 2 Vss Connect to the ground 3 RESET Set to the low level 4 Open Leave this pin unconnected AO to A16 Address Bus RESET Reset CE Chip Enable Vpp Power Supply D0 to D7 Data Bus VPP Programming Power Supply OE Output Enable Vss Ground PGM Program 53 CHAPTER
95. TO2 16 bit timer TMO output also used for 14 bit PWM output 8 bit timer TM1 output 8 bit timer TM2 output P30 P31 P32 PCL Output Clock output for main system clock and subsystem clock trimming P35 BUZ Output Buzzer output P36 to RTP7 Output 78 Real time output port outputting data in synchronization with trigger P120 to P127 CHAPTER 4 PIN FUNCTION uPD78054Y Subseries 2 Pins other than port pins 2 2 Input Output Function After Reset Alternate Function Low order address data bus when expanding external memory P40 to P47 Output High order address bus when expanding external memory P50 to P57 Output Strobe signal output for read operation from external memory P64 Strobe signal output for write operation to external memory Input Wait insertion when accessing external memory Output Strobe output externally latching address information output to ports 4 5 to access external memory Input A D converter analog input P10 to P17 Output D A converter analog output P130 P131 AVREFo Input A D converter reference voltage input AVREF1 Input D A converter reference voltage input AVpp A D converter analog power supply Connect to AVss A D and D A converter ground potential Connect to Vss RESET System reset input Crystal connection for main system clock oscillation Cryst
96. Used 12C bus mode 9 clock wait Generates an interrupt service request on rise of 9th SCL clock cycle In case of master device SCL pin is driven low after output of 9 clock cycles to enter the wait state In case of slave device SCL pin is driven low after input of 9 clock cycles to require the wait state Indicates that the wait state has been released Releases the wait state Automatically cleared to 0 after releasing the wait state This bit is used to release the wait state set by means of WATO and WAT1 Clock level control Used in 2 bus mode In cases other than serial transfer SCL pin output is driven low Used in 2 bus mode In cases other than serial transfer SCL pin output is set to high impedance Clock line is held high Used by master device to generate the start condition and stop condition signals R W SVAM SVA bits used as slave address 0 Bits 0 to 7 1 Bits 1 to 7 INTCSAIO interrupt source selectionNote 3 0 CSIIFO is set to 1 after end of serial interface channel 0 transfer 1 CSIIFO is set to 1 after end of serial interface channel 0 transfer or when stop condition is detected SCL pin level See Note 4 0 Low level 1 High level Notes 1 Bit 6 CLD is read only 2 When the I C bus mode is used be sure to set 1 and 0 or 1 and 1 in and WAT1 respectively 3 When using the wake up function in IC mode be sure to set SIC to 1 4 When CSIEO 0 CLD is 0
97. Vin OE ViL Cautions 1 Be sure to apply Voo before applying VPP and remove it after removing VPP 2 VPP must not exceed 13 5 V including overshoot voltage 3 Disconnecting inserting the device from to the on board socket while 12 5 V is being applied to the VPP pin may have an adverse affect on device reliability 557 CHAPTER 26 uPD78P054 78P058 26 4 3 PROM reading procedure PROM contents can be read onto the external data bus DO to D7 using the following procedure 1 Fix the RESET pin low and supply 5 V to the VPP pin Unused pins are handled as shown in paragraph 2 PROM programming mode in section 1 5 or 2 5 Pin Configuration Top View Supply 5 V to the Voo and VPP pins Input the address of data to be read to pins AO through A16 Read mode is entered Data is output to pins DO through D7 2 3 4 5 va Sw The timing for steps 2 through 5 above is shown in Figure 26 8 Figure 26 8 PROM Read Timing 0 16 Address Input 558 CHAPTER 26 uPD78P054 78P058 26 5 Erasure Procedure uPD78P054KK T and 78P058KK T Only With the uPD78P054KK T or 78P058KK T it is possible to erase or set all contents to FFH the data contents written in the program memory and rewrite the memory The data can be erased by exposing the window to light with a wavelength of approximately 400 nm or shorter Typically data is erased by 254 nm ultraviolet light rays The minimum lighting
98. broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged b Release by unmasked test input When an unmasked test signal is input the STOP mode is cleared And after the lapse of oscillation stabilization time the instruction at the next address of the STOP instruction is executed 531 CHAPTER 23 STANDBY FUNCTION c Release by RESET input When a RESET signal is input the STOP mode is released And after the lapse of oscillation stabilization time reset operation is carried out Figure 23 5 Release by STOP Mode RESET Input Wait 2 fx 26 2 ms STOP Instruction RESET Signal Oscillation Operating Reset Stabilization Operating Mode STOP Mode Period Wait Status Mode Oscillation Oscillation Stop Oscillation Clock m Remarks 1 fx main system clock oscillation frequency 2 y fx 5 0 MHz Table 23 4 Operation after STOP Mode Release Release Source Operation Maskable interrupt request Next address instruction execution Interrupt service execution Next address instruction execution Interrupt service execution STOP mode hold Test input Next address instruction execution STOP mode hold RESET input Reset processing Remark x Don t care 532 CHAPTER 24 RESET FUNCTION 24 1 Reset Function The following two operations are available to generate the reset signal
99. is set to 0 the 5 bit counter is cleared and the count operation stops For simultaneous operation of the interval timer zero second start can be achieved by setting TMC22 to 0 maximum error 26 2 ms when operated at fxx 5 0 MHz 10 4 2 Interval timer operation The watch timer operates as interval timer which generates interrupt requests repeatedly at an interval of the preset count value The interval time can be selected with bits 4 to 6 TMC24 to TMC26 of the watch timer mode control register Table 10 3 Interval Timer Interval Time When operated at When operated at When operated at TMC24 Interval Time fxx 5 0 MHz fxx 4 19 MHz 32 768 kHz 24 x 1 fw 25 x 1 fw 26 x 1 fw 27 x 1 fw 28 x 1 fw 0 29 x 1 fw Other than above Setting prohibited Remark fxx Main system clock frequency or fx 2 fx Main system clock oscillation frequency fxt Subsystem clock oscillation frequency fw Watch timer clock frequency fxx 2 or fxr 246 11 1 Watchdog Timer Functions CHAPTER 11 The watchdog timer has the following functions Watchdog timer nterval timer WATCHDOG TIMER Caution Selectthe watchdog timer mode orthe interval timer mode with the watchdog timer mode register WDTM The watchdog timer and interval timer cannot be used at the same time 1 Watchdog timer mode An inadvertent program loop runaway is detected Upon detection of
100. lt gt lt 0 gt After Address Reset R W FFEOH 00H R W FFE1H 00H R W FFE2H 00H R W No interrupt request signal Interrupt request signal is generated Interrupt request state Note WTIF is test input flag Vectored interrupt request is not generated Cautions 1 TMIF4 flag is R W enabled only when a watchdog timer is used as an interval timer mode If a watchdog timer is used in watchdog timer mode 1 set TMIFA flag to O 2 Set always 0 in IF1L bits 3 through 6 489 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 2 Interrupt mask flag registers MKOL MK1L The interrupt mask flag is used to enable disable the corresponding maskable interrupt service and to set standby clear enable disable MKOL MKOH and MK1L are set with a 1 bit or 8 bit memory manipulation instruction If MKOL and MKOH are used as a 16 bit register MKO use a 16 bit memory manipulation instruction for the setting RESET input sets these registers to FFH Symbol MKOL MKOH MK1L Figure 21 3 Interrupt Mask Flag Register Format After lt gt 6 5b 4 39 lt gt lt gt 0 Address Reset R W PMK6 PMK5 4 PMK3 PMK2 4 FFE4H FFH R W lt gt 0 5b 4 98 lt gt lt gt 0 TMMKO1 TMMK00 TMMK3 STMK SRMK SERMK CSIMK1 CSIMKO FFE5H FFH R W lt 7 gt 6 5 4 3 2 lt gt lt 0 gt WIMK 1 1 1 1 ADMK TMMK2 TMM
101. mode is set with the serial operating mode register 0 CSIMO the serial bus interface control register SBIC and the interrupt timing specify register SINT a Serial operating mode register 0 CSIMO CSIMO is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets Symbol 7 Address After Reset R W e R W CSIMO1 CSIMOO Serial Interface Channel 0 Clock Selection Input clock from off chip to SCL pin 8 bit timer register 2 TM2 output SeeNete 2 Clock specified with bits 0 to 3 of timer clock select register 3 TCL3 R W 3 wire seria i ion 3 wire serial mode 0 x x 2 wire P25 SB1 SDA1 SCKO SCL Note 3 Note 3 serial I O or CMOS I O N chopen N ch open 2 bus mode drain I O drain 2 wire SBO SDAO P26 SCKO SCL serial I O or N ch open CMOS I O N ch open bus mode drain O drain I O R W WUP Wake up Function ControlNote 4 Interrupt request signal generation with each serial transfer in any mode In 12 bus mode interrupt request signal is generated when the address data received after start condition detection when CMDD 1 matches data in slave address register SVA R Slave Address Comparison Result Flag SeeNote 5 Slave address register SVA not equal to data in serial I O shift register 0 5100 Slave address register SVA equal to data in serial I O
102. set When the automatic transmit receive function is used by the external clock it must be selected so that the interval may be longer than the values shown as follows Table 18 3 Interval Timing Through CPU Processing when the external clock is operating CPU Processing Interval Time When using multiplication instruction 13TcPu When using division instruction 20TcPu External access 1 wait mode 9TcPu Other than above Remark l fcPu 7TcPu fcpu CPU clock set by the bits 0 to 2 PCCO to PCC2 of the processor clock control register PCC and bit 0 MCS of the oscillation mode selection register OSMS 437 438 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19 1 Serial Interface Channel 2 Functions Serial interface channel 2 has the following three modes Operation stop mode Asynchronous serial interface UART mode 3 wire serial mode 1 2 3 Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption Asynchronous serial interface UART mode In this mode one byte of data is transmitted received following the start bit and full duplex operation is possible A dedicated UART baud rate generator is incorporated allowing communication over a wide range of baud rates In addition the baud rate can be defined also by scaling the input clock to the ASCK pin The MIDI standard baud rate 31 25
103. watch timer Generation of 16 bit timer register INTTMOO capture compare register CROO match signal Generation of 16 bit timer register INTTMO1 capture compare register CRO1 match signal Generation of 8 bit timer event INTTM1 counter 1 match signal INTTM2 Generation of 8 bit timer event counter 2 match signal INTAD End of A D converter conversion Software BRK BRK instruction execution Notes 1 Default priorities are intended for two or more simultaneously generated maskable interrupt requests 0 is the highest priority and 18 is the lowest priority 2 Basic configuration types A to E correspond to A to E of Figure 21 1 485 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21 1 Basic Configuration of Interrupt Function 1 2 A Internal non maskable interrupt Internal Bus Vector Table Interrupt Priority Control Address Request Circuit Generator Standby Release Signal B Internal maskable interrupt Internal Bus Priority Control Interrupt Circuit Generator Request Standby Release Signal C External maskable interrupt INTPO Internal Bus Sampling Clock Select Register SCS External Interrupt Mode Register INTMO Vector Table Sampling Address Clock Generator Interrupt Request Standby R
104. 0 Therefore interrupts are not acknowledged even when a maskable interrupt request is issued during the execution of the BRK instruction However non maskable interrupt requests are acknowledged Figure 21 17 shows the timing when an interrupt request is reserved Figure 21 17 Interrupt Request Hold CPU processing Instruction N Instruction M Save PSW and Interrupt service Jump to interrupt service program x x IF V Remarks 1 Instruction N Instruction that holds interrupts requests 2 Instruction M Instructions other than instruction N 3 The xxPR priority level values do not affect the operation of xxIF interrupt request 506 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21 5 Test Functions Upon occurrence of watch timer overflow and the detection of the falling falling edge of port 4 the corresponding test input flag is set 1 and a standby release signal is generated Unlike in the case of interrupt functions vector processing is not performed There are two test input sources as shown in Table 21 5 The basic configuration is shown in Figure 21 18 Table 21 5 Test Input Factors Test Input Factors Internal Trigger external INTWT Watch timer overflow Internal INTPT4 Falling edge detection at port 4 External Figure 21 18 Basic Configuration of Test Function Internal bus Test input signal Standby release signal Remark IF test input flag MK test mask flag
105. 0 and then set WDTM4 to 1 If WDTM4 is set to 1 when TMIF4 is 1 the non maskable interrupt request occurs regardless of the contents of WDTM3 Remark x Don t care 252 CHAPTER 11 WATCHDOG TIMER 11 4 Watchdog Timer Operations 11 4 1 Watchdog timer operation When bit 4 WDTMA of the watchdog timer mode register WDTM is set to 1 the watchdog timer is operated to detect any runaway The watchdog timer count clock runaway detection time interval can be selected with bits 0 to 2 TCL20 to 1 22 of the timer clock select register 2 TCL2 Watchdog timer starts by setting bit 7 RUN of WDTM to 1 After the watchdog timer is started set RUN to 1 within the set runaway detection time interval The watchdog timer can be cleared and counting is started by setting RUN to 1 If RUN is not set to 1 and the runaway detection time is past system reset or a non maskable interrupt request is generated according to the WDTM bit 3 WDTM3 value By setting RUN to 1 the watchdog timer can be cleared The watchdog timer continues operating in the HALT mode but it stops in the STOP mode Thus set RUN to 1 before the STOP mode is set clear the watchdog timer and then execute the STOP instruction Cautions 1 The actual runaway detection time may be shorter than the set time by a maximum of 0 5 96 2 When the subsystem clock is selected for CPU clock watchdog timer count operation is stopped Table 11 4 Watchdog Timer Runaway Detecti
106. 0 uPD78054 Subseries 16 4 3 SBI mode operation SBI Serial Bus Interface is a high speed serial interface in compliance with the NEC serial bus format SBI uses a single master device and employs the clocked serial I O format with the addition of a bus configuration function This function enables devices to communicate using only two lines Thus when making up a serial bus with two or more microcontrollers and peripheral ICs the number of ports to be used and the number of wires on the board can be decreased The master device outputs three kinds of data to slave devices on the serial data bus addresses to select a device to be communicated with commands to instruct the selected device and data which is actually required The slave device can identify the received data into address command or data by hardware This function simplifies the application program to control serial interface channel 0 The SBI function is incorporated into various devices including 75X XL Series and 78K Series Figure 16 10 shows a serial bus configuration example when a CPU having a serial interface compliant with SBI and peripheral ICs are used In SBI the SBO SB1 serial data bus pin is an open drain output pin and therefore the serial data bus line behaves in the same way as the wired OR configuration In addition a pull up resistor must be connected to the serial data bus line When the SBI mode is used refer to 11 SBI mode precautio
107. 00 00 pin is measured by clearing TMO and restarting the count see register settings in Figure 8 24 The edge specification can be selected from two types rising and falling edges by external interrupt mode register 0 INTMO bits 2 and 3 ES10 and ES11 In a valid edge detection the sampling is performed by a cycle selected by the sampling clock selection register SCS and a capture operation is only performed when a valid level is detected twice thus eliminating noise with a short pulse width Caution Ifthe valid edge of TI00 P00 is specified to be both rising and falling edge the 16 bit capture compare register 00 CROO cannot perform the capture operation Figure 8 24 Control Register Settings for Pulse Width Measurement by Means of Restart a 16 bit timer mode control register TMCO 03 02 01 OVFO b Capture compare control register 0 CRCO Clear amp start with valid edge of 00 00 CRC02 CRC01 00 eon CROO set as capture register Captured in CROO on invalid edge of 00 00 Pin CR01 set as capture register Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement See the description of the respective control registers for details Figure 8 25 Timing of Pulse Width Measurement Operation by Means of Restart with Rising Edge Specified NEUEN
108. 156 kHz fx 2 156 kHz fx 2 78 1 kHz fx 2 78 1 kHz fx 2 89 1 kHz fx 2 39 1 kHz fx 2 19 5 kHz 2 19 5 kHz fx 2 9 8 kHz fx 2 9 8 kHz fx 2 4 9 kHz fx 2 2 4 kHz fx 2 1 2 kHz Watchdog Timer Count Clock Selection 27 MCS 1 2 39 1 kHz fx 2 19 5 kHz 32 768 kHz TCL26 Buzzer Output Frequency Selection MCS 1 Buzzer output disable fxx 2 fx 2 9 8 kHz fx 2 4 9 kHz fxx 2 fx 2 4 9 kHz fx 2 2 4 kHz fxx 2 fx 2 2 4 kHz fx 2 1 2 kHz Setting prohibited Caution When rewriting TCL2 to other data stop the timer operation beforehand Remarks 1 2 9m m Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency Subsystem clock oscillation frequency x don t care MCS Bit 0 of oscillation mode selection register OSMS Figures in parentheses apply to operation with fx 5 0 MHz or fxr 32 768 kHz 263 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 2 Port mode register 3 PM3 This register sets port 3 input output in 1 bit units When using the P36 BUZ pin for buzzer output function set PM36 and output latch of P36 to 0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to Figure 13 3 Port Mode Register 3 Format After Symbol 7
109. 2 3 UART mode cautions a When bit 7 TXE of the asynchronous serial interface mode register ASIM is cleared and the transmission operation is stopped during transmission be sure to set the transmit shift register TXS to FFH then set the TXE to 1 before executing the next transmission b When bit 6 RXE of ASIM is cleared and the receive operation is stopped during reception the state of the receive buffer register RXB and whether the receive completion interrupt request INTSR is generated depend on the timing of clearing Figure 19 11 shows the timing Figure 19 11 The State of Receive Buffer Register RXB and Whether the Receive Completion Interrupt Request INTSR is Generated t w l l RXB T l INTSR lt gt When RXE is set to 0 at a time indicated by lt 1 gt RXB holds the previous data and does not generate INTSR When RXE is set to 0 at a time indicated by 2 RXB renews the data and does not generate INTSR When RXE is set to 0 at a time indicated by 3 renews the data and generates INTSR 466 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19 4 3 3 wire serial I O mode The 3 wire serial I O mode is useful for connection of peripheral I Os and display controllers etc which incorporate a conventional synchronous clocked serial interface such as the 75X XL series 78K series 17K series etc Communication is perf
110. 2 The baud rate transmit receive clock generated is either a signal scaled from the main system clock or a signal scaled from the clock input from the ASCK pin a Generation of baud rate transmit receive clock by means of main system clock The transmit receive clocks generated by scaling the main system clock The baud rate generated from the main system clock is found from the following expression Baud rate where fx fxx fxx 2 x T Hz Main system clock oscillation frequency Main system clock frequency fx or fx 2 Value set in TPSO TPS3 1 lt n lt 11 Value set in MDLO to MDL3 Ox k x 14 Table 19 3 Relation between Main System Clock and Baud Rate fx 2 5 0 MHz fx 2 4 19 MHz MCS 1 MCS 0 MCS 1 MCS 0 BRGC Set Value Error 96 BRGC Set Value Error 96 BRGC Set Value Error 96 BRGC Set Value Error 96 Remark MCS Oscillation mode selection register bit 0 450 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 b Generation of baud rate transmit receive clock by means of external clock from ASCK pin The transmit receive clock is generated by scaling the clock input from the ASCK pin The baud rate generated from the clock input from the ASCK pin is obtained with the following expression fasck Baud rate Hz 2 x k 16 fasck Frequency of clock
111. 2 Vector Table Interrupt Source RESET input Vector Table Address Interrupt Source INTSER INTWDT INTSR INTCSI2 INTPO INTST INTP1 INTTM3 INTP2 INTTMOO INTP3 INTTMO1 INTP4 INTTM1 INTP5 INTTM2 INTP6 INTAD INTCSIO BRK INTCSI1 2 CALLT instruction table area The 64 byte area 0040H to 007FH can store the subroutine entry address of a 1 byte call instruction CALLT 3 CALLF instruction entry area The area 0800H to OFFFH can perform a direct subroutine call with a 2 byte call instruction CALLF 99 CHAPTER 5 CPU ARCHITECTURE 5 1 2 Internal data memory space The uPD78054 and 78054Y subseries units incorporate the following RAMs 1 Internal high speed RAM The uPD78054 and 78054Y Subseries are provided with the internal high speed RAM as shown below Table 5 3 Internal High Speed RAM Capacity Part Number Internal High Speed RAM uPD78052 78052Y 512 x 8 bits FDOOH to FEFFH uPD78053 78053Y uPD78054 78054 uPD78P054 uPD78055 78055Y uPD78056 78056Y uPD78058 78058Y UPD78P058 78P058Y In this area four banks of general registers each bank consisting of eight 8 bit registers are allocated in the 32 byte area FEEOH to FEFFH 1024 x 8 bits FBOOH to FEFFH The internal high speed RAM can also be used as a stack memory 2 Buffer RAM Buffer RAM is alloca
112. 212 Timings After Change of Compare Register During Timer Count Operation 212 Capture Register Data Retention Timing T 213 Operation Timing Of OVFO Flag u u a m S p tue l 214 8 Bit Timer Event Counters 1 and 2 Block 221 Block Diagram of 8 Bit Timer Event Counter Output Control Circuit 1 222 Block Diagram of 8 Bit Timer Event Counter Output Control Circuit 2 222 Timer Clock Select Register 1 Formatl u enne 224 8 Bit Timer Mode Control Register 1 225 8 Bit Timer Output Control Register Format 226 Port Mode Register Format S u Su a ub nennen nns 227 Interval Timer Operation Timings u enne nnns 228 External Event Counter Operation Timings with Rising Edge Specified 231 Square Wave Output Operation Timing L 233 Interval Timer Operation Timing u 234 External Event Counter Operation Timings with Rising Edge Specified 236 Square Wave Output Operation Timing u 238 8 Bit Timer Registers 1 and 2 Start Timing
113. 27 INSTRUCTION SET l L cii eene oaa isuu 27 1 Legends Used in Operation u u u u uu u 27 1 1 Operand identifiers and description 0 27 1 2 Description of operation nennen 27 1 8 Description of flag operation 27 2 Operation List 27 3 Instructions Listed by Addressing Type s APPENDIX A DIFFERENCES BETWEEN uPD78054 78054Y SUBSERIES AND uPD78058F 78058FY SUBSERIES l u u u uuu u APPENDIX B DEVELOPMENT TOOLS J Language Processing Software u u uu u PROM Writing Tools iqu a Sia hala Sam ii asss B 1 B 2 B 3 B 2 1 B 2 2 aaa a h cec ded br cec Pet d Lec C E oe Ea eg Software Debugging lOols eerte EE EAER B 3 1 B 3 2 a EET s MERERI OPER A Software 23 B 4 OS for Esel 589 B 5 Upgrading Former In circuit Emulators for 78K 0 Series to IE 78001 R A 589 APPENDIX C EMBEDDED SOFTWARE u essen nsnm nna uu u 593 APPENDIX D REGISTER IN
114. 30 fsckNote Note Can only be used in 3 wire serial I O mode Remarks 1 fsck 5 bit counter source clock 2 k Value set in MDLO to MDL3 0 lt k lt 14 448 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19 6 Baud Rate Generator Control Register Format 2 2 5 Bit Counter Source Clock Selection MCS 1 MCS 0 fxx 210 fxx 210 4 9 kHz 2 4 kHz fxx fx 5 0 MHz 2 5 MHz fxx 2 fx 2 2 5 MHz fxx 22 fx 22 1 25 MHz 1 25 MHz 625 kHz fxx 23 fx 23 625 kHz 313 kHz fxx 24 fx 24 313 kHz 156 kHz fxx 25 fx 25 39 1 kHz fxx 27 fx 27 39 1 kHz 19 5 kHz IN O A A O N fxx 28 fx 28 19 5 kHz 9 8 kHz 9 8 kHz 156 kHz 78 1 kHz 26 fx 26 78 1 kHz fxx 29 fx 29 4 9 kHz E Other than above Setting prohibited Caution When datais written to BRGC during a communication operation baud rate generator output is disrupted and communication cannot be performed normally Therefore data must not be written to BRGC during a communication operation Remarks 1 fx Main system clock oscillation frequency 2 fxx Main system clock frequency fx or fx 2 3 MCS Oscillation mode selection register OSMS bit 0 4 n Value set in TPSO to TPS3 1 lt n lt 11 5 Figures in parentheses apply to operation with fx 2 5 0 MHz 449 CHAPTER 19 SERIAL INTERFACE CHANNEL
115. 4 5 366 Transfer start Serial transfer is started by setting transfer data to the serial I O shift register 0 SIOO when the following two conditions are satisfied Serial interface channel 0 operation control bit CSIEO 1 Internal serial clock is stopped or SCKO is at high level after 8 bit serial transfer Cautions 1 If CSIEO is set to 1 after data write to SIOO transfer does not start 2 Because the N ch open drain output must be set to high impedance state for data reception write to SIOO in advance Upon termination of 8 bit transfer serial transfer automatically stops and the interrupt request flag CSIIFO is set Error detection In the 2 wire serial I O mode the serial bus SBO SB1 status being transmitted is fetched into the destination device that is serial I O shift register 0 SIOO Thus transmit error be detected in the following way a Method of comparing SIOO data before transmission to that after transmission In this case if two data differ from each other a transmit error is judged to have occurred b Method of using the slave address register SVA Transmit data is set to both SIOO and SVA and is transmitted After termination of transmission COI bit match signal coming from the address comparator of the serial operating mode register 0 CSIMO is tested If 1 normal transmission is judged to have been carried out If 0 a transmit error is judged to have
116. 4 ees ia id P40 to P47 P47 AD7 WRwmu j PUO Pull up resistor option register MM Memory expansion mode register RD Port 4 read signal WR Port 4 write signal Figure 6 11 Block Diagram of Falling Edge Detection Circuit P40 P41 P42 3 9 Falling Edge 3 Detection Circuit KRIF Set Signal 40 5 P46 G Standby Release Signal P47 142 CHAPTER 6 PORT FUNCTIONS 6 2 7 Port 5 Port 5 is an 8 bit input output port with output latch P50 to P57 pins can specify the input mode output mode in 1 bit units with the port mode register 5 PM5 When P50 to P57 pins are used as input ports an on chip pull up resistor can be used to them in 8 bit units with a pull up resistor option register L PUOL Port 5 can drive LEDs directly Alternate function includes address bus function in external memory expansion mode RESET input sets port 5 to input mode Figure 6 12 shows a block diagram of port 5 Figure 6 12 P50 to P57 Block Diagram Vpp e WReuo i xc PUO5 DAA RD 5 n 2 WRrort oO Output Latch 3 B P50 to P57 prt WRem 50 57 i PUO Pull up resistor option register PM Port mode register RD Port 5 read signal WR Port 5 write signal 143 CHAPTER 6 PORT FUNCTIONS 6 2 8 Port 6 Port 6 is a
117. 64 ms 3 28 ms 6 4 us 12 8 us 26 x 1 fx 27 x 1 fx 214 x 1 fx 21 x 1 fx 26 x 1 fx 2 x 1 fx 12 8 us 25 6 us 3 28 ms 6 55 ms 12 8 us 25 6 us 27 x 1 fx 28 x 1 fx 215 x 1 fx 216 x 1 fx 27 x 1 fx 28 x 1 fx 25 6 us 51 2 us 6 55 ms 13 1 ms 25 6 us 51 2 us 28 x 1 fx 29 x 1 fx 216 x 1 fx 217 x 1 fx 28 x 1 fx 29 x 1 fx 51 2 us 102 4 ps 13 1 ms 26 2 ms 51 2 us 102 4 us 29 x 1 fx 210 x 4 fx 217 x 1 fx 218 x 1 fx 29 x 1 fx 210 x 4 fx 102 4 us 204 8 us 26 2 ms 52 4 ms 102 4 us 204 8 us 211 x 1 fx 212 x 1 fx 219 x 1 fx 220 x 1 fx 211 x 1 fx 212 x 1 fx 409 6 us 819 2 us 104 9 ms 209 7 ms 409 6 us 819 2 us Remarks 1 fx Main system clock oscillation frequency 2 MCS Oscillation mode selection register OSMS bit 0 3 Values in parentheses when operated at fx 5 0 MHz 232 CHAPTER 9 8 TIMER EVENT COUNTERS 1 AND 2 Figure 9 10 Square Wave Output Operation Timing LI OU OU L lI LI LT LI 1 I LI LT LT 1 Tt Count Value X 0 X 0 X o X XN X N X 0 Xo X o X X Ni X N Xo INTTM1 TO1 Pin OutputNete Note Theinitialvalue of TO1 pin output can be set with the bits 2 and 3 LVR1 LVS1 of 8 bit timer output control register TOC1 233 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 AND 2 9 4 2 16 bit timer event counter mode When bit 2 TMC12 of the 8 bit timer mode contro
118. 7 64 0 301 1 8 1 3 0 071 0 051 1 2 0 047 4 01059 0 000 to 0 1979 R 1 58 0 062 r 5 9 0 232 s 3 55 0 140 s 0 8 0 031 T C 2 0 C 0 079 t 2 4 0 094 U 12 31 0 485 2 7 0 106 V 10 17 0 400 3 9 0 154 6 8 0 268 TGK 080SDW G1E x 8 24 0 324 Y 14 8 0 583 2 1 4 0 2 0 055 0 008 Note Product by TOKYO ELETECH CORPORATION 592 APPENDIX EMBEDDED SOFTWARE For efficient program development and maintenance of the uPD78054 78054Y Subseries the following embedded software is available Real time OS 1 2 RX78K 0 Real time OS A real time OS conforming to uITRON specifications Added with the tool configurator to create the RX78K 0 nucleus and multiple information table Used in combination with separately available Assembler Package RA78K 0 and Device File DF78054 Precautions for the use in PC environment Real time OS is a DOS based application Use it with DOS prompt on Windows Part number uSxxxxRX78013 AAAA Caution When purchasing the RX78K 0 fill in the purchase application form in advance and sign the License Agreement Remark and AAAA in the part number differs depending on the host machine and OS used USXxxxRX78013 AAAA Product Outline Max No for Use in Mass Production Evaluation object Do not use for mass production Mass production object 100 000 1 000 000 10 000 000 Source program Source program for mass production object Host Machine
119. 78056Y A Special Function Registers SFRs SFR Addressing 256 x 8 bits Cnr ce horreo h cec teris ter eue tmc x General Registers 2 Register Addressing 32 x 8 bits Y Short Direct Addressing Internal High speed RAM 1024 x 8 bits T S Ton PRA Z Y Reserved Direct Addressing Internal Buffer RAM 32 x 8 bits Reserved Register Indirect Addressing Based Addressing Based Indexed Addressing External Memory 14976 x 8 bits Internal ROM 49152 x 8 bits Y CHAPTER 5 CPU ARCHITECTURE Figure 5 15 Data Memory Addressing uPD78058 78058Y A Special Function Registers SFRs SFR Addressing 256 x 8 bits FOROR ETIN Fe n ov p General Registers E Addressing 32 x 8 bits Y Short Direct Addressing Internal High speed RAM 1024 x 8 bits FE20H Y FE1FH FB00H FAFFH Reserved FAE0H FADEH Direct Addressing Internal Buffer RAM 32 x 8 bits Register Indirect FAC0H Addressing FABFH Reserved Based Addressing F800H F7FFH Based Indexed Addressing Internal Expansion RAM 1024 x 8 bits F400H Reserved F000H EFFFH Internal ROM 61440 x 8 bits 0000H Y Note When internal ROM size is 60K bytes the area F000H to F3FFH cannot be used F000H to F3FFH can be used as external memory by setting the interna
120. B 1 Development Tool Configuration nennen nennen nnne nnne nnne nennt 580 B 2 EV 9200GC 80 Drawing For Reference Only a 590 B 3 EV 9200GC 80 Footprint For Reference Only 0 2 40 0000 591 B 4 TGK 080SDW Drawing For Reference unit 592 32 LIST OF TABLES 1 3 Table No Title Page 1 1 Differences between Standard Quality Grade Products and A Products 48 1 2 Mask Options of Mask ROM Versions L 48 2 1 Mask Options of Mask ROM a 58 3 1 Pin Input Output Circuit Ty POS secs wi eee an egies Su na ge dte n 71 4 1 Pin Input Output Circuit Types 2 eet e t E ep Rede ded 87 5 1 Internal ROM GCapacily ree cient Pct de da te ae encode CERE Dee dae 99 5 2 Nector Tables H 99 5 3 Internal High Speed RAM Capacity nnne nenen nennen 100 5 4 Internal High Speed RAM Area U 110 5 5 Correspondent Table of Absolute Addresses the General Registers 112 5 6 Special Function Register LiSt L U n enne nnne nennen nnne nnn enne as 115 6 1 Port Functions uPD78054 subseries lU U u 130 6 2 Port Functions uPD78054Y subseries
121. CROO TMO continues to operate after one shot pulse is output To stop TMO 00H must be set to TMCO Caution When outputting one shot pulse do not set 1 in OSPT When outputting one shot pulse again set OSPT to 1 after the INTTMOO or interrupt match signal with 00 is generated Figure 8 31 Control Register Settings for One Shot Pulse Output Operation Using Software Trigger a 16 bit timer mode control register TMCO 03 02 01 OVFO CUClear amp start with match of and 00 b Capture compare control register 0 CRCO CRCO2 CRCO1 CRC00 00 set as compare register CR01 set as compare register c 16 bit timer output control register TOCO OSPT OSPE 04 1 50 LVRO 01 TOEO dence sara 8s TOO Output Enabled Inversion of output on match of TMO and CROO Specified TOO output F F initial value Inversion of output on match of TMO and CRO1 One shot pulse output mode Set 1 in case of output Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with one shot pulse output See the description of the respective control registers for details Caution Values in the following range should be set in CROO and 01 0000H lt CRO1 lt CROO lt FFFFH 208 CHAPTER 8 16 TIMER EVENT COUNTER Figure 8 32 Timing of One Shot Pulse Outp
122. Caution When falling edge detection of port4 is used KRIF should be cleared to 0 not cleared to 0 automatically 155 CHAPTER 6 PORT FUNCTIONS 6 4 Port Function Operations Port operations differ depending on whether the input or output mode is set as shown below 6 4 1 Writing to input output port 1 2 Output mode A value is written to the output latch by a transfer instruction and the output latch contents are output from the pin Once data is written to the output latch it is retained until data is written to the output latch again Input mode A value is written to the output latch by a transfer instruction but since the output buffer is OFF the pin status does not change Once data is written to the output latch it is retained until data is written to the output latch again Caution In the case of 1 bit memory manipulation instruction although a single bit is manipulated the port is accessed as an 8 bit unit Therefore on a port with a mixture of input and output pins the output latch contents for pins specified as input are undefined except for the manipulated bit 6 4 2 Reading from input output port 1 2 156 Output mode The output latch contents are read by a transfer instruction The output latch contents do not change Input mode The pin status is read by a transfer instruction The output latch contents do not change CHAPTER 6 PORT FUNCTIONS 6 4 3 Operations on input output
123. Communication is carried out with three lines of serial clock SCKO serial output SOO and serial input SIO 1 Register setting The 3 wire serial I O mode is set with the serial operating mode register 0 CSIMO and serial bus interface control register SBIC a Serial operating mode register 0 CSIMO CSIMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H Symbol 27 5 Address After Reset R W panem R W Serial Interface Channel 0 Clock Selection Input Clock to SCKO pin from off chip 8 bit timer register 2 TM2 output Clock specified with bits O to 3 of timer clock select register 3 TCL3 cSIM CSIM CSIM Operation SIO SBO SDAO SO0 SB1 SDA1 SCKO SCL P27 PM25 P25 26 P26 27 P27 Start Bit 04 03 02 P25 Pin Function 26 Pin Function Pin Function Nott 3 wire serial Sio e SO0 SCK0 CMOS mode Input CMOS output input output 2 wire serial I O mode See the section 17 4 3 2 wire serial mode operation or bus mode See the section 17 4 4 bus mode operation R W Wake up Function Control 3 0 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after detecting start condition L when CMDD 1 matches the slave address regist
124. Configuration The clock output control circuit consists of the following hardware Table 12 1 Clock Output Control Circuit Configuration Timer clock select register 0 TCLO Control register Port mode register 3 PM3 Figure 12 2 Clock Output Control Circuit Block Diagram fxx 24 8 z Synchronizing fxx 2 NS PCL P35 4 4 Primer Clock Select Register 0 Port Mode Register 3 Y Internal Bus 256 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12 3 Clock Output Function Control Registers The following two types of registers are used to control the clock output function Timer clock select register 0 TCLO Port mode register 3 PM3 1 Timer clock select register 0 TCLO This register sets PCL output clock TCLO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TCLO to 00H Remark Besides setting PCL output clock TCLO sets the 16 bit timer register count clock 257 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Symbol lt gt 6 1 0 TCLO CLOE TCL06TCL05 TCL04 TCLOS TCLO2 TCLO1 TCLOO 258 TCLO2 TCLO1 Figure 12 3 Timer Clock Select Register 0 Format After Reset FF40H 00H 5 4 3 2 Address R W R W PCL Output Clock Selection MCS 1 fxr 32 768 kHz fx 5 0 MHz fx 2 2 5 MHz fxx 2 fx 2 2 5 MHz fx 2 1 25 MHz fxx 22 fx
125. D A conversion stop D A conversion enable Normal mode Real time output mode DAM5 D A Converter Channel 1 Operating Mode Normal mode Real time output mode Cautions 1 When using the D A converter a dual function port pin should be set to the input mode and a pull up resistor should be disconnected 2 Always set bits 2 3 6 and 7 to 0 3 When D A conversion is stopped the output state is high impedance 4 The output triggers are INTTM1 and INTTM2 for channel 0 and channel 1 respectively in the real time output mode 284 CHAPTER 15 D A CONVERTER 15 4 Operations of D A Converter 1 Select the channel 0 operating mode and channel 1 operating mode by DAM4 and DAM5 of D A converter mode register DAM respectively 2 Set the data corresponding to the analog voltages output to the ANOO P130 and ANO1 P131 pins to the D A conversion value setting registers 0 and 1 DACSO and DACS 1 respectively 3 The channel 0 and channel 1 D A conversion operations can be started by setting DACEO and DACE1 of the DAM respectively 4 In the normal mode the analog voltage signals are output to the ANOO P130 and ANO1 P131 pins immediately after the D A conversion In the real time output mode the analog voltage signals are output synchronously with the output triggers 5 In the normal mode the analog voltage signals to be output are held until new data are set in DACSO and DACS1 In the realtim
126. F control Active level selection by match of CROO and TMO Active high Inversion operation disabled Active low Inversion operation enabled 16 Bit Timer Event Counter Timer Output F F Status Setting No change Timer output F F reset 0 Timer output F F set 1 Setting prohibited Timer output F F control by match of CRO1 and Inversion operation disabled Inversion operation enabled One Shot Pulse Output Control Continuous pulse output One shot pulse output Control of One Shot Pulse Output Trigger by Software One shot pulse trigger not used One shot pulse trigger used Cautions 1 Timer operation must be stopped before setting TOCO however except OSPT 2 If LVSO and LVRO are read after data is set they will be 0 3 OSPT is cleared automatically after data setting and will therefore be 0 if read 187 CHAPTER 8 16 BIT TIMER EVENT COUNTER 5 Port mode register 3 PM3 This register sets port 3 input output in 1 bit units When using the P30 TOO pin for timer output set PM30 and output latch of P30 to 0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 value to Figure 8 7 Port Mode Register 3 Format Symbol 7 6 Address After Reset R W 5 4 3 2 1 0 PM3n P3n Pin Input Output Mode Selection 0 to 7 Output mode output buffer ON Input mode output buffer OFF
127. FAFFH FAEOH FADFH FACOH FABFH FA80H FA7FH 6000H 5FFFH 0000H 102 Figure 5 10 Data Memory Addressing uPD78053 78053Y Special Function Registers SFRs SFR Addressing 256 x 8 bits General Registers 32 x 8 bits A Register Addressing Internal High speed RAM 1024 x 8 bits Short Direct Addressing Reserved Internal Buffer RAM 32 x 8 bits Reserved Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing External Memory 39552 x 8 bits Internal ROM 24576 x 8 bits Y CHAPTER 5 CPU ARCHITECTURE FE20H FE1FH FBOOH FAFFH FAEOH FADFH FACOH FABFH FA80H FA7FH 8000H 7FFFH 0000H Figure 5 11 Data Memory Addressing uPD78054 78054Y Special Function Registers SFRs SFR Addressing 256 x 8 bits TV p General Registers Addressing 32 x 8 bits Y Short Direct Addressing Internal High speed RAM 1024 x 8 bits Y Reserved Direct Addressing Internal Buffer RAM 32 x 8 bits Reserved Register Indirect Addressing Based Addressing Based Indexed Addressing External Memory 31360 x 8 bits Internal ROM 32768 x 8 bits Y 103 CHAPTER 5 CPU ARCHITECTURE FE20H FE1FH FBOOH FAFFH FAEOH FADFH FACOH FABFH FA80H FA7FH 8000H
128. If two or more requests are specified for the same priority with priority specify flag the interrupt request with higher default priority is acknowledged first Any reserved interrupt requests are acknowledged when they become acknowledgeable Figure 21 13 shows interrupt request acknowledge algorithms If a maskable interrupt request is acknowledged the contents of acknowledged interrupt is saved in the stacks program status word PSW and program counter PC in that order the IE flag is reset to 0 and the acknowledged interrupt priority specify flag contents are transferred to the ISP flag Further the vector table data determined for each interrupt request is loaded into PC and branched Return from the interrupt is possible with the RETI instruction 500 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS xxIF xxMK xxPR IE ISP Interrupt request reserve Interrupt request reserve Figure 21 13 Interrupt Request Acknowledge Processing Algorithm Start N Yes Interrupt Request Generation No Interrupt request reserve Yes High priority Yes Any high priority interrupt request among simultaneously generated xxPR 0 interrupt requests Vectored interrupt servicing Interrupt request flag Interrupt mask flag Priority specify flag No Low Priority Simultaneously generated xxPR 0 interrupt requests Interrupt request reserve
129. P72 Transmit 5 3 Clock o o a 4 TPS0 TPS3 MDLO MDL3 SCK 4 Receive E Match Clock E 1 2 iz Baud Rate Generator Control Register Internal Bus 442 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 1 2 3 4 5 Transmit shift register TXS This register is used to set the transmit data The data written in TXS is transmitted as serial data If the data length is specified as 7 bits bits 0 to 6 of the data written in TXS are transferred as transmit data Writing data to TXS starts the transmit operation TXS is written to with an 8 bit memory manipulation instruction It cannot be read TXS value is FFH after RESET input Caution Do not write a data to TXS during a transmit operation TXS and the receive buffer register RXB are allocated to the same address and when a read is performed the value of RXB is read Receive shift register RXS This register is used to convert serial data input to the RxD pin to parallel data When one byte of data is received the receive data is transferred to the receive buffer register RXB RXS cannot be directly manipulated by a program Receive buffer register RXB This register holds receive data Each time one byte of data is received new receive data is transferred from the receive shift register RXS If the data length is specified as 7 bits the receive data is transferred to bits 0 to 6 of RXB and the MSB o
130. PROM size to less than 56K bytes by the memory size switching register IMS 98 CHAPTER 5 CPU ARCHITECTURE 5 1 1 Internal program memory space The internal program memory space stores programs and table data Normally they are addressed with a program counter PC Each product of the wPD78054 and 78054Y Subseries has the internal ROM or PROM of the size shown below Part number uPD78052 78052Y Table 5 1 Internal ROM Capacity Internal ROM Mask ROM Capacity 16384 x 8 bits 0000H to SFFFH uPD78053 78053Y uPD78054 78054 uPD78055 78055Y uPD78056 78056Y uPD78058 78058Y 24576 x 8 bits 0000H to 5FFFH 32768 x 8 bits 0000H to 7FFFH 40960 x 8 bits 0000H to 9FFFH 49152 x 8 bits 0000H to BFFFH 61440 x 8 bits 0000H to EFFFH uPD78P054 uPD78P058 78P058Y 32768 x 8 bits 0000H to 7FFFH 61440 x 8 bits The following areas are allocated to the internal program memory space 1 Vector table area 0000H to EFFFH The 64 byte area 0000H to 003FH is reserved as a vector table area The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area Of the 16 bit address low order 8 bits are stored at even addresses and high order 8 bits are stored at odd addresses Vector Table Address Table 5
131. Package Internal ROM 38 78052 8 78052 9 78053 8 0780530 9 78054 8 78054 9 uPD78P054GC 3B9 uPD78PO054GC 8BTNote uPD78P054GK BE9 LPD78P054KK T 78055 8 78055 9 78056 8 78056 9 78058 8 78058 9 uPD78P058GC 8BT HPD78P058KK T uPD78052GC A xxx 3B9 uUPD78053GC A xxx 3B9 uPD78054GC A xxx 3B9 Note Under development Caution The uPD78P054GC is available in two packages NEC 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic TQFP Fine pitch 12 x 12 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic TQFP Fine pitch 12 x 12 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic TQFP Fine pitch 12 x 12 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic TQFP Fine pitch 12 x 12 mm 80 pin ceramic WQFN 14 14 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic TQFP Fine pitch 12 x 12 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic TQFP Fine pitch 12 x 12 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic TQFP Fine pitch 12 x 12 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin ceramic WQFN 14 x 14
132. R R R W 352 Figure 17 5 Serial Bus Interface Control Register Format 1 2 lt 7 gt lt 1 gt 0 gt Address After Reset R W 00H Used for stop condition signal output When RELT 1 SOO latch is set to 1 After SOO latch setting automatically cleared to 0 Also cleared to 0 when CSIEO 0 Used for start condition signal output When CMDT 1 SOO latch is cleared to 0 After SOO latch clearance automatically cleared to 0 Also cleared to 0 when CSIEO 0 RELD Stop Condition Detection Clear Conditions RELD 0 Set Conditions RELD 1 When transfer start instruction is executed If SIOO and SVA values do not match in address reception When CSIEO 0 When RESET input is applied CMDD Start Condition Detection Clear Conditions CMDD 0 Set Conditions CMDD 1 When stop condition signal is detected When transfer start instruction is executed When stop condition signal is detected When CSIEO 0 When RESET input is applied When start condition signal is detected Used to generate the ACK signal by software when 8 clock wait mode is selected ACKT Keeps SDAO SDA1 low from set instruction ACKT 1 execution to the next falling edge of SCL Also cleared to 0 upon start of serial interface transfer or when CSIEO 0 Note Bits 2 3 and 6 RELD CMDD and ACKD are read only bits Remarks 1 Bits 0 1 and 4 RELT CMDT ACKT are 0 when read after the data
133. R W R W MCS 1 Setting prohibited fx 22 1 25 MHz fxx 22 fx 22 1 25 MHz fx 23 625 kHz 23 fx 23 625 kHz fx 24 313 kHz fxx 24 fx 24 313 kHz fx 25 156 kHz fxx 25 fx 25 156 kHz fx 28 78 1 kHz 26 fx 26 78 1 kHz fx 27 39 1 kHz fxx 27 fx 27 39 1 kHz fx 28 19 5 kHz fxx 28 fx 28 19 5 kHz fx 29 9 8 kHz Caution Remarks 398 Other than above When rewriting other data to TCL3 stop the serial transfer operation beforehand Bog Setting prohibited fxx Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency MCS Bit 0 of oscillation mode selection register OSMS Figures in parentheses apply to operation with fx 2 5 0 MHz CHAPTER 18 SERIAL INTERFACE CHANNEL 1 2 Serial operating mode register 1 CSIM1 This register sets serial interface channel 1 serial clock operating mode operation enable stop and automatic transmit receive operation enable stop CSIM1 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM1 to 00H Figure 18 3 Serial Operation Mode Register 1 Format Symbol lt 7 gt 6 5 4 3 2 1 0 Address After Reset R W P m CSIM11 CSIM10 Serial Interface Channel 1 Clock Selection Clock externally input to SCK1 pinNote 1 8 bit timer register 2 TM2 output
134. Rising Edge Specified TH Pin Input Count Value X 00 X 01 X 02 Xos X 04 X 05 X XN X N X 99 X ot X 92 X X CR10 N INTTM1 e Remark N 00H to FFH 231 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 AND 2 3 Square wave output operation Operates as square wave output with any selected frequency at intervals of the count value preset to 8 bit compare register 10 and 20 CR10 CR20 The TO1 P31 or TO2 P32 pin output status is reversed at intervals of the count value preset to CR10 or CR20 by setting bit 0 TOE1 or bit 4 TOE2 of the 8 bit timer output control register TOC1 to 1 This enables a square wave with any selected frequency to be output Table 9 8 8 Bit Timer Event Counters 1 and 2 Square Wave Output Ranges Minimum Pulse Width Maximum Pulse Width Resolution MCS 1 MCS 0 1 MCS 0 2 x 1 fx 22 x 1 fx 29 x 1 fx 210 x 1 fx 2 x 1 fx 22 x 1 fx 400 ns 800 ns 102 4 us 204 8 us 400 ns 800 ns 2 x 1 fx 23 x 1 fx 210 x 1 fx 211 x 1 fx 22 x 1 fx 23 x 1 fx 800 ns 1 6 us 204 8 us 409 6 ps 800 ns 1 6 us 23 x 1 fx 2 x 1 fx 211 x 1 fx 212 x 1 fx 23 x 1 fx 2 x 1 fx 1 6 us 8 2 us 409 6 us 819 2 us 1 6 us 8 2 us 24 x 1 fx 25 x 1 fx 212 x 1 fx 213 x 1 fx 24 x 1 fx 25 x 1 fx 8 2 us 6 4 us 819 2 us 1 64 ms 8 2 us 6 4 us 25 x 1 fx 26 x 1 fx 213 x 1 fx 214 x 1 fx 25 x 1 fx 26 x 1 fx 6 4 us 12 8 us 1
135. SB1 SCK0 to SCK2 S10 to S12 SO0 to SO2 STB TIOO TIO1 TH TI2 TOO to TO2 TxD VoD VPP Vss WAIT WR X1 X2 XT1 XT2 Port13 Programmable Clock Read Strobe Reset Real Time Output Port Receive Data Serial Bus Serial Clock Serial Input Serial Output Strobe Timer Input Timer Input Timer Output Transmit Data Power Supply Programming Power Supply Ground Wait Write Strobe Crystal Main System Clock Crystal Subsystem Clock 41 CHAPTER 1 OUTLINE uPD78054 Subseries 2 PROM programming mode 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 mm uPD78P054GC 3B9 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm uPD78P054GC 8BTNete 78P058GC 8BT 80 pin plastic TQFP Fine pitch 12 x 12 mm uPD78P054GK BE9 80 pin ceramic WQFN 14 x 14 mm uPD78P054KK T 78 058 c c POS 88757288795 0 gt gt 0 gt 0 gt lt 0 O 1 O RESET 940 2 O O 3 O Vss 4 O O 5 O 9 Voo O O 8 O O 9 O O O D7 O O D6 O O D5 L lt O O D4 O O D3 O O D2 O D1 O O DO LO OVW 9 1 0 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 OOOOOOOOOOOOOOOOOOOO ggggergeersesre 8 gt Note Under development Cautions 1 L Connect individually to Vss via a pull down resistor 2 Vss Connect to the ground 3 RESET Set to the lo
136. SERIAL INTERFACE 2 A D CONVERTER D A CONVERTER INTERRUPT CONTROL BUZZER OUTPUT CLOCK OUTPUT CONTROL 78K 0 CPU CORE ROM RAM Voo Vss IC Ve PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 7 PORT 12 PORT 13 REAL TIME EXTERNAL OUTPUT PORT ACCESS SYSTEM CONTROL Remarks 1 The internal ROM and RAM capacities depend on the product 2 Pin connection in parentheses is intended for the uPD78P054 78P058 01 06 P07 P10 P17 P20 P27 P30 P37 40 47 50 57 60 67 P70 P72 P120 P127 P130 P131 RTPO P120 RTP7 P127 ADO P40 AD7 P47 A8 P50 A15 P57 RD P64 WR P65 WAIT P66 ASTB P67 RESET 1 2 XT1 P07 XT2 45 CHAPTER 1 OUTLINE uPD78054 Subseries 1 8 Outline of Function Part Number Internal memory uPD78052 uPD78053 078054 uPD78P054 uPD78055 uPD78056 uPD78058 uPD78P058 Note 1 Note 2 Mask ROM PROM Mask ROM PROM 16 Kbytes 24 Kbytes 32 Kbytes 32 Kbytes 40 Kbytes 48 Kbytes 60 Kbytes 60 Kbytes Note 3 Note 3 High speed RAM 512 bytes 1024 bytes 1024 bytes 1024 bytes 1024 bytes Note 3 Note 3 Buffer RAM 32 bytes Expansion RAM None 1024 bytes 1024 bytes Note 4
137. Simulator the operation of the target system on the host machine The SM78KO0 operates on Windows The use of the SM78KO enables the verification of logic and performance of applications independently from hardware development without using in circuit emulator and improves the development efficiency and the software quality Used in combination with separately available Device File DF78054 Part number uSxxxxSM78K0 Remark in the part number differs depending on the host machine and OS used SM78K0 Host Machine Supply Media PC 9800 series Japanese WindowsNetes 1 2 9 5 inch 2HD FD IBM PC AT and Japanese WindowsNetes 1 2 3 5 2HC FD compatible English WindowsNote Note Does not support WindowsNT 587 APPENDIX DEVELOPMENT TOOLS B 3 2 Software 2 2 ID78KO NSNote A control program to debug the 78K 0 Series Integrated debugger Adopting Windows on personal computers and OSF Motif on EWS as supporting in circuit emulator graphical user interface presents the appearance and the operability IE 78K0 NS conforming to them Enhancing the debugging function that supports C ID78KO language the trace result can be displayed in the C language level by using Integrated Debugger window integration function which correlates the source program disassembly supporting in circuit emulator display and memory display to the trace result In addition the debugging IE 7
138. Timings nene enne nennen nennen rennen nnns 407 18 7 Circuit of Switching in Transfer Bit Order 22 2 22 4 1 01000 408 18 8 Basic Transmission Reception Mode Operation Timings 00000 a 417 18 9 Basic Transmission Reception Mode 418 18 10 Buffer RAM Operation in 6 Byte Transmission Reception in Basic Transmit Receive Mode 419 18 11 Basic Transmission Mode Operation Timings 422040 0 00000 421 18 12 Basic Transmission Mode Flowchaltl u 422 18 13 Buffer RAM Operation in 6 Byte Transmission in Basic Transmit Mode 423 18 14 Repeat Transmission Mode Operation Timing u 425 18 15 Repeat Transmission Mode 426 18 16 Buffer RAM Operation in 6 Byte Transmission in Repeat Transmit Mode 427 18 17 Automatic Transmission Reception Suspension and 429 18 18 System Configuration When the Busy Control Option is Used 430 18 19 Operation Timings when Using Busy Control Option BUSYO 0 431 18 20 Busy Signal and Wait Cancel when BUSYO 0 432
139. Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 CSIIF1 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 c Repeat transmission mode In this mode data stored in the buffer RAM is transmitted repeatedly Serial transfer is started by writing any data to serial I O shift register 1 S101 when 1 is set in bit 7 CSIE1 of the serial operating mode register 1 CSIM1 Unlike the basic transmission mode after the last byte data in address FACOH has been transmitted the interrupt request flag CSIIF1 is not set the value at the time when the transmission was started is set in the automatic data transmit receive address pointer ADTP again and the buffer RAM contents are transmitted again When a reception operation busy control and strobe control are not performed the P20 SI1 P23 STB and P24 BUSY pins can be used as ordinary input output ports The repeat transmission mode operation timing is shown in Figure 18 14 and the operation flowchart in Figure 18 15 Figure 18 16 shows the operation of the buffer RAM when 6 bytes of data are transmitted in the repeat transmission mode Figure 18 14 Repeat Transmission Mode Operation Timing Interval Interval sor __XorXoeXosXoaXosXo2XoiXoo AD7ADGADSAD4ADSAD2ADTADO 7 06 05 Caution Since in the repeat transmission mode a read is performed on the buffer RAM after the transmission of one byte the interval is included in the p
140. UART mode the reception completion interrupt request INTSR occurs a certain time after the reception error interrupt request INTSER has occurred and then cleared Consequently the following phenomenon may occur e Description If bit 1 ISRM of the asynchronous serial interface mode register ASIM is set to 1 the reception completion interrupt request INTSR does not occur on occurrence of a reception error If the receive buffer register RXB is read at certain timing a in Figure 19 14 during the reception error interrupt INTSER processing the internal error flag is cleared to 0 As a result it is judged that no reception error has occurred and INTSR which must not occur occurs Figure 19 14 illustrates this operation Figure 19 14 Reception Completion Interrupt Request Generation Timing when ISRM 1 fsck INTSER when framing overrun error occurs a Error flag internal flag T Cleared on reading RXB _Y INTSR Interrupt routine of CPU Reading RXB It is judged that reception error has not occurred and INTSR occurs Remark ISRM Bit 1 of asynchronous serial interface mode register ASIM fsck Source clock of 5 bit counter of baud rate generator RXB Receive buffer register To avoid this phenomenon take the following measures e Countermeasures In case of framing error or overrun error Disable the receive buffer register RXB from being
141. XA A A A NK KX XXX s 1 lal B 4 YVONNE CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 17 4 5 Cautions on use of 12 bus mode 1 Start condition output master The SCL pin normally outputs a low level signal when no serial clock is output It is necessary to change the SCL pin to high in order to output a start condition signal register SINT to drive the SCL pin high After setting CLC clear CLC to 0 and return the SCL pin to low If CLC remains 1 no serial clock is output If itis the master device which outputs the start condition and stop condition signals confirm that CLD is set to 1 after setting CLC to 1 a slave device may have set SCL to low wait state Set 1 in CLC of interrupt timing specify Figure 17 24 Start Condition Output SCL SDAO SDA1 CLC CMDT CLD 385 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 2 Slave wait release slave transmission 386 Slave wait status is released by WREL flag bit 2 of interrupt timing specify register SINT setting or execution of an serial I O shift register 0 SIOO write instruction If the slave sends data the wait is immediately released by execution of an SIOO write instruction and the clock rises without the start transmission bit being output in the data line Therefore as shown in Figure 17 25 data should be transmitted by manipulating the P27 output latch through the program
142. a 466 30 LIST OF FIGURES 7 8 Figure No Title Page 19 12 3 Wire Serial Mode Timing 472 19 13 Circuit of Switching in Transfer Bit Order a 473 19 14 Reception Completion Interrupt Request Generation Timing when ISPM 1 474 19 15 Receive Buffer Register Read Disable Period a s 475 20 1 Real time Output Port Block Diagram nennen nnne nennen nnn 478 20 2 Real time Output Buffer Register Configuration 479 20 3 Port Mode Register 12 Format ir pei dete n e i 480 20 4 Real time Output Port Mode Register 2 2 nennen 480 20 5 Real time Output Port Control Register Format nennen 481 21 1 Basic Configuration of Interrupt Function U 486 21 2 Interrupt Request Flag Register Format mre 489 21 3 Interrupt Mask Flag Register nne 490 21 4 Priority Specify Flag Register Format neret 491 21 5 External Interrupt Mode Register 0 Formatl u 492 21 6 External Interrupt Mode Register 1 Format 493 21 7 Sampling Clock Select Register Formatl nennen nnne 494
143. above software B 5 Upgrading Former In circuit Emulators for 78K 0 Series to IE 78001 R A If you have a former in circuit emulator for the 78K 0 Series IE 78000 R or IE 78000 R A your in circuit emulator can be upgraded to be equivalent to the IE 78001 R A in circuit emulator by simply replacing the break board with the IE 78001 R BK under development Table B 2 Upgrading Former In circuit Emulators for 78K 0 Series to IE 78001 R A In circuit Emulator Cabinet UpgradingNete Board to be Purchased IE 78000 R Required IE 78001 R BK IE 78000 R A Not required Note To upgrade your cabinet bring it to NEC 589 APPENDIX DEVELOPMENT TOOLS Drawing and Footprint for Conversion Socket EV 9200GC 80 Figure B 2 EV 9200GC 80 Drawing For Reference Only M E B _ 1 cc 27 EB t CS n No 1 pin index LP H e H l EV 9200GC 80 G0 ITEM MILLIMETERS INCHES A 18 0 0 709 B 14 4 0 567 C 14 4 0 567 D 18 0 0 709 E 4 C 2 0 4 C 0 079 F 0 8 0 031 G 6 0 0 236 H 16 0 0 63 18 7 0 736 J 6 0 0 236 K 16 0 0 63 L 18 7 0 736 M 8 2 0 323 8 0 0 315 2 5 0 098 2 0 0 079 Q 0 35 0 014 R 02 3 00 091 5 01 5 0 059 590
144. address Table 5 6 gives a list of special function registers The meaning of items in the table is as follows Symbol Symbols indicating the addresses of special function register These symbols are reserved words for the RA78K 0 and defined by header file sfrbit h for the CC78K 0 and can be used as the operands of instructions when the RA78K 0 ID78K0 NS ID78K0 and SM78KO are used R W Indicates whether the corresponding special function register can be read or written R W Read write enable R Read only W Write only Manipulatable bit units Y indicates bit units 1 8 or 16 bits in which the register can be manipulated indicates that the register cannot be manipulated in the indicated bit units After reset Indicates each register status upon RESET input 114 CHAPTER 5 CPU ARCHITECTURE Table 5 6 Special Function Register List 1 3 Manipulatable Bit Unit Address Special Function Register SFR Name After Reset 1 bit 8 bits 16 bits 2271 PortO Port1 Port2 Port3 Port4 Port5 Undefined Port6 Port7 Port12 lt a aly a Port13 Capture compare register 00 Undefined Capture compare register 01 16 bit timer register Compare register 10 Undefined Compare register 20 8 bit timer register 1 8 bit timer register 2 Seri
145. and 3 to 6 are set to 0 452 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 b Asynchronous serial interface mode register ASIM ASIM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIM to 00H Symbol lt 7 gt Address After Reset R W lt 6 gt 5 4 3 2 1 0 Pe pefe eme me Receive Operation Control 0 Receive operation stopped 1 Receive operation enabled Transmit Operation Control Transmit operation stopped ASIM Transmit operation enabled 453 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19 4 2 Asynchronous serial interface UART mode In this mode one byte of data is transmitted received following the start bit and full duplex operation is possible A dedicated UART baud rate generator is incorporated allowing communication over a wide range of baud rates In addition the baud rate can be defined also by scaling the input clock to the ASCK pin The MIDI standard baud rate 31 25 kbps can also be used by employing the dedicated UART baud rate generator 1 Register setting Symbol lt 7 gt 6 CSIM2 454 UART mode settings are performed using serial operating mode register 2 CSIM2 the asynchronous serial interface mode register ASIM the asynchronous serial interface status register ASIS and the baud rate generator control register BRGC a Serial operating mode register 2 CSIM2 CSIM2 is set with a 1 bit or 8 bit memory manipulati
146. and clock input output RESET input sets the input mode Figures 6 15 and 6 16 show block diagrams of port 7 Caution When used as a serial interface set the input output and output latch according to its functions For the setting method refer to Table 19 2 Serial Interface Channel 2 Operating Mode Setting Figure 6 15 P70 Block Diagram e WRPuo PUO7 Hke RD eC 4 n WRrort _ o A Output Latch P70 SI2 RxD 2 PO e 70 512 WRem MP PM70 PUO Pull up resistor option register PM Port mode register RD Port 7 read signal WR Port 7 write signal 146 CHAPTER 6 PORT FUNCTIONS Internal bus Figure 6 16 P71 and P72 Block Diagram PUO PM RD WR Voo WRpuo PUO7 Jo P ch RD WRPonr A Output Latch nd P71 and P72 a WRem PM71 PM72 Alternate Function Pull up resistor option register Port mode register Port 7 read signal Port 7 write signal P71 SO2 TxD P72 SCK2 ASCK 147 CHAPTER 6 PORT FUNCTIONS 6 2 10 Port 12 This is an 8 bit input output port with output latches Input mode output mode can be specified bit wise by means of port mode register 12 PM12 When pins P120 to P127 are used as input port pins an on chip pull up resistor can be used as an 8 bit unit by means of pul
147. are used to control the watch timer Timer clock select register 2 TCL2 Watch timer mode control register TMC2 1 Timer clock select register 2 TCL2 Refer to Figure 10 2 This register sets the watch timer count clock TCL2 is set with an 8 bit memory manipulation instruction RESET input sets TCL2 to 00H Remark Besides setting the watch timer count clock TCL2 sets the watchdog timer count clock and buzzer output frequency 242 CHAPTER 10 WATCH TIMER Figure 10 1 Watch Timer Block Diagram Selector fxx 2 INTWT Selector Selector Selector gt INTTM3 To 16 Bit Timer Event Counter TCL24 Timer Clock Select Register 2 Watch Timer Mode Control Register Internal Bus 243 CHAPTER 10 WATCH TIMER Figure 10 2 Timer Clock Select Register 2 Format After Symbol 7 6 5 4 Address Reset R W 3 2 1 0 TCL2 TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 FF42H 00H R W Watchdog Timer Count Clock Selection TCL21 MCS 1 fx 2 625 kHz fx 2 313 kHz fx 2 313 kHz fx 2 156 kHz fx 2 156 kHz fx 2 78 1 kHz fx 2 78 1 kHz fx 2 39 1 kHz fx 2 39 1 kHz fx 2 19 5 kHz fx 2 19 5 kHz fx 2 9 8 kHz fx 2 9 8 kHz fx 2 4 9 kHz fx 2 2 4 kHz Watchdog Timer Count Clock Selection 27 1 2 kHz
148. bus interface control register SBIC Interrupt timing specify register SINT Port mode register 2 PM2 Nete Note Refer to Figure 6 7 Block Diagram of P20 P21 P23 to P26 and Figure 6 8 Block Diagram of P22 P27 344 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries Figure 17 2 Serial Interface Channel 0 Block Diagram Internal Bus Serial Operating Mode Register 0 CSIM CSIM CSIM CSIM CSIM Slave Address Register SVA m SVAM Match 510 5 0 SDAO P25 Output Latch Oo SOO SB1 SDA1 P26 SCKO VO Shift r 0 SIOO Serial Registe Serial Bus Interface Control Register BSYE ACKT CMDD RELD CMDT RELT CLRSET D Q Acknowledge Stop Condition Start Condition Acknowledge Detector SCL P27 Serial Clock Output Circuit Interrupt Request Signal Generator INTCSIO lt Selector Control Circuit Divider fxx 2 fxx 28 TO2 CSIMOO CSIMO1 L CSIMOO gt 4 CSIMO1 CL33 TCL32 TCL31 TCL30 Interrupt Timing Timer Clock Specify Register Select Register 3 Y Internal Bus Remark Output Control selects between CMOS output and N ch open drain output 345 CHAPTER 17 SERIAL INTERFACE CHA
149. but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment comm
150. by software 511 501 Port 2 SCK1 8 bit input output port STB Input output mode can be specified in 1 bit units BUSY When used as an input port an on chip pull up resistor can be used by software SIO SBO SOO SB1 SCKO TOO TO1 Port 3 TO2 8 bit input output port TH Input output mode can be specified in 1 bit units 2 When used as input port pull up resistor be used by software PCL BUZ Port 4 8 bit input output port P40 to P47 Input output mode can be specified in 8 bit units ADO to AD7 When used as an input port an on chip pull up resistor can be used by software Test input flag KRIF is set to 1 by falling edge detection Port 5 8 bit input output port P50 to P57 LED can be driven directly A8 to A15 Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software 130 CHAPTER 6 PORT FUNCTIONS P63 Table 6 1 Port Functions uPD78054 subseries 2 2 Function N ch open drain input output port On chip pull up resistor can be specified by mask option Mask ROM version only 8 bit input output port LEDs can be driven directly Alternate Function Input output mode can be specified in 1 bit When used as an input port an on chip pull up resistor can be used by software ASTB 3 bit input output port Input output mode can be specified in 1 bit units
151. channels or ports Pins other than those selected as analog input can be used as input output ports ADIS is set with an 8 bit memory manipulation instruction RESET input sets ADIS to 00H Cautions 1 Set the analog input channel in the following order 1 Set the number of analog input channels with ADIS 2 Using A D converter mode register ADM select one channel to undergo A D conversion from among the channels set for analog input with ADIS 2 No internal pull up resistor can be used to the channels set for analog input with ADIS irrespective of the value of bit 1 PUO1 of the pull up resistor option register L PUOL Figure 14 4 A D Converter Input Select Register Format Symbol 7 6 0 Address 17 5 4 3 2 ADIS 0 jans ADIS2 ADIS1 ADIS0 FF84H 00H R W ADIS2 ADIS1 ADISO Number of Analog Input Channel Selection No analog input channel P10 P17 1 channel ANIO P11 P17 2 channel ANIO ANI 12 17 3 channel ANIO ANI2 P13 P17 4 channel ANIO ANI3 P14 P17 5 channel ANIO ANIA P15 P17 6 channel ANIO ANI5 P16 P17 0 0 0 0 0 0 0 0 7 channel ANIO ANI6 P17 8 channel ANI0 ANI7 Other than above Setting prohibited 271 CHAPTER 14 A D CONVERTER 3 External interrupt mode register 1 INTM1 This register sets the valid edge for INTP3 to INTP6 INTM1 is set with an 8 bit memory manipulation instruction RE
152. chip pull up resistors can be used by defining the pull up resistor option register L PUOL 2 Control mode These ports function as control signal output pins RD WR WAIT ASTB in external memory expansion mode When a pin is used as a control signal output the on chip pull up resistor is automatically disabled Caution When external wait is not used in external memory expansion mode P66 can be used as an input output port 67 CHAPTER 3 PIN FUNCTION uPD78054 Subseries 3 2 8 P70 to P72 Port 7 This is a 3 bit input output port In addition to its use as an input output port it also has serial interface data input output and clock input output functions The following operating modes can be specified in 1 bit units 68 1 2 Port mode Port 7 functions as a 3 bit input output port 1 bit units specification as an input port or output port is possible by means of port mode register 7 PM7 When used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL Control mode Port 7 functions as serial interface data input output and clock input output a SI2 SO2 Serial interface serial data input output pins b SCK2 Serial interface serial clock input output pin c RxD TxD Asynchronous serial interface serial data input output pins d ASCK Asynchronous serial interface serial clock input output pin Caution When this port is used as a seria
153. clock cycle scaling factor PCCO to PCC2 and switchover from the main system clock to the subsystem clock changing CSS from 0 to 1 should not be performed simultaneously Simultaneous setting is possible however for selection of the CPU clock cycle scaling factor PCCO to PCC2 and switchover from the subsystem clock to the main system clock changing CSS from 1 to 0 MSC 1 MSC 0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PcC2 PCC1 PCC0 CSS IPcC2 PCC1 PCC0 CSS PCC2 PCC1 PCCO CSS PCC2 PCC1 PCC0 CSS 2 1 0 CSS 2 PCC1 PCC0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 x x x 1 x x x fx 2fxr instruction fx 4fxr instruction 0 0 0 16 instructions 16 instructions 16 instructions 16 instructions RU 77 instructions 39 instructions fx Afxr instruction i i 0 0 1 8 instructions 8 instructions 8 instructions 8 instructions 8trinstruction 39 instructions 20 instructions 7 fx 8fxr instruction fx 16fxr instruction 0 0 1 0 4 instructions 4 instructions 4 instructions 4 instructions 20 instructions 10 instructions I I i i fx 32fxr instruction 0 1 1 2 instructions 2 instructions 2 instructions 2 instructions Pe Tobe instruction ix ii 10 instructions 5 instructions 4 0 1 instruction 1 instruction i instr ctio A fstr stion fx 32fxr instruction fx 64fxr instruction 5 instructions 3 instructions x x x 1 instruction 1 instruction 1 instruction 1 inst
154. counter PC The program counter is a 16 bit register which holds the address information of the next program to be executed In normal operation the PC is automatically incremented according to the number of bytes of the instruction to be fetched When a branch instruction is executed immediate data and register contents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 5 17 Program Counter Configuration 15 0 pois PC14 PO13 PC12 PC11 PCt0 Pcs PC7 Pos Pos PC PC2 PC Poo PC 2 Program status word PSW The program status word is an 8 bit register consisting of various flags to be set reset by instruction execution Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically reset upon execution of the RETB RETI and POP PSW instructions RESET input sets the PSW to 02H Figure 5 18 Program Status Word Configuration 7 0 a Interrupt enable flag IE This flag controls the interrupt request acknowledge operations of the CPU When IE 0 all interrupts except the non maskable interrupt are disabled DI status When IE 1 interrupts are enabled El status At this time acknowledgment of interrupts is controlled with an inservice priority flag ISP an interrupt mask flag for various interrupt sources and a priority specify flag The interrupt en
155. data to from the OSD On Screen Display device and a device with built in display controller driver independently of the CPU thus the software load can be alleviated 393 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18 2 Serial Interface Channel 1 Configuration Serial interface channel 1 consists of the following hardware Table 18 1 Serial Interface Channel 1 Configuration Item Configuration Register Serial I O shift register 1 5101 Automatic data transmit receive address pointer ADTP Control register Timer clock select register 3 TCL3 Serial operating mode register 1 CSIM1 Automatic data transmit receive control register ADTC Automatic data transmit receive interval specify register ADTI Port mode register 2 PM2 Note Note Refer to Figure 6 5 6 7 Block Diagram of P20 P21 P23 to P26 and Figure 6 6 6 8 Block Diagram of P22 P27 394 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18 1 Serial Interface Channel 1 Block Diagram I Internal Bus Automatic Data Transmit Receive Buffer RAM Address Pointer ADTP I Internal Bus Automatic Data Transmit Receive Control Register Automatic Data ATE gt Transmit Receive Interval Specify Register DIR DIR ADTI ADTI ADTI ADTI ADTI Serial I O 7141312 1 0 Serial Operating Mode Register 1 IE1 ATE Ese ps
156. detected Detected CORENI Correction address register 1 and fetch address match detection control Disabled Enabled Note Bits 0 and 2 are read only bits 539 CHAPTER 25 ROM CORRECTION 25 4 ROM Correction Application 1 Store the correction address and instruction after correction patch program to nonvolatile memory such as EEPROMI M outside the microcontroller When two places should be corrected store the branch destination judgment program as well The branch destination judgment program checks which one of the addresses set to CORADO or CORAD1 generates the correction branch Figure 25 4 Storing Example to EEPROM when one place is corrected EEPROM Source program 00H CSEG AT 1000H 01H 02H ADD A 2 RA78K 0 BR 11002H FFH Figure 25 5 Connecting Example with EEPROM using 2 wire serial I O mode uPD78058 78058Y EEPROM SCKO SB1 P32 540 CHAPTER 25 ROM CORRECTION 2 Assemble in advance the initialization routine as shown in Figure 25 6 to correct the program Figure 25 6 Initialization Routine Initialization ROM correction Is ROM N correction used ote Load the contents of external nonvolatile memory into internal expansion RAM Correction address register setting ROM correction enabled Note Whether the ROM correction is used or not should be judged by the port input level For example when the P20 input lev
157. display outputs Added N ch open drain I O to uPD78044F 34 display outputs Basic subseries for driving FIPs 34 display outputs Enhanced SIO of uPD78064 expanded ROM and RAM Reduced EMI noise version of uPD78064 Reduced EMI noise version of uPD78098 Added IEBus controller to uPD78054 Control 100 pin 100 80 80 80 64 64 64 7 PD780141 7 64 pin 64 pin 64 42 44 pin 78083 inverter control 64 pin uPD780988 M 64 pin T uPD780964 x 64 pin HED780924 7 E FIP driving 100 pin 1 0780228 d 80 pin uPD78044H 80 pin uPD78044F E LCD driving 100 pin 100 pin uPD78064 IEBus supported _80 pin Meter control L 80 pin 780973 Note Planned 54 Equipped with controller driver for driving automobile meters CHAPTER 2 OUTLINE uPD78054Y Subseries Major differences among Y subseries are tabulated below 4 Configuration of Serial Interface Capacity Control 78078 48 to 60K 3 wire 2 wire I C 3 wire with automatic transmit receive function 3 wire UART uPD78070AY 780018 48K to 60K 3 wire with automatic transmit receive function Time division 3 wire 12 bus supports multi master uPD780058Y 24K to 60K 3 wire 2 wire I C 3 wire with automatic transmit receive function 3 wire time division UART uPD78058FY 48K to 60K 3 wire 2 wire I C uPD78054Y 16K to 60K 3
158. division UART 1 ch 3 ch UART 1 ch uPD780001 uPD78002 uPD78083 uPD780988 32 K to 60 K uPD780964 uPD780924 uPD780208 8 K to 32 K 32 K to 60 K 3 ch UART 1 ch Time division 3 wire 1 ch 2 ch 1 ch UART 1 ch 3 ch UART 2 ch uPD780228 48 K to 60 K uPD78044H 32 K to 48 uPD78044F uPD780308 16 K to 40 K 48 K to 60K uPD78064B 32K uPD78064 uPD78098B 16Kto 32K 40 K to 60K uPD78098 uPD780973 32 K to 60 K 24 K to 32K 2 ch UART 2 ch 3 ch Time division UART 1 ch 2 ch UART 1 ch 3 ch UART 1 ch 2 ch UART 1 ch Notes 1 16 bit timer 2 channels 10 bit timer 1 channel 2 10 bit timer 1 channel 44 1 OUTLINE uPD78054 Subseries 1 7 Block Diagram TOO P30 00 00 TIO1 INTP1 PO1 TO1 P31 1 TO2 P32 TI2 P34 SIO SBO P25 500 5 1 26 5 27 SI1 P20 SO1 P21 SCK1 P22 STB P23 BUSY P24 SI2 RxD P70 SO2 TxD P71 SCK2 ASCK P72 ANI0 P10 ANI7 P17 AVss AVRnzro ANO0 P130 ANO1 P131 AVss AVner INTP6 P06 BUZ P36 PCL P35 16 bit TIMER EVENT COUNTER 8 bit TIMER EVENT COUNTER 1 8 bit TIMER EVENT COUNTER 2 WATCHDOG TIMER WATCH TIMER SERIAL INTERFACE 0 SERIAL INTERFACE 1
159. edge of the SCKO immediately after the busy mode is released while executing the transfer When acknowledge signal ACK is detected at the start instruction rising edge of SCKO clock after completion of When CSIEO 0 transfer When RESET input is applied R W Synchronizing Busy Signal Output Control Disables busy signal which is output in synchronization with the falling edge of SCKO clock just after execution of the instruction to be cleared to 0 Outputs busy signal at the falling edge of SCKO clock following the acknowledge signal Note The busy mode can be canceled by start of serial interface transfer However the BSYE flag is not cleared to 0 Remark CSIEO Bit 7 of serial operating mode register 0 CSIMO 299 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 4 Interrupt timing specify register SINT This register sets the bus release interrupt and address mask functions and displays the 5 27 level status SINT is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SINT to 00H Figure 16 6 Interrupt Timing Specify Register Format Symbol 6 5 Address After Reset R W mmm 300 R W SVAM SVA Bit to be Used as Slave Address 0 Bits 0 to 7 1 Bits 1 to 7 R W E INTCSIO Interrupt Cause SelectionNete 2 CSIIFO is set upon termination of serial interface channel 0 transfer CSIIFO is set upon bus release det
160. enable disable and displays automatic transmit receive execution and error detection ADTC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ADTC to 00H Figure 18 4 Automatic Data Transmit Receive Control Register Format Symbol 27 lt 6 lt 5 gt lt gt lt gt lt 2 gt lt 1 lt 0 gt Address After Reset R W ADTC ARLD ERCE STRB BUSY1BUSYO FF69H 00H R WNete 1 BUSY1 BUSYO Busy Input Control Not using busy input Busy input enable active high Busy input enable active low STRB Strobe Output Control 0 Strobe output disable 1 Strobe output enable Detection of termination of automatic transmission reception This bit is set to 0 upon suspension of automatic transmission reception or when ARLD 0 During automatic transmission reception This bit is set to 1 when data is written to SIO1 No error This bit is set to 0 when data is written to SIO1 Error occurred ERCE Error Check Control of Automatic Transmit Receive Function Error check disable Error check enable only when BUSY1 1 ARLD Operating Mode Selection of Automatic Transmit Receive Function 0 Single operating mode 1 Repetitive operating mode RE Receive Control of Automatic Transmit Receive Function 0 Receive disable 1 Receive enable Notes 1 Bits 3 and 4 TRF and ERR are Read Only bits 2 The termination of automatic transmission reception should be discriminat
161. expansion mode register MM specifies P40 to P47 as input output pins CHAPTER 6 PORT FUNCTIONS Table 6 5 Port Mode Register and Output Latch Settings when Using Dual Functions Dual functions Pin Name Name INTPO Input Output Input TIOO Input INTP1 Input TIO1 Input P02 to P06 INTP2 to INTP6 Input Po7Note1 XT1 Input P10 to P17Notet ANIO to ANI7 Input P30 to P32 TOO to TO2 Output P33 P34 TH 2 Input P35 PCL Output P36 BUZ Output P40 to P47 ADO to AD7 Input Output P50 to P57 A8 to A15 Output P64 RD Output P65 WR Output P66 WAIT Input P67 ASTB Output P120 to P127 P130 P131 Notet RTPO to RTP7 Output ANOO ANO1 Output Notes 1 Ifthese ports are read out when these pins are used in the alternative function mode undefined values are read 2 When the P40 to P47 pins P50 to P57 pins and P64 to P67 pins are used for dual functions set the function by the memory extension mode register MM Cautions 1 2 Remarks x When not using external wait in the external memory extension mode the P66 pin can be used as an I O port When port 2 and port 7 are used for serial interface the I O latch or output latch must be set according to its function For the setting methods see Figure 16 4 Serial Operation Mode Register 0 Format Figure 1
162. expressions is smaller than 2 fsck the minimum interval time is 2 fsck 6 2 28 05 Minimum n 1 x fsck 6 Maximum n 1 x 2 36 1 5 fxx fxx fsck Cautions 1 Do not write data to ADTI during operation of automatic data transmit receive function 2 Bits 5 and 6 must be set to zero 3 To control the data transfer interval by means of automatic transmission reception with ADTI busy control refer to 18 4 3 4 a Busy control option is disabled Remarks 1 fxx Main system clock frequency or fx 2 2 fx Main system clock oscillation frequency 3 fsck Serial clock frequency 415 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 2 Automatic transmit receive data setting a Transmit data setting lt gt Write transmit data from the least significant address FACOH of buffer RAM up to FADFH at maximum The transmit data should be in the order from high order address to low order address 2 Set to the automatic data transmit receive address pointer ADTP the value obtained by subtracting 1 from the number of transmit data bytes b Automatic transmit receive mode setting lt gt Set bit 7 CSIE1 to 1 and bit 5 ATE to 1 of the serial operating mode register 1 CSIM1 to 1 2 Set bit 7 RE of the automatic data transmit receive control register ADTC to 1 9 Seta data transmit receive interval in the automatic data transmit receive interval specify register
163. function 2 Zero must be set in bits 5 and 6 3 To control the data transfer interval by means of automatic transmission reception with ADTI busy control refer to 18 4 3 4 a Busy control option is disabled 1 fxx Main system clock frequency fx or fx 2 2 fx Main system clock oscillation frequency 3 fsck Serial clock frequency CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Symbol ADTI 7 6 ADTI7 0 ADTI3 ADTI2 ADTI1 4 3 2 1 0 ADTIA ADTIS ADTI2 ADTI1 ADTIO FF6BH Data Transfer Interval Specification bx 5 0 MHz Operation Address R W R W MinimumNete 223 2 us O 5 fsck MaximumNete 224 8 us 1 5 fsck 236 0 us 0 5 fscK 237 6 us 1 5 fsck 248 8 us 0 5 fscK 250 4 us 1 5 fsck 261 6 us 0O 5 fsck 263 2 us 1 5 fsck 274 4 us O 5 fsck 276 0 us 1 5 fsck 287 2 us O 5 fsck 288 8 us 1 5 fsck 300 0 us 0 5 fsck 301 6 us 1 5 fsck C 312 8 us O 5 fsck 314 4 us 1 5 fsck 325 6 us 0 5 fscK 327 2 us 1 5 fsck 338 4 us 0 5 fscK 340 0 us 1 5 fsck 351 2 us 0 5 fscK 352 8 us 1 5 fsck 364 0 us 0 5 fsck 365 6 us 1 5 fsck 376 8 us 0 5 fscK 378 4 us 1 5 fsck 389 6 us 0 5 fscK 391 2 us 1 5 fsck 402 4 us 0 5 fsck 404 0 us 1 5 fsck 415 2 us 0 5 fsck 416 8 us 1 5 fsck Note The data transfe
164. instruction RESET input sets TMC1 to OOH Figure 9 5 8 Bit Timer Mode Control Register 1 Format Symbol 7 6 lt gt lt 0 gt Address After Reset R W 5 4 3 2 o o 0 o Fran ew TCE1 8 Bit Timer Register 1 Operation Control Operation stop TM1 clear to 0 Operation enable TCE2 8 Bit Timer Register 2 Operation Control Operation stop TM2 clear to 0 Operation enable 12 Operating Mode Selection 8 Bit timer register x 2 channel mode TM1 TM2 16 Bit timer register x 1 channel mode TMS Cautions 1 Switch the operating mode after stopping timer operation 2 When used as 16 bit timer register TCE1 should be used for control enable stop 225 CHAPTER 9 8 TIMER EVENT COUNTERS 1 AND 2 3 8 bit timer output control register TOC1 This register controls operation of 8 bit timer event counter output control circuits 1 and 2 It sets resets the R S flip flops LV1 and LV2 and enables disables inversion and 8 bit timer output of 8 bit timer registers 1 and 2 TOC1 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TOC1 to 00H Figure 9 6 8 Bit Timer Output Control Register Format Symbol 7 6 lt gt 3 2 0 Address After Reset R W 5 1 TOC1 LVS2 LVR2 TOC15 2 LVS1 LVR1 11 TOE1 FF4FH 00H R W 8 Bit Timer Event Counter 1 Outptut Control Output disable port mode O
165. interface mode MSB first This mode is used for 8 bit data transfer with two or more devices using two lines of serial clock SCK0 and serial data bus SBO or SB1 The SBI mode conforms to the NEC serial bus format and transmits receives transfer data discriminating it as three types address command and data Address Data that selects the target device of the serial communication Command Data that gives instruction to the target device Data Data that is actually transmitted Forthe actual transmission the master device outputs address on the serial bus and selects the slave device to be the target of communication from multiple devices Then the serial transmission is realized by transmitting receiving command and data between the master device and the slave device The receive side automatically discriminates the received data as address command or data by hardware This function enables the input output ports to be used effectively and simplifies the application program to control serial interface channel 0 In this mode the wake up function for handshake and the output function of acknowledge and busy signals can also be used CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 4 2 wire serial I O mode MSB first This mode is used for 8 bit data transfer using two lines of serial clock SCKO and serial data bus SBO or SB1 This mode enables to cope with any one of the
166. kHz 251 CHAPTER 11 WATCHDOG TIMER 2 Watchdog timer mode register WDTM This register sets the watchdog timer operating mode and enables disables counting WDTM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets WDTM to 00H Figure 11 3 Watchdog Timer Mode Register Format After Symbol 7 6 4 Address Reset R W 5 3 2 1 0 WDTM RM WDTM4 WDTM3 FFF9H 00H R W Watchdog Timer Operation Mode TUNE SelectionNote 1 Interval timer modeNote2 Maskable interrupt request occurs upon generation of an overflow Watchdog timer mode 1 Non maskable interrupt request occurs upon generation of an overflow Watchdog timer mode 2 Reset operation is activated upon generation of an overflow RUN Watchdog Timer Operation Mode SelectionNete Count stop Counter is cleared and counting starts Notes 1 Once set to 1 WDTM3 and WDTM4 cannot be cleared to 0 by software 2 The watchdog timer starts operating as an interval timer as soon as RUN has been set to 1 3 Once set to 1 RUN cannot be cleared to 0 by software Thus once counting starts counting can only be stopped by RESET input Cautions 1 When 1 is set in RUN so that the watchdog timer is cleared the actual overflow time is up to 0 5 shorter than the time set by timer clock select register 2 TCL2 2 To use watchdog timer modes 1 and 2 make sure that the interrupt request flag TMIF4 is
167. kbps can also be used by employing the dedicated UART baud rate generator 3 wire serial I O mode MSB LSB first switchable In this mode 8 bit data transfer is performed using three lines the serial clock SCK2 and serial data lines 512 SO2 In the 3 wire serial I O mode simultaneous transmission and reception is possible increasing the data transfer processing speed Either the MSB or LSB can be specified as the start bit for an 8 bit data serial transfer allowing connection to devices using either as the start bit The 3 wire serial I O mode is useful for connection to peripheral I Os and display controllers etc which incorporate a conventional synchronous clocked serial interface such as the 75X XL series 78K series 17K series etc Caution In the 3 wire serial I O mode of serial interface channel 2 only the output of the internal baud rate generator can be used for the operation clock It is not possible to input a clock to pin SCK2 from external 439 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19 2 Serial Interface Channel 2 Configuration Serial interface channel 2 consists of the following hardware Table 19 1 Serial Interface Channel 2 Configuration Item Configuration Register Transmit shift register TXS Receive shift register RXS Receive buffer register RXB Control register Serial operating mode register 2 CSIM2 Asynchronous serial interface mode register ASIM Asynchronous se
168. level Thus the handshake line previously necessary for connection of two or more devices can be removed resulting in the increased number of available input output ports CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 4 12 Inter IC bus mode MSB first This mode is used for 8 bit data transfer with two or more devices using two lines of serial clock SCL and serial data bus SDAO or SDA1 This mode is in compliance with the I C bus format In this mode the transmitter can output three kinds of data onto the serial data bus start condition data and stop condition to be actually sent or received The receiver automatically distinguishes the received data into start condition data or stop condition by hardware Figure 17 1 Serial Bus Configuration Example Using 2 Bus Master CPU Slave CPU1 SCL gt SCL SDAO SDA1 gt SDAO SDA1 Slave CPU2 SCL SDAO SDA1 Slave CPUn SDAO SDA1 343 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 17 2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware Table 17 2 Serial Interface Channel 0 Configuration Item Configuration Serial I O shift register 0 5100 Register Slave address register SVA Timer clock select register 3 TCL3 Serial operating mode register 0 CSIMO Control register Serial
169. mm 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic QFP 14 x 14 mm Resin thickness Remark xxx indicates ROM code suffix 1 4 mm 1 4 mm 1 4 mm 2 7 mm 1 4 mm 1 4 mm 1 4 mm 1 4 mm 1 4 mm 2 7 mm 2 7 mm 2 7 mm Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM One time PROM One time PROM One time PROM EPROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM One time PROM EPROM Mask ROM Mask ROM Mask ROM For the package that can be supplied consult CHAPTER 1 OUTLINE uPD78054 Subseries 1 4 Quality Grade Part number Package Quality grade 78052 8 uUPD78052GK xxx BE9 uPD78053GC xxx 8BT 0780530 9 uUPD78054GC xxx 8BT 78054 9 uPD78P054GC 3B9 uPD78P054GC 8BTNote HPD78P054GK BE9 HPD78P054KK T uPD78055GC ooc 8BT HPD78055GK ooc BE9 uPD78056GC ooc 8BT 78056 9 uPD78058GC ooc 8BT 78058 9 uPD78P058GC 8BT uPD78P058KK T uPD78052GC A xxx 3B9 uPD78053GC A xxx 3B9 uPD78054GC A xxx 3B9 Note Under development 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic TQFP Fine pitch 12 x 12 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 80 pin plastic TQFP Fine pitch 12 x 12 mm 80 pin plastic QFP 14 x 14 mm Resin thickness
170. mode is specified and the output level is changed the interrupt request flag is set Thus when the output mode is used set the interrupt mask flag to 1 134 CHAPTER 6 PORT FUNCTIONS Figure 6 2 00 and P07 Block Diagram RD p o lt lee PO7 XT1 Internal bus Figure 6 3 P01 to P06 Block Diagram Vpp e WRPuo z 4 PUOO Yo P ch RD tog o 1 8 WRP gt Ponr PO1 INTP1 TI01 9 e Output Latch 4 2 2 Y P01 to PO6 P06 INTP6 WRPM 0 er 01 06 PUO Pull up resistor option register PM Port mode register RD Port 0 read signal WR Port 0 write signal 135 CHAPTER 6 PORT FUNCTIONS 6 2 2 Port 1 Port 1 is an 8 bit input output port with output latch It can specify the input mode output mode in 1 bit units with a port mode register 1 PM1 When P10 to P17 pins are used as input ports an on chip pull up resistor can be used to them in 8 bit units with a pull up resistor option register L PUOL Alternate functions include an A D converter analog input RESET input sets port 1 to input mode Figure 6 4 shows a block diagram of port 1 Caution A pull up resistor cannot be used for pins used as A D converter analog input Figure 6 4 P10 to P17 Block Diagram Vpp 2 WRruo i PUO1 gt 5 RD qC 8 WRPonr 1 NA NE Output Latch m
171. occurred CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 17 4 4 12 bus mode operation The 2 bus mode is provided for when communication operations are performed between a single master device and multiple slave devices This mode configures a serial bus that includes only a single master device and is based on the clocked serial I O format with the addition of bus configuration functions which allows the master device to communicate with a number of slave devices using only two lines serial clock SCL line and serial data bus SDAO or SDA1 line Consequently when the user plans to configure a serial bus which includes multiple microcontrollers and peripheral devices using this configuration results in reduction of the required number of port pins and on board wires In the 12 bus specification the master sends start condition data and stop condition signals to slave devices through the serial data bus while slave devices automatically detect and distinguish the type of signals due to the signal detection function incorporated as hardware This function simplifies the application program to control 1 C bus An example of a serial bus configuration is shown in Figure 17 13 This system below is composed of CPUs and peripheral ICs having serial interface hardware that complies with the 2 bus specification Note that pull up resistors are required to connect to both serial clock line and serial data bus line beca
172. of data ends When one frame of data has been received the receive data in the shift register is transferred to the receive buffer register RXB and a reception completion interrupt request INTSR is generated Even if an error is generated the receive data in which the error was generated is transferred to RXB If bit 1 ISRM of ASIM is cleared 0 when the error is generated INTSR will be generated If ISRM is set 1 INTSR will not be generated If the RXE bit is reset 0 during the receive operation the receive operation is stopped immediately In this case the contents of RXB and ASIS are not changed and INTSR and INTSER are not generated Figure 19 9 Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing oe n START INTSR Caution The receive buffer register RXB must be read even if a receive error is generated If RXB is not read an overrun error will be generated when the next data is received and the receive error state will continue indefinitely 464 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 e Receive errors Three kinds of errors can occur during a receive operation a parity error framing error or overrun error When the data reception result error flag is set in the asynchronous serial interface status register ASIS areceive error interrupt request INTSER is generated INTSER is generated before receive completion interrupt request INTSR Receive error causes
173. of the respective control registers for details 197 CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 18 Configuration Diagram for Pulse Width Measurement by Free Running Counter OVFO INTTM3 2fxx fxx fxx 2 Selector 16 Bit Timer Register TMO 16 Bit Capture Compare Register 01 CRO1 fxx 2 TI00 POO INTP00 INTPO Internal Bus Figure 8 19 Timing of Pulse Width Measurement Operation by Free Running Counter and One Capture Register with Both Edges Specified lt t TI00 Pin Input IL Ho CRO1 Captured Value 00 oe D3 eus l OVFO 198 CHAPTER 8 16 BIT TIMER EVENT COUNTER 2 Measurement of two pulse widths with free running counter When the 16 bit timer register TMO is operated in free running mode see register settings in Figure 8 20 itis possible to simultaneously measure the pulse widths of the two signals input to the 00 00 pin and the 01 01 pin When the edge specified by bits 2 and 3 ES10 and ES11 of external interrupt mode register 0 INTMO is input to the 00 00 pin the value of TMO is taken into 16 bit capture compare register 01 01 and an external interrupt request signal INTPO is set Also when the edge specified by bits 4 and 5 ES20 and ES21 of INTMO is input to the TIO1 PO1 pin the value of TMO is taken into 16 bit capture compare register 00 CR00 and an external interrupt request signal
174. output port set the ports to which real time output is performed to the output mode clear the corresponding bit of the port mode register 12 PM12 to 0 2 In the port specified as a real time output port data cannot be set to the output latch Therefore when setting an initial value data should be set to the output latch before setting the real time output mode 480 CHAPTER 20 REAL TIME OUTPUT PORT 3 Real time output port control register RTPC This register sets the real time output port operating mode and output trigger Table 20 3 shows the relation between the operating mode of the real time output port and output trigger RTPC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Figure 20 5 Real time Output Port Control Register Format After Symbol 7 6 5 4 3 2 lt gt lt 0 gt Address Reset R W o o o evem Real time Output Control by INTP2 INTP2 not specified as real time output trigger 1 INTP2 specified as real time output trigger Real time Output Port Operating Mode 0 4 Bits x 2 Channels 1 8 Bits x 1 Channel Table 20 3 Real time Output Port Operating Mode and Output Trigger Operating Mode RTBH gt Port Output RTBL Port Output INTTM2 2 4 Bits x 2 Channels INTTM1 8 Bits x 1 Channel INTP2 481 CHAPTER 20 REAL TIME OUTPUT PORT
175. peculiar to the device IE 780308 R EM supports 2 0 to 5 0V IE 78064 R EM supports 3 0 to 6 0V Used in combination with the IE 78001 R A EP 78230GC R Emulation Probe A probe to connect an in circuit emulator and the target system For 80 pin plastic QFP GC 3B9 GC 8BT type EV 9200GC 80 Conversion Socket refer to Figure B 2 A conversion socket to connect the board of a target system designed to mount 80 pin plastic GC 3B9 GC 8BT type and the EP 78230GC R The uPD78P054KK T 78P058KK T or 78PO58YKK T ceramic WQFN can be mounted instead of connecting the EP 78230GC R EP 78054GK R Emulation Probe A probe to connect an in circuit emulator and the target system For 80 pin plastic TQFP GK BE9 type TGK 080SDW Conversion Adapter refer to Figure B 3 Notes 1 Under development 2 Maintenance product Remarks 1 A conversion adapter to connect the board of a target system designed to mount 80 pin plastic TQFP GK BE9 type to the EP 78054GK R The TGK 080SDW is a product of TOKYO ELETECH Corporation Contact Daimaru Kogyo Co Ltd Tokyo Electronic Component Department Tel 03 3820 7112 Osaka Electronic Component Department Tel 06 244 6672 2 The TGK 080SDW is sold singly 3 The EV 9200GC 80 is sold in a set of five 586 APPENDIX DEVELOPMENT TOOLS B 3 2 Software 1 2 5 78 0 Capable of debugging in C source level or assembler level while simulating System
176. port 1 Output mode An operation is performed on the output latch contents and the result is written to the output latch The output latch contents are output from the pins Once data is written to the output latch it is retained until data is written to the output latch again 2 Input mode The output latch contents are undefined but since the output buffer is OFF the pin status does not change Caution In the case of 1 bit memory manipulation instruction although a single bit is manipulated the port is accessed as an 8 bit unit Therefore on a port with a mixture of input and output pins the output latch contents for pins specified as input are undefined even for bits other than the manipulated bit 6 5 Selection of Mask Option The following mask option is provided in mask ROM version The PROM versions have no mask options Table 6 6 Comparison between Mask ROM Version and PROM Version Pin PiNam Mask 02 Mask ROM Version Version Version Version Mask option for pins P60 to P63 Bit wise selectable on o pull up resistors No on LL e pull up resistor 157 158 CHAPTER 7 CLOCK GENERATOR 7 1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware The following two types of system clock oscillators are available 1 Main system clock oscillator This circuit oscillates at frequencies of 1 to 5 0 MHz Oscillati
177. possible data transfer formats by controlling the SCKO level and the SBO or SB1 output level Thus the handshake line previously necessary for connection of two or more devices can be used as input output ports Figure 16 1 Serial Bus Interface SBI System Configuration Example Voo Master CPU Slave CPU1 SCKO gt SCKO SBO gt SBO Slave CPU2 SCKO SBO Slave CPUn 289 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 16 2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware Table 16 2 Serial Interface Channel 0 Configuration Item Configuration Serial I O shift register 0 SIOO Register Slave address register SVA Timer clock select register 3 TCL3 Serial operating mode register 0 CSIMO Control register Serial bus interface control register SBIC Interrupt timing specify register SINT Port mode register 2 PM2 Nete Note Referto Figure 6 5 Block Diagram of P20 P21 P23 to P26 and Figure 6 6 Block Diagram of P22 P27 290 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries Figure 16 2 Serial Interface Channel 0 Block Diagram Internal Bus Serial Operating Mode Register 0 CSIM CSIM CSIM CSIM Slave Regis SI0 SBO 25 PM25 Output Control PM26 Y Output Control SOO SB1 o p26 9
178. produced and require high reliability uPD78P054KK T 78 058 78PO58YKK T This manual is intended for users to understand the functions described in the Organization below The uPD78054 78054Y Subseries manual is separated into two parts this manual and the instruction edition common to the 78K 0 Series HPD78054 78054Y 78K 0 Series Subseries User s Manual User s Manual Instruction This manual e Pin functions CPU functions e Internal block functions e Instruction set e Interrupt Explanation of each instruction Other on chip peripheral functions How to Read This Manual Before reading this manual you should have general knowledge of electric and logic circuits and microcontrollers O For users who use this document as the manual for the uPD78052 A 78053 A and 78054 A The only differences between the 078052 78053 and 78054 and the LPD78052 A 78053 A 78054 A are the quality grades and packages refer to 1 9 Differences between Standard Quality Grade Products and A Products For the A products read the part numbers in the following manner uPD78052 uPD78052 A uPD78053 uPD78053 A uPD78054 uPD78054 A O When you want to understand the functions in general Read this manual in the order of the contents O To know the uPD78054 and 78054Y Subseries instruction function in detail Refer to the 78K 0 Series User s Manual Instructions U12326E O How to in
179. read for a certain time T2 in Figure 19 15 after the reception error interrupt request INTSER has occurred 474 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 n case of parity error Disable the receive buffer register RXB from being read for a certain time T1 T2 in Figure 19 15 after the reception error interrupt request INTSER has occurred Figure 19 15 Receive Buffer Register Read Disable Period gt K os Kor fpe stor START INTSR INTSER on occurrence of framing overrun error INTSER on occurrence of parity error T1 T2 T1 Time of one data of baud rate selected by baud rate generator control register BRGC 1 baud rate T2 Time of 2 clocks of source clock fsck of 5 bit counter selected by BRGC e Example of preventive measures Here is an example of the above preventive measures Condition fx 5 0 MHz Processor clock control register PCC 00H Oscillation mode select register OSMS 01H Baud rate generator control register BRGC 2400 bps selected as baud rate Tcv 0 4 us tcv 0 2 us 1 one 416 7 us T2 12 8 x 2 25 6 us T1 2 2212 clocks tcv 475 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 476 Example UART reception error interrupt INTSER servicing Main processing Occurrence of INTSER Instructions equivalent to 2205 CPU clocks MIN are necessary 7 clocks of CPU clock MIN time from inter
180. register 01 01 should first be set as a capture register RESET input sets TMO to 0000H Caution As the value of TMO is read via CR01 the value of 01 previously set is lost 16 Bit Timer Event Counter Control Registers The following seven types of registers are used to control the 16 bit timer event counter Timer clock select register 0 TCLO 16 bit timer mode control register TMCO Capture compare control register 0 CRCO 16 bit timer output control register TOCO Port mode register 3 PM3 External interrupt mode register 0 INTMO Sampling clock select register SCS 1 Timer clock select register 0 TCLO 182 This register is used to set the count clock of the 16 bit timer register TCLO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TCLO value to 00H Remark TCLO has the function of setting the PCL output clock in addition to that of setting the count clock of the 16 bit timer register CHAPTER 8 16 TIMER EVENT COUNTER Figure 8 3 Timer Clock Selection Register 0 Format Symbol 7 6 5 4 3 2 Address X After Reset R W 1 0 TCLO CLOE TCLOG TCLOS TCLO4 TCLOSG TCLO2 TCLO1 TCLOO FF40H 00H R W PCL Output Clock Selection TCLO2 TCLO1 MCS 1 fxr 32 768 kHz fix fx 5 0 MHz 2 5 MHz 2 fx 2 2 5 MHz 1 25 MHz fxx 2 fx 2 1 25 MHz 625 kHz fxx 2 fx 2 625 kHz 313 kHz fxx 2 fx 2 313 kHz 156 kHz
181. shift register 0 5100 R W Serial Interface Channel 0 Operation Control 0 Stops operation 1 Enables operation Notes 1 Bit 6 is a read only bit 2 In the 2 bus mode the clock frequency is 1 16 of the clock frequency output by TO2 3 Can be used freely as a port 4 To use the wake up function WUP 1 set the bit 5 SIC of the interrupt timing specify register SINT to 1 Do not execute an instruction that writes the serial I O shift register 0 SIOO while WUP 1 5 When CSIEO 0 COI is 0 Remark x Don t care PMxx Port mode register Pxx Port output latch 372 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries b Serial bus interface control register SBIC SBIC is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets SBIC to 00H Symbol 27 1 0 Address After Reset R W SBIC BSYE ACKD ACKE ACKT D RELD T RELT FF61H 00H R WNete Use for stop condition output When RELT 1 SOO latch is set to 1 After SOO latch setting automatically cleared to 0 Also cleared to 0 when CSIEO 0 Use for start condition output When CMDT 1 SOO latch is cleared to 0 After clearing SOO latch automatically cleared to 0 Also cleared to 0 when CSIEO 0 Clear Conditions When transfer start instruction is executed If SIOO and SVA values do not match in address reception When CSIE0 0 When RESET input is applied Setting Condition When stop con
182. that if a bus is driven in the SBI mode or 2 wire serial I O mode the bus pin must serve for both input and output Thus in the case of a device for reception write FFH to SIOO in advance except when address reception is carried out by setting bit 5 WUP of CSIMO to 1 In the SBI mode the busy state can be cleared by writing data to SIOO In this case bit 7 BSYE of the serial bus interface control register SBIC is not cleared to 0 RESET input makes SIOO undefined Slave address register SVA This is an 8 bit register to set the slave address value for connection of a slave device to the serial bus SVA is set with an 8 bit memory manipulation instruction This register is not used in the 3 wire serial I O mode The master device outputs a slave address for selection of a particular slave device to the connected slave device These two data the slave address output from the master device and the SVA value are compared with an address comparator If they match the slave device has been selected In that case bit 6 of serial operating mode register 0 CSIMO becomes 1 The address can also be compared on the data of LSB masked high order 7 bits by setting bit 4 SVAM of the interrupt timing specify register SINT to 1 If no matching is detected in address reception bit 2 RELD of the serial bus interface control register SBIC is cleared to 0 In the SBI mode the wake up function can be used by setting the bit 5 WUP o
183. the runaway a non maskable interrupt request or RESET can be generated Table 11 1 Watchdog Timer Runaway Detection Times Runaway Detection Time 211 x 1 fxx 21 x 1 fx 410 us 21 x 1 fx 819 us 212 x 4 fxx 21 x 1 fx 819 us 213 x 1 fx 1 64 ms 213 x 4 fxx 213 x 1 fx 1 64 ms 214 x 1 fx 3 28 ms 214 x 4 fxx 214 x 1 fx 3 28 ms 215 x 1 fx 6 55 ms 215 x 4 fxx 216 x 4 fxx 216 x 1 fx 13 1 ms 217 x 1 fx 26 2 ms 217 x 4 fxx 217 x 1 fx 26 2 ms 218 x 1 fx 52 4 ms 219 x 4 fxx Remarks 1 fxx 2 fx 215 x 1 fx 6 55 ms 219 x 1 fx 104 9 ms Main system clock frequency fx or fx 2 Main system clock oscillation frequency 216 x 1 fx 13 1 ms 220 x 1 fx 209 7 ms 3 MCS Bit 0 of oscillation mode selection register OSMS 4 Figures in parentheses apply to operation with fx 2 5 0 MHz 247 CHAPTER 11 WATCHDOG TIMER 2 Interval timer mode Interrupt requests are generated at the preset time intervals Table 11 2 Interval Times Interval Time 211 x 1 fxx 211 x 1 fx 410 us 21 x 1 fx 819 us 212 x 1 fxx 21 x 1 fx 819 us 213 x 1 fx 1 64 ms 213 x 1 fxx 213 x 1 fx 1 64 ms 214 x 1 fx 3 28 ms 214 x 1 fxx 21 x 1 fx 3 28 ms 215 x 1 fx 6 55 ms 215 x 1 fxx 215 x 1 fx 6 55 ms 216 x 1 fx 13 1 ms 216 x 1 fxx 218 x 1 fx 13
184. to be manipulated in the fixed space is directly addressed with 8 bit data in an instruction word The fixed space to which this address is applied is a 256 byte space of addresses FE20H through FF1FH An internal high speed RAM and a special function register SFR are mapped at FE20H to FEFFH and FFOOH to FF1FH respectively The SFR area FF00H through FF1FH to which short direct addressing is applied is a part of the entire SFR area To this area ports frequently accessed by the program and the compare registers and capture registers of timer event counters are mapped These SFRs can be manipulated with a short byte length and a few clocks When 8 bit immediate data is at 20H to bit 8 of an effective address is set to 0 When it is at OOH to 1FH bit 8 is set to 1 Refer to Illustration on next page Operand format saddr Label of FE20H to FF1FH immediate data saddrp Label of FE20H to FF1FH immediate data even address only Description example MOV OFE30H 50H when setting saddr to FE30H and immediate data to 50H Operation code 0001000 1 OP code 00 0000 30H saddr offset 1 1 01010000 50H immediate data Illustration OP code saddr offset 15 8 7 0 maenas Pea When 8 bit immediate data is 20H to FFH a 0 When 8 bit immediate data is to 1FH a 1 Short Direct Memory 124 CHAPTER 5 CPU ARCHITECTURE 5 4 5 Special Function Register SFR addressing
185. uPD78058 78058 CFH uPD78P058 78P058Y CFH 3 This register is provided only in the uPD78058 78058Y 78P058 and 78P058Y 117 CHAPTER 5 CPU ARCHITECTURE 5 3 Instruction Address Addressing An instruction address is determined by program counter PC contents The contents of PC are normally incremented 1 for each byte automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed When a branch instruction is executed the branch destination information is set to the PC and branched by the following addressing For details of instructions refer to 78K 0 Series User s Manual Instruction U12326E 5 3 1 Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit In the relative addressing modes execution branches in a relative range of 128 to 127 from the first address of the next instruction This function is carried out when the BR addr16 instruction or a conditional branch instruction is executed Illustration u PC indicates the start address after the BR instruction S S E When S 0 all bits of o are 0 When S 1 all bits are 1 118 CHAP
186. us 28 x 1 fx 51 2 us 29 x 1 fx 102 4 us 224 x 1 fx 3 4 s 225 x 1 fx 6 7 s 28 x 1 fx 51 2 us 29 x 1 fx 102 4 us 29 x 1 fx 102 4 us 210 x 1 fx 204 8 us 225 x 1 fx 6 7 s 226 x 1 fx 13 4 s 29 x 1 fx 102 4 us 210 x 1 fx 204 8 us 211 x 1 fx 409 6 us Remarks 1 2 MCS Oscillation mode selection register OSMS bit 0 3 Values in parentheses when operated at fx 5 0 MHz 212 x 1 fx 819 2 us 227 x 1 fx 26 8 s 228 x 1 fx 53 7 s Main system clock oscillation frequency 211 x 1 fx 409 6 us 212 x 4 fx 819 2 us 237 CHAPTER 9 8 TIMER EVENT COUNTERS 1 AND 2 Figure 9 13 Square Wave Output Operation Timing CoutCiock T LT LT LT LT LI TI E EA LI lI l T TM TM2 Count Value X 0000 por ox X N1 X N KooKoo 0 X C X N Yoo INTTM2 TO2 Pin OutputNete i Note Theinitialvalue of TO2 pin output can be set with the bits 6 and 7 LVR2 LVS2 of 8 bit timer output control register TOC1 9 5 Cautions on 8 Bit Timer Event Counters 1 and 2 1 Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start This is because 8 bit timer registers 1 and 2 TM1 and TM2 starts asynchronously with the count pulse Figure 9 14 8 Bit Timer Registers 1 and 2 Start Timing Count Pulse EX
187. wire XT2 and X1 so that they are not in parallel and to correct the IC pin between XT2 and X1 directly to Vss 167 CHAPTER 7 CLOCK GENERATOR 7 4 3 Scaler The scaler divides the main system clock oscillator output fxx and generates various clocks 7 4 4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and clock operations connect the XT1 and XT2 pins as follows XT1 Connect to Vop XT2 Leave open In this state however some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops To suppress the leakage current disconnect the above internal feedback resistor by using the bit 6 FRC of the processor clock control register PCC In this case also connect the XT1 and XT2 pins as described above 168 CHAPTER 7 CLOCK GENERATOR 7 5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode Main system clock fxx e Subsystem clock fxr e CPU clock fcPu Clock to peripheral hardware The following clock generator functions and operations are determined with the processor clock control register PCC and the oscillation mode selection register OSMS a Upon generation of RESET signal the lowest speed mode of the main system clock 12 8 us when operated at 5 0 MHz is selec
188. x 1 fx 225 x 1 fx 28 x 1 fx 29 x 1 fx 51 2 us 102 4 us 3 4 s 6 7 s 51 2 us 102 4 us 29 x 1 fx 210 x 1 fx 225 x 1 fx 226 x 1 fx 29 x 1 fx 210 x 1 fx 102 4 us 204 8 us 6 7 s 13 4 s 102 4 us 204 8 us 211 x 1 fx 212 x 1 fx 227 x 1 fx 228 x 1 fx 211 x 1 fx 212 x 1 fx 409 6 us 819 2 us 26 8 s 53 7 s 409 6 us 819 2 us Remarks 1 fx Main system clock oscillation frequency 2 MCS Oscillation mode selection register OSMS bit 0 3 Values in parentheses when operated at fx 5 0 MHz CHAPTER 9 8 TIMER EVENT COUNTERS 1 AND 2 2 External event counter The number of pulses of an externally input signal can be measured 3 Square wave output A square wave with any selected frequency can be output Table 9 4 Square Wave Output Ranges when 8 Bit Timer Event Counters 1 and 2 are Used as 16 Bit Timer Event Counters Minimum Pulse Width Maximum Pulse Width Resolution 2 x 1 fx 400 ns MCS 1 2 x 1 fx 400 ns MCS 0 22 x 1 fx 800 ns 22 x 1 fx 800 ns 22 x 1 fx 800 ns 23 x 1 fx 1 6 us 23 x 1 fx 1 6 us 23 x 1 fx 1 6 us 24 x 1 fx 3 2 us 24 x 1 fx 3 2 us 24 x 1 fx 3 2 us 25 x 1 fx 6 4 us 25 x 1 fx 6 4 us 25 x 1 fx 6 4 us 26 x 1 fx 12 8 us 26 x 1 fx 12 8 us 26 x 1 fx 12 8 us 2 x 1 fx 25 6 us 2 x 1 fx 25 6 us 27 x 1 fx 25 6
189. 0 5 fsck 122 4 us 1 5 fsck 133 6 us 0 5 fsck 135 2 us 1 5 fsck 146 4 us 0 5 fsck 148 0 us 1 5 fsck 159 2 us 0 5 fsck 160 8 us 1 5 fsck 172 0 us 0 5 fsck 173 6 us 1 5 fsck 184 8 us 0 5 fsck 186 4 us 1 5 fsck 197 6 us 0 5 fsck 199 2us 1 5 fsck 210 4 us O 5 fsck 212 0 us 1 5 fsck Notes 1 The interval is dependent only on CPU processing 2 The data transfer interval includes an error The data transfer minimum and maximum intervals are found from the following expressions n Value set in ADTIO to ADTI4 However if a minimum which is calculated by the following expressions is smaller than 2 fsck the minimum interval time is 2 fsck 6 Minimum n 1 x 2 28 0 5 Maximum n 1 x 2 36 _ 1 5 fxx fxx fsck fxx fxx fsck Cautions 1 Do not write ADTI during operation of automatic data transmit receive function 2 Bits 5 and 6 must be set to zero 3 To control the data transfer interval by means of automatic transmission reception with ADTI busy control refer to 18 4 3 4 a Busy control option is disabled Remarks 1 fxx Main system clock frequency fx or fx 2 2 fx Main system clock oscillation frequency 3 fsck Serial clock frequency 401 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18 5 Automatic Data Transmit Receive Interval Specify Register Format 2 4 Symbol 7 6 5 4 3 2 1 0 Address After Reset R W ADTI A
190. 0 Format and Figure 18 3 Serial Operating Mode Register 1 Format Figure 6 7 P20 P21 P23 to P26 Block Diagram Voo WRPuo 4 PUO2 H E ch RD e 8 WRport a o Output Latch P20 P21 P23 to P26 12 4 P23 STB P24 BUSY P25 SIO SBO SDAO WHRPM P26 SO0 SB1 SDA1 ay PM20 PM21 4 v PM23 to PM26 M zd Alternate Function PUO Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal 139 CHAPTER 6 PORT FUNCTIONS Figure 6 8 P22 and P27 Block Diagram WRPuo z PUO2 I P ch RD Selector m 8 Leg 5 Output Latch P22 SCK1 P22 and P27 T P27 SCKO SCL WRem P PM22 PM27 Alternate Function PUO Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal 140 CHAPTER 6 PORT FUNCTIONS 6 2 5 Port 3 Port 3 is an 8 bit input output port with output latch P30 to P37 pins can specify the input mode output mode in 1 bit units with the port mode register 3 PM3 When P30 to P37 pins are used as input ports an on chip pull up resistor can be used to them in 8 bit units with a pull up resistor option register L PUOL Alternate functions include timer input output clock outpu
191. 0 MHz Operation fx 4 19 MHz Operation MCS 1 MCS 1 80 fx Setting prohibited 160 fx 32 048 80 fx 19 15 160 fx 38 1 5 40 fx Setting prohibited 80 fx Setting prohibited 2 40 fx Setting prohibited 292 80 fx 19 105 50 fx Setting prohibited 2 100 fx 20 005 50 fx Setting prohibited 100 fx 23 86 100 fx 20 005 200 fx 40 005 100 fx 23 8 4s 200 fx 47 75 Setting prohibited No external trigger software starts Conversion started by external trigger hardware starts A D Conversion Operation Control Operation stop Operation start Notes 1 Set so that the A D conversion time is 19 1 us or more 2 Setting prohibited because A D conversion time is less than 19 1 us Cautions 1 The following sequence is recommended for power consumption reduction of A D converter when the standby function is used Clear bit 7 CS to 0 first to stop the A D conversion operation and then execute the HALT or STOP instruction 2 When restarting the stopped A D conversion operation start the A D conversion operation after clearing the interrupt request flag ADIF to 0 Remarks 1 fx Main system clock oscillation frequency 2 MCS Bit 0 of oscillation mode selection register OSMS 270 CHAPTER 14 A D CONVERTER 2 A D converter input select register ADIS This register determines whether the ANIO P10 to ANI7 P17 pins should be used for analog input
192. 0 RTPO P72 SCK2 ASCK O O P37 P20 SH O P36 BUZ P21 SO1 O O P35 PCL 22 5 O O P34 TI2 P23 STB O O P33 TH P24 BUSY O O P32 TO2 25 510 5 0 O P31 TO1 P26 SO0 SB1 O O P30 TO0 P27 SCK0 O O P67 ASTB P40 ADO O O P66 WAIT P41 AD1 O P65 WR 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 OO e lt lt lt qi c n a P44 AD4 O P45 AD5 O P46 AD6 O P47 AD7 O P50 A8 O P51 A9 O P52 A10 O P53 A11 O P54 A12 O P55 A13 O Vss O P56 A14 O P57 A15 O P60 O P61 O P62 O P63 O P64 RD O Note Under development Cautions 1 Be sure to connect IC Internally Connected pin to Vss directly 2 Connect pin to 3 Connect AVss pin to Vss Remark Pin connection in parentheses is intended for the uPD78P054 78P058 40 CHAPTER 1 OUTLINE uPD78054 Subseries Pin Identifications A8 to A15 ADO to AD7 ANIO to ANI7 ANOO ANO1 ASCK ASTB AVpp AVrero AVREF1 AVss BUSY BUZ IC INTP0 to INTP6 P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P72 P120 to P127 Address Bus Address Data Bus Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Busy Buzzer Clock Internally Connected Interrupt from Peripherals Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port12 P130 P131 PCL RD RESET RTP0 to RTP7 RxD SB0
193. 0 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm Standard UPD78058Y GC xxx 8BT 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm Standard uPD78P058YGC 8BT 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm Standard Not applicable for function evaluation Please refer to Quality Grades on NEC Semiconductor Devices Document number C11531E published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications 50 CHAPTER 2 OUTLINE uPD78054Y Subseries 2 5 Pin Configuration Top View 1 Normal operating mode 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm 78052 8 78053YGC xxx 8BT 78054YGC xxx 8BT UPD78055YGC xxx 8BT 78056YGC xxx 8BT 78058YGC xxx 8BT 78P058YGC 8BT 80 pin ceramic WQFN 14 x 14 mm uPD78P0O58YKK T NTP1 TIO1 NTPO TIOO sf CO QN e358 s lt lt f zzzzzzz SSS Se WE Was gt Se Se MES FNS SLASA gt gt lt lt gt 0000 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 610 15 5 1 RESET 16 6 2 P127 RTP7 P17 ANI7 3 O P126 RTP6 AVss O 4 O P125 RTP5 P130 ANOO O 5 O P124 RTP4 P131 ANO1 O 6 O P123 RTP3 AVner 7 O P122 RTP2 P70 SI2 RxD 8 O P121 RTP1 P71 SO2 TxD O 9 O P120 R
194. 092J U10092E ID78KO0 NS Integrated Debugger Reference U12900J To be prepared ID78K0 Integrated Debugger EWS Base Reference U11151J ID78K0 Integrated Debugger PC Base Reference U11539J U11539E ID78KO Integrated Debugger Windows Base Guide U11649J U11649E Caution The above documents are subject to change without prior notice Be sure to use the latest version document when starting design 14 e Documents for Embedded Software 78K 0 Series Real Time OS Document name User s Manual Basics Document No Japanese U11537J English U11537E Installation U11536J U11536E OS for 78K 0 Series MX78K0 e Other Documents IC PACKAGE MANUAL Document name Basics U12257J U12257E Document No Japanese C10943X English Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grade on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892J C11892bE Guide to Quality Assurance for Semiconductor Devices MEI 1202 Microcontroller Related Product Guide Third Party Manufacturers U11416J Caution Theabove documents are subject to change without prior notice Be sure to use the latest version do
195. 1 ms 217 x 1 fx 26 2 ms 217 x 1 fxx 217 x 1 fx 26 2 ms 218 x 1 fx 52 4 ms 219 x 1 fxx 219 x 1 fx 104 9 ms 220 x 1 fx 209 7 ms Remarks 1 fxx Main system clock frequency fx or fx 2 2 fx Main system clock oscillation frequency 3 MCS Oscillation mode selection register bit 0 4 Figures in parentheses apply to operation with fx 2 5 0 MHz 248 CHAPTER 11 WATCHDOG TIMER 11 2 Watchdog Timer Configuration The watchdog timer consists of the following hardware Table 11 3 Watchdog Timer Configuration Timer clock select register 2 TCL2 Control register Watchdog timer mode control register WDTM Figure 11 1 Watchdog Timer Block Diagram 5 Internal Bus fxx 2 Prescaler INTWDT Maskable Interrupt Request Control Circuit RESET INTWDT rL gt Non Maskable Interrupt Request Selector Timer Clock Select Register 2 Watchdog Timer Mode Register 2 Internal Bus 5 249 CHAPTER 11 WATCHDOG TIMER 11 3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer Timer clock select register 2 TCL2 Watchdog timer mode register WDTM 1 Timer clock select register 2 TCL2 This register sets the watchdog timer count clock TCL2 is set with 8 bit memory manipulation instruction RESET input sets TCL2 to 00H Remark Besides setting the watchdog timer co
196. 10 1 10 2 10 3 11 1 11 2 11 3 Title Page Timing of Pulse Width Measurement Operation by Free Running Counter and Two Capture Registers with Rising Edge 202 Control Register Settings for Pulse Width Measurement by Means of 203 Timing of Pulse Width Measurement Operation by Means of Restart with Rising Edge Specified HE Rated 203 Control Register Settings in External Event Counter Mode 204 External Event Counter Configuration Diagram seen 205 External Event Counter Operation Timings with Rising Edge Specified 205 Control Register Settings in Square Wave Output 206 Square Wave Output Operation Timing a 207 Control Register Settings for One Shot Pulse Output Operation Using Software Trigger 208 Timing of One Shot Pulse Output Operation Using Software Trigger 209 Control Register Settings for One Shot Pulse Output Operation Using External Trigger 210 Timing of One Shot Pulse Output Operation Using External Trigger With Rising Edge Specified n caede atteso nece erede ee ede dn 211 16 Bit Timer Register Start Timing enne nnne nnne
197. 15 PC8 SP 1 SP SP 2 SP SP 2 SP 2 SP SP 3 Interrupt and BRK Instruction PC7 PCO PC15 PC8 PSW RETI and RETB Instruction PC7 PCO PC15 PC8 PSW 111 CHAPTER 5 CPU ARCHITECTURE 5 2 2 General registers A general register is mapped at particular addresses FEEOH to FEFFH of the data memory It consists of 4 banks each bank consisting of eight 8 bit registers X A C B E D L and H Each register can also be used as an 8 bit register Two 8 bit registers can be used in pairs as a 16 bit register AX BC DE and HL They can be described in terms of function names X A C B E D L H AX BC DE and HL and absolute names RO to R7 and RPO to RP3 Register banks to be used for instruction execution are set with the CPU control instruction SEL RBn Because of the 4 register bank configuration an efficient program can be created by switching between a register for normal processing and a register for interruption for each bank Table 5 5 Correspondent Table of Absolute Addresses in the General Registers Register Absolute Register Absolute Functional Name Absolute Name Address Functional Name Absolute Name Address I gt x gt O r T gt xX gt O DI GCmior gt gt O r T gt O m O r 112 C
198. 188 CHAPTER 8 16 TIMER EVENT COUNTER 6 External interrupt mode register 0 INTMO This register is used to set INTPO to INTP2 valid edges INTMO is set with an 8 bit memory manipulation instruction RESET input sets INTMO value to 00H Figure 8 8 External Interrupt Mode Register 0 Format Symbol 7 6 5 4 3 2 1 0 seres eso o o lax INTM0 ES31 E FFECH After Reset R W 00H R W ES11 ES10 INTPO Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges Falling edge Rising edge Setting prohibited Both falling and rising edges Falling edge Rising edge Setting prohibited Both falling and rising edges Caution Befoer setting the valid edge of the INTPO TIOO POO pin stop the timer operation by clearing the bits 1 through 3 01 through TMCO3 of the 16 bit timer mode control register TMCO to 0 0 0 189 CHAPTER 8 16 TIMER EVENT COUNTER 7 Sampling clock select registers SCS This register sets clocks which undergo clock sampling of valid edges to be input to INTPO When remote controlled reception is carried out using INTPO digital noise is removed with sampling clock SCS is set with an 8 bit memory manipulation instruction RESET input sets SCS value to 00H Figure 8 9 Sampling Clock Select Register Format Symbol 7 6 Address After Reset R W 5 4 3 2 1 0 s
199. 2 1 25 MHz fx 2 625 kHz fxx 2 fx 2 625 kHz fx 2 313 kHz fxx 2 fx 2 313 kHz fx 2 156 kHz fxx 25 fx 2 156 kHz 25 78 1 kHz fxx 28 fx 2 78 1 kHz fx 2 39 1 kHz fxx 2 fx 2 39 1 kHz fx 2 19 5 kHz Setting prohibited 16 Bit Timer Register Count Clock Selection MCS 1 TIOO Valid edge specifiable 2fxx Setting prohibited fx 5 0 MHz fxx fx 5 0 MHz 2 2 5 MHz fxx 2 fx 2 2 5 MHz fx 2 1 25 MHz fxx 2 2 1 25 MHz fx 2 625 kHz Watch Timer Output INTTM3 Setting prohibited Cautions 1 Set the 00 pin valid edge by external interrupt mode register 0 INTMO and select the sampling clock frequency by the sampling clock selection register SCS When enabling PCL output set 00 to TCLO3 then set 1 in CLOE with a 1 bit memory manipulation instruction To read the count value when TIOO has been specified as the TMO count clock the value should be read from not from 16 bit capture compare register 01 CRO1 When rewriting TCLO to other data stop the clock operation beforehand CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Remarks 1 fxx Main system clock frequency fx or fx 2 2 fx Main system clock oscillation frequency 3 fxr Subsystem clock oscillation frequency 4 TIOO 16 bit timer event counter in
200. 2 2 Applications Cellular phones pagers printers AV equipment air conditioners cameras PPCs fuzzy home appliances vending machines etc 2 3 Ordering Information uPD78PO58YKK T 80 pin ceramic WQFN 14 x 14 mm Remark xxx indicates ROM code suffix Part number Package Internal ROM 78052 8 80 pin plastic 14 x 14 mm Resin thickness 1 4 mm Mask ROM UPD78053Y GC xxx 8BT 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm Mask ROM UPD78054Y GC xxx 8BT 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm Mask ROM UPD78055Y GC xxx 8BT 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm Mask ROM 78056 8 80 pin plastic 14 x 14 mm Resin thickness 1 4 mm Mask ROM uPD78058YGC ooc 8BT 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm Mask ROM uPD78P058YGC 8BT 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm One time PROM uPD78P058YKK T 80 pin ceramic WQFN 14 x 14 mm EPROM Remark xxx indicates ROM code suffix 2 4 Quality Grade Part number Package Quality grade 78052 8 80 pin plastic 14 x 14 mm Resin thickness 1 4 mm Standard uPD78053YGC ooc 8BT 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm Standard UPD78054YGC xxx 8BT 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm Standard UPD78055YGC xxx 8BT 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm Standard UPD78056Y GC xxx 8BT 8
201. 2 OUTLINE uPD78054Y Subseries 2 6 78K 0 Series Expansion The products in the 78K 0 Series are listed below The names in boxes are subseries names uPD78078Y uPD78070A uPD78018F uPD78018FY uPD78014 uPD78014Y uPD78002 uPD78002Y uPD780308Y uPD78064Y Basic subseries for driving LCDs equipped with UART Mass produced products The subseries whose name ends with Y support the bus specifications Reduced EMI noise version of uPD78078 Added timers to uPD78054 and enhanced external interface ROM less version of uPD78078 Fnhanced serial I O of uPD78078Y and functions are defined Enhanced serial I O of uPD78054 reduced EMI noise version Reduced EMI noise version of uPD78054 Added UART and D A to uPD78014 and enhanced I Os Enhanced A D of uPD780024 Enhanced serial I O of uPD78018F Reduced EMI noise version of uPD78018F Low voltage 1 8 V version of uPD78014 and enhanced ROM RAM size options Added A D and 16 bit timer to uPD78002 Added A D to uPD78002 Basic subseries for control applications Equipped with UART and operates at low voltage 1 8 V Enhanced inverter control timer and SIO of uPD780964 expanded ROM and RAM Enhanced A D of uPD780924 Equipped with inverter control circuit and UART reduced EMI noise version Enhanced I O and FIP C D of uPD78044F 53 display outputs Enhanced I O and FIP C D of uPD78044H 48
202. 2 us 24 x 1 fx 25 x 1 fx 212 x 1 fx 213 x 1 fx 24 x 1 fx 25 x 1 fx 3 2 us 6 4 us 819 2 us 1 64 ms 3 2 us 6 4 us 25 x 1 fx 28 x 1 fx 213 x 1 fx 214 x 1 fx 25 x 1 fx 28 x 1 fx 6 4 us 12 8 us 1 64 ms 3 28 ms 6 4 us 12 8 us 28 x 1 fx 27 x 1 fx 214 x 1 fx 215 x 1 fx 28 x 1 fx 27 x 1 fx 12 8 us 25 6 us 3 28 ms 6 55 ms 12 8 us 25 6 us 27 x 1 fx 28 x 1 fx 215 x 1 fx 216 x 1 fx 27 x 1 fx 28 x 1 fx 25 6 us 51 2 us 6 55 ms 13 1 ms 25 6 us 51 2 us 28 x 1 fx 29 x 1 fx 216 x 1 fx 217 x 1 fx 28 x 1 fx 29 x 1 fx 51 2 us 102 4 ps 13 1 ms 26 2 ms 51 2 us 102 4 us 29 x 1 fx 210 x 1 fx 217 x 1 fx 218 x 1 fx 29 x 1 fx 210 x 1 fx 102 4 ps 204 8 26 2 ms 52 4 ms 102 4 us 204 8 ps 211 x 1 fx 212 x 1 fx 219 x 1 fx 220 x 1 fx 211 x 1 fx 212 x 1 fx 409 6 us 819 2 us 104 9 ms 209 7 ms 409 6 us 819 2 us Remarks 1 fx Main system clock oscillation frequency 2 MCS Oscillation mode selection register OSMS bit 0 3 Values in parentheses when operated at fx 5 0 MHz 216 CHAPTER 9 8 TIMER EVENT COUNTERS 1 AND 2 2 External event counter The number of pulses of an externally input signal can be measured 3 Square wave output A square wave with any selected frequency can be output Table 9 2 8 Bit Timer Event Counters 1 and 2 Square Wave Output Ranges Minimum Pulse Width Maximum Pulse Width Resolution 2 x 1
203. 20 WaitSignal aoa edendi o Ped ceto DE 371 17 21 Pin Configuration nc eee d et medie ee n at 377 17 22 Data Transmission from Master to Slave Both Master and Slave Selected 9 Clock Wait 379 17 23 Data Transmission from Slave to Master Both Master and Slave Selected 9 Clock Wait 382 17 245 Start Gondition neuen et o de e i HERR EUR 385 17 25 Slave Wait Release Transmission a 386 29 LIST OF FIGURES 6 8 Figure No Title Page 17 26 Slave Wait Release Reception u 387 17 27 SCKO SCL P27 Pin Configuration ccccccccscssssssescscssesssescssesesesesceseseseseecesesesescesesesesesceeseseseseenens 390 17 28 SCK0 SCL P27 Pin Configuration 390 17 29 Logic Circuit of SCL Sighal uii erret edente ehe D e due ue a e dod adc 391 18 1 Serial Interface Channel 1 Block Diagram 2 24400 44 0 0 nennen 395 18 2 Timer Clock Select Register Format 398 18 3 Serial Operation Mode Register 1 Format a 399 18 4 Automatic Data Transmit Receive Control Register 400 18 5 Automatic Data Transmit Receive Interval Specify Register 401 18 6 3 Wire Serial Mode
204. 295 16 4 Serial Operating Mode Register 0 Format 296 16 5 Serial Bus Interface Control Register Format L 298 16 6 Interrupt Timing Specify Register 300 16 7 3 Wire Serial Mode Timings u nnne nennen rennen nens 305 16 8 and GCMDT Operalioris pe ee mente 305 16 9 Circuit of Switching in Transfer Bit Order U nennen 306 16 10 Example of Serial Bus Configuration with SBI seeneeeeenneneens 307 16 11 SBI Transfer Timings ere D dee ee tee dde Create ee 309 16 12 Bus Release Sighal 2 epo uen ode Or ip He e Ee e d a 310 16 13 Command DAR RENE 310 16 14 Addresses pape ege ees ta ipe et tege uie e p Lip et eres 311 16 15 Slave Selection with Address u 311 16 16 Comimands ite RU en ec aec f ere net bere 312 28 LIST OF FIGURES 5 8 Figure No Title Page 16 17 Data y u ma un Se m u m ge Shes ee edt aed 312 16 18 Acknowledge Signal uu uuu upa ee di eh qahaq o De E eoo gait outs 313 16 19 BUSY and READY Signals 5 uii e e LR I dude Leet 314 16 20 RELT CMDT RELD and CMDD Operations Master 00400 319 16 21 RELT and CMDD Operations Slave
205. 3 1 ms 25 6 us 51 2 us 28 x 1 fx 29 x 1 fx 216 x 1 fx 217 x 1 fx 28 x 1 fx 29 x 1 fx 51 2 us 102 4 us 13 1 ms 26 2 ms 51 2 us 102 4 us 29 x 1 fx 210 x 1 fx 217 x 1 fx 218 x 1 fx 29 x 1 fx 210 x 1 fx 102 4 us 204 8 us 26 2 ms 52 4 ms 102 4 us 204 8 us 211 x 1 fx 212 x 4 fx 219 x 4 fx 220 x 1 fx 211 x 1 fx 212 x 1 fx 409 6 us 819 2 us 104 9 ms 209 7 ms 409 6 us 819 2 us Other than above Setting prohibited Remarks 1 fx Main system clock oscillation frequency 2 MCS Bit 0 of oscillation mode selection register OSMS 3 TCL14 to TCL17 Bits 4 to 7 of timer clock select register 1 TCL1 4 Values in parentheses when operated at fx 5 0 MHz 230 CHAPTER 9 8 TIMER EVENT COUNTERS 1 AND 2 2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI1 P33 and TI2 P34 pins with 8 bit timer registers 1 and 2 TM1 and 2 TM1 and TM are incremented each time the valid edge specified with the timer clock select register 1 is input Either the rising or falling edge can be selected When the TM1 and TM2 counted values match the values of 8 bit compare registers CR10 and CR20 TM1 and 2 are cleared to 0 and the interrupt request signals INTTM1 and 2 are generated Figure 9 9 External Event Counter Operation Timings with
206. 4 4 2 wire serial mode operation R W Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release when CMDD RELD 1 matches the slave address register SVA data in SBI mode Operation stopped Operation enabled Notes 1 Bit 6 is a read only bit 2 Can be used as P25 CMOS input output when used only for transmission 3 Be sure to set WUP to 0 when the 3 wire serial I O mode is selected Remark x don t care PMxx Port mode register Pxx Port output latch 303 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries b Serial bus interface control register SBIC SBIC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SBIC to 00H Symbol lt gt 0 5 4 lt 2 lt gt lt 0 gt Address After Reset R W 3 2 SBIC BSYE ACKD ACKT CMDD RELD CMDT RELT FF61H 00H R W R W When RELT 1 500 latch is set to 1 After SOO latch setting automatically cleared to 0 Also cleared to 0 when CSIEO 0 R W When CMDT 1 SOO latch is cleared to 0 After SOO latch clearance automatically cleared to 0 Also cleared to 0 when CSIEO 0 Remark CSIEO Bit 7 of serial operating mode register 0 CSIMO 304 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 2 Communication operation The 3 wire seria
207. 42 12 AVRBEET i ii nee e Ea e ded UE edere derit 85 430513 AVDDS iet aeterne to gii netu hth deen atten aes torch tes 85 4 244 ANSS ICE 85 d ole ee S uu uum uniman e EO Tred Du IM A 85 42 16 Xl and X2 ctiain oup donate Inn oium saa aa hai 86 4 22 17 XUV and X12 ain moet te pate pide me oce ag a deb cta 86 LEA Mo qi 86 DSL E 86 4 2 0 PROM versions only repisi adian nennen nnne neret nennen nnne nnne 86 4 2 21 1 Mask ROM version only nennen nennt nnne nennen enne 86 4 3 Input output Circuits and Recommended Connection of Unused Pins 87 CHAPTER 5 CPU 24 2 91 5 1 Memory S A O Sa Lm 91 5 1 1 Internal program memory space 99 5 1 2 Internal data memory space I nennen innen 100 5 1 3 Special Function Register SFR area sess enne 100 5 1 4 External Memory SpA O a r egeret een ane 100 5 1 5 Data memory addressing uu erbe dede tede ree tete Ep donee tei 101 5 2 Processor Registers J J J J nennen U u J J J J 109 5 2 1 Controliregisters a ann ci chef Walia tof dei mala ares anu 109
208. 5 0 P26 SO0 SB1 WRem 20 21 i PM23 PM26 4 Alternate Function PUO Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal 137 CHAPTER 6 PORT FUNCTIONS 138 Internal bus WRpeuo Figure 6 6 P22 and P27 Block Diagram Voo ae WRPorT WRem PUO Port mode register Port 2 read signal Port 2 write signal PM RD WR A Output Latch P22 P27 4 MENS PM22 PM27 P22 SCK1 Alternate Function Pull up resistor option register P27 SCK0 CHAPTER 6 PORT FUNCTIONS 6 2 4 Port 2 uPD78054Y Subseries Port 2 is an 8 bit input output port with output latch P20 to P27 pins can specify the input mode output mode in 1 bit units with the port mode register 2 PM2 When P20 to P27 pins are used as input ports an on chip pull up resistor can be used to them in 8 bit units with a pull up resistor option register L PUOL Alternate functions include serial interface data input output clock input output automatic transmit receive busy input and strobe output RESET input sets port 2 to input mode Figures 6 7 and 6 8 show block diagrams of port 2 Caution When used as a serial interface set the input output and output latch according to its functions For the setting method refer to Figure 17 4 Serial Operating Mode Register
209. 5 fsck 344 0 us 0 5 fsck 347 2 us 1 5 fsck 369 6 us 0 5 fsck 372 8 us 1 5 fsck 395 2 us 0 5 fsck 398 4 us 1 5 fsck 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 420 8 us 0 5 fsck 424 0 us 1 5 fsck Notes 1 The interval is dependent only on CPU processing 2 The datatransfer interval includes an error The data transfer minimum and maximum intervals are found from the following expressions n Value set in ADTIO to ADTI4 However if a minimum which is calculated by the following expressions is smaller than 2 fsck the minimum interval time is 2 fsck 6 Minimum n 1 x 2 4 28 n 0 5 fxx fxx fsck 6 Maximum n1 x 2 36 1 5 fsck Cautions 1 Do not write data to ADTI during operation of automatic data transmit receive function 2 Bits 5 and 6 must be set to zero 3 To control the data transfer interval by means of automatic transmission reception with ADTI busy control refer to 18 4 3 4 a Busy control option is disabled Remarks 1 fxx Main system clock frequency fx or fx 2 2 fx Main system clock oscillation frequency 3 fsck Serial clock frequency 403 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18 5 Automatic Data Transmit Receive Interval Specify Register Format 4 4 Symbol 7 6 5 4 3 2 1 0 Address After Reset R W ADTI ADTI7 0 0 ADTIA ADTIS ADTI2 ADTI1 ADTIO 00H R W Data Transfer Interval
210. 53 A 78054 Table 1 1 Differences between Standard Quality Grade Products and A Products Part Number Standard Quality Grade Products A Products Quality grade Standard Special Package 80 pin plastic QFP Note 3 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm 14 x 14 mm Resin thickness 2 7 mm 80 pin plastic TQFP Fine pitch 12 x 12 mm Recommended 22 Refer to separate Data Sheets soldering conditions 1 10 Mask Options The mask ROM versions uPD78052 78053 78054 78055 78056 78058 provide pull up resistor mask options which allow users to specify whether to connect a pull up resistor to a specific port pin when the user places an order for the device production Using this mask option when pull up resistors are required reduces the number of components to add to the device resulting in board space saving The mask options provided in the w PD78054 subseries are shown in Table 1 2 Table 1 2 Mask Options of Mask ROM Versions P60 to P63 Pull up resistor connection can be specified in 1 bit units 48 CHAPTER 2 GENERAL uPD78054Y Subseries 2 1 Features O OO 0 O OO O On chip high capacity ROM and RAM Program Memory Data Memory Part Number ROM Internal High Speed RAM Internal Buffer RAM Internal Expansion RAM 078052 16 Kbytes 512 bytes 32 bytes LPD78053Y 24 Kbytes 1024 bytes LPD78054Y 32 Kbytes HPD78055Y 40 Kbytes uPD78056Y 48 Kbyte
211. 55Y CAH uPD78056 78056Y CCH 78058 78058Y uPD78P058 78 058 4 Provided only in the uPD78058 78058 78P058 and 78P058Y 535 CHAPTER 24 RESET FUNCTION Table 24 1 Hardware Status after Reset 2 2 Hardware Status after Reset Watch timer Mode control register TMC2 00H Clock select register TCL2 00H Mode register WDTM 00H Serial interface Clock select register TCL3 88H Shift registers SIOO SIO1 Undefined Mode registers CSIMO CSIM1 CSIM2 00H Serial bus interface control register SBIC 00H Watchdog timer Slave address register SVA Undefined Automatic data transmit receive control register ADTC 00H Automatic data transmit receive address pointer ADTP 00H Automatic data transmit receive interval specify register ADTI 00H Asynchronous serial interface mode register ASIM 00H Asynchronous serial interface status register ASIS 00H Baud rate generator control register BRGC 00H Transmit shift register TXS Receive buffer register RXB Interrupt timing specify register SINT 00H A D converter Mode register ADM 01H Conversion result register ADCR Undefined Input select register ADIS 00H D A converter Mode register DAM 00H Conversion value setting register DACSO DACS1 00H Real time output port Mode register RTPM 00H Control register RTPC 00H Buffer register RTBL RTBH 00
212. 6 Address Reset PINE 5 4 3 2 1 0 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H FFH R W PM3n P3n Pin Input Output Mode Selection n 0 to 7 Output mode output buffer ON Input mode output buffer OFF 264 CHAPTER 14 CONVERTER 14 1 A D Converter Functions The A D converter converts an analog input into a digital value It consists of 8 channels ANIO to ANI7 with an 8 bit resolution The conversion method is based on successive approximation and the conversion result is held in the 8 bit A D conversion result register ADCR The following two ways are available to start A D conversion 1 Hardware start Conversion is started by trigger input INTP3 2 Software start Conversion is started by setting the A D converter mode register ADM Select one channel of analog input from ANIO to ANI7 and perform A D conversion In the case of hardware start A D conversion operation stops when an A D conversion ends and an interrupt request INTAD is generated In the case of software start the A D conversion operation is repeated Each time an A D conversion operation ends an interrupt request INTAD is generated 14 2 A D Converter Configuration The A D converter consists of the following hardware Table 14 1 A D Converter Configuration Item Configuration Analog input 8 Channels ANIO to ANI7 A D converter mode register ADM Control register A D converter input sel
213. 6 byte mode Port mode 4K byte Memory mode expansion ADO AD7 moge 16K byte mode Port mode Port mode A12 A13 Full address A14 A15 Setting prohibited No wait Wait one wait state insertion Setting prohibited Wait control by external wait pin Note The full address mode allows external expansion to the entire 64 Kbyte address space except for the internal ROM RAM and SFR areas and the reserved areas Remark P60 to P63 enter the port mode without regard to the mode single chip mode or memory expansion mode 516 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 2 Memory size switching register IMS This register specifies the internal memory size In principle use IMS in a default status However when using the external device expansion function with the uPD78058 set IMS so that the internal ROM capacity is 56 Kbytes or lower IMS is set with an 8 bit memory manipulation instruction RESET input sets this register to the value indicated in Table 22 3 Figure 22 3 Memory Size Switching Register Format Symbo 7 6 5 L 0 Address Atter R W 4 3 2 Reset IMS RAM2 1 RAMO 0 ROMS ROM2 ROM1 ROMO FFFOH Note R W Internal ROM size selection 16 Kbytes 24 Kbytes 32 Kbytes 40 Kbytes 48 Kbytes 56 Kbytes 60 Kbytes Setting prohibited RAMO Internal high
214. 7 Pe Pa Voo tT of P ch N ch lt IN OUT pullup enable Vpp lt output disable input enable be IE Pa Voo IN OUT Type 10 A pullup gt P ch enable data open drain output disable Voo P ch IN OUT Type 5 E pullup enable data output disable IN OUT Type 11 pullup g enable ma OIN OUT N ch output disable comparator Vner Threshold voltage Po P ch Vpp P ch rty 1 Voo P ch 73 CHAPTER 3 PIN FUNCTION uPD78054 Subseries 74 Figure 3 1 Pin Input Output Circuit of List 2 2 Type 12 A Vpop Type 13 D 26 9 IN OUT 2 lu enable data output disable J gt Non i Voo IN OUT output disable RD gt P ch input enable my medium breakdown analog output input buffer voltage N ch Type 13 B Type 16 Vpp lt 5 i feedback Option cut off 1 9IN OUT dat P ch ata output disable J gt N ch Fm w gt Vpp gt RD sa lt 1 medium breakdown input buffer CHAPTER 4 PIN FUNCTION uPD78054Y Subseries 4 1 Pin Function List 4 1 1 Normal operating mode pins 1 Port pins 1 3
215. 7 P12 P13 00H Ports 4 to 6 P4 to P6 Undefined Port mode register PMO to PM3 PM5 to PM7 PM12 PM13 Pull up resistor option register PUOH PUOL Processor clock control register PCC Oscillation mode selection register OSMS Memory size switching register IMS Internal expansion RAM size switching register IXS Note4 Memory expansion mode register MM Oscillation stabilization time select register OSTS 16 bit timer event counter Timer register TMO 0000H Capture compare register 00 CR01 Undefined Clock selection register TCLO 00H Mode control register TMCO 00H Capture compare control register 0 CRCO 04H Output control register TOCO 00H 8 bit timer event counter 1and2 Timer register TM1 TM2 00H Compare registers CR10 CR20 Undefined Clock select register TCL1 00H Mode control registers TMC1 00H Output control register TOC1 00H Notes 1 During reset input or oscillation stabilization time wait only the PC contents among the hardware statuses become undefined All other hardware statuses remains unchanged after reset 2 When reset in the standby mode the state before reset is held even after reset 3 The values after reset depend on the product LPD78052 78052Y 44H uPD78053 78053Y C6H uPD78054 78054Y C8H LPD78P054 C8H uPD78055 780
216. 7 4 Serial Operation Mode Register 0 Format Figure 18 3 Serial Operation Mode Register 1 Format and Table 19 2 Serial Interface Channel 2 Operating Mode Settings don t care port mode register Pxx port output latch 151 CHAPTER 6 PORT FUNCTIONS Figure 6 19 Port Mode Register Format After Symbol 7 6 5 4 3 2 1 0 Address Reset R W PMO 1 PMO6 PM05 PM04 PM02 PMO1 1 FF20H FFH R W PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H FFH R W PM2 27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R W PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H FFH R W 5 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 FF25H FFH R W PM6 PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 FF26H FFH R W PM12 PM127 PM126 PM125 PM124PM123 PM122 PM121 PM120 FF2CH FFH R W Pmn Pin Input Output Mode Selection m 0 3 5 7 12 13 n 0 7 0 Output mode output buffer ON 1 Input mode output buffer OFF 152 CHAPTER 6 PORT FUNCTIONS 2 Pull up resistor option register PUOH PUOL This register is used to set whether to use an internal pull up resistor at each port or not A pull up resistor is internally used at bits which are set to the input mode at a port where on chip pull up resistor use has been specified with PUOH PUOL No on chip pull up resistors can be used to the bits set to the output mode or to the bits us
217. 78P054 and uPD78P058 are set to the PROM programming mode This is one of the operating modes shown in Table 26 6 below according to the setting of the CE OE and PGM pins The PROM contents can be read by setting the read mode Table 26 6 PROM Programming Operating Modes Operating mode 1 2 552 Page data latch Page write Byte write Program verify Program inhibit Read Output disabled Standby Remark x Lor H Read mode Data input High impedance Data input Data output High impedance Data output QE ES E E T High impedance Read mode is set by setting CE to L and OE to L Output disable mode x High impedance If OE is set to H data output becomes high impedance and the output disable mode is set Therefore if multiple uPD78P054s or 78P058s are connected to the data bus data can be read from any one device by controlling the OE pin CHAPTER 26 uPD78P054 78P058 3 4 5 6 7 8 Standby mode Setting CE to H sets the standby mode In this mode data output becomes high impedance irrespective of the status of OE Page data latch mode Setting CE to H PGM to H and OE to L at the start of the page write mode sets the page data latch mode In this mode 1 page 4 byte data is latched in the internal address data latch circuit Page write mode After a 1 page 4 b
218. 7FFFH 0000H 104 Figure 5 12 Data Memory Addressing uPD78P054 A Special Function Registers SFRs SFR Addressing 256 x 8 bits Lih Raro pnt ta oto een te us io General Registers A Register Addressing 32 x 8 bits 1 Short Direct Addressing Internal High speed RAM 1024 x 8 bits 5 2585 Y Reserved Direct Addressing Internal Buffer RAM 32 x 8 bits Register Indirect Addressing Reserved Based Addressing Based Indexed Addressing External Memory 31360 x 8 bits Internal PROM 32768 x 8 bits Y CHAPTER 5 CPU ARCHITECTURE FE20H FE1FH FBOOH FAFFH FAEOH FADFH FACOH FABFH FA80H FA7FH A000H 9FFFH 0000H Figure 5 13 Data Memory Addressing uPD78055 78055Y Special Function Registers SFRs SFR Addressing 256 x 8 bits General Registers 32 x 8 bits Short Direct A Register Addressing WM ONCE Addressing Internal High speed RAM 1024 x 8 bits Reserved Internal Buffer RAM 32 x 8 bits Reserved Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing External Memory 23168 x 8 bits Internal ROM 40960 x 8 bits Y 105 CHAPTER 5 CPU ARCHITECTURE 106 FE20H FE1FH FBOOH FAFFH FAEOH FADFH FACOH FABFH FA80H FA7FH C000H BFFFH 0000H Figure 5 14 Data Memory Addressing uPD78056
219. 8001 R A efficiency of programs using real time OS can be improved by integrating function extension modules such as task debuggers and system performance analyzers Used in combination with separately available Device File DF78054 Part number uSxxxxID78K0 NS uSxxxxID78KO0 Note Under development Remark in the part number differs depending on the host machine and OS used uSxxxx ID78K0 NS Host Machine Supply Media PC 9800 series Japanese WindowsNote 3 5 inch 2HD FD IBM PC AT and Japanese WindowsNote 3 5 inch 2HC FD compatible English WindowsNote Note Does not support WindowsNT USxxxx ID78K0 Host Machine Supply Media PC 9800 series Japanese WindowsNote 3 5 inch 2HD FD IBM PC AT and Japanese WindowsNote 3 5 inch 2HC FD compatible English WindowsNote HP9000 series 700 HP UX Rel 9 05 DAT DDS SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD 1 4 inch CGMT NEWS RISC NEWS OS Rel 6 1 3 5 inch 2HC FD Note Does not support WindowsNT 588 APPENDIX DEVELOPMENT TOOLS B 4 OS for IBM PC The following OSs are supported for IBM PC Table B 1 OS for IBM PC Version PC DOS Ver 5 02 to Ver 6 3 J6 1 VNote to J6 3 VNote DOS J5 02 VNote MS DOS Ver 5 0 to Ver 6 22 5 0 VNote to 6 2 y Note Note Only English mode is supported Caution MS DOS ver 5 0 or later has a task swap function but it cannot be used with the
220. After the communication target device has been determined commands and data are transmitted received and serial communication is realized between the master and slave devices Figures 16 27 to 16 30 show data communication timing charts Shift operation of the serial I O shift register 0 5100 is carried out at the falling edge of serial clock SCKO Transmit data is latched into the SOO latch and is output with MSB set as the first bit from the SBO P25 or SB1 P26 pin Receive data input to the SBO or SB1 pin at the rising edge of SCKO is latched into the SIOO Lee Figure 16 27 Address Transmission from Master Device to Slave Device WUP 1 Master Device Processing Transmitter Program Processing Hardware Operation SCKO Pin 5 0 SB1 Pin Slave Device Processing Receiver LE 2227 a Hardware Operation Set Set Set to SIOO A Preparation for the Next Serial Transfer Address CMDD CMDD CHDD 7 Serial Reception RELD Set INTCSIO ACK BUSY 7777 TBUSY Generation Output Output Clear When SVA SIOO seuesqns 608 047 0 13NNVHO 39V4H31NI 1VIH3S 91 H3ldVHO 8c Figure 16 28 Command Transmission from Master Device to Slave Device Master Device Processing Transmitter Write Interrupt Servicing Hardware Operation SCKO Pin SB0 SB1 Pin Slave Device Processing Receiver seuesqns 608 0447 0 14
221. At this time control the low level width a in Figure 17 25 of the first serial clock at the timing used for setting the P27 output latch to 1 after execution of an SIOO write instruction In addition if the acknowledge signal from the master is not output if data transmission from the slave is completed set 1 in the WREL flag of SINT and release the wait For these timings see Figure 17 23 Figure 17 25 Slave Wait Release Transmission Master device operation Writing Software operation FFH to 5100 ion co NEN F SCL a 1 2 3 mre dE ON Vo P27 Write P27 Software operation output data output latch 0 to 5100 latch 1 o E Hardware operation ACK Setting Wait Hardware operation CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 3 Slave wait release slave reception The slave is released from the wait status when the WREL flag bit 2 of the interrupt timing specify register SINT is set or when an instruction that writes data to the serial I O shift register 0 SIOO is executed When the slave receives data the first bit of the data sent from the master may not be received if the SCL line immediately goes into a high impedance state after an instruction that writes data to SIO has been executed This is because SIOO does not start operating if the SCL line is in the high impedance state while the instruction that writes data to SIOO is executed until the next inst
222. Bit 7 of serial operating mode register 0 CSIMO 355 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 17 4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0 Operation stop mode 3 wire serial I O mode 2 wire serial I O mode 2 Inter IC bus mode 17 4 1 Operation stop mode Serial transfer is not carried out in the operation stop mode Thus power consumption can be reduced The serial I O shift register 0 SIOO does not carry out shift operation either and thus it can be used as ordinary 8 bit register In the operation stop mode the P25 SIO SBO SDAO P26 SO0 SB1 SDA1 and P27 SCKO SCL pins can be used as general input output ports 1 Register setting The operation stop mode is set with the serial operating mode register 0 CSIMO CSIMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H Symbol 7 lt 6 gt lt 5 gt Address After Reset R W 4 3 2 1 0 R W CSIEO Serial Interface Channel 0 Operation Control 0 Operation stopped 1 Operation enabled 356 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 17 4 2 3 wire serial mode operation The 3 wire serial I O mode is valid for connection of peripheral I O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X XL 78K and 17K series
223. CRO01 Captured Value 200 CHAPTER 8 16 BIT TIMER EVENT COUNTER 3 Pulse width measurement with free running counter and two capture registers When the 16 bit timer register TMO is operated in free running mode see register settings in Figure 8 22 it is possible to measure the pulse width of the signal input to the 00 00 When the edge specified by bits 2 and 3 ES10 and ES11 of external interrupt mode register 0 INTMO is input to the 00 00 pin the value of TMO is taken into 16 bit capture compare register 01 01 and an external interrupt request signal INTPO is set Also on the inverse edge input of that of the capture operation into CRO1 the value of is taken into 16 bit capture compare register 00 CROO Either of two edge specifications can be selected rising or falling as the valid edges for the 00 00 by means of bits 2 and 3 ES10 and ES11 of INTMO For TIOO POO pin valid edge detection sampling is performed at the interval selected by means of the sampling clock selection register SCS and a capture operation is only performed when a valid level is detected twice thus eliminating noise with a short pulse width Caution If the valid edge of TIOO POO is specified to be both rising and falling edge capture compare register 00 CROO cannot perform the capture operation Figure 8 22 Control Register Settings for Pulse Width Measurement with Free Running Counter and Two Ca
224. CSIEO 0 R RELD Bus Release Detection Clear Conditions RELD 0 Set Conditions RELD 1 When transfer start instruction is executed If SIOO and SVA values do not match in address reception only when WUP 1 When bus release signal REL is detected When CSIEO 0 When RESET input is applied R CMDD Command Detection Clear Conditions CMDD 0 Set Conditions CMDD 1 When transfer start instruction is executed When bus release signal REL is detected When CSIEO 0 When RESET input is applied When command signal CMD is detected R W Acknowledge signal is output in synchronization with the falling edge clock of SCKO just after execution ofthe instruction to be set to 1 and after acknowledge signal output automatically cleared to 0 Used as ACKE 0 Also cleared to 0 upon start of serial interface transfer or when CSIEO 0 R W ACKE Acknowledge Signal Automatic Output Control Acknowledge signal automatic output disable output with ACKT enable Before completion of Acknowledge signal is output in synchronization with the 9th clock falling edge of transfer SCKO automatically output when ACKE 1 Acknowledge signal is output in synchronization with falling edge clock After completion of of SCKO just after execution of the instruction to be set to 1 transfer automatically output when 1 However not automatically cleared to 0 after acknowled
225. CTIONS Figure 21 16 Multiple Interrupt Example 1 2 Example 1 A multiple interrupt is generated at twice Main Processing 22 Servicing Servicing Servicing IE 0 INTxx PR 1 RETI While servicing interrupt INTxx two interrupt requests INTyy and INTzz are acknowledged and a multiple interrupt is generated Before each interrupt request acknowledgment the El instruction is always issued and interrupt request acknowledgment is enabled PR 0 High priority level PR 1 Low priority level IE 0 Interrupt request acknowledgment disabled Example 2 A multiple interrupt is not generated with priority control Main Processing INTxx INTyy Servicing Servicing INTyy Y INTxx PR 1 PR 0 T 1 Instruction Execution IE 0 RETI Y Interrupt request INTyy generated while servicing interrupt INTxx is not acknowledged because it has a lower priority than INTxx and a multiple interrupt is not generated The INTyy request is reserved and acknowledged after execution of one main processing instruction PR 0 High priority level PR 1 Low priority level IE 0 interrupt request acknowledgment disabled 504 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21 16 Multiple Interrupt Example 2 2 Example 3 A multiple interrupt is not generated because interrupt is disabled Main Processing INTxx INTyy Servicing Servici
226. Clock Select Register 3 Format u 349 17 4 Serial Operating Mode Register 0 Format nene 351 17 5 Serial Bus Interface Control Register Format nennen 352 17 6 Interrupt Timing Specify Register Format a 354 17 7 3 Wire Serial Mode Timings 044 001000000 359 17 8 RHELET and CMDT Operatioris eke es edebat ON ettet 359 17 9 Circuit of Switching in Transfer Bit Order 12 2 404424 0 000 360 17 10 Serial Bus Configuration Example Using 2 Wire Serial I O Mode 361 17 11 2 Serial Mode Timings 365 17 12 RECT and GMDT Operations eroe t RE E RR n RR 366 17 13 Example of Serial Bus Configuration Using C Bus sess 367 17 14 Serial Data Transfer Timing 368 17 15 Start Condition ian LN ea ecd A dudes 369 IIS c c 369 17 17 Transfer Direction Specification 00101 369 17 18 Acknowledge Signal uu L T tt ane tet fet dt iei edt he o 370 17519 Stop GondillOIi i oett tiit c reed e ol rcd ise d cate 370 17
227. Clock specified with bits 4 to 7 of timer clock select register 3 TCL3 3 wire serial I O mode 3 wire serial I O mode with automatic transmit receive function DIR Start Bit SI Pin Function SO1 Pin Function MSB SH P20 0 1 CSIM11 x Note 2 x Note 2 x Note 2 x Note 2 LSB Note 2 x Shift Register 1 Operation Operation stop Input Serial Clock Counter Operation Control SH P20 Pin Function P20 CMOS input output SO1 CMOS output SO1 P21 Pin Function P21 CMOS input output SCK1 P22 Pin Function P22 CMOS input output 1 Note 3 Note 3 x Operation enable Count operation 11 Note 3 input SO1 CMOS output SCK1 Input SCK1 CMOS output If the external clock input has been selected with CSIM11 set to 0 set bit 1 BUSY1 and bit 2 STRB of the automatic data transmit receive control register ADTC to 0 0 2 Can be used freely as port function 3 Can be used as P20 CMOS input output when only transmitter is used clear bit 7 RE of ADTC to 0 Remark x Don t care PMxx Port mode register Pxx Port output latch 399 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 3 Automatic data transmit receive control register ADTC This register sets automatic transmit receive enable disable the operating mode strobe output enable disable busy input enable disable error check
228. Configuration 2 2 2 When using in circuit emulator IE 78001 R A Language processing software Debugging tool System simulator Integrated debugger Device file Assembler package C compiler package C library source file Device file PROM programming tool Embedded software PG 1500 controller Real time OS OS Host machine PC or EWS Interface board In circuit emulator Interface adapter PROM programming environment PROM programmer Programmer adapter PROM contained version Emulation probe Conversion socket or conversion adapter Target system Remark The parts shown within broken lines differ depending on the developing environment Refer to B 3 1 Hardware 581 APPENDIX DEVELOPMENT TOOLS B 1 Language Processing Software RA78K 0 A program that converts a program written in mnemonic into object Assembler Package codes that microcomputers can process Provided with functions to automatically perform generation of symbol table optimizing processing of branch instructions etc Used in combination with separately available Device File DF78054 lt Precautions for the use in PC environment gt Although Assembler Package is a DOS based application it can be used in a Windows environment through the use of Project Manager included in Assembler Package on Windows Part number uSxxxx
229. DEX U 595 01 Register Index Anaa EN EAEEREN AEAEE EER 595 APPENDIX REVISION HISTORY 599 24 LIST OF FIGURES 1 8 Figure No Title Page 3 1 Pin Input Outout Circuit of EISE ee Po eb eade en 73 4 1 Pin Input Output Circuit of amp ioo eee ele wall eec Pu Qha Qa EE C oe 89 5 1 Memory Map uPD78052 78052Y u au s i L 0000 00 uu Raka sag 91 5 2 Memory Map uPD78053 78053Y u 92 5 3 Memory uPD78054 78054Y L 93 5 4 Memory Map uPD78P054 inise ta ieee eth linen niin al din E Ide 94 5 5 Memory Map uPD78055 78055Y sse nennen roaa ea ea a E nnne 95 5 6 Memory uPD78056 78056Y nennen neret nennen nnne nnne 96 5 7 Memory Map uPD78058 78058Y u enne trennen 97 5 8 Memory Map uPD78P058 uPD78P058Y a 98 5 9 Data Memory Addressing uPD78052 78052Y 101 5 10 Data Memory Addressing uPD78053 78053Y a 102 5 11 Data Memory Addressing uPD78054 78054 103 5 12 Data Memory Addressing 7 8 54 enne nenne 104 5 13 Data Memory Addressing uPD78055 78055 105 5 14 Data M
230. DTI7 0 0 ADTIA ADTIS ADTIZ ADTI1 ADTIO FF6BH 00H R W Data Transfer Interval Specification fxx 5 0 MHz Operation ADTI3 ADTI2 ADTI1 MinimumNete 223 2 us 0 5 fsck MaximumNete 224 8 us 1 5 fsck 236 0 us 0 5 fsck 237 6 us 1 5 fsck 248 8 us 0 5 fscK 250 4 us 1 5 fsck 261 6 us O 5 fsck 263 2 us 1 5 fsck 274 4 us O 5 fsck 276 0 us 1 5 fsck 287 2 us O 5 fsck 288 8 us 1 5 fsck 300 0 us 0 5 fsck 301 6 us 1 5 fsck 312 8 us 0 5 fscK 314 4 us 1 5 fsck 325 6 us 0 5 fsck 327 2 us 1 5 fsck 338 4 us 0 5 fsck 340 0 us 1 5 fsck 351 2 us 0 5 fsck 352 8 us 1 5 fsck 364 0 us 0O 5 fsck 365 6 us 1 5 fsck 376 8 us 0 5 fscK 378 4 us 1 5 fsck 389 6 us 0 5 fsck 391 2 us 1 5 fsck 402 4 us 0 5 404 0 us 1 5 fsck 415 2 us 0 5 fsck 416 8 us 1 5 fsck The data transfer interval includes an error The data transfer minimum and maximum intervals are found from the following expressions n Value set in ADTIO to ADTI4 However if a minimum which is calculated by the following expressions is smaller than 2 fsck the minimum interval time is 2 fsck 6 Minimum 1 x 28 0 9 fxx fxx fsck 6 Maximum n1 2 36 1 5 fxx fsck Cautions 1 Do not write data to ADTI during op
231. Does fetch address match with correction address No Correction branch branch to address F7FDH Correction program execution ROM correction CHAPTER 25 ROM CORRECTION 25 5 ROM Correction Example The example of ROM correction when the instruction at address 1000H ADD A 1 is changed to ADD A 2 is as follows Figure 25 8 ROM Correction Example Internal ROM Internal expansion RAM 0000H 0080H Program start ADD A 2 BR 11002 1000H ADD A 1 1002H MOV B A BR F702H EFFFH 1 Branches to address F7FDH when the preset value 1000H in the correction address register matches the fetch address value after the main program is started 2 Branches to any address address F702H in this example by setting the entire space branch instruction BR laddr16 to address F7FDH with the main program 3 Returns to the internal ROM program after executing the substitute instruction ADD A 2 543 CHAPTER 25 CORRECTION 25 6 Program Execution Flow Figures 25 9 and 25 10 show the program transition diagrams when the ROM correction is used Figure 25 9 Program Transition Diagram when one place is corrected FFFFH F7FFH BR F7FDH x 2 Correction program 1 3 Internal ROM Correction place Internal ROM 0000H 1 Branches to address F7FDH when fetch address matches correction address 2 Branches to correction pr
232. ER 8 16 TIMER EVENT COUNTER 4 Capture register data retention timings If the valid edge of the TIOO POO pin is input during 16 bit capture compare register 01 CRO1 read CRO1 holds data without carrying out capture operation However the interrupt request flag PIFO is set upon detection of the valid edge Figure 8 37 Capture Register Data Retention Timing Count Pulse DAD C ADD NEGAR TMO Count Value N 1 N42 1 M 2 Edge Input N Interrupt Request Flag Capture Read Signal N Capture Operation Ignored 5 Valid edge setting Set the valid edge of the 00 pin after setting bits 1 to 3 TMC01 to TMC03 of the 16 bit timer mode control register TMC0 to 0 0 and 0 respectively and then stopping timer operation Valid edge is set with bits 2 and 3 ES10 and ES11 of the external interrupt mode register 0 INTM0 6 Re trigger of one shot pulse a One shot pulse output using software When outputting one shot pulse do not set 1 in OSPT When outputting one shot pulse again set OSP T to 1 after the INTTM00 or interrupt match signal with CR00 is generated b One shot pulse output using external trigger When outputting one shot pulses external trigger is ignored if generated again 213 CHAPTER 8 16 BIT TIMER EVENT COUNTER 7 Operation of OVFO flag OFVO flag is set to 1 in the following case The clear amp start mode on match between TMO and CROO is se
233. ERE re train aao 8 5 2 PWM output operations l l U n OR Pe usnu inasa ida s 8 5 9 PPG o utp toperatioris 9i eet e e ete Set e ett 8 5 4 Pulse width measurement operations a 8 5 5 External event counter 8 5 6 Square wave output operation u 8 5 7 One shol pulse output operation T 8 6 16 Bit Timer Event Counter Operating Precautions CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 AND 2 9 1 8 Bit Timer Event Counters 1 and 2 Functions l u 9 1 1 8 bit timer event counter 9 1 2 16 bit timer event counter mode nennen nnne n nennen tnnt 9 2 8 Bit Timer Event Counters 1 and 2 Configurations 9 3 8 Bit Timer Event Counters 1 and 2 Control Registers 9 4 8 Bit Timer Event Counters 1 and 2 Operations 9 4 1 8 bit timer event counter mode 2222 1 10000 9 4 2 16 bit timer event counter mode 9 5 Cautions on 8 Bit Timer Ev
234. FP Fine pitch 12 x 12 mm 80 pin ceramic WQFN 14 x 14 mm Note 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm 80 pin plastic TQFP Fine pitch 12 x 12 mm Electrical characteristics recommended soldering conditions Note PROM version only 578 Refer to individual data sheet APPENDIX DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the w PD78054 and 78054Y subseries Figure B 1 shows the configuration of the development tools 579 APPENDIX DEVELOPMENT TOOLS Figure B 1 Development Tool Configuration 1 2 1 When using in circuit emulator IE 78K0 NS 580 Language processing software Debugging tool System simulator Integrated debugger Device file Assembler package C compiler package C library source file Device file Embedded software Real time OS OS PROM programming tool PG 1500 controller Host machine PC Interface adapter PC card interface etc PROM programming environment PROM Emulation board Power supply Programmer unit adapter PROM contained Emulation probe version In circuit emulator Conversion socket or conversion adapter Target system APPENDIX DEVELOPMENT TOOLS Figure B 1 Development Tool
235. Fax 01 30 67 58 99 NEC Electronics France S A Spain Office Madrid Spain Tel 01 504 2787 Fax 01 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd United Square Singapore 1130 Tel 65 253 8311 Fax 65 250 3583 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 719 2377 Fax 02 719 5951 NEC do Brasil S A Cumbica Guarulhos SP Brasil Tel 011 6465 6810 Fax 011 6465 6829 J98 2 Major Revisions in This Edition Throughout Addition of uPD78052 A 78053 A 78054 A to the applicable types Deletion of uPD78P054Y from the applicable types Deletion of the following package from the uPD78052 78053 78054 78055 78056 78058 78P058 78054Y Subseries 80 pin plastic QFP 14 x 14 mm resin thickness 2 7 mm 233 Addition of Figure 9 10 Square Wave Output Operation Timing 238 Addition of Figure 9 13 Square Wave Output Operation Timing 296 Addition of Note to Figure 16 4 Serial Operating Mode Register 0 Format 430 435 Addition of 4 Synchronization control and 5 Automatic transmit receive Interval time to 18 4 3 3 wire serial mode operation with automatic transmit receive function 439 Addition
236. H ROM correction Note Correction address register CORADO CORAD1 0000H Correction control register CORCN 00H Interrupt Request flag register IFOL IFOH IF1L 00H Mask flag register MKOL MKOH MK1L FFH Priority specify flag register PROL PROH PR1L FFH External interrupt mode register INTMO INTM1 00H Key return mode register KRM 02H Sampling clock select register SCS 00H Note Provided only in the uPD78058 78058Y 78P058 78P058Y 536 CHAPTER 25 ROM CORRECTION 25 1 ROM Correction Functions The uPD78058 78058Y subseries can replace part of a program in the mask ROM with a program in the internal expansion RAM Instruction bugs found in the mask ROM can be avoided and program flow can be changed by using the ROM correction The ROM correction can correct two places max of the internal ROM program Caution The ROM correction cannot be emulated by the in circuit emulator IE 78000 R IE 78000 R A IE 78K0 NS IE 78001 R A 25 2 ROM Correction Configuration The ROM correction is executed by the following hardware Table 25 1 ROM Correction Configuration Configuration Register Correction address registers 0 and 1 CORADO CORAD1 Control register Correction control register CORCN Figure 25 1 shows a block diagram of the ROM correction Figure 25 1 Block Diagram of ROM Correction Program counter PC Correction address register CORADn
237. HAPTER 5 CPU ARCHITECTURE FEFFH FEF8H FEF7H FEFOH FEEFH FEE8H FEE7H FEEOH FEFFH FEF8H FEF7H FEFOH FEEFH FEE8H FEE7H FEEOH Figure 5 22 General Register Configuration a Absolute Name 16 Bit Processing RP3 RP2 RP1 RPO 15 0 b Function Name 16 Bit Processing HL DE BC AX 15 0 8 Bit Processing 8 Bit Processing 113 CHAPTER 5 CPU ARCHITECTURE 5 2 3 Special Function Register SFR Unlike a general register each special function register has special functions It is allocated in the FFOOH to FFFFH area The special function register can be manipulated like the general register with the operation transfer and bit manipulation instructions Manipulatable bit units 1 8 and 16 depend on the special function register type Each manipulation bit unit can be specified as follows 1 bit manipulation Describe the symbol reserved with assembler for the 1 bit manipulation instruction operand sfr bit This manipulation can also be specified with an address 8 bit manipulation Describe the symbol reserved with assembler for the 8 bit manipulation instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved with assembler for the 16 bit manipulation instruction operand sfrp When addressing an address describe an even
238. HC FD compatibles English WindowsNetest 2 HP9000 series 700 HP UX Rel 9 05 DAT DOS SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD 1 4 inch CGMT NEWS RISC NEWS OS Rel 6 1 3 5 inch 2HC FD Notes 1 Operates also in DOS environment 2 Does not support WindowsNT 594 APPENDIX D REGISTER INDEX D 1 Register Index 8 bit timer mode control register TMC1 nennen 225 8 bit timer output control register TOC1 226 8 bit timer register T TM 1 iion re D E e EPHRAIM GA REGEM iere 223 S bit timer register 2 Qu u un cu RE ete ee ee 223 16 bit timer mode control register TMC0 L 184 16 bit timer output control register TOC0 nennen nnnm nnne nennt 186 16 bit timer register T MO cce cote tette et ert cei eed dr er ree an reed 182 T6 bit timer register TM S sa HI Ee REGERE UBER IIO tU Rd Meet E 223 A ADCR A D conversion result register nennen nnne nennen nnn nnne 267 ADIS A D converter input select register uuu u nnn nnne 271 ADM A D converter mode register 1 269 ADTC Automatic data transmit receive control 400 411 ADTI Automatic d
239. IFO is set at the rising edge of the 8th clock cycle of SCL If the 9 clock wait is selected when WUP 0 CSIIFO is set at the rising edge of the 9th clock cycle of SCL CSIIFO is set if an address is received and that address coincides with the value of the slave address register SVA when WUP 1 or if the stop condition is detected 376 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 5 Pin configurations The configurations of the serial clock pin SCL and the serial data bus pins SDAO SDA1 are shown below a SCL Pin for serial clock input output dual function pin lt gt Master N ch open drain output 2 Slave Schmitt input b SDAO SDA1 Serial data input output dual function pin Uses N ch open drain output and Schmitt input buffers for both master and slave devices Note that pull up resistors are required to connect to both serial clock line and serial data bus line because open drain buffers are used for the serial clock pin SCL and the serial data bus pin SDAO or SDA1 on the 12 bus Figure 17 21 Pin Configuration Slave devices Master device SCL SCL 1 Clock output TT I Clock input Clock output 77 Clock input 4f SDAO SDA1 Data output P a 77 Data input 4f SDAO SDA1 Data output 77 gt Data input C
240. IO Shift Register 1 SIO1 b o SO1 lt SCK1 Start bit switching is realized by switching the bit order for data write to SIO1 The SIO1 shift order remains unchanged Thus switching between MSB first and LSB first must be performed before writing data to the SIO1 Transfer start Serial transfer is started by setting transfer data to the serial I O shift register 1 SIO1 when the following two conditions are satisfied Serial interface channel 1 operation control bit CSIE1 1 Internal serial clock is stopped or SCK1 is a high level after 8 bit serial transfer Caution If CSIE1 is set to 1 after data write to SIO1 transfer does not start Upon termination of 8 bit transfer serial transfer automatically stops and the interrupt request flag CSIIF1 is set CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18 4 3 3 wire serial mode operation with automatic transmit receive function This 3 wire serial mode is used for transmission reception of a maximum of 32 byte data without the use of software Once transfer is started the data prestored in the RAM can be transmitted by the set number of bytes and data can be received and stored in the RAM by the set number of bytes Handshake signals STB and BUSY are supported by hardware to transmit receive data continuously OSD On Screen Display LSI and peripheral LSI including LCD controller driver can be connected without difficulty 1
241. K1 FFE6H FFH R W Interrupt Servicing Control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Note WTMK controls standby mode release enable disable It does not perform control of interrupt function Cautions 1 If TMMK4 flag is read when a watchdog timer is used in watchdog timer mode 1 value 490 becomes undefined 2 Because port 0 has a dual function as the external interrupt request input when the output level is changed by specifying the output mode of the port function an interrupt request flag is set Therefore 1 should be set in the interrupt mask flag before using the output mode 3 Set always 1 in MK1L bits 3 through 6 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 3 Priority specify flag registers PROL PROH and PR1L The priority specify flag is used to set the corresponding maskable interrupt priority orders PROL PROH and PR1L are set with a 1 bit or 8 bit memory manipulation instruction If PROL and PROH are used as a 16 bit register PRO use a 16 bit memory manipulation instruction for the setting RESET input sets these registers to FFH Figure 21 4 Priority Specify Flag Register Format After Symbol 7 6 5 4 3 lt gt lt gt lt 0 gt Address Reset R W PROL PPR6 PPR5 PPR4 PPR3 PPR2 PPR1 PPRO TMPR4 FFE8H FFH R W lt gt 0 b 4 lt gt lt gt lt gt 0 PROH TMPRO1 TMPROOTMPR3 STPR SRPR
242. L 0 uPD78054 Subseries 4 Synchronization control and 5 Automatic transmit receive Interval time were added to 18 4 3 3 wire serial I O mode operation with automatic transmit receive function CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Precaution was added to 19 1 3 3 wire serial I O mode MSB LSB first switchable Figure 19 3 Serial Operating Mode Register 2 Format was changed Table 19 2 Serial Interface Channel 2 Operating Mode Settings was changed Figure 19 10 Receive Error Timing was corrected 19 4 4 Limitations when UART mode is used was added CHAPTER 19 SERIAL INTERFACE CHANNEL 2 APPENDIX A DIFFERENCES BETWEEN 4PD78054 78054Y SUBSERIES AND 4PD78058F 78058FY SUBSERIES was added APPENDIX A DIFFERENCES BETWEEN uPD78054 78054Y SUBSERIES AND uPD78058F 78058FY SUBSERIES APPENDIX B DEVELOPMENT TOOL Entire revision Support for in circuit emulator IE 78K0 NS APPENDIX B DEVELOPMENT TOOL APPENDIX C EMBEDDED SOFTWARE Entire revision Deletion of fuzzy inference development support System APPENDIX C EMBEDDED SOFTWARE 601 602 NEC Although NEC has taken all possible steps essage to ensure thatthe documentation supplied to our customers is complete bug free and up to date we readily accept that From errors may occur Despite all the care and precautions we ve taken you may Name encounter problems in the documenta
243. LO4 to 06 of the timer clock select register 0 TCLO For the operation when the value of the compare register is changed during the timer count operation refer to 8 6 16 Bit Timer Event Counter Precautions 3 Figure 8 10 Control Register Settings for Interval Timer Operation a 16 bit timer mode control register TMCO 03 02 01 OVFO SNNN E SESI b Capture compare control register 0 CRC0 Clear amp start on match TM0 and CR00 CRC02 CRC01 CRC00 Remark 0 1 Setting or 1 allows another function to be used simultaneously with the interval timer See CROO set as compare register the description of the respective control registers for details 191 CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 11 Interval Timer Configuration Diagram 16 Bit Capture Compare Register 00 00 INTTM3 00 2fxx 8 16 Bit Timer Register TMO fxx 2 00 Clear Circuit Figure 8 12 Interval Timer Operation Timings DES 4 81 TMO Count Value X N yeso X N X N X A Count Start Clear Clear INTTMOO i Interrupt Request Acknowledge Interrupt Request Acknowledge Interval Time Interval Time Interval Time Remark Interval time N 1 x t N 0001H to FFFFH 192 CHAPTER 8 16 TIMER EVENT COUNTER
244. LT mode is cleared and vectored interrupt service is carried out whether interrupt acknowledge is enabled or disabled Clear upon unmasked test input When an unmasked test signal is input the HALT mode is cleared and the next address instruction of the HALT instruction is executed CHAPTER 23 STANDBY FUNCTION d Clear upon RESET input When a RESET signal is input the HALT mode is released and as is the case with normal reset operation a program is executed after branch to the reset vector address Figure 23 3 HALT Mode Release by RESET Input Wait HALT 217 26 2 ms Instruction RESET Signal Oscillation Operating Reset Stabilization Operating Mode HALT Mode Period Wait Status Mode Oscillation Oscillation stop Oscillation Clock gt a Remarks 1 fx main system clock oscillation frequency 2 y fx 5 0 MHz Table 23 2 Operation after HALT Mode Release Release Source Operation Maskable interrupt Next address instruction execution request Interrupt service execution Next address instruction execution Interrupt service execution HALT mode hold Non maskable interrupt Interrupt service execution request Test input Next address instruction execution HALT mode hold RESET input Reset processing Remark x Don t care 529 CHAPTER 23 STANDBY FUNCTION 23 2 2 STOP mode 1 STOP mode set and operating status The STOP mode is set
245. M versions is given in Table 26 5 Table 26 5 Value Set to the Internal Expansion RAM Size Switching Register Pertinent mask ROM versions Value set to IXS uPD78052 78052Y uPD78053 78053Y uPD78054 78054Y 78055 78055Y uPD78056 78056Y uPD78058 78058Y Remark lfa program for the 78 058 or 78P058Y which includes MOV IXS 40CH is implemented with the uPD78055 78055Y 78056 or 78056Y this instruction is ignored and causes no malfunction 551 CHAPTER 26 uPD78P054 78P058 26 4 PROM Programming The uPD78P054 and 78P058 incorporate a 32 Kbyte and 60 Kbyte PROM as program memory respectively To write a program into the uPD78P054 or 78P058 PROM make the device enter the PROM programming mode by setting the levels of the VPP and RESET pins as specified For the connection of unused pins see paragraph 2 PROM programming mode in section 1 5 or 2 5 Pin Configuration Top View Caution In case of the yPD78P054 write the program in the range of addresses 0000H to 7FFFH specify the last address as 7FFFH In case of the uPD78P058 write the program in the range of addresses 0000H to EFFFH specify the last address as EFFFH The program cannot be correctly written by a PROM programmer which does not have a write address specification function 26 4 1 Operating modes When 5 V or 12 5 V is applied to the VPP and a low level signal is applied to the RESET pin the uPD
246. MOS output N ch open drain input output input output p p R W Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after detecting start condition when CMDD 1 matches the slave address register SVA data in bus mode R Slave address register SVA not equal to serial I O shift register 0 SIOO data Slave address register SVA equal to serial I O shift register 0 5100 data R W Operation stopped Operation enabled 1 2 3 4 5 Notes Bit 6 is a read only bit 2 bus mode the clock frequency becomes 1 16 of that output from TO2 Can be used as P25 CMOS input output when used only for transmission Can be used freely as port function To use the wake up function WUP 1 set the bit 5 SIC of the interrupt timing specify register SINT to 1 Do not execute an instruction that writes the serial I O shift register 0 S100 while WUP 1 6 When CSIEO 0 COI becomes 0 Remark x don t care PMxx Port mode register Pxx Port output latch 351 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 3 Serial bus interface control register SBIC This register sets serial bus interface operation and displays statuses SBIC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SBIC to 00H Symbol SBIC BSYE ACKD RELD CMDT RELT FF61H R W R W
247. Main System Clock 22 2 165 7 7 External Circuit of Subsystem Clock Oscillator eene 166 7 8 Examples of Incorrect Oscillator Connection a 166 7 9 Main System Clock Stop Function sese nnne enne nnne nnne enn 170 7 10 System Clock and CPU Clock Switching L 173 8 1 16 Bit Timer Event Counter Block Diagram u nennen nnne 179 8 2 16 Bit Timer Event Counter Output Control Circuit Block Diagram 180 8 3 Timer Clock Selection Register 0 Format sse nennen nnne 183 8 4 16 Bit Timer Mode Control Register Format nennen nennen 185 8 5 Capture Compare Control Register 0 Format 186 8 6 16 Bit Timer Output Control Register 187 8 7 Port Mode Regist r 3 Format u erri pre phe REM IR RR Rhe ask SAM rn eR danai ii 188 8 8 External Interrupt Mode Register 0 Formatl u 189 8 9 Sampling Clock Select Register Formatl eene nnne 190 8 10 Control Register Settings for Interval Timer 191 8 11 Interval Timer Configuration Diagram sese 192 8 12 Interval Timer Operation Timings u nnns 192 8 13
248. Mask Options CHAPTER PIN FUNCTION uPD78054 Subseries u 3 1 3 2 Pin Function List 3 1 1 3 1 2 3 2 1 3 2 2 3 2 3 3 2 4 3 2 5 3 2 6 3 2 7 3 2 8 3 2 9 3 2 10 3 2 11 3 2 12 3 2 13 3 2 14 3 2 15 3 2 16 3 2 17 Normal operating mode pins PROM programming mode pins PROM versions only Description of Pin Functions J U uu u uuu u u u J J POO to PO7 ed Q iu Q uQ ss P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 pam Port icut ee dudit POTTA uis BLUR RELIER Eh T ee ideo cereo due ett ice don te tet esegue Port RE eR eO tute dex Port 5 dete dio m Be um hei Port EEEE eO ERREUR RN ORARE MERE thas tee P120 to P127 Port E ETE 1 0 1 1 Pot a AVREFO 37 37 38 38 39 40 43 45 46 48 48 49 49 50 50 50 51 54 56 57 58 59 59 59 63 64 64 65 65 66 67 67 67 68 69 69 69 69 70 70 70 70 70 17 S218 lt d e Rl a a o tete 70 23 2419 VSS eui tiie ERREUR eed pa tels el eel BRI am
249. Memory space 64 Kbytes General register 8 bits x 8 x 4 banks Minimum With main system clock selected instruction 0 4 us 0 8 us 1 6 us 3 2 us 6 4 us 12 8 us 5 0 MHz execution time With subsystem clock selected 122 us 32 768 kHz Instruction set 16 bit operation Multiply divide 8 bits x 8 bits 16 bits 8 bits Bit manipulate set reset test and Boolean operation BCD adjust etc port Total 69 CMOS input 2 e CMOS I O 63 N ch open drain I O 4 A D converter 8 bit resolution x 8 channels D A converter 8 bit resolution x 2 channels Serial interface 3 wire serial I O SBI 2 wire serial I O mode selection possible 1 channel 3 wire serial I O mode Max 32 byte on chip auto transmit receive 1 channel 3 wire serial I O UART mode selectable 1 channel 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel Timer output Three outputs 14 bit PWM output enable 1 Clock output 19 5 kHz 39 1 kHz 78 1 kHz 156 kHz 313 kHz 625 kHz 1 25 MHz 2 5 MHz 5 0 MHz 5 0 MHz with main system clock 32 768 kHz 32 768 kHz with subsystem clock Buzzer output 1 2 kHz 2 4 kHz 4 9 kHz 9 8 kHz 5 0 MHz with main system clock Notes 1 The uPD78P054 is the PROM version for the wPD78052 78053 and 78054 2 The uPD78P058
250. Mode Item Table 23 1 HALT Mode Operating Status On Execution of HALT Instruction during Main System Clock Operation On Execution of HALT Instruction during Subsystem Clock Operation Without subsystem clockNote 1 With subsystem clockNote 1 When main system clock continues oscillation When main system clock stops oscillation Clock generator Both main system and subsystem clocks can be oscillated Clock supply to the CPU stops CPU Operation stops Port output latch Status before HALT mode setting is held 16 bit timer event counter Operable Operable when watch timer output is selected as count clock fxr is selected as count clock of watch timer or when TIOO is selected 8 bit timer event counter Operable Operable when TI1 or TI2 is selected as count clock Watch timer Operable when fxx 2 is selected as count clock Operable Operable when fx is selected as count clock Watchdog timer Operable Operation stops A D converter Operable Operation stops D A converter Operable Real time output port Operable Other than automatic Serial interface transmit receive function Operable Operable when external SCK is used Automatic transmit receive function Operation stops External interrupt INTPO INTPO is operable when clock supplied for peripheral hardwar
251. ND TEST FUNCTIONS 6 Program status word PSW PSW 496 The program status word is a register to hold the instruction execution result and the current status for interrupt request The IE flag to set maskable interrupt enable disable and the ISP flag to control multiple interrupt processing are mapped Besides 8 bit unit read write this register can carry out operations with a bit manipulation instruction and dedicated instructions El and DI When a vectored interrupt request is acknowledged or when the BRK instruction is executed contents of the PSW is automatically saved to the stack and the IE flag is reset to O If a maskable interrupt request is acknowledged contents of the priority specify flag of the acknowledged interrupt are transferred to the ISP flag Contents of the PSW is also saved into the stack with the PUSH PSW instruction It is reset from the stack with the RETI RETB and POP PSW instructions RESET input sets PSW to 02H Figure 21 9 Program Status Word Configuration State after Reset 02H 7 6 5 4 3 2 1 0 Ce Tz Tesi ac so se or Used when normal instruction is executed Priority of Interrupt Currently Being Received High priority interrupt servicing low priority interrupt disable Interrupt request not acknowledged or low priority interrupt servicing all maskable interrupts enable Interrupt Request Acknowledge Enable Disable Disable Enable CHAPTER 21 INTE
252. NNEL 0 uPD78054Y Subseries 1 2 3 4 5 346 Serial I O shift register 0 SIOO This is an 8 bit register to carry out parallel serial conversion and to carry out serial transmission reception shift operation in synchronization with the serial clock SIOO is set with an 8 bit memory manipulation instruction When bit 7 CSIEO of serial operating mode register 0 CSIMO is 1 writing data to SIOO starts serial operation In transmission data written to SIOO is output to the serial output SOO or serial data bus SBO SB1 In reception data is read from the serial input SIO or SBO SB1 to SIOO Note that if a bus is driven in the 12 bus mode or 2 wire serial I O mode the bus pin must serve for both input and output Therefore the transmission N ch open drain output of the device which will start reception of data must set to high impedance beforehand Consequently write to SIOO in advance In the 12 bus mode set SIOO to FFH with bit 7 BSYE of the serial bus interface control register SBIC set to 0 RESET input makes SIOO undefined Caution Do not execute an instruction that writes SIOO in the 12 bus mode while WUP bit 5 of the serial operating mode register 0 CSIMO 1 Even if such an instruction is not executed data can be received when the wake up function is used WUP 1 For the detail of the wake up function refer to 17 4 4 1 c Wake up function Slave address register
253. NTWDT TMIF4 TMMK4 TMPR4 INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR1 INTP2 PIF2 PMK2 PPR2 INTP3 PIF3 PMK3 PPR3 INTP4 PIF4 PMK4 PPR4 INTP5 PIF5 PMK5 PPR5 INTP6 PIF6 PMK6 PPR6 INTCSI0 CSIIF0 CSIMKO CSIPRO INTCSI1 CSIIF1 CSIMK1 CSIPR1 INTSER SERIF SERMK SERPR INTSR INTCSI2 SRIF SRMK SRPR INTST STIF STMK STPR INTTMS TMIF3 TMMK3 TMPR3 INTTM00 TMIF00 TMMK00 TMPR00 INTTM01 TMIF01 TMMK01 TMPR01 INTTM1 TMIF1 TMMK1 TMPR1 INTTM2 TMIF2 TMMK2 TMPR2 INTAD ADIF ADMK ADPR 488 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 1 Interrupt request flag registers IFOL IFOH IF1L The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input IFOL IFOH and IF1L are set with a 1 bit or 8 bit memory manipulation instruction If IFOL and IFOH are used as a 16 bit register IFO use a 16 bit memory manipulation instruction for the setting RESET input sets these registers to 00H Symbol IFOL IFOH IF1L Figure 21 2 Interrupt Request Flag Register Format lt gt 0 5b 4 lt 3 gt lt gt lt gt lt 0 gt PIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIFO TMIF4 lt gt 0 5b 4 lt 3 gt lt gt lt gt 0 TMIFO1 TMIF00 TMIF3 STIF SRIF SERIF CSIIF1 CSIIFO lt 7 gt 6 5 4 3 lt 2 gt
254. O and CR00 or match between TMO and CRO1 Clear amp start on match between TMO and CROO Match between TMO and CROO match between and 01 or TIOO valid edge Remarks 1 TOO 16 bit timer event counter output 2 TIOO 16 bit timer event counter input pin 3 TMO 16 bit timer register 4 CROO Compare register 00 5 CR01 Compare register 01 Cautions 1 Switch the clear mode and the TOO output timing after stopping the timer operation by setting 1 to TMCO3 to O O 0 2 Set the valid edge of the TIOO INTPO pin with an external interrupt mode register 0 INTMO and select the sampling clock frequency with a sampling clock select register SCS 3 When using the PWM mode set the PWM mode and then set data to CROO 4 If clear amp start mode on match between and CROO is selected when the set value of CROO is FFFFH and the TMO value changes from FFFFH to 0000H OVFO flag is set to 1 185 CHAPTER 8 16 BIT TIMER EVENT COUNTER 3 Capture compare control register 0 CRCO This register controls the operation of the capture compare registers CR00 CRO1 CRCO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CRCO value to 04H Figure 8 5 Capture Compare Control Register 0 Format Address After Reset R W FFACH 04H R W CRCO00 CROO Operating Mode Selection Operates as compare register Symbol 7 6 5 4 3 2 1 0 cnco EBKNENENEN pno
255. ORADO CORAD 1 should be set when the correction enable flag CORENO COREN 1 is 0 when the correction branch is in disabled state If address is set to CORADO or CORAD1 when CORENO or COREN is 1 when the correction branch is in enabled state the correction branch may start with the different address from the set address value Do not set the address value of instruction immediately after the instruction that sets the correction enable flag CORENO COREN1 to 1 to correction address register 0 or 1 CORADO CORAD 1 the correction branch may not start Do not set the address value in table area of table reference instruction CALLT instruction 0040H to 007FH and the address value in vector table area 0000H to 003FH to correction address registers 0 and 1 CORADO CORAD 1 Do not set two addresses immediately after the instructions shown below to correction address registers 0 and 1 CORADO CORAD1 that is when the mapped terminal address of these instructions is N do not set the address values of N 1 and N 2 RET RETI RETB BR addr16 STOP HALT CHAPTER 26 uPD78P054 78 058 The uPD78054 78054Y subseries include the uPD78P054 78P058 78P058Y as PROM versions For purposes of simplification in this chapter the description of the uPD78P058 applies to both the PD78P058 and 78P058Y Similarly the PD78052 78053 78054 78055 78056 and 78058 are treated as the representative models of the mask ROM
256. OSPT OSPE TOC04 1 50 LVRO TOCO1 TOEO TOO Output Enabled Specifies Active Level Remark 0 1 Setting or 1 allows another function to be used simultaneously with PWM output See the description of the respective control registers for details x Don t care 194 CHAPTER 8 16 BIT TIMER EVENT COUNTER By integrating 14 bit resolution PWM pulses with an external low pass filter they can be converted to an analog voltage and used for electronic tuning and D A converter applications etc The analog output voltage used for D A conversion with the configuration shown in Figure 8 14 is as follows arcs ares capture compare register 00 CROO value 216 Vner External switching circuit reference voltage Figure 8 14 Example of D A Converter Configuration with PWM Output LA PD78054 78054Y PWM signal Analog Output Van Switching Circuit Low Pass Filter Figure 8 15 shows an example in which PWM output is converted to an analog voltage and used in a voltage synthesizer type TV tuner Figure 8 15 TV Tuner Application Circuit Example 4110 V 1 PD78054 78054Y 22 47kO 47kO 47 100 2 0 22 0 22uF 022 Electronic TOO P30 Erw 10 22 uF 0 22 0 22 8 2 u PC574J 8 2 KQ 7T 195 CHAPTER 8 16 TIMER EVENT COUNTER 8 5 3 PPG output operations Setting the 16 bit timer mode control register TMCO and capture compare control re
257. OSTS to 04H However it takes 217 fx not 2 8 fx until the STOP mode is cleared by RESET input Figure 23 1 Oscillation Stabilization Time Select Register Format After Symbol 7 6 Address Reset R W 5 4 3 2 1 0 oss o o fraser re nw Selection of Oscillation Stabilization Time when STOP Mode is Released OSTS1 MCS 1 2124 819 ms MCS 0 2 8 1 64 ms 2 4 fx 3 28 ms 2 fx 6 55 ms 2 fx 6 55 ms 25 5 13 1 ms 2 fx 13 1 ms 2 426 2 ms 2 fx 26 2 ms 2 8 52 4 ms Other than above Setting prohibited Caution The wait time after STOP mode clear does not include the time see a in the illustration below from STOP mode clear to clock oscillation start regardless of clearance by RESET input or by interrupt request generation STOP Mode Clear X1 Pin Voltage Waveform Vss Remarks 1 fxx system clock frequency fx or fx 2 2 fx Main system clock oscillation frequency 3 MCS Bit 0 of oscillation mode select register OSMS 4 Values in parentheses apply to operating at fx 5 0 MHz 526 CHAPTER 23 STANDBY FUNCTION 23 2 Standby Function Operations 23 2 1 HALT mode 1 HALT mode set and operating status The HALT mode is set by executing the HALT instruction It can be set with the main system clock or the subsystem clock The operating status in the HALT mode is described below Setting of HALT
258. Output Clock output for main system clock and subsystem clock trimming P35 BUZ Output Buzzer output P36 RTP7 Output Real time output port outputting data in synchronization with trigger P120 to P127 62 CHAPTER 3 PIN FUNCTION uPD78054 Subseries 2 Pins other than port pins 2 2 Input Output Function After Reset Alternate Function Low order address data bus when expanding external memory P40 to P47 Output High order address bus when expanding external memory P50 to P57 Output Strobe signal output for read operation from external memory P64 Strobe signal output for write operation to external memory Input Wait insertion when accessing external memory Output Strobe output externally latching address information output to ports 4 5 to access external memory Input A D converter analog input P10 to P17 Output D A converter analog output P130 P131 Input A D converter reference voltage input AVREF1 Input D A converter reference voltage input AVpp A D converter analog power supply Connect to AVss A D and D A converter ground potential Connect to Vss RESET System reset input Crystal connection for main system clock oscillation Crystal connection for subsystem clock oscillation Positive power supply High voltage application for program write verify Directly connect to V
259. PTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 2 Communication operation The 2 wire serial I O mode is used for data transmission reception in 8 bit units Data transmission reception is carried out bit wise in synchronization with the serial clock Shift operation of the serial I O shift register 0 SIOO is carried out in synchronization with the falling edge of the serial clock SCKO The transmit data is held in the SOO latch and is output from the SBO P25 or SB1 P26 pin on an MSB first basis The receive data input from the SBO or SB1 pin is latched into the shift register at the rising edge of SCKO Upon termination of 8 bit transfer the shift register operation stops automatically and the interrupt request flag CSIIFO is set Figure 16 32 2 Wire Serial I O Mode Timings SCKO 1 2 3 4 5 6 7 8 SB0 SB1 Kos X ps X o X v Kor X jo CSIIFO End of Transfer Transfer Start at the Falling Edge of SCKO The SBO or SB1 pin specified for the serial data bus is an N ch open drain input output and thus it must be externally connected to a pull up resistor Because it is necessary to set N ch open drain output to high impedance state for data reception write FFH to SIOO in advance The SBO or SB1 pin generates the SOO latch status and thus the SBO or SB1 pin output status can be manipulated by setting bit 0 RELT and bit 1 CMDT of serial bus interface control register SBIC However do not car
260. Port 13 2 bit input output port Input output mode can be specified in 1 bit units When used as an input port on chip pull up resistor can be used by software ANOO ANO1 133 CHAPTER 6 PORT FUNCTIONS 6 2 Port Configuration A port consists of the following hardware Table 6 3 Port Configuration Port mode register PMm m 0 to 3 5 to 10 12 13 Pull up resistor option register PUOH PUOL Control register Memory expansion mode register MM Nete Key return mode register KRM Total 69 ports 2 inputs 67 inputs outputs Mask ROM version Pull up resistor Total 67 software specifiable 63 mask option 4 PROM version Total 63 Note MM specifies port 4 input output 6 2 1 Port 0 Port 0 is an 8 bit input output port with output latch 01 to P06 pins can specify the input mode output mode in 1 bit units with the port mode register 0 POO and pins are input only ports When P01 to P06 pins are used as input ports an on chip pull up resistor can be used to them in 6 bit units with a pull up resistor option register L PUOL Alternate functions include external interrupt request input external count clock input to the timer and crystal connection for subsystem clock oscillation RESET input sets port 0 to input mode Figures 6 2 and 6 3 show block diagrams of port 0 Caution Because port 0 also serves for external interrupt request input when the port function output
261. Pulses with the duty rate determined by the value set in 16 bit capture compare register 00 CR00 beforehand are output from the TOO P30 pin Set the active level width of the PWM pulse to the high order 14 bits of CROO Select the active level with bit 1 01 of the 16 bit timer output control register This PWM pulse has a 14 bit resolution The pulse can be converted to an analog voltage by integrating it with an external low pass filter LPF The PWM pulse is formed by a combination of the basic cycle determined by 28 and the sub cycle determined by 214 so that the time constant of the external LPF can be shortened Count clock can be selected with bits 4 to 6 104 to 1 06 of the timer clock select register 0 TCLO PWM output enable disable can be selected with bit 0 TOEO of TOCO Cautions 1 PWM operation mode should be selected before setting CROO 2 Be sure to write 0 to bits 0 and 1 of CROO 3 Do not select PWM operation mode for external clock input from the TIOO POO INTPO pin 193 CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 13 Control Register Settings for PWM Output Operation a 16 bit timer mode control register TMCO 03 02 01 OVFO b Capture compare control register 0 CRCO PWM mode CRC02 CRC01 CRC00 EE c 16 bit timer output control register CROO set as compare register
262. RA78KO CC78K 0 A program which converts a program written in C language into C Compiler Package object codes that microcomputers can process Used in combination with separately available Assembler Package and Device File Precautions for the use in PC environment Although C Compiler Package is a DOS based application it can be used in Windows environment through the use of Project Manager included in Assembler Package on Windows Part number uSxxxxCC78K0 DF78054Note A file which contains information peculiar to the device Device File Usedin combination with separately available tools RA78K 0 CC78K 0 SM78KO0 ID78KO NS ID78K0 Supporting OS and host machines are dependent on the tool to be combined with Part number uSxxxxDF78054 CC78K 0 L A source file of functions which configure the object library included C Library Source File in C Compiler package Required when modifying the object library included in C Compiler Package for customization Since this is a source file its operation environment is independent from OS Part number u SxxxxCC78K0 L Note DF78054 can commonly be used for all the products of the RA78K 0 CC78K 0 SM78KO0 ID78KO0 NS and ID78KO 582 APPENDIX DEVELOPMENT TOOLS Remark in the part number differs depending on the host machine and OS used uSxxxx RA78K0 uSxxxx CC78K0 uSxxxx DF78078 CC78K0 L Host Machine Su
263. REL Wait Sate Cancellation Control Wait state has been cancelled Cancels wait state Automatically cleared to 0 when the state is cancelled Used to cancel wait state by means of WATO and WAT1 R W Clock Level Controlete 2 Used in bus mode Make output level of SCL pin low unless serial transfer is being performed Used in bus mode Make SCL pin enter high impedance state unless serial transfer is being performed except for clock line which is kept high Used to enable master device to generate start condition and stop condition signals Notes 1 Bit 6 CLD is a read only bit 2 When not using the 12 mode set CLC to 0 354 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries Figure 17 6 Interrupt Timing Specify Register Format 2 2 R W 5 SVA Bit to be Used as Slave Address 00000000000 SVA Bit to be Used as Slave Address to be Used as Slave Address Bits 0 to 7 Bits 1 to 7 R W INTCSIO Interrupt Cause Selection Netet CSIIFO is set to 1 upon termination of serial interface channel 0 transfer CSIIFO is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer R SCKO SCL Pin Level Nete2 0 Low level 1 High level Notes 1 When using wake up function in the 12 mode set SIC to 0 2 When CSIEO 0 CLD becomes 0 Remark SVA Slave address register CSIIFO Interrupt request flag corresponding to INTCSIO CSIEO
264. RRUPT AND TEST FUNCTIONS 21 4 Interrupt Servicing Operations 21 4 4 Non maskable interrupt request acknowledge operation A non maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state It does not undergo interrupt priority control and has highest priority over all other interrupt requests If anon maskable interrupt request is acknowledged the contents of acknowledged interrupt is saved in the stacks program status word PSW and program counter PC in that order the IE and ISP flags are reset to 0 and the vector table contents are loaded into PC and branched A new non maskable interrupt request generated during execution of a non maskable interrupt servicing program is acknowledged after the current execution of the non maskable interrupt servicing program is terminated following RETI instruction execution and one main routine instruction is executed If a new non maskable interrupt request is generated twice or more during non maskable interrupt service program execution only one non maskable interrupt request is acknowledged after termination of the non maskable interrupt service program execution Figure 21 10 shows the flowchart from generation of non maskable interrupt request to acknowledgment Figure 21 11 shows non maskable interrupt request acknowledge timing and Figure 21 12 shows acknowledge operation when multiple non maskable interrupt requests are generated 497
265. S 1 TRG 0 CS 0 TRG 0 A D Conversion ANIn ANIn ANIm ANIm Conversion suspended Conversion results are Stop not stored INTAD Remarks 1 n 0 1 7 2 0 1 7 277 CHAPTER 14 A D CONVERTER 14 5 A D Converter Cautions 1 Power consumption in standby mode The A D converter operates on the main system clock Therefore its operation stops in STOP mode or in HALT mode with the subsystem clock As a current still flows in the AVrero pin at this time this current must be cut in order to minimize the overall system power dissipation In Figure 14 10 the power dissipation can be reduced by outputting a low level signal to the output port in standby mode However there is no precision to the actual AVnero voltage and therefore the conversion values themselves lack precision and can only be used for relative comparison Figure 14 10 Example of Method of Reducing Current Dissipation in Standby Mode Voo Output Port 7T 4 PD78054 78054Y AVrero Series Resistor String AVss 2 Input range of ANIO to ANI7 278 The input voltages of ANIO to ANI7 should be within the specification range In particular if a voltage above AVnero or below AVss is input even if within the absolute maximum rating range the conversion value for that channel will be indeterminate The conversion values of the other channels may also be affected
266. S 70 3 2 20 WpPE PROM versions only uru uu eR uae e s anil u u sika 70 3 2 21 1 Mask ROM version 70 3 3 input output Circuits and Recommended Connection of Unused Pins 71 CHAPTER 4 PIN FUNCTION uPD78054Y Subseries nunne mnnn nnn 75 431 Pin 75 4 1 1 Normal operating mode pins U 75 4 1 2 PROM programming mode pins PROM versions only 79 4 2 Description of Pin Functions 80 4 2 1 P00146 P0Z Porti0 a aio ook s oh rt ha ere a cas ete tede cv te pt deg 80 42 2 PAO To P17 iue tec ER ee ede ruere ees 81 4 23 P20 T0 P27 2 ia ciiam e aee on nt e EE ped ted ti 81 42 4 PICO PSZ POIL 3 82 42 5 P40406P470Portd U tet e de kl i eee ee arte EL le nds 82 4 2 6 BbO To P57 POrb5 uie ett e ten cia nc de E irem aioe 83 4 2 7 P60 to P67 Port 6 i a tede edet a i EET RS 83 4 2 8 P 720 tO P72 POTE adn cct t ct e t epe ad ac t P ecc tts 84 4 2 9 P120 10 P127 Port 12 a trae ei I tuit EH Ene 84 4 210 P130 and P191 Pott 19 errem ette etras 85 4 2 11 GANREFO II iac e ER EGRE RE 85
267. SERPRCSIPR 1 CSIPRO FFE9H FFH R W 7 6 5 4 3 2 lt gt 0 PRiL 1 1 1 1 1 TMPR2 TMPR1 FFEAH FFH R W Priority Level Selection High priority level Low priority level Cautions 1 If a watchdog timer is used in watchdog timer mode 1 set TMPR4 flag to 1 2 Set always 1 in PR1L bits 3 through 7 491 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 4 External interrupt mode register INTMO INTM1 These registers set the valid edge for INTPO to INTP6 INTMO and INTM1 set by 8 bit memory manipulation instructions RESET input sets these registers to 00H Figure 21 5 External Interrupt Mode Register 0 Format After Symbol 7 6 5 4 3 Address Reset R W 2 1 0 INTM0 ES31 ES30 ES21 ES20 ES11 ES10 FFECH 00H R W ES11 ES10 INTPO Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges Falling edge Rising edge Setting prohibited Both falling and rising edges Falling edge Rising edge Setting prohibited Both falling and rising edges Caution Before setting the valid edge of the INTPO TIOO POO pin stop the timer operation by clearing the bits 1 through 3 TMC01 through TMCO3 of the 16 bit timer mode control register to 0 0 0 492 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21 6 External Interrupt Mode Register 1 Format Symbo
268. SET input sets INTM1 to 00H Figure 14 5 External Interrupt Mode Register 1 Format After Symbol 7 6 5 4 3 2 1 0 Address Reset R W INTM1 ES71 ES70 ES61 ES60 ES51 ES50 ES41 ES40 FFEDH 00H R W ES41 ES40 INTP3 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges Falling edge Rising edge Setting prohibited Both falling and rising edges Falling edge Rising edge Setting prohibited Both falling and rising edges Falling edge Rising edge Setting prohibited Both falling and rising edges 272 CHAPTER 14 A D CONVERTER 14 4 A D Converter Operations 14 4 1 Basic operations of A D converter 1 Set the number of analog input channels with A D converter input select register ADIS 2 From among the analog input channels set with ADIS select one channel for A D conversion with A D converter mode register ADM 3 Sample amp hold circuit samples the voltage input to the selected analog input channel 4 Sampling for the specified period of time sets the sample amp hold circuit to the hold state so that the circuit holds the input analog voltage until termination of A D conversion 5 Bit 7 of the successive approximation register SAR is set and the tap selector sets the series resistor string voltage tap to 1 2 AVnero 6 The voltage difference between the series r
269. SIC INTCSIO CSIEO P25 PM25 PM27 382 SIO0 lt Data 1 4 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries Figure 17 23 Data Transmission from Slave to Master Both Master and Slave Selected 9 Clock Wait 2 of 3 b Data Master device operation Write SIOO BSYE ACKE CMDT RELT CLC WREL SIC INTCSIO Transfer line SCL SDAO 5100 FFH SIO0 FFH a lll r r T rj r 1 2 3 14 6 7 8 BQ 112 BI E 07 o6 XD5XD4XD3XD2XD1 ADOC 07 AD6AD5AD4A03 Slave device operation device Slave device operation Pn ee lt Data Write SIO0 CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSIO CSIEO P25 PM25 PM27 Yf poen r 383 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries Figure 17 23 Data Transmission from Slave to Master Both Master and Slave Selected 9 Clock Wait 3 of 3 Master device operation Write SIOO COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSIO SCL SDAO Slave device operation Write SIOO CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSIO CSIEO P25 PM25 PM27 384 r r 5100 lt FFH c Stop Condition SIO0 lt Address CX A A
270. SIOO is carried out at the falling edge of the serial clock SCKO The transmitted data is held in the SOO latch and is output from the SOO pin The received data input to the SIO pin is latched in SIOO at the rising edge of SCKO Upon termination of 8 bit transfer SIOO operation stops automatically and the interrupt request flag CSIIFO is set Figure 17 7 3 Wire Serial I O Mode Timings SCKO SIO 500 End of Transfer is Transfer Start at the Falling Edge of SCKO The SOO pin is a CMOS output pin and outputs current SOO latch statuses Thus the SOO pin output status can be manipulated by setting bit 0 RELT and bit 1 CMDT of serial bus interface control register SBIC However do not carry out this manipulation during serial transfer Control the SCKO pin output level in the output mode internal system clock mode by manipulating the P27 output latch refer to 17 4 7 SCKO SCL P27 pin output manipulation 3 Other signals Figure 17 8 shows RELT and CMDT operations Figure 17 8 RELT and CMDT Operations 500 latch RELT CMDT 359 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 4 5 360 MSB LSB switching as the start bit The 3 wire serial mode enables to select transfer to start from MSB or LSB Figure 17 9 shows the configuration of the serial I O shift register 0 SIOO and internal bus As shown in the figure MSB LSB can be read written in reverse form MSB LSB switch
271. SIOO serial of SCK0 Note 1 8 bit data to be transferred 1 ali transer in synchronization with SCKO 1 2 7 8 instruction Instructions and Master SCKO after output of only messages to the CMD Commands signal output 8 bit data to be transferred Pe Pee nois Data Master synchronization with SCKO 8 i rocessed with slave D7 to DO slave SCKO without output of p Notes 1 When WUP 0 CSIIFO is set at the rising edge of the 9th clock of SCKO When WUP 1 an address is received Only when the address matches the slave address register SVA value CSIIFO is set ifthe address does not coincide with the value of SVA RELD is cleared 2 In BUSY state transfer starts after the READY state is set seuesqns 608 047 0 14 1VIH3S 91 HaldVHO CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 5 Pin configuration The serial clock pin SCKO and serial data bus pin SBO SB1 have the following configurations a 5 0 Serial clock input output pin 1 Master CMOS and push pull output 2 Slave Schmitt input b SBO SB1 Serial data input output dual function pin Both master and slave devices have an N ch open drain output and a Schmitt input Because the serial data bus line has an N ch open drain output an external pull up resistor is necessary Figure 16 26 Pin Configuration Slave De
272. SVA This is an 8 bit register to set the slave address value for connection of a slave device to the serial bus SVA is set with an 8 bit memory manipulation instruction This register is not used in the 3 wire serial I O mode The master device outputs a slave address for selection of a particular slave device to the connected slave device These two data the slave address output from the master device and the SVA value are compared with an address comparator If they match the slave device has been selected In that case bit 6 COI of serial operating mode register 0 CSIMO becomes 1 Address comparison can also be executed on the data of LSB masked high order 7 bits by setting bit 4 SVAM of the interrupt timing specify register SINT to 1 If no matching is detected in address reception bit 2 RELD of the serial bus interface control register SBIC is cleared to 0 In the 12 bus mode the wake up function can be used by setting the bit 5 WUP of CSIMO In this case the interrupt request signal INTCSIO is generated when the slave address output by the master coincides with the value of SVA the interrupt request signal is also generated when the stop condition is detected and it can be learned by this interrupt request that the master requests for communication To use the wake up function set SIC to 1 Further when SVA transmits data as master or slave device in the the IC bus mode or 2 wire serial I O mode errors can be detect
273. Single chip Mode 0000H 513 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 514 Figure 22 1 Memory Map when Using External Device Expansion Function 3 4 e Memory map of u PD78P058 78 058 when the uPD78056 78056Y and internal PROM are 48 Kbytes FFFFH FF00H FEFFH FB00H FAFFH FADFH FACOH FABFH 7 D000H CFFFH C100H COFFH C000H BFFFH 0000H Internal High Speed RAM Reserved Internal Buffer RAM Reserved Full Address Mode when MM2 MMO 1 11 or 16 Kbyte Expansion Mode when MM2 MM0 101 4 Kbyte Expansion Mode when 2 0 100 256 byte Expansion Mode when 2 0 011 Single chip Mode CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION f uPD78058 78058 78P058 78P058Y Memory map when internal ROM PROM size is 56 Kbytes Caution Figure 22 1 Memory Map when Using External Device Expansion Function 4 4 FFFFH FF00H FEFFH FB00H FAFFH FADFH FACOH FABFH F800H F7FFH F400H F3FFH FOOOH EFFFH E100H FOFFH E000H DFFFH 0000H Internal High Speed RAM Reserved Internal Buffer RAM Reserved Internal Expansion RAM Full Address Mode when MM2 MMO 1 11 or 16 Kbyte Expansion Mode when 2 0 101 4 Kbyte Expansion Mode when 2 0 100 256 byte Expansion Mode when 2 0 011 Single chip Mode
274. Specification fxx 2 5 MHz Operation ADTI3 ADTI2 ADTI1 MinimumNete 446 4 0 5 MaximumNete 449 6 us 1 5 fsck 472 0 us 0 5 fscx 475 2 us 4 1 5 fsck 497 6 us 0 5 fscx 500 8 us 1 5 fsck 523 2 us 0 5 fscx 526 4 us 1 5 fsck 548 8 us 0 5 fscx 552 0 us 1 5 fsck 574 4 us 0 5 fsck 577 6 us 1 5 fsck 600 0 us 0 5 fsck 603 2 us 1 5 fsck 625 6 us 0 5 628 8 us 1 5 fsck 651 2 5 0 5 fsck 654 4 5 1 5 fsck 676 8 us 0 5 680 0 us 1 5 fsck 702 4 5 0 5 fsck 705 6 us 1 5 fsck 728 0 us 0 5 fsck 731 2 5 1 5 fsck 753 6 us 0 5 fscx 756 8 us 1 5 fsck 779 2 us 0 5 fsck 782 4 us 1 5 fsck 804 8 us 0 5 fscx 808 0 us 1 5 fsck 830 4 us 0 5 fsck 833 6 us 1 5 fsck The data transfer interval includes an error The data transfer minimum and maximum intervals are found from the following expressions n Value setin ADTIO to ADTI4 However if a minimum which is calculated by the following expressions is smaller than 2 fsck the minimum interval time is 2 fsck 26 28 0 5 Minimum n 1 x bx C f fsck 26 36 1 5 Maximum n 1 x bx T T fsck Cautions 1 Do not write data to ADTI during operation of automatic data transmit receive function 2 Bits 5 and 6 must be set to zero 3 To control
275. Supply Media PC 9800 series Japanese Windows 681 2 35 inch 2HD FD IBM PC AT and Japanese Windows 651 2 35 inch 2HC FD English WindowsNetest 2 compatibles HP9000 series 700 HP UX Rel 9 05 DAT DDS SPARCstation SunOS Rel 4 1 4 3 5 inch 2HC FD 1 4 inch CGMT NEWS RISC NEWS OS Rel 6 1 1 Operates also in DOS environment 2 Does not support WindowsNT 3 5 inch 2HC FD 593 APPENDIX REGISTER INDEX Real time OS 2 2 78 0 A ulTRON specification subset OS Added with MX78KO0 nucleus OS Performs task management event management and time management In task management controls the execution order of tasks and performs processing to change the task to the one executed next Precautions for the use in PC environment gt The 78 0 is a DOS based application Use it with DOS prompt on Windows Part number uSxxxxMX78K0 AAA Remark and AAA in the part number differs depending on the host machine and OS used USXxxxMX78K0 AAA Product outline Evaluation object Max No for Use in Mass Production Use for preproduction Mass production object Use for mass production Source program Host Machine PC 9800 series Can be purchased only when purchasing mass produced object Supply Media Japanese Windows 691 2 35 inch 2HD FD IBM PC AT and Japanese Windows Netes1 2 35 inch 2
276. TA TM1 TM2 Count Value 00H 01H 02H 03H 04H Timer Start 238 CHAPTER 9 8 TIMER EVENT COUNTERS 1 AND 2 2 8 bit compare register 10 and 20 setting The 8 bit compare registers 10 and 20 CR10 and CR20 can be set to 00H Thus when these 8 bit compare registers are used as event counters one pulse count operation can be carried out When the 8 bit compare register is used as 16 bit timer event counter write data to CR10 and CR20 after setting bit 0 TCE1 of the 8 bit timer mode control register 1 to 0 and stopping timer operation Figure 9 15 Event Counter Operation Timing CR10 CR20 00H TM1 TM2 Count Value 00H 00H 00H 00H TO1 TO2 N N Interrupt Request Flag 3 Operation after compare register change during timer count operation If the values after the 8 bit compare registers 10 and 20 CR10 and CR20 are changed are smaller than those of 8 bit timer registers TM1 and TM2 TM1 and TM2 continue counting overflow and then restart counting from 0 Thus if the value M after CR10 and CR20 change is smaller than value N before the change it is necessary to restart the timer after changing CR10 and CR20 Figure 9 16 Timing after Compare Register Change during Timer Count Operation COND LX p CR10 CR20 N X Remark gt gt 239 240 CHAPTER 10 WATCH TIMER 10 1 Watch Timer Functions The watch timer has
277. TER 15 D A CONVERTER u 0 eee hie eek A RRA eins 281 15 1 D A Converter 42 281 15 2 D A Converter Configuration u u u uu u u u u 282 15 3 D A Converter Control Registers u u u u J 284 15 4 Operations of D A Converter U u u u u u u u T 285 15 5 Cautions Related to D A Converter U 286 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 287 16 1 Serial Interface Channel 0 Functions U u J 288 16 2 Serial Interface Channel 0 Configuration l l u u 290 16 3 Serial Interface Channel 0 Control Registers 294 16 4 Serial Interface Channel 0 Operations cesses u u 301 16 4 1 Operation stop mode u ee ee thee rer qe eee 301 16 4 2 3 serial I O mode operation u 302 16 43 SBI mode operation 5 rie creen ep eden nde un a dear edet 307 16 4 4 2 serial mode operation u 333 16 4 5 SCK0 P27 pin output manipulation
278. TER 15 D A CONVERTER 15 1 D A Converter Functions The D A converter converts a digital input into an analog value It consists of two 8 bit resolution channels of voltage output type D A converter The conversion method used is the R 2R resistor ladder method Start the A D conversion by setting the DACEO and DACE1 of the D A converter mode register DAM There are two types of modes for the D A converter as follows 1 Normal mode Outputs an analog voltage signal immediately after the D A conversion 2 Real time output mode Outputs an analog voltage signal synchronously with the output trigger after the D A conversion Since a sine wave can be generated in the mode it is useful for an MSK modem for cordless telephone sets 281 CHAPTER 15 D A CONVERTER 15 2 D A Converter Configuration The D A converter consists of the following hardware Table 15 1 D A Converter Configuration D A conversion value set register 0 DACSO D A conversion value set register 1 DACS1 Control register D A converter mode register DAM Figure 15 1 D A Converter Block Diagram I Internal Bus D A Conversion Value Set Register 1 INTTM2 DACS1 DACSO Write D A Conversion Value DACS1 Write Set Register 0 INTTM1 DACSO AVreF1 1 131 AVss ANOO P130 Selector
279. TER 5 CPU ARCHITECTURE 5 3 2 Immediate addressing Function Immediate data in the instruction word is transferred to the program counter PC and branched This function is carried out when the CALL addr16 or BR addr16 or CALLF addr11 instruction is executed The CALL addr16 and BR addr16 instruction can branch in the entire memory space The CALLF addr11 instruction branches to an area of addresses 0800H through OFFFH Illustration In the case of CALL addr16 and BR addr16 instructions 7 0 CALL or BR Low Addr High Addr 15 87 0 PC In the case of CALLF addr11 instruction 119 CHAPTER 5 CPU ARCHITECTURE 5 3 3 Table indirect addressing Function Table contents branch destination address of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter PC and branched Before the CALLT addr5 instruction is executed table indirect addressing is performed This instruction references an address stored in the memory table at addresses 40H through 7FH and can branch in the entire memory space Illustration 7 6 5 1 0 15 8 7 6 5 10 Effective Address 0 00 0 0 0 0 0 0 dr I 7 Memory Table 0 Low Addr Effective Address 1 High Adar PC 5 3 4 Register addressing Function Register pair AX contents to be specified with an instruction word a
280. TPO P72 SCK2 ASCK O O P37 P20 SH O O P36 BUZ P21 SO1 O O P35 PCL P22 SCK1 O O 4 2 P23 STB O O P33 TH P24 BUSY O O P32 TO2 P25 SI0 SB0 SDA0 O O P31 TO1 P26 SO0 SB1 SDA1 O O P30 TO0 P27 SCK0 SCL O O P67 ASTB P40 ADO O O P66 WAIT PA1 AD1 O O P65 WR 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 OO NO lt lt lt AJ s sf n a P44 AD4 O P45 AD5 O P46 AD6 O P47 AD7 O P50 A8 O P51 A9 O P52 A10 O P53 A11 O P54 A12 O P55 A13 O Vss O P56 A14 O P57 A15 O P60 O P61 O P62 O P63 O P64 RD O Cautions 1 Be sure to connect IC Internally Connected pin to Vss directly 2 Connect pin 3 Connect AVss pin to Vss Remark Pin connection in parentheses is intended for the uPD78PO058Y 51 CHAPTER 2 OUTLINE uPD78054Y Subseries Pin Identifications 52 A8 to A15 ADO to AD7 ANIO to ANI7 ANOO to ANO7 ASCK ASTB AVrero AVREF1 AVss BUSY BUZ IC INTPO to INTP6 POO to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P72 P120 to P127 P130 P131 Address Bus Address Data Bus Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Busy Buzzer Clock Internally Connected Interrupt from Peripherals Porto Port Port2 Port3 Port4 Port5 Port6 Port7 Port12 Port13 PCL RESET RD RTPO to RTP7 RxD SBO SB1
281. Therefore if a lag of changing timing occurs on the bus because of the substrate capacity etc it may be judged as a bus release signal command signal despite that data is being transmitted Exercise care for wiring CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 16 4 4 2 wire serial mode operation The 2 wire serial mode can cope with any communication format by program Communication is basically carried out with two lines of serial clock SCKO and serial data input output SBO or SB1 Figure 16 31 Serial Bus Configuration Example Using 2 Wire Serial I O Mode Vpp Vpp Master Slave SCK0 SCK0 SB0 SB1 SB0 SB1 333 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 1 Register setting The 2 wire serial I O mode is set with the serial operating mode register 0 CSIMO the serial bus interface control register SBIC and the interrupt timing specify register SINT a Serial operating mode register 0 CSIMO CSIMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H Symbol lt gt 6 lt 5 Address After Reset R W gt 4 3 2 1 0 R W Serial Interface Channel 0 Clock Selection Input Clock to SCKO pin from off chip 8 bit timer register 2 TM2 output Clock specified with bits 0 to 3 of timer clock select register 3 TCL3 SIO SBO P25 SOO SB1 P26 5 27 Pin Function Pin Function Pin F
282. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry 24 NC S AS 10 11 12 Notice information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is
283. Transmission Conversely to the situation with even parity the number of bits with a value of 1 including the parity bit in the transmit data is controlled to be odd The value of the parity bit is as follows Number of bits with a value of 1 in transmit data is odd 0 Number of bits with a value of 1 in transmit data is even 1 Reception The number of bits with a value of 1 including the parity bit in the receive data is counted If it is even a parity error occurs iii 0 Parity When transmitting the parity bit is set to 0 irrespective of the transmit data Atreception a parity bit check is not performed Therefore a parity error is not generated irrespective of whether the parity bit is set to 0 or 1 iv No parity A parity bit is not added to the transmit data At reception data is received assuming that there is no parity bit Since there is no parity bit a parity error is not generated CHAPTER 19 SERIAL INTERFACE CHANNEL 2 c Transmission A transmit operation is started by writing transmit data to the transmit shift register TXS The start bit parity bit and stop bit s are added automatically When the transmit operation starts the data in the transmit shift register TXS is shifted out and when the transmit shift register TXS is empty a transmission completion interrupt request INTST is generated Figure 19 8 Asynchronous Serial Interface Transmission Completion In
284. When used as an input port an on chip pull up resistor can be used by software SI2 RxD SO2 TxD SCK2 ASCK P120 to P127 Port 12 8 bit input output port Input output mode can be specified in 1 bit units When used as an input port on chip pull up resistor can be used by software RTPO to RTP7 P130 and P131 Port 13 2 bit input output port Input output mode can be specified in 1 bit units When used as an input port on chip pull up resistor can be used by software ANOO ANO1 131 CHAPTER 6 PORT FUNCTIONS Table 6 2 Port Functions uPD78054Y subseries 1 2 Pin Name Function Alternate Function Input only INTPO TIOO P01 INTP1 TIO1 P02 Input output mode can be specified in 1 bit INTP2 Port 0 units INTP3 P04 8 bit input output port When used as an input port an on chip INTP4 P05 pull up resistor can be used by software INTP5 P06 INTP6 P07 Input only XT1 Port 1 P10 to P17 8 bit input output port ANIO to ANI7 Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software SH SO1 Port 2 SCK1 8 bit input output port STB Input output mode can be specified in 1 bit units BUSY When used as an input port an on chip pull up resistor can be used by software SIO SBO SDAO 500 5 1 5 1 SCK0 SCL TO0 TO1 Port 3 TO2 8 bit input output port TH Input output mode can be spec
285. X Other than above 3 uA MAX PROM version For duration of 1 5 clock no wait when instruction to read port 6 P6 and port mode register 6 PM6 is executed 200 uA MAX Other than above 3 uA MAX 144 CHAPTER 6 PORT FUNCTIONS Figure 6 13 P60 to P63 Block Diagram Output Latch Vpp e Mask Option Resistor Mask ROM products only PROM versions have no pull up resistor P60 to P63 PM60 PM63 Port mode register Port 6 read signal Port 6 write signal Figure 6 14 P64 to P67 Block Diagram RD o 3 WRem T 2 PM RD WR WRPuo RD lt O o 3 WRPonr s o WRem kan PM RD WR EP EN PM64 PM67 PUO Output Latch L o Voo ie D P64 to P67 Port mode register Port 6 read signal Port 6 write signal Pull up resistor option register P60 P63 P64 RD P65 WR 9 P66 WAIT P67 ASTB 145 CHAPTER 6 PORT FUNCTIONS 6 2 9 Port 7 This is a 3 bit input output port with output latches Input mode output mode can be specified bit wise by means of port mode register 7 PM7 When pins P70 to P72 are used as input port pins an on chip pull up resistor can be used as a 3 bit unit by means of pull up resistor option register L PUOL Alternate functions include serial interface channel 2 data input output
286. X DEVELOPMENT TOOLS B 3 1 Hardware 2 2 2 When using in circuit emulator IE 78001 R A IE 78001 R ANote 1 In circuit Emulator An in circuit emulator to debug hardware and software when developing application systems that use the 78K 0 Series Supports integrated debugger ID78K0 Used in combination with an interface adapter to connect to an emulation probe and the host machine IE 70000 98 IF B or IE 70000 98 IF CNote 1 Interface Adapter An adapter required for using a PC 9800 series except notebook type personal computer as the host machine for the IE 78001 R A IE 70000 PC IF B or IE 70000 PC IF CNote 1 Interface adapter An adapter required for using an IBM PC AT or compatible as the host machine for the IE 78001 R A IE 78000 R SV3 Interface Adapter An adapter and a cable required for using EWS as the host machine for the IE 78001 R A Used connected to the board in the IE 78001 R A Supports 10Base 5 for Ethernet A separately available adapter required for other systems IE 780308 NS EM1 Note 1 Emulation Board A board to emulate peripheral hardware peculiar to the device Used in combination with an in circuit emulator and emulation probe conversion board IE 78K0 R EX1Note 1 Emulation Probe Conversion Board A board required for using the IE 780308 NS EM1 with the IE 78001 R A IE 780308 R EM IE 78064 R EMNote 2 Emulation board Aboard to emulate peripheral hardware
287. Y uPD78058Y uPD78P058Y Maskable Vectored Internal 13 External 7 interrupt Non maskable Internal 1 source Software 1 Test input Internal 1 External 1 Supply voltage Vpp 2 0 to 6 0 V Operating ambient temperature Ta 40 to 85 C Package 2 9 Mask Options 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm 80 pin ceramic WQFN 14 x 14 mm uPD78P058 only The mask ROM versions uPD78052Y 78053Y 78054Y 78055Y 78056Y 78058Y provide pull up resistor mask options which allow users to specify whether to connect a pull up resistor to a specific port pin when the user places an order for the device production Using this mask option when pull up resistors are required reduces the number of components to add to the device resulting in board space saving The mask options provided the LPD78054Y subseries are shown in Table 2 1 Table 2 1 Mask Options of Mask ROM Versions P60 to P63 Pull up resistor connection can be specified in 1 bit units 58 CHAPTER 3 PIN FUNCTION uPD78054 Subseries 3 1 Pin Function List 3 1 1 Normal operating mode pins 1 Port pins 1 3 Pin Name nputioutput Function After Reset Alternate Function Input only INTPO TIOO in 1 bit units Input output mode can be specified INTP1 TIO1 Po 8 bit input output port on chip
288. able flag is reset to 0 when the DI instruction is executed or when an interrupt is acknowledged and set to 1 when the El instruction is executed b Zero flag Z When the operation result is zero this flag is set 1 It is reset 0 in all other cases c Register bank select flags RBSO and RBS1 These are 2 bit flags to select one of the four register banks In these flags the 2 bit information which indicates the register bank selected by SEL RBn instruction execution is stored 109 CHAPTER 5 CPU ARCHITECTURE d Auxiliary carry flag AC e f If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set 1 It is reset 0 in all other cases In service priority flag ISP This flag manages the priority of acknowledgeable maskable vectored interrupts When ISP 0 the vectored interrupt whose priority is specified by the priority specify flag registers PROL PROH and PR1L Refer to 21 3 3 Priority specify flag registers PROL PROH and PR1L to be low is disabled Whether the interrupt is actually acknowledged is controlled by the status of the interrupt enable flag IE Carry flag CY This flag stores overflow and underflow upon add subtract instruction execution It stores the shift out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution 3 Stack pointer SP This is a 16 bit register to hold the start a
289. abled 1 fxx Main system clock frequency fx or fx 2 2 fx Main system clock oscillation frequency 3 fsck Serial clock frequency CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Symbol ADTI 7 6 5 4 3 2 1 0 Address After Reset ADTI7 0 0 ADTI4 ADTI3 ADTI2 ADTI1 0 FF6BH 00H R W R W Data Transfer Interval Specification fxx 2 5 MHz Operation ADTI2 ADTI1 MinimumNete 446 4 us O 5 fsck MaximumNete 449 6 us 1 5 fsck 472 0 us 0 5 475 2 us 4 1 5 fsck 497 6 us 0 5 fscx 500 8 us 1 5 fsck 523 2 us 0 5 fsck 526 4 us 1 5 fsck 548 8 us 0 5 fscx 552 0 us 1 5 fsck 574 4 5 0 5 fsck 577 6 us 1 5 fsck 600 0 us 0 5 fsck 603 2 us 1 5 fsck o o o o o o o o 625 6 us 0 5 fsck 628 8 us 1 5 fsck 651 2 us 0 5 fscx 654 4us 1 5 fsck 676 8 us 0 5 fsck 680 0 us 1 5 fsck 702 4 us 0 5 fsck 705 6 us 1 5 fsck 728 0 us 0 5 fsck 731 2 5 1 5 fsck 753 6 us 0 5 756 8 us 1 5 fsck 779 2 5 0 5 fsck 782 4 us 1 5 fsck 804 8 us 0 5 fsck 808 0 us 1 5 fsck 830 4 us 0 5 fscx 833 6 us 1 5 fsck Note The data transfer interval includes an error The data transfer minimum and maximum intervals are found from the following expressions n Value setin ADTIO to ADTI4 However if a minimum which is calculated by the following
290. abled If a software interrupt request is acknowledged the contents is saved in the stacks program status word PSW and program counter PC in that order the IE flag is reset to 0 and the contents of the vector tables 00 and 003FH are loaded into PC and branched Return from the software interrupt is possible with the RETB instruction Caution Do not use the RETI instruction for returning from the software interrupt 21 4 4 Multiple interrupt servicing Acknowledging another interrupt request while servicing an interrupt is called a multiple interrupt A multiple interrupt is not generated unless interrupt request acknowledge enabled state IE 1 is set except non maskable interrupt When an interrupt request is acknowledged interrupt request becomes acknowledge disabled state IE 0 Therefore to enable a multiple interrupt set IE flag to 1 with El instruction during interrupt servicing and set interrupt enable state In some cases a multiple interrupt is not enabled even during interrupt enable state Itis controlled with the interrupt priority There are two interrupt priorities default priority and programmable priority The multiple interrupt is controlled with programmable priority If an interrupt request of the same priority as or a higher priority than the interrupt currently being serviced is generated it is acknowledged as a multiple interrupt If an interrupt request of the priority lower than the interrupt c
291. ag is not cleared to 0 4 When using the wake up function be sure to set BSYE to 1 Remark CSIEO Bit 7 of serial operating mode register 0 CSIMO 353 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 4 Interrupt timing specify register SINT This register sets the bus release interrupt and address mask functions and displays the SCKO SCL pin level status SINT is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SINT to 00H Figure 17 6 Interrupt Timing Specify Register Format 1 2 Symbol 7 Address After Reset R W cur Tee se aasan m m R W WAT1 WATO Wait and Interrupt Control Generates interrupt service request at rising edge of 8th SCKO clock cycle Keeping clock output in high impedance Setting prohibited Used in 2 bus mode 8 clock wait Generates interrupt service request at rising edge of 8th SCKO clock cycle In the case of master device makes SCL output low to enter wait state after 8 clock pulses are output In the case of slave device makes SCL output low to request wait state after 8 clock pulses are input Used bus mode 9 clock wait Generates interrupt service request at rising edge of 9th SCKO clock cycle In the case of master device makes SCL output low to enter wait state after 9 clock pulses are output In the case of slave device makes SCL output low to request wait state after 9 clock pulses are input R W W
292. al I O shift register 0 Serial I O shift register 1 Undefined A D conversion result register Port mode register 0 Port mode register 1 Port mode register 2 Port mode register 3 Port mode register 5 Port mode register 6 Port mode register 7 Port mode register 12 Port mode register 13 Real time output buffer register L Real time output buffer register H Real time output port mode register Ss Real time output port control register 115 CHAPTER 5 CPU ARCHITECTURE Table 5 6 Special Function Register List 2 3 Manipulatable Bit Unit Address Special Function Register SFR Name After Reset 1 bit 8 bits 16 bits Correction address register 0 Note CORADO Correction address register 1 Note CORAD1 Timer clock select register 0 TCLO Timer clock select register 1 TCL1 Timer clock select register 2 TCL2 Timer clock select register 3 TCL3 Sampling clock select register SCS 16 bit timer mode control register TMCO 8 bit timer mode control register 1 TMC1 Watch timer mode control register TMC2 Capture compare control register 0 CRCO 16 bit timer output control register TOCO 8 bit timer output contr
293. al Timing Through CPU Processing when the external clock is operating 437 19 1 Serial Interface Channel 2 Configuration essere nennen 440 19 2 Serial Interface Channel 2 Operating Mode 446 19 3 Relation between Main System Clock and Baud Rate 450 19 4 Relation between ASCK Pin Input Frequency and Baud Rate When BRGCis setto 00H u pee Et p URB HORE bu 451 19 5 Relation between Main System Clock and Baud Rate 459 19 6 Relation between ASCK Pin Input Frequency and Baud Rate When BRGC is set to 460 34 LIST OF TABLES 3 3 Table No Title Page 19 7 Receive Error Cases u xi Ld tede de dad eee ee 465 20 1 Real time Output Port Configuration u nennen nnne 478 20 2 Operation in Real time Output Buffer Register 479 20 3 Real time Output Port Operating Mode and Output Trigger 481 21 1 Interrapt Source List nee n DRE ERE 484 21 2 Various Flags Corresponding to Interrupt Request Sources 488 21 3 Times from Maskable Interrupt Request Generation to Interrupt Service 500 21 4
294. al connection for subsystem clock oscillation Positive power supply High voltage application for program write verify Directly connect to Vss in normal operating mode Ground potential Internally connected Connect directly to Vss Input Output Function PROM programming mode setting Input When 5 V or 12 5 V is applied to the VPP pin or a low level voltage is applied to the RESET the PROM programming mode is set Input High voltage application for PROM programming mode setting and program write verify A0 to A16 Input Address bus to D7 Input output Data bus Input PROM enable input program pulse input Input Read strobe input to PROM Input Program program inhibit input in PROM programming mode Positive power supply Ground potential 79 CHAPTER 4 PIN FUNCTION uPD78054Y Subseries 4 2 Description of Pin Functions 4 2 1 P00 to P07 Port 0 These are 8 bit input output ports Besides serving as input output ports they function as an external interrupt request input an external count clock input to the timer a capture trigger signal input and crystal connection for subsystem oscillation The following operating modes can be specified in 1 bit units 1 Port mode and 07 function as input only ports and P01 to P06 function as input output ports P01 to P06 can be specified for input or output ports in 1 bit units w
295. ale maskable software interrupts refer to Table 21 1 Table 21 1 Interrupt Source List 1 2 Note 1 Interrupt Default Interrupt Source Internal Vector uk Table Type Priority Trigger External Address Non Watchdog timer overflow with maskable INTWDT watchdog timer mode 1 selected Internal INTWDT Watchdog timer overflow with interval timer mode selected INTPO INTP1 INTP2 INTP3 Pin input edge detection External INTP4 INTP5 INTP6 End of serial interface channel 0 Maskable INTCSIO transfer End of serial interface channel 1 INTCSI1 transfer INTSER Serial interface channel 2 UART reception error generation Internal End of serial interface channel 2 UART reception INTSR INTCSI2 End of serial interface channel 2 3 wire transfer End of serial interface channel 2 UART transfer Notes 1 Default priorities are intended for two or more simultaneously generated maskable interrupt requests 0 is the highest priority and 20 is the lowest priority 2 Basic configuration types A to E correspond to A to E of Figure 21 1 484 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Table 21 1 Interrupt Source List 2 2 Note 1 Interrupt Default Interrupt Source Internal Vector NE Table Type Priority Trigger External Address Reference time interval signal from Maskable INTTM3 Internal
296. and XT2 Crystal resonator connect pins for subsystem clock oscillation For external clock supply input it to XT1 and its inverted signal to XT2 4 2 18 VoD Positive power supply pin 4 2 19 Vss Ground potential pin 4 2 20 VPP PROM versions only High voltage apply pin for PROM programming mode setting and program write verify Directly connect to Vss in the normal operating mode 4 2 24 IC Mask ROM version only The IC Internally Connected pin is provided to set the test mode to check the uPD78054Y Subseries before shipment Directly connect the pin to the Vss with the shortest possible wire in the normal operating mode When voltage difference is produced between the IC pin and Vss pin because the wiring between those two pins is too long or an external noise is input to the IC pin the user s program may not run normally O Directly connect IC pins to Vss pins As short as possible 86 CHAPTER 4 PIN FUNCTION uPD78054Y Subseries 4 3 Input output Circuits and Recommended Connection of Unused Pins Table 4 1 shows the input output circuit types of pins and the recommended conditions for unused pins Refer to Figure 4 1 for the configuration of the input output circuit of each type Table 4 1 Pin Input Output Circuit Types 1 2 Input Output Circuit Type 00 Connect to Vss P01 INTP1 TIO1 PO2 INTP2 Pin Name Input Output Recommended Connection of Unused Pins I
297. and ceramic oscillation b External clock External Clock 90 PD74HCUO4 or Ceramic Resonator Caution Do not execute the STOP instruction or do not set MCC bit 7 of processor clock control register PCC to 1 if an external clock is used This is because if STOP instruction is executed or MCC is set to 1 the operation of the main system clock is stopped and the X2 pin is pulled up to 165 CHAPTER 7 CLOCK GENERATOR 7 4 2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator standard 32 768 kHz connected to the XT1 and XT2 pins External clocks can be input to the main system clock oscillator In this case input a clock signal to the XT1 pin and an antiphase clock signal to the XT2 pin Figure 7 7 shows an external circuit of the subsystem clock oscillator Figure 7 7 External Circuit of Subsystem Clock Oscillator a Crystal oscillation b External clock External Clock u PD74HCUO4 Cautions 1 When using a main system clock oscillator and a subsystem clock oscillator carry out wiring in the broken line area in Figures 7 6 and 7 7 to prevent any effects from wiring capacities Minimize the wiring length Donotallow wiring to intersect with other signal conductors Do notallow wiring to come near changing high current Set the potential of the grounding position of the oscillator capacitor to that of Vss Do not ground to any gro
298. are 8 bit input output ports Beside serving as input output ports they function as timer input output clock output and buzzer output The following operating modes can be specified in 1 bit units 66 1 2 Port mode These ports function as 8 bit input output ports They can be specified in 1 bit units as input or output ports with port mode register 3 PM3 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL Control mode These ports function as timer input output clock output and buzzer output a TI1 and TI2 Pin for external count clock input to the 8 bit timer event counter b TOO to TO2 Timer output pins c PCL Clock output pin d BUZ Buzzer output pin CHAPTER 3 PIN FUNCTION uPD78054 Subseries 3 2 5 P40 to P47 Port 4 These are 8 bit input output ports Besides serving as input output ports they function as an address data bus The test input flag KRIF can be set to 1 by detecting a falling edge The following operating mode can be specified in 8 bit units 1 Port mode These ports function as 8 bit input output ports They can be specified in 8 bit units for input or output ports by using the memory expansion mode register MM When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL 2 Control mode These ports function as low order a
299. are shown in Table 19 7 What type of error was generated can be detected by reading the contents of ASIS in the reception error interrupt servicing INTSER see Figures 19 9 and 19 10 The contents of ASIS are reset 0 by reading the receive buffer register RXB or receiving the next data if there is an error in the next data the corresponding error flag is set Table 19 7 Receive Error Causes Receive Errors Parity error Transmission time parity specification and reception data parity do not match Framing error Stop bit not detected Overrun error Reception of next data is completed before data is read from receive register buffer Figure 19 10 Receive Error Timing STOP E Av Av START INTSR ete INTSER when framing overrun error occurs INTSER when parity error occurs Note Ifa reception error is generated while bit 1 ISRM of asynchronous serial interface mode register ASIM is set 1 INTSR will not be generated Cautions 1 The contents of the ASIS register are reset 0 by reading the receive buffer register RXB or receiving the next data To ascertain the error contents ASIS must be read before reading RXB 2 The receive buffer register RXB must be read even if a receive error is generated If RXB is not read an overrun error will be generated when the next data is received and the receive error state will continue indefinitely 465 CHAPTER 19 SERIAL INTERFACE CHANNEL
300. ared until the next falling edge of the serial clock If WUP is set to 1 by mistake during this time BUSY will not be cleared Therefore when setting WUP to 1 do so after clearing BUSY and then making sure that the SBO SB1 pin has gone high CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 3 Register setting The SBI mode is set with the serial operating mode register 0 CSIMO the serial bus interface control register SBIC and the interrupt timing specify register SINT a Serial operating mode register 0 CSIMO CSIMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H Symbol 7 Address After Reset R W oe eese pur an caan e m m R W Serial Interface Channel 0 Clock Selection Input Clock to SCKO pin from off chip 8 bit timer register 2 TM2 output Clock specified with bits O to 3 of timer clock select register 3 TCL3 R W Operation eui SIO SBO P25 SOO SB1 P26 5 27 Mode Pin Function Pin Function Pin Function 3 wire serial 16 4 2 3 wire serial mode operation Note 2 Note 2 SB1 N ch EC P25 CMOS open drain input output input output irc SBI mode SCK0 CMOS Note 2 Note 2 input output SBO N ch p26 CMOS open drain input output input output 2 wire serial mode see section 16 4 4 2 wire serial mode operation R W Interrupt re
301. ast address of program gt II Y Latch Address Address 1 Latch Address Address 1 Latch Address Address 1 Address Address 1 Latch E 1 Yes 0 1 ms program pulse Fail Verify 4 Bytes Pass No Address Vop 4 5 to 5 5 V Fail All bytes verified All Pass End of write Defective product 554 CHAPTER 26 uPD78P054 78P058 A2 A16 AO A1 D0 D7 Vpp 1 5 Voo Vop Vit Vit Vit Figure 26 5 Page Program Mode Timing Page Program m 4 Page Data Latch Program Verify Data Input Data Output ay eee 555 CHAPTER 26 uPD78P054 78P058 Figure 26 6 Byte Program Mode Flowchart Remark Address G G Start address N Last address of program 6 5 V 12 5 V X20 1 Yes 0 1 Ise Address Address 1 MS Program pu Pass Fail Address gt Yes Vpp 4 5 to 5 5 V Vep Pass Fail All bytes verified All Pass Defective product End of write 556 CHAPTER 26 uPD78P054 78P058 Figure 26 7 Byte Program Mode Timing Program Hi Z DO D7 Data Input aic eu Data Output Program Verify Vop4 1 5 Voo Voo Vin PGM
302. at 1 The operation timing of the bit slippage detection function through the busy signal is shown in Figure 18 22 Figure 18 22 Operation Timing of the Bit Slippage Detection Function Through the Busy Slgnal when BUSYO 1 SCK1 TE dua Lu dea Master Side 2 4 Li Ll Ll Bit Slippage Due to Noise Scki REN BERIBEE Slave Side iris EE V Y so 7 5 0100 7 57 0605 04 3 2 01 00 sh 0 5 4 2 01 00 7 07 06 4 01 1 BUSY CSIIF1 CSIE1 1 ERR ee 1 No Busy Detection oae Error Interrupt Request Generation Error Detection Remark CSIIF1 Interrupt Request Flag CSIE1 Bit 7 of serial operation mode register 1 CSIM1 ERR Bit 4 of the auto data send and receive control register ADTC 434 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 5 Automatic transmit receive interval time When using the automatic transmit receive function the read write operations from to the buffer RAM are performed after transmitting receiving one byte Therefore an interval is inserted before the next transmit receive Sincethe read write operations from to the buffer RAM are performed in parallel with the CPU processing when using the automatic transmit receive function by the internal clock the interval depends on the value which is set in the automatic transmit receive i
303. ata is held in the SOO latch and is output from the SBO SDAO P25 or SB1 SDA1 P26 pin on an MSB first basis The receive data input from the SBO or SB1 pin is latched into the shift register at the rising edge of SCKO Upon termination of 8 bit transfer the shift register operation stops automatically and the interrupt request flag CSIIFO is set Figure 17 11 2 Wire Serial I O Mode Timings SCKO 1 2 3 4 5 6 7 8 APA qp 5 0 SB1 CSIIFO End of Transfer Transfer Start at the Falling Edge of SCKO The SBO or SB1 pin specified for the serial data bus is an N ch open drain input output and thus it must be externally connected to a pull up resistor Because it is necessary to set the N ch open drain ouput to high impedance for data reception write to SIOO in advance The SBO or SB1 pin generates the SOO latch status and thus the SBO or SB1 pin output status can be manipulated by setting bit O RELT and bit 1 CMDT of serial bus interface control register SBIC However do not carry out this manipulation during serial transfer Control the SCKO pin output level in the output mode internal system clock mode by manipulating the P27 output latch refer to 17 4 7 SCKO SCL P27 pin output manipulation 365 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 3 Other signals Figure 17 12 shows RELT and CMDT operations Figure 17 12 RELT and CMDT Operations 500 Latch RELT CMDT
304. ata transmit receive interval specify register 401 412 ADTP Automatic data transmit receive address 396 ASIM Asynchronous serial interface mode register 445 453 455 478 ASIS Asynchronous serial interface status register u 447 456 B BRGC Baud rate generator control register 448 457 469 C CORADO Correction address register 0 538 CORAD1 Correction address register 1 eene nennen nennen nnne nnne nnne nennen 538 COROCN Gorrection control register pee asun Am ree e eR RE nanan 539 CROO Capture compare register 00 181 CRO1 Capture compare register 01 181 CR10 Gompare registers 10 ion dt uuu ee ep pc d de eue teer 223 CR20 Compare tegisters 20 eget te Ee en Ld UR AED e ee es 223 CRCO Capture compare control register 0 u nnne 185 CSIMO Serial operating mode register 0 296 302 315 334 350 357 382 372 CSIM1 Serial operating mode register 1 u 396 399 409 CSIM2 Serial operating mode register 2 444 452 454 467 D DACSO D A conversion val
305. atch clearance automatically cleared to 0 Also cleared to 0 when CSIEO 0 Remark CSIEO Bit 7 of serial operating mode register 0 CSIMO 363 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries c Interrupt timing specify register SINT SINT is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SINT to 00H Symbol 7 6 5 4 395 lt gt 1 Address After Reset R W 0 SINT o sic SVAM WAT1 WATO FF63H 00H R W Note 1 R W INTCSIO Interrupt Factor Selection CSIIFO is set upon termination of serial interface channel 0 transfer CSIIFO is set upon bus release detection or termination of serial interface channel 0 transfer 0 Low level 1 High level Notes 1 Bit 6 CLD is a read only bit 2 When CSIEO 0 CLD becomes 0 Caution Be sure to set bits 0 to 3 to 0 in the 2 wire serial I O mode is used Remark CSIIFO Interrupt request flag corresponding to INTCSIO CSIEO Bit 7 of serial operating mode register 0 CSIMO 364 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 2 Communication operation The 2 wire serial I O mode is used for data transmission reception in 8 bit units Data transmission reception is carried out bit wise in synchronization with the serial clock Shift operation of the serial I O shift register 0 SIOO is carried out in synchronization with the falling edge of the serial clock SCKO The transmit d
306. ate Function P40 to P47 Port 4 8 bit input output port Input output mode can be specified in 8 bit units When used as an input port an on chip pull up resistor can be used by software Test input flag KRIF is set to 1 by falling edge detection ADO to AD7 P50 to P57 Port 5 8 bit input output port LED can be driven directly Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software 8 to A15 N ch open drain input output port On chip pull up resistor can be specified by mask option Port 6 Mask ROM version only LEDs can be driven directly 8 bit input output port Input output mode can be When used as an input port an specified in 1 bit units on chip pull up resistor can be used by software ASTB 76 Port 7 3 bit input output port Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software SI2 RxD SO2 TxD SCK2 ASCK CHAPTER 4 PIN FUNCTION uPD78054Y Subseries 1 Port pins 3 3 Input Output Function Port 12 8 bit input output port Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software After Reset Alternate Function RTPO to RTP7 P130 to P131 Port 13 2 bit input output port Input outp
307. ated in case of error generation Transmit Data Stop Bit Length Specification 0 1 bit 1 2 bits Character Length Specification No Parity 7 bits 8 bits PSO Parity Bit Specification Bit Specification 0 parity always added in transmission generated No parity test in reception parity error not Odd parity Even parity Receive operation stopped Receive operation enabled TXE Transmit Operation Control 0 Transmit operation stopped 1 Transmit operation enabled Note When SCK is set to 1 and the baud rate generator output is selected the ASCK pin can be used as an input output port Cautions 1 When the 3 wire serial I O mode is selected 00H should be set ASIM 2 The serial transmit receive operation must be stopped before changing the operating mode 445 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Table 19 2 Serial Interface Channel 2 Operating Mode Settings 1 Operation Stop Mode CSIM2 CSIE2 CSIM22 70 512 P71 SO2 RxD Pin TxD Pin Functions Functions P72 SCK2 ASCK Pin Functions 0 x x y Notet x P70 P71 P72 Other than above 2 3 wire Serial I O Mode CSIM2 CSIE2 CSIM22 Shift Clock Setting prohibited 70 512 P71 SO2 RxD Pin TxD Pin Functions Functions P72 SCK2 ASCK Pin Functions 1 0
308. ates the interrupt request signal in the following cases In the 3 wire serial I O mode and 2 wire serial I O mode This circuit generates an interrupt request signal every eight serial clocks n the SBI mode When WUP is 0 Generates an interrupt request signal every eight serial clocks When WUP is 1 Generates an interrupt request signal when the serial I O shift register 0 SIOO value matches the slave address register SVA value after address reception Remark WUP is wake up function specify bit It is bit 5 of serial operating mode register 0 CSIMO To use the wake up function WUP 1 clear the bit 5 SIC of the interrupt timing specify register SINT to 0 Busy acknowledge output circuit and bus release command acknowledge detector These two circuits output and detect various control signals in the SBI mode These do not operate in the 3 wire serial I O mode and 2 wire serial I O mode 293 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 16 3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0 Timer clock select register 3 TCL3 Serial operating mode register 0 CSIMO Serial bus interface control register SBIC Interrupt timing specify register SINT 1 Timer clock select register 3 TCL3 This register sets the serial clock of serial interface channel 0 TCL3 is set with an 8 bit memo
309. aution To receive data the N ch open drain output must be set to high impedance state Therefore set the bit 7 BSYE of the serial bus interface control register SBIC to 1 in advance and write to the serial I O shift register 0 5100 When the wake up function is used by setting the bit 5 WUP of the serial operating mode register 0 CSIMO however do not write to SIOO before reception Even if is not written to SIOO the N ch open drain output is always in high impedance state 6 Address match detection method In the 12C mode the master can select a specific slave device by sending slave address data CSIIFO is set if the slave address transmitted by the master coincides with the value set to the slave address register SVA when a slave device address has a slave register SVA and the wake up function specify bit WUP 1 CSIIFO is also set when the stop condition is detected When using the wake up function set SIC to 1 Caution Slave selection non selection is detected by matching of the data address received after start condition For this match detection match detection interrupt request INTCSIO of the address to be generated with WUP 1 is normally used Thus execute selection non selection detection by slave address when WUP 1 377 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 7 Error detection In the IC bus mode transmission error detection can be performed by the f
310. automatically decremented ADTP is set with an 8 bit memory manipulation instruction The high order 3 bits must be set to 0 RESET input sets ADTP to 00H Caution Do not write data to ADTP while the automatic transmit receive function is activated Serial clock counter This counter counts the serial clocks to be output and input during transmission reception to check whether 8 bit data has been transmitted received CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18 3 Serial Interface Channel 1 Control Registers The following four types of registers are used to control serial interface channel 1 Timer clock select register 3 TCL3 Serial operating mode register 1 CSIM1 Automatic data transmit receive control register ADTC Automatic data transmit receive interval specify register ADTI 1 Timer clock select register 3 TCL3 This register sets the serial clock of serial interface channel 1 TCL3 is set with an 8 bit memory manipulation instruction RESET input sets TCL3 to 88H Remark Besides setting the serial clock of serial interface channel 1 TCL3 sets the serial clock of serial interface channel 0 397 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Symbol 7 1 0 TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 FF43H 6 5 35 Figure 18 2 Timer Clock Select Register 3 Format 4 3 2 Address After Reset 88H Serial Interface Channel 1 Serial Clock Selection fxx 2
311. bility Remark xxx indicates ROM code suffix Please refer to Quality Grades on NEC Semiconductor Devices Document number C11531E published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications 39 CHAPTER 1 OUTLINE uPD78054 Subseries 1 5 Pin Configuration Top View 1 Normal operating mode 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 mm UPD78P054GC 3B9 80 pin plastic 14 x 14 mm Resin thickness 1 4 mm uPD78052GC ooc8BT 78053GC xxx 8BT 78054GC xxx 8BT 78P054GC 8BTNote uUPD78055GC xxx 8BT 78056GC xxx 8BT 78058GC xxx 8BT 78P058GC 8BT 80 pin plastic TQFP Fine pitch 12 x 12 mm uUPD78052GK xxx BE9 78053GK xxx BE9 78054GK xxx BE9 78P054GK BE9 78055 9 78056GK xxx BE9 78058GK xxx BE9 80 pin ceramic WQFN 14 x 14 mm uPD78P054KK T 78 058 NTP1 TIO1 NTPO TIOO st CO QN e358 p 22 f 2222222 gt SS Se SS e Foadrorarac e 6 gt gt aooooooo Do n un ca xx cxx nunntau ann 0000 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 610 15 5 1 RESET 16 6 2 P127 RTP7 17 7 3 O P126 RTP6 AVss O 4 O P125 RTP5 P130 ANOO O 5 O P124 RTP4 P131 ANO1 O 6 O P123 RTP3 O 7 O P122 RTP2 P70 SI2 RxD 8 O P121 RTP1 P71 SO2 TxD O 9 O P12
312. bseries 2 Serial operating mode register 0 CSIMO 350 This register sets serial interface channel 0 serial clock operating mode operation enable stop wake up function and displays the address comparator match signal CSIMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H Caution Do not switch the operation mode 3 wire serial I O 2 wire serial I O 12 bus while the operation of serial interface channel 0 is enabled Stop the serial operation before switching the operation mode CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries Symbol Figure 17 4 Serial Operating Mode Register 0 Format lt 7 gt Address After Reset R W ce oo pur oen e e mm R W Serial Interface Channel 0 Clock Selection Input Clock to SCKO SCL pin from off chip 8 bit timer register 2 TM2 output Nete2 Clock specified with bits 0 to 3 of timer clock select register 3 TCL3 R W Operation jart pit SIO SBO SDAO SOO SB1 SDA1 SCKO SCL P27 Mode P25 Pin Function P26 Pin Function Pin Function a males 3 wire serial 910 Notes 500 SCK0 CMOS mode Input CMOS output input output Note4 Note4 p s cMos g OP SDI x x N ch open drain SCKO SCL 2 wire serial input output input output mode N ch open Note4 Note4 or SBO SDAO drain input Bus Mode P26 C
313. bus mode CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries Addition of Caution to Figure 18 5 Automatic Data Transmit Receive Interval Specify Register Format Addition of Caution to 18 4 3 3 d Busy control option CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Addition of description on port mode register 12 PM12 CHAPTER 20 REAL TIME OUTPUT PORT Addition of following products IE 78000 R A IE 70000 98 IF B IE 70000 98N IF IE 70000 PC IF B IE 78000 R SV3 5 78 0 ID78K0 78 0 Addition of IBM PC AT compatible machine as host machine Change of supported OS version APPENDIX DEVELOPMENT TOOLS APPENDIX B EMBEDDED SOFTWARE Addition of APPENDIX C REGISTER INDEX APPENDIX C REGISTER INDEX APPENDIX E REVISION HISTORY Edition 4th edition Major revisions from previous version The uPD78052 A 78053 A and 78054 A were added to the applicable types The uPD78P054Y was deleted from the applicable types The following package was deleted from the uPD78052 78053 78054 78055 78056 78058 78P058 78054Y Subseries 80 pin plastic QFP 14 x 14 mm resin thickness 2 7 mm Revised Chapters Throughout Figure 9 10 Square Wave Output Operation Timing was added Figure 9 13 Square Wave Output Operation Timing was added CHAPTER 9 8 BIT TIMER EVENT COUNTER Note was added to Figure 16 4 Serial Operating Mode Register 0 Format CHAPTER 16 SERIAL INTERFACE CHANNE
314. by executing the STOP instruction It can be set only with the main system clock Cautions 1 When the STOP mode is set the X2 pin is internally connected to viaa pull up resistor to minimize the leakage current at the crystal oscillator Thus do notuse the STOP mode in a system where an external clock is used for the main system clock 2 Because the interrupt request signal is used to clear the standby mode if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset the standby mode is immediately cleared if set Thus the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction After the wait set using the oscillation stabilization time select register OSTS the operating mode is set The operating status in the STOP mode is described below Table 23 3 STOP Mode Operating Status etting of STOP Mode With subsystem clock Without subsystem clock Clock generator Only main system clock stops oscillation CPU Operation stops Port output latch Status before STOP mode setting is held 16 bit timer event counter Operable when watch timer output is Operation stops selected as count clock fxr is selected as count clock of watch timer 8 bit timer event counter Operable when TI1 and TI2 are selected for the count clock Watch timer Operable when is selected for the Operation stops count clock Watchdog timer Operation sto
315. ce samples the input busy signal Even if the busy signal becomes active during sending or receiving of 8 bit data the wait does not apply If the busy signal becomes active at the rise of the serial clock 2 clock cycles after sending or receiving of 8 bit data ends the busy input first becomes effective at that point and thereafter sending or receiving of data waits during the period that the busy signal is active The busy signal s active level is set in bit 0 BUSYO of ADTC BUSYO 0 Active High BUSYO 1 Active Low CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Furthermore in the case that the busy control option is used select the internal clock for the serial clock The busy signal cannot be controlled with an external clock The operation timing when the busy control option is used is shown in Figure 18 19 Caution Busy control cannot be used at the same time as interval timing control using the auto data send and receive interval instruction register ADTI If both are used simultaneously busy control becomes invalid Figure 18 19 Operation Timings when Using Busy Control Option BUSYO 0 c Kits i EI 9912 22252156105 CD C C2 CD COSE A 2521222 ED COSNADE 7 BUSY Wait CSIIF1 E Busy Input Clear bostes Busy Input Valid TRF Caution When is cleared the SO1 pin becomes low level Remark CSIIF1 Interrupt request flag TRF Bit 3 of the auto data send an
316. chdog timer function or the interval timer function 3 When capture compare registers CROO CR01 are specified as compare registers 176 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 2 16 Bit Timer Event Counter Functions The 16 bit timer event counter TMO has the following functions Interval timer PWM output Pulse width measurement External event counter Square wave output One shot pulse output PWM output and pulse width measurement can be used at the same time 1 Interval timer TMO generates interrupt requests at the preset time interval Table 8 2 16 Bit Timer Event Counter Interval Times Minimum Interval Time Maximum Interval Time Resolution MCS 1 MCS 0 MCS 1 MCS 0 MCS 1 MCS 0 2 x TIOO input cycle 216 x TIOO input cycle TIOO input edge cycle 2 x 1 fx 400 ns 216 x 1 fx 13 1 ms 1 fx 200 ns 2 x 1 fx 400 ns 22 x 1 fx 800 ns 216 x 4 fx 13 1 ms 217 x 4 fx 26 2 ms 1 fx 200 ns 2 x 1 fx 400 ns 22 x 1 fx 800 ns 23 x 1 fx 1 6 us 217 x 4 fx 26 2 ms 218 x 1 fx 52 4 ms 2 x 1 fx 400 ns 22 x 1 fx 800 ns 23 x 1 fx 1 6 us 24 x 1 fx 3 2 us 218 x 1 fx 52 4 ms 219 x 1 fx 104 9 ms 22 x 1 fx 800 ns 23 x 1 fx 1 6 us 216 x watch timer output cycle 2 x watch timer output cycle Watch timer output edge cycle Remarks 1 fx Main system cl
317. cify register SINT 391 392 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18 1 Serial Interface Channel 1 Functions Serial interface channel 1 employs the following three modes Operation stop mode e 3 wire serial I O mode e 3 wire serial I O mode with automatic transmit receive function 1 2 3 Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption 3 wire serial mode MSB LSB first switchable This mode is used for 8 bit data transfer using three lines each for serial clock SCK1 serial output SO1 and serial input 611 The 3 wire serial I O mode enables simultaneous transmission reception and so decreases the data transfer processing time Since the start bit of 8 bit data to undergo serial transfer is switchable between MSB and LSB connection is enabled with either start bit device 3 wire serial I O mode is valid for connection of peripheral I O units and display controllers which incorporate a conventional synchronous serial interface such as the 75X XL 78K and 17K series 3 wire serial I O mode with automatic transmit receive function MSB LSB first switchable The mode of the same function as 2 3 wire serial I O mode added with the automatic transmit receive function The automatic transmit receive function is used to transmit receive data with a maximum of 32 bytes This function enables the hardware to transmit receive
318. cument when starting design 15 TABLE OF CONTENTS CHAPTER 1 GENERAL uPD78054 Subseries J l l u u u J T 152 uuu uu su E E yaa 1 2 dein rage c 1 3 Ordering Information u nenne uu u u u u T 1 4 DA D neni elei Su 1 5 Pin Configuration Top View u u u u u 1 6 78K 0 Series Expansion U U U u uu u u u u 1 7 Block Dliagram aa Sa eor Dua 4 s Dec P dA 1 8 Outline of Function u u uu u ceca Ce Nu u J T 1 9 Differences between Standard Quality Grade Products and A Products 1 10 Mask Options CHAPTER 2 GENERAL uPD78054Y Subseries u u u u u nnn 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 Features Applications Ordering Information Quality Grade Pin Configuration Top View u u u u u 78K 0 Series Expansion U u u u u u u J Block Diagram Outline of Function
319. d for description Table 27 1 Operand Identifiers and Description Methods Identifier Description Method X RO A R1 C R2 B R3 E R4 D R5 L R6 H R7 AX RPO BC RP1 DE RP2 HL RP3 Special function register symbolNote Special function register symbol 16 bit manipulatable register even addresses only Note FE20H FF1FH Immediate data or labels FE20H FF1FH Immediate data or labels even address only 0000H FFFFH Immediate data or labels Only even addresses for 16 bit data transfer instructions 0800 Immediate data or labels 0040H 007FH Immediate data or labels even address only 16 bit immediate data or label 8 bit immediate data or label 3 bit immediate data or label RBO to RB3 Note Addresses from FFDOH to FFDFH cannot be accessed with these operands Remark For special function register symbols refer to Table 5 6 Special Function Register List 562 CHAPTER 27 INSTRUCTION SET 27 1 2 Description of operation column A TL x BC DE HL PC SP PSW CY AC RBS IE NMIS XH XL addr16 jdisp8 A register 8 bit accumulator X register B register C register D register Eregister H register L register AX register pair 16 bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary car
320. d receive control register ADTC If the busy signal becomes inactive the wait is canceled If the sampled busy signal is inactive sending or receiving of the next 8 bit data begins from the fall of the next serial clock cycle Furthermore the busy signal is asynchronous with the serial clock so even if the slave side inactivates the busy signal it takes nearly 1 clock cycle at the most until it is sampled again Also it takes another 0 5 clock cycle after sampling until data transmission resumes Therefore in order to definitely cancel a wait state it is necessary for the slave side to keep the busy signal for at least 1 5 clock cycles Figure 18 20 shows the timing of the busy signal and wait cancel In this figure an example of the case where the busy signal becomes active when sending or receiving starts is shown 431 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 432 Figure 18 20 Busy Signal and Wait Cancel when BUSYO 0 SCK1 SO XD7XD6XD5XD4XD3XD2XD1XD0 ___ AD7ADOADSADA4ADSAD2AD1ADO 1 XDADGADSADAADSAD2ADIADO ADADOADSADA4ADSAD2AD1ADO S signal becomes inactive directly when sampled Toup BUSY Input Cancel i2 ENICO Y BUSY Input Effective b Busy amp strobe control option Strobe control is a function for synchronizing the sending and receiving of data between a master device and slave device When sending or receiving of 8 bit data ends the strobe signal is output by the master d
321. ddress data bus pins ADO to AD7 in external memory expansion mode When pins are used as an address data bus the on chip pull up resistor is automatically disabled 3 2 6 P50 to P57 Port 5 These are 8 bit input output ports Besides serving as input output ports they function as an address bus Port 5 can drive LEDs directly The following operating modes can be specified in 1 bit units 1 Port mode These ports function as 8 bit input output ports They can be specified in 1 bit units as input output ports with port mode register 5 PM5 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL 2 Control mode These ports function as high order address bus pins A8 to A15 in external memory expansion mode When pins are used as an address bus the on chip pull up resistor is automatically disabled 3 2 7 P60 to P67 Port 6 These are 8 bit input output ports Besides serving as input output ports they are used for control in external memory expansion mode P60 to P63 can drive LEDs directly The following operating modes can be specified in 1 bit units 1 Port mode These ports function as 8 bit input output ports They can be specified in 1 bit units as input or output ports with port mode register 6 PM6 P60 to P63 are N ch open drain outputs Mask ROM version can contain pull up resistors with the mask option When P64 to P67 are used as input ports on
322. ddress of the memory stack area Only the internal high speed RAM area can be set as the stack area The following shows the internal high speed RAM area of each product 110 Table 5 4 Internal High Speed RAM Area Part Number Internal High Speed RAM Area uPD78052 78052Y FD00H to FEFFH uPD78053 78053Y FB00H to FEFFH uPD78054 78054Y uPD78P054 uPD78055 78055Y uPD78056 78056Y uPD78058 78058Y uPD78P058 78P058Y CHAPTER 5 CPU ARCHITECTURE Figure 5 19 Stack Pointer Configuration SP 15 0 PC15 PC14 PC13 PC12 PC11 10 Pca PC7 Pos PCS PC4 PCS PC2 PO1 PCO The SP is decremented ahead of write save to the stack memory and is incremented after read reset from the stack memory Each stack operation saves resets data as shown in Figures 5 20 and 5 21 Caution Since RESET input makes SP contents indeterminate be sure to initialize the SP before instruction execution Figure 5 20 Data to be Saved to Stack Memory PUSH rp Instruction CALL CALLF and CALLT Instruction SP SP 3 A SP SP 2 SP SP 2 SP 3 SP 2 Register Pair Lower SP 2 PC7 PCO SP 2 1 Register Pair Upper SP 1 PC15 PC8 SP 1 SP gt SP gt SP gt Figure 5 21 Data to be Reset from Stack Memory POP rp Instruction RET Instruction SP gt Register Pair Lower SP PC7 PCO SP SP 1 Register Pair Upper SP 1 PC
323. demarks of NEC Corporation MS DOS Windows and Widows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and or other countries IBM DOS PC AT and PC DOS are trademarks of International Business Machines Corporation HP9000 Series 700 and HP UX are trademarks of Hewlett Packard Company SPARCstation is a trademark of SPARC International Inc Sun OS is a trademark of Sun Microsystems Inc Ethernet is a trademark of XEROX Corporation NEWS and NEWS OS are trademarks of SONY Corporation OSF Motif is a trademark of Open Software Foundation Inc TRON is an abbreviation of The Realtime Operating system Nucleus ITRON is an abbreviation of Industrial TRON The export of these products from Japan is regulated by the Japanese government The export of some or all of these products may be prohibited without governmental license To export or re export some or all of these products from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative License not needed uPD78P054KK T 78P058KK T 78PO58YKK T The customer must judge the need for license UPD78052GC xxx 8BT 78052GK xxx BE9 78052YGC xxx 8BT UPD78053GC xxx 8BT 78053GK xxx BE9 78053YGC xxx 8BT UPD78054GC xxx 8BT 78054GK xxx BE9 78054 8 UPD78P054GC 3B9 78P054GC 8BT 78P054GK BE9 uUPD78055GC xxx 8BT 78055GK xxx BE9 78055YGC xxx 8BT 78056
324. dition is detected R CMDD Start Condition Detection Clear Conditions When transfer start instruction is executed When stop condition is detected When CSIE0 0 When RESET input is applied Setting Condition When start condition is detected SDAO SDA1 is set to low after the Set instruction execution ACKT 1 before the next SCL falling edge Used for generating an signal by software if the 8 clock wait mode is selected Cleared to 0 if CSIE 0 when a transfer by the serial interface is started continued Note Bits 2 3 and 6 RELD CMDD ACKD are read only bits Remarks 1 Bits 0 1 and 4 RELT CMDT ACKT are 0 when read after the data is set 2 CSIEO Bit 7 of serial operating mode register 0 CSIMO 373 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries ACKE Acknowledge Signal Automatic Output ControlNete 1 Disabled with ACKT enabled Used when receiving data in the 8 clock wait mode or when transmitting data Note 2 Enabled After completion of transfer acknowledge signal is output in synchronization with the 9th falling edge of SCL clock automatically output when 1 However not automatically cleared to 0 after acknowledge signal output Used for reception when the 9 clock wait mode is selected Clear Conditions When transfer start instruction is executed When 0 When RESET input is applied Set Conditions When acknowledge s
325. e If a write to the ADM is performed during an A D conversion operation the conversion operation is initialized and if the CS bit is set 1 conversion starts again from the beginning After RESET input the value of ADCR is undefined ADCR 274 CHAPTER 14 A D CONVERTER 14 4 2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins ANIO to ANI7 and the A D conversion result the value stored in A D conversion result register ADCR is shown by the following expression VIN ADCR INT 256 0 5 or AVREFO AVREFO ADCR 0 lt V ADCR 0 5 X56 IN lt ADCR 0 5 x 256 Where Function which returns integer parts of value in parentheses VIN Analog input voltage AVrero AVnero pin voltage ADCR Value of A D conversion result register ADCR Figure 14 7 shows the relation between the analog input voltage and the A D conversion result Figure 14 7 Relations between Analog Input Voltage and A D Conversion Result 256 254 L C I L L o A D Conversion 253 E EE Results ADCR p d ee LLEVE ise qi COD S j ree 0 Se eel 1 1 3 2 5 3 507 254 509 255 511 1 512 256 512 256 512 256 512 256 512 256 512 Input Voltage AVnero 275 CHAPTER 14 A D CONVERTER 14 4 3 A D converter operati
326. e 141 6 10 P40 to P47 Block Diagram nuire terere t p at eee 142 6 11 Block Diagram of Falling Edge Detection Circuit 142 6 12 P50 to P57 Block Diagram a eec eR nde aa E 143 6 13 P60 to P63 Block Dido ran Ee i e RO epe berto ER o Qo def cbe ee epus 145 6 14 P64 to P67 Block Diagram c reale IP 145 6 15 P70 Block Diag AM teet eel tasas 146 6 16 P71 and P72 Block Diagram nte eit e eR ERR 147 6 17 P120 to P127 Block Dlagram 5 ia 1 en ect Lee ee eee Let OREL 148 25 LIST OF FIGURES 2 8 Figure No Title Page 6 18 P130 and P131 Block 149 6 19 Port Mode Register Format aiite b a EE eer edt his c idee curd 152 6 20 Pull Up Resistor Option Register Format a 153 6 21 Memory Expansion Mode Register Format U 154 6 22 Key Return Mode Register 155 7 1 Block Diagram of Clock Generator 0 u 160 7 2 Subsystem Clock Feedback Resistor L 161 7 3 Processor Clock Control Register Format nennen nen 162 7 4 Oscillation Mode Selection Register 164 7 5 Main System Clock when Writing to OSMS 02 2 4 1 1 0 164 7 6 External Circuit of
327. e Wave Output Ranges 217 9 3 Interval Times when 8 Bit Timer Event Counters 1 and 2 are Used as 16 Bit Timer Event Counters un u eddie vl ter ed te dei 218 9 4 Square Wave Output Ranges when 8 Bit Timer Event Counters 1 and 2 are Used as 16 Bit Timer Event Counters ite en uat e 219 9 5 8 Bit Timer Event Counters 1 and 2 220 9 6 8 Bit Timer Event Counter 1 Interval 229 9 7 8 Bit Timer Event Counter 2 Interval 230 33 LIST OF TABLES 2 3 Table No Title Page 9 8 8 Bit Timer Event Counters 1 and 2 Square Wave Output Ranges 232 9 9 Interval Times when 2 Channel 8 Bit Timer Event Counters TM1 and TM2 are Used as 16 Bit Timer Event Counter edu cte eee tertie fira ea Lo dee d i Feci nde 235 9 10 Square Wave Output Ranges when 2 Channel 8 Bit Timer Event Counters TM1 and TM2 are Used as 16 Bit Timer Event Counter 1 eene nennen nennen 237 10 1 Interval Timer Interval ll trn nennen 241 10 2 Waich Timer Configura O 2 2 n mirate teile d ee iat uet 242 10 3 Interval Timer Interval 2 4000000400 246 11 1 Watchdog Timer Runaway Detection
328. e completion of the automatic transmission reception not with CSIIF1 but bit 3 TRF of the automatic data transmit receive control register ADTC If busy control and strobe control are not executed the P23 STB and P24 BUSY pins can be used as normal input output ports Figure 18 8 shows the basic transmission reception mode operation timings and Figure 18 9 shows the operation flowchart Figure 18 10 shows the operation of the buffer RAM when 6 bytes of data are transmitted or received Figure 18 8 Basic Transmission Reception Mode Operation Timings Interval pvjpejpojo4jpajpejpiDO BOSCO 2 2222 Cautions 1 Because in the basic transmission reception mode the automatic transmit receive function writes reads data to from the buffer RAM after 1 byte transmission reception an interval is inserted till the next transmission reception As the buffer RAM write read is performed at the same time as CPU processing the maximum interval is dependent upon CPU processing and the value of the automatic data transmit receive interval specify register ADTI see 5 Automatic data transmit receive interval 2 When TRF is cleared the SO1 pin becomes low level Remark CSIIF1 Interrupt request flag TRF Bit 3 of automatic data transmit receive control register ADTC 417 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18 9 Basic Transmission Reception Mode Flowchart
329. e contents of the HL register pair which is used as a base register and by using the result of the addition The HL register pair to be accessed is in the register bank specified by the register bank select flags RBSO and RBS1 Addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format mee Description example MOV A HL 10H when setting byte to 10H Operation code 10101110 00010000 127 CHAPTER 5 CPU ARCHITECTURE 5 4 8 Based indexed addressing Function This addressing addresses the memory by adding the contents of the HL register which is used as a base register to the contents of the B or C register specified in the instruction word and by using the result of the addition The HL B and C registers to be accessed are registers in the register bank specified by the register bank select flags RBSO and RBS1 The addition is performed by extending the contents of the B or C register to 16 bits as a positive number carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format HL B HL C Description example In the case of MOV A HL B Operation code 5 4 9 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is a
330. e data 4 R4 Receive data 5 R5 Receive data 6 R6 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 b SCK1 501 CSIIF1 TRF Basic transmission mode In this mode the specified number of 8 bit unit data are transmitted Serial transfer is started when any data is written to the serial I O shift register 1 SIO1 while bit 7 CSIE1 of the serial operating mode register 1 CSIM1 is set to 1 The interrupt request flag CSIIF1 is set upon completion of transmission of the last byte However judge the completion of the automatic transmission reception not with CSIIF1 but bit 3 TRF of the automatic data transmit receive control register ADTC If receive operation busy control and strobe control are not executed the P20 SI1 P23 STB and P24 BUSY pins can be used as normal input ports Figure 18 11 shows the basic transmission mode operation timings and Figure 18 12 shows the operation flowchart Figure 18 13 shows the operation of the buffer RAM when 6 bytes of data are transmitted or received Figure 18 11 Basic Transmission Mode Operation Timings Interval Aozjoejpejp4jpsjpejptipo jozjpejpejp jpa oe4ptiDO Cautions 1 Because in the basic transmission mode the automatic transmit receive function reads data from the buffer RAM after 1 byte transmission an interval is inserted till the next transmission As the buffer RAM read is performed at the same time as CPU processing the maximum interva
331. e interrupt acknowledgement was corrected CHAPTER 21 Interrupt and Test Functions Oscillation stabilization time after RESET input was corrected CHAPTER 23 Standby Function ROM correction chapter was added CHAPTER 25 ROM Correction Caution on write address specification in PROM programming mode was added CHAPTER 26 uPD78P054 78P058 599 APPENDIX E REVISION HISTORY Edition 4th edition 600 Major revisions from previous version Addition of following package to all devices 80 pin plastic QFP 14 x 14 mm resin thickness 1 4 mm under planning Addition of following package to PD78058 80 pin plastic TQFP fine pitch 12 x 12 mm Revised Chapters Throughout Addition of description to Caution in Figure 8 6 16 Bit Timer Output Control Register Format CHAPTER 8 16 BIT COUNTER Change of Figure 11 3 Watchdog Timer Mode Register Format and addition of Note and Caution CHAPTER 11 WATCHDOG TIMER Addition of caution on serial I O shift register 0 5100 of HPD78054Y subseries Correction of Figure 17 22 Data Transmission from Master to Slave Both Master and Slave Selected 9 Clock Wait Correction of Figure 17 23 Data Transmission from Slave to Master Both Master and Slave Selected 9 Clock Wait Addition of 3 Slave wait release slave reception to 17 4 5 Cautions on use of bus mode Addition of 17 4 6 Restrictions in 2
332. e is selected as sampling clock bo 25 fxx 28 fxx 27 Operation stops INTP1 INTP6 Operable Bus line for ADO AD7 High impedance external 0 15 Status before HALT mode setting is held expansion ASTB Low level WR RD High level WAIT High impedance Notes 1 Including when external clock is not supplied 2 Including when external clock is supplied 527 CHAPTER 23 STANDBY FUNCTION 2 HALT mode clear The HALT mode can be cleared with the following four types of sources 528 a b c Clear upon unmasked interrupt request When an unmasked interrupt request is generated the HALT mode is cleared If interrupt request acknowledge is enabled vectored interrupt service is carried out If disabled the next address instruction is executed Figure 23 2 HALT Mode Clear upon Interrupt Request Generation Interrupt Request HALT Instruction Standby Release Signal Operating Mode HALT Mode Wait Operating Mode Oscillation Clock Remarks 1 line indicates the case when the interrupt request which has cleared the standby status is acknowledged 2 Wait time will be as follows When vectored interrupt service is carried out 8 to 9 clocks When vectored interrupt service is not carried out 2 to 3 clocks Clear upon non maskable interrupt request When a non maskable interrupt request is generated the HA
333. e main system clock is switched to the subsystem clock which must be in an oscillation stable state 4 Upon detection of Vpp voltage reset due to an interrupt request signal 0 is set to the bit 7 MCC of PCC and oscillation of the main system clock is started After the lapse of time required for stabilization of oscillation the PCC and OSMS are rewritten and the maximum speed operation is resumed Caution When subsystem clock is being operated while main system clock was stopped if switching to the main system clock is made again be sure to switch after securing oscillation stable time by software 173 174 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 1 Outline of Timers Incorporated in the u PD78054 78054Y Subseries This chapter explains 16 bit timer event counter Before that the timers incorporated into the 078054 78054Y Subseries and related circuits are outlined below 1 2 3 4 5 6 16 bit timer event counter The TMO can be used for an interval timer PWM output pulse widths measurement infrared ray remote control receive function external event counter square wave output of any frequency or one shot pulse output 8 bit timers event counters 1 and 2 TM1 and TM2 TM1 and TM2 can be used to serve as an interval timer and an external event counter and to output square waves with any selected frequency Two 8 bit timer event counters can be used as one 16 bit timer ev
334. e output mode new data set in DACSO and DACS1 and then they are held until the next trigger is generated Caution Set DACEO and DACE1 after setting data in DACSO and DACS1 285 CHAPTER 15 D A CONVERTER 15 5 Cautions Related to D A Converter 1 Output impedance of D A converter Because the output impedance of the D A converter is high use of current flowing from the ANOn pins n 0 1 is prohibited If the input impedance of the load for the converter is low insert a buffer amplifier between the load and the ANOn pins In addition wiring from the ANOn pins to the buffer amplifier or the load should be as short as possible because of high output impedance If the wiring may be long design the ground pattern so as to be close to those lines or use some other expedient to achieve shorter wiring Figure 15 3 Use Example of Buffer Amplifier a Inverting amplifier uPD78054 78054Y R2 Ri ANOn The input impedance of the buffer amplifier is R b Voltage follower UPD78054 78054Y ANOn 1 ll input impedance of the buffer amplifier is f R1 is not connected the output becomes undefined when RESET is low 2 Output voltage of D A converter Because the output voltage of the converter changes in steps use the D A converter output signals in general by connecting a low pass filter 3 pin When only either one of the D A converter channels is
335. ect register ADIS External interrupt mode register 1 INTM1 Successive approximation register SAR Register A D conversion result register ADCR 265 CHAPTER 14 A D CONVERTER Figure 14 1 A D Converter Block Diagram Internal Bus A D Converter Input Select Register Series Resistor String ANIO P10 11 G AVoo Sample amp Hold Circuit 15 2 12 note1 22 2 Voltage 19 AVntro ANI3 P13 Comparator 2 I o 1o ANI4 P14 lo ANI5 P15 l n ANI6 P16 tt 1 uccessive AVss Approximation te bete 17 G Register SAR 3 ADM1 ADM3 Edge INTP3 P03 Control INTAD Detector Circuit ES40 ES41Note3 gt INTP3 3 Trigger Enable A D Conversion ese nonne ADCR A D Converter Mode Register Internal Bus Notes 1 Selector to select the number of channels to be used for analog input 2 Selector to select the channel for A D conversion 3 Bits 0 and 1 of external interrupt mode register 1 INTM1 266 CHAPTER 14 A D CONVERTER 1 2 3 4 5 6 Successive approximation register SAR This register compares the analog input voltage value to the voltage tap compare voltage value applied from the series resistor string and holds the result from the mos
336. ection or termination of serial interface channel 0 transfer R 27 Pin LevelNetes 0 Low level 1 High level Notes 1 Bit 6 CLD is a read only bit 2 When using wake up function in the SBI mode set SIC to 0 3 When CSIEO 0 CLD becomes 0 Caution Be sure to set bits O to 3 to 0 Remark SVA Slave address register CSIIFO Interrupt request flag corresponding to INTCSIO CSIEO Bit 7 of serial operating mode register 0 CSIMO CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 16 4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0 Operation stop mode 3 wire serial mode SBI mode 2 wire serial I O mode 16 4 1 Operation stop mode Serial transfer is not carried out in the operation stop mode Thus power consumption can be reduced The serial I O shift register 0 SIOO does not carry out shift operation either and thus it can be used as ordinary 8 bit register In the operation stop mode the 25 510 5 0 P26 SO0 SB1 and P27 SCKO pins be used as ordinary input output ports 1 Register setting The operation stop mode is set with the serial operating mode register 0 CSIMO CSIMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H Symbol 7 lt 6 gt lt 5 gt 4 Address After Reset R W 3 2 1 0 R W CSIEO Serial Interface Channel 0 Operation Co
337. ed NMI NMI Request 3 is reserved 1 Instruction Request 3 Execution NMI Request 1 lt NMI Request 2 is processed NMI requests 3 is not acknowledged only one request has been acknowledged even when two or more NMI requests are generated Z 499 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21 4 2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is setto 1 and the interrupt mask flag is cleared to 0 A vectored interrupt request is acknowledged in an interrupt enable state with IE flag set to 1 However a low priority interrupt request is not acknowledged during high priority interrupt service with ISP flag reset to 0 Table 21 3 shows the time from generation of maskable interrupt request to interrupt servicing For the interrupt request acknowledging timing refer to Figure 21 14 and 21 15 Table 21 3 Times from Maskable Interrupt Request Generation to Interrupt Service Time _ Maximum Time ote When xxPRx 0 7 clocks 32 clocks When xxPRx 1 8 clocks 33 clocks Note If an interrupt request is generated just before a divide instruction the wait time is maximized Remark 1 clock zu fCPU CPU clock If two or more maskable interrupt requests are generated simultaneously the request specified for higher priority with the priority specify flag is acknowledged first
338. ed as an analog input pin irrespective of PUOH or PUOL setting PUOH and PUOL are set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to Cautions 1 00 and P07 pins do not incorporate a pull up resistor Symbol 2 When ports 1 4 5 and P64 to P67 pins are used as dual function pins an on chip pull up resistor cannot be used even if 1 is set in PUOm bit of PUOH PUOL m 1 4 to 6 3 Pins P60 to P63 can be connected with pull up resistor by mask option only for mask ROM version Figure 6 20 Pull Up Resistor Option Register Format After 7 3 2 1 0 Address Reset R W PUOH EXE UO13PUO12 0 00H R W PUOL 6 PUO5 PUO4 PUO3 PUO2 FFF7H 00H RW Caution Pm Internal Pull up Resistor Selection m 0 to 7 12 13 0 Internal pull up resistor not used 1 Internal pull up resistor used Bits 0 to 3 6 and 7 of PUOH should be set to 0 153 CHAPTER 6 PORT FUNCTIONS 3 Memory expansion mode register MM This register is used to set input output of port 4 MM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 10H Figure 6 21 Memory Expansion Mode Register Format After Symbol 7 6 5 4 3 2 1 0 Address Reset R W MM 0 0 PW1 PWO 0 MM2 MM1 MMO FFF8H 10H R W Single chip Memory P40 P47 P50 P57 P64 P67 Pin State Expansion Mode Selection P40 P47 P50 P53 P54 P55 P56 P57 P64 P67
339. ed by using TRF not CSIIF1 Interrupt request flag Caution When external clock input is selected with bit 1 CSIM11 of the serial operating mode register 1 CSIM1 set to 0 set STRB and BUSY1 of ADTC to 0 0 When an external clock is input hand shake control cannot be performed Remark Don t care 400 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 4 Automatic data transmit receive interval specify register ADTI This register sets the automatic data transmit receive function data transfer interval ADTI is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets ADTI to 00H Symbol Figure 18 5 Automatic Data Transmit Receive Interval Specify Register Format 1 4 7 6 Address After Reset R W 5 4 3 2 1 0 ADTI ADTI7 EREN ADTI4 ADTIS ADTI2 ADTI1 ADTIO 00H R W ADTI7 Data Transfer Interval Control 0 No control of interval by ADTINote 1 1 Control of interval by ADTI ADTIO to ADTIA Data Transfer Interval Specification fxx 2 5 0 MHz Operation ADTIS ADTI2 ADTI1 MinimumNete 2 MaximumNete 2 18 4 ws 0 5 fsck 20 0 us 1 5 fsck 31 2 us 0 5 fsck 32 8 us 1 5 fsck 44 0 us 0 5 fsck 45 6 us 1 5 fsck 56 8 5 0 5 fscx 58 4 5 1 5 fsck 69 6 us 0 5 fsck 71 2 us 1 5 fsck 82 4 us 0O 5 fsck 84 0 us 1 5 fsck 95 2 us 0 5 fsck 96 8 us 1 5 fsck 108 0 us 0 5 fsck 109 6 us 1 5 fsck 120 8 ws
340. ed using SVA RESET input makes SVA undefined 500 latch This latch holds SIO SBO SDAO P25 and SOO SB1 SDA1 P26 pin levels It can be directly controlled by software Serial clock counter This counter counts the serial clocks to be output and input during transmission reception and to check whether 8 bit data has been transmitted received Serial clock control circuit This circuit controls serial clock supply to the serial I O shift register 0 5100 When the internal system clock is used the circuit also controls clock output to the SCKO SCL P27 pin CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 6 Interrupt request signal generator This circuit controls interrupt request signal generation It generates interrupt request signals according to the settings of interrupt timing specification register SINT bits 0 and 1 WAT1 and serial operation mode register 0 CSIMO bit 5 WUP as shown in Table 17 3 7 Acknowledge output circuit and stop condition start condition acknowledge detector These two circuits output and detect various control signals in the 12C mode These do not operate in the 3 wire serial mode and 2 wire serial I O mode Table 17 3 Serial Interface Channel 0 Interrupt Request Signal Generation Serial Transfer mode Description 3 wire or 2 wire serial I O mode An interrupt request signal is generated each time 8 serial clocks are counted Other than above Setting prohibited
341. efined FFDFH FFEOH Interrupt request flag register OL 00H FFE1H Interrupt request flag register FFE2H Interrupt request flag register 1L FFE4H Interrupt mask flag register OL FFE5H Interrupt mask flag register OH FFE6H Interrupt mask flag register 1L FFE8H Priority order specify flag register OL 9 Priority order specify flag register ay aly al ae FFEAH Priority order specify flag register 1L FFECH External interrupt mode register 0 FFEDH External interrupt mode register 1 FFFOH Memory size switching register FFF2H Oscillation mode selection register FFF3H Pull up resistor option register H FFF4H Internal expansion RAM size switching register Note3 FFF6H Key return mode register FFF7H Pull up resistor option register L FFF8H Memory expansion mode register FFF9H Watchdog timer mode register FFFAH Oscillation stabilization time select register FFFBH Processor clock control register Notes 1 The external access area cannot be accessed in SFR addressing Access the area with direct addressing 2 The value after reset depends on products UPD78052 78052Y 44H uPD78053 78053Y C6H uPD78054 78054Y uPD78P054 C8H 78055 78055Y uPD78056 78056Y CCH
342. egister PCC Oscillation mode selection register OSMS 1 Processor clock control register PCC The PCC sets whether to use CPU clock selection the ratio of division main system clock oscillator operation stop and subsystem clock oscillator internal feedback resistor The PCC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets the PCC to 04H Figure 7 2 Subsystem Clock Feedback Resistor FRC P ch Feedback resistor Wl f gt 161 CHAPTER 7 CLOCK GENERATOR Figure 7 3 Processor Clock Control Register Format After Symbol 7 6 5 lt 4 gt 3 2 1 0 Address Reset R W PCC MCC FRC CLS CSS 2 PCC1 PCC0 FFFBH 04H R w eet CPU Clock fceu Selection R W MCS 1 Other than above Setting prohibited R CPU Clock Status 0 Main system clock 1 Subsystem clock R W Subsystem Clock Feedback Resistor Selection Subsystem Clock Feedback Resistor Selection Feedback Resistor Selection Internal feedback resistor used Internal feedback resistor not used R W Main Main System Clock Oscillation Clock Oscillation Main System Clock Oscillation Oscillation possible Oscillation stopped Notes 1 Bit 5 is Read Only 2 When the CPU is operating on the subsystem clock MCC should be used to stop the main system clock oscillation A STOP instruction should not be used Cauti
343. el is high the ROM correction is used otherwise it is not used After reset store the contents that have been previously stored in the external nonvolatile memory with initialization routine for ROM correction of the user to internal expansion RAM see Figure 25 6 Set the start address of the instruction to be corrected to CORADO and CORAD1 and set bits 1 and 3 CORENO COREN 1 of the correction control register CORCN to 1 Set the entire space branch instruction BR addr16 to the specified address F7FDH of the internal expansion RAM with the main program After the main program is started the fetch address value and the values set in CORADO and CORAD1 always compared by the comparator in the ROM correction circuit When these values match the correction branch request signal is generated Simultaneously the corresponding correction status flag CORSTO or CORST1 is set to 1 Branch to the address F7FDH by the correction branch request signal Branch to the internal expansion RAM address set with the main program by the entire space branch instruction of the address F7FDH When one place is corrected the correction program is executed When two places are corrected the correction status flag is checked with the branch destination judgment program and branches to the correction program 541 CHAPTER 25 ROM CORRECTION 542 Figure 25 7 ROM Correction Operation Internal ROM program start
344. elease Signal 486 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21 1 Basic Configuration of Interrupt Function 2 2 D External maskable interrupt except INTPO Internal Bus External Interrupt Mode Register INTMO INTM1 Vector Table Interrupt Edge aes Request Detector enerator Standby Release Signal E Software interrupt f Internal Bus Interrupt Priority Control 41 Tobis Request Circuit Generator Remark IF Interrupt request flag IE Interrupt enable flag ISP Inservice priority flag MK Interrupt mask flag PR Priority specify flag 487 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21 3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions Interrupt request flag register IFOL IFOH IF1L nterrupt mask flag register MKOL MKOH MK1L Priority specify flag register PROL PROH PR1L External interrupt mode register INTMO 1 Sampling clock select register SCS Program status word PSW Table 21 2 gives a listing of interrupt request flags interrupt mask flags and priority specify flags corresponding to interrupt request sources Table 21 2 Various Flags Corresponding to Interrupt Request Sources Interrupt Source Interrupt Request Flag Interrupt Mask Flag Priority Specify Flag Register Register Register I
345. emory Addressing uPD78056 78056Y sse 106 5 15 Data Memory Addressing uPD78058 78058Y sse enne 107 5 16 Data Memory Addressing uPD78P058 78PO58Y a 108 5 17 Program Counter Configuration nennen nnne nennen tentent entente 109 5 18 Program Status Word Configuration u 109 5 19 Stack Pointer Config lation cincti i cde a daca 111 5 20 Data to be Saved to Stack Memory sse nennen nennen nhe nnne nnne 111 5 21 Data to be Reset from Stack Memory a 111 5 22 General Register Configuration eene nnne nennen nnne nennen neni 113 6 1 Port Types s etti tate bere ah ak eet ecd pak Aoc tics 129 6 2 P00 and P07 Block Diagram enean ett EE E ERR ER EC RES 135 6 3 PO1 to P06 Block Diagram ieri ret recente tL e vr cel see e ten 135 6 4 P1010 P17 Block Diagram u 136 6 5 P20 P21 P23 to P26 Block Diagram pne qan aaa ani a a nai 137 6 6 P22and P27 Block Diagram uu p A eite e ED m D eet o ertt e dad uod 138 6 7 P20 P21 P283 to P26 Block Diagram inci eter cde 139 6 8 P22 and P27 Block Diagram er ete t EAR HER Hd et 140 6 9 P30 to P37 Block Diagram ebbe deeem o
346. ent counter See CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 AND 2 Watch timer This timer can set a flag every 0 5 sec and simultaneously generates interrupt requests at the preset time intervals See CHAPTER 10 WATCH TIMER Watchdog timer WDTM WDTM can perform the watchdog timer function or generate non maskable interrupt requests maskable interrupt requests and RESET at the preset time intervals See CHAPTER 11 WATCHDOG TIMER Clock output control circuit This circuit supplies other devices with the divided main system clock and the subsystem clock See CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Buzzer output control circuit This circuit outputs the buzzer frequency obtained by dividing the main system clock See CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 175 CHAPTER 8 16 BIT TIMER EVENT COUNTER Table 8 1 Timer Event Counter Operations Interval timer 16 bit Timer event Counter 2 channelsNote 3 8 bit Timer event Counters 1 and 2 2 channels Watch Timer 1 channelNote 1 Watchdog Timer 1 channelNote 2 External event counter EI Function Timer output 4 PWM output Pulse width measurement Square wave output One shot pulse output Interrupt source Test input Notes 1 Watch timer can perform both watch timer and interval timer functions at the same time 2 Watchdog timer can perform either the wat
347. ent Counters 1 and 2 CHAPTER 10 WATCH TIMER U u u u uu u u u u u 10 1 Watch Timer Functions 10 2 Watch Timer Configuration U U u u u u u u u u 10 3 Watch Timer Control Registers U u u u u 10 4 Watch Timer Operations U 10 47 Watch timer operation uu uuu uuu uuu RR hai nage eere 10 4 2 Interval tiier operatioh ai nennt CHAPTER 11 WATCHDOG TIMER U U eene nennen annt nnn u u u u 11 1 Watchdog Timer Functions u u u u u u J 11 2 Watchdog Timer Configuration U u u u u 11 3 Watchdog Timer Control Registers u u u u T 11 4 Watchdog Timer Operations u uu u u T 11 4 1 Watchdog timer 11 4 2 Interval timer operation unus un uuu ect dt tere R S qu CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT u
348. ents for users by request The PROM version devices which provide this service are called QTOP microcontrollers For details please consult an NEC sales representative 559 560 CHAPTER 27 INSTRUCTION SET This chapter describes each instruction set of the uPD78054 and 78054Y subseries as list table For details of its operation and operation code refer to the separate document 78K 0 Series User s Manual Instruction U12326E 561 CHAPTER 27 INSTRUCTION SET 27 1 Legends Used in Operation List 27 1 1 Operand identifiers and description methods Operands are described in Operand column of each instruction in accordance with the description method of the instruction operand identifier refer to the assembler specifications for detail When there are two or more description methods select one of them Alphabetic letters in capitals and symbols and are key words and must be described as they are Each symbol has the following meaning Immediate data specification Absolute address specification Relative address specification Indirect address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parentheses in the table below RO R1 R2 etc can be use
349. eption point Refer to Figure 18 10 b Transmission reception of the third byte is completed and transmit data 4 T4 is transferred from the buffer RAM to SIO1 When transmission of the fourth byte is completed the receive data 4 R4 is transferred from SIO1 to the buffer RAM and ADTP is decremented iii Completion of transmission reception Refer to Figure 18 10 c When transmission of the sixth byte is completed the receive data 6 R6 is transferred from SIO1 to the buffer RAM and the interrupt request flag CSIIF1 is set INTCSI1 generation Figure 18 10 Buffer RAM Operation in 6 Byte Transmission Reception in Basic Transmit Receive Mode 1 2 a Before transmission reception FADFH FAC5H Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 FACOH Transmit data 6 T6 419 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 420 Figure 18 10 Buffer RAM Operation in 6 Byte Transmission Reception in Basic Transmit Receive Mode 2 2 FADFH FAC5H FACOH FADFH FAC5H FACOH b 4th byte transmission reception Receive data 1 R1 Receive data 2 R2 Receive data 3 R3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 Receive data 4 R4 SIO1 c Completion of transmission reception Receive data 1 R1 Receive data 2 R2 Receive data 3 R3 Receiv
350. er SVA data in bus mode R W csiEo Serial Interface Channel 0 Operation Control Operation stopped Operation enabled Notes 1 Bit 6 COI is a read only bit 2 Can be used as P25 CMOS input output when used only for transmission 3 Be sure to set WUP to 0 when the 3 wire serial I O mode is selected Remark x don t care PMxx Port mode register Pxx Port output latch 357 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries b Serial bus interface control register SBIC SBIC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SBIC to 00H Symbol lt gt 0 5 4 lt 2 lt gt lt 0 gt Address After Reset R W 3 2 SBIC BSYE ACKT CMDD RELD CMDT RELT FF61H 00H R W R W ReLr When RELT 1 500 latch is set to 1 After 500 latch setting automatically cleared to 0 Also cleared to 0 when CSIEO 0 R W When CMDT 1 SOO latch is cleared to 0 After SOO latch clearance automatically cleared to 0 Also cleared to 0 when CSIEO 0 Remark CSIEO Bit 7 of serial operating mode register 0 CSIMO 358 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 2 Communication operation The 3 wire serial I O mode is used for data transmission reception in 8 bit units Bit wise data transmission reception is carried out in synchronization with the serial clock Shift operation of the serial I O shift register 0
351. erand laddr16 HL byte HL B HL C addr16 HL byte HL B HL C X C Note Exceptr A 573 CHAPTER 27 INSTRUCTION SET 2 16 bit instructions MOVW XCHW ADDW SUBW CMPW PUSH POP INCW DECW Second Operand laddri6 1st Operand Note Only when rp BC DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand sfr bit saddr bit PSW bit HL bit addr16 First Operand saddr bit 574 CHAPTER 27 INSTRUCTION SET 4 Call instructions branch instructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ econd Operand laddr16 laddri 1 addr5 addr16 First Operand Basic instruction Compound instruction 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP El DI HALT STOP 575 576 APPENDIX A DIFFERENCES BETWEEN 4PD78054 78054Y SUBSERIES AND uPD78058F 78058FY SUBSERIES Table 1 shows the major differences between the uPD78054 78054Y Subseries and uPD78058F 78058FY Subseries 577 APPENDIX DIFFERENCES BETWEEN 4 PD78054 78054Y SUBSERIES AND uPD78058F 78058FY SUBSERIES Table 1 Major differences between uPD78054 78054 Subseries and uPD78058F 78058FY Subseries Em Part Number EMI no
352. eration Multiply divide 8 bits x 8 bits 16 bits 8 bits Bit manipulate set reset test and Boolean operation BCD adjust etc port Total 69 CMOS input e CMOS I O 63 N ch open drain 4 A D converter 8 bit resolution x 8 channels D A converter 8 bit resolution x 2 channels Serial interface e 3 wire serial I O 2 wire serial bus mode selection possible 1 channel 3 wire serial I O mode Max 32 byte on chip auto transmit receive 1 channel 3 wire serial I O UART mode selectable 1 channel 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel Timer output Three outputs 14 bit PWM output enable 1 Clock output 19 5 kHz 39 1 kHz 78 1 kHz 156 kHz 313 kHz 625 kHz 1 25 MHz 2 5 MHz 5 0 MHz 5 0 MHz with main system clock 32 768 kHz 32 768 kHz with subsystem clock Buzzer output 1 2 kHz 2 4 kHz 4 9 kHz 9 8 kHz 5 0 MHz with main system clock Notes 1 The capacities of the internal PROM and the internal high speed RAM can be changed using the memory switching register IMS 2 The capacity of the internal expansion RAM can be changed using the internal expansion RAM size switching register IXS 57 CHAPTER 2 OUTLINE uPD78054Y Subseries Part Number Item uPD78052Y uPD78053Y wPD78054Y uPD78055Y uPD78056
353. eration of automatic data transmit receive function 2 Zero must be set in bits 5 and 6 3 To control the data transfer interval by means of automatic transmission reception with ADTI busy control refer to 18 4 3 4 a Busy control option is disabled Remarks 1 fxx 2 fx 3 fsck Serial clock frequency Main system clock frequency fx or fx 2 Main system clock oscillation frequency 402 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18 5 Automatic Data Transmit Receive Interval Specify Register Format 3 4 Symbol 6 Address After Reset R W 5 4 3 2 1 0 ADTI JADTM ADTI3 ADTI2 ADTI1 ADTIO FF6BH 00H R W ADTI7 Data Transfer Interval Control 0 No control of interval by ADTINote 1 1 Control of interval by ADTI ADTIO to ADTI4 Data Transfer Interval Specification fxx 2 5 MHz Operation 2 ADTI1 MinimumNote 2 MaximumNete 2 36 8 us 0 5 fsck 40 0 us 1 5 fsck 62 4 us 0 5 fsck 65 6us 1 5 fsck 88 0 us 0 5 fsck 91 2us 1 5 fsck 113 6 us 0 5 fsck 116 8 us 1 5 fsck 139 2 us 0 5 fsck 142 4 us 1 5 fsck 164 8 us 0 5 fsck 168 0 us 1 5 fsck 190 4 us 0 5 fsck 193 6 us 1 5 fsck Sy 216 0 us 0 5 219 2 us 1 5 fsck 241 6 us 0 5 fsck 244 8 us 1 5 fsck 267 2 us 0 5 fsck 270 4 us 1 5 fsck 292 8 us 0 5 fsck 296 0 us 1 5 fsck 318 4 us 0 5 fsck 321 6 us 1
354. erface channel 0 employs the following four modes Operation stop mode 3 wire serial I O mode 2 wire serial I O mode 12 Inter IC bus mode 1 2 3 342 Caution Do not switch the operation mode 3 wire serial I O 2 wire serial I O bus while the operation of serial interface channel 0 is enabled Stop the serial operation before switching the operation mode Operation stop mode This mode is used when serial transfer is not carried out Power consumption can be reduced 3 wire serial I O mode MSB LSB first selectable This mode is used for 8 bit data transfer using three lines one each for serial clock SCKO serial output SOO and serial input SIO This mode enables simultaneous transmission reception and therefore reduces the data transfer processing time The start bit of transferred 8 bit data is switchable between MSB and LSB so that devices can be connected regardless of their start bit recognition This mode should be used when connecting with peripheral I O devices or display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X XL 78K and 17K series 2 wire serial 1 mode MSB first This mode is used for 8 bit data transfer using two lines of serial clock SCKO and serial data bus SBO or SB1 This mode enables to cope with any one of the possible data transfer formats by controlling the SCKO level and the SBO or SB1 output
355. eriod up to the next transmission As the buffer RAM read is performed at the same time as CPU processing the maximum interval is dependent upon the CPU operation and the value of the automatic data transmit receive interval specify register ADTI see 5 Automatic data transmit receive interval 425 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18 15 Repeat Transmission Mode Flowchart Write transmit data in buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Software Execution Set the transmission reception operation interval time in ADTI Write any data to SIO1 Start trigger Write transmit data from buffer RAM to SIO1 Decrement pointer value Transmission operation Hardware Execution Pointer value 0 Reset ADTP ADTP Automatic data transmit receive address pointer ADTI Automatic data transmit receive interval specify register SIO1 Serial I O shift register 1 426 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6 byte transmission ARLD 1 RE 0 in repeat transmit mode buffer RAM operates as follows i Before transmission Refer to Figure 18 16 After any data has been written to serial I O shift register 1 SIO1 start trigger this data is not transferred transmit data 1 T1 is transferred from the buffer RAM to SIO1 When transmission of the first byte is completed automatic data transmit receive addres
356. ernal interrupt request input an external count clock input to the timer and crystal connection for subsystem clock oscillation INTPO to 6 INTPO to INTP6 are external interrupt request input pins which can specify valid edges rising edge falling edge and both rising and falling edges INTPO or INTP1 becomes a 16 bit timer event counter capture trigger signal input pin with a valid edge input b TIOO Pin for external count clock input to 16 bit timer event counter c TIO1 Pin for capture trigger signal to capture register CROO of 16 bit timer event counter d XT1 Crystal connect pin for subsystem clock oscillation 64 CHAPTER 3 PIN FUNCTION uPD78054 Subseries 3 2 2 P10 to P17 Port 1 These are 8 bit input output ports Besides serving as input output ports they function as an A D converter analog input The following operating modes can be specified in 1 bit units 1 2 Port mode These ports function as 8 bit input output ports They can be specified in 1 bit units as input or output ports with a port mode register 1 PM1 If used as input ports on chip pull up resistors can be used to these ports by defining the pull up resistor option register L PUOL Control mode These ports function as A D converter analog input pins ANIO to ANI7 The on chip pull up resistor is automatically disabled when the pins specified for analog input 3 2 3 P20 to P27 Port 2 These are 8 bit input o
357. es 32 Kbytes 40 Kbytes 48 Kbytes 56 Kbytes 60 Kbytes Setting prohibited RAMO Internal High Speed RAM Capacity Selection 512 bytes 1024 bytes Other than above Setting prohibited The IMS settings to give the same memory map as mask ROM versions are shown in Table 26 4 Table 26 4 Examples of Memory Size Switching Register Settings uPD78P058 Relevant Mask ROM Version IMS Setting LPD78052 78052Y 078053 78053Y LPD78054 78054Y 078055 78055Y uPD78056 78056Y 78058 78058Y 550 CHAPTER 26 uPD78P054 78P058 26 3 Internal Expansion RAM Size Switching Register The uPD78P058 allows users to define its internal expansion RAM size using the internal expansion RAM size switching register IXS so thatthe same memory mapping as that of a mask ROM version with a different size internal expansion RAM is possible The IXS is set by an 8 bit memory manipulation instruction RESET signal input sets IXS to OAH Figure 26 3 Internal Expansion RAM Size Switching Register Format After Reset PN Symbol 7 6 1 0 Address 5 4 3 2 IXS EZE USE SI IXRAM3 IXRAM2 IXRAM1 IXRAM0 FFF4H OAH w IXRAM2 IXRAM1 IXRAMO Internal extension RAM capacity selection 1 0 0 O bytes 0 1 0 1024 bytes Other than above Setting prohibited The value in the IXS that has the identical memory map to the mask RO
358. esistor string voltage tap and analog input is compared with a voltage comparator If the analog input is greater than 1 2 AVrero the MSB of SAR remains set If the input is smaller than 1 2 AVrero the MSB is reset 7 Next bit 6 of SAR is automatically set and the operation proceeds to the next comparison In this case the series resistor string voltage tap is selected according to the preset value of bit 7 as described below e Bit 7 1 3 4 e Bit 7 0 1 4 The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated with the result as follows Analog input voltage gt Voltage tap Bit 6 1 Analog input voltage lt Voltage tap Bit 6 0 8 Comparison of this sort continues up to bit 0 of SAR 9 Upon completion of the comparison of 8 bits any effective digital resultant value remains in SAR and the resultant value is transferred to and latched in the A D conversion result register ADCR At the same time the A D conversion termination interrupt request INTAD can also be generated 273 CHAPTER 14 A D CONVERTER Figure 14 6 A D Converter Basic Operation Conversion Time Sampling Time A D Converter Samplin A D Conversion Operation png Conversion SAR Undefined Result Conversion Result INTAD A D conversion operations are performed continuously until bit 7 CS of ADM is reset 0 by softwar
359. essing accesses a general register as an operand The general register accessed is specified by the register bank select flags RBSO and RBS1 and register specify code Rn or RPn in an instruction code Register addressing is carried out when an instruction with the following operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format r X A C B ED L H rp AX BC DE HL and can be described with function names X A C B E D L AX BC DE and HL as well as absolute names RO to R7 and RPO to RP3 Description example MOV A C when selecting C register as r Operation code 01100010 L Register specify code INCW DE when selecting DE register pair as rp Operation code 10000100 Register specify code 122 CHAPTER 5 CPU ARCHITECTURE 5 4 3 Direct addressing Function This addressing directly addresses the memory indicated by the immediate data in an instruction word Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting addr16 to FE00H Operation code 10001110 OP code 00000000 00H 11111110 Illustration OP code saddr16 low saddr16 high Memory 123 CHAPTER 5 CPU ARCHITECTURE 5 4 4 Short direct addressing Function The memory
360. evice from pin STB P23 Through this means the slave device can know the timing of the end of master data transmission Therefore even if there is noise in the serial clock and bit slippage occurs synchronization is maintained and bit slippage has no effect on transmission of the next byte In the case that the strobe control option is used the conditions shown below are necessary Set bit 5 ATE of serial operation mode register 1 CSIM1 at 1 Set bit 2 STRB of the auto data send and receive control register ADTC at 1 Normally busy control and strobe control are used simultaneously as handshake signals In this case together with output of the strobe signal from pin STB P23 pin BUSY P24 can be sampled and sending or receiving can wait while the busy signal is being input If strobe control is not carried out pin P23 STB can be used as a normal 1 0 port Operation timing when busy and strobe control are used is shown in Figure 18 21 Furthermore if strobe control is used the interrupt request flag CSIIF1 set when sending or receiving ends is set after the strobe signal is output CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18 21 Operation Timings when Using Busy amp Strobe Control Option BUSYO 0 SCK1 SO S STB BUSY CSIIF1 TRF 1 1 1 1 RUD EO CG AB mam musu SSES COCO EO CE GO ED GOR An Busy Input Clear Busy Input Va
361. evice to slave devices to initiate a serial transfer See section 17 4 5 Cautions on Use of 12 Bus Mode for details of the start condition output The start condition signal is detected by hardware incorporated in slave devices Figure 17 15 Start Condition b Address The 7 bits following the start condition signal are defined as an address The 7 bit address data is output by the master device to specify a specific slave from among those connected to the bus line Each slave device on the bus line must therefore have a different address Therefore after a slave device detects the start condition it compares the 7 bit address data received and the data of the slave address register SVA After the comparison only the slave device in which the data are a match becomes the communication partner and subsequently performs communication with the master device until the master device sends a start condition or stop condition signal Figure 17 16 Address SCL 1 2 3 4 5 6 7 Address c Transfer direction specification The 1 bit that follows the 7 bit address data will be sent from the master device and it is defined as the transfer direction specification bit If this bit is 0 it is the master device which will send data to the slave If it is 1 it is the slave device which will send data to the master Figure 17 17 Transfer Direction Specification SCL 1 2 3 4 5 6 7 8 A AA A A A Tran
362. f RXB is always set to O RXB is read with an 8 bit memory manipulation instruction It cannot be written to RXB value is FFH after RESET input Caution Since RXB and the transmit shift register TXS are allocated to the same address even if a write instruction to RXB is executed the value is written to TXS Transmission control circuit This circuit performs transmit operation control such as the addition of a start bit parity bit and stop bit to data written in the transmit shift register TXS in accordance with the contents set in the asynchronous serial interface mode register ASIM Reception control circuit This circuit controls receive operations in accordance with the contents set in the asynchronous serial interface mode register ASIM It also checks errors such as parity error during a receive operation and if an error is detected sets a value in the asynchronous serial interface status register ASIS in accordance with the error contents 443 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19 3 Serial Interface Channel 2 Control Registers Serial interface channel 2 is controlled by the following four registers Serial Operating Mode Register 2 CSIM2 Asynchronous Serial Interface Mode Register ASIM Asynchronous Serial Interface Status Register ASIS Baud Rate Generator Control Register BRGC 1 Serial operating mode register 2 CSIM2 This register is set when serial interface channel 2 is used in the 3
363. f CSIMO In this case the interrupt request signal INTCSIO is generated only when the slave address output by the master coincides with the value of SVA and it can be learned by this interrupt request that the master requests for communication If the bit 5 SIC of the interrupt timing specify register SINT is set to 1 the wake up function cannot be used even if WUP is set to 1 an interrupt request signal is generated when bus release is detected To use the wake up function clear SIC to 0 Further when SVA transmits data as master or slave device in the SBI or 2 wire serial I O mode errors be detected if any using SVA RESET input makes SVA undefined CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 3 4 5 6 7 SOO latch This latch holds SIO SBO P25 and SOO SB1 P26 pin levels It can be directly controlled also by software In the SBI mode this latch is set upon termination of the 8th serial clock Serial clock counter This counter counts the serial clocks to be output and input during transmission reception and to check whether 8 bit data has been transmitted received Serial clock control circuit This circuit controls serial clock supply to the serial I O shift register 0 5100 When the internal system clock is used the circuit also controls clock output to the 5 27 pin Interrupt request signal generator This circuit controls interrupt request signal generation It gener
364. f the 16 bit timer register TMO TMO continues counting overflows and then starts counting again from 0 If the new value of CROO is less than the old value the timer must be restarted after changing the value of CROO 2 Capture compare register 01 CRO1 CR01 is a 16 bit register which has the functions of both a capture register and a compare register Whether itis used as a capture register or a compare register is set by bit 2 2 of capture compare control register 0 When CR01 is used as a compare register the value set in the 01 is constantly compared with the 16 bit timer register count value and an interrupt request INTTMO1 is generated if they match When CR01 is used as a capture register it is possible to select the valid edge of the INTPO TIOO pin as the capture trigger The INTPO TIOO valid edge is set by means of external interrupt mode register O INTMO CR01 is set with a 16 bit memory manipulation instruction After RESET input the value of 01 is undefined 181 CHAPTER 8 16 BIT TIMER EVENT COUNTER Caution If the valid edge of the 0 00 pin is input while CRO1 is read CRO1 does not perform the capture operation and retains the current data However the interrupt request flag PIFO is set 3 16 bit timer register TMO 8 4 TMO is a 16 bit register which counts the count pulses TMO is read by a 16 bit memory manipulation instruction When TMO is read capture compare
365. fceu selected by the processor clock control register PCC 2 This clock cycle applies to internal ROM program 3 n is the number of waits when external memory expansion area is read from 4 m is the number of waits when external memory expansion area is written to 565 27 INSTRUCTION SET Instruction Group Mnemonic Operands A byte Operation A CY A byte saddr byte saddr CY lt saddr A r CY A r CY r A A saddr A CY lt A saddr A laddr 6 A CY lt A addr16 A HL A CY lt A HL byte A HL byte A HL B A CY A HL A CY A HL A HL C A CY A HL C A byte A CY A byte CY saddr byte saddr CY lt saddr A r A CY A r CY CY r A CY A saddr A CY saddr A laddr 6 QI NI N II N GO N N N N CYe A A HL A CY A HL A CY lt A HL byte A HL byte A HL B A CY HL A HL C A CY A HL C A byte A byte saddr byte saddr saddr byte A saddr A saddr A laddr 6
366. fx 400 ns 22 x 1 fx 800 ns MCS 1 29 x 1 fx 102 4 us MCS 0 210 x 4 fx 204 8 us MCS 1 2 x 1 fx 400 ns MCS 0 22 x 1 fx 800 ns 22 x 1 fx 800 ns 23 x 1 fx 1 6 us 210 x 1 fx 204 8 us 211 x 1 fx 409 6 us 2 x 1 fx 800 ns 23 x 1 fx 1 6 us 23 x 1 fx 1 6 us 24 x 1 fx 3 2 us 211 x 1 fx 409 6 us 212 x 1 fx 819 2 us 23 x 1 fx 1 6 us 24 x 1 fx 3 2 us 24 x 1 fx 3 2 us 25 x 1 fx 6 4 us 212 x 1 fx 819 2 us 213 x 1 fx 1 64 ms 24 x 1 fx 3 2 us 25 x 1 fx 6 4 us 25 x 1 fx 6 4 us 26 x 1 fx 12 8 us 213 x 1 fx 1 64 ms 214 x 1 fx 3 28 ms 25 x 1 fx 6 4 us 26 x 1 fx 12 8 us 26 x 1 fx 12 8 us 27 x 1 fx 25 6 us 214 x 1 fx 3 28 ms 215 x 1 fx 6 55 ms 26 x 1 fx 12 8 us 27 x 1 fx 25 6 us 2 x 1 fx 25 6 us 28 x 1 fx 51 2 us 215 x 1 fx 6 55 ms 216 x 1 fx 13 1 ms 2 x 1 fx 25 6 us 28 x 1 fx 51 2 us 28 x 1 fx 51 2 us 29 x 1 fx 102 4 us 216 x 1 fx 13 1 ms 217 x 1 fx 26 2 ms 28 x 1 fx 51 2 us 29 x 1 fx 102 4 us 29 x 1 fx 102 4 us 210 x 1 fx 204 8 us 217 x 1 fx 26 2 ms 218 x 1 fx 52 4 ms 29 x 1 fx 102 4 us 210 x 1 fx 204 8 us 211 x 1 fx 409 6 us Remarks 1 2 MCS Oscillation mode selection register OSMS bit 0 3 Values in parentheses when
367. fxx 5 0 MHz Operation fxx 2 4 19 MHz Operation fxr 2 32 768 kHz Operation 2 tw 0 4 sec 2 4 fw 0 5 sec 2 fw 0 5 sec 2 3 fw 0 2 sec 2 3 fw 0 25 sec 2 3 fw 0 25 sec Prescaler Interval Time Selection TMC25 fxx 5 0 MHz Operation fxx 2 4 19 MHz Operation 32 768 kHz Operation 2 fw 410 us 2 fw 488 us 2 fw 488 us 2 fw 819 us 2 fw 977 us 2 fw 977 us 2 fw 1 64 ms 2 fw 1 95 ms 2 fw 1 95 ms 2 fw 3 28 ms 2 fw 3 91 ms 2 fw 3 91 ms 2 fw 6 55 ms 2 fw 7 81 ms 2 fw 7 81 ms 2 fw 13 1 ms 2 fw 15 6 ms 2 fw 15 6 ms Other than above Setting prohibited Caution When the watch timer is used the prescaler should not be cleared frequently Remarks 1 fw Watch timer clock frequency fxx 27 or fxr 2 fxx Main system clock frequency fx or fx 2 3 fx Main system clock oscillation frequency 4 fxr Subsystem clock oscillation frequency 245 CHAPTER 10 WATCH TIMER 10 4 Watch Timer Operations 10 4 1 Watch timer operation When the 32 768 kHz subsystem clock or 4 19 MHz main system clock is used the timer operates as a watch timer with a 0 5 second or 0 25 second interval The watch timer sets the test input flag WTIF to 1 at the constant time interval The standby state STOP mode HALT mode can be cleared by setting WTIF to 1 When bit 2 TMC22 of the watch timer mode control register TMC2
368. fxx 2 fx 2 156 kHz 78 1 kHz fxx 2 fx 2 78 1 kHz 39 1 kHz fxx 2 fx 2 39 1 kHz 19 5 kHz Setting prohibited 16 Bit Timer Register Count Clock Selection MCS 1 100 Valid edge specifiable 2fxx Setting prohibited 5 0 MHz fix fx 5 0 MHz 2 5 MHz fux 2 fx 2 2 5 MHz 1 25 MHz fxx 2 fx 2 1 25 MHz 625 kHz Watch timer output INTTM 3 Setting prohibited Cautions 1 The TIOO INTPO pin valid edge is set by external interrupt mode register 0 INTMO and the sampling clock frequency is selected by the sampling clock selection register SCS 2 When enabling PCL output set TCL00 to TCL03 then set 1 in CLOE with a 1 bit memory manipulation instruction 3 To read the count value when TIOO has been specified as the TMO count clock the value should be read from TMO not from 16 bit capture compare register 01 CRO1 4 When rewriting TCLO to other data stop the timer operation beforehand 183 CHAPTER 8 16 BIT TIMER EVENT COUNTER Remarks 1 fxx Main system clock frequency fx or fx 2 2 fx Main system clock oscillation frequency 3 fxr Subsystem clock oscillation frequency 4 TIOO 16 bit timer event counter input pin 5 TMO 16 bit timer register 6 MCS Bit 0 of oscillation mode selection register OSMS 7 Figures in parentheses apply to operation with fx 5 0 MHz of fxr 32 768 kHz 2 16 bit timer
369. g X Lower Address X Address Read Data X Higher Address NN CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22 6 External Memory Write Timing a No wait PW1 PWO 0 0 setting ASTB N WR N Hi Z ADO AD7 Lower Address gt Write Data A8 A15 Higher Address b Wait PW1 PWO 0 1 setting ASTB SS ADO AD7 _________ owe Address Write Data A8 A15 Higher Address Internal Wait Signal 7 7 7 7 7 7 7 et977 XU TON IS ur EIUS 1 clock wait A8 A15 X Higher Address i X WAIT 521 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION ASTB RD WR ADO AD7 A8 A15 ASTB RD WR ADO AD7 A8 A15 Internal Wait Signal 1 clock wait ASTB RD WR ADO AD7 A8 A15 WAIT 522 Figure 22 7 External Memory Read Modify Write Timing a No wait PW1 PWO 0 0 setting S X ___ 2 sls G U 7 Lower Address Read Data Write Data Higher Address b Wait PW1 PWO 0 1 setting Read Data Hig Write Data Higher Address c External wait PW1 PWO 1 1 setting NENNEN 2 E e S X Lower Address XK Read Data ye R Write Data X x i Higher Address 3 X CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22 4 Example of Connection with Memory This section provides uPD78054 and external memory connection examples in Figure 22 8 SRAMs are used as the external memory in t
370. ge signal output Continued Note Bits 2 3 and 6 RELD CMDD and ACKD are read only bits Remarks 1 Bits 0 1 and 4 RELT CMDT and ACKT are 0 when read after data setting 2 CSIEO Bit 7 of serial operating mode register 0 CSIMO 316 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries R ACKD Acknowledge Detection Clear Conditions 0 Set Conditions ACKD 1 SCKO fall immediately after the busy mode is When acknowledge signal ACK is detected at the released during the transfer start instruction execution rising edge of SCKO clock after completion of When CSIE0 0 transfer When RESET input is applied R W Synchronizing Busy Signal Output Control Disables busy signal which is output in synchronization with the falling edge of SCKO clock just after execution of the instruction to be cleared to 0 sets READY status Outputs busy signal at the falling edge of SCKO clock following the acknowledge signal Note Busy mode can be cleared by start of serial interface transfer However BSYE flag is not cleared to 0 Remark CSIEO Bit 7 of serial operating mode register 0 CSIMO 317 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries c Interrupt timing specify register SINT SINT is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SINT to 00H Symbol 6 5 4 Address After Reset R W o eo se m o o o e
371. gger a 16 bit timer mode control register TMCO 03 02 01 OVFO SE EE Clear amp start with valid edge of TI00 P00 pin b Capture compare control register 0 CRCO CRC02 CRCO1 CRCOO CR00 set as compare register CR01 set as compare register c 16 bit timer output control register TOCO OSPT OSPE TOCO4 LVSO LVRO TOCO1 TOEO TOO Output Enabled Inversion of output on match of and CROO Specified TOO output F F initial value Inversion of output on match of and CRO1 One shot pulse output mode Remark 0 1 Setting O or 1 allows another function to be used simultaneously with one shot pulse output See the description of the respective control registers for details Caution Values in the following range should be set in CROO and 01 0000H lt CRO1 lt CROO lt FFFFH 210 CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 34 Timing of One Shot Pulse Output Operation Using External Trigger With Rising Edge Specified Set 08H to TMCO TMO count start TMO Count Value 0000 X N Ke vex Xwczxue X M ez 100 Pin Input SS V T INTTM01 5 5 INTTM00 V x Y P F o TOO Pin Output F al Caution The 16 bit timer register starts operation at the moment a value other t
372. gister 0 CRCO as shown in Figure 8 16 allows operation as PPG Programmable Pulse Generator output In the PPG output operation square waves are output from the TO0 P30 pin with the pulse width and the cycle that correspond to the count values set beforehand in 16 bit capture compare register 01 01 and in 16 bit capture compare register 00 CROO respectively Figure 8 16 Control Register Settings for PPG Output Operation a 16 bit timer mode control register TMCO 03 02 01 OVFO mu Clear amp start on match of CROO b Capture compare control register 0 CRCO CRC02 CRC01 00 cc ERES KONETI ESE CR00 set as compare register CR01 set as compare register c 16 bit timer output control register TOC0 OSPT OSPE TOC04 1 50 LVRO 1 TOEO TOO Output Enabled Inversion of output on match of TMO and CROO Specified TOO output F F initial value Inversion of output on match of TMO and CRO1 One shot pulse output disabled Caution Values in the following range should be set in CR00 and CR01 0000H lt CR01 lt CR00 lt FFFFH Remark x Don t care 196 CHAPTER 8 16 TIMER EVENT COUNTER 8 5 4 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TIOO POO pin and TIO1 PO1 pin using the 16 bit timer register TMO There are two measurement methods measuring with TMO u
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374. granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document
375. gt Count Clock Tuo Count Value Kooor X X po YX coor Kor X X X X be X999 X TIOO Pin Input 7122 CROCapuedVaue CR00 Captured Value INTPO D2 xt 203 CHAPTER 8 16 TIMER EVENT COUNTER 8 5 5 External event counter operation The external event counter counts the number of external clock pulses to be input to the 00 00 pin with the 16 bit timer register TMO TMO is incremented each time the valid edge specified with the external interrupt mode register 0 INTMO is input When the TMO counted value matches the 16 bit capture compare register 00 CROO value TMO is cleared to 0 and the interrupt request signal INTTMOO is generated Set the value other than 0000H to CROO 1 pulse count operation cannot be performed The rising edge the falling edge or both edges can be selected with bits 2 and 3 ES10 and ES11 of INTMO Because operation is carried out only after the valid edge is detected twice by sampling at the interval selected with the sampling clock select register SCS noise with short pulse widths can be removed Figure 8 26 Control Register Settings in External Event Counter Mode a 16 bit timer mode control register TMCO 03 02 01 OVFO L b Capture compare control register 0 CRCO Clear amp start with match of TMO and CROO
376. guration The buzzer output control circuit consists of the following hardware Table 13 1 Buzzer Output Control Circuit Configuration i Timer clock select register 2 TCL2 Control register Port mode register 3 PM3 Figure 13 1 Buzzer Output Control Circuit Block Diagram x2 ie BUZ P36 fxx 29 Selector fxx 2 PM36 Port Mode Register 3 P36 Output Latch 5 Internal Bus 1 27 26 TCL25 Timer Clock Select Register 2 261 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13 3 Buzzer Output Function Control Registers The following two types of registers are used to control the buzzer output function Timer clock select register 2 TCL2 Port mode register 3 PM3 1 Timer clock select register 2 TCL2 This register sets the buzzer output frequency TCL2 is set with an 8 bit memory manipulation instruction RESET input sets TCL2 to 00H Remark Besides setting the buzzer output frequency TCL2 sets the watch timer count clock and the watchdog timer count clock 262 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT Symbol 7 6 3 2 1 0 TCL2 TCL27 TCL26 TCL25 TCL24 TCL22TCL21 TCL20 FF42H 00H R W TCL21 Figure 13 2 Timer Clock Select Register 2 Format After Reset 5 4 Address R W Watchdog Timer Count Clock Selection MCS 1 23 625 kHz fx 2 313 kHz fx 2 813 kHz fx 2
377. h the rising edge of SCL 9 Start of transfer 378 A serial transfer is started by setting transfer data in serial I O shift register 0 SIOO if the following two conditions have been satisfied The serial interface channel 0 operation control bit CSIEO 1 After an 8 bit serial transfer the internal serial clock is stopped or SCL is low Cautions 1 Be sure to set CSIEO to 1 before writing data in SIOO Setting CSIEO to 1 after writing data in SIOO does not initiate transfer operation 2 Because the N ch open drain output must be high impedance state during data reception set bit 7 BSYE of serial bus interface control register SBIC to 1 before writing FFH to 5100 Do not write to 5100 before reception when the wake up function is used by setting the bit 5 WUP of the serial operating mode register 0 CSIMO Even if FFH is not written to SIOO the N ch open drain output is always in high impedance state 3 If data is written to 5100 while the slave is in the wait state that data is held The transfer is started when SCL is output after the wait state is cleared When an 8 bit data transfer ends serial transfer is stopped automatically and the interrupt request flag CSIIFO is set CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries Figure 17 22 Data Transmission from Master to Slave Both Master and Slave Selected 9 Clock Wait 1 of 3 a Start Condition to Address Master device opera
378. han 0 0 0 operation stop mode is set to TMC01 to TMC03 respectively 211 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 6 16 Bit Timer Event Counter Operating Precautions 1 2 3 Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start This is because the 16 bit timer register TMO starts asynchronously with the count pulse Figure 8 35 16 Bit Timer Register Start Timing Count Pulse Ne S Count Value 0000H 0001H 0002H 0003H 0004H Timer Start 16 bit compare register setting Set a value other than 0000H to the 16 bit capture compare register 00 CROO Thus when using the 16 bit capture compare register as event counter one pulse count operation cannot be carried out Operation after compare register change during timer count operation If the value after the 16 bit capture compare register CR00 is changed is smaller than that of the 16 bit timer register TMO TMO continues counting overflows and then restarts counting from 0 Thus if the value M after CROO change is smaller than that N before change it is necessary to restart the timer after changing CR00 Figure 8 36 Timings After Change of Compare Register During Timer Count Operation E ge SP rove UMP CN CR00 N X M Count Value X X X d FFFFH 0000H 0001H 0002H 212 Remark gt gt CHAPT
379. he slave address received after bus release RELD 1 For this match detection match interrupt request INTCSIO of the address to be generated with WUP 1 is normally used Thus execute selection non selection detection by slave address when WUP 1 2 When detecting selection non selection without the use of interrupt request with WUP z0 dosoby means of transmission reception of the command preset by program instead of using the address match detection method Error detection In the SBI mode the serial bus SBO SB1 status being transmitted is fetched into the destination device that is the serial I O shift register 0 5100 Thus transmit errors can be detected in the following way a Method of comparing SIOO data before transmission to that after transmission In this case if two data differ from each other a transmit error is judged to have occurred b Method of using the slave address register SVA Transmit data is set to both SIOO and SVA and is transmitted After termination of transmission COI bit match signal coming from the address comparator of the serial operating mode register 0 CSIMO is tested If 1 normal transmission is judged to have been carried out If 0 a transmit error is judged to have occurred Communication operation In the SBI mode the master device selects normally one slave device as communication target from among two or more devices by outputting an address to the serial bus
380. he slave device has been selected After that communication with the master device continues until a release instruction is received from the master device Figure 16 15 Slave Selection with Address J Slave 1 Not selected Slave 2 address transmission Slave 2 Selected Slave 3 Not selected Slave 4 Not selected 311 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 312 d Command and data The master device transmits commands to and transmits receives data to from the slave device selected by address transmission Figure 16 16 Commands SEKO 1 2 3 4 5 6 7 8 SBO 5 1 S Command Signal Command Figure 16 17 Data SEKD 1 2 3 4 5 6 7 8 RU 27 D6 D5 X D4 X D3 D2 X D1 A DO Data 8 bit data following a command signal is defined as command data 8 bit data without command signal is defined as data Command and data operation procedures are allowed to determine by user according to communications specifications CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries e Acknowledge signal ACK The acknowledge signal is used to check serial data reception between transmitter and receiver Figure 16 18 Acknowledge Signal When output in synchronization with 11th clock SCKO SCK0 er ler Hop 11 When output in synchronization with 9th clock SCKO SMS erp E EI sess X X XC X C C C AA 00 Remark The dotted line indicates READY status The ackno
381. hen the SCKO line is at the high level without serial clock output This signal is output by the master device Figure 16 13 Command Signal A command signal indicates that the master is to transmit a command to a slave however the command signal following a bus release signal indicates that the master is to transmit an address The slave device incorporates hardware to detect the command signal Caution A transition of the SBO SB1 pin from low to high while the SCKO line is high is interpreted as a command signal Therefore a shift in the change timing of the bus due to the influence of the board capacitance etc may be incorrectly identified as a command signal regardless of whether data is being transmitted For this reason special care must be taken regarding wiring CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries c Address An address is 8 bit data which the master device outputs to the slave device connected to the bus line in order to select a particular slave device Figure 16 14 Addresses SCKO 1 2 3 4 5 6 7 8 SBO SB1 A7 XAG X A5 A A4 X AB A A2 gt v Address Bus Release Signal Command Signal 8 bit data following bus release and command signals is defined as an address In the slave device this condition is detected by hardware and whether or not 8 bit data matches the own specification number slave address is checked by hardware If the 8 bit data matches the slave address t
382. hese diagrams In addition the external device expansion function is used in the full address mode and the address from 0000H to 7FFFH 32 Kbytes are allocated for internal ROM and the addresses after 8000H for SRAM Figure 22 8 Connection Example of uPD78054 and Memory uPD78054 43256 25 4 i i 55 Data WE Bus l O1 l O8 0 14 Address uPD74HC573 Bus ADO AD7 523 524 CHAPTER 23 STANDBY FUNCTION 23 1 Standby Function and Configuration 23 1 1 Standby function The standby function is designed to decrease power consumption of the system The following two modes are available 1 2 HALT mode HALT instruction execution sets the HALT mode The HALT mode is intended to stop the CPU operation clock System clock oscillator continues oscillation In this mode current consumption cannot be decreased as in the STOP mode The HALT mode is valid to restart immediately upon interrupt request and to carry out intermittent operations such as in watch applications STOP mode STOP instruction execution sets the STOP mode In the STOP mode the main system clock oscillator stops and the whole system stops CPU current consumption can be considerably decreased Data memory low voltage hold down to Vpp 1 8 V is possible Thus the STOP mode is effective to hold data memory contents with ultra low current consumption Because
383. icates READY status The bus release signal and the command signal are output by the master device BUSY is output by the slave signal ACK can be output by either the master or slave device normally the 8 bit data receiver outputs Serial clocks continue to be output by the master device from 8 bit data transfer start to BUSY reset 309 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 310 a b Bus release signal REL The bus release signal is a signal with the SBO SB1 line which has changed from the low level to the high level when the line is at the high level without serial clock output This signal is output by the master device Figure 16 12 Bus Release Signal SCKO H SB0 SB1 Caution A transition of the SB0 SB1 pin from low to high while the SCK0 line is high is interpreted as a bus release signal Therefore a shift in the change timing of the bus due to the influence of the board capacitance etc may be incorrectly identified as a bus release signal regardless of whether data is being transmitted For this reason special care must be taken regarding wiring The bus release signal indicates that the master device is going to transmit an address to the slave device The slave device incorporates hardware to detect the bus release signal Command signal CMD The command signal is a signal with the SBO SB1 line which has changed from the high level to the low level w
384. ified in 1 bit units 2 When used as input port an pull up resistor can be used by software PCL BUZ Port 4 8 bit input output port P40 to P47 Input output mode can be specified in 8 bit units ADO to AD7 When used as an input port an on chip pull up resistor can be used by software Test input flag KRIF is set to 1 by falling edge detection Port 5 8 bit input output port P50 to P57 LED can be driven directly A8 to A15 Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software 132 CHAPTER 6 PORT FUNCTIONS P63 Table 6 2 Port Functions uPD78054Y subseries 2 2 Function N ch open drain input output port On chip pull up resistor can be specified by mask option Mask ROM version only 8 bit input output port LEDs can be driven directly Alternate Function Input output mode can be specified in 1 bit When used as an input port an on chip pull up resistor can be used by software ASTB 3 bit input output port Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software SI2 RxD SO2 TxD SCK2 ASCK P120 to P127 Port 12 8 bit input output port Input output mode can be specified in 1 bit units When used as an input port on chip pull up resistor can be used by software RTPO to RTP7
385. ignal is detected at the rising edge of SCL clock after completion of transfer BSYE Control of N ch Open Drain Output for Transmission in Bus ModeNete 4 Note 3 0 Output enabled transmission 1 Output disabled reception Remark 374 This setting must be performed prior to transfer start In the 8 clock wait mode use ACKT for output of the acknowledge signal after normal data reception The busy mode can be released by the start of a serial interface transfer or reception of an address signal However the BSYE flag is not cleared When using the wake up function be sure to set BSYE to 1 CSIEO Bit 7 of serial operating mode register 0 CSIMO CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries c Interrupt timing specification register SINT SINT is set by the 1 bit or 8 bit memory manipulation instruction RESET input sets SINT to 00H Symbol Address After Reset R W rums em n WAT1 WATO Interrupt control by wait See Note 2 Interrupt service request is generated on rise of 8th SCKO clock cycle clock output is high impedance Setting prohibited Used 12C bus mode 8 clock wait Generates an interrupt service request on rise of 8th SCL clock cycle In case of master device SCL pin is driven low after output of 8 clock cycles to enter the wait state In case of slave device SCL pin is driven low after input of 8 clock cycles to require the wait state
386. imer operations Count Value 9 XNXoX9 X XX A 228 The 8 bit timer event counters 1 and 2 operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset to 8 bit compare registers 10 and 20 CR10 and CR20 When the count values of the 8 bit timer registers 1 and 2 TM1 and TM2 match the values set to CR10 and CR20 counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signals INTTM1 and INTTM2 are generated Count clock of TM1 can be selected with bits 0 to TCL10 to TCL13 of the timer clock select register 1 TCL1 Count clock of TM2 can be selected with bits 4 to 7 TCL14 to TCL17 of the timer clock select register 1 TCL1 For the operation when the value of the compare register is changed during the timer count operation refer to 9 5 8 Bit Timer Event Counter Precautions 3 Figure 9 8 Interval Timer Operation Timings rot i 3 1 Count Clock op li Count Start Clear Clear A A iInterrupt Request Acknowledge i Interrupt Request Acknowledge r die t L i Interval Time i Interval Time Interval Time 1 i Remark Interval time N 1 x t N 00H to FFH CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 AND 2 Table 9 6 8 Bit Timer Event Counter 1 Interval Time Minimum Interval Time Maximum Interval Time Resolution TCL12 TCL11 TCL10 TI1 inpu
387. in output status is reversed at intervals of the count value preset to CR10 and CR20 by setting bit 4 TOE2 ofthe 8 bit timer output control register TOC1 to 1 This enables a square wave with any selected frequency to be output Table 9 10 Square Wave Output Ranges when 2 Channel 8 Bit Timer Event Counters Minimum Pulse Width Maximum Pulse Width TM1 and TM2 are Used as 16 Bit Timer Event Counter Resolution 2 x 1 fx 400 ns 22 x 1 fx 800 ns MCS 1 217 x 1 fx 26 2 ms MCS 0 218 x 1 fx 52 4 ms MCS 1 2 x 1 fx 400 ns MCS 0 22 x 1 fx 800 ns 2 x 1 fx 800 ns 23 x 1 fx 1 6 us 218 x 1 fx 52 4 ms 219 x 1 fx 104 9 ms 2 x 1 fx 800 ns 23 x 1 fx 1 6 us 23 x 1 fx 1 6 us 24 x 1 fx 3 2 us 219 x 1 fx 104 9 ms 220 x 1 fx 209 7 ms 23 x 1 fx 1 6 us 24 x 1 fx 3 2 us 24 x 1 fx 3 2 us 25 x 1 fx 6 4 us 220 x 1 fx 209 7 ms 221 x 1 fx 419 4 ms 24 x 1 fx 3 2 us 25 x 1 fx 6 4 us 25 x 1 fx 6 4 us 26 x 1 fx 12 8 us 221 x 1 fx 419 4 ms 222 x 1 fx 838 9 ms 25 x 1 fx 6 4 us 26 x 1 fx 12 8 us 26 x 1 fx 12 8 us 27 x 1 fx 25 6 us 222 x 1 fx 838 9 ms 223 x 1 fx 1 7 s 26 x 1 fx 12 8 us 27 x 1 fx 25 6 us 27 x 1 fx 25 6 us 28 x 1 fx 51 2 us 223 x 1 fx 1 7 s 224 x 1 fx 3 4 s 2 x 1 fx 25 6 us 28 x 1 fx 51 2
388. ing as the start bit can be specified with bit 2 CSIMO2 of the serial operating mode register 0 CSIMO Figure 17 9 Circuit of Switching in Transfer Bit Order 7 6 Internal Bus 4 ass 1 7 0 e LSB first MSB first Read Write Gate Read Write Gate 500 Latch 510 Serial Shift Register 0 5100 L4 Ld 500 lt SCK0 Start bit switching is realized by switching the bit order for data write to SIO0 The SIOO shift order remains unchanged Thus switching between MSB first and LSB first must be performed before writing data to SIOO Transfer start Serial transfer is started by setting transfer data to the serial I O shift register 0 SIOO when the following two conditions are satisfied Serial interface channel 0 operation control bit CSIEO 1 Internal serial clock is stopped or SCKO is a high level after 8 bit serial transfer Caution If CSIEO is set to 1 after data write to SIOO transfer does not start Upon termination of 8 bit transfer serial transfer automatically stops and the interrupt request flag CSIIFO is set CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 17 4 3 2 wire serial I O mode operation The 2 wire serial mode can cope with any communicatio
389. input to ASCK pin k Value set in MDLO to MDL3 0 lt k x 14 Table 19 4 Relation between ASCK Pin Input Frequency and Baud Rate When BRGC is set to 00H Baud Rate bps ASCK Pin Input Frequency 2 4 kHz 3 52 kHz 4 8 kHz 9 6 kHz 19 2 kHz 38 4 kHz 76 8 kHz 153 6 kHz 307 2 kHz 614 4 kHz 1000 0 kHz 1228 8 kHz 451 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19 4 Serial Interface Channel 2 Operation Serial interface channel 2 has the following three modes Operation stop mode Asynchronous serial interface UART mode 3 wire serial mode 19 4 1 Operation stop mode In the operation stop mode serial transfer is not performed and therefore power consumption can be reduced In the operation stop mode the P70 SI2 RxD P71 SO2 TxD and P72 SCK2 ASCK pins can be used as normal input output ports 1 Register setting Operation stop mode settings are performed using serial operating mode register 2 CSIM2 and the asynchronous serial interface mode register ASIM a Serial operating mode register 2 CSIM2 CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to OOH 5 4 3 2 1 0 CSIM eee Symbol lt 7 gt 6 Address After Reset R W CSIM2 FF72H 00H R W CSIE2 Operation Control 3 wire Serial Mode 0 Operation stopped 1 Operation enabled Caution Ensure that bits 0
390. ion 456 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 d Baud rate generator control register BRGC BRGC is set with an 8 bit memory manipulation instruction RESET input sets BRGC to 00H Symbol 7 6 5 4 3 Address After Reset R W 2 1 0 BRGC TPS3 52 TPS1 50 MDL3 MDL2 MDL1 MDLO FF73H 00H R W MDLO Baud Rate Generator Input Clock Selection k fsck 16 fsck 17 18 19 fsck 20 fsck 21 fsck 22 fsck 23 fsck 24 NI O OQ AJOIN fsck 25 fsck 26 ae fsck 27 fsck 28 fsck 29 a 30 i A continued Remark fsck 5 bit counter source clock k Value set in MDLO to MDL3 0 lt k x 14 457 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 5 Bit Counter Source Clock Selection MCS 1 MCS 0 fxx 210 fx 210 4 9 kHz 2 4 kHz 5 0 MHz 2 5 MHz fxx 2 fx 2 2 5 MHz 22 fx 22 1 25 MHz 1 25 MHz 625 kHz fxx 23 fx 23 625 kHz 313 kHz fxx 24 fx 2 313 kHz 156 kHz 156 kHz 78 1 kHz fxx 25 fx 25 fxx 26 fx 26 78 1 kHz 39 1 kHz fxx 27 fx 27 39 1 kHz 19 5 kHz IN O A C N fxx 28 fx 28 19 5 kHz 9 8 kHz fxx 29 fx 29 9 8 kHz 4 9 kHz E Other than above Setting prohibited Caution When data is writ
391. ion Serial communication synchronization signal Signaled by Master Signaled when See Note 2 below Affected flag s CSIIFO Also see Note 3 below Address A6 to Definition 7 bit data synchronized with SCL immediately after start condition signal Function Indicates address value for specification of slave on serial bus Signaled by Master Signaled when See Note 2 below Affected flag s CSIIFO Also see Note 3 below Transfer direction R W Definition 1 bit data output in synchronization with SCL after address output Function Indicates whether data transmission or reception is to be performed Signaled by Master Signaled when See Note 2 below Affected flag s CSIIFO Also see Note 3 below Data D7 to DO Definition 8 bit data synchronized with SCL not immediately after start condition Function Contains data actually to be sent Signaled by Master or slave Signaled when See Note 2 below Affected flag s CSIIFO Also see Note 3 below Notes 1 The level of the serial clock can be controlled by CLC of interrupt timing specify register SINT 2 Execution of instruction to write data to SIOO when CSIEO 1 serial transfer start directive In the wait state the serial transfer operation will be started after the wait state is released 3 If the 8 clock wait is selected when WUP 0 CSI
392. ion is detected by match detection of the slave address received after bus release RELD 1 For this match detection match interrupt INTCSIO of the address to be generated with WUP 1 is normally used Thus execute selection non selection detection by slave address when WUP 1 When detecting selection non selection without the use of interrupt with WUP 0 do so by means of transmission reception of the command preset by program instead of using the address match detection method A transition of the SBO SB1 pin from low to high or high to low while the line is high is interpreted as a bus release or command signal Therefore a shift in the change timing of the bus due to the influence of the board capacitance etc may be incorrectly identified as a bus release signal or command signal regardless of whether data is being transmitted For this reason special care must be taken regarding wiring For pins which are to be used for data input output be sure to carry out the following settings before serial transfer of the 1st byte after RESET input lt gt Set the P25 and P26 output latches to 1 lt 2 gt Set bit 0 RELT of the serial bus interface control register SBIC to 1 lt 3 gt Reset the P25 and P26 output latches from 1 to 0 If SBO SB1 line changes from low level to high level or from high level to low level while SCKO line is high level it is recognized as a bus release signal or a command signal
393. is available by checking the WTIF flag using a shorter cycle than the watch timer overflow cycle 2 External test signal When a falling edge external test input signal is input to the port 4 P40 to P47 pins KRIF is set If not masked with bit 1 KRMK of key return mode register KRM at this time a standby release signal is generated If port 4 is used as key matrix return signal input whether or not a key input has been applied can be checked from the KRIF status 509 510 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22 1 External Device Expansion Functions The external device expansion functions connect external devices to areas other than the internal ROM RAM and SFR Connection of external devices uses ports 4 to 6 Ports 4 to 6 control address data read write strobe wait address strobe etc Table 22 1 Pin Functions in External Memory Expansion Mode Pin function at external device connection Alternate function Name Function ADO to AD7 A8 to A15 RD Read strobe signal P64 P40 to P47 Multiplexed address data bus Address bus P50 to P57 WR Write strobe signal P65 WAIT ASTB Wait signal P66 Address strobe signal P67 Table 22 2 State of Ports 4 to 6 Pins in External Memory Expansion Mode Ports and bits Single chip mode Port Port 256 byte expansion mode Address data WR WAIT ASTB 4K byte expansion mode Address data Address
394. is set 2 CSIEO Bit 7 of serial operating mode register 0 CSIMO CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries R W R Figure 17 5 Serial Bus Interface Control Register Format 2 2 Acknowledge Signal Output Control ete 1 Disables acknowledge signal automatic output However output with ACKT is enabled Used for reception when 8 clock wait mode is selected or for transmission Nete 2 Enables acknowledge signal automatic output Outputs acknowledge signal in synchronization with the falling edge of the 9th SCL clock cycle automatically output when 1 However not automatically cleared to 0 after acknowledge signal output Used in reception with 9 clock wait mode selected ACKD Acknowledge Detection Clear Conditions ACKD 0 Set Conditions ACKD 1 While executing the transfer start instruction When acknowledge signal ACK is detected at the When CSIEO 0 rising edge of SCL clock after completion of When RESET input is applied transfer Control of N ch Open Drain Output for Transmission 2 Bus Mode Output enabled transmission Output disabled reception Notes 1 Setting should be performed before transfer 2 If 8 clock wait mode is selected the acknowledge signal at reception time must be output using ACKT 3 The busy mode can be canceled by start of serial interface transfer or reception of address signal However the BSYE fl
395. is the PROM version for the uPD78055 78056 and 78058 3 The capacities of the internal PROM and the internal high speed RAM can be changed using the memory switching register IMS 4 The capacity of the internal expansion RAM can be changed using the internal expansion RAM size switching register IXS 46 CHAPTER 1 OUTLINE uPD78054 Subseries Part Number uPD78052 wPD78053 uPD78054 uPD78P054 uPD78055 uPD78056 uPD78058 uPD78P058 Item Note 1 Note2 Vectored Maskable Internal 13 External 7 interrupt Non maskable Internal 1 source Software 1 Test input Internal 1 External 1 Supply voltage 2 0 to 6 0 V Operating ambient temperature Ta 40 to 85 C Package 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 mm uPD78P054 only 80 pin plastic QFPNete 3 14 x 14 mm Resin thickness 1 4 mm 80 pin plastic TQFP Fine pitch 12 x 12 mm except uPD78P058 80 pin ceramic WQFN 14 x 14 mm uPD78P054 78P058 only Notes 1 The uPD78P054 is the PROM version for the uPD78052 78053 78054 2 The uPD78P058 is the PROM version for the 78055 78056 78058 3 The uPD78P054 is under development 47 CHAPTER 1 OUTLINE uPD78054 Subseries 1 9 Differences between Standard Quality Grade Products and A Products Table 1 1 shows the differences between the standard quality grade products uPD78052 78053 78054 and A products uPD78052 A 780
396. ise measure UPD78054 78054Y Subseries None UPD78058F 78058FY Subseries Provided PROM version uPD78P054 uPD78P058 uPD78P058Y uPD78P058F uPD78P058Y Supply voltage Vpp 2 0 to 6 0 V Vpp 2 7 to 6 0 V Internal ROM capacity HPD78052 16 Kbytes HPD78053 24 Kbytes HPD78054 32 Kbytes HPD78P054 32 Kbytes HPD78055 40 Kbytes HPD78056 48 Kbytes HPD78058 60 Kbytes HPD78P058 60 Kbytes UPD78056F 48 Kbytes UPD78058F 60 Kbytes Internal high speed RAM capacity HPD78052 512 bytes HPD78053 1024 bytes HPD78054 1024 bytes HPD78P054 1024 bytes HPD78055 1024 bytes HPD78056 1024 bytes HPD78058 1024 bytes HPD78P058 1024 bytes UPD78056F 1024 bytes UPD78058F 1024 bytes Internal expansion RAM capacity HPD78058 1024 bytes HPD78P058 1024 bytes UPD78058F 1024 bytes Voo Positive power supply including ports Positive power supply excluding ports Vss pin Ground potential including ports Ground potential excluding ports AVpo pin Analog power supply for A D converter D A converter Analog power supply for A D converter D A converter and power supply for ports AVss pin Ground for A D converter D A converter Ground for A D converter D A converter and ground for ports Package 80 pin plastic QFP 14 x 14 mm Resin thickness 2 7 mm 80 pin plastic QFP 14 x 14 mm Resin thickness 1 4 mm 80 pin plastic TQ
397. it units as input or output ports with port mode register 6 PM6 P60 to P63 are N ch open drain outputs Mask ROM version can contain pull up resistors with the mask option When P64 to P67 are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL Control mode These ports function as control signal output pins RD WR WAIT ASTB in external memory expansion mode When a pin is used as a control signal output the on chip pull up resistor is automatically disabled Caution When external wait is not used in external memory expansion mode P66 can be used as an input output port 83 CHAPTER 4 PIN FUNCTION uPD78054Y Subseries 4 2 8 P70 to P72 Port 7 This is a 3 bit input output port In addition to its use as an input output port it also has serial interface data input output and clock input output functions The following operating modes can be specified in 1 bit units 1 Port mode Port 7 functions as a 3 bit input output port 1 bit units specification as an input port or output port is possible by means of port mode register 7 PM7 When used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL 2 Control mode Port 7 functions as serial interface data input output and clock input output a SI2 SO2 Serial interface serial data input output pins b SCK2 Serial interface serial clock inp
398. it wise data transmission reception is carried out in synchronization with the serial clock Shift operation of the serial I O shift register 1 SIO1 is carried out at the falling edge of the serial clock SCK1 The transmit data is held in the SO1 latch and is output from the SO1 The receive data input to the 511 pin is latched into SIO1 at the rising edge of SCK1 Upon termination of 8 bit transfer the SIO1 operation stops automatically and the interrupt request flag CSIIF1 is set Figure 18 6 3 Wire Serial I O Mode Timings SCK1 SH 501 CSIIF1 End of Transfer L Transfer Start at the Falling Edge of SCK1 SIO1 Write Caution 501 pin becomes low level by SIO1 write 407 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 3 4 408 MSB LSB switching as the start bit The 3 wire serial mode enables to select transfer to start from MSB or LSB Figure 18 7 shows the configuration of the serial I O shift register 1 SIO1 and internal bus As shown in the figure MSB LSB can be read written in reverse form MSB LSB switching as the start bit can be specified with bit 6 DIR of the serial operating mode register 1 CSIM1 Figure 18 7 Circuit of Switching in Transfer Bit Order Internal Bus 4 ume a tee Ge DUX M m RID oe ae NUN a EL LSB first MSB first Read Write Gate e Read Write Gate SO1 Latch Sh Serial
399. ith a port mode register 0 PMO When they are used as input ports on chip pull up resistors can be used to them by defining the pull up resistor option register L PUOL 2 Control mode In this mode these ports function as an external interrupt request input an external count clock input to the timer and crystal connection for subsystem clock oscillation INTPO to 6 INTPO to INTP6 are external interrupt request input pins which can specify valid edges rising edge falling edge and both rising and falling edges INTPO or INTP1 becomes a 16 bit timer event counter capture trigger signal input pin with a valid edge input b TIOO Pin for external count clock input to 16 bit timer event counter c TIO1 Pin for capture trigger signal to capture register CROO of 16 bit timer event counter d XT1 Crystal connect pin for subsystem clock oscillation 80 CHAPTER 4 PIN FUNCTION uPD78054Y Subseries 4 2 2 P10 to P17 Port 1 These are 8 bit input output ports Besides serving as input output ports they function as an A D converter analog input The following operating modes can be specified in 1 bit units 1 2 Port mode These ports function as 8 bit input output ports They can be specified in 1 bit units as input or output ports with a port mode register 1 PM1 If used as input ports on chip pull up resistors can be used to these ports by defining the pull up resistor option register L PUOL
400. itten to ADM during A D conversion the A D conversion operation stops immediately Figure 14 8 A D Conversion by Hardware Start INTP3 u u u ADM Rewrite ADM Rewrite CS 1 TRG 1 CS 1 TRG 1 Standby Standby Standby A D Conversion ANIn ANIn State ANIn State ANIm ANIm ANIm S V Ret 3 gt y an INTAD Remarks 1 n 0 1 7 2 0 1 7 CHAPTER 14 A D CONVERTER 2 A D conversion operation in software start When bit 6 TRG and bit 7 CS of A D converter mode register ADM are set to 0 and 1 respectively the A D conversion starts on the voltage applied to the analog input pins specified with bits 1 to ADM1 to ADM3 of ADM Upon termination of the A D conversion the conversion result is stored in the A D conversion result register ADCR and the interrupt request signal INTAD is generated After one A D conversion operation is started and terminated the next A D conversion operation starts immediately The A D conversion operation continues repeatedly until new data is written to ADM If data with CS set to 1 is written to ADM again during A D conversion the converter suspends its A D conversion operation and starts A D conversion on the newly written data If data with CS set to 0 is written to ADM during A D conversion the A D conversion operation stops immediately Figure 14 9 A D Conversion by Software Start Conversion Start ADM Rewrite ADM Rewrite CS 1 TRG 0 C
401. l 7 6 5 4 3 2 1 0 ES71 ES70 ES61 ES60 ES51 ES50 541 ES40 Address FFEDH After Reset FUN 00H R W INTP3 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges Falling edge Rising edge Setting prohibited Both falling and rising edges Falling edge Rising edge Setting prohibited Both falling and rising edges Falling edge Rising edge Setting prohibited Both falling and rising edges 493 21 INTERRUPT AND TEST FUNCTIONS 5 Sampling clock select register SCS This register is used to set the valid edge clock sampling clock to be input to INTPO When remote controlled data reception is carried out using INTPO digital noise is removed with sampling clocks SCS is set with an 8 bit memory manipulation instruction RESET input sets SCS to 00H Symbol 7 6 494 5 4 3 2 1 ws o o eee Figure 21 7 Sampling Clock Select Register Format 0 Address After Reset RAN 00H R W INTPO Sampling Clock Selection MCS 1 MCS 0 1 2 39 1 kHz 2 19 5 kHz 1 25 156 3 kHz 25 78 1 kHz 1 25 78 1 kHz 142 39 1 kHz Caution fxx 2 is a clock to be supplied to the CPU and fxx 25 26 and 27 are clocks to be supplied to the peripheral hardware f
402. l I O mode is used for data transmission reception in 8 bit units Bit wise data transmission reception is carried out in synchronization with the serial clock Shift operation of the serial I O shift register 0 SIOO is carried out at the falling edge of the serial clock SCKO The transmitted data is held in the SOO latch and is output from the SOO pin The received data input to the SIO pin is latched in SIOO at the rising edge of SCKO Upon termination of 8 bit transfer SIOO operation stops automatically and the interrupt request flag CSIIFO is set Figure 16 7 3 Wire Serial I O Mode Timings SCKO 510 500 End of Transfer E Transfer Start at the Falling Edge of SCKO The SOO pin is a CMOS output pin and outputs current SOO latch statuses Thus the SOO pin output status can be manipulated by setting bit 0 RELT and bit 1 CMDT of serial bus interface control register SBIC However do not carry out this manipulation during serial transfer Control the SCKO pin output level in the output mode internal system clock mode by manipulating the P27 output latch refer to 16 4 5 SCKO0 P27 pin output manipulation 3 Other signals Figure 16 8 shows RELT and CMDT operations Figure 16 8 RELT and CMDT Operations SOO latch RELT CMDT 305 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 4 5 306 MSB LSB switching as the start bit The 3 wire serial mode enables to select transfer to sta
403. l ROM size to less than 56K bytes by the memory size switching register 107 CHAPTER 5 CPU ARCHITECTURE Figure 5 16 Data Memory Addressing uPD78P058 78P058Y A Special Function Registers SFRs SFR Addressing 256 x 8 bits eal M rera cse Pee drm ete Ra Sa aee ana ma Seele nn Me D i 207 Register Addressing X SOS Y Short Direct Addressing Internal High speed RAM 1024 x 8 bits 2 ti cta Y FE1FH Reserved FAEOH FADER Direct Addressing Internal Buffer RAM 32 x 8 bits Register Indirect Addressing FABFH Reserved Based Addressing F800H F7FFH Based Indexed Addressing Internal Expansion RAM 1024 x 8 bits F400H F3FFH Reserved FOOOH EFFFH Internal PROM 61440 x 8 bits 0000H Y Note When internal PROM size is 60K bytes the area FOOOH to F3FFH cannot be used F000H to F3FFH can be used as external memory by setting the internal PROM size to less than 56K bytes by the memory size switching register IMS 108 CHAPTER 5 CPU ARCHITECTURE 5 2 Processor Registers The uPD78054 and 78054Y subseries units incorporate the following processor registers 5 2 1 Control registers The control registers control the program sequence statuses and stack memory The control registers consist of a program counter PC a program status word PSW and a stack pointer SP 1 Program
404. l interface the I O and output latches must be set according to the function the user requires For the setting see the operation mode setting list in Table 19 2 Serial Interface Channel 2 CHAPTER 3 PIN FUNCTION uPD78054 Subseries 3 2 9 P120 to P127 Port 12 These are 8 bit input output ports Besides serving as input output ports they function as a real time output port The following operating modes can be specified in 1 bit units 1 Port mode These ports function as 8 bit input output ports They can be specified in 1 bit units as input or output ports with port mode register 12 PM12 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register H PUOH 2 Control mode These ports function as real time output ports RTPO to RTP7 outputting data in synchronization with a trigger 3 2 10 P130 and P131 Port 13 These are 2 bit input output ports Besides serving as input output ports they are used for D A converter analog output The following operating modes can be specified in 1 bit units 1 Port mode These ports function as 2 bit input output ports They can be specified in 1 bit units as input or output ports with port mode register 13 PM13 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register H PUOH 2 Control mode These ports allow D A converter analog output ANOO and ANO1
405. l is dependent upon CPU processing and the value of the automatic data transmit receive interval specify register ADTI see 5 Automatic data transmit receive interval 2 When TRF is cleared the SO1 pin becomes low level Remark CSIIF1 Interrupt request flag TRF Bit 3 of automatic data transmit receive control register ADTC 421 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18 12 Basic Transmission Mode Flowchart Write transmit data in buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Software Execution Set the transmission reception operation interval time in ADTI Write any data to SIO1 Start trigger Write transmit data from buffer RAM to SIO1 Decrement pointer value Transmission operation Hardware Execution Pointer value 0 Software Execution ADTP Automatic data transmit receive address pointer ADTI Automatic data transmit receive interval specify register SIO1 Serial I O shift register 1 TRF Bit 3 of automatic data transmit receive control register ADTC 422 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6 byte transmission ARLD 0 RE 0 in basic transmit mode buffer RAM operates as follows i Before transmission Refer to Figure 18 13 a After any data has been written to serial I O shift register 1 5101 start trigger this data is not transferred transmit data 1 T1 is tra
406. l register TMC1 is set to 1 the 16 bit timer event counter mode is set In this mode the count clock is set with bits 0 to 3 TCL10 to TCL13 of timer clock select register 1 TCL1 and the overflow signal of 8 bit timer register 1 TM1 becomes the count clock of 8 bit timer register 2 TM2 In this mode enable disable of the count operation is selected with bit 0 TCE1 of TMC1 1 Operation as interval timer TMS TM 2 Count Value X N X N A 234 The 8 bit timer event counter operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 2 channel 8 bit compare registers CR10 and CR20 When setting the count value set the value of the higher 8 bits to CR20 and the value of the lower 8 bits to CR10 For the count value that can be set refer to Table 9 9 When 8 bit timer register 1 TM1 and CR10 values match and 8 bit timer register 2 TM2 and CR20 values match counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signal INTTM2 is generated For the timing of interval timer operation refer to Figure 9 11 The count clock is selected with bits 0 to 3 TCL10 to TCL13 of timer clock select register 1 TCL1 and the overflow signal of TM1 becomes the count clock of TM2 Figure 9 11 Interval Timer Operation Timing toa c4 5 A Count Start Clear Clear _ Interrupt Request Acknowledge
407. l signal to be output to SBO SB1 following Acknowledge signal Ready signal READY High level signal to be output to SBO SB1 before serial transfer start and after completion of serial transfer Synchronous BUSY output pum BUSY SBO SB1 lt gt lt BUSY SBO SB1 lt 1 gt 1 2 ACKT set ACKD set Completion of reception BSYE 1 Serial receive disable because of processing lt 1 gt BSYE 0 lt 2 gt Execution of instruction for data write to 5100 transfer start instruction Serial receive enable seuesqns rs08 Gdii 0 14 39VdH31NI 1VIH3S 91 H3ldVHO vce Table 16 3 Various Signals in SBI Mode 2 2 Output Signal Name Definition Timing Chart P Effects on Flag Meaning of Signal Condition Synchronous clock to output address command data AGK signal SCKO E 7 10 Timing of signal Serial clock synchronous BUSY signal Master Ste Address command output to erial data data are transferred with SB0 SB1 SN KLF i DUS the first eight synchronous clocks 8 bit data to be transferred 1 2 7 8 SCK0 L H 7 Le i When CSIEO 1 Address value of Address in synchronization with Master A7 to A0 SCKO after output of REL executi nol s device on the and CMD signals SBO SB1 instruction for CSIIFO set rising serial bus REL CMD data write to edge of 9th clock
408. l up resistor option register H PUOH Alternate function includes real time output RESET input sets the input mode Figure 6 17 shows a block diagram of port 12 Figure 6 17 P120 to P127 Block Diagram Vpp e WRpuo PUO12 gt RD e a 2 2 WRrort s P120 RTP0 Output Latch 4 P120 to P127 P127 RTP7 120 127 e me PUO Pull up resistor option register PM Port mode register RD Port 12 read signal WR Port 12 write signal 148 CHAPTER 6 PORT FUNCTIONS 6 2 11 Port 13 This is a 2 bit input output port with output latches Input mode output mode can be specified bit wise by means of port mode register 18 PM13 When pins P130 and P131 are used as input port pins an on chip pull up resistor can be used as a 2 bit unit by means of pull up resistor option register H PUOH Alternate function includes D A converter analog output RESET input sets the input mode Figure 6 18 shows a block diagram of port 13 Caution When only either one of the D A converter channels is used with AVreri lt Vpp the other pins that are not used as analog outputs must be set as follows Set PM13 bit of the port mode register 13 PM13 to 1 input mode and connect the pin to Vss Set PM13x bit of the port mode register 13 PM13 to 0 output mode and the output latch to 0 to output low level from the pin Fig
409. lation X Subsystem Clock Oscillation CPU Clock 7 5 2 Subsystem clock operations When operated with the subsystem clock with bit 5 CLS of the processor clock control register PCC set to 1 the following operations are carried out a The minimum instruction execution time remains constant 122 us when operated at 32 768 kHz irrespective of bits 0 to 2 PCCO to PCC2 of the PCC b Watchdog timer counting stops Caution Do not execute the STOP instruction while the subsystem clock is in operation 7 6 Changing System Clock and CPU Clock Settings 7 6 1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by means of bits 0 to 2 PCCO to PCC2 and bit 4 CSS of the processor clock control register PCC The actual switchover operation is not performed directly after writing to the PCC but operation continues on the pre switchover clock for several instructions see Table 7 3 Whether the system is operating on the main system clock or the subsystem clock can be discriminated by bit 5 CLS of the PCC register 171 cL Set Values before Switchover Set Values After Switchover Caution 2 MCS Oscillation mode selection register bit 0 3 Figures in parentheses apply to operation with fx 5 0 MHz and fxr 32 768 kHz Selection of the CPU
410. lave device send and receive acknowledge signals to confirm that the serial communication has been executed normally e Wait signal WAIT control function When a slave device is preparing for data transmission or reception and requires more waiting time the slave device outputs a wait signal on the bus to inform the master device of the wait status 2 I C bus definition This section describes the format of serial data communications and functions of the signals used in the 12 bus mode First the transfer timings of the start condition data and stop condition signals which are output onto the signal data bus of the bus are shown in Figure 17 14 Figure 17 14 I C Bus Serial Data Transfer Timing SDAO SDA1 Start Address RAN ACK Data ACK Data ACK Stop condition condition The start condition slave address and stop condition signals are output by the master The acknowledge signal ACK is output by either the master or the slave device normally by the device which has received the 8 bit data that was sent A serial clock SCL is continuously supplied from the master device 368 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries a Start condition When the SDAO SDA1 pin level is changed from high to low while the SCL pin is high this transition is recognized as the start condition signal This start condition signal which is created using the SCL and SDAO or SDA1 pins is output from the master d
411. lected 1 CR00 is set to FFFFH J When TMO is counted up from FFFFH to 0000H Figure 8 38 Operation Timing of OVFO Flag Count Pulse Q CROO FFFFH w ome Xem y mm X OVFO INTTMOO 214 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 AND 2 9 1 8 Bit Timer Event Counters 1 and 2 Functions For the 8 bit timer event counters 1 and 2 two modes are available One is a mode for two channel 8 bit timer event counters to be used separately the 8 bit timer event counter mode and the other is a mode for the 8 bit timer event counter to be used as 16 bit timer event counter the 16 bit timer event counter mode 9 1 1 8 bit timer event counter mode The 8 bit timer event counters 1 and 2 TM1 and TM2 have the following functions nterval timer External event counter Square wave output 215 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 AND 2 1 8 bit interval timer Interrupt requests are generated at the preset time intervals Table 9 1 8 Bit Timer Event Counters 1 and 2 Interval Times Minimum Interval Time Maximum Interval Time Resolution MCS 1 MCS 0 MCS 1 MCS 0 2 x 1 fx 2 x 1 fx 29 x 1 fx 210 x 4 fx 2 x 1 fx 2 x 1 fx 400 ns 800 ns 102 4 us 204 8 us 400 ns 800 ns 22 x 1 fx 23 x 1 fx 210 x 1 fx 211 x 1 fx 22 x 1 fx 23 x 1 fx 800 ns 1 6 us 204 8 us 409 6 us 800 ns 1 6 us 23 x 1 fx 24 x 1 fx 211 x 1 fx 212 x 1 fx 23 x 1 fx 24 x 1 fx 1 6 us 3 2 us 409 6 us 819 2 us 1 6 us 3
412. level to completely erase the written data is shown below e UV intensity x exposure time 30 W s cm or more e Exposure time 40 minutes or more using a 12 mW cm ultraviolet lamp A longer exposure time may be required in case of deterioration of the ultraviolet lamp or dirt on the package window When erasing written data remove any filter on the window and place the device within 2 5 cm of the lamp tube 26 6 Opaque Film Masking the Window uPD78P054KK T and 78 058 Only To prevent unintentional erasure of the EPROM contents by light and to prevent internal circuits from mulfunction due to light coming in through the erasure window mask the window with opaque film after writing the EPROM 26 7 Screening of One Time PROM Versions One time PROM versions uPD78P054GC 3B9 78P054GC 8BT 78P054GK BE9 78P058GC 8BT and 78P058YGC 8BT cannot be fully tested by NEC before shipment due to the structure of one time PROM Therefore after users have written data into the PROM screening should be implemented by user that is store devices at high temperature for one day as specified below and verify their contents after the devices have returned to room temperature Storage Temperature Storage Time 125 0 For users who do not wish to implement screening by themselves NEC provides such users with a charged service in which NEC performs a series of processes from writing one time PROMs and screening them to verifying their cont
413. lid Caution When TRF is cleared the SO1 pin becomes low level Remarks CSIIF1 Interrupt request flag TRF Bit 3 of the auto data send and receive control register ADTC 433 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 c Bit Slippage Detection Function Through the Busy Signal During an auto send and receive operation noise occur in the serial clock signal output by the master device and bit slippage may occur in the slave device side serial clock At this time if the strobe control option is not used this bit slippage will have an effect on sending of the next byte In such a case the busy control option can be used on the master device side and by checking the busy signal during sending bit slippage can be detected Bit slippage detection through the busy signal is accomplished as follows The slave side outputs a busy signal after the serial clock rises on the 8th cycle of data sending or receiving at this time if application of the wait state by the busy signal is not desired the busy signal is made inactive within 2 clock cycles The master device side samples the busy signal in sync with the fall of the serial clock s front side If no bit slippage is occurring the busy signal will be inactive in sampling for 8 clock cycles If the busy signal is found to be active in sampling it is regarded as an occurrence of bit slippage error processing is executed bit 4 ERR of the auto data send and receive control register ADTC is set
414. m each other a transmit error is judged to have occurred b Method of using the slave address register SVA Transmit data is set to both SIOO and SVA and is transmitted After termination of transmission COI bit match signal coming from the address comparator of the serial operating mode register 0 CSIMO is tested If 1 normal transmission is judged to have been carried out If 0 a transmit error is judged to have occurred CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 16 4 5 5 27 pin output manipulation Because the 5 27 pin incorporates an output latch static output is also possible by software in addition to normal serial clock output P27 output latch manipulation enables any value of SCKO to be set by software 510 5 0 and SO0 SB1 pin to be controlled with the RELT and CMDT bits of serial bus interface control register SBIC 5 27 pin output manipulating procedure is described below 1 Setthe serial operating mode register 0 CSIMO SCKO pin enabled for serial operation in the output mode SCKO 1 with serial transfer suspended 2 Manipulate the P27 output latch with a bit manipulation instruction Figure 16 34 SCK0 P27 Pin Configuration Manipulated by bit manipulation instruction gt To Internal P27 Output Circuit Latch SCKO 1 while transfer is stopped Ge Serial Control Circuit When CSIEO 1 and CSIMO1 and CSIMOO are 1 and 0 or 1 and 1
415. marks 1 2 3 4 fx Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency MCS Bit 0 of oscillation mode selection register OSMS Figures in parentheses apply to operation with fx 5 0 MHz 295 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 2 Serial operating mode register 0 CSIMO This register sets serial interface channel 0 serial clock operating mode operation enable stop wake up function and displays the address comparator match signal CSIMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H Caution Do not switch the operation mode 3 wire serial I O 2 wire serial I O SBI of serial interface channel 0 Switch the operation mode after stopping the serial operation Figure 16 4 Serial Operating Mode Register 0 Format 1 2 Symbol 7 lt 6 gt lt 5 gt 4 3 2 1 0 Address After Reset R W R W Input Clock to SCKO pin from off chip Serial Interface Channel 0 Clock Selection 8 bit timer register 2 TM2 output Clock specified with bits 0 to 3 of timer clock select register 3 TCL3 5 5 0 25 Pin Function 500 5 1 26 Pin Function Operation Mode Start Bit S ONote 2 Input 500 CMOS output 3 wire serial mode 5 27 Pin Function SCK0 CMOS input output Note 3 Note 3 SB1 N ch open drain input output P25 CMOS input output SBI m
416. mode control register TMCO 184 This register sets the 16 bit timer operating mode the 16 bit timer register clear mode and output timing and detects an overflow TMCO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TMCO value to 00H Caution The 16 bit timer register starts operation at the moment a value other than 0 0 0 operation stop mode is set in 01 to TMCOS3 respectively Set 0 0 0 in 01 to TMCOS to stop the operation CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 4 16 Bit Timer Mode Control Register Format Symbol 7 6 0 Address After Reset R W 5 4 3 2 1 TMCO o TMCO3TMCO2 TMCO OVFO 4 00H R W OVFO 16 Bit Timer Register Overflow Detection Overflow not detected Overflow detected Operating Mode Clear Mode Selection TO0 Output Timing Selection Interrupt Generation TMC02 Operation stop TM0 cleared to 0 No change Not Generated PWM mode free running PWM pulse output Match between TM0 and CR00 or match between TM0 and CR01 Free running mode Match between TM0 and CR00 match between and CR01 or TI00 valid edge Match between TM0 and Generated on match CR00 or match between between and CR00 TM0 and CR01 or match between TM0 and CR01 Clear amp start on TIOO valid edge Match between TMO and CR00 match between and CR01 or TIOO valid edge Match between TM
417. mory expansion area is read from 4 m is the number of waits when external memory expansion area is written to 569 CHAPTER 27 INSTRUCTION SET Instruction Group Mnemonic Operands Operation SP 1 lt PC 3 SP 2 lt PC 3 PC addr16 SP SP 2 SP 1 lt PC 2 SP 2 PC 2 laddr11 PC 5 11 00001 PCio o lt addr11 SP e SP 2 SP 1 PC 1 SP 2 PC 1 lt 00000000 addr5 1 PC lt 00000000 addr5 SP e SP 2 SP 1 lt PSW SP 2 lt 1 SP 3 lt PC 1 PCH 003FH PC lt 003EH SP SP 3 IE 0 PCH SP 1 PC lt SP SP SP 2 PCH SP 1 SP PSW lt SP 2 SP SP 3 NMIS 0 PCH SP 1 PC SP PSW lt SP 2 SP lt SP 3 SP 1 lt PSW SP lt SP 1 SP 1 lt SP 2 lt rp SP e SP 2 Stack PSW lt SP SP e SP 1 manipulate lt SP 1 rp lt SP SP SP 2 laddr16 addr5 Call return SP word SP AX AX SP SP lt word SP AX AX SP PC lt addr16 PC lt PC 2 jdisp8 PCH A PCL X PC lt PC 2 jdisp8 if CY 1 PC lt PC 2 jdisp8 if CY 0 PC lt PC 2 jdisp8 if Z 1 PC lt PC 2 jdisp8 if Z 0 Uncondi laddr16 tional 16 branch AX
418. n 8 Operates as capture register CRC01 CR00 Capture Trigger Selection Captures on valid edge of TI01 Captures on valid edge of TI00 CRC02 CR01 Operating Mode Selection Operates as compare register Operates as capture register Cautions 1 Timer operation must be stopped before setting CRCO 2 When clear amp start mode on a match between TMO and CROO is selected with the 16 bit timer mode control register CROO should not be specified as a capture register 4 16 bit timer output control register TOCO This register controls the operation of the 16 bit timer event counter output control circuit It sets R S type flip flop LVO setting resetting the active level in PWM mode inversion enabling disabling in modes other than PWM mode 16 bit timer event counter timer output enabling disabling one shot pulse output operation enabling disabling and output trigger for a one shop pulse by software TOCO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TOCO value to 00H 186 CHAPTER 8 16 TIMER EVENT COUNTER Figure 8 6 16 Bit Timer Output Control Register Format Symbol 7 6 5 lt gt lt 2 gt 0 Address After Reset R W 0 osPT ERE 4 Lvso LVRO TOCO1 TOEO FF4EH 00H R W TOEO 16 Bit Timer Event Counter Output Control Output disabled Port mode Output enabled In PWM Mode In Other Modes Timer output F
419. n 3 2 20 VPP PROM versions only High voltage apply pin for PROM programming mode setting and program write verify Directly connect to Vss in the normal operating mode 3 2 21 IC Mask ROM version only The IC Internally Connected pin is provided to set the test mode to check the uPD78054 Subseries before shipment Directly connect this pin to the Vss with the shortest possible wire in the normal operating mode When a voltage difference is produced between the IC pin and Vss pin because the wiring between those two pins is too long or an external noise is input to the IC pin the user s program may not run normally O Directly connect IC pins to Vss pins As short as possible 70 CHAPTER 3 PIN FUNCTION uPD78054 Subseries 3 3 Input output Circuits and Recommended Connection of Unused Pins Table 3 1 shows the input output circuit types of pins and the recommended conditions for unused pins Refer to Figure 3 1 for the configuration of the input output circuit of each type Table 3 1 Pin Input Output Circuit Types 1 2 Input Output Circuit Type 00 Connect to Vss P01 INTP1 TIO1 PO2 INTP2 Pin Name Input Output Recommended Connection of Unused Pins Individually connect to Vss via a resistor Input Output PO4 INTP4 POS INTP5 PO6 INTP6 P07 XT1 Connect to P10 ANIO to P17 ANI7 P20 SI1 P21 SO1 P22 SCK1 P23 STB P24 BUSY 25 510 5 0
420. n SCKO 6 7 8 9 SBO SB1 XwYwYX D2 X D X Do ACK ACK signal is output for a period of one clock just after setting ACKT When set during this period Caution Do not set ACKT before termination of transfer CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries Figure 16 23 ACKE Operations a When 1 upon completion of transfer SCKO 1 2 X06 X signal is output at 9th clock L When 1 at this point b When set after completion of transfer 6 7 ts 9 LI q 1 SB1 X D2 X D X Do ACK ACK signal is output for a period of one clock just after setting ACKE N nT lt If set during this period and 1 at the falling edge of the next SCKO c When 0 upon completion of transfer SCKO 1 2 7 8 9 SBO SB1 X D7 X De Xip2 X D1 X Do ACK signal is not output A When 0 at this point d When ACKE 1 period is short EMEN SBO SB1 D2 X Di X Do ACK signal is not output ACKE gt If set and cleared during this period and 0 at the falling edge of SCKO 321 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries Figure 16 24 ACKD Operations a When ACK signal is output at 9th clock of SCKO Transfer Start m Instruction
421. n 8 bit input output port with output latch P60 to P67 pins can specify the input mode output mode in 1 bit units with the port mode register 6 PM6 This port has functions related to pull up resistors as shown below These functions depending on whether the higher 4 bits or lower 4 bits of a port are used and whether the mask ROM model or PROM model is used Table 6 4 Pull up Resistor of Port 6 NI Higher 4 Bits P64 through P67 pins Lower 4 bits P60 through P63 pins Mask ROM On chip pull up resistor can be connected in 4 bit Pull up resistor can be connected in 1 bit units by version units by PUO6 mask option PROM version Pull up resistor is not connected PUOS Bit 6 of pull up resistor option register L PUOL Pins P60 to P63 can drive LEDs directly Pins P64 to P67 also serve as control signal output in external memory expansion mode RESET input sets port 6 to input mode Figures 6 13 and 6 14 show block diagrams of port 6 Cautions 1 When external wait is not used in external memory expansion mode P66 can be used as an input output port 2 The value of the low level input leakage current flowing to the P60 through P63 pins differ depending on the following conditions Mask ROM version When pull up resistor is connected always 3 uA MAX When pull up resistor is not connected For duration of 1 5 clock no wait when instruction to read port 6 P6 and port mode register 6 PM6 is executed 200 uA MA
422. n format by program Communication is basically carried out with two lines of serial clock SCKO and serial data input output SBO or SB1 Figure 17 10 Serial Bus Configuration Example Using 2 Wire Serial I O Mode Voo Vpop ER Master Slave SCKO SCK0 SB0 SB1 SB0 SB1 1 Register setting The 2 wire serial I O mode is set with the serial operating mode register 0 CSIMO the serial bus interface control register SBIC and the interrupt timing specify register SINT 361 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries a Serial operating mode register 0 CSIMO CSIMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H Symbol lt 7 65 lt 5 gt 4 3 2 1 0 cono se pur e n R W Serial Interface Channel 0 Clock Selection Input Clock to SCKO pin from off chip Address After Reset R W FF60H 00H R WNete 1 8 bit timer register 2 TM2 output Clock specified with bits 0 to 3 of timer clock select register 3 TCL3 CSIM Operation SIO SBO SDAO SO0 SB1 SDA1 SCKO SCL P27 03 Mode P25 Pin Function P26 Pin Function Pin Function ire Serial I Section 17 4 2 3 wire serial mode operati Note 2 Note 2 SB1 SDA1 x x CMOS N ch open drain 2 wire serial input output input output mode SCKO SCL or N ch open drain Note 2 Note 2 bus mode input output x x CMOS inp
423. nal REL is detected When CSIEO 0 When RESET input is applied When command signal CMD is detected R W Acknowledge signal is output in synchronization with the falling edge clock of SCKO just after execution of the instruction to be set to 1 and after acknowledge signal output automatically cleared to 0 Used as ACKE 0 Also cleared to 0 upon start of serial interface transfer or when CSIEO 0 Note Bits 2 3 6 RELD CMDD and are read only bits Remarks 1 Bits 0 1 and 4 RELD CMDT and ACKT are 0 when read after data setting 2 CSIEO Bit 7 of serial operating mode register 0 CSIMO 298 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries Figure 16 5 Serial Bus Interface Control Register Format 2 2 R W ACKE Acknowledge Signal Automatic Output Control Acknowledge signal automatic output disable output with ACKT enable Before completion of Acknowledge signal is output in synchronization with the 9th clock transfer falling edge of SCKO automatically output when 1 Acknowledge signal is output in synchronization with the falling edge of After completion of SCKO just after execution of the instruction to be set to 1 transfer automatically output when ACKE 1 However not automatically cleared to O after acknowledge signal output R ACKD Acknowledge Detection Clear Conditions 0 Set Conditions ACKD 1 Falling
424. nd instruction fetches from external memory The ASTB signal is also output when the internal memory is accessed ADO to AD7 A8 to A15 pins Alternate function P40 to P47 P50 to P57 Address data signal output pin Valid signal is output or input during data accesses and instruction fetches from external memory These signals change when the internal memory is accessed output values are undefined Timing charts are shown in Figure 22 4 to 22 7 518 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION ASTB RD ADO AD7 A8 A15 ASTB RD ADO AD7 A8 A15 Internal Wait Signal 1 clock wait ASTB RD ADO AD7 A8 A15 WAIT Figure 22 4 Instruction Fetch from External Memory a No wait PW1 PWO 0 0 setting Lower Address Operation Code Higher Address b Wait PW1 PWO 0 1 setting c External wait PW1 PWO 1 1 setting TEM uc EC SS X Lower Address X Address Operation Code X X Higher Address X 519 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 520 ASTB RD ADO AD7 A8 A15 ASTB RD ADO AD7 A8 A15 Internal Wait Signal 1 clock wait ASTB ADO AD7 A8 A15 WAIT Figure 22 5 External Memory Read Timing a No wait PW1 PWO 0 0 setting Lower Address Read Data X Higher Address b Wait PW1 PWO 0 1 setting Lower Address Read Data X Higher Address c External wait PW1 PWO 1 1 settin
425. ng INTyy _ INTxx PR 0 PR 0 RETI 1 Instruction Execution Because interrupts are disabled during interrupt INTxx servicing El instruction is not issued interrupt request INTyy is not acknowledged and a multiple interrupt is not generated INTyy request is reserved and acknowledged after execution of one main processing instruction PR 0 High priority level IE 0 Interrupt request acknowledgment disabled 505 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21 4 5 Interrupt request reserve In some cases the acknowledgment of the interrupt request is reserved even an interrupt request is generated during processing of the instruction until the execution of the next instruction is completed The following shows this type of instructions interrupt request reserve instruction MOV PSW byte MOVA PSW MOV PSW A MOV1 PSW bit CY MOV1 CY PSW bit AND1 CY PSW bit OR1 CY PSW bit XOR1 CY PSW bit SET1 PSW bit CLR1 PSW bit RETB RETI PUSH PSW POP PSW PSW bit addr16 BF PSW bit addr16 e BTCLR PSW bit addr16 El DI Manipulate instructions for IFOL IFOH IF1L MKOL MKOH MK1L PROL PROH PR1L INTMO INTM1 registers Caution The BRK instruction is not an interrupt request reserve instruction shown above However in the case of software interrupt that is started up with the execution of the BRK instruction the IE flag is cleared to
426. ng mode Select one analog input channel from ANIO to ANI7 with A D converter input select register ADIS and A D converter mode register ADM and start A D conversion The following two ways are available to start A D conversion Hardware start Conversion is started by trigger input INTP3 Software start Conversion is started by setting ADM The A D conversion result is stored in the A D conversion result register ADCR and the interrupt request signal INTAD is simultaneously generated 1 A D conversion by hardware start When bit 6 TRG and bit 7 CS of A D converter mode register ADM are set to 1 the A D conversion standby state is set When the external trigger signal INTP3 is input the A D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 ADM1 to ADM3 of ADM Upon termination of the A D conversion the conversion result is stored in the A D conversion result register ADCR and the interrupt request signal INTAD is generated After one A D conversion operation is started and terminated another operation is not started until a new external trigger signal is input If data with CS set to 1 is written to ADM again during A D conversion the converter suspends its A D conversion operation and waits for a new external trigger signal to be input When the external trigger input signal is reinput A D conversion is carried out from the beginning If data with CS set to 0 is wr
427. ng register IXS External Memory Expansion Space 64 Kbytes Minimum instruction execution time changeable from high speed 0 4 us In main system clock 5 0 MHz operation to ultra low speed 122 us In subsystem clock 32 768 kHz operation Instruction set suited to system control Bit manipulation possible in all address spaces Multiply and divide instructions 69 I O ports 4 N ch open drain ports 8 bit resolution A D converter 8 channels 8 bit resolution D A converter 2 channels Serial interface 3 channels 3 wire serial I O SBI 2 wire serial mode 1 channel e 9 wire serial I O mode Automatic transmit receive function 1 channel 3 wire serial I O UART mode 1 channel Timer 5 channels 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel 22 vectored interrupt sources 2 test inputs Two types of on chip clock oscillators main system clock and subsystem clock Supply voltage Vpp 2 0 to 6 0 V 37 CHAPTER 1 OUTLINE uPD78054 Subseries 1 2 Applications HP D78052 78053 78054 78P054 78055 78056 78058 78 058 Cellular phones pagers printers AV equipment air conditioners cameras PPCs fuzzy home appliances vending machines etc LP D78052 A 78053 A 78054 A 1 3 Ordering Information Control unit for automobile electronics gas detector breaker various safety unit etc Part number
428. nput Output Individually connect to Vss via a resistor PO4 INTP4 POS INTP5 PO6 INTP6 P07 XT1 Connect to P10 ANIO to P17 ANI7 P20 SI1 P21 SO1 P22 SCK1 P23 STB P24 BUSY P25 SIO SBO SDAO Input Output Individually connect to Voo or Vss via P27 SCK0 SCL resistor P30 TO0 P31 TO1 P32 TO2 P33 TI1 P34 TI2 P35 PCL P36 BUZ P37 P40 ADO to P47 AD7 Input Output Individually connect to Voo via a resistor Individually connect to or Vss via a P50 A8 to P57 A15 Input output resistor CHAPTER 4 FUNCTION uPD78054Y Subseries 88 Table 4 1 Pin Input Output Circuit Types 2 2 Input Output Circuit Type P60 to P63 Mask ROM version Input Output Input output Recommended Connection of Unused Pins Individually connect to Voo via a resistor P60 to P63 PROM version P64 RD P65 WR P66 WAIT P67 ASTB P70 SI2 RxD P71 SO2 TxD P72 SCK2 ASCK P120 RTPO to P127 RTP7 Input output Individually connect to Voo or Vss via a resistor P130 ANOO to P131 ANO1 Input output Individually connect to Vss via a resistor RESET Input XT2 AVREFO AVREF1 AVop AVss IC Mask ROM version Ver PROM version Leave open Connect to Vss Connect to Connect to Vss Directly connect to V
429. ns d described later Figure 16 10 Example of Serial Bus Configuration with SBI Vpp e 7 2 2 53 Serial Clock NEN SCKO SCK0 Slave CPU Master CPU Serial Data Bus SB0 SB1 5 0 SB1 Address 1 SCK0 Slave CPU 7 SB0 SB1 Address 2 SCK0 Slave IC SB0 SB1 Address N Caution When exchanging the master CPU slave CPU a pull up resistor is necessary for the serial clock line SCK0 as well because serial clock line SCK0 input output switching is carried out asynchronously between the master and slave CPUs 307 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 1 SBI functions In the conventional serial I O format when a serial bus is configured by connecting two or more devices many ports and wiring are necessary to provide chip select signal to identify command and data and to judge the busy state because only the data transfer function is available If these operations are to be controlled by software the software must be heavily loaded In SBI a serial bus can be configured with two signal lines of serial clock SCKO and serial data bus SBO SB1 Thus use of SBI leads to reduction in the number of microcontroller ports and that of wirings and routings on the board 308 The SBI functions are described below a b c d e Address command data identify function Serial data is distinguished into addresses commands and data Chip select function by add
430. nsferred from the buffer RAM to SIO1 When transmission of the first byte is completed automatic data transmit receive address pointer ADTP is decremented Then transmit data 2 T2 is transferred from the buffer RAM to SIO1 ii 4th byte transmission point Refer to Figure 18 13 b Transmission of the third byte is completed and transmit data 4 T4 is transferred from the buffer RAM to SIO1 When transmission of the fourth byte is completed ADTP is decremented iii Completion of transmission Refer to Figure 18 13 c When transmission of the sixth byte is completed the interrupt request flag CSIIF1 is set INTCSI1 generation Figure 18 13 Buffer RAM Operation in 6 Byte Transmission in Basic Transmit Mode 1 2 a Before transmission FADFH FAC5H Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 FACOH Transmit data 6 T6 423 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 424 FADFH FAC5H FACOH FADFH FAC5H FACOH Figure 18 13 Buffer RAM Operation in 6 Byte Transmission in Basic Transmit Mode 2 2 b 4th byte transmission point Transmit data 1 T1 y gt SIO1 Transmit data 2 T2 pp 2 ADTP Transmit data 4 T4 Transmit data 5 T5 f Transmit data 6 T6 CSIIF1 c Completion of transmission Transmit data 1 T1 re SIO1 Transmit data 2 T2
431. nt Counters 1 and 2 Chapter 10 Watch Timer Chapter 11 Watchdog Timer Chapter 12 Clock Output Control Circuit Chapter 13 Buzzer Output Control Circuit Chapter 14 A D Converter Chapter 15 D A Converter 4 4 Chapter 16 Serial Interface Channel 0 uPD78054 Subseries Chapter 17 Serial Interface Channel 0 uPD78054Y Subseries Chapter 18 Serial Interface Channel 1 Chapter 19 Serial Interface Channel 2 Chapter 20 Real Time Output Port Chapter 21 Interrupt and Test Functions Chapter 22 External Device Expansion Function Chapter 23 Standby Function Chapter 24 Reset Function Chapter 25 ROM Correction Chapter 26 uPD78P054 uPD78P058 Chapter 27 Instruction Set 11 Differences between 78054 and 78054 Subseries The uPD78054 and uPD78054Y Subseries are different in the following functions of the serial interface channel 0 Modes of serial interface channel 0 uPD78054 uPD78054Y Subseries Subseries 3 wire serial I O mode Y 2 wire serial I O mode SBI serial bus interface mode Inter IC bus mode Y Supported Not supported Legend Data significant Left higher digit right lower digit Active low Xxx top bar over pin or signal name Note F
432. nterval specification register ADTI and the CPU processing at the rising edge of the eighth serial clock Whether it depends on the ADTI or not can be selected by the setting of its bit 7 ADTI7 When it is set to 0 the interval depends only on the CPU processing When it is set to 1 the interval depends on the contents of the ADTI or CPU processing whichever is greater When the automatic transmit receive function is used by an external clock it must be selected so that the interval may be longer than the value indicated by paragraph b Figure 18 23 Automatic Data Transmit Receive Interval Interval SCK1 son AOA Pe AOSD n yD 2100 2620202 Ds m u ES CD mushu 2 C2 2 C2 G2 3 CT CSIIF1 Remark CSIIF1 Interrupt request flag 435 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 a When the automatic transmit receive function is used by the internal clock If bit 1 CSIM11 of serial operation mode register 1 CSIM1 is set at 1 the internal clock operates If the auto send and receive function is operated by the internal clock interval timing by CPU processing is as follows When bit 7 ADTI7 of automatic data transmit receive interval specify register ADTI is set to 0 the interval depends on the CPU processing When ADTI7 is set to 1 it depends the contents of the ADTI or CPU processing whichever is greater Referto Figure 18 5 Automatic Data Transmit Receive Interval Specify Register Format for the inte
433. ntrol 0 Operation stopped 1 Operation enabled 301 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 16 4 2 3 wire serial mode operation The 3 wire serial I O mode is valid for connection of peripheral I O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X XL 78K and 17K series Communication is carried out with three lines of serial clock SCKO serial output 500 and serial input 510 1 Register setting 302 The 3 wire serial mode is set with the serial operating mode register 0 CSIMO and serial bus interface control register SBIC a Serial operating mode register 0 CSIMO CSIMO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMO to 00H CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries Symbol 7 Address After Reset R W e ae oo pur a en oaa rm m m R W Serial Interface Channel 0 Clock Selection Input Clock to SCKO pin from off chip 8 bit timer register 2 TM2 output Clock specified with bits O to 3 of timer clock select register 3 TCL3 CSIM Operation Start Bit SIO SB0 P25 SO0 SB1 P26 SCK0 P27 03 Mode Pin Function Pin Function Pin Function 3 wire serial Sio ee SO0 SCK0 CMOS mode Input CMOS output input output SBI mode See section 16 4 3 SBI mode operation 2 wire serial I O mode See section 16
434. ntrol the real time output port Port mode register 12 PM12 Real time output port mode register RTPM Real time output port control register RTPC 1 Port mode register 12 PM12 This register sets the input or output mode of port 12 pins P120 through P127 which are multiplexed with real time output pins RTPO through RTP7 Touse port 12 as areal time output port the port pin that performs real time output must be set in the output mode PM12n 0 0 to 7 12 is set by using a 1 bit or 8 bit memory manipulation instruction This register is set to FFH by RESET input Figure 20 3 Port Mode Register 12 Format Symbol 7 4 3 2 1 0 Address After Reset R W PM12 PM127 PM126 PM125 PM124 PM123 PM122 PM121 PM120 FF2CH FFH R W 12 Selects I O mode of P12n pin n 0 to 7 Output mode output buffer ON Input mode ourput buffer OFF 2 Real time output port mode register RTPM This register selects the real time output port mode port mode bit wise RTPM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to Figure 20 4 Real time Output Port Mode Register Format After Symbol 7 4 3 2 1 0 Address Reset R W RTPM 7 RTPMSIRTPM4 RTPMSIRTPM2 RTPM1 RTPMO FF34H 00H R W Real time Output Port Selection n 0 to 7 Port mode Real time Output Port Mode Cautions 1 When using these bits as a real time
435. number uSxxxxPG1500 Remark in the part number differs depending on the host machine and OS used uSxxxx PG1500 Host Machine 5A13 PC 9800 series Supply Media MS DOS 3 5 inch 2HD FD ver 3 30 to ver 6 2Note Refer to B 4 5B13 IBM PC AT and 3 5 inch 2HC FD compatibles Note MS DOS ver 5 0 or later has a task swap function but it cannot be used with the above software 584 APPENDIX DEVELOPMENT TOOLS B 3 Debugging Tools B 3 1 Hardware 1 2 1 When using in circuit emulator IE 78K0 NS IE 78K0 NSNote In circuit Emulator An in circuit emulator to debug hardware and software when developing application systems that use the 78K 0 Series Supports integrated debugger ID78KO NS Used in combination with a power supply unit emulation probe and interface adapter to connect to the host machine IE 70000 MC PS B Power Supply Adapter An adapter to supply voltage from AC100 to 240 V outlet IE 70000 98 IF CNote Interface Adapter An adapter required for using a PC 9800 series computer except notebook type personal computer as the host machine for the IE 78KO NS IE 70000 CD IFNote PC Card Interface A PC card and an interface cable required for using PC 9800 series notebook type personal computer as the host machine for the IE 78K0 NS IE 70000 PC IF CNote Interface Adapter An adapter required when using an IBM PC AT and compatible as the host machine f
436. o persons or property arising from a defect in an NEC semiconductor device customers must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application The recommended applications of a device depend on its quality grade as indicated below Customers must check the quality grade of each device before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircrafts aerospace equipment submersible repeaters nuclear reactor control systems life support systems or medical equipment for life support etc The quality grade of NEC devices is Standard unless otherwise specified in NEC s Data Sheets or Data Books If customers intend to use NEC devices for applications other than those specified for Standard quality
437. ock cycle is longer by up to 2 fx only when writing data to OSMS including when writing the same data that was written previously as shown in Figure 7 5 This causes a temporary error in the count clock cycle of timers in the peripheral hardware that operates with the main system clock In addition when the oscillation mode is changed the clocks provided for the peripheral hardware as well as those for the CPU are switched Therefore it is recommended that only one time writing to OSMS be performed between the reset release and the peripheral hardware operation Figure 7 5 Main System Clock when Writing to OSMS Write to OSMS 5 0 Operating at fxx fx 2 MCS 0 asa at fxx fx 2 MCS 0 2 Setting 1 to MCS should be performed after Vpp gt 2 7 V Remarks fxx Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency 164 CHAPTER 7 CLOCK GENERATOR 7 4 System Clock Oscillator 7 4 1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator standard 5 0 MHz connected to the X1 and X2 pins External clocks can be input to the main system clock oscillator In this case input a clock signal to the X1 pin and an antiphase clock signal to the X2 pin Figure 7 6 shows an external circuit of the main system clock oscillator Figure 7 6 External Circuit of Main System Clock Oscillator a Crystal
438. ock oscillation frequency 2 MCS Oscillation mode selection register OSMS bit 0 3 Values in parentheses when operated at fx 5 0 MHz 2 PWM output TMO can generate 14 bit resolution PWM output 3 Pulse width measurement TMO can measure the pulse width of an externally input signal 4 External event counter TMO can measure the number of pulses of an externally input signal 177 CHAPTER 8 16 TIMER EVENT COUNTER 5 Square wave output TMO can output a square wave with any selected frequency Table 8 3 16 Bit Timer Event Counter Square Wave Output Ranges Minimum Pulse Width Maximum Pulse Width Resolution MCS 1 MCS 0 MCS 1 MCS 0 1 MCS 0 2 x 00 input cycle 216 x TIOO input cycle 00 input edge cycle 2 x 1 fx 216 x 1 fx 1 fx 400 ns 13 1 ms 200 ns 2 x 1 fx 22 x 1 fx 216 x 1 fx 217 x 1 fx 1 fx 2 x 1 fx 400 ns 800 ns 13 1 ms 26 2 ms 200 ns 400 ns 22 x 1 fx 23 x 1 fx 217 x 1 fx 218 x 1 fx 2 x 1 fx 22 x 1 fx 800 ns 1 6 us 26 2 ms 52 4 ms 400 ns 800 ns 23 x 1 fx 24 x 1 fx 218 x 1 fx 219 x 1 fx 22 x 1 fx 23 x 1 fx 1 6 us 3 2 us 52 4 ms 104 9 ms 800 ns 1 6 us 2 x watch timer output cycle 216 x watch timer output cycle Watch timer output edge cycle Remarks 1 fx Main system clock oscillation frequency 2 MCS Oscillation mode selection register OSMS bit 0 3 Values in parentheses when operated at fx 5 0 MH
439. ode Note 3 Note 3 SBO N ch open drain input output P26 CMOS I input output SCK0 CMOS input output Note 3 Note 3 SB1 N ch open drain input output P25 CMOS lt input output 2 wire serial mode Note 3 Note 3 SBO N ch open drain input output P26 CMOS input output Notes 1 Bit 6 COI is a read only bit 2 Can be used as P25 CMOS input output when used only for transmission 3 Can be used freely as port function Remark x don t care PMxx Port mode register Pxx Port output latch 296 SCKO N ch open drain input output Continued CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries Figure 16 4 Serial Operating Mode Register 0 Format 2 2 R W Wake up Function ControlNete 1 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release when CMDD RELD 1 matches the slave address register SVA data in SBI mode R Slave Address Comparison Result FlagNete 2 0 Slave address register SVA not equal to serial I O shift register 0 SIOO data Slave address register SVA equal to serial I O shift register 0 SIOO data 0 Operation stopped Notes 1 the wake up function WUP 1 clear the bit 5 SIC of the interrupt timing specify register SINT to 0 2 When CSIEO 0 COI becomes 0 3
440. ode when MM2 MMO 1 11 16 Kbyte Expansion Mode when MM2 MM0 101 4 Kbyte Expansion Mode when 2 0 100 256 byte Expansion Mode when 2 0 011 Single chip Mode CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22 1 Memory Map when Using External Device Expansion Function 2 4 c Memory of uPD78P054 78 058 78P058Y when the uPD78054 78054Y and internal PROM are 32 Kbytes FFFFH FF00H FEFFH FB00H FAFFH FA80H FA7FH C000H BFFFH 9000H 8FFFH 8100H 80FFH 8000H 7FFFH 0000H Internal High Speed RAM Reserved Internal Buffer RAM Reserved Full Address Mode when MM2 MMO 1 11 16 Kbyte Expansion Mode when 2 0 101 4 Kbyte Expansion Mode when 2 0 100 256 byte Expansion Mode when MM2 MMO0 01 1 Single chip Mode d Memory map of uPD78P058 78P058Y when the uPD78055 78055Y internal PROM are 40 Kbytes FFFFH FF00H FEFFH Internal High Speed RAM FB00H FAFFH Reserved FAE0H FADFH Internal Buffer RAM Reserved FA7FH Full Address Mode when MM2 MMO 1 11 E000H DFFFH 16 Kbyte Expansion Mode when 2 0 101 BOOOH AFFFH 4 Kbyte Expansion Mode A100H when 2 0 100 AOFFH 256 byte Expansion Mode A000H when MM2 MMO0 01 1 9FFFH
441. ode they are read with an 8 bit memory manipulation instruction When TM1 and TM2 are used as 16 bit timer x 1 channel mode 16 bit timer TMS is read with a 16 bit memory manipulation instruction RESET input sets TM1 and TM2 to 00H 9 3 8 Bit Timer Event Counters 1 and 2 Control Registers The following four types of registers are used to control the 8 bit timer event counter e Timer clock select register 1 TCL1 8 bit timer mode control register 1 TMC1 8 bit timer output control register TOC1 Port mode register 3 PM3 1 Timer clock select register 1 TCL1 This register sets count clocks of 8 bit timer registers 1 and 2 TCL1 is set with an 8 bit memory manipulation instruction RESET input sets TCL1 to 00H 223 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 AND 2 Figure 9 4 Timer Clock Select Register 1 Format Symbol 7 6 5 4 3 2 1 0 Address After Reset R W TCL1 JTCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10 FF41H 00H R W TCL12 TCL11 8 Bit Timer Register 1 Count Clock Selection TI1 falling edge 1 rising edge fxx 2 fx 2 2 5 MHz 1 25 MHz fxx 2 fx 2 1 25 MHz 625 kHz fxx 2 fx 2 625 kHz 313 kHz fxx 2 fx 2 313 kHz 156 kHz fxx 2 25 156 kHz 78 1 kHz fxx 2 fx 2 78 1 kHz 39 1 kHz fxx 2 fx 2 39 1 kHz 19 5 kHz fo 2 fx 28 19 5 kHz 9 8 kHz
442. of precaution to 19 1 3 3 wire serial I O mode MSB LSB first switchable 444 Change of Figure 19 3 Serial Operating Mode Register 2 Format 446 Change of Table 19 2 Serial Interface Channel 2 Operating Mode Settings 465 Correction of Figure 19 10 Receive Error Timing 474 Addition of 19 4 4 Limitations when UART mode is used 577 578 Addition of APPENDIX A DIFFERENCES BETWEEN 4PD78054 78054Y SUBSERIES AND uPD78058F 78058FY SUBSERIES 579 to APPENDIX B DEVELOPMENT TOOL 592 Entire revision Support for in circuit emulator IE 78K0 NS 593 594 APPENDIX C EMBEDDED SOFTWARE Entire revision Deletion of fuzzy inference development support system The mark x shows major revised points Readers Purpose Organization Caution PREFACE This manual has been prepared for user engineers who want to understand the functions of the uPD78054 and 78054Y Subseries and design and develop its application systems and programs The target products are the products of the following subseries e uPD78054 Subseries uPD78052 78053 78054 78P054 78055 78056 78058 78P058 78052 78053 A 78054 A e uPD78054Y Subseries uPD78052Y 78053Y 78054Y 78055Y 78056Y UPD78058Y 78P058Y Of the above members the following devices with the suffix KK T should be used only for experiment or function evaluation because they are not intended for use in equipment that will be mass
443. ogram 3 Returns to internal ROM program Remark Area filled with diagonal lines Internal expansion RAM JUMP Correction program start address 544 CHAPTER 25 ROM CORRECTION Figure 25 10 Program Transition Diagram when two places are corrected FFFFH F7FFH 6 F7FDH a 2 yyyyH 7 JUMP S 8 4 5 Internal ROM 1 Correction place 2 Internal ROM Correction place 1 Internal ROM 0000H 1 2 3 4 5 6 7 8 Branches to address F7FDH when fetch address matches correction address Branches to branch destination judgment program Branches to correction program 1 by branch destination judgment program BTCLR CORSTO xxxxH Returns to internal ROM program Branches to address F7FDH when fetch address matches correction address Branches to branch destination judgment program 7 Branches to correction program 2 by branch destination judgment program BTCLR ICORST1 yyyyH 2 5 wae ra wa Sree DY NH Returns to internal ROM program Remark Area filled with diagonal lines Internal expansion RAM JUMP Destination judge program start address 545 CHAPTER 25 ROM CORRECTION 25 7 Cautions on ROM Correction 1 2 546 Address values set in correction address registers 0 and 1 CORADO CORAD1 must be addresses where instruction codes are stored Correction address registers 0 and 1 C
444. ol register TOC1 Serial operating mode register 0 CSIMO lt lt Serial bus interface control register SBIC Undefined 00H Slave address register SVA Interrupt timing specify register SINT Serial operating mode register 1 CSIM1 Automatic data transmit receive control register ADTC Automatic data transmit receive address pointer ADTP Automatic data transmit receive interval specify register ADTI Asynchronous serial interface mode register ASIM Asynchronous serial interface status register ASIS Serial operating mode register 2 CSIM2 Baud rate generator control register BRGC 2 2 2 S HS Ha sa 2 2 HS 2 HS HS 2 Transmit shift register TXS SIO2 Receive buffer register RXB A D converter mode register ADM A D converter input select register ADIS Correction control register Note CORCN D A conversion value set register 0 DACSO D A conversion value set register 1 DACS1 D A converter mode register DAM Note This register is provided only in the wPD78058 78P058 78058Y and 78P058Y 116 CHAPTER 5 CPU ARCHITECTURE Table 5 6 Special Function Register List 3 3 Manipulatable Bit Unit Address Special Function Register SFR Name After Reset 1 bit 8 bits 16 bits FFDOH to External access areaNotet Und
445. ollowing methods because the serial bus SDAO SDA1 status during transmission is also taken into the serial I O shift register 0 5100 register of the transmitting device a Comparison of SIOO data before and after transmission In this case a transmission error is judged to have occurred if the two data values are different b Using the slave address register SVA Transmit data is set in SIOO and SVA before transmission is performed After transmission the COI bit match signal from the address comparator of serial operating mode register 0 CSIMO is tested 1 indicates normal transmission and 0 indicates a transmission error 8 Communication operation In the 12 bus mode the master selects the slave device to be communicated with from among multiple devices by outputting address data onto the serial bus After the slave address data the master sends the R W bit which indicates the data transfer direction and starts serial communication with the selected slave device Data communication timing charts are shown in Figures 17 22 and 17 23 In the transmitting device the serial I O shift register 0 SIOO shifts transmission data to the SO latch in synchronization with the falling edge of the serial clock SCL the SOO latch outputs the data on an MSB first basis from the SDAO or SDA1 pin to the receiving device In the receiving device the data input from the SDAO or SDA1 pin is taken into the SIOO in synchronization wit
446. on Reception completion interrupt request generated in case of error generation Reception completion interrupt request not generated in case of error generation Transmit Data Stop Bit Length Specification 0 1 bit 1 2 bits Character Length Specification 0 7 bits 1 8 bits PSO Parity Bit Specification No Parity 0 parity always added in transmission No parity test in reception parity error not generated Odd parity Even parity Receive operation stopped Receive operation enabled TXE Transmit Operation Control Transmit operation stopped Transmit operation enabled 468 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 c Baud rate generator control register BRGC BRGC is set with an 8 bit memory manipulation instruction RESET input sets BRGC to 00H Symbol 7 6 5 4 3 Address After Reset R W 2 1 0 BRGC 53 52 TPS1 TPSO MDL2 MDL1 MDLO FF73H 00H R W MDLO Baud Rate Generator Input Clock Selection k 16 fsck 17 fsck 18 fsck 19 fsck 20 fsck 21 fsck 22 fsck 23 fsck 24 fsck 25 fsck 26 fsck 27 fsck 28 fsck 29 fsck 30 fsck Remark fsck 5 bit counter source clock k Value set in MDLO to MDL3 0 lt k x 14 469 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 5 Bit Counter Source Clock Selection MCS 1 MCS 0 f
447. on Bit 3 must be set to 0 Remarks 1 fxx Main system clock frequency fx or fx 2 2 fx Main system clock oscillator frequency 3 Subsystem clock oscillator frequency 4 MCS Bit 0 of oscillation mode selection register OSMS 162 CHAPTER 7 CLOCK GENERATOR The fastest instruction of the uPD78054 and 78054Y Subseries is executed with two clocks of the CPU clock Therefore relationships between the CPU clock fceu and the minimum instruction execution time are as shown in Table 7 2 Table 7 2 Relationship between CPU Clock and Minimum Instruction Execution Time CPU Clock fceu Minimum Instruction Execution Time 2 fcPu Remarks 1 fx 5 0 MHz fxt 32 768 kHz 2 fx Main system clock oscillation frequency 3 fxr Subsystem clock oscillation frequency 163 CHAPTER 7 CLOCK GENERATOR 2 Oscillation mode selection register OSMS This register specifies whether the clock output from the main system clock oscillator without passing through the scaler is used as the main system clock or the clock output via the scaler is used as the main system clock OSMS is set with 8 bit memory manipulation instruction RESET input sets OSMS to 00H Figure 7 4 Oscillation Mode Selection Register Format After Symbol 7 6 5 4 3 2 1 0 Address Reset R W o Main System Clock Scaler Control 0 Scaler used 1 Scaler not used Cautions 1 Themain system cl
448. on Times TCL20 Runaway Detection Time MCS 1 MCS 0 211 x 1 fxx 211 x 1 fx 410 us 212 x 1 fx 819 212 x 1 fxx 212 x 1 fx 819 213 x 1 fx 1 64 ms 213 x 1 fxx 213 x 1 fx 1 64 ms 214 x 1 fx 3 28 ms 214 x 1 fxx 214 x 1 fx 3 28 ms 215 x 1 fx 6 55 ms 215 x 1 fxx 215 x 1 fx 216 x 1 fx 13 1 ms 216 x 1 fxx 216 x 1 fx 13 1 ms 217 x 1 fx 26 2 ms 217 x 1 fxx 6 55 ms 217 x 1 fx 26 2 ms 218 x 1 fx 52 4 ms 219 x 1 fxx Remarks 1 fxx 2 fx Main system clock oscillation frequency 219 x 1 fx 104 9 ms Main system clock frequency fx or fx 2 220 x 1 fx 209 7 ms 3 MCS Bit 0 of oscillation mode selection register OSMS 4 TCL20 to TCL22 Bits O to 2 of timer clock select register 2 TCL2 5 Figures in parentheses apply to operation with fx 5 0 MHz CHAPTER 11 WATCHDOG TIMER 11 4 2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 WDTM4 of the watchdog timer mode register WDTM is set to 0 A count clock interval time can be selected by the bits 0 through 2 TCL20 through TCL22 of the timer clock select register 2 TCL2 By setting the bit 7 RUN of WDTM to 1 the watchdog timer starts operating as an in
449. on can be stopped by executing the STOP instruction or setting the processor clock control register PCC 2 Subsystem clock oscillator The circuit oscillates at a frequency of 32 768 kHz Oscillation cannot be stopped If the subsystem clock oscillator is not used not using the internal feedback resistance can be set by the processor clock control register PCC This enables to decrease power consumption in the STOP mode 7 2 Clock Generator Configuration The clock generator consists of the following hardware Table 7 1 Clock Generator Configuration Processor clock control register PCC Control register Oscillation mode selection register OSMS Main system clock oscillator Oscillator Subsystem clock oscillator 159 CHAPTER 7 CLOCK GENERATOR 160 Figure 7 1 Block Diagram of Clock Generator FRC XT1 P07 Subsystem fxr Clock XT2 Oscillator Watch Timer Clock Output Function Prescaler S 7 E System Peripheral X2 Clock fxr Hardware Oscillator 2 Selector 8 Wait CPU Clock 9 Control 3 Circuit To INTPO Sampling Clock 1 ESSERE Processor Clock Control Register STOP MCS Oscillation Mode Selection Register 5 Internal Bus 5 CHAPTER 7 CLOCK GENERATOR 7 3 Clock Generator Control Register The clock generator is controlled by the following two registers Processor clock control r
450. on instruction RESET input sets CSIM2 to OOH When the UART mode is selected 00H should be set in CSIM2 Address After Reset R W FF72H 00H R W CSCK Selection of Serial Operating Mode 0 UART mode 1 3 wire serial mode CSIM22 First Bit Specification MSB LSB 5 4 3 2 1 0 CSIM CSIE2 Operation Control in 3 wire Serial Mode 0 Operation stopped 1 Operation enabled Caution Ensure that bits 0 and 3 to 6 are set to 0 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 b Asynchronous serial interface mode register ASIM ASIM is set with a 1 bit or 8 bit memory manipulation instruction Symbol ASIM RESET input sets ASIM to 00H lt gt 6 Fre me re Tc eme Address After Reset R W FF70H 00H R W SCK Clock Selection in Asynchronous Serial Interface Mode Input clock from off chip to ASCK pin Dedicated baud rate generator outputNote ISRM Control of Reception Completion Interrupt Request in Case of Error Generation Reception completion interrupt request generated in case of error generation Reception completion interrupt request not generated in case of error generation Transmit Data Stop Bit Length Specification 0 1 bit 1 2 bits Character Length Specification 0 7 bits 1 8 bits No Parity PS0 Parity Bit Specification 0 parity always added in transmission No parity test in reception parity error n
451. ontrol SI1 P20 Pin Function P20 CMOS input output SO1 P21 Pin Function P21 CMOS input output SCK1 P22 Pin Function P22 CMOS input output Note 2 1 Notes 1 Note 2 x Operation enable Can be used freely as port function Count operation 11 Note 2 Input SO1 CMOS output SCK1 Input SCK1 CMOS output 2 Can be used as P20 CMOS input output when only transmitter is used clear bit 7 RE of the automatic data transmit receive control register ADTC to 0 Remark x Don t care PMxx Port mode register Pxx Port output latch 405 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18 4 2 3 wire serial mode operation The 3 wire serial I O mode is valid for connection of peripheral I O units and display controllers which incorporate a conventional synchronous serial interface such as the 75X XL 78K and 17K series Communication is carried out with three lines of serial clock SCK1 serial output SO1 and serial input 511 1 Register setting 3 wire serial I O mode is set with the serial operating mode register 1 CSIM1 CSIM1 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM1 to 00H Symbol lt 7 gt 6 5 4 3 2 1 0 Address After Reset R W spem mp o reme me CSIM11 1 Serial Interface Channel 1 Clock Selection Clock externally input to SCK1 pinNote
452. ootnote Caution Important information Remark Supplement Numerical notation Binary or xxxxB Decimal Hexadecimal 12 Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such e Related documents for uPD78054 Subseries Document No Document name Japanese English uPD78052 78053 78054 78055 78056 78058 Data Sheet U12327J U12327E uPD78052 A 78053 A 78054 A Data Sheet U12171J U12171E uPD78P054 78P058 Data Sheet U10417J U10417E uPD78054 78054Y Subseries User s Manual U11747J This manual 78K 0 Series User s Manual Instruction U12326J U12326E 78K 0 Series Instruction Table U10903J 78K 0 Series Instruction Set U10904J uPD78054 Subseries Special Function Register Table U10102J 78K 0 Series Application Note Basics lll U10182J U10182E Floating point operation program IEA 718 IEA 1289 Related documents for u PD78054Y Subseries Document No Document name Japanese English uPD78052Y 78053Y 78054Y 78055Y 78056Y 78058Y Data Sheet U10906J U10906E uPD78P058Y Data Sheet U10907J U10907E uPD78054 78054Y Subseries User s Manual U11747J This manual 78K 0 Series User s Manual Instruction U12326J U12326E 78K 0 Series Instruction Table U10903J 78K 0 Series Instruction Set U10904J uPD78054Y Subseries Special Function Regi
453. operated at fx 5 0 MHz 212 x 1 fx 819 2 us 219 x 1 fx 104 9 ms 220 x 4 fx 209 7 ms Main system clock oscillation frequency 211 x 1 fx 409 6 us 212 x 1 fx 819 2 us 217 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 AND 2 9 1 2 16 bit timer event counter mode 1 16 bit interval timer 218 Interrupt requests can be generated at the preset time intervals Table 9 3 Interval Times when 8 Bit Timer Event Counters 1 and 2 are Used as 16 Bit Timer Event Counters Minimum Interval Time Maximum Interval Time Resolution MCS 1 MCS 0 1 MCS 0 2 x 1 fx 22 x 1 fx 217 x 1 fx 218 x 1 fx 2 x 1 fx 22 x 1 fx 400 ns 800 ns 26 2 ms 52 4 ms 400 ns 800 ns 22 x 1 fx 23 x 1 fx 218 x 1 fx 219 x 1 fx 22 x 1 fx 23 x 1 fx 800 ns 1 6 us 52 4 ms 104 9 ms 800 ns 1 6 us 23 x 1 fx 24 x 1 fx 219 x 1 fx 220 x 1 fx 23 x 1 fx 24 x 1 fx 1 6 us 3 2 us 104 9 ms 209 7 ms 1 6 us 3 2 us 24 x 1 fx 25 x 1 fx 220 x 1 fx 221 x 1 fx 24 x 1 fx 25 x 1 fx 3 2 us 6 4 us 209 7 ms 419 4 ms 3 2 us 6 4 us 25 x 1 fx 26 x 1 fx 221 x 1 fx 222 x 1 fx 25 x 1 fx 26 x 1 fx 6 4 us 12 8 us 419 4 ms 838 9 ms 6 4 us 12 8 us 26 x 1 fx 27 x 1 fx 222 x 1 fx 223 x 1 fx 28 x 1 fx 27 x 1 fx 12 8 us 25 6 us 838 9 ms 1 7 s 12 8 us 25 6 us 27 x 1 fx 28 x 1 fx 223 x 1 fx 224 x 1 fx 27 x 1 fx 28 x 1 fx 25 6 us 51 2 us 1 7 s 3 4 s 25 6 us 51 2 us 28 x 1 fx 29 x 1 fx 224
454. operating mode register 0 CSIMO to 1 in the serial transfer statusNete the uPD78054Y subseries checks the address of the data between the other slave and master If that data happens to coincide with the slave address of the uPD78054Y subseries the uPD78054Y subseries takes part in communication destroying the communication data Note The serial transfer status is the status since data has been written to the serial I O shift register 0 SIOO until the interrupt request flag CSIIFO is set to 1 by completion of the serial transfer The above phenomenon can be avoided by modifying the program Before executing the wake up function execute the following program that clears the serial transfer status When executing the wake up function do not execute an instruction that writes data to SIOO Even if such an instruction is not executed data can be received while the wake up function is executed This program releases the serial transfer status To release the serial transfer status the serial interface channel 0 must be once disabled by clearing the CSIEO flag bit 7 of the serial operating mode register CSIMO to 0 If the serial interface channel 0 is disabled in the 12 bus mode however the SCL pin outputs a high level and SDAO SDA1 pin outputs a low level affecting communication of the 12 bus Therefore this program makes the SCL and SDAO SDA 1 pins go into a high impedance state to prevent the 12C bus from being affected
455. or the IE 78K0 NS IE 780308 NS EM1 Note Emulation Board A board to emulate peripheral hardware peculiar to the device Used in combination with an in circuit emulator NP 80GC Emulation Probe A probe to connect an in circuit emulator and a target system For 80 pin plastic QFP GC 3B9 GC 8BT type EV 9200GC 80 Conversion Socket refer to Figure B 2 A conversion socket to connect the board of a target system that is designed to mount 80 pin plastic QFP GC 3B9 GC 8BT type and the NP 80GC The uPD78P054KK T 78PO58KK T and 78P058YKK T ceramic WQFN can be mounted instead of connecting NP 80GC NP 80GK Emulation Probe A probe to connect an in circuit emulator and the target system For 80 pin plastic TQFP GK BE9 type TGK 080SDW Conversion Adapter refer to Figure B 3 Note Under development A conversion adapter to connect the board of a target system designed to mount 80 pin plastic GK BE9 type to the NP 80GK Remarks 1 The NP 80GC and NP 80GK are products of Naito Densei Machidaseisakusho Co Ltd Contact Naito Densei Machidaseisakusho Co Ltd Tel 044 822 3813 2 The TGK 080SDW is a product of TOKYO ELETECH Corporation Contact Daimaru Kogyo Co Ltd Tokyo Electronic Component Department Tel 03 3820 7112 Osaka Electronic Component Department Tel 06 244 6672 3 The TGK 080SDW is sold singly 4 The EV 9200GC 80 is sold in a set of five 585 APPENDI
456. ormed using three lines the serial clock SCK2 serial output SO2 and serial input SI2 1 Register setting 3 wire serial I O mode settings are performed using serial operating mode register 2 CSIM2 the asynchronous serial interface mode register ASIM and the baud rate generator control register BRGC a Serial operating mode register 2 CSIM2 CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to OOH Symbol Address After Reset R W FF72H 00H R W CSCK Selection of Serial Operation Mode 0 UART mode 1 3 wire serial mode CSIM22 First Bit Specification MSB LSB CSIM2 lt 7 gt 6 5 4 3 2 1 0 CSIM CSIE2 Operation Control in 3 wire Serial I O Mode 0 Operation stopped 1 Operation enabled Caution Ensure that bits 0 and 3 to 6 are set to 0 467 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 b Asynchronous serial interface mode register ASIM ASIM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIM to 00H When the 3 wire serial I O mode is selected 00H should be set ASIM Symbol 27 lt 6 gt 5 4 3 2 1 0 Address After Reset R W ASIM PS1 PSO ISRM FF70H 00H R W SCK Clock Selection in Asynchronous Serial Interface Mode Input clock from off chip to ASCK pin Dedicated baud rate generator output ISRM Control of Reception Completion Interrupt Request in Case of Error Generati
457. os o o os rem nw INTPO Sampling Clock Selection 5 51 5 50 5 1 5 0 27 39 1 kHz fx 2 19 5 kHz fx 2 156 3 kHz fx 2 78 1 kHz fx 2 78 1 kHz fx 2 39 1 kHz Caution fxx 2N is the clock supplied to the CPU and fxx 25 26 and fxx 27 are clocks supplied to peripheral hardware fxx 2N is stopped in HALT mode Remarks 1 Value set in bits 0 2 PCCO to PCC2 of the processor clock control register N 0 to 4 2 fxx Main system clock frequency fx or fx 2 3 fx Main system clock oscillation frequency 4 MCS Bit 0 of oscillation mode selection register OSMS 5 Figures in parentheses apply to operation with fx 2 5 0 MHz 190 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 5 16 Bit Timer Event Counter Operations 8 5 1 Interval timer operations Setting the 16 bit timer mode control register and capture compare control register 0 CRCO as shown in Figure 8 10 allows operation as an interval timer Interrupt requests are generated repeatedly using the count value set in 16 bit capture compare register 00 CROO beforehand as the interval When the count value of the 16 bit timer register matches the value set to CROO counting continues with the TMO value cleared to 0 and the interrupt request signal INTTMOO is generated Count clock of the 16 bit timer event counter can be selected with bits 4 to 6 TC
458. ot generated Odd parity Even parity Receive operation stopped Receive operation enabled Transmit operation stopped Transmit operation enabled Note When SCK is setto 1 and the baud rate generator output is selected the ASCK pin can be used as an input output port Caution The serial transmit receive operation must be stopped before changing the operating mode 455 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 c Asynchronous serial interface status register ASIS ASIS is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIS to 00H 5 4 3 2 1 0 EZEXESESEES Symbol 7 6 Address After Reset R W ASIS FF71H 00H R Overrun Error Flag 0 1 Overrun error not generated Overrun error generatedNote 1 When next receive operation is completed before data from receive buffer register is read Framing Error Flag Framing error not generated Framing error generatedNete 2 When stop bit is not detected Parity error not generated Parity error generated When transmit data parity does not match Notes 1 Thereceive buffer register RXB must be read when an overrun error is generated Overrun errors will continue to be generated until RXB is read 2 Even if the stop bit length has been set as 2 bits by bit 2 SL of the asynchronous serial interface mode register ASIM only single stop bit detection is performed during recept
459. output control circuit Figure 9 3 Block Diagram of 8 Bit Timer Event Counter Output Control Circuit 2 Level F F LV2 fsck LVR2 TO2 P32 LVS2 TOC15 INTTM2 TOE2 Remarks 1 The section in the broken line is an output control circuit 2 fsck Serial clock frequency 222 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 AND 2 1 Compare registers 10 and 20 CR10 CR20 These are 8 bit registers to compare the value set to CR10 to the 8 bit timer register 1 TM1 count value and the value set to CR20 to the 8 bit timer register 2 TM2 count value and if they match generate an interrupt request INTTM1 and INTTM2 respectively This register can also be used as the register which holds the interval time when setting TM1 and TM2 to interval timer operation CR10 and CR20 are set with an 8 bit memory manipulation instruction They cannot be set with a 16 bit memory manipulation instruction When the compare register is used as 8 bit timer event counter the 00H to FFH values can be set When the compare register is used as 16 bit timer event counter the 0000H to FFFFH values can be set RESET input makes CR10 and CR20 undefined Caution When using the compare register as 16 bit timer event counter be sure to set data after stopping timer operation 2 8 bit timer registers 1 2 TM1 TM2 These are 8 bit registers to count count pulses When TM1 and TM2 are used in the 8 bit timer x 2 channel m
460. pply Media PC 9800 series Japanese WindowsNetes 1 2 3 5 inch 2HD FD IBM PC AT and Japanese WindowsNetes 1 2 3 5 2HC FD compatibles English WindowsNotes 1 2 HP9000 series 700 HP UX rel 9 05 DAT DDS SPARCstation SunOS rel 4 1 4 3 5 inch 2HC FD 1 4 inch CGMT NEWS RISC NEWS OS rel 6 1 3 5 inch 2HC FD Notes 1 Operates also in DOS environment 2 Does not support WindowsNT 583 APPENDIX DEVELOPMENT TOOLS B 2 PROM Writing Tools B 2 1 Hardware PG 1500 PROM Programmer A PROM programmer that by connecting the attached board and separately available PROM programmer adapter is capable of programming single chip microcomputers incorporating a PROM on stand alone basis or through operation from the host machine Also capable of programming typical 256 Kbit to 4 Mbit PROM PA 78P054GC PA 78P054GK PA 78P054KK T A PROM programmer adapter for the uPD78P054 78P058 and 78P058Y Used connected to the PG 1500 PA 78P054GC 80 pin plastic QFP GC 3B9 GC 8BT type PA 78P054GK 80 pin plastic QFP GK BE9 type PA 78P054KK T 80 pin ceramic WQFN KK T type PROM Programmer Adapter B 2 2 Software PG 1500 Controller Connects PG 1500 and the host machine with serial and parallel interface and controls the PG 1500 on the host machine The PG 1500 controller is a DOS based application Use it with the DOS prompt on Windows Part
461. products The uPD78P054 78P058 replace the internal mask ROM of the wPD78054 78058 with one time PROM or EPROM Table 26 1 lists the differences among the uPD78P054 78P058 and the mask ROM versions Table 26 2 lists the differences between the uwPD78P054 and the uPD78P058 Table 26 1 Differences between PD78P054 78P058 and Mask ROM Versions LuPD78P054 78P058 Mask ROM version Internal ROM structure One time PROM EPROM Mask ROM Internal ROM capacity LPD78P054 32 Kbytes HPD78052 16 Kbytes 078 058 60 Kbytes 078053 24 Kbytes HPD78054 32 Kbytes HPD78055 40 Kbytes HPD78056 48 Kbytes HPD78058 60 Kbytes Internal high speed RAM capacity 1024 bytes HPD78052 512 bytes 78053 1024 bytes HPD78054 1024 bytes 78055 1024 bytes HPD78056 1024 bytes 78058 1024 bytes Internal expansion RAM capacity HPD78P054 None HPD78052 None LPD78P058 1024 bytes LPD78053 None HPD78054 None HPD78055 None HPD78056 None HPD78058 1024 bytes Changing internal ROM and internal high EnableNote 1 Disable speed RAM capacities with memory size switching register Changing of internal expansion RAM Enable with uPD78P058 onlyNote 2 Disable capacity by internal expansion RAM size switching register IC pin None Available VPP pin Available None Mask option with on chip pull up resistor None None for P60 to P63 pins Electrical characteristics Refer to the separate Data Sheet
462. ps converter D A converter Operable Real time output port Operable when external trigger is used or TI1 and TI2 are selected for the 8 bit timer event counter count clock Serial interface Other than Operable when externally supplied clock is specified as the serial clock automatic transmit receive function and UART Automatic Operation stops transmit receive function and UART External interrupt INTPO Not operable INTP1 INTP6 Operable Bus line for ADO AD7 High impedance external A0 A15 Status before STOP mode setting is held expansion Low level High level High impedance 530 CHAPTER 23 STANDBY FUNCTION 2 STOP mode release The STOP mode can be cleared with the following three types of sources a Release by unmasked interrupt request When an unmasked interrupt request is generated the STOP mode is cleared If interrupt request acknowledge is enabled after the lapse of oscillation stabilization time vectored interrupt service is carried out If interrupt request acknowledge is disabled the next address instruction is executed Figure 23 4 STOP Mode Release by Interrupt Request Generation Wait STOP Interrupt Time set by OSTS Instruction Request Standby Release Signal m RET Operationg Oscillation Stabilization Operating Mode STOP Mode Wait Status Mode Oscillation Oscillation Stop Oscillation Clock a Remark
463. pt external input clock operation 169 CHAPTER 7 CLOCK GENERATOR 7 5 1 Main system clock operations When operated with the main system clock with bit 5 CLS of the processor clock control register PCC set to 0 the following operations are carried out by PCC setting a Because the operation guarantee instruction execution speed depends on the power supply voltage the minimum instruction execution time can be changed by bits 0 to 2 PCCO to PCC2 of the PCC b If bit 7 MCC of the PCC is set to 1 when operated with the main system clock the main system clock oscillation does not stop When bit 4 CSS of the PCC is set to 1 and the operation is switched to subsystem clock operation CLS 1 after that the main system clock oscillation stops see Figure 7 9 Figure 7 9 Main System Clock Stop Function 1 2 a Operation when MCC is set after setting CSS with main system clock operation MCC CSS y CLS f E Main System Clock Oscillation Subsystem Clock Oscillation X CPU Clock b Operation when MCC is set in case of main system clock operation MCC CSS CLS Oscillation does not stop Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock 170 CHAPTER 7 CLOCK GENERATOR Figure 7 9 Main System Clock Stop Function 2 2 c Operation when CSS is set after setting MCC with main system clock operation MCC CSS CLS A Main System Clock Oscil
464. pture Registers a 16 bit timer mode control register TMCO 03 02 01 OVFO b control register 0 CRCO Free Running Mode CRC02 01 CRCOO E ESE EIE REC CROO set as capture register Captured in CROO on invalid edge of 00 00 Pin 01 set as capture register Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement See the description of the respective control registers for details 201 CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 23 Timing of Pulse Width Measurement Operation by Free Running Counter and Two Capture Registers with Rising Edge Specified DELE lt gt TMO Count Value X D3 X TI00 Pin Input 4 i CR01 Captured Value p 1 3i X91 CROO Captured Value 1X 91 EE INTPO Z a 24 2 si __ gt lt e e e B gt lt B e 7 B 85 i gt lt T m e e e gt gt lt N OVFO i n K z E D1 DO xt 10000H D1 D2 xt D3 D2 xt 202 CHAPTER 8 16 TIMER EVENT COUNTER 4 Pulse width measurement by means of restart When input of a valid edge to the 00 00 pin is detected the count value of the 16 bit timer register TMO is taken into 16 bit capture compare register 01 CRO1 and then the pulse width of the signal input to the
465. pull up resistor can be used Pos by software P07Note1 Input only P10 to P17 Port 1 P00 P01 P02 P03 Port 0 When used as an input port an P04 P05 P06 8 bit input output port Input output mode can be specified in 1 bit units ANIO to ANI7 When used as input port an on chip pull up resistor can be used by softwareNote2 Port 2 8 bit input output port Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by SIO SBO software SOO SB1 Notes 1 Whenthe 7 pinis used as an input port set the bit 6 FRC ofthe processor clock control register PCC to 1 do not use the feedback resistor internal to the subsystem clock oscillator 2 When pins P10 ANIO to P17 ANI7 are used as an analog input of the A D converter set port 1 to input mode The on chip pull up resistor will automatically be disabled 59 CHAPTER 3 PIN FUNCTION uPD78054 Subseries 1 Port pins 2 3 Pin Name Input Output Function Port 3 8 bit input output port Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software After Reset Alternate Function P40 to P47 Port 4 8 bit input output port Input output mode can be specified in 8 bit units When used as an input port an on chip pull up resistor can be used by software Test input flag KRIF is
466. put 2 TO1 TO2 Timer clock select register 1 TCL1 8 bit timer mode control register 1 TMC1 8 bit timer output control register TOC1 Port mode register 3 PM3 Note Control register Note Refer to Figure 6 9 Block Diagram of P30 to P37 220 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 AND 2 Figure 9 1 8 Bit Timer Event Counters 1 and 2 Block Diagram Internal Bus bo 2 ho 2 bor TI1 P33 Selector fxoJ2 fo 2 5 fof o TI2 P34 44 Match gt INTTM1 Selector Timer Clock Select Register 1 TCL TCL 17 16 15 14 13 12 11 10 8 Bit Compare Register CR20 Match Selector 8 Bit Timer Register 2 TM2 Clear 8 Bit Timer Mode Control Register 8 Bit Timer Event Counter Output Control Circuit Note TO2 P32 TO1 P31 i 1 8 Bit Timer Output M Internal Bus Note Refer to Figures 9 2 and 9 3 for details of 8 bit timer event counters 1 and 2 output control circuits 1 and 2 respectively 221 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 AND 2 Figure 9 2 Block Diagram of 8 Bit Timer Event Counter Output Control Circuit 1 Level F F LV1 O TO1 P31 1 Remark The section in the broken line is an
467. put pin 5 TMO 16 bit timer register 6 MCS Oscillation mode selection register OSMS bit 0 7 Figures in parentheses apply to operation with fx 5 0 MHz or fxr 32 768 kHz 2 Port mode register 3 PM3 This register set port 3 input output in 1 bit units When using the P35 PCL pin for clock output function set PM35 and output latch of P35 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to Figure 12 4 Port Mode Register 3 Format After Symbol 7 6 Reset Address R W 5 4 3 2 1 0 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H FFH R W P3n Pin Input Output Mode Selection n 0 to 7 0 1 Output mode output buffer ON Input mode output buffer OFF 259 260 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13 1 Buzzer Output Control Circuit Functions The buzzer output control circuit outputs 1 2 kHz 2 4 kHz 4 9 kHz or 9 8 kHz frequency square waves The buzzer frequency selected with timer clock select register 2 TCL2 is output from the BUZ P36 pin Follow the procedure below to output the buzzer frequency 1 Select the buzzer output frequency with bits 5 to 7 TCL25 to TCL27 of TCL2 2 Set the P36 output latch to 0 3 Set bit 6 PM36 of port mode register 3 PM3 to 0 Set to output mode Caution Buzzer output cannot be used when setting P36 output latch to 1 13 2 Buzzer Output Control Circuit Confi
468. quest signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release when CMDD RELD 1 matches the slave address register SVA data in SBI mode Slave Address Comparison Result Flag 4 Slave address register SVA not equal to serial I O shift register 0 SIOO data Slave address register SVA equal to serial I O shift register 0 SIOO data 0 Operation stopped Notes 1 Bit 6 COI is a read only bit 2 Can be used as a port 3 To use the wake up function WUP 1 clear the bit 5 SIC of the interrupt timing specify register SINT to 0 4 When CSIE0 0 COI becomes 0 Remark x don t care PMxx Port mode register Pxx Port output latch 315 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries b Serial bus interface control register SBIC SBIC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SBIC to 00H The shaded area is used in the SBI mode Symbol 1 0 Address After Reset R W SBIC BSYE RELD CMDT RELT FF61H 00H R WNote R W Used for bus release signal output When RELT 1 SOO latch is set to 1 After SOO latch setting automatically cleared to 0 Also cleared to 0 when CSIEO 0 R W Used for command signal output When CMDT 1 00 latch is cleared to 0 After SOO latch clearance automatically cleared to 0 Also cleared to 0 when
469. quipped with inverter control circuit and UART reduced EMI noise version FIP driving uPD780208 Enhanced I O and FIP C D of uPD78044F 53 display outputs Enhanced I O and FIP C D of uPD78044H 48 display outputs uPD78044H Added N ch open drain I O to uPD78044F 34 display outputs uPD78044F Basic subseries for driving FIPs 34 display outputs LCD driving uPD780308 uPD780308Y Enhanced SIO of uPD78064 expanded ROM and RAM uPD78064B Reduced EMI noise version of uPD78064 uPD78064 uPD78064Y Basic subseries for driving LCDs equipped with UART IEBus supported uPD78098B uPD78098 Reduced EMI noise version of uPD78098 Added IEBus controller to uPD78054 Meter control oa m n i n uPD780973 d axxo mE nm Equipped with controller driver for driving automobile meters 43 1 OUTLINE uPD78054 Subseries The following shows the major differences between subseries products Subseries Name Control Inverter control FIP driving LCD driving IEBus supported Meter control uPD78075B ROM Capacity 32 K to 40 K Timer uPD78078 48 K to 60 K uPD78070A uPD780058 24 K to 60 K uPD78058F 48 K to 60 K uPD78054 16 K to 60 K uPD780034 uPD780024 uPD78014H 8Kto32K uPD78018F uPD78014 16 bit Watch 10 bit A D Serial Interface 8 ch UART 1 ch Vpp MIN Value 3 ch Time
470. r The stop condition signal is detected by hardware incorporated in the slave device Figure 17 19 Stop Condition SCL CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries f Wait signal WAIT The wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data During the wait state the slave device continues to output the wait signal by keeping the SCL pin low to delay subsequent transfers When the wait state is released the master device can start the next transfer For the releasing operation of slave devices see section 17 4 5 Cautions on Use of Bus Mode Figure 17 20 Wait Signal a Wait of 8 Clock Cycles Set low because slave device drives low though master device returns to Hi Z state No wait is inserted after 9th clock cycle and before master device starts next transfer SCL of master device SCL of slave device SDAO SDA1 D2 D1 fess Output by manipulating ACKT b Wait of 9 Clock Cycles Set low because slave device drives low though master device returns to Hi Z state SCL of master device SCL of slave device umo SDAO SDA1 t Output based on the value set in ACKE in advance 371 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 3 Register setting 2
471. r interval includes an error The data transfer minimum and maximum intervals are found from the following expressions n Value setin ADTIO to ADTI4 However if a minimum which is calculated by the following expressions is smaller than 2 fsck the minimum interval time is 2 fsck Minimum n 1 x Maximum n 1 28 0 5 x28 fxx fsck 36 1 5 fxx fsck Cautions 1 Do not write data to ADTI during operation of automatic data transmit receive Remarks 1 2 3 function Bits 5 and 6 must be set to zero To control the data transfer interval by means of automatic transmission reception with ADTI busy control refer to 18 4 3 4 a Busy control option is disabled fx Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency fsck Serial clock frequency 413 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 414 5 4 3 2 1 0 ADTI ADTI7 fo o ADTI4 ADTI3 ADTI2 ADTI1 ADTIO FF6BH ADTI7 Data Address Transfer Interval Control No control of interval by ADT Note 1 After Reset 00H R W R W 0 1 ADTIS Control of interval by ADTI ADTIO to ADTI4 Data Transfer Interval Specification fxx 2 5 MHz Operation ADTI2 ADTI1 MinimumNote 2 36 8 us O 5 fsck MaximumNete 2 40 0 us 1 5 fsck 62 4 5 O 5 fsck 65 6 5 1 5 fsck 88 0 us 0 5 fsck 91 2 5 1 5 fsck 113 6 us 0 5 116 8 us 1 5 fsck
472. rame are specified with asynchronous serial interfaece mode register ASIM When 7 bits are selected as the number of character bits only the lower 7 bits bits O to 6 are valid in transmission the most significant bit bit 7 is ignored and in reception the most significant bit bit 7 is always 0 The serial transfer rate is set with ASIM and the baud rate generator control register BRGC If a serial data receive error is generated the receive error contents can be determined by reading the status of the asynchronous serial interface status register ASIS 461 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 462 b Parity types and operation The parity bit is used to detect a bit error in the communication data Normally the same kind of parity bit is used on the transmitting side and the receiving side With even parity and odd parity a one bit odd number error can be detected With 0 parity and no parity an error cannot be detected i Even parity Transmission The number of bits with a value of 1 including the parity bit in the transmit data is controlled to be even The value of the parity bit is as follows Number of bits with a value of 1 in transmit data is odd 1 Number of bits with a value of 1 in transmit data is even 0 Reception The number of bits with a value of 1 including the parity bit in the receive data is counted If it is odd a parity error occurs ii Odd parity
473. ransfer to start from MSB or LSB Figure 19 13 shows the configuration of the transmit shift register TXS SIO2 and internal bus As shown in the figure MSB LSB can be read written in reverse form MSB LSB switching as the start bit can be specified with bit 2 CSIM22 of the serial operating mode register 2 CSIM2 Figure 19 13 Circuit of Switching in Transfer Bit Order Internal Bus 4 nex pa SI rue ara a rA a ERE LSB first MSB first Read Write Gate Read Write Gate Start bit switching is realized by switching the bit order for data write to TXS SIO2 The TXS SIO2 shift order remains unchanged Thus switching between MSB first and LSB first must be performed before writing data to the TXS SIO2 Transfer start Serial transfer is started by setting transfer data to the transmission shift register TXS SIO2 when the following two conditions are satisfied Serial interface channel 2 operation control bit CSIE2 1 Internal serial clock is stopped or SCK2 is a high level after 8 bit serial transfer Caution If CSIE2 is set to 1 after data write to TXS SIO2 transfer does not start Upon termination of 8 bit transfer serial transfer automatically stops and the interrupt request flag SRIF is set 473 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19 4 4 Limitations when UART mode is used In the
474. ration u u u u u uu u 20 3 Real Time Output Port Control Registers CHAPTER 21 INTERRUPT AND TEST FUNCTIONS u u u nnne tennis 21 1 Interrupt Function Types l U nennen nnns nnne nnn T J J 21 2 Interrupt Sources and Configuration u u 21 3 Interrupt Function Control Registers u u u u u 21 4 Interrupt Servicing Operations U 21 4 4 Non maskable interrupt request acknowledge operation 21 4 2 Maskable interrupt request acknowledge operation u 21 4 8 Software interrupt request acknowledge operation 21 4 4 Multiple interrupt servicing U u uuu nennen nnns 21 4 5 entente enne nnne nennen nente enne 21 5 Test Functlons 5 einander acere ier 21 5 1 Registers controlling the test function 21 5 2 Test input signal acknowledge operation CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION
475. rator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins itis possible that an internal inputlevel may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to Voo or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function FIP EEPROM IEBus are tra
476. re transferred to the program counter PC and branched This function is carried out when the BR instruction is executed Illustration 120 CHAPTER 5 CPU ARCHITECTURE 5 4 Operand Address Addressing The following various methods are available to specify the register and memory addressing which undergo manipulation during instruction execution 5 4 1 Implied addressing Function The register which functions as an accumulator A and AX in the general register is automatically illicitly addressed Of the uPD78054 and 78054Y subseries instruction words the following instructions employ implied addressing Instruction Register to be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register for storage of numeric values which become decimal correction targets ROR4 ROL4 A register for storage of digit data which undergoes digit rotation Operand format Because implied addressing can be automatically employed with an instruction no particular operand format is necessary Description example In the case of MULU X With an 8 bit x 8 bit multiply instruction the product of A register and X register is stored in AX In this example the A and AX registers are specified by implied addressing 121 CHAPTER 5 CPU ARCHITECTURE 5 4 2 Register addressing Function This addr
477. register CORCN is 1 and the correction address matches the fetch address value the correction branch request signal BR F7FDH is generated from the ROM correction circuit 538 CHAPTER 25 ROM CORRECTION 25 3 ROM Correction Control Registers The ROM correction is controlled with the correction control register CORCN 1 Correction control register CORCN This register controls whether or not the correction branch request signal is generated when the fetch address matches the correction address set in correction address registers 0 and 1 The correction control register consists of correction enable flags CORENO COREN 1 and correction status flags CORSTO CORST1 The correction enable flags enable or disable the comparator match detection signal and correction status flags show the values are matched CORCN is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CORCN to 00H Figure 25 3 Correction Control Register Format State lt gt lt Address after reset TUE 0 CORENO CORSTO FF8AH 00H R W Note CORSTO Correction address register 0 and fetch address match detection Symbol 7 6 5 4 lt gt lt 2 gt CORCN CORST1 o o o eorex const Not detected Detected ORENO Correction address register 0 and fetch address match detection control Disabled Enabled CORST1 Correction address register 1 and fetch address match detection Not
478. ress transmission The master executes slave chip selection by address transmission Wake up function The slave can easily discriminate address reception chip select with the wake up function which can be set reset by software When the wake up function is set the interrupt request signal INTCSIO is generated upon reception of a match address Thus when communication is executed with two or more devices the CPU except the selected slave devices can operate regardless of underway serial communications Acknowledge signal ACK control function The acknowledge signal to check serial data reception is controlled Busy signal BUSY control function The busy signal to report the slave busy state is controlled CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 2 SBI definition The SBI serial data format and the signals to be used are defined as follows Serial data to be transferred with SBI consists of three kinds of data address command and data Figure 16 11 shows the address command and data transfer timings Figure 16 11 SBI Transfer Timings Address Transfer 1 SBO 581 5 Bus Release Signal Address Command Transfer Command Signal SCKO lel MCK BUSY SBO SB1 Command Data Transfer SCKO 11 NE EE EE SB0 S81 X X X X X 0 sus Data Remark The dotted line ind
479. rial Operation Mode Register 0 Format and Figure 18 3 Serial Operation Mode Register 1 Format 81 CHAPTER 4 PIN FUNCTION uPD78054Y Subseries 4 2 4 P30 to P37 Port 3 These are 8 bit input output ports Beside serving as input output ports they function as timer input output clock output and buzzer output The following operating modes can be specified in 1 bit units 1 2 Port mode These ports function as 8 bit input output ports They can be specified in 1 bit units as input or output ports with port mode register 3 PM3 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL Control mode These ports function as timer input output clock output and buzzer output a TI1 and TI2 Pin for external count clock input to the 8 bit timer event counter b TOO to TO2 Timer output pins c PCL Clock output pin d BUZ Buzzer output pin 4 2 5 P40 to P47 Port 4 These are 8 bit input output ports Besides serving as input output ports they function as an address data bus The test input flag KRIF can be set to 1 by detecting a falling edge The following operating mode can be specified in 8 bit units 82 1 2 Port mode These ports function as 8 bit input output ports They can be specified in 8 bit units for input or output ports by using the memory expansion mode register MM When they are used as input port
480. rial interface status register ASIS Baud rate generator control register BRGC Nete Note Refer to Figure 6 15 Block Diagram of P70 and Figure 6 16 Block Diagram of P71 P72 440 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19 1 Serial Interface Channel 2 Block Diagram Internal Bus Asynchronous Asynchronous Serial Interface Serial Interface Status Register Mode Register Receive Buffer Direction Register Control Circuit ne mue PS1 PS0 cL SL ISRW SCK RXB SIO2 WZ Transmit Shift Register TXS SIO2 Direction Control Circuit Receive Shift RxD SI2 9 Register RXS P70 TxD SO2 p71 9 lt PM71 4 K Reception DANSER Transmission gt ica Control Control Circuit INTSR INTCSI2 Circuit ISRM INTST PM72 X ASCK SCK2 P72 Note Baud Rate Generator focfa 210 eal SCK 4 4 TXE RXE MDL3 MDL2 MDL1 MDL0 TPS3 TPS2 TPS1 TPSO Serial Operating Baud Rate Generator Mode Register 2 Control Register Internal Bus Note See Figure 19 2 for the baud rate generator configuration 441 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19 2 Baud Rate Generator Block Diagram CSIE2 Start Bit Sampling Clock A 5 Bit m Counter Q 9 O ASCK SCK2
481. rt from MSB or LSB Figure 16 9 shows the configuration of the serial I O shift register 0 SIOO and internal bus As shown in the figure MSB LSB can be read written in reverse form MSB LSB switching as the start bit can be specified with bit 2 CSIMO2 of the serial operating mode register 0 CSIMO Figure 16 9 Circuit of Switching in Transfer Bit Order Internal Bus 4 G ueni er See oer al Weiler treu afe LSB first MSB first Read Write Gate Read Write Gate 500 Latch 510 Serial Shift Register 0 5100 500 lt SCKO Start bit switching is realized by switching the bit order for data write to SIOO The SIOO shift order remains unchanged Thus switching between MSB first and LSB first must be performed before writing data to SIOO Transfer start Serial transfer is started by setting transfer data to the serial I O shift register 0 SIOO when the following two conditions are satisfied Serial interface channel 0 operation control bit CSIEO 1 Internal serial clock is stopped or SCKO is a high level after 8 bit serial transfer Caution If CSIEO is set to 1 after data write to SIOO transfer does not start Upon termination of 8 bit transfer serial transfer automatically stops and the interrupt request flag CSIIFO is set CHAPTER 16 SERIAL INTERFACE CHANNEL
482. ruction 1 instruction Remarks 1 One instruction is the minimum instruction execution time with the pre switchover CPU clock JOAOYDUMS 20 2 10 eui wnNnwIXeN 7 HOLIVHIN3DO 2010 2 YALdVHO CHAPTER 7 CLOCK GENERATOR 7 6 2 System clock and CPU clock switching procedure This section describes switching procedure between system clock and CPU clock Figure 7 10 System Clock and CPU Clock Switching Vpp RESET Interrupt Request Signal System Clock fxx fxx CPU Clock asig Minimum Maximum Speed Subsystem Clock High Speed Speed Operation Operation Operation Operation Wait 26 2 ms 5 0 MHz Internal Reset Operation 1 The CPU is reset by setting the RESET signal to low level after power on After that when reset is released by setting the RESET signal to high level main system clock starts oscillation At this time oscillation stabilization time 217 fx is secured automatically After that the CPU starts executing the instruction at the minimum speed of the main system clock 12 8 us when operated at 5 0 MHz 2 After the lapse of a sufficient time for the Vpp voltage to increase to enable operation at maximum speeds the processor clock control register PCC and oscillation mode selection register OSMS are rewritten and the maximum speed operation is carried out 3 Upon detection of a decrease of the Vpp voltage due to an interrupt request signal th
483. ruction is executed Therefore receive the data by manipulating the output latch of P27 by program as shown in Figure 17 26 For this timing refer to Figure 17 22 Figure 17 26 Slave Wait Release Reception Master device operation Writing Software operation data to SIO0 Setting Hardware operation o m CSIIFO Serial transmission wl 234 1 2 3 Slave device operation P27 Write P27 Software operation output FFH output 0 to al latch 1 E Setting Wait ic B T EN SR mere 387 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 4 Reception completion of salve In the reception completion processing of the slave check the bit 3 CMDD of the serial bus interface control register SBIC and bit 6 of the serial operation mode register 0 CSIMO when CMDD 1 This is to avoid the situation where the slave cannot judge which of the start condition and data comes first and therefore the wake up condition cannot be used when the slave receives the undefined number of data from the master 17 4 6 Restrictions in 2 bus mode The following restrictions are applied to the LPD78054Y subseries e Restrictions when used as slave device I2C bus mode 388 Subject Description Preventive measure LPD78052Y 78053Y 78054Y 78055Y 78056Y 78058Y 78P058Y IE 78064 R EM IE 780308 R EM If the wake up function is executed by setting the bit 5 of the serial
484. rupt request to servicing MOV A RXB RETI CHAPTER 20 REAL TIME OUTPUT PORT 20 1 Real Time Output Port Functions Data set previously in the real time output buffer register can be transferred to the output latch by hardware concurrently with timer interrupt requests or external interrupt request generation then output externally This is called the real time output function The pins that output data externally are called real time output ports By using a real time output a signal which has no jitter can be output This port is therefore suitable for control of stepping motors etc Port mode real time output port mode can be specified bit wise 477 CHAPTER 20 REAL TIME OUTPUT PORT 20 2 Real Time Output Port Configuration The real time output port consists of the following hardware Table 20 1 Real time Output Port Configuration Configuration Register Real time output buffer register RTBL RTBH Control register Port mode register 12 PM12 Real time output port mode register RTPM Real time output port control register RTPC Figure 20 1 Real time Output Port Block Diagram Internal Bus Real time Output Port Control Register BYTE EXTR Port Mode Register 12 PM12 INTP2 __J Real time Output Real time Output INTTM1 Output Trigger Buffer Register Buffer Register Control Circuit Higher 4 Bits Lower 4 Bits INTTM2 RTBH RTBL
485. rvals which are set by the ADTI Table 18 2 Interval Timing Through CPU Processing when the internal clock is operating CPU Processing Interval Time When using multiplication instruction 2 5Tsck 13TcPu When using division instruction 2 5Tsck 20TcPu External access 1 wait mode 2 5Tsck 9TcPu 2 5Tsck 7TcPu Other than above Remark Tsck 1 fsck fsck Serial clock frequency TcPu d fceu fcPu CPU clock set by bits 0 to 2 PCC0 to PCC2 of the processor clock control register PCC and bit 0 MCS of the oscillation mode selection register OSMS MAX a b a or b whichever is greater Figure 18 24 Operation Timing with Automatic Data Transmit Receive Function Performed by Internal Clock fcPu L LI LI I Teo Interval soi K o X X ps X oe X os X pe X r o K sn X o X pe K os X a Y s Y oe Xoo X v 1 fx Main system clock oscillation frequency fcpu CPU clock set by bits 0 to 2 PCCO to PCC2 of the processor clock control register PCC and bit 0 MCS of the oscillation mode select register OSMS 1 fcpu Tsck 1 fsck fsck Serial clock frequency 436 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 b When the automatic transmit receive function is used by the external clock If bit 1 CSIM11 of serial operation mode register 1 CSIM1 is cleared to 0 external clock operation is
486. ry flag Zero flag Register bank select flag Interrupt request enable flag Non maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data 16 bit immediate data or label Signed 8 bit data displacement value 27 1 3 Description of flag operation column Blank o Nt affected Cleared to 0 Set to 1 Set cleared according to the result Previously saved value is restored 563 27 INSTRUCTION SET 27 2 Operation List Instruction Group Mnemonic Operands Clock Note 1 Note 2 Operation r lt byte saddr byte saddr byte sfr byte G O no sfr byte Aer r lt saddr lt saddr A sfr lt sfr sfr A sfr lt A A laddr16 amp addr16 laddr16 A addr16 A PSW byte PSW lt byte A PSW lt PSW PSW N OO N N N SN PSW lt A A DE A DE 8 bit data DE A DE A transfer A HL A lt HL HL A HL A A HL byte A lt HL byte HL b
487. ry manipulation instruction RESET input sets TCL3 to 88H 294 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries Symbol 7 6 Figure 16 3 Timer Clock Select Register 3 Format 5 Address After Reset R W 4 3 2 1 0 TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 FF43H 88H R W Serial Interface Channel 0 Serial Clock Selection TCL32 TCL31 fxx 2 MCS 1 Setting prohibited fx 22 1 25 MHz fxx 22 fx 22 1 25 MHz fx 23 625 kHz fxx 23 fx 23 625 kHz fx 24 313 kHz fxx 24 fx 24 313 kHz fx 25 156 kHz fxx 25 fx 25 156 kHz fx 28 78 1 kHz 26 fx 26 78 1 kHz fx 27 39 1 kHz fxx 27 fx 27 39 1 kHz fx 28 19 5 kHz fxx 28 fx 28 19 5 kHz fx 29 9 8 kHz Setting prohibited Serial Interface Channel 1 Serial Clock Selection fxx 2 MCS 1 Setting prohibited fx 22 1 25 MHz fxx 22 fx 22 1 25 MHz fx 23 625 kHz 23 fx 23 625 kHz fx 24 313 kHz fxx 24 fx 24 313 kHz fx 25 156 kHz fxx 25 fx 25 156 kHz fx 28 78 1 kHz 26 fx 26 78 1 kHz fx 27 39 1 kHz fxx 27 fx 27 39 1 kHz fx 28 19 5 kHz fxx 28 fx 28 19 5 kHz fx 29 9 8 kHz Other than above Setting prohibited Caution When rewriting TCL3 to other data stop the serial transfer operation beforehand Re
488. ry out this manipulation during serial transfer Control the SCKO pin output level in the output mode internal system clock mode by manipulating the P27 output latch refer to 16 4 5 5 27 pin output manipulation 337 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 3 Other signals Figure 16 33 shows RELT and CMDT operations Figure 16 33 RELT and CMDT Operations 500 Latch 4 5 338 RELT CMDT Transfer start Serial transfer is started by setting transfer data to the serial I O shift register 0 SIOO when the following two conditions are satisfied Serial interface channel 0 operation control bit CSIEO 1 Internal serial clock is stopped or SCKO is at high level after 8 bit serial transfer Cautions 1 If CSIEO is set to 1 after data write to SIOO transfer does not start 2 Because it is necessary to set N ch open drain output to high impedance state for data reception write to SIOO in advance Upon termination of 8 bit transfer serial transfer automatically stops and the interrupt request flag CSIIFO is set Error detection In the 2 wire serial I O mode the serial bus SBO SB1 status being transmitted is fetched into the destination device that is serial I O shift register 0 SIOO Thus transmit error can be detected in the following way a Method of comparing SIOO data before transmission to that after transmission In this case if two data differ fro
489. s LPD78058Y 60 Kbytes 1024 bytes uPD78P058Y 60 KbytesNote 1 1024 bytesNote 1 1024 bytesNote 2 Notes 1 The capacities of internal PROM and internal high speed RAM can be changed by means of the memory size switching register IMS 2 The capacity of internal high speed RAM can be changed by means of the internal expansion RAM size switching register IXS External Memory Expansion Space 64 Kbytes Minimum instruction execution time changeable from high speed 0 4 us In main system clock 5 0 MHz operation to ultra low speed 122 us In subsystem clock 32 768 kHz operation Instruction set suited to system control Bit manipulation possible in all address spaces Multiply and divide instructions ports 69 N ch open drain ports 4 8 bit resolution A D converter 8 channels 8 bit resolution D A converter 2 channels Serial interface 3 channels 3 wire serial I O 2 wire serial 2 bus mode 1 channel e 9 wire serial I O mode Automatic transmit receive function 1 channel 3 wire serial I O UART mode 1 channel Timer Five channels 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel 22 vectored interrupt sources 2 test inputs Two types of on chip clock oscillators main system clock and subsystem clock Supply voltage Vpp 2 0 to 6 0 V 49 CHAPTER 2 OUTLINE uPD78054Y Subseries
490. s on chip pull up resistors can be used by defining the pull up resistor option register L PUOL Control mode These ports function as low order address data bus pins ADO to AD7 in external memory expansion mode When pins are used as an address data bus the on chip pull up resistor is automatically disabled CHAPTER 4 PIN FUNCTION uPD78054Y Subseries 4 2 6 P50 to P57 Port 5 These are 8 bit input output ports Besides serving as input output ports they function as an address bus Port 5 can drive LEDs directly The following operating modes can be specified in 1 bit units 1 2 Port mode These ports function as 8 bit input output ports They can be specified in 1 bit units as input output ports with port mode register 5 PM5 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL Control mode These ports function as high order address bus pins A8 to A15 in external memory expansion mode When pins are used as an address bus the on chip pull up resistor is automatically disabled 4 2 7 P60 to P67 Port 6 These are 8 bit input output ports Besides serving as input output ports they are used for control in external memory expansion mode P60 to P63 can drive LEDs directly The following operating modes can be specified in 1 bit units 1 2 Port mode These ports function as 8 bit input output ports They can be specified in 1 b
491. s other than port pins 1 2 Pin Name Input Output Function After Reset Alternate Function INTPO 00 00 P01 TIO1 INTP2 External interrupt request inputs with specifiable valid edges rising P02 INTP3 edge falling edge both rising and falling edges INTP4 P04 INTP5 P05 NTP6 P06 510 25 5 0 51 Serial interface serial data input P20 512 P70 RxD SO0 P26 SB1 SO1 Output Serial interface serial data output P21 502 P71 TxD SBO Input P25 SIO Serial interface serial data input output SB1 output 26 500 SCKO P27 Input SCK1 Serial interface serial clock input output P22 output SCK2 P72 ASCK STB Output Serial interface automatic transmit receive strobe output P23 BUSY Input Serial interface automatic transmit receive busy input P24 RxD Input Asynchronous serial interface serial data input P70 SI2 TxD Output Asynchronous serial interface serial data output P71 SO2 ASCK Input Asynchronous serial interface serial clock input P72 SCK2 TIOO External count clock input to 16 bit timer TMO POO INTPO TIO1 Input Capture trigger signal input to capture register CROO P01 INTP1 TH External count clock input to 8 bit timer TM1 P33 2 External count clock input to 8 bit timer TM2 P34 TOO 16 bit timer TMO output also used for 14 bit PWM output P30 TO1 Output 8 bit timer TM1 output P31 TO2 8 bit timer TM2 output P32 PCL
492. s pointer ADTP is decremented Then transmit data 2 T2 is transferred from the buffer RAM to SIO1 ii Upon completion of transmission of 6 bytes Refer to Figure 18 16 b When transmission of the sixth byte is completed the interrupt request flag CSIIF1 is not set The first pointer value is set to ADTP again iii 7th byte transmission point Refer to Figure 18 16 c Transmit data 1 T1 is transferred from the buffer RAM to SIO1 again When transmission of the first byte is completed ADTP is decremented Then transmit data 2 T2 is transferred from the buffer RAM to SIO1 Figure 18 16 Buffer RAM Operation in 6 Byte Transmission in Repeat Transmit Mode 1 2 a Before transmission FADFH FAC5H Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 FACOH Transmit data 6 T6 427 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 428 FADFH FAC5H FACOH FADFH FAC5H FACOH Figure 18 16 Buffer RAM Operation in 6 Byte Transmission in Repeat Transmit Mode 2 2 b Upon completion of transmission of 6 bytes Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 CSIIF1 c 7th byte transmission point Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4
493. sed Select a serial clock frequency with TPSO to TPS3 Be sure then to set MDLO to MDL3 to 1 1 1 1 The serial clock frequency is calculated by the following formula fxx ial clock f So Serial clock frequency 2 x 16 Hz Remarks 1 fx Main system clock oscillation frequency 2 fx Main system clock frequency fx or fx 2 3 n Value set in TPSO to TPS3 1 lt n lt 11 4 k Value set in MDLO to MDL3 0 lt k lt 14 471 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 2 Communication operation In the 3 wire serial I O mode data transmission reception is performed in 8 bit units Data is transmitted received bit by bit in synchronization with the serial clock Transmit shift register TXS SIO2 and receive shift register RXS shift operations are performed in synchronization with the fall of the serial clock SCK2 Then transmit data is held in the SO2 latch and output from the SO2 pin Also receive data input to the SI2 pin is latched in the receive buffer register RXB SIO2 on the rise of SCK2 At the end of an 8 bit transfer the operation of the TXS SIO2 or RXS stops automatically and the interrupt request flag SRIF is set Figure 19 12 3 Wire Serial I O Mode Timing SCK2 512 502 SRIF End of Transfer E Transfer Start at the Falling Edge of SCK2 472 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 3 4 MSB LSB switching as the start bit 3 wire serial I O mode enables to select t
494. sed in free running mode and measuring by restarting the timer in synchronization with the edge of the signal input to the TIOO POO pin 1 Pulse width measurement with free running counter and one capture register When the 16 bit timer register TMO is operated in free running mode see register settings in Figure 8 17 and the edge specified by external interrupt mode register 0 INTMO is input to the TIOO POO pin the value of TMO is taken into 16 bit capture compare register 01 CRO1 and an external interrupt request signal INTPO is set Any of three edge specifications can be selected rising falling or both edges by means of bits 2 and 3 ES10 and ES11 of INTMO For valid edge detection sampling is performed at the interval selected by means of the sampling clock selection register SCS and a capture operation is only performed when a valid level is detected twice thus eliminating noise with a short pulse width Figure 8 17 Control Register Settings for Pulse Width Measurement with Free Running Counter and One Capture Register a 16 bit timer mode control register TMCO 03 02 01 OVFO b Capture compare control register 0 CRCO Free Running Mode 2 CRC01 CRC00 oO 0 CR00 set as compare register CR01 set as capture register Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement See the description
495. set to 1 by falling edge detection ADO to AD7 P50 to P57 Port 5 8 bit input output port LED can be driven directly Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software 8 to A15 N ch open drain input output port On chip pull up resistor can be specified by mask option Port 6 Mask ROM version only LEDs can be driven directly 8 bit input output port Input output mode can be When used as an input port an specified in 1 bit units on chip pull up resistor can be used by software ASTB 60 Port 7 3 bit input output port Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software SI2 RxD SO2 TxD SCK2 ASCK CHAPTER 3 PIN FUNCTION uPD78054 Subseries 1 Port pins 3 3 Input Output P120 to P127 Function Port 12 8 bit input output port Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software After Reset Alternate Function RTPO to RTP7 P130 to P131 Port 13 2 bit input output port Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software ANOO to ANO1 61 CHAPTER 3 PIN FUNCTION uPD78054 Subseries 2 Pin
496. sfer direction specification 369 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 370 d Acknowledge signal ACK The acknowledge signal indicates that the transferred serial data has definitely been received This signal is used between the sending side and receiving side devices for confirmation of correct data transfer In principle the receiving side device returns an acknowledge signal to the sending device each time it receives 8 bit data The only exception is when the receiving side is the master device and the 8 bit data is the last transfer data the master device outputs no acknowledge signal in this case The sending side that has tranferred 8 bit data waits for the acknowledge signal which will be sent from the receiving side If the sending side device receives the acknowledge signal which means a successful data transfer it proceeds to the next processing If this signal is not sent back from the slave device this means that the data sent has not been received by the slave device and therefore the master device outputs a stop condition signal to terminate subsequent transmissions Figure 17 18 Acknowledge Signal SCL 1 2 3 4 5 6 7 8 9 ow Y pepe IT P e Stop condition If the SDAO SDA1 pin level changes from low to high while the SCL pin is high this transition is defined as a stop condition signal The stop condition signal is output from the master to the slave device to terminate a serial transfe
497. speed RAM is possible IMS is set with an 8 bit memory manipulation instruction RESET input sets IMS to C8H Figure 26 1 Memory Size Switching Register Format uPD78P054 i5 Address RW Symbol 7 6 Reset 5 4 3 2 IMS 2 RAM1 RAMO 0 ROMS ROM2 ROM1 ROM0 FFFOH C8H R W ROMO Internal ROM Capacity selection 16 Kbytes 24 Kbytes 32 Kbytes Setting prohibited RAM2 RAM1 Internal High Speed RAM Capacity Selection 512 bytes 0 1024 bytes Other than above Setting prohibited The IMS settings to give the same memory map as mask ROM versions are shown in Table 26 3 Table 26 3 Examples of Memory Size Switching Register Settings wPD78P054 Relevant Mask ROM Version IMS Setting uPD78052 uPD78053 uPD78054 549 CHAPTER 26 uPD78P054 78P058 26 2 Memory Size Switching Register uPD78P058 The uPD78P058 allows users to define its internal ROM and high speed RAM sizes using the memory size switching register IMS sothatthe same memory mapping as that of a mask ROM version with a different size internal ROM and high speed RAM is possible IMS is set with an 8 bit memory manipulation instruction RESET input sets IMS to CFH Figure 26 2 Memory Size Switching Register Format uPD78P058 After Symbol 7 6 5 4 3 2 1 0 Address IMS RAM2 RAMt RAMO 0 ROMs ROM2 ROM1 ROMO R W 16 Kbytes 24 Kbyt
498. speed RAM size selection 0 512 bytes 0 1024 bytes Other than above Setting prohibited Note The values after reset depend on the product See Table 22 3 Table 22 3 Values when the Memory Size Switching Register is Reset Part number Reset value uPD78052 78052Y uPD78053 78053Y uPD78054 78054Y uPD78055 78055Y uPD78056 78056Y uPD78058 78058Y 517 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22 3 External Device Expansion Function Timing Timing control signal output pins in the external memory expansion mode are as follows 1 2 3 4 5 RD pin Alternate function P64 Read strobe signal output pin The read strobe signal is output in data accesses and instruction fetches from external memory During internal memory access the read strobe signal is not output maintains high level WR pin Alternate function P65 Write strobe signal output pin The write strobe signal is output in data access to external memory During internal memory access the write strobe signal is not output maintains high level WAIT pin Alternate function P66 External wait signal input pin When the external wait is not used the WAIT pin can be used as an input output port During internal memory access the external wait signal is ignored ASTB pin Alternate function P67 Address strobe signal output pin Timing signal is output without regard to the data accesses a
499. ss CHAPTER 4 PIN FUNCTION uPD78054Y Subseries Figure 4 1 Pin Input Output Circuit of List 1 2 Schmitt Triggered Input with Hysteresis Characteristics pullup Voo enable deta output disable be Vpp P ch IN OUT N ch 77 lt L Voo Do IE Pe Voo pullup enable data ch IN OUT L output N ch disable 77 input enable Type 10 A pullup efe Pan enable data open drain output disable Vpp IN OUT Type 5 E pullup enable P ch IN OUT output disable Type 11 pullup VDD D ll P ch enable output disable comparator OIN OUT N ch P ch rt T N chT Vner Threshold voltage 89 CHAPTER 4 PIN FUNCTION uPD78054Y Subseries Figure 4 1 Pin Input Output Circuit of List 2 2 Type 12 A Type 13 D gt 9IN OUT pullup Po B enable Pan data output disable gt 2s data P ch T IN OUT Vpop output disable RD sa input enable medium breakdown analog output input buffer voltage N ch 90 Type 13 B zh Vpp nal pies IE feedback Option cut off o IN OUT P ch data output disable J gt T
500. ss in normal operating mode Ground potential Internally connected Directly connect to the Vss pin PROM programming mode setting When 5 V or 12 5 V is applied to the VPP pin or a low level voltage is applied to the RESET the PROM programming mode is set High voltage application for PROM programming mode setting and program write verify A0 to A16 Address bus D0 to D7 Data bus PROM enable input program pulse input Read strobe input to PROM Program program inhibit input in PROM programming mode Positive power supply Ground potential 63 CHAPTER 3 PIN FUNCTION uPD78054 Subseries 3 2 Description of Pin Functions 3 2 1 00 to P07 Port 0 These are 8 bit input output ports Besides serving as input output ports they function as an external interrupt request input an external count clock input to the timer a capture trigger signal input and crystal connection for subsystem oscillation The following operating modes can be specified in 1 bit units 1 Port mode and P07 function as input only ports and P01 to P06 function as input output ports P01 to P06 be specified for input or output ports in 1 bit units with a port mode register 0 When they are used as input ports on chip pull up resistors can be used to them by defining the pull up resistor option register L PUOL 2 Control mode In this mode these ports function as an ext
501. ss the memory that is manipulated when an instruction is executed the uPD78054 78054Y Subseries is provided with many addressing modes with a high operability Especially at addresses corresponding to data memory area particular addressing modes are possible to meet the functions of the special function registers SFRs and general registers This area is between FDOOH and FFFFH for the uPD78052 and 78052Y and between FBOOH and FFFFH for the uPD78053 78053Y 78054 78054Y 78P054 78055 78055Y 78056 78056Y 78058 78058Y 78P058 and 78P058Y The data memory space is the entire 64K byte space 0000H to FFFFH Figure 5 9 to 5 16 show the data memory addressing modes For details of each addressing refer to 5 4 Operand Address Addressing Figure 5 9 Data Memory Addressing uPD78052 78052Y i Special Function Registers SFRs SFR Addressing 256 x 8 bits By b General Registers n Addressing 32 x 8 bits Short Direct Addressing Internal High speed RAM 512 x 8 bits FE20H Y FE1FH FD00H FCFFH Reserved FAE0H FADE Direct Addressing Internal Buffer RAM 32 x 8 bits Register Indirect FACOH Addressing FABFH Reserved Based Addressing FA80H FA7FH Based Indexed Addressing External Memory 47744 x 8 bits 4000H 3FFFH Internal ROM 16384 x 8 bits 0000H Y 101 CHAPTER 5 CPU ARCHITECTURE FE20H FE1FH FBOOH
502. ster Table U10087J 78K 0 Series Application Note Basics III U10182J U10182E Caution Theabove documents are subject to change without prior notice Be sure to use the latest version document when starting design 13 Development Tool Documents User s Manuals Document No Document name RA78KO0 Assembler Package Operation Japanese U11802J English U11802E Assembly Language U11801J U11801E Structured Assembly U11789J U11789E RA78K Series Structured Assembler Preprocessor U12323J EEU 1402 CC78KO0 C Compiler Operation U11517J U11517E Language U11518J U11518E CC78KO0 C Compiler Application Note Programming know how U13034J EEA 1208 CC78K Series Library Source File U12322J PG 1500 PROM Programmer U11940J U11940E PG 1500 Controller PC 9800 Series MS DOS Base EEU 704 EEU 1291 PG 1500 Controller IBM PC Series PC DOS Base EEU 5008 U10540E IE 78K0 NS To be prepared To be prepared IE 78001 R A To be prepared To be prepared IE 780308 NS EM1 To be prepared To be prepared IE 780308 R EM U11362J U11362E EP 78230 EEU 985 EEU 1515 EP 78054GK R EEU 932 EEU 1468 SM78KO System Simulator Windows Base Reference U10181J U10181E SM78K Series System Simulator External component user open interface specifications U10
503. struction prevents the SDAO pin from outputting a low level when instruction 8 is executed This instruction sets the P27 pin in the output mode because the P27 pin must be in the output mode in the 12C bus mode This instruction clears the output latch of the P25 pin to 0 because the output latch of the P25 pin must be set to 0 the 2 bus mode This instruction sets the P25 pin in the output mode because the P25 pin must be in the output mode in the 2 bus mode Remark RELI Bit 0 of serial bus interface control register SBIC 389 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 17 4 7 SCKO SCL P27 pin output manipulation The SCKO SCL P27 pin can execute static output via software in addition to outputting the normal serial clock The value of serial clocks can also be arbitrarily set by software the SIO SBO SDAO and SOO SB1 SDAt pins are controlled with the RELT and CMDT bits of serial bus interface control register SBIC The SCKO SCL P27 pin output should be manipulated as described below 1 In 3 wire serial I O mode and 2 wire serial I O mode The output level of the SCKO SCL P27 pin is manipulated by the P27 output latch 1 Setthe serial operating mode register 0 CSIMO SCKO pin is set in the output mode and serial operation is enabled SCKO 1 while serial transfer is stopped 2 Manipulate the content of the P27 output latch by executing the bit manipulation instruction Figure 17 27
504. t Ao CY Am 1 lt Am x 1 time CY lt Az Ao CY Am 1 Am x 1 time lt HL s o HL z 4 lt HL s o lt HL z 4 Aa o lt HL z 4 o lt HL z 4 lt HL s o NI SN INI NI Y IN N E Decimal Adjust Accumulator after Addition Decimal Adjust Accumulator after Subtract CY lt saddr bit CY lt sfr bit CY lt A bit CY PSW bit CY c HL bit saddr bit CY sfr bit CY A bit CY PSW bit CY HL bit CY N CY saddr bit CY sfr bit CY A bit CY PSW bit CY HL bit saddr bit CY sfr bit CY A bit CY PSW bit CY HL bit CY Bit manipulate m coj m co co nmiconm co co Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed Remarks 1 One instruction clock cycle is one cycle of the CPU clock fceu selected by the processor clock control register PCC 2 This clock cycle applies to internal ROM program 3 n is the number of waits when external memory expansion area is read from 4 m is the number of waits when external memory expansion area is written to 568 27 INSTRUCTION SET Instruction Group Mnemonic Operands CY saddr bit Operation CY lt CY saddr bit
505. t and buzzer output RESET input sets port 3 to input mode Figure 6 9 shows a block diagram of port 3 Figure 6 9 P30 to P37 Block Diagram Vpp e WRpeuo E Mac PUO3 5 m a RD 1 5 P30 TOO Output Latch i P32 TO2 E P30 to P37 2172 n Ou e P34 TI2 P35 PCL P36 BUZ WRem P37 PM30 PM37 4 Alternate Function PUO Pull up resistor option register PM Port mode register RD Port 3 read signal WR Port 3 write signal 141 CHAPTER 6 PORT FUNCTIONS 6 2 6 Port 4 Port 4 is an 8 bit input output port with output latch P40 to P47 pins can specify the input mode output mode in 8 bit units with the memory expansion mode register MM When P40 to P47 pins are used as input ports an on chip pull up resistor can be used to them in 8 bit units with pull up resistor option register L PUOL The test input flag KRIF can be set to 1 by detecting falling edges Alternate function includes address data bus function in external memory expansion mode RESET input sets port 4 to input mode Figures 6 10 and 6 11 show a block diagram of port 4 and block diagram of falling edge detection circuit respectively Figure 6 10 P40 to P47 Block Diagram Voo e WRpeuo z ome PUO4 gt gt P ch RD WRrort s c Output Latch
506. t cycle 28 x TI input cycle TI1 input edge cycle TI1 input cycle 28 x TI1 input cycle TI1 input edge cycle 2 x 1 fx 2 x 1 fx 29 x 1 fx 210 x 1 fx 2 x 1 fx 2 x 1 fx 400 ns 800 ns 102 4 us 204 8 us 400 ns 800 ns 22 x 1 fx 23 x 1 fx 210 x 1 fx 211 x 1 fx 22 x 1 fx 23 x 1 fx 800ns 1 6 204 8 us 409 6 us 800ns 1 6 us 23 x 1 fx 24 x 1 fx 211 x 1 fx 212 x 1 fx 23 x 1 fx 24 x 1 fx 1 6us 3 2 409 6 us 819 2 us 1 6 3 2 ns 24 x 1 fx 25 x 1 fx 212 x 1 fx 213 x 1 fx 24 x 1 fx 2 x 1 fx 3 2 us 6 4 819 2 us 1 64 ms 3 2 uis 6 4 us 25 x 1 fx 26 x 1 fx 213 x 1 fx 214 x 1 fx 25 x 1 fx 26 x 1 fx 6 4 us 12 8 1 64 ms 3 28 ms 6 4us 12 8 us 26 x 1 fx 27 x 1 fx 214 x 1 fx 215 x 1 fx 26 x 1 fx 27 x 1 fx 12 8 us 25 6 8 28 ms 6 55 ms 12 8 us 25 6 us 27 x 1 fx 28 x 1 fx 215 x 1 fx 218 x 1 fx 27 x 1 fx 28 x 1 fx 25 6 us 51 2 us 6 55 ms 13 1 ms 25 6 us 51 2 us 28 x 1 fx 29 x 1 fx 216 x 1 fx 217 x 1 fx 28 x 1 fx 29 x 1 fx 51 2 us 102 4 us 13 1 ms 26 2 ms 51 2 us 102 4 us 29 x 1 fx 210 x 1 fx 217 x 1 fx 218 x 1 fx 29 x 1 fx 210 x 1 fx 102 4 us 204 8 us 26 2 ms 52 4 ms 102 4 us 204 8 us 211 x 1 fx 212 x 4 fx 219 x 4 fx 220 x 1 fx 211 x 1 fx 212 x 1 fx 409 6 us 819 2 us 104 9 ms 209 7 ms 409 6 us 819 2 us
507. t in the CROO is constantly compared with the 16 bit timer register TMO count value and an interrupt request INTTMOO is generated if they match It can also be used as the register which holds the interval time when TMO is set to interval timer operation and it can be used as the register which sets the pulse width when TMO is set to PWM output operation When CROO is used as a capture register it is possible to select the valid edge of the INTPO TIOO pin or the INTP1 TIO1 pin as the capture trigger The INTPO TIOO or INTP1 TIO1 valid edge is set by means of external interrupt mode register 0 INTMO If CROO is specified as a capture register and capture trigger is specified to be the valid edge of the INTPO TIOO pin the situation is as shown in the following table Table 8 5 INTPO TIOO Pin Valid Edge and CROO Capture Trigger Valid Edge ES11 ES10 INTPO TIOO Pin Valid Edge CR00 Capture Trigger Valid Edge Falling edge Rising edge Rising edge Falling edge Setting prohibited Both rising and falling edges No capture operation CR00 is set by a 16 bit memory manipulation instruction After RESET input the value of CROO is undefined Cautions 1 Set the data of PWM 14 bits to the higher 14 bits of CROO At this time clear the lower 2 bits to 00 2 Setavalue other than 0000H to CROO When the event counter function is used therefore one pulse cannot be counted 3 If the new value of CROO is less than the value o
508. t of Interrupt Mask Flag Register 1L When Symbol lt gt 6 lt i gt 0 Address Reset R W 5 4 3 lt 2 gt MK1L WK 1 1 ofo ADMK TMMK 2 1 FFE6H FFH R W wrwk Standby mode control by watch timer 0 1 Enables releasing the standby mode Disables releasing the standby mode Caution Be sure to set bits 3 through 6 to 1 508 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 3 Key return mode register KRM This register is used to set enable disable of standby function clear by key return signal port 4 falling edge detection KRM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets KRM to 02H Figure 21 21 Key Return Mode Register Format When Symbol 7 lt gt lt 0 gt Address Reset R W To e mw KRIF Key Return Signal 0 Not detected Detected port 4 falling edge detection Standby Mode Control by Key Return Signal Standby mode release enabled Standby mode release disabled Caution When port 4 falling edge detection is used be sure to clear KRIF to 0 not cleared to 0 automatically 21 5 2 Test input signal acknowledge operation 1 Internal test signal The internal test input signal INTWT is generated with watch timer overflow and the WTIF flag is set If not masked with bit 7 WTMK of interrupt mask flag register 1L MK1L at this time a standby release signal is generated The watch function
509. t significant bit MSB When up to the least significant bit LSB is held termination of A D conversion the SAR contents are transferred to the A D conversion result register ADCR A D conversion result register ADCR This register holds the A D conversion result Each time A D conversion terminates the conversion result is loaded from the successive approximation register SAR ADCR is read with an 8 bit memory manipulation instruction RESET input makes ADCR undefined Sample amp hold circuit The sample amp hold circuit samples each analog input signal sequentially applied from the input circuit and sends it to the voltage comparator This circuit holds the sampled analog input voltage value during A D conversion Voltage comparator The voltage comparator compares the analog input to the series resistor string output voltage Series resistor string The series resistor string is connected between AVrero and AVss and generates a voltage to be compared to the analog input ANIO to ANI7 pins These are 8 channel analog input pins to input analog signals to undergo A D conversion to the A D converter Pins other than those selected as analog input by the A D converter input select register ADIS can be used as input output ports Cautions 1 Use ANIO to ANI input voltages within the specified range If a voltage higher than orlowerthan AVssis applied even if within the absolute maximum ratings the converted
510. t the same potential as the Vss pin when not using the A D converter pin This is an A D converter analog power supply pin Keep it at the same potential as the Vss pin when not using the A D converter Caution AVDpppin is the power supply pin of the analog circuit and it supplies power also to the input circuit of ANIO P10 to ANI7 P17 Therefore always supply the voltage of the same level as Voo as shown in Figure 14 2 also in applications which switch to backup power supply Figure 14 2 Handling of AVpp Pin gt AVREFO Main power Capacitor supply for back up CHAPTER 14 A D CONVERTER 14 3 A D Converter Control Registers The following three types of registers are used to control the A D converter A D converter mode register ADM A D converter input select register ADIS External interrupt mode register 1 INTM1 1 A D converter mode register ADM This register sets the analog input channel for A D conversion conversion time conversion start stop and external trigger ADM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ADM to 01H 269 CHAPTER 14 A D CONVERTER Figure 14 3 A D Converter Mode Register Format After Address Reset Symbol 7 6 5 R W 4 3 2 1 0 ADM CS TRG FR1 FRO ADM3 ADM2 ADM1 FF80H 01H R W ADM1 Analog Input Channel Selection A D Conversion Time Selection fx 2 5
511. tage source is high this will result in parallel connection to the series resistor string between the AVrero pin and the AVss pin and there will be a large reference voltage error 279 CHAPTER 14 A D CONVERTER 6 Interrupt request flag ADIF The interrupt request flag ADIF is not cleared even if the A D converter mode register ADM is changed If an analog input pin is changed during A D conversion the A D conversion result and ADIF for the pre change analog input may have been set immediately before the ADM rewrite In this case if ADIF is read immediately after the ADM rewrite ADIF may be set despite the fact that the A D conversion for the post change analog input has not ended When the A D conversion is stopped and then resumed clear the ADIF before it is resumed Figure 14 12 A D Conversion End Interrupt Request Generation Timing ADM Rewrite ADIF is set but ANIm Start of ANIm Conversion conversion has not ended ADM Rewrite Start of ANIn Conversion A D Conversion ADCR 7 AVppo The pin is the analog circuit power supply pin and supplies power to the input circuits of ANIO P10 to 7 17 Therefore be sure to apply the same voltage as Von to this pin even when the application circuit is designed so as to switch to a backup battery as shown in Figure 14 13 Figure 14 13 Handling of AVpp Pin pl AVREFO Main power Capacitor supply for back up 280 CHAP
512. te to SIO1 Aorjpejpsjpeppejpejpripo 1 1 00 07 06 5 4 9 224040 1 1 00 Remark CSIE1 Bit 7 of serial operating mode register 1 CSIM1 429 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 4 Synchronization Control 430 Busy control and strobe control are functions for synchronizing sending and receiving between the master device and slave device By using these functions it is possible to detect bit slippage during sending and receiving a Busy control Option Busy control is a function which causes the master device s serial transmission to wait when the slave device outputs a busy signal to the master device and maintain the wait state while that busy signal is active When the busy control option is used the conditions shown below are necessary Bit 5 ATE of serial operation mode register 1 CSIM1 should be set at 1 Bit 1 BUSY1 of the auto data send and receive control register ADTC should be set at 1 The system configuration between the master device and slave device in cases where the busy control option is used is shown in Figure 18 18 Figure 18 18 System Configuration When the Busy Control Option is Used Master Device uPD78054 78054Y Sub series Slave Device The master device inputs the busy signal output by the slave device to pin BUSY P24 In sync with the fall of the serial clock the master devi
513. ted PCC 04H OSMS 00H Main system clock oscillation stops while low level is applied to RESET pin With the main system clock selected one of the six CPU clock types 0 4 us 0 8 us 1 6 us 3 2 us 6 4 us 12 8 us 5 0 MHz can be selected by setting the PCC and OSMS With the main system clock selected two standby modes the STOP and HALT modes are available In a system where the subsystem clock is not used the current consumption in the STOP mode can be further reduced by specifying with bit 6 FRC of the PCC not to use the feedback resistor The PCC can be used to select the subsystem clock and to operate the system with low current consumption 122 us when operated at 32 768 kHz With the subsystem clock selected main system clock oscillation can be stopped with the PCC The HALT mode can be used However the STOP mode cannot be used Subsystem clock oscillation cannot be stopped The main system clock is divided and supplied to the peripheral hardware The subsystem clock is supplied to 16 bittimer event counter the watch timer and clock output functions only Thus 16 bit timer event counter when selecting watch timer output for count clock operating with subsystem clock the watch function and the clock output function can also be continued in the standby state However since all other peripheral hardware operate with the main system clock the peripheral hardware also stops if the main system clock is stopped Exce
514. ted to the 32 byte area from FACOH to FADFH The buffer RAM is used to store transmit receive data of serial interface channel 1 in three wire serial I O mode with automatic transfer receive function If the three wire serial mode with automatic transfer receive function is not used the buffer RAM can also be used as normal RAM Buffer RAM can also be used as normal RAM 3 Internal expansion RAM uPD78058 78058Y 78P058 78P058Y only Internal expansion RAM is allocated to the 1024 byte area from F400H to F7FFH 5 1 3 Special Function Register SFR area An on chip peripheral hardware special function register SFR is allocated in the area FFOOH to FFFFH Refer to Table 5 6 Special Function Register List in 5 2 3 Special Function Register SFR Caution Do not access addresses where the SFR is not assigned 5 1 4 External memory space The external memory space is accessible by setting the memory expansion mode register MM External memory space can store program table data etc and allocate peripheral devices 100 CHAPTER 5 CPU ARCHITECTURE 5 1 5 Data memory addressing The method to specify the address of the instruction to be executed next or the address of a register or memory to be manipulated when an instruction is executed is called addressing The address of the instruction to be executed next is addressed by the program counter PC for details refer to 5 3 Instruction Address Addressing To addre
515. ten to BRGC during a communication operation baud rate generator output is disrupted and communication cannot be performed normally Therefore data must not be written to BRGC during a communication operation Remarks 1 fx Main system clock oscillation frequency 2 fx Main system clock frequency fx or fx 2 3 MCS Oscillation mode selection register OSMS bit 0 4 n Value set in TPSO to TPS3 1 lt lt 11 5 Figures in parentheses apply to operation with fx 5 0 MHz 458 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit receive clock generated is either a signal scaled from the main system clock or a signal scaled from the clock input from the ASCK pin i Generation of baud rate transmit receive clock by means of main system clock The transmit receive clock is generated by scaling the main system clock The baud rate generated from the main system clock is obtained with the following expression Baud rate c Hz 2 x k 16 where fx Main system clock oscillation frequency Main system clock frequency fx or fx 2 n Value set in TPSO to TPS3 1 lt n lt 11 k Value set in MDLO to MDL3 0 lt k x 14 Table 19 5 Relation between Main System Clock and Baud Rate fx 2 5 0 MHz fx 4 19 MHz MCS 1 MCS 0 MCS 1 MCS 0 BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error 96
516. ter Format u 539 25 4 Storing Example to EEPROM when one place is corrected 540 25 5 Connecting Example with EEPROM using 2 wire serial I O mode 540 25 6 Initialization Routine on c ei e duka a bie fupe eerta 541 25 7 ROM Correction Operation 542 25 8 ROM Correction Example susu eee re cae dia cde crea t ees 543 25 9 Program Transition Diagram when one place is corrected 544 25 10 Program Transition Diagram when two places are corrected 545 26 1 Memory Size Switching Register Format uPD78P054 a 549 26 2 Memory Size Switching Register Format uPD78P058 sse 550 26 3 Internal Expansion RAM Size Switching Register Format 2 551 26 4 Page Program Mode uu u 554 26 5 Page Program Mode Timing nr 555 26 6 Byte Program Mode Flowchart essen 556 26 7 Byte Program Mode TIMING i i e tte pe ce cer red Ye eg 557 26 8 PROM oder ree o ie 558
517. terpret the register format For the circled bit number the bit name is defined as a reserved word in RA78K 0 and in CC78K 0 already defined in the header file named sfrbit h O To learn the function of a register whose register name is known Refer to Appendix D Register Index O To know the electrical specifications of the uPD78054 and 78054Y Subseries Refer to separately available Data Sheet O To know application examples of the functions provided in the uPD78054 and 78054Y Subseries Refer to Application Note separately provided Caution The application examples in this manual are created for Standard quality grade products for general electric equipment When using the application examples in this manual for purposes which require Special quality grades thoroughly examine the quality grade of each part and circuit actually used 10 Chapter Organization This manual divides the descriptions for the uPD78054 and 78054Y Subseries into different chapters as shown below Read only the chapters related to the device you use uPD78054 uPD78054Y Subseries Subseries Chapter 1 Outline uPD78054 Subseries Chapter 2 Outline uPD78054Y Subseries Chapter 3 Pin Function uPD78054 Subseries Chapter 4 Pin Function uPD78054Y Subseries Chapter 5 Architecture Chapter 6 Port Functions Chapter 7 Clock Generator Chapter 8 16 Bit Timer Event Counter Chapter 9 8 Bit Timer Eve
518. terrupt Request Generation Timing a Stop bit length 1 ss ifo oo START INTST b Stop bit length 2 iis START INTST Caution Do not rewrite the asynchronous serial interface mode register ASIM during a transmit operation If rewriting of the ASIM register is performed during transmission subsequent transmit operations may not be possible the normal state is restored by RESET input Whether transmission is in progress or not can be determined by software using a transmission completion interrupt INTST or the interrupt request flag STIF set by the INTST 463 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 d Reception When the bit 6 RXE of the asynchronous serial interface mode register ASIM is set 1 a receive operation is enabled and sampling of the RxD pin input is performed RxD pin input sampling is performed using the serial clock specified by ASIM When the RxD pin input becomes low the 5 bit counter of the baud rate generator refer to Figure 19 2 starts counting and at the time when the half time determined by specified baud rate has passed the data sampling start timing signal is output If the RxD pin input sampled again as a result of this start timing signal is low it is identified as a start bit the 5 bit counter is initialized and starts counting and data sampling is performed When character data a parity bit and one stop bit are detected after the start bit reception of one frame
519. terval timer When the watchdog timer operated as interval timer the interrupt mask flag TMMK4 and priority specify flag TMPRA are validated and the maskable interrupt request INTWDT can be generated Among maskable interrupt requests the INTWDT default has the highest priority The interval timer continues operating in the HALT mode but it stops in STOP mode Thus set bit 7 RUN of WDTM to 1 before the STOP mode is set clear the interval timer and then execute the STOP instruction Cautions 1 Once bit4 WDTM4 of WDTM is set to 1 with the watchdog timer mode selected the interval timer mode is not set unless RESET input is applied 2 Theinterval time just after setting with WDTM may be shorter than the set time by a maximum of 0 5 96 3 When the subsystem clock is selected for CPU clock watchdog timer count operation is stopped Table 11 5 Interval Timer Interval Time 211 x 1 fxx 21 x 1 fx 410 us 212 x 1 fx 819 us 212 x 1 fxx 212 x 1 fx 819 us 213 x 1 fx 1 64 ms 213 x 1 fxx 213 x 1 fx 1 64 ms 214 x 1 fx 3 28 ms 214 x 1 fxx 214 x 1 fx 3 28 ms 215 x 1 fx 6 55 ms 215 x 1 fxx 215 x 1 fx 216 x 1 fx 13 1 ms 216 x 1 fxx 216 x 1 fx 13 1 ms 217 x 1 fx 26 2 ms 217 x 1 fxx 6 55 ms 217 x 1 fx 26 2 ms 218 x 1 fx 52 4 ms 219 x 1 fxx Remarks 1 fxx 2 fx Main system clock oscillation frequency
520. th a 1 bit or 8 bit memory manipulation instruction RESET input sets SBIC to 00H Symbol lt gt 0 5b 4 35 2 lt gt 0 Address After Reset R W SBIC BSYE ACKD sex wos D RELD CMDT RELT FF61H 00H R W R W RELT When RELT 1 500 latch is set to 1 After 500 latch setting automatically cleared to 0 Also cleared to 0 when CSIEO 0 R W When CMDT 1 500 latch is cleared 0 After 500 latch clearance automatically cleared to 0 Also cleared to 0 when CSIEO 0 Remark CSIEO Bit 7 of serial operating mode register 0 CSIMO 335 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries c Interrupt timing specify register SINT SINT is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SINT to 00H Symbol 7 lt 6 Address After Reset R W gt b lt 4 gt 3 2 1 0 cw s es sees eo e ror m R W SIC INTCSI0 Interrupt Factor Selection CSIIFO is set upon termination of serial interface channel 0 transfer CSIIFO is set upon bus release detection or termination of serial interface channel 0 transfer R CLD SCKO P27 Pin LevelNote2 0 Low level 1 High level Notes 1 Bit 6 CLD is a read only bit 2 When CSIEO 0 CLD becomes 0 Caution Be sure to set bits O to 3 to 0 Remark CSIIFO Interrupt request flag corresponding to INTCSIO CSIEO Bit 7 of serial operating mode register 0 CSIMO 336 CHA
521. the data transfer interval by means of automatic transmission reception with ADTI busy control refer to 18 4 3 4 a Busy control option is disabled Remarks 1 fxx 2 fx 3 fsck Serial clock frequency Main system clock frequency fx or fx 2 Main system clock oscillation frequency 404 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18 4 Serial Interface Channel 1 Operations The following three operating modes are available to the serial interface channel 1 Operation stop mode 3 wire serial I O mode 3 wire serial mode with automatic transmit receive function 18 4 1 Operation stop mode Serial transfer is not carried out in the operation stop mode Thus power consumption can be reduced The serial I O shift register 1 SIO1 does not carry out shift operation either and thus it can be used as an ordinary 8 bit register In the operation stop mode the P20 SI1 P21 SO1 P22 SCK1 P23 STB and P24 BUSY pins can be used as ordinary input output ports 1 Register setting The operation stop mode is set with the serial operating mode register 1 CSIM1 CSIM1 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM1 to 00H Symbol 27 6 5 4 3 2 1 0 Address After Reset R W CSIM1 CSIE1 DIR ATE 0 cow cse FF68H 00H R W CSIM11 Note 1 x Note 1 x Note 1 x Note 1 x Note 1 x Shift Register 1 Operation Operation stop Serial Clock Counter Operation C
522. the following functions Watch timer nterval timer The watch timer and the interval timer can be used simultaneously 1 Watch timer When the 32 768 kHz subsystem clock is used a flag WTIF is set at 0 5 second or 0 25 second intervals When the 4 19 MHz standard 4 194304 MHz main system clock is used a flag WTIF is set at 0 5 second or 0 25 second intervals Caution 0 5 second intervals cannot be generated with the 5 0 MHz main system clock You should Switch to the 32 768 kHz subsystem clock to generate 0 5 second intervals 2 Interval timer Interrupt requests INTTM3 are generated at the preset time interval Table 10 1 Interval Timer Interval Time When operated at When operated at When operated at THOSE MIN 5 0 MHz 4 19 MHz 32 768 kHz 24 x 1 fw 25 x 1 fw 28 x 1 fw 27 x 1 fw 28 x 1 fw 29 x 1 fw Remark Main system clock frequency or fx 2 fx Main system clock oscillation frequency fxr Subsystem clock oscillation frequency fw Watch timer clock frequency fxx 2 or fxr 241 CHAPTER 10 WATCH TIMER 10 2 Watch Timer Configuration The watch timer consists of the following hardware Table 10 2 Watch Timer Configuration Counter 5 bits x 1 Timer clock select register 2 TCL2 Watch timer mode control register TMC2 Control register 10 3 Watch Timer Control Registers The following two types of registers
523. this mode can be cleared upon interrupt request it enables intermittent operations to be carried out However because a wait time is necessary to secure an oscillation stabilization time after the STOP mode is cleared select the HALT mode if it is necessary to start processing immediately upon interrupt request In any mode all the contents of the register flag and data memory just before standby mode setting are held The input output port output latch and output buffer statuses are also held Cautions 1 The STOP mode can be used only when the system operates with the main system clock subsystem clock oscillation cannot be stopped The HALT mode can be used with either the main system clock or the subsystem clock 2 When proceeding to the STOP mode be sure to stop the peripheral hardware operation and execute the STOP instruction 3 The following sequence is recommended for power consumption reduction of the A D converter when the standby function is used first clear bit 7 CS of A D converter mode register ADM to 0 to stop the A D conversion operation and then execute the HALT or STOP instruction 525 CHAPTER 23 STANDBY FUNCTION 23 1 2 Standby function control register A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register OSTS OSTS is set with an 8 bit memory manipulation instruction RESET input sets
524. timer clock select register 1 TCL1 is input When TM1 overflows TM2 is incremented with the overflow signal as the count clock Either the rising or falling edge can be selected When the TM1 and 2 counted values match the values of 8 bit compare registers 10 and 20 CR10 and CR20 TM1 and TM2 are cleared to 0 and the interrupt request signal INTTM2 is generated Figure 9 12 External Event Counter Operation Timings with Rising Edge Specified LT LI U IJ ULI U UUU LI TM1 TM2 Count Value X0000 X0001 0002 K0003 000400054 1 X N X0000X0001X0002A0003X CR10 CR20 2 Caution Even if the 16 bit timer event counter mode is used when the TM1 count value matches the CR10 value interrupt request INTTM1 is generated and the F F of 8 bit timer event counter output control circuit 1 is inverted Thus when using 8 bit timer event counter as 16 bit interval timer set the INTTM1 mask flag TMMK1 to 1 to disable INTTM1 acknowledgment When reading the 16 bit timer register TMS count value use the 16 bit memory manipulation instruction 236 CHAPTER 9 8 TIMER EVENT COUNTERS 1 AND 2 3 Square wave output operation Operates as square wave output with any selected frequency at intervals of the count value preset to 8 bit compare registers 10 and 20 CR10 CR20 When setting the count value set the value of higher 8 bits to CR20 and the value of lower 8 bits to CR10 The TO2 P32 p
525. tion 11 Note 3 Input SO1 CMOS output SCK1 Input SCK1 CMOS output Notes 1 If the external clock input has been selected with CSIM11 set to 0 set bit 1 BUSY 1 and bit 2 STRB of the automatic data transmit receive control register ADTC to 0 0 2 Can be used freely as port function 3 Can be used as P20 CMOS input output when only transmitter is used clear bit 7 RE of ADTC to 0 Remark x Don t care PMxx Port mode register Pxx Port output latch 410 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 b Automatic data transmit receive control register ADTC ADTC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ADTC to 00H Symbol 7 lt 6 gt lt 5 gt lt 4 gt lt 3 gt lt 2 lt 0 gt Address After Reset R W gt lt l gt ADTC ARLD ERCE STRB BUSY1BBUSYO FF69H 00H R WNete 1 BUSY1BUSYO Busy Input Control Not using busy input Busy input enable active high Busy input enable active low Detection of termination of automatic transmission reception This bit is set to 0 upon suspension of automatic transmission reception or when ARLD 0 During automatic transmission reception This bit is set to 1 when data is written to SIO1 ERR Error Detection of Automatic Transmit Receive Function 0 No error This bit is set to O when data is written to SIO1 1 Error occurred
526. tion Write SIOO COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSIO SCL SDAO 5 0 lt Address 5100 lt Data oo SS oeoo r C Xannnnnnis if eri br ob VA ASA MAS 2 AQI VD7 ADGADSADA4AD3 Slave device operation Write SIOO COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSIO CSIEO P25 PM25 PM27 5100 lt 260050 J pp oo 45 27 rj ir r r r 379 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries Figure 17 22 Data Transmission from Master to Slave Both Master and Slave Selected 9 Clock Wait 2 of 3 b Data Master device operation SIO0 lt Address Write SIO0 SIO0 Data col 0 0 0 Ee cmoo f RELO Ub yf MMMM SS o P27 H Medi 0 ge ve 271 ACKE d C J o RELT CLC WREL SIC INTCSIO SCL 1 2 iS 14 9 1 lal 3 MI 5 SDAO COPS V D7 AD6 XD5XD4XD3 4 SIO0 lt FFH 222 Write 5100 fac col VA A A A XA A X X X X X RELD L l j _ cp 3 P27 r l5 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSIO CSIEO P25 PM25 PM27 rjir r r r rJ r 380 CHAPTER 17 SERIAL INTERFACE CHANNEL 0
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528. trol register 1 U enne 225 TMC2 Watch timer mode control 245 TMS 16 bittiMer register u L IR pp ere e pep UR es 223 TOCO 16 bit timer output control register u 186 TOC1 8 bit timer output control register u nennen nnne rene rennen nenne 226 TXS Transmit shitt register sas itus tuc t 443 W WDTM Watchdog timer mode register l l u u u u ua 252 Watch timer mode control register TMC2 a 245 597 598 Major revisions by edition and revised chapters are shown below Edition APPENDIX E REVISION HISTORY Major revisions from previous version P40 ADO P47 AD7 pin I O circuit types were changed Connection method of unused AVner pin was changed Revised Chapters CHAPTER 2 Pin Functions Caution on OVFO flag operations was added CHAPTER 6 16 Bit Timer Event Counter Interval time of interval timer was corrected CHAPTER 8 Watch Timer Buzzer output frequency was corrected CHAPTER 11 Buzzer Output Control Circuit Description of settings of port mode register and output latch was added CHAPTER 14 Serial Interface Channel 0 CHAPTER 15 Serial Interface Channel 1 CHAPTER 16 Serial Interface Channel 2
529. ttings in Square Wave Output Mode a 16 bit timer mode control register TMCO 03 TMC02 01 OVFO CN S b Capture compare control register 0 CRCO Clear amp start on match of TMO and CROO CRC02 CRCO1 CRCOO ew e Te on CROO set as compare register c 16 bit timer output control register TOCO OSPT OSPE 04 1 50 LVRO 01 TOEO p L TOO Output Enabled Inversion of output on match of and CROO Specified TOO output F F initial value No inversion of output on match of and CRO1 One shot pulse output disabled Remark 0 1 Setting O or 1 allows another function to be used simultaneously with square wave output See the description of the respective control registers for details CHAPTER 8 16 TIMER EVENT COUNTER Figure 8 30 Square Wave Output Operation Timing CoutCiock LI U U L L T LT LI E LIT U TMO Count Value Y 0000 X 0001 X 0002 X X N1 X N 0002X X Na X N TOO Pin Output Table 8 7 16 Bit Timer Event Count Square Wave Output Ranges INTTMO Minimum Pulse Width Maximum Pulse Width MCS 1 MCS 0 Resolution MCS 1 MCS 0 2 x 00 input cycle 216 x TIOO input cycle 00 input edge cycle 2 x 1 fx 216 x 1 fx 1 fx 400 ns 13 1 ms 200 ns 2 x 1 fx 400 ns 22 x 1 fx 800 ns 216 x 4 f
530. u 490 MKOL Interrupt mask flag register OL cote u ects adie ce ost pus aska eels 490 MK1L Interrupt mask flag register 1L 490 508 MM Memory expansion mode register 154 516 Memory size switching register IMS a 517 549 550 OSMS Oscillation mode selection register u 164 OSTS Oscillation stabilization time select register 516 P ehe to t tea uf dehors aes etta det o imde cedes s 134 P1 Port EBR A A Ioan 136 P2 ueni 137 139 eina attente REDE 141 P4 suu a 142 5 Porras dene pd iiu eite 143 P6 iet e ERECTA eU RR ee uha Lb fen 144 P7 POE ass dre bed ete ect dct c teat la c bone de ated Fa oa et e sbs 146 P12 Pott12 RARE e ec DE gc bate e 148 P13 Port 8 cena eat dta ded ep vin Edad ie E uN a 149 PCC Processor clock control register Uu enne nennen nnne snnt 161 PMO Port riode register O eite eiu ret oin e ie eel eed 150 PM1 Port mode register 4 x i aeo a a be tette nette ea 150 PM2 mode register 2 ris RE eere dent 150
531. uPD78054Y Subseries Figure 17 22 Data Transmission from Master to Slave Both Master and Slave Selected 9 Clock Wait 3 of 3 c Stop Condition Master device operation Write SIOO 5100 lt Data 5100 lt Address col LX XXX XXX XN X X ACKD I R co 1 4 27 WUP L 4 1 L ay A _ a o WREL L iam He E 2 SCL 1 lal lal 4 lel 7 deat 1 lel fal 4 SDAO 07 06 0504 03 02 01 00 X Z VA6JASAA KAS Write SIO0 LX KX A A AG A OU To cnr dE Ren o _ lt 4 we a UUAA P27 WUP BSYE H CMDT L L 21 SIC INTCSIO CSIEO P25 PM25 PM27 L 381 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries Figure 17 23 Data Transmission from Slave to Master Both Master and Slave Selected 9 Clock Wait 1 of 3 a Start Condition to Address Master device operation Write SIOO COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSIO SCL SDAO SIO0 lt Address SIO0 lt FFH IA A A A A ACA XXX X A 1 lel la VAS XAS M AM RNO X07 0605404403 Slave device operation Write SIOO COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL
532. ue set register 0 nennen nnne nnns 283 DACS1 D A conversion value set register 1 a 283 DAM D A converter mode register 284 External interrupt mode register 189 492 External interrupt mode register 272 492 595 APPENDIX D REGISTER INDEX I IFOH Interrupt request flag register OH 489 IFOL Interrupt request flag register 0L 489 IF1L Interrupt request flag register 11 44222 4 00 00 nnne nnne 489 508 IMS Memory size switching register u 517 549 550 INTM0 External interrupt mode register I 0000 nnne nnne nnne 189 492 INTM1 External interrupt mode register 272 492 IXS Internal expansion RAM size switching register 551 Interrupt mask flag register OH MK0H 490 Interrupt mask flag register OL 490 Interrupt mask flag register 1L MK1L oe eee uuu 490 508 Interrupt timing specify register 300 318 336 354 364 375 K KRM Key return mode register iere mH RE MR RR Red A 155 509 M MKOH Interrupt mask flag register nnne
533. unction CSIM Operation 25 P25 26 P26 PM27 P27 Mode Start Bit 3 wire Serial I O mode See Section 16 4 2 3 wire serial I O mode operation SBI mode See section 16 4 3 SBI mode operation Note 2 Note 2 SB1 N ch P25 CMOS open drain 2 wire serial input output input output SCKO N ch Note 2 Note 2 mode MSB SBO N ch open drain open drain P26 CMOS input output input output Put output R W Wake up Function Control e 0 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release 1 when CMDD RELD 1 matches the slave address register SVA data in SBI mode R COI Slave Address Comparison Result FlagNete 4 Slave address register SVA not equal to serial I O shift register 0 SIOO data Slave address register SVA equal to serial I O shift register 0 SIOO data R W Operation stopped Operation enabled Notes 1 Bit 6 is a read only bit 2 Can be used freely as port function 3 Be sure to set WUP to 0 when the 2 wire serial I O mode 4 When CSIE0 0 COI becomes 0 Remark x don t care PMxx Port mode register Pxx Port output latch 334 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries b Serial bus interface control register SBIC SBIC is set wi
534. und pattern where high current is present Do not fetch signals from the oscillator Take special note of the fact that the subsystem clock oscillator is a circuit with low level amplification so that current consumption is maintained at low levels Figure 7 8 shows examples of incorrect oscillator connection Figure 7 8 Examples of Incorrect Oscillator Connection 1 2 a Wiring of connection b Signal lines intersect circuits is too long each other PORTn n 0 7 12 13 IC X2 xi 77 77 Remark When using subsystem clock replace X1 and X2 with 1 and 2 respectively Further insert resistors in series on the side of XT2 166 CHAPTER 7 CLOCK GENERATOR Figure 7 8 Examples of Incorrect Oscillator Connection 2 2 d Current flows through the grounding line of the oscillator potential at points A B and C fluctuate VoD Pnm IC X2 IC X2 X1 High Current X1 77 High Current e Signals are fetched IC 2 E 77 c Changing high current is too near a signal conductor Remark When using a subsystem clock replace X1 and X2 with XT1 and XT2 respectively Also insert resistors in series on the XT2 side Cautions 2 In Figure 7 8 f XT2 and X1 are wired in parallel Thus the cross talk noise of X1 may increase with XT2 resulting in malfunctioning To prevent that from occurring it is recommended to
535. unications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions
536. unt clock TCL2 sets the watch timer count clock and buzzer output frequency 250 CHAPTER 11 WATCHDOG TIMER Symbol 7 6 Figure 11 2 Timer Clock Select Register 2 Format 5 4 3 2 1 0 After R W Reset TCL2 TCLe7 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 00H R W TCL21 Watchdog Timer Count Clock Selection MCS 1 fx 2 625 kHz fx 2 313 kHz fx 2 313 kHz fx 2 156 kHz fx 2 156 kHz fx 2 78 1 kHz fx 2 78 1 kHz fx 2 39 1 kHz fx 2 39 1 kHz fx 2 19 5 kHz fx 2 19 5 kHz fx 2 9 8 kHz fx 2 9 8 kHz fx 2 4 9 kHz fx 2 2 4 kHz fx 2 1 2 kHz Watchdog Timer Count Clock Selection fxx 2 MCS 1 fx 2 39 1 kHz fx 2 19 5 kHz fxr 32 768 kHz TCL26 Buzzer Output Frequency Selection MCS 1 Buzzer output disable fxx 2 fx 2 9 8 kHz fx 2 4 9 kHz fxx 2 fx 2 4 9 kHz fx 2 2 4 kHz fxx 2 fx 2 2 4 kHz 2 1 2 kHz Setting prohibited Caution When rewriting TCL2 to other data stop the timer operation beforehand Remarks 1 2 9m s fx Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency Subsystem clock oscillation frequency x Don t care MCS Bit 0 of oscillation mode selection register OSMS Figures in parentheses apply to operation with fx 5 0 MHz or fxr 32 768
537. ure 24 2 Timing of Reset Input by RESET Input Reset Period Oscillation Stop Stabilization JH AQ N N NC PVP A X Oscillation Normal Operation Time Wait Reset Processing Figure 24 3 Timing of Reset due to Watchdog Timer Overflow Reset Period Oscillation Oscillation dX Nx VE VI V NC Normal Operation Stabilization Reset Processing Stop Time Wait Figure 24 4 Timing of Reset Input in STOP Mode by RESET Input X1 Normal Operation RESET Internal Reset Signal Delay Port Pin x1 Normal Operation Watchdog Timer Overflow Internal Reset Signal Port Pin X1 STOP Instruction Execution Stop Status Normal Operation lt Oscillation Stop RESET Internal Reset Period Oscillation Stop Oscillation I lt Stabilization Normal Operation Time Wait Reset Processing Reset Signal Port Pin 534 CHAPTER 24 RESET FUNCTION Table 24 1 Hardware Status after Reset 1 2 Hardware Status after Reset Program counter PC Note1 The contents of reset vector tables 0000H and 0001H are set Stack pointer SP Undefined Program status word PSW 02H RAM Data memory Undefined Note2 General register Undefined Note2 Port Output latch Ports 0 to 3 Port 7 Port 12 Port 13 PO to P3 P
538. ure 6 18 P130 and P131 Block Diagram Vpp WRPuo z PUO13 b P ch RD ox 9 a WRrort g s Output Latch P180 ANOO zi P130 and P131 P131 ANO1 WRem us PM130 PM131 CNET PUO Pull up resistor option register PM Port mode register RD Port 13 read signal WR Port 13 write signal 149 CHAPTER 6 PORT FUNCTIONS 6 3 Port Function Control Registers The following four types of registers control the ports Port mode registers PMO to PM3 PM5 to PM7 PM12 PM13 Pull up resistor option register PUOH PUOL Memory expansion mode register MM Key return mode register KRM 1 Port mode registers PMO to PM3 PM5 to PM7 PM12 PM13 150 These registers are used to set port input output in 1 bit units to PM5 to PM7 12 and 13 are independently set with a 1 bit or 8 bit memory manipulation instruction RESET input sets registers to FFH When port pins are used as the dual function pins set the port mode register and output latch according to Table 6 5 Cautions 1 Pins P00 and 07 input only pins 2 As port 0 has a dual function as external interrupt request input when the port function output mode is specified and the output level is changed the interrupt request flag is set When the output mode is used therefore the interrupt mask flag should be set to 1 beforehand 3 The memory
539. urrently being serviced is generated it is not acknowledged as a multiple interrupt An interrupt request that is not acknowledged due to interrupt disable or low priority is reserved The reserved interrupt request is acknowledged after the current interrupt servicing is completed and one instruction of the main processing is executed A multiple interrupt is not acknowledged while a non maskable interrupt is being serviced Table 21 4 shows the interrupt requests that are capable of multiple interrupts and Figure 21 16 shows examples of multiple interrupts Table 21 4 Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing Multiple Interrupt Maskable Interrupt Request Request Non maskable Interrupt PR 0 PR 1 Interrupt being Serviced Request 1 E 0 IE 1 Non maskable interrupt ISP 0 Maskable interrupt ISP 1 Software interrupt Remarks 1 E Multiple interrupt enable 2 D Multiple interrupt disable 3 ISP and IE are the flags contained in PSW ISP 0 An interrupt with higher priority is being serviced ISP 1 An interrupt request is not accepted or an interrupt with lower priority is being serviced IE 0 Interrupt request acknowledge is disabled IE 1 Interrupt request acknowledge is enabled 4 flag contained in PROL PROH and PR1L PR 0 Higher priority level 1 Lower priority level 503 CHAPTER 21 INTERRUPT AND TEST FUN
540. us 28 x 1 fx 51 2 us 28 x 1 fx 51 2 us 28 x 1 fx 51 2 us 29 x 1 fx 102 4 us 29 x 1 fx 102 4 29 x 1 fx 102 4 us 210 x 4 fx 204 8 us 211 x 1 fx 409 6 us Remarks 1 2 MCS Oscillation mode selection register OSMS bit 0 3 Values in parentheses when operated at fx 5 0 MHz MCS 1 MCS 0 22 x 1 fx 217 x 1 fx 218 x 1 fx 800 ns 26 2 ms 52 4 ms 23 x 1 fx 218 x 1 fx 219 x 1 fx 1 6 us 52 4 ms 104 9 ms 2 x 1 fx 219 x 1 fx 220 x 1 fx 3 2 us 104 9 ms 209 7 ms 25 x 1 fx 220 x 1 fx 221 x 1 fx 6 4 us 209 7 ms 419 4 ms 26 x 1 fx 221 x 1 fx 222 x 1 fx 12 8 us 419 4 ms 838 9 ms 27 x 1 fx 222 x 1 fx 223 x 1 fx 25 6 us 838 9 ms 1 7 s 28 x 1 fx 223 x 1 fx 224 x 1 fx 51 2 us 1 7 s 3 4 s 29 x 1 fx 224 x 1 fx 225 x 1 fx 102 4 us 3 4 s 6 7 s 210 x 1 fx 225 x 1 fx 226 x 1 fx 204 8 us 6 7 s 13 4 s 212 x 1 fx 227 x 1 fx 228 x 1 fx 819 2 us 26 8 s 53 7 s fx Main system clock oscillation frequency 211 x 1 fx 409 6 us 212 x 1 fx 819 2 us 219 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 AND 2 9 2 8 Bit Timer Event Counters 1 and 2 Configurations The 8 bit timer event counters 1 and 2 consist of the following hardware Table 9 5 8 Bit Timer Event Counters 1 and 2 Configurations Item Configuration Timer register 8 bits x 2 TM1 TM2 Register Compare register 8 bits x 2 CR10 CR20 Timer out
541. us 6 4 us 209 7 ms 419 4 ms 8 2 us 6 4 us 25 x 1 fx 26 x 1 fx 221 x 1 fx 222 x 1 fx 25 x 1 fx 26 x 1 fx 6 4 us 12 8 us 419 4 ms 838 9 ms 6 4 12 8 us 26 x 1 fx 27 x 1 fx 222 x 4 fx 223 x 1 fx 26 x 1 fx 27 x 1 fx 12 8 us 25 6 us 838 9 ms 1 7 s 12 8 us 25 6 us 27 x 1 fx 28 x 1 fx 223 x 1 fx 224 x 1 fx 27 x 1 fx 28 x 1 fx 25 6 us 51 2 us 1 7 s 3 4 s 25 6 us 51 2 us 28 x 1 fx 29 x 1 fx 224 x 1 fx 225 x 1 fx 28 x 1 fx 29 x 1 fx 51 2 us 102 4 us 8 4 s 6 7 s 51 2 us 102 4 us 29 x 1 fx 210 x 1 fx 225 1 fx 226 x 1 fx 29 x 1 fx 210 x 1 fx 102 4 us 204 8 us 6 7 s 13 4 s 102 4 us 204 8 us 211 x 1 fx 212 x 1 fx 227 x 1 fx 228 x 1 fx 211 x 1 fx 212 x 1 fx 409 6 us 819 2 us 26 8 s 53 7 s 409 6 us 819 2 us Other than above Setting prohibited Remarks 1 fx Main system clock oscillation frequency 2 MCS Oscillation mode selection register OSMS bit 0 3 TCL10 to TCL13 Bits 0 to 3 of timer clock select register TCL1 4 Values in parentheses when operated at fx 5 0 MHz 235 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 AND 2 2 External event counter operations The external event counter counts the number of external clock pulses to be input to the 1 pin with 2 channel 8 bit timer registers 1 and 2 TM1 and 2 TM1 is incremented each time the valid edge specified with the
542. use open drain buffers are used for the serial clock pin SCL and the serial data bus pin SDAO or SDA1 on the I C bus The signals used in the 2 bus mode are described in Table 17 4 Figure 17 13 Example of Serial Bus Configuration Using I C Bus Voo Voo 8 Master CPU Slave CPU1 SCL Serial clock SCL Serial data bus SDAO SDA1 SDAO SDA1 Slave CPU2 SCL SDAO SDA1 Slave IC SCL SDA 367 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries 1 bus mode functions In the I C bus mode the following functions are available a Automatic identification of serial data Slave devices automatically detect and identifies start condition data and stop condition signals sent in series through the serial data bus b Chip selection by specifying device addresses The master device can select a specific slave device connected to the I2C bus and communicate with it by sending in advance the address data corresponding to the destination device c Wake up function An interrupt request is generated during slave operation when the received address matches the value of slave address register SVA the interrupt request also occurs when the stop condition is detected Therefore CPUs other than the selected slave device on the 12 bus can perform independent operations during the serial communication d Acknowledge signal ACK control function The master device and a s
543. used with lt Vpp the other pins that are not used as analog outputs must be set as follows Set PM13x bit of the port mode register 13 PM13 to 1 input mode and connect the pin to Vss Set PM13x bit of the port mode register 13 PM13 to 0 output mode and the output latch to 0 to output low level from the pin 286 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries The uPD78054 subseries incorporates three channels of serial interfaces Differences between channels 0 1 and 2 are as follows Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1 Refer to CHAPTER 19 SERIAL INTERFACE CHANNEL 2 for details of the serial interface channel 2 Table 16 1 Differences between Channels 0 1 and 2 Serial Transfer Mode 3 wire serial I O Clock selection Channel 0 fxx 2 fxx 22 fxx 23 fxx 24 fxx 25 26 27 fxx 28 external clock TO2 output Channel 1 fxx 2 fxx 22 fxx 23 fxx 24 fxx 25 26 fxx 2 fxx 28 external clock TO2 output Channel 2 Baud rate generator output Transfer method MSB LSB switchable as the start bit MSB LSB switchable as the start bit Automatic transmit receive function MSB LSB switchable as the start bit Transfer end flag Serial transfer end interrupt request flag CSIIFO Serial transfer end interrupt request flag CSIIF1 Serial transfer end interrupt request flag
544. ut Operation Using Software Trigger Set OCH to TMCO TMO count start TMO Count Value 0000 Xooy X N N X X Koo0e OSPT x INTTM01 INTTMOO x TOO Pin Output Caution The 16 bit timer register starts operation at the moment a value other than 0 0 0 operation stop mode is set to 01 to TMCO3 respectively 209 CHAPTER 8 16 BIT TIMER EVENT COUNTER 2 One shot pulse output using external trigger If the 16 bit timer mode control register TMCO capture compare control register 0 CRCO and the 16 bit timer output control register TOCO are set as shown in Figure 8 33 a one shot pulse is output from the TOO P30 pin with a TIOO POO valid edge as an external trigger Any of three edge specifications can be selected rising falling or both edges as the valid edges for the 00 00 pin by means of bits 2 and 3 ES10 and ES11 of external interrupt mode register 0 INTMO When a valid edge is inputto the TIOO POO pin the 16 bit timer event counter is cleared and started and output is activated by the count values set beforehand in 16 bit capture compare register 01 CRO1 Thereafter output is inactivated by the count value set beforehand in 16 bit capture compare register 00 CROO Caution When outputting one shot pulses external trigger is ignored if generated again Figure 8 33 Control Register Settings for One Shot Pulse Output Operation Using External Tri
545. ut mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used by software ANOO to ANO1 77 CHAPTER 4 PIN FUNCTION uPD78054Y Subseries 2 Pins other than port pins 1 2 Pin Name Input Output Function External interrupt request inputs with specifiable valid edges rising edge falling edge both rising and falling edges After Reset Alternate Function 00 00 P01 TIO1 P02 P04 P05 P06 Serial interface serial data input P25 SBO SDAO P20 P70 RxD Serial interface serial data output P26 SB1 SDA1 P21 P71 TxD Serial interface serial data input output P25 SI0 SDAO P26 SO0 SDA1 P25 SI0 SBO P26 SO0 SB1 Serial interface serial clock input output P27 SCL P22 P72 ASCK P27 SCK0 Output Serial interface automatic transmit receive strobe output P23 Input Serial interface automatic transmit receive busy input P24 Input Asynchronous serial interface serial data input P70 SI2 Output Asynchronous serial interface serial data output P71 SO2 Input Asynchronous serial interface serial clock input P72 SCK2 Input External count clock input to 16 bit timer TMO Capture trigger signal input to capture register CROO External count clock input to 8 bit timer TM1 External count clock input to 8 bit timer TM2 POO INTPO 1 1 P33 P34
546. ut output input output R W Wake up Function Control ete 0 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after detecting start condition when CMDD 1 matches the slave address register SVA data in PC bus mode R Slave Address Comparison Result Flag Note Slave address register SVA not equal to serial I O shift register 0 5100 data 1 Slave address register SVA equal to serial I O shift register 0 SIOO data R W Operation stopped Operation enabled Notes 1 Bit 6 is a read only bit 2 Can be used freely as port function 3 Be sure to set WUP to 0 when the 2 wire serial I O mode 4 When CSIE0 0 COI becomes 0 Remark x don t care PMxx Port mode register Pxx Port output latch 362 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 uPD78054Y Subseries b Serial bus interface control register SBIC SBIC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SBIC to 00H Symbol lt gt 0 5 4 lt gt lt gt lt 0 gt Address After Reset R W 2 SBIC BSYE ACKT CMDD RELD CMDT RELT FF61H 00H R W R W RELT When RELT 1 SOO latch is set to 1 After 500 latch setting automatically cleared to 0 Also cleared to 0 when CSIEO 0 R W cmpr When CMDT 1 500 latch is cleared to 0 After 500 l
547. ut output pin c RxD TxD Asynchronous serial interface serial data input output pins d ASCK Asynchronous serial interface serial clock input output pin Caution When this port is used as a serial interface the I O and output latches must be set according to the function the user requires For the setting see to the operation mode setting list in Table 19 2 Serial Interface Channel 2 4 2 9 P120 to P127 Port 12 84 These are 8 bit input output ports Besides serving as input output ports they function as a real time output port The following operating modes can be specified in 1 bit units 1 Port mode These ports function as 8 bit input output ports They can be specified in 1 bit units as input or output ports with port mode register 12 PM12 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register H PUOH 2 Control mode These ports function as real time output ports RTPO to RTP7 outputting data in synchronization with a trigger CHAPTER 4 PIN FUNCTION uPD78054Y Subseries 4 2 10 P130 and P131 Port 13 These are 2 bit input output ports Besides serving as input output ports they are used for D A converter analog output The following operating modes can be specified in 1 bit units 1 Port mode These ports function as 2 bit input output ports They can be specified in 1 bit units as input or output ports with port mode register 13
548. utomatically employed when the PUSH POP subroutine call and RETURN instructions are executed or the register is saved reset upon generation of an interrupt request Stack addressing enables to address the internal high speed RAM area only Description example In the case of PUSH DE Operation code 10110101 128 CHAPTER 6 PORT FUNCTIONS 6 1 Port Functions The uPD78054 and 78054Y subseries units incorporate two input ports and sixty seven input output ports Figure 6 1 shows the port configuration Every port is capable of 1 bit and 8 bit manipulations and can carry out considerably varied control operations Besides port functions the ports can also serve as on chip hardware input output pins Figure 6 1 Port Types Port 5 Port 0 Port 6 Port 1 Port 7 Port 2 Port 12 Port 3 Port 13 P37 P40 P47 K 8 gt Port 4 129 CHAPTER 6 PORT FUNCTIONS Table 6 1 Port Functions uPD78054 subseries 1 2 Pin Name Function Alternate Function Input only INTPO TIOO P01 INTP1 TIO1 P02 Input output mode can be specified in 1 bit INTP2 Port 0 units INTP3 P04 8 bit input output port When used as an input port an on chip INTP4 P05 pull up resistor can be used by software INTP5 P06 INTP6 P07 Input only XT1 Port 1 8 bit input output port P10 to P17 ANIO to ANI7 Input output mode can be specified in 1 bit units When used as an input port an on chip pull up resistor can be used
549. utput enable 8 Bit Timer Event Counter 1 Timer Output F F Control Inverted operation disable Inverted operation enable LVR1 8 Bit Timer Event Counter 1 Timer Output F F Status Set Unchanged Timer output F F reset 0 Timer output F F set 1 Setting prohibited LVR2 8 Bit Timer Event Counter 2 Timer Output F F Status Set Unchanged Timer output F F reset 0 Timer output F F set 1 Setting prohibited Cautions 1 Be sure to set TOC1 after stopping timer operation 2 After data setting 0 can be read from LVS1 LVS2 LVR1 and LVR2 226 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 1 AND 2 4 Port mode register 3 PM3 This register sets port 3 input output in 1 bit units When using the P31 TO1 and P32 TO2 pins for timer output set PM31 PM32 and output latches of P31 and P32 to 0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to Figure 9 7 Port Mode Register 3 Format Symbol 7 6 Address After Reset R W 5 4 3 2 1 0 PM37 PM36 PM35 PM34 PM32 PM31 PM30 FF23H FFH R W PM3n P3n Pin Input Output Mode Selection n 0 to 7 Output mode output buffer ON Input mode output buffer OFF 227 CHAPTER 9 8 TIMER EVENT COUNTERS 1 AND 2 9 4 8 Bit Timer Event Counters 1 and 2 Operations 9 4 1 8 bit timer event counter mode 1 Interval t
550. utput ports Besides serving as input output ports they function as data input output to from the serial interface clock input output automatic transmit receive busy input and strobe output functions The following operating modes can be specified in 1 bit units 1 2 Port mode These ports function as 8 bit input output ports They can be specified in 1 bit units as input or output ports with port mode register 2 PM2 When they are used as input ports on chip pull up resistors can be used to them by defining the pull up resistor option register L PUOL Control mode These ports function as serial interface data input output clock input output automatic transmit receive busy input and strobe output functions 10 SH 500 501 Serial interface serial data input output pins b SCK0 and SCK1 Serial interface serial clock input output pins c SBO and SB1 NEC standard serial bus interface input output pins 65 CHAPTER 3 PIN FUNCTION uPD78054 Subseries d BUSY Serial interface automatic transmit receive busy input pins e STB Serial interface automatic transmit receive strobe output pins Caution When this port is used as a serial interface the I O and output latches must be set according to the function the user requires For the setting refer to Figure 16 4 Serial Operation Mode Register 0 Format and Figure 18 3 Serial Operation Mode Register 1 Format 3 2 4 P30 to P37 Port 3 These
551. value of the corresponding channel becomes indeterminate and may adversely affect the converted values of other channels 2 Analog input ANIO to ANI7 pins are multiplexed with the input output port port 1 When performing A D conversion with one of ANIO to ANI7 selected do not execute an input instruction to port 1 during conversion Otherwise the conversion resolution may be deteriorated In addition if a digital pulse is applied to a pin adjacentto the pin performing A D conversion the desired A D conversion value may not be obtained due to coupling noise Therefore do not apply a pulse to a pin adjacent to the pin performing A D conversion 267 CHAPTER 14 A D CONVERTER 7 8 9 268 pin This pin inputs the A D converter reference voltage It converts signals input to ANIO to ANI7 into digital signals according to the voltage applied between and AVss The current flowing in the series resistor string can be reduced by setting the voltage to be input to the AVnEro pin to AVss level in standby mode Caution serial resistor string of approximately 10 is connected between the AVnero pin and the AVss pin Therefore when the output impedance of the reference voltage is high it is connected in parallel to the serial resistor string between the AVrero pin and the AVss pin so that the reference voltage error increases AVss pin This is a GND potential pin of the A D converter Keep it a
552. vice Master Device SCK0 UI LI Clock Output Clock Output gt gt gt gt Clock Input Serial Clock Clock Input N ch Open Drain SB0 SB1 fn sB1 N ch Open Drain 500 4F Serial Data Bus 500 77 si E des SE ded G si Caution Because the N ch open drain output must be high impedance state at time of data reception write to serial I O shift register 0 SIOO in advance The N ch open drain can be high impedance state at any time of transfer However when the wake up function specify bit WUP 1 the N ch open drain output always becomes high impedance state Thus it is not necessary to write to SIOO before reception 325 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 6 7 8 326 Address match detection method In the SBI mode the master transmits a slave address to select a specific slave device Coincidence of the addresses can be automatically detected by hardware CSIIFO is set only when the slave address transmitted by the master coincides with the address set to SVA when the wake up function specify bit WUP 1 If the bit 5 SIC of the interrupt timing specify register SINT is set the wake up function cannot be used even if WUP is set an interrupt request signal is generated when bus release is detected To use the wake up function clear SIC to 0 Cautions 1 Slave selection non selection is detected by matching of t
553. w level 4 Open Leave this pin unconnected to A16 Address Bus RESET Reset CE Chip Enable VoD Power Supply DO to D7 Data Bus VPP Programming Power Supply OE Output Enable Vss Ground PGM Program 42 CHAPTER 1 OUTLINE uPD78054 Subseries 1 6 78K 0 Series Expansion The products in the 78K 0 Series are listed below The names in boxes are subseries names 100 pin 100 pin 100 pin 100 pin 80 pin 80 pin 80 pin 64 pin 64 pin 64 pin 64 pin 64 pin 64 pin 64 pin 64 pin 64 pin 64 pin Series 100 100 80 80 pin 100 pin 100 pin 100 pin 80 pin 80 80 pin Note Planned 42 44 pin Z 7 Mass produced products The subseries whose name ends with Y support the bus specifications Control uPD78075B uPD78078 Reduced EMI noise version of uPD78078 uPD78078Y Added timers to 1PD78054 and enhanced external interface Reduced EMI noise version of uPD78018F Low voltage 1 8 V version of uPD78014 and enhanced ROM RAM size options Added A D and 16 bit timer to uPD78002 Added A D to uPD78002 Basic subseries for control applications Equipped with UART and operates at low voltage 1 8 V uPD78014H uPD78018F Inverter control uPD780988 7 uPD780964 7 15078092474 Enhanced inverter control timer and SIO of uPD780964 expanded ROM and RAM Enhanced A D of uPD780924 E
554. wake up function specify bit WUP z 1 the N ch open drain output is always high impedance state Thus it is not necessary to write FFH to SIOO 3 If data is written to SIOO when the slave is busy the data is not lost When the busy state is cleared and SBO or SB1 input is set to the high level READY state transfer starts Upon termination of 8 bit transfer serial transfer automatically stops and the interrupt request flag CSIIFO is set Perform the following settings to the pins used for input output of data SBO or SB1 after inputting RESET before the first byte of serial transmission 1 Set the P25 and P26 output latches to 1 2 Set bit 0 RELT of the serial bus interface control register SBIC to 1 3 Reset the P25 and P26 output latches from 1 to 0 331 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 10 Discrimination of slave busy state When device is in the master mode follow the procedure below to judge whether slave device is in the busy state or not 1 Detect acknowledge signal ACK or interrupt request signal generation 2 Set the port mode register PM25 or PM26 of the SBO P25 or SB1 P26 pin into the input mode 3 Read out the pin state when the pin level is high the READY state is set After the detection of the READY state set the port mode register to O and return to the output mode 11 SBI mode precautions 332 a Slave selection non select
555. wire serial I O mode CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to OOH Figure 19 3 Serial Operating Mode Register 2 Format 5 4 3 2 1 0 CSIM Pl IE Symbol 7 6 Address After Reset R W FF72H 00H R W CSCK Selection of Serial Operating mode 0 UART mode 1 3 wire serial I O mode First Bit Specification 0 MSB 1 LSB CSIM2 CSIE2 Operation Control in 3 wire Serial Mode 0 Operation stopped 1 Operation enabled Cautions 1 Ensure that bits 0 and 3 to 6 are set to 0 2 When UART mode is selected CSIM2 should be set to 00H 444 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 2 Asynchronous serial interface mode register ASIM This register is set when serial interface channel 2 is used in the asynchronous serial interface mode ASIM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIM to 00H Figure 19 4 Asynchronous Serial Interface Mode Register Format Symbol lt 75 lt 6 gt Address After Reset R W se pe e a umen SCK Clock Selection in Asynchronous Serial Interface Mode Input clock from off chip to ASCK pin Dedicated baud rate generator outputNete in Case of Error Generation in case of error generation Control of Reception Completion Interrupt Request Reception completion interrupt request generated Reception completion interrupt request not gener
556. wledge signal is one shot pulse to be generated at the falling edge of SCKO after 8 bit data transfer It can be positioned anywhere and can be synchronized with any clock SCKO After 8 bit data transmission the transmitter checks whether the receiver has returned the acknowledge signal If the acknowledge signal is not returned for the preset period of time after data transmission it can be judged that data reception has not been carried out correctly 313 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 uPD78054 Subseries 314 f Busy signal BUSY and ready signal READY The BUSY signal is intended to report to the master device that the slave device is preparing for data transmission reception The READY signal is intended to report to the master device that the slave device is ready for data transmission reception Figure 16 19 BUSY and READY Signals SCK0 le lef LE LI LI LI 1 5 0 5 1 ACK BUSY READY In SBI the slave device notifies the master device of the busy state by setting SBO SB1 line to the low level The BUSY signal output follows the acknowledge signal output from the master or slave device It is set reset at the falling edge of SCKO When the BUSY signal is reset the master device automatically terminates the output of SCKO serial clock When the BUSY signal is reset and the READY signal is set the master device can start the next transfer Caution SBI outputs the BUSY signal after BUSY has been cle
557. x 13 1 ms 217 x 1 fx 26 2 ms 1 fx 200 ns 2 x 1 fx 400 ns 22 x 1 fx 800 ns 23 x 1 fx 1 6 us 217 x 4 fx 26 2 ms 218 x 1 fx 52 4 ms 2 x 1 fx 400 ns 22 x 1 fx 800 ns 23 x 1 fx 1 6 us 24 x 1 fx 3 2 us 218 x 1 fx 52 4 ms 219 x 1 fx 104 9 ms 22 x 1 fx 800 ns 23 x 1 fx 1 6 us 216 x watch timer output cycle 2 x watch timer output cycle Watch timer output edge cycle Remarks 1 fx Main system clock oscillation frequency 2 MCS Oscillation mode selection register OSMS bit 0 3 Values in parentheses when operated at fx 5 0 MHz 207 CHAPTER 8 16 TIMER EVENT COUNTER 8 5 7 One shot pulse output operation It is possible to output one shot pulses synchronized with a software trigger or an external trigger 00 00 pin input 1 One shot pulse output using software trigger If the 16 bit timer mode control register TMCO capture compare control register 0 CRCO and the 16 bit timer output control register TOCO are set as shown in Figure 8 31 and 1 is set in bit 6 OSPT of TOCO by software a one shot pulse is output from the TOO P30 pin By setting 1 in OSPT the 16 bit timer event counter is cleared and started and output is activated by the count value set beforehand in 16 bit capture compare register 01 CRO1 Thereafter output is inactivated by the count value set beforehand in 16 bit capture compare register 00
558. xx 2 stops in the HALT mode Remarks 1 gm moo N Value N 0 to 4 at bits 0 to 2 PCCO to PCC2 of processor clock control register PCC Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency MCS Oscillation mode selection register OSMS bit 0 Values in parentheses when operated with fx 5 0 MHz CHAPTER 21 INTERRUPT AND TEST FUNCTIONS When the sampled INTPO input level is active twice in succession the noise eliminator sets interrupt request flag PIFO to 1 Figure 21 8 shows the noise eliminator input output timing Figure 21 8 Noise Eliminator Input Output Timing during rising edge detection a When input is less than the sampling cycle tsmp 15 Sampling Clock INTPO D li PIFO L Because INTPO level is not high level at the time of sampling PIFO flag remains at low level b When input is equal to or twice the sampling cycle 15 15 gt Sampling Clock INTPO 1 2 PIFO Because the sampled INTPO level is high level twice in succession in 2 PIFO flag is set to 1 L 4 4 When input is twice or more than the cycle frequency tsmp tsp pw Sampling Clock When INTPO level becomes high level twice in succession PIFO flag is set to 1 495 CHAPTER 21 INTERRUPT A
559. xx 210 fx 210 4 9 kHz 2 4 kHz fxx fx 5 0 MHz 2 5 MHz fxx 2 fx 2 2 5 MHz 1 25 MHz fxx 2 fx 2 1 25 MHz 625 kHz fxx 23 fx 23 625 kHz 313 kHz fxx 24 fx 24 313 kHz 156 kHz fxx 26 26 78 1 kHz 39 1 kHz fxx 27 fx 27 39 1 kHz 19 5 kHz 9 8 kHz o IN IOA A oO N fxx 28 fx 28 19 5 kHz 25 fx 25 156 kHz 78 1 kHz fxx 29 fx 29 9 8 kHz 4 9 kHz A Other than above Setting prohibited Caution When Data is written to BRGC during a communication operation baud rate generator output is disrupted and communication cannot be performed normally Therefore data must not be written to BRGC during a communication operation Remarks 1 fx Main system clock oscillation frequency 2 fx Main system clock frequency fx or fx 2 3 MCS Oscillation mode selection register OSMS bit 0 4 n Value set in TPSO to TPS3 1 lt n lt 11 5 Figures in parentheses apply to operation with fx 5 0 MHz 470 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 When the 3 wire serial I O mode is used set BRGC as described below i When the baud rate generator is not used Select a serial clock frequency with TPSO to TPS3 Be sure then to set MDLO to MDL3 to 1 1 1 1 The serial clock frequency becomes 1 2 of the source clock frequency for the 5 bit counter ii When the baud rate generator is u
560. you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics 434 NE SAS User s Manual uPD78054 78054Y SUBSERIES 8 BIT SINGLE CHIP MICROCONTROLLERS uPD78052 uPD78052Y uPD78053 uPD78053Y uPD78054 uPD78054Y uPD78P054 uPD78055Y uPD78055 uPD78056Y uPD78056 uPD78058Y uPD78058 uPD78P058Y uPD78P058 uPD78052 A uPD78053 A uPD78054 A Document No U11747EJ5VOUMOO 5th edition Date Published April 1998 CP K Corporation 1992 Printed in Japan NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The ope
561. yte A HL byte A A HL B lt HL B HL B A HL B lt A A HL C A lt HL HL A A BLM 6 A 6 A c sfr laddr16 10 n m addr16 DE 6 n m DE HL 6 n m HL HL byte 10 n m HL byte HL 10 n m HL B HL C 10 n m HL C Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed 3 Except r A Remarks 1 One instruction clock cycle is one cycle of the CPU clock fceu selected by the processor clock control register PCC 2 This clock cycle applies to internal ROM program 3 nis the number of waits when external memory expansion area is read from 4 mis the number of waits when external memory expansion area is written to 564 27 INSTRUCTION SET Instruction Group Mnemonic Operands rp word Operation rp word saddrp word saddrp lt word sfrp word sfrp word AX saddrp AX lt saddrp saddrp AX saddrp AX AX sfrp AX lt sfrp sfrp AX sfrp AX AX rp AX lt rp rp AX AIR
562. yte address and data are latched by the page data latch mode a page write is executed by applying a 0 1 ms program pulse active low to the PGM pin while CE H and OE H After this program verification can be performed by setting CE to L and OE to L If programming is not performed by one program pulse repeated write and verify operations are executed X times X x 10 Byte write mode A byte write is executed by applying a 0 1 ms program pulse active low to the PGM pin while CE L and OE H After this program verification can be performed by setting OE to L If programming is not performed by one program pulse repeated write and verify operations are executed X times X x 10 Program verify mode Setting CE to L PGM to H and OE to L sets the program verify mode After writing is performed this mode should be used to check whether the data was written correctly Program inhibit mode The program inhibit mode is used when the OE pins VPP pins and pins DO to D7 of multiple uPD78P054s or 78P058s are connected in parallel and any one of these devices must be written to The page write mode or byte write mode described above is used to perform a write At this time the write is not performed on the device which has the PGM pin driven high 553 CHAPTER 26 uPD78P054 78P058 26 4 2 PROM write procedure Figure 26 4 Page Program Mode Flowchart Start Address G Voo 6 5 V 12 5 V Remark G Start address N L
563. z 6 One shot pulse output TMO is able to output one shot pulse which can set any width of output pulse 178 CHAPTER 8 16 BIT TIMER EVENT COUNTER 8 3 16 Bit Timer Event Counter Configuration The 16 bit timer event counter consists of the following hardware Table 8 4 16 Bit Timer Event Counter Configuration Item Configuration Timer register 16 bits x 1 TMO Register Capture compare register 16 bits x 2 CR00 CRO1 Timer output 1 TOO Timer clock select register 0 TCLO 16 bit timer mode control register TMCO Capture compare control register 0 CRCO Control register 16 bit timer output control register TOCO Port mode register 3 PM3 External interrupt mode register 0 INTMO Sampling clock select register SCS Note Note Refer to Figure 21 1 Basic Configuration of Interrupt Function Figure 8 1 16 Bit Timer Event Counter Block Diagram Internal bus Capture Compare Control Register 0 Y INTP1 S 5 16 Bit Capture Compare 9 Control Register CROO INTTMOO PWM Pulse Output Controller Note 2 E 16 Bit Timer Event bold 8 TMCOI TMCO3 Counter Output TOO PSO 22 9 16 Bit Timer Register TMO Control Circuit Clear Circuit TMC01 TMC03 Match INTTMO1 3 INTPO 16 Bit Capture Compare Control Register

uPD78054, 78054Y SUBSERIES 8-BIT SINGLE

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