Manual - S100 Computers
Contents
1. INC 23600 Mercantile Road Cleveland Ohio 44122 Phone 216 464 7410 8086 S100 CPU INTERRUPT Copyright C 1981 TecMar Inc 1 A INTRODUCTION 8086 S 100 CPU INTERRUPT The Tecmar 16 bit S 100 CPU Interrupt board is based on the INTEL 8086 microprocessor and consists of the CPU with 8 levels of vectored interrupt and 5 100 interface with extended addressing The board complies with the proposed IEEE 16 bit S 100 protocol providing the ability to fetch and store two bytes at a time which effectively doubles the previous capacity of the bus This board can access I O devices byte at a time or word at a time through memory locations or I O ports providing compatibility with conventional S 100 8080 280 systems The board permits a one megabyte address space by utilizing a 20 bit address which is formed using the extended address protocol in the proposed standard for the S 100 bus allowing full use of the 8086 The INTEL 8086 microprocessor is fully described in INTEL s MCS 861M User s Manual Please refer to this since the information on the 8086 integrated circuit will not be repeated in this manual The primary features include eight 16 bit registers hardware multiply and divide hardware trace mode and inherently position independent code via base registers The 8086 machine language provides a 5 to 10 fold base increase in performance over the 8080 Assembly language programs for2. ed for Direction 8 bit write to even byte 8086 to bus l6 bit read even byte bus to 8086 16 bit write even byte 8086 to bus 39 DIg DI4 led for Direction 8 bit read from odd byte bus to 8086 16 bit read odd byte bus to 8086 l6 bit write odd byte 8086 to bus IC 15 DOg DO 7 8 bit write to odd byte IC 38 019 012 8 bit read from even byte data is latched when A0 goes high on second half of 16 bit read from 8 bit memory _All of these IC s also require that DEN from 8288 and EN from 8259A both be high for a transfer to take place Copyright C 1981 TecMar Inc 13 A The 16 bit transfer to from 8 bit memory is accomplished by a circuit that detects the abscence of SIXTN when SXTRQ is active If this happens wait states are inserted while the circuit holds AO low for three clock periods and then holds AO high for the rest of the bus cycle 3 more clock periods The transfer proceeds as if two memory operations were done back to back at the even and odd byte locations The only difference is that the data from the even byte IC 38 is latched while the odd byte is read and IC 38 is still enabled Te 1C38 Strobe 0 Control Wail States wt bul d 100 AENEID i c cMECEMGEMEM MM CE ERN PWR Le ET AMA UNA MAT Lo 2 LLL RUNI ree Copyright 1981 14 The details on the 8259 int
3. Copyright C 1981 TecMar Inc 19 A This leaves the other signals CLOCK MWRITE and is the processor clock CLK CLOCK is required to be a 2 MHz signal of 40 60 duty cycle When a 4MHz 8086 is used the PCLK output of the 8284 provides a suitable signal When 5 MHz operation is desired the OSC output of the 8284 at 15 MHz must somehow be divided to give 2 MHz Clearly it is not possible to produce a symmetric waveform but dividing by 8 with a reset every 15 pulses will produce a waveform which is shaped like this me eS 4 15 usec 4 15 usec 4 15 psec 3 15 use This can be done with one 74LS161 or 163 counter as shown in the schematic For 8MHz operation the 7415161 is used to divide the PCLK output by two MWRITE poses a serious design problem Either it can be treated in the older fashion and left always driving the bus as PWR not Or it can be treated as a status signal and disabled during a DMA hold sequence as some later designs have done If the memory and memory mapped I O designer avoids using this line no problem will result If no DMA devices are used the designs are equivalent The latter design is selected for ease of implementation and MWRITE is thus AMWTC POC is the RESET 8284 line which conveniently mirrors PRESET We now have the schematic Copyright C 1981 TecMar Inc 20 A IC 17 CLOCK Next comes the DMA request grant circuitry It is necessa
4. DUUM Bl DI R AWN BY D keene Rrvisto 0 7 a gt gt J 8 4 et e scat None 0 4 81 AUAU DI 012 013 DI4 015 016 017 1 7 7 DRAWIMQ NUMRER gle gt se 8 amp gt amp S 2 gt amp gt amp LA E TES a lt gt 8 C 5 sin p lt 81 gt SH zm oiu E lt lt 5 lt b UY x xin alo 92 EC cul 2 el als B a als 9 aa aoa 2292922229 449944 lt 8086 Ao co Au 6273 Arrfes gt A3 64 gt Ale te gt Aa gt Au sa 12 2 CLEVELAND OHIO TECMAR INC NT FAUA OUY PRINTED OM MO ISCH a CLEAN MI CO J OY Ut i CJ PO ES PART 74LS32 74LS05 741504 741504 741 504 741 505 8282 7415245 74368 74368 7415136 741 611 8259 8282 8282 741 500 8 97 741 504 74164 74125 741 500 741 574 741 532 8288 741 574 741 504 7415175 741 508 7415161 741508 8284 8086 741510 7415175 741502 741500 7415173 811595 7415245 PARTS LIST 8086 S 100 BUS COMPONENTS QUANTITY PART TYPE AND NUMBER 1 1N915 DIODE 1 100 0 RESISTOR 3 1KQ RESISTORS 6 4 7 0 RESISTORS 2 4 7 0 RESISTOR NETWORKS BOURNS 4310R 101 472 29 0 luf CERAMIC DECOUPLING CAPACITORS 5 18uf
5. J5 This jumper is in for 8 MHz operation out for 5 or 4 MHz Copyright C 1981 TecMar Inc 30 A J7 This jumper is in for 5 MHz operation out for 4 or 8 MHz 18 6 9 For 8 MHz operation 4 For 4 MHz operation No jumper for 5 MHz operation J9 6 For 5 MHz operation For 8 MHz operation No jumper for 4 MHz operation Copyright C 1981 TecMar Inc 31 A TIMING REQUIREMENTS 8086 S 100 CPU INTERRUPT ara r AMHz 2MHz 8MHz read pulse 500ns 400ns 250ns address to read puls 80ns 65ns 40ns write pulse width 500ns 400ns 250ns address to write pulse 80ns 65ns 40ns worst case minimum access time from read strobe 480ns 380ns 230ns worst case write cycle time 1000ns 800ns 500ns These timing requirements refer to memory boards not memory chips The bus driver delays on the board will require chips to have access times that are around 50ns faster than the board timing requirement These read and write times also apply to I O devices note that standard 8251A requires a read pulse of 250ns and a write pulse of 250ns with data setup of 150ns soa write state is required on write operations The standard 8255 requires a read pulse width of 300ns and a write pulse width of 400ns with a 100ns data setup time and 30ns hold time so it requires a wait state also Copyright C 1981 TecMar Inc 32 8086 CPU BUS TIMING WITH ONE WAIT STATE 2 Ti Ti Wait T3 ALE Jf Lei ewe fC Status
6. the 8080 can be easily translated into 8086 programs with approximately a factor of two increase in performance The CPU Interrupt board can be used with 8 bit memory boards but memory capable of 16 bit transfers will allow faster operation The board has a power on jump feature to FFFFO where a monitor is provided on the PROM I O board Depending upon the crystal installed the system can be set up to operate at 4 5 or 8 MHz The 8086 uses a full 16 bit address for I O devices unlike the 8080 which duplicates the 8 bit I O address on 15 8 and 7 0 The board is shipped with all jumpers in a standard configuration but can easily be changed to take advantage of the optional features such as the wait state generator Copyright C 1981 TecMar Inc 2 1 2 3 4 5 6 7 8 9 10 1 FEATURES 8086 S 100 CPU INTERRUPT 5 100 bus compatible 16 bit microcomputer 8086 8 levels of vectored interrupt Designed for operation at 4 5 or 8 MHz Compatible with conventional S 100 8080 280 boards One megabyte address space Full 16 bit address for I O device On board regulators Operates with 8259A vectored interrupt chip or from PINT line 73 of S 100 bus Operates with 8 bit wide memory or 16 bit wide memory REQUIREMENTS S 100 bus Copyright C 1981 TecMar Inc 3 A FUNCTIONAL BLOCKS 8086 5 100 CPU INTERRUPT Processor Timing using a crystal oscillator supply the process
7. Signals Active PDBIN _ I1 lo X Copyright C 1981 TecMar Inc 33 A CRITICAL TIMING SIGNALS 8086 S 100 CPU INTERRUPT Please observe that all signals are necessary to the oeration of the board there are very few failures that will not crash the system CLK processor clock without this nothing will work 4 5 or 8 MHz also check this at pin 2 of the 8288 and look for glitches data path gating signals ILC Pin DI bus OE 39 19 DIR 39 1 38 9 5 38 11 DO bus OE 8 19 DIR 8 1 15 1 EN2 15 19 Address bus OE 7 9 14 9 37 1 2 ALE 7 1 14 11 37 7 ALE inverted 24 3 from bus SIXTN absence of this signal on 16 bit operations to 16 bit memory will cause the operation to fail Proper 8086 operation can be diagnosed by examining the outputs of the 8288 controller chip while single stepping the processor and comparing them to the operations implied by the software FOR EXAMPLE SEE NEXT SECTION Copyright C 1981 TecMar Inc 34 A DIAGNOSTIC AIDS 8086 5 100 CPU INTERRUPT The 8086 board set is fully static in that it can be single cycled from the bus Note however that only memory or I O cycles may be extended to yield useful information on the bus If a known program is being executed i e a ROM monitor or bootstrap upon startup the sequence of instruction fetches of data accesses as well as I O Operations may be observed with the use of 1 A device to drive the XRDY
8. from bus contention in the event of the failure of a l6 bit operation This block is centered around a Set of bidirectional bus transceivers and address latches Copyright C 1981 TecMar Inc 4 A I C s associated with block diagram layout 8086 Processor Timing Bus Control Vectored Interrupt Data Path Copyright C 1981 TecMar Inc Type 8086 4 74LS05 74LS04 74367 74LS161 8284 74LS08 8288 74368 74LS04 74LS 00 74LS10 74LS02 74LS175 74367 74LS74 74LS136 74LS05 74LS04 8259A See Component 3 5 17 29 31 30 24 9 10 4 26 DMA 16 36 DMA 33 35 DMA 34 27 DMA 17 25 DMA 1l DMA 2 6 13 make sure strap for interrupt source is correct 8282 74LS10 74LS04 7415245 741532 741511 74164 74125 741 500 741574 741508 7415173 811595 5 7 14 15 33 4 5 18 8 39 1 23 12 19 20 21 22 28 37 38 1 9 BLOCK DIAGRAM OF 8086 CPU CARD 8086 RQ GT So By 55 INT control incl DMA INTA processor Bo Processor speed status comman lines control 3 100 BUS lines SWO SINTA SINP SOUT PWR PDBIN PSYNC PWAIT MWRITE SMEMR SHLTA SMI PHLDA SXTRQ 4 vectored interrupt NEHME 16 19 0 5 VIP VI7 HARDWARE OPERATION 8086 S 100 CPU INTERRUPT The reader cf this section is cautioned that he is expected to be reasonabl
9. pin 3 line low from the time that PSYNC is high and 2 8086 clock is low until a debounced pushbutton is depressed It should be possible to disable this circuit by means of a double throw toggle switch These are the single cycle and run stop switches respectively 2 Some means for displaying the states of all the bus lines If a lot of time is available a logic probe will do Otherwise you will need a display panel which captures every line used on the bus 3 A logic probe or clip on display to show the logic states of all 37 signal lines on the 8086 chip itself and on any other package desired The technique consists of resetting the processor while the run stop switch is at stop and then examining the bus data address status and control information for incorrect signals If an incorrect signal is found it Should be traced back to the I C it originates at for address signals the 8282 data signals through the 74LS245 s or the other two data buffers Bus cycles should be repeatedly examined until the program appears to execute correctly having performed 1 16 bit memory read 2 8 bit memory read from odd location 0 1 3 8 bit memory read from an even location A020 4 16 bit memory write 5 8 bit memory write to an odd location A0 1 6 8 bit memory write to an even location A020 7 1 0 input operation 8 I O output operation 9 16 bit read from 8 bit memory if 8 bit memory is present
10. 10 16 bit write to 8 bit memory Copyright C 1981 TecMar Inc 35 A If all those operations appear successful the problem is probably either 1 bus noise are you using an active terminator card Is the bus adequately shielded 2 bus signal risetime problem do all your boards conform to the electrical portion of the proposed S 100 specification 3 bus contention is another device dynamically driving the bus due to faulty address decoding logic or control logic In single stepping a program do not forget that the 8086 pre fetches instructions It is therefore necessary to keep track of where it should be going and not decide that you have a defective processor chip when instructions are fetched beyond a jump which should have been taken Here is an example taken from the first few instructions of the INTEL Demo 86 monitor FFFFO JMP FF60 00BC EA BC00 60FF FF6BC CLI FA FF6BD MOV SS CS 00B8 2E 8E 16 00B8 6 2 MOV 5 07 0 07 0 FF6B8 1000 First cycle FFFFO DI BC DO EA SMEMR 1 SXTRQ 0 SMl 1 PDBIN 1 Second cycle FFFF2 DI 60 DO 00 i n Third cycle 4 DI XX DO FF n n n insert possible additional fetch cycle at FFFF6 Next cycle FF6BC DI 2E DO FA SMEMR 1 SXTRQ 0 SMl 1 PDBIN 1 And so on Please note that in order to implement this debugging technique an intimate knowledge of the hardware and listing of the software a well as special hardware is required Conventional 80
11. 80 front panels will not work and may damage the 8086 board set if their use is attempted In the example given above assume that on a memory read operation the correct information is found on the bus but the processor acts as if it had received incorrect data i e jumps into nonexistent memory In this cae reset the processor again and compare the data Signals at the processor pins AD15 to ADO with the apropriate DI to DIg and DO to DOg Signals respectively Copyright C 1981 TecMar Inc 36 A If they not the same at say bit 3 i e DO is not the same as AD3 trace the DO4 signal into pin 18 of IC8 74LS245 verify that it is the same at pin 5 and at pin 13 of the 8086 The location of the failure must then be in the node which first has an incorrect signal such as a shorted of broken trace or in the device driving that node i e bad IC or in a device receiving data from that node i e bad IC shorting input to 5 or ground Copyright C 1981 TecMar Inc 37 A LIMITATIONS 8086 S 100 CPU INTERRUPT l Due to the complex nature of the 8086 addressing scheme it is essentially infeasible to implement a front panel in the manner done on the IMSAI and ALTAIR machines The reset run stop and single step features of those front panels as well as a bus display the address data and status lights can be implemented in a manner similar to those front panels with the addition of status display lights o
12. C 1981 TecMar Inc 9 A MCE ALE requiring the inputs from 8086 5 from 8086 82 from 8086 CLK from 8284 AEN tie low CEN tie high IOB tie low Summarizing the required inputs we have INTR RDY2 RES and the data input lines time multiplexed into AD 5 ADg The 808675 complex scheme of addressing and intstruction look ahead prohibits the use of a conventional front panel for altering memory examining memory or starting program execution at an arbitrary location as is done with IMSAI or Altair 8080 based S 100 Systems The convention used in the systems which have no front panel is a simple switch called RESET which when pressed connects line 75 of the bus PRESET to ground and no other lights or switches This scheme seems to be most reasonable for use in an 8086 system and thus it is adopted A software based front panel could of course be designed with lights and switches as I O devices under program control The most complicated part of the mapping between the 8086 and the S 100 bus is in the data paths There are so many functions that the only reasonable way to list them is in a table Copyright C 1981 TecMar Inc 10 A function 8 bit memory write ESL output to an even numbered port or location 8 bit memory Write or 8 bit I O output to an odd numbered port or location l6 bit memory fead l6 bit I O output 8 bit memory fead or 8 bit I O in
13. IOWC 8288 drives WR 8259A IOR 8288 drives RD 8259A CS is asserted when AO and A2 A8 are all low I O ports 0 and 2 Al bus from 8282 drives 0 8259A Two consecutive even ports are chosen so that the data lines used by the 8086 will be the same for both These particular ports are those used by the INTEL DEMO 86 monitor ROM INTA 8288 drives INTA 8259A directly INT 8259A drives INTR 8086 directly as discussed before EN 8259A is used to disable the outputs of the multiplexers to AD7 ADg as discussed under data paths The CAS lines are left open consigning the 8259A to operate in buffered non cascaded mode because their use would require the definition of additional bus lines Copyright C 1981 TecMar Inc 22 A The schematic is thus 5 5 Vip IC 3 VIL 5 9 5 Viz IC 3 VI3 3 5 o 5 Tra 3 VI5 4 Qr5 9 5 Vi amp IC AU VI7 gt 4 gt AIQ 8288 108 8288 A Ag 1k p A 6 6 gt DAC 6 IC 6 A gt A ca Copyright C 1981 TecMar Inc D AD 8086 IRI ADs IR2 Ds ADs IR3 Dy AD M 8259A IRA D4 ADs a IR5 D AD2 IC 13 P IR6 Dy AD IR7 Do AD WR INTA INTA 8288 RD INT INTR 8086 AO quU 1k to control EN P circuitry 3 23 Outside of mapping a series of logic equations into SSI logic and selecting bus drivers for the control Signals the design is now complete Rema
14. TANTALUM CAPACITORS 15VWDC 1 CRYSTAL 12 0 MHz for 4 MHz CPU 15 0 MHZ for 5 MHz CPU 24 0 MHz for 8 MHz CPU 2 7805 VOLTAGE REGULATORS 2 HEAT SINKS 74367 THERMALLOY 6107 14 7 JUMPER CONNECTORS for 5 MHz or 8 MHz 28 A Copyright C 1981 TecMar Inc SET UP 8086 S 100 CPU INTERRUPT Boards built and tested by Tecmar Inc will have all jumpers in place for the processor speed purchased options will be set as follows l 16 bit operation only 2 No wait state except for 8 MHz boards which will have the wait state option selected 3 PHANTOM line driver not connected 4 8259A vectored interrupt selected No set up is needed for these boards If one desires to change this set up or if the board was not built and tested by Tecmar see the Jumper Summary that follows If changing the processor speed remember to change the crystal also 12 000MHz crystal for 4MHz operation 15 000 MHz for 5MHz or 24 000MHz for 8MHz Also note that an 8086 chip will run at slower speeds than it is rated but not at faster speeds i e don t expect to run an 8086 4 4MHz version at 8MHz Copyright C 1981 TecMar Inc 29 A JUMPER SUMMARY 8086 S 100 CPU INTERRUPT There are nine jumper locations on the board that are used for setting the operating speed and selecting the optional features on the board All illustrations of jumper placement are in the same orientation as on the parts placement diagram See the diagram for po
15. eginning of a bus cycle This is accomplished by latching ALE from the 8282 on the rising edge of the system clock CLK from one 8284 ALE is high for one rising CLK edge at the beginning of each cycle PDBIN is asserted when either MRDC 8288 or IORC 8288 is asserted PWR occurs with either AIOWC or AMWTC 8288 The schematic is shown on the next page Copyright C 1981 TecMar Inc 17 A PHL DA PHL DA from circuit 5 2 PSYNC CL MRDC bi j 17 PDBIN TORC P AMWTC 9 PWR 16 a 10K Kt IC 4 The status lines are next SMEMR bus is MRDC 8288 SINP bus is IORC 8288 SM 1 bus is decoded from 50 S 82 8086 and this could not be decoded unless the 8086 were operating MAX mode Since Sg 1 and 5 are valid only at the falling edge ofALE this output must be latched SOUT bus is AIOWC 8288 SHLTA bus is derived from 50 5 and 52 in much the same manner as SM1 SWO bus is asserted with either AIOWC 8288 or AMWTC 8288 SINTA bus is INTA 8288 SXTRQ bus is asserted for a cycle whenever both ADO and BHE are low when ALE falls The schematic is thus Copyright C 1981 TecMar Inc 18 A ROC ne ae SMEMR 8288 6 TORC 8288 INP ATOLS OUT 8288 50 8086 5 54 8086 SHLTA ALE 8288 through inverter AIOWC 8288 AMWTC 0 SINTA NIA ADO 8086 35 BHE 57 8086 NE TR 5 tlk 10K e gt STAT IC DSB
16. errupt chip are given in its section later Now that the data paths are taken care of the address path naturally comes next Rather conventionally this is 14 IG 15 1 37 2 20 bi 2 ADo iic A bus ALE 8288 IC 24 IC 5 74L504 ADD DSB bus Associated with this is the PHANTOM line circuitry The extended address lines 16 19 are or ed and a true output causes the PHANTOM line S 100 pin 67 to be pulled low if PHANTOM jumper is in place whenever memory is addressed above the lower 64K This allows the use of RAM cards that only decode the A0 A15 address lines in the lower 64K without conflict above this space Copyright C 1981 TecMar Inc 15 A Next the required 8086 8284 inputs INTR 1 and RES will be considered the 8259A s interrupt inputs are considered separately as well as the DMA request grant sequence The interrupt line PINT can indirectly drive the INTR interrupt input of the 8086 However if the 8259A interrupt chip is used jt must drive the INTR To avoid noise problems from disconnected inputs a wired strap is used rather than an OR gate The circuitry is simple 5 connect here if strap 8259A not installed bus FIM i e onm INTR 8056 8259 INT 4 connect here if IC 13 8259A installed The ready inputs from the bus drive the 828475 IC 31 RDY2 input Both lines must be ready for the RDYl line to be ready Note that the 8284 has a
17. hat input is asserted exactly as if the power had just been turned on The PINT line is ignored by the CPU if the vectored interrupt option is instaled on the CPU card See jumper summary Note that the response to the INTA signal by the interrupt controller or interupting device for the 8086 is ENTIRELY different from the response on an 8080 system The 8086 requires that a one byte interrupt type be put on the bus whereas the 8080 requires than an instruction be put onto the bus For this reason the use of the vectored interrupt option on the CPU card is recommended whenever interrupts are to be used The system presently runs on a 5 clock of 5 MHz as the standard The system can also be used with 4 or 8 MHz 8086 s but at 8MHz this is faster than the S 100 Standard indicates To run at 8 MHz the wait state option will have to be used as there will probably not be very many devices in the system that can run that fast The wait state option will slow bus operations down to a reasonable speed while allowing internal 8086 operations to proceed at 8 MHz Devices which use the Bo clock as a timing base for external operations assuming that it is 2MHz should be modified to use the CLOCK 49 signal which is 2MHz Note in 5 MHz systems the CLOCK signal will not be symmetrical Note that unlike the 8080 the 8086 does not duplicate the 8 bit I O address on A15 A8 and A7 A0 but rather uses a full 16 bit address for I O devices 1 0 map
18. ining is a check on power consumption and design of the on board power supply a timing check of the circuit to make sure that there are no ridiculously long delays in sending data to Or taking data from the bus and a system check to make sure that all of the individually designed circuits will work together Without going into the details of gate counts and individual worst case supply currents the board will consume at most about 1 800 ma This means that two conventional 7805 regulators will have to be used if they are to regulate for the board Adequate bypassing and decoupling are also necessary Decoupling is accomplished by an 0 1 f ceramic disk capacitor across the power supply at the Vcc terminal of each package Bypassing is inherent in the supply The timing check shows that at worst a 20 ns delay is possible in read and write operations due to bus drivers on the card This must be accounted for in specifying memory and I O speed This assumes all 74LS parts The system check turns up an anomaly in the use of the 8288 bus controller in systems having wait states The 8288 bus controller cannot detect the occurence of a not ready condition wait state and will proceed as if said condition had not occurred Since the 8288 is a static device the clock into it can be gated to solve this problem as follows READY 8284 CLK 8288 IC 30 CLK 8284 The gate delays are necessary to prevent glitching on the 8288 s CLK in
19. n OR between RDYl and RDY2 so both inputs cannot be used Added to this is the optional wait state generator This adds one wait state to every bus cycle in addition to any requested by the device being accessed The circuit adds a one clock duration low on the RD2 line at the end of a low caused by another device slow memory or right after the PSYNC pulse if no other wait state is requested The circuit is Copyright C 1981 TecMar Inc 16 A The RES input of the 8284 I C 31 remains This input should provide power on reset reset in the event of momentary power failure and reset when the bus PRESET line is brought low A Schmitt trigger is provided on the 8284 so an R C network is adequate for power on detection with a delay of 0 2 0 5 sec to allow the power supply to settle A diode is added to discharge the capacitor in the event of momentary power failure An open collector gate serves to discharge and hold low the capacitor as PRESET is brought low The complete circuit is PRESE The required output signals are divided into three groups the command control lines PHLDA PSYNC PDBIN PWR the status lines SMEMR SINP SMI SOUT SHLTA SWO SINTA and SXTRQ and the other lines f5 CLOCK MWRITE POC The command control lines will be discussed first The discussion of PHLDA is reserved for the DMA request grant paragraph later PSYNC is a positive going pulse of one clock period duration at the b
20. n SXTRQ and SIXTN Altering memory could be accomplished through the use of a DMA scheme but starting program execution ata particular point would be completely infeasible from a front panel like device Therefore it is recommended that the machine be set up with a terminal oriented monitor It has a power on jump feature to fixed address and a simple monitor is available from INTEL in a pair of 2616 PROMS A front panel effect could also be achieved by storing in ROM a program to treat a set of lights and switches as I O devices and emulate a front panel but that implementation sacrifices the ability to single step a program 2 The 8086 system for the S 100 bus meets all of the requirements for a bus master outlined in the proposed standard published in the March 1979 IEEE Computer magazine except that it is faster It uses no lines that are specified as undefined or reserved for future use It also does not use the STVAL status valid line which was not well defined in the proposed standard and is not even needed since the status lines are valid immediately following the PSYC pulse It drives the following lines which are not considered type M master signals 0 24 CLOCK 49 MWRITE 68 disabled by STAT DSB low POC 99 Copyright C 1981 TecMar Inc 38 A The CPU card treats PRESET 75 as an open collector input or momentary normally open switch to ground and emits a low on the POC line when t
21. or clock 4 5 or 8 MHz to the processor and the bus f line Supply a 2 MHz peripheral timing clock to the bus Provide power on clear to the processor and bus and synchronize the reset to the processor Synchronize the wait state generation with the clock XRDY PRDY AND CPU READY This circuit is centered around the Intel 8284 clock generator chip Bus Control From the processor clock and the 50 S1 52 signals provided by the processor generate the S 100 bus status lines and the S 100 bus command control lines disabling them on the assertion of STAT DSB and C C DSB respectively Handle DMA request grant timing Provide timing and control signals to the rest of the board ALE PSYNC DT R DEN INTA IORDC AIOWC Centered on an Intel 8288 bus controller chip Vectored Interrupt Based on the VIO VI7 lines on the bus generate and vector interrupts to the 8086 processor INT Based on an 8259A priority interrupt chip Data Path Control and Buffers Using signals generated by the bus control section Latch the address from ADO 19 and drive the address lines A0 A19 on the bus drive the 8086 AD inputs from the appropriate S100 bus lines at the appropriate times drive the bus from the 8086 AD outputs at the appropriate times The address and data outputs to the bus may be disabled by ADD DSB and DO DSB respectively The output depends on SIXTN rather than on the internally generated SXTRQ to avoid any problems which might arise
22. ped boards accessing lines A15 through A8 as substitutes for A7 through AO will need to be addressed differently in software as opposed to the way they were on the 8080 The extended address bits are all zero for an I O operation Copyright C 1981 TecMar Inc 39 A
23. put Experimentally this circuit offers the largest margin against varying gate delays in either direction so that aging and temperature will have a minimum effect on its operation Electrical compliance with the S 100 standard is accomplished by the use of 74367 and 74368 bus drivers for the control signals and by making pullup resistors on the open collector bus lines 5 10K to be well within the current limits The 8282 and 74LS245 far exceed the drive capability requirement Copyright C 1981 TecMar Inc 24 A INSWIIV1d 1 3 04402 quvog 142 9808 nnnm npn Al d pma o lone Un sme murem EI aco rn 46v lt SAT oe SINTA 9 10 74558 NOTE 1 gt INDICATES SIGNALS THAT ARE CONNECTED TO COMPONENTS Ai WHICH ARE SHOWN ON PART 2 OF THIS DIAGRAM SHEET 42 pev 2 ENCIRCLED 5 INDICATE CHP IN GATES INVERTERS 7415 24 THE CIRCLE 15 NOT USED TO IDENTIFY CHIP TYPE SEE UST M 74 15 04 5 ONLY PARTOF THE CPU CHIP 15 SHOWN HERE THE REST OF IT 1S DESCRIBED ON SHEET 2 OF THIS BOARDS DIAGRAM 74 8284 Bose 741510 Wis oz lt 19 vse lt 77 POR C78 PDBIN lt 36 vc PRDY rz xRDY 3 gt 2 4 ws 5V 8 lt T 7l cmn PHANTOM 8086 S 100 CPU 0 e NONE Y Raf Lewy May 17 9 TECMAR INC Cleveland Ohio berte PRINTED UM
24. put from even numbered or location 8 bit memory read or 8 bit I O input from odd numbered port or location l6 bit memory read or l6 bit I O input l6 bit read from 8 bit memory l6 bit write to 8 bit memory interrupt acknowledge 8259A chip not installed interrupt acknowledge 8259A chip installed destnation B57 A9 59 00 5 A 207 D0g X AD DI7 DI 15 ADg 7 509 DI DIg gt AD7 AD DI7 DIg AD 5 ADg DI DI 2 AD 5 ADg DO DOg AD7 ADg DI DI 7 jg ADj5 ADg AD4 AD 07 00 5 ADg DIj DIQ 7 8259 data 7 lines These transfers are conceptually implemented as follows Copyright C 1981 TecMar Inc 11 Id ea 4 SbS1 19 She STAL LE gt 821 5529 8 14 98 08 h OL 12 A Copyright C 1981 TecMar Inc The transfers needed may be organized by destination destination Source DO ADj ADg AD15 ee ADg DI AD AD DI B 3 DO on board 8259A AD15 ADg DI The bus buffers will all be disabled when DO DSB is pulled low for DMA or when the 8259A is acknowledging an interrupt The DIR inputs of the two transceivers are driven by the DT R line of the bus controller 8288 The control lines for the drivers must now be considered The IC s at the data bus interface are enabled as follows 80 DO DO
25. ry to generate a low true pulse of one CLK cycle duration into the RQ GT pin of the 8086 upon receiving PHOLD signal When the processor responds with a low true pulse through the same pin PHLDA is asserted on the bus When PHOLD is released another low true pulse must be generated into the pin This circuitry will accomplish the task PHOLD DUS inverted from 8284 PHL DA CLK 8284 A B C E 8086 C IC 32 is PHOLD synchronized on the falling edge of the processor clock is A inverted and delayed one clock period when high the master request pulse is over is the RQ GTO pin of the 8086 ET is high when PHLDA is asserted or RQ GTO is low is high when the master request pulse is done either the CPU grant is being pulsed on RQ GTO or PHLDA is already asserted Copyright C 1981 TecMar Inc 21 A See the relevant timing diagram on p 5 17 of Intel s MCS 86 User s Manual Finally there is the optional 8259A priority interrupt controller chip and its associated circuitry First what happens if the chip is not present The EN 8259A line is pulled high by a pullup resistor to 5 volts and during the second INTA pulse the interrupt address is expected to be on the DI lines on the bus The Strap option for INTR 8086 output was discussed earlier The interrupt lines are derived from VIO VI7 on the bus the data lines are connected to _AD AD on the 8086 A
26. sition of jumpers NOTE 5o means place the small jumper connector so that it connects covers the two jumper pins that are connected by the m the third pin will have nothing it Jl PHANTOM jumper Put a jumper here to cause the PHANTOM line S 100 pin 67 to be pulled low whenever the CPU addresses memory above the lower 64K This allows an older memory card with a 16 bit address to be used in the lower 64K as long as the memoy cards also have a PHANTOM line connection If there is no jumper here the CPU card has no affect on PHANTOM J2 Selection of 8259A or PINT interrupt operation A For operation with 8259A vectored interrupt chip 4 For operation of interrupts with the PINT line S 100 pin 73 J3 Selection of the 16 bit transfers from 8 bit memory option A o Jumper this way if all of system memory 15 l6 bits wide B 5 Jumper this way if any of system memory 8 bit only memory J6 Selection of optional wait state With jumper this way the CPU board will insert oa wait state in addition to any wait state requested by the device being accessed in every bus cycle This is needed for 8 MHz operation or for use with very slow memory B With jumper this way no extra wait states will be added All other jumpers are for CPU speed selection and should not be changed unless the crystal is changed also see system set up 24 This jumper is in for 5 or 4 MHz operation out for 8 MHz
27. timing signals Since there is no front panel the CPU must generate Bo bus timing CLOCK peripheral timing MWRITE memoy write POC power on clear Besides the data lines DO7 DOg and DIj DIg the inputs to the CPU board from the 100 bus as follows XRDY PRESET VIO STAT DSB VIL C C DSB ADD DSB 13 DO DSB V14 SIXTN Vl5 PRDY V16 PINT 17 PHOLD in addition to the 8V and ground lines on the bus Based on the 8086 documentation operating in MAX mode the following signals are available see pages 5 9 and 5 11 of the MCS 86 User s Manual AD15 ADg Alg 16 BHE Copyright C 1981 TecMar Inc 8 A And the 8086 requires the following inputs READ INTR TEST RESE CLK Y tie low T Adding an 8284 I C 31 clock generator provides the following outputs RESET 8086 input OSC CLK 8086 input PCLK READY 8086 input and the following inputs are required X 1 connect to 12 15 or 24 MHz fundamental X frequency crystal 2 TANK leave open for use with overtone mode crystals F C tie low input is from crystal not EFI EFI tie low unused input CSYNC tie low unused multiprocessor sync facility RDY2 AEN2 tie low tie high a RDY1 tie low unused alternate bus ready line RES Adding an 8288 I C 44 bus controller provides the outputs see MCS 86 User s Manual pages 5 33 MRDC MWTC AMWC IORDC IOWC AIOWC INTA DT R DEN Copyright
28. y familiar with use of the 7400 series TTL and have reviewed the data sheets for the Intel 8086 8282 8284 8286 8288 and 8259A ICs in chapter 5 of the MCS 86 users manual He is also expected to have reviewed a copy of the proposed IEEE standard for the S 100 bus The first step in interfacing a processor to the S 100 bus is defining the exact meaning of each bus signal to be generated under all possible conditions The second Step is establishing what signals are available from the processor A mapping is then defined to create those Signals required at the processor and at the bus from those available at the bus and at the processor The mapping must then be examined to ensure tha it places no unnecessary restrictions upon the operation of the processor or the bus and that it will in fact work even under worst case conditions In order to conform with the proposed standard for the S 100 bus the CPU card must generate the following Signals A19 DI7 DATA15 A18 DI6 DATA14 A17 DIS DATA13 PHLDA 16 DI4 DATA12 SM1 A15 DI3 DATA11 SOUT A14 DI2 DATA10 SINP A13 DI1 DATA9 SMEMR A12 DIO DATAS8 SHLTA A11 DO7 DATA7 SXTRQ A10 DO6 DATA6 PSYNC A9 DO5 DATA5 PWR A8 DO4 DATA4 PDBIN A7 DO3 DATA3 SINTA A6 DO2 DATA2 SWO A5 DO1 DATAl A4 DO0 DATAO A3 A2 Al 0 See IEEE Computer magazine March 1979 20 44 Copyright C 1981 TecMar Inc 7 In addition to those lines the CPU card or front panel must generate certain
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