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Rastergraf / Peritek VCL-V Manual

1. amp Tinian H a g Ornan s Big ol aate a nel a m m an BOOT E sul nl erm anisms hinting Jumper A sien m v 48 yee E Jumper B renner ak TTT in E mun 8 Jumper C uulu E m E sain E n a ee 2 Jumper D T r Tunney a gt Jumper E MTT ay SBE E P Sen n e y m 4 a suis cea ae LF E omer j i a H 4 m T Jumper G z wit a 3 Re z T T a a dumper H E e Section 2 6 7 2 15 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 5 Other Configuration Jumpers for the VCL Series The following subsections cover other less frequently used options 2 5 1 DRAM and VRAM Size VCL V only The VCL V but not VCL M 34020 system memory DRAM and VRAM display memory may be changed in the field The DRAM is contained on a SIMM Single Inline Memory Module The VRAM is contained on a Rastergraf VMEM8 or VMEM24 daughterboard Note The VCL V 8 X10 and VCL V 8 X12 do not support expansion of video memory beyond the chips in
2. 5 13 Flash EEPROM and Serial EEPROM Flash EEPROM The VCL V has four locations for installing 32 pin PLCC EEPROMs The devices can range in capacity from 16K x 8 to 512K x 8 The VCL M has two locations for installing 48 pin TSOP EEPROMs The devices can range in capacity from 256K x 16 to 512K x 16 The EEPROMs are wired as a full 32 bit wide memory to the 34020 Although one wait state is required because of the EEPROM access time performance is quite good memory cycle time is 300 ns 50 longer than normal for a non page acceess The VCL can accommodate any of the sizes mentioned without jumpers Smaller devices simply repeat Rastergraf has developed procedures for generating PROM based software and loading EEPROMs with the code using a PC and a BP Microsystems Programmer We also have a VxWorks SunOS Solaris and HP UX based program for loading code into the EEPROM when they are already installed Please contact Rastergraf for more information As part of Rastergraf s software offerings a Built In Self Test terminal emulator SmartPTERM a terminal emulator PTERM PX Windows X11R6 server and CLP Graphics Subroutine Package can be supplied in EEPROM A control bit initialized by host bus RESET and buried in the 34020 address decoder allows the flash memory to respond to the highest 1 MB section of 34020 memory instead of the DRAM The VCL can autoboot on power up or reset when enabled by a jumper see Section 2 4 5
3. IOREQ is used to request 34020 related functions A valid LAR and an offset into the line buffer address block will select a unique address in the 34020 address space The following diagram illustrates the mapping CMA 25 24 23 22 21 2019 18 17 16 15 1413121110 9 8 7 65432 LAR 15 141312111098 765 43 2 1 0 LAD 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98765 Notes CMA is VMEbus address LAR is Line Address Register and LAD is 34020 address bus LAD 31 and 30 are tied high 29 and 28 are wired together Address Decoding The address decoder provides 3 signals IOREQ CSRREQ and BFREQ IOREQ and CSRREQ provide decoding for the A16 space addresses CSR and I O window In the case of the I O window MEMON must be set to enable board response and the I O window can be enabled to appear in A24 space instead of A16 BFREQ is the decode for A32 space addresses When IOREQ MEMON CSRREQ BFREQ XMEMON IACK AS DSn 1 where means logical OR and means logical AND then VREQ is set It can be assumed that a valid address has been clocked into the address register and data is already set up on the VMEbus for write or the CPU is waiting to receive data from the board read VREQ is used to request control of the VCL V by the VMEbus The operation of the arbitrator in this case is described in the Section 4 5 The low 10 bits of the BAR are always active on the VCL s internal CMA bus If the VMEbus address
4. The graphics board CSR block and 1 KB Line Buffer both reside in A16 space The CSR block base address is controlled by 4 jumpers see Section 11 4 1 which give 16 possible address offsets within the A16 space Normally the offset is C000 giving a MVME CPU address of FFFFC000 for the CSR block Now the Line Buffer has an address offset determined by a programmable register in the CSR block These bits correspond to address lines 10 15 for A16 and lines 10 23 for A24 On the MVME CPU s Rastergraf uses is 8000 giving a CPU address of FFFF8000 for A16 The graphics board also can respond to a 64 MB window in A32 space giving access to the entire on board memory In this case a programmable register in the CSR block allows you program the address of that window The 6 bits in this register correspond to the high 6 bits of the A32 address In the MVME CPU A32 space extends up to MVME CPU address F0000000 Normally we place the board at A0000000 It is important to remember that the addresses which the graphics board responds to are a function of the VMEbus address and the address modifier codes The address modifier codes must be asserted such that the board s CSR group and Line Buffer spaces are in A16 space and the extended memory block appears in A32 space Not surprisingly the address modifier codes are set up by the CPU board s bus controller The graphics board responds to D8 D16 and D32 accesses in A16 space and D8 D16 and D32
5. 888 88 SOURCE www artisantg com Rastergraf Digital Video Connector Serial Connector PS 2 Connectors High Speed Port HSP Module Size Power Requirements Environment Ruggedization Option 1 13 General Information A 68 pin mini D ribbon type connector supplies TTL level 1 4 8 9 12 18 or 24 bit digital sync blanking and 5 to flat panel displays A variety of monochrome and color panels have been tested and qualified Current limited sequenced 5 and 12 are also supplied Contact Rastergraf about information regarding panel compatibility DB 9 connectors are provided for the console and mouse connectors Secondary serial ports are included on each channel thereby giving a total of 4 serial ports Fused 12 volts is provided on the mouse connector 7 pin Mini DIN PS 2 type connectors are provided for the PC keyboard and PS 2 mouse peripherals Fused 5 volts is provided on the connectors On the VCL V only a 32 bit port allows the 34020 to connect to an external device and read data directly into memory at page mode speeds 100 ns per transfer A simple handshake interface is used to control the external device Special routines in the graphics subroutine package support HSP transfers The HSP is connected via the VMEbus P2 connector using the VSB pinout for most signals However it is not VSB compatible 6U Eurocard 233 mm x 160 mm 5V 5 3 0 A typical Temperature 0
6. R only R only Static Display ENable When SDEN is set and PSEN is clear overlay is static not pannable When PSEN is also set primary is static When SDEN is clear primary and overlay are both pannable See Sections 5 4 3 and 5 4 4 Primary Static ENable See SDEN Static Display DINC SDINC1 SDINCO video wide 1 1 8K 1 0 4K 0 1 2K 0 0 1K Allows s w to verify that ID register is here because this bit is R W on Rev 2 or 3 VCL V and on all VCL M boards Bus Revision register Indicates Bus Type BT2 BTI BTO Bus Type 1 0 0 VMEbus 0 0 0 reserved x 1 x PMC Bus x 0 1 reserved unused reads 0 Must write with 0 Three bit code to indicates Board Fab Revision RV2 RVI RVO Board Revision 0 0 0 Rev 0 0 1 1 Rev 3 1 x x not used yet W only Must write with 0 R W R W R W Set to force 30 pixels of skew between Digital port horizontal and vertical sync leading edges Set to make Digital vertical sync high active Set to make Digital horizontal sync high active On board Devices and Memories 5 44 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 5 18 General Purpose Control Register continued 11 12BITMODE R W Set for two 12 bit pixel clock mode on Digital 10 DCLKPOL R W 9 GENLOCK R W 8 DEN 7 3 PVCLK2 1 6 VCMODE R W 5 VSCSPOL R W 4 HSPOL 2 ICSHERE ICSHOLD 1 32HI ICSDATA 0 VCLFLAG ICSCLK 5 45 On board Device
7. The VCL uses the IBM RGBS561 DAC chip which is a fine chip but has some limitations One of these is that updating the color map during active display time can cause some sparkle on the screen Another problem is that the digital output bus is shared with the MPU bus This means that the DAC can not be accessed when driving a digital display except during blanking A third problem is that the chip select signal for the DAC needs to have a time duration relative to the pixel speed This means that the chip that generates the DAC chip select needs to generate enough wait states to match the slowest pixel speed that may need to be supported These wait states slow down the maximum rate that data can be moved to the DAC when running faster pixel clocks These problems affect software performance because in order to update the DAC cleanly the program must poll the blanking bit then do its writes Only a limited number of writes can be done during blanking after which the program must poll for another scan line Write latency due to host requests screen refreshes and DRAM refreshes all combine to limit the number of writes that can be done during blanking To address these limitations we add the FIFO The FIFO provides an alternate way to get data to the DAC Data can be written to the FIFO with no wait states The FIFO is synchronized to the video clock so it can efficiently feed the DAC at the fastest possible rate The FIFO can also feed t
8. correctly Software Release Notes No image on Monitor COAX cables not Check BNC cables replace if connected properly or necessary Be sure to initialize board monitor is not on with correct initialization table Image is smeared or Sync signals missing or Make sure monitor accepts sync on doing flip flops monitor sync failure green that monitor is terminated and the hold controls are adjusted properly Make sure that R G and B cables do go to R G and B inputs Check initialization parameters PX Windows Server is Graphics board to Host Check interrupt pass grant jumpers very slow to startup CPU interrupts are not Check operating system for correct Mouse movement is being serviced interrupt configuration fast but windows are slow to open No response to mouse Keyboard or mouse Check cabling Reload software motion and or cable not plugged in PX keyboard entry Windows board side server is crashed 6 8 Troubleshooting Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 6 5 Dealing with the PCI Bus Because of the nature of the PCI protocol and the way support has been implemented in the Operating Systems for PCI bus devices such as the VCL P and VCL M it is not possible to follow the same debugging strategies In fact there are no address jumpers for these boards Everything is configured in software through a set of on board re
9. A direct A32 address mapping gives a 64 MB window into board memory In general Rastergraf software does not use the A32 addressing feature The graphics board has a four register block in the A16 space which contains the Control Status Register CSR Line Address Register LAR Line Buffer Address Register Extended Address Register and Interrupt Vector Address Register The 34020 can cause an interrupt to the VMEbus Two bus loads Times were measured using an HP1650A logic analyzer at the VME P1 connector using 1000 test cycles The 34020 was halted The host CPU was a Motorola MVME162 You must add about 150 ns of VMEbus overhead to get the total cycle time The long maximum access time results from access during a memory refresh cycle Using the 162 s DMA controller running VMEbus long word block transfers we measured an average 18 MB s write data tranfer rate The 34020 was set for host bus block transfer mode and read prefetch disabled Write min 140 ns Read min 420 ns max 1 2 us max 2 0 us average 168 ns average 497 ns The VCL V uses a 15 pin VGA style with Red Green with Composite Sync and Blue separate horizontal and vertical sync The pixel clock can optionally be output Genlock is an option available on the VCL V It requires HSYNC in and VSYNC in Contact Rastergraf for details regarding genlock operation General Information 1 12 Artisan Technology Group Quality Instrumentation Guaranteed
10. A rtisan Artisan Technology Group is your source for quality TecmoogyGroup new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilized and idle used equipment TENS OF THOUSANDS OF at our full service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment 7 EQUIPMENT DEMOS HUNDREDS OF InstraV ea REMOTE INSPECTION LOOKING FOR MORE INFORMATION MANUFACTURERS Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com information on price quotations drivers technical LEASING MONTHLY specifications manuals and documentation RENTALS ITAR CERTIFIED D a gaa tia Contact us 888 88 SOURCE sales artisantg com www artisantg com VCL V and VCL M Graphics Boards User s Manual Rastergraf Rastergraf Inc 1804 P SE First St Redmond OR 97756 541 923 5530 FAX 541 923 6575 web http www rastergraf com email support rastergraf com Release 2 0 November 8 2006 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table o
11. Color Map Operation for the VCL 24 The VCL 24 by virtue of its 24 bit pixel size supports true color mode This gives a full range 8 bits each Red Green and Blue of color selection for each pixel in other words 16 7 million colors Every pixel on a 1280 x 1024 display can be a unique value 24 bits of display memory divided into 8 bit Red Green and Blue sections are required for true color displays In order to allow modification of color balance e g gamma correction each 8 bit section is coupled to its own secondary 8 bit in 10 bit out gamma lookup table inside the 561 On board Devices and Memories 5 46 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Color Map Operation for the VCL 8 Because each pixel has only 8 bits the VCL 8 provides the more common pseudo color mode The 8 bit input to the RGB561 is mapped to a 1024 entry x 24 bit 8 bits each Red Green and Blue output lookup table This gives a selection of 256 colors from the full range of 16 7 million colors In order to allow modification of color balance e g gamma correction each 8 bit section is coupled to its own secondary 8 bit in 10 bit out gamma lookup table inside the 561 Rastergraf software normally allocates the 1024 entry color map as follows Pixel Value Display Function 0 255 Primary 256 511 Overlay 512 767 Primary Blink 768 1023 Overlay Blink Graphics Curso
12. Themis SPARC CPU s Address Ranges 00400000 FOFFFFFF FBFF0000 FBFF7FFF 00400000 FOFFFFFF FBFF0000 FBFF7FFF 80000000 EFFFFFFF F1000000 F100FFFF DRAMsize 01000000 01000000 EFFFFFFF FFFFO000 FFFFFFFF F0000000 FEFFFFFF FFFFO000 FFFFFFFF 04000000 FCFFFFFF FFFFO000 FFFFFFFF Resource VSB VME VME Short I O VSB VME VME Short I O VSB VME VME Short I O VME Standard VME Extended VME Short I O VME VME Short I O VME Extended VME Short I O Comments A32 D32 A16 D32 A32 D32 A16 D32 A32 D32 A16 D32 A24 D32 A32 D32 A16 D16 A24 A32 D32 A16 D32 A32 D32 A16 D32 Troubleshooting 6 3 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 6 3 VCL V Memory Map Example The following paragraphs assume Motorola MVME167 This Single Board Computer SBC has a 68040 serial and parallel I O memory SCSI and Ethernet Its specifications are similar to SBCs made by other firms The Motorola 142 167 memory maps are programmed in the debugger ENV command for A24 A32 D16 and D32 functions Contact Rastergraf for more information The CPU s have an undocumented register which responds at offset 10 in A16 space so Rastergraf boards cannot use the bottom of A16 space Also the 167 may be configured by operating system software to support only A16 D16 transfers The Rastergraf device driver writes the correct value in VMEchip2
13. www artisantg com Rastergraf FIOR The purpose of FIOR is to set the point at which the almost empty flag AEF and the almost full flag AFF turn on The EOR Empty Offset Register controls the AEF turn on point and the FOR Full Offset Register controls the AFF turn on point It takes 4 accesses to the FIOR to write to both registers The registers are accessed sequentially in this order EOR LSB EOR MSB FOR LSB FOR MSB after which the cycle repeats Resetting the FIFO resets the internal pointer to EOR LSB and sets both EOR and FOR to 7 FIOR can only be accessed when FIOREN is set FIOR may not be read when the FIFO is running EF 0 and FDM1 1 or FDMO 1 FIOR may not be read when running DAC in digital output mode except during blanking FDR Data written to FDRn will be subsequently written to DACn The order is preserved Data reads from FDRn are undefined FDRn can only be accessed when FIOREN is clear FDRn should not be written when the FIFO is full Interrupts Interrupts for the VCL V are via DUART1 IP3 This used to be user jumper G bit position 6 User jumper G is moved to DUART 0 IP6 Interrupts are not latched except in the DUART IPCR Interrupts for the VCL M are assigned to QUART bit IOD1 FIFO Size The actual FIFO size may be 64 256 512 1K 2K or 4K words The effective FIFO size is 1 2 the actual size This is because each FDRn write takes 2 FIFO locations 1 for the a
14. 1 Bidirectional Keyboard Data 1 not used 2 6 6 Ground 3 Fused 5 Volts 5A max 4 2 Bidirectional Keyboard Clock 5 Installing Your Rastergraf Display Board 2 34 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 9 Video Connections to the VCL Although all the VCLs have analog and digital video out separate sections are provided for connections to the VCL V and VCL M This is because the front panels for each board are very different In addition the VCL M digital video protocol differs from the other boards VCL V Video Connectors The VCL V has a standard high density 15 pin D sub for analog video and a 68 pin mini D ribbon connector for digital video The connectors are mounted to the front panel of the VCL V Front Panel Name Section Connector Description VIDEO 2 9 3 VGA style HDB 15 video DIGITAL VIDEO OUT 2 9 4 Digital Video Mini D ribbon VCL M Video Connectors The VCL M front panel connector for the analog video is a 9 pin MDSM micro D sub connector A separate cable is required to adapt to a standard VGA connector The digital video output is optional on the VCL M A 20 pin 050 connector is used for digital video and is located just behind the front panel An LVDS compatible ribbon cable can be connected to the header Connector Name Section Connector Description VIDEO 2 9 1 MDSM 9 pin micro D sub DIGITAL VIDEO OU
15. Although the program boots from highest memory it cannot continue running there Therefore using relocatable code the program must jump to normal EEPROM address space Once this happens the control bit changes state so as to allow DRAM to takes its normal place DRAM can be set up in advance of this since it also responds at the bottom of 34020 address space Thus trap vectors and other code can be set up prior to making the jump Autoboot capability is highly desirable when a single tube system is required In this case the board can boot up to its terminal emulator and print out messages from the console port when the VCL console port is connected to the host CPU console port Simple editing can also be done 5 65 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Serial EEPROM The graphics board includes an IC position for an Atmel AT93C66 or equivalent 4 Kb 512 bytes Serial Electrically Erasable Programmable Read Only Memory EEPROM Rastergraf uses this device to store board parameters special initialization tables and serial number The programming of the Serial EEPROM is done through control lines on the DUARTs or QUART Programming on the VCL V DUART EEPROM Signal Name Mnemonic Description DUARTI OPI ECLK Serial EEPROM clock DUART OP2 EDIN Serial EEPROM data input DUARTI IP6 EDOUT Serial EEPROM data outpu
16. LAR bits 0 15 A16 A24 DBR line buffer address bits 0 13 XAR A32 space address bits 0 5 VEC interrupt vector bits 0 7 PLD outputs drive 34020 host address lines CMA 10 25 Data lines DAO DA15 are I O s for the registers and output bits 0 7 of the interrupt vector Generates byte swap and bus control for VCL10 Enables A24 and A32 VME block transfers MACH231 VMEbus arbitrator and bus control Address modifier decoder Generates 34020 autoboot CRTCON byte selects and chip select Control VMEbus 74BCT 16652 bus transceivers Interrupt arbitrator Transmits 34020 interrupt to VMEbus Buffers VMEbus address lines 2 9 Table 4 2 VCL M PCI PMC side PLD Device Summary Device Type Description MACH445 VCL address decoder LAR bits 0 15 A16 A24 DBR line buffer address bits 0 13 PLD outputs drive 34020 host address lines CMA 10 25 Data lines DAO DA15 are I O s for the registers Generates 34020 autoboot CRTCON byte selects and chip select Control PLX 34020 74BCT16652 bus transceivers Transmits 34020 interrupt to 9060 4 13 Theory of Operation Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Part Number VCL10 VCLI VCL191 VCL192 VCLI1 Table 4 3 VCL V and VCL M 34020 side PLD Device Summary Device Type MACH231 MACH231 MACH231 MACH211 MACH211 Description Functions as a 32 bit registered bus transceiver with byte word an
17. The DUARTs and QUART use a 3 6864 MHz oscillator for the master clock Each DUART has internal divider chains provide a full range of software programmable baud rates and timer periods 44 pin DUARTs are used on the VCL V Some control lines are reserved for HSP operations and for programming the serial EEPROM see Section 5 11 Unused inputs are connected to pullups and jumper pin blocks for use as user inputs Three control outputs are used to drive red yellow and green LEDs The RS 232 interface is provided by a MAX208 238 CMOS quad EIA RS 232 receiver transmitter This chip provides four transmit receive complete channels as well as built in slew rate control The chip also includes 10 volt charge pump generators to supply the necessary RS 232 voltage swings and clamping diodes for protection against static charges on both inputs and outputs Each DUART contains 16 register locations several of which are either read or write only The register number shown in the table below is added to the DUART base address in the device buffer to obtain the actual location The values enable TX RX no parity 8 bits char no loop no RTS or CTS 1 stop bit 38 4 KB based on external clock 3 6864 MHz and no interrupts On board Devices and Memories 5 60 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Each DUART has a single interrupt request line which is connect
18. analog and digital video outputs digital is an option on the VCL M e interrupts 40 MHz TMS 34020 Graphics Systems Processor Everything else is controlled by the options Please contact Rastergraf and or refer to the short form catalog for more information about configurations and accessories The following tables show some common models Table 1 1 Common VCL V Configurations Overlay 34082 34020 X Windows Model Memory FPU Memory Compatible VCL V 24 X16 yes yes 32 MB yes VCL V 8 X10 yes option 4MB yes VCL V 8 X12 yes option 16 MB yes VCL V 8 X16 yes option 16 MB yes Table 1 2 Common VCL M Configurations Overlay 34082 34020 X Windows Model Memory FPU Memory Compatible VCL M 8 X12 yes n a 16 MB yes VCL M 8 X16 yes n a 16 MB yes Part number notes see next page Display Format 1600 x 1280 1024 x 768 1280 x 1024 1600 x 1280 Display Format 1280 x 1024 1600 x 1280 Pixel Si 24 Ze 8 8 t8 t8 Pixel Si ze 8 8 General Information 1 18 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Part Number Options Xn 1X10 X12 X16 SM 2M 4M 8M FPU HSD HSP 1 19 General Information implies at least 4 MB of DRAM 1280 x 1024 display 1024 x 1024 addressable 1280 x 1024 display 2048 x 1024 addressable 1600 x 1280 display 2048 x 2048 addressable 34020 system memory in
19. etc and control bits for programming the Serial EEPROM 32 bit access only This register is used to set the dot clock frequency for static display feature and some video output options Bits 16 32 Valid Bit 16 Jumper A etc The User Jumpers are read by Rastergraf software to determine startup parameters On board Devices and Memories 5 16 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 5 5 TMS 34020 Graphics Systems Processor The Texas Instruments 34020 Graphics System Processor GSP is a general purpose 32 bit programmable processor with specialized graphics instructions and a 512 byte LRU instruction cache It includes a full set of video timing control registers The 34020 has a 32 bit processor data LAD bus which is connected directly to the 34082 FPU and to a set of two 74BCT16652 16 bit bus transceivers which act as buffers between the low drive capability LAD bus and the high load memory device MAD bus A 34020 s 32 bit host address bus and 34020 to VMEbus data multiplexers support a low latency interface between the VMEbus and the 34020 memory and devices The 34020 takes care of arbitration and data and address bus control for the host interface Commands status display parameters graphics drawing refresh and display update address data are all passed over these common busses The 34020 operates on memory in byte word or long w
20. height of video memory width of displayed part of video memory height of displayed part of video memory Note Locations 12 18 1C 36 3C 4C 50 5A 5E 68 7E reserved On board Devices and Memories 5 34 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 5 6 1 Application Note Tweaking 34020 Initialization Parameters Ordinarily you should be able to use one of the initialization tables shown in the list on the previous pages However it may be that small adjustments are required This section gives you some advice on how to do this You can also supply Rastergraf with a filled in copy of the monitor parameters sheet which follow this section We can then provide you with a complete correct calculated version Most monitors have adjustments for Horizontal Frequency Horizontal Position Horizontal Size Vertical Frequency Vertical Position and Vertical Size It is recommended that the monitor adjustments be tried before changing values in the initialization table To change the horizontal frequency Indications that the horizontal frequency needs to be changed are an unviewable picture with diagonal lines Some monitors display no picture when the horizontal frequency is out of its bandwidth The same symptoms can be caused by no sync at all so make sure that the cables are connected correctly and that the monitor is configured correctly The VCL default outp
21. memory via its 32 bit data bus and multiplexed row and column address bus Access is controlled by the 34020 The VCL display memory size is a function of the board type and the display configuration Except for special cofigurations the VRAM is contained on a daughterboard which contains the correct amount of the VRAM for the configuration VCL V 8 and VCL M 8 Display Memory On these boards the pixel memory size is 8 bits for both primary and overlay Each long word contains 4 pixels starting pixel 0 located in byte 0 bits 0 7 Separate address spaces are allocated for the primary and overlay memories For a VCL with a 640 x 480 display the minimum primary video memory is 1 MB of byte addressable memory Using a VMEM8 daughterboard video memory is expandable to 8 MB overlay takes a comparable amount The VCL V 8 baseboard can hold up to 2 MB each of primary and overlay memory The VCL M 8 is limited to 4 MB total of VRAM and has no VMEM option VCL V 24 Display Memory On the boards pixel memory size is 24 bits for primary and 8 bits for overlay The primary and overlay share the same address space the primary uses the low 24 bits of each word Red is byte 0 Green is byte 1 and Blue is byte 2 and the overlay uses the top 8 bits byte3 For this Theory of Operation 4 10 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf reason the writemas
22. reads back 0 no no 7 A24EN clear A16 DBR access set A24 DBR access yes sysreset 6 CRTCON turns on the 34020 yes sysreset 5 MEMON enables the DBR addresses yes sysreset 4 XMEMON Enables 32 bit address response yes sysreset 3 A1624SWAPEN Enables A16 and A24 swap mode yes sysreset 2 VINTEN VMEbus interrupt enable yes sysreset l A32SWAP Enables A32 swap mode yes sysreset 0 XARSEL Select XAR register access yes sysreset On board Devices and Memories 5 4 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 5 2 CSR Bit Definitions REVFLAG A24EN CRTCON MEMON XMEMON Al1624SWAPEN VINTEN A32SWAPEN XARSEL 5 5 On board Devices and Memories used by software to determine that this is a board with PC Keyboard and byte swapper capability This bit reads back set allows the 1K DBR address range to respond in A24 space The CSR is still only addressable in A16 space turns on the 34020 It must be set before the 34020 has been loaded with its timing parameters See Section 5 4 When CRTCON is reset the 34020 internal register set is held cleared allows the board to respond to the IKB DBR line buffer address range allows the board to respond to the 32 bit address range Enables byte swapping in the DBR A16 or A24 address range Note that when this bit is set the DBR address range expands to 4 KB from 1 KB allows the 34020 on th
23. 10 B9 GND 36 Vsyne 9 A9 VSYNC 35 GND 14 B8 GND 1 CLK 13 A7 2CLK GND 12 B8 GND Power Supply 33 67 34 5 volts 3 4 A12 B12 VL connect to supply 24 volts 5 6 A11 B11 VD 30 65 32 Ground 7 8 A10 B10 GND Logic power connector is a standard dual row standard 1 connector 2 51 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 2 33 Panel Side Connector Summary Sharp Panel Model Connector Type Manufacturer Model Number LQ10DX01 CN1 21 pin Bdto Bd Hirose DF9B 21S 1V CN2 15 pin Bd to Bd Hirose DF9B 15S 1V CNA CNB 3 pin Honda QZ 19 3MYL LQ12D011 CNI 30 pin 1 mm FPC Elco 006200 307 032 800 CN2 15 pin 1 mm FPC Elco 006200 157 032 800 CN3 6 pin 2 5 mm JST EHR 6 LJ64ZU48 9 CN1 26pin 1 dualrow 3M CHG 2026 001010 KCP LQ10D011 CNI 22 pin 2 mm Hirose DF11 22DS 2C LQ10DH11 i j JAE LX DC22 LQ10DH15 CN2 CN3 8 pin Molex 51005 0800 LQ10D021 CNI 15 pin 05 Hirose DF13 15S 1 25C LQ9D011 CN2 6 pin 05 Hirose DF13 6S 1 25C CNA CND 2 pin JST S2B EH NEC Panel Model Connector Type Manufacturer Model Number NL10276AC20 01 CN1 68 pin Mini D 3M 10168 6000EC NL128102AC20 04 CNI 20 pin Mini D 3M 10120 6000EC 1280 analog CN2 8 pin JAE IL Z 8S S125C3 CN3 11 pin JAE IL S 11S S2C2 S NL128102AC20 05 CNI 68 pin Mini D 3M 10168 6000EC 1280 digital CN2 16 pin JSt S16B PHDSS Other manufacturers of display panels in
24. 2 3 3 _ 35 Em a A amp H Byte 2 a a JP407 E gt Pare foal e Dm g JP102 JP409 a a E z i kd s p Byte3 i JP41 0 Ea 3 A JP403 o P ELELE Ue E 2507 Jel x z JP404 R jl JEE m JSection D Ja Ay g gt j g Z alld 2 3 3 i fa T E more _ F Ja pE JP101 A F203 bled fia Hoo E 3 A Section lt IE IJ 2 6 7 f Z E J 2 z I4 3 JP401 Jagg amy i oa 8 4 Y 2 CY E3 ce 8s N i o g Q eS x poe lt vs mg 2 8 Ja RAT 3 2 E g gt E 7 Installing Your Rastergraf Display Board 2 10 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 4 VCL M Installation The VCL M is designed to plug into any IEEE 1386 compatible single module PMC location PMC locations are currently supported on VME and CompactPCI compatible computers and PCI PMC expander boards The VCL M will work also corr
25. 44 BAI BOO Blue Pixel A bit 0 24 46 GB3 G12 Green Pixel B bit 2 22 13 GB2 G11 Green Pixel B bit 1 21 48 GBI G10 Green Pixel B bit 0 20 50 GA3 G02 Green Pixel A bit 2 18 17 GA2 G01 Green Pixel A bit 1 17 52 GA1 G00 Green Pixel A bit 0 16 54 RB3 R12 Red Pixel B bit 2 14 21 RB2 R11 Red Pixel B bit 1 13 56 RB1 R10 Red Pixel B bit 0 12 58 RA3 R02 Red Pixel A bit 2 10 25 RA2 R01 Red Pixel A bit 1 9 60 RAI ROO Red Pixel A bit 0 8 3 Hsync HSYNC Horizontal Sync 6 36 Vsync VSYNC Vertical Sync 4 1 CLK CK Pixel Clock 2 2 26 even GND GND Ground 1 3 5 7 35 59 odd 15 19 23 27 VCL Signal LQ12D011 LQ12D011 Pin Name Name Description Pin CN2 33 34 67 5 V Vcc sequenced 5 5 6 31 64 66 12 V Vdd sequenced 12 1 2 no connect no connect 9 12 14 15 30 32 65 GND GND Ground 3 4 7 8 13 VCL Signal LQ12D011 LQ12D011 Pin Name Name Description Pin CN3 connect to power supply Vdd Backlight 12 1 connect to power supply Vetl Backlight enable 2 connect to power supply GND Ground 3 no connect no connect 4 no connect DIMh DIMI1 connect pins via 1K pot 5 6 Milgray Electronics see last page of this section for address has an engineering kit for the LQ12D011 the part number is Milgray RT 42 2 49 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 2 31 Sharp 640 x 480 Panels VCL connector PX Windows LQ10D011 LQ10DH11 LQI
26. 7 you choose whether the primary or the overlay is to remain fixed Then you use the DPYST registers to move the other display around Static Display and Panning If you want to hold a screen static and horizontal pan the other and midline reload is on then you must also set the GPCR register bit MLPEN and change DPYMASK to double the number of reload cycles from 512 pixels to 256 pixels yes you read it right In the table x is V P or M and y is V or P Board Type MLPEN clear MLPEN set VCL x 8 Set DPYMASK bit 6 Clear DPYMASK bit 6 VCL y 24 Set DPYMASK bit 8 Clear DPYMASK bit 8 This results in a performance hit because it increases the number of midline reload cycles so don t use this function unless you need to On board Devices and Memories 5 42 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 5 7 General Purpose Control Register The General Purpose Control Register GPCR contains control bits for the Static Display option the optional ICS1562 PLL for genlock and miscellaneous sync polarity and video timing control bits The pixel clock is generated with a programmable Phase Locked Loop PLL oscillator The PLL is located either in the RGB561 RAMDAC or when genlock external sync is required an ICS1562 The RGB561 PLL is programmed via its microprocessor port The ICS1562 is programmed using the GPCR The GPCR supports D16 D32 cyc
27. A E neler E EEEE ESE 5 31 5 7 GENERAL PURPOSE CONTROL REGISTER meneen eara ar EEEE EEN AE EAER E AE AE ENE 5 43 5 8 RGB561 COLOR MAP CURSORS AND PIXEL CLOCK c cccccesscceeesseeeesseeeceesececsesaeeeceneaeessseeeenaas 5 46 5 9 SERAL VO PORTS eneren eE E EE EOE EKO EE S EEEE 5 60 5 10 PC KEYBOARD MOUSE CONTROLLER 8242PC ccccsssssseeseeeseesecesecesecseceesaecaecaaecaeeeaeseneeeneeenees 5 62 5 11 VCL V HIGH SPEED DATA PORT HSP kciios iodinea ai e eade e ETE EEEa 5 62 512 VCL INTERRUPTS sie ci ea eE E E E a E 5 64 5 13 FLASH EEPROM AND SERIAL EEPROM cccccccccecsesssssceceeececsenseseeeeececeesssaeceeecesesnsaeeeeseeesenseaees 5 65 CHAPTER 6 TROUBLESHOOTING sscccccccssssssssssrsscccsssssssssscsscesscssssssssssees OWL 6 1 INTRODUCTION isecscssdsvccegeveccaettceesadtenscedagecavce staves stakecessoseusassegesaneacquvsscdeeeaded egucgenddieaeend gueaexteteuedensxcts 6 1 6 2 SELECTING AN ADDRESS RANGE FOR THE VCL V BOARD cccssccessseseseeseeeeceseeecessaececseseeeesseeeeneaaes 6 2 6 3 VCL V MEMORY MAP EXAMPLE ccsescecesssececssececessaececsesaececseeecsesaeeecsesaeesseaeeecsesaesecseseesesseeecseaaes 6 4 6 4 DOES THIS VCL V BOARD TALK AT ALL cccccecesssccesssececssseececsueeeceesaeeecsesaeesssseeecsesaececseseeesssueeeeseaaes 6 5 6 5 GENERAL PROCEDURES c cccssssscecseseeseessececsssaeeeceeeeesesaeeecsesaesecseeecsesaeeecseaaeessaeeecsesaececseseesessaeeeesenaes 6 7 6 5 DEALING WITH THE PCI BU
28. EEPROM tables you can at least get to the default table set Review Remember that if Serial EEPROM has tables loaded then PTERM will not follow the table below exactly But if jumper G is installed PTERM will follow this list exactly Table 2 6 Default Initialization Table Selection Options Table Jumper Table Screen Number G E D Name Dimensions 0 in out out L VX168 ibm 1600 x 1280 1 in out in L VX128 ibm 1280 x 1024 2 in in out L VX108 ibm 1024 x 768 3 in in in L VVGA8 ibm 640 x 480 4 7 out in out in out Serial EEPROM tables custom for VCL 8 5 for VCL 24 When Jumper F is not installed the PTERM screen size is set to be 80 characters x 24 lines When the jumper is installed you get a full screen whose row and columns dimensions are a function of the initialization table PTERM reports the dimensions on its startup screen In order to make the VT100 emulation mode work correctly with the vi editor you need to set the TERM environment variable to TERM vt100 If you use the full screen then you also need to stty rows cols where the rows and cols are the numbers reported by PTERM on its startup screen Installing Your Rastergraf Display Board 2 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Other PTERM Features Self Test While starting up PTERM will turn on the yellow Test light It will then turn all t
29. Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com rtisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Theory of Operation 4 1 Introduction Section 1 2 contains a complete Functional Description Please refer to that section before continuing with this chapter which contains a somewhat detailed look at the proprietary parts of the VCL design We depend on the manufacturer s data sheets to provide information about standard devices such as color map chips and DUARTs and so they are not covered here Chapter 5 does have some application specific information This manual deals with both of Rastergraf s VCL series 34020 based graphics boards The awkward places which result are in having to delineate differences between boards while maintaining a coherent flow in the material The most significant differences arise out of the variety of bits pixel options 24 bit true color for the VCL V 24 and 8 bit color for the VCL V 8 and VCL M 8 While reading this material you may want to refer to the block diagrams appended to this chapter In the following sections host bus means VMEbus or PCI bus This chapter has the following sections 4 2 VCL V System Design 4 3 VCL M System Design 4 4 54020 Functional Unit 4 5 Master Clock 4 6 Display Memory 4 7 System Memory 4 8 Summary of Programmed Devices Artisan Technology Group Quality Inst
30. L3 L5 L6 L7 Character 3 is always V Display Characters 4 6 Format VGA 640 x 480 X10 1024 x 768 1x1 1024 x 1024 X12 1280 x 1024 X16 1600 x 1280 Vertical Horizontal Pixel Refresh Refresh Clock 60 Hz 31 5 KHz 27 MHz 70 Hz 60 KHz 80 MHz 60 Hz 64 KHz 85 MHz 60 Hz 64 KHz 110 Mhz 60 Hz 79 KHz 170 MHz Character 7 is 8 for VCL 8 board and 9 for VCL 24 board The following two pages contain an actual Rastergraf timing table as generated by Rastergraf s in house timing table program VIDP This table applies to the VCL V 8 X12 It is included only for illustrative purposes On board Devices and Memories 5 32 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 5 17 Example Initialization Table 1280 x 1024 110 MHz Rastergraf Initialization Generated with the following command line options Ibi bt VCL1 canned L X12 561 isvme y duarts 2 scsi n overlay n halt y 1024 lines 1280 pixels non interlaced 1561 derived frequency of 110 000000 MHz actual frequencies horizontal 63 953488 KHz vertical 60 562016 Hz Version of generator main 68 Wed Nov 1 10 40 59 PST 1995 TI34020_BT 0x34 0x110a config 0x10 0x0040 dpyctl 0x16 0x0000 controla 0x5c 0x007f dpymsk Oxle 0x0000 hstctll 0x20 0x8000 hstctlh 0x40 0x0000 dpystl 0x42 0xc800 dpysth 0x22 0x0000 intenb 0x24 0x0000 intpend 0x26 0x0000 convs
31. PLX9060 also has DMA Registers which are only accessible via Local Address Space Configuration Registers The PCI Configuration Registers are accessed by PCI bus configuration cycles The addresses are 0 to 0x3C as are all PCI devices The slot decode is system dependent These registers are usually accessed after a hardware reset by firmware e g BIOS This is when the BARs are assigned They are written with 1 then read to determine their size requirements then written with their base addresses Refer to the PCI specification for detailed information Some of the PCI Configuration Registers are loaded upon reset by a serial EEPROM on the VCL M This happens before the registers are accessed by the firmware These are Device ID Vendor ID Class Code Revision ID Max lat Min Gnt Interrupt Pin and Interrupt Line Certain Runtime Registers are also loaded which affect the BARs See Table 5 3 for the values Rastergraf s EEPROM loads these registers with The PCI Configuration Registers can also be accessed through Local Address Space Runtime Registers The Runtime Registers are divided into two sections Local Configuration Registers 0x00 0x2C and Shared Runtime Registers 0x40 0x6C The Local Configuration Registers control Local Address Space and Expansion ROM range bus control and remapping These registers are loaded by the Serial EEPROM upon system reset The Shared Runtime Registers control mailboxes doorbells and interr
32. Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Overlay and Cursor Color and Priority In addition to the 8 or 24 bit primary input the RGB561 contains additional table entries for the 8 bit graphics overlay planes and 3 entries for the 2 bit cursor Each table entry is a 24 bit value 8 bits each for R G and B For both the cursor and overlay planes pixel intersections between any of the planes results in a unique color so that the pixels will still be visible This is because the overlay has a higher priority than the primary input in selecting an output color value In other words as long as the data bits going into the overlay inputs are NON ZERO they will select a color for a particular pixel position The cursor has priority over both primary and overlay pixels Setting control bits the 561 splits the overlay plane into overlay underlay mode Several combinations are available Window Attribute Tables WAT The RGB561 contains window attribute tables which allow the user to specify on a pixel by pixel basis many of the attributes of the frame buffer including pixel size for primary and overlay and frame buffer A B mapping Except for a special VCL 8LC configuration and blink the VCL software does not support the use of the WATs Using the WAT with the Primary Only VCL 8 Special versions of VCL 8 combine the primary and overlay memory as one 2K x 1K or 2K x 2K
33. The swapper can give between 5 and 15 performance boost under PX Windows The swap mode expands the address space and allow multiple mappings to the same physical memory This permits swap modes to be changed on the fly without changing control bits The only penalty is memory space requirements on the VMEbus which jumps by 4 times A16 A24 Swap Modes If A1624SWAPEN is set then the 1 KB DBR expands to 4 contiguous 1 KB DBRs and the lower 2 bits of the DBRADR are don t care The 4 KB block must start on a 4 KB boundary Each DBR points to the same memory on the board but with a different swap mode offset swap mode 0x000 none 0x400 byte 0x800 word 0xC00 both A32 Swap Modes If AZ2SWAPEN is set then the 64 MB space expands to 4 contiguous 64 MB spaces and the lower 2 bits of the XARADR are don t care The 256 MB block must start on a 256 MB boundary Each 64 MB space points to the same memory on the board but with a different swap mode offset swap mode 0x00000000 none 0x04000000 byte 0x08000000 word 0x0C000000 both On board Devices and Memories 5 22 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Swap Mode examples ABCD refers to 4 bytes 0 3 big endian or 3 0 little endian Swap mode examples may be verified by writing in each mode and reading back in none mode or by writing in none mode and reading back in each mode The examples reflect D32 accesse
34. VCL display memory at a position determined by software Frames are transferred at a rate determined by software and can be as often as 30 times per second with a 640 x 480 display frame A write mask register protects any or all bits in the display memory from being written during the transfer process Experiment has shown that data can be transferred at a sustainable rate of one 640 8 bit pixel line in about 67 us Thus there is ample margin to satisfy the data transfer requirements and still perform routine graphic On board Devices and Memories 5 62 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 5 63 On board Devices and Memories functions The control lines use four spare control lines lines in DUARTO All bits are read or write only The lines are as follows Table 5 26 DUART Control Bit Usage for HSP Address R W Mnemonic Function 113 R only W only IPCR Bit 0 ACR Bit 0 Bit 1 Bit 2 DUARTO Input Port Change Register PRDYL allows the UE to tell the VCL V when it has the first long word of pixel data available to be read PRDYL must be driven high within 150 ns of HSL going low if data is not ready PRD YL low indicates that data is ready and that REL may be activated Software will poll PRDYL before initiating the transfer sequence and will not activate REL until PRDYL goes low Once the software starts reading the data PRDYL is ignor
35. VCL is the system arbitrator The function of the arbitrator is to allow the VMEbus to access the non 34020 related functions on the VCL and to provide handshaking between the 34020 and the VMEbus for 34020 related functions The VCL has four addressable registers CSR group on the VMEbus side of the board and 8 devices on the 34020 side 34020 writemask register color map cursor controller 2 DUART serial I O chips PC Keyboard controller and general purpose control register Although the VMEbus can access the 34020 side devices the 34020 cannot access the CSR group Separate device address decoders are therefore required to select the 34020 devices Note that because they are all on the 34020 side of the board the arbitrator is not required for 34020 access to display or processor memory or any device except the CSR group which the 34020 can t access anyway Arbitration is required for VMEbus access to any part of the board Theory of Operation 4 2 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Control Register Decoding CSRREQ CSRREQ is used to request non 34020 related functions CSR group When the arbitrator receives a valid request it grants access by asserting VSTRB and gating the address and data onto the board s internal busses Once the operation is complete about 100 ns DTACK is set terminating the VMEbus request Line Buffer Decoding TOREQ
36. VMEbus system it is necessary to window into on board memory because it is so large maximum memory capacity on the board is more than 48 MB The 1KB window is an efficient way of doing this The VCL V also has a 64 MB window in A32 VMEbus address space which allows direct access to all on board memory VMEbus D32 block transfers are supported for A16 A24 and A32 address spaces which allows up to 256 bytes to be transferred at high speed over the VMEbus Another performance feature for the boards is a hardware byte swapper When enabled four 1 KB buffers are mapped to the board which provide unswapped byte word and long swaps respectively The board has a VMEbus interrupt controller which supports a vectored interrupt from the 34020 VCL M Host Bus Interface The VCL M is designed to interface to a host processor which uses the PCI bus They use a PLX9060 PCI to Local Bus bridge to interface the host processor to the 34020 host bus control The 9060 contains PCI bus local bus and on chip DMA control registers By necessity therefore the software specific to setting up the control registers is different from the VCL V Device interrupt enables line buffer response enable 34020 hardware reset programmable line buffer address interrupt vector address and programmable extended address decoder bits are all contained in the 9060 The LAR is a separately addressed 16 bit register which maps a portion of the 34020 address space into
37. accesses in A32 space However bytes 0 and 1 bits 16 31 are undefined for D32 accesses to the CSR block Byte D8 writes to the CSR block have no effect only D16 and D32 writes will change these registers Byte reads however do return the correct data 6 4 Troubleshooting Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 6 4 Does this VCL V board talk at all Note Most 680xx based CPU boards use some variation of the Motorola debugger for base level communications and diagnostics The installation debug section uses the Motorola version of the debugger in the examples It is a great help in determining the cause of a board problem if you have either the PTERM or autobooting CnP PROM because if you get a display on power up it is a reassurance that the board probably works If you don t have a PROM then you are running blind especially if this is a new installation Typical equipment required for the test is a suitable monitor analog RGB with sync on green and a MVME167 based computer with Unix System V Rastergraf supports QIC 150 cartridge tape distribution media If you have problems with the board responding you may have an address conflict This section tells you how to check to be sure there are no other devices which respond to its addresses The board in this example follows MVME167 VMEbus address assignments with respect to A16 A24 and A3
38. already made up All you have to do is wire the other end The part number is CA111972 22 Note due to a layout error the pin which is marked on the PCB with a square indicating pin 1 is on the wrong pin It is actually on pin 5 The pin list below shows the correct ITT Cannon pin numbers Just ignore the pin 1 square on the PCB Table 2 19 VCL M Serial Connector Pinout MDSM Pin Number Description Bidirectional Keyboard Data Bidirectional Keyboard Clock not used Bidirectional Mouse Data Bidirectional Mouse Clock Ground Fused 5 Volts 25A max Fused 5 Volts 25A max Ground OANNDNABRWNH MKM 2 2 VCL M to PS 2 Breakout Cable The MKM cable is the MDSM to dual PS 2 cable The MDSM end plugs into the VCL M and is retained with jackscrews The PS 2 ends plugs into the computer side of a PS 2 PC Comaptible Mouse and or Keyboard The following table provides the wiring information 2 33 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 2 20 MKM Cable Connections MDSM Name Mouse Pin or means jumper controlled PS 2 Pin Number TX or to means VCL is source Number 4 Bidirectional Mouse Data 1 not used 2 6 9 Ground 3 8 Fused 5 Volts 5A max 4 5 Bidirectional Mouse Clock 5 Keyboard PS 2 Pin Number
39. and reduces emitted noise A twenty pin 050 header is located near the front panel which can connect to an off board LVDS micro D ribbon connector Contact Rastergraf about information regarding panel compatibility and LVDS interfacing A 15 pin MDSM micro D Sub connects the four serial channels via a breakout cable to two offboard DB 9 connectors The ports are used nominally for the console mouse trackball and serial keyboard Ordinarily the serial keyboard RS 232 lines are used for RTS CTS for the console port In this case then you only have 3 ports Fused 12 volts is provided on the mouse connector Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf PS 2 Connector Module Size Power Requirements Environment A 9 pin MDSM micro D Sub connects via a breakout cable to two 7 pin Mini DIN PS 2 type connectors These are provided for the PC keyboard and PS 2 mouse peripherals Fused 5 volts is provided on the connectors Standard IEEE 1386 PMC bus card 149 mm x 74 mm 5V 5 1 5 A typical Temperature 0 to 70 degrees C operating 55 to 85 degrees C storage Humidity 10 to 90 non condensing General Information 1 16 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 1 5 Monitor Requirements Rastergraf graphics boards can be used with a wide variety of mon
40. artisantg com Rastergraf The VCL V only does include sequenced 5 and 12 on the digital connector 1 A max may be drawn from each source MOSFET switches controlled by a digital timer supply 5 then 12 to the connector The VCL M encodes a single overall enable line in the LVDS output Backlight Power and Control The digital panels also require a backlight so that the display is visible Typically the backlight is two or more small fluorescent lights powered by an inverter which runs off the 12 volt supply Some panels require 24 volts You will have to have a separate power supply to take care of this Because of the typically high current draw and the noise which can be fed back from the inverter supply Rastergraf advises you to run a separate power supply line to the inverter power input Do not use the sequenced 12 supply from the VCL 68 pin connector Some panels may have separate brightness and display enable controls Although the VCL does have a blanking signal it does not provide any support for brightness adjust Caution Some example connection tables are shown on the following pages They are believed to be accurate Please verify them against the data sheet which you received with your panel Please contact Rastergraf if you have any questions or difficulties Installing Your Rastergraf Display Board 2 44 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE ww
41. available for modules which are out of warranty or which have sustained damage making them ineligible for warranty repair A flat fee will be charged for normal repairs and must be covered by a valid purchase order If extensive repairs are required Rastergraf will request authorization for an estimated time and materials charge If replacement is required additional authorization will be requested All repair work will be done at the Rastergraf factory in Redmond Oregon unless otherwise designated by Rastergraf Troubleshooting 6 11 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com rtisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Index 1 Mb 4 Mb DRAM 4 11 16 Mb DRAM 4 11 256 MB Window 5 6 32 bit addressing 5 4 32 bit memory 5 6 34020 4 2 5 17 34020 and PCI bus Register Offsets VCLLAR 400 5 30 34020 and VMEbus Register Offsets VCLLAR 400 5 29 34020 device addresses 5 23 34020 display calculations 5 31 34020 interrupt functions 5 64 34020 memory addressing 5 23 34082 5 18 3D transformation routines 3 8 64 MB Window 5 6 8242PC 5 62 A16 6 2 A16 space 5 25 A16 A24 Mapping 5 7 A1624SWAPEN 5 4 A24 6 2 A24EN 5 4 A32 6 2 A32 space 5 25 A32SWAPEN 5 4 Additional References 1 8 address bus 4 8 address decoder 4 2 Address Match Registers 5 7 address space 2 4 analo
42. boot to PTERM a simple vi compatible terminal emulator CLP or PX Windows ROM images included SmartPTERM can store and modify initialization tables and configuration data in the VCL s Serial EEPROM The ability to reprogram the serial EEPROM from SmartPTERM requires that a keyboard to be plugged into the VCL SmartPTERM s BIST results can be reported either to the VCL screen or a serial terminal or read by the host through a VCL register Caution Jumper definitions are changed with boards which use SmartPTERM Consult the SmartP TERM documentation for correct settings Console Emulator PTERM or SmartPTERM The VCL console port is connected to the host CPU serial terminal connector The graphics board functions as a terminal on power up Once the PX Windows or Graphics Subroutine Package program starts up the console terminal function goes away and may not be recalled No hot key provision to dynamically switch between the application program and the firmware exists at this time However in PX Windows the firmware may be restarted by first running a special program which kills the server Installing Your Rastergraf Display Board 2 22 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 6 Checking your Display Turn on the power and check your monitor s display If your graphics board does not use a PTERM terminal emulator or the CLP Graphics Subr
43. console terminal port if you don t use the fourth serial port This is done because the RS 232 gates for it are used instead to provide RTS and CTS to the Console port The two VCL serial connectors are DB 9 type Each are wired to support two serial ports The MOUSE connector has the Serial Mouse Port 0 and the LK401 Serial Keyboard Port 1 The CONSOLE connector has the Console Port 2 and the Secondary Pointer Port 3 The Secondary Pointer port is available only if the jumpers are not set for RTS CTS Fused 12 and 5 are provided since the mouse and keyboard require power The 5 and 12 are protected by auto resetting fuses which are PTC elements which reset automatically when an overload is removed Important Notes Total current draw for all fused 5 volt outputs should not exceed 5 A Total current draw for all fused 12 volt outputs should not exceed 5 A There is a 220 ohm current limiting resistor in the 12 volt line to Mouse Connector pin 7 and a 470 ohm current limiting resistor in the 12 volt line to JP405 pin 1 which can be jumpered to Mouse Connector pin 3 Silkscreen chamfers at one end of a jumper strip indicates Pin 1 The Rastergraf Display Subroutine Package CLP includes support for PS 2 mouse and keyboard devices and general purpose serial I O routines It has no specific knowledge of any device connected a serial port Sample Installing Your Rastergraf Display Board 2 24 Artisan Technology G
44. default possibly slower if HPFW HSTCTLH is set Additional note on using VMEbus block transfers To address the TI HSTCTLH register 1 Set LAR to 0 LAR is usually at VMEbus address 0xFFFFC004 2 Access the HSTCTLH at VMEbus offset 0x22 from line buffer base thus OxFFFF8022 assuming line buffer base is OxFFFF8000 Set Bit 12 HINC in that register location On board Devices and Memories 5 8 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Note Bit 12 is little endian bit 12 and it is bit 12 i e 0x1000 not the 12th bit rather it is the 13th bit USE A BIT SET instruction DO NOT JUST WRITE A WORD OF ZEROES WITH BIT 12 SET Also use a D16 not a D32 transfer 3 Note that ONLY 32 bit transfers can be done 4 Rastergraf has measured an average 18 MB s transfer rate using the MVME162 DMA controller in block tansfer mode 5 9 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 5 3 PCI bus VCL M Control Registers PLX9060 The PLX9060 has decodes for PCI Configuration Registers Runtime Registers Local Address Space and Expansion ROM The VCL M does not need to use the Expansion ROM decode Except for the PCI Configuration Registers which have a fixed size and address each decode has a Base Address Register BAR associated with it The
45. do not Grounds must be paired with signals What to do With Unused or Extra Data Lines If your panel doesn t use all the data lines from the VCL V don t include the unused data lines in your cable assembly It serves no good purpose to have unused digital video data lines driving extra noise onto the cable If you do encounter noise or jitter problems in your display you may want to add terminations at the panel end of the cable Limiting the cable length to less than 2 5 feet will help ensure reliable operation Panels which do not make full use of the VCL s 12 or 24 bit pixel output should connect the data lines from the VCL starting from the VCL s high order data line 7 For example if you have a panel which just has 3 Installing Your Rastergraf Display Board 2 42 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf bits color 9 color inputs total connect the VCL s Red Green and Blue data lines as follows for 24 bit output mode VCL bit 7 to Panel bit 2 6 to 1 and 5 to 0 for 12 bit output mode VCL bit 3 to Panel bit 2 2 to 1 and 1 to 0 Leave the unused data lines unconnected at the VCL end You will probably have to make the cable out of twisted pairs since unless you split it up ribbon cable will force you to pick up extra lines Alternatively you may have a panel which has more input bits than the VCL output can supply This can happen if y
46. flat panel interface using a direct TTL compatible interface The VCL M 8 uses an encoded LVDS Low Voltage Differential Signalling protocol developed by National Semiconductor and VESA LVDS allows longer cable lengths and is more noise tolerant Host Bus Interface The VCL communicates with the VME or PMC host bus processor via a host bus interface Graphics board memory and on board devices are accessed through control registers and a 1 KB line buffer which are located in VMEbus A16 space or PMC memory address space The VCL V line buffer can also appear in A24 space The VCL V differs with the VCL M with respect to the implementation of the control registers The following sections detail these differences 1 5 General Information Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf VCL V Host Bus Interface The VCL V has a four word control register group The CSR contains device interrupt enables line buffer response enable and 34020 hardware reset The LAR is a 16 bit register which maps a portion of the address space of the graphics board into the 1 KB line buffer Two additional registers include programmable line buffer address interrupt vector address and programmable extended address A32 decoder Access to the board through the A16 space provides a lowest common denominator access mode which allows the board to be compatible with any host CPU In an A16
47. for availability Figure 3 1 Software Development Flow assembler C source files C compiler object files source object COFF object libraries files graphics linker subroutine gt library Software Summary 3 10 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Features of the 34020 Development Tools e Standard Kernighan and Ritchie C Compiler with extensions compiles standard C programs as defined by The C Programming Languge This is a full featured optimizing compiler using advanced techniques for generating efficient compact assembly code The compiler supports these standard extensions enumeration types structure assignments passing structures to functions and returning structures from functions e Assembly Language output is generated by the compiler from the C source An interlist utility associates each C source line with its corresponding assembly code output The Assembler translates the assembly language source output from the compiler into 34020 machine language object files The Linker combines all object files into a single executable module e The archiver allows you to collect a group of source or object modules into a library It also permits you to modify a library by deleting replacing extracting or adding members It is functionally equivalent to ar Unix 3 11 Software Summary Artisan Technology
48. has been set up The hardware byte swapping function can be enabled for A32 space You must first set the AZ2SWAPEN bit in the CSR Note that the A32 space usage increases to 256 MB when A32 byte swapping is enabled The reason for this is revealed in Section 5 3 5 which contains detailed information on the byte swapping The XARADR DBRADR Address Match Registers are programmed through a single register in the CSR block Which register is accessed through the register slot is controlled by the XARSEL bit in the CSR When XARSEL 1 the XARADR address match register is selected Table 5 3 XARADR Address Match Register A32 Space XARADR Address Bit Data Bit R W Reset 26 0 yes SYSRESET 27 yes SYSRESET 1 28 2 yes SYSRESET 29 3 yes SYSRESET 30 4 yes SYSRESET 31 5 yes SYSRESET 6 31 reads 0 no Note When A32SWAPEN is set XARADR 0 and 1 are don t care On board Devices and Memories 5 6 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 5 2 4 A16 A24 Address Map and DBRADR Address Register The VCL s A16 A24 I O standard addressing function allows the board to respond for the line buffer DBR in A16 or A24 space In order for the A16 A24 space on the board to respond the DBRADR register must be set up with a valid address the 34020 must be initialized and CSR bit MEMON must be set The only reason for selecting A24 space is if your CPU doesn
49. is an A16 space address the LAR is gated onto CMA 10 25 If instead the address is an A32 address bits 10 25 of the BAR are gated onto the CMA bus 4 3 Theory of Operation Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Note XMEMON disables the VCL s A32 address decoder until it is set by a user program since it is cleared on power up or system reset Rastergraf software doesn t use extended addressing except in multiprocessing Sun and Motorola PX Windows systems Control Registers The 4 word CSR LAR group and a 1 KB line buffer are all in the A16 space A control bit can be used to enable A24 operation for the line buffer when the VMEbus host doesn t support A16 D32 transfers D32 capability is important because long word data transfers will go twice as fast The CSR provides basic control over the board including 34020 reset line buffer response enable A24 enable A32 enable hardware byte swapper enable and interrupt enable The LAR selects which 1 KB section of memory or block of device registers is accessed through the line buffer The line buffer mechanism is used instead of direct addressing because the internal memory capacity of the VCL is in excess of 48 MB which is a substantial amount of address space one that is outside the reach of both A16 and A24 bus masters Alternatively the VCL can respond to a 64 MB section of A32 VMEbus address space
50. of blanking This mode MUST NOT be used when the DAC is in Digital mode There may be a latency of up to 16 pixel clock times for FDMn writes to take effect including changing of the flags 5 59 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 5 9 Serial YO Ports The VCL has four serial ports The VCL V uses two Philips SCN2681 dual serial I O port chips DUARTs and the VCL M uses one Philips SCC26C94 QUART which has all four ports in one chip From a serial I O programming standpoint the registers for the QUART map to the two DUARTs except for some special interrupt registers which are above the second DUART s address space However the mapping of the I O auxiliary control bits which are used not only for RTS and CTS but also a variety of functions local to the VCL are different between the QUART and the DUART Each DUART contains two independent asynchronous serial I O ports Each port can be programmed separately for transmit and receive baud rates with a maximum baud rate of 38 Kb The receive buffers are quadruply buffered to minimize the possibility of data overrun The serial interface provides data leads only RS 232 as well as internal loopback for testing To obtain more understanding of the DUART and or QUARTs please refer to the data sheets available from the manufacturer see Section 1 2 or contact Rastergraf
51. offset 8000 0000 XARADR 20 The board appears at the 32 bit address A32 VMEbus X offset so we would get 1000 0000 8000 0000 9000 0000 On board Devices and Memories 5 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 5 11 VCL V Local Memory Map abcd C000 CSR LAR XARADR abcd COOA DBRADR VECADR A32 A16 LAR 34020 34020 VMEbus VMEbus address zero based X offset D offset addresses for system RAM abcd 0000 C000 0000 34020 Internal abcd 007E C000 03E0 Registers 100000 abcd 0003 400 C080 0000 Device Buffer abcd 03BF C080 ODEO color map DUARTSs PC Keyboard Mouse General Purpose Control Register 20 0000 abcd 0000 0800 C100 0000 High Speed Port 800000 abcd 0000 2000 C400 0000 Flash EEPROM abcd O3FF 2FFF CSFF FFEO 100 0000 abcd 0000 4000 C800 0000 VCL V 24 abcd O3FF 7FFF CFFF FFEO IK x 1K x 32 Primary Overlay Display Plane Four Pages 100 0000 abcd 0000 4000 C800 0000 VCL V 8 abcd 03FF 5FFF CBFF FFEO IkKx 1K x8 180 0000 abcd 0000 6000 CC00 0000 abcd O3FF 7FFF CFFF FFEO 3C0 0000 abcd 0000 F000 FEOO 0000 abcd 03FF F3FF FE7F FFEO 3D0 0000 abcd 0000 F400 FE80 0000 0080 0000 Low mid 1 MB abcd O3FF F7FF FEFF FFEO 00FF FFFF 4 MB Config 3E0 0000 abcd 0000 F800 FFO0 0000 0100 0000 High mid 1 MB abcd 03FF FBFF FF7F FFEO
52. primary only pixel display A control bit switches between Window Attribute Table WAT entry 0 and 1 on a top half bottom half screen period WATO points to the overlay port and WATI points to the primary port Both WATs point to the same area in the color map In detail LWID 2 only 1 bit is actually used WIDO memory pagel WID1 memory page 0 AUX OL WAT1 has overlay disabled AUX OL WATO has overlay enabled OL WATO has transparency set to opaque OL WAT1 is don t care FB WAT and OL WAT start address are the same On board Devices and Memories 5 48 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Using the WAT for Blink The RGB561 does not have a blink register so you can t easily assign a given bit plane to blink In order to rectify this the VCL has an external blink function A programmable rate blink bit controlled by the GPCR is wired to the second bit of the Window Attribute Table control bits When you enable the blink the pixel attribute is toggled between WAT 0 and WAT 2 You can then program the WAT2 entry to point to a different section of the color map and blink to different colors Pixel Clock and Output The RGB561 also contains a programmable Phase Locked Loop PLL which is used to generate the pixel clock internal to the the chip It also supplies a local pipeline reset differential ECL level dot clock and load clock for the
53. section Rastergraf can supply the Rastergraf PS 2 Mouse which uses a small rolling ball and mechanical position encoders A pad is not supplied but can sometimes make the roller mouse operation smoother Table 2 17 PS 2 Mouse Connector Pinout PS 2 Mini DIN Pin Number Description 1 Bidirectional Mouse Data 2 6 not used 3 Ground 4 Fused 5 Volts 5A max 5 Bidirectional Mouse Clock 2 8 2 PS 2 Keyboard The Rastergraf PC Keyboard is a standard PC type keyboard Rastergraf uses the mini DIN PS 2 keyboard connector If you use a standard PC keyboard you will need to get a PC DIN to PS 2 mini DIN adapter which is often included with the keyboard but if not is readily available Table 2 18 PC Keyboard Connector Pinout PS 2 Mini DIN Pin Number Description 1 Bidirectional Keyboard Data 2 6 not used 3 Ground 4 Fused 5 Volts 5A max 5 Bidirectional Keyboard Clock Installing Your Rastergraf Display Board 2 32 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 8 3 VCL M PS 2 Connector Due to space limitations the VCL M uses a 9 pin ITT Cannon MDSM MDSM 9PE Z10 connector for the serial port connections It is necessary to build a breakout cable to make connections to standard devices Rastergraf can supply the cable or you can build it yourself You can get a 3 foot pigtail from ITT Cannon which has the MDSM connector and a shielded twisted pair cable
54. side of PX Windows SmartP TERM and CLP Subroutine Package can be provided in PROM Jumpers permit the board to autoboot into the terminal emulator for use as a console terminal see Section 3 4 below Software Summary 3 2 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 3 3 Write Posting Features of many of the newer CPU designs include pipelining and write posting The CPU which is much faster than the host bus interface is allowed to store or post a write operation to the CPU board s Host bus controller The controller takes care of the write within the timing requirements of the Host bus Pipelining is a procedure whereby the CPU can process more than one instruction at a time As a result instructions are not necessarily completed in the order that they were started In the case of sequential accesses to the Host bus which the Rastergraf boards use it can happen that the a write of the Rastergraf display board Line Buffer can occur before a write to the Line Address Register LAR has been completed If you had wanted to change the LAR and then write you are not guaranteed that this has happened This results in incorrect operation The way to get around this is to immediately read back the data which has been written to the LAR which flushes the pipeline and ensures correct operation Since this is a problem just for the LAR the performance impact is min
55. t support D32 long word accesses in A16 space You will pay a small 10 20 performance penalty for running D16 only Rastergraf software must be explicity told to use A24 space because the A24EN bit in the CSR must be set Note that the 4 register CSR block can only respond in A16 space To enable A24 response turn off MEMON set the DBRADR to match the upper 14 bits of the A24 address then set both MEMON and A24EN The hardware byte swapping function can be enabled for A16 A24 space You must first set the A1624SWAPEN bit in the CSR Note that the A16 A24 space usage increases to 4 KB when byte swapping is enabled The reason for this is revealed in Section 5 3 5 which contains detailed information on the byte swapping The XARDBR DBRADR Address Match Registers are programmed through a single register in the CSR block Which register is accessed through the register slot is controlled by the XARSEL bit in the CSR When XARSEL 0 the DBRADR address match register is selected Remember that MEMON in CSR also has to be set The size of the DBRADR register varies as a function of A24 and byte swapping see Table 5 2 Table 5 4 DBRADR Address Match Register A16 A24 VMEbus DBRADR Address Bit Data Bit R W Reset 10 23 0 13 yes SYSRESET 14 31 reads 0 no Note When A1624SWAPEN is set DBRADR 0 1 are don t care When A24EN is clear DBRADR 6 13 are don t care 5 7 On board Devices and Memories Artisan Technology Group Qu
56. the 1 KB line buffer window Access to the board through the 1K line buffer space provides a lowest common denominator access mode which allows the board to be compatible with any host CPU In some PCI systems even it is necessary to window into on board memory because it is so large maximum memory capacity on the board is more than 48 MB The 1KB window is actually an efficient way of doing this General Information 1 6 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf The graphics boards also have an 64 MB window which allows direct access to all on board memory The PLX9060 supports local chained DMA burst transfers between the host and 34020 memory Initial testing has shown that for Digital UNIX at least there is no better than a 10 benefit to using DMA Rastergraf will evaluate DMA performance on other CPUs and OSs and support DMA in its software when and as it is appropriate Please contact Rastergraf engineering if you have questions about this Peripheral Support The graphics board has four asynchronous RS 232 serial I O ports Ordinarily two ports are used to support serial mouse trackball and console with RTS CTS The other two ports are not allocated Each port can be programmed separately for transmit and receive baud rates up to 38 4 Kb Each receiver is quadruply buffered to minimize the possibility of data overrun Each channel has an inter
57. the A16 A24 and A32 address space assignments in its local bus controller If a controller chip isn t used then the map will be hardwired into the CPU board design For A16 space the high 16 bits of the CPU chip s address space is determined by the memory map and thus the bus controller What this means is that although the CSR block in the graphics board itself only sees the VMEbus address bits A1 A15 you actually use a 32 bit address in the CPU chip to address the board The high 16 bits of the address is predetermined by the bus controller as corresponding to an A16 segment Given the broad range of computers which support the VMEbus it is impossible to cover installation on all of them However we have provided in the following table a representative sampling The table below summarizes the relevant A16 A24 and A32 spaces All boards support A24 spaces too and the graphics board can use it This would only be necessary if your CPU doesn t support A16 D32 accesses D32 accesses give the best data transfer performance If you encounter difficulty please do not hesitate to contact the factory for assistance 6 2 Troubleshooting Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 6 1 Common CPU board addresses Manufacturer Force CPU 30 and CPU 40 Force SPARC CPU s GMS V36 and V46 Motorola MVMEI147S Motorola MVME162 167 187 188 197
58. to 70 degrees C operating 55 to 85 degrees C storage Humidity 10 to 90 non condensing Although Rastergraf is not formally in the militarized business it does offer a ruggedized version of the VCL V Commercial grade components are used The board is protected with a conformal coating It is Miller Stephenson MS 460A spray on and is MIL I 46058C Type SR and MIL T 152B compliant All socketed devices including the DRAM SIMM and Flash are soldered in place The board is tested under extended temperature conditions Temperature 40 to 85 degrees C operating 55 to 85 degrees C storage Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 1 4 2 Specifications for the VCL M VRAM Memory Options DRAM Memory Options PCI bus Access On Board DMA PCI bus Interrupts Bus Loading The small size of the VCL M limits the choice of display memory VRAM relative to the VCL V In fact the VCL M is built in only one standard configuration which is with 4 MB of VRAM It is normally allocated as 2 MB for primary and 2 MB for overlay This is sufficient for 1280 x 1024 displays Using a special initialization table the VCL M can be set to 1600 x 1200 but due to intrinsic timing overhead there is a loss of about 25 in performance for certain graphics drawing functions Alternatively the VRAM can be allocated to serve as 4 MB of primary displa
59. to a comprehensive understanding of 5 17 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf this device and can be ordered from TI or Rastergraf see Section 1 2 Rastergraf offers in depth software support which is covered in Chapter 3 Note that the 34020 registers can be accessed as long words in D32 mode by the VMEbus when the LAR 0 consistent with the register organization shown in the 34020 User s Guide When accessing 34020 registers from the VMEbus as 16 bit words the order of the registers is reversed from what is shown in the 34020 manual PCI Bus accesses do not have this problem 34020 side VME word address address 0 2 2 0 4 6 6 4 etc etc 5 5 1 34082 Floating Point Coprocessor The 34082 Floating Point Unit FPU chip can be installed in the socket provided on the board When properly utilized it can significantly enhance performance TI compiler assembler switches must be set to use it Since the chip select for the FPU always responds you must run an FPU instruction An uncompleted operation will reveal its absence The Coprocessor ID for the 34082 is 0 The VCL M does not support the 34082 The 34082 conforms to the IEEE floating point standard P754 R10 0 for high level math functions In addition it offers transcendental functions trigonometrics hyperbolics exponentials logarithmics etc and non tran
60. true Thinking of a memory block starting from the bottom of the address space the top of that memory block will map to the top of the address space Table 5 10 LAR 34020 Starting Address Table TMS34020 address LAR High Low 34020 Registers 0 C000 0000 Device Registers 400 C080 0000 High Speed Port 0800 C100 0000 EEPROM 2000 C400 0000 Primary Display Memory 1st 2 MB 4000 C800 0000 2nd 2 MB 4800 C900 0000 3rd 2 MB 5000 CA00 0000 4th 2 MB 5800 CB00 0000 On board Devices and Memories 5 24 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 5 10 LAR 34020 Starting Address Table continued Overlay Display Memory lst 2 MB 6000 2nd 2 MB 6800 3rd 2 MB 7000 4th 2 MB 7800 CC00 0000 CD00 0000 CE00 0000 CF00 0000 System Memory referenced to the top of the 34020 address space LAR System Memory 1 MB FC00 4 MB F000 8 MB E000 16 MB C000 32 MB 8000 Last Valid TMS34020 address high low FF80 0000 FE00 0000 FC00 0000 F800 0000 F000 0000 System Memory referenced to the bottom of the 34020 address space System Memory 1 MB n a 4 MB n a 8 MB n a 16 MB n a 32 MB n a n a these addresses are not accessible to the VMEbus 5 5 8 Sample VMEbus Address Calculations 007F FFFF O1FF FFFF O3FF FFFF O7FF FFFF OFFF FFFF This section is intended to help you figure out what VMEbus addresses the board appears at All addresses are
61. video memory However it does share a common address space with the display memory and can thus be used for program store or off screen display data The standard size is 4 MB of 0 wait state DRAM and is expandable to 32 MB There are four 32 pin IC locations which support up to 2 MB of 0 wait state Flash EEPROM Jumpers can be installed which cause the 34020 to automatically start executing from PROM on power up An additional 512 byte serial EEPROM is installed which is used by Rastergraf s programs to store information necessary at power up such as initialization data EEPROM sets can be ordered from Rastergraf which include a simple console terminal emulator combined with the graphics subroutine package and or X11R6 X Windows server Display Features The VCL contains a special function control part which allows the display address for the overlay VRAM to be different from that of the primary VRAM This feature is used to support a waterfall display wherein a static non moving overlay status screen has an image in the primary display memory which is scrolled or panned underneath it Normally the alternatives are to A hardware scroll both overlay and primary and using the 34020 software scroll back the overlay or B just software scroll the primary In either of these cases the 34020 has to copy large amounts of screen data which can result in limited scroll rates In fact a static General Information 1 4 Artisan Technology G
62. which might be convenient for a disk controller Note that in general Rastergraf software uses only the A16 and A24 space addressing modes VMEbus Block Mode The VMEbus supports a high speed data transfer method known as block mode According to the specification up to 64 contiguous long words may be transferred using the technique of implied addressing However the VCL can support as many transfers as you wish Using the Address Modifier control lines the bus master signals its intent to initiate block transfers It supplies a memory starting address and the bus slave i e the VCL using the 34020 s block transfer function supplies its own addresses which increments after each memory cycle This allows the bus master to skip the address output cycle which can result in significantly higher data transfer rates Theory of Operation 4 4 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Data Bus Transceivers and the Byte Swapper The 74BCT 16652 BiCMOS high drive low power registered bidirectional bus transceivers provide a 32 bit path for data transfers between the VMEbus processor and the on board devices during programmed I O cycles Since the board as a VMEbus slave must support D32 D16 and D8 bus transfers the byte swapper which sits in the data path is used to pass 32 bit data straight to the 34020 side or to multiplex data from the high data bits to
63. will need to contact Rastergraf for advice and assistance All the timing parameters will need to be recalculated 3 Change the horizontal frequency Increasing the horizontal frequency will result in a wider image decreasing it will result in a narrower image Changing the horizontal frequency will also affect the vertical frequency To change the vertical frequency Indications that the vertical frequency needs to be changed are a picture which rolls up or down Sometimes the appearance is of multiple pictures one on top of another with multiple horizontal lines An excessively slow vertical frequency will cause the image to flicker Some monitors display no picture when the vertical frequency is out of it s bandwidth The same symptoms can be caused by no sync at all make sure that the cables are connected correctly and that the monitor is configured correctly The default output is sync on green It is best to calculate VTOTAL based on the monitors specified vertical scan rate If that is not possible you can try adjusting it by this method There are two ways to change the vertical frequency 1 Change the horizontal scan rate As vertical timings are in units of horizontal lines the vertical rate will change proportionately 2 Change VTOTAL To decrease the vertical frequency make VTOTAL larger To increase the vertical frequency make VTOTAL smaller VTOTAL must be larger than VSBLNK On board Devices and Memories 5 36 A
64. 0 mA Rastergraf LK401 Serial Keyboard The Rastergraf Serial Keyboard is a modified DEC LK401 AA unit It is especially suited for applications which require long cables It is a 4800 baud unit and supplies a keyswitch matrix code The LK401 uses an RJ11 4 pin handset modular phone connector You will have to build an adapter cable to go from the VCL M breakout cable s DB9 to the LK401 s modular type RJ11 connector Rastergraf software will detect the presence of either a PC compatible keyboard or an LK401 compatible keyboard If both are installed the default is the LK401 Table 2 14 LK401 Connector Pinout RJ11 Pin Number Description TX or to means VCL is source 1 TX Data to Serial Keyboard 2 Fused 12 Volts 3 Ground 4 RX Data from Serial Keyboard Installing Your Rastergraf Display Board 2 28 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 7 3 VCL M Serial Connector Due to space limitations the VCL M uses a 15 pin ITT Cannon MDSM MDSM 15PE Z10 connector for the serial port connections It is necessary to build a breakout cable to make connections to standard devices Rastergraf can supply the cable or you can build it yourself You can get a 3 foot pigtail from ITT Cannon which has the MDSM connector and a shielded twisted pair cable already made up All you have to do is wire the other end The part number is CA111972 11 Note due to a la
65. 0 to restart PTERM It also resets local config registers so if Bit 30 is toggled 1 to 0 then Bit 29 should also be toggled 0 to 1 On board Devices and Memories 5 12 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 5 4 Line Address Register LAR The LAR selects a memory or device register group on the board and permits a 1K Byte segment to be accessed through the DBR Fully configured the board contains a number of programmable devices each of which has between 2 and 16 control registers The board uses spare LAR values 0 and 400 to permit access to all of these devices through the DBR line buffer See Section 5 2 3 for A32 addressing information Note The 34020 must be initialized prior to accessing memories or devices Table 5 6 LAR Bit Definitions LAR 0 400 800 2000 2FFF Video RAM 4000 SFFF 6000 7FFF Memory Selected 34020 internal device registers See Section 5 5 and 5 6 for more information Device Buffer color map DUARTs VCL M QUART PC Keyboard controller General Purpose Control Register High Speed Data input port HSP special VCL V only Up to 2 MB of Flash EEPROM using four 512 KB devices VCL V 8 VCL M 8 Primary 8 bit graphics RAM 1024 pixels for each LAR value 1K x 1K pixels is 1 MB or 1024 LARs Memory is byte addressable and writemask applies Overlay 8 bit graphics RAM 102
66. 0 x 1280 displayable analog resolution Up to 1280 x 1024 displayable digital resolution LVDS compatible digital output VCL M 8 only 8 bit overlay Static overlay repositionable primary display or vice versa Optional multiple display pages Hardware pan zoom and scroll and bitmapped cursors PLL controlled pixel clock Genlock option for system wide synchronization VCL V only Non interlaced interlaced NTSC PAL and high refresh rate displays Optional 32 bit High Speed Data port VCL V only Optional autoboot console terminal emulator Low power BiCMOS bus transceivers and Lattice MACH FPGAs Single 6U VMEbus board or PMC single wide module Ruggedized version available Graphics Subroutine Package X11R6 X Window System Server General Information 1 2 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf TMS 34020 Graphics Processor The TMS 34020 is a CMOS 32 bit processor with hardware support for graphics operations such as PIXBLT and curve drawing algorithms Included is a complete set of general purpose instructions with addressing modes tuned to high level languages In addition to addressing a 512 MB external memory range the 34020 contains 30 general purpose 32 bit registers stack pointer and a 512 byte LRU instruction cache On chip functions include 64 programmable registers used for CRT timing I O control and instruction parameters The 34020 can rec
67. 017FF FFFF 4 MB Config 3F0 0000 abcd 0000 FCOO FF80 0000 0180 0000 Top 1 MB abcd 03FF FFFF FFFF FFEO 01FF FFFF all versions Primary Display Plane Eight Pages VCL V 8 I1Kx1Kx4 Overlay Display Plane Eight Pages 34020 System Memory Bottom 1 MB 4 MB Config 0000 0000 007F FFFF 5 27 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 5 12 VCL M Local Memory Map PCI LAR 34020 34020 address zero based Window addresses X offset D offset for system RAM 0000 007E C000 0000 34020 Internal C000 03E0 Registers 100000 0003 03BF 400 C080 0000 Device Buffer C080 ODEO color map DUARTSs PC Keyboard Mouse General Purpose Control Register 800000 0000 03FF 2000 C400 0000 Flash EEPROM 2FFF CSFF FFEO I1Kx1Kx8 Primary Display Plane 100 0000 0000 03FF 4000 C800 0000 5FFF CBFF FFEO Eight Pages 180 0000 0000 03FF 6000 CC00 0000 IKx 1K x4 7FFF CFFF FFEO Overlay Display Plane Eight Pages 3C0 0000 0000 03FF F000 FE00 0000 0000 0000 34020 System Memory F3FF FE7F FFEO 007F FFFF Bottom 1 MB 4 MB Config 3D0 0000 0000 03FF F400 FE80 0000 0080 0000 Low mid 1 MB F7FF FEFF FFEO 0OFF FFFF 4 MB Config 3E0 0000 0000 03FF F800 FF00 0000 0100 0000 High mid 1 MB FBFF FF7F
68. 1 0 FF xx xx xx overlay palette entry FF 1 XX XX XX XX cursor palette entry 1 2 XX XX XX Xx cursor palette entry 2 3 XX XX XX XX cursor palette entry 3 5 51 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Figure 5 2 RGBS61 VCL x 8 Display Memory Bit Assignments RGBS561 VCL x 8 Pseudo Color RAMDAC PLL pixel clock 3 color bit mapped cursor On board VRAM WTO pixel 0 3 bank select WTI1 7 pixel 0 3 unused display data bits overlay 24 3 1 Overlay Pixel 3 16 23 Overlay Pixel 2 8 15 Overlay Pixel 1 Video Outputs 0 7 Overlay Pixel 0 primary DODRZ gt Digital 24 3 1 Primary Pixel 3 16 23 Primary Pixel2 B gt Blue 8 15 Primary Pixell G gt Green 0 7 Primary PixelO Rf gt Red RGBS561 latches 4 pixels at a time Table 5 21 RGB561 VCL x 8 Color Map Input Conversion Graphics Primary Cursor Overlay Screen Value Input Input Color Value 0 0 00 primary palette entry 0 0 0 FF primary palette entry FF 0 1 XX overlay palette entry 1 0 FF XX overlay palette entry FF 1 XX XX cursor palette entry 1 2 XX XX cursor palette entry 2 3 XX XX cursor palette entry 3 On board Devices and Memories 5 52 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 5 6 1 RGB561 DAC FIFO Introduction
69. 1 Interrupt Grant Level 2 6 Interrupt Priority Jumpers 2 7 interrupt settings 2 6 2 12 interrupt vector 4 5 interrupt vector address 2 6 2 12 Interrupt Vector Address Register 5 8 Interrupt Vector Register 5 8 interrupts 4 5 5 4 5 64 Jumper Locations for the VCL M 2 15 Jumper Locations for the VCL V 2 10 LAR 4 2 5 13 LAR Bit Definitions 5 13 LAR 34020 Starting Address Table 5 24 Line Buffer 5 7 little endian 5 20 LK401 Connector Pinout 2 28 LK401 Port 2 27 LK401 Serial Keyboard Port 1 2 29 LQ10D011 2 50 LQ10D021 2 50 LQ10DH11 2 50 LQ10DH15 2 50 Maintenance 6 10 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf master clock 4 9 MEMON 5 4 midline reload 5 40 mini DIN 2 31 2 32 miscellaneous routines 3 7 Monitor Requirements 1 17 monitors 5 wire 2 8 2 13 Motorola MVME147S 6 3 Motorola MVME167 6 3 Motorola MVME187 188 197 6 3 Mouse Port 2 27 NEC NL10276AC20 01 Connections 2 46 NEC NL12810AC20 04 Connections 2 47 off screen pixmaps 3 8 overlay 5 48 page fault 5 23 pan 5 40 Panel Side Connector Summary 2 52 PC Keyboard Controller 5 62 PCI 0 1 PCI bus Side Device Buffer 5 16 Peritek Mouse 2 27 2 32 Peritek Software and Operating Systems Support 3 2 pipelining 3 3 pixel routines 3 8 PMC 0 1 PMC bus installation 2 11 Port 0 2 27 2 29 Port 1 2 27 2 29 Port 2 2 26 2 29 Port 3 2 29
70. 2 areas If you are not using a 167 see Chapter for other CPU board addresses The graphics board responds to A16 and A32 bus masters but not A24 unless specially enabled The standard addresses for the graphics board are MVME167 Physical Address Address Type Data Type Control Registers FFFFCO00 FFFFCOOF A16 D16 D32 Line Buffer FFFF8000 FFFF83FF A16 A24 D8 D16 D32 Full Memory 4A0000000 A3FFFFFF A32 D8 D16 D32 optional set by control bit in CSR The MVME167 debugger can be used to determine whether there are address conflicts Except for the graphics board CSR base address itself all address areas are software programmable If you want to use the console debugger to examine the physical address areas that the board will occupy do not allow the computer to boot Using the following procedure Troubleshooting 6 5 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Note This procedure requires that the graphics board is not plugged in enter MM FFFFCOOO L lt CR gt examines one CSR location enter MM FFFF8000 L lt CR gt examines the line buffer base address You will get an Exception Access Fault Local Off Board if there is no device already installed which uses the board s addresses This is what should happen for both of these attempted memory examine operations Note Now install the board following the procedure in Section 2 3 Powe
71. 4 pixels for each LAR value Same characteristics as Primary graphics RAM 5 13 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 5 6 LAR Bit Definitions continued Video RAM VCL 24 LAR Memory Selected 4000 7FFF Graphics RAM bits 0 23 are primary RBG true color memory bits 24 29 are overlay and window type table bits 30 31 are r w but not used 256 pixels for each LAR value 1K x 1K pixels is 4 MB or 4096 LARs Memory is byte addressable and writemask applies System RAM 1K bytes for each LAR value Used for the 34020 program store Memory is not displayable Byte addressable 1 MB of memory is 1024 LARs Memory capacity is expandable to 32 MB See Section 5 3 4 for information on 34020 memory access Memory Installed LAR ranges 4 MB FO00 FFFF 8 MB E000 FFFF 16 MB C000 FFFF 32 MB 8000 FFFF 5 4 1 Device Register Access The board devices and memory are accessed through the 1 KB line buffer in the A16 A24 space The 34020 registers are available when LAR 0 See Section 5 3 7 for 34020 side addressing of devices and memory The color map General Purpose Control Register PC Keyboard controller HSP interface and 2681 DUARTs are accessible when LAR 400 Although most of the devices are just 8 bits they are placed on long word 4 byte boundaries which simplifies addressing by the 34020 which controls th
72. 4677 Old Ironsides Dr 800 366 9782 Suite 450 FastFacts 800 366 0476 Santa Clara CA 95054 Sharp 5700 NW Pacific Rim Blvd 206 834 2500 206 834 8903 Suite 2 Camas WA 98607 Installing Your Rastergraf Display Board 2 54 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 10 High Speed Data Port VCL V Only The output buffers on the User Equipment UE will be 74ACT374 FCT BCT and ABT are OK with 64 mA output drivers terminated with 220 330 resistors on the UE Input signals from the graphics board to the UE will be conditioned by a hysteresis device such as a 74F 14 See Section 5 9 for HSP signal functions Table 2 35 HSP VMEbus P2 Connector Pin Connections Signal Name Pin Polarity Direction UE Type Board Type DATA 00 Al active high VCL input 74ACT374 74ACT652 DATA 01 C1 active high VCL input 74ACT374 74ACT652 DATA_02 A2 active high VCL input 74ACT374 74ACT652 DATA_03 C2 active high VCL input T4ACT374 T4ACT652 DATA_04 A3 active high VCL input T4ACT374 T4ACT652 DATA_05 C3 active high VCL input T4ACT374 T4ACT652 DATA_06 A4 active high VCL input T4ACT374 T4ACT652 DATA _07 C4 active high VCL input T4ACT374 T4ACT652 DATA_08 AS active high VCL input T4ACT374 TAACT652 DATA_09 C5 active high VCL input T4ACT374 T4ACT652 DATA_10 A6 active high VCL input 74ACT374 74ACT652 DATA 11 C6 active high VCL input 74ACT374 74ACT652 DATA 12 A7 active high VCL inp
73. 7 5 60 DUART Control Bits used by HSP 5 63 EEPROM 1 9 EL gray scale panel 2 51 EPROM 4 11 Example Intialization Table 1280 x 1024 5 33 extended addressing 5 6 external sync 4 9 External sync 2 40 FIFO Control Register FCRO Bit Assignments 5 57 FIFO Control Register FCR1 Bit Assignments 5 58 FIFO Control Register FCR2 Bit Assignments 5 58 Flash EEPROM 5 65 flat panel display 2 50 2 51 Flat Panel Supplier Summary 2 53 floating point FPU 1 3 5 18 fonts management routines 3 6 Force CPU 30 and CPU 40 6 3 Force Overlay Jumper 2 18 Force SPARC CPU s 6 3 functional description 1 2 fuse 1 11 6 7 Fuse 2 24 2 31 General Purpose Register 5 43 General Specifications 1 9 Genlock 2 40 GMS V36 and V46 6 3 graphics attributes routines 3 6 cursor routines 3 6 fill routines 3 6 frame routines 3 7 line drawing routines 3 7 memory routines 3 7 patterned line drawing routines 3 7 graphics board console port 2 14 Graphics Subroutine Package Library Routines 3 6 High Speed Data Port HSP 2 55 5 62 High Speed Digital Input Port routines 3 7 horizontal zoom 5 39 host only routines 3 7 HSP VMEbus P2 Connector Pin Connections 2 55 T O window 5 14 initial testing 2 2 initialization routines 3 7 Initialization Table Selection Options 2 20 initialization tables 5 31 5 wire VGA monitors 2 8 2 13 Installation 2 3 installation into a Motorola MVME167 computer 6 5 interlaced display 5 4
74. A zoomed display is achieved by re initializing the board with a different table Vertical Zoom Except when the static display function is selected see Section 5 4 3 the primary and overlay graphics screens are zoomed together vertically through bits 0 4 of 34020 register DINCL This is a binary zoom factors 1 2 4 8 16 32 Due to a bug in the 34020 vertical zoom does not work properly in interlaced displays Horizontal Zoom Because the VCL uses a programmable Phase Locked Loop PLL pixel clock horizontal zoom is accomplished by loading a new master pixel clock into the the PLL and reprogramming the 34020 horizontal display parameters Ordinarily the PLL is located in the RGB561 However when genlock is used the ICS1562 an external chip is used The 1562 is programmed through the General Purpose Control Register 5 6 3 Static Display The VCL series boards have a special circuit which allows the primary and overlay graphics screens to have different starting addresses Depending on bits set in the GPCR see Section 5 5 either the overlay or the primary remains at a fixed position essentially DPYST 0 while the other display s starting address is changed see Section 5 4 4 This is useful for waterfall displays which require a significant amount of stationary status information some of which may occasionally be updated as well as an image or stripchart which is constantly moving Hardware controlled screen positioni
75. A0 m 37 C080 xC0 m 3B C080 xEO0 m 3F E00 1C2 Miscellaneous control bits D16 or D32 access C080 5 29 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 5 14 34020 and PCI bus Register Offsets WCLLAR 400 PCI bus Byte TMS34020 Offset from Address DBR Base high low Address VCL M Color map Cursor PLL Pixel Clock Address Register low byte C080 0 0 Address Register high byte C080 20 4 Data Buffer for control cursor overlay C080 40 8 Data Buffer for primary color palette C080 60 C VCL M Keyboard Mouse Controller Data Buffer C080 100 20 Control Status Register C080 120 24 VCL M Serial Port Controllers Mode Registers 1A and 2A C080 w00 m 00 Status Clock Register A C080 w20 m 04 Command Register A C080 w40 m 08 Receive Transmit A Buffers C080 w60 m 0C Input Port Auxiliary Control C080 w80 m 10 Interrupt Status Mask Registers C080 wA0 m 14 Counter Timer Upper Registers C080 wC0d m 18 Counter Timer Lower Registers C080 wEO m 1C Mode Registers 1B and 2B C080 x00 m 20 Status Clock Register B C080 x20 m 24 Command Register B C080 x40 m 28 Receive Transmit B Buffers C080 x60 m 2C Reserved C080 x80 m 30 Not used C080 xA0 m 34 Stop Counter C080 xC0 m 38 Start Counter C080 xE0 m 3C For QUART m 100 w 8 x 9 for ports 0 and 1 and m 140 w A x B for ports 2 and 3 VCL M General Purpose Control Register Misc
76. FFEO 017FF FFFF 4 MB Config 99 3F0 0000 0000 03FF FC00 FF80 0000 0180 0000 Top 1 MB FFFF FFFF FFEO 01FF FFFF all versions On board Devices and Memories 5 28 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 5 13 34020 and VMEbus Register Offsets WCLLAR 400 VCL V Color map Cursor PLL Pixel Clock Address Register low byte Address Register high byte Data Buffer for control cursor overlay Data Buffer for primary color palette VCL V Keyboard Mouse Controller Data Buffer Control Status Register VCL V serial port controllers Mode Registers 1A and 2A Status Clock Register A Command Register A Receive Transmit A Buffers Input Port Auxiliary Control Interrupt Status Mask Registers Counter Timer Upper Registers Counter Timer Lower Registers Mode Registers 1B and 2B Status Clock Register B Command Register B Receive Transmit B Buffers Reserved Not used Stop Counter Start Counter For DUART A m 100 w 8 x 9 For DUART B m 140 w A x B VCL V General Purpose Control Register VMEbus Byte TMS34020 Offset from Address DBR Base high low Address C080 0 3 C080 20 7 C080 40 B C080 60 F C080 100 23 C080 120 27 C080 w00 m 03 C080 w20 m 07 C080 w40 m 0B C080 w60 m 0F C080 w80 m 13 C080 wAO m 17 C080 wCO0 m 1B C080 wEO m 1F C080 x00 m 23 C080 x20 m 27 C080 x40 m 2B C080 x60 m 2F C080 x80 m 33 C080 x
77. Fig r 4 1 VCL V Blo k Dilaga assis csaavovscvantinurasnvsnrasiantevneranmeccsuwlinuanvereaumminaatinans 4 16 Fig r 4 2 VCL M Block Diagrat secetei ieni e A 4 18 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com rtisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Introduction This introductory chapter contains information about the organization of this manual how to get technical support and the typographical conventions used throughout the manual The Organization of This Manual This manual provides information about how to configure install and program the Rastergraf 34020 based graphics controllers Products covered include the VCL series of 8 bit and 24 bit graphics controllers for VME and PMC PCI Mezzanine Card bus compatible computers The boards can be covered in one manual because their feature set is largely the same and as a result the software is nearly identical This manual is broken down into six chapters Chapter 1 Overview of the Rastergraf display boards Chapter 2 Installing Rastergraf display boards Chapter 3 Summary of Rastergraf s Software Products Chapter 4 Theory of Operation Chapter 5 Programming On board Devices and Memories Chapter 6 Troubleshooting Chapter 1 provides interesting background material about Rastergraf display boards Understanding the information in the chapter ho
78. For detailed information concerning operation of the PCI bus please refer to the Section I 3 Additional References PCT bus Interface A PLX9060 PCI to local bus bridge is used to make the interface between the 34020 controlled logic of the VCL M and the PMC acutally a PCI bus In addition to providing the actual 32 bit data path between the VCL and the PCI bus the PLX9060 does the PCI local address mapping and decoding It has on chip FIFOs for buffering data and two DMA controllers which can transfer data between the on board memory and other PCI bus resources The functions of the PLX9060 are documented in the data sheet Section 5 3 also has VCL specific information regarding the use of the 9060 The functions of the PLX9060 are supplemented by a MACH231 PLD which supports control signals for the PLX9060 address decoders for the VCL s local Control Status Register CSR and Line Address Register LAR and PLX9060 34020 arbitrator The VCL M uses the PLX9060 PCI interface chip to provide the PCI interface to the graphics controller This chip is PCI 2 1 compliant PCI signals connect to the PLX9060 only The placement and routing is PCI 2 1 compliant The PLX9060 connects the PCI bus to the TI34020 local bus via support logic supplied by an AMD MACH231SP The standard board provides a 16 bit LAR for maximum software compatibility with previous software An additional MACH211SP standard on CGS boards is required to support a 19 bit LA
79. GA3 Green Pixel A bit 3 17 17 GA2 GA2 Green Pixel A bit 2 19 52 GA1 GA1 Green Pixel A bit 1 21 19 GAO GAO Green Pixel A bit 0 23 54 RB3 RB3 Red Pixel B bit 3 49 21 RB2 RB2 Red Pixel B bit 2 51 56 RBI RBI Red Pixel B bit 1 53 23 RBO RBO Red Pixel B bit 0 55 58 RA3 RA3 Red Pixel A bit 3 25 25 RA2 RA2 Red Pixel A bit 2 2 60 RAI RAI Red Pixel A bit 1 29 27 RAO RAO Red Pixel A bit 0 31 3 Hsync Hsync Horizontal Sync 61 36 Vsync Vsync Vertical Sync 57 1 CLK CLK Pixel Clock 7 33 VCC DE Blanking Enable 59 29 CBLANK DESEL Composite Blank 58 67 5 V POWC Panel Enable 6 2 28 even GND GND Signal Ground 8 62 even 35 61 odd GND GND Signal Ground 35 61 odd VCL Signal NL10276AC20 01 NL10276AC20 01 Pin Name Name Description Pin CN1 33 34 67 5 V VCC sequenced 5 4 31 64 66 12 V VDD1 sequenced 12 5 connect to supply VDD2 backlight 12 1 2 3 connect to supply GNDB backlight Ground 63 64 65 no connect BRTH BRTL connect pins via 1K pot 67 to 68 62 GND BRTC backlight enable 66 Installing Your Rastergraf Display Board 2 46 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 2 28 VCL Analog Video Signal Pin Name 1 Red 2 Green 3 Blue 6 Ground 7 Ground 8 Ground 9 Ground 10 Ground 13 HSYNCOUT 14 VSYNCOUT 5 Ground VCL Analog Video Signal Pin Name no connect VCL Analog Video Signal Pin Name 4 SSV 15 S12V connect to supply via relay connect to su
80. If there has been physical damage file a claim with the carrier at once and contact Rastergraf for information regarding repair or replacement Do not attempt to use damaged equipment Caution Be careful not to remove the board from its antistatic bag until you are ready to install it It is preferable to wear a grounded wrist strap whenever handling computer boards Some operating systems require that you reboot your system after installing a device driver because only after the reboot will your system utilize the driver and recognize the board If yours is such an operating system you might like to install PX Windows or the Subroutine Package before installing the board since you will have to shut down the computer to install the board anyway If you want to install the software before shutting down the computer proceed to the correct part of the relevant software manual and return to this chapter afterwards Recommendation The following sections tell how to install the VCL board and how to change jumpers In order to avoid unintended side effects it is best not to change any jumpers except critical address jumpers until you are sure the board works in your system Installing Your Rastergraf Display Board 2 2 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 3 VCL V Installation The VCL V is designed to plug into any standard VME or VME64 backpl
81. ODH15 LQ10D021 Pin Signal Name Signal Name Pin Pin Pin Pin 56 RAI R5 3 4 4 CN1 5 21 RA2 R6 4 3 3 CN1 6 54 RA3 R7 5 6 6 CN1 7 48 GA1 G5 7 8 8 CN1 9 13 GA2 G6 8 7 7 CN1 10 46 GA3 G7 9 10 10 CN1 11 40 BA1 B5 11 12 12 CN1 13 5 BA2 B6 12 11 11 CN1 14 38 BA3 B7 13 14 14 CN1 15 29 Blank n a s 22 CN2 5 3 Agyne n a 15 16 16 CN1 3 36 Vsyne n a 17 18 18 CN1 4 1 CLK n a 1 2 2 CN1 1 55 Ground n a 6 5 5 2 22 Ground n a 6 5 5 2 53 Ground n a 6 5 5 2 47 Ground n a 10 9 9 8 14 Ground n a 10 9 9 8 45 Ground n a 10 9 9 8 39 Ground n a 14 13 13 12 6 Ground n a 14 13 13 12 37 Ground n a 14 13 13 12 28 Ground n a 15 15 2 4 Ground n a 16 15 15 8 37 Ground n a 16 15 15 8 2 Ground n a 2 1 1 2 33 34 67 5 n a 18 17 17 CN2 1 2 31 64 66 12 n a 20 19 19 30 32 65 Ground n a 19 20 20 CN2 3 4 Lighting n a Backlit Backlit Backlit Edgelit Installing Your Rastergraf Display Board 2 50 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 2 32 Sharp EL Panel Model LJ64ZU48 9 VCL VCL Standard Sharp Sharp Pin Signal Name Pin Name Pin Name Signal Name 15 GBO 24 B2 D10 16 GND 14 B7 GND 48 GB1 23 A2 D11 47 GND 14 B7 GND 13 GB2 22 B3 D12 14 GND 14 B7 GND 46 GB3 21 A3 D13 45 GND 14 B7 GND 19 GAO 20 B4 D00 20 GND 14 B7 GND 52 GA1 19 A4 D01 51 GND 10 B9 GND 17 GA2 18 B5 D02 18 GND 10 B9 GND 50 GA3 17 AS D03 49 GND 10 B9 GND 3 Asyne 11 A8 HSYNC 4 GND
82. Oils from your hand can break down the metal used in the circuit board 5 After making sure the board is seated correctly tighten the screwlock on each end of the board 6 Close the computer and plug the video cable into the monitor and the graphics board Make sure to plug the three BNC cables colored red green and blue into the monitor s corresponding red green and blue inputs Also make sure the 75 ohm switch on the monitor is turned on VGA monitors which use a 5 wire cable which can be obtained on special order may also require modified initialization tables Installing Your Rastergraf Display Board 2 8 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 3 5 Connecting the Mouse Keyboard and Console If you are not using a keyboard or other I O device just skip on to Section 2 6 Checking your Display PS 2 Mouse and Keyboard Ports Plug a PS 2 compatible mouse cable into the PS 2 connector round 6 pin DIN socket labeled PS 2 MOUSE Plug a PC AT compatible keyboard with a PS 2 style connector or adapter into the round DIN 6 pin socket labeled PC KBD RS 232 Serial Ports Plug an RS 232 serial mouse cable into the 9 pin DB 9 male connector labeled MOUSE You can also use a trackball in this port If you are using the PTERM terminal emulator plug the console cable from the computer into the 9 pin female connector labeled CONSOLE PTERM s
83. PCI address space Note that Rastergraf software supports only the 1 KB address mode The 9060 supports interrupts between the PCI bus and the 34020 and also allows the local DMA controller to interrupt the PCI bus when a transfer is complete PLX 9060 DMA Controllers The VCL M can autonomously transfer data between VCL memory and some other PMC device by using the PLX9060 s two DMA controllers Each controller can chain load which means that once started the DMA engine can load its parameters from local 34020 memory run the data transfer then load up another set of parameters etc In this way the DMA can implement a scatter gather mapping such that data can be transferred between virutally contiguous physically discontiguous CPU memory blocks and VCL memory 4 4 34020 Functional Unit The 34020 section is the same for all VCLs and can be considered as a unit unto itself Although differing in some internal details such as amount of memory and I O devices this section operates the same on all boards as far as the host bus interface is concerned 4 7 Theory of Operation Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf It includes display and 34020 system memory writemask register color maps which one is installed depends on configuration two DUARTs VCL V or one QUART VCL M serial I O 8242PC keyboard controller and local memory and device deco
84. Port 3 2 26 programmable logic devices PLDs 4 11 PS 2 2 31 2 32 PS 2 Keyboard Port 2 33 PS 2 Mouse Port 2 33 ps2 mouse routines 3 8 PTC 1 11 2 24 2 31 PTERM Serial Control Options 2 19 QUART 1 7 5 60 RAMDAC 5 46 Register Summary 5 57 Request for Timing Table 5 38 Return Policy 6 10 REVFLAG 5 4 RGB561 5 46 RGB561 VCL 24 Color Map Input Conversion 5 51 RGB561 VCL 24 Display Memory Bit Assignments 5 51 RGB561 VCL 8 Color Map Input Conversion 5 52 RGB561 VCL 8 Display Memory Bit Assignments 5 52 RGB561 registers 5 50 RS 232 see DUART and QUART 1 7 scroll 5 40 Secondary Pointer Port 3 2 29 Serial EEPROM 5 66 serial I O routines 3 8 Serial Mouse Port 0 2 29 Serial Mouse Connector 2 27 Service 6 11 SGI Iris 4D 6 3 Sharp 640 x 480 Panels 2 50 Sharp EL Panel Model LJ64ZU48 9 2 51 Sharp LQ10DX01 Connections 2 48 SharpLQ12D011 Connections 2 49 SIMM 4 11 smooth scroll 5 41 Software Development Flow 3 10 static display 1 4 Static Display 5 39 static overlay 5 39 static primary 5 39 Summary of Initialization Tables 5 32 system arbitrator 4 2 system memory 4 11 5 14 5 19 Table 5 4 XAR Address Match Register 5 6 technical support 1 2 text attribute routines 3 8 output routines 3 8 TFT LCD color panel 2 50 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Themis SPARC CPU s 6 3 Twea
85. R Line Address Register The PLX9060 has decodes for PCI Configuration Registers Runtime Registers Local Address Space and Expansion ROM The VCL M does not need to use the Expansion ROM decode Except for the PCI Configuration Registers which have a fixed size and address each decode Theory of Operation 4 6 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf has a Base Address Register BAR associated with it The PLX9060 also has DMA Registers which are only accessable via Local Address Space Control Registers Unlike the VCL V the CSR functions are assumed by the PLX9060 The 9060 provides the VCL CSR functions 34020 reset line buffer response enable and interrupt enable Refer to Chapter 5 and the PLX9060 data book for more details about the 9060 The LAR selects which 1 KB section of memory or block of device registers is accessed through the line buffer The line buffer mechanism is used instead of direct addressing because the internal memory capacity of the VCL is in excess of 48 MB Since only KB of address space is required to access any of the VCL devices this design has been applied successfully across many bus interfaces While the added overhead to chop up transfers into 1KB increments is not significant for a CPU controller it is sometimes inconvenient for DMA controllers Therefore the VCL can also respond to a linear 64 MB section of
86. R2 Bit Assignment cecssceeseeeeeseeeneeeneees 5 58 DUART Control Bit Usage for HSP cece eccccessecetecesecseeeeescecseeeneeeees 5 63 VMEbus Interrupt Functions sseicsssssccestinontctnsctatussotiaeapesiasces avndataaineesioteaus 5 64 34020 Interr pt F NCH ODS osc sessasmuvsnessarswecanioldeseasamesesmemionswestesseseagoreouanees 5 64 Common CPU board addresses s sicciassseccvissssscasssstcxincnsdansess asectaaseaniasassreciagesanne 6 3 Curing General System F AUG isacscracccescvosanssasasinnsaionsennsuasesncteulansaientenntuasisncade 6 8 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Figures Figure 2 1 CSR Address and Interrupt Grant Level Jumpers ccccecceeseeeeeeeteeeeees 2 5 Figure 2 2 Interrupt Priority Jumpers 0 ccccecceeceeseeesceceseceeceeeeeeseecseceeeeseeeeeseeeeaeees 2 7 Figure 2 3 Jumper Locations for the VCL V saccdnnnasniiasnaunundnmadancwn 2 10 Figure 2 4 Jumper Locations for the VCL M ecceesescceseceecneeeseeeeeeeeeeseceaeceeeneeeneees 2 15 Figure 2 5 VCL V DRAM and VRAM Size Jumpers cescseceseeseeceeeceeeencesneees 2 16 Figure 2 6 VCL V PTERM Configuration Jumpers JP401 eecceesseceseceeteceeeeeeeee 2 19 Figure 2 7 VCL M PTERM Configuration Jumpers JP301 ccceeceesceesteeeteceteeeeees 2 19 Figure 3 1 Software Development FIOW c sessssssessarssosssnssssersessavssnesnssonsonsonss 3 10
87. RGB561 and the VRAM and 34020 shift load clocks The IBM PLL is used except for genlock or slow clock pixel clock lt 16 MHz applications where a separate ICS1562 must be used On each loadclock pulse the RGB561 latches four pixels of primary screen data plus four pixels for overlay The data is synchronized internally through another register and then fed pixel by pixel through the chip Additional mode control bits window type are also latched at each pixel time but they are normally not used on the VCL They are only used in a bankswitch mode for blink or when the 2 or 4 MB of on board VRAM are used normally VRAM is contained on a separate daughterboard Digital Output The RGB561 provides a 24 bit digital output function by sending 12 bits at a time through a multifunction port The high 4 bits of each color are put out at the rising edge of the digital data clock and the low 4 bits are valid at the falling edge 8 bits of the multifunction port double as the microprocessor data interface the other 4 bits are only for digital output The result of this is that if the digital port function is being used the RGBS561 can only be programmed during blanking Otherwise the image on the flat panel will be disrupted and the IBM registers will be clobbered RGBS561 Programming The RGB561 internal register set and LUTs are accessed via a four single byte register data buffer group programmed through the device buffer VCLLAR 400 Ea
88. S 0 cccccecesssscecsessececssececeeaececsesaececsaeeceesueeecsesaeesceaeeecsesaeeecseseesessueeeeseaaes 6 9 6 6 MAINTENANCE WARRANTY AND SERVICE cssssccecececsesssececececsesscneceeececeesesssseeeeeesesesssaeeeeecessensaaees 6 10 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 1 1 Table 1 2 Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 2 6 Table 2 7 Table 2 8 Table 2 9 Table 2 10 Table 2 11 Table 2 12 Table 2 13 Table 2 14 Table 2 15 Table 2 16 Table 2 17 Table 2 18 Table 2 19 Table 2 20 Table 2 21 Table 2 22 Table 2 23 Table 2 23 Table 2 24 Table 2 26 Table 2 26 Table 2 27 Table 2 28 Table 2 29 Table 2 30 Table 2 31 Table 2 32 Table 2 33 Table 2 34 Tables Common VCL V Configurations cccccecccesceeeseeeseeceeceeeeeeseesseecsseeneeeees 1 18 Common VCL M Configurations 5 oseiacessnidenseitndescsaatecxastentcotincaseenierceuries 1 18 VMEbus graphics board addresses cccccesccesceesceesceeeeceeeeeseeeeeecsseensaeenes 2 4 CPU board addi sseS arsericrerricnieno neire n E E T aia 2 4 Interr pt Grant Level cssciadccaucsadisacnsexsasesssaveedsedsvaceneaiaadonnainiunss EAE TREE EERE 2 6 VCL V DRAM and VRAM Size Jumpers oo sisscccsssassssscssestorsuistosssaaunsessanoes 2 16 PTERM Serial Control Options ccsccssscsssscssstscssscssccsscsssecsseecseecesscees 2 19 Default Initialization T
89. S Port 2 or 7 RX Data from Secondary Pointer Port 3 4 RX Data from Console Port 2 3 9 Console RTS Port 2 or 8 TX Data to Secondary Pointer Port 3 11 TX Data to Console Port 2 2 Mouse DB9 Pin Number 5 7 Ground 5 6 RX Data from LK401 Serial Keyboard 6 Port 1 8 RX Data from Serial Mouse Port 0 2 10 12 Volts via 220 ohm resistor 4 7 13 TX Data to LK401 Serial Keyboard 8 Port 1 15 12 Volts via 470 ohm resistor or 3 TX Data to Serial Mouse Port 0 Installing Your Rastergraf Display Board 2 30 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 8 PS 2 Connections In this manual PS 2 and PC compatible are used synonomously PS 2 denotes the smaller 6 pin mini DIN connector which was first used on the PS 2 computers and now in wide use because it is half the size of the original PC 5 pin DIN connector The electrical and software protocols are identical Rastergraf can supply cables and devices please contact the factory for ordering information All VCLs support two PS 2 ports and include 5 power The power lines are protected by auto resetting fuses These are PTC elements which reset automatically when an overload is removed PS 2 devices are especially suited for desktop applications because they use TTL levels which cannot support cable lengths over 10 feet Third party active cable extenders are available to overcome this limi
90. T 2 9 2 Digital Video Mini D ribbon 2 35 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 9 1 Analog Video Connector VCL M The video connector for the VCL M is a 9 pin MDSM micro D sub An adapter cable is required to make the transition from the 9 pin MDSM to a standard VGA connector You can get a 3 foot pigtail from ITT Cannon which has the MDSM connector and a shielded twisted pair cable already made up All you have to do is wire the other end The part number is CA111972 22 The R G and B video outputs are driven by the RAMDAC which is capable of driving terminated cable 75 ohms to standard RS 330 IRE levels Cable length should be limited to 50 feet unless you use low loss RG 59 You must use the correct initialization table since a VGA monitor depends on the sync polarities to determine operating frequency If you use the Rastergraf VGA 3 20 VGA to BNC cable only composite signals are carried to the monitor and it will autoscan if the monitor is so equipped Note that the VCL M does not support Genlock Note due to a layout error the pin which is marked on the PCB with a square indicating pin 1 is on the wrong pin It is actually on pin 5 The pin list below shows the correct ITT Cannon pin numbers Just ignore the pin 1 square on the PCB Table 2 21 VCL M Video Connector Pinout MDSM Pin Numb
91. Table 5 15 Table 5 16 Table 5 17 Table 5 18 Table 5 19 Table 5 20 Table 5 21 Table 5 22 Table 5 23 Table 5 24 Table 5 25 Table 5 26 Table 5 27 Table 5 28 Table 6 1 Table 6 2 HSP VMEbus P2 Connector Pin Connections cccceeceeseeseeesteeeeeeeees 2 55 Rastergraf Software and Operating Systems Support 0 ccccsseeseeseeees 3 2 Graphics Subroutine Package Library Routines cccceesceeeeeeseeeseeeeeeees 3 6 VCL V VMEbus side PLD Device Summary ccceeccesseceteceeeeeeeeeenees 4 13 VCL M PCI PMC side PLD Device Summary ccccesseeeseceseeeeeesees 4 13 VCL V and VCL M 34020 side PLD Device Summary cesceeeee 4 14 CSR Bit SUMMATY retiarii iE ERE EEEE A EAE R SARTE EER ENEA 5 4 CSR Bit TVG TUB GINS Jccx vac onacencs aseweksqevanerenesentnaceaneta nies car S Darieta Kina Nap EER EDERE Sia 5 5 XARADR Address Match Resistor sisie cissccinivaindesessihgansdetiecetnenccsvivadensations 5 6 DBRADR Address Match Register cccccesccesscesceeseeesseceseceeeeeeaeecsseceneenees 5 7 Interrupt Vector Address R COIS TE isasssvsenssncvuncnnasbosnsnocsisnaseeneenctemseapteleensiess 5 8 VCL M PLX9060 Serial EEPROM Listing cccceeseeceeeceseeeeeeeeeneeneeaee 5 12 LAR Bit De MMOS ssa ccaspiaeasichvnsaascuia titaria Eaa NE aE TEAS NORTE AEREE E EAEE 5 13 VCEL V Side Device Burren si sasisacsadssncccavssincasassauceasnsuceaassaeiasasanociassenctensssinn 5 15 VCL M PCI bus Side Device BOt
92. _transp install_patn nw_install_patn select_patn set color0 set_colorl get color0 get_colorl set_pensize set_pmask set_ppop transp_off transp_on Graphics Cursor Routines curctl curmoy cursor gcurs_reset Graphics Fill Routines bound fill fill convex fill_oval fill piearc fill polygon fill rect nw fill convex nw_patnfill convex patnfill convex patnfill_ oval patnfill piearc patnfill polygon patnfill rect seed_fill seed_patnfill Software Summary 3 6 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 3 2 Graphics Subroutine Package Library Routines continued Graphics Frame Routines frame_oval frame_rect patnframe_oval patnframe_rect Graphics Line Drawing Routines draw_line draw_ oval draw_ovalarc draw_piearc draw_point draw_ polyline draw_rect pen_line pen_ovalarc pen_piearc pen_point pen_polyline pr_draw_polygon_abs pr_draw_polygon_rel pr_draw_polyline_abs pr_draw_polyline_rel pr_pen_polygon_abs pr_pen_polygon_rel pr pen polyline abs pr pen polyline rel xy_draw_polygon_abs xy_draw_polygon rel xy_draw_polyline_abs xy_draw_polyline_rel xy_pen_polygon_abs xy_pen_polygon_ rel xy_pen_polyline_abs xy_pen_polyline rel Graphics Memory Routines pixmap select plmov plovl plpri pixmap_alloc pixmap free pixmap_ copy pixmap_xxxid pixmap info pixmap_read pixmap_write Graphics Patter
93. a sheets and application notes are available on the web page http www nationalsemi com You can also contact Rastergraf for information regarding panel compatibility and LVDS interfacing The LVDS output can be taken from a low profile two row twenty pin 2 x 10 050 header which is located near the front panel You may want to use 3M s Mini D Ribbon receptacle board side 10220 1210VE which is intended for LVDS applications Due to space limitations we didn t The cable connector is a 10320 series part 3M Tech Support is 800 225 5373 The LVDS protocol can support either 18 bit 6 bit RGB or 24 bit 8 bit RGB In the case of 18 bit LVDS Clock and Data Pairs 0 2 are used The 24 bit mode adds Data Pair 3 Unfortunately the standard LVDS TTL pin mapping provided for the 24 bit part CF581 won t work on an 18 bit panel Rastergraf has remapped the pinout so that there is compatibility LVDS requires that the length of all pairs must be closely matched If you look at the VCL M s LVDS header you will see that some of the traces have turns and twists in them to equalize the lengths Be sure to observe this equal length practice when you build cables or adapters for LVDS Table 2 23 VCL M LVDS Digital Video Connector J206 VCL M Pin Signal Name Description 3 03 LVDS Data Pair 0 4 02 LVDS Data Pair 0 7 01 LVDS Data Pair 1 8 00 LVDS Data Pair 1 11 15 LVDS Data Pair 2 12 14 LVDS Data Pair 2 19 13 LVDS Data Pair 3 20 12 LVDS D
94. able Selection Options ssssssesssessesesssseseesersssesee 2 20 Initialization Table Selection Options sccssisccsccasscsnsseesacnssineecsauseteasssnsianssender 2 21 Console Connector PI Out cxzcccsscnscacscessceessansvecenseasdsesnsavanenssioeenaeansdanunpeanvnands 2 26 Jumpers for Console Port Port 2 and Port 3 VCL V eceecceeseeereeeteees 2 26 Jumpers for Console Port Port 2 and Port 3 VCL M 00 ee eeeeeeeeeeees 2 26 Serial Mouse Connector PINOU icscnecesminanueanaionndacmnad aac 2 27 Mouse Port Port 0 and Port 1 VCL V ccccccceceseceseeeesseecssseeesseeeenaes 2 28 Mouse Port Port 0 and Port 1 VCL M ou cccccceescceesceeesscecssseecsteeeesaes 2 28 LK401 Connector Pim Qt sepicis risenti a ie K Ea EELEE 2 28 VCL M Serial Connector Pinout sssssseeseeeseseeseesseesseseresressessresresseeseese 2 29 MSE Cable Connections sisanra iie EE E E R E 2 30 PS 2 Mouse Connector Pino issctssssinecsavecsasdusseestavmnesientinasvastsceednmnusuentenes 2 32 PC Keyboard Connector Pinout sisssiiscctsssssscssssssccsasnttessasianccinsiivuesesssiccosansic 2 32 VCL M Serial Connector Pm outsccssicscsscndceaesethvnassansentunnsguaceventieensaaveneanents 2 33 MKM Cable Connections jcc ssicsicasideadieianinnnnaalierieaiiaanmoatis 2 34 VCL M Video Connector Pinout eccecceesceceseceeeeeeeeeeaeecneceeeeeeeenseees 2 36 EY Tale Connections iiaiccasniat ons snedaracuituassntnsemaianinexpsentiecassibnapaaonieasnnaes 2 37 VCL M LVDS D
95. aecnaseeesaeeaeeaeeaeeeeeneees 2 55 CHAPTER 3 SOFTWARE SUMMARY cccccscsssssscsrcrcccessssssscssscscscssssssssssseees J L Be INTRODUCTION cz sce sccorececaa aacecntvcccnis cate cacotes cute eceecasecovece coerce asauce converses E 3 1 3 2 SOFTWARE AVAILABILITY BY PLATFORM AND OG ccssessssecececeessaeceeececeesseaesecececeeseasaeeeeeeeessanaeees 3 2 3 3 WRITE POSTING sicce2sdavcecgurscscediceeedeneng onenen e aena a a a Sa Eea iN SaS E a NEESS EEEa e ISTENES Ey 3 3 3 4 PX WINDOWS SERVER csccccssssscecssscecesseececseseececsneeeesesaeeecseaeececuaeecsesaeeecsesaeessaeeeesesaeeecseseesesseeeesenaes 3 4 3 5 GRAPHICS SUBROUTINE PACKAGE cssssssecsssececescceeessaececsesaececeeeeceesaeeecseaaeesseeeecsesaececseseesesseeeseeaaes 3 5 3 6 SMARTP TERM sysscoccessavestacvescaeteedesaselaaeigueces odigcnevssadedevscaqeuestcagesasqaveosduedapaudegesgetie qeasscoedemanstedgegecenanaees 3 9 3 7 SOFTWARE DEVELOPMENT PACKAGE sccccsssssceessseecessaececseseeeeceuceecsssaeeecseaeeseeueeecsesaeeeceaaeeesseeeensgas 3 10 CHAPTER 4 THEORY OF OPERATION ccccccccscscscccscscscscscscscscscscsccescceseceees A L 4 1 INTRODUCTION essscdecoas lt tchbssdsatueeds eaea eea eNe En exag de geebaneees Eea EREE S EAE EESE ENEE E ETEEN ENES 4 1 4 2 VCL V SYSTEM DESIGN ccccsssccecssssecesssececssssececseseecseseeecessaeesceseeecsesueeecsesaeseceeseecsesaeeecseaaeesenseaeenses 4 2 4 3 VCL M SYSTEM DESIGN cccsessesceececsessssecece
96. af Display Board 2 26 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 7 2 Serial Mouse Connector and Jumper Options The Serial Mouse connector uses a male pin DB9 connector It actually supports two serial ports the Mouse Port which can also be used with a trackball or other pointing device and the LK401 Port which is used to support a serial keyboard If you buy the Mouse Trackball or Keyboard directly from Rastergraf it will come tested and prepared to work correctly with Rastergraf software Rastergraf can supply the Rastergraf Roller Mouse which uses a small rolling ball and mechanical position encoders A pad is not required but can make operation smoother The Rastergraf Trackball works like an upside down roller mouse with a large ball A compatible mouse or trackball should use the 5 byte Mouse Systems 3 button protocol A 2 button Microsoft Mouse protocol unit can be supported with a special command line option when starting the PX Windows server see the PX Windows User Manual Man Page section Most mice and trackballs rely on the current which can be sourced through the serial port s transmit RTS and CTS lines for power Since the VCL mouse port just has data leads only current limited 12 and 12 volts are supplied to these lines instead Note If you experience difficulty getting a device to work you may be drawing too much current
97. ality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 5 2 5 VECADR Interrupt Vector Address Register The interrupt vector address which the board supplies to the VMEbus during an interrupt acknowledge cycle is also programmable Now it should be pointed out that this is not literally the address to which the CPU will vector but a 1 of 256 index which is left shifted 2 bits by the CPU and then used as the vector address Bits 0 7 in this register correspond to vector addresses in the range 0 to 1020 Remember that VINTEN in CSR also has to be set before you will get an interrupt from the board Also some processors require that the low 2 bits of VECADR be 0 to vector correctly Bits 8 15 in VECADR read zero Sections 2 4 2 2 4 3 and 5 10 have more information on interrupts Table 5 5 Interrupt Vector Address Register VECADR Data Bit VMEbus Address Bit 0 0 NYDAUNBWNK NYDN BWNeR 5 2 6 VMEbus Block Transfers BLT The BLT data transfer supports D32 only BLT is supported for both A24 and A32 accesses A16 BLTs are not defined The 34020 itself generates the addresses so the HINC bit 12 in the TI HSTCTLH register must be set otherwise the same location is accessed repetitively This bit can be left on all the time If HINC is always on then non BLT reads will be faster if sequential possibly slower if random If HINC is always on then non BLT writes will be unaffected if HPFW HSTCTLH is clear
98. and 24 bit graphics controllers Additional sections contain a bibliography specifications monitor requirements and common configurations This is summary information and is not critical to the one who wishes to press on to the installation procedures which are contained in Chapter 2 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 1 2 Functional Description The Rastergraf VCL series boards are based on the TMS 34020 32 bit Graphics System Processor GSP The boards offer a high degree of on board intelligence and functionality as well as a straightforward frame buffer interface The boards are differentiated chiefly by the bits pixel of the primary display memory and by bus support For example the VCL V 8 has 8 bits pixel in the primary plane and the VCL V 24 has 24 bits Both versions have analog and digital outputs The VCL M PMC version is available only in 8 bit pixel only so its full model name is VCL M 8 The PX Windows and Graphics Subroutine Package software are bus independent enabling a user to easily switch between different bus versions of the VCL The feature set of the VCL includes 40 MHz 34020 Graphics Processor 34082 Floating Point Unit FPU option VCL V only RS 232 serial I O ports and 2 PC PS 2 compatible ports 4 Kb serial EEPROM plus up to 2 MB autoboot Flash PROM Up to 32 MB 34020 memory on a single SIMM Better than 160
99. anes The VCL V will work also correctly in a 5 row DIN VME64x systems as these connectors have the center 3 rows of connections in common with the the VME64 backplane The VCL V 24 and VCL V 8 share virtually all jumper configurations They use the identical PC board They differ only in their plug in parts such as FPGAs and the VRAM memory module The following instructions tell how to modify the VCL V FAB REV 2 and REV 3 to a non standard configuration Refer to Figure 2 3 Jumper Option Locations for VCL V at the end of this section for jumper locations For wire wrap changes only KYNAR or TEFLON not enamel or plastic coated insulated wire should be used 2 3 1 Checking Board Addresses Before installing the board in the backplane you must confirm that the addresses used by the Rastergraf display board are not used by other devices in your computer Since many boards are fully configured after the operating system boots up this may not be easy to do Refer to the Rastergraf PX Windows and Graphics Subroutine Package manuals for more installation information The Rastergraf VMEbus graphics boards have three address ranges e Control Registers Jumper programmable e Line Buffer Software Programmable e 64 MB Memory Window Software Programmable Note Only the multiprocessor version of the PX Windows server uses the 64 MB memory window Before installing the board into your backplane make sure no other devices in your comp
100. art by any person without prior approval of Rastergraf Inc Its sole purpose is to provide the user with adequately detailed documentation to effectively install and operate the equipment supplied The use of this document for any other purpose is specifically prohibited The information in this document is subject to change without notice The specifications of the VCL V and VCL M and other components described in this manual are subject to change without notice Although it regrets them Rastergraf Inc assumes no responsibility for any errors or omissions that may occur in this manual Rastergraf Inc assumes no responsibility for the use or reliability of software or hardware that is not supplied by Rastergraf or which has not been installed in accordance with this manual Trademarks mentioned in this manual are the property of their respective owners The VCL V and VCL M are manufactured and sold under license from Curtiss Wright Controls Embedded Computing Contact Rastergraf Inc for additional information Copyright 2006 by Rastergraf Inc Manual Revisions Introduction 3 Revision 1 0 October 17 1997 Master cloned from VCL V Manual Text altered and expanded to include the VCL P and the VCL M Revision 1 1 January 26 1998 Revisions and cleanup Revision 1 2 February 9 1998 More revisions and cleanup First full customer release Revision 2 0 October 21 2006 Delete the VCL P Convert from Peritek names to Ras
101. ask register It is buried inside the 74BCT16652 registered bus transceivers which pass data between the 34020 local data bus LAD and the 34020 common memory and device data bus MAD bus The 74BCT16652s hold the writemask data essentially acting as the VRAM writemask holding register and gate it onto the MAD bus at the beginning of every VRAM cycle Writing the 74BCT16652 writemask register is a bit of a trick When a program writes into the 34020 writemask register the 34020 executes a special cycle to update the VRAM writemask holding register A PLD detects this cycle and stores this data in the 74BCT16652s 5 5 3 VRAM Color Register and Block Fill Special Function There are a few instructions VBLT VFILL and VLCOL which can only be used with Video RAMs VRAMs which support so called VRAM special functions which include block write and color register support Rastergraf PX Windows software automatically detects and uses special functions if the board s VRAM can support them The Color Register is used in conjunction with the VRAM block fill mode which allows up to 4 adjacent locations in the VRAM to be written in one cycle In this way large areas with repetitive patterns can be written at a considerable higher rate that normal 5 5 4 Memory Types and Sizes The VCL V can have a maximum of 16 MB of 4 Mbit VRAM display memory contained on a field replaceable VMEM8 or VMEM24 daughterboard With the VCL V 8 X10 and VCL V X12 c
102. ata Pair 3 15 07 LVDS Clock Pair H 16 06 LVDS Clock Pair L 1 2 5 6 9 10 GND Ground 13 14 17 18 GND Ground Installing Your Rastergraf Display Board 2 38 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf The table shown below shows the mapping between the actual 90CF581 pins labeled TXINOO TXIN27 and Rastergraf s dual 4 bit pixel and single 8 bit pixel modes In addition the equivalent TXINs for a 6 bit part such as the 90CF561 are shown so that you can see that the low six bits of each 8 bit pixel mode set match correctly Table 2 23 Digital Output to LVDS Transmitter Conversion 90CF581 6 bit Equivalent Description Encoded on LVDS TXIN TXIN Dual Pixel Name Single Pixel Name Data Pair 20 15 Blue Pixel B bit 3 Blue Pixel bit 3 2 19 14 Blue Pixel B bit 2 Blue Pixel bit 2 2 18 13 Blue Pixel B bit 1 Blue Pixel bit 1 1 15 12 Blue Pixel B bit 0 Blue Pixel bit 0 1 17 Blue Pixel A bit 3 Blue Pixel bit 7 3 16 Blue Pixel A bit 2 Blue Pixel bit 6 3 22 17 Blue Pixel A bit 1 Blue Pixel bit 5 2 21 16 Blue Pixel A bit 0 Blue Pixel bit 4 2 12 09 Green Pixel B bit 3 Green Pixel bit 3 1 09 08 Green Pixel B bit 2 Green Pixel bit 2 1 08 07 Green Pixel B bit 1 Green Pixel bit 1 1 07 06 Green Pixel B bit 0 Green Pixel bit 0 0 11 Green Pixel A bit 3 Green Pixel bit 7 3 10 Green Pixel A bit 2 Green Pixel bit 6 3 14 11 Green Pixel A bit 1 Green P
103. ation Guaranteed 888 88 SOURCE www artisantg com A rtisan Artisan Technology Group is your source for quality TecmoogyGroup new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilized and idle used equipment TENS OF THOUSANDS OF at our full service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment 7 EQUIPMENT DEMOS HUNDREDS OF InstraV ea REMOTE INSPECTION LOOKING FOR MORE INFORMATION MANUFACTURERS Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com information on price quotations drivers technical LEASING MONTHLY specifications manuals and documentation RENTALS ITAR CERTIFIED D a gaa tia Contact us 888 88 SOURCE sales artisantg com www artisantg com
104. bit access only Control Register This register is used to set the dot clock frequency for static display feature genlock and some video output options 800 BFF 0 3FC HSP 5 11 16 or 32 bit access only High Speed Port optional allows the 34020 to directly copy data into memory via a 32 bit port connected to VMEbus P2 connector 5 15 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 5 8 VCL M PCI bus Side Device Buffer Selected Relative See by LAR Address Device Section Function 0000 0 7C 34020 5 5 0000 20 2C WRITEMASK 5 5 2 400 0 C RBGS561 5 8 400 20 2C 8242PC 5 10 400 CO DC DACFIFO 5 8 400 100 IDF QUART 5 9 400 1C0 General Purpose 5 7 Control Register 400 1EO User Jumpers The 34020 provides control and video timing registers The writemask register supports display memory bit plane write protection The high resolution color map processes the primary overlay and cursor pixel data into 8 bit Red Green with Sync and Blue analog video outputs The 561 also includes on chip 2 bit bitmap cursor gamma LUT digital output and PLL pixel clock The 8242PC is an Intel 8042 programmed with the Phoenix Multikey keyboard BIOS The DAC FIFO buffers data transfers to the RGBS561 The 26C94 Quad UART QUART provide RS 232 ports for mouse trackball LK401 type keyboard and console
105. calculated by adding a host CPU s A16 or A32 VMEbus base address an offset In this example A16 VMEbus is the base address which the host CPU has mapped to the VMEbus A16 space see Section 6 2 and is of the form A16 VMEbus abcd 0000 In many systems A16 space is mapped to high memory so let s assume that A16 VMEbus FFFF0000 A32 VMEbus is the base address which the host CPU has mapped to the VMEbus A32 space see Section 6 2 and will be A32 VMEbus xy00 0000 Fot this example let s assume xy 10 5 25 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Calculating the VCL V CSR and DBR Base Addresses The VCL V s CSR group A16 address has a jumper selectable base address which we assume here to be C000 set by jumpers in Section 2 4 1 Therefore the board appears at the 32 bit address A16 VMEbus C000 so we would get FFFFC000 The DBRADR is a register containing the high 6 bits of the DBR A16 address see Section 5 2 4 The actual VMEbus offset value D offset DBRADR 400h Let us assume D offset 8000 DBRADR 20 The board appears at the 32 bit address A16 VMEbus D offset so we would get FFFF8000 Calculating the VCL V A32 Base Address The XARADR is a register containing the high 6 bits of the A32 extended address see Section 5 2 3 The actual VMEbus offset value X offset XAR 400000h Let us assume X
106. can supply software which you can use to load new images into Flash 4 8 Programmed Logic Devices Virtually all logic on the VCL is contained in commercial parts such the 34020 bus buffers and programmed parts The board uses several AMD MACH Programmed Logic Devices PLDs This section outlines the functions implemented by them 4 11 Theory of Operation Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf AMD MACH Programmed Logic Devices The VCL V uses AMD MACH211 MACH231 and MACH445 PLDs All parts use EEPROM technology which permits easy reprogrammability Starting with VCL V Fab Rev 2 the PLDs are In System Programmable ISP which means that they are soldered onto the board and programmed via a special programming connector All VCL M boards use ISP The MACH parts use two to eight 26V 16 building blocks linked by a partially implemented crossbar switch Registered and asynchronous I O pins abound and I O and buried register per pin capability global clocks and resets are included The MACH445 adds input registers Theory of Operation 4 12 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Part Number VCL234 VCL78 Part Number VCL23478 Table 4 1 VCL V VMEbus side PLD Device Summary Device Type Description MACH445 A16 A24 A32 space VMEbus decoder CSR bits 0 15
107. ceceeaueceeececsesseaesecececeeseaaeceeececseseaasseeeesccesenseaeeeeeeeeeenees 4 6 4 4 34020 FUNCTIONAL UNIT cccccccccccececsessssececececeesssaeceeecceseeaaesecececeesesaeceeececeeseaaeseceesceesenssaeeeeseeeeesees 4 7 rss ies E E EEO lt lt ge E A EA E A PO EO 4 9 4 6 DISPLAY MEMORY ccccccccccecsessssssecceececsessesececececseesueseeseceseeaaesecececeeseaaeseeeceeseseaaeaeeeeseeesenssaeeeeeeeesenees 4 9 4 7 SYSTEM MEMORY sccsccccccecsesssstcecececsessaeceeececsesssaeeecececeeseaseseeececseseuaeaeceeeceesesusaeseeeeseseasaeeeeseeesensea 4 11 4 8 PROGRAMMED LOGIC DEVICES ccsesesssseceeeesesseeeceeececseseaeeeeecseseueaeseesccesesuaeeeeececeesssaseeeseeesensaaees 4 11 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf CHAPTER5 ON BOARD DEVICES AND MEMORIES ccscsssesssessessseoees S L 5 1 INTRODUCTION ise 2eceisetesevse dence sehbestedeh sien aE Eea EE EEE EEE OEE EE EA EEEE EERE ARTE E EEEE EE 5 1 5 2 VMEBUS VCL V CONTROL REGISTERS ccssscesseecssccesncecsseceeeeecsaeceeneecsaccsaeecsaeceneecsaeeseeeecaeensnees 5 3 5 3 PCI BUS VCL M CONTROL REGISTERS osori e e Eia a E E E EE EAR 5 10 5 4 LNEADDRESS REGISTER LAR Jroen enoksen eass e aiae t ia E a EE AE EEEE A 5 13 5 5 TMS 34020 GRAPHICS SYSTEMS PROCESSOR cscsscecesssetseeececsessnsececececseseaeaeeeecesesesnsaeceeseeesenseaees 5 17 S0 INTETALIZATION TABLE S airearen r AEE E
108. ch byte is located on a long word boundary The first two bytes make a 16 bit address register Byte 3 and Byte 4 are data buffers for the register cursor and color and gamma lookup tables 5 49 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf In order to make loading of the RGB561 as fast as possible the address register autoincrements after each access to one of the data buffer bytes In the case of access to control registers the address register increments after each access If you set the high bit in the high byte of the address register autoincrementing is disabled It takes 1 byte wide data buffer access to load a control register or cursor functions Because the gamma and window attribute table WAT functions are 10 bits wide it takes 2 accesses to load each entry Finally since each color map entry has an 8 bit Red Green and Blue component it takes 3 accesses to load it All registers but not LUTS are cleared by reset The details of the internal control registers are documented in the RGB561 data sheet RGB561 Access Register Summary There are four register entries which are accessed by the 34020 or the host bus The RGB561 data sheet details the internal register set Table 5 19 RGBS61 registers VMEOffset PCI Offset Mnemonic Function 3 0 ADRLO amp Low and High bytes of the 16 bit 7 4 ADRHI address register A
109. clude Plasmaco Planar and Mitsubishi Installing Your Rastergraf Display Board 2 52 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 2 34 Flat Panel Supplier Summary Connectors Company Address Phone FAX 3M 6801 River Place Blvd 800 225 5373 800 325 5329 Austin TX 78726 512 984 1800 Elco Huntington Industrial Park 814 643 0700 814 643 0426 Huntington PA 16652 Hirose 2688 Westhills Court 805 522 7958 805 522 3217 Simi Valley CA 93065 6235 JAE 142 Technology Drive 714 753 2600 714 753 2699 Irvine CA 92718 JST 1200 Business Center Drive 708 803 3300 708 803 4918 Prospect IL 60056 Molex 2222 Wellington Ct 708 969 4550 708 969 1352 Lisle IL 60532 FPC Cable Company Address Phone FAX Parlex 7 Industrial Way 603 893 0040 Salem New Hampshire Engineering Kits adapters for Sharp s weird connectors Company Address Phone FAX Milgray 2860 Zanker Rd 408 456 0900 408 456 0300 Ste 209 San Jose CA 95134 Examples Engineering kit for the Sharp LQ12D011 is Milgray RT 42 2 53 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 2 34 Flat Panel Supplier Summary continued Display Panels Company Address Phone FAX Mitsubishi c o QCI 2216 O Toole Avenue 408 432 1070 San Jose CA 95131 NEC
110. d configuration data in the VCL s Serial EEPROM Rastergraf s PTERM is a terminal emulator for use as a simple interface where a console terminal is not available It is not a comprehensive VT 100 emulator but can be used effectively in the vi editor or as a terminal emulator PTERM can also be used to initiate an OS boot procedure Once the OS is up PX Windows can be started whereupon PTERM ceases to function Console terminal output can be redirected to an xterm window By running a special program PX Windows can be killed and PTERM restarted There is at this time no hot key function to permit dynamic switching A cable is connected between the host computer s console port and the graphics board Console Port In addition a Rastergraf keyboard must be connected to either the graphics board s LK401 or PC Keyboard port The program runs the console link at 9600 baud selects automatically between PC Keyboard or LK401 Keyboard and can be jumper configured for 7 or 8 bit data and RTS CTS or XON XOFF See Section 2 6 7 for a complete description of PTERM jumpers and functions 3 9 Software Summary Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 3 7 Software Development Package A SunOS based C compiler cross assembler and linker for user written 34020 applications is available from Rastergraf Its general characteristics are described below Contact Rastergraf
111. d long data swapping All data passing between host bus and 34020 side goes through this device Provides LRDY and BUSFLT to 34020 Supplies address decoders for color maps cursors HSP general purpose control register PC Keyboard and serial I O Has input jumpers for DRAM size and 8 bit pixel VCL 8 or 32 bit pixel VCL 24 VRAM Supplies RAS lines for graphics and system memory Decodes LADO 3 for page mode writes refresh VRAM special functions shift register load writemask block fill color register and FPU select Provides modified SF line to VRAMs for correct special function operation Controls 74BCT16652 hidden writemask register Provides chip select and special address decoding shift for autobooting PROMS Controls access to the RGB561 RAMDAC microprocessor port Latches the digital video data which is shared across that port Formats the data for the digital video output Pipelines the blanking and horizontal and vertical sync Supplies the sync control functions of the General Purpose Control Register GPCR Supplies the pixels VCLK external sync genlock and ICS1562 3 wire control interface functions of the General Purpose Control Register GPCR ICS1562 is used as the pixel clock in genlock applications VCLIMACH231Decodes LADO 3 to support VRAM block write for the VCL V 24 Takes the two low order 34020 low address lines and CAS lines and recodes them according to the VCL V 24 memory architecture to cor
112. dbook 1992 pages 72 92 and 212 243 RGBS561 Product Specification IBM Microelectronics IOG561DSU 02 Rev 1 1 Route 100 Somers NY 10589 1 800 IBM 0181 VME64 Specification VITA 10229 N Scottsdale Road Suite B Scottsdale AZ 85253 602 951 8866 PCI Local Bus 2 1 Specification PCI Special Interest Group P O Box 14070 Portland OR 97214 800 433 5177 Graphics Textbooks Fundamentals of Interactive Computer Graphics Addision Wesley 1993 Foley and Van Dam Principles of Interactive Computer Graphics McGraw Hill 1979 Newman and Sproull General Information 1 8 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 1 4 General Specifications for the VCL Series Graphics Processor Floating Point Unit Non Display Memory EEPROM Memory Video Display 1 9 General Information 40 MHz TMS 34020 Graphics System Processor has a complete instruction set 32 bit CPU vector and pix blt functions and programmable video timing A socket is provided on the VCL V board for the companion 40 MHz TMS 34082 Floating Point Unit FPU coprocessor which can accelerate floating point intensive operations by an order of magnitude Due to space limitations the FPU is not available for the VCL M Memory is 4 MB of 32 bits word byte addressable no wait state dynamic RAM This memory is in the same memory space as the display memory so it can hold program s
113. ddress and 1 for the data Therefore FIFO Full Flag from the FIFO is not provided because FF 0 does not mean that it is permissible to write to the FDR as the FIFO might overrun To use AFF as a Full Flag set FOR to 1 5 55 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Testing FIFO Present Test Write a 0 to FCRO This resets the FIFO Read a 3 from FCRO EF and AEF are set Read a 0 from DUART 1 IP3 No interrupt request from FIFO Write a 1 to FCR1 EFIE is set Read a 1 from DUART 1 IP3 An interrupt request from FIFO A diagnostic test can be run Board side software could use a subset of this to test for the presence of the FIFO Note this is only a diagnostic test not a functional test Diagnostic Test Write a 0 to FCRO This resets the FIFO Read a 3 from FCRO EF and AFF are set Test the R W bits in FCR1 if interrupts in DUART for IP3 are disabled Write a 0 to FCR1 FIFO interrupts are disabled Test the R W bits in FCR2 Write a 4 to FCR2 FIOREN is set Read a 7 from FIOR EOR LSB set to default Read a 0 from FIOR EOR MSB set to default Read a 7 from FIOR FOR LSB set to default Read a 0 from FIOR FOR MSB set to default FIFO Sizing Test Write a 0 to FCRO This resets the FIFO A FIFO size test can be run The FIFO may have a depth of 64 256 512 1K 2K or 4K words The depth can be
114. de has run Section 5 3 has details on how the PLX9060 controls access to the on board registers Since it is not intended for PC type applications the VCL M does not support an x86 BIOS However Rastergraf does have autobooting PROM sets for the VCL M which will make it load and run Built In Self Test terminal emulator SmartPTERM PTERM console emulator PX Windows server or Graphics Subroutine Package programs in its on board CPU Contact Rastergraf for more information on these options 2 11 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf You will notice that there isn t any good information supplied here which will allow you to reliably probe the VCL M addresses That is because the ability to do this is absolutely dependent on the CPU board memory map as implemented by the system OS and the address ranges of the PCI bus as determined by the CPU hardware These things change from OS to OS board to board and vendor to vendor making this simple task a big pain Therefore you have to work closely with your CPU board the OS s BSP and collateral information supplied by Rastergraf and PLX to actually touch the registers Fortunately if you install the PX Windows or Graphics Subroutine software the board will show up and you will get pictures 2 4 2 Default Interrupt Settings on the VCL M Rastergraf boards are confi
115. determined by the number of R W bits in the EOR or FOR 5 bits for the 64 word part 7 bits for the 256 word 8 bits for the 512 etc Note that the non R W bits are intended to but not guaranteed to read 0 Another method of determing the FIFO size is to set NMODE disables FIFO to DAC writes then writing FDRn until the ORF flag is set counting the writes If the FIFO is initially empty the actual FIFO size is number of writes 1 times 2 Remember because each FDRn write takes 2 FIFO locations the usable FIFO size is 1 2 the actual FIFO size On board Devices and Memories 5 56 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 5 22 Register Summary Mnemonic Offset FCRO FCR1 FCR2 FIOR FDRO FDRI FDR2 FDR3 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 Ox1C Function This register reads EF AEF AFF and ORF Writing this register resets the FIFO Contains FIFO interrupt generation control bits EFIE AEFIE AFFIE and ORFIE Contains FIFO control bits FDM1 FDMO and FIOREN This is actually 2 registers EOR and FOR FIFO Data Register 0 Data written to this register get written to DAC register 0 via the FIFO FIFO Data Register 1 Data written to this register get written to DAC register 1 via the FIFO FIFO Data Register 2 Data written to this register get written to DAC register 2 via the FIFO FIFO Data Registe
116. ding The two sections have little to do with one another except for passing data back and forth once loaded with a program and started the 34020 can run independently of the host Note that the 34020 cannot directly interact with the host bus in other words it can t act as a bus master Of course on the VCL M the PLX9060 s DMA controllers can partially compensate for this Except for the CSR group the 34020 has complete control over the functions of the board The host bus going through the 34020 host interface also has ready access to those functions The 34020 provides a very fast and efficient interface to the host supporting byte operations and translating host bus 8 16 and 32 bit accesses into the 34020 s native 32 bit environment The 34020 host bus arbitrator allows the host PCI PMC or VME bus to access not only the CSR group but also the 34020 side devices The 34020 participates in the termination of those cycles since it must synchronize them to its own bus activity The latching bus transceivers are actually controlled by the 34020 which reads or writes them in conjunction with the completion of the cycle requested by the arbitrator When the arbitrator receives the request from the host bus it asserts the 34020 control lines HCS HWR HRD and waits until the 34020 responds typically within 100 ns If data is being read from the 34020 side then that data is loaded into the host bus 34020 32 bit bus transceivers whe
117. dmond OR 97756 USA TEL 541 923 5530 FAX 541 923 6475 email support rastergraf com Company Information Company Name Contact Phone Number Fax Number email Monitor Information Monitor Brand Model Number VCL Information Model Number Serial Number Horizontal Timing Information Note Horizontal timings may be given in pixel units if given or time units Horizontal Pixels per Line Displayed Pixel Time or Frequency optional Horizontal Total Line Time or Frequency Horizontal Front Porch Horizontal Sync Width Horizontal Back Porch Vertical Timing Information Note Vertical timings may be given in line units or time units Vertical Lines Displayed Interlaced Yes No Vertical Lines Total or Frequency Field Rate Vertical Lines Total or Frequency Frame Rate same as Field Rate unless interlaced Vertical Front Porch Vertical Syne Width Vertical Back Porch Sync Information Composite Sync on Green Yes No If Not Composite Sync on Green Sync Format Composite or Separate Horizontal and Vertical Sync Polarity or Composite Horizontal Vertical Additional Notes On board Devices and Memories 5 38 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 5 6 2 Vertical and Horizontal Zoom Neither CLP Graphics Subroutine Package nor PX Windows support dynamoc zoom
118. e data bits 24 31 while its byte 3 A0 A1 11 is the low byte data bits 0 7 Since the VMEbus can do byte and word operations on board memories care must be taken that bytes are not inadvertently swapped Long word operands are stored by the VMEbus with the high order word bytes 0 and 1 preceding the low order word bytes 2 and 3 in memory the reverse of the 34020 The TI cross assembler compiler tools will supply the object code in big or little endian The Rastergraf downloader and software are written for little endian The VMEbus must use an odd address for byte access of 8 bit devices e g color map and DUART Table 5 9 Byte Word Longword Mapping VME 34020 Byte Data Address Address Lines Byte Addressing 0 3 24 31 l 2 16 23 2 l 8 15 3 0 0 7 Word Addressing 0 2 16 31 2 0 0 15 Long Addressing 0 0 0 31 5 5 5b Example Code for Software Byte Swapping If you consider the graphics memory as a 2D array of bytes and index into it as a byte matrix the byte order will be reversed relative to the 34020 byte sense This can be dealt with easily by Exclusive ORing the low two bits of the index pointer In C this would be primem y x 3 pv where primem is the memory 5 21 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 5 5 5c The Hardware Byte Swapper A hardware byte swapper has been included in the VCL V design
119. e 561 s clock This is usually only for genlock or slow pixel clock applications 5 31 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 5 16 Summary of Initialization Tables Filename LIVVGA8 ibm L1VX108 ibm L1V1x18 ibm L1VX128 ibm L1VX168 ibm L1Vsn38 ibm L2VFP28 ibm L2VFP38 ibm L3VFP08 ibm LSVVGAQ9 ibm L5VX109 ibm L5V1x19 ibm L5VX129 ibm L5VX169 ibm L5Vsn39 ibm L6VFP29 ibm L6VFP39 ibm L7VFP09 ibm Decoding the Filename Characters Characters 1 2 Board Model Configuration Frequency Type VCL n 8 VGA 640x480 27 MHz Analog VCL n 8 1024x768 80 MHz Analog VCL n 8 1024x1024 100 MHz Analog VCL n 8 1280x1024 110 MHz Analog VCL n 8 1600x1280 170 MHz Analog VCL n 8 Sun Mode 3 107 MHz Analog VCL n 8 Flat Panel 1024x768 27 MHz Digital VCL n 8 Flat Panel 1280x1024 110 MHz Digital VCL n 8 Flat Panel VGA 640x480 27 MHz Anal amp Dig VCL n 24 VCL n 24 VCL n 24 VCL n 24 VCL n 24 VCL n 24 VGA 640x480 27 MHz Analog 1024x768 80 MHz Analog 1024x1024 100 MHz Analog 1280x1024 110 MHz Analog 1600x1280 170 MHz Analog Sun Mode 3 107 MHz Analog VCL n 24 Flat Panel 1024x768 27 MHz Digital VCL n 24 Flat Panel 1280x1024 110 MHz Digital VCL n 24 Flat Panel VGA 640x480 27 MHz Anal amp Dig Format 8 bit analog 8 bit digital 8 bit analog and digital 24 bit analog 24 bit digital 24 bit analog and digital Ll L2
120. e a display which has the memory array on binary boundaries e g a 1280 x 1024 active display inside a 2048 x 1024 video memory video wide 2048 display wide 1280 the CVxX YL instruction executes in 2 machine cycles But if you use midline reload and make DINC video wide display wide 1280 then CVxXYL will take 3 machine cycles Now for the killer if the display wide is not a sum of two powers of 2 e g 1600 the CVxXYL goes to 15 cycles This translates to a real world performance loss of about 30 Thus it is faster although not cheaper to have a memory array of 2048 x 1024 pixels Note If the video wide is gt 1024 or 2 then you must use midline reload because of the requirements of the VRAM used on the VCL See the 34020 User s Manual Chapter 9 for more information Wraparound Effects when Panning Scroll Wraparound occurs when as you pan horizontally the data at the end of the line appears at the beginning of the line The only way on the VCL to get an exact horizontal wraparound where data on a given line wraps to the beginning of the same line is to run with video wide 1024 and not use midline reload Various strange effects result when panning the display if video wide display wide and or if midline reload is enabled If video wide 1024 then panning past the end of video wide will wrap the display to the next scan line Also the last scan line of each 1 MB of display memory will wrap to th
121. e board to interrupt the VMEbus When entering the interrupt service routine VINTEN should be cleared To avoid spurious interrupts be sure that the 34020 s interrupt request flag has dropped before reenabling VINTEN Interrupts are level sensitive i e if VINTEN is enabled after a device interrupt has been asserted the VMEbus will be interrupted immediately The VMEbus interrupt request goes away only if the VINTEN is cleared Device interrupts are latched if VINTEN is on Enables byte swapping in the 64 MB window s A32 address range Note that when this bit is set the address range expands to 256 MB from 64 MB selects the XAR register for access through the dual function XAR DBRADR address match registers CSR group offset 8 See Section 5 2 4 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 5 2 3 A32 Address Map and the XARADR Address Register The VCL has an extended addressing function which allows a VMEbus host to linearly access the board through a 64 MB block in A32 space You can access all on board devices and memory through this block Except for PX Windows multiprocessor drivers Rastergraf software does not use A32 access In order for the A32 space on the board to respond the XARADR register must be set up with a valid address the 34020 must be initialized and CSR bit XMEMON must be set Caution Do not set XMEMON until after the XARADR
122. e first scan line If video wide 1024 n and midline reload is not on then panning past the end of video wide will wrap n lines back every n lines Just for information if you are using Static Display see Section 5 6 3 and 5 7 the static display can be set to one screen width 1K 2K 4K or 8K while DINC which controls the other display can be set to some other value To scroll you must add the value of DINC to DPYSTRT If you scroll up by adding the line going off the top will appear at the bottom when you reach the end of memory 5 41 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf The appearance of smooth vertical scrolling can be obtained by synchronizing the scrolling with Vertical Sync If DPYST is changed during the vertical retrace interval then the screen will move smoothly It is important that the registers be changed immediately after vertical sync Some jerkiness in the scrolling may be observed if there is a significant delay Note that for interlaced displays the screen s must be scrolled 2 lines at a time not 1 as is the case for non interlaced display Static Display and Scrolling As discussed in Sections 5 6 3 and 5 7 the VCL can be programmed to support a stationary primary or overlay while the overlay or primary respectively is panned or scrolled By setting the correct bits in the GPCR Section 5
123. ectly in a system where the base board is a PCI motherboard In this case you use a Technobox 1586 PMC to PCI adapter to enable plugging a PMC board the VCL M into a PCI slot Although perhaps not suitable for a long term installation it can be a convenient thing to do The following instructions tell how to modify the VCL M FAB REV 0 and above to a non standard configuration Refer to Figure 2 4 Jumper Option Locations for VCL M at the end of this section for jumper locations For wire wrap changes only KYNAR or TEFLON not enamel or plastic coated insulated wire should be used 2 4 1 Checking Board Addresses on the VCL M Since the PMC bus actually it is really a PCI bus and the VCL M are configured by the operating system and or BIOS while booting up there isn t any hardware to change for the addresses Refer to the Rastergraf PX Windows and Graphics Subroutine Package manuals for more information The Rastergraf VCL M uses registers in the PLX9060 PCI bus to local bus bridge chip internal register set and also has address ranges outside the PLX s internal address space which give access to the VCL M s control registers and memory blocks The BAR Base Address Register sets in the 9060 are programmed to point to these areas The Rastergraf VCL M device driver loads these registers And if you can determine the actual PCI base address you should be able to probe the address spaces with an on line debugger once the driver co
124. ed to the 34020 X2P interrupt pin Internally an interrupt can be caused by break receiver full and transmit ready for either channel Externally an interrupt can be caused by one of the two DUART input lines which function as change of state interrupts from the PC Keyboard controller The interrupt mask register IMR filters out unwanted interrupts A complementary interrupt status register holds the ANDs of the request s and the corresponding IMR bit While there are general purpose serial I O routines in the CLP Subroutine Package CLP has no knowledge of a mouse or keyboard For the mouse you will have to take the 5 byte packets and convert them into cursor motion on the screen If you use an LK401 type keyboard with CLP you will have to generate a scan code to ASCII translation table because the LK401 is not ASCII neither is a PC Keyboard 5 61 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 5 10 PC Keyboard Mouse Controller 8242PC The VCL includes a PC Keyboard Mouse controller chip This is an Intel 8042 preprogrammed with the Phoenix Multikey keyboard mouse BIOS It supports both AT and XT keyboards and the PS 2 mouse The PC Keyboard is supported in the CLP Graphics Subroutine Package Please refer to the CLP manual for details 8242PC interrupts are processed through the DUART or QUART change of state inputs This i
125. ed until the next HSL cycle is started DUARTO Auxiliary Control Register VSL going low indicates preparation to read a new frame VSL is a static bit controlled by software No transitions will occur on VSL unless frames are being transferred to the VCL No set duty cycle is ascribed to VSL Its period depends on the size of the frames being transferred Only the falling edge is important HSL going low indicates preparation to transfer a line of data The first data of a line should be presented to the HSP data bus in response When frames of data are not being transferred a programmable timer on the board will ensure a reliable stream of HSL pulses which the UE can use for refresh When frames are being acquired HSL will be activated before each line by the software The period is a function of the time it takes to transfer a line of data HSL may have a varied duty cycle and only the falling edge is important REL is low indicates that data is being read from the buffer New data may be presented as soon as REL goes low no hold time is required Data should be valid 20 ns before REL goes low REL will be low for 62 5 ns it shouldn t matter to the UE what this is REL is inactive when frames are not being transferred Only the falling edge of REL is important Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 5 12 VCL Interrupts The VCL provides priorit
126. eeeeessnsnaeees 1 9 1 5 MONITOR REQUIREMENTS cccsccccccecsesssesecececsessssssecececceseseseeececseseuaeaesecseceseseaeeeeeesesesaaeeeeseeesenseaees 1 17 1 6 CONFIGURATION INFORMATION cccsesssseeececsesssssseccceceesenseseeececeeseaaeeeseeseceseaesseeeeeeeeeeseaaeeeeseeesenseaees 1 18 CHAPTER2 INSTALLING YOUR RASTERGRAF DISPLAY BOARD 2 1 2A INTRODUCTION isecen niise E estrus seadae dbs Solan eis ead doce ERE EEEE RERE eee 2 1 2 2 UNPACKING YOUR BOARD 42 fe50 55 5cs055 cheeses ieaiaia aor AE EEE ER ORE KE EREEREER ieee 2 2 2 3 VCLE V INSTALLATION 5 seces522 605 csie Sera ae ees teste ses dances lass EEA ERE ee E OESE EE 2 3 24 VCE M INSTALLATION cece 20 00e0 30000500 ceseraecavsee ses EE A ies cik tad sees EERE EEEE devon ea she ee ESR 2 11 2 5 OTHER CONFIGURATION JUMPERS FOR THE VCL SERIES ccccesssecessesceceeaeeecsneeeeeeseeeceesaeeesseeeeenes 2 16 2 6 CHECKING YOUR DISPLAY 2esicssese c 54 deics deshe0as050des EEE REEE EE EEE KEEA EEEE EE a EEEE EEE 2 23 2 7 RS 232 CONNECTIONS TO THE VGLiuiis ccseeseceessescedessesceseececcsecncetiaces dea secesduasneesseddheesseeesdusdecceceadeieeasss 2 24 2 8 PS 2 CONNECTIONS cesses tenisere s aee EEEE ORE AEE EEE E E EER EES A EAE ETCEN SEE EEEE EEEE 2 31 2 9 VIDEO CONNECTIONS TO THE VL cccccsssccececsesssssceececsenseaeeececscseeaeseesccesesuaeeeeecscsesssaeeeeseeesenseaees 2 35 2 10 HIGH SPEED DATA PORT VCL V ONLY eccsssescessssessecstesecuevseenaeenceaecaessecaee
127. eir addressing Having initialized the 34020 and set the CSR MEMON bit these registers appear as shown on the next page Note Except where noted LAR 400 devices are byte D8 addresses Convert to D16 address by subtracting 1 Convert to D32 address by subtracting 3 On board Devices and Memories 5 14 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 5 7 VCL V Side Device Buffer Selected Relative See by LAR Address Device Section Function 0000 0 7F 34020 5 5 The 34020 provides control and video timing registers 0000 2C 2F WRITEMASK_ 5 5 2 The writemask register supports display memory bit plane write protection 400 3 F RBG561 5 8 The high resolution color map processes the primary overlay and cursor pixel data into 8 bit Red Green with Sync and Blue analog video outputs The 561 also includes on chip 2 bit bitmap cursor gamma LUT digital output and PLL pixel clock 400 20 2F 8242PC 5 10 The 8242PC is an Intel 8042 programmed with the Phoenix Multikey keyboard BIOS 400 C0 DF DAC FIFO 5 8 The DAC FIFO buffers data transfers to the RGB561 400 103 13F DUART A 5 9 The 2681 Dual Aynchronous 400 143 17F DUART B Receiver Transmitters DUARTSs provide RS 232 ports for mouse or trackball LK401 type keyboard and console etc User Jumper inputs and control bits for programming the Serial EEPROM 400 1CO General Purpose 5 7 16 or 32
128. eive interrupts from the the host bus and from serial I O The 34020 mediates all host accesses to display and processor memory and control registers through a byte addressable 32 bit interface port Bus transceivers between the 34020 bus and host VME or PMC bus support single and burst 16 and 32 bit data transfers The 34020 features single cycle execution of general purpose instructions and most common integer arithmetic and Boolean operations from instruction cache A 32 bit barrel shifter supports single cycle shift and rotation for 1 to 32 bits The 34020 graphics processing hardware supports pixel and pixel array processing It incorporates two and three operand raster operations with Boolean and arithmetic operations XY addressing window clipping and checking to n bits pixel transforms transparency and plane masking Operations on single pixels PIXT instruction or two dimensional arrays PIXBLT are supported TMS 34082 Floating Point Coprocessor VCL V only For floating point intensive applications a socket is provided on the VCL V for a 34082 FPU coprocessor due to space constraints the FPU is not available for the VCL M The 34082 conforms to the IEEE floating point standard 754 1985 for binary floating point single or double precision addition subtraction multiplication division square root and comparison In addition it offers 32 bit integer arithmetic logical comparisons and shifts Complex operations f
129. ellaneous control bits 16 or 32 bit access CO80 E00 1C0 VCL M User Jumper Input Register Bits 16 23 valid Jumper A on Bit 16 etc C080 F00 1E0 On board Devices and Memories 5 30 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 5 6 Initialization Tables The 34020 must be programmed to generate the proper video timing for the hardware configuration and display format This section includes a list of precalculated timing tables and their applicability You can check pin 13 horizontal and pin 14 vertical on the video connector for correct timing intervals If you think that the table you are using is incorrect or you don t know which table to use please call Rastergraf The following table summarizes the notation for board features Table 5 15 VCL Option Description Option Type Description X10 Analog Digital 1024 x 768 X Compatible X12 Analog Digital 1280 x 1024 X Compatible X16 Analog Digital 1600 x 1280 X Compatible Digital is limited to 1280 x 1024 The table on the following lists some common initialization tables by board and oscillator type This listing is accurate as of the time of manual publication The ibm file suffix means that the PLL pixel clock in the RGB561 color map is used Although not shown in this table the file suffix can also be ics In that case it means that the ICS1562 programmable pixel clock is used instead of th
130. er Description VSYNC HSYNC Blue Green Red Sync Ground Blue Ground Green Ground Red Ground OANNNABRWN KE MVI 2 2 VCL M to VGA Breakout Cable The MVI cable is the MDSM to VGA cable The MDSM end plugs into the VCL M and is retained with jackscrews The VGA end plugs into the computer side of a VGA cable The following table provides the wiring information Installing Your Rastergraf Display Board 2 36 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 2 22 MVI Cable Connections MDSM End VGA End Pin Pin Number Name Number Name 1 VSYNC 14 V CSYNCOUT 2 HSYNC 13 HSYNCOUT 3 Blue 3 Blue 4 Green 2 Green 5 Red 1 Red 6 Sync Ground 10 SyncGround 7 Blue Ground 8 Blue Ground 8 Green Ground 7 Green Ground 9 Red Ground 6 Red Ground 2 37 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 9 2 Digital Video Connector VCL M Digital video is encoded into LVDS Low Voltage Differential Signaling compatible data Each of the five LVDS differential pairs carries seven digital video TTL lines A separate pair carries the PLL clock for the LVDS system LVDS allows longer data cables and reduces emitted noise The VCL M uses a 90CF581 FPD Link transmitter from National Semiconductor Dat
131. essor s A16 VMEbus address space 2 5 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 3 3 Interrupt Grant and Priority Jumpers Rastergraf boards are normally configured for interrupt level 3 IRQ3 If you change this setting the device driver needs to be changed accordingly Rastergraf boards have a programmable interrupt vector address which is usually set by the software to default to EO hex However some platforms such as Sun permit the vector to be chosen transparently by the operating system In these cases you do not need to specify an interrupt vector address Make sure that any boards which do not use interrupts have their interrupt pass grant jumper installed Conversely remove the jumpers for all boards that use interrupts Finally make sure you install the jumper in slot 0 IACK to IACKIN Don t confuse this jumper with the IACKIN IACKOUT jumper On many backplanes slot 0 IACK to IACKIN does not have a removable jumper IACK is always connected to slot 0 IACKIN The VMEbus has a seven level interrupt grant receive acknowledge protocol which requires each board to acknowledge that it is responding to the interrupt grant level that it requested Three jumpers set this response level Refer to the Jumper Location Figure for the VCL V above for the location of the jumpers In the table below 0 equals jumpe
132. f Contents THE ORGANIZATION OF THIS MANUAL cecsssceeesssececseseeceeseeecsesaececeeeeecsesuececsesaececuaeeceesaeeecseaaeeesneeeenes 1 1 GRETTING HBL ces ezcacesse2eesieacesgeesaveseeesncdegeuancseducas E E 1 2 BOARD REVISIONS cccssssscessescecsessececseseeeessneeecsssaececseseeseeseeeecsesaeeeceeeeeeesaeeecsesaececeuaeessesueeecseaaeeeseeeeeenes 1 2 INOTIGES ise 3 3eesscnseeeg cagstecadwndgeresezadecivatacsuestes teas odd guvsecdeas canes eguvaenss duces lt adgaeeeadescdenchaneiacttahee EEE 1 3 INOTIGES ise sc E E E incnegeueeads A E E 1 3 MANUAL REVISIONS cccsssccesssscecsessececsnscecessececsesaececseseeceesueeecsesaececeaeecsesaeeecsesaeesceseeceesaeeecseaaeeeceeeaeenses 1 3 CONVENTIONS USED IN THIS MANUAL ccssssscecssssececsssceceeseeecsesaececeeeeesesuececsesaececaeeeseesaeeecseaaeescseeeenses 1 4 CHAPTER 1 GENERAL INFORMATION 22 cccccccscscscscscccscccscscscccscessccescessceeeee L 1 1 1 INTRODUCTION si 545 ccuehcadeceqesdecceebeacnasGasdenckedsitedassteacdacs du Diran n EEr inei Ennii sa nir Sae tein Eiee Ernita riia et 1 1 1 2 FUNCTIONAL DESCRIPTION cccccccccecsessssscecececsesssseceeececsessuassecececceseausseeececseseaasaeeecsceeseauaeteeeeeeseaaaaees 1 2 1 3 ADDITIONAL REFERENCES cccsccccccecsessssssecececeessansecececsessuaseecececeeseaaesesececsessaasaesececeeseeseteeeeeeserseaaees 1 8 1 4 GENERAL SPECIFICATIONS FOR THE VCL SERIES cccecsessscecececeeseeeseeececeessascesececeeseauseee
133. from pins 3 4 or 7 There are current limiting resistors in series with the power sources for these lines See Section 2 7 Table 2 11 Serial Mouse Connector Pinout D Sub Pin Number Description TX or to means VCL is source not used RX Data from Mouse Port 0 12 Volts via 470 ohm resistor or TX Data to Mouse Port 0 Optional 12 Volts via 220 ohm resistor Ground Optional RX Data from LK401 Port 1 12 Volts via 220 ohm resistor Optional TX Data to LK401 Port 1 Optional 5 or 12 volts Ww N OANINNA 2 27 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 2 12 Mouse Port Port 0 and Port I VCL V Jumper Mouse Connector Pin Option Default JP405 1 2 pin 3 to 12V yes JP405 2 3 pin 3 to Port 0 TX no JP406 1 2 pin 4 to fused 5A 5 volts no JP409 1 2 only pin 9 to fused 5A 12 volts no JP409 2 3 only pin 9 to fused 5A 5 volts no JP407 1 2 pin 6 to LK401 Port 1 RX no JP408 1 2 pin 8 to LK401 Port 1 TX no Notes Current draw on pins 3 4 and 7 should not exceed 10 mA Table 2 13 Mouse Port Port 0 and Port I VWCL M Jumper Mouse Connector Pin Option Default JP303 9 10 pin 3 to 12V yes JP303 8 10 pin 3 to Port 0 TX no Notes Actual connections to the Mouse and LK401 are determined by how the breakout cable is built Current draw on pin 3 should not exceed 1
134. g 0x0c Oxc2 0x0000 MSW Mailbox 0 0x0e OxcO 0x0000 LSW Mailbox 0 0x10 Oxc6 O0x0000 MSW Mailbox 1 0x12 Oxc4 0x0000 LSW Mailbox 1 0x14 0x82 Oxffff MSW PCI to local addr range 2K 0x16 0x80 Oxf800 LSW PCI to local addr range 2K 0x18 0x86 0x0000 MSW PCI to local addr remap Oxla 0x84 0x0001 LSW PCI to local addr remap dec enabld Oxlc 0x22 Oxff O0x0000 spare eeprom data 0x24 0x92 0x0000 MSW ROM address range 0x26 0x90 0x0000 LSW ROM address range 0x28 0x96 0x0000 MSW ROM remap amp BREQ control 0x2a 0x94 0x0000 LSW ROM remap amp BREQ control 0x2c 0x9a 0xf003 MSW local bus ctrl coplt transfers JX 0x2e 0x98 0x0143 LSW local bus control prefetch disabled ready enabled JX 0x30 0x9e 0x0000 MSW local to PCI memory decode range 0x32 0x9c 0x0000 LSW local to PCI memory decode range 0x34 Oxa2 0x0000 MSW local to PCI decode 0x36 Oxa0 0x0000 LSW local to PCI decode 0x38 Oxa6 0x0000 MSW local to PCI IO decode range Ox3a Oxa4 0x0000 LSW local to PCI IO decode range Ox3c Oxaa 0x0000 MSW local to PCI control amp remap Ox3e Oxa8 0x0000 LSW local to PCI control amp remap 0x40 Oxae 0x0000 MSW local to PCI CFG control 0x42 Oxac 0x0000 LSW local to PCI CFG control 0x44 0x7e Oxff 0x0000 spare eeprom data Important register bits in the PLX EEPROM Control Register offset Ox6c Bit 16 CRTCON Clear holds 34020 reset Bit 29 Reload Configuration Registers from EEPROM when toggled 0 to 1 Bit 30 Reset Toggle 1 to
135. g and the DEVINTEN in the CSR is set the board will drive one of IRQ1 through IRQ7 lines depending on the IRQ jumper option selection The VME interrupt handler will then drive true VIACK IACKO and AS and drive true or false AO1 A03 LWORD DS1 and DSO depending if it wants a D32 D16 or D08 Status ID A01 A03 reflect the interrupt priority the interrupt handler is acknowledging When the interrupt controller receives these signals it compares A01 A03 with the vector priority select jumpers VPSELO 2 If there is not a match it will drive IAKO as outlined above If there is a match it will cause a read of 4 5 Theory of Operation Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf the 8 bit Interrupt Vector Register IVAR The board will drive the contents of the IVAR into bits 0 7 of the transceivers Bits D08 D31 are not driven by the board They are pulled high by the VMEbus terminators The interrupt cycle then terminates as a normal read cycle The interrupt handler uses the vector number read from the board to point to an exception routine address As the interrupter is a RORA device the exception routine should negate or toggle the DEVINTEN bit in the CSR The exception routine then executes its function and ends with an RTE return from exception instruction 4 3 VCL M System Design The following discussion assumes a working knowledge of the PCI bus
136. g color map 1 5 array conversion routines 3 6 auto increment 5 23 base address calculation 5 25 baud rate see DUART and QUART 1 7 big endian 5 20 block mode 4 4 block transfers 5 3 board side runtime support 3 6 bus architecture 4 8 byte sense 5 20 byte swapper 5 22 Byte Word Longword Mapping 5 21 color map 5 46 color palette and controller routines 3 6 color register 5 19 Common Board Configurations 1 18 Common CPU board addresses 6 3 6 8 CompactPCI 0 1 configuration information 3 6 Configuration Information 1 18 Console Port 2 2 29 Console connector 2 26 Control Registers 5 3 conventions used in manual 1 4 CPU board addresses 2 4 CRTCON 5 4 CSR 4 2 CSR 5 4 CSR Address and Interrupt Grant Level Jumpers 2 5 CSR Bit Definitions 5 5 CSR Bit Summary 5 4 CSR group addresses 5 3 cursor 3 6 D16 6 2 D32 6 2 DAC FIFO 5 53 data bus 4 8 DBR 5 14 DBRADR Address Match Register 5 7 DBRADR Registers 5 7 device addresses 5 23 device and memory access routines 3 6 device buffer 5 14 device selection 4 3 digital color map 1 5 Digital Output to LVDS Transmitter Conversion 2 39 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Digital Panel Cable Assembly Notes 2 42 Digital Video Connector 2 41 display memories 1 3 4 9 5 19 double precision math routines 3 6 DRAM and VRAM Size Jumpers 2 16 DUART 1
137. gisters which control the characteristics of the board as required by the PCI Specification The information used to program these registers is supplied to Operating System OS specific functions by Rastergraf s software Ordinarily several address map translations occur including the CPU physical and virtual address maps and the CPU to PCI bridge address map The result of this is that the operation of the PCI board either VCL P or VCL M is very sensitive to the host CPU as no standards have been adopted which guarantee or even imply universality among CPU boards even if they use the sam e CPU and PCI bridge Therefore it is vital to ensure that Rastergraf can vouch for the board s operation in a particular CPU before you go crazy trying to figure out why it doesn t Please contact us support rastergraf com or 541 923 5530 if you have problems Troubleshooting 6 9 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 6 6 Maintenance Warranty and Service Maintenance The VCL requires no regular service but if used in a particularly dirty environment periodic cleaning with dry compressed air is recommended Because of the heat generated by normal operation of the graphics board and other boards in the system forced crossflow ventilation is required If forced ventilation is not used IC temperatures can rise to 60 degrees C or higher Such high temperature
138. gured for interrupt request INTA Since each PMC slot maps its interrupt lines to a permuted set of INTA INTD the VCL M will show up on a different interrupt line according to the slot it is plugged into Therefore the device driver needs to be changed accordingly to reflect this The VCL M has a programmable interrupt vector address which is set by the Rastergraf device driver 2 4 3 Installing the Graphics Board Use the following procedure to install the VCL M into the computer 1 Shut down the operating system and turn off the power Warning Never open the computer without turning off the power supply Unless internal AC wiring is exposed leave the power cord plugged in so as to ground the computer chassis You can easily get shocked ruin computer parts or both unless you turn off the power Even with power switched off lethal voltages can exist in the equipment 2 Open the computer and remove the CPU board onto which the VCL M is to be installed Find identify an empty PMC location typically there are at most two on a given CPU board In the interest of allowing air flow and if you have a choice try to install the VCL M in the location which allows the best airflow through card cage Installing Your Rastergraf Display Board 2 12 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 3 Ifyou are using the digital video connector you may need additi
139. h as the mouse keyboard or trackball and graphics display and 2 The client s which is are the actual programs which the user wants to interact with This might include a terminal emulator desktop publishing program or an image processing package The client application is usually linked with the standard XLIB library which manages the actual communications between clients and the server Most operating systems come supplied with a local xlib and a standard client package Many also come with the Motif window manager Contact your OS vendor for specifics on what they supply Under certain circumstances and for particular operating systems Rastergraf can supply an extended version of PX Windows which includes a client side package including Motif As this software is currently in development please contact Rastergraf for availability Software Summary 3 4 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 3 5 Graphics Subroutine Package The Graphics Subroutine Package hereinafter referred to as CLP comprises a significant value added component for the Rastergraf display controllers It is intended for the user who wishes to interface an application program directly to the board CLP is a library of subroutines which run under a shell on the graphics board and provide functions for the board CLP is based on the TI math graphics library Modified and en
140. hanced by Rastergraf the package contains over 250 subroutines It is designed to allow the user to program the board without having to contend with all the hardware details All font characters are software defined patterns which are drawn in the graphics memory The subroutine package supplies about 40 bit mapped fonts which are from TI They include contemporary and typewriter styles in different weights and pitches CLP has a second set of fonts which are derived from X Window System fonts A utility program is available which can convert X fonts over to CLP CLP is compatible with BSD and System V Unix and many real time operating systems Operating systems using memory management must allow the user to map to the portions of the I O page where the board registers are accessed The packages will map the I O page for operating systems using memory management Two versions of CLP are included a A hybrid version wherein a front end process running in the host computer interprets subroutine calls and directs commands to be executed by the 34020 on the graphics board In some cases it is more efficient to directly execute these functions so the 34020 is not used b A board based version for standalone programs The user links the CLP with an application program developed with Rastergraf s Program Development Package compiler assembler and linker see section 3 2 CLP and the application runs entirely on the graphics board Other softwa
141. he DAC during blanking only The FIFO provides a parallel path to the DAC so the DAC can still be accessed in the usual way However the programmer must be careful not to access the DAC when the FIFO is feeding the DAC The two paths are asynchronous and do not know about each other so conflicts would result Fortunately it is easy to determine when the FIFO is done via a status bit EF aka Empty Flag Using the FIFO The FIFO and DAC should be initialized before use Refer to the following sections and Tables 5 20 through 5 23 for more details Method 1 Poll EF Empty Flag before each access and only write data when the FIFO is empty This is inefficient because it takes 2 accesses minimum for each DAC write and the FIFO never gets loaded with more than 1 value 5 53 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Method 2 Poll AFF Almost Full Flag before each access and only write data when the FIFO is not full This is not as inefficient as method 1 but it still takes 2 accesses minimum for each DAC write Method 3 Program the FIFO so that AFF or AEF Almost Full Flag or Almost Empty Flag reflect some specific number of words left 64 for example Then do that many accesses to the FIFO before checking the flag This is more efficient than method 1 or 2 but won t use the whole FIFO There is a tradeoff between how man
142. he VCL each VRAM shift loads four pixels at one time into the RGB561 RAMDAC for output sequencing This implies a minimum of 4 pixels pan resolution Also to be taken into account is the nominal bits pixel for example the VCL V 8 is 8 bits pixel and the VCL V 24 is 32 bits pixel This difference is accounted for by a multiplier of 8 or 32 A pan address is calculated as follows DPYSThpew desired offset in increments of 4 x bits pixel Thus in order to pan the display by four pixels on a VCL V 8 you add 0x20 to DPYSTL on the VCL V 24 you add 0x80 DINC Registers and Midline Reload The DINC register determines the horizontal memory width You must set DINC video wide x bits pixel Video wide is the logical memory width e g 2048 or 1024 If midline reload is enabled then DINC can be set to be exactly the visble display width video wide display wide Otherwise it must be a multiple of 1024 1K pixels Using midline reload and setting DINC to the display width would allow you to use 2 MB of VRAM to get 1600 x 1280 instead of 4 MB While using midline reload in this way can save you money you can experience a significant performance decrease Certain graphics operations such as ConVertx XY to Linear CVxXYL are dependent on the screen pitch On board Devices and Memories 5 40 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf For example if you hav
143. hen the X server or CLP is running the values in the initialization table you used may not be correct see the Section 5 4 You can select a different table or call Rastergraf for assistance If you have any trouble with any part of the installation refer to Chapter 6 Otherwise proceed to the instructions supplied in your software manual 2 23 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 7 RS 232 Connections to the VCL Although all the VCLs have RS 232 functions separate subsections are provided for connections to the VCL V and VCL M This is because the front panels for each board are very different All VCLs support 4 serial ports Serial devices are suitable for applications which require long cables because they use the RS 232C electrical protocol which can support cable lengths well in excess of 100 feet When running PX Windows typically only two ports are used one for Serial Mouse and one for Console PTERM The other two ports can be used to provide a second serial pointing device e g trackball and serial LK401 keyboard The LK401 is handy when cable lengths are long since a PS 2 PC keyboard can t drive more than about 10 feet In general the VCLs support Data Leads Only RS232C which means that the XON XOFF software protocol must be used to control data flow However RTS CTS is supported for the
144. his section describes the features of the RGB561 Some of these features are not directly used or supported in the Rastergraf PX Windows or CLP Graphics Subroutine Package PX Windows does not support window type tables or multiple color maps The CLP Graphics Subroutine Package has the potential to support some unused RGB561 functions by virtue of special subroutine calls which allow you to access any internal register The composite video output is generated by the IBM RGB561 RAMDAC The RGB561 is used in two different modes depending on whether the VCL is configured for 8 bits per pixel or 24 bits pixel It provides individual color maps for the red green and blue planes in 24 bit mode and supports a pseudo color translation of 8 bits into a full 24 bits 8 bits each for red green and blue It has a 1024 entry lookup table LUT for primary and overlay and 12 entries for cursor colors Programmable Window Attribute Tables WATs select the starting address in the LUT and other parameters for both primary and overlay An additional gamma correction LUT precedes the output DACs The RGBS561 converts the pixel data coming from the display memory into analog voltages which drive the display monitor A separate data path takes the 8 MSBs of the R G and B and sends them out a 12 bit digital data port The 24 bits are divided into high and low nybbles 12 bit words There are two ways to make this conversion true color and pseudo color
145. hree lights on Finally if all is well the green Pass light goes on If PTERM encounters a problem it will terminate operation blink the red Fail light according to the following table then stop with the Fail light on Table 2 7 Initialization Table Selection Options Blink Count 1 Hn nn A WwW N 10 11 gt 16 Problem Board was not initialized and board side code was not able to load an initialization table either from memory or the serial EEPROM The board side code was unable to determine the board type The pixel size set to a value other than 8 or 24 The pixel is incorrect for this board configuration Unable to determine the video width The video width does not match the VideoWide info variable from the initialization table Display size too big Either DisplayWide is larger than VideoWide or DisplayHigh is larger than VideoHigh Initialization table does not match board type Initialization table does not match colormap type not used Bad initialization state IBMS61 software error 2 21 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Built In Self Test and Console Emulator SmartPTERM Rastergraf has released SmartPTERM which is an Open Firmware Monitor and BIST System It is a Flash based auto booting monitor that provides Built In Self Test BIST front panel LED diagnostics and can
146. hronized locked to external horizontal and vertical signals This works in conjunction with the 34020 to provide a completely genlocked system 4 6 Display Memory The display memories chips are expressly designed for high speed graphics applications These devices are called video RAMs VRAMsS They are like ordinary DRAMs but they also contain an internal 256 x 16 4 9 Theory of Operation Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf line buffer During a special data transfer cycle an entire row address worth of data is loaded into this line buffer The VRAMs have a mode control input DT OE which is used to trigger a data transfer When DT OE is active when RAS is asserted a data transfer cycle occurs The row address selects a line of data and the column address selects the starting position within that line The data are then shifted out by a serial clock 16 bits clock appearing at the outputs Since the internal VRAM buffer needs to be loaded only once per line time the VRAM is available for random access operations at all other times There is a small additional overhead time for memory refresh which occurs about once every 15 us Thus VRAM availability for external access is about 95 as compared to about 35 for DRAM The VMEbus accesses the memory via the 34020 host interface which includes two 74BCT16652 bus transceivers The 34020 accesses the
147. igital Video Connector J206 ececccecceeeeeeteeeteeeeeees 2 38 Digital Output to LVDS Transmitter Conversion eeceeseeeeeeeeeteeeeeees 2 39 Video Connector Pim OU sisese aE E E E 2 40 How to Connect Unused Digital Input Lines 0 0 ee eee eeeeeeeeeteeeneeeees 2 43 VCL Digital Video Connector J206 ssissscccsiasssccsanisieceoaisacctaarsseivalanecsevnans 2 45 NEC NL10276AC20 01 Conn GtOs x cisiccsacssvanstienssseesdvactaciiantalenssiocsaene s 2 46 NEC NL12810AC20 04 Connections ccssecccosscesessseccssssesentensnessnes 2 47 Sharp LO 10D X01 Comme etiiis iaccasiascssncscacveevetiassenseetvianscatevwsiteeesaavseoasens 2 48 Sharp LQ12D011 C GhineciOIns lt ssecadecatxiiecniatbnceine lect xnaoioaadiee 2 49 Sharp 640 x 480 Panel Ss aissqenuctence aacecgunterceeeumaeuaernr macabre amaume 2 50 Sharp EL Panel Model LJ64ZU48 9 cccssicccasesce eisveidespsuieedcussvieaeeenaciodere 2 51 Panel Side Connector Summary ccccceccceeceeeeeeeeeeseeceeeceeceeeeeeseeesseenes 2 52 Flat Panel Supplier Summary s ssnesenseeseseseesseseneseessrssrnssesseesresseeseesersseesse 2 53 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 2 35 Table 3 1 Table 3 2 Table 4 1 Table 4 2 Table 4 3 Table 5 1 Table 5 2 Table 5 3 Table 5 4 Table 5 5 Table 5 5 Table 5 6 Table 5 7 Table 5 8 Table 5 9 Table 5 10 Table 5 11 Table 5 12 Table 5 13 Table 5 14
148. ignal will be asserted because the 34020 should be able to service UART interrupts prior to the next character being received The RTS signal will control output from PTERM to the host Note If RTS is enabled but not connected PTERM will not transmit to the host Table 2 5 PTERM Serial Control Options Jumper Function Open Shorted A serial mode 8 bits No parity 7 bits Even parity B XON XOFF disabled enabled C RTS CTS disabled enabled 2 19 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Initialization Tables in PTERM The PTERM flash EEPROM contains 4 default tables The Serial EEPROM which is a different memory can contain up to four more tables The tables in Serial EEPROM can be changed by reprogramming Contact Rastergraf to obtain the necessary software to do this When jumper G is not installed PTERM checks to see if there are any tables in Serial EEPROM It will use every table it finds in place of the corresponding table in Flash EEPROM Thus if there are no tables in Serial EEPROM the default tables 0 3 are used if there is one table in Serial EERPOM that table is used in place of Table 0 The table below shows you how to select one of four standard initialization tables When jumper G is installed PTERM uses the table set in Flash EEPROM Thus if for some reason you don t want to use Serial
149. installation and functional problems with your board Most sections are devoted to the VCL V VME version 6 2 Selecting an Address Range for the VCL V Board 6 3 VCL V Memory Map Address Example 6 4 Does this VCL V board talk at all 6 5 Dealing with the PCI bus 6 6 General procedures 6 7 Maintenance Warranty and Service Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 6 2 Selecting an Address Range for the VCL V Board Note It is necessary to determine the correct address ranges of your CPU before you attempt to run the Rastergraf software If you are unable to do so even after reading this section please contact Rastergraf for assistance Most CPU boards used on the VMEbus have a 32 bit physical address space even if the CPU chip itself only puts 24 bits i e 68000 or 68010 Normally a bus controller chip such as the VIC068 or SCV64 located on the CPU board converts the CPU chip s physical addresses to VMEbus addresses Certain blocks of VMEbus address space are assigned to A16 A24 and A32 VMEbus address types Unfortunately since the VMEbus specification does not dictate a memory map for the address types each manufacturer s board has its own assignments Clearly knowledge of the details of the processor board memory map are important you need to know the map in order to test out the board Normally the CPU board s boot PROM will set up
150. ire some handling care Unless you have the special tools you will probably have to have the cables made outside If you look at the pinout shown in Table 2 25 you will see that it has a ground between every signal Note that by convention pin 1 and pin 2 are next to each other on the same side of the connector Pin 35 is exactly opposite pin 1 You can use either ribbon cable or discrete twisted pair wiring to build the cable If you use discrete wiring pairs we recommend that you pair the signal with the adjacent ground pin e g pin with pin 2 You will notice however that the connector signals are assigned in such a way as to yield grounds both opposite and adjacent to signals That is pins 1 3 5 33 are signals as are pins 36 38 68 This means that you get twisted pairs going across the connector too You have to remember then that the signals are going to alternate 1 36 3 38 and so on With ribbon cable the cable assembly which is made for a 68 pin connector of this type can be done in two ways Only one way is correct First This is the right way two 050 space ribbon cables are made one cable is pressed into pins 1 34 and the other into pins 35 68 Grounds are properly interspersed with signals Second This is the wrong way a single 025 space ribbon cable is pressed onto all the pins Grounds are paired with grounds Warning Please follow the cabling recommendations You may come to grief if you
151. isan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 3 Software Summary 3 1 Introduction This chapter provides an overview of Rastergraf s software offerings Rastergraf also has Software Product Descriptions and complete Technical Manual sets for the PX Windows and Graphics Subroutine Package products Rastergraf provides software for the VCL including Rastergraf PX Windows X11R6 X Windows Server 34020 Compiler Tools Rastergraf s Open Firmware based Built In Self Test BIST terminal emulator PTERM and booter SmartPTERM and finally a comprehensive Graphics Subroutine Package generically CLP The following table summarizes the current availability Contact Rastergraf if your choice is not shown Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 3 2 Software Availability by Platform and OS Table 3 1 Rastergraf Software and Operating Systems Support Operating Current OS Subroutine System Version CPU Type PX Windows Package HPUX 10 10 PA RISC yes no LynxOS 2 5 PowerPC yes no Digital Unix 4 0 Alpha yes yes OS9 3 0 68K yes yes psOSystem 2 0 68K yes yes Solaris 2 5 SPARC yes yes SunOS 4 1 4 SPARC yes yes Unison 3 2 68K yes no VxWorks 5 3 68K yes yes VxWorks 5 3 PowerPC yes yes VxWorks 5 2 MIPS yes no VxWorks 5 2 SPARC yes no In addition to being available by FTP and on CD ROM media the board
152. itors For best performance a monitor should have the following features Color RGB with composite sync on green analog video input Switchable Termination for monitor loopthrough Height pincushion width phase and position controls Autotracking horizontal and vertical synchronization High bandwidth 70 MHz 640 x 480 135 MHz 1280 x 1024 180 MHz 1600 x 1280 Horizontal refresh rate 32 KHz 640 x 480 70 KHz 1280 x 1024 90 KHz 1600 x 1280 Note A standard VGA type multi scan monitor can be plugged directly into a VCL V or VCL M s adapter cable VCL V and VCL M Standard Display Timing Specifications Display Vertical Horizontal Pixel Format Refresh Refresh Clock 640 x 480 60 Hz 31 5 KHz 27 MHz 1024 x 768 60 Hz 60 KHz 80 MHz 1024 x 1024 70 Hz 64 KHz 85 MHz 1280 x 1024 67 Hz 64 KHz 110 Mhz 1280 x 1024 72 Hz 72 KHz 125 MHz 1600 x 1280 60 Hz 79 KHz 170 MHz See Table 5 14 for more initialization table information Composite Video Signal 1 Volt peak to peak consisting of 660 mV Reference White 54 mV Reference Black 286 mV Sync Level 1 17 General Information Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 1 6 Configuration Information The basic graphics board includes hardware cursors hardware pan scroll and zoom programmable pixel clock hardware byte swapper VCL V 4 RS 232 data leads only serial ports 2 PS 2 compatible ports
153. ixel wrtcol wrtmem wrtplcol wrtplmem zoom rect PS 2 Mouse Routines ps2_init ps2 read ps2_peek ps2 error ps2_ flush ps2_mouse_position ps2_set_kdbleds ps2_mouse_warp Serial I O Routines sio_break sio error sio_iflush sio_init sio_oflush sio_peek sio_read sio_ write Text Attribute Routines add_text_space char high char wide max get ascent get descent get_first_ch get last_ch get leading get_width Text Output Routines clr_draw_string clrw_draw_ string draw_char draw_ string nw_draw_char nw_draw_string Three D Transformation Routines copy_matrix copy_vertex init matrix perspec rotate scale transform translate vertex_to_ point Viewport Routines close_vuport copy_vuport cpw get_vuport_ max init vuport move _vuport nw_close_vuport nw_copy_vuport nw_select_vuport nw_size_vuport open_vuport select_vuport set_cliprect set_origin size_vuport Software Summary 3 8 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 3 6 SmartPTERM Rastergraf can supply SmartPTERM which is an Open Firmware based Monitor and BIST System It is a Flash based auto booting monitor that provides Built In Self Test BIST front panel LED diagnostics and can boot to PTERM a simple vi compatible terminal emulator CLP or PX Windows ROM images included SmartPTERM can store and modify initialization tables an
154. ixel bit 5 1 13 10 Green Pixel A bit 0 Green Pixel bit 4 1 03 03 Red Pixel B bit 3 Red Pixel bit 3 0 02 02 Red Pixel B bit 2 Red Pixel bit 2 0 01 01 Red Pixel B bit 1 Red Pixel bit 1 0 00 00 Red Pixel B bit 0 Red Pixel bit 0 0 05 Red Pixel A bit 3 Red Pixel bit 7 3 27 Red Pixel A bit 2 Red Pixel bit 6 3 06 05 Red Pixel A bit 1 Red Pixel bit 5 0 04 04 Red Pixel A bit 0 Red Pixel bit 4 0 90CF581 6 bit Equivalent Encoded on LVDS TXIN TXIN Description Data Pair 23 Panel Power Enable 3 26 20 Composite Blank 2 24 18 Horizontal Sync 2 25 19 Vertical Sync 2 FPSHIFT FPSHIFT Pixel Clock CLK 2 39 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 9 3 VGA Analog Video Connector VCL V The video connector is a VGA style compressed 15 pin D SUB The R G and B video outputs are driven by the RAMDAC which is capable of driving terminated cable 75 ohms to standard RS 330 IRE levels Cable length should be limited to 50 feet unless you use low loss RG 59 A VGA monitor can be plugged in directly using a standard VGA connector You must use the correct initialization table since a VGA monitor depends on the sync polarities to determine operating frequency If you use the Rastergraf VGA 3 20 VGA to BNC cable only composite signals are carried to the monitor and it will autoscan if the monitor is so e
155. ized interrupts for use with the 34020 and the host CPU The host bus can be interrupted by the 34020 Interrupt sources for the 34020 are the DUART or QUART host bus and line count Vertical Sync is not supported because the 34020 has internal registers which support interrupt on any line Interrupt enables are handled at the device level The host bus receives a single interrupt from the 34020 A host bus interrupt enable in the VCL V CSR VINTEN is used to disable interrupts to the VMEbus See note about VINTEN in Table 5 2 See Section 5 2 5 for information about the VMEbus Interrupt Vector Address Interrupts to the PCI bus VCL M are controlled by the PLX9060 The following table provides information regarding the interrupts For the 34020 side interrupts all device interrupts are OR d into X2P interrupt see 34020 internal registers INTENB and INTPEND This means that you have to poll the DUART or QUART to find out who interrupted Figure 6 1 in the 34020 manual has a complete Vector Address Map Table 5 27 VMEbus Interrupt Functions Interrupt VMEbus Standard Source Addresses assumes VECADR 40 34020 100 Table 5 28 34020 Interrupt Functions Interrupt 34020 autovector 34020 INTPEND Source address register name DUART FFFF FFAO X2P 34082 FPU FFFF FFCO X1P On board Devices and Memories 5 64 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf
156. k is very useful on the 24 bit VCL Due to space limitations there is no 24 bit VCL M On a VCL V 24 with a 1280 x 1024 display the video memory is 8 MB and is expandable to 16 MB 4 7 System Memory The 34020 has its own private 32 bit memory which is independent of the video RAM VRAM configuration and timing Obviously the writemask register is not used with system memory because it would cause unpredictable operation of the board The system memory resources for the VCL are comprehensive and consist of four components SIMM sockets for field upgradability and Flash EEPROM Section 5 3 4 has address ranges and memory maps for the DRAM and EEPROM memories SIMM Sockets The VCL V is built with a 72 pin SIMM socket because it allows considerable manufacturing flexibility 4 MB 16 MB and 32 MB units can be fitted into the same slot with only jumper changes required to accommodate the different capacities Rastergraf makes some of its own SIMMs because most commercial vendors do not make modules short enough The SIMM must not exceed 95 inches in overall height Note that due to space constraints the VCL M has soldered in memory Using 64 Mb DRAMs the memory options are 16 MB and 32 MB Flash EEPROM The Flash EEPROM uses four 150 ns 32 pin PLCC 8 bit wide parts for a maximum capacity of 2 MB The VCL M uses two 16 bit parts in order to reduce package count The VCL is designed to permit on board reprogramming Rastergraf
157. king 34020 Initialization Parameters 5 35 underlay 5 48 unpacking your graphics board 2 2 VCL Digital Video Connector J206 2 45 VCL Option Description 5 31 VCL M Block Diagram 4 18 VCL M Local Memory Map 5 28 VCL M LVDS Digital Video Connector J206 2 38 VCL M PCI PMC side PLD Device Summary 4 13 VCL M PLX9060 Serial EEPROM Listing 5 12 VCL M PS 2 Breakout Cable 2 33 VCL M PS 2 Connector Pinout 2 33 VCL M Serial Breakout Cable 2 29 VCL M VGA Breakout Cable 2 36 VCL M Video Connector Pinout 2 36 VCL M 8 for PMC bus 1 2 VCL V and VCL M 34020 side PLD Device Summar 4 14 VCL V Block Diagram 4 16 VCL V Local Memory Map 5 27 VCL V VMEbus side PLD Device Summary 4 13 VECADR 5 8 vertical zoom 5 39 VGA cables 5 45 VGA connector 2 36 2 40 Video connector 2 36 2 40 Video Connector Pinout 2 40 video RAMs VRAMs 4 9 viewport routines 3 8 VINTEN 5 4 VLBLT VFILL VLCOL 5 19 VMEbus 4 2 4 5 5 3 installation 2 3 interrupt pass grant jumper 2 7 VMEbus address ranges 2 3 VMEbus addressing 6 2 VMEbus Block Transfers BLT 5 8 VMEbus graphics board addresses 2 4 VMEbus interrupt functions 5 64 VMEbus Side Device Buffer 5 15 VMEbus 34020 address conversion 5 23 Warranty 6 10 What to do With Unused or Extra Data Lines 2 42 window type table 5 50 write posting 3 3 writemask register 5 18 XARSEL 5 4 XMEMON 5 4 zoom modes 5 39 Artisan Technology Group Quality Instrument
158. lay Board VCL Pin 37 6 39 8 41 10 43 12 45 14 47 16 49 18 51 20 53 22 55 24 57 26 59 28 VCL Pin 28 4 35 2 Signal Name NQAQQAQAAQAQAQAQAQQAQAQAQAQAQAQQAQQAQAQAQAQAQAQAQQAQQQ 22 2 Z2 Z Z2 2 Z2 2 Z 2 2 Z 2 2 2 Z Z 2 2 Z SRO RO ROR RORCRORORO RRO RC RORC RO RCRCRORCRC RC RCRS Signal Name GND GND GND GND Description signal ground signal ground signal ground signal ground signal ground signal ground signal ground signal ground signal ground signal ground signal ground signal ground signal ground signal ground signal ground signal ground signal ground signal ground signal ground signal ground signal ground signal ground signal ground signal ground Description signal ground signal ground signal ground signal ground Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 2 27 NEC NL10276AC20 01 Connections VCL Signal NL10276AC20 01 NL10276AC20 01 Pin Name Name Description Pin CN1 38 BB3 BB3 Blue Pixel B bit 3 33 5 BB2 BB2 Blue Pixel B bit 2 35 40 BB1 BB1 Blue Pixel B bit 1 37 7 BBO BBO Blue Pixel B bit 0 39 42 BA3 BA3 Blue Pixel A bit 3 9 9 BA2 BA2 Blue Pixel A bit 2 11 44 BA1 BA1 Blue Pixel A bit 1 13 11 BAO BAO Blue Pixel A bit 0 15 46 GB3 GB3 Green Pixel B bit 3 41 13 GB2 GB2 Green Pixel B bit 2 43 48 GBI GBI Green Pixel B bit 1 45 15 GBO GBO Green Pixel B bit 0 47 50 GA3
159. les only i e not byte addressable Bits 0 15 and bits 16 31 are at board side relative byte addresses 0 and 2 respectively Of course the offsets are reversed for VMEbus big endian accesses They can also be accessed as a single long word at address 0 Table 5 18 General Purpose Control Register Bit Mnemonic R W Function 31 OLAYDIS R W This bit is R W only on VCL 8s which do not use the VMEM8 daughterboard When set all VRAM is allocated to primary no overlay when clear divides VRAM in half for primary and overlay display reads 0 R only On versions which use VMEM8 or VMEM24 29 30 Blink 0 1 R W See Section 5 6 for more information Blink 1 Blink 0 Blink Rate 1 1 slow VS 64 1 0 medium VS 32 0 1 fast VS 16 0 0 no blink Note VS Vertical Sync Frequency 28 MLPEN R W Mid Line Pan ENable MLPEN must be set for horizontal static panning if midline reload is enabled as it will be if video wide 1024 DPYMASK must also be changed See Section 5 6 4 5 43 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 5 18 General Purpose Control Register continued Bit Mnemonic R W Function 27 26 24 25 SDINCO 1 23 SDEN PSEN IDHERE R W R W R W R W 16 22 IDREGO 6 R only 20 22 19 16 18 15 14 13 12 BT0 2 reserved RVO 2 reserved DSKEW DVSPOL DHSPOL R only
160. ling Your Rastergraf Display Board 2 14 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Figure 2 4 Jumper Locations for the VCL M ce s aros aron g g a Dgs manukku e ggz i 3 5 z o Sa u cA g Ci Cd ta O amp ge DRAM DRAM 2g i Hi Bank Lo Bank Fe et eg sede taal ora cece fee J meals 1S we E ae DRAM DRAM JO oS gale Lo Bank Hi Bank 1 Bales AALI E TTT 26 al 38 mor ER aa Og oe o W O 1E o o mbna wat got a Z me L LLANTA KUTTIN at E a ooo CATETAN LILL g E Cna T hii i i 310 a x10 mun 473 Section 2 8 1 JP303 o e Su coer Section 2 6 4 JP301 smd eatin muhindi ozn goza pe Z Green LED 4 ae A x Flash m Yellow LED HiWord r i aon F rmdir Red LED A Bohol eal a A Flash fp m T F wt LoWord i
161. megabytes where n 4 16 or 32 Note VCL M is 16 MB or 32 MB only 2 pages of 1024 x 1024 2048 x 1024 addressable pixels primary and overlay this is already part of an X12 version 4 pages of 1024 x 1024 2048 x 2048 addressable pixels primary and overlay this is already part of an X16 version 8 pages of 1024 x 1024 2048 x 4096 addressable pixels primary and overlay VCL V 8 version only 40 MHz 34082 Floating Point Coprocessor VCL V ONLY Digital Output for VCL M Standard on VCL V 32 bit digital input port on P2 connector for VCL V only Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com rtisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 2 Installing Your Rastergraf Display Board 2 1 Introduction There are 2 steps involved in getting your Rastergraf display board to work in your system Unpack and install the Rastergraf display board Install the software This chapter shows you how to install the Rastergraf display board in your computer The PX Windows Manual and the Graphics Subroutine Package Manual provide instructions on how to install the software Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 2 Unpacking Your Board When you unpack your board inspect the contents to see if any damage occurred in shipping
162. mory is to double the primary memory Thus you can increase the display resolution from for example 1024 x 768 to 1280 x 1024 So you can run an X10 board as an X12 or an X12 as an X16 board as long as you don t need overlay Jumper Settings If the jumper is installed the OLAYDIS in the GPCR see Table 5 19 is overridden and overlay memory is forced on The jumper prevents you from programmably enabling overlay memory Note the VCL M doesn t have a FORCEOLAY jumper so be careful about the OLAYDIS bit If the jumper is removed then the OLAYDIS bit can be set under program control Setting the bit causes all memory to allocated to the primary only and overlay cannot be used Installing Your Rastergraf Display Board 2 18 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 5 7 Selecting PTERM Options all VCLs Figure 2 6 VCL V PTERM Configuration Jumpers JP401 J402 nv ono ono ono For ono ow om rete fefo fel fofo Figure 2 7 VCL M PTERM Configuration Jumpers JP301 cad oo ono on nn ono oo ono Jo Pee Pe Le fo Le a a frown The XON XOFF flow control only applies to data being sent to PTERM However PTERM has an input buffer which can handle bursts of up to 8KB without requiring XON XOFF flow control The RTS CTS flow control is done by programming the UART to enable auto control of the RTS CTS lines It is unlikely that the CTS s
163. n 4 18 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf weibeig 490 g 8 IN 1OA soyd 8 siosuna SLM 40109 yoo 9 exId 1d oaplA eysa sqm Mowe Woyda Wa shS gN ce 91 SJOAIOOSUBIL LYVNOD Odevcs py VHO EHD CHO IHO Od 1Od Jaysi6ay YSCWOW sng yoyeq 8 J9po0eq SSOlppy sueying ss lppy p x jdyny s dn13 u 89149 SJ A ISULIL sng Ja sibey ss lppy un puq snq e90 0 9d 0906X 1d JO e19Ud Buru L JOyeMQUY Wa shS OcOrE HVT HS9 Japo0eq ssoJppy IDd OWd sng 4 19 Theory of Operation Guaranteed 888 88 SOURCE www artisantg com Artisan Technology Group Quality Instrumentation Rastergraf Theory of Operation 4 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 5 On board Devices and Memories 5 1 Introduction As with the other chapters this one covers all the VCLs Most of the features are common so the number of exceptions does not get out of control Operating on the assumption that most users have either PX Windows or CLP generally available detailed device specific information has been omitted This chapter covers the special programming features of the individual devices used on the VCL It is intended to supply information unique to the board or to the application of a particular chip Section 1 2 pr
164. n the 34020 responds If data is being written to the 34020 side the bus transceivers are latched into the 34020 side 32 bit address bus where it is loaded directly into memory or a device Once the reply phase is entered the arbitrator singals to the host bus that the 34020 has completed the transaction 34020 Data and Address Buses The 34020 has a multiplexed address data bus MAD which supplies 32 bit data to memory and devices The 34020 address is actually a bit address not the more customary byte address Thus 34020 address line 5 corresponds to host bus address 2 34020 address lines 0 4 are not used to address memory 4 CAS lines are used instead to select 1 to 4 bytes of the data bus The host bus address line 1 and Upper and Lower Data Strobes are used for byte selection The 34020 also has a separate multiplexed row and column address bus which is used for the dynamic RAMs and video RAMs both of which have multiplexed address inputs In order to ensure retention of the data in Theory of Operation 4 8 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf the VRAMs each row of the 512 rows of data in the memories must be refreshed every 8 ms They are refreshed using the CAS before RAS refresh mode which is controlled by the 34020 s DRAM refresh logic This mode utilizes a refresh counter internal to the memory chip When CAS is asserted before RAS the opp
165. n the card cage that is closest to the CPU Do not leave any slots empty between the graphics board and the CPU 2 7 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Note There must not be any open slots between the first and last boards which use either DMA or interrupts this includes the Rastergraf display board which uses interrupts 3 Remove the interrupt pass grant from the board slot The shorting jumper for Slot 2 IAKIN OUT should be removed assuming the VCL V is to be installed in that slot Shorting jumpers should be installed for all unused slots The jumper may be on the front or back of the backplane Some backplanes don t have jumpers to remove The jumper is an integral part of the slot in such cases It is activated automatically when the card is inserted 4 Wear a grounded wrist strap Touch a metal part of the computer chassis remove the graphics board from its anti static bag and immediately slide it into the slot Caution The static electricity that your body builds up normally can seriously damage the integrated circuits on the graphics board You should first touch the metal part of the chassis which will short circuit the static charge on your body to ground It is preferable to wear a grounded wrist strap whenever handling computer boards Handle the graphics board only by its edges
166. n the display memory by using the writemask register see Section 5 3 3 5 5 5 Byte Ordering and the VCL V Hardware Byte Swapper The infamous big endian little endian dilemma must be dealt with here Big endian means that the least significant byte Byte 0 is assigned to the high order DA24 DA31 data lines Conversely little endian means that the least significant byte Byte 0 is assigned to the low order DA0O DA7 data lines The merits of one way or the other are truly religious and therefore we won t talk about that However we do have deal with the consequences The 34020 is intrinsically a little endian device The VMEbus is big endian Although the 34020 does have a big endian mode there is a performance penalty for using it Therefore the VCL is designed to run little endian A programmable byte swapper is included in the VCL V to alleviate some of the CPU overhead that is otherwise incurred On board Devices and Memories 5 20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf This section contains three parts a a discussion of the VMEbus and 34020 byte ordering issues b example code for software byte swapping c a discussion of the new hardware byte swapper 5 5 5a VMEbus and 34020 Byte Order Mapping The VMEbus observes reversed byte polarity relative to the 34020 and the board internal bus It considers its byte 0 A0 A1 00 to be the high byt
167. nal loopback mode for testing The VCL V uses two Philips SCN2681 DUARTs Dual UART The VCL M uses a single Philips SCC26C91 QUART Quad UART An 8242PC controller provides PC compatible keyboard and mouse ports PS 2 mini DIN connectors are used The VCL V only can be supplied with a 32 bit High Speed Port HSP When connected to a compatible interface via the P2 VMEbus connector the 34020 can pass 32 bit data between the port and 34020 memory The Rastergraf graphics boards are highly configurable for special requirements In order to ensure optimum performance at the lowest OEM cost please contact Rastergraf for quotes for customized feature sets 1 7 General Information Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 1 3 Additional References Rastergraf documentation includes User s Manuals Graphics Subroutine Package Manual and Rastergraf PX Windows Server Installation and User s Guide Data sheet extracts are available upon request The manufacturer sources of this information are TMS 34020 User s Guide Texas Instruments Order SPVU019 Customer Response Center 1 800 232 3200 SCN2681AC1A44 Philips Semiconductors Dual Asynchronous Receiver 811 E Arques Avenue Transmitter DUART Data Sheet Sunnyvale CA 94088 3409 SC26C94C1A 800 234 7381 Quad Asynchronous Receiver Transmitter QUART Data Sheet ICs for Data Communications Data Han
168. nded to 220 MHz by special order The basic display memory size for the 8 bit VCL is 1024 x 1024 8 bit pixels of 32 bits word byte addressable no wait state dual port VRAM Most configurations include both primary and overlay displays The display memory is expandable the 2M option can give either 1280 x 1024 displayable or two pages of 1024 x 1024 pixels The 4M option can give one page of 1600 x 1280 two pages of 1280 x 1024 or four pages of 1024 x 1024 pixels The 8M option can give two pages of 1600 x 1280 four pages of 1280 x 1024 or eight pages of 1024 x 1024 The standard memory size for the 24 bit VCL is 2048 x 1024 32 bit pixels of 32 bits word byte addressable no wait state dual port VRAM This typically provides a 1280 x 1024 display size The display memory is expandable the 4M option can give one page of 1600 x 1280 two pages of 1280 x 1024 or four pages of 1024 x 1024 A writemask register permits individual bits in display memory to be write protected This allows write operations as opposed to read modify write on display memory The VCL contains a special function which allows the overlay screen to remain stationary while the primary screen is moved by changing the 34020 s display start address Alternatively the overlay can move and the primary can be static Normally the 34020 would have to copy the whole screen from one place to another to accomplish this effect which can lead to poor performance f
169. ned Line Drawing Routines init_patn patnpen_line patnpen_ovalarc patnpen_piearc patnpen_point patnpen_polyline pr_patnpen_polygon_abs pr_patnpen_polyline_abs pr_patnpen_polygon_ rel pr_patnpen_polyline_rel styled_line xy_patnpen_polygon_abs xy_patnpen_polygon_rel xy_patnpen_polyline_abs xy_patnpen_polyline_rel High Speed Port Routines hsp_init hsp_isr hsp_planemask hsp_ppop hsp_ transparency hsp direction hsp position hsp start hsp speed hsp duration hsp_ stop Host Only Routines bootboard clrsys devint gcntl GetErrval initboard info info_options int mode loadtask mapboard poll mode sysint Image Change Routines pan panplane panplanerl panrl wpan wpanw Initialization Routines clear_screen init_grafix init_text init_video nw_ init_video init_vuport Miscellaneous Routines delay lib id Imo rmo wait line wait_scan xytoaddr gettimeout settimeout 3 7 Software Summary Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 3 2 Graphics Subroutine Package Library Routines continued Off_Screen Pixmap pixmap_primaryid pixmap_overlayid pixmap_movieid pixmap_ alloc pixmap free pixmap_info pixmap_copy pixmap_ select pixmap_currentid pixmap_read pixmap write Pixel Routines bit_expand get pixel get rect move pixel move rect put_pixel put rect rdcol rdmem rdplcol rdplmem rep_p
170. ng scroll and pan requires only a small amount of overhead as opposed to screen copies which would otherwise be required to move the image Static Display is most commonly used with the CLP subroutine package but can be used under particular circumstances in PX Windows Contact Rastergraf for more information about this option Note Static Display mode is not supported for interlaced displays 5 39 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 5 6 4 Panning and Scrolling Panning and scrolling are techniques used to provide a window into a larger memory than can be displayed This method is also called roaming The display X pan and Y scroll starting points are changed allowing new data areas to be displayed This function is appropriate on the VCL with expanded 8 MB memory or when using a display format of less than 1024 x 1024 DPYST Registers The 32 bit TMS34020 Display Control Register DPYST is used to change the display start address refer to Table 5 15 Example Initialization Table The value loaded is the first address in the frame buffer which will give visible data and points to the upper left hand corner of the display The DPYST register is a 32 bit register but the low order 5 bits are reserved The value loaded into the register is dependent on the frame buffer architecture and the RAMDAC In the case of t
171. on Registers 0x000 0x03C Local Configuration Registers 0x080 0x0AC Runtime Registers 0x0C0 0x0EC and the DMA registers 0x100 0x130 Expansion ROM In theory you might be able to set up the Expansion ROM address space to one of these three address spaces so that two of the three spaces was available at any given time Individual system quirks e g ROM writes disallowed might cause problems with this technique however Note that if your operating system can not change the BARs then the only way to change Local Address Space range is to reprogram the serial EEPROM This can be done via a Runtime Register Rastergraf has software to do this Note the serial EEPROM has some unused locations 5 11 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 5 5 VCL M PLX9060 Serial EEPROM Listing plx_load tab format EEPROM address white space local register address white space data white space optional comment ler address Oxff means no eeprom lt gt lcr mapping exists data lines must start with digit other lines ignored 0x00 0x02 OxB300 Device ID for VCL M 0x02 0x00 0x10F0 Vendor ID Rastergraf 0x04 Ox0c 0x0380 MSW Class Code display other type 0x06 0x08 0x0000 LSW Class Code amp Revision 0x08 Ox3e 0x0000 Maximum Latency Minimum Gnt 0x0a Ox3c 0x0100 Interrupt Pin Interrupt Line Routin
172. onal panel space to mount it since cable comes off the VCL M and has to be routed and installed elsewhere 4 Wear a grounded wrist strap Touch a metal part of the computer chassis remove the graphics board from its anti static bag and immediately slide it into the slot Caution The static electricity that your body builds up normally can seriously damage the integrated circuits on the graphics board You should first touch the metal part of the chassis which will short circuit the static charge on your body to ground It is preferable to wear a grounded wrist strap whenever handling computer boards Handle the graphics board only by its edges Oils from your hand can break down the metal used in the circuit board 5 Remove the blocking plate from computer s front panel and after making sure the board is seated correctly install the four mounting screws two near the front and two near the PMC connectors In a similar way install any additional plate for the digital video port 6 Close the computer and plug the video cable into the monitor and the graphics board Make sure to plug the three BNC cables colored red green and blue into the monitor s corresponding red green and blue inputs If you are using a VGA to monitor 15 pin D Sub cable then of course plug that end into monitor Also make sure the 75 ohm switch on the monitor is turned on VGA monitors which use a 5 wire cable which can be obtained on special o
173. onfigurations 2 or 4 MB of VRAM are soldered directly on the base board Due to space constraints the VCL M 8 video memory which is soldered on the board is limited to 4 MB 5 19 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf The VCL V also has 32 MB of 34020 system memory capacity contained on a field replaceable Single Inline Memory Module SIMM In addition locations are provided for Flash EEPROM devices see Sections 2 6 2 2 6 3 and 5 13 for more information The memory combinations are flexible so that the experienced user may tailor memory tailored to the application Please contact Rastergraf to discuss your requirements The 34020 shares access to the display and system memories with the VMEbus by means of the 34020 s host interface When accessed by the VMEbus or 34020 the display and system RAM are byte addressable The board memories can be accessed by the VMEbus in one of two ways A 1 KB window in A16 or A24 space which gives access to memory selected by the LAR see Section 5 2 or a 64 MB block in A32 space When used the hardware byte swapper quadruples these memory sizes The 34020 addresses long 32 bit words so masking must be done to limit the operation to a single byte or less if desired The masking may be done by setting the proper bit field size in the 34020 or if the operation is to be performed o
174. operation causes IC failures and reduced MTBE With proper forced air cooling IC temperatures will be less than 35 degrees C Warranty The VCL graphics boards are warranted to be free from defects in material or manufacture for a period of 1 year from date of shipment from the factory Rastergraf s obligation under this warranty is limited to replacing or repairing at its option any board which is returned to the factory within this warranty period and is found by Rastergraf to be defective in proper usage This warranty does not apply to modules which have been subjected to mechanical abuse electrical abuse overheating or other improper usage This warranty is made in lieu of all other warranties expressed or implied All warranty repair work will be done at the Rastergraf factory Return Policy Before returning a module the customer must first request a Return Material Authorization RMA number from the factory The RMA number must be enclosed with the module when it is packed for shipment A written description of the trouble should also be included Customer should prepay shipping charges to the factory Rastergraf will prepay return shipping charges to the customer Repair work is normally done within ten working days from receipt of module 6 10 Troubleshooting Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Out of Warranty Service Factory service is
175. or Rastergraf can supply its software with the read after write operation already incorporated When ordering software be sure to specify the CPU Known offenders include 68K PowerPC Alpha and MIPS based CPUs 3 3 Software Summary Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 3 4 PX Windows Server Rastergraf s PX Windows Server is a Motif client compatible X Windows X11R6 board based server for a variety of Operating Systems see Table 3 1 All functions of the server are actually executed by the 34020 which maximizes performance and eliminates many host processor responsibilities Rastergraf supplies the hardware specific parts of the X Window System which is the server Rastergraf has written its own highly optimized graphics layer for the 34020 The software is broken up into 2 functional parts the board based X server and the CPU host side stub program which provides a communication link between the server clients and the CPU network and file system resources The board side server code also provides complete support for PC compatible keyboard or LK401 AA keyboard and Microsoft 2 button and Mouse Systems 3 button compatible pointing devices i e mouse or trackball X Windows is a machine independent network based windowing system It divides graphics functions into two parts 1 The server which controls the hardware dependent functions suc
176. or graphics support include matrix operations 1 x 3 3 x 3 1x 4 and 4 x 4 backface testing polygon elimination and clipping viewport scaling and conversion 2D and 3D linear interpolation 2D window compare 3D volume compare 2 plane clipping X Y Z 2 plane color clipping R G B I 2D and 3D cubic splines 3 x 3 convolution vector operations add subtract dot and cross products 1 3 General Information Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf magnitude scaling normalization and reflection polynomial expansion multiply accumulate and 1D and 2D min max Video RAM The display memories use advanced 4 Mbit 256K x 16 2 port Video RAM VRAM technology which gives approximately 95 memory availability to the 34020 and host processors A writemask register supports write protection of bit planes The 34020 supports the VRAM accelerated functions such a block write and fill with special VFILL and VBLT instructions These can be used to quickly replicate one and two dimensional patterns in memory at up to 16 times the single pixel rate Up to sixteen 8 bit pixels can be written in each 100 ns page mode cycle resulting in a 160 Mpixel sec VFILL time With the VCL V 24 which use 32 bit pixels you get up to 40 Mpixel sec VFILL time 34020 Processor Memory DRAM and EEPROM The 34020 has its own system memory which is independent of the
177. or large screens Scroll single line smooth scroll Pan anywhere on 4 pixel boundaries Zoom vertical 1 2 4 8 16 32 horizontal sub integer uses the RGB561 PLL to adjust master pixel clock General Information 1 10 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Color Map Digital Output Features Serial I O Ports PS 2 Compatible Ports Fuse Elements 1 11 General Information The VCL output uses an IBM RGB561 connected in basic 4 1 mux mode It supports interlaced and non interlaced displays ranging from 640 x 480 up to better than 1600 x 1280 The RGB561 has a 64 x 64 x 2 bitmapped cursor and a Gamma correction LUT The DAC outputs are 10 bits Both analog and digital outputs are supported The digital output is limited to 1280 x 1024 maximum The digital output resolution can be programmed to be 1 4 8 9 12 18 or 24 bits per pixel Dual pixel output mode required for 1024 x 768 and above is supported In this mode pixel width is limited to 12 bits 4 bits each Red Green Blue The VCL M features the LVDS high speed encoded digital interface The LVDS port supports longer cable length and reduced noise sensitivity Four asynchronous serial I O ports are contained in either two Philips SCN2681 DUARTs or SC26C94 QUART Each port can be programmed for transmit and receive baud rates up to 38 4 Kb Receive buffers are quad
178. ord segments It also supports page mode read and write memory accesses for maximum memory performance For graphics memory color register block fill and writemask functions are supported The writemask operation is write enable per bit enable function which allows direct writes instead of read modify writes The 34020 derives its timing from a clock which is independent of the video clock In fact the standard clock is 40 MHz while the typical video clock is 110 MHz The 34020 has internal synchronizers which take care of VRAM memory accesses CPU clock synchronous and VRAM shift load and blank functions video clock synchronous The 34020 has inputs for the VRAM shift and load clocks so that it can keep track of blanking Section 4 2 covers the high speed video clock generation An interesting consequence of the dual clock nature of the 34020 is that if you read a register driven by the pixel clock e g VCOUNT you will get erratic results You have to read the comparison flag or use interrupts to get correct results The reason for this is simple the VCOUNT register can change state in the middle of a 34020 read cycle Its operations are totally asynchronous to the 34020 CPU clock The purpose of this section is to supplement the well written and already complete information provided in the 34020 User s Guide especially in the areas which relate to display timing and memory interface The 34020 User s Guide is a necessary adjunct
179. osite of the normal order the memory chip executes a self refresh cycle In general though devices themselves e g color maps are only eight bits wide so the device registers while located on 32 bit boundaries have at most 8 valid bits 4 5 VCL Clocks There are several clock sources on the VCL a 40 MHz clock for the 34020 and host bus 34020 arbitrator a programmable phase locked loop PLL pixel clock included in the RGB561 or in an ICS1562 for genlock and a 14 7456 MHz reference oscillator for the pixel clock PLL with a divide by 4 to provide a 3 6864 MHz clock for the DUARTs or QUART Phase Locked Loop PLL Clock The VCL incorporates a programmable pixel clock oscillator in the RGBS61 color map chip which is used in most cases However since the 561 does not support a genlock function a separate PLL chip must be used in this case ICS1562 201AM Genlock is not available on the VCL M In either case a PLL allows the user to program virtually any frequency pixel clock up to more than 170 MHz A special order version of the VCL can boost this limit to 220 MHz The PLL uses a 10 MHz oscillator as its reference clock to drive an internal phase locked loop PLL 34020 Video and Processor Clock Synchronization The 34020 among all of its nice features has separate processor and video clocks It has internal synchronizers which make this work The 1562 supports a genlock feature which allows the pixel clock to be sync
180. ou are using the two pixel 12 bit pixel 4 bit color output mode which is common for 1024 x 768 and 1280 x 1024 panels There are panels which have 18 or 24 bits pixel 6 or 8 bits color In two pixel clock mode the VCL supplies 4 bits color so you have 2 or 4 extra bits to deal with Rastergraf recommends that for a given color you connect starting with the high order unused bit one to one to the high order used bits MSB justified Here are two examples Table 2 26 How to Connect Unused Digital Input Lines 18 bit Color Panel 12 bit Panel Panel VCL Panel VCL Bit Bits Bits Pins R G B5 R G B 3 R G B7 R G B 3 R G B 4 R G B2 R G B 6 R G B2 R G B 3 R G B 1 R G B 5 R G B 1 R G B2 R G BO Rk G B 4 R G BO R G B 1 R G B 3 R G B7 R G B 3 R G BO R G B 3 R G B 6 R G B2 R G B5 R G B 1 R G B 4 R G B 1 Power Sequencing Rastergraf recommends that you evaluate the power requirements of your panel including power sequencing very carefully It is tempting to use the graphics board to source power to the panel because it can make the installation nice and neat But panels tend to draw a fair amount of power and generate considerable electrical noise This can lead to problems which may be difficult to track down 2 43 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www
181. outine Package autoboot PROM there will be no display This is because the board doesn t have an automatic boot up sequence to initialize itself Only when you boot your computer and the graphics board software has been downloaded will you see anything In the case of PX Windows your monitor should display a uniform stippled raster and a cross hair cursor which is controlled by the mouse For the CLP you have to load both the sp ram and a test program e g pk_examp1e before you will see anything If your graphics board uses the PTERM terminal emulator a white rectangular cursor should appear in the upper left corner of the monitor As the computer boots it should print messages on the screen If none appear make sure the console connector is correctly plugged in and the console terminal parity and data bits are set correctly see Jumper Settings Once you have a picture on the screen you may need to adjust the width height brightness contrast and hold controls on your monitor to get a good centered image If these controls don t adjust the image properly the parameters used to set the 34020 graphics timing registers might be wrong If you encounter display problems with PTERM the timing parameters may need to be changed However they are not user definable they are hard coded into the PROM Contact Rastergraf for a different PROM set to set the correct display timings for your installation If you encounter display problems w
182. ovides a list of appropriate publications which include manufacturer s data sheets and manuals Rastergraf offers a variety of software to support the VCL in both Unix and real time environments These offerings are covered in detail in Chapter 3 Software includes e demo programs e SmartPTERM Built In Self Test BIST and console PTERM e CLP Comprehensive Graphics Subroutine Package and e PX WIndows X Windows X11R6 server Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Note Please read these sections before starting on this chapter Section 1 2 Functional description of the VCL V board Chapter 2 Installation Chapter 3 Summary of software support from Rastergraf Chapter 4 Theory of operation This chapter includes the following sections 5 1 Introduction 5 2 VMEbus VCL V Control Registers 5 3 PCI bus VCL M Control Registers 5 4 Line Address Register LAR 5 5 TMS 34020 Graphics Systems Processor 5 6 Initialization Tables 5 7 General Purpose Control Register 5 8 RGBS561 High Resolution Analog Digital RAMDAC 5 9 Serial I O Ports 5 10 PC Keyboard Controller 5 11 High Speed Port HSP 5 12 VCL Interrupts 5 13 Flash EEPROM and Serial EEPROM On board Devices and Memories 5 2 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 5 2 VMEbus VCL V Control Regi
183. p 0x28 0x0000 convdp Ox2c 0x0000 pmask1l Ox2e 0x0000 pmaskh 0x30 0x0000 convmp 0x14 Ox01ff dpyint 0x58 0x0000 scount 0x48 0x4000 dincl Ox4a 0x0000 dinch The following are the vertical timing parameters 0x0 5 vesync 0x4 28 veblnk 0x8 1052 vsblnk Oxc 1055 vtotal The following are the horizontal timing parameters 0x2 23 hesync 0x6 48 heblnk Oxa 208 hsblink Oxe 214 htotal Ox4e 190 heserr Ox2a 0x8 psize 1 GPCR GENERAL PURPOSE CONTROL REGISTER 0x0 0x81000008 GPC register Next block is cursor control register block IBM561 0x021 Oxad PLL VCO Divider 0x022 0x05 PLL Reference 0x082 0x10 Divided Dot Clock 0x020 0x02 Sync Control 0x001 0x29 Conf1 0x002 0x19 Conf2 0x003 0x40 Conf3 0x004 0x00 Conf4 0x021 0x00 PLL VCO Divider hack 0x021 Oxad PLL VCO Divider hack hack 5 33 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 5 17 Example Initialization Table continued TI34020_BI 0x10 0xd047 Information region INFO CMMType 0x0080 CURSType 0x0080 Overlay 0 VideoWide 2048 VideoHigh 1024 DisplayWide 1280 DisplayHigh 1024 NumDuarts 2 DlutSize DlutCurs HasScsi MovieMeg MovieHigh MovieWide FlagBits0 DONE FOGOD dpyctl IBM561 IBM561 width of video memory
184. pply via relay connect to supply via relay no connect 4 S5V 5 GND connect to supply NEC NL12810AC20 04 Connections NL12810AC20 04 Name Description Red Analog Red Green Analog Green Blue Analog Blue GND Red Ground GND Green Ground GND Blue Ground GND HSYNC Ground GND VSYNC Ground H SYNC Horizontal Sync V SYNC Vertical Sync GND Clock Ground NL12810AC20 04 Name Description various no connect NL12810AC20 04 Name Description VCC sequenced 5 sequenced 12 VDD1 10 volts VDD2 23 volts VDDC 12 volts backlight BRTH BRTL connect pins via 1K pot BRTC backlight enable GND Ground GND Ground Requires special factory installed jumpers use S12V sequenced 12V from the VCL to control the VDDn voltages NL12810AC20 04 Pin CN1 15 16 17 5 6 AUN e AU NL12810AC20 04 Pin CN2 1 8 NL12810AC20 04 Pin CN3 1 relay 2 47 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 2 29 Sharp LQ10DX01 Connections VCL Signal Pin Name 38 BB3 5 BB2 40 BB1 42 BA3 9 BA2 44 BAI 46 GB3 13 GB2 48 GBI 50 GA3 17 GA2 52 GA1 54 RB3 21 RB2 56 RBI 58 RA3 25 RA2 60 RAI 6 26 even GND 37 59 odd VCL Signal Pin Name 1 CLK 3 Hsync 36 Vsync 33 34 67 5 V 31 64 66 12 V 2 4 30 32 35 65 GND no connect VCL Signal Pin Name connect to power supply no connect connec
185. quipped The direction and polarity of the Vertical Composite Sync and Horizontal Sync are controlled by the General Purpose Control Register see Section 5 5 Table 2 24 Video Connector Pinout Pin AW NN am Description Red Red Ground Green Green Ground Blue Blue Ground n c Ground HSYNCIN connected only for genlock VSYNCIN connected only for genlock SYNC Ground HSYNCOUT programmable polarity V CSYNCOUT programmable polarity Notes for Genlock VCL V Genlock is a special order option which requires additional components to be added to the board Separate TTL level active low horizontal and vertical sync input signals are required Please contact Rastergraf if you are interested in using this feature Installing Your Rastergraf Display Board 2 40 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 9 4 Digital Video Connector VCL V Unfortunately the one thing that is common about flat panel displays is that no two panels have the same connector pinout Even within one manufacturer s line almost every panel has a different connector and or pinout and the timing requirements are often different too Rastergraf has chosen a pinout derived from the NEC NL128102AC20 05 1280 x 1024 12 bit two pixel clock digital flat panel which has a convenient and representative pinout While Rastergraf has qualified a number of panel
186. r The RGBS561 has a two bit graphics cursor It contains a 64 x 64 x 2 bit map position match registers and counters triggered by the dot clock and referenced to horizontal and vertical sync By setting the correct internal control bits the RGB561 can supply a bit map cursor and or a cross hair cursor The display window for the cross hair is programmable The cursor coordinates are a function of the color map load clock which makes a transition every 4 pixel times and horizontal and vertical syncs which clear the cursor s X and Y position counters It then counts load pulses to position itself along the horizontal axis and counts horizontal sync pulses to determine vertical position The position match registers compare a programmed value corresponding to an X Y position on the screen to the counters When coincidence occurs the cursor output become active and select one of the three cursor colors Since the cursor clock is referenced to HSYNC and VSYNC you can derive the relative 0 0 position from the 34020 timing initialization table see Section 5 4 One complication of the hardware cursor is that interlaced displays confuse the cursor s vertical timing The result is that unless special measures are taken it is Zoomed vertically by a factor of two for interlace displays The RGB561 has an internal control bit which can be set for interlaced mode which then makes it work correctly 5 47 On board Devices and Memories Artisan
187. r 2 MB total EEPROMs Rastergraf has a program which is available upon request which can be used to load images into the EEPROMs under VxWorks and Solaris 2 17 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 5 4 Autoboot Enable all VCLs The VCL can start up from on board Flash on power up or anytime SYSRESET is asserted NOTE to avoid unpredictable board operation do not install this jumper unless autobooting EEPROMS are installed To enable autoboot operation install a jumper in the BOOT location of JP301 See Figure 2 3 for the VCL V or Figure 2 4 for the VCL M 2 5 5 Master Pixel Clock Oscillator Frequency all VCLs The VCL boards have a software programmable pixel clock contained in the IBM RGB561 RAMDAC which can be set up to 170 MHz Rastergraf distributes a number of standard initialization tables and can provide custom versions upon request Using a specially upgraded VCL the pixel clock can be in excess of 250 MHz 2 5 6 Force Overlay Jumper all VCLs Actually there is no FORCEOLAY jumper on the VCL M but you should still read this section Background You can configure the VCL display memory to have equal parts primary and overlay or to be all primary You might use the primary only case if you don t need overlay and you want as much primary memory as possible The effect of disabling overlay me
188. r 3 Data written to this register get written to DAC register 3 via the FIFO Base Address device space at offset 0xCO Table 5 23 FIFO Control Register FCRO Bit Assignments Bit Mnemonic 4 7 RSVD_ Readonly ReSerVeD Writing 1 or 0 causes FIFO 3 ORF 2 AFF 1 AEF 0 EF R W Name and Function reset Read undefined Read only Overrun Flag Writing 1 or 0 causes FIFO reset Normally reads 0 This bit will read 1 if the FIFO overruns Read only Almost Full Flag Set means Almost Full Writing 1 or 0 causes FIFO reset Read only Almost Empty Flag Set means Almost Empty Writing anything causes FIFO reset Read only Empty Flag Set means Empty Writing 5 57 On board Devices and Memories anything causes FIFO reset Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 5 24 FIFO Control Register FCR1 Bit Assignments Bit Mnemonic 4 7 3 RSVD ORFIE AFFIE AEFIE EFIE R W no yes yes yes yes Name and Function ReSerVeD Write 0 Read undefined Overrun Flag Interrupt Enable 0 interrupt disabled 1 interrupt enabled Almost Full Flag Interrupt Enable 0 interrupt disabled 1 interrupt enabled Almost Empty Flag Interrupt Enable 0 interrupt disabled 1 interrupt enabled Empty Flag Interrupt Enable 0 interrupt disabled 1 interrupt enabled Table 5 25 FIFO Control Register FCR2 Bit Assignment
189. r installed Table 2 3 Interrupt Grant Level Grant Level VS Jumper Number Default 2 1 0 1 0 0 1 2 0 1 0 3 0 l l yes 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 The VMEbus interrupt request priority is jumper programmable for the seven levels 1 7 The lower the priority number the less likely the board will be serviced The Interrupt Request Priority jumper block the left side of J1 VME P1 connector The pin layout is as follows Installing Your Rastergraf Display Board 2 6 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Caution The Vector Priority setting must match the Interrupt Request Priority setting Figure 2 2 Interrupt Priority Jumpers T 7 2 3 4 Installing the VCL V Graphics Board Review Section 2 5 Other Jumper Options for the VCL Series for other jumpers which you may need to change Use the following procedure to install the Rastergraf display board into the VMEbus backplane 1 Shut down the operating system and turn off the power Warning Never open the computer without turning off the power supply Unless internal AC wiring is exposed leave the power cord plugged in so as to ground the computer chassis You can easily get shocked ruin computer parts or both unless you turn off the power Even with power switched off lethal voltages can exist in the equipment 2 Open the computer and identify the empty slot i
190. r up and don t let the debugger boot the operating system Use the debugger to verify that board registers can now be read see below The Line Buffer cannot be read until the MEMON enable bit in the graphics board CSR is set Since we can t use the bottom of A16 space in a 167 or 187 it is also necessary to load the Line Buffer Address Register LBAR at FFFFC008 This is because the register comes up zero enter MM FFFFC000 W lt CR gt receive FFFFCO00 4000 enter 60 lt CR gt sets MEMON and CRTCON receive WARNING NO MATCH error because the 4000 bit is always set enter lt CR gt end the dialog enter MM FFFFC008 W lt CR gt receive FFFFC008 0000 enter 20 lt CR gt set line buffer address to FFFF8000 receive FFFFCOOA 0020 enter lt CR gt end the dialog enter MD FFFF8000 400 B lt CR gt dumps 1024 bytes starting at FFFF8000 receive a bunch of bytes enter MD FFFF8022 1 W lt CR gt dumps the 34020 HSTCTLH register receive FFFFC008 8010 this is the right value for a halted 34020 enter lt CR gt end the dialog You will get an error message which is not what you want if there is no response If indeed the board appears to be dead call Rastergraf for further assistance 6 6 Troubleshooting Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 6 5 General Procedures The VCL boards were designed with reliability and durability in mind Ne
191. rder may also require modified initialization tables 2 13 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 4 4 Connecting the Mouse Keyboard and Console If you are not using a keyboard or other I O device just skip on to Section 2 6 Checking your Display PS 2 Mouse and Keyboard Ports The PS 2 ports are available on a 9 pin MDSM micro D sub A breakout cable available from Rastergraf provides the PS 2 connectors Plug a PS 2 compatible mouse cable into the PS 2 connector round 6 pin DIN socket labeled PS 2 MOUSE Plug a PC AT compatible keyboard with a PS 2 style connector or adapter into the round DIN 6 pin socket labeled PC KBD RS 232 Serial Ports The RS 232 serial ports are available on a 15 pin MDSM micro D sub A breakout cable available from Rastergraf provides the 9 pin D sub connectors Plug an RS 232 serial mouse cable into the 9 pin DB 9 male connector labeled MOUSE You can also use a trackball in this port If you are using the PTERM terminal emulator plug the console cable from the computer into the 9 pin female connector labeled CONSOLE PTERM supports 9600 baud Jumpers control the data bits parity and RTS CTS and XON XOFF protocol See Section 2 7 The console port of your computer should match the VCL M settings If you have trouble refer to Chapter 6 or contact Rastergraf Instal
192. re shipped with CLP includes initialization demo programs 34020 downloader and 34020 utilities Most programs are supplied in source and executable and are written in C A list of the Graphics Subroutine Package library functions is shown on the following page 3 5 Software Summary Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 3 2 Graphics Subroutine Package Library Routines Note Routines may be listed in more than one category Array Conversion Routines fix_to_ float fix_to_long fix_to_short float_to_fix long to_fix short_to_ fix Board side Runtime Support strxfrm Color Palette Routines cmmr_ command cmmr_readmask cmmrblk cmmw_command cmmw_readmask cmmwblk hlsrd hlsrgb hlswrt rgbhls rgbrd rgbwrt wndwrd nw_ wndwrd wndwwrt nw_wndwwrt Configuration Information getframeinfo boardinfo videoinfo xferbuf_resize readjumpers setleds GetInfoValue get timeout set_timeout Device and Memory Access Routines peek peek_breg resr rlar rmem rregs size_mem wesr wlar wmem wregs poke poke_breg Double Precision Math Routines bessel erf erfc gamma hypot j0 j1 jn yO yl yn Font Management Routines download_font download _fontfile get_font max install_font nw_install font select_font nw_ select_font unload_font Graphics Attribute Routines get_patn_max get _pmask get_ppop get_psize get
193. rectly select up to four pixels ina VRAM for simultaneous writing from the VRAM color register Supplies CAS lines for display and system memory Different versions for VCL 24 and VCL 8 Theory of Operation 4 14 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf VCL20 MACH231 Supports Static Display feature for different primary and overlay starting addresses Also required for VCL 8 8M 4 15 Theory of Operation Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Figure 4 1 VCL V Block Diagram Theory of Operation 4 16 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com wel beig yolg A IOA s dnueju eo1neq Jaddems 4g pue slanlaosuell sng Jaysibay Zd BIA Mowe Mowe WOdas ysewew uog ea 19 s1 H Ke dsiq Wa shS AW Z L 9 peeds y IH sseJppy AW 9 2 aN zer SJ A ISULIL eur sng Rastergraf soyd siosunD SLM 40109 yoo 9 axid Wd sluvnd Odevces yae 8 Japooeq sselppy sueying ssoJppy pexedininyw Ndd dS9 10 e19U99 Buru L JOyeMQUY Wa shS OcOrE YVT1 HS9 Japooeq ssoJppy 4 17 Theory of Operation Guaranteed 888 88 SOURCE www artisantg com Artisan Technology Group Quality Instrumentation Rastergraf Figure 4 2 VCL M Block Diagram Theory of Operatio
194. roup Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf overlay moving primary or moving overlay static primary can be supported Although not currently supported in Rastergraf software the VCL can provide binary vertical zoom 1 2 4 8 16 32 and smooth horizontal zoom The VCL display memory data is directed to the monitor via an IBM RGBS561 RAMDAC color map control chip which provides a programmable 30 bit wide color map 10 bits each red green and blue The pixel is used as an index into the lookup table giving 256 colors out of a palette of 16 7 Million 2 24 The 24 bit VCL has a full 16 7 million color selection A two bit cursor with a 64 x 64 x 2 bit map function is also included on chip Additional color map entries are provided for the 8 bit overlay screen and 2 bit cursors The analog output DACs are 10 bits per pixel Additional gamma correction lookup tables can be enabled to compensate for monitor characteristics The analog Red Green and Blue signals from the RAMDAC are connected to a standard composite or VGA type analog monitor The RGB561 also contains digital outputs which can be used to drive LCD plasma or EL flat panel displays Depending on how the VCL V is configured 1 4 or 8 bit monochrome or 8 9 12 18 or 24 bit color can be supported In all cases the MSBs of the internal lookup tables are used The VCL V 8 bit pixel and 24 bit pixel VCL drive the
195. roup Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf programs exist which process keyboard and mouse inputs on the serial ports but no intelligent keyboard or mouse software is available That is why we have PX Windows Rastergraf can supply cables and devices please contact the factory for ordering information In the following subsections Port refers to the way Rastergraf software identifies the ports VCL V RS 232 Connectors There are two DB 9 RS 232 connectors used on the VCL V The connectors are mounted to the front panel of the VCL V Front Panel Name Section Connector Description CONSOLE XT Console PTERM DB 9 female MOUSE 2 7 2 Serial Mouse and LK401 DB 9 male VCL M RS 232 Connectors The VCL M front panel connection for the RS 232 is a 15 pin MDSM micro D sub connector See Section 2 7 3 for the connection details A separate cable is required to breakout the RS 232 ports to the Rastergraf standard DB9 connectors Breakout Cable Name Section Connector Description CONSOLE 21 4 Console PTERM DB 9 female MOUSE Pang fe Serial Mouse and LK401 DB 9 male 2 25 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 7 1 Console Connector and Jumper Options The console port uses a female DB9 connector It can be used with the optional PTERM and SmartPTERM firm
196. rtisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf To change the vertical position To shift the image up subtract an equal amount from VEBLNK and VSBLNK VEBLNK must be larger than VESYNC To shift the image down add an equal amount to VEBLNK and VSBLNK VSBLNK must be less than VTOTAL To change the number of lines To display fewer lines make the difference between VEBLNK and VSBLNK smaller To display more lines make the difference between VEBLNK and VSBLNK larger VEBLNK must be larger than VESYNC VSBLNK must be less than VTOTAL To change the height of the image There are 2 ways to change the height vertical size of the image 1 Display more lines The aspect ratio remains the same 2 Change the vertical frequency Increasing the vertical frequency will result in a shorter image decreasing it will result in a taller image Declaration Rastergraf is dedicated to making your application work We can assist in creating special initialization tables for specific monitors and other output devices If you need help it would be very useful if you can gather the data requested in the following form before calling us 5 37 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Request for Timing Table Submit to Rastergraf Corporation 1804 P SE First Street Re
197. rumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 4 2 VCL V System Design The following discussion assumes a working knowledge of the VMEbus For detailed information concerning operation of the VMEbus please refer to the Section I 3 Additional References VMEbus Interface Rather than use a commercial VMEbus interface controller such as the VIC064 or the SCV64 Rastergraf uses a proprietary chip set which is tailored to the interface requirements of the 34020 Implemented in 3 high density AMD MACH FPGA devices the chip set includes control signals for the VMEbus bus drivers address decoders for the VMEbus Control Status Register CSR Line Address Register LAR Line Buffer Address Register DBRADR Extended Address Register XAR Interrupt Vector Address Register IVAR an interrupt controller VMEbus 34020 arbitrator and a byte swapper see Section 5 5 5 The VMEbus is an asynchronous bus consisting of 32 bit bidirectional address and data busses a 6 bit address modifier code and 5 primary control lines The VCL has two devices connected to the VMEbus a bus address register BAR and 32 bit bidirectional data transceiver The BAR is actually part of a MACH231 which latches the address bits provides A16 A24 and A32 address decode ranges and block transfers as determined by the CSR programmable address decoder registers System Arbitration One of the most important pieces of logic on the
198. ruply buffered to minimize the possibility of data overrun The DUARTs contain one programmable timer counter and the QUART has two Ordinarily one port is for a serial mouse and one port is for the console PTERM RTS CTS for the console port is also included Two ports are not assigned An Intel 8242PC controller supports 2 standard PC PS 2 ports They can be used for PS 2 compatible mice and keyboards PTERM and PX Windows software support available Connection is made via a mini DIN PS 2 connectors or on the VCL M via a micro D SUB All voltages supplied to the serial and digital connectors are protected either by current limiting resistors or resettable fuses The fuse is actually a Positive Temperature Coefficient PTC resistor It resets automatically when the overload is removed Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 1 4 1 Specifications for the VCL V VCL V VMEbus Access VMEbus Interrupts Bus Loading Data Strobe to DTACK 34020 arbitrated accesses Analog Video Connections All VCL V on board registers are accessible to the VMEbus through a 1 KB Line Buffer in A16 I O space using the 16 bit Line Address Register LAR Best performance results if the VMEbus address space supports D32 transfers The Line Buffer may be located in A24 space if the host CPU only supports A16 D16 Contact Rastergraf if you need to use this mode
199. s Bit Mnemonic 4 7 3 2 1 0 RSVD RSVD FIOREN FDM1 FDMO R W no yes yes yes yes Name and Function ReSerVeD Write 0 Read undefined This R W bit is reserved Write 0 only Assume read undefined FIOR ENable Must be set to access FIOR It may not be set when the FIFO is active EF 0 and MODEO 1 or MODE 1 FIFO Dump Mode 1 Along with FDMO controls DAC update mode as per Operation Mode Table FDM1 FDM0 MODE DAC FIFO Function 0 0 N DAC is not updated 0 1 B DAC is updated during blanking analog mode 1 0 D DAC is updated during blanking digital mode 1 1 A DAC is updated always FIFO Dump Mode 0 Along with FDM1 controls DAC update mode as per Operation Mode Table See MODE notes on next page On board Devices and Memories 5 58 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf DAC FIFO Loading Mode Notes When Mode is N the FIFO can be loaded but the DAC will not be updated until the MODE is changed The FIFO can also be flushed by writing FCRO When Mode is B the DAC is updated during blanking This gets rid of the sparkle problem This is the suggested mode for analog output When Mode is D the DAC is updated when the digital output is tristated during blanking This mode is required when digital output is enabled When Mode is A the DAC is updated as fast as possible regardless
200. s however the swapper works correctly for D8 and D16 accesses as well UATs also work but are not recommended because they may not give the results that you expect In particular a string of bytes written to the board using UATs will end up non contiguous mode write data on board none ABCD ABCD byte ABCD BADC word ABCD CDAB both ABCD DCBA 5 5 5d The VCL M and Byte Swapping Since the PCI bus is little endian it is not really necessary to include a hardware byte swapper for the VCL M However since the CPUs are generally big endian Rastergraf is evaluating whether it is desirable to provide this function on future revisions of the VCL M 5 5 6 Virtual Memory Page Faults and Autoincrement Registers When copying data into host memory from the color map auto incrementing registers color palettes one must be careful about page faulting on a virtual memory machine Before reading the color map you should touch the variable s you are copying into to ensure that they are in CPU memory If you don t do this you may get a page fault which would force a retry of the instruction Since the color map has already been read when the page fault occurs you will end up reading the color palette too many times 5 5 7 34020 Memory and Device Addresses This section covers the 34020 address equivalents for the board on board memory and devices The 34020 address is a bit address not a byte address In the case of 34020 internal registers
201. s it is impossible to do them all Therefore in order to aid you the user Rastergraf can take on loan from your company a panel of the sort you wish to use We can qualify it and develop the timing initialization table for it Be sure to obtain a complete data sheet from the manufacturer before attempting to use the panel If you want Rastergraf to help you determine compatibility we will need a copy of the data sheet Digital Panels and Bits Pixel Support Please note that although we follow the NEC pinout it does not follow that we do not support 18 or 24 bit panels At this stage of development in the flat panels 640 x 480 panels go up to 24 bits pixel and one pixel is clocked into the panel at a time With 1024 x 768 and 1280 x 1024 panels the practice is to clock two 12 bit pixels in at a time VCL Digital Panel Connector Part Numbers The connector used for the digital video connector is a 68 pin mini D ribbon connector The board side connector is a 3M N10268 52E2VC or Harting 60110685140 The cable side connector is a 3M 10168 6000EC Harting 60130685200 or Fujitsu FCN247RO68G E Connectors for the Panel side are summarized at the end of this section 2 41 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Cable Assembly Notes Since the 68 pin connector uses a 050 pitch interface the connector and cable do requ
202. s and Memories R only R W R W ZRP ZR ER port Clear for one 24 bit pixel clock mode Digital Clock Polarity Set for Digital output data to be valid on the rising edge of the Digital Output Clock Clear for data to be valid on the falling edge When the Genlock option is installed this bit enables Genlock when set 34020 DPYCTL register must be programmed first Reads 0 when video blanking is asserted Bits are programmed in units of 1 VCLK Note 34020 horizontal timing parameters are in terms of VCLK PVCLK2 PVCLK1 pixels VCLK 1 don t care 4 0 1 8 0 0 16 Vertical Composite Mode for J3 pin 14 clear vertical sync set composite syne Vertical Composite Sync Polarity for J3 pin 14 clear active low set active high Horizontal Sync Polarity for J3 pin 13 clear active low set active high For a 5 wire VGA cable set the sync polarities so the monitor can select the right line mode GPCR Bit 480 lines 400 lines 350 lines HSPOL clear set clear VSCSPOL clear clear set VCMODE clear clear clear High if ICS1562 chip is installed Connected to the HOLD line if a 1562 is used Reads high for VCL 24 Connected to the DATA line if a 1562 is used Reads back 0 ONLY if it is a VCL Connected to the CLK line if a 1562 is used Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 5 8 RGB561 Color Map Cursors and Pixel Clock Note T
203. s convenient because the DUART drives the 34020 device interrupt pin directly Care must be taken when accessing these bits as they clear on read The keyboard and mouse connections are via mini DIN PS 2 style connectors Bidirectional clock and data lines communicate with an intelligent keyboard scan controller Both chips must arbitrate and re send if there is a collision on the clock data lines 5 11 VCL V High Speed Data Port HSP The HSP is a 32 bit input port connected to the VMEbus P2 which allows the 34020 to transfer data from User Equipment UE into on board memory The HSP is available only by special order and its use must be qualified by the factory to ensure that the application is appropriate for the HSP hardware and software design The Graphics Subroutine Package CLP includes subroutines to support the HSP functions Refer to the CLP manual for detailed information Section 2 5 3 has the connector pinout listing and suggests some appropriate bus receiver types A two port memory located in the UE will store the image In the case of the VCL V 8 DATA_00H DATA_31H carry four bytes of pixel data where pixel 0 the leftmost pixel on the display is carried on DATA_00H DATA_07H DATA_00H is the LSB In the VCL V 24 DATA_00H DATA_31H carry one pixel Four additional control signals are defined all low active outputs VSL HSL and REL and input PRDYL Under control of the 34020 a line of data is written into the
204. scendental functions absolute values square roots negate etc performed to 32 bit 64 bit or 80 bit precision Typical instructions sequences also include copying data between the 34020 and the FPU accessing memory and executing internal instuction microcode See Section 1 2 for a complete description of the functions of the FPU 5 5 2 Writemask Register The 34020 writemask register is a 32 bit read write register located in the TI register buffer LAR 0 It is used to enable any or all of the bit planes in graphics memory VRAM This memory has a write per bit feature which allows bit planes to be selectively write enabled The complement of the bits to be write enabled is loaded into this register i e On board Devices and Memories 5 18 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf bit set write disabled The writemask register has no effect on system memory The 34020 actually maintains a writemask register internally which is intended to be passed to VRAMs which support a persistent writemask function It depends on a special function of the VRAMs which involves passing the contents of the 34020 writemask register into the VRAMs where the data is stored until changed by the 34020 Since regular VRAM s only hold the writemask data for the current cycle the standard 34020 writemask function won t work Therefore the VCL has an auxiliary writem
205. stalled on the VCL board Two pairs of jumpers set the memory sizes The video memory size is in pages where one page 1024 x 1024 pixels The jumpers are part of jumper strip JP301 see Figure 2 5 below Note that for both the DRAM and VRAM tables 0 Jumper Installed Figure 2 5 VCL V DRAM and VRAM Size Jumpers 10 Pin Resistor Pack OLAY Installing Your Rastergraf Display Board 2 16 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 5 2 Flash EEPROM for the VCL V The VCL V requires four 32 pin PLCC Flash EEPROMS Acceptable devices include AM28F020 150JC for 1 MB total and AM29F040 150JC for 2 MB total Access time must be less than 150nS Install a jumper between pins 1 and 2 of JP402 see Figure 2 3 when using the AM29F040 parts Rastergraf has a program which is available upon request which can be used to load images into the EEPROMs under VxWorks and Solaris 28F 020 Program Voltage Enable In order to program the 28F020 EEPROMs ONLY a jumper to enable 12 Volts must be installed between pins 2 and 3 of JP402 see Figure 2 3 Caution 1 Remove the jumper once you are done programming 2 DO NOT INSTALL JUMPER WHEN PROGRAMMING 29F040 2 5 3 Flash EEPROM for the VCL M The VCL M Flash is soldered onto the board and is therefore not field changeable The Flash EEPROMS are either 2 Mbit AM28F400 for 1 MB total or 4 Mbit AM29F800 fo
206. sters 5 2 1 VME Control Status Register The control registers and I O window lie in a region of the VMEbus address space reserved for peripheral devices and is usually to be found in A16 space The I O window can also be placed in A24 space Multiuser operating systems i e Unix do not automatically allow a user to access the VMEbus or physical memory All Rastergraf software including CLP and PX Windows include special mapping calls to give access to that part of the VMEbus where the board addresses are located The VMEbus interface is implemented as a 1024 byte byte addressable raster line buffer DBR and a 4 word CSR group 16 bit word long word boundaries VMEbus bits 0 15 in A16 space the DBR can also be in A24 space see Sections 5 2 1 and 5 2 4 For the sake of compatibility over numerous CPUs and OS s or as one might say the lowest common denominator A16 space is the most general and there is a minimal performance impact for using the line buffer Thus Rastergraf software supports A16 A24 space addressing only The standard addresses are shown in Section 2 4 1 For linear address access to the entire board it can also respond to a 64 MB byte addressable section of the 32 bit VMEbus memory map Contact Rastergraf for assistance in determining when it is appropriate to use A32 space High speed VMEbus block transfers are supported for accesses to the A24 and A32 64 MB block Using the 34020 s implied address mode this permi
207. t DUARTO OP4 ECS Serial EEPROM chip select The EEPROM is programmed using a four wire protocol The protocol for programming the EEPROM is delineated in the data sheet In general the method for accessing the EEPROM is to use OP2 to clock commands and data into or out of the EEPROM with data from the EEPROM being read in on IP6 or written into the EEPROM on OP2 OP4 is toggled during a write or erase cycle so that the EEPROM will put status on OP2 This is necessary because the EEPROM takes about 1 ms to write or erase data Programming on the VCL M QUART EEPROM Signal Name Mnemonic Description IOA3 SK Serial EEPROM clock IOB2 DI Serial EEPROM data input IOB3 DO Serial EEPROM data output IOA2 CS Serial EEPROM chip select The EEPROM is programmed using a four wire protocol which is delineated in the data sheet In general the method for accessing the EEPROM is to use IOA3 to clock commands and data into or out of the EEPROM with data from the EEPROM being read in on IOB3 or written into the EEPROM on IOB2 IOA2 is toggled during a write or erase cycle so that the EEPROM will put status on IOB2 This is necessary because the EEPROM takes about 1 ms to write or erase data On board Devices and Memories 5 66 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 6 Troubleshooting 6 1 Introduction This chapter contains information which should assist you in tracking down
208. t to power supply LQ10DX01 Name Description B12 Blue Pixel B bit 2 B11 Blue Pixel B bit 1 B10 Blue Pixel B bit 0 B01 Blue Pixel A bit 2 B01 Blue Pixel A bit 1 B00 Blue Pixel A bit 0 G12 Green Pixel B bit 2 G11 Green Pixel B bit 1 G10 Green Pixel B bit 0 G02 Green Pixel A bit 2 G01 Green Pixel A bit 1 G00 Green Pixel A bit 0 R12 Red Pixel B bit 2 R11 Red Pixel B bit 1 R10 Red Pixel B bit 0 R02 Red Pixel A bit 2 RO1 Red Pixel A bit 1 ROO Red Pixel A bit 0 GND Ground LQ10DX01 Name Description CK Pixel Clock HSYNC Horizontal Sync VSYNC Vertical Sync Vcc sequenced 5 Vdd sequenced 12 GND Ground no connect LQ10DX01 Name Description Vhigh Backlight 12 no connect Vlow Ground LQ10DX01 Pin CN1 21 20 19 18 17 16 14 13 12 11 10 9 NU RADAN l oo 15 LQ10DX01 Pin CN2 2 4 6 9 13 14 15 10 11 12 1 3 5 share 7 8 LQ10DX01 Pin CNA CNB 1 2 3 Note Sharp has a breakout kit for the LQ10DX01 part number is FPC LQ10DX01 Installing Your Rastergraf Display Board 2 48 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 2 30 Sharp LQ12D011 Connections VCL Signal LQ12D011 LQ12D011 Name Name Description Pin CN1 Pin CN1 38 BB3 B12 Blue Pixel B bit 2 30 5 BB2 B11 Blue Pixel B bit 1 29 40 BB1 B10 Blue Pixel B bit 0 28 42 BA3 B01 Blue Pixel A bit 2 26 9 BA2 B01 Blue Pixel A bit 1 25
209. tation The Rastergraf Display Subroutine Package CLP includes PC Mouse and PC Keyboard routines Sample programs exist which process keyboard and mouse inputs but no other keyboard or mouse software is available for CLP That is why we have PX Windows VCL V PS 2 Connectors Two 6 pin mini DIN connectors are used on the VCL V They are mounted on the front panel Front Panel Name Section Connector Description PS 2 MOUSE 2 8 1 mini DIN PC Mouse PC KBD 2 8 2 mini DIN PC Keyboard VCL M PS 2 Connectors Although there is a front panel connector on the VCL M for the PS 2 ports it is a9 pin MDSM micro D sub connector A separate cable is required to breakout the PS 2 ports to the standard mini DIN connectors Breakout Cable Connector Name Section Connector Description PS 2 MOUSE 2 8 1 mini DIN PC Mouse PC KBD 2 8 2 mini DIN PC Keyboard 2 31 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 8 1 PS 2 Mouse and Trackball If you buy a PS 2 Mouse or Trackball directly from Rastergraf it will come tested and prepared to work correctly with Rastergraf PX Windows A compatible mouse or trackball should be a 3 button Mouse Systems protocol 5 byte device A 2 button Microsoft Mouse protocol unit can be supported with a special command line option when starting the PX Windows server see the PX Windows User Manual Man Page
210. ter asccaiussavsessdeceseuviguariaesciamedenivsancaamas 5 16 Byte Word Longword Mapping ccccccceessecsseceeeceeeeeeseeceaeceeeneeeeneeeenneees 5 21 LAR 34020 Starting Address Table nnneneeseeesseseessenssesseseesseesseserssesse 5 24 VCL V Local Memory Manin scainiee coaanen aoe aaa uosae 5 27 VCL M Local Memory Map ssc sicscsscndvncunstceacenentdeesnaanenGineensncetntdinecsuntentenses 5 28 34020 and VMEbus Register Offsets VCLLAR 400 eeeeeeeeeeeeee 5 29 34020 and PCI bus Register Offsets WCLLAR 400 eeeeeeeeeeeeeee 5 30 VCL Option DESC PION x avenuxssrzcseencasaddaseaucminessssussdsuuniessue a a eE 5 31 Summary of Initialization Tables ececcecsceceseceeeeeeeeeeeeceeeceeeeneeeesneee 5 32 Example Initialization Table 1280 x 1024 110 MHZ eee eeeeeeeseeeeees 5 33 General Purpose Control Register x sssccsssacisssusdestavertiss sasacesaoseaters taiatassausnus 5 43 RGB IG Ul registet S sestnscesucussessnesastesensisaenatincssilsisemeanunnsteuinadvumescesusmuisneeiiaes 5 50 RGBS561 VCL V 24 Color Map Input Conversion c ccccesteeeteeees 5 51 RGBS561 VCL x 8 Color Map Input Conversion cccccesseeesseeeteeees 5 52 Re gist r Summa Yo aiasav recess na R RER RA 5 57 FIFO Control Register FCRO Bit Assignments ssseseeeseeseeseseeseesseseees 5 57 FIFO Control Register FCR1 Bit Assignment ceceseeseeeeeeeeneeeeeees 5 58 FIFO Control Register FC
211. tergraf Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Conventions Used In This Manual The following list summarizes the conventions used throughout this manual Code fragments Commands or program names System prompts and commands Caution Warning Keyboard usage Code fragments file directory or path names and user computer dialogs in the manual are presented in the courier typeface Commands or the names of executable programs except those in code fragments are in bold Commands in code fragments are preceded by the system prompt a percentage sign the standard prompt in UNIX s C shell a dollar sign the OS 9 prompt or the hash mark the standard UNIX prompt for the Super User Note boxes contain information either specific to one or more platforms or interesting background information that is not essential to the installation Caution boxes warn you about actions that can cause damage to your computer or its software Warning boxes warn you about actions that can cause bodily or emotional harm lt CR gt stands for the key on your keyboard labeled RETURN or ENTER Introduction 4 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter I General Information 1 1 Introduction This chapter provides an overview of the VCL series 8 bit
212. the low data bits for D16 and D8 transfers Note that accessing the CSR group with D32 instead of D16 will result in bytes 0 and 1 undefined The MACH445 FPGA controls the state of the 74BCT16652s and the byte swapper when the VMEbus is master The 74BCT16652 output register which drives the VMEbus is edge triggered It is clocked at the end of a read cycle to hold data read from an on board device DTACK READ allows the 74BCT16652s to drive the VMEbus The 74BCT 16652 inputs which receive data from the VMEbus latch the data at the end of the write cycle The 34020 will read the data out of the transceivers later The 34020 will delay its response if a second write occurs before the 34020 has finished the first one VMEbus Interrupt Controller The on board interrupt controller supports an interrupt from the 34020 to the VMEbus host Interrupt level is jumper selectable The interrupt controller FPLA is a D08 RORA Release On Register Access interrupter It may be used with a D08 interrupt handler which is the most common interrupter type and includes CPUs that use the VIC068 chip If the board is not requesting an interrupt and it receives an IAKI it will drive IAKO As IAKI is internally synchronized it may take up to two 34020 clocks 50 ns to drive IAKO after receipt of IAKI IAKO is asynchronously reset immediately negated upon the negation of AS as required by the VME specification When the 34020 sets its HINT interrupt fla
213. this means that the smallest increment in the 34020 space is 10 hex The 34020 uses the concept of field size FE to control the amount of data which is transferred at one time this applies to memory and registers This parameter is set up with special 34020 instructions The field size for accessing 34020 internal registers should be 16 bits If it is 32 the register following the one meant to be accessed will also get changed this 5 23 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf is actually desirable with the timing registers Table 5 12 lists all of the board device registers in the 34020 address space To ease program development the 34020 system memory appears in two places in the 34020 memory map at the top and the bottom This is done because while the VMEbus LAR addressing can only access the 34020 memory at the top of 34020 address space it can in fact be desirable to have 34020 programs execute starting at 34020 address 0 Therefore the board address decoder permits system memory to appear in two places As long as you write relocatable position independent code you could even switch between the spaces dynamically If you have 1 MB system memory this means that the both the top and the bottom of the 34020 address spaces have the same 1 MB of memory However for larger system memory configurations this is not
214. tions Digital Video Connector Serial I O Connector 1 15 General Information Times were measured using an HP1650A logic analyzer at the PCI connector using 1000 test cycles The 34020 was halted The host CPU was a Digital 21066 Alpha AXPpci33 computer Using the on board 9060 s DMA controller running 32 bit block transfers we have measured an average 18 MB s write data tranfer rate across the PCI bus The 34020 was set for host bus block transfer mode and read prefetch disabled The 34020 is the limiting factor in the bus transfer speed and the theoretical maximum is 20 MB s The small size of the PMC board outline required the omission of several secondary features available in the VCL V These include TMS34082 Floating Point coprocessor genlock 24 bit true color version SIMM DRAM and High Speed Port for digital data input The digital output port is different as it uses LVDS instead of standard TTL format to reduce pin count The VCL M uses a 9 pin MDSM micro D Sub connector to supply Red Green with Composite Sync Blue and TTL level horizontal and vertical sync An adapter cable is required to allow connection to a VGA or BNC compatible monitor Digital video is encoded into LVDS Low Voltage Differential Signalling compatible data Each of the five LVDS differential pairs carries seven digital video TTL lines A separate pair carries the PLL clock for the LVDS system LVDS allows much longer data cables
215. tisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf 2 3 2 CSR Address Jumpers The address range for the CSR block is jumper selectable to certain addresses in A16 space As configured at the factory bits 4 5 14 15 are used in the address selection bits 0 3 are used in the register selection and bits 6 13 are hardwired low If required bits 6 13 can be some other pattern contact Rastergraf if you need this Remember that the base addresses for the Line Buffer Extended Address Block and Interrupt Vector are all software programmable Furthermore if you select the Alternate group 12 15 you will conflict with the standard Line Buffer address FFFFO000 FFFF03FF used by Rastergraf software for the Line Buffer Section 5 2 has complete information about programming these registers Refer also to Chapter 6 and note the comments concerning use of the Motorola MVME167 and MVME187 Figure 2 1 CSR Address and Interrupt Grant Level Jumpers 8 pin resistor pack A15 Al4 VS2 VSI VSO Address Selection VMEbus Hex default jumpers Standard xxxxC000 xxxxC00F A4 A5 installed Alternate 1 xxxxC0Q10 xxxxCO1F A5 installed Alternate 2 xxxxC020 xxxxC02F A4 installed Alternate 3 xxxxC030 xxxxC03F Alternate 4 7 xxxx80n0 xxxx80nF A14 A5 A4 Alternate 8 11 xxxx40n0 xxxx40nF A15 A5 A4 Alternate 12 15 xxxx00n0 xxxx00nF A14 A15 A5 A4 Note xxxx depends on host proc
216. tore and off screen display data It is expandable in steps of 4 16 and 32 MB A 72 pin SIMM is used A minimum of 4 MB is required for PX Windows Four 8 bit Flash EEPROMs support wait state firmware storage of up to 2 MB total of 32 bit wide permanent storage A user jumper allows any VCL to auto start from EEPROM A 4 Kbit 512 byte serial Electrically Eraseable Programmable Read Only Memory EEPROM programmed via DUART or QUART control lines supplies non volatile read mostly memory for an EPROM based application to retain some changeable data during power down The IBM RGBS561 lookup table LUT resolves the display priority between the primary overlay and cursor last through first respectively screens On the 8 bit VCL e g VCL V 8 both the primary and overlay word size is 32 bits and there is 1 byte per pixel On the 24 bit VCL e g VCL V 24 the word size and pixel size are both 32 bits Bits 0 7 are Red bits 8 15 are green bits 16 23 are blue and bits 24 31 are overlay Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Pixel Clock VCL 8 bit Display Memory VCL 24 bit Display Memory Writemask Register Static Display Scroll Pan and Zoom The RGB561 RAMDAC contains a programmable pixel clock generator This allows the pixel clock to be set to vitually any frequency between 5 and 170 MHz The upper range can be exte
217. ts up to 64 long words to be transferred over the VMEbus with only one address cycle See 4 2 for more information Hardware byte swapping is now included in the VCL V This can be used to advantage in transferring large blocks of data between the big endian VMEbus and the little endian VCL see Section 5 3 for more information Note When byte swapping is enabled the 1KB line buffer expands to 4KB and the 64 MB block expands to 256 MB 5 3 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf The CSR group consists of 4 registers Relative Register Section Offset Mnemonic Description Reference 0 CSR General Control 5 2 2 4 LAR Line Address Register 5 4 8 XARADR A32 Address Match Register 5 2 3 DBRADR A16 A24 Address Match Register 5 2 4 C VECADR Interrupt Vector Address Register 5 2 5 The XAR DBRADR and VECADR registers allow all VMEbus address areas to which the board responds to be programmable except for the CSR base address which is necessarily jumper selected from 16 different combinations see Section 2 2 1 Note CSR group registers should be accessed as words not long words because the high word will not read back useful data 5 2 2 Control Status Register Bits CSR Table 5 1 CSR Bit Summary Bit Mnemonic Function R W Reset 15 spare reads back 0 no no 14 REVFLAG reads back set no no 8 13 spare not used
218. upports 9600 baud Jumpers control the data bits parity and RTS CTS and XON XOFF protocol See Section 2 7 The console port of your computer should match the VCL M settings If you have trouble refer to Chapter 6 or contact Rastergraf 2 9 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Figure 2 3 Jumper Locations for the VCL V Sections 2 6 1 2 6 4 Section 34082 FPU amp 2 6 6 262 Flash Socket EEPROM optional JP301 JP402 Sockets A 9 N BOOT g j togar on B 3 qd k m 2 8 a E H I E Ea i ci z a 5 a lt soen i ONR Fa Fa 60 af H a Pe a Ea 5 Ps 7 c E gl H Section De q wn Bm B E 2 Cg cory j 2 8 1 ao qoca ies JP405 h Jo cag ee J3 fa Sections JP4o8 h PS E t o E S 2 3 2 amp
219. upt control The VCL M does not need to use mailboxes or doorbells because the TI34020 can not access the PLX9060 Refer to the PLX9060 data sheet for detailed information See Table 5 1 for the values loaded into the registers by Rastergraf s EEPROM On board Devices and Memories 5 10 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Local Address Space The Local Address Space maps to 1 of 3 spaces depending on the address remapping When the Local Address Space bits 31 30 are mapped to 0 0 default the Local Address Space range only needs to be 2K The first 1K will be the LAR 256 redundant 32 bit locations The second 1K will be the DBR Data Buffer Register This is a 1K window to any address on the TI34020 side of the VCL M Bits 0 15 of the LAR map to TI34020 bit address bits 13 28 equivalent to a byte address of bits 10 25 T134020 address bits 28 and 29 are tied together and bits 30 and 31 are tied high When the Local Address Space bits 31 30 are remapped to 0 1 the LAR is bypassed In this case the Local Address Space range could be any value from 128 bytes to 4 GB as the Local Address Space remapping register can be programmed to take the place of the LAR A 128MB window would be a good size for this window Finally when the Local Address Space bits 31 30 are remapped to 1 0 the Local Address Space is mapped to the PCI Configurati
220. ut 74ACT374 74ACT652 DATA_13 C7 active high VCL input 74ACT374 74ACT652 DATA _14 A8 active high VCL input T4ACT374 T4ACT652 DATA _ 15 C8 active high VCL input 74ACT374 74ACT652 DATA_16 A9 active high VCL input 74ACT374 74ACT652 DATA_17 C9 active high VCL input T4ACT374 T4ACT652 DATA 18 A10 active high VCL input 74ACT374 74ACT652 DATA_19 C10 active high VCL input 74ACT374 74ACT652 DATA _ 20 All active high VCL input T4ACT374 T4ACT652 DATA 21 Cll active high VCL input T4ACT374 T4ACT652 DATA _ 22 A12 active high VCL input 74ACT374 74ACT652 DATA _23 C12 active high VCL input T4ACT374 T4ACT652 DATA 24 A13 active high VCL input 74ACT374 74ACT652 DATA 25 C13 active high VCL input 74ACT374 74ACT652 DATA 26 Al4 active high VCL input T4ACT374 74ACT652 DATA_27 C14 active high VCL input 74ACT374 74ACT652 DATA 28 A15 active high VCL input 74ACT374 74ACT652 DATA 29 C15 active high VCL input 74ACT374 74ACT652 DATA 30 A16 active high VCL input 74ACT374 74ACT652 DATA 31 C16 active high VCL input 74ACT374 74ACT652 REL C25 active low VCL output 74F14 LS244 74ACT244 HSL C28 active low VCL output 74F14 LS244 74ACT244 VSL C27 active low VCL output 74F14 LS244 74ACT244 PRDYL C26 active low VCL input TALS 244 74F 14 LS244 GND A17 A25 A26 A27 C17 C18 C19 C20 C24 B2 B12 B22 B31 VCC B1 B13 B32 2 55 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com rt
221. ut is sync on green The horizontal frequency is controlled by HTOTAL The number of diagonal lines is an indication of how close you are fewer lines are closer more lines are farther Changing the horizontal frequency will also affect the vertical frequency Decrease the horizontal frequency by making HTOTAL larger This will generally result in a wider picture Increase the horizontal frequency by making HTOTAL smaller HTOTAL must be larger than HSBLNK HSERR must be smaller than HTOTAL Once the correct value of HTOTAL is found reduce or increase HSERR by the amount you change HTOTAL To change the horizontal position To shift the image left subtract an equal amount from HEBLNK and HSBLNK HEBLNK must be larger than HESYNC To shift the image right add an equal amount to HEBLNK and HSBLNK HSBLNK must be less than HTOTAL 5 35 On board Devices and Memories Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf To change the number of pixels To display less pixels make the difference between HEBLNK and HSBLNK smaller To display more pixels make the difference between HEBLNK and HSBLNK larger HEBLNK must be larger than HESYNC HSBLNK must be less than HTOTAL To change the width of the image There are 3 ways to change the width horizontal size of the image 1 Display more pixels The aspect ratio remains the same 2 Change the oscillator frequency You
222. uter respond to Rastergraf s graphics board addresses listed in Table 2 1 2 3 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 2 1 VMEbus graphics board addresses Standard Address Address Data Type Type Control Registers xxxxC000 xxxxC00F A16 D16 D32 Line Buffer xxxxy000 xxxxy3FF Al6 D8 D16 D32 Full Memory AQ000000 A3FFFFFF A32 D8 D16 D32 Interrupt Vector EO E D8 interrupter The xxxx is a placeholder for digits that are processor specific Some common values are shown in Table 2 2 Full memory settings are only used in multiple Rastergraf board configurations The y in the line buffer address is a placeholder for a digit which is processor specific These addresses are the defaults used by Rastergraf Only the Control Register address is set by jumpers on the graphics board The Line Buffer and Full Memory addresses and the Interrupt Vector are software configurable The table below gives you values for xxxx and y for some common CPUs Consult Chapter 6 for information on determining addresses of boards not shown in the table Table 2 2 CPU board addresses Processor Mfer Value of xxxx Valueofy Addressing Modes Force 68K FBFF 0 A16 Force SPARC FBFF 0 A16 D32 Heurikon 68K 0100 8 A16 Motorola 68K 88K FFFF 8 A16 Themis SPARC FFFF 0 A16 D32 Sun HP 0000 8 A16 Installing Your Rastergraf Display Board 2 4 Ar
223. utoincrements after each access Setting bit 7 of ADRHI disables the autoincrement Note ADRLO must be loaded first B 8 REGDBR Data buffer for control registers some of the WAT registers cursor pixmap and control F C PALET Data buffer for main and cursor color maps gamma tables the rest of the WAT registers and palette R or W Note When using the digital output mode access to the RGB561 must be restricted to vertical and horizontal blanking times On board Devices and Memories 5 50 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Figure 5 1 RGB561 VCL V 24 Display Memory Bit Assignments RGBS561 VCL V 24 True Color RAMDAC PLL pixel clock 3 color bit mapped cursor WT0 7 pixel 0 3 unused Video Outputs display data bits DO D23 gt Digital 24 3 OLO0 OL7 pixel 0 3 16 23 BO B7 pixel 0 3 B gt Blue 8 15 G0 G7 pixel 0 3 G gt Green 0 7 RO R7 pixel 0 3 R gt Red RGB561 latches 4 pixels at a time The following table and block diagram show what color value you get depending on the various inputs to the color map Table 5 20 RGB561 VCL V 24 Color Map Input Conversion Primary Cursor Overlay Input Value Input R G B Color Value 0 0 0 0 0 R G B palettes 0 0 a b c R G B palettes 0 0 FF FF FF R G B palettes 0 1 xx xx xx overlay palette entry
224. vertheless it may happen that a problem will occur This section is devoted to aiding the user in tracking down the problem efficiently and quickly You may be able to locate minor problems without technical assistance Before placing a service call try to solve the problem by following the directions given below in Table 6 2 If the problem can not be remedied Rastergraf can then issue a Return Material Authorization RMA so that the board can be returned to the factory for quick repair It can happen that installing a new board will overload the computer s power supply if the power supply margins are exceeded The first step in ascertaining if this is the problem is to calculate a power supply budget This involves adding up the power requirements of each board in the system to see if you are within specification Consult your computer s technical manual for information on how to correctly determine this A typical VCL will draw about 2 amps at 5 volts When attempting to verify that the power supply is working properly it is not unusual to unplug everything and measure the supply without a load While this practice is acceptable for linear supplies switching supplies which are very commonly used in computers require a certain load before proper regulation is achieved Typically at least 5 Amps must be drawn from the 5 volt supply before the 12 volt supplies will give the proper readings It can also happen that if you build your o
225. w artisantg com Rastergraf VCL Pin 33 34 67 31 64 66 62 63 68 30 32 65 This pin can be a no connect or connected to VCL signal Composite Blank Table 2 26 VCL Digital Video Connector J206 Signal Description Name Dual Pixel Name Single Pixel Name 03 Blue Pixel B bit 3 Blue Pixel bit 3 02 Blue Pixel B bit 2 Blue Pixel bit 2 01 Blue Pixel B bit 1 Blue Pixel bit 1 00 Blue Pixel B bit 0 Blue Pixel bit 0 15 Blue Pixel A bit 3 Blue Pixel bit 7 14 Blue Pixel A bit 2 Blue Pixel bit 6 13 Blue Pixel A bit 1 Blue Pixel bit 5 12 Blue Pixel A bit 0 Blue Pixel bit 4 07 Green Pixel B bit3 Green Pixel bit 3 06 Green Pixel B bit2 Green Pixel bit 2 05 Green Pixel B bit1 Green Pixel bit 1 04 Green Pixel B bitO Green Pixel bit 0 19 Green Pixel A bit3 Green Pixel bit 7 18 Green Pixel A bit2 Green Pixel bit 6 17 Green Pixel A bit 1 Green Pixel bit 5 16 Green Pixel A bitO0 Green Pixel bit 4 11 Red Pixel B bit 3 Red Pixel bit 3 10 Red Pixel B bit 2 Red Pixel bit 2 09 Red Pixel B bit 1 Red Pixel bit 1 08 Red Pixel B bit 0 Red Pixel bit 0 23 Red Pixel A bit 3 Red Pixel bit 7 22 Red Pixel A bit 2 Red Pixel bit 6 21 Red Pixel A bit 1 Red Pixel bit 5 20 Red Pixel A bit 0 Red Pixel bit 4 Signal Name Description den Composite Blank Hsync Horizontal Sync Vsync Vertical Sync CLK Pixel Clock 5 V sequenced 5 1A max 12 V sequenced 12 1A max not connected GND Ground 2 45 Installing Your Rastergraf Disp
226. ware see Section 2 5 7 The console s RTS and CTS pins may be re jumpered to support a fourth serial port Secondary Pointer PX Windows supports this port using the Xinput extension CLP supports it as just another serial port See Section 2 7 for information about limitations on current draw from the connectors Table 2 8 Console Connector Pinout D Sub Pin Number 1 4 6 2 3 5 7 8 9 Description TX or to means VCL is source not used TX Data to Console Port 2 RX Data from Console Port 2 Ground CTS from Console Port 2 or RX Data from Secondary Pointer Port 3 RTS to Console Port 2 or TX Data to Secondary Pointer Port 3 Optional 5 or 12 volts 5 A max Table 2 9 Jumpers for Console Port Port 2 and Port 3 VCL V Jumper JP404 1 2 JP404 2 3 JP403 1 2 JP403 1 3 JP410 1 2 only JP410 2 3 only Console Connector Pin Option Default pin 7 to Console Port 2 CTS yes pin 7 to Secondary Pointer Port 3 RX no pin 8 to Console Port 2 RTS yes pin 8 to Secondary Pointer Port 3 TX no pin 9 to fused 5A 12 volts no pin 9 to fused 5A 5 volts no Table 2 10 Jumpers for Console Port Port 2 and Port 3 VCL M Jumper JP303 2 4 JP303 4 6 JP303 1 3 JP303 3 5 Console Connector Pin Option Default pin 7 to Console Port 2 CTS yes pin 7 to Secondary Pointer Port 3 RX no pin 8 to Console Port 2 RTS yes pin 8 to Secondary Pointer Port 3 TX no Installing Your Rastergr
227. wever is not essential for the hardware or software installation If you want to perform the installation as quickly as possible start with Chapter 2 If you have problems installing the hardware refer to Chapter 6 for help Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Getting Help This installation manual gives specific steps to take to install your Rastergraf display board There are however variables specific to your computer configuration and monitor that this manual cannot address Normally the default values given in this manual will work If you have trouble installing or configuring your system first read Chapter 6 Troubleshooting If this information does not enable you to solve your problems do one of the following 1 call Rastergraf technical support at 541 923 5530 2 fax your questions to 5410 923 6475 3 or send E mail to support rastergraf com If your problem is monitor related Rastergraf technical support will need detailed information about your monitor Board Revisions This manual applies to the following board revision levels VCL V Fab Rev 2 3 VCL M Fab Rev 0 1 Introduction 2 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Notices Information contained in this manual is disclosed in confidence and may not be duplicated in full or in p
228. wn cables and you short 12 or 5 to ground on the connector you may trigger the auto resetting fuse which protect power supply pins when an overload occurs These fuses are actually PTC elements which reset automatically when an overload is removed You may also wish to refer to the following sections 2 2 2 3 Installation and Checkout 2 4 Jumper Changes 3 Software Summary 5 4 Initialization Tables 6 6 Maintenance Warranty and Service Troubleshooting 6 7 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 6 2 Curing General System Faults Control Panel dead No AC power Check power cord It may have been On Off switch unlit dislodged when installing board On Off Switch lit No DC power Check for correct 5 and 12 volts Cannot Boot Cable s dislodged During installation an unrelated cable can get dislodged Cannot read Rastergraf Improperly inserted Check insertion and position Take distribution media damaged or incorrect care that media is mounted media properly Unix distribution uses TAR format No message on Terminal disconnected Make sure cable between terminal console terminal or or not configured and computer is plugged into proper messages are garbled properly terminal port Put terminal into Local mode and verify operation System crashes or you Software not installed Check installation procedures See get a Trap message
229. y no overlay memory In this case you can have the 1600 x 1200 at no loss of performance or have double buffered primary only 1280 x 1024 In the case of DRAM there are two choices of DRAM size 16 MB and 32 MB Unless you are using 1600 x 1200 or have a lot of pixmaps 16 MB is usually sufficient All VCL M on board registers are accessible to the PCI bus through a PLX9060 PCI to Local Bus Bridge The 9060 provides programmable address and control registers which map the 9060 s PCI bus related registers and also the VCL M s CSR bits Line Address Register LAR and 1 KB Line Buffer functions A secondary address mapping supported by the 9060 gives a 64 MB window into board memory This feature is useful for applications which require direct full frame buffer access Note that Rastergraf standard software products do not use this feature The 9060 has two complete on chip DMA controllers They are capable of chain loading which means that scatter gather mapping can be supported Initial testing indicates that unless the transfer block is in excess of a few KB the CPU overhead doesn t make DMA worth the effort Both 9060 local DMA controller and the 34020 can cause an interrupt to the PCI bus One PCI 2 1 compatible load General Information 1 14 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Performance Omitted Features Analog Video Connec
230. y writes you can do before checking the flag and how much of the FIFO you can use Method 4 Combine method 2 and 3 Use the AEF to know you can write n number of words without checking between accesses then when the FIFO is almost full check AFF before each access Method 5 Program the FIFO and DUART1 to generate an interrupt on AFF In the interrupt routine wait for AFF to be clear then return This method lets you write the FIFO at full speed with no checks and also lets you use the entire FIFO These are just some examples of how the FIFO can be used There may be other ways to use the FIFO as well Use whatever method s that seem appropriate for your situation Accessing the FIFO DAC The DAC should be initialized before using the FIFO because the FIFO needs the video timing generator running to operate The DAC can be accessed in the usual way except it may not be accessed when the FIFO is running You can tell when the FIFO is running because EF will be clear The FIFO will not run when both FDM1 and FDM0 are clear RESET The FIFO should be reset before being used and before accessing the DAC Reset the FIFO by writing any value including 0 to FCRO The FIFO state after reset is the internal pointers are reset EOR 7 FOR 7 EF 1 AEF 1 and AFF 0 A reset also clears all FCRn R W bits On board Devices and Memories 5 54 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE
231. yout error the pin which is marked on the PCB with a square indicating pin 1 is on the wrong pin It is actually on pin 8 The pin list below shows the correct ITT Cannon pin numbers Just ignore the pin 1 square on the PCB Table 2 15 VCL M Serial Connector Pinout MDSM Pin Number Description TX or to means VCL is source 1 Ground 2 RX Data from Secondary Pointer Port 3 3 Ground 4 RX Data from Console Port 2 5 Ground 6 RX Data from LK401 Port 1 7 Ground 8 RX Data from Mouse Port 0 9 TX Data to Secondary Pointer Port 3 10 12 Volts via 220 ohm resistor 11 TX Data to Console Port 2 12 5 Volts via PTC fuse 5A max 13 TX Data to LK401 Port 1 14 12 Volts via 470 ohm resistor 15 TX Data to VCL Mouse Port 0 MSE 2 2 VCL M to DB9 Breakout Cable The MSE cable is the MDSM to dual DB9 Serial I O cable The MDSM end plugs into the VCL M and is retained with jackscrews The DB9 ends plugs into the computer side of a Serial Mouse etc The following table provides the wiring information 2 29 Installing Your Rastergraf Display Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rastergraf Table 2 16 MSE Cable Connections MDSM Name Console Pin or means jumper controlled DB9 Pin Number TX or to means VCL is source Number 1 3 Ground 5 2 Console CT

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