LAX016 User Guide
Contents
1. and select the right directory based on your operating system 2 Identification fail or work unstably with the device connected to the computer When the logic analyzer works at full speed there would be a lot of the current consumed maybe more than 500mA So if the USB port of the computer can not supply sufficient power the device could be identified incorrectly or work unstably To solve this the laptop users could try to switch to the USB port on the other side and the desktop users must use the USB port behind the tower box If the USB HUB is being used please connect the device USB port directly 3 Signal glitches appear on individual channels There are two cases when signal glitches appear the unused channels are floating or several signals with high speed are sampled simultaneously It is normal that the glitch appears on unused channels this is because the floating channel wire is like an antenna and it will transmit weak and alternating signal and this would result in glitches We could hide such channels or keep them and the signal channels at a longer distance And we should check the grounding of the logic analyzer and the system under test And for the glitches which appear when measuring multiple channels with high speed the reason for that has been explained in the section Multipoint grounding to increase accuracy and the method to handle this is multipoint grounding 25 2014 9 15 Jiankun Loginc2. oh Analyzer 0 Channel 0 1 item the channel to use 23 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org 9 User defined protocol analyzer Besides the standard protocol analyzers in the software the API functions provided by the software allow users develop their own analyzers The software API and user manual could be downloaded from the link below http www kingst org download fl JkiAnalyzerSDK zip 24 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org VI FAQs l Driver installation fail with the device connected to computer First JkiSuite should have been installed before connecting the device to computer If the software has not been installed the OS could not find the driver so the installation would fail And it would be a good idea to install the software without the hardware connected to the computer Second the device driver is installed automatically by installation program during installing process If the driver installation is blocked unintentionally during installation process or it 1s not installed correctly due to other reasons when you connect the device for the first time the driver installation would fail too In this case you can find the unknown hardware devices in the device manager click the right button to install the driver program again Please select manual installation The driver program is located in installation directory Drivers
3. 021875000000000 Ox0A 023958333333333 OxOB 026041666666667 0x0C 028125000000000 0xOD 030208333333333 Ox0E 032291666666667 OxOF 034375000000000 0x10 036458333333333 0x11 038541666666667 0x12 040625000000000 0x15 042708333333333 0x14 044791666666667 0x15 046875000000000 0x16 048958333333333 Ox1T oOoqoooqoncoooqocncoqcoeooqooooonooqooooococ oooocoocooceocjocococpocjocqoocooooo 8 PWM export There are two PWM waveform generators in the logic analyzer and they can generate square wave whose duty cycle could be adjusted By default PWM 1 is turned on and outputs 1 KHz square wave with 50 duty cycle while PWM2 is turned off and outputs low level As is shown in the figure below the PWM settings could be change through the menu button on the right side of PWM settings window In this dialog the PWM channel could be turned off through Enable box If it is turned on we could edit the frequency and duty cycle After the settings are complete just press the save button and the software will generate the PWM signal with the new configuration 17 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org W Enable Frequency 1 PWM2 Enable Frequency 1 kuz Duty cycle 18 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org V Settings for standard protocols 1 UARTY RS232 485 For stan
4. 15 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org T Analyze standard protocols If the signal to test conforms to standard protocols like UART I2C SPI which are supported by JkiSuite software the complete protocol list is in section Product technical specification besides displaying the waveform and some measurement data the software could analyze the data to get the specific data according to protocol specifications For example channels 0 3 are used for the standard 4 wire SPI signal You can press the button on the right side of the analyzers window and select SPI in the dialog Y PRAT ae DMx amp 312 2C 123 PCM Manchester 1 Wire Simple Parallel SPI UART RS232 485 Tea wrens In this dialog the actual parameter of SPI should be set Please check section Standard protocol set for more details When this is done the SPI analyzer would be added Then the software would analyze the data of channels 0 3 according to standard SPI timing specification and display the result on channel MOSI and channel MISO 305 608ms 305 609ms 305 61ms 305 611ms 305 612ms Sn SS Sn eo Sh E Eri errr r ghana eae fica eae ame raf Te oa I I I 0 MOSI U cae 1 MISO 2 CLOCK u HEE 3 ENABLE The data is displayed in hexadecimal by default If you want to change the format please press the button which looks like a circle in the analyzer bar and select the format requ
5. __ 2 Channel 2 5 fiers 3 Channel 3 5 ceca 3 Set trigger conditions In the example above the logic analyzer could sample signal of 640ms with 32M sample depth and 50M sample rate The trigger is not set by default and if we press start button the logic analyzer would start to sample It would stop automatically in 640ms and display the waveform in the screen But in real environment the signal may not be continuous and the user can not tell when it would occur such as UART communication In this way maybe we could not sample any effective data during the time since we pressed start To solve this problem we could utilize the trigger function First we set a certain condition and then when the signal meets the condition the data sample would start This is how trigger works and the conditions here are trigger conditions such as jump edge of the signal high low level or the combinations of them The trigger conditions should be set based on the characteristics of the signal to test for example in UART communication for the idle state in which no data are transferred the signal is high level and every UART data frame is started by the transfer from idle state to start bit which is low level so we should set the falling edge of this channel as the trigger condition If the channel 0 is used for UART signal we just need to press the falling edge button on the right side of channel 0 12 2014 9 15 J
6. Analyzer User Guide http www kingst org 4 The actual sample time is less than expected when the depth is set to a large value The logic analyzer is designed with a large sized memory to store the sample data temporarily And through compression algorithm the depth is further extended With this compression algorithm the current and last sample data would be compared if they are not the same a new sample data would be generated otherwise only the count for last state would be incremented and no new sample data would be generated And as a result of this if the signal is discontinuous for most communication system or change slowly the sample depth would be extended greatly However if the signal change rapidly the extension effect would not be so obvious This is why the sample time is less than expected when the sample depth is set above 100M all the depth items with and the signal changes rapidly oO Auto update of the software fails The software supports auto update when a new version is released a message would tell the user to update However because of system permission and security policy of the operating system the auto update could fail It this happens the user could download the software from our website and after uninstalling the software the user could install the new version http www kingst org download fl JkiSuiteSetup zip 26 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org VII
7. is complete a shortcut like would be created in the start menu and desktop and then the JkiSuite software could be accessed with this shortcut 2 Brief introduction to GUI Whe the software is started through start menu or desktop shortcut you will get a screen similar to the figure below It contains the tool bar channel settings bar waveform display window measurement window PWM settings window and analyzers settings window 6 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org Jiankun Virtual Instruments Suite cae x 0 Channel 0 Y Measurements 1 Channel 1 Width Period 2 Channel 2 Frequency D nee O FF 3 Channel 3 4 Channel 4 5 Channel 5 A Baka E __ _ vY PWM AWA Go aa CT PWM1 1 00K 50 PWM2 6 Channel 6 vg we Y Analyzers 8 Channel 8 A Geka eis g a P T Channel 7 9 Channel 9 A Geka 10 Channel 10 A Geka 11 Channel 11 A Geka 12 Channel 12 A Geka 13 Channel 13 A Gk 14 Channel14 E DEEN 15 Channel 15 A Geka The software could display in English faj 4k F X If you want to change the language you could press the Optios button in the top right corner and select the language The selection would become effective after the software is restarted Open Save Settings Save Data Y Measurements Export Data Width Period ae Preferences V English Restart to take effect Lan
8. tt tt th Ft H S H Ht Ht H Le ES 3 ENABLE Wh 1 00K 50 From the measurement window we can see the relative data of current waveform And all the measurement items could be turned on or off by pressing the circle on the right side of the measurement window Y Measurements Show Width Show Period Show Duty Cycle Width Period Duty cycle Frequency Byte Ti T T1 T2 Show Frequency Show Byte Show Timing Markers Show More Timing Markers Show Error tt tt tt te tt te tt FH Ae Ae ae Ae Te HH He He tt He tt tt H H After the measurement items required are set if you move the mouse to the waveform window the software would measure the relative data of the position where the cursor stays and display them in the measurement window 14 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org D Sas ee balba EEM v EEES 250MHz 7 PUSHER 128 0ms 305 6116ms 305 6117ms 305 6118ms 1 l l l i i l 1 l 1 1 i i 1 1 i i l 1 I I 1 1 0 MOSI 8 Bre 1 MISO 305 611772ms 305 611824ms 52 0ns 2 CLOCK 3 ENABLE A Geka For example if the cursor is located in the low pulse of channel 2 an arrow would appear in the high pulse next to this pulse And at the same time the relative measurement information would appear in the measurement window on the right side Pulse width which is 28ns refers to the low level pulse and the period is result of low level ne
9. wire remains low in idle state CPOL 1 the clock wire remains high in idle state 8 item the edge in which data is latched CPHA 0 data latched in last clock edge CPHA 1 data latched in next clock edge 9 item the active level of enable signal active low Enable line is Active Low or active high Enable line is Active High 4 CAN The setting dialog of CAN analyzer is shown below Analyzer 0 Channel 0 Bit Rate Bits 5 1000000 Cancel 1 item the channel to use d ae 2 item baud rate in communication 21 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org Please note that the signal from CAN bus 1s differential there are 3 ways to measure CAN signal 1 The GND channel of the logic analyzer is connected to the GND of the test system and 2 signal channels are connected to RXD and TXD pins of the level shift chip respectively 2 The GND channel of the logic analyzer is connected to the L end of CAN bus and 1 signal channel is connected to the H end of CAN bus 8 Connect the CAN bus to a module that transfer CAN to TTL and the GND and a signal channel of the logic analyzer are connected to the GND and signal export end of the system under test Most of the time all these 3 ways could be used to sample the signal but according to CAN specification the voltage between the H L ends is OV and 2V In complicated situations such as master with many slaves or long wi
10. 0 001087500000000 4 0x41 0x04 Read NAK 0 000140416666667 3 0x0C 0x0D 001267500000000 5 0x41 0x05 Read ACK 0 000148750000000 3 0x0D 0x0E 001322500000000 5 0x41 0x05 Read NAK 0 000157083333333 3 OxOE OxOF 001502500000000 6 0x41 0x06 Read ACK 0 000183750000000 4 0x10 0x11 001557500000000 6 0x41 0x06 Read NAK 0 000192083333333 4 0x11 0x12 001737500000000 7 0x41 0x07 Read ACK 0 000200416666667 4 0x12 0x13 001792500000000 7 0x41 0x07 Read NAK 0 000227083333333 5 0x14 0x15 001972500000000 8 0x41 0x08 Read ACK 0 000235416666667 5 0x15 0x16 002027500000000 8 0x41 0x08 Read NAK 0 000243750000000 5 0x16 0x17 002207500000000 9 0x41 0x09 Read ACK 0 000270416666667 6 0x18 0x19 002262500000000 9 0x41 0x09 Read NAK 0 000278750000000 6 0x19 Ox1A 002442500000000 10 0x41 OxOA Read ACH 0 000287083333333 6 OxlA Ox1B 002497500000000 10 0x41 0x0A Read NAH 0 000313750000000 7 Ox1C Ox1D 002677500000000 11 0x41 0x0B Read ACH 0 000322083333333 7 Ox1D Ox1E 000330416666667 7 Ox1E Ox1F EEM Time s Value Parity Err 001041666666667 0x00 003125000000000 0x01 005208333333333 0x02 007291666666667 0x03 009375000000000 0x04 011458333333333 0x05 013541666666667 0x06 015625000000000 0x07 017708333333333 0x08 019791666666667 0x09
11. Depth 10M 7 e 50MHz 7 ExpectedTime 200 0ms 0 Channel 0 e hol 1 Channel 1 z 2 Channel 2 3 Channel 3 4 Channel 4 5 Channel 5 6 Channel 6 T Channel 7 4 Get the waveform The sampling process is started by pressing the start button The logic analyzer samples the signal since then trigger conditions should be met if they are set and stops if it has got the sample points sample depth required It would upload the data to the computer The software would restore the waveform and maybe measures or analyzes the data later 13 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org 5 Check and measure the waveform After the sampling process is complete the waveform would be displayed in the screen T Sere Lo k Stes 32M v steers SOMHz v FtSERt A 640 0ms 300 0ms 1 L 1 0 MOSI eE Fiber a lt 1 MISO BS Piper oa Jali T2 t t 2 CLOCK 1 St Sh th th th te tt 1 Fk Th Tk t tH th He He He OH OH o 1 00K 50 From this figure we can see the coordinate values of the time axis are too large and the effective waveform is within a very short period You can click the left button of the mouse to zoom out the waveform while the right button would zoom it in And you can get these done with the mouse wheel too After the waveform is zoomed up you could s ce EEEE aere E rr FHRA 640 0ms 3 0us l 0 MOSI 1 MISO
12. Jiankun Loginc Analyzer User Guide http www kingst org LAX016 Series Logic Analyzer User Guide http www kingst org QQ 415942827 1 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org Contents Mi COV CE VICW a E E E EA E E E E 4 e Bere EION e E nee ENR 4 a PO E tet a E cereal bacaratictiacieteelbacataticdiatietedda bacatucddiacaeetdalbadatencencceecdaledates 4 Sy Technical specification cccccccccccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseeeeeeeeeeeeeeeeeeeeees 5 II Brief introduction to JkiSuite software eccccceccceccccccccccccccccccccceccccececeeee 6 1 How to install the software ccccccccccccccccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseseseseseess 6 Zs Brief introdaction to GUD essoseurasiunosurasiiynoii an 6 3 Brief introduction to the demo function ec ccccceceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 7 CLL Cne UNG CE VICE iepr AEE EEES 9 bs Connect The de ViCe 10 Pe arccdsincacadaieersndshntacadaveetidshndacadaseedidd thntacadeveededdsvetacadaveatectseeeds 9 Zs Connect device to system under CSL 2cccesczesscesentsenesentcasenentsonenenteacesentaenanentoaceeenteononest 9 3 Multipoint grounding to increase accuracy cccecceceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 10 iye Details OF OD ET AMOI sisne 11 L THEW AC Channel settings cccccccccccescscescsscscsssscescscsscsscscsssscescssssesstscessseeeeeseass 11 24 Sample depth and samp
13. Sns PWM frequency adjustment output Min interval for pulse width adjustment Output voltage Export impedance Power supply port USB2 0 3 0 USB2 0 3 0 USB2 0 3 0 power Standby current 130mA 150mA 300mA supply Maximum active current PC software 260mA 300mA 550mA UART RS 232 485 422 I2C SPI CAN DMX512 I2S PCM Manchester 1 Wire Simple Parallel UNI O Windows XP Vista Windows 7 8 32bit 64bit Supported protocols Supported OS 5 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org Il Brief introduction to JkiSuite software 1 How to install the software The software package is JkiSuiteSetup exe and it could be found in the attached CD or downloaded from the link http www kingst org download fl JkiSuiteSetup zip Double click JkiSuiteSetup exe to execute the installation program The procedure is similar with the common software in windows and there are instructions that you could follow in every step In the last step you should install the driver program of hardware device and you will see the dialog as the figure below there could be differences between different OSs Please select Install to complete the procedure a 71 Windows amp PEE MRS ZFR Jiankun BRST Saale IT BAe Xinyi Electronic Technology Shanghai C SSES Xinyi Electronic Technology AREN Shanghai C BIBRA SEENED LARNER MARE Be After the install procedure
14. a lt Address Display g bit read write bit included default 1 item the channel used for SDA signal data 2 item the channel used for SCL signal clock 3 item the way to display the address byte For I2C protocol every communication is started with addressing operation and this byte contains 1 bit read write flag and device address which is 7 bit wide And there are three options to display to display as a whole 8 bit read write bit included to display as a whole but the read write flag is O 8 bit read write bit set as 0 only display 7 bit address 7 bit address bits only 3 SPI The setting dialog of SPI analyzer is shown below 20 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org act Analyzer _2 Ea MOSI MISO CLOCK ENABLE Most Significant Bit First Standard 8 Bits per Transfer Standard Clock is Low when inactive CPOL 0 Data is Valid on Clock Leading Edge CPHA 0 Enable line is Active Low Standard 1 item the channel for MOSI signal master out slave in 2 item the channel for MISO signal master in slave out 3 item the channel for CLOCK signal clock 4 item the channel for ENABLE signal enable 5 item transmission mode of data bits MSB Most Significant Bit First or LSB Least Significant Bit First usually MSB 6 item data length for one transfer usually 8 or 16 bits 7 item idle state of the clock CPOL Q the clock
15. contact us Thanks for choosing our product if you have any questions please contact us in the following ways and we will serve you wholeheartedly Tel 13780615696 Web http www kingst org E mail 51kingst 163 com QQ 415942827 2 2014 9 15
16. d the signal below 1 5V would be low level logic 0 Thus we get a sample point and then we could link all these points logic 1 and logic 0 to get a waveform in which the user could see and analyze the timing of the signal logic errors and the relation between each other The figure below shows how the logic analyzer samples the signal Original Wave Reference Voltage Interval Sample TUT TTP TTITTTTT TET ITT TT TT TTT TTT TT Restore Wave 2 Product series This product series include LA1016 LA2016 LA5016 Jiankun LA5016 Logic Analyzer 2929288 TE B 200MHz 16 Channels E Input Voltage Range 50 4 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org 3 Technical specification Product type LA1016 LA2016 LAS016 500MHz 80MHz 6 25ns 512Mbits 32M channel 5G channel 200MHz 40MHz 12 5ns 1Gbits 50M channel 10G channel 100MHz 20MHz Total number of channels Max sample rate Measurement bandwidth Min pulse captured 20ns Hardware storage 1Gbits Input Hardware Sample depth 50M channel Max compression depth 10G channel Input voltage range 50V 50V Input impedance 220K 2 12pF Threshold voltage eer 1 6V high level 50V 50V 220K 2 12pF lt 0 8V low level 1 6V high level 50V 50V 220K 2 12pF lt 1 0V low level 2 0V high level Number of channels 2 2 2 Output frequency range 0 1 20MHz 0 1 20MHz 0 1 12 5MHz Min interval for 10ns 10ns
17. dard UART RS232 and RS485 they have the same timing definitions of the physical layer so they share the same analyzer and the figure below shows the setting dialog of UART RS232 485 analyzer E Analyzer a Bit Rate Bits S o600 E Use Autobaud 8 Bits per Transfer Standard 1 Stop Bit Standard No Parity Bit Standard Least Significant Bit Sent First Standard Non Inverted Standard SpecialMode None cancel 1 item select the channel to use I item set the baud rate and the baud rate here should match that in actual use item use the auto baud and the software could identify the baud rate automatically In case of the baud rate is unknown this option should be enabled But the accuracy of automatic identification depends on actual signal and the result could be incorrect ae item select the number of data bits and it is 8 most of the time s item select the number of stop bits and there are 3 options 1 1 5 and 2 6 item set the parity bit and there are 3 options no parity even parity and odd parity ie item set the bit order in data transfer and the options could be LSB Least Significant Bit Sent First and MSB Most Significant Bit Sent First 8 item invert the data or not Normally Inverted is only used for RS232 As For RS232 positive level is O and negative level is 1 and Non Inverted could used for UART and RS485 9 item set bit 9 as address
18. es the time accuracy of sample result Larger sample rate results in better accuracy The sample period represents the time accuracy of sample result The time one sampling process could last equals to sample depth sample rate Before sampling we could first estimate the signal to test about the maximum frequency the data required etc Then we could select the sample rate based on the maximum frequency and we might follow the following rule Sample rate should be 5 times more than the signal to test 11 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org and 10 times would be better However it is not a good idea to have a too large sample rate because with the same sample depth large sample rate means short sample time Therefore sample rate and sample time are two factors we should consider In real applications the parameters should be slightly more than the minimum requirement The settings of sample depth and sample rate are shown in the figure below Jiankun Virtual Instruments Suite Jiankun Virtual Instruments Suite SampleDepth TEEI SampleRate 500MHz Sera 10K 7 Seat SOOMHZ 7 SOOMHzigs 250MHz 125MHz 50MHz res OH 1 Channel 1 10MHz en f H 7 2 Channel 2 2MHz 1MHz 100KHz 0 Channel 0 3 Channel 3 a Jiankun Virtual Instruments Suite SampleDepth 32M 7 eA S0MHz 7 Simulate ExpectedTime 640 0ms 0 Channel 0 E gt __ 1 Channel 1 E
19. flag in multiple machine communication or not and by default None When this mode is actually used seldom used note that it is different with RS485 multiple machine communication it could be used for address byte flag Please note that if the signal under test is differential signal like RS485 and RS232 there are 3 ways to connect the wire 1 The GND channel of the logic analyzer is connected to the GND of the test system and 2 signal channels are connected to RXD and TXD pins of the level shift chip respectively 19 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org 2 The GND channel of the logic analyzer is connected to the GND of the test system and 1 signal channel is connected to the A end of the RS485 bus 8 Connect the RS485 bus to a module that transfer RS485 to TTL and the GND and a signal channel of the logic analyzer are connected to the GND and signal export end of the system under test Most of the time all these 3 ways could be used to sample the signal but according to RS485 specification the voltage which the AB ends could identify is between 0 2 6V In complicated situations such as master with many slaves or long wire the difference of the bus end could be too little and the logic analyzer could not identify the signal level correctly with method 2 So method 1 and method 3 are recommended if conditions permit 2 RC The setting dialog of I2C analyzer is shown below a Analyzer C
20. guage AX SRE Check For Update 3 Brief introduction to the demo function The software could provide demo function You can simulate the functions without the actual hardware and you could get a good experience of the software through this function With the example of SPI you could press the button on the right side of Analyzers In analyzers settings window the SPI analyzer would be added with default configurations Then you could set sample depth and sample rate and the sample time would be calculated automatically by the software After all these are done just press the Simulate button in the tool bar and you will get simulation waveform which is shown in the figure below 7 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org Jiankun Virtual Instruments Suite Options Sea 32M 7 rls cig 125MHz ExpectedTime 256 0ms 5 0us I i i 1 1 L 1 0 MOSI 1 MISO 2 CLOCK 3 ENABLE 4 Channel 4 CE 5 Channel 5 WM1 1 00K 50 6 Channel 6 Analyzers 7 Channel 7 E gt 1 O_o SS we 8 Channel 8 i gt i Ce a 9 Channel 9 I kom _ ON ee 10 Channel10 o CE 11 Channel 11 BA GEE pon bee ee EE sr nei 12 Channel12 Ea a ee ee 13 Channel 13 8 Geom a S a 2 om PO 14 Channel 14 B GEE ij 15 Channel 15 8 Geka SS ee es In the figure above channels 0 3 contain the simulated SPI signals and t
21. he signals in other channels are random You could zoom the waveform though the mouse and if you click the left button without releasing you could drag the waveform More details are covered in following chapters 8 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org III Connect the device 1 Connect the device to PC When the installation process is completed the logic analyzer can be connected to PC through the attached USB cable In case of desktop computer use the USB port behind the tower box Then the computer would report that new hardware has been found In Windows XP there would appear a driver installation dialog and just select to install automatically In Windows 7 8 a dialog would appear in the top right corner of the screen Then the install process would start automatically and we just need to wait for a while After the installation process is completed a new device called Jiankun Instrument Logic Analyzer would appear in Device Manager gt Universal Serial Bus 2 Connect device to system under test Please note that the logic analyzer and the computer share the same ground so the voltage between the GND of system under test and the CND of the computer should be zero Especially when the system is connected to the force electricity please make sure the isolation is made If devices with force electricity like frequency transformer are not isolated through the isolation transformer t
22. he system would be connected to the force electricity And if you connect the logic analyzer to such a system the logic analyzer even the computer would be broken And the damage could be beyond repair so the isolation should be made in advance When the logic analyzer is connected with the system under test you should first connect the GND channel to the system under test and then connect the signal channels There are 16 channels in the logic analyzer It means that up to 16 digital signals could be tested simultaneously If the number of existing signal is less than 16 the channels could be selected at will The channel numbers of the software correspond to that of the hardware device In addition when measuring the signal with high speed the measuring lines of logic analyzer should be near the signal of system under test The cable between the logic analyzer and the system under test should not be long because long cables would result in heavy inductive effect and signal reflection Therefore it is recommended that in debug stage of the system some pins should be reserved on the experiment board to make the best of measurement The connection between the logic analyzer and the system under test is shown in the figure below 9 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org 3 Multipoint grounding to increase accuracy when measuring multiple channels with high frequency signal the signal current from all channel
23. iankun Loginc Analyzer User Guide http www kingst org Jiankun Virtual Instruments Suite Sona am Mug SomHz E Start 0 MOSI 2 Clock After the trigger is set and the button start is pressed again if the trigger condition falling edge we have set have not appeared on channel O the logic analyzer would stay in wait state until the falling edge arrives Then the device will sample and save the data and upload the data to the computer for displaying and analyzing when the process is complete Except the edge and level trigger condition for single channel the logic analyzer also supports the condition combinations of multiple channels such as levels one edge and multiple levels The final condition is the logical AND of these conditions which means the sampling process starts when all conditions are met In this way the trigger can be the result of certain parallel data It could be used in the situation when the master device like MCU accesses the peripheral through the bus and we want to check the data write read operations of a certain address For example if we want to check the data operations of address 0x35 channels 0 7 should be connected to 8 address lines and the other channels are connected to the data lines After we set the level combination of channel 0 7 as the trigger condition the data in this address could be sampled The trigger settings are a Jiankun Virtual Instruments Suite Sample
24. ired in the menu 16 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org Edit Export Display in BINARY J DECIMAL ASCI The analyzed data could be exported as txt or csv through export menu and they could be used in other software If you want to change the configuration of SPI analyzer the menu edit could provide help X button on the left could remove the analyzer The figure below shows the exported data of UART I2C and SPI and we can see the result contains time value data packet number and the analyzed data J LUART H T 2o TICHI REET I soe SPTE RENT LHF ASE ERO SF SE ERO BBW RH TAA SAE TARO BBM BH Time s Packet ID Address Data Read Wij Time s Packet ID MOSI MISO 000092500000000 0 0x41 0x00 Read ACK 0 000010416666667 0 0x00 0x01 000147500000000 0 0x41 0x00 Read NAK 0 000018750000000 0 0x01 0x02 000327500000000 1 0x41 0x01 Read ACK 0 000027083333333 0 0x02 0x03 000382500000000 1 0x41 0x01 Read NAK 0 000053750000000 1 0x04 0x05 000562500000000 2 0x41 0x02 Read ACK 0 000062083333333 1 0x05 0x06 00061 7500000000 2 0x41 0x02 Read NAK 0 000070416666667 1 0x06 0x07 000797500000000 3 0x41 0x03 Read ACK 0 000097083333333 2 0x08 0x09 000852500000000 3 0x41 0x03 Read NAK 0 000105416666667 2 0x09 Ox0A 001032500000000 4 0x41 0x04 Read ACK 0 000113750000000 2 OxOA 0x
25. le Tale cisdccecessccsecsssdeccnenstonedsasdaesenstanededideesenseanedelidenecensensecens 11 P E EO o E E E E 12 AL Get the waveform eeesseseseeeeseeeeereeereeeeererererrrrrrrrrerererrerereererereeeeererrerereeerereeeeeeeees 13 Ox CHECK aNd measure th waveform caciccsusescrdsosazuddccdedcedcubedondsstosandensadehadueacczdsebedcadiae 14 0s Dalisave AE PON oper aceiae ceccatnratncrcaeceacauseatnenuiecencaasecesentaecencausesasentiecencatsecaseatiecare 15 Analyze standard protocols cccccccccccsssssssssessssseeccccesceeeeeeeaaeaeesesssssseeeeeeeeeeeeeeeaags 16 a VV NC acs erica acne cease omsecicn etal E 17 V Settings for standard protocols scsssssssssseseececccocccoocsssssesececececeeosssssssssssoe 19 ls UART RS232 4 5J orc teaace coset aeccdnenciedeta seas secegheedetnetaaieaaatantetagiaaceen sao dein eeauiennrbenteaneies 19 i aces oe acess cele sede sce cate te escape carded E sasdeaeopde cs deeecalledeesdevadancacacet 20 Oe GE E N A EEE A E E E E A 20 w A a A E E E E 21 e n E aaa E E 22 Ge TPN a E E E E E 23 ls DMX Sl enen a a a E E E E 23 Ca UNTO a E E E E E E E 23 9 User defined protocol analyzer eccccciccsicesicesivesicceicasiaesiealiccetialecenieeleccetcediaestwasnedeceasins 24 2 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org MMe PAO eats to viata cect E AEE E 25 l Driver installation fail with the device connected to computer cccccececeeeeees 25 2 Identification fail
26. or work unstably with the device connected to the computer 23 3 Signal glitches appear on individual channels ccccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 25 4 The actual sample time is less than expected when the depth is set to a large value 26 b Auto update of the software fails ccccccccccccccccceceeeceeeaeseseseeeeececeeeeeeeeeeaaeaeeeeeeses 26 yiia COMAC S a E 27 3 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org I Overview 1 Basic knowledge Logic analyzer is the instrument that collects and displays the digital signal from the devices under test It is mainly used for timing judgement an analysis Unlike the oscilloscope with many voltage grades It has only two grades Logic one and Logic zero After the reference voltage is set the logic analyzer could decide from the test signal that the signal above the reference voltage is logic one and the signal below is logic zero The digital waveform is formed with and 0 Compared with the oscilloscope when testing and measuring the digital systems like MCU ARM FPGA and DSP the logic analyzer could provide better accuracy much more data and more complicated measuring methods For example if you are sampling a signal with the logic analyzer the sample rate of which is 1Mhz and the reference voltage is set to 1 5V the logic analyzer would compare the current voltage with 1 5V The signal above 1 5V would be high level logic 1 an
27. re the difference of the bus end could be too little and the logic analyzer could not identify the signal level correctly with method 2 In addition the GND channel of method 2 need to be connected to the CAN L end but if other signals need to be tested at the same time the grounding could be confusing So method 1 and method 3 are recommended if conditions permit Oo Simple Parallel The setting dialog of simple parallel analyzer is shown below we Analyzer lo Channel 0 f Channel i gt 2 anneal 2 3 Channel3 4 Channel4 5 ChannelS 6 Channel6 7 Channel 7 Clock 8 Channels Data is valid on Clock rising edge 380 item the channel used for data bus 9 item the channel used for clock signal of data latch 10 item data latch on the rising edge Data is valid on Clock rising edge of clock signal or falling edge Data is valid on Clock falling edge 22 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org 6 1 Wire The setting dialog of 1 Wire analyzer is shown below ant Analyzer 0 Channel 0 Y 1 item the channel to use T DMX 512 The setting dialog of DMX 512 analyzer is shown below Analyzer Serial Channel oO F Accept DMX 1986 4us MAB C 1 item the channel to use 2 item accecpt DMX 1986 4us MAB signal or not 8 UNIO The setting dialog of UNI Oanalyzer is shown below
28. re 16 channels in the logic analyzer and not all these channels would be in real use Limited to the size of computer screen when more channels need to be displayed on the screen every channel looks even smaller and it is not convenient to watch After setting some parameters the software could display the channels required and hide other unused channels We can make it done in this way Press the down arrow on the right side of the channel label and select Hide or Show to hide or show the channel As shown in the figure below the settings could be used for this channel all channels above this channel and all channels below this channel 0 Channel 0 E e i Channel 1 E amp _ Hide this channel 3 Channel 3 Show all channels above me Move all channels below me 4 Channel 4 Reset 2 Channel 2 Options In addition current channel could be moved up and down through the Move menu Reset menu will restore the channels to default settings and labels and Options menu could hide or show the trigger button bar and channel label bar 2 Sample depth and sample rate Sample depth is the number of sample points It determines how much data the logic analyzer could sample at a time And it is apparent that the larger sample depth is the more data it could sample Sample rate the frequency to sample the signal is the number of sample point per second It determin
29. s would flow into the system under test through GND channel and the inductive effect of the wire in high frequency is strong so signal current of multiple channels would overlap on GND channel and as a result of that the instantaneous voltage difference would be too large to result in the glitch on the waveform under test To remove these glitches we could take the multipoint grounding method Normally the logic analyzer would provide several GND channels If we connect these channels to the grounding point of the system under test the signal current which we have mentioned would be divided into different path and the glitch could also be removed The multipoint grounding mainly includes Direct connection GND channel of the logic analyzer should be connected to the GND wire of the system under test directly the GND channels should be connected to different parts of the Dispersed connection system under test Multiple GND channels should not be connected to one grounding point of the system 10 2014 9 15 Jiankun Loginc Analyzer User Guide http www kingst org IV Details of operations After the software installation and device connection are complete we could sample the signal and analyze it In this chapter we will see how to use the logic analyzer step by step Some of these steps need to be configured only once and in future operations we could just skip them 1 R E Channel settings There a
30. xt high level which is 56ns The duty cycle is 50 and the frequency is 17 86MHz The byte is a 16 bit data which is the combination of value in channel 15 0 When we press the T1 and T2 in the measurement window a vertical green line which is called time marker would appear If we press T1 and put the marker on the rising edge of channel 1 then we press T2 and put the marker on the falling edge of channel 1 the time corresponding to T1 and T2 would appear on the right side and the absolute value of time difference between T1 and T2 would also be calculated In addition there is another time marker T3 which can be turned on through the options menu of measurement window and provide more information 6 Data save and export The data sampled could be saved into the hard disk of the computer for future check and comparison Data saving can be handled through the menu options gt save data on the top right corner of software interface You just need to specify the file path and file name to save If you need to check the data saved before just use the menu options gt open Open Save Settings Save Data Export Data Preferences Language d Check For Update About Instead of the sample data the menu save settings only saves the configuration data Export data could export sample data in the format of txt bin and csv and they could be used in other software like MATLAB Excel
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