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Getting Started with Altera`s DE2 Board

1. Figure 11 Select the megafunction and name the output file 3 In Figure 12 specify that the frequency of the inclockO input is 50 MHz Leave the other parameters as given by default Click Next to reach the window in Figure 13 MegaWizard Plug In Manager ALTPLL page 3 of 9 XxX Able to implement the requested PLL Jump to page for General Modes r General Which device family will you be using Cyclone Il k Which device speed grade will you be using sdram_pll What i the frequency of the inclockO input InclkD frequency 40 000 hHz Ee r Set up Phin iy GS made Operation kode Normal locked he Clk Ratio Ph dgoh DE C gt PLL type Peo i o oo 50 00 Which PLL type will wou be using pe od Al L 4 4 crt a Select the PLL type automatically gt Operation mode How will the PLL outputs be generated f Use the feedback path inside the PLL gs f n Normal Mode 6 ASauree Sunchkronow Compercaston Mode In Zero Delay Buffer Mode With no compensation Eo Greate an fbi input foran extemal feediac Which output clack will be compensated for Documentation Cancel lt Back Ment gt Finish Figure 12 Define the clock frequency MegaWizard Plug In Manager ALTPLL page 4 of 9 Able to implement the requested PLL Jump to page for Scan Lock sdram_pll Optional inputs inclkO frequency 50 000 hiHz Create an pllena input to selectively
2. SW7 SW0 LEDG7 LEDG0O SDRAM chip Figure 1 Example Nios II system implemented on the DE2 board The system realizes a trivial task Eight toggle switches on the DE2 board SW 7 0 are used to turn on or off the eight green LEDs LE DG7 0 The switches are connected to the Nios II system by means of a parallel I O interface configured to act as an input port The LEDs are driven by the signals from another parallel I O interface configured to act as an output port To achieve the desired operation the eight bit pattern corresponding to the state of the switches has to be sent to the output port to activate the LEDs This will be done by having the Nios II processor execute an application program Continuous operation is required such that as the switches are toggled the lights change accordingly The introductory tutorial showed how we can use the SOPC Builder to design the hardware needed to imple ment this task assuming that the application program which reads the state of the toggle switches and sets the green LEDs accordingly is loaded into a memory block in the FPGA chip In this tutorial we will explain how the SDRAM chip on the DE2 board can be included in the system in Figure 1 so that our application program can be run from the SDRAM rather than from the on chip memory Doing this tutorial the reader will learn about e Using the SOPC Builder to include an SDRAM interface for a Nios I based system e Timing issues wit
3. 1 Not Enough memory on your Mios I System bo contain the SREC File 2 The locations in your SREC file do not correspond to a memory device 3 You may need 4 PLL to access the SORAM or FLASH memory Using cable USB Blaster USB 0 device 1 instance 0x00 Processor is already paused Downloading 00000000 i 0 Downloaded 1KB in 0 05 verifying OOOOO000 i 0 verify Failed Figure 9 An error message 5 Using a Phase Locked Loop The clock skew depends on physical characteristics of the DE2 board For proper operation of the SDRAM chip it is necessary that its clock signal DRAM_CLK leads the Nios II system clock CLOCK_S0O by 3 nanoseconds This can be accomplished by using a phase locked loop PLL circuit There exists a Quartus II Megafunction called ALTPLL which can be used to generate the desired circuit The circuit can be created by using the Quartus II MegaWizard Plug In Manager as follows 1 Select Tools gt MegaWizard Plug In Manager This leads to the window in Figure 10 Choose the action Create a new custom megafunction variation and click Next MegaWizard Plug In Manager page 1 Ix The Megaizard Plug In Manager helps you create or modify design files that contain custom variations of megarunctions Which action do vou want to perform f Create a new custom megafunction variation C Edit an existing custom megafunction variation f Copy an existing custom megafunction variation Copyright
4. CASE eas 18 n Zeal ess th p 558 ne Sel fa Clock Setup Clock 5 Clock Hold Clock nnanannnnnnnnnnnnnnnnn NA NAA None iSelR None i 175 ne 300 irr MHz period 3 333 n NAA Areg 0 Zreg t za 16 Total number of failed paths j lg 469 n na 1300 03 MHz ii period 3 333 n ng 1 263 Oe MHz ii period 3 802r n s AddS ubR Overflow regl lE Timing Analyzer SEA Summary S Settings S Clock Settings Summary BEA Clock Setup Clock g5 Clock Hold Clack RD Messages Figure 9 The timing constraint cannot be met The specified fmax of 300 MHz cannot be achieved because one or more paths in the circuit have long propa gation delays To locate the most critical path highlight the Clock Setup entry in the table by clicking on it Then right click to get the pop up menu shown in Figure 10 Select Locate gt Locate in RIL Viewer which will cause the RTL Viewer to display the critical path as presented in Figure 11 Note that this path begins at flip flop AddSubR and ends at the Overflow flip flop SS Compilation Report Timing Analyzer Summary iS Compilation Report 4B Legal Notice EB Flow Summary EB Flow Settings SRE Flow Elapsed Time A Flow Log 0 Analysis amp Synthesis Sp Fitter H Tan Assembler ao Timing Analyzer ox Timing Analyzer Summary Me bte e feke i 1 Worst case teu Hone 4191 n AD a
5. Figure 29 The complete assignment The DE2 board has fixed pin assignments Having finished one design the user will want to use the same pin assignment for subsequent designs Going through the procedure described above becomes tedious if there are many pins used in the design A useful Quartus II feature allows the user to both export and import the pin assignments from a special file format rather than creating them manually using the Assignment Editor A simple 18 file format that can be used for this purpose is the comma separated value CSV format which is a common text file format that contains comma delimited values This file format is often used in conjunction with the Microsoft Excel spreadsheet program but the file can also be created by hand using any plain ASCII text editor The format for the file for our simple project is To Location xl PIN_N25 x2 PIN_N26 f PIN _AE22 By adding lines to the file any number of pin assignments can be created Such csv files can be imported into any design project If you created a pin assignment for a particular project you can export it for use in a different project To see how this is done open again the Assignment Editor to reach the window in Figure 29 Now select File gt Export which leads to the window in Figure 30 Here the file light csv is available for export Click on Export If you now look in the directory introtutorial you will see that the file light csv has been
6. Progress box in Figure 50 will indicate when the configuration and programming process is completed as shown in Figure 51 light cdf Ea Hardware Setup USB Blaster 056 0 Mode Active Serial Programming Progress sa AMAR Blight pot EPCS16 1C79348E O O Delete ie Change File Figure 51 The Programmer window upon completion of programming 8 Testing the Designed Circuit Having downloaded the configuration data into the FPGA device you can now test the implemented circuit Flip the RUN PROG switch to RUN position Try all four valuations of the input variables x and x2 by setting the corresponding states of the switches SW and SWo Verify that the circuit implements the truth table in Figure 12 If you want to make changes in the designed circuit first close the Programmer window Then make the desired changes in the Verilog design file compile the circuit and program the board as explained above Copyright 2005 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and
7. Total virtual ping 0 Total memory bits O 483 840 0 Embedded Multiplier 93 bit elements O 7O 02 Total PLLs Of4 028 Figure 3 The Compilation Report Compilation Report Timing Analyzer Summary 3 Compilation Report Timing Analyzer Summary aamen e betere fe SE Flow Settings 1 worst case tsu 4 548 ne B 14 Eregi 4 SE Flow Elapsed Time Worst case too Trol ne regie Z 8 E B Flow Log Worst case th 0 267 nz A O Areg O Clock Setup Clock 214 27 MHz period 4 667 ne AddSubR Overflow regi Total number of failed paths SE Settings BE Clock Settings Summary RES Clock Setup Clack SHEA tsu SHEA tco SEs th 4 i Messages Figure 4 The Timing Analyzer Summary fo Compilation Report SB Legal Notice Bg Flow Summary SE Flow Settings AddSubR Overflow regi SE Flow Elapsed Time 390 3 MHz ap 1343 ns SelA Overflow reg amp E Flow Log 250 88 MHz period 3 986 ne AddSubR Zreg 15 251 76 MHz period 3 972 ne regio Overflow reg 254 13 MHz period 3 935 ne AddSubR Zreg 4 257 47 MHz period 3 884 ne AddSubR Zreg 1 3 260 89 MHz period 3 833 ne AddSubR Zreg 2 264 41 MHz period 3 782 ne AddSubR Zreg 11 264 55 MHz period 3 780 ne regii 3 Overflow regQ 265 67 MHz period 3 764 ne regl Overflow reg 268 02 MHz period 3 731 ne AddSubR reg 10 271 74 MHz period 3 680 ne AddSubR reg 9 271 89 MH
8. Contents Example Circuit Library of Parameterized Modules Augmented Circuit with an LPM Results for the Augmented Design Practical designs often include commonly used circuit blocks such as adders subtractors multipliers decoders counters and shifters Altera provides efficient implementations of such blocks in the form of library modules that can be instantiated in Verilog designs The compiler may recognize that a standard function specified in Verilog code can be realized using a library module in which case it may automatically infer this module However many library modules provide functionality that is too complex to be recognized automatically by the compiler These modules have to be instantiated in the design explicitly by the user Quartus II software includes a library of parameterized modules LPM The modules are general in struc ture and they are tailored to a specific application by specifying the values of general parameters Doing this tutorial the reader will learn about e Library of parameterizes modules LPMs e Configuring an LPM for use in a circuit e Instantiating an LPM in a designed circuit The detailed examples in the tutorial were obtained using the Quartus II version 5 0 but other versions of the software can also be used 1 Example Circuit As an example we will use the adder subtractor circuit shown in Figure 1 It can add subtract and accu mulate n bit numbers using the 2 s complement
9. O p 40 0 n 30 0 n 1200 n 1600 n O ps Figure 40 The result of timing simulation 7 Programming and Configuring the FPGA Device The FPGA device must be programmed and configured to implement the designed circuit The required configura tion file is generated by the Quartus II Compiler s Assembler module Altera s DE2 board allows the configuration to be done in two different ways known as JTAG and AS modes The configuration data is transferred from the host computer which runs the Quartus II software to the board by means of a cable that connects a USB port on the host computer to the leftmost USB connector on the board To use this connection it is necessary to have the USB Blaster driver installed If this driver is not already installed consult the tutorial Getting Started with Altera s DE2 Board for information about installing the driver Before using the board make sure that the USB cable is properly connected and turn on the power supply switch on the board In the JTAG mode the configuration data is loaded directly into the FPGA device The acronym JTAG stands for Joint Test Action Group This group defined a simple way for testing digital circuits and loading data into them which became an IEEE standard If the FPGA is configured in this manner it will retain its configuration as long as the power remains turned on The configuration information is lost when the power is turned off The second possibility is to use
10. light sof EP2U35F 672 O02F 7666 FFFFFFFF oe Auto Detect ca Add File Figure 43 The Programmer window 26 Observe that the configuration file light sof is listed in the window in Figure 43 If the file is not already listed then click Add File and select it This is a binary file produced by the Compiler s Assembler module which contains the data needed to configure the FPGA device The extension sof stands for SRAM Object File Note also that the device selected 1s EP2C35F672 which is the FPGA device used on the DE2 board Click on the Program Configure check box as shown in Figure 45 Hardware Setup Hardware Settings JTAG Settings Select a programming hardware setup to use when programming devices This programming hardware setup applies only to the curent programmer window Currently selected hardware Available hardware items Hardware Sever Pot Add Hardware USB Blaster Local Feno Harare Figure 44 The Hardware Setup window light cdf E Hardware Setup U5B Blaster USB 0 Mode JTAG ad Progress yo ee ve Bak light sof EF2C35F6r2 O02F 76BE FFFFFFFF oe Auto Detect Delete cay Add File ie Change File Figure 45 The updated Programmer window Now press Start in the window in Figure 45 An LED on the board will light up when the configuration data has been downloaded successfully If you see an error reported by Quartus II software indicating that
11. 57 198 ns gt Painter 31 94ns_ Interval 25 26 ns Start End 40 0 ns 50 0 ns 60 0 ns 70 0 ns Overtow Boll 0 0 o oo sin lebo o o AddSubR BI i s D Areg Breg 5 OX 1850 Sa 0 reg Sfp a 1904 bg _ i DESEE SRR RRERo Be E Figure 22 An enlarged image of the simulated waveforms 15 In this discussion we have used the numbers obtained during our simulation run The user is likely to obtain somewhat different numbers depending on the version of Quartus II software that is used Copyright 2005 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending applications mask work rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any informa tion product or service descr
12. M Generate Signal Activity File File name fig itsa a signal Activity File Options E 4 Figure 38 Specifying the simulation mode Simulation Waveforms Masher Time Bar esta O ps 4 Pointer pEr 196 84 nz Interval at 196 84 nz Shark End l l l 1200s 160 0 ns Name a eee Figure 39 The result of functional simulation 6 1 2 Timing Simulation Having ascertained that the designed circuit is functionally correct we should now perform the timing simulation to see how it will behave when it is actually implemented in the chosen FPGA device Select ASsignments gt Settings gt Simulator to get to the window in Figure 38 choose Timing as the simulation mode and click OK Run the simulator which should produce the waveforms in Figure 40 Observe that there is a delay of about 6 ns in producing a change in the signal f from the time when the input signals x and x2 change their values This delay is due to the propagation delays in the logic element and the wires in the FPGA device You may also notice that a momentary change in the value of f from 1 to 0 and back to 1 occurs at about 106 ns point in the simulation This glitch is also due to the propagation delays in the FPGA device because changes in x and z2 may not arrive at exactly the same time at the logic element that generates f 23 Simulation Waveforms Master Time Bar O ps 4 Pointer B98 ps Interval B98 ps Start End
13. Quartus II software performs a timing analysis to determine the expected performance of the circuit It evaluates several parameters which are listed in the Timing Analyzer section of the Compilation Report Click on the small symbol next to Timing Analyzer to expand this section of the report and then click on the Timing Analyzer item Summary which displays the table in Figure 4 The last entry in the table shows that the maximum frequency for our circuit implemented on the specified chip is 214 27 MHz You may get a different value of fmax dependent on the specific version of Quartus II software that you are using To see the paths in the circuit that limit the fmax click on the Timing Analyzer item Clock Setup Clock in Figure 4 to obtain the display in Figure 5 This table shows that the critical path begins at the flip flop AddSubR and ends at the flip flop Overflow Compilation Report Flow Summary fo Compilation Report 48 Legal Notice ES Flow Summary Flow Status Successful Thu Sep 29 16 46 00 2005 Se Flow Settings Quartus Il Version 5 0 Build 168 06 22 2005 SP 1 SJ Full version SE Flow Elapsed Time Revision Name addersubtractor cS Flow Log Top level Entity Hame addersubtractor Analysis amp Synthesis Family Cyclone II I Fitter Device EP2C35r672C6 3 assembler Timing Models Preliminary Timing Analyzer Met timing requirements es Total logic elements Bzr 33 216 lt 1 72 Total registers 5 Total pins 63 475 11
14. a message corresponding to each error found will be displayed in the Messages window Double clicking on an error message will highlight the offending statement in the Verilog code in the Text Editor window Similarly the Compiler may display some warning messages Their details can be explored in the same way as in the case of error messages The user can obtain more information about a specific error or warning message by selecting the message and pressing the F1 function key To see the effect of an error open the file Jight v Remove the semicolon in the assign statement illustrating a typographical error that is easily made Compile the erroneous design file by clicking on the icon A pop up box will ask if the changes made to the light v file should be saved click Yes After trying to compile the circuit Quartus IT software will display a pop up box indicating that the compilation was not successful Acknowledge it by clicking OK The compilation report summary given in Figure 21 now confirms the failed result Expand the Analysis amp Synthesis part of the report and then select Messages to have the messages displayed as shown in Figure 22 Double click on the first error message Quartus II software responds by opening the light v file and highlighting the statement which is affected by the error as shown in Figure 23 Correct the error and recompile 14 the design 2B Legal Notice Flow Summary Flow Status Flow Failed Fri Jul 1
15. click on the Program Configure check box as shown in Figure 50 Quartus II x IN Some devices in current device list cannot be added to selected programming mode Active Serial Programming Do you want to clear all devices in current device list and switch to selected mode Yes No Figure 47 Clear the previously selected devices 21 ieni ga Hardware Setup 15B Blaster 056 0 Mode Active Serial Programming Progress O va e pe feon dd git Stop eg Auto Detect 1 Delete Gay Add File i Change File Get Save File GH Add Device Up Figure 48 The Programmer window with Active Serial Programming selected Select Programming File Look in E introtutorial E cb File name Jiight pot Files of type POF Files pof Cancel p Figure 49 Choose the configuration file ienie ga Hardware Setup USB Blaster 056 0 Mode Active Serial Programming Progress Oz pel Start CE File Device Checksum Usercode Faerie Vert Blar Examine al a gt Mee _ t Misie eu pof ia it Auto Detect Delete Ea Add File ie Change File Let Save File BaF Add Device Figure 50 The updated Programmer window Flip the RUN PROG switch on the DE2 board to the PROG position Press Start in the window in Figure 50 An LED on the board will light up when the configuration data has been downloaded successfully Also the 28
16. normally specify which button to press In the few cases when it is necessary to use the right mouse button it will be specified explicitly Quartus Il File Edit View Project Assignments Processing Tools Window Help Project Navigator Entity d Compilation Hierarchy QUARTUS II dp Hierarchy E Files d Design Units Version 5 0 Status http www altera com Estra Info Critical waming A Eror Message t Location r Locate For Help press F1 ih a Idle 5 essages x Figure 2 The main Quartus II display 5 Quartus II File Edit View Project Assignment O New Ctl n Open chl o Close Cirl F4 L New Project Wizard Open Project Ctrl Convert MAX PLUS II Project Save Project Close Project led Save Grits Gave As Save Current Report Section As Eile Properties Create Update Export Convert Programming Files Ri Page Setup E Print Preview ee Print Cri P Recent Files Recent Projects Exit Alt F4 Figure 3 An example of the File menu For some commands it is necessary to access two or more menus in sequence We use the convention Menu1 gt Menu2 gt Item to indicate that to select the desired command the user should first click the left mouse button on Menu1 then within this menu click on Menu2 and then within Menu2 click on Item For example File gt Exit uses the mouse to exit f
17. to destination pin F is 5 740 ns i Info Quartus II Timing Analyzer was successful 0 errors 0 wamings lt Processing Extra Info Info Waming A Criticalwaming A Eror Message 171 of 184 t a Location For Help press F1 l msa m Idle ix i ages Figure 21 Display after a successful compilation Compilation Report Compilation Report Analysis amp Synthesis Equations EB Legal Notice A1L2 is inst2 5 ES Flow Summary operation mode is normal BEE Flow Settings EE Flow Elapsed Time AlL2 x1 x2 B Flow Log 283 Analysis amp Synthesis EB Summary xl is xl gT Settings g Hierarchy mam gE Resource Utilization t amp ES Source Files Read operation mode is xl INPUT z g Resource Usage Sun x2 is x2 2 Optimization Results operation mode is input HD Messages ca i Fitter H E Assembler 0 Timing Analyzer x2 INPUT f is f operation mode is output f OUTPUT A1LZ Figure 22 Compilation report showing the synthesized equations 15 4 1 Errors Quartus IT software displays messages produced during compilation in the Messages window If the block diagram design file is correct one of the messages will state that the compilation was successful and that there are no errors If the Compiler does not report zero errors then there is at least one mistake in the sche
18. 4 Kbytes Figure 20 The Nios II Debug Client Settings window Nios II Debug Client n2client as oe Ba 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Figure 21 The Nios II Debug Client window 17 Look In I app software File Mame lights s Files of Type 4ssembly Language Source Files f s Figure 22 Open File dialog box Nios Il Debug Client n2client File Help Connect Using NIOS Il Debug Output Disassemble Memory Advanced Console Trace Debug 00000018 00000018 Registers __ Register ii RO zero R1 at R2 R3 R4 IRS R6 RT IRS RO R10 R11 R12 R13 R14 R15 R16 RIT R18 R19 R20 Value oooo0000 deadbeet 00801800 00801810 oo000000 deadbeet deadbeet deadbeet deadbeet deadbeet deadbeet deadbeet deadbeet deadbeet deadbeet deadbeet deadbeet deadbeet deadbeet deadbeet deadbeet Interesting Memory Type Address Data Disassemble Controls Start Address for Symbol 00000000 Num Instructions Next Instruction OxO0000000 orhi R2 zero 0x80 NIOSII Controls Restart Single Step Display Memory Disconnect Run Disassemble Figure 23 Display of the downloaded program 18 The Nios II Debug Client allows a number of useful functions to be performed in a simp
19. Bridg Communication en JTAG UART i SPI 3 Wire Serial i UART RS 232 serial D16550 UART with 1 i DI2CM I2C Bus Interfe DI2CSB I2C Bus Inter iO DSPI Serial Periphera O H16550S UART CA i H8250 CAST Inc HO High Performance Git 4 Use Module Name Description Input Clock Base GI Awailshle Camnanente So 4 Done checking For updates Figure 5 The System Contents tab window 5 Next specify the processor as follows e On the left side of the window in Figure 5 select Avalon Components gt Nios II Processor Altera Corporation and click Add which leads to the window in Figure 6 I Altera Nios Il cpu_0 Nios IT Core Caches amp Tightly Coupled Memories JTAG Debug Module Custom Instructions Nios II e O Nios II s Nios II f RISC RIS RISC Nios II zhi 32 bit 32 bit Selector Guide Instruction Cache Instruction Cache Branch Prediction Branch Prediction Hardware Multiply Hardware Multiply F ystern 50 MHz Hardware Divide Hardware Divide Barrel Shifter Data Cache Dynamic Branch Prediction Performance at 50 MHz Up to 5 DMIPS Up to 26 DMIPS Up to 56 DMIPS Logic Usage 600 700 LEs 1200 1400 LEs 1400 1800 LEs Memory Usage Two M4Ks Two M4Ks cache Three M4Ks cache Select a Mios ll core Family Cyclone II Hardware Divide Figure 6 Create a Nios II processor e Choose Nios II e which is the simplest
20. Device Design Files Software Files Other Files AHDL Include File Block Symbol File Chain Description File Hexadecimal Intel Format File Memory Initialization File SignalT ap Il File Tel Script File Text File VYector Waveform File Figure 33 Choose to prepare a test vector file 2 The Waveform Editor window is depicted in Figure 34 Save the file under the name light vwf note that this changes the name in the displayed window Set the desired simulation to run from 0 to 200 ns by selecting Edit gt End Time and entering 200 ns in the dialog box that pops up Selecting View gt Fit in Window displays the entire simulation range of 0 to 200 ns in the window as shown in Figure 35 You may wish to resize the window to its maximum size light vwf ojx Master Time Bar 14 15ns f gt Pointer 1 0 ns Interval 13 15 ns Start End 14 15 ns Figure 34 The Waveform Editor window 21 light vwf Master Time Bar 14175ns lt gt Pointer 4 8 ns Interval 9 28 ns Start End 120 0 ns 160 0 ns 200 0 ns Name 14 15 ns secececocesscesoceseosoessoosecosesseesseoseesseossessesseesssssod Figure 35 The augmented Waveform Editor window 3 Next we want to include the input and output nodes of the circuit to be simulated Click Edit gt Insert Node or Bus to open the window in Figure 36 It is possible to type the name of a signal pin into the Name box but it is easier to cl
21. Figure 39 If your report window does not show the entire simulation time range click on the report window to select it and choose View gt Fit in Window Observe that the output f is as specified in the truth table of Figure 12 22 Settings light Category General Files User Libraries Device E Requirements amp Options E EDA Tool Settings Design Entry Synthesis Simulation Timing Analysis Board Level Formal verification Physical Synthesis a Le Conipilation Process Settings i Early Timing Estimate Analysis amp Synthesis Settings Fitter Settings Physical Synthesis Optimizations Timing Analyzer Design Assistant SignalTap Il Logic Analyzer SignalProbe Settings Simulator H PowerPlay Power Analyzer Settings Simulator Select options for simulation Note the availability of same options depends on the current device family Simulation mode arise Simulation input E Simulation period Run simulation until all vector stimuli are used C End simulation at ns Mv Automatically add pins to simulation output waveforms T Check outputs setup and hold time violation detection gt Glitch detection fi ns M Simulation coverage reporting M Overwrite simulation input file with simulation results Software Build Settings HardCopy Settings uPGore Transaction Model Fle Wane vy Signal activity output for power analysis
22. Functional Simulation Netlist A simulation run is started by Processing gt Start Simulation or by using the icon F At the end of the simulation Quartus II software indicates its successful completion and displays a Simulation Report illustrated in Figure 41 If your report window does not show the entire simulation time range click on the report window to select it and choose View gt Fit in Window Observe that the output f is as specified in the truth table of Figure 12 24 Settings light Category General Files User Libraries Device E Requirements amp Options E EDA Tool Settings Design Entry Synthesis Simulation Timing Analysis Board Level Formal verification Physical Synthesis a Le Conipilation Process Settings i Early Timing Estimate Analysis amp Synthesis Settings Fitter Settings Physical Synthesis Optimizations Timing Analyzer Design Assistant SignalTap Il Logic Analyzer SignalProbe Settings Simulator H PowerPlay Power Analyzer Settings Simulator Select options for simulation Note the availability of same options depends on the current device family Simulation mode arise Simulation input E Simulation period Run simulation until all vector stimuli are used C End simulation at ns Mv Automatically add pins to simulation output waveforms T Check outputs setup and hold time violation detection gt Glitch dete
23. GR ED GED G18 GE si Figure 20 The result of new simulation 3 2 Timing Simulation Having ascertained that the designed circuit is functionally correct we should now perform the timing simulation to see how well it performs in terms of speed Select Assignments gt Settings gt Simulator to get to the window in Figure 16 choose Timing as the simulation mode and click OK Run the simulator which should produce the waveforms in Figure 21 Observe that there are delays in loading the various registers as well as longer delays in producing valid signals on the output pins 14 Simulation Waveforms Master Time Bar Ae olons 4 Pointer 11 36 ns Interval 4 46 ns Start End 40 0 ns 50 0 ns 120 0 ns 160 0 ns 62 010 ns Pee ot ee Reset SS 2 Hi idssssss AddSub EERSISES py ELO i A Ai A Tadi Gl o Gris 0 anne 150 Aba A 0 4 120 ODO 4 S0000 i H 1404 Abs Ko 0 630 630 2 406 Overlow SelR oF TT Areg SENTEN a EE 0 Breg y SERIE 1850 EZE SUN EEN A000 4 30000 0 reg RE ED 804 TR BX D A G30 Ek E30 Tk 724906 Figure 21 The result of timing simulation As an aid in seeing the actual values of the delays we can use the reference line Point to the small square handle at the top of the reference line and drag it to the rising edge of the first AddSubR pulse at which time the reg isters are also loaded as indicated in the figure To make it possible to move the reference line to a
24. I More cpu 0 Settings System Generation Extra Utilities 4 Interfaces and Periphe Legacy Components Math Coprocessors F Memory l see Cypress CYTC1S i EPCS Serial Flash se Flash Memory Cc ae ai IDTT1V416 SRAM El cpu 4 Mios Processor Alter clk La On Chip Memory instruction_master Master port SDRAM Controller data_master Master port Ra Ra 31 an O AND 29LV800 Fle flag debug module Slave port Ox00007000 Ox000017FF iy DDR SDRAM Cort onchip_memonr On Chip Memory RAM or R Ox00000000 OxO0000FFF ai O DDR SDRAM Cor Switches PIG Parallel Wo 0x00001800 Ox00001 80F Ea O IDT71 016 SRAM LEDs Plo Parallel Io OxO0001810 Ox0000181F i jtag_uart_0 JTAG UART 0x00001 820 ox00001827 0 sdram SDRAM Controller OxO0300000 OxO0FFFFFF Board Unspecified Board Device Family Cyclone I w Module Mame Description Input clock Base HAHAE I SH sesila R a Ceara m ejoj e fs cpu_O was generated as plain text HDL 0 cpu 0 The reset address points to volatile memory Execution of undefined code may occur upon reset ia Done checking for updates L Figure 5 The expanded Nios II system The augmented Verilog module generated by the SOPC Builder is in the file nios_system v in the directory of the project Figure 6 depicts the portion of the code that defines the input and output signals
25. M Do vou want to pipeline the function dataa 15 0 A 5 Ma E Yes want an output latency of Clack cycles datab 15 0 p i Create an asynchronous Clear input eate a Clack Enable input Resource Estimate w 35 lut Documentation Cancel lt Back Next gt Finish Figure 9 Refuse the pipelining option 7 In the box in Figure 9 say No to the pipelining option and click Next 8 Figure 10 gives a summary which shows the files that the wizard will create Press Finish to complete the process MegaWizard Plug In Manager LPM_ADD_SUB page 7 of 7 Summary VWihen the Finish button is pressed the MegaWizard Plug in Manager will create the checked files in the following list ou may choose to Include or exclude a file by checking or unchecking its corresponding checkbox respectively The state of checkboxes will be remembered for the next Meqavvizard Plug In Manager session The Megavvizard Plug In Manager will create these files in the directory d tutorial_lprmni Mf meqaddsub v Variation file O megaddsub inc AHADL Include file O megaddsub cmp VHDL Component declaration file O megaddsub bst Quartus symbol tile O megaddsub_insty Instantiation template file O megaddsub_bbv Verilog Black Box declaration file O megaddsub_wavetorms html Sample waveforms in summary megaddsub wave jog Sample waveform file s Documentation Cancel lt Back Hest gt Fin
26. Package Any E Software Build Settings EP2C8F 25618 Advanced ecHardConu Settings EP2CS0208C7 Advanced Preset Any EP2Cea208Cs Advanced lay FP2C80 20818 Advanced Spee gai Any EP2C8T 14406 Advanced Core voltage 1 24 EP2CeT 1440 Advanced i EP2C8T144C8 Advanced W Show advanced devices EP2CeT 14418 Advanced EP2C20F256C6 ai a p EP2C2DF256C7 M Migration compatibility O migration devices selected Migration Devices Available devices Show in Available devices list EP2C20F 4540 EP2C20F 45408 EP2C35F 45406 EP2U35F 45416 EP2L sore f2C6 Figure 46 The Device Settings window Device amp Pin Options Dual Purpose Pins Voltage Fin Flacement Error Detection CAC General Configuration Frogramming Files Unused Pins Specify general device options These options are not dependent on the configuration scheme Options fa 4uto restart configuration after error Release clears before tr states Enable user supplied start up clock CLEUSR Enable device wide reset DEY_CLAn JEnable device wide output enable DEY OE JEnable INIT DONE output Auto usercode JTAG user code 32 bit hexadecimal FFFFFFFF In system programmini Description Directs the device to restart the configuration process automatically if a data error is encountered If this option ie turned o
27. Settings specify that the required value of fmax is 250 MHz Click OK 3 Recompile the circuit 4 Open the Timing Analyzer Summary to see that the new fmax is 263 02 MHz as indicated in Figure 8 You may get a slghtly different result depending on the version of the Quartus II software used Settings addersubtractor Category General Timing Requirements amp Options Files User Libraries Current Project Specify timing requirements and options Individual timing assignments can be made Device through the Assignment Editor Timing Requirements amp Options H EDA Tool Settings Delay requirements H Compilation Process Settings h E Report minimam timing checks Analysis amp Synthesis Settings Hu ns See e a a Fitter Settings too ins ms Timing Analyzer Design Assistant tock ins r Signall ap II Logic Analyzer SignalProbe Settings th ins z Simulator l PowerPlay Power Analyzer Settings mee ate o l Software Build Settings M Hack aetlings HardCopy Settings f Default required fmax 250 0 MHz f Settings for individual clack signals Cloct More Settings Cancel Figure 7 Specify the timing constraints in the Settings window Compilation Report Timing Analyzer Summary S 3 Compilation Report Timing Analyzer Summary Brze e ee e kek 4 Dw SUMMary BEB Flow Settings 1 Worst case teu JNA 14191 ne i a Areal a snnnnnnnnnnnniunnnnnnnnnnnnnnnnnnnnnie
28. Z A t4 B t4 B ts 4 B te using the values of A and B shown above We can generate the desired input waveforms as follows Click on the waveform name for the Clock node Once a waveform is selected the editing commands in the Waveform Editor can be used to draw the desired waveforms Commands are available for defining the clock or setting the selected signal to 0 1 unknown X high impedance Z don t care DC and inverting its existing value INV Each command can be activated by using the Edit gt Value command or via the toolbar for the Waveform Editor The Edit menu can also be opened by right clicking on a waveform name With the Clock signal highlighted click on the Overwrite Clock icon F in the toolbar This leads to the pop up window in Figure 10 Enter the clock period value of 20 ns make sure that the phase is O and the duty cycle is 50 percent and click OK The desired clock signal is now displayed in the Waveform window Base waveform on fs a f Time period Period 20 ng Phase 0 0 ng Duty cycle 72 50 a Cancel Figure 10 Definition of the clock period phase and duty cycle We will assume for simplicity of timing that the input signals change coincident with the negative edges of the clock To reset the circuit set Reset 1 in the time interval O to 20 ns Do this by pressing the mouse at the start of the interval and dragging it to its end which highlights the se
29. a a a a a A T t A M a Figure 37 Setting of test values 6 1 Performing the Simulation A designed circuit can be simulated in two ways The simplest way is to assume that logic elements and intercon nection wires in the FPGA are perfect thus causing no delay in propagation of signals through the circuit This is called functional simulation A more complex alternative is to take all propagation delays into account which leads to timing simulation Typically functional simulation is used to verify the functional correctness of a circuit as it is being designed This takes much less time because the simulation can be performed simply by using the logic expressions that define the circuit 6 1 1 Functional Simulation To perform the functional simulation select Assignments gt Settings to open the Settings window On the left side of this window click on Simulator to display the window in Figure 38 choose Functional as the simulation mode and click OK The Quartus II simulator takes the inputs and generates the outputs defined in the light vwf file Before running the functional simulation it is necessary to create the required netlist which is done by se lecting Processing gt Generate Functional Simulation Netlist A simulation run is started by Processing gt Start Simulation or by using the icon F At the end of the simulation Quartus II software indicates its successful completion and displays a Simulation Report illustrated in
30. adder module adderk carryin X Y S carryout parameter k 8 input k 1 0 X Y input carryin output k 1 0 S output carryout reg k 1 0 S reg carryout always X or Y or carryin carryout S X Y carryin endmodule Figure 2 Verilog code for the circuit in Figure 1 Part b 2 Using the Waveform Editor Quartus II software includes a simulation tool that can be used to simulate the behavior of a designed circuit Before the circuit can be simulated it is necessary to create the desired waveforms called test vectors to represent the input signals It is also necessary to specify the outputs as well as possible internal points in the circuit which the designer wishes to observe The simulator applies the test vectors to the model of the implemented circuit and determines the expected response We will use the Quartus II Waveform Editor to draw the test vectors as follows 1 Open the Waveform Editor window by selecting File gt New which gives the window shown in Figure 3 Click on the Other Files tab to reach the window displayed in Figure 4 Choose Vector Waveform File and click OK Device Design Files Software Files Other Files Block DiagramS chematic File EDIF File Verilog HDL File WHOL File Figure 3 Need to prepare a new file Device Design Files Software Files Other Files AHOL Include File Block Symbol File Chain Description File Hexadecimal Intel Format File Memor In
31. are used some of the images may be slightly different Contents Nios II System Altera s SOPC Builder Integration of the Nios II System into a Quartus II Project Running the Application Program Altera s Nios II is a soft processor defined in a hardware description language which can be implemented in Altera s FPGA devices by using the Quartus H CAD system To implement a useful system it is necessary to add other funcional units such as memories input output interfaces timers and communications interfaces To facilitate the implementation of such systems it is useful to have computer aided design CAD software for implementing a system on a programmable chip SOPC Altera s SOPC Builder is the software needed for this task This tutorial provides a basic introduction to Altera s SOPC Builder which will allow the reader to quickly implement a simple Nios II system on the Altera DE2 board For a fuller treatment of the SOPC Builder the reader can consult the Nios IJ Hardware Development Tutorial A complete description of the SOPC Builder can be found in the Quartus II Handbook Volume 4 SOPC Builder These documents are available on the Altera web site 1 Nios Il System A Nios II system can be implemented on the DE2 board as shown in Figure 1 Host computer USB Blaster interface JTAG Debug JTAG UART module interface Nios II processor Avalon switch fabric SRAM SDRAM Flash Parallel 1 0 Serial I O m
32. as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services This document is being provided on an as is basis and as an accommodation and therefore all warranties rep resentations or guarantees of any kind whether express implied or statutory including without limitation war ranties of merchantability non infringement or fitness for a particular purpose are specifically disclaimed Quartus II Introduction Using Verilog Design This tutorial presents an introduction to the Quartus II CAD system It gives a general overview of a typi cal CAD flow for designing circuits that are implemented by using FPGA devices and shows how this flow is realized in the Quartus II software The design process is illustrated by giving step by step instructions for using the Quartus II software to implement a very simple circuit in an Altera FPGA device The Quartus II system includes full support for all of the popular methods of entering a description of the desired circuit into a CAD system This tutorial makes use of the Verilog design entry method in which the user specifies the desired circuit in the Verilog hardware description language Two other versions of this tutorial are also available one uses the VHDL hardware description language and the other is based on defining t
33. created db save as type Comma Separated Value File cs Cancel Figure 30 Exporting the pin assignment You can import a pin assignment by choosing Assignments gt Import Assignments This opens the dia logue in Figure 31 to select the file to import Type the name of the file including the csv extension and the full path to the directory that holds the file in the File Name box and press OK Of course you can also browse to find the desired file Import Assignments Specify the source and categories of assignments to import Click LogicLock Import File Assignments to select LogicLock Import File s Assignment source f File name etl eral f Use LogicLock Import File Assignments iw Copy existing assignments into light gsf bak before importing Figure 31 Importing the pin assignment 19 For convenience when using large designs all relevant pin assignments for the DE2 board are given in the file called DE2_pin_assignments csv in the directory DE2_tutorials design_files which is included on the CD ROM that accompanies the DE2 board and can also be found on Altera s DE2 web pages This file uses the names found in the DE2 User Manual If we wanted to make the pin assignments for our example circuit by importing this file then we would have to use the same names in our Block Diagram Schematic design file namely SW 0 SW I1 and LEDG O0 for x1 x2 and f respectively Since these signals are
34. design we first have to define a new design project Quartus II software makes the designer s task easy by providing support in the form of a wizard Create a new project as follows 1 Select File gt New Project Wizard to reach the window in Figure 4 which indicates the capability of this wizard You can skip this window in subsequent projects by checking the box Don t show me this intro duction again Press Next to get the window shown in Figure 5 New Project Wizard Introduction The New Project Wizard helps vou create a new project and preliminary project settings including the Following Project name and directory Name of the top level design entity Project files and libraries Target device family and device EDA tool settings You can change the settings for an existing project and specify additional project wide settings with the Settings command Assignments menu You can use the various pages of the Settings dialog bos to add functionality to the project Dont show me this introduction again tens crea Figure 4 Tasks performed by the wizard New Project Wizard Directory Name Top Level Eg What is the working directory for this project D introtutorial 7 ae What is the name of this project light What is the name of the top level design entity for this project This name it case sensitive and must exactly match the entity name in the design file light ka Use Existing Project Setti
35. enable the PLL Operation Mode Normal Create an areset input to asynchronously reset the PLL Clk Ratio f Ph gdaj OC cE Create an pfdena input to selectively enable the phase freg detector peo vt ooo 60 00 Lock output Create locked output E 1048575 Advanced PLL Parameters Using these parameters iz recommended for advanced users only Create output file s using the Advanced PLL parameters Configurations with output clock s that use cascade counters are not supported Documentation Cancel Back Next gt Finish Figure 13 Remove unnecessary signals 10 4 We are interested only in the input signal inclock0 and the output signal c0 Remove the other two signals shown in the block diagram in the figure by de selecting the optional input areset as well as the locked Output as indicated in the figure Click Next on this page as well as on page 5 until you reach page 6 which is shown in Figure 14 MegaWizard Plug In Manager ALTPLL page 6 of 9 Bad cO CoreExternal Output Clock Jump to page for Ey Clock co ka Able to implement the requested PLL W Use this clock Clock Tap Settings be Requested settings Actual settings sdram_pll q g g Enter output clock frequency 50 MHz FO 000000 r inclkO frequency 50 000 tHe Enter output clock parameters Operation hode Normal Clock multiplication factor Elk Ratio f Ph gaaaf OC cE Clock division facto
36. file syn thesize the circuit and generate an implementation of it for the target chip These tools are controlled by the application program called the Compiler Run the Compiler by selecting Processing gt Start Compilation or by clicking on the toolbar icon that looks like a purple triangle As the compilation moves through various stages its progress 1s reported in a window on the left side of the Quartus II display Successful or unsuccessful compilation is indicated in a pop up box Acknowledge it by clicking OK which leads to the Quartus II display in Figure 21 In the message window at the bottom of the figure various messages are displayed In case of errors there will be appropriate messages given When the compilation is finished a compilation report is produced A window showing this report is opened automatically as seen in Figure 21 The window can be resized maximized or closed in the normal way and it can be opened at any time either by selecting Processing gt Compilation Report or by clicking on the icon The report includes a number of sections listed on the left side of its window Figure 21 displays the Compiler Flow Summary section which indicates that only one logic element and three pins are needed to implement this tiny circuit on the selected FPGA chip Another section is shown in Figure 22 It is reached by selecting Analysis amp Synthesis gt Equations on the left side of the compilation report H
37. for the mod ule nios_system As in our initial system that we developed in the introductory tutorial the 8 bit vector that is the input to the parallel port Switches is called in_port_to_the_Switches The 8 bit output vector is called out_port_from_the_LEDs The clock and reset signals are called clk and reset_n respectively A new module called sdram is included It involves the signals indicated in Figure 2 For example the address lines are re ferred to as the output vector zs_addr_from_the_sdram 11 0 The data lines are referred to as the inout vector zs_dq_to_and_from_the_sdram 15 0 This is a vector of the inout type because the data lines are bidirectional nios_system v module nios system f 1 global signals clk reset n EE the LEDs out port from the LEDs if the Switches in port to the switches f the sdram 23 addr from the sdram 23 ba from the sdram 23 Cas n from the sdram 23 Cke from the sdram 23 C08 n from the sdram 23 dq to and from the sdram 235 dqm from the sdram 23 ras n from the sdram 23 we n from the sdram ODuUtput i out port from the LEDs output l 23 addr from the sdram DUuUtput l z3 ba from the sdram DUtput 23 Cas n from the sdram DUuUtput 23 Cke from the sdram output 23 0S n from the sdram inout 23 dq to and from the sdram DUuUtput x 23 dqm from the sdram output 23 ras n from the sdram output 23 we n from the sdram input clk Figure 6 A part of the generate
38. generated in response In addition to being able to observe the simulated values on the I O pins of the circuit it is also possible to probe the internal nodes in the circuit The simulator makes use of the Waveform Editor which makes it easy to represent the desired signals as waveforms Doing this tutorial the reader will learn about e Test vectors needed to test the designed circuit e Using the Quartus II Waveform Editor to draw the test vectors e Functional simulation which is used to verify the functional correctness of a synthesized circuit e Timing simulation which takes into account propagation delays due to logic elements and interconnecting wiring This tutorial is aimed at the reader who wishes to simulate circuits defined by using the Verilog hardware description language An equivalent tutorial is available for the user who prefers the VHDL language PREREQUISITES The reader is expected to have access to a computer that has Quartus II software installed The detailed examples in the tutorial were obtained using the Quartus II version 5 0 but other versions of the software can also be used 1 Example Circuit As an example we will use the adder subtractor circuit shown in Figure 1 The circuit can add subtract and accumulate n bit numbers using the 2 s complement number representation The two primary inputs are numbers A Qn_14n_ 2 G9 and B bp 1bn 2 bo and the primary output is Z Zn 1Zn 2 Zo A
39. labeled Location Now the drop down menu in Figure 28 appears Scroll down and select PIN N25 Instead of scrolling down the menu to find the desired pin you can just type the name of the pin N25 in the Location box Use the same procedure to assign input x2 to pin N26 and output f to pin AE22 which results in the image in Figure 29 To save the assignments made choose File gt Save You can also simply close the Assignment Editor window in which case a pop up box will ask if you want to save the changes to assignments click Yes Recompile the circuit so that it will be compiled with the correct pin assignments Figure 27 The drop down menu displays the input and output names Location DO Bank I O Standard General Function Special Fun LYTTL O PIN Mi I O Bank 2 Dedicated Clock CLE1 LYDSCLEOn Input A PIN_ Nz I O Bank 2 Dedicated Clock CLEO LYDSCLEOp Input E PIN Na lOBank Row I O LYDS31p O Bank 5 Dedicated Clock CLE4 LYDSCLE2p Input PIN Pi LO Bank 1 Dedicated Clock CLES LYDSCLE1n Input PIN_P2 I O Bank 1 Dedicated Clock CLE2 LYDSCLE1p Input PIN PS WoBanki Row Tid LYDSZ6p DPCLEL DOSILICOIL PIN P4 WoBanki Row Ti LYDS26n PIN P WoBanki Row Tid LYDS22n PIN PF VWoBanki Row lid LYDS22p PIN PS VOBank Row I O LYDS31n 4 Figure 28 The available pins S Assignment Editor E o Eg ii Category Pin T All W Pin A Timing Logic Options a ij mh T oe Ft
40. observe the expected values of the outputs In a large circuit the number of possible input valuations may be huge so in practice we choose a relatively small but representative sample of these input valuations However for our tiny circuit we can simulate all four input valuations given in Figure 12 We will use four 50 ns time intervals to apply the four test vectors We can generate the desired input waveforms as follows Click on the waveform name for the x node Once a waveform is selected the editing commands in the Waveform Editor can be used to draw the desired waveforms Commands are available for setting a selected signal to 0 1 unknown X high impedance Z don t care DC inverting its existing value INV or defining a clock waveform Each command can be activated by using the Edit gt Value command or via the toolbar for the Waveform Editor The Edit menu can also be opened by right clicking on a waveform name Set x to O in the time interval O to 100 ns which is probably already set by default Next set x to 1 in the time interval 100 to 200 ns Do this by pressing the mouse at the start of the interval and dragging it to its end which highlights the selected interval and choosing the logic value 1 in the toolbar Make x2 1 from 50 to 100 ns and also from 150 to 200 ns which corresponds to the truth table in Figure 12 This should 23 produce the image in Figure 39 Observe that the output f is displayed as havin
41. pending applications mask work rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services This document is being provided on an as is basis and as an accommodation and therefore all warranties rep resentations or guarantees of any kind whether express implied or statutory including without limitation war ranties of merchantability non infringement or fitness for a particular purpose are specifically disclaimed 29 Quartus II Introduction Using Schematic Design This tutorial presents an introduction to the Quartus II CAD system It gives a general overview of a typi cal CAD flow for designing circuits that are implemented by using FPGA devices and shows how this flow is realized in the Quartus II software The design process is illustrated by giving step by step instructions for using the Quartus II software to implement a very simple circuit in an Altera FPGA devic
42. program In our case this is the memory block in the FPGA device The SOPC builder assigned the name onchip_memory_0 to this block If not already done select this name in the window in Figure 20 Having provided the necessary information click Confirm Next the main Nios II Debug Client window appears as shown in Figure 21 To assemble and download the light s program click Compile amp Load A dialog box in Figure 22 appears Select the file Jights s as indicated in the figure and click Open As a result of opening the file the Nios If Debug Client invokes an assembler program followed by a linker program The commands used to invoke these programs and the output they produce can be viewed in the Debug tab of the Client window The downloaded program is displayed in the Disassemble tab of the Client window as illustrated in Figure 23 Observe that movia is a pseudoinstruction which is implemented as two separate instructions See the Nios IT Processor Reference Handbook for a description of the Nios II instruction set Click Run to execute the program With the program running you can now test the design by turning the switches SW 7 to SWO on and off the LEDs should respond accordingly 16 Settings Window Nios Il System Properties SOPC Builder PTF File File Name nios_system ptf Files of Type SOPC Builder PTF Files ptt 7 Program Memory onchip_memory_0 Selected Memory Size
43. programming failed then check to ensure that the board is properly powered on 7 2 Active Serial Mode Programming In this case the configuration data has to be loaded into the configuration device on the DE2 board which is identified by the name EPCS16 To specify the required configuration device select ASsignments gt Device which leads to the window in Figure 46 Click on the Device amp Pin Options button to reach the window in Figure 47 Now click on the Configuration tab to obtain the window in Figure 48 In the Configuration device box which may be set to Auto choose EPCS16 and click OK Upon returning to the window in Figure 46 click OK Recompile the designed circuit 27 Settings light Category General Files User Libraries Current Project Select the family and device you want to target for compilation Device Timing Requirements amp Options fees Sorell SC H EDA Tool Settings Family Cyclone Il Device amp Pin Options l Compilation Process Settings Analysis amp Synthesis Settings l Fitter Settings Timing Analyzer Specific device selected in Available devices list i Target device Auto device selected by the Fitter from the Available devices list Design Assistant Oren nz lt Signal ap Il Logic Analyzer l i SignalProbe Settings Simulator EP2C8F256C7 fad d PowerPlay Power Analyzer Settings EPZCSFASECS R
44. same aspects of the Quartus II software they differ only in the design entry method that is used They illustrate the entire process of implementing a design targetted for the DE2 board Detailed information about the DE2 board is given in the DE2 User Manual which describes all of the features of the board It also describes a Control Panel utility which allows the user to write read data into from various components on the board in a simple and direct manner The user is encouraged to explore and make use of this utility Copyright 2005 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending applications mask work rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except
45. select JTAG in the Mode box Also if the USB Blaster is not chosen by default press the Hardware Setup button and select the USB Blaster in the window that pops up The configuration file lights sof should be listed in the window If the file is not already listed then click Add File and select it Click the box under Program Configure to select this action At this point the window settings should appear as indicated in Figure 18 Press Start to configure the FPGA 14 a lights cdf Z Hardware Setup USB Blaster USB 0 Made JTAG Progress Enable real time SP to allow background programming for Max Il devices pif EA EP2C35F672 Oo420547 FFFFFFFF oe Auto Detect Delete Gay Add File ie Change File Gi Add Device Figure 18 The Programmer window 4 Running the Application Program Having configured the required hardware in the FPGA device it is now necessary to create and execute an appli cation program that performs the desired operation This can be done by writing the required program either in the Nios II assembly language or in a high level language such as C We will illustrate both approaches A parallel I O interface generated by the SOPC Builder is accessible by means of registers in the interface Depending on how the PIO is configured there may be as many as four registers One of these registers is called the Data register In a PIO configured as an input interfa
46. signal and the XOR gates along with the signal defined as wire H are no longer needed e The adderk instance of the adder circuit is replaced by megaddsub Note that the dataa and datab inputs shown in Figure 6 are driven by the G and Breg vectors respectively Also the inverted version of the AddSubR signal is specified to conform with the usage of this control signal in the LPM e The adderk module is deleted from the code 10 Top level module module addersubtractor2 A B Clock Reset Sel AddSub Z Overflow parameter n 16 input n 1 0 A B input Clock Reset Sel AddSub output n 1 0 Z output Overflow reg SelR AddSubR Overflow reg n 1 0 Areg Breg Zreg wire n 1 0 G M Z wire over_flow Define combinational logic circuit mux2tol multiplexer Areg Z SelR G defparam multiplexer k n megaddsub nbit_adder AddSubR G Breg M over_flow assign Z Zreg Define flip flops and registers always posedge Reset or posedge Clock if Reset 1 begin Areg lt 0 Breg lt 0 Zreg lt 0 SelR lt 0 AddSubR lt 0 Overflow lt 0 end else begin Areg lt A Breg lt B Zreg lt M SelR lt Sel AddSubR lt AddSub Overflow lt over_flow end endmodule k bit 2 to 1 multiplexer module mux2tol V W Selm F parameter k 8 input k 1 0 V W input Selm output k 1 0 F reg k 1 0 F always V or W or Selm if Selm 0 F V el
47. specified in the DE2_pin_assignments csyv file as elements of vectors SW and LEDG we must refer to them in the same way in our design file For example in the DE2_pin_assignments csv file the 18 toggle switches are called SW 17 to SW O In a design file they can also be referred to as a vector SW 17 0 6 Simulating the Designed Circuit Before implementing the designed circuit in the FPGA chip on the DE2 board it is prudent to simulate it to ascertain its correctness Quartus II software includes a simulation tool that can be used to simulate the behavior of a designed circuit Before the circuit can be simulated it is necessary to create the desired waveforms called test vectors to represent the input signals It is also necessary to specify which outputs as well as possible internal points in the circuit the designer wishes to observe The simulator applies the test vectors to a model of the implemented circuit and determines the expected response We will use the Quartus II Waveform Editor to draw the test vectors as follows 1 Open the Waveform Editor window by selecting File gt New which gives the window shown in Figure 32 Click on the Other Files tab to reach the window displayed in Figure 33 Choose Vector Waveform File and click OK New xi Device Design Files Software Files Other Files Block Diagram Schematic File EDIF File Verilog HDL File VHDL File Figure 32 Need to prepare a new file 20 New xj
48. the Active Serial AS mode In this case a configuration device that includes some flash memory is used to store the configuration data Quartus II software places the configuration data into the configuration device on the DE2 board Then this data is loaded into the FPGA upon power up or reconfiguration Thus the FPGA need not be configured by the Quartus II software if the power is turned off and on The choice between the two modes is made by the RUN PROG switch on the DE2 board The RUN position selects the JTAG mode while the PROG position selects the AS mode 7 1 JTAG Programming The programming and configuration task is performed as follows Flip the RUN PROG switch into the RUN position Select Tools gt Programmer to reach the window in Figure 41 Here it is necessary to specify the programming hardware and the mode that should be used If not already chosen by default select JTAG in the Mode box Also if the USB Blaster is not chosen by default press the Hardware Setup button and select the USB Blaster in the window that pops up as shown in Figure 42 light cdf a Hardware Setup U5B Blaster 058 0 Mode JTAG ki Progress aa e ieee eo ome Pee ve B LI LI LI LI light sof EP2U35F 672 O02F 7666 FFFFFFFF oe Auto Detect ca Add File Figure 41 The Programmer window 24 Observe that the configuration file light sof is listed in the window in Figure 41 If the file is not already listed then cli
49. toolbar to bring up the pop up window in Figure 13 Enter the value 54 and click OK Similarly for the subsequent 20 ns intervals set A to the values 132 0 750 and then 0 to the end Set the corresponding values of B to 1850 63 0 120 7000 30000 and 0 to generate the waveforms depicted in Figure 14 Observe that the outputs Z and Overflow are displayed as having unknown values at this time which is indicated by a hashed pattern their values will be determined during simulation Save the file 10 Arbitrary Value Ea Node group names K A Radix Signed Decimal Numeric or named walue 54 Cancel i Figure 13 Specifying a value for a multibit signal T addersubtractor vwwf Master Time Bar Nps 4 Pointer 146 25 ns Interval 146 25 ns Start End Nps 40 0 ns 0 0 ns 120 0 ns 160 0 ns Value at T ps JS GEES AOO A O Tae AOO DO Gls SE O A T650 GES GEES A 120 Gil Ta i a Ot Mt aaa a a a a a a A T a E T a a a t a Figure 14 The specified input test vectors Another convenient mechanism for changing the input waveforms is provided by the Waveform Editing tool which is activated by the icon When the mouse is dragged over some time interval in which the waveform is 0 1 the waveform will be changed to 1 0 Experiment with this feature on signal AddSub 3 Performing the Simulation A designed circuit can be simulated in two ways The simplest way is to assume that logic elements and int
50. version of the processor Click Finish to return to the window in Figure 5 which now shows the Nios II processor specified as indicated in Figure 7 There may be some warnings or error messages displayed in the SOPC Builder Messages window at the bottom of the screen because some parameters have not yet been specified Ignore these messages as we will provide the necessary data later Observe also that a new tab called Nios II More cpu_0 Settings appears which allows further configuration of the processor we will not use it LE Altera SOPC Builder nios_system SEE File Module System View Tools Help E System Contents Nios I More cpu_0 Settings System Generation Altera SOPC Builder eee hu be Create New Component re aN Clock Source Pipeline Avalon Components Board Unspecified Board clk External Nios I Processor Altera ee Bridges Device Family Cyclone II i Avalon Tristate Bridg on SPI 3 Wire Serial E cpu_0 Nios Il Processor Altera Corporation clk i UART RS 232 serial instruction_master Master port i D16550 UART with 1 data_master Master port RQ 0 IRQ 31 2 Communication TT psec a JTAG UART Use Module Name Description Input Clock Base IRQ jtag_debug_tmodule slave port 0x00000000 0x000007FF H O DIZCM 12C Bus Interte H O DIZCSB 12C Bus Inter H O DSPI Serial Periphera H O H16550S UART C H O H8250 CAST Inc HO High P
51. we concatenated these signals as DRAM_BA_1 DRAM_BA_0O Similarly the vector zs_dqm_from_the_sdram 1 0 corresponds to DRAM_UDQM DRAM_LDQM Finally note that we tried an obvious approach of using the 50 MHz system clock CLOCK_50 as the clock signal DRAM_CLK for the SDRAM chip This is specified by the assign statement in the code This approach leads to a potential timing problem caused by the clock skew on the DE2 board which can be fixed as explained in section 5 Implements the augmented Nios II system for the DE2 board Inputs SW7 0 are parallel port inputs to the Nios II system CLOCK_50 is the system clock KEYO is the active low system reset Outputs LEDG7 0 are parallel port outputs from the Nios II system SDRAM ports correspond to the signals in Figure 2 their names are those used in the DE2 User Manual module lights SW KEY CLOCK_50 LEDG DRAM_CLK DRAM_CKE DRAM_ADDR DRAM_BA_1 DRAM_BA_0 DRAM_CS_N DRAM_CAS_N DRAM _RAS_N DRAM_WE_N DRAM_DQ DRAM_UDQM DRAM_LDQM input 7 0 SW input 0 0 KEY input CLOCK_50 output 7 0 LEDG output 11 0 DRAM_ADDR output DRAM_BA_1 DRAM_BA_0 DRAM_CAS_N DRAM_RAS_N DRAM_CLK output DRAM_CKE DRAM_CS_N DRAM_WE_N DRAM_UDQM DRAM_LDQM inout 15 0 DRAM_DQ Instantiate the Nios II system module generated by the SOPC Builder nios_system NioslI CLOCK_50 KEY O LEDG SW DRAM_ADDR DRAM_BA_1 DRAM_BA_ 0 DRAM_CAS_N DRAM_CK
52. 12 Select File x Lookin introtutorial eX Fav File name flightv Cancel Files of type Design Files tdf vhd vhdl v vig vh verilc 4 Figure 18 Select the file 4 Compiling the Designed Circuit The Verilog code in the file light v is processed by several Quartus II tools that analyze the code synthesize the circuit and generate an implementation of it for the target chip These tools are controlled by the application program called the Compiler Run the Compiler by selecting Processing gt Start Compilation or by clicking on the toolbar icon that looks like a purple triangle As the compilation moves through various stages its progress 1s reported in a window on the left side of the Quartus II display Successful or unsuccessful compilation is indicated in a pop up box Acknowledge it by clicking OK which leads to the Quartus II display in Figure 19 In the message window at the bottom of the figure various messages are displayed In case of errors there will be appropriate messages given Quartus Il D introtutorial light light eles File Edit View Project Assignments Processing Tools Window Help Oe Some ool hon KL SB Orv h Ow Project Navigator 4 x F light v Compilation Report Flow Summary module light xl x2 input x1 x2 Compilation Report Flow Summary JX Compilation Report Flow Summary amp BE Legal Notice an Flow Summary Flow Status Succe
53. 1991 2005 Altera Corporation Cancel Figure 10 The MegaWizard 2 In the window in Figure 11 specify that Cyclone II is the device family used and that the circuit should be defined in Verilog HDL Also specify that the generated output Verilog file should be called sdram_pll v From the list of megafunctions in the left box select I O gt ALTPLL Click Next MegaWizard Plug In Manager page 2a Which megafunction would you like to customize Select a megafunction from the list below 3 8 Installed Plug Ins A Altera SOPC Builder arithmetic A ARM Based Excalibur gates 0 2 ALTASMI_PARALLEL 2 ALTCLKCTRL ALTDDIC_BIDIR ALTDDIC_IN ALTDDIQ_OUT ALTDG 2 ALTDOS ALTLYDS a memory compiler Signall ap II Logic Analyzer Which device Family will you be using Cyclone Il ka Which type of output file do you want to create f AHOL f VHDL f Verilog HOL What name do you want for the output file Browse D DE2_sdram_tutorial ssdram_pll y Return to this page for another create operation Note To compile a project successfully in the Quartus software your design files must be in the project directory in the global user branes specified in the Options dialog box Tools menu or a user library specified in the User Libraries page of the Settings dialog box Assignments menu Your current user library directories are Cancel lt Back Next gt
54. 5 11 23 39 2005 pEi Flow Settings Quartus Il Version 5 0 Build 168 06 22 2005 SP 1 SJ Fullversion g E Flow Elapsed Time Revision Name light 8 B Flow Log Top level Entity Mame light Analysis amp Synthesis Family Cyclone II Device EP2U35F 67206 Timing Models Preliminary Met timing requirements M A Figure 21 Compilation report for the failed design cae PAOD rapuri Analysis amp Svih PEJ O20 mmm SB Legal Notice Bg Flow Summary D ine Running Quartus Il Analysis amp Synthesis SEB Flow Settings 42 Info Command quartus_map read_settings_files on write_settings_files off is c light Bs Flow Elapsed Time x Error Verilog HOL syntax error at light v 6 near test endmodule expecting R B Flow Log 42 Info Found 0 design units including 0 entities in source file light Error Quartus Il Analysis amp Synthesis was unsuccessful 1 error 0 warnings fo Analysis amp Synthesis i y 25 Summary Settings SE Source Files Read gD Meas Message Qof10 E Location Figure 22 Error messages EB light v _jolx module light x1 x2 f input xl x2 output f assign f xl amp x2 xl amp x2 Figure 23 Identifying the location of the error 5 Pin Assignment During the compilation above the Quartus II Compiler was free to choose any pins on the selected FPGA to serve as inputs and outputs However the DE2 board has hardwired connections between the FPGA pins and
55. AM_WE_N DRAM_DQ DRAM_UDQM DRAM_LDQM input 7 0 SW input 0 0 KEY input CLOCK_50 output 7 0 LEDG output 11 0 DRAM_ADDR output DRAM_BA_1 DRAM_BA_0 DRAM_CAS_N DRAM_RAS_N DRAM_CLK output DRAM_CKE DRAM_CS_N DRAM_WE_N DRAM_UDQM DRAM_LDQM inout 15 0 DRAM_DQ Instantiate the Nios II system module generated by the SOPC Builder nios_system NioslI CLOCK_50 KEY O LEDG SW DRAM_ADDR DRAM_BA_1 DRAM_BA_ 0 DRAM_CAS_N DRAM_CKE DRAM_CS_N DRAM_DQ DRAM_UDQM DRAM_LDQM DRAM_RAS_N DRAM_WE_N Instantiate the module sdram_pll GinclkO c0 sdram_pll neg_3ns CLOCK_50 DRAM_CLK endmodule Figure 17 Proper instantiation of the expanded Nios H system Compile the code and download the design into the Cyclone II FPGA on the DE2 board Use the application program in Figure 8 to test the circuit 13 Copyright 2006 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending applications mask work rights and copyrights Altera warrants performance of its semic
56. Areg 3 Worst case lco 7181 n Zregl8 EG p Worst case th 0 559 ns SaR E lock Setup Elo ck Sa ae SERS SEH3 T period 3 802 ne AddSubl a Crt Clock Hold Clock rea tl Bl Total number of failed _ cirta E Align Left Fra Cla i El anrr ae V E FA T E Y S Copy Select All Zea ace ES Summary BEB Settings BEB Clock Settings Summary BEA Clock Setup Clock BEA Clock Hold Clock 3 SEa teu Ee Bes too SD Bh 2 Messages Align Right List Paths Locate Locate in Assignment Editor Locate in Pin Planner Locate in Timing Closure Floorplan Locate in Chip Editor Locate in Resource Property Editor Timing Settings Save Current Report Section As Locate in Technology Map viewer Locate In RTL Viewer Locate in Design File Figure 10 Locate the critical path AddSubR Overflovweregd Overflow Figure 11 Path for which the timing constraint cannot be met It is likely that there are other paths that make it impossible to meet the specified constraint To identify these paths choose Clock Setup Clock on the left side of the Compilation Report in Figure 9 As seen in Figure 12 there are 10 paths with propagation delays that are too long Observe a column labeled Slack The term slack is used to indicate the margin by which a timing requirement is met or not met In the top ro
57. B port on a computer that runs the Quartus II software Turn on the power switch on the DE2 board The computer will recognize the new hardware connected to its USB port but it will be unable to proceed if it does not have the required driver already installed The DE2 board is programmed by using Altera s USB Blaster mechanism If the USB Blaster driver is not already installed the New Hardware Wizard in Figure 1 will appear Found New Hardware Wizard Welcome to the Found New Hardware Wizard Windows will search for curent and updated software by looking on your computer on the hardware installation CD or on the Windows Update Web site with your permission Read our privacy policy Can Windows connect to Windows Update to search for software Yes this time only Yes now and every time connect a device No not this time Click Next to continue Figure 1 Found New Hardware Wizard Since the desired driver is not available on the Windows Update Web site select No not this time in response to the question asked and click Next This leads to the window in Figure 2 Found New Hardware Wizard This wizard helps you install software for Altera USB Blaster oo j i If your hardware came with an installation CD TE or floppy disk insert it now What do you want the wizard to do Install the software automatically Recommended Install from a list or specific location Advanced Clic
58. E DRAM_CS_N DRAM_DQ DRAM_UDQM DRAM_LDQM DRAM_RAS_N DRAM_WE_N assign DRAM_CLK CLOCK_50 endmodule Figure 7 A first attempt at instantiating the expanded Nios II system As an experiment you can enter the code in Figure 7 into a file called lights v Add this file and all the v files produced by the SOPC Builder to your Quartus II project Compile the code and download the design into the Cyclone II FPGA on the DE2 board Use the application program from the tutorial Introduction to the Altera SOPC Builder which is shown in Figure 8 Use the Nios II Debug Client which is described in the tutorial Nios IT Debug Client to assemble download and run this application program If successful the lights on the DE2 board will respond to the operation of the toggle switches Due to the clock skew problem mentioned above the Nios II processor may be unable to properly access the SDRAM chip A possible indication of this may be given by the Nios II Debug Client which may display the message depicted in Figure 9 To solve the problem it is necessary to modify the design as indicated in the next section pmi 4 include nios _macros s equ Switches 0x00001800 equ LEDs 0x00001810 GFUNC _ start movia r2 Switches movia r3 LEDs loop Idbio r4 O r2 Stbio r4 O 73 br loop BREAK Figure 8 Assembly language code to control the lights Could not download this SREC Verification Failed Possible Causes
59. EPCS16 To specify the required configuration device select Assignments gt Device which leads to the window in Figure 44 Click on the Device amp Pin Options button to reach the window in Figure 45 Now click on the Configuration tab to obtain the window in Figure 46 In the Configuration device box which may be set to Auto choose EPCS16 and click OK Upon returning to the window in Figure 44 click OK Recompile the designed circuit 25 Settings light Category General Files User Libraries Current Project Select the family and device you want to target for compilation Device Timing Requirements amp Options fees Sorell SC H EDA Tool Settings Family Cyclone Il Device amp Pin Options l Compilation Process Settings Analysis amp Synthesis Settings l Fitter Settings Timing Analyzer Specific device selected in Available devices list i Target device Auto device selected by the Fitter from the Available devices list Design Assistant Oren nz lt Signal ap Il Logic Analyzer l i SignalProbe Settings Simulator EP2C8F256C7 fad d PowerPlay Power Analyzer Settings EPZCSFASECS R Package Any E Software Build Settings EP2C8F 25618 Advanced ecHardConu Settings EP2CS0208C7 Advanced Preset Any EP2Cea208Cs Advanced lay FP2C80 20818 Advanced Spee gai Any EP2C8T 14406 Advanced Core voltage 1 24 EP2CeT 1440 Advance
60. FPGA pins e Compile the designed circuit e Program and configure the Cyclone II device on the DE2 board 12 3 1 Instantiation of the Module Generated by the SOPC Builder The instantiation of the generated module depends on the design entry method chosen for the overall Quartus II project We have chosen to use Verilog HDL but the approach is similar for both VHDL and schematic entry methods Normally the Nios II module is likely to be a part of a larger design However in the case of our simple example there is no other circuitry needed All we need to do is instantiate the Nios I system in our top level Verilog file and connect inputs and outputs of the parallel I O ports as well as the clock and reset inputs to the appropriate pins on the Cyclone II device The Verilog module generated by the SOPC Builder is in the file nios_system v in the directory of the project Note that the name of the Verilog module is the same as the system name specified when first using the SOPC Builder The Verilog code is quite large Figure 16 depicts the portion of the code that defines the input and output signals for the module nios_system The 8 bit vector that is the input to the parallel port Switches 1s called in_port_to_the_Switches The 8 bit output vector is called out_port_from_the_LEDs The clock and reset signals are called clk and reset_n respectively Note that the reset signal 1s added automatically by the SOPC Builder it is called reset_n beca
61. Figure 2 in the project For convenience this file is provided in the directory DE2_tutorials design_files which is included on the CD ROM that accompanies the DE2 board and can also be found on Altera s DE2 web pages Choose the Cyclone I EP2C35F672C6 device which is the FPGA chip on Altera s DE2 board Compile the design Simulate the design by applying some typical inputs Top level module module addersubtractor A B Clock Reset Sel AddSub Z Overflow parameter n 16 input n 1 0 A B input Clock Reset Sel AddSub output n 1 0 Z output Overflow reg SelR AddSubR Overflow reg n 1 0 Areg Breg Zreg wire n 1 0 G H M Z wire carryout over_flow Define combinational logic circuit assign H Breg n AddSubR mux2tol multiplexer Areg Z SelR G defparam multiplexer k n adderk nbit_adder AddSubR G H M carryout defparam nbit_adder k n assign over_flow carryout G n 1 H n 1 M n 1 assign Z Zreg Define flip flops and registers always posedge Reset or posedge Clock if Reset 1 begin Areg lt 0 Breg lt 0 Zreg lt 0 SelR lt 0 AddSubR lt 0 Overflow lt 0 end else begin Areg lt A Breg lt B Zreg lt M SelR lt Sel AddSubR lt AddSub Overflow lt over_flow end endmodule k bit 2 to 1 multiplexer module mux2tol V W Selm F parameter k 8 input k 1 0 V W input Selm output
62. Getting Started with Altera s DE2 Board This document describes the scope of Altera s DE2 Development and Education Board and the suporting ma terials provided by the Altera Corporation It also explains the installation process needed to use a DE2 board connected to a computer that has the Quartus II CAD system installed on it Contents Purpose of the DE2 Board Scope of the DE2 board and Supporting Material Installation and USB Blaster Driver Using the DE2 Board Altera s DE2 Development and Education Board has been developed to provide an ideal vehicle for learning about digital logic and computer organization in a laboratory setting It uses the state of the art technology in both hardware and CAD tools to expose students to a wide range of topics covered in typical courses The power of the board is such that it is also highly suitable for a variety of design projects as well as for the development of sophisticated digital systems In addition to the DE2 board and the associated software Altera provides supporting materials that include tutorials laboratory exercises and interesting demonstrations 1 Purpose of the DE2 Board University and college courses on the design of logic circuits and computer organization usually include a lab oratory component In a modern curriculum the laboratory equipment should ideally exemplify state of the art technology and design tools but be suitable for exercises that range from the simple t
63. Hz clock frequency add the needed timing as signment in your Quartus II project The tutorial Timing Considerations with Verilog Based Designs shows how this is done 13 Implements a simple Nios II system for the DE2 board Inputs SW7 0 are parallel port inputs to the Nios II system CLOCK_50 is the system clock KEYO is the active low system reset Outputs LEDG7 0 are parallel port outputs from the Nios II system module lights SW KEY CLOCK_50 LEDG input 7 0 SW input 0 0 KEY input CLOCK_50 output 7 0 LEDG Instantiate the Nios II system module generated by the SOPC Builder nios_system clk reset_n out_port_from_the_LEDs in_port_to_the_Switches nios_system NiosII CLOCK_50 KEY 0 LEDG SW endmodule Figure 17 Instantiating the Nios II system Having made the necessary settings compile the code You may see some warning messages associated with the Nios II system such as some signals being unused or having wrong bit lengths of vectors these warnings can be ignored 3 2 Programming and Configuration Program and configure the Cyclone I FPGA in the JTAG programming mode as follows L Connect the DE2 board to the host computer by means of a USB cable plugged into the USB Blaster port Turn on the power to the DE2 board Ensure that the RUN PROG switch is in the RUN position Select Tools gt Programmer to reach the window in Figure 18 If not already chosen by default
64. OOOUOOO00R00000 PS SECCEEESE CECE ESSEC EEE ESSE EEEEEEE EE EE EEEE ELE EE A EE ES Ee it EERI coo TEMI suai T EES a Figure 8 The nodes needed for simulation 4 We will now specify the logic values to be used for the input signals during simulation The logic values at the outputs Z and Overflow will be generated automatically by the simulator To make it easy to draw the desired waveforms the Waveform Editor displays by default vertical guidelines and provides a drawing feature that snaps on these lines which can otherwise be invoked by choosing View gt Snap to Grid Observe also a solid vertical line which can be moved by pointing to its top and dragging it horizontally This reference line is used in analyzing the timing of a circuit as described later move it to the time 0 position The waveforms can be drawn using the Selection Tool which is activated by selecting the icon ls in the toolbar or the Waveform Editing Tool which is activated by the icon In the instructions below we will use the Selection Tool To simulate the behavior of a large circuit it is necessary to apply a sufficient number of input valuations and observe the expected values of the outputs The number of possible input valuations may be huge so in practice we choose a relatively small but representative sample of these input valuations We will choose a very small set of input test vectors which is not sufficient to simulat
65. R lt 0 AddSubR lt 0 Overflow lt 0 end else begin Areg lt A Breg lt B Zreg lt M SelR lt Sel AddSubR lt AddSub Overflow lt over_flow end endmodule k bit 2 to 1 multiplexer module mux2tol V W Selm F parameter k 8 input k 1 0 V W input Selm output k 1 0 F reg k 1 0 F always V or W or Selm if Selm 0 F V else F W endmodule continued in Part b Figure 2 Verilog code for the circuit in Figure 1 Part a k bit adder module adderk carryin X Y S carryout parameter k 8 input k 1 0 X Y input carryin output k 1 0 S output carryout reg k 1 0 S reg carryout always X or Y or carryin carryout S X Y carryin endmodule Figure 2 Verilog code for the circuit in Figure 1 Part b 2 Timing Analyzer Report Successful compilation of our circuit generates the Compilation Report in Figure 3 This report provides a lot of useful information It shows the number of logic elements flip flops called registers and pins needed to implement the circuit It gives detailed information produced by the Synthesis and Fitter modules It also indicates the speed of the implemented circuit A good measure of the speed is the maximum frequency at which the circuit can be clocked referred to as fmax This measure depends on the longest delay along any path called the critical path between two registers clocked by the same clock
66. Separated Value File cs k Cancel Figure 28 Exporting the pin assignment 17 You can import a pin assignment by choosing Assignments gt Import Assignments This opens the dia logue in Figure 29 to select the file to import Type the name of the file including the csv extension and the full path to the directory that holds the file in the File Name box and press OK Of course you can also browse to find the desired file Import Assignments Specify the source and categories of assignments to import Click LogicLock Import File Assignments to select LogicLock Import File s Assignment source f File name ea f Use LogicLock Import File Assignments Advanced jw Copy existing assignments into light gsf bak before importing Cancel Figure 29 Importing the pin assignment For convenience when using large designs all relevant pin assignments for the DE2 board are given in the file called DE2_pin_assignments csv in the directory DE2_tutorials design_files which is included on the CD ROM that accompanies the DE2 board and can also be found on Altera s DE2 web pages This file uses the names found in the DE2 User Manual If we wanted to make the pin assignments for our example circuit by importing this file then we would have to use the same names in our Verilog design file namely SW 0 SW I and LEDG 0 for x1 x2 and f respectively Since these signals are specified in the DE2_pin_assignments csv file as e
67. Unassigned Registered User ente Eil Areg 4 Unassigned Registered User ente Areg 5 Unassigned Registered User ente gt Areg 6 Unassigned Registered User ente Areg 7 Unassigned Registered User ente eq Areg 8 Unassigned Registered User ente Areg 9 Unassigned Registered User ente amp Areg 10 Unassigned Registered User ente Aregi11 Unassigned Registered User ente Aregi12 Unassigned Registered User ente aAregl13 Unassigned Registered User ente Areqi14 Unassigned Reaistered User emal 4 gt gt M addersubtractor vwwf Master Time Bar Nps aj Pointer 156 67 ns Interval 156 67 ns Start 0ps End 180 0 ns Nps 40 0 ns oO 0 ns 120 0 ns 160 0 ns Value at Mame Ops Clock Reset Sel AddSub GE ES GEIS SHEHE GEES Gre SE ES A 1650 A 63 AO o 0 4 120 Git T 0 2 QMS le fEOWVElelefey Overlow Fe nM Ng MM RM Ma NT NN MN S5elR E AddSubP J Areg X Breg x reg 5 Figure 19 Inclusion of registered signals in the test Simulation Waveforms Master Time Bar 0ps 4 t Pointer 5 57 ns Interval 5 57 ns Start End Nps 40 0 ns 0 0 ns 120 0 ns 160 0 ns T Clock Bo Reset Sel AddSub GE ES GEES A dazi GEES Ge 0 SS A 1650 b3 AO 0 A 120 000 el 0 SEREEEEEES GE S GL GEER G8 Gis 2 906 Overlow oelF AddsubR Areg SER BES SETE SEHERE Gus i Breg o U A TSO A 63 AO O A 120 000 30000 i reg SEREE EEEES GE S egdi
68. Wizard Plug In Manager page 1 The Megaiwizard Plug In Manager helps you create or modify design files that contain custom wariations of megafunctions Which action do you wantto perorm Create anew custom megafunction variation Editan existing custom meqafunction variation Copy an existing custom megafunction variation Copyright 1991 2004 Altera Corporation Cancel lt Back Next gt Finish Figure 4 Choose to define an LPM MegaWizard Plug In Manager page 2a Which megafunction would you like to customize which device family will you be Cyclone ing Select 4 megafunction from the list below using E E Installed Plug Ins Which type of output file do vou want to create LA Altera SOFC Builder F F AHDL arithmetic p Z ALTACCUMULATE ee 7 ALTFP_ADD_SUB Breas ALTFP_MULT ine 7 ALTMEMMLILT What name do you want for the output file Browse ALTMULT ACCUM MAC D tutorial_lpm megaddsub v ALTMULT_ADD ALTSGRT Generate clear box netlist file instead of a default wrapper file LPM _ABS for use with supported EDA synthesis tools only LPM ADE SUB LFM_COMPARE LPM _COUNTER Note To compile a project successfully in the Quartus software LPM DIVIDE your design files must be in the project directory in the global user LPM MULT aa e e dialog box a UZET 7 PARALLEL ADD a n ibraries page of the Settings dialog ARM Based Excalibur T Return to this page for a
69. accommodation and therefore all warranties rep resentations or guarantees of any kind whether express implied or statutory including without limitation war ranties of merchantability non infringement or fitness for a particular purpose are specifically disclaimed 13 Timing Considerations with Verilog Based Designs This tutorial describes how Altera s Quartus II software deals with the timing issues in designs based on the Verilog hardware description language It discusses the various timing parameters and explains how specific tim ing constraints may be set by the user Contents Example Circuit Timing Analyzer Report Specifying the Timing Constraints Timing Simulation Quartus II software includes a Timing Analyzer module which performs a detailed analysis of all timing delays for a circuit that is compiled for implementation in an FPGA chip This tutorial discusses the types of analyses performed and shows how particular timing requirements may be specified by the user The discussion assumes that the reader is familiar with the basic operation of Quartus II software as may be learned from an introductory tutorial Doing this tutorial the reader will learn about e Parameters evaluated by the Timing Analyzer e Specifying the desired values of timing parameters e Using timing simulation The timing results shown in the examples in this tutorial were obtained using Quartus II version 5 0 but other versions of the
70. arallel 1 0 0x00001800 0x0000180F i O H16550S UART C2 F i PIO Parallel VO 0x00001810 0x0000181 i tee H8250 CAST Inc jtag_uart_0 JTAG UART 0x00001820 0x00001827 o High Performance Gig 4 Figure 14 The final specification 12 Having specified all components needed to implement the desired system it can now be generated Select the System Generation tab which leads to the window in Figure 15 Turn off Simulation Create simulator project files because in this tutorial we will not deal with the simulation of hardware Click 1 Generate on the bottom of the SOPC Builder window The generation process produces the messages displayed in the figure When the message SUCCESS SYSTEM GENERATION COMPLETED appears click Exit This returns to the main Quartus II window Altera SOPC Builder nios_system File Module System View Tools Help r Options BR Run Nios 11 IDE HDL Generate system module logic in Verilog C Simulation Create simulator project files Info to the terms and conditions of the Altera Program License Info Subscription Agreement Altera MegaCore Function License Info Agreement or other applicable license agreement including Info without limitation that your use is for the sole purpose of Info programming logic devices manufactured by Altera and sold by Info Altera or its authorized distributors Please refer to the Info applicable agreement for further details Info P
71. asks that illustrate the most basic concepts to challenging designs that require knowledge of advanced topics From the logistic point of view it is ideal if the same equipment can be used in all cases The DE2 board has been designed to provide the desired platform 2 Scope of the DE2 Board and Supporting Material The DE2 board features a powerful Cyclone II FPGA chip All important components on the board are con nected to the pins of this chip allowing the user to configure the connection between the various components as desired For simple experiments the DE2 board includes a sufficient number of switches of both toggle and pushbutton variety LEDs and 7 segment displays For more advanced experiments there are SRAM SDRAM and Flash memory chips as well as a 16 x 2 character display For experiments that require a processor and simple I O interfaces it is easy to instantiate Altera s Nios II processor and use interface standards such as RS 232 and PS 2 For experiments that involve sound or video signals there are standard connectors provided on the board For large design projects it is possible to use USB and Ethernet connections as well as the SD memory card Finally it is possible to connect other user designed boards to the DE2 board by means of two expansion headers Software provided with the DE2 board features the Quartus II web edition design tools It also includes a simple monitor program that allows the student to contro
72. ation Wizard in Figure 12 e Do not change the default settings e Click Finish to return to the System Contents tab JTAG UART jtag _uart_0 Configuration Simulation write FIFO i data from Avalon to JTAG Depth IRQ Threshold Construct using registers instead of memory blocks Read FIFO i data From JTAG to Ayalon Depth IRQ Threshold Construct using registers instead of memory blocks Figure 12 Define the JTAG UART interface 10 The complete system is depicted in Figure 13 Note that the SOPC Builder automatically chooses names for the various components The names are not necessarily descriptive enough to be easily associated with the target design but they can be changed In Figure 2 we use the names Switches and LEDs for the parallel input and output interfaces respectively These names can be used in the implemented system Right click on the pio_O name and then select Rename Change the name to Switches Similarly change pio_1 to LEDs 11 The base and end addresses of the various components in the designed system can be assigned by the user but they can also be assigned automatically by the SOPC Builder We will choose the latter possibility So select the command using the menus at the top of the SOPC Builder window System gt Auto Assign Base Addresses which produces the assignment shown in Figure 14 10 Altera SOPC Builder nios_system MER System Contents Nios II More cpu_0 Setti
73. basic features of the Quartus II software It shows how the software can be used to design and implement a circuit specified by means of a schematic diagram It makes use of the graphical user interface to invoke the Quartus II commands Doing this tutorial the reader will learn about Creating a project Entering a schematic diagram Synthesizing a circuit from the schematic diagram Fitting a synthesized circuit into an Altera FPGA Assigning the circuit inputs and outputs to specific pins on the FPGA Simulating the designed circuit e Programming and configuring the FPGA chip on Altera s DE2 board 1 Getting Started Each logic circuit or subcircuit being designed with Quartus II software is called a project The software works on one project at a time and keeps all information for that project in a single directory folder in the file system To begin a new logic circuit design the first step is to create a directory to hold its files To hold the design files for this tutorial we will use a directory introtutorial The running example for this tutorial is a simple circuit for two way light control Start the Quartus II software You should see a display similar to the one in Figure 2 This display consists of several windows that provide access to all the features of Quartus II software which the user selects with the computer mouse Most of the commands provided by Quartus II software can be accessed by using a set of menus that a
74. ce the data read from the Data register is the data currently present on the PIO input lines In a PIO configured as an output interface the data written by the Nios II processor into the Data register drives the PIO output lines If a PIO is configured as a bidirectional interface then the PIO inputs and outputs use the same physical lines In this case there is a Data Direction register included which determines the direction of the input output transfer In our unidirectional PIOs it is only necessary to have the Data register The addresses assigned by the SOPC Builder are 0x00001800 for the Data register in the PIO called Switches and Ox00001810 for the Data register in the PIO called LEDs as indicated in Figure 14 You can find a full description of the PIO interface by opening the SOPC Builder window in Figure 14 and right clicking on the module name of a PIO either Switches or LEDs Then in the pop up box select Data Sheet to open the document PIO Core with Avalon Interface which gives a full description of the interface To use this facility you need to be connected to the Internet 4 1 Using a Nios II Assembly Language Program Figure 19 gives a Nios II assembly language program that implements our trivial task The program loads the addresses of the Data registers in the two PIOs into processor registers r2 and r3 It then has an infinite loop that merely transfers the data from the input PIO Switches to the output PIO LEDs Note tha
75. chematic diagram or by using a hardware description language such as Verilog or VHDL e Synthesis the entered design is synthesized into a circuit that consists of the logic elements LEs provided in the FPGA chip e Functional Simulation the synthesized circuit is tested to verify its functional correctness this simulation does not take into account any timing issues e Fitting the CAD Fitter tool determines the placement of the LEs defined in the netlist into the LEs in an actual FPGA chip it also chooses routing wires in the chip to make the required connections between specific LEs e Timing Analysis propagation delays along the various paths in the fitted circuit are analyzed to provide an indication of the expected performance of the circuit e Timing Simulation the fitted circuit is tested to verify both its functional correctness and timing e Programming and Configuration the designed circuit is implemented in a physical FPGA chip by pro gramming the configuration switches that configure the LEs and establish the required wiring connections This tutorial introduces the basic features of the Quartus II software It shows how the software can be used to design and implement a circuit specified by using the Verilog hardware description language It makes use of the graphical user interface to invoke the Quartus II commands Doing this tutorial the reader will learn about Creating a project e Design entry usin
76. ck Add File and select it This is a binary file produced by the Compiler s Assembler module which contains the data needed to configure the FPGA device The extension sof stands for SRAM Object File Note also that the device selected 1s EP2C35F672 which is the FPGA device used on the DE2 board Click on the Program Configure check box as shown in Figure 43 Hardware Setup Hardware Settings JTAG Settings Select a programming hardware setup to use when programming devices This programming hardware setup applies only to the curent programmer window Currently selected hardware Available hardware items Hardware Sever Pot Add Hardware USB Blaster Local Feno Harare Figure 42 The Hardware Setup window light cdf E Hardware Setup U5B Blaster USB 0 Mode JTAG ad Progress yo ee ve Bak light sof EF2C35F6r2 O02F 76BE FFFFFFFF oe Auto Detect Delete cay Add File ie Change File Figure 43 The updated Programmer window Now press Start in the window in Figure 43 An LED on the board will light up when the configuration data has been downloaded successfully If you see an error reported by Quartus II software indicating that programming failed then check to ensure that the board is properly powered on 7 2 Active Serial Mode Programming In this case the configuration data has to be loaded into the configuration device on the DE2 board which is identified by the name
77. ction fi ns M Simulation coverage reporting M Overwrite simulation input file with simulation results Software Build Settings HardCopy Settings uPGore Transaction Model Fle Wane vy Signal activity output for power analysis M Generate Signal Activity File File name fig itsa a signal Activity File Options E 4 Figure 40 Specifying the simulation mode Simulation Waveforms Masher Time Bar esta O ps 4 Pointer pEr 196 84 nz Interval at 196 84 nz Shark End l l l 1200s 160 0 ns Name a eee Figure 41 The result of functional simulation 6 1 2 Timing Simulation Having ascertained that the designed circuit is functionally correct we should now perform the timing simulation to see how it will behave when it is actually implemented in the chosen FPGA device Select ASsignments gt Settings gt Simulator to get to the window in Figure 40 choose Timing as the simulation mode and click OK Run the simulator which should produce the waveforms in Figure 42 Observe that there is a delay of about 6 ns in producing a change in the signal f from the time when the input signals x and x2 change their values This delay is due to the propagation delays in the logic element and the wires in the FPGA device You may also notice that a momentary change in the value of f from 1 to 0 and back to 1 occurs at about 106 ns point in the simulation This glitch is also due to
78. d i EP2C8T144C8 Advanced W Show advanced devices EP2CeT 14418 Advanced EP2C20F256C6 ai a p EP2C2DF256C7 M Migration compatibility O migration devices selected Migration Devices Available devices Show in Available devices list EP2C20F 4540 EP2C20F 45408 EP2C35F 45406 EP2U35F 45416 EP2L sore f2C6 Figure 44 The Device Settings window Device amp Pin Options Dual Purpose Pins Voltage Fin Flacement Error Detection CAC General Configuration Frogramming Files Unused Pins Specify general device options These options are not dependent on the configuration scheme Options fa 4uto restart configuration after error Release clears before tr states Enable user supplied start up clock CLEUSR Enable device wide reset DEY_CLAn JEnable device wide output enable DEY OE JEnable INIT DONE output Auto usercode JTAG user code 32 bit hexadecimal FFFFFFFF In system programmini Description Directs the device to restart the configuration process automatically if a data error is encountered If this option ie turned off You must externally direct the device to restart the configuration process if an error occurs Reset Figure 45 The Options window 26 Device amp Pin Options Dual Purpose Pins Voltage Pin Placement Error Detection CAC Genera
79. d Verilog module 4 Integration of the Nios II System into the Quartus II Project Now we have to instantiate the expanded Nios II system in the top level Verilog module as we have done in the tutorial Introduction to the Altera SOPC Builder Using Verilog Design The module is named lights because this is the name of the top level design entity in our Quartus II project A first attempt at creating the new module is presented in Figure 7 The input and output ports of the mod ule use the pin names for the 50 MHz clock CLOCK_50 pushbutton switches KEY toggle switches SW and green LEDs LEDG as used in our original design They also use the pin names DRAM_CLK DRAM_CKE DRAM_ADDR DRAM_BA_I DRAM_BA_0 DRAM_CS_N DRAM_CAS_N DRAM_RAS_N DRAM_WE_N DRAM_DQ DRAM_UDQM and DRAM_LDQM which correspond to the SDRAM signals indicated in Figure 2 All of these names are those specified in the DE2 User Manual which allows us to make the pin assignments by importing them from the file called DE2_pin_assignments csv in the directory DE2_tutorials design_files which is included on the CD ROM that accompanies the DE2 board and can also be found on Altera s DE2 web pages Observe that the two Bank Address signals are treated by the SOPC Builder as a two bit vector called zs_ba_from_the_sdram 1 0 as seen in Figure 6 However in the DE2_pin_assignments csv file these signals are given as scalars DRAM_BA_I and DRAM_BA_0O Therefore in our Verilog module
80. ded in the project Choose light as the name for both the project and the top level entity as shown in Figure 5 Press Next Since we have not yet created the directory introtutorial Quartus II software displays the pop up box in Figure 6 asking if it should create the desired directory Click Yes which leads to the window in Figure 7 Quartus II x AN Directory D Antrotutorial does not exist Do you want to create it Yes No Figure 6 Quartus II software can create a new directory for the project New Project Wizard Add Files page 2 of 5 Eg Select the design files you want to include in the project Click Add All to add all design files in the project directory to the project Mote you can always add design files to the project later File name ae File name Type Add All Specify the path names of any non default libraries User Libraries g Back Finish Cancel Figure 7 The wizard can include user specified design files 3 The wizard makes it easy to specify which existing files if any should be included in the project Assuming that we do not have any existing files click Next which leads to the window in Figure 8 New Project Wizard Family amp Device Settings p Eg Select the family and device you want to target for compilation Family Cyclone Target device f Auto device selected by the Fitter from the Available devices list Specific device selected in Avai
81. e The Quartus II system includes full support for all of the popular methods of entering a description of the desired circuit into a CAD system This tutorial makes use of the schematic design entry method in which the user draws a graphical diagram of the circuit Two other versions of this tutorial are also available which use the Verilog and VHDL hardware description languages respectively The last step in the design process involves configuring the designed circuit in an actual FPGA device To show how this is done it is assumed that the user has access to the Altera DE2 Development and Education board connected to a computer that has Quartus II software installed A reader who does not have access to the DE2 board will still find the tutorial useful to learn how the FPGA programming and configuration task is performed The screen captures in the tutorial were obtained using the Quartus II version 5 0 if other versions of the software are used some of the images may be slightly different Contents Typical CAD flow Getting started Starting a New Project Schematic Design Entry Compiling the Design Pin Assignment Simulating the Designed Circuit Programming and Configuring the FPGA Device Testing the Designed Circuit Computer Aided Design CAD software makes it easy to implement a desired logic circuit by using a pro grammable logic device such as a field programmable gate array FPGA chip A typical FPGA CAD flow is illustra
82. e Avalon Components Board Unspecified Board iclk External 50 0 H Nios Il Processor Altera a Bridges Device Family Cyclone II i Avalon Tristate Bridg Communication amp Target Module Name Description Input Clock Base con SPI 3 Wire Serial E cpu_0 Nios Il Processor Altera Corporation clk i UART RS 232 serial instruction_master Master port LO D16550 UART with 4 data_master Master port RQ 0 RQ 31 DIZCM 2C Bus interfe jtag_debug_module Slave port 0x00001000 0x000017FF iO DI2CSB I2C Bus Inter onchip_memory_0 On Chip Memory RAM or ROM 0x00000000 0xO00000FFF DSPI Serial Periphera Switches PIO Parallel VO 0x00001800 0x0000180F i H16550S UART CA PIO Parallel VO 0x00001810 0x0000181F H8250 CAST Inc jtag_uart_0 JTAG UART 0x00001820 0x00001827 f 0 H O High Performance Git 4 gt _ Kg IRIE Add check 4 Move Up w Move Down 2 cpu_0 defaulting Reset Address Exception Address to onchip_memory_0O cpu_O The reset address paints to volatile memory Execution of undefined code may occur upon reset 4 Done checking for updates C Crees eevee Figure 3 The Nios II system defined in the introductory tutorial If you saved the lights project then open this project in the Quartus II software and then open the SOPC Builder Otherwise you need to create and implement the project as explained in the intr
83. e Files Other Files Figure 13 Choose to prepare a block diagram 10 Save As x Save in introtutorial eX Fav db Save as type Block Diagram Schematic File bdf Cancel IV Add file to current project Figure 14 Name the file i light bdf Figure 15 Graphic Editor window 3 1 Importing Logic Gate Symbols The Graphic Editor provides a number of libraries which include circuit elements that can be imported into a schematic Double click on the blank space in the Graphic Editor window or click on the icon in the toolbar that looks like an AND gate A pop up box in Figure 16 will appear Expand the hierarchy in the Libraries box as shown in the figure First expand libraries then expand the library primitives followed by expanding the library logic which comprises the logic gates Select and2 which is a two input AND gate and click OK Now the AND gate symbol will appear in the Graphic Editor window Using the mouse move the symbol to a desirable location and click to place it there Import the second AND gate which can be done simply by positioning the mouse pointer over the existing AND gate symbol right clicking and dragging to make a copy of the symbol A symbol in the Graphic Editor window can be moved by clicking on it and dragging it to a new location with the mouse 1 button pressed Next select or2 from the library and import the OR gate into the diagram Then select not and import
84. e the circuit properly but is adequate for tutorial purposes We will use eight 20 ns time intervals to apply the test vectors as shown in Figure 9 The values of signals Reset Sel AddSub A and B are applied at the input pins as indicated in the figure The value of Z at time t is a function of the inputs at time t 1 When Sel 1 the accumulator feedback loop is activated so that the current value of Z rather than A is used to compute the new value of Z Time Reset Sel AddSub A B 0 0 0 54 1850 0 132 63 1904 0 0 69 750 120 0 0 7000 630 O 30000 7630 0 0 37630 pa ee eek a oO O oO Cre CO eS Oo oO 1 0 0 0 0 0 0 0 Figure 9 The required testing behavior The effect of the test vectors in Figure 9 is to perform the following computation to Reset t Z t1 0 to Z t2 A t B t 54 1850 1904 t3 Z t3 A te B t2 132 63 69 t4 Z t4 A t3 F B ts3 i 0 0 ts Z ts A t4 B t4 750 120 630 te Z te Z ts B ts 630 7000 7630 t7 Z t7 Z te B te 7630 30000 37630 overflow Initially the circuit is reset asynchronously Then for two clock cycles the output Z is first the sum and then the difference of the values of A and B at that time This is followed by setting both A and B to zero to clear the contents of register Z Then the accumulator feedback path is tested in the next three clock cycles by performing the computation
85. ect Select File x Look in Si tutorial_Ipm e f amp er db addersubtractor2 v eqaddsub y File name megaddsub v Files of type Design Files tat vhd vhdl av vig h verilc Cancel Zi Figure 14 Specify the megaddsub v file 12 4 Results for the Augmented Design Compile the design and look at the summary which is depicted in Figure 15 Observe that the modified design is implemented in 51 logic elements rather than 52 obtained when using the code in Figure 2 The reduction in the number of logic elements is small because our example is rather simple In more complex designs the advantage of using LPMs is likely to be more pronounced The reason is that the LPMs implement the required logic more efficiently than what the compiler can do from simple Verilog code such as the code in Figure 2 The user should consider using an LPM whenever a suitable one exists Compilation Report Flow Summary EEX 3 Compilation Report 42 Legal Notice Sm Flow Summary Flow Status Successtul Fr Sep 02 17 56 45 2005 SE Flow Settings Quartus Il Version 5 0 Build 168 06 22 2005 SP 1 5J Fullversion amp S ES Flow Elapsed Time Revision Mame addersubtractar 42 Flow Log Toplevel Entity Mame addersubtractorz Analysis amp Synthesis Family Cyclone Il Fitter Device EP2CS5F672C6 3 Assembler Timing Models Preliminary D Timing Analyzer Met timing requirements es Total logic elements Al S21 lt 1 To
86. ed the lights change accordingly We will use the SOPC Builder to design the hardware depicted in Figure 2 Next we will assign the Cyclone II pins to realize the connections between the parallel interfaces and the switches and LEDs which act as I O devices Then we will configure the FPGA to implement the designed system Finally we will use the software tool called the Nios IT Debug Client to assemble download and execute a Nios II program that performs the desired task Doing this tutorial the reader will learn about e Using the SOPC Builder to design a Nios I based system e Integrating the designed Nios II system into a Quartus II project e Implementing the designed system on the DE2 board e Running an application program on the Nios I processor 2 Altera s SOPC Builder The SOPC Builder is a tool used in conjuction with the Quartus II CAD software It allows the user to easily create a system based on the Nios II processor by simply selecting the desired functional units and specifying their parameters To implement the system in Figure 2 we have to instantiate the following functional units e Nios II processor which is referred to as a Central Processing Unit CPU e On chip memory which consists of the memory blocks in the Cyclone II chip we will specify a 4 Kbyte memory arranged in 32 bit words e Two parallel I O interfaces e JTAG UART interface for communication with the host computer To define the desired system start
87. emo interface interface Ty interface interface interface Parallel Serial D i me I O port I O port chip l l lines lines Figure 1 A Nios II system implemented on the DE2 board The Nios II processor and the interfaces needed to connect to other chips on the DE2 board are implemented in the Cyclone IJ FPGA chip These components are interconnected by means of the interconnection network called the Avalon Switch Fabric The memory blocks in the Cyclone II device can be used to provide an on chip memory for the Nios II processor The SRAM SDRAM and Flash memory chips on the DE2 board are accessed through the appropriate interfaces Parallel and serial input output interfaces provide typical I O ports used in computer systems A special JTAG UART interface is used to connect to the circuitry that provides a Universal Serial Bus USB link to the host computer to which the DE2 board is connected This circuitry and the associated software is called the USB Blaster Another module called the JTAG Debug module is provided to allow the host computer to control the Nios II system It makes it possible to perform operations such as downloading programs into memory starting and stopping execution setting breakpoints and collecting real time execution trace data Since all parts of the Nios II system implemented on the FPGA chip are defined by using a hardware descrip tion language a knowledgeable user could write such code to implement a
88. entering 200 ns in the dialog box that pops up Selecting View gt Fit in Window displays the entire simulation range of 0 to 200 ns in the window as shown in Figure 33 You may wish to resize the window to its maximum size 18 AHDL File Block Diagram Schematic File Figure 30 Need to prepare a new file AHDL Include File Block Symbol File Chain Description File Hexadecimal Intel Format File Memory Initialization File Vector Waveform File Figure 31 Choose to prepare a test vector file D light vwf ox 1415ns f Pointer tOns Interval 1315ns Set Ends 14 15 ns Figure 32 The Waveform Editor window 19 light vwf Master Time Bar 14175ns lt gt Pointer 4 8 ns Interval 9 28 ns Start End 120 0 ns 160 0 ns 200 0 ns Name 14 15 ns secececocesscesoceseosoessoosecosesseesseoseesseossessesseesssssod Figure 33 The augmented Waveform Editor window 3 Next we want to include the input and output nodes of the circuit to be simulated Click Edit gt Insert Node or Bus to open the window in Figure 34 It is possible to type the name of a signal pin into the Name box but it is easier to click on the button labeled Node Finder to open the window in Figure 35 The Node Finder utility has a filter used to indicate what type of nodes are to be found Since we are interested in input and output pins set the filter to Pins all Click the List b
89. er connection wires are perfect thus causing no delay in propagation of signals through the circuit This is called functional simulation A more complex alternative is to take all propagation delays into account which leads to timing simulation Typically functional simulation is used to verify the functional correctness of a circuit as it is being designed This takes much less time because the simulation can be performed simply by using the logic expressions that define the circuit 3 1 Functional Simulation To perform the functional simulation select Assignments gt Settings to open the Settings window shown in Figure 15 On the left side of this window click on Simulator to display the window in Figure 16 choose Functional as the simulation mode and click OK The Quartus II simulator takes the inputs and generates the outputs defined in the addersubtractor vwf file Before running the functional simulation it is necessary to create the required netlist which is done by selecting Processing gt Generate Functional Simulation Netlist Settings addersubtractor xi Category o Egge General Files User Libraries Device Timing Requirements amp Options EDA Tool Settings Design Entry Synthesis Simulation Timing Analysis Board Level Formal verification Physical Synthesis Compilation Process Settings Early Timing Estimate Analysis amp Synthesis Settings Fitter Settings Timing Analyzer Design As
90. ere we see the logic expressions produced by the Compiler when synthesizing the designed circuit Observe that f is the output derived as f 71 542 where the sign is used to represent the Exclusive OR operation Obviously the Compiler recognized that the functionality of the circuit in our design file light bdf can be represented by this expression 14 Quartus Il D introtutorial light light Sele File Edit View Project Assignments Processing Tools Window Help a EE dA a A a light bat amp Compilation Report Flow Summary Project Navigator aj xj amp Cyclone ll EP2C35F672C6 ra light bdf 2 light Compilation Report Flow Summary BEA Compilation Report Flow Summary i B Legal Notice EE Flow Summary Flow Status Successful Thu Sep 15 18 07 20 2005 gm Flow Settings Quartus Il Version 5 0 Build 168 06 22 2005 SP 1 SJ Full Version M Flow Elapsed Time Revision Name light 4B Flow Log Top level Entity Name light 4 Analysis amp Synthesis Family Cyclone II gA Fitter Device EP2C35F672C6 GA Assembler Timing Models Preliminary Timing Analyzer Met timing requirements Yes Total logic elements 1 33 216 lt 1 Fitter Total registers 0 PANS Guns Total pins 3 475 lt 1 Timing Analyzer ag 100 Total virtual pins 0 Total memory bits 0 483 840 0 Embedded Multiplier 9 bit elements O 70 0 Total PLLs O 4 0 i Info Longest tpd from source pin x2
91. erformance Git a ET gt SI wsilahla Camnanante E epu_O Exception Address must be at least 0x20 bytes higher than the Reset Address cpu_O Unspecified Reset Address Exception Address eee V Bence ten See fh EE Yaron pga Ba OR Ney mr Apron PCa BREN PN Tinie Genet poy pe A EA 3 Figure 7 The defined processor 6 To specify the on chip memory perform the following Select Avalon Components gt Memory gt On Chip Memory RAM or ROM and click Add In the On Chip Memory Configuration Wizard window shown in Figure 8 set the memory width to 32 bits and the total memory size to 4 Kbytes Do not change the other default settings Click Finish which returns to the System Contents tab as indicated in Figure 9 Block Type ji w Figure 8 Define the on chip memory Altera SOPC Builder nios_system zu cakam We eS TA RN h ep System view Smelt BRNIE ieee i System Contents EPCS Serial Flash Co be Flash Memory Comer H IDT71416 SRAM 1 SDRAM Controller HO AMD 29LV800 Flash O DDR SDRAM Controll Modul iO DDR2 SDRAM Contro E cpu_0 O IDT71 016 SRAM for instruction master LaO Legacy SDRAM Cont data_master 4 Microcontrollers 5 Other CompactFlash Interfa site DMA H Interval timer o Mailbox Figure 9 The on chip memory is included 7 Specify the input parallel I O interface as follows e Select Avalon Com
92. ff You must externally direct the device to restart the configuration process if an error occurs Reset Figure 47 The Options window 28 Device amp Pin Options Dual Purpose Pins Voltage Pin Placement Error Detection CAC General Configuration Frogramming Files Unused Pins Specify the device configuration scheme and the configuration device Configuration scheme Active Serial can use Configuration Device T Configuration mode r Configuration device jw Use configuration device WW Generate compressed bitstreams EPCSE4 Description Species the configuration device that you want to use as the means of configuring the target device Figure 48 Specifying the configuration device The rest of the procedure is similar to the one described above for the JTAG mode Select Tools gt Program mer to reach the window in Figure 43 In the Mode box select Active Serial Programming If you are changing the mode from the previously used JTAG mode the pop up box in Figure 49 will appear asking if you want to clear all devices Click Yes Now the Programmer window shown in Figure 50 will appear Make sure that the Hardware Setup indicates the USB Blaster If the configuration file is not already listed in the window press Add File The pop up box in Figure 51 will appear Select the file light pof in the directory introtutorial and click Open As a result the configuration file light pof will be lis
93. g A Eror Lopate For Help press F1 Figure 11 The Quartus II display for the created project 3 Design Entry Using the Graphic Editor As a design example we will use the two way light controller circuit shown in Figure 12 The circuit can be used to control a single light from either of the two switches x and x2 where a closed switch corresponds to the logic value 1 The truth table for the circuit is also given in the figure Note that this is just the Exclusive OR function of the inputs x and x2 but we will implement it using the gates shown X 5O 5D onma ols re O e lO X2 Figure 12 The light controller circuit The Quartus II Graphic Editor can be used to specify a circuit in the form of a block diagram Select File gt New to get the window in Figure 13 choose Block Diagram Schematic File and click OK This opens the Graphic Editor window The first step is to specify a name for the file that will be created Select File gt Save As to open the pop up box depicted in Figure 14 In the box labeled Save as type choose Block Diagram Schematic File bdf In the box labeled File name type light to match the name given in Figure 5 which was specified when the project was created Put a checkmark in the box Add file to current project Click Save which puts the file into the directory introtutorial and leads to the Graphic Editor window displayed in Figure 15 New xi Device Design Files Softwar
94. g Verilog code Synthesizing a circuit specified in Verilog code Fitting a synthesized circuit into an Altera FPGA Assigning the circuit inputs and outputs to specific pins on the FPGA Simulating the designed circuit e Programming and configuring the FPGA chip on Altera s DE2 board 1 Getting Started Each logic circuit or subcircuit being designed with Quartus II software is called a project The software works on one project at a time and keeps all information for that project in a single directory folder in the file system To begin a new logic circuit design the first step is to create a directory to hold its files To hold the design files for this tutorial we will use a directory introtutorial The running example for this tutorial is a simple circuit for two way light control Start the Quartus II software You should see a display similar to the one in Figure 2 This display consists of several windows that provide access to all the features of Quartus II software which the user selects with the computer mouse Most of the commands provided by Quartus II software can be accessed by using a set of menus that are located below the title bar For example in Figure 2 clicking the left mouse button on the menu named File opens the menu shown in Figure 3 Clicking the left mouse button on the entry Exit exits from Quartus II software In general whenever the mouse is used to select something the left button is used Hence we will not
95. g an unknown value at this time which is indicated by a hashed pattern its value will be determined during simulation Save the file i light vwf 4 Pointer 128 07 ns Interval 128 07 ns Start 40 0 ng 30 0 ns 120 0 ng 160 0 ng a a a a a a a a a a A T t A M a Figure 39 Setting of test values 6 1 Performing the Simulation A designed circuit can be simulated in two ways The simplest way is to assume that logic elements and intercon nection wires in the FPGA are perfect thus causing no delay in propagation of signals through the circuit This is called functional simulation A more complex alternative is to take all propagation delays into account which leads to timing simulation Typically functional simulation is used to verify the functional correctness of a circuit as it is being designed This takes much less time because the simulation can be performed simply by using the logic expressions that define the circuit 6 1 1 Functional Simulation To perform the functional simulation select Assignments gt Settings to open the Settings window On the left side of this window click on Simulator to display the window in Figure 40 choose Functional as the simulation mode and click OK The Quartus II simulator takes the inputs and generates the outputs defined in the light vwf file Before running the functional simulation it is necessary to create the required netlist which is done by se lecting Processing gt Generate
96. h Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services This document is being provided on an as is basis and as an accommodation and therefore all warranties rep resentations or guarantees of any kind whether express implied or statutory including without limitation war ranties of merchantability non infringement or fitness for a particular purpose are specifically disclaimed 1 Quartus IJ Simulation with Verilog Designs This tutorial introduces the basic features of the Quartus II Simulator It shows how the Simulator can be used to assess the correctness and performance of a designed circuit Contents Example Circuit Using the Waveform Editor Functional Simulation Timing Simulation Quartus II software includes a simulator which can be used to simulate the behavior and performance of circuits designed for implementation in Altera s programmable logic devices The simulator allows the user to apply test vectors as inputs to the designed circuit and to observe the outputs
97. h respect to the SDRAM on the DE2 board e Using a phase locked loop PLL to control the clock timing 2 The SDRAM Interface The SDRAM chip on the DE2 board has the capacity of 64 Mbits 8 Mbytes It is organized as 1M x 16 bits X 4 banks The signals needed to communicate with this chip are shown in Figure 2 All of the signals except the clock can be provided by the SDRAM Controller that can be generated by using the SOPC Builder The clock signal is provided separately It has to meet the clock skew requirements as explained in section 5 Note that some signals are active low which is denoted by the suffix N Clock CLK Clock Enable CKE ADDR 11 0 Bank Address 1 BAI Bank Address 0 BAO Chip Select CS_N SDRAM Column Address Strobe CAS _N chip Row Address Strobe RAS N Write Enable WE_N DQ 15 0 SDRAM controller High byte Data Mask UDQM Low byte Data Mask LDQM Figure 2 The SDRAM signals 3 Using the SOPC Builder to Generate the Nios II System Our starting point will be the Nios II system discussed in the Introduction to the Altera SOPC Builder Using Ver ilog Design tutorial which we implemented in a project called lights We specified the system shown in Figure 3 Altera SOPC Builder nios_system SE File Module System View Tools Help System Contents Nios I More cpu_0 Settings System Generation H Altera SOPC Builder 3 ky Create New Component l Clock Source MHz Pipelin
98. he desired circuit in the form of a schematic diagram The last step in the design process involves configuring the designed circuit in an actual FPGA device To show how this is done it is assumed that the user has access to the Altera DE2 Development and Education board connected to a computer that has Quartus II software installed A reader who does not have access to the DE2 board will still find the tutorial useful to learn how the FPGA programming and configuration task is performed The screen captures in the tutorial were obtained using the Quartus II version 5 0 if other versions of the software are used some of the images may be slightly different Contents Typical CAD flow Getting started Starting a New Project Verilog Design Entry Compiling the Design Pin Assignment Simulating the Designed Circuit Programming and Configuring the FPGA Device Testing the Designed Circuit Computer Aided Design CAD software makes it easy to implement a desired logic circuit by using a pro grammable logic device such as a field programmable gate array FPGA chip A typical FPGA CAD flow is illustrated in Figure 1 Design Entry Functional Simulation No Design correct Yes Timing Analysis and Simulation Timing requirements met Yes Programming and Configuration Figure 1 Typical CAD flow The CAD flow involves the following steps e Design Entry the desired circuit is specified either by means of a s
99. hich leads to the window in Figure 8 New Project Wizard Family amp Device Settings p Eg Select the family and device you want to target for compilation Family Cyclone Target device f Auto device selected by the Fitter from the Available devices list Specific device selected in Available devices list Available devices EP2C20F256C6 EP2C20F 2560 Package Ary EP2C20F 25608 Filters Pin count Ary Speed grade Ary EP2C20F 48408 EP2C20F 48418 Core voltage 1 2 W Show Advanced Devices TE EP2CS0F 45406 Advanced Figure 8 Choose the device family and a specific device 4 We have to specify the type of device in which the designed circuit will be implemented Choose Cyclone II as the target device family We can let Quartus II software select a specific device in the family or we can choose the device explicitly We will take the latter approach From the list of available devices choose the device called EP2C35F672C6 which is the FPGA used on Altera s DE2 board Press Next which opens the window in Figure 9 New Project Wizard EDA Tool Settings page 4 of X Specify the other EDA tools in addition to the Quartus Il software used with the project EDA design entry 7 synthesit tool EDA simulation bool EDA timing analysis tool lt Back Finish Cancel Figure 9 Other EDA tools can be specified 5 The user can specify any third party
100. ibed herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published infor mation and before placing orders for products or services This document is being provided on an as is basis and as an accommodation and therefore all warranties rep resentations or guarantees of any kind whether express implied or statutory including without limitation war ranties of merchantability non infringement or fitness for a particular purpose are specifically disclaimed 16 Introduction to the Altera SOPC Builder Using Verilog Design This tutorial presents an introduction to Altera s SOPC Builder software which is used to implement a system that uses the Nios II processor on an Altera FPGA device The system development flow is illustrated by giving step by step instructions for using the SOPC Builder in conjuction with the Quartus II software to implement a simple system The last step in the development process involves configuring the designed circuit in an actual FPGA device and running an application program To show how this is done it is assumed that the user has access to the Altera DE2 Development and Education board connected to a computer that has Quartus II and Nios I software installed The screen captures in the tutorial were obtained using the Quartus II version 5 1 if other versions of the software
101. ick on the button labeled Node Finder to open the window in Figure 37 The Node Finder utility has a filter used to indicate what type of nodes are to be found Since we are interested in input and output pins set the filter to Pins all Click the List button to find the input and output nodes as indicated on the left side of the figure Insert Node or Bus Name Type INPUT Cancel e Value type J Level id Node Finder Radix Binary Bus width hi Start index fo M Display gray code count as binary count Figure 36 The Insert Node or Bus dialogue Node Finder Named f Filter Pins all Customize List ae Look in light IM Include subentities Stop Cancel Modes Found Selected Nodes Assignments gt PIM_AE 22 Output gt E Jlight 1 PIM_N26 Input PIM_N26 Input E Jlighthi2 PIM_N25 Input PIN_N25 Input 3 lightlf PIM_AE 22 Output a lt ja y gt Figure 37 Selecting nodes to insert into the Waveform Editor 22 Click on the x signal in the Nodes Found box in Figure 37 and then click the gt sign to add it to the Selected Nodes box on the right side of the figure Do the same for x2 and f Click OK to close the Node Finder window and then click OK in the window of Figure 36 This leaves a fully displayed Waveform Editor window as shown in Figure 38 If you did not select the nodes in the same order as displayed in Figure 38 it is possible to rearrange the
102. ish Figure 10 Files created by the wizard 3 Augmented Circuit with an LPM We will use the file megaddsub v in our modified design Figure 11 depicts the Verilog code in this file note that we have not shown the comments in order to keep the figure small Adder subtractor module created by the MegaWizard module megaddsub add_sub dataa datab result overflow input add_sub input 15 0 dataa input 15 0 datab output 15 0 result output overflow wire sub_wire0 wire 15 0 sub_wirel wire overflow sub_wire0 wire 15 0 result sub_wirel 15 0 Ipm_add_sub lpm_add_sub_component dataa dataa add_sub add_sub datab datab overflow sub_wireQ result sub_wirel defparam Ipm_add_sub_component lpm_width 16 Ipm_add_sub_component lpm_direction UNUSED Ipm_add_sub_component lpm_type LPM_ADD_SUB Ipm_add_sub_component lpm_hint ONE_INPUT_IS_CONSTANT NO endmodule Figure 11 Verilog code for the ADD_SUB LPM The modified Verilog code for the adder subtractor design is given in Figure 12 Put this code into a file tutorial_lpm addersubtractor2 For convenience the required file addersubtractor2 v is provided in the directory DE2_tutorials design_files which is included on the CD ROM that accompanies the DE2 board and can also be found on Altera s DE2 web pages The differences between this code and Figure 2 are e The assign statements that define the over_flow
103. it register Zreg F F eee Overflow LS ped Zo Figure 1 The adder subtractor circuit The required circuit is described by the Verilog code in Figure 2 For our example we use a 16 bit circuit as specified by n 16 Implement this circuit as follows e Create a project addersubtractor e Include a file addersubtractor v which corresponds to Figure 2 in the project For convenience this file is provided in the directory DE2_tutorials design_files which is included on the CD ROM that accompanies the DE2 board and can also be found on Altera s DE2 web pages e Choose the Cyclone II EP2C35F672C6 device which is the FPGA chip on Altera s DE2 board e Compile the design Top level module module addersubtractor A B Clock Reset Sel AddSub Z Overflow parameter n 16 input n 1 0 A B input Clock Reset Sel AddSub output n 1 0 Z output Overflow reg SelR AddSubR Overflow reg n 1 0 Areg Breg Zreg wire n 1 0 G H M Z wire carryout over_flow Define combinational logic circuit assign H Breg n AddSubR mux2tol multiplexer Areg Z SelR G defparam multiplexer k n adderk nbit_adder AddSubR G H M carryout defparam nbit_adder k n assign over_flow carryout G n 1 H n 1 M n 1 assign Z Zreg Define flip flops and registers always posedge Reset or posedge Clock if Reset 1 begin Areg lt 0 Breg lt 0 Zreg lt 0 Sel
104. itialization File SignalT ap Il File Tel Script File Text File Vector Waveform File Figure 4 Choose to prepare a test vector file 2 The Waveform Editor window is depicted in Figure 5 Save the file under the name addersubtractor vwf note that this changes the name in the displayed window In this figure we have set the desired simulation to run from 0 to 180 ns by selecting Edit gt End Time and entering 180 ns in the dialog box that pops up Selecting View gt Fit in Window displays the entire simulation range of 0 to 180 ns in the window as shown Resize the window to its maximum size addersubtractor vwft Master Time Bar 17 875 ns 4 Pointer 177 64 ns Interval 159 77 ns Start 120 0 ns 160 0 ns H Value at i i ama 17 98 ns 17 875 ns Figure 5 The Waveform Editor window 3 Next we want to include the input and output nodes of the circuit to be simulated Click Edit gt Insert Node or Bus to open the window in Figure 6 It is possible to type the full hierarchical name of a signal pin into the Name box but it is easier to click on the button labeled Node Finder to open the window in Figure 7 The Node Finder utility has a filter used to indicate what type nodes are to be found Since we are interested in input and output pins set the filter to Pins all Click the List button to find the pin names as indicated on the left side of the figure Observe that the input and output signals A B and Z can be
105. k 1 0 F reg k 1 0 F always V or W or Selm if Selm 0 F V else F W endmodule continued in Part b Figure 2 Verilog code for the circuit in Figure 1 Part a k bit adder module adderk carryin X Y S carryout parameter k 8 input k 1 0 X Y input carryin output k 1 0 S output carryout reg k 1 0 S reg carryout always X or Y or carryin carryout S X Y carryin endmodule Figure 2 Verilog code for the circuit in Figure 1 Part b 2 Library of Parameterized Modules The LPMs in the library of parameterized modules are general in structure and they can be configured to suit a spe cific application by specifying the values of various parameters Select Help gt Megafunctions LPM to see a list ing of the available LPMs One of them is an adder subtractor module called pm_add_sub megafunction Select this module to see its description The module has a number of inputs and outputs some of which may be omitted in a given application Several parameters can be defined to specify a particular mode of operation For example the number of bits in the operands is specified in the parameter LPM_WIDTH The LPM_REPRESENTATION parameter specifies whether the operands are to be interpreted as signed or unsigned numbers and so on Tem plates on how an LPM can be instantiated in a hardware description language are given in the description of the module Using these templates is s
106. k Next to continue Figure 2 The driver is found in a specific location The driver is available within the Quartus II software Hence select Install from a specific location and click Next to get to Figure 3 Found New Hardware Wizard Please choose your search and installation options Search for the best driver in these locations Use the check boxes below to limit or expand the default search which includes local paths and removable media The best driver found will be installed C Search removable media floppy CO ROM Include this location in the search D altera quartus50 crivers usb blaster w Don t search will choose the driver to install Choose thie option to select the device driver from a list Windows does not guarantee that the driver you choose will be the best match for your hardware Figure 3 Specify the location of the driver Now choose Search for the best driver in these locations and click Browse to get to the pop up box in Figure 4 Find the desired driver which is at location altera quartus50 drivers usb blaster Click OK and then upon returning to Figure 3 click Next At this point the installation will commence but a dialog box in Figure 5 will appear indicating that the driver has not passed the Windows Logo testing Click Continue Anyway Browse For Folder G qdesignsso E 9 quartwus50 i bin E drivers G i386 G sentinel usb blaster i winz2
107. l Jeteg Bregl4 Breit Aref l ren Overflow regl Overflow regi O vertlow reg0 0 verflow regi Overflow regi Overflow regi Overflow regi Overflow reg Overflow regi Overflow regi Overtlow reg Overflow reg hal Mvertiom ren gt Figure 12 The longest delay paths We have shown how to set the fmax constraint The other constraints depicted in the window in Figure 7 can be set in the same way 4 Timing Simulation Timing simulation provides a graphical indication of the delays in the implemented circuit as can be observed from the displayed waveforms For a discussion of simulation see the tutorial Quartus IT Simulation with Verilog Designs which uses the same addersubtractor circuit as an example 10 Copyright 2005 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending applications mask work rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance wit
108. l Configuration Frogramming Files Unused Pins Specify the device configuration scheme and the configuration device Configuration scheme Active Serial can use Configuration Device T Configuration mode r Configuration device jw Use configuration device WW Generate compressed bitstreams EPCSE4 Description Species the configuration device that you want to use as the means of configuring the target device Figure 46 Specifying the configuration device The rest of the procedure is similar to the one described above for the JTAG mode Select Tools gt Program mer to reach the window in Figure 41 In the Mode box select Active Serial Programming If you are changing the mode from the previously used JTAG mode the pop up box in Figure 47 will appear asking if you want to clear all devices Click Yes Now the Programmer window shown in Figure 48 will appear Make sure that the Hardware Setup indicates the USB Blaster If the configuration file is not already listed in the window press Add File The pop up box in Figure 49 will appear Select the file light pof in the directory introtutorial and click Open As a result the configuration file light pof will be listed in the window This is a binary file produced by the Compiler s Assembler module which contains the data to be loaded into the EPCS16 configuration device The extension pof stands for Programmer Object File Upon returning to the Programmer window
109. l various parts of the board in an easily understandable manner There are also several applications that demonstrate the utility of the DE2 board Traditionally manufacturers of educational FPGA boards have provided a variety of boards and the CAD tools needed to implement designs on these boards However there has been a paucity of supporting materials that could be used directly for teaching purposes Altera s DE2 board is a significant departure from this trend In addition to the DE2 board Altera Corporation provides a full set of associated exercises that can be performed in a laboratory setting for typical courses on logic design and computer organization In effect the DE2 board and the available exercises can be used as a ready to teach platform for such laboratories Of course the DE2 board is also likely to be suitable for exercises that have been developed for other hardware platforms and can be ported to the DE2 platform 3 Installation and USB Blaster Driver The DE2 board is shipped in a package that includes all parts necessary for its operation The only essential parts are the 9 volt power adapter and the USB cable There is also a protective plexiglass cover that may be used in the laboratory environment to protect the board from accidental physical damage Plug in the 9 volt adapter to provide power to the board Use the USB cable to connect the leftmost USB connector the one closest to the power switch on the DE2 board to a US
110. lable devices list Available devices EP2C20F256C6 EP2C20F 2560 Package Ary EP2C20F 25608 Filters Pin count Ary Speed grade Ary EP2C20F 48408 EP2C20F 48418 Core voltage 1 2 W Show Advanced Devices TE EP2CS0F 45406 Advanced Figure 8 Choose the device family and a specific device 4 We have to specify the type of device in which the designed circuit will be implemented Choose Cyclone II as the target device family We can let Quartus II software select a specific device in the family or we can choose the device explicitly We will take the latter approach From the list of available devices choose the device called EP2C35F672C6 which is the FPGA used on Altera s DE2 board Press Next which opens the window in Figure 9 New Project Wizard EDA Tool Settings page 4 of X Specify the other EDA tools in addition to the Quartus Il software used with the project EDA design entry 7 synthesit tool EDA simulation bool EDA timing analysis tool lt Back Finish Cancel Figure 9 Other EDA tools can be specified 5 The user can specify any third party tools that should be used A commonly used term for CAD software for electronic circuits is EDA tools where the acronym stands for Electronic Design Automation This term is used in Quartus II messages that refer to third party tools which are the tools developed and marketed by companies other than Altera Since we will re
111. le manner They include e single stepping through the program e examining the contents of processor registers e examining the contents of the memory e setting breakpoints for debugging purposes e disassembling the downloaded program A description of this software and all of its features is available in the Nios IT Debug Client tutorial 4 2 Using a C Language Program An application program written in the C language can be handled in the same way as the assembly language pro gram A C program that implements our simple task is given in Figure 24 Enter this code into a file called lights c define Switches volatile char OxO001800 define LEDs char 0x0001810 void main while 1 LEDs Switches Figure 24 C language code to control the lights To use this program get to the window in Figure 21 and press Compile amp Load In the dialog box in Figure 22 select the file lights c The rest of the operation is the same as described above Copyright 2006 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerou
112. lected interval and choosing the logic value 1 in the toolbar Make Sel 1 from 100 to 160 ns and AddSub 1 in periods 40 to 60 ns and 80 to 100 ns This should produce the image in Figure 11 T addersubtractor vwf _ Master Time Bar E Pointer Start End 120 0 ne 160 0 ne Value at i i Mame 0 Clock Reset Sel AddSub Bo BA B 000000000 ddodiad 1 IB B OO0000000 HOOOOGOOOGOO00G H 2 BO Overflow Bs Figure 11 Setting of test values for the control signals 5 Vectors can be treated as either octal hexadecimal signed decimal or unsigned decimal numbers The vectors A B and Z are initially treated as binary numbers For our purpose it is convenient to treat them as signed decimal numbers so right click on A and select Properties in the pop up box to get to the window displayed in Figure 12 Choose signed decimal as the radix make sure that the bus width is 16 bits and click OK In the same manner declare that B and Z should be treated as signed decimal numbers General Mame a Type INPUT O Value type Level Radix Signed Decimal Bus width fis Display gray code count as binary count cence Figure 12 Definition of node properties The default value of A is 0 To assign specific values in various intervals proceed as follows Select highlight the interval from 20 to 40 ns and press the Arbitrary Value icon K2 in the
113. lements of vectors SW and LEDG we must refer to them in the same way in the Verilog design file For example in the DE2_pin_assignments csv file the 18 toggle switches are called SW 17 to SW 0 In Verilog code they can also be referred to as a vector SW 17 0 6 Simulating the Designed Circuit Before implementing the designed circuit in the FPGA chip on the DE2 board it is prudent to simulate it to ascertain its correctness Quartus II software includes a simulation tool that can be used to simulate the behavior of a designed circuit Before the circuit can be simulated it is necessary to create the desired waveforms called test vectors to represent the input signals It is also necessary to specify which outputs as well as possible internal points in the circuit the designer wishes to observe The simulator applies the test vectors to a model of the implemented circuit and determines the expected response We will use the Quartus II Waveform Editor to draw the test vectors as follows 1 Open the Waveform Editor window by selecting File gt New which gives the window shown in Figure 30 Click on the Other Files tab to reach the window displayed in Figure 31 Choose Vector Waveform File and click OK 2 The Waveform Editor window is depicted in Figure 32 Save the file under the name light vwf note that this changes the name in the displayed window Set the desired simulation to run from 0 to 200 ns by selecting Edit gt End Time and
114. ly solely on Quartus II tools we will not choose any other tools Press Next 6 A summary of the chosen settings appears in the screen shown in Figure 10 Press Finish which returns to the main Quartus II window but with light specified as the new project in the display title bar as indicated in Figure 11 New Project Wizard Summary page 5 of 5 Eg When you click Finish the project will be created with the following settings Project directory D fintrotutorial Project name Top level design entity Number of files added Number of user libraries added Device assignments Family name Cyclone Il Device EP2C35F672C6 EDA tool Design entm synthesis None gt Simulation None gt Timing analysis None gt lt Back Hert gt Cancel Figure 10 Summary of the project settings Quartus Il D introtutorial light light File Edit View Project Assignments Processing Tools Window Help Doe bed Sew gt RP light PER A AE Project Navigator ajx Cyclone Il EP2C35F672C6 OUARTUS II Version 5 0 http www altera com Critical Warming A Eror Lopate For Help press F1 Figure 11 The Quartus II display for the created project 3 Design Entry Using Verilog Code As a design example we will use the two way light controller circuit shown in Figure 12 The circuit can be used to control a single light from either of the two switches x and
115. m To move a waveform up or down in the Waveform Editor window click on the node name in the Name column and release the mouse button The waveform is now highlighted to show the selection Click again on the waveform and drag it up or down in the Waveform Editor M light vwf Master Time Bar 14 15 ns gt Pointer 35 85 ns Interval 21 7 ns Start End PR 14 15 ns KEKE KKK I N I N IKKE N NIE N IE N IE NE IKK IE N NCE KIKI IE NC I NC I NC IE IKK II IGN gt 4 2 Figure 38 The nodes needed for simulation 4 We will now specify the logic values to be used for the input signals x and x2 during simulation The logic values at the output f will be generated automatically by the simulator To make it easy to draw the desired waveforms the Waveform Editor displays by default vertical guidelines and provides a drawing feature that snaps on these lines which can otherwise be invoked by choosing View gt Snap to Grid Observe also a solid vertical line which can be moved by pointing to its top and dragging it horizontally This reference line is used in analyzing the timing of a circuit move it to the time 0 position The waveforms can be drawn using the Selection Tool which is activated by selecting the icon Is in the toolbar or the Waveform Editing Tool which is activated by the icon Ss To simulate the behavior of a large circuit it is necessary to apply a sufficient number of input valuations and
116. ma separated list of names Pin name s ha Defaultvalue VCC X Cenco Figure 19 Naming of a pin 3 3 Connecting Nodes with Wires The symbols in the diagram have to be connected by drawing lines wires Click on the icon 1 in the toolbar to activate the Orthogonal Node Tool Position the mouse pointer over the right edge of the x1 input pin Click and hold the mouse button and drag the mouse to the right until the drawn line reaches the pinstub on the top input of the AND gate Release the mouse button which leaves the line connecting the two pinstubs Next draw a wire from the input pinstub of the leftmost NOT gate to touch the wire that was drawn above it Note that a dot will appear indicating a connection between the two wires Use the same procedure to draw the remaining wires in the circuit If a mistake is made a wire can be selected by clicking on it and removed by pressing the Delete key on the keyboard Upon completing the diagram click 13 on the icon to activate the Selection and Smart Drawing Tool Now changes in the appearance of the diagram can be made by selecting a particular symbol or wire and either moving it to a different location or deleting it The final diagram is shown in Figure 20 save it fa light bdf Figure 20 The completed schematic diagram 4 Compiling the Designed Circuit The entered schematic diagram file light bdf is processed by several Quartus II tools that analyze the
117. matic entry In this case a message corresponding to each error found will be displayed in the Messages window Double clicking on an error message will highlight the offending part of the circuit in the Graphic Editor window Similarly the Compiler may display some warning messages Their details can be explored in the same way as in the case of error messages The user can obtain more information about a specific error or warning message by selecting the message and pressing the F1 function key To see the effect of an error open the file light bdf Remove the wire connecting the output of the top AND gate to the OR gate To do this click on the b icon click the mouse on the wire to be removed to select it and press Delete Compile the erroneous design by clicking on the icon A pop up box will ask if the changes made to the light bdf file should be saved click Yes After trying to compile the circuit Quartus II software will display a pop up box indicating that the compilation was not successful Acknowledge it by clicking OK The compilation report summary given in Figure 23 now confirms the failed result Expand the Analysis amp Synthesis part of the report and then select Messages to have the messages displayed as shown in Figure 24 Double click on the first error message which states that one of the nodes is missing a source Quartus II software responds by displaying the light bdf schematic and highlighting the OR gate which is affec
118. n The screen captures in the tutorial were obtained using the Quartus II version 5 1 if other versions of the software are used some of the images may be slightly different Contents Example Nios II System The SDRAM Interface Using the SOPC Builder to Generate the Nios H System Integration of the Nios II System into the Quartus II Project Using a Phase Locked Loop The introductory tutorial Introduction to the Altera SOPC Builder Using Verilog Design explains how the memory in the Cyclone II FPGA chip can be used in the context of a simple Nios II system For practical applications it is necessary to have a much larger memory The Altera DE2 board contains an SDRAM chip that can store 8 Mbytes of data This memory is organized as 1M x 16 bits x 4 banks The SDRAM chip requires careful timing control To provide access to the SDRAM chip the SOPC Builder implements an SDRAM Controller circuit This circuit generates the signals needed to deal with the SDRAM chip 1 Example Nios II System As an illustrative example we will add the SDRAM to the Nios II system described in the Introduction to the Altera SOPC Builder Using Verilog Design tutorial Figure 1 gives the block diagram of our example system Host computer USB Blaster Reset_n Clock interface JTAG Debug JTAG UART Nios II processor module interface Avalon switch fabric Switches LEDs parallel input parallel output interface interface SDRAM controller
119. n N26 and output f to pin AE22 which results in the image in Figure 27 To save the assignments made choose File gt Save You can also simply close the Assignment Editor window in which case a pop up box will ask if you want to save the changes to assignments click Yes Recompile the circuit so that it will be compiled with the correct pin assignments Figure 25 The drop down menu displays the input and output names Location 10 Bank I O Standard General Function Special Fun LYTTL O n _ __ PIN Mi O Bank 2 Dedicated Clock CLE1 LYBSCLEOn Input A PIN_M2 I O Bank 2 Dedicated Clock CLEO LYDSCLEOp Input E PIN No lOBank Row I O LYDS31p PIN N25 Dedicated Clock CLE4 LYDSCLE2p Input Io Bank 5 PIN Pi LO Bank 1 Dedicated Clock CLES LYBDSCLE1n Input PIN _P2 LO Bank 1 Dedicated Clock CLE2 LYDSCLE1p Input PIN PS VWoBanki Row Tid LYDSZ6p DPCLEL DOSILICOIL PIN P4 WoBanki Row Tid LYDS26n PIN P WoBanki Row Tid LYDS22n PIN PF WoBank1 Row Tid LYDS22p PIN_FS lOBank Row DO LYDS31n lt Figure 26 The available pins 16 SAssienment Editor Category All Pin A Timing Logic Options l Information This cell specifies the pin name to which you want to make an assignment Soei O xE O pe ke pa pe mes s e o o ome o 4 SEN i fi T al 5 Figure 27 The complete assignment The DE2 board has fixed pin assignments Ha
120. ndow in subsequent projects by checking the box Don t show me this intro duction again Press Next to get the window shown in Figure 5 New Project Wizard Introduction The New Project Wizard helps vou create a new project and preliminary project settings including the Following Project name and directory Name of the top level design entity Project files and libraries Target device family and device EDA tool settings You can change the settings for an existing project and specify additional project wide settings with the Settings command Assignments menu You can use the various pages of the Settings dialog bos to add functionality to the project Dont show me this introduction again tens crea Figure 4 Tasks performed by the wizard New Project Wizard Directory Name Top Level Eg What is the working directory for this project D introtutorial 7 ae What is the name of this project light What is the name of the top level design entity for this project This name it case sensitive and must exactly match the entity name in the design file light ka Use Existing Project Settings Finish Cancel Figure 5 Creation of a new project 2 Set the working directory to be introtutorial of course you can use some other directory name of your choice if you prefer The project must have a name which is usually the same as the top level design entity that will be inclu
121. ngs Finish Cancel Figure 5 Creation of a new project 2 Set the working directory to be introtutorial of course you can use some other directory name of your choice if you prefer The project must have a name which is usually the same as the top level design entity that will be included in the project Choose light as the name for both the project and the top level entity as shown in Figure 5 Press Next Since we have not yet created the directory introtutorial Quartus II software displays the pop up box in Figure 6 asking if it should create the desired directory Click Yes which leads to the window in Figure 7 Quartus II x AN Directory D Antrotutorial does not exist Do you want to create it Yes No Figure 6 Quartus II software can create a new directory for the project New Project Wizard Add Files page 2 of 5 Eg Select the design files you want to include in the project Click Add All to add all design files in the project directory to the project Mote you can always add design files to the project later File name ae File name Type Add All Specify the path names of any non default libraries User Libraries g Back Finish Cancel Figure 7 The wizard can include user specified design files 3 The wizard makes it easy to specify which existing files if any should be included in the project Assuming that we do not have any existing files click Next w
122. ngs Altera SOPC Builder ad Target Be Create New Component oo Nios Il Processor Altera Nee cence jae y Bridges Device Family Hardcopy Compatible Avalon Tristate Bridg a Communication JTAG UART H SPI 3 Wire Serial i UART RS 232 serial Aan iO D16550 UART with 1 data_master TN DI2CM I2C Bus Intertz jtag_debug_module wes 0x00000000 i DI2CSB I2C Bus Inter onchip_memory_0 0x00001000 i ne DSPI Serial Periphera i 0x00000800 i H16550S UART CA P 0x00000810 i H8250 CAST Inc jtag_uart_0 0x00000820 High Performance Git y en lt me Cee Next gt gt Generate Generate Figure 13 The complete system Altera SOPC Builder nios I Seles FS Altera SOPC Builder a Target ob Create New Component Avalon Components Board unsnecfiedGoerd OOOO O i Nios Il Processor Altera EO a ee 5 Bridges Device Family Cyclone IT HardCopy Compatible wa _ Avalon Tristate Bridg k c Communication ERIN ARTE JTAG UART Use Module Name i SPI 3 Wire Serial E cpu_0 ios II Processor Altera aay Ik wA UART RS 232 serial instruction_master Master port SO iO D16550 UART with 1 data_master Master port i RQ O0 RQ 31 iO DI2CM 2C Bus Interfe jtag_debug_module Slave port x00001000 0x000017FF i si DRCSB I2C Bus Inter onchip_memory_0 On Chip Memory RAM or ROM 0x00000000 0x00000FF ve DSPI Serial Periphera i PIO P
123. nless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending applications mask work rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services This document is being provided on an as is basis and as an accommodation and therefore all warranties rep resentations or guarantees of any kind whether express implied or statutory including without limitation war ranties of merchantability non infringement or fitness for a particular purpose are specifically disclaimed 31 Using Library Modules in Verilog Designs This tutorial explains how Altera s library modules can be included in Verilog based designs which are imple mented by using the Quartus II software
124. nnnnnnns nnnnnnnninannnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnn 8E Flow Elapsed Time 2l Worst case tco NAA IE 181 ns Zeal Z 8 orst case t ns e e GB Flow Log 3 Worst case th N A 0 558 Sel Sel BA Analysis amp Synthesis 4 Clock Setup Clock lo 198 ns ng 250 00 MHz period 4 000 ns 263 02 MHz period 3 802 r ne AddSubF Overflow regi ga Fitter Clock Hold Clock it 175 ne 250 oo MHz period 4 000 ns I N A Areglo Zreg E O Assembler fel Total number of failed paths Sa Timing Analyzer SEA Summary SEB Settings SEB Clock Settings Summary BES Clock Setup Clock SEA Clock Hold Clock Bw SEA tro SD ED Messages Figure 8 New timing results If the specified constraint is too high the Quartus II compiler will not be able to satisfy it For example set the jfmax constraint to 300 MHz and recompile the circuit Now the Timing Analyzer Summary will show that this constraint cannot be met as seen in Figure 9 ZCompilation Report 4 Compilation Report s o B Legal Notice BES Flow Summary EB Flow Settings a Flow Elapsed Time H pm Analysis amp Synthesis BA Fitter 9 Assembler Timing Analyzer Summary _ Timing Analyzer 5 Summary Required Actual M A PPABAPABASIBD r ALERE E EEEE HF wiorst caze leu None seg TE Peores 3 All ap z Areg 5 a Worst
125. nother create operation our current user library directories are fg memory compiler pica Parallel Flash Loader fe Signall ap Il Logic Analyzer fa storage IP MegaStore I i f i i i I i k Cancel Back Next gt Finish Figure 5 Choose an LPM from the available library 3 The box in Figure 5 provides a list of the available LPMs Expand the arithmetic sublist and select LPM _ADD_SUB Choose Verilog HDL as the type of output file that should be created The output file must be given a name choose the name megaddsub v and indicate that the file should be placed in the directory tutorial_Ipm as shown in the figure Press Next MegaWizard Plug In Manager LPM_ADD_SUB page 3 of 7 Eg Currently selected device Family Cyclone megaddsub How wide should the dataa and datab input buses be 16 bits Which operating mode do you want for the addersubtractor f Addition only f Subtraction only f Create an add sub input port to allow me to do both 1 adds subtracts Resource Estimate eR 33 lut Documentation Cancel g Back Next gt Finish Figure 6 Specify the size of data inputs 4 In the box in Figure 6 specify that the width of the data inputs is 16 bits Also specify the operating mode in which one of the ports allows performing both addition and subtraction of the input operand under the control of the add_sub input A symbol f
126. nother input is the AddSub control signal which causes Z A B to be performed when AddSub 0 and Z A B when AddSub 1 A second control input Sel is used to select the accumulator mode of operation If Sel 0 the operation Z A B is performed but if Se 1 then B is added to or subtracted from the current value of Z If the addition or subtraction operations result in arithmetic overflow an output signal Overflow is asserted To make it easier to deal with asynchronous input signals they are loaded into flip flops on a positive edge of the clock Thus inputs A and B will be loaded into registers Areg and Breg while Sel and AddSub will be loaded into flip flops SelR and AddSubR respectively The adder subtractor circuit places the result into register Zreg ay Sel B b _ bo AddSub F F Areg areg 4 arego Breg breg _ o is AddSubR n bit 2 to 1 MUX SelR G Sl eee 0 carryout n bit adder carryin W n bit register Zreg F F eee Overflow LS ped Zo Figure 1 The adder subtractor circuit The required circuit is described by the Verilog code in Figure 2 For our example we use a 16 bit circuit as specified by n 16 Implement this circuit as follows e Create a project addersubtractor e Include a file addersubtractor v which corresponds to Figure 2 in the project For convenience this file is provided in the directory DE2_tutorials design_files which is included on the CD ROM that accompanie
127. ns 2reg 3 Z 3 Clock 9 Timing Analyzer 196 ns Zreg b Z 6 Clock SEs Summary 7 173 ng Zreg 0 z 0 Clock ES Settings 7 093 ns Zreq 11 Z 11 Clock SES Clock Settings Summary 7088 ns 2reg 5 z5 Clock Sr Clock Setup Clock TOF na 2reg 10 lt 00 Clock gE tsu 7 068 ne regi 4 an4 Clock gE tco T046 ne regi 3 13 Clock SEs ih 7 046 ne regi iH Clock gD Messages 6 801 ne reg 7 lt m Clock 6 744 ne Zreg 15 15 Clock 6 547 ne Zreg r r Clock Figure 6 The tco delays 3 Specifying Timing Constraints So far we have compiled our Verilog code without indicating to the Quartus II software the required speed per formance of the circuit In the absence of such timing constraints the Quartus II software implements a designed circuit in a good but not necessarily the best way in order to keep the compilation time short If the result does not meet the user s expectations it is possible to specify certain timing constraints that should be met For example suppose that we want our example circuit to operate at a clock frequency of at least 250 MHz rather than the 214 27 MHz as indicated by the value of fmax in Figure 4 To see if this can be achieved we can set the fmax constraint as follows 1 Select Assignments gt Timing Settings to reach the Timing Requirements amp Options window in Figure 7 In this window it is possible to specify the requirements for a number of different parameters 2 In the box Clock
128. number representation The two primary inputs are numbers A an 1 n 2 ao and B by_1bn_2 bo and the primary output is Z z _12 n_2 Zo Another input is the AddSub control signal which causes Z A B to be performed when AddSub 0 and Z A B when AddSub 1 A second control input Sel is used to select the accumulator mode of operation If Sel 0 the operation Z A B is performed but if Sel 1 then B is added to or subtracted from the current value of Z If the addition or subtraction operations result in arithmetic overflow an output signal Overflow is asserted To make it easier to deal with asynchronous input signals they are loaded into flip flops on a positive edge of the clock Thus inputs A and B will be loaded into registers Areg and Breg while Sel and AddSub will be loaded into flip flops Se R and AddSubR respectively The adder subtractor circuit places the result into register Zreg ay Sel B b _ bo AddSub F F Areg areg 4 arego Breg breg _ o is AddSubR n bit 2 to 1 MUX SelR G Sl eee 0 carryout n bit adder carryin W n bit register Zreg F F eee Overflow Z he a Zo Figure 1 The adder subtractor circuit The required circuit is described by the Verilog code in Figure 2 For our example we use a 16 bit circuit as specified by n 16 Implement this circuit as follows e Create a project addersubtractor Include a file addersubtractor v which corresponds to
129. ny part of the system This would be an onnerous and time consuming task Instead one can use the SOPC Builder to implement a desired system simply by choosing the required components and specifying the parameters needed to make each component fit the overall requirements of the system In this tutorial we will illustrate the capability of the SOPC Builder by designing a very simple system The same approach is used to design large systems Host computer USB Blaster Reset_n Clock interface JTAG Debug JTAG UART Nios II processor module interface Avalon switch fabric Switches LEDs parallel input parallel output interface interface SW7 SWO LEDG7 LEDGO Figure 2 A simple example of a Nios II system Our example system is given in Figure 2 The system realizes a trivial task Eight toggle switches on the DE2 board SW 7 0 are used to turn on or off the eight green LEDs LE DGT 0 The switches are connected to the Nios II system by means of a parallel I O interface configured to act as an input port The LEDs are driven by the signals from another parallel I O interface configured to act as an output port To achieve the desired operation the eight bit pattern corresponding to the state of the switches has to be sent to the output port to activate the LEDs This will be done by having the Nios II processor execute a program stored in the on chip memory Continuous operation is required such that as the switches are toggl
130. ny point in the waveform display you may have to turn off the feature View gt Snap on Grid This operation places the reference line at about the 52 8 ns point which indicates that it takes 2 8 ns to load the registers after the rising edge of the clock which occurs at 50 ns The output Z attains its correct value some time after this value has been loaded into Zreg To determine the propagation delay to the output pins drag the reference line to the point where Z becomes valid This can be done more accurately by enlarging the displayed simulation waveforms by using the Zoom Tool Left click on the display to enlarge it and right click to reduce it Enlarge the display so that it looks like the image in Figure 22 After enlarging the image click on the Selection Tool icon Is Position the reference line where Z changes to 1904 which occurs at about 57 2 ns The display indicates that the propagation delay from register Zreg to the output pins Z is 57 2 52 8 4 4 ns It is useful to note that even before we performed this simulation the Quartus II timing analyzer evaluated various delays in the implemented circuit and reported them in the Compilation Report From the Compilation Report we can see that the worst case tco Clock to Output Delay for the Z output pin z3 was estimated as 7 18 ns this delay can be found by zooming into the simulation results at the point where Z changes to the value 7630 Simulation Waveforms Master Time Bar
131. o0o0 fl ith eda To view any subfolders click a plus sign above Figure 4 Browse to find the location Hardware Installation The software you are installing for this hardware Altera USB Blaster has not passed Windows Logo testing to verify its compatibility with Windows P Tell me why this testing iz important Continuing your installation of this software may impair or destabilize the correct operation of pour system either immediately or in the future Microsoft strongly recommends that you stop this installation now and contact the hardware vendor for software that has passed Windows Logo testing Continue Anyway STOP Installation Figure 5 There is no need to test the driver The driver will now be installed as indicated in Figure 6 Click Finish and you can start using the DE2 board Found New Hardware Wizard Completing the Found New Hardware Wizard The wizard has finished installing the software for Altera USB Blaster Click Finish to clase the wizard Back Cancel Figure 6 The driver is installed 4 Using the DE2 Board The DE2 board is used in conjuction with the Quartus II software A reader who is not familiar with this software should read an introductory tutorial There are three versions of the tutorial e Quartus II Introduction Using Verilog Design e Quartus II Introduction Using VHDL Design e Quartus II Introduction Using Schematic Design These tutorials cover the
132. oductory tutorial to obtain the system shown in the figure To add the SDRAM in the window of Figure 3 select Avalon Components gt Memory gt SDRAM Con troller and click Add A window depicted in Figure 4 appears Set the Data Width parameter to 16 bits and leave the default values for the rest Since we will not simulate the system in this tutorial do not select the option Include a functional memory model in the system testbench Click Finish Now in the window of Figure 3 there will be an sdram_0 module added to the design Since there is only one SDRAM on the DE2 board change the name of this module to simply sdram Then the expanded system is defined as indicated in Figure 5 Observe that the SOPC Builder assigned the base address OxOO800000 to the SDRAM Leave the addresses of all modules as assigned in the figure and regenerate the system SDRAM Controller sdram_0O Eg Memory Profile Timing Data Width Architecture Bits Chip Selects Banks Ba Address Widths Ro Column Share Pins via Tristate Bridge Controller shares dq dgmjaddr 1 0 pins Generic Memory Model Simulation Only Include a Functional memory model in the system testbench Memory size 3 MBytes 4194304 x 16 64 MBits Figure 4 Add the SDRAM Controller Altera SOPC Builder nios_system File Module System View Tools Help A i System Contents Nios
133. of Verilog code is sometimes difficult for a designer to remember To help with this issue the Text Editor provides a collection of Verilog templates The templates provide examples of various types of Verilog statements such as a module declaration an always block and assignment statements It is worthwhile to browse through the templates by selecting Edit gt Insert Template gt Verilog HDL to become familiar with this resource 3 2 Adding Design Files to a Project As we indicated when discussing Figure 7 you can tell Quartus II software which design files it should use as part of the current project To see the list of files already included in the light project select Assignments gt Settings which leads to the window in Figure 17 As indicated on the left side of the figure click on the item Files An alternative way of making this selection is to choose Project gt Add Remove Files in Project If you used the Quartus II Text Editor to create the file and checked the box labeled Add file to current project as described in Section 3 1 then the ight v file is already a part of the project and will be listed in the window in Figure 17 Otherwise the file must be added to the project So if you did not use the Quartus II Text Editor then place a copy of the file Jight v which you created using some other text editor into the directory introtutorial To add this file to the project click on the File name button in Figure 17 to get the p
134. omewhat cumbersome so Quartus II software provides a wizard that makes the instantiation of LPMs easy We will use the pm_add_sub module to simplify our adder subtractor circuit defined in Figures 1 and 2 The augmented circuit is given in Figure 3 The pm_add_sub module instantiated under the name megaddsub replaces the adder circuit as well as the XOR gates that provide the input H to the adder Since arithmetic overflow is one of the outputs that the LPM provides it is not necessary to generate this output with a separate XOR gate To implement this adder subtractor circuit create a new directory named tutorial_lpm and then create a project addersubtractor2 Choose the same Cyclone I EP2C35F672C6 device to allow a direct comparison of imple mented designs m i bo AddSub dataa datab megaddsub module add_sub overflow result AddSubR Mo over_flow ES Overflow Z 4 Zo Figure 3 The augmented adder subtractor circuit The new design will include the desired LPM subcircuit specified as a Verilog module that will be instantiated in the top level Verilog design module The Verilog module for the LPM subcircuit is generated by using a wizard as follows 1 Select Tools gt MegaWizard Plug in Manager which leads to a sequence of seven pop up boxes in which the user can specify the details of the desired LPM 2 In the box shown in Figure 4 indicate Create a new custom megafunction variation and click Next Mega
135. onductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services This document is being provided on an as is basis and as an accommodation and therefore all warranties rep resentations or guarantees of any kind whether express implied or statutory including without limitation war ranties of merchantability non infringement or fitness for a particular purpose are specifically disclaimed 14
136. op up window in Figure 18 Select the light v file and click Open The selected file is now indicated in the Files window of Figure 17 Click OK to include the light v file in the project We should mention that in many cases the Quartus II software is able to automatically find the right files to use for each entity referenced in Verilog code even if the file has not been explicitly added to the project However for complex projects that involve many files it is a good design practice to specifically add the needed files to the project as described above Settings light Category General User Libraries Select the design files you want to include in the project Click Add All to add all design files in the project Device directory to the project Timing Requirements amp Options 3 EDA Tool Settings Design Entry Synthesis File name 5 Simulation Timing Analysis File name Type Add All Board Level light Verilog HDL File Formal Verification Remove Physical Synthesis 3 Compilation Process Settings Early Timing Estimate Analysis amp Synthesis Settings Fitter Settings Physical Synthesis Optimizations Timing Analyzer Design Assistant SignalTap Il Logic Analyzer SignalProbe Settings Simulator PowerPlay Power Analyzer Settings Software Build Settings HardCopy Settings Propenies Cenco Z Figure 17 Settings window
137. or the resulting LPM is shown in the top left corner Note that if add_sub 1 then result A B otherwise result A B This interpretation of the control input and the operation performed is different from our original design in Figures 1 and 2 which we have to account for in the modified design Observe that we have included this change in the circuit in Figure 3 Click Next MegaWizard Plug In Manager LPM_ADD_SUB page 4 of 7 Eg megaddsub lz the dataa or datab input bus value a constant f No both values vary C Yes dataa C Yes datab Resource Estimate ae 33 lut Documentation Cancel lt Back Next gt Finish Figure 7 Further specification of inputs 5 In the box in Figure 7 specify that the values of both inputs may vary and click Next MegaWizard Plug In Manager LPM_ADD_SUB page 5 of 7 Eg megaddsub ie Do you want any optional inputs or outputs Input Create a camy borrow out input Outputs Create a camy borrow in output lf Create an overflow output Resource Estimate age 35 lut Documentation Cancel lt Back Next gt Finish Figure 8 Specify the Overflow output 6 The box in Figure 8 allows the designer to indicate optional inputs and outputs that may be specified Since we need the overflow signal make the Create an overflow output choice and press Next MegaWizard Plug In Manager LPM_ADD_SUB page 6 of 7 Eg megaddsub
138. orm Editor M light vwf Master Time Bar 14 15 ns gt Pointer 35 85 ns Interval 21 7 ns Start End PR 14 15 ns KEKE KKK I N I N IKKE N NIE N IE N IE NE IKK IE N NCE KIKI IE NC I NC I NC IE IKK II IGN gt 4 2 Figure 36 The nodes needed for simulation 4 We will now specify the logic values to be used for the input signals x and x2 during simulation The logic values at the output f will be generated automatically by the simulator To make it easy to draw the desired waveforms the Waveform Editor displays by default vertical guidelines and provides a drawing feature that snaps on these lines which can otherwise be invoked by choosing View gt Snap to Grid Observe also a solid vertical line which can be moved by pointing to its top and dragging it horizontally This reference line is used in analyzing the timing of a circuit move it to the time 0 position The waveforms can be drawn using the Selection Tool which is activated by selecting the icon Is in the toolbar or the Waveform Editing Tool which is activated by the icon Ss To simulate the behavior of a large circuit it is necessary to apply a sufficient number of input valuations and observe the expected values of the outputs In a large circuit the number of possible input valuations may be huge so in practice we choose a relatively small but representative sample of these input valuations However for our tiny circuit we can sim
139. pll_wavetorms html Sample waveforms in summary i edram_pllwave jpg Sample waveform file s Documentation Cancel lt Back e Frish Figure 15 The summary page The desired PLL circuit is now defined as a Verilog module in the file sdram_pll v which is placed in the project directory Add this file to the lights project Figure 16 shows the module ports consisting of signals inclkO and cO sdram_pll v module sdram pll inclko cOj input inclkdo output co wire 5 0 sub wired wire 0 0 sub wire4 1 ho wire 0 0 sub wirel Sub wireO O 0 wire cO sub wirel wire sub wirez inclkd wire 1 0 Sub wires Sub wire4t sub wiree Figure 16 The generated PLL module Next we have to fix the top level Verilog module given in Figure 7 to include the PLL circuit The desired code is shown in Figure 17 The PLL circuit connects the shifted clock output c0 to the pin DRAM_CLK 12 Implements the augmented Nios II system for the DE2 board Inputs SW7 0 are parallel port inputs to the Nios II system CLOCK_50 is the system clock KEYO is the active low system reset Outputs LEDG7 0 are parallel port outputs from the Nios II system SDRAM ports correspond to the signals in Figure 2 their names are those used in the DE2 User Manual module lights SW KEY CLOCK_50 LEDG DRAM_CLK DRAM_CKE DRAM_ADDR DRAM_BA_1 DRAM_BA_0 DRAM_CS_N DRAM_CAS_N DRAM _RAS_N DR
140. ponents gt Other gt PIO Parallel I O and click Add to reach the PIO Config uration Wizard in Figure 10 e Specify the width of the port to be 8 bits and choose the direction of the port to be Input as shown in the figure e Click Finish to return to the System Contents tab as given in Figure 11 Avalon PIO pio_0 Basic Settings Input Options Simulation Figure 10 Define a parallel input interface Altera SOPC Builder nios_system HO IDT71 016 SRAM for O Legacy SDRAM Cont Microcontrollers Other be CompactFlash Interfa i ad DMA oe interval timer instruction_master SS SNR data_master N RQ O jag debug _t module ave SSS 0x00000000 Se DMA Controller Eur 5 PCI g Toonas Figure 11 The parallel input interface is included 8 In the same way specify the output parallel I O interface e Select Avalon Components gt Other gt PIO Parallel I O and click Add to reach the PIO Config uration Wizard again e Specify the width of the port to be 8 bits and choose the direction of the port to be Output e Click Finish to return to the System Contents tab 9 We wish to connect to a host computer and provide a means for communication between the Nios II system and the host computer This can be accomplished by instantiating the JTAG UART interface as follows e Select Avalon Components gt Communication gt JTAG UART and click Add to reach the JTAG UART Configur
141. r lt lt Copy feo 11 84 00 50 00 Clock phase shift 3 ins Clock duty cycle Boo H More Details gt gt Quick Navigation CoO Ci C2 Documentation Cancel lt Back Ment gt Finish Figure 14 Specify the phase shift 5 The shifted clock signal is called c0 Specify that the output clock frequency is 50 MHz Also specify that a phase shift of 3 ns is required as indicated in the figure Click Finish which advances to page 9 6 In the summary window in Figure 15 click Finish to complete the process 1 MegaWizard Plug In Manager ALTPLL page 9 of 9 Summary When the Finish button is pressed the MegaWizard Plug In Manager will create the checked files in the following list You may choose to include or exclude a file by checking or unchecking its coresponding checkbox respectively The state of checkboxes will be remembered for the next MegaWizard Plug In Manager session sdram_pll The Megawizard Plug In Manager will create these files in the directory DADE sdram_tutorial inclkO frequency 40 000 MHz x File Description Operation iode Monmal m fet sdram_pll v Variation file Cik Ratio Ph tdg J OC C4 O sdram_plline AHEL Include file Peo 1 54 00 50 00 O adram_pl cmp WHOL Component declaration file O adram_pll bsf Quartus symbol file O sdram_pll_inst y lnstantiation template file O edram_pll_bb y Verilog Black Box declaration file Lf sdram_
142. re located below the title bar For example in Figure 2 clicking the left mouse button on the menu named File opens the menu shown in Figure 3 Clicking the left mouse button on the entry Exit exits from Quartus II software In general whenever the mouse is used to select something the left button is used Hence we will not normally specify which button to press In the few cases when it is necessary to use the right mouse button it will be specified explicitly Quartus Il File Edit View Project Assignments Processing Tools Window Help Project Navigator Entity d Compilation Hierarchy QUARTUS II dp Hierarchy E Files d Design Units Version 5 0 Status http www altera com Estra Info Critical waming A Eror Message t Location r Locate For Help press F1 ih a Idle 5 essages x Figure 2 The main Quartus II display 5 Quartus II File Edit View Project Assignment O New Ctl n Open chl o Close Cirl F4 L New Project Wizard Open Project Ctrl Convert MAX PLUS II Project Save Project Close Project led Save Grits Gave As Save Current Report Section As Eile Properties Create Update Export Convert Programming Files Ri Page Setup E Print Preview ee Print Cri P Recent Files Recent Projects Exit Alt F4 Figure 3 An example of the File menu For some commands it is necessa
143. rilog VHDL Cancel Figure 4 Create a new Nios II system 3 Figure 5 displays the System Contents tab of the SOPC Builder which is used to add components to the system and configure the selected components to meet the design requirements The available components are listed on the left side of the window Before choosing our components examine the area in the figure labeled Target A drop down list is provided that allows some available Altera boards to be selected It is not necessary to select a board and since the DE2 board is not included in the list leave the selection as Unspecified board Next check the setting for the Device Family and ensure that Cyclone II is selected 4 The Nios II processor runs under the control of a clock For this tutorial we will make use of the 50 MHz clock that is provided on the DE2 board As shown in Figure 5 it is possible to specify the names and frequency of clock signals in the SOPC Builder display If not already included in this list specify a clock named clk with the source designated as External and the frequency set to 50 0 MHz E Altera SOPC Builder nios_system il System Generation E Altera SOPC Builder tagt i ty Create New Component B Clock Source MHz Pipeline Avalon Components Board Unspecified Board il ick lExternal 50 0 Nios Il Processor Altera an click ta add t Bridges Device Family Cyclone m W 1o he Avalon Tristate
144. rocessing started Wed Apr 19 17 32 56 2006 Info Command quartus sh t nios system setup quartus tecl Info Evaluation of Tel script nios system setup quartus tcel was successful Info Quartus II Shell was successful O errors O warnings Info Processing ended Wed Apr 19 17 32 57 2006 Info Elapsed time 00 00 01 2006 04 19 17 32 57 Completed generation for system nios system 2006 04 19 17 32 57 THE FOLLOWING SYSTEM ITEMS HAVE BEEN GENERATED SOPC Builder database D sope builder tutorial nios system ptf System HDL Model D sope builder tutorial nios system v system Generation Script D sope builder tutorial nios system generation script 2006 04 19 17 32 57 SUCCESS SYSTEM GENERATION COMPLETED Press Exit to exit JE cpu_0 was generated as plain text HDL cpu_0 The reset address points to volatile memory Execution of undefined code may occur upon reset J Done checking for updates Figure 15 Generation of the system Changes to the designed system are easily made at any time by reopening the SOPC Builder tool Any com ponent in the System Contents tab of the SOPC Builder can be selected and deleted or a new component can be added and the system regenerated 3 Integration of the Nios II System into a Quartus IT Project To complete the hardware design we have to perform the following e Instantiate the module generated by the SOPC Builder into the Quartus II project e Assign the
145. rom the system Many commands can be invoked by clicking on an icon displayed in one of the toolbars To see the command associated with an icon position the mouse over the icon and a tooltip will appear that displays the command name 1 1 Quartus IT Online Help Quartus II software provides comprehensive online documentation that answers many of the questions that may arise when using the software The documentation is accessed from the menu in the Help window To get some idea of the extent of documentation provided it is worthwhile for the reader to browse through the Help menu For instance selecting Help gt How to Use Help gives an indication of what type of help is provided The user can quickly search through the Help topics by selecting Help gt Search which opens a dialog box into which key words can be entered Another method context sensitive help is provided for quickly finding documentation for specific topics While using most applications pressing the F1 function key on the keyboard opens a Help display that shows the commands available for the application 2 Starting a New Project To start working on a new design we first have to define a new design project Quartus II software makes the designer s task easy by providing support in the form of a wizard Create a new project as follows 1 Select File gt New Project Wizard to reach the window in Figure 4 which indicates the capability of this wizard You can skip this wi
146. ry to access two or more menus in sequence We use the convention Menu1 gt Menu2 gt Item to indicate that to select the desired command the user should first click the left mouse button on Menu1 then within this menu click on Menu2 and then within Menu2 click on Item For example File gt Exit uses the mouse to exit from the system Many commands can be invoked by clicking on an icon displayed in one of the toolbars To see the command associated with an icon position the mouse over the icon and a tooltip will appear that displays the command name 1 1 Quartus IT Online Help Quartus II software provides comprehensive online documentation that answers many of the questions that may arise when using the software The documentation is accessed from the menu in the Help window To get some idea of the extent of documentation provided it is worthwhile for the reader to browse through the Help menu For instance selecting Help gt How to Use Help gives an indication of what type of help is provided The user can quickly search through the Help topics by selecting Help gt Search which opens a dialog box into which key words can be entered Another method context sensitive help is provided for quickly finding documentation for specific topics While using most applications pressing the F1 function key on the keyboard opens a Help display that shows the commands available for the application 2 Starting a New Project To start working on a new
147. s the DE2 board and can also be found on Altera s DE2 web pages e Choose the Cyclone II EP2C35F672C6 device which is the FPGA chip on Altera s DE2 board e Compile the design Top level module module addersubtractor A B Clock Reset Sel AddSub Z Overflow parameter n 16 input n 1 0 A B input Clock Reset Sel AddSub output n 1 0 Z output Overflow reg SelR AddSubR Overflow reg n 1 0 Areg Breg Zreg wire n 1 0 G H M Z wire carryout over_flow Define combinational logic circuit assign H Breg n AddSubR mux2tol multiplexer Areg Z SelR G defparam multiplexer k n adderk nbit_adder AddSubR G H M carryout defparam nbit_adder k n assign over_flow carryout G n 1 H n 1 M n 1 assign Z Zreg Define flip flops and registers always posedge Reset or posedge Clock if Reset 1 begin Areg lt 0 Breg lt 0 Zreg lt 0 SelR lt 0 AddSubR lt 0 Overflow lt 0 end else begin Areg lt A Breg lt B Zreg lt M SelR lt Sel AddSubR lt AddSub Overflow lt over_flow end endmodule k bit 2 to 1 multiplexer module mux2tol V W Selm F parameter k 8 input k 1 0 V W input Selm output k 1 0 F reg k 1 0 F always V or W or Selm if Selm 0 F V else F W endmodule continued in Part b Figure 2 Verilog code for the circuit in Figure 1 Part a k bit
148. s U S and foreign patents and pending applications mask work rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services This document is being provided on an as is basis and as an accommodation and therefore all warranties rep resentations or guarantees of any kind whether express implied or statutory including without limitation war ranties of merchantability non infringement or fitness for a particular purpose are specifically disclaimed 19 Using the SDRAM Memory on Altera s DE2 Board with Verilog Design This tutorial explains how the SDRAM chip on Altera s DE2 Development and Education board can be used with a Nios II system implemented by using the Altera SOPC Builder The discussion is based on the assumption that the reader has access to a DE2 board and is familiar with the material in the tutorial Introduction to the Altera SOPC Builder Using Verilog Desig
149. se F W endmodule Figure 12 Verilog code for the circuit in Figure 3 1 To include the megaddsub v file in the project select Project gt Add Remove Files in Project to reach the window in Figure 13 The file addersubtractor2 v should already be listed as being included in the project Browse for the other files by clicking the button File name to reach the window in Figure 14 Select the file megaddsub v and click Open which returns to the window in Figure 13 Click Add to include the file and then click OK Now the modified design can be compiled and simulated in the usual way Settings addersubtractor2 Category General Files User Libraries Select the design files you want to include in the project Click Add All to add all design files in the project Device directory to the project Timing Requirements amp Options EDA Tool Settings Design Entry Synthesis File name E Add Simulation Timing Analysis Add All Board Level addersubtractor2 v Verilog HDL File Formal Verification Remove Physical Synthesis Compilation Process Settings Up Early Timing Estimate Analysis amp Synthesis Settings Down Fitter Settings Physical Synthesis Optimizations Properties Timing Analyzer Design Assistant SignalTap Il Logic Analyzer SignalProbe Settings Simulator PowerPlay Power Analyzer Settings H Software Build Settings HardCopy Settings Figure 13 Inclusion of the new file in the proj
150. selected either as individual nodes denoted by bracketed subscripts or as 16 bit vectors which is a more convenient form Insert Node or Bus Type INPUT Cancel Value type 9 Level S Node Finder Radix Binary Bus width fi Start index fo I Display gray code count as binary count Figure 6 The Insert Node or Bus dialogue Named i Filter Pins all Customize List os Look jaddersubtractor E V Include subentities Stop Cancel Nodes Found Selected Nodes Name Assignments Type Creator Name Assignments Type w AddSub Unassigned Input User entere i gt addersubtractor Clock Unassigned Input DB Unassigned Input Group User entere w addersubtractor Reset Unassigned Input gt B 0 Unassigned Input User entere o gt addersubtractor Sel Unassigned Input Pp 1 Unassigned Input User entere w addersubtractor AddSub Unassigned Input B 2 Unassigned Input User entere E addersubtractor A Unassigned Input Group mB 3 Unassigned Input User entere E addersubtractor B Unassigned Input Group B 4 Unassigned Input User entere gt addersubtractor Z Unassigned Output Groug mp5 Unassigned Input User entere addersubtractor Overflow Unassigned Output gt p 6 Unassigned Input User entere Ea mB 7 Unassigned Input User entere mp8 Unassigned Input User entere ea ipl Unassigned Input User entere B 10 Unassigned Input User entere l mB 11 Unassigned Inpu
151. signals SelR AddSubR Areg Breg and Zreg Open the addersubtractor vwf file and activate the Node Finder window as done for Figure 6 The filter in Figure 6 specified Pins all There are several other choices To find the registered signals set the filter to Registers post fitting and press List Figure 18 shows the result Select the signals SelR AddSubR Areg Breg and Zreg for inclusion in the addersubtractor vwf file and specify that Areg Breg and Zreg have to be displayed as signed decimal numbers thus obtaining the display in Figure 19 Save the file and simulate the circuit using these waveforms which should produce the result shown in Figure 20 Node Finder Eq Named i Filter Registers posttitting Customize List p Look Jacdersubtractor E V Include subentities Cancel Nodes Found Selected Nodes Name Assignments Type Name Assignments Sia a Creator J Figure 18 Finding the registered signals 13 W AddSubR Unassigned Registered User ente addersubtractor SelR Unassigned Registered Areg Unassigned Registered User ente addersubtractor AddSubR Unassigned Registered Areg O Unassigned Registered User ente amp addersubtractor Areg Unassigned Registered Areg 1 Unassigned Registered User ente a gt addersubtractor Breg Unassigned Registered Areg 2 Unassigned Registered User ent amp addersubtractor Zreg Unassigned Registered Areg 3
152. sistant SignalT ap Il Logic Analyzer SignalProbe Settings Simulator Power Analyzer Settings Software Build Settings HardCopy Settings Select the design files you want to include in the project Click Add All to add all design files in the project directory to the project File name Add Add All File name addersubtractor v Verilog HDL File Remove Up Down Properties OK Cancel Figure 15 Settings window 4 Settings addersubtractor xi Category General Files User Libraries Device Timing Requirements amp Options EDA Tool Settings Design Entry Synthesis Simulation Timing Analysis Board Level Formal Verification Physical Synthesis Compilation Process Settings Early Timing Estimate Analysis amp Synthesis Settings Fitter Settings Timing Analyzer Design Assistant SignalTap Il Logic Analyzer SignalProbe Settings Simulator Power Analyzer Settings Software Build Settings HardCopy Settings Select options for simulation Note the availability of some options depends on the current device family Simulation mode mme Simulation input A Simulation period Run simulation until all vector stimuli are used C End simulation at ns M Automatically add pins to simulation output waveforms T Check outputs M Setup and hold time violation detection F Glitch detection Simulation coverage reporting M Overwrite sim
153. software can also be used 1 Example Circuit Timing issues are most important in circuits that involve long paths through combinational logic elements with registers at inputs and outputs of these paths As an example we will use the adder subtractor circuit shown in Figure 1 It can add subtract and accumulate n bit numbers using the 2 s complement number representation The two primary inputs are numbers A ayjn_ 1Gn_2 ao and B b _1by_2 bo and the primary output is Z Zn 1 n 2 Zo Another input is the AddSub control signal which causes Z A B to be performed when AddSub 0 and Z A B when AddSub 1 A second control input Sel is used to select the accumulator mode of operation If Sel 0 the operation Z A B is performed but if Sel 1 then B is added to or subtracted from the current value of Z If the addition or subtraction operations result in arithmetic overflow an output signal Overflow is asserted To make it easier to deal with asynchronous input signals they are loaded into flip flops on a positive edge of the clock Thus inputs A and B will be loaded into registers Areg and Breg while Sel and AddSub will be loaded into flip flops Se R and AddSubR respectively The adder subtractor circuit places the result into register Zreg ay Sel B b _ bo AddSub F F Areg areg 4 arego Breg breg _ o is AddSubR n bit 2 to 1 MUX SelR G Sl eee 0 carryout n bit adder carryin W n b
154. ssful Tue Jul 12 16 13 37 2005 gm Flow Settings Buertis Il Version SA Build 168 06 22 2005 SP 1 SJ Full Full Compilation 100 gE Flow Elapsed Time Revision Name light Analysis amp Synthesis amp B Flow Log Top level Entity Name light Fitter SD Analysis amp Synthesis Cyclone II i Assembler 5 8a Fitter Device EP2C35F672C6 Timing Analyzer 00 8a Assembler Timing Models Preliminary Timing Analyzer Met timing requirements Yes Total logic elements 1 33 216 lt 1 Total registers 0 2 Info Longest tpd from source pin x2 to destination pin f is 5 158 ns 2 Info Quartus Il Timing Analyzer was successful 0 errors 0 warmings i Dy eT FS m RE ERE T E AE a EE Foy EERE E E Wp HAORA fa aor Processing Extra Info Message 0 of 95 t Location For Help press F1 hea Idle f Figure 19 Display after a successful compilation 13 When the compilation is finished a compilation report is produced A window showing this report is opened automatically as seen in Figure 19 The window can be resized maximized or closed in the normal way and it can be opened at any time either by selecting Processing gt Compilation Report or by clicking on the icon The report includes a number of sections listed on the left side of its window Figure 19 displays the Compiler Flow Summary section which indicates that only one logic element and three pins are needed
155. t User entere iB 12 Unassigned Input User entere wB 13 Unassigned Input User entere B 14 Unassigned Input User entere wB 15 Unassigned Input User entere w Clock Unassigned Input User ls gt Figure 7 Selecting nodes to insert into the Waveform Editor Use the scroll bar inside the Nodes Found box in Figure 7 to find the Clock signal Click on this signal and then click the gt sign in the middle of the window to add it to the Selected Nodes box on the right side of the figure Do the same for Reset Sel and AddSub Then choose vectors A B and Z as well as the output Overflow in the same way Several nodes can be selected simultaneously in a standard Windows manner Click OK to close the Node Finder window and then click OK in the window of Figure 6 This leaves a fully displayed Waveform Editor window as shown in Figure 8 If you did not select the nodes in the same order as displayed in Figure 8 it is possible to rearrange them To move a waveform up or down in the Waveform Editor window click on the node name in the Name column and release the mouse button The waveform is now highlighted to show the selection Click again on the waveform and drag it up or down in the Waveform Editor addersubtractor vwt Master Time Bar 17 875 ns 4 Pointer 179 66 ns Interval 161 79 ns Start O pe 40 0 n 30 0 n 1200 n 1600 n 17 875 ns BO E OOOO00000 E OOOOO0000 BAA Bs OOOOUOOO00000000 Q
156. t bdf Figure 25 Identifying the location of the error 5 Pin Assignment During the compilation above the Quartus II Compiler was free to choose any pins on the selected FPGA to serve as inputs and outputs However the DE2 board has hardwired connections between the FPGA pins and the other components on the board We will use two toggle switches labeled SWo and S W4 to provide the external inputs x1 and 2 to our example circuit These switches are connected to the FPGA pins N25 and N26 respectively We will connect the output f to the green light emitting diode labeled LE DGo which is hardwired to the FPGA pin AE22 Assignment Editor Jopm r all fc Pin Timing Logic Options Show assignments for specific nodes 0O Check All Uncheck All Delete All Information This cell specifies the pin name to which you want to make an assignment gt Double click to creal Category Figure 26 The Assignment Editor window Pin assignments are made by using the Assignment Editor Select Assignments gt Pins to reach the window in Figure 26 Under Category select Pin Double click on the entry lt lt new gt gt which is highlighted in blue in the column labeled To The drop down menu in Figure 27 will appear Click on x1 as the first pin to be assigned this will enter x1 in the displayed table Follow this by double clicking on the box to the right of this new x1 17 entry in the column
157. t the program contains a statement that includes the nios_macros and two statements GFUNC and BREAK needed to assemble the program properly 15 include nios_macros s equ Switches 0x00001800 equ LEDs 0x00001810 GFUNC _ start movia r2 Switches movia r3 LEDs loop Idbio r4 0 r2 stbio r4 0 r3 br loop BREAK Figure 19 Assembly language code to control the lights Enter this code into a file lights s and place the file into a working directory We placed the file into direc tory sopc_builder_tutorial app_software The program has to be assembled and converted into an S Record file lights srec suitable for downloading into the implemented Nios II system Altera provides the monitor software called Nios I Debug Client for use with the DE2 board This software provides a simple means for compiling assembling and downloading of programs into a Nios II system imple mented on a DE2 board It also makes it possible for the user to perform debugging tasks A description of this software is available in the Nios II Debug Client tutorial Open the Nios II Debug Client which leads to the window in Figure 20 This software needs to know the characteristics of the designed Nios II system which are given in the ptf file lights ptf Select the file lights ptf as indicated in the figure Note that this file is in the design directory sopc_builder_tutorial The Nios II Debug Client also needs to know where to load the application
158. tal registers F Total pins Barli Total virtual pins T Total memory bits O 483 640 0 Embedded Multiplier 9 bit elements O fO 0 Total PLL Of4 02 Figure 15 Compilation Results for the Augmented Circuit Copyright 2005 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending applications mask work rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any informa tion product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published infor mation and before placing orders for products or services This document is being provided on an as is basis and as an
159. ted by the error as shown in Figure 25 Correct the error and recompile the design Compilation Report Flow Summary i Compilation Report 48 Legal Notice lt a Sr Flow Summary Flow Status Flow Failed Fri Sep 16 18 03 35 2005 sm Flow Settings Quartus Il Version 5 0 Build 168 06 22 2005 SP 1 SJ Full version EES Flow Elapsed Time Revision Name light Flow Log Top level Entity Hame light 0 Analysis amp Synthesis Family Cyclone Il Device EP2C35F672C6 Timing Models Preliminary Met timing requirements M A Figure 23 Compilation report for the failed design Compilation Report lt 4 Compilation Report Analysis amp Synthesis Messages amp B Legal Notice ED Inf 722a FS Flow Summary i Info Running Quartus Il Analysis amp Synthesis gm Flow Settings Info Command quartus_map import_settings_files on export_settings_files 5m Flow Elapsed Time H 42 Info Found 1 design units including 1 entities in source file light bdf 5B Flow Log amp Warning Primitive AND2 of instance inst not used a amp Warning Primitive NOT of instance inst4 not used gj Analysis amp Synthesis Error Node inst2 is missing source ri asda Error Quartus Il Analysis amp Synthesis was unsuccessful 1 error 2 warnings O 2etongs am Source Files Read gt 4 Message 0of13 Location gi Messages Figure 24 Error messages 16 i ligh
160. ted in Figure 1 Design Entry Functional Simulation No Design correct Yes Timing Analysis and Simulation Timing requirements met Yes Programming and Configuration Figure 1 Typical CAD flow The CAD flow involves the following steps e Design Entry the desired circuit is specified either by means of a schematic diagram or by using a hardware description language such as Verilog or VHDL e Synthesis the entered design is synthesized into a circuit that consists of the logic elements LEs provided in the FPGA chip e Functional Simulation the synthesized circuit is tested to verify its functional correctness this simulation does not take into account any timing issues e Fitting the CAD Fitter tool determines the placement of the LEs defined in the netlist into the LEs in an actual FPGA chip it also chooses routing wires in the chip to make the required connections between specific LEs e Timing Analysis propagation delays along the various paths in the fitted circuit are analyzed to provide an indication of the expected performance of the circuit e Timing Simulation the fitted circuit is tested to verify both its functional correctness and timing e Programming and Configuration the designed circuit is implemented in a physical FPGA chip by pro gramming the configuration switches that configure the LEs and establish the required wiring connections This tutorial introduces the
161. ted in the window This is a binary file produced by the Compiler s Assembler module which contains the data to be loaded into the EPCS16 configuration device The extension pof stands for Programmer Object File Upon returning to the Programmer window click on the Program Configure check box as shown in Figure 52 Quartus II x IN Some devices in current device list cannot be added to selected programming mode Active Serial Programming Do you want to clear all devices in current device list and switch to selected mode Yes No Figure 49 Clear the previously selected devices 29 ieni ga Hardware Setup 15B Blaster 056 0 Mode Active Serial Programming Progress O va e pe feon dd git Stop eg Auto Detect 1 Delete Gay Add File i Change File Get Save File GH Add Device Up Figure 50 The Programmer window with Active Serial Programming selected Select Programming File Look in E introtutorial E cb File name Jiight pot Files of type POF Files pof Cancel p Figure 51 Choose the configuration file ienie ga Hardware Setup USB Blaster 056 0 Mode Active Serial Programming Progress Oz pel Start CE File Device Checksum Usercode Faerie Vert Blar Examine al a gt Mee _ t Misie eu pof ia it Auto Detect Delete Ea Add File ie Change File Let Save File BaF Add Device Fig
162. the Quartus II software and perform the following steps 1 Create a new Quartus II project for your system As shown in Figure 3 we stored our project in a directory called sopc_builder_tutorial and we assigned the name lights to both the project and its top level design entity You can choose a different directory or project name but be aware that the SOPC Builder software does not permit the use of spaces in file names For example an attempt to use a directory name sopc builder tutorial would lead to an error In your project choose the EP2C35F672C6 chip as the target device because this is the FPGA on the DE2 board 2 Select Tools gt SOPC Builder which leads to the pop up box in Figure 4 Enter nios_system as the system name this will be the name of the system that the SOPC Builder will generate Choose Verilog as the target HDL in which the system module will be specified Click OK to reach the window in Figure 5 New Project Wizard Directory Name Top Level Entity page 1 of 5 x What is the working directory for this project D sope_builder_tutoria ane What is the name of this project What is the name of the top level design entity for this project This name it case sensitive and must exactly match the entity name in the design file Use Existing Project Settings Hegt gt Finish Cancel Figure 3 Create a new project I Create New System System Mame nios system Target HOL Ve
163. the other components on the board We will use two toggle switches labeled SWo and SW to provide the external inputs x and 2 to our example circuit These switches are connected to the FPGA pins N25 and N26 respectively We will connect the output f to the green light emitting diode labeled LE DGo which is hardwired to the FPGA pin AE22 15 2 Assignment Editor BEEJ l category Sme ae al Pno Timing Logic Options Information This cell specifies the pin name to which you wank to make an assignment gt Double click to create a new assignment xlv oo feo in 10 Bank IO Standard General Function Special Function o d y D TEA gt D EWA gt Figure 24 The Assignment Editor window Pin assignments are made by using the Assignment Editor Select Assignments gt Pins to reach the window in Figure 24 Under Category select Pin Double click on the entry lt lt new gt gt which is highlighted in blue in the column labeled To The drop down menu in Figure 25 will appear Click on x1 as the first pin to be assigned this will enter x1 in the displayed table Follow this by double clicking on the box to the right of this new x1 entry in the column labeled Location Now the drop down menu in Figure 26 appears Scroll down and select PIN N25 Instead of scrolling down the menu to find the desired pin you can just type the name of the pin N25 in the Location box Use the same procedure to assign input x2 to pi
164. the propagation delays in the FPGA device because changes in x and z2 may not arrive at exactly the same time at the logic element that generates f 25 Simulation Waveforms Master Time Bar O ps 4 Pointer B98 ps Interval B98 ps Start End O p 40 0 n 30 0 n 1200 n 1600 n O ps Figure 42 The result of timing simulation 7 Programming and Configuring the FPGA Device The FPGA device must be programmed and configured to implement the designed circuit The required configura tion file is generated by the Quartus II Compiler s Assembler module Altera s DE2 board allows the configuration to be done in two different ways known as JTAG and AS modes The configuration data is transferred from the host computer which runs the Quartus II software to the board by means of a cable that connects a USB port on the host computer to the leftmost USB connector on the board To use this connection it is necessary to have the USB Blaster driver installed If this driver is not already installed consult the tutorial Getting Started with Altera s DE2 Board for information about installing the driver Before using the board make sure that the USB cable is properly connected and turn on the power supply switch on the board In the JTAG mode the configuration data is loaded directly into the FPGA device The acronym JTAG stands for Joint Test Action Group This group defined a simple way for testing digital circuits and loading data in
165. to them which became an IEEE standard If the FPGA is configured in this manner it will retain its configuration as long as the power remains turned on The configuration information is lost when the power is turned off The second possibility is to use the Active Serial AS mode In this case a configuration device that includes some flash memory is used to store the configuration data Quartus II software places the configuration data into the configuration device on the DE2 board Then this data is loaded into the FPGA upon power up or reconfiguration Thus the FPGA need not be configured by the Quartus II software if the power is turned off and on The choice between the two modes is made by the RUN PROG switch on the DE2 board The RUN position selects the JTAG mode while the PROG position selects the AS mode 7 1 JTAG Programming The programming and configuration task is performed as follows Flip the RUN PROG switch into the RUN position Select Tools gt Programmer to reach the window in Figure 43 Here it is necessary to specify the programming hardware and the mode that should be used If not already chosen by default select JTAG in the Mode box Also if the USB Blaster is not chosen by default press the Hardware Setup button and select the USB Blaster in the window that pops up as shown in Figure 44 light cdf a Hardware Setup U5B Blaster 058 0 Mode JTAG ki Progress aa e ieee eo ome Pee ve B LI LI LI LI
166. to implement this tiny circuit on the selected FPGA chip Another section is shown in Figure 20 It is reached by selecting Analysis amp Synthesis gt Equations on the left side of the compilation report Here we see the logic expressions produced by the Compiler when synthesizing the designed circuit Observe that f is the output derived as i 27 571 where the sign is used to represent the Exclusive OR operation Obviously the Compiler recognized that the logic expression in our design file is equivalent to this expression ff Compilation Report Analysis amp Synthesis Equations S E Legal Notice RiL2 x2 x1 5 Flow Summary SES Flow Settings SE Flow Elapsed Time X2 is x2 48 Flow Log operation mode is input ff Analysis amp Synthesis SE Summary Settings gE Source Files Read xl is xi EB Resource Usage Summary operation mode is input F Resource Utilization by Entity x2 INFUT xi INFUT f S 2 E Fitter operation mode is output Assembler J Timing Analyzer f OUTPUT A1L2 Figure 20 Compilation report showing the synthesized equations 4 1 Errors Quartus II software displays messages produced during compilation in the Messages window If the Verilog design file is correct one of the messages will state that the compilation was successful and that there are no errors If the Compiler does not report zero errors then there is at least one mistake in the Verilog code In this case
167. tools that should be used A commonly used term for CAD software for electronic circuits is EDA tools where the acronym stands for Electronic Design Automation This term is used in Quartus II messages that refer to third party tools which are the tools developed and marketed by companies other than Altera Since we will rely solely on Quartus II tools we will not choose any other tools Press Next 6 A summary of the chosen settings appears in the screen shown in Figure 10 Press Finish which returns to the main Quartus II window but with light specified as the new project in the display title bar as indicated in Figure 11 New Project Wizard Summary page 5 of 5 Eg When you click Finish the project will be created with the following settings Project directory D fintrotutorial Project name Top level design entity Number of files added Number of user libraries added Device assignments Family name Cyclone Il Device EP2C35F672C6 EDA tool Design entm synthesis None gt Simulation None gt Timing analysis None gt lt Back Hert gt Cancel Figure 10 Summary of the project settings Quartus Il D introtutorial light light File Edit View Project Assignments Processing Tools Window Help Doe bed Sew gt RP light PER A AE Project Navigator ajx Cyclone Il EP2C35F672C6 OUARTUS II Version 5 0 http www altera com Critical Warmin
168. two instances of the NOT gate Rotate the NOT gates into proper position by using the Rotate left 90 icon d Arrange the gates as shown in Figure 17 Symbol Ea Libraries EE d quartus42 libraries H megafunctions H others AE primitives H buffer SE logic ft and12 Name Jand2 E l Repeatinsert mode T Insert symbol as black M Launch MegeWvizerd Plug dn MegaWizard Plug In Manager cancel Figure 16 Choose a symbol from the library fi light bdf Figure 17 Import the gate symbols into the Graphic Editor window 3 2 Importing Input and Output Symbols Having entered the logic gate symbols it is now necessary to enter the symbols that represent the input and output ports of the circuit Use the same procedure as for importing the gates but choose the port symbols from the library primitives pin Import two instances of the input port and one instance of the output port to obtain the image in Figure 18 12 ra light bdf Figure 18 Import the input and output pins Assign names to the input and output symbols as follows Point to the word pin_name on the top input symbol and double click the mouse The dialog box in Figure 19 will appear Type the pin name 21 and click OK Similarly assign the name x2 to the other input and f to the output Pin Properties x General Format To create multiple pins enter a name in AHDL bus notation for example namef 3 0 or enter a com
169. ulate all four input valuations given in Figure 12 We will use four 50 ns time intervals to apply the four test vectors We can generate the desired input waveforms as follows Click on the waveform name for the x node Once a waveform is selected the editing commands in the Waveform Editor can be used to draw the desired waveforms Commands are available for setting a selected signal to 0 1 unknown X high impedance Z don t care DC inverting its existing value INV or defining a clock waveform Each command can be activated by using the Edit gt Value command or via the toolbar for the Waveform Editor The Edit menu can also be opened by right clicking on a waveform name Set x to O in the time interval O to 100 ns which is probably already set by default Next set x to 1 in the time interval 100 to 200 ns Do this by pressing the mouse at the start of the interval and dragging it to its end which highlights the selected interval and choosing the logic value 1 in the toolbar Make x2 1 from 50 to 100 ns and also from 150 to 200 ns which corresponds to the truth table in Figure 12 This should 21 produce the image in Figure 37 Observe that the output f is displayed as having an unknown value at this time which is indicated by a hashed pattern its value will be determined during simulation Save the file i light vwf 4 Pointer 128 07 ns Interval 128 07 ns Start 40 0 ng 30 0 ns 120 0 ng 160 0 ng a a a a a
170. ulation input file with simulation results uPCore Transaction Model File ame m m Signal activity output for power analysis M Generate Signal Activity File File name e Signal Activity File Options Figure 16 Specifying the simulation mode 12 Simulation Waveforms 0ps 4 t Pointer 4 4ns Interval qd ns Start End 120 0 ns Master Time Bar 160 0 ns SOE O GES Gk GEES Gris i SOf O 1650 4 63 0 X 120 000 30000 0 GREE BERES 190d y 6s GEES GS F630 GE si Figure 17 The result of functional simulation A simulation run is started by Processing gt Start Simulation or by using the icon F At the end of the simulation Quartus II software indicates its successful completion and displays a Simulation Report illustrated in Figure 17 As seen in the figure the Simulator creates waveforms for the outputs Z and Overflow As expected the values of Z indicate the correct sum or difference of the applied inputs one clock cycle later because of the registers in the circuit Note that the last value of Z is incorrect because the expected sum of 37630 is too big to be represented as a signed number in 16 bits which is indicated by the Overflow signal being set to 1 In this simulation we considered only the input and output signals which appear on the pins of the FPGA chip It is also possible to look at the behavior of internal signals For example let us consider the registered
171. ure 52 The updated Programmer window Flip the RUN PROG switch on the DE2 board to the PROG position Press Start in the window in Figure 52 An LED on the board will light up when the configuration data has been downloaded successfully Also the 30 Progress box in Figure 52 will indicate when the configuration and programming process 1s completed as shown in Figure 53 light cdf Ea Hardware Setup USB Blaster 056 0 Mode Active Serial Programming Progress sa AMAR Blight pot EPCS16 1C79348E O O Delete ie Change File Figure 53 The Programmer window upon completion of programming 8 Testing the Designed Circuit Having downloaded the configuration data into the FPGA device you can now test the implemented circuit Flip the RUN PROG switch to RUN position Try all four valuations of the input variables x and x2 by setting the corresponding states of the switches SW and SW o Verify that the circuit implements the truth table in Figure 12 If you want to make changes in the designed circuit first close the Programmer window Then make the desired changes in the Block Diagram Schematic file compile the circuit and program the board as explained above Copyright 2005 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are u
172. use it is active low ES nios_system v module nios system f f 1 global signals clk reset n ve the LEDs out port from the LEDs the Switches in port to the switches out port from the LEDs clk in port to the Switches reset n Figure 16 A part of the generated Verilog module Figure 17 shows a top level Verilog module that instantiates the Nios H system This module is named lights because this is the name we specified in Figure 3 for the top level design entity in our Quartus II project Note that the input and output ports of the module use the pin names for the 50 MHz clock CLOCK_50 pushbutton switches KEY toggle switches SW and green LEDs LEDG that are specified in the DE2 User Manual Type this code into a file called lights v Add this file and all the v files produced by the SOPC Builder to your Quartus II project Also add the necessary pin assignments on the DE2 board to your project The procedure for making pin assignments is described in the tutorial Quartus IT Introduction Using Verilog Design Note that an easy way of making the pin assignments when we use the same pin names as in the DE2 User Manual is to import the assignments given in the file called DE2_pin_assignments csv in the directory DE2_tutorials design_files which is included on the CD ROM that accompanies the DE2 board and can also be found on Altera s DE2 web pages Since the system we are designing needs to operate at a 50 M
173. utton to find the input and output nodes as indicated on the left side of the figure Insert Node or Bus Name Type INPUT Cancel e Value type J Level id Node Finder Radix Binary Bus width hi Start index fo M Display gray code count as binary count Figure 34 The Insert Node or Bus dialogue Node Finder Named f Filter Pins all Customize List ae Look in light IM Include subentities Stop Cancel Modes Found Selected Nodes Assignments gt PIM_AE 22 Output gt E Jlight 1 PIM_N26 Input PIM_N26 Input E Jlighthi2 PIM_N25 Input PIN_N25 Input 3 lightlf PIM_AE 22 Output a lt ja y gt Figure 35 Selecting nodes to insert into the Waveform Editor 20 Click on the x signal in the Nodes Found box in Figure 35 and then click the gt sign to add it to the Selected Nodes box on the right side of the figure Do the same for x2 and f Click OK to close the Node Finder window and then click OK in the window of Figure 34 This leaves a fully displayed Waveform Editor window as shown in Figure 36 If you did not select the nodes in the same order as displayed in Figure 36 it is possible to rearrange them To move a waveform up or down in the Waveform Editor window click on the node name in the Name column and release the mouse button The waveform is now highlighted to show the selection Click again on the waveform and drag it up or down in the Wavef
174. ving finished one design the user will want to use the same pin assignment for subsequent designs Going through the procedure described above becomes tedious if there are many pins used in the design A useful Quartus I feature allows the user to both export and import the pin assignments from a special file format rather than creating them manually using the Assignment Editor A simple file format that can be used for this purpose is the comma separated value CSV format which is a common text file format that contains comma delimited values This file format is often used in conjunction with the Microsoft Excel spreadsheet program but the file can also be created by hand using any plain ASCII text editor The format for the file for our simple project is To Location xl PIN_N25 x2 PIN_N26 f PIN_AE22 By adding lines to the file any number of pin assignments can be created Such csv files can be imported into any design project If you created a pin assignment for a particular project you can export it for use in a different project To see how this is done open again the Assignment Editor to reach the window in Figure 27 Now select File gt Export which leads to the window in Figure 28 Here the file light csv is available for export Click on Export If you now look in the directory introtutorial you will see that the file light csv has been created Save Ire E introtutorial db File name ight csv save as type Comma
175. w in Figure 12 we see that the timing delays along the path from the AddSubR flip flop to the Overflow flip flop are 0 469 ns longer than the maximum of 4 ns that is the period of the 250 MHz clock specified as the fmax constraint EEE Clock Setup Clock I ae fmax T 03 MHz PRR 3 744 ng l J Compilation Report B Legal Notice RES Flow Summary BE Flow Settings E Flow Elapsed Time Te Overtown regi E Flow Log 1 Analysis amp Synthesis Sp Fitter 9 Assembler 2 Timing Analyzer GEA Summary S Settings BEB Clock Settings Summary BEA Clock Setup Clack BEA Clock Hold Clack BES teu gE tro BES th EED Messages Em e Em pai ES u HE 15 Pei 285 ng D270 ns 0 247 ne 0 191 ns 0 152 ng 0 146 ne O63 he O 043 ng oO 01 g ng 0 023 ns D 118 ng D 123 ng oO 163 ng nivd ne T 276 40 MHz period 3 E1 n i CE 55 MHz period 3 603 ng 1273 3 33 MHz i period 2 580 n 283 77 MHz period 3 524 ne 288 g4 MHz period 45 ns J 2S7 44 MHz period 3 473 n 294 46 MHz i period 3 396 ne 295 68 MHz period 3 362 ns 301 75 MHz period 3 314 ns a02 66 MHz period 3 304 ne l a11 04 MHz period 3215 ns EH 53 MHz period 3 210 ne 315 46 MHz period 3 170 ns TEBE MH I nerind 2159 ne 1 jaag er Zrealt Zregi2 Zregl4 Zreg a Zreg E eregi 1 1 Overflow reg Breal
176. x2 where a closed switch corresponds to the logic value The truth table for the circuit is also given in the figure Note that this is just the Exclusive OR function of the inputs x and x2 but we will specify it using the gates shown Xi f 0 0 0 f 01 1 1 0 1 1 1 0 Figure 12 The light controller circuit The required circuit is described by the Verilog code in Figure 13 Note that the Verilog module is called light to match the name given in Figure 5 which was specified when the project was created This code can be typed into a file by using any text editor that stores ASCII files or by using the Quartus II text editing facilities While the file can be given any name it is a common designers practice to use the same name as the name of the top level Verilog module The file name must include the extension v which indicates a Verilog file So we will use the name light v module light x1 x2 f input x1 x2 output f assign f x1 amp x2 x1 amp x2 endmodule Figure 13 Verilog code for the circuit in Figure 12 3 1 Using the Quartus II Text Editor This section shows how to use the Quartus II Text Editor You can skip this section if you prefer to use some other text editor to create the Verilog source code file which we will name light v Select File gt New to get the window in Figure 14 choose Verilog HDL File and click OK This opens the Text Editor window The first step is to specif
177. y a name for the file that will be created Select File gt Save As to open the pop up box depicted in Figure 15 In the box labeled Save as type choose Verilog HDL File In the box labeled File name type light Put a checkmark in the box Add file to current project Click Save which puts the file into the directory introtutorial and leads to the Text Editor window shown in Figure 16 Maximize the Text Editor window and enter the Verilog code in Figure 13 into it Save the file by typing File gt Save or by typing the shortcut Ctrl s Most of the commands available in the Text Editor are self explanatory Text is entered at the insertion point which is indicated by a thin vertical line The insertion point can be moved either by using the keyboard arrow keys or by using the mouse Two features of the Text Editor are especially convenient for typing Verilog code First the editor can display different types of Verilog statements in different colors which is the default choice Second the editor can automatically indent the text on a new line so that it matches the previous line Such options can be controlled by the settings in Tools gt Options gt Text Editor 10 AHDL File Block Diagram Schematic File EDIF File Figure 14 Choose to prepare a Verilog file Save As E introtutorial MEJ Figure 15 Name the file Figure 16 Text Editor window 1 3 1 1 Using Verilog Templates The syntax
178. z period 3 678 ne lt reg 0 Overflow regQ 2r3 15 MHz l paida 3 661 ne l SelA Zenil l E E fo Timing Analyzer SES Summary SSE Settings F Clock Settings Summary SRE Clock Setup Clack SHEA tsu HEA tco SEs th 4 22 Messages i EJE EIE H H H H H NAA H H H H H B Figure 5 Critical paths The table in Figure 4 also shows other timing results While fmax is a function of the longest propagation delay between two registers in the circuit it does not indicate the delays with which output signals appear at the pins of the chip The time elapsed from an active edge of the clock signal at the clock source until a corresponding output signal is produced from a flip flop at an output pin is denoted as the tco delay at that pin In the worst case the tco in our circuit is 7 750 ns Click on tco in the Timing Analyzer section to view the table given in Figure 6 The first entry in the table shows that it takes 7 750 ns from when an active clock edge occurs until a signal propagates from bit 8 in register Zreg to the output pin zg The other two parameters given in Figure 4 are setup time tsu and hold time th fo Compilation Report 48 Legal Notice E43 Flow Summary SEB Flow Settings 2m Flow Elapsed Time 2 7o03 ne Overflow regl Overflow Clock SE Flow Log 456 ne regi 2 an2 Clock 5 z Analysis amp Synthesis T411 ne regi 3 Clock P Fitter T a28 ne reg z e Clock J Assembler 311

Getting Started with Altera`s DE2 Board

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