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uPD750108 User`s Manual

1. A XA 00H HL 02H DE 04H BC 06H When RBE RBS 0 XA 08H HL OAH DE OCH BC OEH Y 10H HL 12H DE 14H BC 16H when RBE RBS 2 XA 18H HL 1AH DE 1CH BC eye User s Manual U11330EJ2V1UMO00 When RBE RBS 1 When RBE RBS 3 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP 3 3 MEMORY MAPPED I O The u4PD750108 employs memory mapped I O which maps peripheral hardware such as timers and ports to addresses F80H to FFFH in data memory space as shown in Figure 3 2 This means that there is no particular instruction to control peripheral hardware but all peripheral hardware is controlled using memory manipulation instructions Some mnemonics for hardware control are available to make programs readable To manipulate peripheral hardware the addressing modes listed in Table 3 4 can be used Table 3 4 Addressing Modes Applicable to Peripheral Hardware Operation Bit manipulation Applicable addressing mode Direct addressing mode specifying mem bit with MBE 0 MBE 1 MBS 15 Applicable hardware All hardware allowing bit manipulation Direct addressing mode specifying fmem bit regardless of MBE and MBS setting IST1 ISTO MBE RBE IExxx IRQxxx PORTn x Indirect addressing mode specifying pmem L regardless of MBE and MBS setting BSBn x PORTn
2. piel a resistor P ch O P01 SCK P02 SO SBO O P03 SI SB1 Input buffer N ch Output buffer which can 5 open drain be switched to either push pull output N ch T g open drain output g Pull up resistor l P ch gt V Fr Bit 1 of HE Input buffer 1F e o 9 K 5 T 18 lt 0 P10 INTO eliminator oO 1 T t lt P11 INT1 T lt P12 INT2 T 41 O P13 TIO M T Input buffer with hysteresis TIO INT2 INT1 INTO Users Manual U11330EJ2V1UMO00 71 uPD750108 USER S MANUAL Figure 5 3 Configurations of Ports 2 and 7 Pull up resistor P ch Key interruptNote PMm 0 AA Input buffer AAAA Input buffer with hysteresisNote a T E Pe x4 OPm1 4 gt OPm2 x4 OPm3 Output buffer Bits 2 and 7 of port mode register group B m 2 7 Note For port 7 only User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 4 Configurations of Ports 3n and 6n n 0 to 3 Key interruptNote Input buffer with Voo hystere
3. 221 8 1 Configuration of Reset Functions eene nennen nnns 229 8 2 Reset Operation by Generation of RESET Signal sse 229 B 1 Drawings of the EV 9200G 44 Reference 310 B 2 Recommended Pattern on Boards for the EV 9200G 44 Reference 311 User s Manual U11330EJ2V1UMO00 LIST OF TABLES 1 2 Table No Title Page 2 1 Digital l O Pott Pls ecc toros ete tote eec te ace e cio TREE 9 2 2 Non Port Pin EUnctlons dei dice te Cadore Eti Oo ent e ttle 11 2 3 Connection of Un sed PIns u etie n e m eee reet ee tee 21 3 1 Addressing Modes cerei edicta d dm an En EY na dk adis 27 3 2 Register Bank to Be Selected with the and 36 3 3 Recommended Use of Register Banks with Normal Routines and Interrupt Routines 36 3 4 Addressing Modes Applicable to Peripheral Hardware Operation 41 4 1 Differences between Mk Mode and Mk Mode 47 4 2 Stack Area to Be Selected by the SBS sssssssssssssssseeeeeeen nnne 60 4 3 PSW Flags Saved Restored in Stack Operation 64 4 4 Carry Flag Manipulation 65 4 5 Information Indicated by the Interrupt Status
4. ITEM MILLIMETERS INCHES A 15 7 0 618 B 11 0 0 433 C 0 8 0 02 10 8 0 0 05 0 031 200 x 0 394 0 315 10002 D 0 8 0 02 10 8 0 0 05 0 031 2 008 x 0 394 0 315 10002 11 0 0 433 15 7 0 618 G 5 00 0 08 0 197 0 003 H 5 00 0 08 0 197205 0 5 0 02 0 02 0055 J 1 5740 03 90 062090 K 2 2 0 1 0 087 0005 L 1 57 0 03 0 062 0 003 Caution Dimensions of mount pad for EV 9200 and that for target device QFP may be different in some parts For the recommended mount pad dimensions for QFP refer to SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL C10535E Caution Dimensions of mount pad for EV 9200 and that for target device QFP may be different in some parts For the recommended mount pad dimensions for QFP refer to SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL C10535E User s Manual U11330EJ2V1UMO00 311 uPD750108 USER S MANUAL MEMO 312 User s Manual U11330EJ2V1UMO00 APPENDIX C MASKED ROM ORDERING PROCEDURE After program development is completed the masked ROM is ordered by the following procedure 1 c2 3 4 Advance notice of an order for masked ROM Give advance notice of masked ROM ordering to a special agent or NEC s Sales Department otherwise the ordered products may be delivered with delay Preparation of media for ordering Masked ROM orders can be placed on the following media types UV EPROMNote 3 5 inch IB
5. O o o olo oloi o Special 0 5 2 T4 To User s Manual U11330EJ2V1UMO00 267 uPD750108 USER S MANUAL 11 4 FUNCTIONS AND APPLICATIONS OF THE INSTRUCTIONS This section explains functions and applications of the instructions For the uPD750104 uPD750106 uPD750108 and uPD75P0116 usable instructions and their functions in Mk mode are different from those in Mk Il mode Read the following explanation How to read Can be used in both Mk mode and Mk II mode for the uPD750104 uPD750106 uPD750108 and uPD75P0116 CL Can be used in only Mk mode for the uPD750104 uPD750106 uPD750108 and uPD75P0116 Qu Can be used in only II mode for the uPD750104 uPD750106 0750108 and uPD75P0116 C Can be used in both Mk mode and Mk Il mode for the 750104 4PD750106 uPD750108 and uPD75P0116 However Mk mode is different from Mk mode in the functions Read the explanation of Mk mode for Mk mode and the explanation of Mk II mode for Mk Il mode as required Remark Function in this section is applicable to the 0750106 and uPD750108 whose program counters consist of 13 bits each This is also applicable to the uPD750104 whose program counter consists of 12 bits and the uPD75P0116 whose program counter consists of 14 bits however 11 4 1 Transfer Instructions MOV A n4 Function lt n4 n4 13 9 O FH Transfers the 4
6. Data Restored from the Stack Memory II Mode RETI instruction Stack SPD PC11 1 1 Note 1 1 Note 2 0 0 0 12 PC3 PCO PC3 PCO Notes 1 For the uPD75P0116 PC13 is entered instead of 0 2 For the uPD750104 0 is entered instead of PC12 3 PSW bits other than MBE and RBE are not saved or restored Remark indicates an undefined bit User s Manual U11330EJ2V1UM00 63 uPD750108 USER S MANUAL 4 8 PROGRAM STATUS WORD PSW 8 BITS The program status word PSW consists of various flags closely associated with processor operations The PSW is mapped to addresses FBOH and FB1H in data memory space Four bits at address FBOH can be manipulated with a memory manipulation instruction Figure 4 16 Program Status Word Format Address FB1H FBOH gt Symbol Cannot be manipulated Can be manipulated Can be manipulated by an instruction specifically provided for controlling this flag Table 4 3 PSW Flags Saved Restored in Stack Operation Saved restored flag Save When a CALL CALLA or CALLF instruction is executed MBE and RBE are saved When a hardware interrupt occurs All PSW bits are saved Restore When a RET or RETS instruction is executed MBE and RBE are restored When a RETI is executed All PSW bits are restored 1 Carry flag CY The carry flag is a 1 bit flag used to store information about an overflow or
7. MB MBE MBS MBS 0 1 15 MB 0 MBE 0 MB 0 000H 07FH MB 15 F80H FFFH MBE 1 MB MBS MBS 0 1 15 9 15 fmem FBOH FBFH FFFH MB 15 FFFH Y 0750104 addr addr1 0000H OFFFH uPD750106 addr addr1 0000H 17FFH uPD750108 addr addr1 0000H 1FFFH uPD75P0116 addr addr1 0000H 3FFFH addr addr1 Current PC 15 to Current PC 1 Current PC 2 to Current PC 16 uPD750104 caddr 0000H OFFFH uPD750106 caddr 0000H OFFFH PCi2 0 or 1000H 17FFH PCi2 1 uPD750108 caddr 0000H OFFFH PCi2 0 or 1000H 1FFFH PC 1 Program memory addressing uPD75P0116 caddr 0000H OFFFH PCs PC12 008 1000H PC s PC12 018 2000H 2FFFH PC s PC12 108 3000H 3FFFH PC s PC12 118 faddr 0000H 07FFH taddr 0020H 007FH For MkII mode only addr1 0000H OFFFH uPD750104 0000H 17FFH uPD750106 0000H 1FFFH uPD750108 0000H 3FFFH uPD75P0116 Remarks 1 MB represents an accessible memory bank 2 For 2 MB 0 regardless of the setting of MBE and MBS 3 For 4 and 5 MB 15 regardless of the setting of MBE and MBS 4 Each of 6 to 11 indicates an addressable area User s Manual U11330EJ2V1UMO00 247 uPD750108 USER S MANUAL 4 Explanation of the machine cycle column S represents the number of machi
8. Accumulator manipulation ODS G T S S S D G gt aa User s Manual U11330EJ2V1UMO00 265 uPD750108 USER S MANUAL Instruction code Instruction Operand Bo Increment INCS decrement 00000010 Ds De Ds D4 D3 D2 D4 Ds Po Comparison SKE Ro R4 l gt h Carry flag SET1 manipu lation Memory bit manipu lation D7 Dg 05 04 Dg Do Dy 2 Dy De Ds D4 Dg Ds D4 2 Dz Ds D5 D4 Dg Da D4 2 D7 Dg 05 04 02 Dy 2 SKTCLR 2 AND1 2 OR1 XOR1 2 2 266 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET Instruction code Instruction Operand Branch laddr addr1 Ao A4 Ao 16 to 2 1 to 15 S3 S2 8 So PCDE 1 0 PCXA BCDE BCXA laddr1 Icaddr Sub laddr routine stack control Ifaddr laddr1 A PORTn XA PORTn PORTn A PORTn XA Interrupt control CPU control 9 gt
9. 4 Festal mem 1 t 0 LSB first MSB first Read write gate Read write gate 2 SO latch Sl Shift resister SIO b SO lt SCK The first bitis switched by changing the order of data bits written to shift register SIO The shift operation order of SIO is always the same Accordingly the first bit must be switched between the MSB and LSB before writing data to the shift register 144 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 6 Transfer start Serial transfer is started by writing transfer data into shift register SIO provided that the following two conditions are satisfied The serial interface operation enable disable specification bit CSIE is set to 1 The internal serial clock is not operating after 8 bit serial transfer or SCK is high Caution Setting CSIE to 1 after writing data to the shift register does not start transfer When eight bits have beentransferred serial transfer automatically terminates setting the interrupt request flag IRQCSI Example To transfer the RAM data specified with the HL register to SIO load the SIO data to the accumulator and start serial transfer MOV XA HL X Fetch transmit data from RAM SEL MB15 or CLR1 MBE XCH XA SIO Exchange transmit data and receive data and start transfer 7 Appli
10. SARIS y ui y y YOS JO ef pe eui uo 195 SI S9OHI indino Bulag euis AWO Jou euis 13H MOS eseud 19 8 ueuM U9SuM o e s heise S JON 185 085 jou euis 13H si AWO Jaye 42S eseud 10 8 Jejse 00 20 LN las oas 8 2 AOS jeubis pue jeubls 13H Jaye YOS eseud 19 8 ov 2v sseJppv Las 085 ITI 8 2 MOS yeyo Se o o 9 151 Buunp 1ndino si uo os pue jeubis ASNg snouoiyous jeubis MOV Bunndino JO snououuou S POW 195 991 ui snoer 01 9 eigen 7905 jeues eureu 169 U11330EJ2V1UM00 User s Manual uPD750108 USER S MANUAL 6 Pin configuration The configurations of serial clock pin SCK and serial data bus pin SBO or SB1 are as follows a SCK Pin for serial clock I O lt 1 gt Master CMOS push pull output lt 2
11. S SI ANO 195 S LANO MOS UYM 185 085 jo puewwoy sseJppe SI pue jeubis sejeoipu paea st AAWO 195 4 195 SI 1139 indino 10 UOI IPUOD Las 095 H MOS yeyo MOS 185 10 085 epe uonuyeq 2 1 SPOW 185 941 ui sjeuBis snoueA 01 6 Jeise nding 199 jeubis sng jeus U11330EJ2V1UM00 User s Manual 168 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 10 SARIS Aq pesseoo4d o e s 0 pue eues uo e e s JO SseJppy snq jenas uo 1ndino jeuBis jo jo Ley AOS Jo ui6 Jo uo 195 s SDOHI YOS ey jo y uo s 50081 0 z ey 1891091 pes jenas 2150 OIS eiuw uononujsul Jo uonnoax3 indino 10 395 5 91215 AQV3 Joye pejeniui si ejeis ASN eur UI 2 VAS 49181601
12. 105 5 26 Block Diagram of the Clock Timer ssssssssssssssseseeeee eene nnne 109 5 27 Clock Mode Register Format ssessssssssssssssseeee eene nennen nennen nennen 110 5 28 Block Diagram of the Timer Event Counter Channel 0 112 5 29 Block Diagram of the Timer Counter Channel 1 113 5 30 Timer Event Counter Mode Register channel 0 115 5 31 Timer Counter Mode Register Channel 1 116 5 32 Timer Event Counter Output Enable Flag 117 5 33 Timer Event Counter Mode Register Setup 118 5 34 Timer Event Counter Output Enable Flag Setup 2 119 5 35 Configuration of Timer Event Counter sse enne enne nnns 121 5 36 Count Operation Timing sess sen nennen nennen 122 5 37 Error at the Start of the iania entente senten 123 5 38 Example of the SBI System Configuration 127 5 39 Block Diagram of the Serial Interface sssssssssssseeeeeeen enne 128 5 40 Format of Serial Operation Mode Register CSIM 130 5 41 Format of Serial Bus Interface Control R
13. Yes If two or more VRQns occur select one VRQn according to Table 6 1 Selected Remaining VRQn VRQns pa Save contents of PC and PSW in stack memory and set dataN te 2 in vector table corresponding to activated VRQn to PC RBE and MBE Change contents of ISTO and IST1 from 00 to 01 or from 01 to 10 Reset accepted IRQxxx oss Section 6 6 when those PR Sources share vector address Jump to the start address for processing the interrupt service program Notes 1 ISTO and IST1 are the interrupt status flags bits 3 and 2 of the PSW See Table 6 3 2 An interrupt service program start address and MBE and RBE setting values at the start of interrupt are stored in each vector table User s Manual U11330EJ2V1UMO0 199 uPD750108 USER S MANUAL 6 5 MULTIPLE INTERRUPT PROCESSING CONTROL The wPD750108 can handle multiple interrupts by either of the following methods 1 200 Multiple interrupt processing by a high order interrupt In this method the uPD750108 selects an interrupt source among multiple interrupt sources enabling double interrupt processing That is the high order interrupt specified by the interrupt priority specification register IPS is enabled when the processing status is O or 1 Other interrupts interrupts lower than the specified high order interrupt are enabled only when the status is 0 See Figure 6 8 and Table 6 3 When only one interrupt is used as a level two inter
14. 85 5 11 Block Diagram of the Clock Generator ssssssssssssesseeeeenee eene 86 5 12 Format of the Processor Clock Control Register sse 89 5 13 Format of the System Clock Control Register ssssssssssseeeeeen 90 5 14 External Circuit for the Main System Clock 91 5 15 External Circuit for the Subsystem Clock 91 5 16 Examples of Oscillator Connections Which Should Be Avoided 92 5 17 Subsystem Clock Oscillator a a 96 5 18 Sub Oscillator Control Register SOS Format sss 97 5 19 Changing the System Clock and CPU Clock sess 99 5 20 Configuration of the Clock Output Circuit 100 5 21 Format of the Clock Output Mode Register 101 5 22 Application to Remote Control Waveform 102 5 23 Block Diagram of the Basic Interval Timer Watchdog Timer 103 5 24 Format of the Basic Interval Timer Mode 104 5 25 Format of the Watchdog Timer Enable Flag WDTM
15. Cau BUSY ACK The timing for reading SIO and start of serial transfer writing to SIO is as follows When the serial interface operation enable disable bit CSIE 1 However the case where CSIE is set to 1 after data is written to the shift register is excluded When the serial clock is masked after 8 bit serial transfer SCKis high When reading from or writing to SIO make sure that SCK is high In the two wire serial 1 mode and SBI mode the pins specified for the data bus are used for both input and output Because the configuration of output pins is N ch open drain write FFH in SIO for devices that are to receive data N ch open drain output Slave address register SVA The slave address register SVA is an 8 bit register for a slave to set its slave address number assigned to it SVA is manipulated using an 8 bit manipulation instruction When the RESET signal is generated the value of SVA is undefined However the value of SVA is preserved when the RESET signal is generated in the standby mode SVA has the following two functions User s Manual U11330EJ2V1UMO00 137 uPD750108 USER S MANUAL a Slave address detection b In the SBI mode SVA is used when the 4PD750108 is connected as a slave device to the serial bus SVA is an 8 bit register for a slave to set its slave address number assigned to it The master outputs a slave address to the connected slaves to select a
16. E Y v 8 13181691 NISO 1591 pane uoneindiuew yg ug rs Y Y Y Y snq 99eJ19 u 991 jo 62 6 ainbi4 User s Manual U11330EJ2V1UMO00 128 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 1 2 3 4 5 6 7 Serial operation mode register 0 CSIM CSIM is an 8 bit register which specifies a serial interface operation mode serial clock wake up function and so forth See 1 in Section 5 6 3 for details Serial bus interface control register SBIC SBIC is an 8 bit register consisting of bits for controlling the serial bus and flags for indicating the states of input data from the serial bus SBIC is used mainly in the SBI mode See 2 in Section 5 6 3 for details Shift register SIO SIO is an 8 bit register which converts 8 bit serial data to parallel data and 8 bit parallel data to serial data SIO performs transfer shift in phase with the serial clock Transfers operations are controlled by writing data to SIO See 3 in Section 5 6 3 for details SO latch SO is a latch to hold the levels of pins SO and SBO or SI and SB1 which can be controlled directly by software In the SBI mode SO is set when the eighth clock of SCK has been output See 2 in Section 5 6 3 for details Serial clock selector The serial clock selector selects the serial clock to be used Serial clock counter The serial c
17. gt interrupt occurrence Status 1 Low or high order interrupt occurrence User s Manual U11330EJ2V1UMO00 201 uPD750108 USER S MANUAL 6 6 PROCESSING OF INTERRUPTS SHARING A VECTOR ADDRESS Interrupt sources INTBT and INT4 share a vector table so an interrupt source is selected as described below 1 Using only one interrupt The interrupt enable flag for desired one of the two interrupt sources sharing a vector table is set to 1 and the interrupt enable flag for the other is cleared to 0 In this case the enabled IExxx 1 interrupt source causes an interrupt request When the interrupt request is accepted the interrupt request flag is reset 2 Using both interrupts The interrupt enable flags corresponding to the two interrupt sources are both set to 1 In this case the logical sum of the interrupt request flags for the two interrupt sources is used as an interrupt request In this case even if an interrupt request or interrupt requests caused by the setting of one or both of the interrupt request flags are accepted the interrupt request flag or flags are not reset Accordingly which of the two interrupt sources caused the interrupt needs to be determined using the interrupt service routine For this determination the DI instruction is to be executed at the start of the interrupt service routine and the interrupt request flags are checked with the SKTCLR instruction If both the request fla
18. 214 7 1 Operation Statuses in the Standby Mode 220 User s Manual U11330EJ2V1UMOO LIST OF TABLES 2 2 Table No Title Page 8 1 Status of the Hardware after a Reset 230 10 1 Selecting Mask Option of Pin 239 11 1 Types of Bit Manipulation Addressing Modes and Specification Range 242 User s Manual U11330EJ2V1UMO00 MEMO User s Manual U11330EJ2V1UMOO CHAPTER 1 GENERAL The wPD750104 uPD750106 uPD750108 anduPD75P01 16 are 75XL series 4 bitsingle chip microcontrollers The 75XL series is a successor of the 75X series consisting of many products These uPD750104 uPD750106 uPD750108 and uPD75P0116 are collectively called the uPD750108 subseries The uPD750108 subseries is produced by replacing the main system clock oscillator of the 4 PD750008 subseries with an RC oscillator enabling operation at the relatively low voltage of 1 8 V The 75XL series takes over the CPUs of the 75X series realizing a wide range of operating voltages In addition to having upward compatibility with existing products the 75XL series is best suited for battery driven applications The uPD750104 uPD750106 uPD750108 and uPD75P0116 have the following features Built in RC oscillator for main system clock oscillation enabling the immediate start of processing aft
19. 66 4 6 Register Bank to Be Selected with the and 68 5 1 Types and Features of Digital Ports nennen 70 5 2 Pin Manipulation Instructions sessssseseseeeseneneneenneenn nennen nnns 80 5 3 Operations by I O Port Manipulation Instructions 82 5 4 Specification of Built In Pull Up Resistors 83 5 5 Maximum Time Required to Change the System Clock and CPU Clock 98 5 6 Resolution and Longest Setup Time sse nennen 120 5 7 Serial Clock Selection and Application in the Three Wire Serial I O Mode 143 5 8 Serial Clock Selection and Application in the Two Wire Serial I O Mode 151 5 9 Serial Clock Selection and Application in the SBI Mode 163 5 10 Various Signals Used in the SBI 168 6 1 Interrupt SOUPCOS epe D ae EM e cate E ERIT Rea nd 189 6 2 Set Signals for Interrupt Request 5 essen 192 6 3 Interrupt Processing Statuses of ISTO and IST1 198 6 4 Identifying Interrupt Sharing Vector Table Address 202 6 5 a SOUE EHE CP 214 6 6 Signals Setting Test Request Flags
20. BR addr1 Note The shaded portion is supported Mk II mode only The other portions are supported in Mk mode only User s Manual U11330EJ2V1UMO00 253 uPD750108 USER S MANUAL Operand Machine cycle Operation 1 0750104 PC 1 0 lt e uPD750106 uPD750108 PC412 9 lt addr 75 0116 13 0 lt addr Address ing area Skip condition 1 0750104 PC 1 0 lt 7 addr e uPD750106 uPD750108 PC12 0 addr 75 0116 PC13 9 lt addr addr1 1 0750104 PC11 0 lt addr1 1 0750106 750108 PC12 9 lt addr1 uPD75P0116 PC13 0 lt addr1 750104 PC41 9 PC41 94 DE 0750106 uPD750108 PC12 0 PC42 g DE yPD75P0116 PC13 0 lt PC13 g DE 750104 PC41 9 PC41 9 XA 1 0750106 uPD750108 PC12 0 lt PC42 8 XA uPD75P0116 PC13 0 gt PC13 8 XA Notes1 Set register B to 0 2 Only the LSB is valid in register B 3 Only the low order two bits are valid in register B 254 uPD750104 11 0 lt BCDENote 1 uPD750106 uPD750108 12 0 lt BCDENote 2 075 0116 PC13 9 lt BCDENote 3 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET Address Operation ing Skip condition area Operand Machine cycle uPD750104 11 0 lt BCXANote
21. Busy enable bit R W Remarks 1 R Read only 2 W Write only 3 R W Read write 134 User s Manual U11330EJ2V1UM00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 41 Format of Serial Bus Interface Control Register SBIC 2 3 Busy enable bit R W lt 1 gt The busy signal is automatically disabled lt 2 gt Busy signal output is stopped in phase with the falling edge of SCK immediately after clear instruction execution The busy signal is output after the acknowledge signal in phase with the falling edge of SCK Acknowledge detection flag R ACKD Condition for being cleared ACKD 0 Condition for being set ACKD 1 lt 1 gt The transfer operation is started The acknowledge signal ACK is detected lt 2 gt The RESET signal is generated in phase with the rising edge of SCK Acknowledge enable bit R W Disables automatic output of the acknowledge signal ACK Output by ACKT is possible When set before transfer ACK is output in phase with the 9th clock of SCK When set after transfer ACK is output in phase with SCK immediately following the set instruction execution Acknowledge trigger bit W When set after transfer ACK is output in phase with the next SCK After ACK signal output this bit is automatically cleared to 0 Cautions 1 Never set ACKT before or during serial transfer 2 ACKT cannot be cleared by software 3 Before setting ACKT set ACKE
22. Le z 9 SI SI uPD7525G gt CS gt SCK uPD75402A uPD75104 gt SCK SO To configure the bus as shown above connect the SI pin and SO pin Then writes FFH to the shift register to make the SO pin high except when serial data is output and free the bus by setting off the output buffer The SO pin of the uPD75402A cannot go into a high impedance state so that a transistor must be connected as shown in the figure to make open collector output appear on the pin When data is input OOH must be set beforehand in the shift register to set the transistor off The timing of data output by each microcontroller must be predetermined 152 User s Manual U11330EJ2V1UM00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS The uPD7501 08 which is the master microcontroller outputs a serial clock and all slave microcontrollers operate with an external clock 5 6 7 SBI Mode Operation The SBI serial bus interface is a high speed serial interface that conforms to the NEC serial bus format To allow communication with multiple devices on a single master and high speed serial bus using two signal lines the SBI has a bus configuration function added to the clock synchronous serial I O method So the SBI can reduce ports and wires on boards when multiple microcontrollers and peripheral ICs are used to configure a serial bus The master can output on the serial data bus an address for selecting
23. lt 1 gt Enable the feedback resistor switches on or off by software lt 2 gt Disable the feedback resistor cuts by hardware To use the feedback resistor after selecting lt 1 gt turn the feedback resistor on by setting 505 0 to 0 for details see 6 in Section 5 2 2 Select 1 to use the subsystem clock For the uPD75P0116 the mask option need not be set use of the feedback resistor is factory set 240 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET The instruction set of the 4PD750108 is an improved and extended version of the 75X series instruction set This instruction set takes over the instruction set of the 75X series having the following features 1 2 1 Bit manipulation instructions allowing a wide variety of applications 2 Efficient 4 bit manipulation instructions 3 Eight bit instructions comparable to 8 bit microcontrollers 4 GETI instruction for reducing program sizes 5 String effect instructions and number system conversion instructions for increased program efficiency 6 Table reference instructions suitable for successive references 7 1 byte relative branch instructions 8 NEC standard mnemonics designed for clarity and readability See Section 3 2 for the addressing modes applicable to data memory manipulation and register banks used for instruction execution 11 1 UNIQUE INSTRUCTIONS This section outlines the unique instructions among the uPD750108 instruction set
24. 135 B BS 67 BSBO BSB3 184 BSYE 135 BT 103 BTM 103 C CLOM 101 CMDD 135 CMDT 136 COI 181 CSIE 131 CSIM 130 CY 64 I IEO 191 IE1 191 IE2 214 IEA 191 IEBT 191 IECSI 191 IETO 191 IET1 191 IEW 214 IMO IM1 197 IM2 217 IME 193 IPS 192 IRQO 191 IRQ1 191 IRQ2 214 IRQA 191 IRQBT 191 IRQCSI 191 IRQTO 191 191 IRQW 214 ISTO 65 198 IST1 65 198 KRO KR7 215 M MBE 23 66 MBS 23 67 P PC 49 PCC 88 PMGA 77 PMGB 77 PMGC 77 POGA 84 POGB 84 PORTO PORTS 70 PSW 64 R 36 66 RBS 36 67 RELD 136 136 User s Manual U11330EJ2V1UMO00 323 uPD750108 USER S MANUAL S SBIC 134 SBS 48 60 SCC 90 SIO 137 SKO SK1 SK2 65 SOS 97 SP 60 SVA 137 T TO 112 1 113 TOEO 117 TOE1 117 TMO 114 TM1 114 112 TMOD I 113 W WDTM 105 WM 109 WUP 131 324 User s Manual U11330EJ2V1UMO00 APPENDIX F REVISION HISTORY The revision history is shown below The chapters described in the revised chapter column indicate those for the corresponding edition Edition Second Major changes The uPD750104 uPD750106 uPD750108 and uPD75P0116 have already been develope
25. D Function rp 1 CY lt 1 Subtracts the contents of the XA register pair together with the carry flag from the contents of register pair rp 1 HL DE BC XA HL DE BC then sets the result in register pair rp 1 If the subtraction generates a borrow the carry flag is set If no borrow is generated the carry flag is reset AND A n4 Function lt 4 4 13 9 0 FH ANDs the contents of the A register with the 4 bit immediate data n4 then sets the result in the A register Example high order two bits of an accumulator are set to 0 AND A 0011B 280 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET AND A HL Function A A HL ANDs the contents of the A register with the data at the data memory location addressed by the HL register pair then sets the result in the A register XA rp Function XA XA rp ANDs the contents of the XA register pair with the contents of register pair rp XA HL DE BC XA HL DE BC then sets the result in the XA register pair Ce AND rp 1 XA Function rp rp1 XA ANDs the contents of register pair rp 1 HL DE BC XA HL DE BC with the contents of the XA register pair then sets the result in the specified register pair C 2 OR A n4 Function A c Av4 4 13 0 0 FH ORs the contents of the A register with the 4 bit immediate
26. SEL MB15 or CLR1 MBE MOV XA 10001010B MOV CSIM XA CSIM lt 10001010B 2 Serial transfer dependent on the contents of CSIM is enabled SEL MB15 or CLR1 MBE CSIE User s Manual U11330EJ2V1UMO00 133 uPD750108 USER S MANUAL 2 Serial bus interface control register SBIC Figure 5 41 shows the format of the serial bus interface control register SBIC SBIC is an 8 bit register consisting of bits for controlling the serial bus and flags for indicating the states of input data from the serial bus SBIC is used mainly in the SBI mode SBIC is manipulated using a bit manipulation instruction SBIC cannot be manipulated using a 4 bit or 8 bit memory manipulation instruction Each bit may or may not allow read and or write operation Figure 5 41 When the RESET signal is generated all bits are cleared to 0 Caution Only the following bits can be used in the three wire and two wire serial I O modes Bus release trigger bit RELT Sets the SO latch Command trigger bit CMDT Clears the SO latch Figure 5 41 Format of Serial Bus Interface Control Register SBIC 1 3 Address Symbol 7 6 5 4 3 2 1 0 FE2H BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT SBIC Bus release trigger bit W Command trigger bit W Bus release detection flag R Command detection flag R Acknowledge trigger bit W Acknowledge enable bit R W Acknowledge detection flag R
27. 255 289 BRCB Icaddr 255 290 TBR addr 260 292 Subroutine stack control instructions CALLA laddr1 255 293 CALL laddr 256 293 CALLF Ifaddr 256 294 TCALL laddr 260 294 RET 257 295 RETS 258 295 RETI 258 296 PUSH rp 259 296 PUSH BS 259 297 POP 259 297 POP BS 259 297 Interrupt control instructions El 259 297 EI IExxx 259 297 DI 259 297 DI IEXxx 259 298 instructions IN A PORTn 259 298 IN XA PORTn 259 298 OUT PORTn A 259 298 OUT PORTn XA 259 298 CPU control instructions HALT 259 299 STOP 259 299 NOP 259 299 Special instructions SEL RBn 260 299 SEL MBn 260 299 GETI taddr 260 300 User s Manual U11330EJ2V1UM00 317 uPD750108 USER S MANUAL D 2 INSTRUCTION INDEX ALPHABETICAL ORDER A CLR1 mem bit 252 286 ADDC A HL 250 278 CLR1 pmem L 252 286 ADDC rp 1 XA 250 279 CLR1 H mem bit 252 286 ADDC XA rp 250 279 ADDS 4 250 277 D ADDS A HL 250 278 DECS reg 251 284 ADDS rp 1 XA 250 278 DECS 251 284 ADDS XA rp 250 278 DI 259 297 ADDS 8 250 278 DI IExxx 259 298 AND A n4 251 280 AND A HL 251 281 E AND 1 251 281 El 259 297 AND 251 281 EI IExxx 259 297 AND1 CY fmem bit 252 288 AND1 C
28. PY rp 1 XA rp 1 XA A HL A lt gt HL A HL A lt gt HL then L lt L 1 A HL A lt gt HL then L lt L 1 A rpat lt gt 1 XA HL lt gt HL A mem A mem XA mem XA lt gt mem A reg1 A lt gt reg XA rp lt gt rp Users Manual U11330EJ2V1UMO00 249 uPD750108 USER S MANUAL Address Operation ing Skip condition area Operand Machine cycle XA PCDE uPD750104 XA lt PC14 8 DE Rom uPD750106 uPD750108 XA lt PC42 g DE RoM uPD75P0116 XA PC13 g DE Rom XA PCXA pgPD750104 XA PC14 3 XA Rom Table reference 1 0750106 1 0750108 lt 12 8 pPD75P0116 XA lt PC13 8XA ROM XA BCDE XA lt BCDE noyNote XA BCXA lt BCXA RomNote CY fmem bit CY fmem bit CY pmem L CY lt pmem7 o L3_9 bit L4 9 CY H mem bit CY lt H mem3 o bit fmem bit CY ke N c pd fmem bit CY pmem L CY pmemz7 2 L3 2 bit L4 0 lt CY ToO INI NI NIJI OOJO H mem bit CY H mems o bit CY A n4 02 A n4 8 lt 8 A HL A lt A HL XA rp XA XA rp rp 1 XA rp lt rp 1 XA A HL A CY lt A HL CY XA rp XA CY lt XA rp CY rp 1
29. SUBC A HL ADDS A m An underflow is set in the carry flag If the execution of the instruction SUBC A HL generates no borrow the next instruction ADDS A n4 is skipped If a borrow is generated the instruction ADDS A 14 is executed In this case the skip function of this instruction ADDS A n4 is disabled so that even if this addition generates a carry the instruction following this instruction is not skipped Accordingly programs can be written after ADDS A n4 Users Manual U11330EJ2V1UMO00 243 uPD750108 USER S MANUAL 11 1 5 Skip Instructions and the Number of Machine Cycles Required for a Skip The instruction set of the PD750108 is designed to organize a program by testing a condition with the skip function When a skip instruction satisfies the skip condition the immediately following instruction is skipped to execute the instruction immediately after the skipped instruction A skip requires the following number of machine cycles a When the instruction to be skipped immediately following the skip instruction is a 3 byte instruction that is the BR BRA addr1 CALL or CALLA addr1 instruction 2 machine cycles b When the instruction to be skipped immediately following the skip instruction is an instruction other than the instructions described in a above 1 machine cycle 244 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET 11 2 INSTRUCTION SET AND OPERATION 1
30. WM7 Disables BUZ output Enables BUZ output BUZ output frequency selection bit BUZ output frequency si oo Not to be set XT1 pin input level bit test only WM3 Input to the 1 pin is low level Input to the XT1 pin is high level Clock operation enable disable bit WM2 Disables clock operation clears the frequency dividing circuit Enables clock operation Operation mode selection bit WM1 Normal clock mode A sets IRQW at 0 5 s Advanced clock mode 7 sets IRQW at 3 91 ms Count clock fw selection bit S Selects divided system clock output ES Selects subsystem clock fxr Remark for fw 32 768 kHz 110 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5 5 TIMER EVENT COUNTER The uPD750108 has timer event counter channel channel 0 and one timer counter channel channel 1 Figures 5 28 and 5 29 show the configuration of these channels In this section the timer event counter and timer counters are referred to as timer event counters When you read this section for description of channel 1 take timer event counter as timer counter The timer event counter has the following functions a Programmable interval timer operation b Square wave output of any frequency to the PTOn pin n 0 1 c Event counter operation Channel 0 only d Divides the frequency of signal input via the
31. 11 1 1 GETI Instruction The GETI instruction converts any of the following instructions to a 1 byte instruction a Subroutine call instruction for the entire space b Branch instruction for the entire space c Arbitrary 2 byte instruction operating with two machine cycles Except the BRCB and CALLF instructions d A combination of two 1 byte instructions The GETI instruction references the table located at addresses 0020H to 007FH in program memory and executes referenced 2 byte data as an instruction of a b c or d above This means that 48 instructions consisting of a to d can be converted to 1 byte instructions Thus the GETI instruction can be used to convert frequently used instructions of a to d to 1 byte instructions to reduce the number of program bytes significantly Users Manual U11330EJ2V1UMO00 241 uPD750108 USER S MANUAL 11 1 2 Bit Manipulation Instruction The uPD750108 has reinforced bit test bit transfer and bit Boolean AND OR and XOR instruction in addition to the ordinary bit manipulation set and clear instructions The bit to be manipulated is specified in the bit manipulation addressing mode Three types of bit manipulation addressing modes can be used The bits manipulated in each addressing mode are shown in Table 11 1 Table 11 1 Types of Bit Manipulation Addressing Modes and Specification Range Peripheral hardware that can be Addressing range of bit that can be Addressin
32. HL DE BC to the contents of the XA register pair in binary then skips the next instruction if the addition generates a carry The carry flag is not affected CG ADDS rp 1 XA Function rp lt rp 1 XA Skip if carry Adds the contents of the XA register pair to the contents of register pair 1 HL DE BC XA HL DE BC in binary then skips the next instruction if the addition generates a carry The carry flag is not affected Example The register pair is left shifted MOV XA 1 ADDS rp XA NOP T ADDC A HL Function A CY A HL CY Adds the data at the data memory location addressed by the HL register pair together with the carry flag to the contents of the A register in binary If the addition generates a carry the carry flag is set If no carry is generated the carry flag is reset If the execution of this instruction generates a carry when this instruction is immediately followed by the ADDS A n4 instruction the ADDS A n4 instruction is skipped If no carry is generated the ADDS A n4 instruction is executed and the skip function of the ADDS A n4 instruction is disabled Accordingly a combination of these instructions can be used for number system conversion See Section 11 1 278 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET Cc ADDC XA rp Function XA CY lt Adds the contents of register pair rp XA HL DE BC XA
33. HL DE BC together with the carry flag to the contents of the XA register pair in binary If the addition generates a carry the carry flag is set If no carry is generated the carry flag is reset C 3 ADDC rp 1 XA Function rp 1 CY lt rp 1 XA CY Adds the contents of the XA register pair together with the carry flag to the contents of register pair HL DE BC XA HL DE BC in binary If the addition generates a carry the carry flag is set If no carry is generated the carry flag is reset SUBS A HL Function A lt A HL Skip if borrow Subtracts the data at the data memory location addressed by the HL register pair from the contents of the A register then sets the result in the A register If the subtraction generates a borrow the immediately following instruction is skipped The carry flag is not affected SUBS XA rp Function XA XA rp Skip if borrow Subtracts the contents of register pair rp XA HL DE BC XA HL DE BC from the contents of the XA register pair then sets the result in the XA register pair If the subtraction generates a borrow the immediately following instruction is skipped The carry flag is not affected Example Data memory is compared with register pair rp MOV XA mem SUBS XA rp mem 2 rp mem lt rp User s Manual U11330EJ2V1UMO00 279 uPD750108 USER S MANUAL 7 SUBS rp 1 XA
34. MBE 1 SEL MB1 MBS 1 24 User s Manual U11330EJ2V1UMO00 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP 3 1 2 Data Memory Addressing Modes With the architecture of the 4PD750108 seven addressing modes summarized in Figure 3 2 and Table 3 1 are available to address data memory space efficiently for each bit length of data to be processed These addressing modes enable more efficient programming 1 1 bit direct addressing mem bit Inthis addressing mode the operand of an instruction can directly specify any bit in the entire data memory space A particular memory bank MB is always used in this addressing mode In the MBE 0 mode when an address from 00H to 7FH is specified in the operand memory bank 0 MB 0 is always used When an address from 80H to FFH is specified memory bank 15 MB 15 is always used Accordingly both the data area ranging from 000H to 07FH and the peripheral hardware area ranging from F80H to FFFH can be addressed in the MBE 0 mode In the MBE 1 mode MB MBS and specifiable data memory space can be expanded This addressing mode can be applied to four instructions bit set and reset instructions SET1 and CLR1 and bit test instructions SKT and SKF Example FLAG is set FLAG2 is reset and whether FLAGS is zero is tested FLAGI EQU OSFH 1 Bit 1 at address FLAG2 EQU 087H 2 Bit 2 at address 87H FLAGS EQU OA7H 0 Bit 0 at address A7H SET1 MBE MBE lt 1 SEL MBO M
35. Thank you for your kind support Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 465 250 3583 Japan NEC Semiconductor Technical Hotline Fax 044 548 7900 would like to report the following error make the following suggestion Document title Document number Page number If possible please fax the referenced page or drawing Document Rating Excellent Clarity Technical Accuracy Organization
36. low order 8 bits high order 5 bits 0006H 0008H 000AH 000CH 0020H 007FH 0080H 07FFH 0800H OFFFH 1000H 17FFH INTO start address INT1 start address INT1 start address INTCSI start address INTCSI start address INTTO start address INTTO start address INTT1 start address INTT1 start address low order 8 bits high order 5 bits low order 8 bits high order 5 bits low order 8 bits high order 5 bits low order 8 bits high order 5 bits low order 8 bits GETI instruction reference table Note Can be used only in the MkII mode Remark 52 Entry address specified in CALLF instruc tion Branch address specified in BRCB Icaddr instruc tion Y Branch address specified in BRCB Icaddr instruction User s Manual U11330EJ2V1UMO00 Branch address specified in BR BR BCDE BR BCXA BRA laddr1 ets CALL addr or CALLA addr1 Ne nm d Branch call address by GETI Relative branch address specified in BR addr instruction 715 to 1 2 to 16 In addition to the above the BR PCDE and BR instructions can cause a branch to an address with only the 8 low order bits of the PC changed CHAPTER 4 INTERNAL CPU FUNCTIONS 0000H 0002H 0004H 0006H 0008H 000AH 000CH 0020H 007
37. of bits that can be Hardware name symbol Pee Bit Address manipulation Remarks ME Stack pointer SP FgoH Register bank selection register RBS F83H Memory bank selection register MBS F85H Basic interval timer mode register BTM Eg Basic interval timer BT R P ra Miu A Only bit 3 can R be tested Notes 1 Can be manipulated separately as the RBS and MBS in 4 bit units Can also be manipulated as the BS in 8 bit units Use SEL MBn and SEL RBn instructions to write data to the MBS and RBS respectively Use a PUSH or POP instruction to write data to the BS 2 WDTM Watchdog timer enable flag W cannot be cleared by an instruction User s Manual U11330EJ2V1UMO00 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Figure 3 7 uPD750108 I O Map 2 5 Number of bits that can be Hardware name symbol manipulated Address E FAOH Bit manipulation Remarks addressing Bit write manipu mem bit lation is enabled only for bit 3 FA2H FA4H FA6H FA8H FACH n Timer counter count register T1 FAEH D Timer counter modulo register TMOD1 Notes 1 TOEO Timer event counter output enable flag W 2 TOE1 Timer counter output enable flag W User s Manual U11330EJ2V1UM00 Bit write manipu lation is enabled 43 uPD750108 USER S MANUAL 44 Figure 3 7 uPD750108 I O Map 3 5 Number of bits that can be Hardware nam
38. ojoquu AS 5995 0086 Od SoH ulejs s 3I eyoNIN3 H 00 S7 3I u g980087 d3 O eSu 277 77 8 1080092 34 a z Pd t vet 8 10092 3 ES 2 10 H 000S7 3l 2 oo 1jueudoje eg 309 U11330EJ2V1UM00 User s Manual uPD750108 USER S MANUAL Drawings of the Conversion Socket EV 9200G 44 and Recommended Pattern on Boards Figure B 1 Drawings of the EV 9200G 44 Reference Based on EV 9200G 44 1 Package drawing in mm E V 9200G 4 No 1 pin index EV 9200G 44 G0 ITEM MILLIMETERS INCHES A 15 0 0 591 B 10 3 0 406 10 3 0 406 15 0 0 591 4 3 0 4 0 118 0 8 0 031 G 5 0 0 197 H 12 0 0 472 14 7 0 579 J 5 0 0 197 K 12 0 0 472 L 14 7 0 579 M 8 0 0 315 7 8 0 307 N 2 0 0 079 P 1 85 0 053 Q 0 35 0 1 0 014 0 005 R 1 5 0 059 310 User s Manual U11330EJ2V1UMO00 APPENDIX B DEVELOPMENT TOOLS Figure B 2 Recommended Pattern on Boards for the EV 9200G 44 Reference Based on EV 9200G 44 2 Pad drawing in mm WD eh sull oY E WES EV 9200G 44 P1E
39. 0000H 3FFFH immediate data or label uPD75P0116 caddr 12 bit immediate data or label faddr 11 bit immediate data or label taddr 20H 7FH immediate data bit 0 0 or label PORTn PORTO PORT8 IETO IET1 IEO IE2 IE4 IECSI IEW RBn RBO RB3 MBn MBO MB1 MB15 Note For mem only even addresses can be coded for 8 bit data processing Users Manual U11330EJ2V1UMO00 245 uPD750108 USER S MANUAL 2 Legend PSW MBE RBE PORTn IME IPS RBS MBS PCC 246 A register 4 bit accumulator B register C register D register E register H register L register X register Register pair XA 8 bit accumulator Register pair BC Register pair DE Register pair HL Extended register pair XA Extended register pair BC Extended register pair DE Extended register pair HL Program counter Stack pointer Carry flag bit accumulator Program status word Memory bank enable flag Register bank enable flag Port n n 0 to 8 Interrupt master enable flag Interrupt priority specification register Interrupt enable flag Register bank select register Memory bank select register Processor clock control register Address bit delimiter Contents addressed by xx Hexadecimal data User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET 3 Explanation of symbols used for the addressing area column
40. 2 Operation is possible only when the noise eliminator is not selected by bit 2 of the edge detection mode register IMO when IMO2 1 A STOP instruction is used to set the STOP mode and a HALT instruction is used to set the HALT mode A STOP instruction sets bit 3 of PCC and a HALT instruction sets bit 2 of PCC STOP instruction or HALT instruction must always be followed by an NOP instruction When changing a CPU operation clock pulse with the low order two bits of PCC a time lag may occur from the time when PCC is rewritten as shown in Table 5 5 to the time when the CPU clock signal is changed When changing an operation clock pulse before the standby mode or a CPU clock signal after the standby mode is released it is necessary to rewrite PCC and set the standby mode after as many machine cycles as required to change the CPU clock pulse have elapsed In a standby mode the contents of all registers and data memory that are stopped during the standby mode including general registers flags mode registers and output latches are retained 220 User s Manual U11330EJ2V1UMO00 CHAPTER 7 STANDBY FUNCTION Caution Resetall the interrupt request flags before setting the standby mode If an interrupt source whose interrupt request flag and interrupt enable flag are both set exists the initiated standby mode is released immediately after it is set see Figure 6 1 When the STOP mode is set however the 4PD750108 enters the HALT mode
41. 3 PORT PORT PORT 6 PORT 7 XA PORTn Note 1 PORTn A Note PORTn XA Note 1 A PORTn Note 1 XA PORTn Note 1 PORTn Note 1 PORTn XA Note 1 A PORTn Note XA PORTn Note 1 CY PORTn bit CY PORTn LNote 2 PORTn bit CY PORTn L CYNote 2 PORTn Note 1 PORTn bit PORTn L PORTn bit PORTn L PORTn bit PORTn L PORTn bit PORTn L SKTCLR PORTn bit SKTCLR PORTn L Note 2 AND1 CY PORTn bit AND1 CY PORTn LNote 2 OR1 CY PORTn bit OR1 CY PORTn LNote 2 XOR1 CY PORTn bit XOR1 Notes 80 CY PORTn LNote 2 1 MBE 0 or MBE 1 MBS 15 must be set before execution 2 The low order two bits of an address and bit address are indirectly specified using the L register User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5 1 4 Digital Port Operation When a data memory manipulation instruction is executed for a digital I O port the operation of the port and pins depends on the I O mode setting Table 5 3 This is because data taken in on the internal bus is the data input from the pins in the input mode or the output latch data in the output mode as obvious from the configurations of I O ports 1 Operation when the input mode is set 2 D
42. 56 us at 1 MHz 2 INT4 is useful User s Manual U11330EJ2V1UM00 99 uPD750108 USER S MANUAL 5 2 4 Clock Output Circuit 1 Configuration of the clock output circuit Figure 5 20 shows the configuration of the clock output circuit 2 Functions of the clock output circuit The clock output circuit outputs a clock pulse from the P22 PCL pin and is applicable to a remote control waveform output or can be used to supply clock pulses to peripheral LSI devices The procedure for outputting a clock pulse signal is as follows Select a clock output frequency and disable clock output Write a 0 in the P22 output latch Set the output mode for port 2 Enable clock output Figure 5 20 Configuration of the Clock Output Circuit From the clock generator Output fcc 2 buffer Selector 4 fool2 gt PCL P22 26 PORT2 2 Bit 2 of PMGB Port 2 input E output mode aic specification bit Internal bus 4 Remark The clock output circuit is designed so that pulses with short widths do not appear in enabling or disabling clock output 100 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 3 Clock output mode register CLOM The CLOM is a 4 bit register to control clock output The CLOM is set by a 4 bit memory manipulation instruction Example CPU clock is output on the PCL P22 pin SEL MB15 or CLR1 MBE A 41000B MOV CLOM A A RESET signal clears the
43. BC then sets the result in the XA register pair C gt gt XOR rp t XA Function rp 1 rp 1 XA Exclusive ORs the contents of register pair HL DE BC XA HL DE BC with the contents of the XA register pair then sets the result in register pair rp 1 282 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET 11 4 5 Accumulator Manipulation Instructions C D RORCA Function CY lt Ag An 1 lt An lt CY n 1 3 Rotates the contents of the A register 4 bit accumulator through the carry flag one bit position to the right A CY 3 2 1 0 Bef p Econ RORC A gt Function A lt A Obtains the one s complement of the A register 4 bit accumulator that is inverts each bit of the A register 11 4 6 Increment Decrement Instructions INCS reg Function reg lt reg 1 Skip if reg 0 Increments the contents of register reg X A H L D E B C If the result of increment produces reg 0 the immediately following instruction is skipped C INCS rp1 Function lt 1 1 Skip if OOH Increments the contents of register pair rp1 HL DE BC If the result of increment produces rp1 00H the immediately following instruction is skipped INCS HL Function HL lt HL 1 Skip if HL 0 Increments the data at the data memory location addressed by the HL register pair If the result of in
44. BT CSI TO T1 W 0 1 2 4 11 4 13 I O Instructions IN A PORTn Function lt 0 8 Transfers the contents of the port specified by PORTn 0 8 to the A register Caution Before this instruction can be executed MBE 0 or MBE 1 MBS 15 must be set A number from 0 to 8 can be specified as n Depending on I O mode specification output latch data in the output mode or pin data in the input mode are transferred IN XA PORTn Function lt PORTn X lt PORTu4 4 6 Transfers the contents of the port specified by PORTn n 4 or 6 to the A register then transfers the contents of the next port to the X register Caution Only the number 4 or 6 can be specified as n Before this instruction can be executed MBE 0 or MBE 1 MBS 15 must be set Depending on I O mode specification output latch data in the output mode or pin data in the input mode are transferred D OUT PORTn Function A n N39 2 8 Transfers the contents of the A register to the output latch of the port specified by PORTn n 2 8 Caution Before this instruction can be executed MBE 0 or MBE 1 MBS 15 must be set A number from 2 to 8 can be specified as n D our PORTh Function PORTn lt A PORTu4 X 0 4 6 Transfers the contents of the A register to the output latch of the port specified by PORTn n 4 6 then transfers the contents o
45. Function rp 1 rp 1 XA Skip if borrow Subtracts the contents of the XA register pair from the contents of register pair rp 1 HL DE BC XA HL DE BC then sets the result in register pair rp 1 If the subtraction generates a borrow the immediately following instruction is skipped The carry flag is not affected SUBC A HL Function A CY lt A HL CY Subtracts the data at the data memory location addressed by the HL register pair together with the carry flag from the contents of the A register then sets the result in the A register If the subtraction generates a borrow the carry flag is set If no borrow is generated the carry flag is reset If the execution of this instruction generates no borrow when this instruction is followed by the ADDS A 14 instruction the ADDS A n4 instruction is skipped If a borrow is generated the ADDS A 14 instruction is executed and the skip function of the ADDS A n4 instruction is disabled Accordingly a combination of these instructions can be used for number system conversion See Section 11 1 SUBC XA rp Function XA CY lt XA rp CY Subtracts the contents of register pair rp XA HL DE BC XA HL DE BC together with the carry flag from the contents of the XA register pair then sets the result in the XA register pair If the subtraction generates a borrow the carry flag is set If no borrow is generated the carry flag is reset
46. I ISOLNI O ofp3 00d 7LNI U11330EJ2V1UM00 User s Manual 188 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 6 2 TYPES OF INTERRUPT SOURCES AND VECTOR TABLES Table 6 1 lists the types of interrupt sources and Figure 6 2 shows vector tables Table 6 1 Interrupt Sources Interrupt Vectored interrupt request priorityNote vector table address Interrupt source signal Reference time interval signal from VRQ1 0002H basic interval timer wactchdog timer Detection of both rising and falling edges Rising falling edge 7 VRQ2 0004H detection specification VRQ3 0006H INTCSI Serial data transfer completion signal VRQ4 0008H INTTO Match signal between the count VRQ5 000AH register of timer event counter 0 and modulo register Match signal between the count VRQ6 000CH register of timer counter 1 and modulo register Note The interrupt priority is used to determine the priority when two or more interrupts are simultaneously generated Figure 6 2 Interrupt Vector Table Address 0000H Internal reset start address high order 6 bits Internal reset start address low order 8 bits 0002H INTBT INT4 start address high order 6 bits INTBT INT4 start address low order 8 bits 000
47. MD3 pins as listed in the table below Operating mode specification Operating mode Vpp MDO MD2 Program memory address clear mode Write mode Verify mode H L L H Program inhibit mode Remark X indicates L or H 9 2 WRITING TO THE PROGRAM MEMORY The procedure for writing to program memory is described below high speed write is possible 1 Pull low all unused pins to Vss by means of resistors Bring CL1 to low level Apply 5 V to Vpp and to Vpp Wait 10 us Select program memory address clear mode Apply 6 V to Vpp and 12 5 V to Vpp Select write mode for 1 ms duration and write data Select verify mode If write is successful proceed to step 8 If write fails repeat steps 6 and 7 Perform additional write for Number of repetitions of steps 6 and 7 x 1 ms duration Increment the program memory address by inputting four pulses on the CL1 pin Repeat steps 6 to 9 until the last address is reached Select program memory address clear mode Apply 5 V to Vpp and to Vpp Turn the power off 2 3 4 5 6 7 8 9 10 11 12 13 234 User s Manual U11330EJ2V1UMO00 CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY PROM The timing for steps 2 to 9 is shown below Repeat x times Additional Address Write Verify write increment MM __ 00 40 03 43 X f
48. Operand Machine cycle RETINote 1 uPD750104 0 0 0 0 lt SP 1 PC41 9 lt SP SP 3 SP 2 PSW SP 4 SP 5 SP SP 6 1 0750106 uPD750108 0 0 0 PC42 SP 1 PC44 9 lt SP SP 3 SP 2 PSW SP 4 SP 5 SP lt SP 6 75 0116 0 0 PCs PC42 SP 1 PC41 9 lt SP SP 3 SP 2 PSW lt SP 4 SP 5 SP SP 6 SP 1 SP 2 rp SP SP 2 SP 1 lt MBS SP 2 lt RBS SP SP 2 Subroutine stack control rp lt SP 1 SP SP lt SP 2 MBS SP 1 RBS SP SP SP 2 IME IPS 3 lt 1 1 Interrupt control IME IPS 3 0 0 lt PORT n 0 8 lt PORT 4 PORT n 4 6 PORT lt 2 8 PORT XA PORT 4 PORT lt XA n 4 6 Set HALT Mode PCC 2 lt 1 To To PY Set STOP Mode PCC 3 1 CPU control No Operation Notes 1 The shaded portion is supported in Mk Il mode only The other portions are supported in Mk mode only 2 MBE 0 or MBE 1 and MBS 15 must be set when an IN OUT instruction is executed User s Manual U11330EJ2V1UMO00 259 uPD750108 USER S MANUAL Note The TBR and TCALL instructions are assembler pseudo instructi
49. The format of serial data and signal used in the SBI mode are described below Serial data to be transferred in the SBI mode is classified into three types Address command and data Serial data forms one frame as shown below Figure 5 51 is a timing chart for transferring address command and data Figure 5 51 Timing of SBI Transfer Address transfer 580 581 Bus release signal Command transfer Command signal 580 581 Data transfer SCK LJ LILI LILILI Li lel lel LILI LIL 80 58 UK OCOCOCOCOCOXeeWe aey The bus release signal command signal are output the master BUSY is output by a slave ACK is output by either the master or a slave Normally the device which received 8 bit data outputs ACK The master continues to output the serial clock from when 8 bit data transfer starts to when BUSY is released User s Manual U11330EJ2V1UMO00 155 uPD750108 USER S MANUAL a Bus release signal REL When the SCK line is high the serial clock is not output the SBO or SB1 line changes from low to high This signal is called the bus release signal and is output by the master Figure 5 52 Bus Release Signal ew This signal indicates that the master is to send an address to slave Slaves contain hardware to detect the bus release signal b Command signal CMD When the SCK line is high the serial clock is not output the SBO or SB1 line changes from high to low T
50. XOR1 XOR1 XOR1 320 A HL 250 280 rp 1 XA 250 280 XA rp 250 280 A HL 250 279 rp 1 XA 250 280 XA rp 250 279 addr 260 292 laddr 260 294 A mem 249 273 A reg1 249 273 A HL 249 272 A HL 249 272 A HL 249 272 A rpal 249 272 XA mem 249 273 XA rp 249 273 XA HL 249 273 A n4 251 282 A HL 251 282 rp 1 XA 251 282 XA rp 251 282 fmem bit 252 288 CY pmem L 252 288 CY H mem bit 252 288 User s Manual U11330EJ2V1UMO00 APPENDIX E HARDWARE INDEX HARDWARE INDEX ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE NAME A Acknowledge detection flag ACKD 135 Acknowledge enable bit ACKE 135 Acknowledge trigger bit ACKT 135 B Bank select register BS 67 Basic interval timer BT 103 Basic interval timer mode register BTM 103 Bit sequential buffer BSBO BSB3 184 BT interrupt enable flag IEBT 191 BT interrupt request flag IRQBT 191 Bus release detection flag RELD 136 Bus release trigger bit RELT 136 Busy enable bit BSYE 135 C Carry flag CY 64 Clock mode register WM 109 Clock output mode register CLOM 101 Command detection flag CMDD 135 Command trigger bit CMDT 136 I Interrupt enable flag for clock timer IEW 214 Interrupt master enable flag IME 193 Interrupt
51. after executing the instruction being executed an interrupt processing of three machine cycles is executed then the interrupt service routine is started An instruction other than interrupt control instruction A IRQxxx is set C Interrupt processing 3 machine cycles D Interrupt service routine is executed User s Manual U11330EJ2V1UMO00 205 uPD750108 USER S MANUAL 6 8 EFFECTIVE USE OF INTERRUPTS The interrupt function can be used more effectively in the ways described below 1 MBE 0 is set for the interrupt service routine By allocating addresses 00H to 7FH as data memory used by the interrupt service routine and specifying MBE 0 in an interrupt vector table the user can code a program without being concerned with a memory bank If a program must use memory bank 1 for some reason save the memory bank select register using the PUSH BS instruction before selecting memory bank 1 2 Use different register banks for the normal routine and interrupt routine The normal routine uses register banks 2 and 3 with RBE 1 and RBS 2 If the interrupt routine is for one nested interrupt use register bank 0 with RBE 0 so that you do not have to save or restore the registers When two or more interrupts are nested set RBE to 1 save the register bank by using the PUSH BS instruction and set RBS to 1 to select register bank 1 3 Use of a software interrupt for debugging Setting an interrupt request fla
52. before an interrupt occurs The interrupt status flag can be manipulated using a memory manipulation instruction and the status of processing being performed can be changed by program control Caution The user must always disable interrupts with the DI instruction before manipulating this flag and must enable interrupts with the El instruction after manipulating this flag 4 Memory bank enable flag MBE 5 66 The memory bank enable is a 1 bit flag used to specify the address information generation mode for the high order four bits of a 12 bit data memory address The MBE can be set or reset any time with a bit manipulation instruction regardless of memory bank setting When the MBE is set to 1 the data memory address space is expanded allowing all data memory space to be addressed When the MBE is reset to 0 the data memory address space is fixed regardless of MBS setting See Figure 3 2 A RESET signal automatically initializes the MBE by setting the MBE to the content of bit 7 at program memory address 0 In vectored interrupt processing the MBE is automatically set to the content of bit 7 in the vector address table for servicing the interrupt Usually the MBE is set to 0 in interrupt processing and static RAM in memory bank 0 is used Register bank enable flag RBE The register bank enable flag is a 1 bitflag used to determine whether to expand the general register bank configuration The RBE
53. n PC42 0 1 Branches to the address specified by the program counter whose low order 12 bits have been replaced with the 12 bit immediate data caddr Aj1 9 Since the program counter of the uPD750104 consists of 11 bits this instruction enables a branch to any location in the program memory space In the uPD750106 and PD750108 PC42 cannot be changed so no branch occurs beyond the block Similarly in the PD75P0116 12 and PC43 cannot be changed so no branch occurs beyond the block Caution The BRCB caddr instruction usually causes a branch within the block containing the instruction However if the first byte is located at address OFFEH or OFFFH a branch to block 1 instead of block 0 occurs Program memory 7 0 Block 0 OFFEH OFFFH b 1000H Block 1 If the BRCB caddr instruction is located at a or b in the figure above a branch to block 1 instead of block 0 occurs Remark Function in this section is applicable to the uPD750108 whose program counter consists of 13 bits addr OOOOH to 1FFFH However this is also applicable to the uPD750104 whose program counter consists of 12 bits addr 0000H to OFFFH the uPD750106 whose program counter consists of 13 bits addr OOOOH to 17FFH and the uPD75P0116 whose program counter consists of 14 bits addr 0000H to 3FFFH 290 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET C2 BR PCDE Function For the J PD750108
54. 0 Command detection flag R Condition for being cleared CMDD 0 Condition for being set CMDD 1 lt 1 gt The transfer start instruction is executed The command signal CMD is detected lt 2 gt The bus release signal REL lt 3 gt The RESET signal is generated lt 4 gt CSIE 0 See Figure 5 40 User s Manual U11330EJ2V1UMO00 135 uPD750108 USER S MANUAL Figure 5 41 Format of Serial Bus Interface Control Register SBIC 3 3 Bus release detection flag R Condition for being cleared RELD 0 Condition for being set RELD 1 The transfer start instruction is executed The bus release signal REL is detected The RESET signal is generated CSIE 0 See Figure 5 40 SVA does not match SIO when an address is received Command trigger bit W Control bit for command signal CMD trigger output By setting CMDT 1 the SO latch is cleared Then the CMDT bit is automatically cleared to 0 Caution Never clear SBO or SB1 during serial transfer Be sure to clear SBO or SB1 before or after serial transfer Bus release trigger bit W Control bit for bus release signal REL trigger output By setting RELT 1 the SO latch is set to 1 Then the RELT bit is automatically cleared to 0 Caution Never clear SBO or SB1 during serial transfer Be sure to clear SBO or SB1 before or after serial transfer Examples 1 A command signal is output SEL MB15 or CLR1 MBE S
55. 1 e uPD750106 uPD750108 PC42 9 lt BCXANote 2 uPD75P0116 PC13 9 BCXANote 3 BRANote 4 e uPD750104 PC11 9 addr UPD750106 uPD750108 2 0 lt uPD75P0116 lt addr1 Icaddr e uPD750104 11 0 e 0750106 750108 12 0 12 1 e uPD75P0116 PC13 9 lt 13 12 caddr11 0 CALLANote 4 laddr1 e uPD750104 8 2 lt x x MBE RBE SP 6 SP 3 SP 4 lt PC11 o SP 5 lt 0 0 0 0 PC44 9 addr SP lt SP 6 uPD750106 PD750108 SP 2 lt x x MBE RBE SP 6 SP 3 SP 4 lt 1 9 SP 5 lt 0 0 0 PCy PC12 9 lt addr SP SP 6 e uPD75P0116 SP 2 lt x x MBE RBE SP 6 SP 3 SP 4 lt 11 0 5 0 0 PCi3 PC42 PC13 9 lt addr1 SP lt SP 6 Subroutine stack control Notes 1 Set register B to 0 2 Only the LSB is valid in register B 3 Only the low order two bits are valid in register B 4 The shaded portion is supported in Mk mode only The other portions are supported in Mk mode only User s Manual U11330EJ2V1UMO00 255 uPD750108 USER S MANUAL Address Operation ing Skip condition area Operand Machine cycle uPD750104 SP 3 lt MBE RBE 0 0 SP 4 SP 1 SP 2 lt PC14 9 PC44 9 lt addr SP lt SP 4 750106 uPD75010
56. 2 2 244 Hz 100 279 977 Hz 28 3 91 kHz 1 26 15 6 kHz Other than above Not to be set Timer start indication bit TM13 When 1 is written into the bit the counter and IRQT1 flag are cleared If bit 2 is set to 1 count operation is started Operation mode 12 Count operation Stop retention of count contents Count operation 116 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 2 Timer event counter output enable flag TOEO TOE1 The timer event counter output enable flag TOEO TOE1 controls the output enable disable to the PTOO and PTO 1 pins in the timer out flip flop TOUT flip flop status The timer out flip flop is inverted by the match signal sent from the comparator When bit 3 of the timer event counter mode register TM1 is set to 1 the timer out flip flop is cleared to 0 TOEO TOE1 and timer out flip flop are cleared to 0 by a RESET signal generation Figure 5 32 Timer Event Counter Output Enable Flag Format Address FA2H Channel 0 FAAH Channel 1 Timer event counter output enable flag W 0 Disabled 1 Enabled 5 5 2 8 Bit Timer Event Counter Mode Operation It is used as an 8 bit timer event counter in this mode It performs an 8 bit programmable interval timer and event counter operation channel 0 only 1 Register setting The following three registers and one flag are used in the 8 bit time
57. 221 7 8 OPERATION AFTER A STANDBY MODE IS RELEASED 223 7 4 SELECTION OF A MASK OPTION nnns en 223 7 5 APPLICATIONS OF THE STANDBY MODES esee 224 User s Manual U11330EJ2V1UMO00 CHAPTER 8 CHAPTER 9 CHAPTER 10 CHAPTER 11 RESET FUNCTION 11 229 WRITING TO AND VERIFYING PROGRAM MEMORY PROM 233 9 1 OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORY Pe etr eta roe ere edges Mr rrt ict erdt teal 234 9 2 WRITING TO THE PROGRAM MEMORY 234 9 3 READING THE PROGRAM MEMORY enne nennen nns 236 9 4 SCREENING OF ONE TIME PROM nnns 237 MASK OPTION cm 239 PIN tA etd t EI e 239 10 2 MASK OPTION OF STANDBY FUNCTION eene nens 239 10 3 MASK OPTION FOR FEEDBACK RESISTOR OF SUBSYSTEM CLOCK 240 INSTRUCTION m 241 11 1 UNIQUE nentes innert nens innen 241 11 41 6 ceedacei tives ett t Ee initia et 241 11 1 2 Manipulation Instruction ees 242 11 1 3 String Effect Instructions 242 11 1 4 Number System Conversion Instructions sees 243 11 1 5 Skip Instructions and the Number of
58. 299 User s Manual U11330EJ2V1UMOO APPENDIX A APPENDIX B APPENDIX C APPENDIX D APPENDIX E APPENDIX F FUNCTIONS OF THE uPD750008 uPD750108 AND 75 0116 303 DEVELOPMENT 5 305 MASKED ROM ORDERING PROCEDURE rere ener 313 INSTRUCTION INDEX rennen nnne nnne nn nr intra san sns n antea snas 315 D 1 INSTRUCTION INDEX BY FUNCTION seeeneenen emn 315 D 2 INSTRUCTION INDEX ALPHABETICAL ORDER eee 318 HARDWARE INDEX 321 E 1 HARDWARE INDEX ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE NAME rne etr etit Fere Er ei t pn eter de ea irre eei 321 E 2 HARDWARE INDEX ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE SYMBOL seen rennen enne trennt nenne 323 REVISION HISTORY nnne nnns tnis ntn sites sns s sna strane 325 User s Manual U11330EJ2V1UMO00 LIST OF FIGURES 1 4 Figure No Title Page 2 1 Pin Input Output Circuits en neni nnns innen 19 3 1 Use of MBE 0 Mode and MBE 1 Mode 24 3 2 Data
59. 3FFFH User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET 11 4 11 Subroutine Stack Control Instructions Cu CALLA addr1 Function For the uPD750108 SP 2 lt x x MBE SP 3 PCz 4 SP 4 lt PC3 o 5 5 0 0 0 PCi2 SP 6 PC 11 8 PC12 0 lt addr1 SP lt SP 6 CALL Function For the u PD750108 Mk mode SP 1 lt 7 4 SP 2 SP 3 MBE RBE 0 12 SP 4 lt 11 8 PC12 0 lt addr SP SP 4 addr 0000H 1FFFH Mk II mode SP 2 x x MBE RBE SP 3 PC7 4 SP 4 PC3 9 SP 5 lt 0 0 0 12 SP 6 lt PC 14 8 12 lt addr SP lt SP 6 addr 0000H 1FFFH Saves the contents of the program counter return address memory bank enable flag MBE and register bank enable flag RBE to the data memory location stack addressed by the stack pointer SP then branches to the location addressed by the 14 bit immediate data addr after decrementing SP Remark Function in this section is applicable to the uPD750108 whose program counter consists of 13 bits addr OOOOH to 1FFFH However this is also applicable to the PD750104 whose program counter consists of 12 bits addr 0000H to OFFFH the 4PD750106 whose program counter consists of 13 bits addr 0000H to 17FFH and the uwPD75P0116 whose program counter consists of 14 bits addr 0000H to 3
60. Also Used for KRO KR3 I O Pins Also Used for KR4 KR7 These are 4 bit I O ports with output latches which also have the following functions User s Manual U11330EJ2V1UM00 13 uPD750108 USER S MANUAL 1 Port 2 Timer event counter output PTOO Timer counter output PTO1 Clock output PCL Arbitrary frequency output BUZ 2 Port 3 Mode selection for program memory PROM write verify operation MDO MD3 Note 3 Ports 4 and 5 Data bus for program memory PROM write verify operation 00 03 D4 D7 Note 4 Ports 6 and 7 Key interrupt input KRO KR3 KR4 KR7 Note Provided only in the PD75P0116 Ports 4 and 5 are N ch open drain intermediate withstand voltage 13 V ports The port mode register specifies I O mode selection for each port Ports 2 4 5 and 7 can be specified in units of 4 bits Ports 3 and 6 can be specified bit by bit Ports 2 3 6 and 7 can be connected with built in pull up resistors in units of 4 bits by software This can be done by manipulating pull up resistor specification register group A POGA For ports 4 and 5 the use of built in pull up resistors can be specified bit by bit with the mask option However pull up resistors specified with the mask option are not connected to the uPD75P0116 Ports 4 and 5 and ports 6 and 7 can be paired for 8 bit I O A RESET signal places ports 2 3 6 and 7 in input mode high impedance and drives ports 4 and 5 high when a pull up resistor s
61. BS 1 Memory bank select register MBS 2 The memory bank select register is a 4 bit register used to store the high order four bits of 12 bit data memory address The contents of this register specify a memory bank to be accessed The uPD750108 allows memory banks 0 1 and 15 only to be specified The MBS is set with the SEL MBn instruction n 0 1 15 Figure 3 2 shows the range of addressing using MBE and MBS settings A RESET signal initializes the MBS to 0 Register bank select register RBS The register bank select register specifies a register bank to be used as general registers a register bank can be selected from register banks 0 to 3 The RBS is set by the SEL RBn instruction n 0 to 3 A RESET signal initializes the RBS to O User s Manual U11330EJ2V1UM00 67 uPD750108 USER S MANUAL 68 Table 4 6 Register Bank to Be Selected with the RBE and RBS Register bank Bank 0 is always selected x Don t care Bank 0 is selected Bank 1 is selected Bank 2 is selected Bank 3 is selected Always 0 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 51 DIGITAL I O PORTS The uPD750108 employs the memory mapped I O method Thus all input output ports are mapped on the data memory space Figure 5 1 Data Memory Addresses of Digital Ports Address 3 2 1 0 FFOH PORT 0 FF1H PORT 1 FF2H PORT 2 FF3H PO
62. Bit Manipulation Instructions C SET1 mem bit Function mem bit lt 1 mem 07 0 00H FFH bit By 9 0 3 Sets the bit specified by the 2 bit immediate data bit at the address specified by the 8 bit immediate data mem gt SET1 fmem bit C SET1 pmem L C D GH membit Function Bit specified in operand lt 1 Sets the bit in data memory specified by bit manipulation addressing fmem bit pnem L H mem bit CLR1 mem bit CLR1 mem bit Function mem bit Cc 0 mem Dz g 00H FFH bit By 9 0 3 Clears the bit specified by the 2 bit immediate data bit at the address specified by the 8 bit immediate data mem D fmembit CLR1 pmem L 2 H mem bit Function Bit specified in operand lt 0 Clears the bit in data memory specified by bit manipulation addressing fmem bit pmem QL H mem bit SKT mem bit 286 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET SKT mem bit Function Skip if mem bit 1 mem 07 0 00H FFH bit By 9 0 3 Skips the immediately following instruction if the bit specified by the 2 bit immediate data bit at the address specified by the 8 bit immediate data mem is 1 C 7 SKT fmem bit C SKT pmem L SKT H mem bit Function Skip if bit specified in operand 1 Skips the immediately following instruction if the bit in data memory specified by bit manipulation addressing fmem bit pnem L H mem bit is
63. CLOM to 0 disabling clock output Figure 5 21 Format of the Clock Output Mode Register Address 3 2 1 0 Symbol Clock output frequency selection bit fcc 2 MHz output 500 250 125 31 3 kHz 1 fcc 2 output 250 kHz 1 0 fcc 2 output 125 kHz 26 output 31 3 kHz fcc 1 MHz output 250 125 62 5 15 6 kHz fcc 2 output 125 kHz fcc 2 output 62 5 kHz EXE 26 output 15 6 kHz Note is the CPU clock selected by PCC Clock output enable disable bit Output disable Output enable Caution Be sure to write a 0 in bit 2 of the CLOM User s Manual U11330EJ2V1UMO00 101 uPD750108 USER S MANUAL 4 102 Application to remote control waveform output The clock output function of the uPD750108 is applicable to remote control waveform output The frequency of the carrier for remote control waveform output is selected by the clock frequency select bit of the clock output mode register Pulse output is enabled or disabled by controlling the clock output enable disable bit by software The clock output circuit is designed so that pulses with short widths do not appear in enabling or disabling clock output Figure 5 22 Application to Remote Control Waveform Output Bit 3 of CLOM E EE a PCL pin output User s Manual U11330EJ2V1UM00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5 3 BASIC INTERVAL TIMER WATCHDOG TIMER
64. CSIE 3 Clear the interrupt request flag IRQCSI User s Manual U11330EJ2V1UMO00 139 uPD750108 USER S MANUAL 5 6 5 Three Wire Serial I O Mode Operations The three wire serial I O mode is compatible with other modes used in the 75XL series 75X series uPD7500 series and 87AD series Communication is performed using three lines Serial clock SCK serial output SO and serial input SI Figure 5 43 Example of Three Wire Serial I O System Configuration 3 wire serial lt 3 wire serial I O Master CPU Slave CPU uPD750108 SCK SCK SO SI SI lt so Remark The uPD750108 can also be used as a slave CPU 1 Register setting To set the three wire serial I O mode manipulate the following two registers Serial operation mode register CSIM Serial bus interface control register SBIC a Serial operation mode register CSIM To use the three wire serial I O mode set CSIM as shown below For details CSIM format see 1 in Section 5 6 3 CSIMO is manipulated using an 8 bit manipulation instruction Bits 7 6 and 5 of CSIM can be manipulated bit by bit When the RESET signal is input CSIM is set to 00H In the figure below hatched portions indicate the bits used in the three wire serial I O mode 7 6 5 4 3 2 1 0 pu Serial clock selection bit W Address FEOH Serial interface operation mode selection bit W Wake up function specification bit W Mat
65. FUNCTIONS Figure 5 33 Timer Event Counter Mode Register Setup 2 2 b In the case of timer counter channel 1 Address 7 0 Symbol 6 5 4 3 2 1 FA8H TM16 TM15 TM14 TM13 12 TM1 Count pulse CP selection bit Count pulse CP Rising edge of INTW overflow output for clock timer fcc 2 fec 2 fcc 28 1 fcc 29 Other than above Not to be set Timer start indication bit When 1 is written to the bit the counter and IRQT1 flag are cleared If bit 2 is set to 1 count operation is started Operation mode Count operation Stop retention of count contents Count operation b Timer event counter output enable flag TOEn The TOEn is manipulated by a bit manipulation instruction The TOEn is cleared to 0 by an internal reset signal Figure 5 34 Timer Event Counter Output Enable Flag Setup Address FA2H TOEO Channel 0 FAAH TOE1 Channel 1 Timer event counter output enable flag W Disabled outputs the low level signal Enabled User s Manual U11330EJ2V1UMO00 119 uPD750108 USER S MANUAL 2 Timer event counter time setting Timer setup time cycle is found by dividing modulo register contents 1 by count pulse CP frequency selected by setting the mode register n 1 T sec ion n 1 resolution T sec Timer setup time seconds fcp Hz Count pulse frequency Hz n Modulo register content
66. INT4 4 bit input port PORTO x Input P01 SCK For P01 to built in pull up resistors A P02 SO SBO can be connected by software in units of P03 SI SB1 3 bits M C P10 Input INTO 4 bit input port PORT1 x Input B C P11 INT1 Built in pull up resistors can be connected P12 INT2 by software in units of 4 bits P13 TIO For P10 INTO the noise eliminator can be selected P20 4 bit I O port PORT2 X Input E B P21 PTO1 Built in pull up resistors can be connected P22 PCL by software in units of 4 bits P23 BUZ P30 MDO Note 2 Programmable 4 bit I O port PORTS x Input E B P31 MD1 Note 2 O can be specified bit by bit P32 MD2 Note 2 Built in pull up resistors can be connected P33 MD3 Note 2 by software in units of 4 bits Notes 1 circuits enclosed in circles have a Schmitt triggered input 2 wPD75P0116 User s Manual U11330EJ2V1UMO00 uPD750108 USER S MANUAL Pin Table 2 1 Digital I O Port Pins 2 2 Also d used Function p circuit outpu as typeNote 1 P40Note 2 DO Note 3 N ch open drain 4 bit I O port PORT4 High level when M D Withstand voltage is 13 V in open drain a pull up resistor M E Note 3 P41Note 2 D1 Note 3 mode is provided or A pull up resistor can be provided bit high impedance P42Note 2 D2 Note 3 by bit mask option Note 4 P43Note 2 D3 Note 3 verifying lower 4 bits of program Data input ou
67. INTERRUPT AND TEST FUNCTIONS 3 Nesting of interrupts with higher priority INTBT has higher priority and INTTO and INTCSI have lower priority lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt Reset RBE 1 MBE 0 SEL RB2 EI IEBT EI IETO EI IECSI 1 MOV A 9 MOV IPS A Status 0 INTTO service program T 0 lt INTBT service program gt T 1 lt 2 gt INTTO 4 SEL RB1 Status 2 5 SEL RB2 RETI INTBT is specified as having the higher priority by setting of IPS and the interrupt is enabled at the same time INTTO service program is started when INTTO with the lower priority occurs Status 1 is set and the other interrupts with the lower priority are disabled RBE 0 to select register bank 0 INTBT with the higher priority occurs The level two interrupts occurs The status is changed to 0 and all the interrupts are disabled RBE 1 and RBS 1 to select register bank 1 only the registers used may be saved by the PUSH instruction RBS is returned to 2 and execution returns to the main program The status is returned to 1 User s Manual U11330EJ2V1UMO00 209 uPD750108 USER S MANUAL 4 Execution of held interrupts interrupt requests when interrupts are disabled lt Main program gt Reset IEO lt INTO service program gt 1 INTO 3 INTCSI 2 El RETI INTCSI service program
68. INTO start address low order 8 bits INT1 start address INT1 start address low order 8 bits Internal reset start address ow order 8 bits NTCSI start address high order 4 bits ow order 8 bits INTTO start address low order 8 bits INTT1 start address wee meE o INTCSI start address NTTO start address high order 4 bits NTT1 start address ow order 8 bits GETI instruction reference table Note Can be used only in the MkII mode Remark Entry address specified in CALLF faddr instruc tion User s Manual U11330EJ2V1UM00 Figure 4 3 Program Memory Map in 1 0750104 Branch address specified in BRCB Icaddr instruc tion Branch address specified in BR addr BR BCDE BR BCXA BRA laddr1Nete CALL laddr or CALLA Branch call address by GETI Relative branch address specified in BR addr instruction 715 to 1 2 to 16 In addition to the above the BR PCDE and BR instructions can cause a branch to an address with only the 8 low order bits of the PC changed 51 uPD750108 USER S MANUAL 0000H 0002H 0004H Figure 4 4 Program Memory Map in uPD750106 Internal reset start address 20288 INTBT INT4 start address NTBT INT4 start address INTO start address low order 8 bits CEs Internal reset start address high order 5 bits high order 5 bits
69. Ifthe CPU clock is changed required machine cycles must elapse before the standby mode is set Select a wait time to be used when a standby mode is released Set a standby mode using a STOP or HALT instruction A standby mode when combined with the system clock switch function enables a lower power consumption and lower voltage operation 1 Application of the STOP mode at fcc 1 MHz 224 lt Use of the STOP mode under the following conditions gt The STOP mode is set on the falling edge of INT4 and is released on the rising edge of INT4 INTBT is not used All I O ports have a high impedance The INTO and INTTO interrupts are used for the program but are not used to release the STOP mode After the STOP mode is released interrupts are enabled After the STOP mode is released operation is started using the lowest speed CPU clock The wait time applied when the STOP mode is released is set to 512 us by using a mask option After the STOP mode is released another wait time of 32 8 ms is used for stable power supply operation The POO INT4 pin is checked twice to remove chattering User s Manual U11330EJ2V1UMO00 CHAPTER 7 STANDBY FUNCTION lt Timing chart gt 0v POO INT4 CPU operation lt Sample program gt Operating mode HALT mode Low speed High speed wait Operation operation STOP mode Y Y Y INT4 4512 us 32 8 ms INT4 STOP instruction INT4 se
70. Machine Cycles Required for a Uta as hxc mi SIE 244 11 2 INSTRUCTION SET AND OPERATION 245 11 8 INSTRUCTION CODES OF EACH INSTRUCTION 262 11 4 FUNCTIONS AND APPLICATIONS OF THE INSTRUCTIONS 268 11 4 1 Transfer Instructions 268 11 4 2 Table Reference Instructions ssesseeenne 274 11 4 3 Bit Transfer Instructions sse 277 11 4 4 A Arithmetic Logical 277 11 4 5 Accumulator Manipulation Instructions 283 11 4 6 dncrement Decrement Instructions 283 11 4 7 X Compare 284 11 4 8 Flag Manipulation Instructions 285 11 4 9 Memory Bit Manipulation Instructions 286 11 4 10 Branch Instructions enne 288 11 4 11 Subroutine Stack Control Instructions 293 11 4 12 Interrupt Control Instructions 0 cece cece eeeeeeeeeeeeeeeaeeeeeeeeeseaeeeeeaeeteaees 297 TAAL TS OSINSTHUCU ONS ueri eren rte eit reet rtt recive 298 11 4 14 CPU Control Instructions sse enne 299 11 4 15 Special
71. Memory Organization and Addressing Range of Each Addressing Mode 26 3 3 Updating Static RAM Addresses ccccccscccceessseceeeeeeneeeeeeeceneceeeeeaaeeeeesseeeeeesssseeeeeeeeea 30 3 4 Example of Register Bank Selection sess 37 3 5 General Register Configuration 4 Bit Processing 39 3 6 General Register Configuration 8 Bit Processing 40 3 7 HPD 750108 eve eit apt D V teat eei eo dede de eae 42 4 1 Stack Bank Selection Register Format sssssssssssssseeeeee nnne 48 4 2 Program Counter Organization ssssssssssssssseeeee eene nennen nennen nnne 49 4 3 Program Memory Map in UPD750104 51 4 4 Program Memory Map in UPD750106 essen eene 52 4 5 Program Memory in UPD750108 53 4 6 Program Memory in 75 0116 enne 54 4 7 Data Memory Map iot t eb t t i ei pa perg peser Hs 56 4 8 General Register Format trennen nennen en 58 4 9 Register Pair e reed cede esee Ra Les 59 4 10 favere 59 4 11 F
72. O 4 P02 SO SBO P62 KR2 5 P03 SI SB1 P61 KR1 6 O P80 P60 KRO 7 P81 P53 D7 O 8 P30 MDO P52 D6 O 9 O P31 MD1 P51 D5 10 O P32 MD2 P50 D4 O 11 P33 MD3 NC O P43 D3 O P42 D2 O P41 D1 O 40 00 Vss XM XT2 O RESET O CL1 O CL2 O Note Connect IC Vpp to Vpp keeping the wiring as short as possible Remark uPD75P0116 User s Manual U11330EJ2V1UMO00 uPD750108 USER S MANUAL Pin name Port 0 TIO Timer input 0 P10 P13 Port 1 PTOO 1 Programmable timer output 0 1 P20 P23 Port 2 BUZ Buzzer clock P30 P33 Port 3 PCL Programmable clock P40 P43 Port 4 INTO 1 4 External vectored interrupt 0 1 4 P50 P53 Port 5 INT2 External test input 2 P60 P63 Port 6 CL1 2 RC oscillator P70 P73 Port 7 XT1 2 Subsystem clock oscillation 1 2 P80 P81 Port 8 NC No connection KRO KR7 Key return 0 7 IC Internally connected SCK Serial clock Positive power supply Sl Serial input Vss Ground SO Serial output Vpp Programming power supply 580 1 Serial bus 0 1 MDO MD3 Mode selection 0 3 RESET Reset input 00 07 Data bus 0 7 User s Manual U11330EJ2V1UMO00 CHAPTER 2 PIN FUNCTIONS 2 1 PIN FUNCTIONS OF THE uPD750108 Table 2 1 Digital I O Port Pins 1 2 Pin Input pur Function 8 bil Upon ara output typeNote 1 Input
73. Signals eene nnne renis nnne 159 5 60 Operations of RELT CMDT RELD and CMDD Master 164 5 61 Operations of RELT CMDT RELD and CMDD Slave 164 5 62 Operation ot AGIT entrate 165 5 63 Operation of AGKE uae ce e tte ieee da ee PE E ie Rd ea adde 165 5 64 Operation o AGKD iei e tet E peer ee eti Pepe re rne rect b ere brin eda 166 5 65 Operation ofi BSYE eld A daa nat re dpt Managed 167 5 66 nite c Peu Tae d re ade Pe la ate 170 5 67 Address Transfer Operation from Master Device to Slave Device WUP 1 172 5 68 Command Transfer Operation from Master Device to Slave Device 173 5 69 Data Transfer Operation from Master Device to Slave 174 5 70 Data Transfer Operation from Slave Device to Master 175 5 71 Example of Serial Bus Configuration ssssssssssseeneeeeeeen nes 177 5 72 Transfer Format of the READ Command sse 178 5 73 Transfer Format of the WRITE and END Commands 179 5 74 Transfer Format of the STOP Command sse 179 5 75 Transfer Format of the STATUS Command sse 180 5 76 Status Format of the STATUS sse 180 5 77
74. The export of this product from Japan is regulated by the Japanese government To export this product may be prohibited without governmental license the need for which must be judged by the customer The export or re export of this product from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative The information in this document is subject to change without notice Before using this document please confirm that this is the latest version Not all devices types available in every country Please check with local NEC representative for availability and additional information No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation NEC Corporation assumes no responsibility for any errors which may appear in this document NEC Corporation does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Corporation or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application exampl
75. Transfer Format of the RESET Command sse 181 5 78 Transfer Format of the CHGMST Command sse 181 5 79 Master and Slave Operation in Case of Error 182 5 80 1 Pin Circuit ttt cd pt 183 5 81 Format of the Bit Sequential Buffer sssssssssssssssseseeeneneen eene 184 User s Manual U11330EJ2V1UMOO LIST OF FIGURES 4 4 Figure No Title Page 6 1 Block Diagram of Interrupt Control Circuit essen 188 6 2 Interrupt Vector Table 189 6 3 Interrupt Priority Specification Register enne 193 6 4 Configurations of the INTO INT1 and INT4 Circuits 195 6 5 I O Timing of a Noise Eliminator sesssseseseeeeennneeenmnnen nennen 196 6 6 Format of Edge Detection Mode Registers 197 6 7 Int rr pt SEQUENCE doe et ulti ee e n it tap sida 199 6 8 Multiple Interrupt Processing by a High Order Interrupt 200 6 9 Multiple Interrupt Processing by Changing the Interrupt Status Flags 201 6 10 Block Diagram of the INT2 and KRO to KR7 Circuits 216 6 11 Format of INT2 Edge Detection Mode Register 1 2 217 7 1 Standby Mode Release Operation
76. XA rp 1 CY lt rp 1 XA CY Arithmetic logical A HL A lt A HL borrow XA rp XA XA rp borrow rp 1 XA rp lt rp 1 XA borrow A HL A CY lt A HL CY XA rp 2 XA CY lt XA rp CY rp 1 XA rp 1 CY lt rp1 XA CY Note Set register B 0 in the uPD750104 Only the LSB is valid in register B in the uPD750106 and uPD750108 Only the low order two bits are valid in the PD75P01 16 250 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET Number 4 Address Operand of Machine Operation ing Skip condition bytes cycle area lt A n4 lt A HL XA XAArp rp1 XA lt Av n4 lt Av HL XA lt XAv rp Arithmetic logical rp lt rp1v XA lt Ax n4 A lt Ay HL XA XA v rp rp lt 1 v XA CY Ao A3 CY An S5 58 Eg c 8a lt lt reg reg 1 lt rp1 1 HL lt HL 1 mem lt mem 1 reg lt reg 1 Increment decrement rp lt rp 1 Skip if reg n4 Skip if HL n4 Skip if A HL Skip if XA HL Comparison Skip if A reg Skip if XA rp CY 1 CY 0 Skip if CY 1 CY lt CY Carry flag manipulation User s Manual U11330EJ2V1UMO00 251 uPD75010
77. a device subject to serial communication commands directed to the remote device and data A slave can identify an address commands and data from received data by hardware This function simplifies the serial interface control portion of an application program The SBI function is available with devices such as the 75X series 75XL series and 78K series 8 16 bit single chip microcontrollers Figure 5 50 is an example of the SBI system configuration when the CPU with a serial interface conforming to SBI or peripheral ICs are used Figure 5 50 Example of SBI System Configuration Voo e Master CPU uPD750108 580 581 lt Slave CPU uPD750108 SCK gt SBO 581 Address 1 SCK Slave CPU SBO SB1 Address 2 n A Slave IC User s Manual SBO SB1 Address N n A U11330EJ2V1UMO00 153 uPD750108 USER S MANUAL Cautions 1 In the SBI mode the serial data bus pin SBO or SB1 is an open drain output So the serial data bus line is placed in the wired OR state A pull up resistor is required for the serial data bus line 2 To switch between the master and slave a pull up resistor is required also for the serial clock line SCK because SCK input output switching is performed between the master and slave asynchronously 1 SBI functions Conventional serial I O methods provide only data transfer functions Therefore many ports and wires are required to identify chip select signal
78. a program voltage input pin for program memory one time PROM write verify operation For normal use connect this pin to Vpp keeping the wiring as short as possible shown above 12 5 V is applied for PROM write verify operation 2 2 20 MDO MD3 for the uPD75P0116 only MDO to MD3 select a mode for program memory one time PROM write verify operation 2 2 21 00 07 for the uPD75P0116 only These are the data bus pins for the program memory one time PROM write verify operation 18 User s Manual U11330EJ2V1UM00 CHAPTER 2 PIN FUNCTIONS 2 3 PIN INPUT OUTPUT CIRCUITS Figure 2 1 shows schematic diagrams of the I O circuitry of the PD750108 Figure 2 1 Pin Input Output Circuits 1 2 Voo Q Ye gt EM CMOS input buffer Schmitt trigger input with hysteresis Type D Voo aig P U R P U R P ch enable P U R Pull Up Resistor Output disable Voo e Data Ff gt P ch OUT O HF N ch TIT Push pull output which can be set to high impedance output off for both P ch and N ch User s Manual U11330EJ2V1UM00 19 uPD750108 USER S MANUAL Figure 2 1 Pin Input Output Circuits 2 2 Voo Dec P U R P U R enable gt s I P ch IN OUT Type D O FM P U R Pull Up Resistor Data Output disable P U R P U R enable Pen IN OUT e oO Da
79. a vectored interrupt request VRQn 1 to 6 occurs This condition is also used to release a standby mode A bit manipulation instruction or 4 bit memory manipulation instruction is used to manipulate an interrupt request flag and interrupt enable flag A bit manipulation instruction allows direct manipulation regardless of MBE setting An interrupt enable flag can be manipulated using an IExxx instruction or DI IExxx instruction The SKTCLR instruction is usually used to test an interrupt request flag Example IEO Enable INTO DI IE1 Disable INT1 SKTCLR IRQCSI Skip and clear IRQCSI when it is set to 1 When an interrupt request flag is set using an instruction even if there is no interrupt request a vectored interrupt is executed in the same way as when an interrupt is requested Inputting a RESET signal clears the interrupt request and interrupt enable flags to 0 disabling all interrupts User s Manual U11330EJ2V1UMO00 191 uPD750108 USER S MANUAL Table 6 2 Set Signals for Interrupt Request Flags Interrupt Interrupt request flag Set signals for interrupt request flags enable flag Set by a reference time interval signal from the basic interval timer watchdog timer Set by a detected rising or falling edge of an INT4 P00 pin input signal Set by a detected edge of an INTO P10 pin input signal The detection edge is specified by the INTO edge detection mode register IMO Set by a detected
80. allows static output by software manipulation in addition to normal serial clock output The number of SCK pulses can be software set arbitrarily by manipulating the PO1 output latch The SO 580 02 or SI SB1 P03 pin is controlled by manipulating the and CMDT bits of SBIC The procedure for manipulating SCK P01 pin output is explained below 1 Set serial operation mode register CSIM SCK pin output mode When serial transfer is halted SCK from the serial clock control circuit is set to 1 2 Manipulate the P01 output latch by using a bit manipulation instruction 182 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Example To output one SCK PO1 pin clock cycle by software SEL MB15 CLR1 MBE MOV 10000011 SCK fcc 23 output mode MOV CSIM XA CLR1 OFFOH 1 SCK PO1 lt 0 OFFOH 1 SCK PO1 lt 1 Figure 5 80 5 Pin Circuit Configuration Address FFOH 1 PO1 SCK gt To internal circuit output latch lt Gina From the serial clock control circuit 5 SCK pin output mode The output latch is mapped to bit 1 of address FFOH A RESET signal sets the output latch to Cautions 1 During normal serial transfer the P01 output latch must be set to 1 2 The P01 output latch cannot be addressed by specifying PORTO 1 as described below The address of the latch OFFOH 1 must be coded in the operand of an i
81. bit immediate data n4 to the A register 4 bit accumulator The string effect group A can be utilized When MOV A n4 and or MOV XA n8 instructions are located contiguously the string instructions following an executed instruction are processed as NOP instructions Examples 1 The data OBH is set in the accumulator MOV A 0BH 2 Data to be output to port 3 is selected from 0 to 2 A0 MOV A 0 A1 MOV AH A2 MOV A 2 OUT 268 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET MOV reg1 n4 Function regi lt n4 n4 13 0 0 FH Transfers the 4 bit immediate data n4 to A register reg1 X H L D E B C C _ Mov Function XA n8 n8 17 0 OOH FFH Transfers the 8 bit immediate data n8 to register pair XA The string effect can be utilized When two or more of this instruction are executed in succession or when MOV A n4 instruction is located continguously the string instructions following an executed instruction are processed as NOP instructions MOV HL n8 Function HL n8 8 17 9 OOH FFH Transfers the 8 bit immediate data n8 to register pair HL The string effect can be utilized When two or more of this instruction are executed in succession the string instructions following an executed instruction are processed as NOP instructions rp2 n8 Function rp2 lt n8 n8 15 0 OOH FFH Transfers the 8 bit immediate data n8 to register pair rp2 B
82. can be set or reset any time with a bit manipulation instruction regardless of memory bank setting When the RBE is setto 1 aset of general registers can be selected from register banks 0 to 3 depending on the setting of the register bank select register RBS User s Manual U11330EJ2V1UMO00 CHAPTER 4 INTERNAL CPU FUNCTIONS When the is reset to 0 register bank 015 always selected as general registers regardless of the setting of the RBS A RESET signal automatically initializes the RBE by setting the RBE to the state of bit 6 at program memory address 0 When a vectored interrupt occurs the RBE is automatically set to the state of bit 6 in the vector address table for servicing the interrupt Usually the RBE is set to 0 in interrupt processing Register bank 0 is used for 4 bit processing and register banks 0 and 1 are used for 8 bit processing 4 9 BANK SELECT REGISTER BS The bank select register BS consists of a register bank select register RBS and memory bank select register MBS which specify a register bank and memory bank to be used respectively The RBS and MBS are set using the SEL RBn instruction and SEL MBn instruction respectively The contents of the BS can be saved to or restored from a stack memory eight bits at a time by using the PUSH BS POP BS instruction Figure 4 17 Bank Select Register Format Address Symbol F83H ES F82H 4 F82H MBS3 MBS2 MBS1 MBSO RBS1 RBSO
83. can be specified by software for some pins or a mask option for the other pins Table 5 4 shows how a built in pull up resistor is specified for each port pin The built in pull up resistor is connected by software in the format shown in Figure 5 8 In input mode the pull up resistor can be connected only to the pins of port 3 and 6 When the pins are set in output mode the pull up resistor cannot be connected regardless of the settng of POGA Table 5 4 Specification of Built In Pull Up Resistors Port pin name Pull up resistor incorporation specification method Specified bit Port 0 P01 P03 Note Connection specification by software in units of 3 bits Port 1 P10 P13 Connection specification by software in units of 4 bits Port 2 P20 P23 Port 3 P30 P33 Port 4 P40 P43 Connection specification by software bit by bit Port 5 P50 P53 Port 6 P60 P63 Connection specification by software in units of 4 bits Port 7 P70 P73 Port 8 P80 P81 Connection specification by software in units of 2 bits Note The POO pin cannot specify connection of a built in pull up resistor Remark Pull up resistors specified with the mask option are not connected to the uPD75P01 16 User s Manual U11330EJ2V1UMOO 83 uPD750108 USER S MANUAL Figure 5 8 Pull Up Resistor Specification Register Format ped Specification contents Built in pull up resistor not connected Built in pull
84. clock is explained using Figure 5 19 Figure 5 19 Changing the System Clock and CPU Clock Commercial ON power line voltage OFF Lowest speed operation supply voltage pin voltage RESET signal Wait Note 1 System clock Y fxr fcc os A 32 us 2us 122035 2us M fxr 32 768 kHz nternal rese i operation 1 i i lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 1 gt A RESET signal starts CPU operation at the lowest speed of the main system clock 32 us at 2 MHz 64 us at 1 MHz after a wait timeNote 1 for stable oscillation lt 2 gt The PCC is rewritten for highest speed operation after a time elapse which is sufficient for the voltage on the Vpp pin to be high enough for highest speed operation lt 3 gt The removal of commercial current is detected using for example an interrupt inputNote 2 then bit 0 of the SCC is set to 1 to operate with the subsystem clock In this case subsystem clock generation must have been started After a time 15 machine cycles required to switch to the subsystem clock elapses bit 3 of the SCC is set to 1 to terminate main system clock generation 4 After detecting the input of commercial current by using an interrupt bit 3 of the SCC is cleared to start main system clock generation After a time required for stable generation bit 0 of the SCC is cleared to 0 to operate at the highest speed Notes 1 The wait time is fixed to 56 fcc 28 us at 2 MHz
85. design your system User s Manual U11330EJ2V1UM00 MEMO User s Manual U11330EJ2V1UMOO CHAPTER 1 CHAPTER 2 CHAPTER 3 CONTENTS GENERAL canat d aad rere ata cnp 1 1 1 FUNCTION OVERVIEW otro rie rft eet e tatio 2 1 2 SOBDERINGANROBMATIONS aeta esas serpunt 3 1 3 DIFFERENCES AMONG uPD750108 SUBSERIES PRODUCTS 4 iE BLOCK DAGAA M Monta n 5 1 5 PIN CONFIGURATION VIEW re het GR Reate tun 6 PIN FUNCTIONS aset dette dae tati tet tete ertet 9 Bai PIN FUNCTIONS OF THE PD750108 octets tta ette titan 9 22 PIN IEDC TONS 13 224 PO0 P03 PORTO P10 P13 PORTA icit tecti 13 2 2 2 20 23 PORT2 P30 P33 PORT3 P40 P43 PORTA P50 P53 PORTS P60 P63 PORT6 P70 P73 7 13 2 2 3 __ P80 P81 PORTB 14 POG REO 14 BOG BIOUOPRO eis 15 LOC NER CEPI 15 15 BOB SCK SO SBO SI SB1 oen terit a er dedit ar erii 15 DX MEI PROIN NE RE 15 2510 RR EET 16 16 2 2 12 KRO KP3 KR4 KP7 17 Dos cole aM iM MU 17 ONT WES qu SERERE PS 17 EROR 18 18 BOA 18 2 248 1 for 750104 750106 and uPD750108 only 18 2 2 19 VPP for the 7
86. equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under ce
87. gt Slave Schmitt input b 580 581 Pin for serial data I O Output to SBO or SB1 is an N ch open drain output and input is Schmitt input for both the master and a slave The serial data bus line must be externally pulled up because it has originally an N ch open drain output Figure 5 66 Pin Configuration Slave device LJ LJ lt Ho Clock output Clock output y gt gt gt Clock input Serial clock Clock input N ch open drain SBO SB1 i SBO SB1 N ch open drain gt SO us Serial data bus es SO Master device Caution When data is received the N ch transistor must be turned off so FFH must be written to SIO beforehand The N ch open drain output can be turned off at any time during transfer However when the wake up function specification bit WUP is set to 1 the N ch transistor is always off so there is no need to write FFH to SIO before reception 170 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 7 8 9 Address match detection method In the SBI mode communication starts when the master selects a particular slave device by outputting an address An address match is detected by hardware The slave address register SVA is available In the wake up state WUP 1 IRQCSI is set only when the address transmitted by the master and the value held in SVA match Cautions 1 Whether a slave is selected is determi
88. have been added p 21 Section 2 4 has been changed pp 234 to 235 Section 9 2 has been changed p 236 Section 9 3 has been changed p 267 Modification of the instruction list in 11 3 Op code of Each Instruction pp 303 to 304 The target for comparison in the table of Appendix A has been changed from the uPD75008 to the PD750008 p 325 Appendix F has been added The mark shows major revised points User s Manual U11330EJ2V1UMOO Readers Purpose Configuration Guidance PREFACE This manual is intended for engineers who want to learn the capabilities of the uPD750104 uPD750106 uPD750108 and uwPD75P0116 to develop application sys tems based on them The purpose of this manual is to help users understand the hardware capabilities shown below of the PD750104 uPD750106 uPD750108 and uPD75P0116 This manual is roughly divided as follows General Pin functions Architecture feature and memory map Internal CPU functions Peripheral hardware functions Interrupt and test functions Standby function Reset function Writing to and verifying program memory PROM Mask option Instruction set Readers of this manual should have general knowledge of the electronics logical circuit and microcomputer fields e For users who have used the uPD750008 See Appendix A to check for any difference in the functions and read the explanation of those di
89. in binary to a decimal number A time related application may require sexagesimal conversion For this reason the instruction set of the LPD750108 contains number system conversion instructions for converting the result of a 4 bit data addition or subtraction to a number in an arbitrary number system a Number system conversion for addition b Let m be a desired number system after conversion The following combination of instructions adds the contents of an accumulator to data in memory HL then converts the result of the addition to number system m ADDS A 16 m ADDC A HL A CY lt A HL CY ADDS A m An overflow is set in the carry flag If the execution of the instruction ADDC A HL generates a carry the next instruction ADDS A n4 is skipped If no carry is generated ADDS A n4 is executed In this case the skip function of this instruction ADDS A n4 is disabled so that even if this addition generates a carry the instruction following this instruction is not skipped Accordingly programs can be written after ADDS A n4 Example An accumulator is added to memory data in decimal ADDS A 6 ADDC A HL A CY lt A HL CY ADDS A 10 Number system conversion for subtraction Let m be a desired number system after conversion The following combination of instructions subtracts data in memory HL from the contents of an accumulator then converts the result of the subtraction to number system m
90. in each mode Used in the SBI mode only to set IRQCSI only when an address received after bus release matches the data in the slave address register wake up state SBO or SB1 goes to high impedance state Caution When WUP 1 is set during BUSY signal output BUSY is not released In the SBI mode the BUSY signal is output until the next falling edge of the serial clock SCK appears after release of BUSY is directed Before setting WUP 1 be sure to confirm that pin SBO or SB1 is high after releasing BUSY User s Manual U11330EJ2V1UMO00 131 uPD750108 USER S MANUAL Figure 5 40 Format of Serial Operation Mode Register CSIM 3 4 Serial interface operation mode selection bit W Operation Bit order of P02 SO SBO pin PO3 SI SB1 pin mode shift register function function 3 wire 107 9 lt gt XA SO CMOS output SI CMOS input serial Transfer starting mode with MSB 109 7 lt gt XA Transfer starting with LSB SBI mode 5107 0 SBO CMOS input Transfer starting N ch open drain I O with MSB P02 CMOS input SB1 N ch open drain I O 2 wire 5107 lt gt XA SBO CMOS input serial Transfer starting N ch open drain 1 0 UO meds MaRS P02 CMOS input SBI N ch open drain I O Remark x Don t care Serial clock selection bit W Serial clock MESE SCK pin mode 3 wire serial mode SBI mode 2 w
91. in the MBE 0 mode a fixed space consisting of the static RAM area ranging from 000H to 07FH and the peripheral hardware area ranging from F80H to FFFH can be addressed In the MBE 1 mode MB MBS and specifiable data memory space can be expanded to the entire space This addressing mode can be applied to the MOV XCH INCS IN and OUT instructions Caution Less efficient program processing results if data associated with an I O port is stored in the static RAM area of bank 1 asin Example 1 The modification of the MBS as contained in Example 2 becomes unnecessary in the programming if data associated with an I O port is stored at addresses 00H to 7FH of bank 0 Examples 1 The data contained in BUFF is output on port 5 BUFF EQU 11AH BUFF located at address 11AH SET1 MBE MBE lt 1 SEL MB1 MBS lt 1 MOV A BUFF A lt BUFF SEL MB15 MBS 15 OUT PORT5 A PORT5 lt 2 Data on port 4 is entered and is saved in DATA1 DATA1 EQU 5FH DATA1 located at address 5FH CLR1 MBE MBE lt 0 IN A PORT4 A lt PORTA MOV DATA1 A 0 lt 8 bit direct addressing mem In this addressing mode the operand of an instruction directly specifies any area in the data memory space in units of eight bits The operand can specify an even address The 4 bit data at the address specified in the operand and the 4 bit data at the address incremented by 1 are processed as a pair on an 8 bit basis with th
92. indicating error occurrence and cancels all command processing being performed When the transmission of one byte is completed the master checks for ACK from the slave User s Manual U11330EJ2V1UMO00 181 uPD750108 USER S MANUAL If ACK is not returned from the slave within a predetermined period after transmission completion the occurrence of an error is assumed the master outputs the ACK signal as a dummy Figure 5 79 Master and Slave Operation in Case of Error Processing by slave Reception is completed Error is assumed and processing is halted SBO SB1 Erroneous data ACK ACK wait time m Processing by master ACK from slave is checked Transfer is completed Us Error is assumed ACK check is started ACK is output The following errors may occur Error that may occur on the slave side lt 1 gt Invalid command transfer format lt 2 gt Reception of an undefined command lt 3 gt Insufficient number of transfer data bytes fora READ command lt 4 gt Insufficient area to contain data for a WRITE command lt 5 gt Change in data during transmission of a READ STATUS or CHGMST command If any of the above types of errors occurs ACK is not returned Error that may occur on the master side If data transmitted with a WRITE command changes during transmission the master transmits a STOP command to the slave 5 6 8 Manipulation of SCK Pin Output The SCK P01 pin has a built in output latch so that this pin
93. its inverted signal to the XT2 pin The state of the XT1 pin is tested by bit 3 of the clock mode register WM Figure 5 15 External Circuit for the Subsystem Clock Oscillator a Crystal oscillation b External clock p PD750108 uPD750108 asd Vss External XTi li HI xn dock D gt 1 Bt XT2 XT Crystal Standard frequency 32 768 kHz User s Manual U11330EJ2V1UM00 91 uPD750108 USER S MANUAL 92 Caution When the main system clock or subsystem clock oscillator is used conform to the following guidelines when wiring enclosed in broken lines of Figures 5 14 and 5 15 to eliminate the influence of the stray capacitance around the wiring The wiring must be as short as possible Other signal lines must not run in these areas Any line carrying a high pulsating current must be kept away as far as possible The grounding point of the capacitor of the oscillator must have the same potential as that of Vss It must not be grounded to a grounding pattern carrying a high current No signal must be taken directly from the resonator The subsystem clock oscillator has low amplification to minimize current consumption For this reason more malfunctions can occur due to noise than the main system clock oscillator So pay special attention to wiring when using the subsystem clock Figure 5 16 gives examples of oscillator connections which should be avoided Figur
94. of serial transfer External Automatically In the operable mode Slave CPU SCK masked when CSIE 1 8 bit data When the serial clock is Arbitrary speed TOUT transfer is masked after 8 bit transfer flip flop completed When SCK is high serial transfer fcc 24 Middle speed serial transfer fcc 23 High speed serial transfer When the internal system clock is selected SCK is internally terminated when the 8th clock has been output and is externally counted until the slave enters the ready state 5 Signals Figures 5 60 to 5 65 show signals to be generated in the SBI mode and flag operations on the SBIC Table 5 10 lists signals used in the SBI mode User s Manual U11330EJ2V1UMO00 163 uPD750108 USER S MANUAL Figure 5 60 Operations of RELT CMDT RELD and CMDD Master J Transfer start request SIO SCK H SO latch ELLA RELD EY CMDD EN Y Figure 5 61 Operations of RELT CMDT RELD and CMDD Slave Transfer start request Write to SIO E 3 SIO RELT Master CMDT Master Y When address match is found RELD iH When address mismatch is found CMDD 164 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 62 Operation of ACKT When ACKT is set after transfer completion SCK 6 7 8 9 ACK signal is output during the first clock SBO SB1 o2 X ACK cycle immediately afte
95. operation mode register CSIM For details on CSIM format see 1 in Section 5 6 3 CSIM is manipulated with an 8 bit manipulation instruction Only the CSIE bit of CSIM can be independently manipulated CSIM can also be manipulated using the name of each bit When the RESET signal is entered CSIM is set to In the figure below hatched portions indicate bits used in the operation halt mode 138 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Address FEOH 7 6 5 4 3 2 1 0 __ Serial clock selection bit W Note Serial interface operation mode selection bit W Wake up function specification bit W Match signal from address comparator R Serial interface operation enable disable specification bit W Note The status of the PO1 SCK pin is selectable Remark R Read only W Write only Serial interface operation enable disable specification bit W 5 EIS Shift register operation Serial clock counter IRQCSI flag SO SBO and SI SB1 pins CSIEO Shift operation disabled Used only for port 0 Serial clock selection bit W The P01 SCK pin assumes the following state according to the setting of CSIMO and CSIM1 P01 SCK pin state High impedance High level output When clearing CSIE during serial transfer use the following procedure 1 Disable interrupts by clearing the interrupt enable flag IECSI 2 Clear
96. pair are transferred to the DE register pair PUSH HL POP DE DE HL 3 A branch is made to the address indicated by the XABC register PUSH BC PUSH XA RET Branch to address XABC User s Manual U11330EJ2V1UM00 35 uPD750108 USER S MANUAL 3 2 GENERAL REGISTER BANK CONFIGURATION The uPD750108 contains four register banks each consisting of eight general registers X B C D E and L These registers are mapped to addresses to 1FH in memory bank 0 of the data memory see Figure 3 5 To specify a general register bank a register bank enable flag RBE and a register bank select register RBS are contained The RBS is a register used to select a register bank and the RBE is a flag used to determine whether a register bank selected using the RBS is to be enabled The register bank RB enabled at instruction execution is determined as RBE RBS Table 3 2 Register Bank to Be Selected with the RBE and RBS Register bank 0 X Bank 0 is always selected Bank 0 is selected Bank 1 is selected Bank 2 is selected Bank 3 is selected Always 0 Remark x Don t care The contents of the RBE are automatically saved or restored at the beginning or end of subroutine processing so that the RBE can be freely modified during subroutine processing In interrupt processing the RBE is automatically saved or restored and when interrupt processing is started the con
97. particular slave Two data values a slave address output from the master and the value of SVA are compared with each other by the address comparator If a match is found the slave is selected At this time bit 6 COI of serial operation mode register CSIM is set to 1 If a match with received address data is not found the bus release detection flag RELD is cleared to 0 When WUP 1 wake up state detection IRQCSI is set only when a match is found With this interrupt request the uPD750108 can be informed of a communication request transmitted from the master Error detection In the two wire serial mode or SBI mode SVA detects an error when addresses commands or data is transferred with the uPD750108 operating as the master or when data is transferred with the LPD750108 operating as a slave For details see 6 in Section 5 6 6 and 8 in Section 5 6 7 5 6 4 Operation Halt Mode The operation halt mode is used when serial transfer is not performed This mode reduces power consumption The shift register does not perform shift operation in this mode so the shift register can be used as a normal 8 bit register When the RESET signal is entered the operation halt mode is set The P02 SO SBO and P03 SI SBI pin function as input only port pins The P01 SCK pin can be used as an input port pin by setting the serial operation mode register 1 Register setting To set the operation halt mode manipulate serial
98. program processing Effect MBE 0 mode Interrupt processing MBS save restoration becomes unnecessary Processing that repeats internal MBS modification becomes unnecessary hardware and static RAM operations Subroutine processing MBS save restoration becomes MBE 1 mode Usual program processing Figure 3 1 Use of MBE 0 Mode and MBE 1 Mode lt Main program gt SET1 MBE gt lt Subroutine gt MBE 1 CLR1 MBE Y 0 Internal hardware CER MBE and static RAM MBE RET Interrupt processing operations are 0 repeated SET1 MBE gt MBE 0 is to be set in the vector table MBE 0 MBE 24 RETI The contents of the MBE are automatically saved or restored at the time of subroutine processing so that the MBE can be freely modified during subroutine processing In interrupt processing the MBE is automatically saved or restored and when interrupt processing is started the contents of the MBE can be specified for the interrupt processing by setting the interrupt vector table This speeds up interrupt processing The setting of the MBS can be modified for subroutine processing or interrupt processing by saving or restoring the MBS with the PUSH or POP instruction The MBE is set using the SET1 or CLR1 instruction The MBS is set using the SEL instruction Examples 1 The MBE is cleared and a fixed memory bank is used CLR1 MBE MBE 0 2 Memory bank 1 is selected SET1 MBE
99. required to execute the instruction are cut When an internal clock is used for the count pulse signal this problem does not occur because of synchronization with the instruction Accordingly in an attempt to read the contents of the count register with a count pulse signal applied to TIO the signal must have a pulse wide enough to avoid incorrect counting even if count pulses are cut That is the contents of the count register are held by a read instruction for one machine cycle so that a signal applied to the TIO pin must have a pulse wider than that Read instruction External clock TIO Instruction CP Count register A change in a count A count pulse is canceled pulse is placed on hold by the instruction by the instruction 4 Notes on changing the count pulse When the count pulse is changed by rewriting the contents of the timer event counter mode register this takes effect immediately after the rewrite instruction is executed Re set instruction Re set instruction Clock A specified unu Clock A specified QUT ONLINE T UN Ne A combination of clocks used for changing count pulse signals can generate a spike lt 1 gt or lt 2 gt count pulse as shown in the figure below In this case an incorrect count operation may occur or the contents ofthe count register may be destroyed So when the count pulse is changed bit 3 ofthe timer event counter mode register must be set to 1 and the timer must be restarted at the s
100. service program starts and status 1 is set Status 0 is set by clearing ISTO INTCSI and INT4 not allowed to be level two interrupts are disabled When INTTO allowed to be a level two interrupt occurs the level two interrupt is executed and status 1 is set to disable all interrupts When INTTO processing is completed status 0 is set again INTCSI and INT4 which have been disabled are enabled then control returns User s Manual U11330EJ2V1UMO00 213 uPD750108 USER S MANUAL 6 10 TEST FUNCTION 6 10 1 Test Sources The uPD750108 has two test sources INT2 provides two types of edge detection test inputs Table 6 5 Test Source Test source Internal external INT2 detection of the rising edge of the signal input to the INT2 pin or that of External the first falling edge of the signals input to KRO to KR7 INTW signal from clock timer Internal 6 10 2 Hardware to Control Test Functions 1 Test request flags test enable flags Test request flags IRQxxx are setto 1 when the corresponding test requests INTxxx are issued Clear the test request flags to 0 with the software once the test processing has been executed Test enable flags IExxx correspond to test request flags The test enable flags enable the standby release signal when they are to 1 They disables the standby release signal when they are set to 0 When both a test request flag and the corresponding test enable flag are set to 1 the standby release
101. v bit specified in operand Exclusive ORs the content of the carry flag with the bit in data memory specified by bit manipulation addressing fmem bit pnem L H mem bit then sets the result in the carry flag 11 4 40 Branch Instructions 675 Function For the 0750108 PC 12 9 lt addr addr 0000H 1FFFH Branches to the address specified by the immediate data addr This instruction is an assembler pseudo instruction and the assembler automatically replaces this instruction with the BR addr instruction BRCB caddr instruction or BR addr instruction as required at assembly time 288 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET Cu BR addri Function For the uPD750108 PC42 9 lt addr1 addr1 0000H 1FFFH Branches to the address specified by the immediate data addr1 This instruction is an assembler pseudo instruction and the assembler automatically replaces this instruction with the BRA laddr1 instruction BR addr instruction BRCB caddr instruction or BR addr1 instruction as required at assembly time Remark Function in this section is applicable to the uPD750108 whose program counter consists of 13 bits addr 0000H to 1FFFH However this is also applicable to the PD750104 whose program counter consists of 12 bits addr 0000H to OFFFH the LPD750106 whose program counter consists of 13 bits addr 0000H to 17FFH and the uwPD75P0116 whose program counter consists o
102. 08 whose program counters consist of 13 bits each This is also applicable to the uPD750104 whose program counter consists of 12 bits and the uPD75P0116 whose program counter consists of 14 bits however Caution The MOVT XA PCDE instruction usually references table data in the page containing that 274 instruction However when the instruction is located at address xxFFH table data in the next page is referenced instead of table data in the page containing that instruction Program memory 7 0 Page 2 2 0300H Page 3 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET For example if MOVT XA PCDE is located at a as shown above the table data in page 3 specified by the contents of the DE register pair is transferred to the XA register pair instead of that in page 2 Example The 16 byte data at addresses xxFOH xxFFH in program memory is transferred to addresses 30H 4FH in data memory SUB SEL MOV MOV MOVT MOV INCS INCS INCS BR RET ORG DB MOVT PCXA LOOP MBO HL 30H HL lt 30H DE 0FOH DE lt FOH XA PCDE XA lt table data HL XA HL XA HL HL lt HL 2 HL E lt 1 LOOP xxFOH XxH xxH Table data Function For the uPD750106 and uPD750108 XA lt ROM 12 8 Transfers the low order four bits of the table data in program memory to the A register and the high order four bits to the X reg
103. 1 0 4 bit manipulation instructions All 4 bit memory manipulation instructions including the IN OUT MOV XCH ADDS and INCS instructions can be used However before these instructions can be executed memory bank 15 must Examples 1 The contents of the accumulator are output to port 3 SEL MB15 or CLR1 MBE OUT PORTS A The value of the accumulator is added to the data output on port 5 then the result is output SET1 MBE SEL MB15 MOV HL PORT5 ADDS A HL lt A PORTS5 NOP MOV HL A PORT5 A Whether the data on port 4 is greater than the value of the accumulator is tested SET1 MBE SEL MB15 MOV HL PORT4 SUBS A HL lt PORT4 BR NO NO YES User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 3 8 bit manipulation instructions The MOV XCH and SKE instructions as well as the IN and OUT instructions can be used for ports 4 and 5 that allow 8 bit manipulation As with 4 bit manipulation memory bank 15 must be selected in advance Example The data contained in the BC register pair is output on the output port specified by 8 bit data applied to ports 4 and 5 SET1 MBE SEL MB15 IN XA PORT4 XA lt ports 5 4 MOV HL XA HL XA XA BC XA lt BC MOV HL XA Port L XA User s Manual U11330EJ2V1UMOO 79 uPD750108 USER S MANUAL A PORTn Note 1 Table 5 2 I O Pin Manipulation Instructions PORT PORT 1 2 PORT 0 PORT
104. 1 lt SO 146 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS lt Sample program gt master side CLR1 MBE MOV XA 10000011B MOV CSIM XA Set transfer mode MOV XA TDATA MOV SIO XA Set transfer data and start transfer LOOP SKTCLR IRQCSI Test IRQCSI BR LOOP MOV XA SIO Read in receive data 5 6 6 Two Wire Serial I O Mode The two wire serial mode can be made compatible with any communication format by programming In this mode communication is basically performed using two lines Serial clock SCK and serial data input output 580 or 581 Figure 5 47 Example of Two Wire Serial I O System Configuration 2 wire serial I O 2 wire serial I O Master CPU Slave CPU uPD750108 SCK SCK SBO 581 gt 580 581 Remark The uPD750108 can also be used as slave CPU 1 Register setting To set the two wire serial I O mode manipulate the following two registers Serial operation mode register CSIM Serial bus interface control register SBIC Users Manual U11330EJ2V1UMO00 147 uPD750108 USER S MANUAL a Serial operation mode register CSIM To use the two wire serial mode set CSIM as shown below For details on CSIM format see 1 in Section 5 6 3 CSIM is manipulated using an 8 bit manipulation instruction Bits 7 6 and 5 of CSIM can be manipulated bit by bit When the RESET signal is input CSIM is set to 00H In the figure below hatche
105. 16fxr machine cyclesNote 4 machine cycles 8 machine cycles 8 machine cycles 8 machine cycles fcc 8fxr machine cycles 8 machine cycles 16 machine cycles 16 machine cycles 16 machine cycles fcc 4fxr machine cycles 15 machine cycles 98 1 machine cycle 1 machine cycleNote Note Cannot be emulated using the tool 1 machine cycle 1 machine cycle Remarks 1 Time indicated in parentheses is required when fcc 2 MHz and fxr 32 768 kHz 2 x Don t care CPU clock is supplied to the CPU of the uPD750108 The reciprocal of this frequency is a minimum instruction time defined as one machine cycle in this manual Caution The fluctuation of the ambient temperature around an oscillator and the performance of a load capacity change fcc and fxr In particular when fcc is higher than the nominal value or fxr is lower than the nominal value the machine cycles calculated by fcc 6e4fxr fcc 16fxyr fcc 8fy7 and fcc 4fxr in Table 5 5 are longer than the machine cycle calculated by the nominal values of fcc and Therefore the wait time required to change the system clock and CPU clock should be longer than the machine cycle calculated by the nominal values of fcc and User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 2 Procedure for changing the system clock and CPU clock The procedure for changing the system clock and CPU
106. 1FH Y 58 User s Manual U11330EJ2V1UMO00 Address 000H 3 gt lt CHAPTER 4 INTERNAL CPU FUNCTIONS Figure 4 9 Register Pair Format 3 0 3 0 gt One bank 4 6 ACCUMULATOR In the PD750108 the A register XA register pair function as accumulators The A register is mainly used for 4 bit data processing instructions and the XA register pair is mainly used for 8 bit data processing instructions For a bit manipulation instruction the carry flag CY functions as a bit accumulator Figure 4 10 Accumulator Bit accumulator User s Manual U11330EJ2V1UM00 59 uPD750108 USER S MANUAL 4 7 STACK POINTER SP AND STACK BANK SELECT REGISTER SBS The uPD750108 uses static RAM as stack memory scheme and the 8 bit register holding the start address of the stack area is the stack pointer SP The stack area is located at addresses 000H to 1FFH in memory banks 0 and 1 One memory bank is selected according to the value of the 2 bit SBS See Table 4 2 Table 4 2 Stack Area to Be Selected by the SBS SBS Stack area SBS1 SBSO 0 0 Memory bank 0 0 1 Memory bank 1 Other than above Not to be set The SP is decremented before a write save operation to stack memory and is incremented after a read restoration operation from stack memory Figures 4 12 to 4 15 show data saved to and restored from stack memory in these stack operations To place the stack a
107. 1UMO00 174 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS m _ B F E uoissiusueJ eueg ns Bursseooud eoiep gt AGQvadu ASN 95 20 085 YOS J9JSUEJ xos yeas uondeoei g uoneiedo 1919991 Buisseooud 1 1 921A9Q 1 SEN 921A9q 5 ed 07 6 4 175 User s Manual U11330EJ2V1UM00 uPD750108 USER S MANUAL 10 Transfer start Serial transfer is started by writing transfer data in shift register SIO provided that the following two conditions are satisfied The serial interface operation enable disable bit CSIE is set to 1 The internal serial clock is not operating after 8 bit serial transfer or SCK is high Cautions 1 Transfer cannot be started by setting CSIE to 1 after writing data to the shift register 2 The N ch transistor needs to be turned off when data is received So FFH must be written to SIO beforehand However when the wake up function specification bit WUP is set to 1 the N ch transistor is always off So FFH need not be written to SIO beforehand for reception 3 If data is written to SIO when the slave is busy the data is not lost Transfer is started when the busy state is released and input to SBO or
108. 2 287 Accumulator manipulation instructions SKT pmem L 252 287 RORC A 251 283 SKT H mem bit 252 287 NOT A 251 283 SKF mem bit 252 287 SKF fmem bit 252 287 Increment decrement instructions SKF pmem L 252 287 INCS reg 251 283 SKF H mem bit 252 287 INCS rp1 251 283 SKTCLR fmem bit 252 287 INCS HL 251 283 SKTCLR pmem L 252 287 INCS mem 251 284 SKTCLR QH mem bit 252 287 DECS reg 251 284 AND1 CY fmem bit 252 288 DECS rp 251 284 AND1 CY pmem L 252 288 AND1 CY H mem bit 252 288 Compare instructions OR1 CY fmem bit 252 288 SKE reg n4 251 284 OR1 CY pmem L 252 288 SKE 251 284 OR1 CY H mem bit 252 288 SKE A HL 251 284 XOR1 CY fmem bit 252 288 SKE XA HL 251 285 CY pmem L 252 288 SKE A reg 251 285 XOR1 CY H mem bit 252 288 SKE XA rp 251 285 Branch instructions Carry flag manipulation instructions BR addr 253 288 SET1 CY 251 285 BR addr1 253 289 CLR1 CY 251 285 BR laddr 254 289 SKT CY 251 285 BR addr 254 289 NOT1 CY 251 286 BR addr1 254 289 BR PCDE 254 291 Memory bit manipulation instructions BR PCXA 254 291 SET1 mem bit 252 286 BR BCDE 254 292 SET1 fmem bit 252 286 BR BCXA 255 292 316 User s Manual U11330EJ2V1UMO00 APPENDIX D INSTRUCTION INDEX BRA laddr1
109. 2 to 8 and the data at address 0001H are set in PC bits 7 to O uPD75P0116 6 low order bits at address 0000H in program memory are set in PC bits 13 to 8 and the data at address 0001H are set in PC bits 7 to O 6 low order bits at address 0000H in program memory are set in PC bits 13 to 8 and the data at address 0001H are set in PC bits 7 to O Carry flag CY Held Undefined Skip flags SKO to SK2 0 0 Interrupt status flags ISTO IST1 0 0 Bank enable flags MBE RBE Bit 6 at address OOOOH in program memory is set in RBE and bit 7 is set in MBE Bit 6 at address OOOOH in program memory is set in RBE and bit 7 is set in MBE Stack pointer SP Undefined Undefined Stack bank selection register SBS 1000B 1000B Data memory RAM Held Undefined General registers X A H L D E B C Held Undefined Bank selection register MBS RBS 0 0 0 0 Basic interval timer watch dog timer Counter BT Undefined Undefined Mode register BTM Watchdog timer enable flag WDTM Timer event counter Counter TO Modulo register TMODO Mode register TMO TOEO TOUT flip flop Timer counter Counter T1 Modulo registers TMOD1 Mode register TM1 TOE1 TOUT flip flop 0 0 Clock timer Mode register WM 0 Serial interface 230 Shift r
110. 272 A HL 249 272 A rpal 249 272 XA HL 249 273 A mem 249 273 XA mem 249 273 A reg1 249 273 XA rp 249 273 Table reference instructions MOVT XA PCDE 250 274 MOVT XA PCXA 250 275 MOVT XA BCDE 250 276 MOVT XA BCXA 250 276 Bit transfer instructions MOV1 CY fmem bit 250 277 MOV1 CY pmem L 250 277 MOV1 CY H mem bit 250 277 MOV1 fmem bit CY 250 277 MOV1 pmem L CY 250 277 MOV1 H mem bit CY 250 277 Arithmetic logical instructions ADDS A n4 250 277 ADDS XA n8 250 278 ADDS A HL 250 278 ADDS XA rp 250 278 ADDS rp 1 XA 250 278 ADDC A HL 250 278 ADDC XA rp 250 279 ADDC rp 1 XA 250 279 SUBS A HL 250 279 SUBS XA rp 250 279 SUBS rp 1 XA 250 280 SUBC A HL 250 280 SUBC XA rp 250 280 SUBC rp 1 XA 250 280 AND A n4 251 280 AND A HL 251 281 AND XA rp 251 281 AND rp 1 XA 251 281 OR A n4 251 281 User s Manual U11330EJ2V1UMO00 315 uPD750108 USER S MANUAL OR A HL 251 281 SET1 pmem L 252 286 OR XA rp 251 281 SET1 H mem bit 252 286 OR rp 1 XA 251 282 CLR1 mem bit 252 286 XOR A n4 251 282 CLR1 fmem bit 252 286 XOR A HL 251 282 CLR1 pmem L 252 286 XOR XA tp 251 282 CLR1 H mem bit 252 286 XOR rp 1 XA 251 282 SKT mem bit 252 287 SKT fmem bit 25
111. 4 El IECSI RETI 1 If INTO is set when interrupts are disabled the interrupt request flag is held 2 When the interrupt is enabled by the El instruction the INTO interrupt service program starts 3 Same as 1 4 When the held INTCSI flag is enabled the INTCSI interrupt service program starts 210 User s Manual U11330EJ2V1UMO00 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 5 Execution of held interrupts two interrupts with lower priority occur concurrently lt Main program gt IETO IEO El INTO service program As lt 2 gt RETI lt INTTO service routine gt RETI 1 When INTO and INTTO with the lower priority occur concurrently during execution of the same instruction INTO with a higher priority is executed first INTTO is held 2 When the INTO interrupt service program has been executed the RETI instruction is executed to start the interrupt service program for INTTO which has been held User s Manual U11330EJ2V1UMO00 211 uPD750108 USER S MANUAL 6 Executing pending interrupt interrupt occurs during interrupt processing INTBT has higher priority and INTTO and INTCSI have lower priority Main program Reset EI IEBT EI IETO EI IECSI MOV A 9 lt INTBT service program gt MOV IPS A PUSH rp POP rp 1 INTCSI service program 4 RETI INTTO service program RETI 1 When INTBT
112. 4H INTO start address high order 6 bits INTO start address low order 8 bits 0006H INT1 start address high order 6 bits INT1 start address low order 8 bits 0008H INTCSI start address high order 6 bits INTCSI start address low order 8 bits 000AH INTTO start address high order 6 bits INTTO start address low order 8 bits 000CH INTT1 start address high order 6 bits INTT1 start address low order 8 bits User s Manual U11330EJ2V1UMO00 189 uPD750108 USER S MANUAL The column of interrupt priority in Table 6 1 indicates a priority assigned when multiple interrupt requests occur concurrently or are held A vector table contains interrupt processing start addresses and MBE and RBE setting values during interrupt processing An assembler pseudo instruction VENTn n 1 to 6 is used to set a vector table Example A vector table is set for INTBT INT4 VENT1 MBE 0 RBE 0 GOTOBT LY HSAN ii 4 Vector table at MBE RBE setting value Symbol for indicating address 0002 in interrupt service routine an interrupt service routine start address Caution The contents MBE RBE and start address described in the operand of the VENTn n 1 to 6 instruction are stored in the vector table address at address 2n Example Vector tables are set for INTBT INT4 and INTTO VENT1 MBE 0 0 GOTOBT INTBT INT4 start address VENT5 MBE 0 1
113. 5 0116 only Lite 18 2 2 20 MDO MD3 for the pPD75P0116 Only 18 2 2 21 00 07 for the uPD75P0116 only e 18 2 3 PIN INPUT OUTPUT CIRCUITS i tur aen cmd 19 24 CONNECTION OF UNUSED oot ca t t c bg 21 FEATURES OF THE ARCHITECTURE AND MEMORY MAP 23 3 1 DATA MEMORY BANK STRUCTURE AND ADDRESSING MODES 23 User s Manual U11330EJ2V1UMO00 CHAPTER 4 CHAPTER 5 3 1 1 Data Memory Bank Structure 23 3 1 2 Data Memory Addressing Modes 25 3 2 GENERAL REGISTER BANK CONFIGURATION eene 36 3 9 Hte e e D a e E eR PLA LER hides 41 INTERNAL CPU FUNCTIONS 47 4 1 MkI MODE MK MODE SWITCH FUNCTIONS seen 47 4 1 1 Differences between Mk Mode and Mk 47 4 1 2 Setting of the Stack Bank Selection Register 585 48 4 2 PROGRAM COUNTER PO sse 49 4 3 PROGRAM MEMORY nennen nennen sentent enn sistens 50 4 4 DATA MEMORY RAM 512 WORDS x 4 BITS 55 4 4 1 Data Memory Configuration sssssesseeeeeeneeneen nens 55 4 4 2 Specification of a Data Memory 56 4 5 GE
114. 6 PCC Processor clock control register SCC System clock control register User s Manual U11330EJ2V1UMO00 Frequency divider LE Wait release signal from BT lt RESET signal eui Standby release signal from interrupt control circuit CPU INTO noise eliminator Clock output circuit One clock cycle tcy of the CPU clock is equal to one machine cycle of an instruction CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5 2 2 Functions and Operations of the Clock Generator The clock generator generates the following clocks and controls the CPU operation modes such as the standby mode Main system clock fcc Subsystem clock fxr CPU clock Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register PCC and system clock control register SCC The function and operation ofthe clock generator are described in a to g below a b c d A RESET signal selects the lowest speed mode 32 us at 2 MHz Note 1 for the main system clock PCC 20 SCC 0 When the main system clock is selected the PCC can be set to select one of four CPU clocks 2 4 8 and 32 us at 2 MHz Note 2 When the main system clock is selected the two standby modes STOP mode and HALT mode are available The SCC can be set to select the subsystem clock for very low speed low current operation 122 us at 32 768 kHz The value in the PCC does not affect
115. 603E U11330J U11330E This manual U11456J U10453J U10453E Documents related to development tools Hardware Document name IE 75000 R IE 75001 R User s Manual Document number Japanese EEU 846 English EEU 1416 IE 75300 R EM User s Manual U11354J U11354E EP 75008CU R User s Manual EEU 699 EEU 1317 EP 75008GB R User s Manual EEU 698 EEU 1305 PG 1500 User s Manual U11940J EEU 1335 Software RA75X Assembler Package User s Operation EEU 731 EEU 1346 Manual Language EEU 730 EEU 1363 PG 1500 Controller PC 9800 Series MS DOSTM Base EEU 704 EEU 1291 User s Manual IBM PC Series PC DOSTM Base Other documents Document name SEMICONDUCTORS SELECTION GUIDE Products amp Packages CD ROM EEU 5008 U10540E Document number Japanese X13769X English Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grade on NEC Semiconductor Devices 11531 11531 NEC Semiconductor Device Reliability and Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892J C11892E Microcontroller Related Products Guide by third parties U11416J Caution The above related documents are subject to change without notice Be sure to use the latest edition when you
116. 782 Fax 408 588 6130 800 729 9288 NEC Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Spain Office Madrid Spain Tel 91 504 2787 Fax 91 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 User s Manual U11330EJ2V1UM00 NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd United Square Singapore 1130 Tel 65 253 8311 Fax 65 250 3583 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC do Brasil S A Electron Devices Division Rodovia Presidente Dutra Km 214 07210 902 Guarulhos SP Brasil Tel 55 11 6465 6810 Fax 55 11 6465 6829 J99 1 Page Throughout Major Changes Description The uPD750104 uPD750106 uPD750108 and pPD75P0116 have already been developed Data bus pins 00 07
117. 8 SP 3 lt MBE RBE 0 PC42 SP 4 SP 1 SP 2 lt 1 0 12 0 lt addr SP lt SP 4 e uPD75P0116 SP 3 MBE RBE PC43 PC42 SP 4 SP 1 SP 2 lt PC41 0 1 0 addr1 SP SP 4 uPD750104 SP 2 lt x x MBE RBE SP 6 SP 3 SP 4 11 0 SP 5 lt 0 0 0 0 PC44 9 lt addr SP lt SP 6 750106 uPD750108 SP 2 lt x x MBE RBE SP 6 SP 3 SP 4 lt 4 0 SP 5 lt 0 0 0 PC42 PC12 9 lt addr SP lt SP 6 e uPD75P0116 SP 2 lt x x MBE RBE SP 6 SP 3 SP 4 lt PC14 9 5 m 0 0 12 1 0 lt addr SP SP 6 CALLFNote Ifagdr uPD750104 SP 3 lt MBE RBE 0 0 SP 4 SP 1 SP 2 lt PC14 9 PC44 9 lt O faddr SP lt SP 4 2 c ZU o o c 5 2 2 n e uPD750106 PD750108 SP 3 lt MBE RBE 0 PC42 SP 4 SP 1 SP 2 1 0 PC12 9 lt 00 faddr SP lt SP 4 e uPD75P0116 SP 3 lt MBE RBE PC13 PCy SP 4 SP 1 SP 2 lt 1 0 1 0 lt 000 faddr SP lt SP 4 Note The shaded portion is supported in Mk Il mode only The other portions are supported Mk mode only 256 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET Address Operation ing Skip condition area Operand Machine cycle CALLFNote faddr uPD750104 SP 2 x x
118. 8 USER S MANUAL Memory bit manipulation 252 Operand mem bit Machine cycle Operation mem bit 1 Address ing area Skip condition fmem bit fmem bit lt 1 pmem L pmem7 2 L3 2 bit L41 0 1 H mem bit H mem3 9 bit lt 1 mem bit mem bit 0 fmem bit fmem bit 0 pmem L pmem7 2 L3 2 bit Ly 0 lt 0 H mem bit mi gt NM DN H mem3 9 bit lt 0 mem bit Skip if mem bit 1 mem bit 1 fmem bit Skip if fmem bit 1 fmem bit 1 pmem L Skip if pmem7 2 L3 2 bit L4 0 1 pmem L 1 H mem bit Skip if H mem3 9 bit 1 H mem bit 1 mem bit Skip if mem bit 0 mem bit 0 fmem bit Skip if fmem bit 0 fmem bit 0 pmem L Skip if pmem7 o L3 9 bit Ly 0 0 pmem L 0 H mem bit Skip if H mem3 o bit 0 H mem bit 0 fmem bit Skip if fmem bit 1 and clear fmem bit 1 pmem L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Skip if pmem7 2 L3 2 bit Ly 9 1 and clear pmem L 1 H mem bit Skip if H mem3 9 bit 1 and clear H mem bit 1 CY fmem bit CY lt CYA fmem bit CY pmem L CY lt pmem 2 L3 2 bit L1 0 CY H mem bit CY lt CYA CY fmem bit CY lt CYv fmem bit CY pmem L CY CYv p
119. ATA MEMORY BANK STRUCTURE AND ADDRESSING MODES 3 1 1 Data Memory Bank Structure In the PD750108 addresses 000H to 1FFH in data memory space are assigned to static RAM 512 words X 4 bits and addresses F80H to FFFH are assigned to peripheral hardware such as I O ports and timers To address a 12 bit location in this data memory space 4K x 4 bits the uPD750108 uses such a memory bank structure that the low order eight bits are specified with an instruction directly or indirectly and the high order four bits are used to specify a memory bank To specify a memory bank MB two hardware items are incorporated Memory bank enable flag MBE Memory bank select register MBS The MBS is a register used to select a memory bank and the register can be set to 0 1 or 15 The MBE is a flag used to determine whether the memory bank selected using the MBS is valid As shown in Figure 3 1 when the MBE is set to 0 a certain memory bank is always selected regardless of the setting of the MBS When the MBE is set to 1 memory bank selection depends on the setting of the MBS thus enabling data memory space expansion In addressing data memory space the MBE is usually set to 1 MBE 1 and data memory in the memory bank specified in the MBS is operated However the MBE 0 mode or MBE 1 mode can be selected for each step of processing for more efficient programming User s Manual U11330EJ2V1UMOO 23 uPD750108 USER S MANUAL Applicable
120. Avoided 4 4 f The signal lines of the main system clock and subsystem clock are parallel and adjacent to each other uPD750108 Vss XT1 XT2 77 XT2 CL1 are wired in parallel 4 Frequency divider The frequency divider divides the output fcc of the main system clock oscillator to generate various clocks User s Manual U11330EJ2V1UMOO 95 96 uPD750108 USER S MANUAL 5 Control functions of subsystem clock oscillator The subsystem clock oscillator of the uPD750108 subseries has two control functions to decrease the supply current The function to select with the software whether to use the built in feedback resistorNote The function to suppress the supply current by reducing the drive current of the built in inverter when the operating supply voltage is high Vpp 2 7 V Note When the subsystem clock is not to be used select SOS 0 1 by software the built in feedback resistor will not be used connect the XT1 pin to Vss or Vpp and leave the XT2 pin open This reduces the supply current to the subsystem clock oscillator Each function can be used by switching bits 0 and 1 in the sub oscillator control register SOS See Figure 5 17 Figure 5 17 Subsystem Clock Oscillator Feedback resistor Inverter uPD750108 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 6 Sub oscillator control register SOS The SOS register
121. BS lt 0 FLAG1 FLAG1 lt 1 CLR1 FLAG2 FLAG2 0 SKF FLAGS 0 User s Manual U11330EJ2V1UM00 25 uPD750108 USER S MANUAL Figure 3 2 Data Memory Organization and Addressing Range of Each Addressing Mode 000H 01FH 020H 07FH OFFH 100H 1FFH F80H FCOH FFFH Remark 26 mem mem bit Addressing mode MBE Memory bank enable flag Area for general register Data area Static RAM memory bank 1 Not provided Peripheral hardware area memory bank 15 i 1 1 Don t care HL H mem bit User s Manual U11330EJ2V1UMO00 Stack address E fmem bit pmem L ud SES NN mm d SS CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Addressing mode 1 bit direct addressing Representation format mem bit Table 3 1 Addressing Modes Specified address Bit specified by bit at the address specified by MB and mem When MBE 0 and mem 00H 7FH mem 80H FFH When MBE 1 0 15 MBS 4 bit direct addressing 8 bit direct addressing Address specified by MB and mem When MBE 0 and mem 00H 7FH mem 80H FFH When MBE 1 0 15 MBS Address specified by mem even address When MBE 0 and mem 00H 7F
122. C DE C mov A GHL C D Mov A HL C mov AenL C2 MOV A rpat Function A lt Register pair specified by the operand When is specified for the register pair Skip if L 0 When HL is specified for the register pair Skip if L 2 FH Transfers the data at the data memory location addressed by the specified register pair HL HL HL DE DL to the A register When HL automatic increment is specified for the register pair automatically increments the contents of the L register by one after the data transfer and continues the operation until the contents are set to O User s Manual U11330EJ2V1UMO00 269 uPD750108 USER S MANUAL Then skips the immediately following instruction When HL automatic decrement is specified for the register pair automatically decrements the contents of the L register by one after the data transfer and continues the operation until the contents are set to FH Then skips the immediately following instruction MOV XA HL Function A lt HL X lt HL 1 Transfers the data at the data memory location addressed by the HL register pair to the A register and transfers the data at the next data memory address to the X register However if the contents of the L register are odd numbered an address with the low order bit ignored is specified Example The data at addresses 3EH and 3FH are transferred to the XA register pair MOV HL 3EH MOV XA HL gt HL A
123. D3 A D2 X Dt X DO Data The 8 bit data following the command signal is defined as a command The 8 bit data without the command signal is defined as data The usage of commands or data can be selected optionally according to the communication specifications e Acknowledge signal ACK The acknowledge signal confirms the reception of serial data between the transmitter and the receiver User s Manual U11330EJ2V1UMO00 157 uPD750108 USER S MANUAL 158 Figure 5 58 Acknowledge Signal When output in phase with the 11th clock of SCK SCK 8 91 hi When output in phase with the 9th clock of SCK sk LIU UU UU ls p lr LT LT LT SBO SB1 CK The acknowledge signal is a one shot pulse output in phase with the falling edge of SCK after 8 bit data transfer This signal may be synchronized with any clock of SCK The transmitter checks if the receiver returns the acknowledge signal after 8 bit data transfer If the acknowledge signal is not returned after a specified period of time the transmitter can assume that the reception failed User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS f Busy signal BUSY and ready signal READY The busy signal informs the master that a slave is getting ready for data transfer The ready signal informs the master that a slave is ready for data transfer Figure 5 59 Busy and Ready Signals sc elitr 7 SBO SB1 X BUSY READY In the SBI mode a slave noti
124. E SET1 WDTM SET1 BTM 3 Set bit 3 of BTM to 1 The generation of a RESET signal clears WDTM to 0 Figure 5 25 Format of the Watchdog Timer Enable Flag WDTM Address F8BH 3 BT mode Sets IRQBT when the basic interval timer BT overflows WT mode Generates an internal reset signal when the basic interval timer BT overflows 5 3 4 Operation of the Basic Interval Timer When WDTM is set to 0 the basic interval timer BT functions as an interval timer An interrupt request flag IRQBT is set when the timer overflows BT is constantly incremented by the clock supplied from the clock generator So it is impossible to stop the timer from incrementing One of four interrupt generation intervals can be selected by setting BTM See Figure 5 24 BT and IRQBT can be cleared by setting bit 3 of BTM to 1 instruction for starting as an interval timer The count status of BT can be read by an 8 bit manipulation instruction No data can be loaded to the timer Perform the timer operation as follows lt 1 gt and 2 can be performed with the same instruction 1 Set the interval in BTM 2 Set 1 in bit 3 of BTM Example Generate an interrupt at intervals of 4 10 ms at 2 MHz SET1 MBE SEL MB15 MOV A 1111B MOV Set the interval and start processing EI Enable interrupt EI IEBT Enable BT interrupt User s Manual U11330EJ2V1UMO00 105 uPD750108 USER S MANUAL 5 3 5 Operation of the Watchdog Ti
125. E75X PC 9800 series MS DOS 3 5 inch 2HD PC AT See OS for 3 5 inch 2HC uS7B13IE75X IBM PC compatibles 5 25 inch 2HC uS7B10IE75X Notes 1 Maintenance service only 2 These software products cannot use the task swap function which is available in MS DOS Ver 5 00 or later Remarks 1 Operation of the IE control program is guaranteed only on the above host machines and OSs 2 The uPD750104 uPD750106 uPD750108 and uPD75P0116 are collectively referred to as the uPD750108 subseries User s Manual U11330EJ2V1UMO00 307 uPD750108 USER S MANUAL OS for IBM PC The following IBM PC OSs are supported Version PC DOS Ver 5 02 to Ver 6 3 J6 1 VNote to J6 3 VNote MS DOS Ver 5 0 to Ver 6 22 5 0 VNote to 6 2 VNote IBM DOSTM J5 02 VNote Note Only English version is supported Caution These software products cannot use the task swap function which is available in MS DOS Ver 5 00 or later 308 User s Manual U11330EJ2V1UMO00 APPENDIX B DEVELOPMENT TOOLS 90026 Z f10800dS7 Vd 7 i pe1epao eq 01 N3 H 00 S7 3l 991 0 JOU op 5 9u 5 0091 9 2911049 Buiurejuoo yonpold Jejojuoo 0081 9d eiqissod s
126. ET1 CMDT 2 RELD CMDD are tested to identify the types of received data and the types of processing accordingly By setting WUP 1 this interrupt routine is processed only when an address match is found SEL MB15 SKF RELD RELD test BR IADRS SKT CMDD CMDD test BR IDATA BR ICMD Command analysis DATA Data processing ADRS eis Address decode 136 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 3 Shift register SIO Figure 5 42 shows the configuration of peripheral hardware of shift register SIO is an 8 bit register which performs parallel serial conversion and serial transfer shift operation in phase with the serial clock Serial transfer is started by writing data to SIO In transmission data written to SIO is output on the serial output SO or serial data bus SBO or SB1 In receive operation data is read from the serial input SI or 580 or 581 into SIO Data can be read from or written to SIO by using an 8 bit manipulation instruction When the RESET signal is generated during operation the value of SIO is undefined When the RESET signal is generated in the standby mode the value of SIO is preserved Shift operation is stopped after 8 bit send or receive operation is completed Figure 5 42 Peripheral Hardware of Shift Register comparator CMDT Shift register Us SO latch RELT 4 Shift clock
127. FFFH User s Manual U11330EJ2V1UMO00 293 uPD750108 USER S MANUAL faddr Function Saves the contents of the program counter PC Return address memory bank enable flag MBE and register bank enable flag RBE to the data memory location stack addressed by the stack pointer SP then branches to the location addressed by the 11 bit immediate data faddr after decrementing SP Only the For the uPD750108 Mk mode SP 1 PC7 4 SP 2 lt PC3 9 SP 3 MBE RBE 0 12 SP 4 11 SP lt SP 4 PC12 9 00 faddr faddr 0000H 07FFH Mk II mode SP 2 lt x x MBE SP 3 lt PC7 4 SP 4 PC3 9 SP 5 lt 0 0 0 PC12 SP 6 lt PC 44 8 SP lt SP 6 PC12 0 00 faddr faddr 0000H 07FFH address range 0000H 07FFH 0 2047 can be called C TCALL addr Function Remark Function in this section is applicable to the uPD750108 whose program counter consists of Assembler pseudo instruction of the GETI instruction for table definition This instruction is used to replace a 3 byte CALL addr instruction with a 1 byte GETI instruction The 12 bit address data must be coded in addr For detailed information refer to RA75X Assembler Package User s Manual Language EEU 1363 13 bits addr OOOOH to 1FFFH However this is also applicable to the uPD750104 whose program counter consists of 12 bits addr 0000H to O
128. FFFH the uPD750106 whose program counter consists of 13 bits addr OOOOH to 17FFH and the uwPD75P0116 whose program counter consists of 14 bits addr 0000H to SFFFH 294 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET Function For the uPD750108 Mk mode PC11 8 SP MBE 0 12 SP 1 PC3 9 lt SP 2 PC7 4 lt SP 3 SP lt SP 4 Mk mode PC11 g lt SP x x x 12 lt SP 1 PC3 9 lt SP 2 PC7 4 lt SP 3 x X MBE RBE lt SP 4 SP lt SP 6 Restores the program counter PC memory bank enable flag MBE and register bank enable flag RBE with the data at the data memory location stack addressed by the stack pointer SP then increments the contents of SP Caution The program status word PSW is not restored except MBE and RBE Remark Function in this section is applicable to the uPD750108 whose program counter consists of 13 bits addr 0000H to 1FFFH However this is also applicable to the PD750104 whose program counter consists of 12 bits addr OOOOH to OFFFH the uPD750106 whose program counter consists of 13 bits addr 0000H to 17FFH and the uPD75P0116 whose program counter consists of 14 bits addr 0000H to 3FFFH RETS Function For the u PD750108 Mk mode PC11 8 SP MBE 0 0 12 lt SP 1 PC3 9 lt SP 2 PCz 4 lt SP 3 SP lt SP 4 Then skip uncond
129. FH 0080H 07FFH 0800H OFFFH 1000H 1FFFH Figure 4 5 Program Memory Map in 1 0750108 RBE Internal reset start address high order 5 bits Internal reset start address low order 8 bits MBE RBE o INTBT INT4 start address high order 5 bits TBT INT4 start address TO start address ow order 8 bits high order 5 bits TO start address RBE E INT1 start address INT1 start address MBE RBE INTCSI start address high order 5 bits INTCSI start address low order 8 bits TO start address INTTO start address low order 8 bits low order 8 bits high order 5 bits low order 8 bits high order 5 bits INTT1 start address high order 5 bits TT1 start address ow order 8 bits GETI instruction reference table Entry address specified in CALL faddr instruc tion F Branch address specified in BRCB Icaddr instruc tion specified in BR BR BCDE BR BCXA CALL E d Branch call address by GETI Relative branch address specified in BR addr instruction 715 to 1 2 to 16 Note Can be used only in the MkII mode Remark Branch address specified in BRCB Icaddr instruction Branch address BRA addr1 ete or CALLA In addition to the above the BR PCDE and BR instructions can cause a branch to an address with only t
130. FUNCTIONS 2 2 1 P00 P03 PORTO P10 P13 PORT1 Input Pins Also Used for INT4 SCK SO SBO and SI SB1 Input Pins Also Used for INTO INT2 and TIO These are 4 bit input ports which also have the following functions 1 Port 0 Vectored interrupt input INT4 Serial interface I O SCK SO SBO SI SB1 2 Port 1 Vectored interrupt input INTO INT1 Edge detection test input INT2 External event pulse input TIO for timer event counter When the serial interface function is used the operation mode causes the dual function pin of PO to become an output pin Schmitt triggered inputs are used for the pins of port 0 and port 1 to prevent malfunction due to noise In addition for P10 the noise eliminator can be selected See 3 of Section 6 3 for details Port 0 can be connected with built in pull up resistors in units of bits P01 to by software Port 1 can be connected with built in pull up resistors in units of 4 bits P10 to P13 by software This is done by manipulating pull up resistor specification register group A POGA A RESET signal places these pins in input mode 2 2 2 P20 P23 PORT2 P30 P33 PORT3 P60 P63 PORTS P70 P73 PORT7 Pins Also Used for PTOO PTO1 PCL and BUZ VO Pins Also Used for MDO MD3Note P40 P43 PORTA P50 P53 PORTS I O Pins Also Used for DO D3Note N ch Open Drain Intermediate Withstand Voltage 13 V I O Pins Also Used for D4 D7Note Pins
131. Function HL A Transfers the contents of the A register to the data memory location addressed by the HL register pair MOV HL XA Function HL A HL 1 lt X Transfers the contents of the A register to the data memory location addressed by the HL register pair and transfers the contents of the X register to the next memory address However if the contents of the L register are odd numbered an address with the low order bit ignored is specified Cc MOV A mem Function A lt mem 07 0 00H FFH Transfers the data at the data memory location addressed by the 8 bit immediate data mem to the A register 270 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET MOV XA mem Function A mem X mem 1 07 0 00H FEH Transfers the data atthe data memory location addressed by the 8 bit immediate data mem to the A register and transfers the data at the next address to the X register An even address can be specified with mem Example The data at addresses 40H and 41H are transferred to the XA register pair MOV XA 40H MOV mem A Function mem c mem Dz g 00H FFH Transfers the contents of the A register to the data memory location addressed by the 8 bit immediate data mem Mov Function mem lt A mem 1 mem 070 00H FEH Transfers the contents of the A register to the data memory location addressed by the 8 bit immediate
132. GOTOTO INTTO start address 190 User s Manual U11330EJ2V1UMO00 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 6 3 VARIOUS DEVICES TO CONTROL INTERRUPT FUNCTIONS 1 Interrupt request flags and interrupt enable flags The following seven interrupt request flags IRQxxx corresponding to the interrupt sources are provided INTO interrupt request flag IRQO Serial interface interrupt request flag IRQCSI INT1 interrupt request flag IRQ1 Timer event counter interrupt request flag IRQTO INT4 interrupt request flag IRQ4 Timer counter interrupt request flag IRQT1 BT interrupt request flag IRQBT An interrupt request flag is setto 1 by an interrupt request and is automatically cleared to 0 when interrupt processing is performed However IRQBT and IRQ4 are cleared in a different way because these flags share a vector address See Section 6 6 The following seven interrupt enable flags IExxx corresponding to the interrupt request flags are provided INTO interrupt enable flag IEO Serial interface interrupt enable flag IECSI INT1 interrupt enable flag IE1 Timer event counter interrupt enable flag IETO INT4 interrupt enable flag IE4 Timer counter interrupt enable flag IET1 BT interrupt enable flag IEBT An interrupt enable flag set to 1 enables the corresponding interrupt and an interrupt enable flag set to 0 disables the corresponding interrupt When an interrupt request flag and the interrupt enable flag are set to 1
133. H mem 80H FFH When MBE 1 0 15 MBS 4 bit register indirect addressing Address specified by MB and HL In this case MB MBE MBS HL automatically increments the L register after addressing HL automatically decrements the L register after addressing Address specified by DE in memory bank 0 Address specified by DL in memory bank 0 8 bit register indirect addressing Address specified by MB and HL Contents of the L register is an even address In this case MB MBE MBS Bit manipulation addressing fmem bit Bit specified by bit at the address specified by fmem In this case fmem FBOH FBFH interrupt related hardware FFOH FFFH ports Bit specified by the low order two bits of the L register at the address specified by the high order 10 bits of pmem and the high order two bits of the L register In this case pmem FCOH FFFH H mem bit Bit specified by bit at the address specified by MB H and the low order four bits of mem In this case MB MBE MBS Stack addressing Address specified by the SP in memory bank 0 or 1 selected by the SBS Users Manual U11330EJ2V1UMO00 27 uPD750108 USER S MANUAL 2 3 28 4 bit direct addressing mem In this addressing mode the operand of an instruction directly specifies any areain the data memory space in units of four bits As with the 1 bit direct addressing mode
134. H to 1FFH INCS L vb 1 BR RAMC1 INCS H H lt H 1 BR RAMC1 Note Data memory locations at 000H to are allocated to general registers XA and HL so these not cleared User s Manual U11330EJ2V1UMOO 57 uPD750108 USER S MANUAL 4 5 GENERAL REGISTER 8 x 4 BITS x 4 BANKS The general registers are mapped to particular addresses in data memory Four banks of registers are provided with each bank consisting of eight 4 bit registers B C D E H L X and A The register bank RB to be enabled at the time of instruction execution is determined by RB RBE RBS RBS 0 to 3 Each general register allows 4 bit manipulation In addition BC DE HL or XA serves as a register pair for 8 bit manipulation DL also makes a register pair as well as DE and HL These three register pairs can be used as data pointers In 8 bit manipulation the register pairs in the register banks 0 lt gt 1 2 3 that have the inverted value of bit 0 of the register bank RB address can be specified as BC DE HL and XA in addition to the register pairs BC DE HL and XA See Section 3 2 A general register area can be addressed and accessed as normal RAM regardless of whether it is used as a register Figure 4 8 General Register Format Data memory 3 0 Register bank 0 008H Same as bank 0 Register bank 1 00FH 010H Same as bank 0 Register bank 2 017H Y A 018H Same as bank 0 Register bank 3 O
135. HERAL HARDWARE FUNCTIONS When the slave receives a transmission data count if it has data enough for transmitting the specified number of bytes of data the slave returns ACK Ifthe slave does not have enough data for transmission an error occurs ACK is not returned in this case The master sends ACK to the slave each time it receives one byte lt 2 gt WRITE command END command STOP command These commands write data to a slave One to 256 bytes of data can be written The data length is specified in a parameter by the master When OOH is specified as the data length the 256 byte data transfer is assumed Figure 5 73 Transfer Format of the WRITE and END Commands Command Data Data Data Command Remark M Output by the master S Output by the slave If the slave has an enough area for storing receive data of the specified length the slave returns ACK If the slave does not have an enough area an error occurs ACK is not returned in this case The master transmits an END command when all data have been transferred The END command informs the slave that all data have been transferred correctly The slave accepts an END command even before data reception is uncompleted Inthis case the data received just before the acceptance of the END command becomes valid The master compares the contents of SIO before transfer with the contents of SIO after transfer to check whether the data has been output onto the bus correctly If the conten
136. I SB1 Shift register sequence f pin function pin function 107 9 lt gt XA SBO N ch open CMOS input Transfer starting with MSB drain I O P02 CMOS input 581 N ch open drain 1 0 Serial clock selection bit W Serial clock SCK pin mode External clock applied to SCK pin Input Timer event counter output TOUTO Output 26 31 3 kHz during 2 MHz operation 15 6 kHz during 1 MHz operation b Serial bus interface control register SBIC To use the two wire serial I O mode set SBIC as shown below For details on SBIC format see 2 in Section 5 6 3 SBIC is manipulated using a bit manipulation instruction When the RESET signal is input SBIC is set to OOH In the figure below the hatched portions indicate the bits used in the two wire serial I O mode 7 6 5 4 3 2 1 0 Address FE2H BSYE ACKT CHDD RELD SBIC Do not use these bits in the Bus release trigger bit W two wire serial I O mode Command trigger bit W Remark W Write only Command trigger bit W Control bit for command signal CMD trigger output By setting CMDT 1 the SO latch is cleared to 0 Then the CMDT bit is automatically cleared to 0 Users Manual U11330EJ2V1UMO00 149 uPD750108 USER S MANUAL Bus release trigger bit W Control bit for bus release signal REL trigger output By setting RELT 1 the
137. M 4 After 1 to 3 are set set 1 in bit 3 of BTM within each interval Example Use the basic interval watchdog timer as a watchdog timer with 16 4 ms interval at 2 MHz A program is divided into several modules each of which can be executed within the interval set in BTM 16 4 ms BT is cleared at the end of each module If a program crash occurs BT overflows and an internal reset signal is generated because BT is not cleared within the set interval Initial setting MBE MB15 A 1101B BTM A Specifies a time interval and Starts processing Enables the watchdog timer From now on 1 is set in bit 3 of BTM at intervals of 16 4 ms 106 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Module 1 Processing completes within 16 4 ms Module 2 Processing completes within 16 4 ms 5 3 6 Other Functions The basic interval timer watchdog has the following functions regardless of whether it operates as a basic interval timer or watchdog timer Reading the count The count status of the basic interval timer BT can be read by using an 8 bit manipulation instruction No data can be loaded to the timer Caution When reading the count value of BT execute a read instruction twice so that unstable data which has been counted will not be read If the two read values are reasonable use the second one as the result If the two read values are far apart retry from the beg
138. M format floppy disk outside Japan only 5 25 inch IBM format floppy disk outside Japan only Note When the UV EPROM option is selected prepare three UV EPROMs each having the same contents Record the mask option data on the mask option information sheet Preparation of the required documents Prepare the following documents when ordering a masked ROM Masked ROM order sheet Masked ROM order check sheet Mask option information sheet Ordering Send aset of the media created in 2 and the documents created in 3 to a special agent or NEC s Sales Department by the date indicated in the advance notice User s Manual U11330EJ2V1UMO00 313 uPD750108 USER S MANUAL MEMO 314 User s Manual U11330EJ2V1UMO00 D 1 INSTRUCTION INDEX BY FUNCTION APPENDIX D INSTRUCTION INDEX Transfer instructions A n4 249 268 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV XCH XCH XCH XCH XCH XCH XCH XCH XCH reg1 n4 8 HL n8 2 8 A QHL A QHL A QHL A rpa1 XA HL HL A HL XA A mem XA mem mem A 249 269 249 269 249 269 249 269 249 269 249 269 249 269 249 269 249 270 249 270 249 270 249 270 249 271 249 271 mem XA 249 271 A reg 249 271 XA rp 249 271 reg1 A 249 272 rp 1 XA 249 272 A HL 249 272 A QHL 249
139. MBE RBE SP 6 SP 3 SP 4 PC14 o SP 5 lt 0 0 0 0 PC11 0 lt a 0 faddr SP lt SP 6 uPD750106 PD750108 SP 2 x x MBE RBE SP 6 SP 3 SP 4 lt PC SP 5 0 0 0 PC42 PC12 9 00 faddr SP lt SP 6 uPD75P0116 SP 2 lt x x MBE RBE SP 6 SP 3 SP 4 lt 1 0 5 lt 0 0 13 12 PC43 0 000 faddr SP SP 6 750104 PC44 9 SP SP 3 SP 2 MBE RBE 0 0 SP 1 SP SP 4 1 0750106 uPD750108 PC44 9 lt SP SP 3 SP 2 MBE RBE 0 lt SP 1 SP lt SP 4 UPD75P0116 PC44 9 SP SP 3 SP 2 MBE RBE PC5 PCy lt SP 1 SP lt SP 4 o o 7 5 o I a 5 ep 1 0750104 x x MBE RBE SP 4 0 0 0 0 lt SP 1 PC44 9 SP SP 3 SP 2 SP lt SP 6 750106 uPD750108 x x MBE RBE SP 4 MBE 0 0 SP 1 PC14 9 SP SP 3 SP 2 SP lt SP 6 75 0116 x x MBE RBE SP 4 0 0 PC13 PC42 SP 1 PC41 9 lt SP SP 3 SP 2 SP lt SP 6 Note The shaded portion is supported in Mk II mode only The other portions are supported in Mk mode only User s Manual U11330EJ2V1UMO00 257 uPD750108 USER S MANUAL Address Operation ing Skip condition area Operand Machine cycle RETSNote e uPD750104 Unconditionally MBE 0 0 lt
140. NCTIONS Figure 5 30 Timer Event Counter Mode Register Channel 0 Format Address 7 6 5 4 3 2 1 0 Symbol FAOH TMO5 4 TMO3 TW2 TMO Count pulse CP selection bit When fcc 2 MHz Count pulse CP TIO rising edge TIO falling edge fcc 2 1 95 kHz 28 7 81 kHz foc 2 31 3 kHz 1 foc 24 125 kHz Not to be set Count pulse CP TIO rising edge TIO falling edge foc 2 977 Hz 28 3 91 kHz 2 15 6 kHz foc 24 62 5 kHz Other than above Not to be set Timer start indication bit TMO3 When 1 is written into the bit the counter and IRQTO flag are cleared If bit 2 is set to 1 count operation is started Operation mode Count operation Stop retention of count contents Count operation User s Manual U11330EJ2V1UMO00 115 uPD750108 USER S MANUAL Figure 5 31 Timer Counter Mode Register Channel 1 Format Address 7 0 Symbol 6 5 4 3 2 1 FA8H TMI6 TM15 TM14 TM13 12 TM1 Count pulse CP select bit When fcc 2 MHz Count pulse CP Rising edge of INTW overflow output for clock timer foc 2 2 488 Hz fcc 2 1 95 kHz fcc 29 7 81 kHz 1 0 28 31 3 kHz Other than above Not to be set When fcc z 1 MHz Count pulse CP Rising edge of INTW overflow output for clock timer foo
141. NERAL REGISTER 8x4 BITS x 4 BANKS 58 4 6 AGGUMULATOR tira eei t P endet Re Ta o e E UE ien 59 4 7 STACK POINTER SP AND STACK BANK SELECT REGISTER SBS 60 4 8 PROGRAM STATUS WORD PIW sse nennen nene 64 4 9 BANK SELECT REGISTER BS esses eese entrent nnn nennen 67 PERIPHERAL HARDWARE FUNCTIONS nien nnne 69 DIGITAL IO POBTS itae tenete te dde ete eta ct dresser ek 69 5 1 1 Types Features and Configurations of Digital I O Ports 70 5 1 2 VO Mode Setting iret 76 5 1 3 Digital I O Port Manipulation Instructions 78 5 1 4 Digital Port Operation 81 5 1 5 Specification of Built In Pull Up Resistors 83 5 1 6 Timing of Digital l O Ports Peenstra n aaa genna iaa ae 84 52 CLOCK GENERATOR ete ett teta di e ene dieu 86 5 2 1 Clock Generator Configuration 86 5 2 2 Functions and Operations of the Clock 87 5 2 3 System Clock and CPU Clock Setting 98 5 2 4 Clock Output Circuit eessssssssseseeseeeeeen nennen nennen 100 5 3 BASIC INTERVAL TIMER WATCHDOG TIMER senes 103 5 3 1 Co
142. O specification P61 I O specification P62 I O specification P63 I O specification Port mode register group B Address 7 6 Symbol 5 4 3 2 1 0 rec PMGB Port 2 P20 P23 I O specification Port 4 P40 P43 I O specification Port 5 P50 P53 I O specification Port 7 P70 P73 I O specification Port mode register group C Address 6 Symbol 5 4 3 2 1 0 FEEH gt moe Port 8 P80 P81 I O specification Users Manual U11330EJ2V1UMO00 77 uPD750108 USER S MANUAL 5 1 3 Digital I O Port Manipulation Instructions All I O ports contained in the uPD750108 are mapped to data memory space so that all data memory manipulation instructions can be used Table 5 2 lists the instructions that are particularly useful for I O pin manipulation and their application ranges 1 Bit manipulation instructions 2 78 For digital ports PORTO to PORTS specific address bit direct addressing fmem bit and specific address bit register indirect addressing pbmem L be used This means that bit manipulation can be freely performed for these ports regardless of MBE and MBS settings P50 is ORed with P41 then the result is output to P61 SET1 CY CY lt 1 AND1 CY PORT5 O0 CY lt 50 OR1 CY PORT4 1 CY lt CYVP41 SKT CY BR CLRP SET1 PORT6 1 P61 lt 1 CLRP CLR1 PORT6 1 P6
143. Od jeseH eiqeue OL euis jeo 2 8 uno 8 8 4e1s1681 uejs 210 99 012 09 yoojo 82 29 y uio14 90 29 em VIAL SEAL omil aont LAS 1 52 62 6 113 User s Manual U11330EJ2V1UM00 uPD750108 USER S MANUAL 1 114 Timer event counter mode register TMO TM1 The timer event counter mode register TMO TM1 is an 8 bit register which controls the timer event counter Its format is shown in Figures 5 30 and 5 31 The timer event counter mode register is set by an 8 bit memory manipulation instruction Bit 3 is a start bit and can be operated bit wise It is automatically reset to 0 when the timer operation starts All the bits of the timer event counter mode register are cleared to 0 by a RESET signal generation Examples 1 Start the timer in the interval timer mode of CP 1 95 kHz during 2 MHz operation SEL MB15 or CLR1 MBE MOV XA 01001100B MOV TMn XA TMn lt 4CH 2 Restart the timer according to the setting of the timer event counter mode register SEL MB15 or CLR1 MBE SET1 TMn 3 IMn bit3 1 n 0 1 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FU
144. Operand identifier and description The operand field of an instruction must contain an operand coded according to the description rule for the operand identifier of the instruction Refer to RA75X Assembler Package User s Manual Language EEU 1343 for detailed information When there are multiple descriptions for an identifier one item is to be selected The uppercase letters and and signs are keywords which must be coded as they appear For immediate data a proper numeric value or label must be coded The abbreviations for register flags shown in Figure 3 7 can be coded as labels in place of mem fmem pmem and bit However not all labels can be coded for the fmem and pmem For details see Table 3 1 and Figure 3 7 Representation format Description method reg X A D H L 1 X B C D E H L rp XA BC DE HL BC DE HL rp2 BC DE rp XA BC DE HL XA BC DE HL rp 1 BC DE HL XA BC DE HL rpa HL HL HL DE DL 1 DE DL n4 4 bit immediate data or label n8 8 bit immediate data or label mem 8 bit immediate data or labelNote bit 2 bit immediate data or label fmem FBOH FBFH and FFOH FFFH immediate data or label pmem FCOH FFFH immediate data or label addr 0000H 0FFFH immediate data or label uPD750104 addr1 for MkII mode only 0000H 17FFH immediate data or label uPD750106 0000H 1FFFH immediate data or label uPD750108
145. Output An external clock cannot be input XT1 Input Connection pin to a crystal for subsystem clock generation When an external clock is used it is input XT2 to XT1 and its inverted signal is input to XT2 XT1 can be used as the 1 bit input test pin RESET Input System reset input Low level active CNote 2 Internally connected Connect to Vpp keeping the wiring as short as possible Vpp Positive power supply Vss m GND potential Vpp mE Provided only in the uPD75P0116 Program voltage application for program memory PROM write verify operation 12 5 V is applied for PROM write verify operation Connect to Vpp keeping the wiring as short as possible Notes1 The circuits enclosed in circles have a Schmitt triggered input 11 uPD750108 USER S MANUAL Table 2 2 Non Port Pin Functions 2 2 input Also U fete t used Function m circuit outpu typeNote MDO Input P30 P33 Provided only in the uPD75P0116 Input E B MD3 Mode selection for program memory PROM write verify operation DO D3 P40 P43 Provided only the 075 0116 Data bus pins for Input M E D4 D7 P50 P53 program memory PROM write verify operation NC No connection Note The circuits enclosed in circles have a Schmitt triggered input 12 User s Manual U11330EJ2V1UMO00 CHAPTER 2 PIN FUNCTIONS 2 2 PIN
146. PC42 9 PC42 g DE PC7 lt D PC3 9 lt E Branches to the address specified by the program counter whose low order 8 bits PC7 9 have been replaced with the contents of the DE register pair The high order bits of the program counter are not affected Caution The BR PCDE instruction usually causes a branch within the page containing the instruction However if the first byte of the instruction code is located at address xxFEH or xxFFH a branch to the next page instead of that page occurs Program memory 7 0 Page 2 2 2FFH 0 gt b 0300H Page 3 If the BR PCDE instruction is located at a or b in the figure above a branch to page 3 instead of page 2 occurs jumping to the low order 8 bits of the address specified by the contents of the DE register pair Function For the 0750108 PC42 9 12 8 PCz 4 X PC3 9 lt A Branches to the address specified by the program counter whose low order 8 bits PC7 9 have been replaced with the contents of the XA register pair The high order bits of the program counter are not affected Caution As with the BR PCDE instruction if the first byte is located at address xxFEH or xxFFH a branch to the next page instead of the page containing the instruction occurs Remark Function in this section is applicable to the uPD750108 whose program counter consists of 13 bits addr OOOOH to 1FFFH However this is also applicab
147. R S MANUAL LZINI 1 16s 2081 40 99 9 lt uonoojop ZHM 01 pue ZLNI 94 jo 401g 01 9 A AAAAAAAA 09d 08 L9d LHM c9d cHM E9d EYM OZd PHM LZd SUM 2Zd 98 Zd ZUM User s Manual U11330EJ2V1UMO00 216 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Figure 6 11 Format of INT2 Edge Detection Mode Register IM2 Address Symbol 3 2 1 0 FB6H IM21 IM20 IM2 IM21 IM20 INT2 interrupt source Interrupt input pin 0 0 Specifies rising edge of INT2 pin input INT2 1 KR7 4 Specifies falling edge of any of KRx pin KR2 6 inputs KRO KR7 8 Cautions 1 When the edge detection mode register is modified test request flags may be set in some cases So disable test inputs before modifying the edge detection mode register Then clear the test request flags using a CLR1 instruction before enabling test inputs 2 When alow level signal is applied to any of the pins subjected to falling edge detection IRQ2 is not set when a falling edge is detected on another pin User s Manual U11330EJ2V1UMO00 217 uPD750108 USER S MANUAL MEMO 218 User s Manual U11330EJ2V1UMO00 CHAPTER 7 STANDBY FUNCTION The uPD7501068 provides a standby functi
148. RETI User s Manual U11330EJ2V1UM00 203 uPD750108 USER S MANUAL 6 7 MACHINE CYCLES FOR STARTING INTERRUPT PROCESSING With the 4PD750108 series the following machine cycles are used to start the execution of the interrupt service routine after an interrupt request flag IRQxxx is set 1 When IRQxxx is set during execution of an interrupt control instruction When IRQxxx is set during execution of an interrupt control instruction an instruction preceded by that instruction is executed and an interrupt processing of three machine cycles is executed then the interrupt service routine is started Interrupt control instruction IRQxxx is set The next instruction is executed 1 to 3 machine cycles according to the instruction Interrupt processing 3 machine cycles Interrupt service routine is executed OO Cautions 1 When interrupt control instructions are contiguous these interrupt control instruc tions are executed up to the last one An instruction preceded by the interrupt control instruction executed last is executed and an interrupt processing of three machine cycles is executed then the interrupt service routine is started 2 When a Dl instruction is executed in the period during which IRQxxx is set A in the figure or in the immediately following period the interrupt request of the set IRQxxx is held until an El instruction is executed Remarks 1 Aninterrupt control instruction manipulates hardwar
149. RIPHERAL HARDWARE FUNCTIONS lt 4 gt RESET command The RESET command changes the currently selected slave to a non selected slave When a RESET command is transmitted any slave can be placed in the non selected state Figure 5 77 Transfer Format of the RESET Command M S RESET ACK Command Remark M Output by the master S Output by the slave b CHGMST command The CHGMST command passes the master authority to the currently selected slave Figure 5 78 Transfer Format of the CHGMST Command M 5 S S Command Data Remark M Output by the master S Output by the slave When the slave receives a CHGMST command the slave returns one of the following data to the master after checking whether the slave can receive the master authority OFFH Master changeable 00H Master not changeable The slave compares the contents of SIO before transfer with the contents of SIO after transfer If the contents of SIO disagree with each other an error occurs ACK is not returned in this case If the master receives OFFH the master returns ACK to the slave and starts to operate as aslave The slave which transmitted OFFH starts to operate as the master when it receives ACK iv Error occurrence If a communication error occurs the operation described below is performed The slave reports the occurrence of an error by not returning ACK to the master If an error occurs during reception of data the slave sets the status bit for
150. RT 3 FF4H PORT 4 FF5H PORT 5 FF6H PORT 6 FF7H PORT 7 FF8H PORT 8 Remark Some O parts can be used as static RAM Input output port manipulation instructions are as listed in Table 5 2 Ports 4 to 7 can be manipulated not only in 4 bit units but also in 8 bit or 1 bit units so that these ports can be controlled in various ways Examples 1 To test the condition of P13 and output different values to ports 4 and 5 according to the test result SKT MOV MOV SEL OUT 2 SET1 PORT1 3 Skips if bit 3 of port 1 is 1 XA 48H XA 18H XA 14H XA 14H MB15 Or CLR1 MBE PORTA XA Port 5 4 XA String effect instructions PORTA L Sets the bit s specified by the L register in ports 4 to 7 to 1 User s Manual U11330EJ2V1UMOO 69 uPD750108 USER S MANUAL 5 1 1 Types Features and Configurations of Digital I O Ports Table 5 1 lists the types of digital I O ports Figures 5 2 to 5 6 show the configurations of the ports Table 5 1 Types and Features of Digital Ports Port Function Operation and feature Remarks pin name 4 bit input When the serial interface function is used Also used as INT4 SCK operation mode causes the dual function pin SO SBO and SI SB1 to become an output pin PORT1 4 bit input only port Also used as INTO INT2 P10 P13 and TIO PORT2 4 bit I O Allows input or output mode setting in units Also used as PTOO PTO1 P20 P23 of 4 bits PCL and BU
151. SB1 goes high When eightbits have beentransferred serial transfer automatically terminates setting the interrupt request flag IRQCSI Example When RAM data specified by the HL register is transferred to SIO from which data is loaded into the accumulator at the same time and serial transfer is started MOV XA QHL Extracts transmit data from RAM SEL MB15 CLR1 MBE XA SIO Exchanges transmit data with receive data and starts transfer 11 Notes on the SBI mode a Whether a slave is selected is determined by detecting a match for a slave address received after bus release in the state of RELD 1 An address match is detected usually using an address match interrupt IRQCSI generated when WUP is 1 So detect selection nonselection state by slave address when WUP is set to 1 b When determining whether a slave is selected without using an interrupt when WUP 0 do not use the address match detection method Instead use transfer of commands set in advance in a program c When WUP is setto 1 during BUSY signal output BUSY is not released In the SBI mode after release of BUSY is directed the BUSY signal is output until the next falling edge of the serial clock SCK appears Before setting WUP to 1 be sure to confirm that the SBO or SB1 pin is high after releasing BUSY 176 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 12 SBI mode This section describes an example of a
152. SET1 or CLR1 instruction The RBS is set using the SEL instruction Example SET1 RBE CLR1 RBE SEL RBO SEL RB3 RBE RBE RBS RBS The general register area of the uPD750108 can be used not only on a 4 bit basis but also on an 8 bit basis with register pairs This enables users to perform transfers arithmetic logical operations comparisons and increments and decrements at a speed comparable to that of an 8 bit microcontroller and thereby enables to program using mainly general registers 1 When used as a 4 bit register When the general register area is used on a 4 bit basis eight general registers the X A B C D E H and L registers are available in the register bank specified with RB RBE RBS as shown in Figure 3 5 The A register functions as a 4 bit accumulator which performs transfers arithmetic logical operations andcomparisons The other general registers perform transfers comparisons and increments decrements with the accumulator User s Manual U11330EJ2V1UM00 37 uPD750108 USER S MANUAL 2 When used as an 8 bit register 38 When the general register area is used on an 8 bit basis the register pairs in the register bank specified by RBE RBS can be specified as XA BC DE and HL as shown in Figure 3 6 and the register pairs in the register bank that has the inverted value of bit 0 of the register bank RB can be specified as XA BC DE and HL thus prov
153. SO latch is set to 1 Then the RELT bit automatically cleared to O Caution Never use bits other than RELT and CMDT in the two wire serial I O mode 2 Communication operation The two wire serial I O mode transfers data with eight bits as one block Data is transferred bit by bit in phase with the serial clock The shift register performs shift operation on the falling edge of the serial clock SCK Transmit data is latched on the SO latch and is output on the SBO PO2 pin or SB1 P03 pin starting with the Receive data applied to the SBO pin or SB1 pin is latched in the shift register on the rising edge of SCK When eight bits have been transferred shift register operation automatically terminates setting the interrupt request flag IRQCSI Figure 5 48 Timing of Two Wire Serial I O Mode SCK SBO SB1 IRQCSI A A Completion of transfer __________ Transfer operation is started in phase with falling edge of SCK Execution of instruction that writes date to SIO Transfer start request The 580 or SB1 pin becomes an N ch open drain I O when specified as the serial data bus so the voltage level on that pin must be pulled up externally The state of the SO latch is output on the SBO or SB1 pin so the SBO or SB1 pin output states can be controlled by setting the RELT or CMDT bit However this operation must not be performed during serial transfer The output state of the SCK pin can be controlled by manipul
154. SP 1 PC41 0 SP SP 3 SP 2 SP SP 4 Then skip unconditionally e uPD750106 0750108 MBE 0 0 PCy SP 1 PC41 9 lt SP SP 3 SP 2 SP SP44 Then skip unconditionally e uPD75P0116 MBE PC45 12 SP 1 PC41 9 SP SP 3 SP 2 SP SP44 Then skip unconditionally e uPD750104 0 0 0 0 SP 1 PC41 9 lt SP SP 3 SP 2 x X MBE RBE SP44 SP SP 6 Then skip unconditionally e uPD750106 0750108 0 0 0 PC42 S m SP 1 PC11 0 lt SP SP 3 SP 2 x X MBE RBE SP44 SP SP 6 Then skip unconditionally 2 5 c x o o c 5 2 2 n e uPD75P0116 0 0 PC45 12 lt SP 1 PC41 9 lt SP SP 3 SP 2 x X MBE RBE SP44 SP SP 6 Then skip unconditionally 0750104 MBE RBE 0 0 SP 1 PC14 9 lt SP SP 3 SP 2 PSW lt SP 4 SP 5 SP lt SP 6 750106 uPD750108 MBE 0 PC12 lt SP 1 PC14 9 lt SP SP 3 SP 2 PSW lt SP 4 SP 5 SP lt SP 6 UPD75P0116 MBE PC45 PCy SP 1 PC14 9 lt SP SP 3 SP 2 PSW lt SP 4 SP 5 SP lt SP 6 Note The shaded portion is supported in Mk Il mode only The other portions are supported Mk mode only 258 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET Address Operation ing Skip condition area
155. SP XA SP lt 00H User s Manual U11330EJ2V1UM00 61 uPD750108 USER S MANUAL Figure 4 12 Data Saved to the Stack Memory Mk Mode PUSH instruction CALL or CALLF instruction Interrupt Stack Stack Stack i i Note 1 i i Note 1 Note 2 Lower bits of pair register PC3 PCO PC3 PCO t Upper bits of pair register PC7 PC4 PC7 PC4 PSW CY SK SK1 SKO Figure 4 13 Data Restored from the Stack Memory Mk I Mode POP instruction RET or RETS instruction RETI instruction Stack Stack Stack Lower bits of pair register PC11 PC8 PC11 PC8 i i Note 1 Note 2 i i Note 1 Note 2 Upper bits of pair register MBE RBE 0 12 1 0 iPC12 POS PCO sp2 D PCT PO PS W SP 5 CY SK2 SK1 SKO S 9 5 6 Notes 1 For the uPD75P0116 PC13 is entered instead of 0 2 For the uPD750104 0 is entered instead of PC12 User s Manual U11330EJ2V1UMO00 CHAPTER 4 INTERNAL CPU FUNCTIONS Figure 4 14 Data Saved to the Stack Memory Mk II Mode PUSH instruction Stack t t Figure 4 15 POP instruction Stack CALL CALLA or CALLF instruction Interrupt Stack PC11 PC8 0 10 1 0 12 RET instruction Stack SP gt PC11 1 Note1 Note2 0 i 0 i 0 iPC12 Note1 Note 2 Stack P i Note1 Note2 0 170 10 IPC12
156. T1 pins 2 211 INT2 Input Pin Also Used for Port 1 This is a rising edge active external test input pin When INT2 is selected with the edge detection mode register IM2 or when the signal applied to this pin goes high the internal test flag IRQ2 is set INT2 is an asynchronous input and can accept a signal with some high level width regardless of the operating clock of the CPU A RESET signal clears IM2 to 0 In this case the test flag IRQ2 is set by a rising edge on the INT2 pin The INT2 pin can also be used to release the STOP and HALT modes A Schmitt triggered input is used for this pin 16 User s Manual U11330EJ2V1UMOO CHAPTER 2 PIN FUNCTIONS 2 2 12 KRO KR3 Input Pins Also Used for Port 6 KR4 KR7 Input Pins Also Used for Port 7 KRO to KR7 are key interrupt input pins An interrupt is caused when parallel falling edges are detected them An interrupt source can be selected from among KRO KR7 KR2 KR7 KR4 KR7 by means of the edge detection mode register IM2 A RESET signal places these pins in the port 6 and 7 input modes 2 2 13 CL1 CL2 These pins are used for connection to a resistor R and capacitor C for main system clock generation An external clock cannot be input RC oscillation uPD750108 CL1 CL2 Vss 2 214 1 XT2 These pins are used for connection to a crystal for subsystem clock oscillation An external clock can also be applied a Crystal oscillati
157. TIO pin to 1 Nth of the original signal and outputs the divided frequency to the PTOO pin frequency divider operation Channel 0 only e Supplies the shift clock to the serial interface circuit Channel 0 only f Read function for the count value 5 5 1 Configuration of Timer Event Counter Figures 5 28 and 5 29 shows the configuration of the timer event counter User s Manual U11330EJ2V1UMO00 111 uPD750108 USER S MANUAL eui JO uonnoex3 e1oN jeubis lt OLOUI 13534 l euBis yes 010 25 86 09 mte 188 m 2 99 ou 010ul lt 8 aui ye OLLNI o bd OIL x 1nduJ Jaynq jesoy jndino lt C 8 were Joyng eoepelul i OLNOL indui uo peueso lt HOd 8 Opon EOIALL SONL 9OWL eiqeue OL g Nd joz 4g O CLYOd 03OL LLIS 0 JQUUeYD 1e1uno 1 WeIBeIg yOOIg 82 User s Manual U11330EJ2V1UMO00 112 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS yeubis y JO Jeop 11081 18584 195 Jeynq jndino e 89d 10 2 Ha L eld
158. TIONS Asng Tasna MOV Tiso aano E EE jenas den uonejedo WA A 4e9 9 JOS ezAeuv 119991 ie fo fo jo pj AQV3H I MOV uid Lgs 10 085 YOS AOS 01851 jenos 1xeu JO BuljpueY 1dnueju MII II a 5 2 Buisseooud SARIS 19 Se 89 4 173 User s Manual U11330EJ2V1UM00 uPD750108 USER S MANUAL asna jenas 49A19994 Buisseooud SARIS Doooooon vaso YOS AQVaY MOS B UU ISOOUI UOISSILUSUBL dois 19 ejeJouet jenas 1xeu 10 1dnueiu BuisseooJd eoi ep SARIS 9D1A9Q 1 1 ejeq 69 6 4 User s Manual U11330EJ2V
159. The relative branch instruction BR addr allows a branch to addresses contents of the PC less 15 to one or plus two to 16 regardless of block The program memory is located at following addresses e 0000H to OFFFH 0750104 e 0000H to 17FFH uPD750106 e 0000H to 1FFFH wPD750108 e 0000H to SFFFH uPD75P0116 The following addresses are assigned to special functions All areas excluding 0000H and 0001H can be used as normal program memory 0000H to 0001H Vector address table for holding the RBE and MBE values and program start address when a RESET signal is issued allowing a reset start at an arbitrary address 0002H to 000DH Vector address table for holding the RBE and MBE values and program start address for each vectored interrupt allowing interrupt processing to be started at an arbitrary address 0020H to 007FH Table area referenced by the GETI instructionNote Note The GETI instruction can represent an arbitrary two byte or three byte instruction or two one byte instructions in one byte and is used to reduce the number of program bytes See Section 11 1 1 50 User s Manual U11330EJ2V1UMO00 CHAPTER 4 INTERNAL CPU FUNCTIONS 0000H 0002H 0004H 0006H 0008H 000AH 000CH 0020H 007FH 0080H 07FFH 0800H OFFFH 7 6 5 4 0 Internal reset start address o ihgrowerd oi INTBT INT4 start address INTBT INT4 start address low order 8 bits INTO start address
160. The uPD750108 contains an 8 bit basic interval timer watchdog timer which has the following functions a Interval timer operation which generates a reference timer interrupt b Operation as a watchdog timer for detecting program crashes and resetting the CPU c Reading the count value 5 3 1 Configuration of the Basic Interval Timer Watchdog Timer Figure 5 23 shows the configuration of the basic interval timer watchdog timer Figure 5 23 Block Diagram of the Basic Interval Timer Watchdog Timer Clear signal Clear signal MPX Basic interval timer BT interrupt 8 bit frequency divider request flag Vectored interrupt request signal From the clock generator 22 2 212 _ Internal reset signal SET1Note BTM3 BTM2 BTM1 BTMO SET1Nete 4 Internal bus Note Instruction execution 5 3 2 Basic Interval Timer Mode Register BTM The BTM is a 4 bit register for controlling operation of the basic interval timer BT A 4 bit memory manipulation instruction is used to set the BTM Bit 3 can be independently manipulated using a bit manipulation instruction Example The interrupt generation interval is set to 4 10 ms at 2 MHz SEL MB15 or CLR1 MBE MOV A 1111B MOV lt 11118 User s Manual U11330EJ2V1UMO00 103 uPD750108 USER S MANUAL When bit 3 is set to 1 the BT is cleared and the basic interval tim
161. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 17 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry 24 NC S AS 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is gr
162. USY Serial interface operation mode selection bit W Shift register sequence P02 SO SBO POS SI SB1 pin function pin function 107 9 XA SBO N ch open CMOS input Transfer starting with MSB drain I O P02 CMOS input 581 N ch open drain I O 160 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Serial clock selection bit W Serial clock SCK pin mode External clock applied to SCK pin Input Timer event counter output TOUTO Output 24 125 kHz during 2 MHz operation 62 5 kHz during 1 MHz operation fcc 23 250 kHz during 2 MHz operation 125 kHz during 1 MHz operation b Serial bus interface control register SBIC To use the SBI mode set SBIC as shown below For details on SBIC format see 2 in Section 5 6 3 SBIC is manipulated using a bit manipulation instruction When the RESET signal is input SBIC is set to OOH In the figure below hatched portions indicate the bits used in the SBI mode BSYE ACKD CMDD RELD CMDT RELT SBIC Bus release trigger bit W Command trigger bit W Bus release detection flag R Command detection flag R Acknowledge trigger bit W Acknowledge enable bit R W Acknowledge detection flag Busy enable bit R W Remark R Read only W Write only R W Read write B
163. Y pmem L 252 288 G AND1 CY H mem bit 252 288 eeu TACO 00380 H B HALT 259 299 BR addr 253 288 BR addr1 253 289 BR BCDE 254 292 IN 259 298 BR BCXA 255 292 IN XA PORTR 259 298 BR PCDE 254 291 INCS mem 251 284 BR 254 291 INCS reg 251 283 BR laddr 254 289 INCS 251 283 BR Saddr 254 289 INCS 251 283 BR addr1 254 289 BRA laddr1 255 289 i BRCB Icaddr 255 290 MOV A mem 249 270 MOV A reg 249 271 A n4 249 268 CALL laddr 256 293 MOV A QHL 249 269 CALLA laddri 255 293 MOV A HL 249 269 CALLF 256 294 MOV A HL 249 269 CLR1 CY 251 285 CLR1 fmem bit 252 286 318 User s Manual U11330EJ2V1UMO00 APPENDIX D INSTRUCTION INDEX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVT MOVT MOVT MOVT MOV1 MOV1 MOV1 MOV1 MOV1 MOV1 N NOP NOT NOT1 OR OR OR OR 1 1 1 249 269 HL n8 249 269 mem A 249 271 mem XA 249 271 reg1 A 249 272 reg1 n4 249 269 rp 1 XA 249 272 2 8 249 269 XA mem 249 271 XA rp 249 271 XA n8 249 269 XA HL 249 270 HL A 249 270 HL XA 249 270 XA BCDE 250 276 XA BCXA 250 276 XA PCDE 250 274 XA PCXA 250 275 CY fmem b
164. Z PORT3 Allows input or output mode setting ona Also used as MDO MD3Note 1 P30 P33 bit by bit basis PORT4 4 bit I O Allows input or output mode Ports 4 and 5 Also used as DO D3Note 1 P40 P43 N ch open drain setting in units of 4 bits can be paired withstand voltage Whether to use pull up allowing data I O PORT5 of 13 V resistors can be specified in units of 8 bits Also used as D4 D7Note 1 P50 P53 bit by bit with the mask optionNote 2 PORT6 4 bit Allows input or output mode Ports 6 and 7 Also used as KRO KR3 P60 P63 setting on a bit by bit basis be paired allowing data I O in units of 8 bits Also used as KR4 KR7 PORT7 Allows input or output mode P70 P73 setting in units of 4 bits PORT8 2 bit I O Allows input or output mode setting in units P80 P81 of 2 bits Notes 1 Only for the uPD75P0116 2 Pull up resistors specified with the mask option are not connected to the uPD75P0116 P10 is also used as an external vectored interrupt input pin This input is provided with a noise eliminator See Section 6 3 for details When the RESET signal is generated output latches of ports 2 to 8 are cleared to 0 and the output buffer is turned off so that these ports are in the input mode 70 User s Manual U11330EJ2V1UM00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 2 Configurations of Ports 0 and 1 SI SCK INT4 SO Internal A A A SCK
165. ag is set INT4 is an asynchronous input and can accept a signal with some high level width or low level width regardless of what the CPU clock is The INT4 pin can also be used to release the STOP and HALT modes A Schmitt triggered input is used for this pin User s Manual U11330EJ2V1UM00 15 uPD750108 USER S MANUAL 2 2 10 INTO INT1 Input Pins Also Used for Port 1 These are the edge detection vectored interrupt input pins For INTO the noise eliminator can be selected The edge to be detected can be selected using the edge detection mode registers IMO IM1 1 INTO bits 0 and 1 of IMO a Rising edge active b Falling edge active c Both rising and falling edges active d External interrupt signal input disabled 2 INT1 bit of IM1 a Rising edge active b Falling edge active INTO and INT1 are asynchronous inputs and can accept a signal with some high level width regardless of what the CPU clock is INTO can be provided with the noise eliminator function by software and change the sampling clock that eliminates the noise at two levels In this case the width of the signal received by the CPU operation clock varies A RESET input clears IMO and IM1 to 0 selecting rising edge active The INTO and INT1 pins can be used to release STOP and HALT modes When the noise eliminator is selected however the INTO pin cannot be used to release STOP and HALT modes Schmitt triggered inputs are used for the INTO and IN
166. ame time 124 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Re set instruction Re set instruction Clock A specified Clock B specified Clock A specified Clock B lt 1 gt lt 2 gt XN 5 Operation after the modulo register is changed The contents of the modulo register are changed when an 8 bit data memory manipulation instruction is executed CP Modulo register n X m Re set instruction Count register n Match signal Match signal If the new value of the modulo register is less than the value of the count register the count register continues count operation until it overflows then it restarts count operation from 0 Accordingly if the new value m of the modulo register is less than the value n before it is changed the timer must be restarted after the contents of the modulo register are changed CP Modulo register n Count register User s Manual U11330EJ2V1UMO00 125 uPD750108 USER S MANUAL 5 6 5 6 SERIAL INTERFACE 1 Serial Interface Functions The wPD750108 contains a clock synchronous 8 bit serial interface which has four modes The functions of the four modes are outlined below 1 2 3 4 126 Operation halt mode This mode is used when serial transfer is not performed This mode reduces power consumption Three wire serial I O mode In this mode 8 bit data is transferred through t
167. an interrupt 220 fy 217 fy 215 fy 213 fy selected accord ing to BTM setting Fixed to 29 29 fcc or no wait selected using a mask option Subsystem clock oscillator Crystal oscillator Instruction execution time When selecting the main system clock 0 95 1 91 3 81 15 3 us when operating at 4 19 MHz 0 67 1 33 2 57 10 7 us when operating at 6 0 MHz 4 8 16 64 us when operating at 1 MHz 2 4 8 32 us when operating at 2 MHz When selecting the subsystem clock 122 us when operating at 32 768 kHz Pin connection 20 CU 38 GB IC 24 CU 42 GB P21 PTO1 6 9 CU 23 26 GB P33 P30 P33 MD3 P30 MDO 38 41 CU 13 16 GB P43 P40 P43 D3 P40 DO 34 37 CU 8 11 GB P53 P50 User s Manual U11330EJ2V1UMO00 P53 D7 P50 D4 303 uPD750108 USER S MANUAL 2 2 120750008 120790108 75 16 CMOS input 8 Built in pull up resistors that can be connected by software 7 CMOS I O 18 Built in pull up resistors that can be connected by software N ch open drain I O 8 Pull up resistors that can be incorporated by 8 No mask option mask option Withstand voltage of Withstand voltage of 13 V 13 V 34 4 channels 4 channels 8 bit timer counter 1 8 bit timer counter clock timer output function 8 bit timer event provided 1 count
168. anipulated In this addressing mode the high order four bits of the data memory address in the memory bank specified by MB MBE MBS are indirectly specified using the H register and the low order four bits and bit address are directly specified in the operand This addressing mode enables a wide variety of manipulations for each bit in the entire data memory space Example Bit 2 at address 32H FLAG3 is reset if both bit 3 at address 30H FLAG1 and bit 0 at address 31H FLAG2 are set to 0 or 1 FLAG1 FLAG2 _ FLAG1 FLAG2 FLAG3 EQU EQU EQU SEL MOV MOV1 XOR1 MOV1 FLAG3 30H 3 31H 0 32H 2 MBO H FLAG1 SHR 6 CY H FLAG1 CY H FLAG2 H FLAG3 CY lt FLAG CY lt CY VFLAG2 FLAG3 lt CY User s Manual U11330EJ2V1UMO00 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP 7 Stack addressing This addressing mode is used for save restoration operation in interrupt processing or subroutine processing In this addressing mode the address indicated by the stack pointer 8 bits of data memory bank 0 is specified This addressing mode can be used for register save restoration operation using the PUSH or POP instruction as well as save restoration operation in interrupt and subroutine processing Examples 1 A register is saved and restored in subroutine processing SUB PUSH XA PUSH HL PUSH BS Save MBS and RBS POP BS POP HL POP XA RET 2 The contents of the HL register
169. anipulation 8 bit manipulation DE 4 bit transfer Direct addressing Bit manipulation 4 bit transfer 8 bit transfer Automatic increment INCS L H mem bit Bit manipulation User s Manual U11330EJ2V1UM00 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP 5 8 bit register indirect addressing HL Inthis addressing mode the data pointer HL register pair indirectly specifies any areain the data memory space in units of eight bits The 4 bit data at the address determined with bit 0 of the data pointer bit O of the L register set to 0 and the 4 bit data at the address incremented by 1 are processed as a pair on an 8 bit basis with the 8 bit accumulator XA register pair A memory bank is specified in the same way as the 4 bit register indirect addressing with the HL register specified In this case MB MBE MBS This addressing mode can be applied to the MOV XCH and SKE instructions Examples 1 comparison is made to determine whether the value of the count register TO of timer event counter 0 is equal to the data at addresses and 31H DATA EQU 30H CLR1 MBE MOV HL DATA MOV XA TO XA lt Count register 0 SKE XA HL XA HL 2 The data memory of OOH to FFH is cleared to 0 CLR1 CLR1 MBE MOV XA 00H MOV HL 04H LOOP MOV HL XA HL lt XA INCS HL INCS HL BR LOOP 6 Bit manipulation addressing This addressing mode is used to perform bit manipulations suc
170. anted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document b
171. ared and P63 is reset SKTCLR IRQTO IRQTO 1 BR NO NO CLR1 PORT6 3 YES 3 If both P30 and are set to 1 P53 is reset MOV1 CY PORT3 0 CY lt P30 AND1 CY PORT4 1 CYAP41 NOT1 CY lt MOV1 PORT5 3 CY P53 lt CY User s Manual U11330EJ2V1UMO00 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP b Specific address bit register indirect addressing pmem L In this addressing mode the bits of peripheral hardware I O ports are indirectly specified using a register to allow continuous manipulations This addressing mode can be applied to data memory addresses FCOH to FFFH In this addressing mode the high order 10 bits of a 12 bit data memory address is directly specified in the operand and the low order two bits and bit address are indirectly specified using the L register Thus the use of the L register enables 16 bits four ports to be continuously manipulated This addressing mode again enables bit manipulation regardless of MBE and MBS setting Example Pulses are output on the bits in the order from port 4 to port 7 Po JL TL sus P73 MOV L 0 LOOP SET1 PORT4 L Bits L4 9 of ports 4 to 7 1 CLR1 PORT4 L Bits 11 0 of ports 4 to 7 lt 0 INCS L NOP BR LOOP User s Manual U11330EJ2V1UMOO 33 uPD750108 USER S MANUAL 34 c Specific 1 bit direct addressing H mem bit This addressing mode enables any bit in the data memory space to be m
172. ata each pin is manipulated when atest instruction such as the SKT instruction a bit input instruction such as MOV1 or an instruction for taking in port data on the internal bus in units of four or eight bits such as an IN MOV arithmetic logical or comparison instruction is executed When an instruction the OUT or MOV instruction is executed to transfer the contents of the accumulator to a port in units of four or eight bits the data of the accumulator is latched in the output latch with the output buffers kept off When the XCH instruction is executed the data on each pin is loaded into the accumulator and the data in the accumulator is latched in the output latch with the output buffers kept off When the INCS instruction is executed the 4 bit data existing on the pins plus 1 is latched in the output latch with the output buffers kept off When an instruction such as the CLR1 or SKTCLR instruction is executed to rewrite a data memory bit the output latch data of the specified bit can be rewritten according to the instruction but the states of the other output latch bits are undefined Operation when the output mode is set When a test instruction or instruction for taking in port data on the internal bus in units of four or eight bits is executed output latch data is manipulated When an instruction is executed to transfer the contents of the accumulator in units of four or eight bits the output latch data is rewri
173. ating the output latch in the output mode internal system clock mode See Section 5 6 8 150 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 3 Serial clock selection To select the serial clock manipulate bits 0 and 1 of serial operation mode register CSIM The serial clock can be selected out of the following four clocks Table 5 8 Serial Clock Selection and Application in the Two Wire Serial I O Mode Mode register Serial clock CSIM CSIM S Masking of acd serial clock Timing for shift register R W and Application start of serial transfer External Automatically In the operable mode Slave CPU SCK masked when CSIE 1 8 bit data When the serial clock is TOUT transfer is masked after 8 bit transfer Arbitrary speed flip flop completed When SCK is high serial transfer 26 Low speed serial transfer 4 Signals Figure 5 49 shows operations of RELT and CMDT Figure 5 49 Operations of RELT and CMDT SO latch RELT CMDT 5 Transfer start Serial transfer starts by writing transfer data into shift register SIO provided that the following two conditions are satisfied The serial interface operation enable disable specification bit CSIE is set to 1 The internal serial clock is not operating after 8 bit serial transfer or SCK is high Cautions 1 Setting CSIE to 1 after writing data to the shift register does not start trans
174. be set to 0 Mode switching designation Mk II mode Mk mode Caution The CPU operates in Mk mode after the RESET signal is issued because bit 3 of SBS is set to 1 Set bit 3 of SBS to 0 Mk Il mode to use the CPU in Mk II mode 48 User s Manual U11330EJ2V1UM00 CHAPTER 4 INTERNAL CPU FUNCTIONS 4 2 PROGRAM COUNTER PC 12 BITS uPD750104 13 BITS uPD750106 AND up PD750108 14 BITS uPD75P0116 The program counter is a binary counter which retains the address data of the program memory The program counter consists of 12 bits in the 4PD750104 see Figure 4 2 a 13 bits in the uPD750106 and uPD750108 see Figure 4 2 b and 14 bits in the uPD75P0116 see Figure 4 2 c Figure 4 2 Program Counter Organization a WPD750104 b 0750106 and 0750108 uPD75P0116 Usually each time an instruction is executed the program counter is automatically incremented according to the number of bytes in the instruction When a branch instruction BR BRA BRCB is executed immediate data indicating the branch destination and the contents of a register pair are set in all or some bits of the program counter When a Subroutine call instruction CALL CALLA CALLF is executed or a vectored interrupt occurs the current contents of the program counter already incremented return address for fetching the next instruction are savedin the stack memory data memory indicated by the stack pointer then t
175. by a 2 machine cycle instruction Instruction Manipulation instruction execution Output latch output pin Figure 5 10 ON Timing Chart of Built In Pull Up Resistor Connected by Software D1 2 machine cycles D1 Instruction Built in pull up resistor setting instruction execution Pull up resistor specification register User s Manual U11330EJ2V1UM00 85 uPD750108 USER S MANUAL 5 2 CLOCK GENERATOR The clock generator supplies various clock signals to the CPU and peripheral hardware to control the CPU operation mode 5 2 1 Clock Generator Configuration Figure 5 11 shows the configuration of the clock generator Figure 5 11 Block Diagram of the Clock Generator clock generator Subsystem Main system clock generator RC oscillation external resistor and capacitor Clock timer 1 2 1 4 1 16 Timer event counter Timer counter Serial interface Clock timer INTO noise eliminator Clock output circuit Basic interval timer BT 1 1 to 1 4096 Frequency divider 3 Oscillator SCC disable signal gt gt SCC3 gt SCCO Internal bus HALT flip flop 4 sTopNe PCC2 PCC3 clear signal STOP flip flop Q S R Main system clock frequency 2 fxr Subsystem clock frequency Note Instruction execution Remarks 1 fcc 3 CPU clock 4 5 6 8
176. by mode fa Selects a noise eliminator Enabled Cannot be released Does not select a noise eliminator Disabled Can be released Sampling clock 9 2 4 8 32 us at 2 MHz 4 8 16 64 us at 1 MHz fcc 64 32 us at 2 MHz 64 us at 1 MHz b INT1 edge detection mode register IM1 Address Symbol 3 2 1 0 IM10 Detection edge specification o Specifies rising edge Specifies falling edge Caution Changing the edge detection mode register may set an interrupt request flag So disable the interrupts before changing the edge detection mode register Then clear the interrupt request flag with a CLR1 instruction and enable the interrupts When fcc 64 is selected as a sampling clock pulse in changing IMO wait for 16 machine cycles after changing the mode register and clear the interrupt request flag User s Manual U11330EJ2V1UMO00 197 uPD750108 USER S MANUAL 4 Interrupt status flags The interrupt status flags ISTO and IST1 which are contained in the PSW indicate the status of processing currently executed by the CPU By using the content of these flags the interrupt priority control circuit controls multiple interrupts as indicated in Table 6 3 A 4 bit manipulation instruction or bit manipulation instruction can be used to set and reset ISTO and IST1 so that multiple interrupts are enabled by changing the current status of execution ISTO and IST1 can be manipulated on a single bit basis at an
177. can be Hardware name symbol manipulated Address SCKP FFOH Port 0 PORTO Dem Dm erem FF6HNote 2 pate OH Note 2 EE Port 7 PORT m FF8H Port 8 PORTS Notes 1 Bit 1 can be read or written only in serial operation enable mode manipulation is performed Bit manipulation Remarks addressing fmem bit It can be read when four bit 2 KRO to KR7 can be read R bit by bit When inputting 4 bits at a time specify PORT6 or PORT7 User s Manual U11330EJ2V1UMO00 CHAPTER 4 INTERNAL CPU FUNCTIONS 41 Mk MODE Mk MODE SWITCH FUNCTIONS 4 1 1 Differences between Mk I Mode and Mk II Mode The CPU of the PD750108 subseries has two modes Mk mode and Mk II mode and which mode is used is selectable Bit 3 of the stack bank selection register SBS determines the mode e Mk mode This mode has the upward compatibility with the 75X series It can be used in the 75XL CPUs having a ROM of up to 16KB Mk Il mode This mode is not compatible with the 75X series It can be used in all 75XL CPUS including those having a ROM of 16KB or more Table 4 1 shows the differences between Mk mode and Mk II mode Table 4 1 Differences between Mk I Mode and Mk II Mode Mk mode Mk 1 mode Number of stack bytes in a subroutine instruction 2 bytes 3 bytes BRA addr1 instruction Not supported Supported CALLA addr1 instruction CALL addr instruction 3 machi
178. cation Sampling clock selection V Input buffer fcc 64 Internal bus Note Even if fcc 64 is selected HALT mode cannot be released by INTO b Configuration of the INT1 circuit INT1 INT1 P11 O Edge detection circuit Ge set signal Detection edge specification Input buffer Internal bus c Configuration of the INT4 circuit INT4 INT4 P00 Both edge gt oy j detection circuit set signal Input buffer Internal bus User s Manual U11330EJ2V1UMO00 195 uPD750108 USER S MANUAL Figure 6 5 I O Timing of a Noise Eliminator 15 15 15 tsp tsp 1 Shorter than sampling cycle tsmp D D INTO a OEO Shaped output Es Removed as noise lt 2 gt 1102 times a INTO D n Shaped output b INTO Shaped output Removed as noise lt 3 gt Longer than 2 times INTO Shaped output Remark tsp tcy or 64 foc 196 User s Manual U11330EJ2V1UMO00 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Figure 6 6 Format of Edge Detection Mode Registers a INTO edge detection mode register IMO Address Symbol 3 2 1 0 IMO1 IMOO Detection edge specification EIE Specifies rising edge 0 1 Specifies falling edge 1 0 Specifies both rising and falling edges Ignored No interrupt request flag is set IM02 Noise eliminator selection bit Sampling Stand
179. cation of the three wire serial I O mode a Data is transferred starting with the MSB on a transfer clock of 62 5 kHz during 1 MHz operation Master operation Sample program CLR1 MBE MOV XA 10000010B MOV CSIM XA Set transfer mode MOV XA TDATA TDATA is transfer data storage address MOV SIO XA Set transfer data and start transfer Caution A second or subsequent transfer can be started by setting data in SIO MOV SIO XA or XCH XA SIO uPD750108 uPD7225G LCD controller driver etc In this case the SI SBI pin on the LPD750108 can be used as an input Users Manual U11330EJ2V1UMO00 145 uPD750108 USER S MANUAL b Data is transmitted and received starting with the LSB on an external clock slave operation In this case the function of inverting the MSB LSB is used for shift register read write operation uPD750108 Other microcomputers P01 SCK SCK 5 581 lt SO SO SBO SI Sample program Main routine CLR1 MBE MOV XA 84H MOV CSIM XA Serial operation halt MSB LSB invert mode external clock MOV XA TDATA MOV SIO XA Set transfer data and start transfer EI IECSI EI Interrupt routine MBE 0 MOV XA TDATA XCH XA SIO Start to transfer receive data and transmit data MOV RDATA XA Save receive data RETI c Data is transmitted and received by using a transfer clock of 125 kHz during 1 MHz operation uPD750108 master uPD75206 etc SCK SCK SO SBO Sl SI SB
180. ch signal from address comparator R Serial interface operation enable disable specification bit W Remark R Read only W Write only 140 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Serial interface operation enable disable specification bit W Shift Shift register operation operation Serial clock counter clock counter IRQCSI ROCSI flag SO SBO and 5 581 pins and SI SB1 pins Shift operation enabled Count operation Can be set Used in each mode as well as for port 0 Signal from address comparator R CO Note Condition for being cleared COI 0 Condition for being set COI 1 When the slave address register SVA does When the slave address register SVA match the data of the shift register matches the data of the shift register Note COI can be read only before serial transfer is started or after serial transfer is completed An undefined value may be read during transfer COI data written by an 8 bit manipulation instruction is ignored Wake up function specification bit W WUP 0 Sets IRQCSI each time serial transfer is completed Serial interface operation mode selection bit W Shift register sequence P02 SO SBO POS SI SB1 pin function pin function 107 9 XA SO SI Transfer starting with MSB CMOS output CMOS input 109 7 lt gt XA Transfer starting with LSB Remark x Don t care Serial c
181. connected to the uPD75P0116 User s Manual U11330EJ2V1UMO00 CHAPTER 1 GENERAL 1 2 ORDERING INFORMATION Part number Package On chip ROM uPD750104CU xxx 42 pin plastic shrink DIP 600 mil Masked ROM uPD750104GB xxx 3BS MTX 44 pin plastic QFP 10 x 10 mm Masked ROM uPD750106CU xxx 42 pin plastic shrink DIP 600 mil Masked ROM uPD750106GB xxx 3BS MTX 44 pin plastic QFP 10 x 10 mm Masked ROM uPD750108CU xxx 42 pin plastic shrink DIP 600 mil Masked ROM uPD750108GB xxx 3BS MTX 44 pin plastic QFP 10 x 10 mm Masked ROM uPD75P0116CU uPD75P0116GB 3BS MTX 42 pin plastic shrink DIP 600 mil 44 pin plastic QFP 10 x 10 mm Remark xxx is a ROM code number User s Manual U11330EJ2V1UMO00 One time PROM One time PROM uPD750108 USER S MANUAL 1 3 DIFFERENCES AMONG gu PD750108 SUBSERIES PRODUCTS Item uPD750104 uPD750106 u PD750108 uPD75P0116 Program counter 12 bits 13 bits 14 bits ROM byte Masked ROM Masked ROM Masked ROM One time PROM 4096 6144 8192 16384 RAM x 4 bits 512 Mask Pull up resistors at Incorporated None option ports 4 and 5 Whether to incorporate pull up resistors can Cannot be be specified incorporated Wait time applied Available Not available when STOP mode is 29 fcc or no wait Note Fixed to 29 fcc Note released by an interrupt Selection to use Yes No feedback resistors Whether to use feedback resistors can be Feedback resistors fo
182. crement produces data that is 0 the immediately following instruction is skipped User s Manual U11330EJ2V1UMO00 283 uPD750108 USER S MANUAL CS INCS mem Function mem lt mem 1 Skip if mem 0 mem Dz g 00H FFH Increments the data at the data memory location addressed by the 8 bit immediate data mem If the result of increment produces data that is 0 the immediately following instruction is skipped C gt DECS reg Function reg lt reg 1 Skip if reg FH Decrements the contents of register reg X A H L D E B C If the result of decrement produces reg FH the immediately following instruction is skipped C DECS rp Function rp lt 1 Skip if rp FFH Decrements the contents of register pair rp XA HL DE BC XA HL DE BC If the result of decrement produces rp FFH the immediately following instruction is skipped 11 4 7 Compare Instructions SKE reg n4 Function Skip ifreg n4 n4 13 9 0 FH Skips the immediately following instruction if the contents of register reg X A H L D E B C match the 4 bit immediate data n4 AD SKE HL n4 Function Skip if HL n4 n4 13 9 Skips the immediately following instruction if the data at the data memory location addressed by the HL register pair match the 4 bit immediate data n4 C2 SKE A HL Function Skip if A HL Skips the immediately following instruction if the contents of t
183. d The data bus pins 00 07 have been added Revised chapter Throughout CONNECTION OF UNUSED PINS has been changed Chapter 2 WRITING TO THE PROGRAM MEMORY has been changed READING THE PROGRAM MEMORY has been changed Chapter 9 Modification of the instruction list Chapter 11 The target to be compared has been changed from the uPD75008 to PD750008 User s Manual U11330EJ2V1UMO00 Appendix A 325 uPD750108 USER S MANUAL MEMO 326 User s Manual U11330EJ2V1UMO00 NEC Message From Name Company Tel FAX Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete bug free and up to date we readily accept that errors may occur Despite all the care and precautions we ve taken you may encounter problems in the documentation Please complete this form whenever you d like to report errors or suggest improvements to us Address North America Hong Kong Philippines Oceania NEC Electronics Inc NEC Electronics Hong Kong Ltd Corporate Communications Dept Fax 852 2886 9022 9044 Fax 1 800 729 9288 1 408 588 6130 Korea Europe NEC Electronics Europe GmbH Hong Kong Ltd Technical Documentation Dept ss 02 226 imn Fax 49 211 6503 274 ax x E South America Taiwan NEC do Brasil S A NEC Electronics Taiwan Ltd Fax 55 11 6465 6829 Fax 02 2719 5951
184. d portions indicate the bits used in the two wire serial I O mode 7 6 5 4 3 2 1 0 Serial clock selection bit W Address FEOH Serial interface operation mode selection bit W Wake up function specification bit W Match signal from address comparator R Serial interface operation enable disable specification bit W Remark R Read only W Write only Serial interface operation enable disable specification bit W Shift register operation Serial clock counter clock counter IRQCSI RQCSI flag SO SBO and 5 581 pins and SI SB1 pins E Shift operation enabled Count operation Can be set Used in each mode as well as for port 0 Signal from address comparator R CO Note Condition for being cleared COI 0 Condition for being set COI 1 When the slave address register SVA does not When the slave address register SVA match the data of the shift register matches the data of the shift register Note COI can be read only before serial transfer is started or after serial transfer is completed An undefined value may be read during transfer COI data written by an 8 bit manipulation instruction is ignored Wake up function specification bit W WUP EN Sets IRQCSI each time serial transfer is completed 148 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Serial interface operation mode selection bit W P02 SO SBO P03 S
185. data mem and transfers the contents of the X register to the next memory address An even address can be specified with mem Te MOV A reg Function A lt reg Transfers the contents of register reg X A H L D E B C to the A register MR MOV XA rp Function XA rp Transfers the contents of register pair rp XA HL DE BC XA HL DE BC to the XA register pair Example The contents of the XA register pair are transferred to the XA register pair MOV XA XA User s Manual U11330EJ2V1UMO00 271 uPD750108 USER S MANUAL MOV reg1 A Function regi A Transfers the contents of the A register to register reg1 X H L D E B C C D Mov rp t xa Function rp 1 XA Transfers the contents of the XA register pair to register pair rp 1 HL DE BC XA HL DE BC C XCH A HL Cc XCH A HL XCH A HL A rpat Function Register pair specified by the operand When is specified for the register pair Skip if L 0 When HL is specified for the register pair Skip if L FH Exchanges the contents of the A register with the data at the data memory location addressed by the specified register pair HL HL HL DE DL When HL automatic increment is specified for the register pair automatically increments the contents of the L register by one after the data exchange and continues the operation until the contents are set to 0 Then skips t
186. data n4 then sets the result in the A register Example The low order three bits of an accumulator are set to 1 OR A 0111B OR A HL Function A Av HL ORs the contents of the A register with the data at the data memory location addressed by the HL register pair then sets the result in the A register C D ORXArm Function XA XA v rp ORs the contents of the XA register pair with the contents of register pair rp XA HL DE BC XA HL DE BC then sets the result in the XA register pair User s Manual U11330EJ2V1UMO00 281 uPD750108 USER S MANUAL C OR rp 1 XA Function rp 1 rp v XA ORs the contents of register pair rp 1 HL DE BC XA HL DE BC with the contents of the XA register pair then sets the result in register pair rp 1 C XOR A n4 Function A 4 14 13 0 Exclusive ORs the contents of the A register with the 4 bit immediate data n4 then sets the result in the A register Example The high order four bits of an accumulator is inverted XOR A 1000B C D XOR A HL Function A HL Exclusive ORs the contents of the A register with the data at the data memory location addressed by the HL register pair then sets the result in the A register XA rp Function XA XA vrp Exclusive ORs the contents of the XA register pair with the contents of register pair rp XA HL DE BC XA HL DE
187. de STOP instruction HALT mode HALT instruction System clock for setting Can be set only when operating on the main system clock Can be set either with the main system clock or the subsystem clock Operation Clock oscillator status The main system clock stops its operation Only the CPU clock stops its operation oscillation continues Basic interval timer watchdog timer Does not operate Can operate only at main system clock oscillation IRQBT is set at reference time intervals Serial interface Can operate only when the external SCK input is selected for the serial clock Can operate only when external SCK input is selected as the serial clock or at main system clock oscillation Timer event counter Can operate only when the TIO pin input is selected for the count clock Can operate only when TIO pin input is specified as the count clock or at main system clock oscillation Timer counter Does not operate Can operateNote 1 Clock timer Can operate when fxr is selected as the count clock Can operate External interrupt INT1 INT2 and INT4 can operate Only INTO cannot operate Note 2 CPU Does not operate Release signal Notes 1 An interrupt request signal from hardware whose operation is enabled by the interrupt enable flag or the generation of a RESET signal Operation is possible only when the main system clock operates
188. decrement mode each time an instruction is executed thus simplifying the program step Example The data at 50H to 57H is transferred to 110H to 117H DATA1 EQU 57H DATA2 EQU 117H SET1 MBE MBE lt 1 SEL MBS lt 1 MOV D DATA1 SHR4 D lt 5 MOV HL DATA2 OFFH HL 17H LOOP MOV A DL A DL XCH A HL SA lt HL L lt L 1 BR LOOP The addressing mode using the HL register pair as the data pointer finds a wide range of operations such as data transfer operations comparison and I O The addressing mode using the DE register pair or DL register pair is applied to the MOV and XCH instructions This addressing mode combined with an increment decrement instruction for a general register or register pair enables data memory space addresses to be freely updated as shown in Figure 3 3 Example 1 The data at 50H to 57H is compared with the data at 110H to 117H DATA1 EQU 57H DATA2 EQU 117H SET1 MBE SEL MB1 MOV D DATA1 SHR4 MOV HL DATA2 AND OFFH LOOP MOV A DL SKE A HL _ A HL BR NO NO DECS L YES L L 1 BR LOOP User s Manual U11330EJ2V1UMOO 29 uPD750108 USER S MANUAL 30 Example 2 The data memory of 00H to FFH is cleared to 0 Automatic decrement DECS L CLR1 CLR1 MOV MOV LOOP MOV INCS BR RBE MBE XA 00H HL 04H QHLA HL lt A HL HL lt HL 1 LOOP Figure 3 3 Updating Static RAM Addresses DL 4 bit transfer HL 4 bit m
189. e address FBxH in data memory which handles interrupt processings There are two types of interrupt control instruction a DI instruction and an El instruction 2 Three machine cycles required for the interrupt processing include the time to manipulate the stack when an interrupt is accepted 204 User s Manual U11330EJ2V1UMO00 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 2 When IRQxxx is set during an instruction other than that described in 1 a When IRQxxx is set at the last machine cycle of the instruction being executed In this case an instruction preceded by the instruction being executed is executed and an interrupt processing of three machine cycles is executed then the interrupt service routine is started An instruction other than interrupt control instruction IRQxxx is set The next instruction is executed 1 to 3 machine cycles to the instruction Interrupt processing 3 machine cycles Interrupt service routine is executed 2 Ou Caution When one or more interrupt control instructions follow an instruction preceded by the interrupt control instructions is executed and an interrupt processing of three machine cycles is executed then the interrupt service routine is started When an instruction to be executed after setting IRQxxx is a Dl instruction the interrupt request of the set IRQxxx is held b When IRQxxx is set earlier than the last machine cycle of the instruction being executed In this case
190. e symbol manipulated Bit Address manipulation Remarks addressing ISTO Manipulation in 8 bit units is enabled only SkKpNote 1 SK1Note SKQNote1 for reading Program status word PSW FB2H Interrupt priority select register IPS rer mem m O pn ww o 9 fmem bit R W ww o 9 ron prenen ron pem ror _ Notes 1 Not registered as a reserved 2 Use the CY manipulation operation to write data to the CY 3 Only bit be manipulated by an EI DI instruction 4 Bits 3 and 2 can be manipulated bit by bit by a STOP HALT instruction Remarks 1 Interrupt enable flag 2 IRQxxx Interrupt request flag User s Manual U11330EJ2V1UMO00 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Figure 3 7 uPD750108 I O Map 4 5 Number of bits that can be Hardware name symbol up Address FDOH Clock output mode register CLOM PO3 Note 1 PO2 Note 1 PO1 Note 1 Bit manipulation Remarks addressing PM30 Nete 1 Notes 1 Not registered as a reserved word 2 Whether a bit can be read or written depends on the bit User s Manual U11330EJ2V1UM00 Whether this location is read or write accessible de pends on the bit 45 uPD750108 USER S MANUAL 46 Figure 3 7 uPD750108 I O Map 5 5 Number of bits that
191. e 32 768 kHz fcc Net E Selector IO E E 128 7 8125 kHz e si a romthe 7 8125 kHz Selector Frequency divider 9 clock enerator 9 32 768 kHz 4 kHz 2 kHz Clear signal Output buffer gt gt P23 BUZ PORT2 3 Bit 2 of PMGB P23 output Port 2 input latch output mode WM b s ne ons oe nno Bit test instruction Internal bus Note When a frequency divided main system clock is used 32 768 kHz cannot be selected as the source clock Remark The values in parentheses are for fcc 1 MHz and fxr 32 768 kHz 5 4 2 Clock Mode Register The clock mode register WM is an 8 bit register which controls the clock timer Figure 5 27 shows the format of the clock mode register All bits except bit 3 of the clock mode register are controlled by an 8 bit manipulation instruction Bit 3 is for testing the XT1 pin input level The input level of the XT1 pin can be tested by bit test operation No data can be written to this register When the RESET signal is generated all bits except bit 3 of this register are cleared to 0 User s Manual U11330EJ2V1UMO00 109 uPD750108 USER S MANUAL Example Time is set using the subsystem clock 32 768 kHz and buzzer output is enabled CLR1 MBE MOV XA 85H MOV WM XA Sets WM Figure 5 27 Clock Mode Register Format Address 7 0 Symbol e ws ws ror T BUZ output enable disable bit
192. e 5 16 Examples of Oscillator Connections Which Should Be Avoided 1 4 a The wiring is too long Main system clock Subsystem clock uPD750108 uPD750108 CL1 CL2 Vss User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 16 Examples of Oscillator Connections Which Should Be Avoided 2 4 b The signal lines cross Main system clock Subsystem clock uPD750108 PORTn n 0 8 uPD750108 PORTn n 0 8 Vss Vss c A high pulsating current is too close to the signal line e Main system clock Subsystem clock PD750108 PD750108 High current High current User s Manual U11330EJ2V1UM00 93 uPD750108 USER S MANUAL Figure 5 16 Examples of Oscillator Connections Which Should Be Avoided 3 4 d The current flows through the ground line of the oscillator The potential at points A B and C fluctuates e Main system clock Subsystem clock e uPD750108 uPD750108 PORTn n 0 8 High current High current e A signal is taken directly from the resonator Main system clock Subsystem clock uPD750108 uPD750108 94 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 16 Examples of Oscillator Connections Which Should Be
193. e 8 bit accumulator XA register pair A memory bank is specified in the same way as the 4 bit direct addressing This addressing mode can be applied to the MOV XCH IN and OUT instructions Example 1 Eight bit data from port 4 and port 5 is transferred to addresses 20H and 21H DATA EQU 020H CLR1 MBE MBE 0 IN XA PORT4 X lt PORT5 A lt PORTA MOV DATA XA 21H lt X 20H lt A User s Manual U11330EJ2V1UMO00 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP 4 Example 2 Eight bit data is latched into the serial interface shift register SIO and the transfer data is set at the same time SEL MB15 MBS 15 XCH XA SIO XA lt gt SIO 4 bit register indirect addressing rpa In this addressing mode the pointer general register pair specified in the operand of an instruction indirectly specifies a data memory space in units of four bits There are three types of data pointers One is the HL register pair which can specify any area in the data memory space when MB 5 is specified The other two are the DE register pair and DL register pair with which memory bank 0 is always used regardless of how the MBE and MBS are specified More efficient programming is possible by selecting a data pointer according to a data memory bank to be used When the HL register pair is specified the L register can be incremented or decremented by one in the automatic increment or automatic
194. e connected to Vss or Vpp P01 SCK To be connected to Vss or Vpp through PO2 SO SBO preston P03 SI SB1 To be connected to Vsg P10 INTO P12 INT2 To be connected to Vss or Vpp P13 TIO P20 PTOO Input state be connected to Vss or P21 PTO1 Vpp through a resistor P22 PCL Output state To be left open P23 BUZ P30 MDO P33 MD3 Note 1 P40 P43 P50 P53 To be connected to Vss A pull up resistor specified with the mask option must not be connected P60 KRO P63 KR3 P70 KR4 P73 KR7 Input state To be connected to Vgs or Vpp through a resistor Output state To be left open P80 P81 XT1Note 2 To be connected to 55 or XT2Note 2 To be left open IC Vpp Note 1 Notes 1 uPD75P0116 To be always connected directly to Vpp 2 Whenthe subsystem clock is notto be used select 505 0 1 the built in feedback resistor will not be used Users Manual U11330EJ2V1UMO00 21 uPD750108 USER S MANUAL MEMO 22 User s Manual U11330EJ2V1UMO00 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP The 75XL series architecture of the 4PD750108 has the following features Internal RAM of up to 4K words x 4 bits 12 bit address Peripheral hardware expansibility To provide these features the following are used 1 Data memory bank structure 2 General register bank structure 3 Memory mapped This chapter explains these topics 3 1 D
195. e data H Table data L 12 11 87 43 0 peje fal MOVT XA BCDE Function For the uwPD750106 and 0750108 XA BCDE Transfers the low order four bits of the table data eight bits in program memory to the A register and the high order four bits to the X register The table data is addressed by the low order three bits of the B register and the contents of the C D and E registers The table area must have necessary data loaded by an assembler pseudo instruction DB instruction The program counter is not affected by the execution of this instruction Table data H Table data L 12 11 87 43 0 gt fe Remark Function in this section is applicable to the uPD750106 and uPD750108 whose program counters consist of 13 bits each This is also applicable to the uPD750104 whose program counter consists of 12 bits and the uPD75P0116 whose program counter consists of 14 bits however 276 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET 11 4 3 Bit Transfer Instructions a MOV1 CY fmem bit C MOV1 CY pmem L C MOV1 CY H mem bit Function CY lt bit specified in operand Transfers the data memory bit specified by bit manipulation addressing fmem bit pnem L H mem bit to the carry flag CY MOV1 pmem L CY C 3 MOV1 H mem bit CY Function bit specified in operand CY Transfers the carry flag CY bit to the data memory bit specified by bit mani
196. e preserved In addition the states of the output latches of the I O ports and the states of the output buffers are also preserved so that the states of the I O ports are to be processed to minimize the power consumption of the entire system Cautions 1 The STOP mode can be used only for the main system clock Subsystem clock generation cannot be terminated The HALT mode can be used for either the main system clock or the subsystem clock 2 Ifthe STOP mode is set when main system clock fcc is used for clock timer operation the clock stops operating For continued operation the clock must be changed to subsystem clock fxr before the STOP mode is set 3 A lower power consumption and lower voltage operation are enabled by switching standby modes or switching CPU and system clocks However a switching time as described in Section 5 2 3 is required before operation is started with a new clock after the clock is selected with the control register For this reason when the clock switching function is used together with a standby mode the standby mode must be set after a time needed for switching elapses 4 Configure I O ports for minimum power consumption in the stand by mode Be sure to connect signals which are high or low to input ports User s Manual U11330EJ2V1UMO00 219 uPD750108 USER S MANUAL 7 1 SETTING OF STANDBY MODES AND OPERATION STATUS Table 7 1 Operation Statuses in the Standby Mode Instruction for setting STOP mo
197. e result is set in P50 Set the high order 4 bits of the address in H register MOV H 3H MOV1 CY H 0FH 3 AND1 CY PORT3 3 MOV1 PORT5 0 CY P50 CY 2 Skip flags SK2 SK1 SKO The skip flags are used to store skip status and are automatically set or reset when the CPU executes an instruction CY bit 3 at SFH CY CY P33 The user cannot directly manipulate these flags by specifying an operand 3 Interrupt status flag IST1 ISTO The interrupt status flag is a 2 bit flag used to store the status of processing being performed See Table 6 3 for details User s Manual U11330EJ2V1UM00 65 uPD750108 USER S MANUAL Table 4 5 Information Indicated by the Interrupt Status Flag IST1 ISTO Status of processing Processing and interrupt control being performed 0 0 Status 0 Normal program processing is being performed Any interrupts are acceptable 0 1 Status 1 A lower or higher priority interrupt is being serviced Higher priority interrupts are acceptable 1 0 Status 2 A higher priority interrupt is being serviced No interrupts are acceptable 1 1 Not to be set The interrupt priority control circuit see Figure 6 1 checks this flag to control multiple interrupts The contents of the IST1 and ISTO are saved as part of the PSW to stack memory if an interrupt is accepted then are automatically set to a one step higher status The RETI instruction restores the contents present
198. e written to this area beforehand When a 1 byte instruction or 2 byte instruction is written its mnemonic can be used directly For a 3 byte call instruction or 3 byte branch instruction an assembler pseudo instruction TCALL TBR is used Only an even address can be specified as taddr 300 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET Caution All 2 byte instructions except the BRCB instruction and CALLF instruction set in the reference table must be 2 machine cycle instructions Pairs of 1 byte instructions can be set as indicated in the table below First byte instruction Second byte instruction INCSL MOV A HL DECS L MOV HL A INCSH XCH A HL DECS H INCSHL INCSE MOV A QDE DECS E INCSD XCH A DE DECS D INCSDE MOV A DL INCSL L DECS L XCH A DL INCS D L DECS D The PC is not incremented during execution of a GETI instruction so that after a reference instruction is executed execution is resumed starting at the address immediately after the GETI instruction If the instruction immediately preceding a GETI instruction has the skip function the GETI instruction is skipped as with other 1 byte instructions If an instruction referenced with a GETI instruction has the skip function the instruction immediately following the GETI instruction is skipped If a GETI instruction references an instruction having a string effect the following processing is performed e Ifthe ins
199. ed data by hardware This function enables more efficient input output port utilization as in the case of the two wire serial I O mode In addition this function can simplify the serial interface control portion of an application program User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 38 Example of the SBI System Configuration Master CPU Serial clock Slave CPU x o SCK Address 1 580 581 Address IN es i Command PERPE d gt Data Slave SCK N Address N gt 5 0 581 5 6 2 Configuration of Serial Interface Figure 5 39 shows the block diagram of the serial interface User s Manual U11330EJ2V1UMO00 127 uPD750108 USER S MANUAL MOS E 0170 90 99 50 299 gt 2159 Jojoejes 2 jenas e E xoojo 4Jejunoo uoje 1ndino lOd A MOS LOd 08S OS c0d LaS IS E0d 15908 enas ISOLNI no sng nd no JO eDpe wouxoe oejeg Asng 1 Q 10 i oejes 5i peus
200. edge of an INT1 P11 pin input signal The detection edge is specified by the INT1 edge detection mode register IM1 IRQCSI Set by a serial data transfer completion signal for the serial interface IRQTO Set by a match signal from timer event counter 0 IRQT1 Set by a match signal from the timer counter 2 Interrupt priority specification register IPS The interrupt priority specification register selects an interrupt with a higher priority from multiple interrupts using the low order three bits Bit 3 interrupt master enable flag IME specifies whether to disable all interrupts The IPS is set using a 4 bit memory manipulation instruction Bit 3 is set by an El instruction and reset by a Dl instruction When changing the low order three bits of the IPS interrupts must be disabled IME 0 beforehand Example DI Disable interrupts CLR1 MBE MOV A 1011B MOV IPS A Assign a higher priority to INT1 then enable interrupts A RESET signal clears all bits to 0 Caution Disable interrupts before setting the IPS 192 User s Manual U11330EJ2V1UMO00 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Figure 6 3 Interrupt Priority Specification Register Address Symbol 0 FB2H IPS High order interrupt selection All low order interrupt VRQ1 The listed vectored INTBT INT4 interrupts are treated as high order interrupts VRQ2 INTO VRQ3 INT1 VRQ4 INTCSI VRQ5 INTTO VRQ6 INTT1 Not t
201. egister SBIC 134 5 42 Peripheral Hardware of Shift Register 137 5 43 Example of Three Wire Serial I O System Configuration 140 5 44 Timing of Three Wire Serial Mode sse 143 User s Manual U11330EJ2V1UMO00 LIST OF FIGURES 3 4 Figure No Title Page 5 45 Operations of RELT and CMDT sssssssssssseseee 144 5 46 Transfer Bit Switching Circuit essen nnne nennen 144 5 47 Example of Two Wire Serial I O System Configuration 147 5 48 Timing of Two Wire Serial l O Mode 0 cccccceeceeceeeeeeeeeeeeeeeeaeeeseeeeeesaeeeseaeeeseeeeeenaeeteaes 150 5 49 Operations of RELT and CMDT ssssssssssssseseeee entrent nennen 151 5 50 Example of SBI System Configuration sse 153 5 51 TIMINQLOR SBI Transfer ieu eo ref te Het eet age denne a 155 5 52 Bus Release Signal eene tenen nnns nre nnns nnne 156 5 53 Command Signal pee Ec n ep e Lo eit te e aged 156 5 54 E EET EM 156 5 55 Slave Selection Using an Address ennt 157 5 56 COMM AN E 157 5 57 157 5 58 Acknowledge Signal ce cu lc d Rd ac tds 158 5 59 Busy and Ready
202. egister SIO Undefined Operation mode register CSIM 0 SBI control register SBIC 0 Slave address register SVA User s Manual U11330EJ2V1UMO00 Undefined CHAPTER 8 RESET FUNCTION Table 8 1 Statuses of the Hardware after a Reset 2 2 Generation of a RESET Generation of a RESET Hardware signal in a standby mode signal during operation Clock Processor clock control register generator PCC clock System clock control register output SCC circuit Clock output mode register CLOM Sub oscillator control register SOS Interrupt Interrupt request flag IRQxxx Interrupt enable flag IExxx Priority selection register IPS INTO INT1 and INT2 mode registers IMO IM1 IM2 Digital Output buffer ports Output latch I O mode registers PMGA PMGB PMGC Pull up resistor specification register POGA POGB Bit sequential buffers BSBO to BSB3 Undefined User s Manual U11330EJ2V1UMO00 231 uPD750108 USER S MANUAL MEMO 232 User s Manual U11330EJ2V1UMO00 CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY PROM The program memory the uPD75P0116 consists of a one time PROM 16384 x 8 bits Writing to and verifying the contents of the one time PROM is accomplished by using the pins shown in the table below Note that address inputs are not used instead the address is updated using the clock input from
203. er 1 8 bit timer event counter 1 Basic interval timer Basic interval timer watchdog timer 1 watchdog timer 1 Clock timer 1 Clock timer 1 Serial interface 3 modes supported Three wire serial mode First transferred bit switchable between LSB and MSB Two wire serial I O mode SBI mode Clock output PCL 524 262 65 5 kHz 6 125 62 5 15 6 kHz when the main system when the main system clock operates at 1 MHz clock operates at 4 19 MHz 750 375 93 8 kHz 250 125 31 3 kHz when the main system when the main system clock operates at 2 MHz clock operates at 6 0 MHz Buzzer output BUZ 2 4 32 kHz when the 2 4 32 kHz when the subsystem clock main system clock operates at 32 768 kHz operates at 4 19 MHz 0 488 0 977 7 813 kHz when the main or the subsystem clock system clock operates at 1 MHz operates at 32 768 kHz 0 977 1 953 15 625 kHz when the main 2 93 5 86 46 9 kHz system clock operates at 2 MHz when the main system clock operates at 6 0 MHz Vectored interrupt External 3 internal 4 Test input External 1 internal 1 Supply voltage Vpp 2 2 to 5 5 V Vpp 1 8 to 5 5 V Operating ambient temperature TA 40 to 85 C Package 42 pin plastic shrink DIP 600 mil 44 pin plastic QFP 10 x 10 mm 304 User s Manual U11330EJ2V1UMO00 APPENDIX B DEVELOPMENT TOOLS The following development tools are pr
204. er the release of standby mode Operable on low voltage Vpp 1 8 to 5 5 V Switchable instruction execution times useful for power saving 4 8 16 64 us at 1 MHz 2 4 8 32 us at 2 MHz 122 us at 32 768 kHz Enhanced timers 4 channels Easy replacement The functions and instructions of the 4PD750008 are taken over The uPD75P0116 having the electrically programmable one time PROM is pin compatible with the uPD750104 uPD750106 and uPD750108 It is suitable for small scale production or prototype production in system development Applications Camera Meter Automobile Pager Remark This manual will explain only the uPD750108 when the uPD750108 uPD750104 uPD750106 and uPD75P01 16 are functionally the same Users ofthe uPD750104 uPD750106 or wPD75P0116 should read uPD750108 as referring to uPD750104 uPD750106 or uPD75P0116 User s Manual U11330EJ2V1UM00 1 uPD750108 USER S MANUAL 1 1 Item Instruction execution time FUNCTION OVERVIEW Function 4 8 16 64 us when the main system clock operates at 1 MHz 2 4 8 32 us when the main system clock operates at 2 MHz 122 us when the subsystem clock operates at 32 768 kHz 2 Internal memory ROM 4096 x 8 bits uPD750104 6144 x 8 bits 750106 8192 x 8 bits uPD750108 16384 x 8 bits uPD75P0116 RAM 512 x 4 bits General register When operating in 4 bits 8 x 4 banks When operating
205. er watchdog timer interrupt request flag IRQBT is also cleared to start the basic interval timer watchdog timer A RESET signal clears the interval timer to 0 and the longest interrupt request signal generation interval time is set Figure 5 24 Format of the Basic Interval Timer Mode Register Address 3 2 1 0 Symbol F85H BTM3 BTM2 BTM1 BTMO BTM fcc 2 MHz Input clock specification Interrupt interval time fcc 2 488 Hz 2201 524 ms fcc 29 3 91 kHz 2 7 fco 65 5 ms fcc 2 15 6 kHz 21 1 16 4 ms Bu foc 2 62 5 kHz 2 3 fcc 4 10 ms Other than above wem to be set fcc 1 MHz fcc 2 244 Hz 2 tcc 1 05 s 217 ffcc 131 ms 2 5 fcc 32 8 ms rere foc 2 31 3 kHz 2 3 8 19 ms Other than above wee to be set Basic interval timer watchdog timer start control bit When 1 is written to this bit the basic interval timer watchdog timer operation starts the counter and the interrupt request flag are cleared When the operation starts this bit is automatically reset to 0 104 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5 3 3 Watchdog Timer Enable Flag WDTM WDTM when set is a flag for enabling the generation of the reset signal when the basic interval timer overflows WDTM is set by a bit manipulation instruction It cannot be cleared by an instruction Example Set the watchdog timer function SEL MB15 or CLR1 MB
206. es The incorporation of these circuits software and information in the design of the customer s equipment shall be done under the full responsibility of the customer NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits software and information While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices the possibility of defects cannot be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customers must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application The recommended applications of a device depend on its quality grade as indicated below Customers must check the quality grade of each device before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains shi
207. f 14 bits addr 0000H to 3FFFH Cu BRA addri Function For the uPD750108 PC42 9 lt addr1 BR laddr Function For the 1 0750108 PC42 0 lt addr addr 0000H 1FFFH Transfers the immediate data addr to the program counter PC then branches to the location addressed by the program counter CD BR addr Function For the uPD750108 PC42 0 lt addr addr PC 15 to 1 PC 2 to PC 16 Relative branch instruction with branch ranges of 15 to 1 and 2 to 16 from the current address The instruction is not affected by page or block boundaries Cu BR addr1 Function For the 1 0750108 PC 5 9 lt addr1 addr PC 15 to 1 PC 2 to PC 16 Relative branch instruction with branch ranges of 15 to 1 and 2 to 16 from the current address The instruction is not affected by page or block boundaries User s Manual U11330EJ2V1UMO00 289 uPD750108 USER S MANUAL Remark Function in this section is applicable to the uPD750108 whose program counter consists of 13 bits addr OOOOH to 1FFFH However this is also applicable to the uPD750104 whose program counter consists of 12 bits addr OOOOH to OFFFH the uPD750106 whose program counter consists of 13 bits addr 0000H to 17FFH and the uPD75P01 16 whose program counter consists of 14 bits addr 0000H to 3FFFH D BRCB caddr Function For the uPD750108 PC42 9 lt 12 caddry4 9 caddr n000H nFFFH
208. f 6 MD1 P31 ee e Sl MD2 P32 o MD3 P33 User s Manual U11330EJ2V1UMO00 235 uPD750108 USER S MANUAL 9 3 READING THE PROGRAM MEMORY The procedure for reading the contents of program memory is described below The read is performed in the verify mode 1 2 3 4 5 6 Pull low all unused pins to Vss by means of resistors Bring CL1 to low level Apply 5 V to Vpp and Vpp Wait 10 us Select program memory address clear mode Apply 6 V to Vpp and 12 5 V to Vpp Select verify mode Data is output sequentially one address at a time for each cycle of four clock pulses appearing on the CL1 pin 7 Select program memory address clear mode 8 Apply 5 V to Vpp and to Vpp 9 Turn the power off 1 2 3 4 5 6 The timing for steps 2 to 7 is shown below D0 P40 D3 P43 MDO P30 MD1 P31 _ MD2 P32 MD3 P33 236 User s Manual U11330EJ2V1UMO00 CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY PROM 9 4 SCREENING OF ONE TIME PROM Because of its structure it is difficult for NEC to completely test the one time PROM product before shipment It is therefore recommended that screening be performed to verify the PROM contents after the necessary data has been written to the PROM and the product has been stored under the following conditions Storage Temperature Storage Time 125 C 24 hours User s Manual U11330EJ2V1UMO00 237
209. f the X register to the output latch of the next port 298 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET Caution Before this instruction can be executed MBE 0 or MBE 1 MBS 15 must be set Only 4 or 6 can be specified as n 11 4 14 CPU Control Instructions D Function PCC 2 1 Sets the HALT mode This instruction is used to set bit 2 of the processor clock control register Caution The instruction immediately following a HALT instruction must be a NOP instruction C 2 stop Function PCC 3 1 Sets the STOP mode This instruction is used to set bit 3 of the processor clock control register Caution The instruction immediately following a STOP instruction must be a NOP instruction gt Nop Function Uses one machine cycle without performing an action 11 4 15 Special Instructions SELRBn Function RBS lt n n Nj 9 0 3 Sets the 2 bit immediate data n in the register bank select register RBS C D SEL Function MBS lt n n 0 1 15 Transfers the 4 bit immediate data n to the memory bank select register MBS Only 0 1 or 15 can be specified as n User s Manual U11330EJ2V1UMO00 299 uPD750108 USER S MANUAL GETI taddr Function taddr T5 9 20H 7FH Remark For the uPD750108 Mk mode When a table defined by the TBR instruction is referenced PC12 9 taddr 4 9 taddr 1 When table defined by the TCALL instruction is re
210. fer 2 When data is received the N ch transistor must be turned off so FFH must be written to SIO beforehand When eight bits have been transferred serial transfer automatically terminates setting the interrupt request flag IRQCSI User s Manual U11330EJ2V1UMO00 151 uPD750108 USER S MANUAL 6 Error detection In the two wire serial I O mode the state of serial bus 580 581 being used for communication is loaded into the shift register SIO of the transmitting device So a transmission error can be detected by the methods described below a Comparing SIO data before start of transmission with SIO data after start of transmission With this method the occurrence of a transmission error is assumed when two SIO values disagree with each other b Using the slave address register SVA Transmit data is set in SVA as well before the data is transmitted On completion of transmission the COI bit match signal from the address comparator of serial operation mode register CSIM is tested If the result is 1 the transmission is regarded as successful If the result is 0 the occurrence of a transmission error is assumed 7 Application of two wire serial mode A serial bus is configured and multiple devices are connected to it Example A system is configured with a uLPD750108 as the master to which a uPD75104 uPD754024A and uPD7225G are connected as slaves uPD750108 master Port SCK SO SBO
211. ferenced SP 1 lt PCz 4 SP 2 PC3 9 SP 3 MBE 0 PCy SP 4 PC41 8 PC12 9 lt taddr 4 9 taddr 1 SP SP 4 When a table defined by an instruction other than the TBR or TCALL instruction is referenced An instruction using taddr taddr 1 as its operation code is executed Mk Il mode When a table defined by the TBR instruction is referenced PC12 9 taddr 4 9 taddr 1 When table defined by the TCALL instruction is referenced SP 2 x x MBE RBE SP 3 lt 7 4 SP 4 PC3 9 SP 5 lt 0 0 0 PCy2 5 6 lt PC41 g PC12 9 taddr 4 9 taddr 1 SP SP 6 When a table defined by an instruction other than the TBR or TCALL instruction is referenced An instruction using taddr taddr 1 as its operation code is executed Function in this section is applicable to the uPD750108 whose program counter consists of 13 bits addr OOOOH to 1FFFH However this is also applicable to the uPD750104 whose program counter consists of 12 bits addr 0000H to OFFFH the uPD750106 whose program counter consists of 13 bits addr OOOOH to 17FFH and the uwPD75P0116 whose program counter consists of 14 bits addr 0000H to 3FFFH The 2 byte data at the program memory addresses specified by taddr and taddr 1 is referenced and executed as an instruction Addresses 0020H to 007FH are used as a reference table area Data must b
212. fferences To check the functions of an instruction in detail when the reader knows its mnemonics See the instruction index in Appendix D To check the functions of specific internal circuits etc See Appendix E e To understand the overall functions of the uPD750104 uPD750106 uPD750108 and uPD75P0116 Read through all chapters sequentially User s Manual U11330EJ2V1UMO00 Notation Data bit significance Active low Memory map address Note Caution Remark Important and emphasized matter Numeric value Higher order bits on the left side Lower order bits on the right side Xxx Pin and signal names are overscored Low order address on the upper side High order address on the lower side Explanation of an indicated part of text Information requesting the user s special attention Supplementary information Described in bold face Binary XXXX or xxxxB Decimal XXXX Hexadecimal XxxxH User s Manual U11330EJ2V1UMOO Some documents are preliminary editions but they are not so specified in the tables below Related documents Documents related to devices Document number Document name English Japanese 0750104 750106 750108 750104 A 750106 A U12301J U12301E 750108 A Data Sheet uPD75P0116 Data Sheet uPD750108 User s Manual uPD750008 750108 Instruction List 75XL Series Selection Guide U12603J U12
213. fies the master of the busy state by changing SBO or SB1 from high to low The busy signal is output following the acknowledge signal output by the master or a slave The busy signal is set and released in phase with the falling edge of SCK The master automatically terminates output of serial clock SCK when the busy signal is released The master can transfer the next data when the busy signal is released and a slave enters the state in which the ready signal is to be output 3 Register setting To set the SBI mode manipulate the following two registers Serial operation mode register CSIM Serial bus interface control register SBIC a Serial operation mode register CSIM To use the SBI mode set CSIM as shown below For details on CSIM format see 1 in Section 5 6 3 CSIM is manipulated using an 8 bit manipulation instruction Bits 7 6 and 5 of CSIM can be manipulated bit by bit When the RESET signal is input CSIM is set to 00H In the figure below hatched portions indicate the bits used in the SBI mode 7 6 5 4 3 2 1 0 a i um Serial clock selection bit W Serial interface operation mode selection bit W Wake up function specification bit W Match signal from address comparator R Serial interface operation enable disable specification bit W Remark HR Read only W Write only User s Manual U11330EJ2V1UMO00 159 uPD750108 USER S MANUAL Serial inte
214. g manipulated manipulated fmem bit RBE MBE IST1 ISTO SCC FBOH FBFH IExxx IRQxxx PORTO 8 FFOH FFFH pmem L 8580 3 PORTO 8 FCOH FFFH bit All peripheral hardware units that can be All bits of memory bank specified by MB manipulated bitwise that can be manipulated bitwise Remarks 1 xxx 0 1 2 4 BT TO T1 W CSI 2 MB MBE MBS 11 1 3 String Effect Instructions With the uPD750108 two types of string effect instructions are available a MOV A n4 or MOV XA n8 b MOV HL n8 String effect means the locating of these two types of instructions at contiguous addresses Example A0 MOV A 0 A1 MOV A 1 XA7 MOV XA 07 When string effect instructions are arranged as in this example if execution starts at address 0 the following two instructions are replaced with an NOP instruction If execution starts at address A1 the following One instruction is replaced with an NOP instruction That is only the instruction first executed is valid and any following instructions are processed as an NOP instruction By using string effect instructions a constant can be set in an accumulator the A register or the XA register pair or data pointer the HL register pair more efficiently 242 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET 11 1 4 Number System Conversion Instructions An application may need to convert the result of a 4 bit data addition or subtraction performed
215. g using an instruction has the same effect as the occurrence of an interrupt Debug operation for irregular interrupts or concurrently occurring interrupts can be performed more efficiently by setting the interrupt request flags using an instruction 6 9 INTERRUPT APPLICATIONS To use the interrupt function a main program must a b c d Set a desired interrupt enable flag using the El IExxx instruction Select an active edge when INTO or INT1 is used set IMO or IM1 To use nesting of an interrupt with the higher priority set IPS IME can be set at the same time Set the interrupt master enable flag IME using the El instruction a b c d In the interrupt routine MBE and RBE are set by the vector table However when the interrupt specified as having the higher priority is processed the register bank must be saved and set To return from the interrupt routine use the RETI instruction 206 User s Manual U11330EJ2V1UMO00 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 1 Interrupt enable disable lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt Main program gt 1 Reset gt I 2 EI IEO Interrupt disabled EI IETO lt gt El 1 INTO and INTTO enabled lt 4 gt DI IEO y INTTO enabled lt 5 gt DI t Interrupt disabled A RESET signal disables all interrupts Interrupt enable flags are set by the El IExxx instruction At this stage all interrupts are disabled The interrupt master e
216. gs are set when this request flag is tested or cleared the interrupt request remains even if one of the request flags is cleared If this interrupt is selected as having the higher priority nesting processing is started by the remaining interrupt request Consequently the interrupt request not tested is processed first If the selected interrupt has the lower priority the remaining interrupt is kept pending and therefore the interrupt request tested is processed first Therefore an interrupt sharing a vector address with another interrupt is identified differently depending whether it has the higher priority as shown in Table 6 4 Table 6 4 Identifying Interrupt Sharing Vector Table Address With higher priority Interrupt is disabled and interrupt request flag of interrupt that takes precedence is tested With lower priority Interrupt request flag of interrupt that takes precedence is tested 202 User s Manual U11330EJ2V1UMO00 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Examples 1 To use both VSUBBT 2 To use both VSUBBT INTBT and INT4 as having the higher priority and give priority to INT4 DI SKTCLR IRQ4 IRQ4 21 BR _ VSUBBT Processing routine of INT4 RETI CLR1 IRQBT Processing routine of INTBT EI RETI INTBT and INT4 as having the lower priority and give priority to INT4 SKTCLR IRQ4 IRQ4 1 BR VSUBBT Processing routine of INT4 RETI CLR1 IRQBT Processing routine of INTBT
217. h as Boolean operations and bit transfer for each bit in the data memory space The 1 bit direct addressing mode can be applied only to the set reset and test instructions On the other hand the bit manipulation addressing enables a wide variety of bit manipulations such as Boolean operations using the AND1 OR1 and XOR1 instructions bit transfers using the MOV1 instruction and test and reset operations using the SKTCLR instruction There are three types of bit manipulation addressing The user can choose from these options according to the data memory address used User s Manual U11330EJ2V1UM00 31 uPD750108 USER S MANUAL 32 a Specific address bit direct addressing fmem bit In this addressing mode peripheral equipment that frequently performs bit manipulations involving for example I O ports and interrupt flags can be processed at all times regardless of memory bank setting Accordingly the data memory addresses that allow this addressing mode to be used are FFOH to FFFH where I O ports are mapped and FBOH to FBFH where interrupt related hardware is mapped Hardware mapped to these data memory areas can freely perform bit manipulations in the direct addressing mode at any time regardless of MBS and MBE setting Examples 1 Value input to P02 is inverted and the result is output on P33 MOV1 CY 2 NOT1 CY MOV1 PORT3 3 CY 2 The timer 0 interrupt request flag IRQTO is tested The request flag if set is cle
218. he 8 low order bits of the PC changed User s Manual U11330EJ2V1UM00 53 uPD750108 USER S MANUAL Figure 4 6 Program Memory in uPD75P0116 7 6 0 0000H Internal reset start address high order 6 bits Internal reset start address low order 8 bits 0002H INTBT INT4 start address high order 6 bits INTBT INT4 start address low order 8 bits Entry address 0004H INTO start address high order 6 bits specified in CALLF INTO start address low order 8 bits faddr 7 instruc Branch 0006H INT1 start address high order 6 bits tion address 3 specified INT1 start address low order 8 bits in BRCB 0008H INTCSI start address high order 6 bits und INTCSI start address low order 8 bits tgn 000AH INTTO start address high order 6 bits Branch address specified in INTTO start address low order 8 bits BR addr BR BCDE 000CH INTT1 start address high order 6 bits BR BCXA BRA addr1 Nee INTT1 start address low order 8 bits CALL adar or CALLA addr1 Note Branch call 0020H address by GETI instruction reference table 007FH 0080H Relative branch address specified in BR addr O7EFH nmm ten eee EE meets instruction 0800H 715 to 1 2 to 16 a Y 1000H A Branch address specified in BRCB Icaddr instruction SE eR ORE RCE A Y 1FFFH 1 Branch address specified in BRCB Icaddr inst
219. he A register match the data at the data memory location addressed by the HL register pair 284 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET d SKE XA HL Function Skip if A HL and X HL 1 Skips the immediately following instruction ifthe contents ofthe A register match the data atthe data memory location addressed by the HL register pair and the contents of the X register match the data atthe next address in data memory However if the contents of the L register are odd numbered an address with the lowest order bit ignored is specified gt SKE A reg Function Skip if A reg Skips the immediately following instruction if the contents of the A register match the contents of register reg X A H L D E B C D SKE XA rp Function Skip if XA rp Skips the immediately following instruction if the contents of the XA register pair match the contents of register pair rp XA HL DE BC XA HL DE BC 11 4 8 Carry Flag Manipulation Instructions SET1 Function lt 1 Sets the carry flag C D cri cy Function CY lt 0 Clears the carry flag Cy SKT CY Function Skip if CY 1 Skips the immediately following instruction if the carry flag is set to 1 User s Manual U11330EJ2V1UMO00 285 uPD750108 USER S MANUAL NOT1 Function CY CY Inverts the carry flag If it is O it is set to 1 or vice versa 11 4 9 Memory
220. he immediately following instruction When HL automatic decrement is specified for the register pair automatically decrements the contents of the L register by one after the data exchange and continues the operation until the contents are set to FH Then skips the immediately following instruction Example The data at addresses 20H 2FH are exchanged with the data at addresses 30H 3FH SEL MOV _ D 2 MOV HL E30H LOOP A HL lt gt 3 A DL lt gt 2 A HL lt gt 3 BR LOOP 272 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET C3 XCH XA GHL Function A lt gt HL X lt gt HL 1 Exchanges the contents of the A register with the data at the data memory location addressed by the HL register pair and exchanges the contents of the X register with the data at the next memory address However if the contents of the L register are odd numbered an address with the low order bit ignored is specified Function mem mem 07 0 00H FEH Exchanges the contents of the A register with the data at the data memory location addressed by the 8 bit immediate data mem XCH XA mem Function A lt gt mem X lt gt mem 1 05 0 OOH FEH Exchanges the contents of the A register with the data at the data memory location addressed by the 8 bit immediate data mem and exchanges the contents of the X register 1 wi
221. he jump destination address is loaded When a return instruction RET RETS RETI is executed the contents of the stack memory are set in the program counter When the RESET signal is issued the program counter is initialized to the contents of the program memory at addresses 000H and 001H The program can be started from any address according to the contents uPD750104 PC44 POg lt 000H 3 9 7 lt 001H 7 9 uPD750106 and uPD7501068 PC42 POg lt OOOH 4 9 7 lt 001H 7 9 uPD75P0116 PC43 POg lt OOOH 5 9 7 lt 001H 7 9 User s Manual U11330EJ2V1UMO00 49 uPD750108 USER S MANUAL 4 3 PROGRAM MEMORY ROM 4096 WORDS x 8 BITS uPD750104 MASKED ROM 6144 WORDS x 8 BITS uPD750106 MASKED ROM 8192 WORDS x 8 BITS uPD750108 MASKED ROM 16384 WORDS x 8 BITS uPD75P0116 ONE TIME PROM The program memory is used for storing programs an interrupt vector table GETI instruction reference table table data and so forth The wPD750104 uPD750106 and uPD750108 are provided with a mask programmable ROM as the program memory and the uPD75P0116 is provided with a one time PROM Figures 4 3 to 4 6 show the program memory maps Program memory is addressed by the program counter Table data can be referenced using the table reference instruction MOVT Figures 4 3 to 4 6 also show the allowable branch address ranges for the branch instructions and subroutine call instructions
222. his signal is called the command signal which is output by the master Figure 5 53 Command Signal SCK w Slaves contain hardware to detect the command signal c Address An address is 8 bit data and is output by the master to connected slaves to select a particular slave Figure 5 54 Address SCK 580 581 Bus release signal Command signal The 8 bit data following the bus release signal or command signal is defined as an address A slave detects the condition for the addresses by hardware and checks whether the 8 bit data matches the number assigned to the slave slave address If the 8 bit data matches the slave address that slave is selected The selected slave continues to communicate with the master until disconnection is directed by the master 156 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 55 Slave Selection Using an Address E Transmits address for slave 2 Slave 2 Selected gt Slave 3 Not selected lt gt Slave 4 Not selected d Command and data The master sends commands to the slave selected by sending an address The master also transfers data to or from the slave Figure 5 56 Command SCK 1 l2 l3 4 5 le 7 8 SBO SB1 7 XC6 5 A AC2 X C1 CO Command signal Command Figure 5 57 Data SCK 1 2 13 14 5 le 7 l8 SBO SB1 X D7 D6 X D5 A D4 X
223. hree lines Serial clock SCK serial output SO and serial input SI The three wire serial I O mode allows full duplex transmission so data transfer be performed at higher speed The user can choose 8 bit data transfer starting with the MSB or LSB so devices starting with either the MSB or LSB can be connected The three wire serial I O mode enables connections to be made with the 75XL series 78K series and many other types of peripheral I O devices Two wire serial mode In this mode 8 bit data is transferred through two lines Serial clock SCK and serial data bus SBO or SB1 By controlling output levels on the two lines by software communication with multiple devices is enabled The output levels of SCK and SBO or SB1 can be controlled by software so the user can match an arbitrary transfer format This means that a line that has been required for handshaking to connect multiple lines can be eliminated for more efficient input output port utilization Serial bus interface SBI mode In this mode communication with multiple devices can be performed using two lines Serial clock SCK and serial data bus SBO or SB1 This mode conforms to the NEC serial bus format In this mode the transmitter can output on the serial data bus an address for selecting a device subject to serial communication commands directed to the remote device and data The receiver can identify an address commands and data from receiv
224. ial Operation Mode Register CSIM 1 4 Address Symbol 7 6 5 4 3 2 1 0 Serial clock selection bit W Serial interface operation mode selection bit W Wake up function specification bit W Signal from address comparator R Serial interface operation enable disable specification bit W Remarks 1 R Read only 2 W Write only 130 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 40 Format of Serial Operation Mode Register CSIM 2 4 Serial interface operation enable disable specification bit W Shift register Serial clock IRQCSI SO SBO and operation counter flag SI SB1 pins Shift operation Cleared Held Used only for port 0 disabled Shift operation Count operation Can be set Used in each mode as well enabled as for port 0 Signal from address comparator R CO Note Condition for being cleared COI 0 Condition for being set COI 1 When the data in the slave address When the data in the slave address register register SVA does not match the data SVA matches the data in the shift in the shift register register Note COI can be read only before serial transfer is started or after serial transfer is completed An undefined value may result during transfer COI data written by an 8 bit manipulation instruction is ignored Wake up function specification bit W Sets IRQCSI each time serial transfer is completed
225. ication MBE 1 a memory bank is specified with the 4 bit memory bank select register MBS 0 1 15 If the MBE disables bank specification MBE 0 memory bank 0 or 15 is automatically selected according to the addressing mode Locations a bank is addressed by 8 bit immediate data or a register pair For details on the selection of a memory bank and addressing see Section 3 1 For how to use the particular data memory areas see the following sections and chapter General register area Section 4 5 Stack memory area Section 4 7 Peripheral hardware area Chapter 5 Figure 4 7 Data Memory Map Data memory Memory bank A A Area for 000H A general register O1FH 020H 0 Data area Stack static RAM areaNote 51 2x 4 OFFH 100H 1 Y Y 1FFH Y F80H Peripheral hardware area 15 FFFH Note Memory bank 0 or 1 can be selected as the stack area 56 User s Manual U11330EJ2V1UM00 CHAPTER 4 INTERNAL CPU FUNCTIONS Data memory is undefined when itis reset For this reason it is to be initialized to zero RAM clear usually at the start of a program Remember to perform this initialization Otherwise unexpected bugs may occur Example The following program clears data at addresses 000H to 1FFH in RAM SET1 MBE SEL MBO MOV XA 00H MOV HL 04H MOV HL A Clear 04H to FFHNote INCS L Lee 4 BR RAMCO INCS H H lt H 1 BR RAMCO SEL MB1 RAMC1 MOV HL A Clear 100
226. ics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics 434 NE SAS User s Manual uPD750108 4 bit Single Chip Microcontrollers uPD750104 uPD750106 uPD750108 uPD75P0116 Document No U11330EJ2V1UMO00 2nd edition Date Published December 1999 J CP K O NEC Corporation 1996 Printed in Japan MEMO User s Manual U11330EJ2V1UMOO NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar preca
227. iding up to eight 8 bit registers The XA register pair functions as an 8 bit accumulator which performs transfers arithmetic logical operations comparisons and increments decrements of 8 bit data The other register pairs perform transfers arithmetic logical operations comparisons and increments decrements with the accumulator The HL register pair functions mainly as a data pointer and the DE and DL register pairs function as an auxiliary data pointer Examples 1 INCS HL HL lt HL 1 skip at HL 00H ADDS XA BC XA lt XA BC skip at carry SUBC DE XA DE lt DE XA CY MOV XA XA lt XA MOVT XA PCDE XA lt PC12 g DE ROM reference table SKE XA BC Skip if XA BC 2 The value of the count register TO for timer event counter 0 is tested until it becomes greater than the value of the BC register pair CLR1 MBE MOV XA TO Read count register SUBS XA BC XA gt BC BR YES YES BR NO NO User s Manual U11330EJ2V1UMO00 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Figure 3 5 General Register Configuration 4 Bit Processing User s Manual U11330EJ2V1UM00 Register bank 0 RBE RBS 0 Register bank 1 RBE RBS 1 Register bank 2 RBE RBS 2 Register bank 3 RBE RBS 3 39 uPD750108 USER S MANUAL 40 Figure 3 6 General Register Configuration 8 Bit Processing
228. illator Built in feedback resistor is used Built in feedback resistor is not used Cut flag for the sub oscillator current 0 Drive current is high 1 8 V 1 Drive current is low 2 7 V lt Bits 2 and 3 of SOS must be set to 0 Remark If the subsystem clock is not required the XT1 and XT2 pins and SOS register must be treated as follows XT1 Connected to Vss or XT2 Open SOS 00x1B x Don t care User s Manual U11330EJ2V1UM00 97 uPD750108 USER S MANUAL 5 2 3 System Clock and CPU Clock Setting 1 Time required to change the system clock and CPU clock The system clock and CPU clock can be changed by using the least significant bit of the SCC and the low order two bits of the PCC This switching is not performed immediately after the contents of the registers are rewritten but the system operates with the previous clock for some machine cycles Accordingly after this time period the STOP instruction must be executed to terminate main system clock generation Table 5 5 Maximum Time Required to Change the System Clock and CPU Clock Setting before switching Setting after switching SCCO PCC1 PCCO PCCO SCCO0 PCC1 PCCO SCCO 1 1 machine cycle 0 1 0 1 machine cycle 0 1 machine cycle fcc 64fxr machine cycles 1 machine cycle 4 machine cycles 4 machine cycles 4 machine cycles fcc
229. immediately after the STOP instruction is executed then returns to the operation mode after the specified wait timeNote has elapsed Note Either of the following can be selected by using a mask option e 29 fcc 256 us at 2 MHz 512 us at 1 MHz No wait The uPD75P0116 however does not have a mask option Its wait time is fixed to 29 fcc 7 2 RELEASE OF THE STANDBY MODES The STOP mode and HALT mode are released by a RESET signal or the generation of an interrupt request signal that is enabled with the interrupt enable flag Figure 7 1 shows how the STOP and HALT modes are released Figure 7 1 Standby Mode Release Operation 1 2 a Release of the STOP mode by RESET signal STOP instruction Wait Note 1 E DET RESET signal Operating Operating mode STOP mode HALT mode mode J t 3 Oscillation No oscillation Oscillation Clock gt gt a b Release of the STOP mode by the occurrence of an interrupt Wait Note 2 lt gt STOP instruction Standby Y release l signal Deen Operating Operating mode STOP mode HALT mode mode 3 4 31 4 Oscillation No oscillation Oscillation Clock at User s Manual U11330EJ2V1UMO00 221 uPD750108 USER S MANUAL Notes 1 56 fcc 28 us at 2 MHz 56 us at 1 MHz 2 Either of the following can be selected by using a mask option 29 fcc 256 us at 2 MHz 512 us at 1 MHz No wait The uPD75P0116 however does
230. in 8 bits 4 x 4 banks I O port 34 8 CMOS input pins Can incorporate 25 pull up resistors 18 CMOS pins that are specified with the software Four pins can directly drive the LED 8 N ch open drain I O pins Can withstand 13 V Eight pins can directly drive Can incorporate pull up resistors that the LED are specified with the mask option Note Timer 4 8 bit timer event counter 1 channel 8 bit timer counter 1 channel clock timer output function is provided Basic interval timer watchdog timer 1 channel Clock timer 1 channel Serial interface Three wire serial mode switchable between the start LSB and the start MSB e Two wire serial I O mode SBI mode Bit sequential buffer 16 bits Clock output 125 62 5 15 6 kHz when the main system clock operates at 1 MHz 250 125 31 3 kHz when the main system clock operates at 2 MHz Vectored interrupt External 3 Internal 4 Test input External 1 Internal 1 System clock oscillator RC oscillator for the main system clock with external resistor and capacitor Crystal oscillator for the subsystem clock Standby function STOP HALT mode Operating ambient temperature TA 40 to 85 C Supply voltage 1 8to55V Package 42 pin plastic shrink DIP 600 mil 44 pin plastic QFP 10 x 10 mm Note Pull up resistors specified with the mask option are not
231. in system clock operation EA Main system clock Can oscillate EJEN Subsystem clock 1 0 Not to be set 1 1 Subsystem clock Oscillation stopped Cautions 1 A time period of up to 1 is needed to change the system clock This means that to terminate main system clock generation bit 3 of the SCC must be set to 1 when the machine cycles indicated in Table 5 4 or more have elapsed after the clock is switched from the main system clock to the subsystem clock 2 When the main system clock is used for operation setting bit 3 of the SCC to stop clock generation does not enter the normal STOP mode 90 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 3 System clock oscillator The main system clock oscillator operates with a resistor R and capacitor C connected to the CL1 and CL2 pins as shown in Figure 5 14 The external clock cannot be input The output frequency fcc of the main system clock oscillator is determined from the resistance R and capacitance C as follows Caution fcc may be subject to a frequency deviation caused by a variation in the supply voltage or temperature Figure 5 14 External Circuit for the Main System Clock Oscillator RC oscillation uPD750108 CL1 CL2 Vss The subsystem clock oscillator operates with a crystal resonator 32 768 kHz standard connected to the XT1 and XT2 pins An external clock can also be input Input the clock signal to the XT1 pin and
232. ing procedure 1 Set a count in the TMODn 2 Set the operating mode count pulse and start indication in the TMn Caution Set a value other than 00H in the modulo register TMODn When using the timer event counter output pin PTOn set the dual function pin P2n as follows 1 Clear the output latch of P2n 2 Set port 2 to the output mode 3 Make a status wherein the internal pull up resistor is not connected in port 2 4 Set the timer event counter output enable flag TOEn to 1 Remark 0 1 Figure 5 35 Configuration of Timer Event Counter INTTn IRQTn set signal TOUT flip flop PTOn TOUTO Modulo register TMODn Comparator Internal clock Count register Tn To serial interface ete Note Channel 0 of the timer event counter only User s Manual U11330EJ2V1UMO00 121 uPD750108 USER S MANUAL Figure 5 36 Count Operation Timing compuse TE ITITI CP Modulo register i TMODn Match Match Reset TOUT flip flop Timer start indication Remark m Set value of the modulo register n 0 1 4 Applications of the timer event counter a Timer event counter is used as an interval timer that generates interrupts at intervals of 30 ms Thehigh order four bits of the timer event counter mode register are setto 0100B to select maximum set time 131 ms at 2 MHz The low order four bits of the timer event counter mode registe
233. inning Example Read the count value of BT SET1 MBE SEL MB15 MOV HL BT Set the BT address in HL LOOP MOV XA HL _ First read MOV BC XA MOV XA HL _ Second read SKE XA BC BR LOOP User s Manual U11330EJ2V1UMO00 107 uPD750108 USER S MANUAL 54 CLOCK TIMER The uPD750108 contains one clock timer which has the following functions a The clock timer sets the test flag IRQW every 0 5 seconds when WMO 1 The IRQW can release the standby mode b The subsystem clock 32 768 kHz can be used to produce 0 5 second intervals c The fast forward mode produces an interval 128 times faster which is useful for program debugging and testing d An arbitrary frequencyNote can be output to the P23 BUZ pin so that it can be used for sounding the buzzer and for system clock frequency trimming e The clock can be started from zero seconds by clearing the frequency divider Note 0 977 1 953 or 15 625 kHz when the main system clock is running at 2 MHz 0 488 0 977 or 7 813 kHz when the main system clock is running at 1 MHz 2 048 4 096 or 32 768 kHz when the subsystem clock is running at 32 768 kHz Caution Set WMO 1 when using the clock function 108 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5 4 1 Configuration of the Clock Timer Figure 5 26 shows the configuration of the clock timer Figure 5 26 Block Diagram of the Clock Timer fw lot
234. ire serial I O mode Input clock externally applied to SCK pin Timer event counter output TOUTO fcc 24 125 kHz during 2 MHz operation 26 62 5 kHz during 1 MHz operation 31 3 kHz during 2 MHz operation 15 6 kHz during 1 MHz operation fcc 23 250 kHz during 2 MHz operation 125 kHz during 1 MHz operation Remarks 1 Each mode can be selected using CSIE CSIM3 and CSIM2 Operation mode Operation halt mode Three wire serial I O mode SBI mode Two wire serial mode 132 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 40 Format of Serial Operation Mode Register CSIM 4 4 Remarks 2 The 1 5 pin assumes any of the following states according to the state of CSIE CSIM1 and CSIMO P01 SCK pin state Input port P01 High impedance SCK input High level output Serial clock output High level output Upon completion of serial transfer 3 When clearing CSIE during serial transfer use the following procedure 1 Disable interrupts by clearing the interrupt enable flag IECSI 2 Clear CSIE 3 Clear the interrupt request flag IRQCSI Examples 1 24 is selected as the serial clock serial interrupt IRQCSI is generated each time serial transfer is completed and serial transfer is performed in the SBI mode with the SBO pin used as the serial data bus
235. ister The table data is addressed by the program counter PC with its low order eight bits PC7 9 exchanged with the contents of the XA register pair The table address is determined by the contents of the program counter present when this instruction is executed The table area must have necessary data loaded by an assembler pseudo instruction DB instruction The program counter is not affected by the execution of this instruction Caution As with MOVT XA PCDE when the instruction is located at address xxFFH table data in the next page is transferred Remark counters consist of 13 bits Function in this section is applicable to the uPD750106 and uPD750108 whose program each This is also applicable to the uPD750104 whose program counter consists of 12 bits and the uPD75P0116 whose program counter consists of 14 bits however User s Manual U11330EJ2V1UMO00 275 uPD750108 USER S MANUAL MOVT XA BCXA Function For the 0750106 and uPD750108 XA Transfers the low order four bits of the table data eight bits in program memory to the A register and the high order four bits to the X register The table data is addressed by the low order one bit of the B register and the contents of the C X and A registers The table area must have necessary data loaded by an assembler pseudo instruction DB instruction The program counter is not affected by the execution of this instruction Tabl
236. it 250 277 CY pmem L 250 277 CY H mem bit 250 277 fmem bit CY 250 277 pmem L CY 250 277 H mem bit CY 250 277 259 299 A 251 283 CY 251 286 A n4 251 281 A HL 251 281 rp 1 XA 251 282 XA rp 251 281 CY fmem bit 252 288 CY pmem L 252 288 OR1 CY H mem bit 252 288 OUT PORTn A 259 298 OUT PORTn XA 259 298 P POP BS 259 297 POP rp 259 297 PUSH BS 259 297 PUSH rp 259 296 R RET 257 295 RETI 258 296 RETS 258 295 RORC A 251 283 S SEL MBn 260 299 SEL RBn 260 299 SET1 CY 251 285 SET1 fmem bit 252 286 SET1 mem bit 252 286 SET1 pmem L 252 286 SET1 H mem bit 252 286 SKE A reg 251 285 SKE A HL 251 284 SKE reg n4 251 284 SKE XA rp 251 285 SKE XA HL 251 285 SKE HL n4 251 284 SKF fmem bit 252 287 SKF mem bit 252 287 SKF pmem L 252 287 SKF H mem bit 252 287 SKT CY 251 285 SKT fmem bit 252 287 SKT mem bit 252 287 User s Manual U11330EJ2V1UMO00 319 uPD750108 USER S MANUAL SKT SKT SKTCLR SKTCLR SKTCLR pmem L 252 287 H mem bit 252 287 fmem bit 252 287 pmem L 252 287 H mem bit 252 287 STOP 259 299 SUBC SUBC SUBC SUBS SUBS SUBS T TBR TCALL X XCH XCH XCH XCH XCH XCH XCH XCH XCH XOR XOR XOR XOR
237. itionally Mk mode _ PC44 g SP 0 0 0 12 SP 1 lt SP 2 PCz 4 lt SP 3 x x MBE RBE SP 4 SP SP 6 Then skip unconditionally Restores the program counter PC memory bank enable flag MBE and register bank enable flag RBE with the data atthe data memory location stack addressed by the stack pointer SP then skips unconditionally after incrementing the contents of SP Caution The program status word PSW is not restored except MBE and RBE User s Manual U11330EJ2V1UMO00 295 uPD750108 USER S MANUAL Remark Function in this section is applicable to the uPD750108 whose program counter consists of 13 bits addr OOOOH to 1FFFH However this is also applicable to the uPD750104 whose program counter consists of 12 bits addr 0000H to OFFFH the uPD750106 whose program counter consists of 13 bits addr OOOOH to 17FFH and the uPD75P0116 whose program counter consists of 14 bits addr 0000H to 3FFFH Function For the 0750108 Mk mode 11 8 SP MBE 0 12 lt SP 1 lt SP 2 PC7 4 lt SP 3 PSW lt SP 4 PSWy lt SP 5 SP lt SP 6 Mk mode PC44 g lt SP 0 0 0 12 SP 1 lt SP 2 PC7 4 lt SP 3 PSW lt SP 4 PSWy lt SP 5 SP lt SP 6 Restores the program counter PC and program status word with the data at the data memory locatio
238. k output then the pin is placed in the normal mode to function as a normal port See Section 5 2 4 for details 2 2 7 BUZ Output Pin Also Used for Port 2 An arbitrary frequency 2 048 4 096 or 32 768 kHz when the subsystem clock operates at 32 768 kHz output on this pin can be used for sounding the buzzer or trimming the system clock frequency This pin is used also as the P23 pin and can be used only when bit 7 WM 7 of the clock mode register WM is set to 1 A RESET signal clears WM 7 to 0 and places this pin in the normal operation mode as a general port See Section 5 4 2 for details 2 2 8 SCK SO SBO SI SB1 I O Pins Also Used for Port 0 These I O pins for serial interface They operate according to the setting of the serial operation mode registers CSIM When three wire serial I O mode is selected SCK functions as CMOS l O SO functions as CMOS output and SI functions as CMOS input When two wire serial I O mode is selected SCK functions as CMOS I O and 581 580 functions as N ch open drain I O A RESET signal stops serial interface operation and places these pins in the input port mode A Schmitt triggered input is used for each pin See Section 5 6 for details 2 2 9 INT4 Input Pin Also Used for Port 0 INT4 is an external vectored interrupt input pin which is rising edge active as well as falling edge active When a signal applied to this pin goes from low to high or from high to low the interrupt request fl
239. l REL The RESET signal is entered CSIE 0 Figure 5 40 Bus release detection flag R Condition for being cleared RELD 0 Condition for being set RELD 1 The transfer start instruction is executed The bus release signal REL is detected The RESET signal is entered CSIE 0 Figure 5 40 SVA does not match SIO when an address is received Command trigger bit W Control bit for command signal CMD trigger output By setting CMDT 1 the SO latch is cleared to 0 Then the CMDT bit is automatically cleared to 0 Caution Never set SBO or SB1 during serial transfer Be sure to set SBO or SB1 before or after serial transfer 162 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Bus release trigger bit W Control bit for bus release signal REL trigger output By setting RELT 1 the SO latch is set to 1 Then the RELT bit automatically cleared to 0 Caution Never set SBO or SB1 during serial transfer Be sure to set SBO or SB1 before or after serial transfer 4 Serial clock selection To select the serial clock manipulate bits 0 and 1 of serial operation mode register CSIM The serial clock can be selected out of the following four clocks Table 5 9 Serial Clock Selection and Application in the SBI Mode Mode register Serial clock CSIM CSIM S Masking of serial clock Timing for shift register R W and aa Application start
240. l O Mode sese 147 5 6 7 SBI Mode Operation enne enne 153 5 6 8 Manipulation of SCK Pin OUTPUT irr etit tbe Pra 182 5 7 SEQUENTIAL BUFFER enters nennen nete 184 INTERRUPT AND TEST FUNCTIONS 187 61 CONFIGURATION OF THE INTERRUPT CONTROL 187 6 2 TYPES OF INTERRUPT SOURCES AND VECTOR TABLES 189 6 3 VARIOUS DEVICES TO CONTROL INTERRUPT FUNCTIONS 191 6 4 INTERRUPT SEQUENCE essere nennen enhn nennen tren 199 6 5 MULTIPLE INTERRUPT PROCESSING sese 200 6 6 PROCESSING OF INTERRUPTS SHARING A VECTOR ADDRESS 202 6 7 MACHINE CYCLES FOR STARTING INTERRUPT PROCESSING 204 6 8 EFFECTIVE USE OF INTERRUPTS 12 4 sensere nennen nnns 206 6 9 INTERRUPT 5 entente nnns nnne ns 206 6 10 TEST EUNGTION eto reete tees 214 6 104 Fest SOUFCOS Li iiim etd ee eot Here D I ae 214 6 10 2 Hardware to Control Test Functions ssssssssseeeee 214 STANDBY FUNCTION conet runde 219 71 SETTING OF STANDBY MODES AND OPERATION STATUS 220 7 2 RELEASE OF THE STANDBY 5 4 seen
241. le to the uPD750104 whose program counter consists of 12 bits addr 0000H to OFFFH the uPD750106 whose program counter consists of 13 bits addr 0000H to 17FFH and the uPD75P0116 whose program counter consists of 14 bits addr 0000H to 3FFFH User s Manual U11330EJ2V1UMO00 291 uPD750108 USER S MANUAL CD BR BCDE Function For the uPD750108 12 0 lt BCDE Branches of the Bo C to the address specified by the program counter whose bits have been replaced with the contents D and E registers Function For the uPD750108 PC42 9 lt BCXA Branches to the address specified by the program counter whose bits have been replaced with the contents of the Bo C Function Remark 292 X and A registers Assembler pseudo instruction of the GETI instruction for table definition This instruction is used to replace 3 byte BR instruction with a 1 byte GETI instruction The 12 bit address data must be coded in addr For detailed information refer to RA75X Assembler Package User s Manual Language EEU 1363 Function in this section is applicable to the uPD750108 whose program counter consists of 13 bits addr OOOOH to 1FFFH However this is also applicable to the uPD750104 whose program counter consists of 12 bits addr 0000H to OFFFH the uPD750106 whose program counter consists of 13 bits addr OOOOH to 17FFH and the uPD75P0116 whose program counter consists of 14 bits addr 0000H to
242. lock counter counts the serial clock to be output or input during transfer and checks whether 8 bit data has been transferred Slave address register SVA and address comparator In the SBI mode SVA is used when the uPD750108 is used as a slave device A slave sets the number assigned to it slave address in SVA The master outputs a slave address to select a particular slave Two data values a slave address output from the master and the value of SVA are compared with each other by the address comparator If a match is found the slave is selected n the two wire serial I O mode SBI mode SVA detects an error when data is transferred with the uPD750108 operating as the master or a slave See 4 in Section 5 6 3 for details 8 INTCSI control circuit The INTCSI control circuit controls interrupt request processing The circuit issues an interrupt request INTCSI and set an interrupt request flag IRQCSI in the following cases See Figure 6 1 n the three wire or two wire serial mode An interrupt request is issued whenever eight serial clocks are counted n the SBI mode When WUP7Note 0 an interrupt request is issued whenever eight serial clocks are counted When WUP 1 an interrupt request is issued when values of SVA and SIO match after an address is received Note WUP Wake up function specification bit bit 5 of CSIM User s Manual U11330EJ2V1UMO00 129 uPD750108 USER S MANUAL 9 Serial clock co
243. lock selection bit W Serial clock SCK pin mode External clock applied to SCK pin Timer event counter output TOUTO 24 125 kHz during 2 MHz operation 62 5 kHz during 1 MHz operation fcc 23 250 kHz during 2 MHz operation 125 kHz during 1 MHz operation Users Manual U11330EJ2V1UMO00 141 uPD750108 USER S MANUAL b Serial bus interface control register SBIC To use the three wire serial mode set SBIC as shown below For details on SBIC format see 2 in Section 5 6 3 SBIC is manipulated using a bit memory manipulation instruction When the RESET signal is input SBIC is set to OOH In the figure below hatched portions indicate the bits used in the three wire serial I O mode Address FE2H 7 6 5 4 3 2 1 0 BSYE ACKT CMDD RELD CMDT RELT SBIC Do not use these bits in the Bus release trigger bit W three wire serial mode Command trigger bit W Remark W Write only Command trigger bit W Control bit for command signal CMD trigger output By setting CMDT 1 the SO latch is cleared Then the CMDT bit is automatically cleared to 0 Bus release trigger bit W Control bit for bus release signal REL trigger output By setting RELT 1 the SO latch is set to 1 Then the RELT bit automatically cleared to 0 Caution Never use bits other than RELT and CMDT in the three wire serial I O mode 2 Communication opera
244. manipulation instruction is used to set the low order two bits of the PCC The high order two bits are set to 0 Bit 3 and bit 2 are set to 1 using the STOP instruction and HALT instruction respectively The STOP instruction and HALT instruction can always be executed regardless of MBE setting The CPU clock can be selected only while the processor is operated by the main system clock When the processor is operated by the subsystem clock the low order 2 bits of the PCC are invalidated and fx1 4 is automatically set The STOP instruction can be executed only when the processor is operated by the main system clock Examples 1 The machine cycle is entered in highest speed mode 2 us at fcc 2 MHz SEL MB15 MOV A 0011B MOV 2 The machine cycle is set to 8 us at fcc 1 MHz SEL MB15 MOV A 0010B MOV PCC A 3 The STOP mode is set A STOP instruction or HALT instruction must always be followed by an NOP instruction STOP NOP A RESET signal clears the PCC to 0 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 12 Format of the Processor Clock Control Register Address Symbol 3 2 1 0 CPU clock selection bit Operation with fcc 2 MHz SCC3 SCCO 00 SCC3 SCCO 01 or 11 is actual frequency at fcc 2 MHz is actual frequency at fxr 32 768 kHz fcc 64 31 3 kHz 4 8 192 kHz fcc 16 125 kHz eevee nm O
245. med on output latch data and the accumulator SKE SKE A HL XA HL Pin data is compared with the accumulator Output latch data is com pared with the accumulator OUT OUT MOV MOV MOV MOV PORTn A PORTn XA PORTn A PORTn XA HL A HL XA Accumulator data is transferred to the output latch with the output buffers kept off Accumulator data is transferred to the output latch and is output on the pins XCH XCH XCH XCH A PORTn XA PORTn A HL XA HL Pin data is transferred to the accumulator and accumulator data is transferred to the output latch with the output buffers kept off Data is exchanged between the output latch and accumulator INCS INCS PORTn HL Pin data incremented by 1 is latched in the output latch Output latch data is incremented by 1 SET1 CLR1 MOV1 SKTCLR 1 1 1 CY 15 82 1 The output latch data of a specified bit is rewritten but the output latch data of the other bits is undefined The output pin state is modified according to the instruction Represents an addressing mode PORTn bit or PORTn L User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5 1 5 Specification of Built In Pull Up Resistors A pull up resistor can be contained at each port pin of the uPD750108 except for POO Whether to use the pull up resistor
246. mem7 2 L3 2 bit L1 0 CY H mem bit CY lt CYv H mems o bit CY fmem bit CY lt CY v fmem bit CY pmem L CY lt CYv pmem7 2 L3 2 bit L1 0 CY H mem bit CY lt CY y H mema o bit User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET Number Address Operand of Machine Operation ing Skip condition bytes cycle area e uPD750104 PC11 0 lt addr The assembler selects the most adequate instruction from instructions below BR laddr BR addr BRCB caddr uPD750106 uPD750108 PC12 9 lt addr The assembler selects the most adequate instruction from instructions below BR addr BRCB caddr BR addr uPD75P0116 1 0 lt addr The assembler selects the most adequate instruction from instructions below BR addr BRCB caddr BR addr addr1 Note e uPD750104 11 0 lt addr1 The assembler selects the most adequate instruction from instructions below BRA addr1 BR addr BRCB caddr BR addr1 uPD750106 uPD750108 PC12 9 lt addr zi The assembler selects the most adequate instruction from instructions below BRA addr1 BR addr BRCB caddr BR addri uPD75P0116 1 0 lt addr1 The assembler selects the most adequate instruction from instructions below BRA addr1 BR addr BRCB caddr
247. mer When WDTM is set to 1 the basic interval timer watchdog timer functions as a watchdog timer An internal reset signal is generated when the basic interval timer BT overflows No reset signal however is generated during the oscillation settling time following the STOP instruction has been released WDTM cannot be cleared without using reset BT is constantly incremented by the clock supplied from the clock generator It cannot be stopped from counting In the watchdog timer mode program crashes are detected using the intervals at which BT overflows The interval can be selected from among four values depending on bits 2 to 0 of BTM see Figure 5 24 Select an interval for detecting crashes according to the user system A large program should be divided into modules each of which can be executed within the set interval Include an instruction which clears BT at the end of each module If execution does not reach the instruction which clears BT within the set interval in which case a program error leading to a program crash may have occurred BT overflows and an internal reset signal is generated to forcibly terminate the program The occurrence of internal reset possibly means that a program crash has occurred A crash can thus be detected Set the watchdog timer as follows lt 1 gt and lt 2 gt can be performed with the same instruction lt 1 gt Set the interval in BTM 2 Set 1 in bit 3 of BTM Initial settings 3 Set 1 in WDT
248. mer event counter 0 output enable flag TOEO 117 Serial bus interface control register SBIC 134 Serial interface interrupt enable flag IECSI 191 Serial interface interrupt request flag IRQCSI 191 IW Wake up function specification bit WUP 131 Watchdog timer enable flag WDTM 105 Serial interface operation enable disable specification bit CSIE 131 Serial operation mode register CSIM 130 Shift register SIO 137 Signal from address comparator COI 131 Skip flag SK0 SK2 65 Slave address register SVA 137 Stack bank select register SBS 48 60 Stack pointer SP 60 Sub oscillator control register SOS 97 System clock control register SCC 90 T Timer counter 1 interrupt enable flag IET1 191 Timer counter 1 interrupt request flag IRQT1 191 Timer counter 1 count register T1 113 Timer event counter 1 mode register TM1 114 Timer counter 1 modulo register TMOD1 113 Timer event counter 1 output enable flag TOE1 117 Timer event counter 0 count register 112 Timer event counter 0 interrupt enable flag IETO 191 Timer event counter 0 interrupt request flag IRQTO 191 322 User s Manual U11330EJ2V1UMO00 APPENDIX E HARDWARE INDEX E 2 HARDWARE INDEX ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE SYMBOL A ACKD 135 ACKE 135 ACKT
249. mode register 0 CSIM The serial clock can be selected out of the following four clocks Table 5 7 Serial Clock Selection and Application in the Three Wire Serial Mode Mode register Serial clock CSIM CSIM S Masking of serial clock Timing for shift register R W and start of serial transfer Application External Automatically In the operable mode Slave CPU SCK masked when CSIE 1 8 bit data When the serial clock is TOUT transfer is masked after 8 bit transfer Half duplex asyn flip flop completed When SCK is high chronous transfer software control fcc 24 Middle speed serial transfer fcc 23 High speed serial transfer Users Manual U11330EJ2V1UMO00 143 uPD750108 USER S MANUAL 4 Signals Figure 5 45 shows operations of RELT and Figure 5 45 Operations of RELT and CMDT SO latch RELT CMDT Switching between MSB and LSB as the first transfer bit The three wire serial I O mode has a function that can switch between the MSB and LSB as the first bit of transfer Figure 5 46 shows the configuration of shift register SIO and internal bus As shown in Figure 5 46 read or write operation can be performed by switching between the MSB and LSB This switching can be specified using bit 2 of serial operation mode register CSIM Figure 5 46 Transfer Bit Switching Circuit 7 6 Internalbus
250. n 0 Once the timer is set interrupt request signal IRQTO IRQT1 is generated atthe intervals set in the timer Table 5 6 lists the resolution and longest setup time time when FFH is setin the modulo register for each count pulse to the timer event counter Table 5 6 Resolution and Longest Setup Time a When timer event counter channel 0 Mode register At 2 MHz At 1 MHz TMOG TMO05 Resolution Longest setup time Resolution Longest setup time b When timer counter channel 1 Mode register At 2 MHz At 1 MHz TM16 TM15 Resolution Longest setup time Resolution Longest setup time 1049 ms 262 ms 65 5 ms 16 4 ms 120 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 3 Timer event counter operation The timer event counter operates as follows Figure 5 35 shows the configuration of the timer event counter lt 1 gt The count pulse CP is selected by setting the timer event counter mode register TMn and is input to the timer event counter count register Tn lt 2 gt The Tn is compared with the timer event counter modulo register TMODn and if they are equal a match signal is generated and the interrupt request flag IRQTn is set At the same time the timer out flip flop TOUT flip flop is inverted Figure 5 36 is a timing chart of the timer event counter The timer event counter normally begins operation in the follow
251. n stack addressed by the stack pointer SP then increments the contents of SP This instruction is used when control is returned from an interrupt service routine Remark Function in this section is applicable to the uPD750108 whose program counter consists of 13 bits addr OOOOH to 1FFFH However this is also applicable to the uPD750104 whose program counter consists of 12 bits addr 0000H to OFFFH the uPD750106 whose program counter consists of 13 bits addr OOOOH to 17FFH and the uPD75P0116 whose program counter consists of 14 bits addr 0000H to 3FFFH PUSH Function SP 1 lt rpp SP 2 lt SP SP 2 Saves the contents of register pair rp XA HL DE BC to the data memory location stack addressed by the stack pointer SP then decrements SP The high order part of a register pair X H D B is saved to the stack location addressed by 5 1 and the low order part A L E is saved to the stack location addressed by 5 2 296 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET PUSH BS Function SP 1 MBS SP 2 lt RBS SP lt SP 2 Saves the contents of the memory bank select register MBS and the register bank select register RBS to the data memory location stack addressed by the stack pointer SP then decrements SP C gt POP rp Function rp lt SP lt SP 1 SP lt SP 2 Restores register
252. nable flag is set by the El instruction At this stage INTO and INTTO are enabled An interrupt enable flag is cleared by the DI IExxx instruction to disable INTO The DI instruction disables all interrupts User s Manual U11330EJ2V1UMO00 207 uPD750108 USER S MANUAL 2 Example of using INTBT INTO falling edge active and INTTO without multiple interrupt processing 1 2 3 4 5 Main program 1 Reset n 1 0 2 MOV A 1 MOV IMO A CLR1 IRQO 3 IEBT Status 0 INTO service program 0 EI IETO EI A lt 4 gt INTO i Status 1 5 RETI Y A RESET signal disables all interrupts setting status O INTO is set to be falling edge active Interrupts are enabled by the El and EI IExxx instructions On the falling edge of INTO the INTO interrupt service program is started status is set to 1 and all interrupts are disabled Control is returned from the interrupts by the RETI instruction status 0 is set again and interrupts are enabled Remark all the interrupts are used as having the lower priority as shown in this example saving 208 restoring the register bank is not necessary if RBE 1 and RBS 2 for the main program and register banks 2 and are used 0 for the interrupt service program and register banks 0 and 1 are used User s Manual U11330EJ2V1UMO00 CHAPTER 6
253. ne cycles 4 machine cycles CALLF faddr instruction 2 machine cycles 3 machine cycles Caution For the 75X and 75XL series Mk Il mode supports a program area of more than 16K bytes This mode is provided to maintain software compatibility with products requiring a program memory of more than 16K bytes When Mk II mode is selected each use area of the stack byte when the subroutine call instruction is executed will be increased by one byte compared to Mk mode When the CALL addr or faddr instruction is used the machine cycle will need one more machine cycle Therefore Mk mode is recommended for those applications where emphasis is placed on RAM efficiency or speed rather than software compatibility Users Manual U11330EJ2V1UMO00 47 uPD750108 USER S MANUAL 4 1 2 Setting of the Stack Bank Selection Register SBS The Mk mode and Mk mode are switched by stack bank selection register Figure 4 1 shows the register configuration The stack bank selection register is set with a 4 bit memory operation instruction To use the CPU in Mk mode initialize the register to 100xBNote at the beginning of the program To use the CPU in Mk II mode initialize it to OOOxBNote Note Specify the desired value in x Figure 4 1 Stack Bank Selection Register Format Address 3 2 1 0 Symbol Stack area designation o Memory bank 0 o i Memory bank 1 Other settings are inhibited Bit 2 must
254. ne cycles required when a skip instruction with the skip function performs a skip operation S assumes one of the following values e When no skip operation is performed S 0 e When a 1 byte instruction or 2 byte instruction is skipped S 1 When a 3 byte instructionNote js skipped S 2 Note 3 byte instruction BR addr BRA addri CALL addr and CALLA addr1 instructions Caution The GETI instruction is skipped in one machine cycle One machine cycle is equal to one cycle tcy of the CPU clock and four different machine cycles are available for selection according to the PCC setting See Figure 5 12 248 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET Address Operation ing Skip condition area Machine Operand A n4 lt n4 String effect A reg1 n4 regi lt n4 XA n8 XA lt n8 String effect A HL n8 HL n8 String effect B rp2 n8 rp2 n8 A HL A lt HL A HL A lt HL then L lt L 1 A HL A lt HL then L lt L 1 1 A lt 1 XA HL XA lt HL HL A HL lt A HL XA HL lt XA A mem A lt mem XA mem XA mem mem A mem A x 0 o c mem XA mem XA A reg A reg XA rp XA lt rp reg1 A regi A IDM m gt
255. ned by detecting a match for a slave ad dress received after bus release in the state of RELD 1 An address match is detected usually using an address match interrupt IRQCSI generated when WUP is set to 1 So detect selection nonselection state by slave address when WUP is set to 1 2 When determining whether a slave is selected without using an interrupt when WUP is O do not use the address match detection method Instead use transfer of commands set in advance in a program Error detection In the SBI mode the state of serial bus SBO or SB1 being used for communication is loaded into the shift register SIO of the transmitting device So a transmission error can be detected by the methods described below a Comparing SIO data before start of transmission with SIO data after start of transmission With this method the occurrence of a transmission error is assumed if two SIO values disagree with each other b Using the slave address register SVA Transmit data is set in SIO and SVA as well before the data is transmitted On completion of transmission the COI bit match signal from the address comparator of serial operation mode register CSIM is tested If the result is 1 the transmission is regarded as successful If the result is 0 the occurrence of a transmission error is assumed Communication operation In the SBI mode the master usually selects a slave device to communicate with from multiple devices by outputting
256. nfiguration of the Basic Interval Timer Watchdog Timer 103 5 3 2 Basic Interval Timer Mode Register BTM 103 5 3 3 Watchdog Timer Enable Flag 105 5 3 4 Operation of the Basic Interval Timer 105 5 3 5 Operation of the Watchdog Timer 106 5 3 6 Other FUNCIONS det teste e RU CERE delet eres 107 User s Manual U11330EJ2V1UMOO CHAPTER 6 CHAPTER 7 5 4 e CLOCK TME R eaten tuens 108 5 4 1 Configuration of the Clock Timer 109 5 4 2 Clock Mode Register enne 109 5 5 TIMER EVENT COUN TER 111 5 5 1 Configuration of Timer Event Counter 111 5 5 2 8 Bit Timer Event Counter Mode Operation 117 5 5 3 Notes on Timer Event Counter 123 5 6 SERIAL INTERFACE iere te e peer anne ein ap de de eae Ud qudd 126 5 6 1 Serial Interface Functions maicena ieira aa traap kraai aea aiana RTEA 126 5 6 2 Configuration of Serial Interface sse 127 5 6 3 Register Functions 130 5 6 4 Operation Halt Mode 138 5 6 5 Three Wire Serial Mode Operations 140 5 6 6 Two Wire Serial
257. not have a mask option Its wait time is fixed to 29 fcc Remark The dashed line indicates the case where the interrupt request that releases the standby mode is accepted Figure 7 1 Standby Mode Release Operation 2 2 c Release of the HALT mode by RESET signal Wait Note gt HALT instruction oes RESET signal Operating mode Operating mode HALT mode gt lt Clock Oscillation d Release of the HALT mode by the occurrence of an interrupt HALT instruction Standby Y release signal ___ _ Operating mode HALT mode Operating mode 3 E Oscillation Clock Note 56 fcc 28 us at 2 MHz 56 us at 1 MHz Remark The dashed line indicates the case where the interrupt request that releases the standby mode is accepted 222 User s Manual U11330EJ2V1UMO00 CHAPTER 7 STANDBY FUNCTION 7 3 OPERATION AFTER A STANDBY MODE IS RELEASED 1 If a standby mode is released by a RESET signal normal reset operation is performed 2 Ifastandby mode 15 released by the occurrence of an interrupt request the contents of the interrupt master enable flag IME determines whether to perform a vectored interrupt when the CPU resumes instruction execution a When IME 0 If a standby mode is released execution restarts with the instruction immediately following the in
258. nstruction directly the address must be specified with SCKP However MBE 0 or MBE 1 MBS 15 must be specified before the instruction is executed Not allowed Allowed CLR1 PORTO 1 CLR1 OFFOH 1 PORTO 1 SET1 OFFOH 1 CLR1 SCKP SET1 User s Manual U11330EJ2V1UMO00 183 uPD750108 USER S MANUAL 5 7 BIT SEQUENTIAL BUFFER 16 BIT The bit sequential buffer BSB is special data memory for bit manipulations In particular the buffer allows bit manipulations to be performed very easily by sequentially changing address and bit specifications So the buffer is useful in processing long data bit by bit This data memory consists of 16 bits and allows pmem L addressing with a bit manipulation instruction This addressing uses the L register for indirect bit specification In this case only by incrementing or decrementing the L register in a program loop the bit to be manipulated can be sequentially shifted for continued processing Figure 5 81 Format of the Bit Sequential Buffer Address FC3H FC2H FC1H FCOH Bit Symbol L register L CH L BH L L 7H L 4H L 3H gt DECSL INCS L lt Remarks 1 With pmem L addressing bit specification is shifted according to the L register 2 With pmem L addressing BSB can be manipulated at any time regardless of MBE MBS specification Data can also be manipulated by direct addressing The buffer can be used for applications such as continuou
259. ntrol circuit The serial clock control circuit controls the serial clock to be supplied to the shift register or controls the clock to be output to the SCK pin when the internal system clock is used 10 Busy acknowledge output circuit and bus release command acknowledge detection circuit The busy acknowledge output circuit and bus release command acknowledge detection circuit output and detect control signals generated in the SBI mode These circuits do not operate in the three wire or two wire serial I O mode 11 output latch The P01 output latch generates serial clock by software after the eighth serial clock has been output When the RESET signal is entered this latch is set to 1 To select the internal system clock as the serial clock set the P01 output latch to 1 5 6 3 Register Functions 1 Serial operation mode register CSIM Figure 5 40 shows the format of serial operation mode register CSIM CSIM is an 8 bit register which specifies a serial interface operation mode serial clock wake up function and so forth CSIM is manipulated using an 8 bit memory manipulation instruction The higher three bits can be manipulated bit by bit Each bit can be manipulated using its name Each bit may or may not allow read and or write operation see Figure 5 40 Bit 6 allows bit test operation only any data written to this bit is invalid When the RESET signal is generated all bits are cleared to 0 Figure 5 40 Format of Ser
260. o program typical 256K bit to 4M bit PROMs PA 75P008CU The PA 75P008CU is a PROM programmer adapter provided for the uPD75P0116CU GB It is used in conjunction with the PG 1500 Software PG 1500 This program enables the host machine to control the PG 1500 through the serial and controller parallel interfaces Host machine Part number OS Distribution media PC 9800 series MS DOS 3 5 inch 2HD wS5A13PG1500 Ver 3 30 to 5 25 inch 2HD uS5A10PG1500 Ver 6 2Note PC AT and See OS for IBM 3 5 inch 2HD uS7B13PG1500 compatibles PC 5 25 inch 2HC uS7B10PG1500 Note These software products cannot use the task swap function which is available in MS DOS Ver 5 00 or later Remark Operation of the PG 1500 controller is guaranteed only on the above host machines and OSs 306 User s Manual U11330EJ2V1UMO00 APPENDIX B DEVELOPMENT TOOLS Debugging tools The in circuit emulators IE 75000 R and IE 75001 R are provided to debug programs used for the uPD750108 The following system is shown below Hardware IE 75000 RNete 1 The IE 75000 R is an in circuit emulator used to debug hardware and software when developing an application system using the 75X series and 75XL series Use this emulator together with optional emulation board IE 75300 R EM and emulation probe to develop application systems of the 1PD750108 subseries For efficient debugging connect the emulator to the hos
261. o be set All interrupts are disabled and no vectored interrupt is activated The interrupt enable flag corresponding to an interrupt request flag controls interrupt enabling disabling gg 0 1 User s Manual U11330EJ2V1UMO00 193 uPD750108 USER S MANUAL 3 Configurations of the INTO INT1 and INT4 circuits 194 a As shown in Figure 6 4 a the INTO circuit accepts an external interrupt at its rising or falling edge c The edge to be detected can be selected The INTO circuit has a noise elimination function see Figure 6 5 called a noise eliminator using a sampling clock which removes pulses shorter than two sampling clock cyclesNote as noise The INTO circuit may accept pulses which are longer than one sampling clock cycle and shorter than two cycles as interrupts depending on the sampling timing see Figure 6 4 a The circuit is sure to accept pulses equal to or longer than two sampling clock cycles as interrupts The INTO pin is supplied with sampling clock or foc 64 whichever is selected by bit IMO3 of the INTO edge detection mode register IMO Bit 0 IMOO and bit 1 IMO1 of the INTO edge detection mode register IMO are used to select a detection edge Figure 6 6 a shows the format of IMO A 4 bit memory manipulation instruction is used to set IMO A RESET signal clears all bits to 0 and a rising edge is specified to be detected Note When the frequency of a sampling cl
262. ock is these cycles are equal to 2tcy When the frequency of a sampling clock is 64 these cycles are equal to 128 Cautions 1 Inputa pulse wider than two sampling clock cycles to the INTO P10 pin Otherwise the pulse is suppressed as noise by a noise eliminator when the pin is used as a port 2 When the noise eliminator is selected IMO2 is set to 0 INTO does not operate in standby mode because INTO requires a clock for sampling the noise eliminator does not operate unless the CPU clock is supplied Do not select the noise eliminator when using INTO to release standby mode set IM02 to 1 As shown in Figure 6 4 b the INT1 circuit accepts an external interrupt at its rising or falling edge The INT1 edge detection mode register IM1 is used to select a detection edge Figure 6 6 b shows the format of IM1 A bit manipulation instruction is used to set IM1 A RESET signal clears all bits to 0 and a rising edge is specified to be detected As shown in Figure 6 4 c the INT4 circuit accepts an external interrupt at its rising and falling edges User s Manual U11330EJ2V1UMO00 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Figure 6 4 Configurations of the INTO INT1 and INT4 Circuits a Configuration of the INTO circuit 5 INTO Edge detection circuit set signal INTO P10 Noise eliminator Selector ete IM02 IMOO IMO1 IMOS3 Detection edge specifi
263. ock output Clock divider Standby O PCL P22 xn CL1 CL2 Voo Vss RESET uPD750108 and 14 bits for the uwPD75P0116 2 The ROM capacity depends on the product 3 uPD75P0116 User s Manual U11330EJ2V1UMO00 Peo P63 Port 7 1 P70 P73 1 C Z P80 P81 Port 8 Bit sequential buffer 16 The program counter for the uPD750104 consists of 12 bits 13 bits for the 750106 and uPD750108 USER S MANUAL 1 5 PIN CONFIGURATION TOP VIEW 1 42 pin plastic shrink DIP 600 mil uPD750104CU xxx uPD750106CU xxx uPD750108CU xxx uPD75P0116CU 1 2 3 4 5 6 7 8 9 P80 PO3 SI SB1 P02 SO SBO P01 SCK POO INT4 P13 TIO P12 INT2 P11 INT1 P10 INTO IC Vep Nete P53 D7 P60 KRO P61 KR1 P62 KR2 P63 KR3 P70 KR4 P71 KR5 P72 KR6 P73 KR7 P20 PTOO P21 PTO1 P22 PCL P23 BUZ Note Connect IC Vpp to Vpp keeping the wiring as short as possible Remark PD75P0116 6 User s Manual U11330EJ2V1UMOO CHAPTER 1 GENERAL 2 44 pin plastic QFP 10 x 10 mm uPD750104GB xxx 3BS MTX uPD750106GB xxx 3BS MTX uPD750108GB xxx 3BS MTX uPD75P0116GB 3BS MTX P20 PTOO O P21 PTO1 O P22 PCL O P23 BUZ IC Vep Note O P10 INTO O P11 INT1 O P12 INT2 O NC n P72 KR6 1 P13 TIO P71 KR5 2 POO INT4 P70 KR4 3 PO1 SCK P63 KR3
264. on low speed high speed Operating mode CPU operation gt lt 32 8 ms INT4 INT4 226 User s Manual U11330EJ2V1UMO00 CHAPTER 7 STANDBY FUNCTION lt Sample program gt Initialization MOV A 0011B MOV PCC A High speed mode MOV XA 05 MOV WM XA Subsystem clock EI IE4 EI IEW EI Enable interrupt Main routine SKT PORTO 0 Power normal HALT Power down mode NOP Power normal SKTCLR IROW Flag set for 0 5 second BR MAIN NO CALL WATCH Clock subroutine MAIN INT4 service routine VINT4 SKT PORTO 0 Power normal MBE 0 BR PDOWN CLR1 SCC 3 Start main system clock oscillation MOV A 0DH MOV BTM A WAIT1 SKT IRQBT Wait for 32 8 ms BR WAIT1 SKT PORTO 0 Chattering check BR PDOWN CLR1 SCC 0 Switch to main system clock RETI PDOWN SET1 SCC 0 Switch to subsystem clock MOV A 0AH WAIT2 INCS A Wait for 15 machine cycles BR WAIT2 SET1 SCC 3 Stop main system clock oscillation RETI Caution Before the system clock is changed from the main system clock to the subsystem clock a wait time sufficient for stable subsystem clock generation is required User s Manual U11330EJ2V1UMO00 227 uPD750108 USER S MANUAL MEMO 228 User s Manual U11330EJ2V1UMO00 CHAPTER 8 RESET FUNCTION The uPD750108 is reset with the external reset signal RESET or the reset signal received from the basic interval timer watchdog timer When either reset signal is input the internal
265. on b External clock uPD750108 uPD750108 Vss External xn clock 2o AH Lr E 28 XT2 XT2 Crystal Standard frequency 32 768 kHz Remark f the subsystem clock is not to be used see 6 of Section 5 2 2 Users Manual U11330EJ2V1UMO00 17 uPD750108 USER S MANUAL 2 2 15 RESET This is the pin for active low reset input The RESET inputis asynchronous When a signal with certain low level width is applied to the pin a RESET signal is generated to cause a system reset which has priority over any other operations The RESET signal is used for normal CPU initialize start operation and is also used to release STOP or HALT mode A Schmitt triggered input is used for the RESET input pin 2 2 16 Vpp This is the positive power supply pin 2 2 17 Vss This is the ground pin 2 2 18 IC for the 0750104 0750106 and 4PD750108 only The internally connected IC pin is used to set the 4PD7501 08 to test mode for inspection prior to shipping In normal operation connect the IC pin to the Vpp pin keeping the writing as short as possible When the wiring between the IC pin and the Vpp pinis too long or noise is generated on the IC pin a potential difference may occur between the IC pin and the Vpp pin This may cause your program to malfunction Connect the IC pin to the Vpp pin keeping the wiring as short as possible Keep the wiring as short as possible 2 2 19 Vpp for the uPD75P0116 only This is
266. on to reduce the power consumption by the system The standby function is available in the two modes the STOP mode and HALT mode 1 2 Differences between these two modes are as follows STOP mode Inthe STOP mode the main system clock oscillator is stopped and the entire system stops The current used by the CPU is reduced to quite a low level In addition the contents of data memory can be preserved with a low supply voltage of down to Vpp 1 8 V that is this mode is effective to retain data memory with a very low current The wait time applied when STOP mode is released by an interrupt request can be specified as 29 fcc or no wait by using a mask option To start processing immediately upon the detection of an interrupt request select no wait The uPD75P0116 however does not have a mask option and its wait time is fixed to 2910 If 29 fcc has been selected and processing must be started immediately upon the detection of an interrupt request select HALT mode HALT mode In the HALT mode the CPU clock is stopped but the oscillation of the system clock oscillator continues In this mode the system uses more currentthan in the STOP mode However the HALT mode is suitable for starting processing immediately after an interrupt request or for intermittent operations such as watch operation In either mode all contents of the registers flags and data memory that are present immediately before the standby mode is set ar
267. ons to define tables used for GETI 260 Operand Number of bytes Machine cycle Operation RBS n n 0 3 Address ing area Skip condition MBS n n 0 1 15 GETINote instructions e uPD750104 When the TBR instruction is used 11 0 taddr a o taddr 1 When the TCALL instruction is used SP 4 SP 1 SP 2 lt 11 SP 3 lt MBE 0 0 PC41 9 taddr 3 9 taddr 1 SP lt SP 4 When an instruction other than the TBR or TCALL instruction is used Execution of taddr taddr 1 instruction e uPD750106 uPD750108 When the TBR instruction is used PC12 0 taddr 4 9 taddr 1 When the TCALL instruction is used SP 4 SP 1 SP 2 lt PC11 9 SP 3 lt MBE 0 PC42 12 0 lt taddr 4 9 taddr 1 SP lt SP 4 When an instruction other than the TBR or TCALL instruction is used Execution of taddr taddr 1 instruction e uPD75P0116 When the TBR instruction is used PC143 9 taddr 5 9 taddr 1 When the TCALL instruction is used SP 4 SP 1 SP 2 lt 11 SP 3 lt MBE PC45 12 PC13 0 taddr 5 9 taddr 1 SP lt SP 4 When an instruction other than the TBR or TCALL instruction is used Execution of taddr taddr 1 instruction User s Manual U11330EJ2V1UMO00 Depends on the referenced instruction Depends on the referenced instruction De
268. ormat of Stack Pointer and Stack Bank Select Register 61 4 12 Data Saved to the Stack Memory Mk Mode 62 4 13 Data Restored from the Stack Memory Mk 62 4 14 Data Saved to the Stack Memory Mk II Mode 63 4 15 Data Restored from the Stack Memory Mk Mode 63 4 16 Program Status Word Format sse eene 64 4 17 Bank Select Register 67 5 1 Data Memory Addresses of Digital Ports 69 5 2 Configurations of Ports 0 and 1 nennen nnne 71 5 3 Configurations of Ports 2 and 7 72 5 4 Configurations of Ports and 6n n 0 to 73 5 5 Configurations of Ports 4 and eene nennen nnne nnns 74 5 6 Gonfigurationi of POLT 8 c eerte 75 5 7 Formats of Port Mode Registers 77 5 8 Pull Up Resistor Specification Register Format 84 User s Manual U11330EJ2V1UMOO LIST OF FIGURES 2 4 Figure No Title Page 5 9 Timing Chart of Digital O Ports sssssssseeeeeneeneenenm enne 84 5 10 ON Timing Chart of Built In Pull Up Resistor Connected by Software
269. orts 2 4 5 and 7 can be set in units of four bits by port mode register group B PMGB The I O mode of port 8 can be set in units of two bits by port mode register group C PMGC Each port functions as an input port when the corresponding bit of the port mode register is set to 0 and functions as an output port when the same corresponding bit is set to 1 When the output mode is selected by the port mode register the contents of the output latch appear on the output pins and so the contents of the output latch must be changed to a desired value before the output mode is set An 8 bit memory manipulation instruction is used to set port mode register group A B or C A RESET signal clears all bits of each port mode register to 0 This means that the output buffers are set off and all ports are placed in the input mode Example P30 P31 P62 and P63 are used as input pins and P32 P33 P60 and P61 are used as output pins CLR1 MBE or SEL MB15 MOV XA 3CH MOV PMGA XA 76 User s Manual U11330EJ2V1UMOO CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 7 Formats of Port Mode Registers S Contents of specification Input mode Output buffer off Output mode Output buffer on Port mode register group A Address 7 6 5 4 3 2 1 0 Symbol PM63 PM62 PM61 PM60 PM33 PM32 PM31 PM30 FE8H PMGA P30 I O specification P31 I O specification P32 I O specification P33 I O specification P60 I
270. ovided for the development of a system which employs the uPD750108 In the 75XL series use the common relocatable assembler together with a device file of each model RA75X relocatable assembler Device file Host machine OS Distribution media Part number PC 9800 series MS DOS Ver 3 30 io Ver 6 2Note 3 5 inch 2HD US5A13RA75X 5 25 inch 2HD uS5A10RA75X IBM PC AT and compatibles Host machine See OS for IBM PC 3 5 inch 2HC uS7B13RA75X 5 25 inch 2HC OS Distribution media uS7B10RA75X Part number PC 9800 series MS DOS Ver 3 30 to Ver 6 2Note 3 5 inch 2HD US5A13DF 750008 5 25 inch 2HD US5A10DF750008 IBM PC AT and compatibles See OS for IBM PC 3 5 inch 2HC uS7B13DF750008 5 25 inch 2HC uS7B10DF750008 Note These software products cannot use the task swap function which is available in MS DOS Ver 5 00 or later Remark operations of the assembler and device file are guaranteed only on the above host machines and OSs User s Manual U11330EJ2V1UMO00 305 uPD750108 USER S MANUAL PROM programming tools Hardware PG 1500 The PG 1500 PROM programmer is used together with an accessory board and optional program adapter It allows the user to program a single chip microcomputer containing PROM from a standalone terminal or a host machine The PG 1500 can be used t
271. pair rp XA HL DE BC with the data at the data memory location stack addressed by the stack pointer SP then increments SP The low order part of a register pair A L E C is restored from the contents of SP and the high order part X D B is restored with the contents of SP D Pop Bs Function RBS lt SP MBS lt SP 1 SP lt SP 2 Restores the register bank select register RBS and the memory bank select register MBS with the data at the data memory location stack addressed by the stack pointer SP then increments SP 11 4 12 Interrupt Control Instructions Function IME IPS 3 lt 1 Sets the interrupt master enable flag bit 3 of the interrupt priority specification register to 1 to enable interrupts Whether to accept an interrupt is controlled with the corresponding interrupt enable flag EI IExxx Function 1 XXX 5 Noo Sets an interrupt enable flag IExxx to 1 to enable an interrupt xxx BT CSI TO T1 W 0 1 2 4 On Function IME IPS 3 lt 0 Resets the interrupt master enable flag bit 3 of the interrupt priority specification register to 0 to disable all interrupts regardless of the states of the interrupt enable flags User s Manual U11330EJ2V1UM00 297 uPD750108 USER S MANUAL DI IExxx Function 0 xxx Ns No Resets an interrupt enable flag IExxx to 0 to disable an interrupt xxx
272. pecified with the mask option is incorporated Or it causes ports 4 and 5 to enter the high impedance state 2 2 3 P80 P81 PORTS These are 2 bit I O ports with output latches Built in pull up resistors can be connected to port 8 in units of 2 bits by software This can be done by manipulating pull up resistor specification register group B POGB 2 2 4 TIO Input Pin Also Used for Port 1 This is an external event pulse input pin for programmable timer event counter 0 To use this pin select the external event pulse input as the count pulse CP in the timer event counter mode register TMO A Schmitt triggered input is used for the TIO pin See 1 of Section 5 5 1 for details 14 User s Manual U11330EJ2V1UMO00 CHAPTER 2 PIN FUNCTIONS 2 2 5 PTOO PTO1 Output Pin Also Used for Port 2 These are the output pins of timer event counter 0 and timer counter 1 Square wave pulses appear on this pin To output a signal from the timer event counter and timer counter clear the output latch to 0 and set bit 2 for port mode register group B to 1 The timer start instruction clears the output of TOUT flip flop to 0 See 3 of Section 5 5 2 for details 2 2 06 PCL Output Pin Also Used for Port 2 This is the programmable clock output pin It is used to supply the clock pulse to a peripheral LSI circuit such as a slave microcontroller or A D converter A RESET signal clears the clock output mode register CLOM to 0 disabling cloc
273. pends on the referenced instruction CHAPTER 11 INSTRUCTION SET Address Operation ing Skip condition area Operand Machine cycle GETINotes1 2 uPD750104 When the TBR instruction is used PC411 0 taddr 3 9 taddr 1 When the TCALL instruction is used SP 6 SP 3 SP 4 PC41 0 SP 5 lt 0 0 0 0 8 2 lt x MBE PC44 9 taddr 3 9 taddr 1 SP lt SP 6 When an instruction other than Depends on the the TBR or TCALL instruction is referenced used instruction Execution of taddr taddr 1 instruction e uPD750106 uPD750108 When the TBR instruction is used PC12 9 taddr 4 9 taddr 1 When the TCALL instruction is used SP 6 SP 3 SP 4 PC11 o SP 5 lt 0 0 0 12 8 2 lt x x MBE PC12 9 taddr 4 9 taddr 1 When an instruction other than Depends on the the TBR or TCALL instruction is referenced used instruction Execution of taddr taddr 1 instruction e uPD75P0116 When the TBR instruction is used PC13 9 lt taddr 5 9 taddr 1 When the TCALL instruction is used SP 6 SP 3 SP 4 PC41 0 SP 5 lt 0 0 13 12 SP 2 lt x MBE taddr 5 9 taddr 1 SP lt SP 6 When an instruction other than Depends on the the TBR or TCALL instruction is referenced used instruction Execution of taddr taddr 1 instruction Notes 1 The shaded po
274. peration with 1 MHz SCC3 SCCO 01 or 11 is actual frequency at foc 1 MHz is actual frequency at fxt 32 768 kHz otn sein eters Remarks 1 fcc Output frequency from the main system clock oscillator 2 fxr Output frequency from the subsystem clock oscillator CPU operation mode control bits Normal operation mode 0 1 HALT mode 1 0 STOP mode Not to be set User s Manual U11330EJ2V1UM00 89 uPD750108 USER S MANUAL 2 System clock control register SCC The SCC is a 4 bit register for selecting CPU clock with the least significant bit and for controlling the termination of main system clock generation with the most significant bit see Figure 5 13 Bits 0 and 3 of the SCC are located at the same data memory address but both bits cannot be changed at the same time Accordingly bits 0 and 3 of the SCC are set using bit manipulation instructions Bits 0 and 3 of the SCC can be manipulated regardless of MBE setting Main system clock generation can be terminated by setting bit 3 of the SCC only when the subsystem clock is used for operation The STOP instruction must be used to terminate main system clock generation A RESET signal clears the SCC to 0 Figure 5 13 Format of the System Clock Control Register Address 3 2 1 0 Symbol FB7H SCC3 SCCO SCC SCC3 SCCO CPU clock frequency Ma
275. pplication which performs serial data communication in the SBI mode In the example the u PD750108 can be used as either the master CPU or a slave CPU on the serial bus The master can be switched to another CPU with a command a Serial bus configuration In the serial bus configuration used for the example of this section a uPD750108 is connected to the bus line as a device on the serial bus Two pins on the LPD750108 are used serial data bus 580 or 581 and serial clock SCK Figure 5 71 shows an example of the serial bus configuration Figure 5 71 Example of Serial Bus Configuration Master CPU uPD750108 580 581 SCK Slave CPU uPD750108 SBO SB1 Address 1 S A Slave CPU SBO SB1 Address 2 n A Slave IC SBO SB1 Address N n A U11330EJ2V1UM00 177 uPD750108 USER S MANUAL b Explanation of commands i Types of commands This example uses the following commands lt 1 gt READ command Transfers data from slave to master 2 WRITE command Transfers data from master to slave 3 END command Informs slave of WRITE command completion 4 STOP command Informs slave of WRITE command interruption 5 STATUS command Reads slave status 6 RESET command Sets currently selected slave as non selected slave 7 CHGMST command Passes master authority to slave ii Protocol The following protocol is used for communication between the ma
276. priority specification register IPS 192 Interrupt request flag for clock timer IRQW 214 Interrupt status flag ISTO IST1 65 198 INTO edge detection mode register IMO 197 INTO interrupt enable flag IEO 191 INTO interrupt request flag IRQO 191 INT1 edge detection mode register IM1 197 INT1 interrupt enable flag IE1 191 INT1 interrupt request flag IRQ1 191 INT2 edge detection mode register IM2 217 INT2 interrupt enable flag IE2 214 INT2 interrupt request flag IRQ2 214 INT4 interrupt enable flag IE4 191 INT4 interrupt request flag IRQ4 191 K Key interrupt input KRO KR7 215 M Memory bank enable flag MBE 23 66 Memory bank select register MBS 23 67 P Port 0 to port 8 PORTO PORTS 70 Port mode register group A PMGA 77 Port mode register group B PMGB 77 Port mode register group C PMGC 77 Processor clock control register PCC 88 Program counter PC 49 Program status word PSW 64 Pull up resistor specification register group A POGA 84 Pull up resistor specification register group B POGB 84 User s Manual U11330EJ2V1UMO00 321 uPD750108 USER S MANUAL R Register bank enable flag RBE 36 66 Register bank select register RBS 36 67 S Timer event counter 0 mode register TMO 114 Timer event counter 0 modulo register TMODO 112 Ti
277. ps etc traffic control systems anti disaster Systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems or medical equipment for life support etc The quality grade of NEC devices is Standard unless otherwise specified in NEC s Data Sheets or Data Books If customers intend to use NEC devices for applications other than those specified for Standard quality grade they should contact an NEC sales representative in advance M7D 98 12 User s Manual U11330EJ2V1UMOO Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics Inc U S Santa Clara California Tel 408 588 6000 800 366 9
278. pulation addressing fmem bit pmem L H mem bit Example The flag bit 3 at address 3FH in data memory is set in bit 2 of port 3 FLAG EQU 3FH 3 SEL MBO MOV H FLAG SHR6 H high order 4 bits of FLAG MOV1CY H FLAG CY lt FLAG MOV1PORT3 2 CY P32 lt CY 11 4 4 Arithmetic Logical Instructions i ADDS A n4 Function A lt A n4 Skip if carry 4 13 0 0 FH Adds the 4 bit immediate data n4 to the contents of the A register in binary then skips the next instruction if the addition generates a carry The carry flag is not affected This instruction when combined with the ADDC A HL or SUBC A HL instruction functions as a number system conversion instruction See Section 11 1 User s Manual U11330EJ2V1UMO00 277 uPD750108 USER S MANUAL C 2 ADDS XA n8 Function XA lt XA n8 Skip if carry n8 17 0 OOH FFH Adds the 8 bit immediate data n8 to the contents of the XA register pair in binary then skips the next instruction if the addition generates a carry The carry flag is not affected C ADDS A HL Function A lt A HL Skip if carry Adds the data the data memory location addressed by the HL register pair to the contents of the A register in binary then skips the next instruction if the addition generates a carry The carry flag is not affected C gt ADDS XA rp Function XA lt XA rp Skip if carry Adds the contents of register pair rp XA HL DE BC XA
279. r ACKT is set ACKT When set during this period a Caution Do not set the ACKT until the transfer is completed Figure 5 63 Operation of ACKE 1 2 a When ACKE 1 at time of transfer completion The ACK signal is output during the ninth clock cycle AL When 1 at this point b When ACKE is set after transfer completion SCK ef bf lef lof LJ LI VI Li SBO SB1 02 Di Do The ACK signal is output during the first clock cycle ACKE immediately after is set When is set during this period 1 at the falling edge of the next SCK c When ACKE 0 at time of transfer completion SCK 1 2 7 8 9 The ACK signal is not sms X Cor X M AL When ACKE 0 at this point User s Manual U11330EJ2V1UMO00 165 uPD750108 USER S MANUAL Figure 5 63 Operation of ACKE 2 2 d When 1 period is too short The ACK signal is not ACKE gt When is set or cleared during this period and ACKE 0 at the falling edge of SCK Figure 5 64 Operation of ACKD 1 2 a When ACK signal is output during the ninth SCK clock i Transfer start request Transfer start SCK SBO SB1 ACKD SBO SB1 ACKD 166 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 64 Operation of ACKD 2 2 c Clear timing for case where s
280. r are set to 1100B The timer event counter modulo register is set to the following value 30 ms 512 us 58 6 3BH lt Sample program gt SEL MB15 MOV XA 3BH MOV TMODO XA Set the modulo register MOV XA 01001100B MOV TMO XA Set the mode register and start the timer EI Enable an interrupt EI IETO Enable a timer interrupt Remark In this application the TIO pin can be used as an input pin b An interrupt is caused when the number of pulses active high applied to the TIO pin reaches 100 The high order four bits of the timer event counter mode register are set to 0000 to select the rising edge The low order four bits of the timer event counter mode register are set to 1100B The timer event counter modulo register is set to 99 100 1 122 Users Manual U11330EJ2V1UMO0 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS lt Sample program gt SEL MB15 MOV XA 100 1 MOV TMODO XA Set the modulo register MOV XA 00001100B MOV TMO XA Set the mode register EI EI IETO Enable INTTO 5 5 3 Notes on Timer Event Counter Applications 1 Time error at the start of the timer A maximum error of one count pulse CP cycle from a value calculated according to Section 5 5 2 2 occurs in a time period from the start of the timer bit 3 of the TMO is set to the generation of a match signal This is because the count register TO is cleared not in phase with the CP as shown in Figure 5 97 Figure 5 37 E
281. r event counter mode Timer event counter mode register TMn Timer event counter count register Tn Timer event counter modulo register TMODn Timer event counter output enable flag TOEn a Timer event counter mode register TMn When the 8 bit timer event counter mode is used TMn must be set as shown in Figure 5 33 For the format of the TMn see Figures 5 30 and 5 31 The TMn is manipulated by an 8 bit manipulation instruction Bit 3 is a timer start indication bit and can be manipulated bit wise and is automatically cleared to 0 when the timer starts The TMn is cleared to 00H when an internal reset signal is generated Remark 0 1 User s Manual U11330EJ2V1UMO00 117 uPD750108 USER S MANUAL Figure 5 33 Timer Event Counter Mode Register Setup 1 2 a In the case of timer event counter channel 0 Address 7 0 Symbol 6 5 4 3 2 1 FAOH TMO6 TMO5 TMO4 TMOS TMO Count pulse CP selection bit Count pulse CP TIO rising edge TIO falling edge fec 2 fcc 28 fcc 29 fcc 2 Other than above Not to be set Timer start indication bit When 1 is written into the bit the counter and IRQTO flag are cleared If bit 2 is set to 1 count operation is started Operation mode Count operation Stop retention of count contents Count operation 118 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE
282. r subsystem clock specified are used Pin 6 9 CU P33 P30 P33 MD3 P30 MDO connection 23 26 GB 20 CU IC Vpp 38 GB 38 41 CU P43 P40 P43 D3 P40 DO 13 16 GB 34 37 CU P53 P50 P53 D7 P50 D4 8 11 GB Others Noise immunity and noise radiation vary with the circuit scale and mask layout Note 29 fcc 256 us at 2 MHz 512 us at 1 MHz Caution The noise immunity and noise radiation of the PROM model differ from those of the mask ROM model If you replace the PROM model with the ROM model of the course of experimental production to mass production perform thorough evaluation by using the CS model not ES model of the mask ROM model User s Manual U11330EJ2V1UMO00 CHAPTER 1 GENERAL 1 4 BLOCK DIAGRAM Basic interval timer watchdog timer 8 bit timer event counter TOUTO Y INTTO 8 bit timer counter C INTT1 euz os wee K INTW Clocked serial interface PTO1 Interrupt control Notes 1 Program counterNote 1 ROMNete 2 program memory Decode and control data memory 512 x 4 bits Port 0 ti POO Port 1 P10 P13 ti Port 2 ji K T X P20 P23 P30 P33 yt 3 P33 MD3 1 Port 3 P40 P43 40 00 Notes P43 D3 gt P50 P53 Port 4 ji Port 5 Port 6 fcc 2N PUE clock Clock Clock generator Cl
283. ration of four bits per address However the memory can be manipulated in 8 bit units using an 8 bit memory manipulation instruction and in bit units using a bit manipulation instruction Note that an even address must be specified in an 8 bit manipulation instruction Note Memory bank 0 or 1 can be selected as the stack area General register area The general register area can be manipulated with either general register manipulation instructions or memory manipulation instructions Up to eight 4 bit registers are available Of the 8 general registers registers not used by the program can be used as a data area or stack area See Section 4 5 Stack memory area The stack memory area is set by the instruction This area can be used as a save area for subroutine or interrupt execution See Section 4 7 Peripheral hardware area The peripheral hardware area is mapped at addresses F80H to FFFH of memory bank 15 Memory manipulation instructions are used to manipulate the peripheral hardware area as well as the static RAM area Note that however the number of bits to be manipulated at a time varies according to the individual addresses Addresses to which no peripheral hardware is assigned cannot be accessed since such address locations contain no data memory See Figure 3 7 User s Manual U11330EJ2V1UM00 55 uPD750108 USER S MANUAL 4 4 2 Specification of a Data Memory Bank If the memory bank enable flag MBE enables bank specif
284. rea at a given location the SP can be initialized with an 8 bit memory manipulation instruction and the SBS can be initialized with a 4 bit memory manipulation instruction Both can be read from as well When the SP is initialized to 00H a stack operation starts at the high order address nFFH of memory bank n specified with the SBS A stack area must be within the memory bank specified with the SBS If a stack operation exceeds address nOOH the operation returns to address nFFH in the same bank Linear stacking beyond memory bank boundaries is enabled only by resetting the SBS A RESET signal causes the contents of the SP to be undefined and causes the contents of the SBS to be 1000B Remember to initialize the SP and SBS to a desired value at the start of a program Remark 0 1 60 User s Manual U11330EJ2V1UMO00 CHAPTER 4 INTERNAL CPU FUNCTIONS Figure 4 11 Format of Stack Pointer and Stack Bank Select Register Address Symbol ww oor an SBS 000H OFFH 100H 3 1FFH Note The Mk mode and Mk II mode can be switched by bit 3 of SBS The stack bank selection function can be used in both Mk mode and Mk Il mode See Section 4 1 for details Example SP initialization Specify memory bank 1 as a stack area to start stack operation at address 1FFH SEL MOV MOV MOV MOV MB15 or CLR1 MBE A 1 SBS A Specify memory bank 1 as a stack area XA 00H
285. reset signal is generated Figure 8 1 shows the configuration of the reset circuit Figure 8 1 Configuration of Reset Functions RESET Internal reset signal Reset signal from basic interval timer watchdog timer WDTM Internal bus When the RESET signal is generated all hardware is initialized as indicated in Table 8 1 Figure 8 2 shows the reset operation timing Figure 8 2 Reset Operation by Generation of RESET Signal Wait Note i RESET signal is generated Operating mode or standby mode HALT mode Operating mode 3 za Internal reset operation Note 56 fcc 28 us at 2 MHz 56 us at 1 MHz User s Manual U11330EJ2V1UMO00 229 uPD750108 USER S MANUAL Program counter PC Table 8 1 Status of the Hardware after a Reset 1 2 Hardware uPD750104 Generation of a RESET signal in a standby mode 4 low order bits at address 0000H in program memory are set in PC bits 11 to 8 and the data at address 0001H are set in PC bits 7 to O Generation of a RESET signal during operation 4 low order bits at address 0000H in program memory are set in PC bits 11 to 8 and the data at address 0001H are set in PC bits 7 to O uPD750106 uPD750108 5 low order bits at address 0000H in program memory are set in PC bits 12 to 8 and the data at address 0001H are set in PC bits 7 to 0 5 low order bits at address 0000H in program memory are set in PC bits 1
286. rface operation enable disable specification bit W Shift register operation Shift register operation operation Serial clock counter clock counter ROCSI flag ROCSI flag SO SBO and 51 981 pins and SI SB1 SO SBO and 51 981 pins M Shift operation enabled ELIT operation Can be set Used in each mode as well as for port 0 Signal from address comparator R CO Note Condition for being cleared COI 0 Condition for being set COI 1 When the slave address register SVA does not When the slave address register SVA match the data of the shift register matches the data of the shift register Note COI can be read only before serial transfer is started or after serial transfer is completed An undefined value may be read during transfer COI data written by an 8 bit manipulation instruction is ignored Wake up function specification bit W Sets IRQCSI each time serial transfer is completed in each mode Used in the SBI mode only to set IRQCSI only when an address received after bus release matches the data in the slave address register wake up state SBO or SB1 goes to high impedance state Caution When WUP 1 is set during BUSY signal output BUSY is not released In the SBI mode the BUSY signal is output until the next falling edge of the serial clock SCK appears after release of BUSY is directed Before setting WUP 1 be sure to confirm that the SBO or 581 pin is high after releasing B
287. rily c Multiple interrupt function which can specify the priority by the interrupt priority specification register IPS d Test function of an interrupt request flag IRQxxx The software can confirm that an interrupt occurred e Release of the standby mode Interrupts released by an interrupt enable flag can be selected 2 Test functions a Whether test request flags IRQxxx are issued can be checked with software b Release of the standby mode A test source to be released can be selected with test enable flags 6 1 CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT Figure 6 1 shows the configuration of the interrupt control circuit Each hardware item is mapped to a data memory space User s Manual U11330EJ2V1UMO00 187 uPD750108 USER S MANUAL jeuBis qpuels SseJppe 10129A peseeje eq 1ouueo qpueis pejoejes s esiou 204 1 CT 0108 1 ISODUI youl UOHA 015 xxx31 ejgeuo LLSI Sdl gt 1 1dnaa81u jo 2 1 9 y UBYM Jojeulull e SION JON 49 O09d 0H Oc ld cLNl lt
288. rror at the Start of the Timer LI LILI LI LU Li Timer start Timer start 2 Notes on the start of the timer Usually when the timer is started bit 3 of the TMO is set the count register TO and the interrupt request flag IRQTO are cleared However when the timer is placed in the operation mode and the setting of IRQTO and the start of the timer occur at the same time IRQTO may not be cleared This causes no problem if IRQTO is used for a vectored interrupt However if IRQTO is being tested a problem arises because IRQTO is set even if the timer is started Accordingly in a situation where the timer is started on such timing that IRQTO may be set the timer must be restarted after itis once stopped bit 2 of the is cleared to 0 or timer start operation must be performed twice Example The timer is started on such timing that IRQTO may be set SEL MB15 MOV XA 0 MOV TMO XA Stop the timer MOV XA 4CH MOV TMO XA Restart or SEL MB15 SET1 TMO 3 SET1 TMO 3 Restart User s Manual U11330EJ2V1UMO00 123 uPD750108 USER S MANUAL 3 Error in reading the count register The contents of the count register can be read using an 8 bit data memory manipulation instruction at any time During operation by such an instruction all count pulse changes are held not to change the count register This means that if the count pulse signal source is applied to the TIO input as many count pulses as corresponding to the time
289. rtain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electron
290. rtion is supported in Mk Il mode only The other portions are supported in Mk mode only 2 The TBR and TCALL instructions are assembler pseudo instructions to define tables used for GETI instructions User s Manual U11330EJ2V1UMO00 261 uPD750108 USER S MANUAL 11 3 INSTRUCTION CODES OF EACH INSTRUCTION 1 Explanations of the symbols for the instruction codes reg pair gt A X L H rp rp 1 D C Qs Q Qo addressing reg pair 1 In Immediate data for n4 or n8 Dn Immediate data for mem B4 Immediate data for bit Nn Immediate data for n or IExxx Immediate data for taddr x 1 2 An Immediate data for the address 2 to 16 relative to branch destination address minus one 5 Immediate data for the one s complement of the address 15 to 1 relative to the branch destination address 262 User s Manual U11330EJ2V1UMO00 CHAPTER 11 INSTRUCTION SET 2 Bit manipulation addressing instruction codes 1 in the operand field indicates that there are three types of bit manipulation addressing fmem bit pmem L and H mem bit The table below lists the second byte N of an instruction code corresponding to the above addressing Second byte of instruction code Accessible bits fmem bit FBOH FBFH manipulatable bits FFOH FFFH manipulatable bits pmem L FCOH FFFH manipulatable bits H mem bi
291. ruction ee RS Re ORD EL Re OR ee Y 3000H iu D TE A Branch address specified in BRCB Icaddr instruction 3FFFH Note Can be used only in the MkII mode Remark In addition to the above the BR PCDE and BR instructions can cause a branch to an address with only the 8 low order bits of the PC changed User s Manual U11330EJ2V1UMO00 CHAPTER 4 INTERNAL CPU FUNCTIONS 4 4 DATA MEMORY RAM 512 WORDS x 4 BITS The data memory consists of a data area and peripheral hardware area as shown in Figure 4 7 The data memory consists of the following memory banks with each bank made of 256 words x 4 bits Memory banks 0 and 1 data area Memory bank 15 peripheral hardware area 4 4 1 Data Memory Configuration 1 Data area 2 The data area consists of a static RAM and is used for storing program data and as stack memory for subroutine and interrupt execution Battery backup enables the memory to hold data for a long time even if the CPU is stopped in the standby mode The data area can be manipulated with memory manipulation instructions The static RAM is mapped to memory banks 0 and 1 with each made up of 256 words x 4 bits Bank 015 used as a data area but can also be used as a general register area OOOH to 01FH and stack areaNote 000H to 1FFH Whole locations in memory banks 0 1 2 and 3 OOOH to 3FFH can be used as a stack area The static RAM has a configu
292. rupt using this method saves the user the trouble of enabling or disabling interrupts during an interrupt processing and holds down the number of nesting levels to two Figure 6 8 Multiple Interrupt Processing by a High Order Interrupt Normal Low or high order High order processing interrupt processing interrupt Status 0 Status 1 processing Status 2 Interrupt is disabled IPS setting Interrupt is enabled High order interrupt occurrence Low or high order interrupt occurrence User s Manual U11330EJ2V1UMO00 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 2 Multiple interrupt processing by changing the interrupt status flags Changing the interrupt status flags with the program causes multiple interrupts to be enabled That is when the interrupt processing program changes both IST1 and ISTO to 0 status 0 multiple interrupt processing is enabled This method is used when two or more interrupts are to be enabled at a time or when the processing of three or more interrupts is to be performed When changing IST1 and ISTO interrupts must be disabled beforehand with a DI instruction Figure 6 9 Multiple Interrupt Processing by Changing the Interrupt Status Flags Normal processing Single interrupt Dual interrupts status 0 Interrupt is disabled IPS setting Interrupt is Interrupt is enabled disabled Modification of IST Interrupt is enabled Low or high order
293. rvice program MBE 0 VSUB4 SKT BR MOV MOV WAIT SKT BR SKT BR MOV MOV MOV MOV EI EI RETI PDOWN MOV MOV MOV MOV MOV DI DI STOP NOP RETI PORTO O PDOWN A 1101B BTM A IRQBT WAIT 0 PDOWN A 0011B PCC A XA XXH 7 PMGm XA IEO IETO A 0 PCC A XA 00H PMGA XA PMGB XA IEO IETO POO 1 Power down Wait time 32 8 ms Wait for 512 us Chattering check Set high speed mode Set port mode register Lowest speed mode port high impedance Disable INTO and INTTO Set STOP mode User s Manual U11330EJ2V1UMO00 225 uPD750108 USER S MANUAL 2 Application of the HALT mode at fcc 1 MHz Intermittent operation under the following conditions The main system clock is switched to the subsystem clock on the falling edge of INT4 The oscillation of the main system clock is stopped and HALT mode is set n the standby mode intermittent operation is performed at intervals of 0 5 s The subsystem clock is switched back to the main system clock on the rising edge of INT4 INTBT is not used Afterthe STOP mode is released another wait time of 32 8 ms is used for stable power supply operation The POO INT4 pin is checked twice to remove chattering Timing chart gt um MEN nm Voltage on OV POO INT4 Intermittent operation Operating mode Operating mode HALT mode low speed operati
294. s commands and data and to detect busy states when the serial bus is configured with multiple devices Also these processes are too burdensome to be controlled by software The SBI method can configure a serial bus with two signal lines Serial clock SCK and serial data bus SBO or SB1 For this reason the number of ports on a microcontroller can be reduced and the wiring on a circuit board can be simplified SBI functions are described below a Address commandy data identification function Serial data is classified into three types Address command and data b Address based chip select function The master selects a chip for a slave by address transfer c Wake up function A slave can easily check address reception for chip select identification with the wake up function This function can be set or released by software When the wake up function is set an interrupt IRQCSI is generated when a match address is received For this reason in communication with multiple devices a CPU other than a selected slave can operate independently of serial communication d Acknowledge signal ACK control function The acknowledge signal which is used to confirm the reception of serial data can be controlled e Busy signal BUSY control function The busy signal which is used to post the busy state of a slave can be controlled 154 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 2 SBI definition
295. s 1 bit data input or output operations by combining direct 1 bit 4 bit and 8 bit addressing with pmem L addressing In 8 bit manipulation the higher eight bits or lower eight bits are manipulated by specifying BSBO or BSB2 184 User s Manual U11330EJ2V1UM00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Example To output 16 bit data of BUFF1 and BUFF2 serially from bit 0 of port 3 LOOPO LOOP1 LOOP2 CLR1 MOV MOV MOV MOV MOV SKT BR NOP SET1 BR CLR1 NOP NOP INCS BR RET MBE XA BUFF1 BSBO XA Set BSBO and BSB1 XA BUFF2 BSB2 XA Set BSB2 and BSB3 L 0 8580 QL Tests the specification bit of BSB LOOP1 Dummy For timing adjustment PORTS 0 Sets bit 0 of port LOOP2 PORTS 0 Clears bit 0 of port Dummy For timing adjustment L L lt L 1 LOOPO User s Manual U11330EJ2V1UM00 185 uPD750108 USER S MANUAL MEMO 186 User s Manual U11330EJ2V1UMO00 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS The uPD750108 has seven vectored interrupt sources and two test inputs allowing a wide range of applications In addition the interrupt control circuitry of the LPD750108 has the following features for very high speed interrupt processing 1 Interrupt functions a Hardware controlled vectored interrupt function which can control whether or notto accept an interrupt using the interrupt flag IExxx and interrupt master enable flag IME b The interrupt start address can be set arbitra
296. set to 1 SKF mem bit Function Skip if mem bit 0 mem D7 9 OOH FFH bit By 9 0 3 Skips the immediately following instruction if the bit specified by the 2 bit immediate data bit at the address specified by the 8 bit immediate data mem is 0 Function Skip if bit specified in operand 0 Skips the immediately following instruction if the bit in data memory specified by bit manipulation addressing fmem bit pnem L H mem bit is 0 D SKTCLR H mem bit Function Skip if bit specified in operand 1 then clear Skips the immediately following instruction if the bit in data memory specified by bit manipulation addressing fmem bit pmem QL H mem bit is 1 then clears the bit to 0 User s Manual 011330 2 10 00 287 uPD750108 USER S MANUAL C D ANDI CY fmem bit Cc gt AND1 CY pmem L D AND1 CY H mem bit Function CY lt CYA bit specified in operand ANDs the content of the carry flag with the bit in data memory specified by bit manipulation addressing fmem bit pnem L H mem bit then sets the result in the carry flag C D cy tmem bit OR1 CY pmem L C D CY H mem bit Function CY lt bit specified in operand ORs the content of the carry flag with the bit in data memory specified by bit manipulation addressing fmem bit pnem L H mem bit then sets the result in the carry flag XOR1 CY pmem L D xoni CY H mem bit Function CY lt CY
297. signal is generated Table 6 6 shows the signals which set test request flags Table 6 6 Signals Setting Test Request Flags Test request flag Signals setting test request flags Test enable flag Signal from the clock timer Detection of the rising edge of INT2 P12 pin input signal or the first falling edge of the signals input to the KRO P60 to KR7 P73 pins The detection edge is selected with the INT2 edge detection mode register IM2 214 User s Manual U11330EJ2V1UMO00 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 2 INT2 and key interrupt KRO to KR7 hardware Figure 6 10 shows the configuration of INT2 and KRO to KR7 The IRQ2 set signal is output in either of the following edge detection modes which is selected with the INT2 edge detection mode register IM2 a Detection of a rising edge on the INT2 input pin IRQ2 is set when a rising edge is detected on the INT2 input pin b Detection of a falling edge on any of the KRO to KR7 input pins key interrupt One of the pins KRO to KR7 is selected to be used for interrupt input with the INT2 edge detection mode register IM2 When a falling edge of one of input signals applied to the selected pin is detected IRQ2 is set Figure 6 11 shows the format of IM2 IM2 is set using a 4 bit manipulation instruction When the RESET signal is generated all bits are cleared to 0 and the rising edge on INT2 is specified User s Manual U11330EJ2V1UMO00 215 uPD750108 USE
298. sisNote 2 Input buffer PMmn 0 Pull up resistor P 1 pe Bit m of i gt LE Output latch Output buffer Pmn PMmn gt Internal bus Corresponding bits of 3 6 port mode register group n 0to3 Note For port 6n only User s Manual U11330EJ2V1UM00 73 uPD750108 USER S MANUAL Figure 5 5 Configurations of Ports 4 and 5 Pull up resistor Input buffer Mask option 0 4 lt 1 b o e a E R D Pmt Pa Pm2 N ch open drain output buffer Corresponding bits of port mode register group B m 4 5 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 6 Configuration of Port 8 Pull up resistor Bit 0 of E P ch POGB 4 Input buffer 8 0 s 8 1 2 lt Output buffer P80 Ouput latch 24 O P81 Corresponding bit of port mode register group C User s Manual U11330EJ2V1UM00 uPD750108 USER S MANUAL 5 1 2 Mode Setting The I O mode of each I O port is set by the port mode register as shown in Figure 5 7 The I O modes of ports 3 and 6 can be set bit by bit by port mode register group A PMGA The I O modes of p
299. specifies whether to use the built in feedback resistor and controls the drive current of the built in inverter See Figure 5 18 Inputting a RESET signal clears all bits of the SOS register The functions of each flag in the SOS register are described below a SOS 0 feedback resistor cut flag To use the feedback resistor of the subsystem clock the mask option setup and switching SOS 0 by software are required Set SOS 0 to 0 to turn on the feedback circuit When the resonator is not used set SOS 0 to 1 The feedback circuit is turned off reducing the current drain To use the resonator be sure to select Enable the feedback resistor upon setting the mask option Then set 505 0 to 0 feedback circuit is turned on b SOS 1 drive capability switch flag The built in inverter in the subsystem clock oscillator of the uPD750108 subseries has a large drive current because it can be used at low supply voltage 1 8 V so that the supply current becomes too high to use at high supply voltage Vpp 2 2 7 V To reduce the supply current set SOS 1 to 1 so as to reduce the drive current of the inverter However if SOS 1 is set to 1 when Vpp is less than 2 7 V the oscillation may stop for insufficient drive current Set this flag to 0 when Vpp is less than 2 7 V Figure 5 18 Sub Oscillator Control Register SOS Format Address Symbol 3 2 1 0 FCFH o 5081 SOSO SOS Cut flag for feedback resistor of the sub osc
300. ster and slaves 1 The address of a slave with which the master intends to communicate is transmitted to select the slave chip select This starts communication The slave that has received the address returns ACK to engage in communication with the master The state of the slave is changed from the non selected state to selected state 2 Commands and data are transferred between the master and the slave selected in 12 Command and data are transferred between the master and the selected slave on a one to one basis so the other slaves must be placed in the non selected state 3 Communication is completed when the selected slave is placed in the non selected state This state is caused in the following cases The selected slave is placed in the non selected state when the slave receives a RESET command from the master The device that is switched from the master to a slave with a CHGMST command is placed in the non selected state iii Command format The transfer format of each command is described below 1 READ command The READ command reads data from a slave One to 256 bytes of data can be read The data length is specified in a parameter by the master When 00H is specified as the data length the 256 byte data transfer is assumed Figure 5 72 Transfer Format of the READ Command Command Data Data Data Remark M Output by the master S Output by the slave 178 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIP
301. struction used to set the standby mode The interrupt request flag is held b When IME 1 If a standby mode is released a vectored interrupt is executed after the two instructions are executed However if the standby mode is released by INT2 or INTW testable input no vectored interrupt occurs and the same processing as a above is performed 7 4 SELECTION OF A MASK OPTION For the standby function of the uPD750108 the wait time applied when STOP mode is released by interrupt can be set to either of the following by using a mask option 1 29 fcc 256 us at 2 MHz 512 us at 1 MHz 2 No wait The uPD75P01 16 however does have a mask option Its wait time is fixed to 29 User s Manual U11330EJ2V1UMO00 223 uPD750108 USER S MANUAL 7 5 APPLICATIONS OF THE STANDBY MODES When the standby modes are used the following steps are used 1 c2 3 4 5 6 lt 7 gt Detect standby mode setting factor such as power removal on an interrupt input or port input INT4 is useful for power removal detection Configure I O ports for minimum current drain Specify interrupts for releasing a standby mode INT4 is useful All interrupt enable flags not used for release are to be cleared Specify an operation to be performed after release IME is to be manipulated according to whether interrupt processing is performed or not Specify a CPU clock to be used after release
302. t Manipulatable bits of accessible memory bank Bn Immediate data for bit F Immediate data for fmem Low order four bits of address Immediate data for pmem Bits 2 to 5 of address Dn Immediate data for mem Low order four bits of address User s Manual U11330EJ2V1UMO00 263 uPD750108 USER S MANUAL Instruction code Instruction Operand Bo Transfer A n4 reg1 n4 l3 lo lo 1 Ro R4 rp n8 I7 lg l5 lo A rpat XA HL HL A HL XA 00010000 A mem D7 De D5 D4 D3 Do D Do 05 Dg Ds D4 D3 Do D4 0 mem A D7 Dg Ds D4 D3 Do D4 Do mem XA D7 De D5 D4 D3 Do D 0 A reg 0 R2 R4 Ro XA rp P2 P4 Po reg1 A 0 0 0 0 0 0 0 0 0 0 0 Ro R4 Ro rp 1 XA 0 A rpat XA HL P2 P4 Po Q 00010001 A mem D7 De Ds D4 D3 Do D Do jojo XA mem D7 De D5 D4 D3 Do D4 0 A reg1 XA rp 0 1 0 0 0 Pp Py Po Table XA PCDE reference XA PCXA XA BCXA XA BCDE Bit CY transfer 4 264 User s Manual 011330 2 10 00 CHAPTER 11 INSTRUCTION SET Instruction Arithmetic logical Operand Instruction code 0 0 0 0 0 0 0 0 O O
303. t machine and a PROM programmer The IE 75000 R contains emulation board IE 75000 R EM The board is connected to the IE 75000 R IE 75001 R The IE 75001 R is an in circuit emulator used to debug hardware and software when developing an application system using the 75X series and 75XL series Use this emulator together with optional emulation board IE 75300 R EM and emulation probe For efficient debugging connect the emulator to the host machine and a PROM programmer IE 75300 R EM The IE 75300 R EM is an emulation board used to evaluate an application system using the uPD750108 subseries Use this board together with the IE 75000 R or IE 75001 R EP 75008GB R EV 9200G 44 The EP 75008GB R is an emulation probe for the LPD750108GB Connect this emulation probe to the IE 75000 R or IE 75001 R and the IE 75300 R EM A 44 pin conversion socket the EV 9200G 44 supplied with this probe facili tates the connection of the probe to the target system EP 75008CU R The EP 75008CU R is an emulation probe for the PD750108CU Connect this emulation probe to the IE 75000 R or IE 75001 R and the IE 75300 R EM Software IE control program This program enables the host machine to control the IE 75000 R or IE 75001 R through the RS 232 C and Centronics interface Host machine Part number OS Distribution media uS5A13IE75X Ver 3 3010 5 95 inch 2HD Ver 6 2Note 2 uS5A101I
304. ta 4 N ch Output disable TT P U R Pull Up Resistor e P U R Do gt P paa IN OUT Type D O Output disable O lt Type B P U R Pull Up Resistor Type M D vop P U R Maskoption o IN OUT Output Withstand disable HN Input P ch instruction P U R Note Voltage limitation circuit Withstand voltage of 13 V Note Pull up resistor that operates only when an input instruction is executed with no pull up resistor contained by mask option Current flows from to the pins when at low level Voo 20 P U R P U R enable H Po Output disable gt o Rs P gt gt P ch Data Ay Output l N ch disable Output TT disable N ch IN OUT P U R Pull Up Resistor User s Manual Type M E m o IN OUT Output Withstand voltage of disable Voo 13 V av Input P ch instruction P U R Note Voltage limitation circuit Withstand voltage of 13 V Note Pull up resistor that operates only when an input instruction is executed Current flows from to the pins when at low level U11330EJ2V1UM00 CHAPTER 2 PIN FUNCTIONS 2 4 CONNECTION OF UNUSED PINS Table 2 3 Connection of Unused Pins Pin name Recommended connection POO INT4 To b
305. tart of transfer is directed during BUSY Transfer start request SCK 7 8 SCK 6 7 8 9 BSYE When 1 at this point When reset operation is executed during this period and BSYE 0 at the falling edge of SCK lt User s Manual U11330EJ2V1UM00 167 uPD750108 USER S MANUAL pejqeue s eues yey sejeorpu 15 11215 19JSUe4 OIS 0 Byep 0 uononujsul Jo uonnoax3 e 0 73AS8 lt b gt sseJBoJd ui si BuisseooJd esneoeq peigesip si eues yey sejeoipu 5 Las 085 Las 095 uondada sejeoipu 195 S QMOV 195 S OV c L 3M9V lt b gt AOS indjno snououupuAS 1 si 1 5 eves Jaye JO 5 s JejsueJl ees 940Jeq 195 10085 uo indjno jane uBiH Aavau Apeay jeuBis Jaye 95 10 095 uo 1ndjno euss asna jeuBis Asng s enas ejo o MOS euo 185 10 085 uo 1ndino jeuBis JASEN yeubis abpeajmouyoy pueululoo 8 indino Bulag jou 13H eyeq SseJppe si jndjno jeubls 734 194e
306. tents of the RBE can be specified for the interrupt processing by setting the interrupt vector table Therefore as indicated in Table 3 3 by selecting a register bank depending on whether the processing is normal or interrupt the general register need not be saved and restored for the level one interrupt processing and only the RBS needs to be saved and restored for the level two interrupt processing thus speeding up interrupt processing Table 3 3 Recommended Use of Register Banks with Normal Routines and Interrupt Routines Normal processing Use register banks 2 and 3 with RBE 1 Level one interrupt processing Use register bank 0 with RBE 0 Level two interrupt processing Use register bank 1 with RBE 1 In this case the RBS needs to be saved and restored Multiple triple or more interrupt processing Save and restore the registers with PUSH or POP 36 User s Manual U11330EJ2V1UMO00 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Figure 3 4 Example of Register Bank Selection lt Main program gt RB 2 Level one interrupt lt Level two interrupt lt Level three interrupt RBE 0 in the 1 in the 0 in the vector table vector table vector table PUSH BS PUSH rp SEL RB1 POP rp RETI The setting of the RBS can be modified for subroutine processing or interrupt processing by saving or restoring the RBS with the PUSH or POP instruction The RBE is set using the
307. th the data at the next memory address An even address can be specified with mem gt A reg1 Function lt gt regt Exchanges the contents of the A register with register reg1 X H L D E B C XCH XA rp Function XA lt gt rp Exchanges the contents of the XA register pair with the contents of register pair rp XA HL DE BC XA HL DE BC User s Manual U11330EJ2V1UMO00 273 uPD750108 USER S MANUAL 11 4 2 Table Reference Instructions C 7 MOVT xA PCDE Function For the uPD750106 and 0750108 XA lt ROM 12 8 Transfers the low order four bits of the table data in program memory to the A register and the high order four bits to the X register The table data is addressed by the program counter PC with its low order eight bits PCz 9 exchanged with the contents of the DE register pair The table address is determined by the contents of the program counter PC present when this instruction is executed The table area must have necessary data loaded by an assembler pseudo instruction DB instruction The program counter is not affected by the execution of the pseudo instruction This instruction is useful for consecutive table data references Example For the uPD750106 and uPD750108 Remark Program memory 43 0 Table data L Table Table data H address Function in this section is applicable to the uPD750106 and uPD7501
308. the CL1 pin Pin name Function Vpp Voltage is applied to this pin when writing to the program memory or verifying its contents normally Vpp electric potential CL1 CL2 An address update clock used when writing to program memory or verifying its contents is input to the CL1 pin Leave the CL2 pin open MDO to MD3 Operation mode selection pins used when writing to the program memory or verifying its contents DO P40 to D3 P43 low order four bits D4 P50 to D7 P53 high order four bits pins for 8 bit data used when writing to the program memory or verifying its contents Vpp Power voltage is applied to this pin During normal operation 1 8 to 5 5 V should be applied 6 V should be applied when writing to the program memory or verifying its contents Cautions 1 The uPD75P0116CU GB does not have an erasure window so the erasing with ultraviolet radiation cannot be performed 2 Handle the pins not used for writing to or verifying the program memory as follows Pins other than XT2 Connect these pins to Vss through pull down resistors XT2 pin Open User s Manual U11330EJ2V1UMO00 233 uPD750108 USER S MANUAL 9 1 OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORY If 6 V is applied to the Vpp pin and 12 5 V is applied to the Vpp pin the PD75P0116 enters program memory write verify mode The specific operating mode is then selected by the setting of the MDO through
309. the CPU clock When the subsystem clock is selected main system clock generation can be stopped with the SCC In addition the HALT mode can be used but the STOP mode cannot be used Subsystem clock generation cannot be stopped The clock to be supplied to peripheral hardware is produced by frequency dividing the main system clock signal The subsystem clock can directly be supplied only to the clock timer This enables the clock function and the buzzer output function to continue operating even in the standby state When the subsystem clock is selected the clock timer can continue to operate normally The serial interface timer event counter and timer counter can continue to operate when the external clock is selected However other hardware cannot be used when the main system clock is stopped because they operate with the main system clock Notes 1 At 1 MHz 64 us 2 Atfcc 1 MHz 4 8 16 and 64 us User s Manual U11330EJ2V1UM00 87 uPD750108 USER S MANUAL 1 Processor clock control register PCC 88 The PCC is a 4 bit register for selecting a CPU clock with the low order two bits and for controlling the CPU operation mode with the high order two bits see Figure 5 12 When bit 3 or bit 2 is set to 1 the standby mode is set When the standby mode is released by the standby release signal these bits are automatically cleared to return to the normal operation mode See Chapter 7 for details A 4 bit memory
310. the address of the slave to the serial bus After selecting a device to communicate with the master exchanges commands and data with the slave device thus establishing serial communication Figures 5 67 to 5 70 show the timing charts of data communication operations In the SBI mode the shift register performs shift operation on the falling edge of the serial clock SCK Transmit data is held on the SO latch and is output on the SBO P02 or SB1 P03 pin starting with the MSB Receive data applied to the SBO or SB1 pin is latched in the shift register on the rising edge of SCK User s Manual U11330EJ2V1UMO00 171 uPD750108 USER S MANUAL OIS VAS ueuM 5 MOV 1520 aawo aawo aano I 1 I realy indino jes 195 5 eoiep SseJppy uid 185 10 085 YOS J9JSUeJ 15908 jenas 1xeu 104 Buipueu 1 Whe LE BuisseooJd Bursseooud 1 jeues L dNM 921 9g ALIS 0 5 ssoJppy 29 6 4 User s Manual U11330EJ2V1UMO00 172 CHAPTER 5 PERIPHERAL HARDWARE FUNC
311. tion The three wire serial I O mode transfers data with eight bits as one block Data is transferred bit by bit in phase with the serial clock The shift register performs shift operation on the falling edge of the serial clock SCK Send data is latched on the SO latch and is output on the SO pin Receive data applied to the SI pin is latched in the shift register on the rising edge of SCK When eight bits have been transferred shift register operation automatically terminates setting the interrupt request flag IRQCSI 142 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 44 Timing of Three Wire Serial I O Mode SCK D1 QD 2 3 4 5 6 7 8 s cee IRQCSI A Completion of transfer Transfer operation is started in phase with falling edge of SCK Execution of instruction that writes data to SIO Transfer start request When CSIE is set to 1 IRQCSI is automatically cleared to 0 The SO pin becomes a CMOS output and outputs the state of the SO latch So the output state of the SO pin can be manipulated by setting the RELT bit and CMDT bit However this manipulation must not be performed during serial transfer The output level of the SCK pin can be controlled by manipulating the P01 output latch in the output mode internal system clock mode See Section 5 6 8 3 Serial clock selection To select the serial clock manipulate bits 0 and 1 of serial operation
312. tput pins for writing memory PROM P50Note 2 D4 Note 3 N ch open drain 4 bit I O port PORT5 High level when M D Withstand voltage is 13 V in open drain a pull up resistor M E Note 3 P51Note 2 D5 Note 3 mode is provided or A pull up resistor can be provided bit high impedance P52Note 2 D6 Note 3 by bit mask option Note 4 P53Note 2 D7 Note 3 verifying higher 4 bits of program Data input output pins for writing memory PROM P60 KRO Programmable 4 bit I O port PORT6 O Input 61 KR1 I O can be specified bit by bit P62 2 Built in pull up resistors can be P63 connected by software in units of 4 bits P70 KR4 4 bit I O port PORT7 Input F A P71 KR5 jBulilt in pull up resistors can be P72 KR6 connected by software in units of P73 KR7 4 bits P80 2 bit input port PORTS X Input E B P81 Built in pull up resistors can be connected by software in units of 2 bits Notes 1 O circuits enclosed in circles have a Schmitt triggered input 10 2 When pull up resistors that can be specified with the mask option are not incorporated when pins are used as N ch open drain input ports the input leak low current increases when an input instruction or bit operation instruction is executed 3 wPD75P0116 4 Pull up resistors specified with the mask option are not connected to the
313. truction immediately preceding the GETI instruction also has the string effect in the same group the execution of the GETI instruction cancels the string effect and the referenced instruction is not skipped Ifthe instruction immediately following the GETI instruction also has the string effect of the same group the string effect of the referenced instruction remains valid and the next instruction is skipped User s Manual U11330EJ2V1UMO00 301 uPD750108 USER S MANUAL Example MOV HL 00H MOV XA FFH are replaced with instructions CALL 5081 SUB2 ORG 20H HLOO MOV HL 00H XAFF MOV XA FFH CSUB1 TCALL SUB1 BSUB2 TBR SUB2 GET HLOO MOV HL 00H GETI BSUB2 BR SUB2 GETI CSUB1 CALL 5081 GETI XAFF MOV XA FFH 302 User s Manual U11330EJ2V1UMO00 APPENDIX A FUNCTIONS OF THE uPD750008 u PD750108 AND u PD75P0116 1 2 PD 780008 CEN Masked ROM 0000H 1FFFH 8192 x 8 bits One time PROM 0000H 3FFFH 16384 x 8 bits Data memory 000H 1FFH 512 x 4 bits CPU 75XL CPU General purpose register 4 bits x 8 or 8 bits x 4 x 4 banks Main system clock oscillator Crystal ceramic oscillator RC oscillator with external resistor and capacitor Time required for start after reset 217 fy 215 fy selected using a mask option Fixed to 56 Wait time applied when STOP mode is released by
314. ts of SIO disagree with each other the master interrupts data transfer by transmitting a STOP command Figure 5 74 Transfer Format of the STOP Command M S M S Data Data check error occurs Data transfer interruption Remark M Output by the master S Output by the slave When the slave receives a STOP command the slave invalidates the most recently received one byte User s Manual U11330EJ2V1UMO00 179 uPD750108 USER S MANUAL lt 3 gt STATUS command The STATUS command reads the status of the current slave Figure 5 75 Transfer Format of the STATUS Command M S S S Data Command Remark M Output by the master S Output by the slave The slave returns the status in the format shown in Figure 5 78 Figure 5 76 Status Format of the STATUS Command MSB LSB Status Bit indicating whether there is data ready for transmission 0 No transmit data 1 Transmit data of one byte or more Bit indicating whether the device is ready for data reception 0 No receive data storage area 1 Receive data storage area not smaller than one byte is present Bit indicating whether an error occurred 0 No error 1 Error occurred during previous transfer Bit indicating whether master can be changed or not 0 Master cannot be changed 1 Master can be changed When the master receives a status it returns ACK to the current slave 180 User s Manual U11330EJ2V1UMO00 CHAPTER 5 PE
315. tten and is output on the pins When the XCH instruction is executed the output latch data is transferred to the accumulator The contents of the accumulator are latched in the output latches and are output on the pins When the INCS instruction is executed the contents of the output latch incremented by 1 are latched in the output latch and are output on the pins When a bit output instruction is executed the specified bit of the output latch is rewritten and is output on the pin User s Manual U11330EJ2V1UM00 81 uPD750108 USER S MANUAL Instruction SKT SKF lt 1 gt lt 1 gt Table 5 3 Operations by I O Port Manipulation Instructions Port and pin operation Input mode Pin data is tested Output mode Output latch data is tested MOV1 CY lt 1 gt Pin data is transferred to CY Output latch data is transferred to CY AND1 OR1 XOR1 1 1 1 CY CY CY An operation is performed on pin data and CY An operation is performed on output latch data and CY IN IN MOV MOV MOV MOV A PORTn XA PORTn A PORTn XA PORTn A QHL XA HL Pin data is transferred to the accumulator Output latch data is transferred to the accumulator ADDS ADDC SUBS SUBC AND OR XOR A HL A HL A HL A HL A HL A HL A HL An operation is performed on pin data and the accumulator An operation is perfor
316. uPD750108 USER S MANUAL MEMO 238 User s Manual U11330EJ2V1UMO00 CHAPTER 10 MASK OPTION 10 1 The pins of the uPD750108 have the following mask options Table 10 1 Selecting Mask Option of Pin Mask Option E P43 Pull up resistor can be connected in 1 bit units P50 P53 P53 P40 through P43 port 4 or P50 through P53 port 5 can be connected with pull up resistors by mask option The mask option can be specified in 1 bit units If the pull up resistor is connected by mask option port 4 or 5 goes high on reset If the pull up resistor is not connected the port goes into a high impedance state on reset Pull up resistors specified with the mask option are not connected to the uPD75P01 16 10 2 MASK OPTION OF STANDBY FUNCTION The standby function of the 750108 allows you to select wait time by using a mask option The wait time is required for the CPU to return to the normal operation mode after STOP mode has been released by an interrupt for details see Section 7 2 The wait time can be set to either of the following 1 29 fcc 256 us at 2 MHz 512 us at 1 MHz 2 No wait The uPD75P0116 does not have a mask option and its wait time is fixed to 29 fcc User s Manual U11330EJ2V1UMO00 239 uPD750108 USER S MANUAL 10 3 MASK OPTION FOR FEEDBACK RESISTOR OF SUBSYSTEM CLOCK For the subsystem clock of the uPD750108 whether to enable the feedback resistor is selected by the mask option
317. uPD75P0116 User s Manual U11330EJ2V1UMO00 CHAPTER 2 PIN FUNCTIONS Table 2 2 Non Port Pin Functions 1 2 2 Used as the pin for the uwPD75P0116 User s Manual U11330EJ2V1UM00 Also U used Function eae circuit output ds rese typeNote 1 TIO Input P13 Inputs external event pulse to the timer event counter Input B C PTOO Output P20 Timer event counter output Input E B PTO1 P21 Timer counter output PCL P22 Clock output BUZ P23 Arbitrary frequency output for buzzer or system clock trimming SCK 1 Serial clock I O Input P A SO SBO P02 Serial data output or serial data bus I O D B SI SB1 Serial data input or serial data bus I O M C INT4 Input Edge detection vectored interrupt input Either a rising or falling edge is detected INTO Input P10 Edge detection vectored interrupt input Asynchronous Input The edge to be detected is selectable with noise For INTO P10 the noise eliminator eliminator can be selected selectable INT1 P11 Asynchronous INT2 P12 Rising edge detection testable input Asynchronous KRO KR3 Input P60 P63 Falling edge detection testable input Input KR4 KR7 Input P70 P73 Falling edge detection testable input Input CL1 Pin for connecting a resistor or capacitor C for main system clock oscillation Cle
318. underflow that occurs when an arithmetic operation with a carry ADDC SUBC is executed The carry flag functions as a bit accumulator and therefore can be used to store the result of a Boolean algebra operation performed on the CY and a bit at a specified data memory bit address The carry flag is manipulated using special instructions independently of the other PSW bits A RESET signal causes the carry flag to be undefined 64 User s Manual U11330EJ2V1UMO00 CHAPTER 4 INTERNAL CPU FUNCTIONS Table 4 4 Carry Flag Manipulation Instructions Instruction dedicated to carry flag manipulation Instruction mnemonic SET1 CY CLR1 CY NOT1 CY SKT CY Carry flag operation processing Sets CY to 1 Clears CY to 0 Inverts the state of CY Skips if CY is 1 Bit transfer instruction MOV1 mem bit CY MOV1 CY mem bit Transfers the state of CY to a specified bit Transfers the state of a specified bit to CY Bit Boolean instruction AND1 CY mem bit OR1 CY mem bit XOR1 CY mem bit ANDs ORs or XORs CY with a specified bit then sets the result in CY Interrupt handling Remark mem bit represents the following bit addressing fmem bit pmem L H mem bit Interrupt execution Saves CY and all other PSW bits to stack memory in parallel RETI Restores CY together with the other PSW bits from stack memory in parallel Example Bit 3 at address 3FH is ANDed with P33 then th
319. up resistor connected Pull up resistor specification register group A Address Symbol 7 6 5 4 3 2 1 0 espe re me Port 0 PO1 Port 1 P10 P13 Port 2 P20 P23 Port 3 P30 P33 Port 6 P60 P63 Port 7 P70 P73 Pull up resistor specification register group B Address 7 6 Symbol 5 4 3 2 1 0 ON EEX ES E Port 8 P80 P81 5 1 6 I O Timing of Digital Ports Figure 5 9 shows the timing of data output to an output latch and the timing of taking in pin data or output latch data on the internal bus Figure 5 10 shows an ON timing chart when a built in pull up resistor is connected to a port pin by software Figure 5 9 I O Timing Chart of Digital I O Ports 1 2 a When data is input by a 1 machine cycle instruction 1 machine cycle Di 2 instruenon Manipulation instruction execution Input timing gt 84 User s Manual U11330EJ2V1UM00 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 9 I O Timing Chart of Digital I O Ports 2 2 b When data is input by a 2 machine cycle instruction 2 machine cycles d Instruction xn jd uct 9 Manipulation instruction execution Input timing lt gt When data is latched by a 1 machine cycle instruction Manipulation instruction execution Output latch output pin d When data is latched
320. usy enable bit R W 1 The busy signal is automatically disabled 2 Busy signal output is stopped in phase with the falling edge of SCK immediately after clear instruction execution The busy signal is output after the acknowledge signal in phase with the falling edge of SCK User s Manual U11330EJ2V1UMO00 161 uPD750108 USER S MANUAL Acknowledge detection flag R Condition for being cleared ACKD 0 Condition for being set ACKD 1 1 The transfer operation is started The acknowledge signal ACK is detected 2 The RESET signal is entered in phase with the rising edge of SCK Acknowledge enable bit R W Disables automatic output of the acknowledge signal Output by ACKT is possible When set before transfer ACK is output in phase with the 9th clock of SCK When set after transfer ACK is output in phase with SCK immediately following the set instruction execution Acknowledge trigger bit W When set after transfer ACK is output in phase with the next SCK After ACK signal output this bit is automatically cleared to 0 Cautions 1 Never set ACKT to 1 before or during serial transfer 2 ACKT cannot be cleared by software 3 Before setting ACKT set ACKE 0 Command detection flag R Condition for being cleared CMDD 0 Condition for being set CMDD 1 The transfer start instruction is executed The command signal CMD is detected The bus release signa
321. ut Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office
322. utions need to be taken for PW boards with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins itis possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function MS DOS is a trademark of Microsoft Corporation IBM DOS PC AT and PC DOS are trademarks of IBM Corporation User s Manual U11330EJ2V1UMO00
323. with the higher priority and INTTO with the lower priority occur at the same time the processing of the interrupt with the higher priority is started if there is no possibility that an interrupt with the higher priority occurs while another interrupt with the higher priority is processed DI IExx is not necessary 2 When an interrupt with the lower priority occurs while the interrupt with the higher priority is executed the interrupt with the lower priority is kept pending 3 When the interrupt with the higher priority has been processed INTCSI with the higher priority of the pending interrupts is executed 4 When the processing of INTCSI has been completed the pending INTTO is processed 212 User s Manual U11330EJ2V1UMO00 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 7 Enabling of level two interrupts enabling level two INTTO and INTO interrupts with INTCSI and INT4 handled as level one interrupts lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt Main program gt Reset A El E m Status 0 INTCSI service program IE4 i 5 Status 1 CLR1 ISTO Y 1 INTCSI gt DI IECSI A DI 4 Status 0 INTTO service program Status 0 A 3 gt Status 1 4 RETI Status 0 lt 5 gt IECSI RETI When an INTCSI interrupt not allowed to be a level two interrupt occurs the INTCSI
324. x 4 bit manipulation Direct addressing mode specifying mem with MBE 0 or MBE 1 MBS 15 Register indirect addressing mode specifying HL with MBE 1 MBS 15 All hardware allowing 4 bit manipulation 8 bit manipulation Direct addressing mode specifying mem even address with MBE 0 or MBE 1 MBS 15 Register indirect addressing mode specifying HL with the L register containing an even number with MBE 1 and MBS 15 Figure 3 7 summarizes the I O map of the uPD750108 The items in the figure have the following meanings All hardware allowing 8 bit manipulation Symbol Name representing incorporated hardware which can be coded in the operand field of an instruction R W Indicates whether the hardware allows read write operation R W Both read and write operations possible R Read only W Write only Number of manipulatable bits Indicates the number of bits that can be processed at a time in hardware manipulation O Bit manipulation is possible in units of the indicated number of bits 1 4 or 8 bits A Particular bits can be manipulated For these bits see Remarks Bit manipulation is impossible in units of the indicated number of bits 1 4 or 8 bits Bit manipulation addressing Bit manipulation addressing applicable in hardware bit manipulation Users Manual U11330EJ2V1UMO00 41 uPD750108 USER S MANUAL 42 Figure 3 7 uPD750108 I O Map 1 5
325. y time regardless of MBE setting Before ISTO or IST1 is manipulated the DI instruction must be executed to disable interrupts then the El instruction must be executed to enable interrupts IST1 and ISTO as well as the other PSW bits are saved in the stack memory when an interrupt is accepted and the status of ISTO and IST1 changes to a status one level higher When a RETI instruction is executed the former values of IST1 and ISTO are resumed Inputting a RESET signal clears the content of the flag to 0 Table 6 3 Interrupt Processing Statuses of ISTO and IST1 Processing Interrupts that After acceptance can be accepted IST1 ISTO status CPU operation Status 0 Is processing the normal program All Status 1 Is processing a low or high order Only high order interrupt interrupts Status 2 Is processing a high order interrupt No Not to be set 198 User s Manual U11330EJ2V1UMO00 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 6 4 INTERRUPT SEQUENCE When an interrupt occurs it is processed using the procedure shown in Figure 6 7 Figure 6 7 Interrupt Sequence Interrupt INTxxx occurrence IRQxxx setting Hold until IExxx is set Yes Corresponding VRQn occurrence Hold until IME is set Hold until process ing being executed is finished Is VRQn high order interrupt No No Note 1 IST1 0 2 00 or 01 Note 1 IST1 0 2 00

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