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MC68F333 Flash EEPROM Programming Utilities

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1. lib ipd inc BD32 call code definitions lib M68F333 inc M68F333 device constants BD32 return error codes see file BULK MSG for associated text UsageError equ T Usaget BulkError equ 2 error programming data ExcepError equ 3 unhandled exception PassError equ 4 erase successful 32 call return codes see bd32 file BD32 DOC SRecS9 equ 2 S9 Record end of file zd General constants ErasedValue equ Sffff erased state of EEPROM sup prog equ 6 supervisor program space code Flash control register constants FEEMCR flashdis equ 90c0 Module DISABLED disable VFPE in BDM no boot unrestricted space 2 cycle access flashen equ 10c0 Module ENABLED disable VFPE in BDM no boot unrestricted space 2 cycle access FEECTL erase on equ 7 Erase VFPE enabled VEPE ERAS LAT ENPE set erase_off equ 6 Erase VFPE disabled VFPE ERAS LAT set norm equ 0 No programming erase All cleared Variable area section data des T Bulk start address add load offset ds 1 30 Stack area initial stack pointer stack odSize ded 0 Module size odAddress slo mM A 0 Module address StartAddress dc 1 0 Start array address Error ds w 1 error code i sm m AN1255 D MOTOROLA 25 Era_shadow dc w 9B00 0000 SFFFF S EO000 erased shadow register mask dc w 0000 5 0000 0000 0000 used f
2. move w S42cf Sfffa00 SMCR move w S7 08 fffa04 T SYPCR move w 0006 Sfffa20 FR SYPCR move w 0000 fffale ie PFPAR move w 0000 Sfffa4A Tf CSORBT move w S0000 fffa4E 1 CSORO move w 0000 fffa76 ny CSOR10 bsr sciinit MAIN ROUTINE bsr clrscrn clear screen loop bsr home home cursor bsr printstring Print 1st frame dc b 1 x CR LF desb flash EEPROM boot demo CR LF deb SPR Eo 3 o ST ER ELE O bsr home home cursor bsr printstring Print 2nd frame dc b Vx CR LF dc b flash EEPROM boot demo CR LE dc b ok CR LF 0 bsr home home cursor bsr printstring Print 3rd frame dc b CR LF dc b flash EEPROM boot demo CR LF ni is CR LF 0 bra loop and loop KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KK KKK KK KK PRINTCHAR Entry a Output a single character to SCI serial port Character in DO Registers B15 of DO cleared only Ck Ck ck ck Ck ck ck Ck ck ck Ck Ck Ck Sk KKK KKK KKK KKK KK KKK KKK ck kk ck kk kk ck kk ck kk kk ko Sk Sk ko Sk ko ko ko ko k ckck kk o KK f 0 SfffcOC TDRE of SCSR printchar btst Ready for transmit beq printchar loop if not move w dO fffc0e Send data to SCDR rts KKK KKK KKK KKK KKK KKK KK KKK KKK KK KKK KKK KKK KKK KKK KKK KK KKK KKK KKK KKK kk KKK
3. Execution start of driver BULK ig Entry from BD32 d0 number of driver parameters a0 address of parameter array x a5 driver offset address ck ck Ck ck ck 0k ck Ck ck ck Ck Ck kk ck Ck ck ck Ck ck kk ck Ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ko ck kk ck Sk Sk ko Sk kv Mk ko ko ko ko Bulk x Exception handler initialisation lea 1 vectable PC al get start of vector table movea l al a2 working loop copy lea 1 excep h PC a3 get address of handler move w S 0c dl initialise copy loop vecloop move l a3 82 build new vector table dbf dl vecloop movec l al vbr set up vbr for new table a SP and general register initialisation lea 1 stack A5 a7 set up stack lea 1 stack PC a7 set up stack move l a0 a2 get argv into a2 move l d0 d2 get argc into d2 E Print signon and warning message bsr Print print signon message deb M68F333 Flash EEPROM Bulk Eraser Version 2 0 13 10 0 Check command line cmpi 2 32 argc 2 beq Bulk 1 move UsageError Error A5 arg count is wrong bra Bulk end is Get module parameter and use to set up ModAddress Bulk 1 move l FER 1 ModAddress a5 assume 16K module initially move l FEE SIZE 1 ModSize a5 addq 1 4 a2 Skip over program name move l a2 a0 get address of parameter move b a0 d0 get two bytes of parameter asl w 8 d0 data in buffer may not be mov
4. PRINTSTRING Output a string of characters to serial port defined by routine printchar A Entry Character string resides at return PC address ie after bsr printstring command charcter string is terminated by null 00 a Exit Program returns to word location after string ud end no registers modified Registers Stack return address modified ck ck Ck ck ck Ck ck Ck ck ck Ck ck kk ck Ck ck ck Ck ck Ck ck ck ck ck Sk ck ck Ck ck ck ck KKK ck ck ck ck ck ck kk ck ko ck kk ck Ck ck ko Sk Sk Mk Sk kv kx ko ko ko ko ko KK printstring movem l a0 d0 a7 Preserve a0 d0 move l 8 a7 a0 get return PC address of string moveq 1 0 d0 clear all of d0 psloop move b a0 d0 get a char to print beq psnull finish if null bsr printchar bra psloop and loop psnull 5 ensure return PC is word aligned move l a0 d0 btst 0 d0 beq psok Already word aligned so continue addq 1 1 d0 not aligned so adjust MOTOROLA 38 AN1255 D psok move l d0 8 a7 Update return PC movem l a7 a0 d0 Recover a0 d0 rts Ck Ck ck ck Ck ck ck Ck ck ck kk Ck Sk ck Ck Sk ck Ck KKK KKK ck kk Ck kk Ck ck ck kk ck kk kk Sk kk ck kk ck kk ck ko ko Sk kc ko ko ko kc KK KK KK CLRSCRN Clear screen by sending clear screen escapet K sequence d Registers A0 D0 modified ck ck Ck ck ck 0k ck Ck ck ck Ck ck kk ck Ck ck ck Ck ck Ck ck ck ck ck ck ck ck ck ck ck ck KKK ck ck ck ck ck ck ck ck ck ko ck kk ck ko ck ko ko ck Mk
5. Set the ENPE bit in FEExCTL This applies the erase voltage to the array Delay the proper amount of time for one erase pulse Delay is specified by parameter tepx Clear the ENPE bit in FEExCTL This turns off erase voltage to the array Delay while high voltage to array is turned off Delay is specified by parameter ter Read the entire array and control block to ensure all locations are erased o NO OPW If all locations are not erased calculate a new value for tei x pulse number and repeat steps 3 through 10 until all locations erase or the maximum number of pulses has been applied 10 If all locations are erased calculate the erase margin m and repeat steps 3 through 10 for the single margin pulse 11 Clear the LAT and ERAS bits in FEExCTL This allows normal access to the flash 12 Reduce voltage applied to the pin to normal read level PR SEES MOTOROLA AN1255 D 10 INCREASE TO 1 PROGRAM ERASE VERIFY LEVEL r SET ENPE CLEAR ny COUNTER 2 Y SET LAT 3 CLEAR ERAS Y WRITE DATA TO ADDRESS Y Y START PROGRAM PULSE TIMER Y DELAY FOR pui CLEAR ENPE START t TIMER Y DELAY FOR tp MARGIN FLAG SET N INCREMENT npp COUNTER READ LOCATION TO VERIFY DATA CORRECT LOCATION FAILED TO PR
6. Object file DEMOR O Object file format Motorola S records ck ck Ck ck ck ck ck 0k ck ck Ck ck ck ck ck Ck ck ck Ck ck Ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ckock ck ocko ck Ck ock ck ck ck ko ck ok kx kx KKK ko ko ko 7 16K flash module register bank org SFFF800 dc w 0200 FEEIMCR STOP 0 i BOOT 0 LOCK 0 ASPC 10 org FFF804 dc w 0000 FEEIBAH dc w 0000 FEE1LBAL Base addr 0000 range 0000 4000 org SFFF810 dc 1 0010fffe FEE1BS0 1 Reset SP and PC dcl 00001000 FEE1BS2 3 end E H AN1255 D MOTOROLA 39 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK DEMOR boot program for the 16K Flash array to be used with the array file DEMOA Source file DEMOR S62 Object file DEMOR O Object file format Motorola S records ck ck Ck ck ck 0k ck Ck ck ck Ck ck ck ck ck Ck ck ck Ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck Ck ck ck ck ck ck Ck ck ck ck ck ck KKK ck ko ck ck ck ock ck cock kk ck ko k kk ck ko Sk ko kx kv Mk ko ko ko 16K Flash module register bank org SFFF800 dc w 0200 FEEIMCR STOP 0 BOOT 0 LOCK 0 ASPC 10 org SFFF804 dc w 0000 FEEIBAH dc w 0000 FEE1BAL Base addr 0000 b range 0000 4000 org SFFF810 de l 0010fffe FEE1BSO 1 Reset SP and PC del 000
7. BD_FCLOSE d0 bgnd rts KKK KKK KKK KKK KKK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KKK KKK KKK ck ck ko Sk KKK KKK KKK Eval valuates numeric string Entry string address in a0 Exit result in D1 error flag in DO ck ck Ck ck ck 0k ck Ck ck ck Ck ck kk ck Sk ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck kk ck ko ck ko ko ck Pk Sk Mk kx kv Mk ko ko ko oko Eval moveq l BD_EVAL d0 bgnd tst do rts KKK KKK ck Ck ck KKK KK KKK KKK KKK KKK KK KKK KKK KKK KK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK ko ko ko KKK fopen performs file open routine Entry filename pointer in AO m file mode pointer in A1 Exit file pointer in DO ck ck Ck ck ck Ck ck Ck ck ck Ck ck ck ck ck Ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck kk ck ck ck ko ko ck ko Sk Mk kx kv Mk ko ko kokok fopen moveq l BD_FOPEN d0 bgnd ECS KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK FindStrEnd searches an ASCII string for end of string marker null 0 char Entry string pointed to by AO Exit returns a0 pointing to end of string marker ck ck Ck ck ck 0k ck Ck ck ck Ck Ck kk ck ck ck ck ck ck ck ck ck Ck ck ck ck ck Ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck KK c
8. EEPROM Module Configuration Register YFF 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STOP FRZ 0 BOOT LOCK ASPC WAIT 0 0 0 0 0 0 RESET SB 0 0 SB SB 0 SB SB 0 0 0 0 0 0 STOP Stop Mode Control 0 Normal operation 1 Low power stop operation Setting the STOP bit places the module in low power stop mode The EEPROM array is inaccessible during low power stop The array can be re enabled by clearing STOP If STOP is set during program ming or erasing program erase voltage is automatically turned off However when this is done the en able programming erase bit ENPE in the FEECTL remains set Unless ENPE is cleared program erase voltage is automatically reapplied when STOP is cleared Since the default state of the STOP bit out of reset is determined by the value stored in the shadow MCR it is possible for the module to come out of reset in low power mode The reset state of the STOP bit can also be affected by reset mode selection Refer to the integration module section of the appro priate device user s manual for more information FRZ Freeze Mode Control 0 Disable program erase voltage while FREEZE is asserted 1 Allow ENPE bit to turn on the program erase voltage while FREEZE signal is asserted FRZ determines the response of the FLASH module to assertion of the FREEZE signal by the CPU When FRZ 0 the program erase voltage is disabled while FREEZE is asserted When FRZ 1 the ENPE bit in the FEECTL can turn on
9. FEEIMCR etc kk ck ck ck ck Ck ck ck Ck ck kk ck Sk ck ck KKK KKK KKK KKK KKK ck Ck ck KK KKK KKK KKK ck kk ko kk Ck kk kk ck kk ko kk KKK Sk kc kc KKK KKK Include files lib ipd inc BD32 call code definitions lib M68F333 inc 68F333 device constants i BD32 return error codes see file PROG MSG for associated text UsageError equ 1 Usage FileError equ 2 Error opening file EvalErrorl equ 3 Error evaluating start address EvalError2 equ 4 Error evaluating end address SRecError equ 4 Starting value for SRec errors SRecEOFError equ 5 Reached EOF on input file SRecS9Error equ 6 S9 read not an error SRecChecksum equ 7 Checksum error in record SRecFormat equ 8 Format error in S record file ProgError equ 9 Error programming data ExcepError equ 10 Unhandled exception error ProgdOK equ 11 Good return value programmed OK EC QE MOTOROLA AN1255 D 14 32 call return codes see bd32 file BD32 DOC SRecS9 equ 2 ReadSRecord call S9 Record read end of file B Flash control register constants i FEEMCR flashdis equ 90c0 odule DISABLED disable VFPE in BDM no boot unrestricted space 2 cycle access flashen equ 10c0 odule ENABLED disable VFPE in BDM no boot unrestricted space 2 cycle
10. KKK KKK KKK KKK KK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK usedelay programmable software delay loop Entry delay in us approximate stored in dl legal values are 2 65535 Exit dl corrupted Environment timings assume 2 clock program memory access and 16 778MHz clckout frequency KKKKKKKKKKKKKKKKKKKKKKKKKKKK II II II II SII II I III I I Sk I I SI kk Ik Sk Sk kk Sk Sk Sk Sk Sk Sk Sk Sk Sk Sk Sk kk ko ko ko jsr usdelay 13 usdelay subq 2 d01 2 adjust for overhead asl 1 d1 6 multiply count by 2 for us loop tst d1 2 dbf dl loop 6 rts 12 KEK KKK KKK KKK KKK KKK KKK KKK KK KKK KKK KKK ck ck ck KKK KKK KKK KKK KKK KK KKK KKK ko ck kk ck Pk Sk KKK KKK KKK check address searches through valid flash address ranges to find which array is being accessed and therefore x which set of control registers to use bi Note flash register ranges are tested first as they have priority over an array that is mapped to the same address Entry AO contains address to be programmed Exit Al contains start address of register bank or 0 if no valid flash module found for adress ck ck Ck ck ck 0k ck Ck ck ck Ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck KKK KKK ko ck kk ck ko Sk ko kx kv Mk ko ko kokok check address movem
11. ProgdOK Error A5 initialise successful return value rts done return no error KKK KKK KKK KKK KK KKK KKK KKK KK KKK KKK KKK KKK KKK KK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK ko ko ko KKK ProgRecord programs data from S record buffer into EEPROM loops through the record retrieving each byte word and programming it at the specified S record address OffsetAddr x IF ModeAddr 1 OffsetAddr is calculated so that OffsetAddr S record address StartAddress where StartAddress is user specified and ModeAddr is then cleared Entry no parameters assumes S Record is in buffer Exit d0 is difference between data and EEPROM location this will be 0 if programmed successfully a0 will contain address at which program failed d5 will be non zero if byte program 0 if word program Ck CK kk Sk SII I I SI II II I II II II II SII II II II II SII III III I I I I kk I Sk kk kk Sk kk Sk Sk Sk Sk Sk Sk Sk Sk Sk Sk kk ko ko ko ProgRecord movem l al a2 d6 a7 save working registers lea 1 buffer A5 a2 point to S record buffer Cael d6 move b a2 d6 get record type beq prog good record type 0 header m em AN1255 D MOTOROLA 21 exit as no data to program cmpi b 7 d6 bcs prog start record type 1 2 or 3 code data 5 start programming bra prog_good record type gt 3 not code data ex
12. Sk kv kx ko ko ko ko ko KK clrscrn bsr printstring Clear Screen escape sequenc desp ESC 2 Jg 0 90 ESC 2 J rts Ck Ck ck ck kk ck Ck ck ck kk ck Sk KKK ck Ck KKK ck kk ck kk Ck kk kk ck kk ck kk kk ck kk ck kk ck kk Sk Sk ko kc k kc kckock KKKKKK b HOME Move cursor to home position home escape sequenc Registers A0 D0 modified ck ck Ck ck ck ck ck 0k ck ck Ck ck ck ck ck Ck ck ck Ck ck Ck ck ck ck ck Ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ock kk ck kk ck ko ck Pk Sk ck Mk Sk kv kx ko kx ko home bsr printstring Home escape sequenc dc b ESQ 50190 ESC OH rts KKK KKK ck Ck KKK KKK KKK KKK KKK KKK KK KKK KKK KKK KKK KEK KKK KKK KKK KKK KKK KKK KKK KKK m SCIINIT SCI initialisation ck ck Ck ck ck Ck ck Ck ck ck Ck ck ck ck ck Ck ck ck Ck ck Sk ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ko ck ck Sk ck ko Sk ck kx kx kv Sk ko ko ko Sciinit move w 0001 fffc00 Initialize QMCR move w S000f Sfffc04 QILR move w S00f0 Sfffc14 QPDR move w 4 0000 Sfffc16 QPAR move w 0037 Sfffc08 SCCRO move w S000c Sfffc0a SCCR1 rts end Ck Ck ck ck kk ck Ck ck ck kk Ck Sk ck Ck Sk ck Ck KKK KKK KK KKK KKK KK KKK KKK ck kk ck kk ck kk KKK kk Sk kk ck kk Sk Sk Sk Sk kc k ko KKK KKK DEMOR boot program for the 16K flash array to be used with the array file DEMOA Source file DEMOR 562
13. a0 Entry a0 should contain register start address Exit if verified blank d0 0 else d0 1 x dl fault data and a0 fault address Ck ck Ck ck ck 0k ck Ck ck ck Ck Ck kk ck kc ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ko ck kk ck Pk Sk Mk kx kv Mk ko ko ko oko check regs movem l d2 d3 al a2 a7 preserve registers move l ModAddress a5 a0 get module address into a0 move l a0 a2 use a2 as general pointer Check shadow registers against erased values tabl move w 15 31 number of word checks loop cnt lea l Era_shadow a5 al table address in al cr_loop move w a2 d2 get a shadow register value move w d2 d3 store and w al d2 ignore un implemented bits cmp w al d2 and check erased bne cr_bad Q K 7 dbf dl cr loop yes loop if not finished clr l do finished signal blank check OK bra cr_end and return Un erased shadow register found notify and abort cr bad suba l 2 82 get correct fault address move w d3 d1 and fault data move w 1 d0 flag fault cr end move l a2 a0 return fault address if any movem l a7 d2 d3 al a2 restore registers EUS end KKK KKK KKK KKK KK KKK KKK KKK KK KKK KKK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK ko ko ko KKK Bulk msg message file for bulk erase driver KKKKKKKKKKKKKKKKKKKKKKKKKKKK KK KKK KKK KKK KKK KKK KKK KK KKK KKK k
14. access FEECTL latch equ a Enable prog latch prgen equ Sb Enable prog volts shadow equ 2 Read shadow reg norm equ 0 ormal operation Variable area section data Ges Prog start address add load offset buffer ds b 40 space for S record from host ds 1 40 stack area initial stack pointer stack StartAddr ds 1 1 start address parameter odeAddr dc w 0 address mode OffsetAddr dc 1l 0 calculated S record offset FilePtr ds l 1 file pointer FileName ds b 64 file name Error ds w 1 error code KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KK KKK KKK KKK KKK KKK KKK KEK KKK KKK KKK KKK KKK ko ko ko KKK CUSTOM VECTOR TABLE reserved space KKKKKKKKKKKKKKKKKKKKKKKKKKKKKK II SII II III I III I SI I I I Sk kk Sk Sk kk kk Sk Sk Sk Sk Sk Sk Sk Sk Sk Sk Sk kk ko ko ko vectable L3 Alternate vector table ck ck Ck ck ck 0k ck Ck ck ck Ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ko ck kk ck Pk Sk ko Sk kv Mk ko ko kokok EXCEPTION HANDLER ROUTINE Use Quits to BD32 with unhandled exception error code d Exception handling is included because many user errors k mapping of flash drivers etc could cause bus errors f line exceptions etc Flash programming voltage is disabled in case exception ocurred during a programming cycle ck ck Ck ck ck 0k ck 0k ck ck Ck Ck kk ck ck ck ck Ck ck k
15. array non blank Ei Blank test shadow registers bsr check regs registers now blank tst b do beq db 2 i Array and or registers not blank db q cmpi w nep d2 used max pulses k nep bcs db 1 no continue Fail so print error message and quit move w norm FEECTL al yes flag and quit bsr Print deb 13 10 bulk erase failed address 0 move l a0 d0 print address bsr ltoh bsr crlt move w 1 d0 flag error in d0 bra db end AN1255 D MOTOROLA 29 T Erase verifies OK now add erase margin db 2 move w d3 d1 erase margin time em sum of erase pulses d3 move w erase_on FEECTL al enable prog voltage set ENPE bsr msdelay delay em move w f erase off FEECIL al disable voltage clear ENP move w ter dl delay erase recovery time ter bsr msdelay move w norm FEECTL al normal accesses ely do clear d0 to signal success db end movem l a7 d1 d3 al restore registers pts Ck Ck ck ck Ck ck ck Ck ck ck kk Ck Sk ck C Ck ck Ck ck Ck KKK KKK KKK KKK KKK ck kk ck kk Ck ck ck kk ck kk KKK KKK kk ck kk ck kk Sk ko k Sk kc k ko ko ko kokok Initialize initialize routine is called by BD32 before bulk erasing initialize main flash registers i in
16. associated bits in shadow registers The values of the shadow bits determine the reset states of the control register bits In subsequent register diagrams bits with reset states determined by shadow bits are shaded and the reset state is annotated SB Shadow registers are programmed or erased in the same manner as a location in the array using the address of the correspond ing control registers When a shadow register is programmed the data is not written to the corresponding control register the new data is not copied into the control register until the next reset The contents of shadow registers are erased when the array is erased EXE A A wee ee ee MOTOROLA AN1255 D 2 Configuration information is specified and programmed independently of the array After reset registers in the control block that contain writable bits can be modified Writes to these registers do not affect the asso ciated shadow register Certain registers can be written only when the LOCK bit in the FEEMCR is disabled or when the STOP bit in the FEEMCR is set Module Configuration Register FLASH module configuration registers FEEMCR control module configuration This register can be written only when the control block is not write locked when LOCK 0 All active fields and bits in the MCR take values from the associated shadow register during reset FEEMCR Flash
17. base address registers FEEBAH and FEEBAL and the flash EEPROM control register FEECTL Four additional flash EEPROM words in the control block can contain bootstrap information for use during reset Table 1 Flash EEPROM Address Map Access Address Register S YFF 0 Flash EEPROM Module Configuration FEEMCR S YFF 2 Flash EEPROM Test Register FEETST S YFF 4 Flash EEPROM Base Address High FEEBAH S YFF 6 Flash EEPROM Base Address Low FEEBAL S YFF 8 Flash EEPROM Control Register FEECTL S YFF A RESERVED S YFF C RESERVED S YFF E RESERVED S YFF 0 Flash EEPROM Bootstrap Word 0 FEEBSO S YFF 2 Flash EEPROM Bootstrap Word 1 FEEBS1 S YFF 4 Flash EEPROM Bootstrap Word 2 FEEBS2 S YFF 6 Flash EEPROM Bootstrap Word 3 FEEBS3 S YFF 8 RESERVED S YFF A RESERVED S YFF C RESERVED S YFF E RESERVED In the address map Y M111 where M represents the state of the MODMAP MM bit in the system inte gration module configuration register MM defines the MSB ADDR23 of the IMB address for MCU module MM can be written only once after reset An S in the access column indicates registers are located in su pervisor data space In M68300 family devices access to supervisor space can be restricted but M68HC16 devices operate only in supervisor space see the respective CPU reference manuals for more information A number of control register bits have
18. ck ck KK ko ck kk ck Pk Sk Mk kx kv Mk ko ko ko ko FindStrEnd move w d0 a7 push temp register moveq 1 d0 max loop count 1st time thru FSE 1 tst b 80 byte 0 dbeq dO FSE 1 uses loop mode bne FSE 1 loop till test true subq 1 1 a0 decrement address reg move w a7 d0 restore register rts Ck Ck ck ck Ck ck ck Ck ck ck Ck ck Ck Sk ck Ck Sk ck Ck KKK ck kk KK KKK KKK ck kk ck kk ck kk kk ck kk KKK Ck kk kk ck kk ck kk ck kk ko kc k Sk kv kc k ko ko kokok ntoh prints hex value of register DO least sig nibble to screen Entry DO contains nibble value Exit all registers preserved ck ck Ck ck ck 0k ck Ck ck ck Ck ck kk ck Ck ck ck Ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck KKK ko ck ko ko ck Sk Sk Mk kx kv kx ko ko kokok ntoh movem 1 d0 d1 a7 move b d0 dl andi w Sf dl addi b 0 dl cmpi b 10 0O dl bcs nt 1 addi b A 9 1 dl HeT moveq BD_PUTCHAR dO bgnd movem l a7 4 d0 d1 rts Ck Ck ck ck Ck ck ck Ck ck ck kk Ck Sk KKK KKK ck Ck KKK KKK KKK KKK KKK KK KKK KKK ck kk ck kk kk ck Ck ck Sk kk ck kk Sk kk KKK Sk kv ko KKK kokok ptoh prints hex value of byte register DO to screen Entry DO contains byte value Exit all registers preserved ck ck Ck ck ck 0k ck 0k ck ck Ck ck ck ck KKK ck Ck ck ck ck ck KK ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ck ck kk ck ck ck ck ck ck ck ck ck ck ck ck ck ck kk ck ko ck ko k
19. down pulses ri Check still programmed store diff in d0 0 d0 dQ ready to hold byte word diff tst d5 byte or word beq dp verw2 move b a0 d0 byte verify bra dp vertst2 dp verw2 move w a0 d0 word verify dp vertst2 move w t4norm FEECTL al normal flash reads writes bra dp end return programmed data to caller don t need to test x check_address address fail dp_addrfail move w Sff d0 force fail because of bad address a Fail pass termination dp_end bsr dis_both disable both modules rts and quit KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KK KKK KKK KKK KKK KKK KEK KKK KKK KKK KKK KKK KKK KKK Initialize initialize routine is called by BD32 before any programming ii initialize and check main registers d initialize global variables 5 returns non zero in DO if can t continue with programming Exit d0 cleared KEK KKK KKK KKK KKK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK ck ck ck ock ck ko ck kk ck ko Sk KKK KKK KKK Initialize x Initialise modules but leave STOPped El Initialisation module 1 main registers move w flashdis FEEMCR FER 1 STOP module 1 move w 4 FEECTL FER 1 make sure verify mode off Initialisation module 2 main registers move w flashdis FEEMCR FER 2 STOP module 2 move w 4 FEECTL FER 2 make sure verify mode off a Now initialize globals Clr l do no error function return value move
20. equ 7 fclose close disk file BD FREAD equ 8 fread read from disk file BD FWRITE equ 9 fwrite write to disk file BD FTE equ 10 ftell report current pointer position BD FSEEK equ T I fseek seek disk file to given position BD FGETS equ 12 fgets read string from file BD_FPUTS equ 13 fputs write string to file BD EVAL equ 14 val valuate arithmetic expression BD FREADSREC equ 15 read s record end of ipd inc PROGRAMMING ERASURE EXAMPLES The following examples show various program and erase operations In all of the examples keyboard input from the user is shown as bold text Example 1 Programming The FLASH Modules This example shows operations required to program the both 16 kbyte and 48 kbyte flash modules from their erased state Programming data for the shadow registers is in the file TEST1R 0 while programming data for the arrays is in the file ARRAY64 0 First initialize MCU memory resources to allow the driver software to execute In this case the file SRAM HIGH DO is used to configure the on chip TPURAM and SRAM BD32 do sramhigh do The file SRAMHIGH DO initializes the device and terminates by checking that the required memory re sources are responding correctly This is done by writing the first few bytes of TPURAM and SRAM and then reading them back The flash register blocks are also displayed The macro file prints the following results BD32 gt Finished should have TPURA
21. other MCU resources These resources may be 1 FLASH module control register blocks 2 Control registers of other IMB modules 3 Memory required by the driver software The third type of conflict is easily resolved by relocating the driver BD32 macro files provide a convenient way to do this and all other required configuration Two example macro files SRAMHIGH DO and SRAMZ ERO DO are listed and used in the example section The first two conflict types require the array to be remapped However if the LOCK bit is set itis not possible to immediately relocate the array by writing to the base address registers instead the module shadow registers must be reprogrammed so that the array will be mapped to the new address after reset The following procedure also shown in Example 1 avoids possible address conflicts It is recommended for routine programming of a blank FLASH module 1 Program the shadow registers for the required configuration and array address 2 Reset and re initialize the device 3 Program the array Erasing an array which has been programmed this way should not cause problems as the module is never in a programmed state with a conflicting array address range If the array has been mapped to a conflicting address it must be relocated before erasure to avoid an erase fail during the blank check process If the LOCK bit is clear the array can be remapped by writing FEEBAH L otherwise it is necessary toperform steps 1 a
22. program verify circuit The VFPE bit invokes a special program verify circuit During programming sequences ERAS 0 VFPE is used in conjunction with the LAT bit to determine when programming of a location is complete If VFPE and LAT are both set a bit wise exclusive OR of the latched data with the data in the location being programmed occurs when any valid FLASH location is read If the location is completely pro grammed a value of zero is read Any other value indicates that the location is not fully programmed When VFPE is cleared normal reads of valid FLASH locations occur The value of VFPE cannot be changed while ENPE 1 ERAS Erase Control 0 Flash EEPROM configured for programming 1 Flash EEPROM configured for erasure The erase control bit ERAS in FEECTL configures the array for either programming or erasure Setting ERAS causes all locations in the array and all control bits in the control block to be configured for era sure at the same time When the LAT bit is set ERAS also determines whether a read returns the data in the addressed loca tion ERAS 1 or the address itself ERAS 0 ERAS cannot be changed while ENPE 1 E eee AN1255 D MOTOROLA 5 LAT Latch Control 0 Programming latches disabled 1 Programming latches enabled The latch control bit LAT in the FEECTL configures the EEPROM array for normal reads or for pro gramming When LAT is cleared the FLASH module a
23. the program erase voltage while FREEZE is asserted BOOT Boot Control 0 Flash EEPROM module responds to the bootstrap addresses after reset 1 Flash EEPROM module does not respond to the bootstrap addresses after reset On reset the BOOT bit takes on the default value stored in the shadow MCR If BOOT 0 and STOP 0 the module responds to program space accesses to IMB addresses 000000 to 000006 following reset and the contents of FEEBS 3 0 are used as bootstrap vectors After address 000006 is read the module responds normally to control block or array addresses only LOCK Lock Registers 0 Write locking disabled 1 Write locked registers protected When LOCK is set writes to locked registers in the control block have no effect Once set LOCK cannot be cleared until reset occurs The default state of the LOCK bit out of reset is determined by the value stored in the shadow MCR If the default state is zero LOCK can be set once to protect the registers after initialization Once set LOCK cannot be cleared again until another reset occurs When a default reset state of zero is used the initialization routine should set LOCK to prevent inadvertent reconfigu ration of the FLASH module H Y UR C C E r1 AN1255 D MOTOROLA 3 ASPC 1 0 Flash EEPROM Array Space ASPC assigns the array to a particular address space The default state of the ASPC field out of reset is determined by the value stored in the
24. 01000 FEE1BS2 3 end Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries af filiates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such uninten
25. ER 5 ARRAY FAILED TO ERASE REDUCE VFPETO 1 NORMAL READ LEVEL NOTES EXIT ERASE ROUTINE 1 SEE ELECTRICAL CHARACTERISTICS FOR PIN VOLTAGE SEQUENCING FEEPROM PGM FLOW TD 2 THE MARGIN FLAG IS A SOFTWARE DEFINED FLAG THAT INDICATES WHETHER THE PROGRAM SEQUENCE IS GENERATING ERASE PULSES OR MARGIN PULSES Figure 4 Erasure Flow EUER A H UR CREE AN1255 D MOTOROLA 12 DRIVER SOFTWARE Driver Relocatability Because a user can define a driver execution address to be anywhere in the MCU memory map the BD32 driver system requires that driver code be fully relocatable Accesses to variables that are relative to the driver location e g variables within the driver area therefore cannot use absolute addressing Instead use either PC relative addressing or offset addressing using register A6 The latter is possible because BD32 writes A6 with the base address of the driver before the driver code is executed and has the advantage of allowing writes in a single instruction Because the CPU32 regards PC relative addresses as non alterable locations an extra LEA instruction is required when writing a location using this addressing mode Special care is also required when accessing driver parameters as these cannot be guaranteed to be on word boundaries Byte accesses are always used in this case to guarantee correct operation regardless of driver load address and size
26. Eraser Version 2 0 bulk module erased O K The message indicates that the erase is successful The number of periods on the last message line indi cates the number of erase passes used In this instance there is only one An erase failure results in the following message which indicates the first address to fail erase verification As before the number of periods on the last message line indicates the number of erase passes used In this case five passes the maximum number are made before a failure is reported BD32 gt bulk 16 ERIO O LON ot eid aka S EH ote Download completed OK 35 records read M68F333 Flash EEPROM Bulk Eraser Version 2 0 d bulk erase failed address 00000002 bulk bulk erase failed To erase the 48 kbyte array the following command is used BD32 gt bulk 48 5199050 rx tw OE ee E er eene Download completed OK 35 records read M68F333 Flash EEPROM Bulk Eraser Version 2 0 bulk module erased O K The erase is successful with one erase pulse required Disable VEpE if no more operations are required E NEN AN1255 D MOTOROLA 35 Example 3 Attempting To Erase A Conflicting Array When the 16 kbyte array is mapped to its default erased address of F FFFCOOO portions of the array co incide with other MCU register blocks such as the ADC control registers which start at F FFF700 Since
27. Error symptoms A PROG program fail occurs at the first location to be programmed BULK fails to verify blank after the maximum erasure time Tofix apply the correct VEPE supply 5 FLASH module not erased Error symptoms A PROG program fail occurs at the first location which has bits to remain erased at one that are already programmed to zero To fix program to all zeroes bulk erase and reprogram THE DEMO PROGRAM DEMO executes from the MC68F333 16 kbyte flash EEPROM array from reset It displays information on an RS232 terminal connected to the MCU SCI port via a level shifter Apart from the level shifter only internal resources are used with the FLASH TPURAM and SRAM supplying all of the required memory ANSI con trol codes are used to allow cursor movement and screen clearing The software is split into the files DEMOA and DEMOR DEMOA contains the code to be programmed into the flash array DEMOR contains programming data for flash shadow registers flash array mapped to 00000000 flash enabled at reset if reset logic state of DATA15 pin allows and supplies the CPU32 boot information SP 10fffe PC 001000 Example 3 shows how these files are used DEMO Program Code Listing ck ck Ck ck ck 0k ck Ck Ck ck Ck ck ck ck ck ck ck ck ck ck Ck ck ck cock ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck KKK ck ck ck ck ck Ck ck ck ck ck ck ck ok kk ck ck ck ko ck kv kx kx Mk ko ko ko ko ko DEMOA demo boot program for t
28. M 100000 100e00 BD32 gt SRAM 100e00 100fff BD32 gt SSP 100ffe BD32 gt Drivers load 100000 BD32 gt BD32 gt BD32 gt Test read of TPURAM BD32 md 100000 10 00100000 5450 5520 5241 4D20 6D65 6D6F 7279 2020 TPU RAM memory BD32 gt BD32 gt Test read of SRAM BD32 md 100e00 10 00100E00 5352 414D 206D 656D 6F72 7920 2020 2020 SRAM memory BD32 BD32 gt Flash register area BD32 md fff800 40 Yr C c ENT AN1255 D MOTOROLA 33 OOFFF800 9BCO 0000 OOFF C000 0000 0000 0000 0000 zs doo OOFFF810 FFFF FEFFE FFFF FFFF 0000 0000 0000 0000 OOFFF820 9BCO 0000 OOFF 0000 0000 0000 0000 0000 Ne a une OO0FFF830 FFFF FEFE FFFF FFFF 0000 0000 0000 0000 J NOTE Ensure that the supply is enabled before the programming command is entered The base address registers are programmed to ensure that the array is correctly mapped BD32 prog testlr 0 9 100 OSEN dom eto cider x A DR ote p Download completed OK 53 records read M68F333 Flash EEPROM Programmer Version 2 0 prog Programming completed O K At this point the shadow registers are programmed with appropriate values but the MCU must be reset for these to take effect The initialization file SRAMHIGH DO resets the MCU as one of its operations If either of the flash modules have been programmed with the boot option enabled it is best
29. OGRAM SET MARGIN FLAG CLEAR MARGIN FLAG INCREMENT ADDRESS A READ LOCATION TO VERIFY Y 4 DATA CORRECT CLEAR LAT DONE PROGRAMMING NOTES 1 SEE ELECTRICAL CHARACTERISTICS FOR Vepe PIN VOLTAGE SEQUENCING Y REDUCE Vepe TO 1 NORMAL READ LEVEL EXIT PROGRAM ROUTINE 2 THE MARGIN FLAG IS A SOFTWARE DEFINED FLAG THAT INDICATES WHETHER THE PROGRAM SEQUENCE IS GENERATING PROGRAM PULSES OR MARGIN PULSES 3 TO SIMPLIFY THE PROGRAM OPERATION THE Vrpg BIT IN FEEXCTL CAN BE SET 4 CLEAR Vrpg BIT ALSO IF ROUTINE USES THIS FUNCTION Figure 3 Programming Flow FEEPROM PGM FLOW TD GG AN1255 D MOTOROLA 11 REDUCE Vfpg TO 1 PROGRAM ERASE VERIFY LEVEL Y CLEAR ng COUNTER 2 CLEAR MARGIN FLAG Y SET LAT SET ERAS Y WRITE TO ARRAY Or OR CONTROL BLOCK Y SET ENPE Y START ERASE PULSE TIMER tepx Y DELAY FOR tepk CLEAR ENPE START tpr TIMER Y DELAY FOR ty CLEAR LAT MARGIN FLAG SET CALCULATE NEW READ ARRAY AND SHADOW tepk REGISTERS TO VERIFY ERASE CALCULATE EM SET MARGIN FLAG SET fex EM ALL LOCATIONS ERASED INCREMENT nep COUNTER Nep COUNT
30. Order this document by MOTOROLA AN1255 D eee SEMICONDUCTOR mmm APPLICATION NOTE MC68F333 Flash EEPROM Programming Utilities By Mark Maiolani and Mark Weidner INTRODUCTION The MC68F333 modular microcontroller MCU is a member of the M68300 product family The MCU mod ule complement includes a CPUS2 processor a single chip integration module SCIM an 8 channel 10 bit analog to digital converter ADC a time processor unit TPU a queued serial module QSM a 512 byte standby RAM SRAM a 3 5 kbyte RAM with TPU emulation capabilities TPURAM and two flash EE PROM modules FLASH one with a 16 kbyte array and the other with a 48 kbyte array This application note specifically describes software utilities that program and erase the FLASH modules in the MC68F333 but also gives general information that applies to other Motorola modular microcontrollers that incorporate flash EEPROM modules Since the software utilities are device specific code must be modified for other members of the M68300 family and re written for devices in the M68HC16 family Refer to he device user s manual for complete information including timing and voltage parameters The programming and erasure software utilities are drivers for the CPU32 background debugger program BD32 Use of BD32 allows a simple PC interface to be supported without an excessive increase in code size and permits the MCU to be programmed with only an external programming voltage
31. Sk Sk Sk Sk Sk Sk Sk kA Sk ko ko ko prog filename lt start gt program M68F333 flash EEPROM from file prog Usage error prog filename lt start address gt prog Error opening input file prog Error evaluating start address parameter prog prog End of file reached before S7 S8 S9 record was read prog S9 record read file closed normally prog Checksum error in S Record input file prog Format error in S Record input file file is probably not S Records prog Programming error check Vfpe EEPROM is blank prog Unhandled exception encountered prog Programming completed O K rO t AN1255 D MOTOROLA 23 BULK Erasure Driver User Details The BULK driver performs bulk erasure of a single flash EPROM module The syntax used is BULK lt module id gt The argument module id is used to specify the module to be erased The value can be either 16 or 48 to specify the 16 kbyte or 48 kbyte Flash EEPROM modules respectively A series of erasure passes are used Each successive pulse is of progressively longer duration until erasure is verified Each erasure pass is indicated by the printing of a period and if erasure is not verified after the maximum erasure time has been used a bulk fail message is printed along with the address of the first failed location As with the PROG driver the BULK driver does not map the flash
32. addi SRecError 40 otherwise flag error move dO Error A5 bra Prog 3 K Program data from S Record into EEPROM Prog 25 bsr ProgRecord program data from S Record tst do beq Prog 2 loop till done bsr not prog print fault address move ProgError Error A5 error report it x Close input file Prog 3 bsr CloseInputFile close file Report any errors exit back to BD32 Prog end move Error A5 d1 get error code BD_QUIT d0 exit program bgnd ErNMIPRER WM CES MOTOROLA AN1255 D 16 ck ck Ck KKK KKK KKK KKK KK KKK KKK KK KKK KKK KK KK KKK KKK KKK KKK KKK KKK ck ck ck ck KKK ko ck kk ck Pk Sk KKK KKK KKK ReadSRecord reads one S record from FilePtr Exit d0 contains returned status dl corrupted K a0 points to s record buffer kkkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkkxkxkxkxkxkkxkxkxk xkkxkxkxkxkxkxkxkxkxkxkxkxkxkkkkkxxkx k ReadSRecord move w FilePtr A5 dl file pointer lea 1 buffer A5 a0 point to S Record buffer moveq l BD_FREADSREC d0 bgnd rts KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KK KKK KKK ko ko ko KKK CloseInputFil closes FilePtr Exit d0 corrupted k dl corrupted K does not affect Error KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK CloseInputFile move l FilePtr A5 dl moveq l
33. array to a particular address The user must make certain that the array address does not conflict with addresses of other MCU modules causing erasure to fail The array can be relocated either by programming the shadow registers and then resetting the device or by directly reconfiguring the base address registers The base address registers can only be changed when the FLASH module LOCK bit is cleared Software Details The BULK software applies erase pulses of increasing duration until the array and shadow registers verify as erased then a final erase pulse is applied as an erase margin The source files for the BULK driver software are BULK S62 Erase code source file BULK MSG Message text file used by BD32 IPD INC Definitions required for the BD32 system calls M68F333 INC MC68F333 constants definition file including register addresses other flash module information and programming erasure timing data Timing information is compatible with the definitions used in the MC68F333 device specification to simplify updates Common include files used by both drivers are shown after the erasure driver code AN1255 D 24 BULK Driver Listing KKK KKK KKK KKK KKK KKK KKK KKK KK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK ko ck kk ck Pk Sk Mk kx kv KK KKK BULK Resident Command Driver for MC68F333 device Utility to bulk erase an MC68F333 flash EPROM module Source file bulk s62 Object file bul
34. ase address the base address low register FEEBAL contains the low order bits of the address The number of active con trol bits in FEEBAL is determined by the size of the array as shown in Table 4 During reset both FEEBAH and FEEBAL take on default values programmed into associated shadow registers After reset if LOCK 0 and STOP 1 software can write to FEEBAH and FEEBAL to relocate the array EGCERIUCE MEN VRNVCNCNCER Y MOTOROLA AN1255 D 4 FEEBAH Flash EEPROM Base Address High Register YFF 4 15 0 Flash EEPROM Base Address high order bits RESET SB FEEBAL Flash EEPROM Base Address Low Register YFF 6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Flash EEPROM Base Address low order bits RESET 580 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4 FEEBAL Bit Implementation Array Size Bits Used 8 Kbyte 15 13 Up to 16 Kbyte 15 14 Up to 32 Kbyte 15 Up to 64 Kbyte None Flash EEPROM Control Register FLASH control registers FEECTL control programming and erasure of the array FEECTL is accessible in supervisor mode only Refer to EFFECTS of LOCK Bit Operation for more information FEECTL Flash EEPROM Control Register 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 VFPE ERAS LAT ENPE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VFPE Verify Program Erase 0 Normal read cycles 1 Invoke
35. c ck ck ck ck ck ck Ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ok KKK ko ck kk ck ko Sk ko Sk kv Mk ko ko ko ko excep h move w norm FEECTL al normal flash reads writes disable programming voltage move ExcepError Error A5 unhandled excep error bra Prog_end FileMode dc b Wages ous read mode for file open syscall ck ck Ck ck ck 0k ck Ck ck ck Ck Ck kk ck Ck ck ck Ck ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ko ck kk ck ko Sk ko kx kv Mk ko ko KKK Execution start of driver PROG by Entry from BD32 dO number of driver parameters x a0 address of parameter array 85 driver offset address x Useage a7 stack pointer ck ck Ck ck ck 0k ck Ck ck ck Ck ck kk ck kc ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck kk KKK KKK ck ck ck ck ck ck ck ck ck ck ck kk ck ko ck ko ko ck Pk Sk Mk kx kv Mk ko ko ko KK Prog Exception handler initialisation lea 1 vectable PC al get start of vector table movea l al a2 working loop copy lea l excep_h PC a3 get address of handler move w S 0c dl initialise copy loop vecloop move l a3 a2 build new vector table dbf dl vecloop movec l al vbr set up vbr for new table A SP and general register initialisation lea 1 stack A5 a7 set up stack lea 1 stack PC a7 set up stack equivalent move l a0 a2 get argv into a2 m
36. ck ck ck ck ck kk kk kk kk Ck Ce Sk Ck Ck kk CSS CCS Ck Sk kk CK Sk kk kk Sk kk ke Kk x Kk Sk Sk Kk k kc k ck ck ko ko KKK getchar moveq l BD GETCHAR d0 bgnd rts Ck Ck ck ck Ck ck ck Ck ck ck Ck ck Ck Sk ck Ck Sk KKK KKK KKK KK KKK KKK KKK KK KKK KKK ck kk ck kk KKK Ck kk kk Sk kk ck kk Sk kc k Sk kv kc KKK kokok msdelay programmable milliseconds delay Entry delay time in ms in dl x legal values are 1 65535 Exit dl corrupted Note routine calibrated for 16 78MHz clock 2 clock memory ck ck Ck ck ck 0k ck Ck ck ck Ck ck ck ck ck Ck ck ck Ck ck ck ck ck Ck ck kk ck ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ck ck ko ck ck ko ck ko Sk ck Sk Sk Mk kx kv Mk ko ko ko ko msdelay move l d2 a7 preserve d2 subq w 1 d1 compensate for dbcc offset of 1 move w 4 826 d2 initialise inner loop count to x compensate for entry overhead ih OL EE E MOTOROLA AN1255 D 28 loop Est di loop2 tst d2 dbf d2 100p2 move w 82d d2 inner loop count dbf dl loop move l a7 d2 restore d2 rts ck ck Ck ck ck 0k ck 0k ck ck Ck ck kk ck Ck ck ck Ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ck KKK ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ko ck kk ck ko Sk Mk kx kx ko ko ko ko ko Erase bulk erase routine x performs erase algorithm u
37. control registers generally take precedence in the memory map erasure will fail as the erase driver attempts to verify that the array is blank BD32 gt bulk 16 910 00 30 crescentes eR ER Download completed OK 35 records read M68F333 Flash EEPROM Bulk Eraser Version 2 0 bulk unhandled exception encountered The failure indicated is an unhandled exception but the results of any attempt to erase a conflicting array are unpredictable and the operation should be prevented by remapping the array This can be done either by modifying the base address in the FEEBAH and FEEBAL registers if the LOCK bit is cleared or by pro gramming the module shadow registers and resetting the device Erasing the 48 kbyte array at the default address will not normally cause these problems as it is mapped from to FFFFBFFF avoiding other MCU register areas BD32 bulk 48 S800 0 3 0 sess eie hag cates m eo PER ale re ER eee EE Download completed OK 35 records read M68F333 Flash EEPROM Bulk Eraser Version 2 0 bulk module erased O K FINDING ERRORS Following are descriptions of errors that commonly occur during programming or erasure of FLASH mod ules using the BD32 drivers Typical error messages and fixes are given in each case 1 Flash array mapped over the BD32 driver area Error symptoms The driver may hang or terminate with a line F or non documented error To
38. d tst w do programmed O K beq prog 35 quit2 bsr not progd no does user want to quit bne prog done Either programmed O K word or user wishes to continue prog_35 addq l 32 80 increment target address subq 12 d6 dec byte count bne prog 1 loop till byte count 0 prog_good 0 d0 no error prog_done movem l a7 al a2 d6 restore registers rts done A E EE E MOTOROLA AN1255 D 22 KKK KKK ck Ck ck KKK KK KKK KKK KKK KKK KK KKK KKK KK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK not_progd informs user of programming error not blank informs user of blank check error 5 user enters escape to stop any other key to continue programming exit d0 is 0 and Z flag is set if user wants to continue x d0 is non zero and Z flag is clear if user wants to abort ck ck Ck ck ck 0k ck Ck ck ck Ck ck ck ck ck Ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ckck ck ck ck ck ck ck ck ck ck ck ock ck ck ck kk ck ko ck ko ko ck Pk Sk ke kx kx Mk ko ko kockok not progd bsr Print dc b prog program fail at address 0 bra n 1 not blank bsr Print dc b prog EEPROM not blank address 0 n_bl move l a0 d0 print address bsr ltoh bsr Print dc b 13 10 prog Press esc to stop any other to continue 7 0 bsr getchar move d0 a7 save char bsr move a7 d0 get char andi S d0 cmpi 4919 escape s
39. d and the programming data 4 Set the ENPE bit in FEExCTL This starts the program pulse 5 Delay the proper amount of time for one programming pulse to take place Delay is specified by pa rameter PWop Clear the ENPE bit in FEExCTL This stops the program pulse Delay while high voltage to array is turned off Delay is specified by parameter tpr Read the address to verify that it has been programmed o N Oo If the location is not programmed repeat steps 4 through 7 until the location is programmed or until the specified maximum number of program pulses has been reached Maximum number of pulses is specified by parameter 10 If the location is programmed repeat the same number of pulses as required to program the loca tion This provides 10096 program margin 11 Read the address to verify that it remains programmed 12 Clear the LAT bit in FEExCTL This disables the programming address and data latches 13 If more locations are to be programmed repeat steps 2 through 10 14 Reduce voltage applied to the Vgpg pin to normal read level Erasure The following steps are performed to erase the array Figure 4 is a flowchart of erasure operation Increase voltage applied to the Vepg pin to program erase verify level Set the ERAS bit and the LAT bit in FEExCTL This configures the module for erasure Perform a write to any valid address in the control block or array The data written does not matter
40. ddress and data buses are connected to the IMB address and data buses and the module is configured for normal reads When LAT is set module ad dress and data buses are connected to parallel internal latches and the array is configured for program ming or erasing Once LAT is set the next write to a valid FLASH module address causes the programming circuitry to latch both address and data Unless control register shadow bits are to be programmed the write must be to an array address The value of LAT cannot be changed while ENPE 1 ENPE Enable Programming Erase 0 Disable program erase voltage 1 Apply program erase voltage to flash EEPROM Setting the enable programming erasure ENPE bit in FEECTL applies program erase voltage to the array ENPE can be set only after LAT has been set and a write to the data and address latches has occurred ENPE remains cleared if these conditions are not met While ENPE is set the LAT VFPE and ERAS bits cannot be changed and attempts to read an array location are ignored Flash EEPROM Bootstrap Words The bootstrap words FEEBS 3 0 can be used as system bootstrap vectors When the BOOT bit in FEEM CR 1 during reset the FLASH module responds to program space accesses of IMB addresses 000000 to 000006 after reset When BOOT 0 the FLASH module responds only to normal array and register accesses FEEBS 3 0 can be read at any time but the values in the words can only be changed by pro gramming
41. ded or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part MOTOROLA js a registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer How to reach us USA EUROPE Motorola Literature Distribution P O Box 20912 Phoenix Arizona 85036 1 800 441 2447 MFAX RMFAX0 email sps mot com TOUCHTONE 602 244 6609 INTERNET http Design NET com JAPAN Nippon Motorola Ltd Tatsumi SPD JLDC Toshikatsu Otsuki 6F Seibu Butsuryu Center 3 14 2 Tatsumi Koto Ku Tokyo 135 Japan 03 3521 8315 HONG KONG Motorola Semiconductors H K Ltd 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po N T Hong Kong 852 26629298 wm AA MOTOROLA AN1255 D
42. e b a0 d0 word aligned so read 2 bytes EXGFENNMPPZ REC SEES MOTOROLA AN1255 D 26 cmpi w 16 d0 16k array specified beq Bulk11 yes so O K to continue move l FER_2 ModAddress a5 no so first assume 48k move l FEE_SIZE_2 ModSize a5 cmpi w 48 d0 and then verify beq Bulk11 yes so O K to continue move UsageError Error A5 no so flag useage error bra Bulk_end and quit Initialise module and calculate array addresses Bulk11 bsr Initialize init hardware Erase module now bsr Erase tst b do was erase succesful beq Bulk_end move BulkError Error A5 no so flag erase error bra Bulk_end Report any errors exit back to BD32 Bulk end move Error A5 d1 get error code moveq l BD_QUIT d0 exit program bgnd ck ck Ck ck ck 0k ck Ck ck ck Ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ko ck ko ko ck ko Sk ko kx kv Mk ko ko ko ko FindStrEnd searches an ASCII string for end of string marker null 0 char Entry string pointed to by AO Exit returns a0 pointing to end of string marker RS all other registers preserved ck ck Ck ck ck 0k ck Ck ck ck Ck ck ck ck ck Ck ck ck Ck ck ck ck KK ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck KKK ck ck
43. ected to the pin low to minimize diode voltage drop Emu AL MOTOROLA AN1255 D 6 There are a number of interlocks designed to prevent accidental programming or erasure For increased protection raise the Vepe input to programming voltage only immediately prior to issuing a PROG or BULK command and remove programming voltage as soon as the operation is complete 30 ns MAXIMUM 13 5 V ENVELOPE Vpp ENVELOPE E COMBINED Vpp AND Vepg 12 6V 114V 65V 45V 4 0 V 0 30 V POWER NORMAL PROGRAM POWER ON READ ERASE DOWN VERIFY PROG VOLT ENVELOPE Figure 1 Programming Voltage Envelope PROGRAMMING VOLTAGE POWER SUPPLY VY Y R1 10kQ D2 45V V VDD dis R2 22 KQ 1 y 0 1 WF Vepe CIRCUIT Figure 2 Conditioning Circuit AN1255 D MOTOROLA 7 EFFECTS OF LOCK BIT OPERATION FLASH modules can be configured to prohibit access to the base address registers and the module config uration register This capability prevents application failures caused by accidental writes to the registers Access is controlled by the LOCK bit in the module configuration register FEEMCR Because it restricts relocating the array to resolve address conflicts the LOCK bit can also affect program ming and erasing Conflicts arise when the array is mapped to an address range that coincides with the ad dresses of
44. eq do make dO nonzero if so tst do set SR for subsequent test rts KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK not_prog informs user of programming error Entry a0 contains fault address ck ck Ck ck ck 0k ck 0k ck ck Ck ck ck ck KKK ck Ck ck Sk ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck kk ck ck ck ck ck ck ck ck ck ko ck ko ko ck Pk Sk Mk kx kv Mk ko ko kokok not prog bsr Print dc b prog program failed before 0 move l a0 d0 print address bsr ltoh bsr CELE rts KKK KKK KKK KKK KK KKK KKK KK KKK KKK KKK KKK KKK KK KKK KKK KK KKK KKK KKK KKK KKK KKK KK KKK KKK KK KKK dis_both disables both flash EEPROM modules exit no registers modified ck ck Ck ck ck 0k ck Ck ck ck Ck ck kk KKK ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ck KKK ck ck ck ck ck ck kk ck ck ck ck ck ck ck ock ck ko ck ko ko ck Mk Sk ke kx kv Mk ko ko ko ko dis both move w flashdis FEEMCRt FER_1 disable module 1 set STOP move w flashdis FEEMCRt FER_2 disable module 2 set STOP ps end KKK KKK ck Ck ck ck kk Ck Sk ck Ck Sk ck KKK KKK kk KKK KKK KKK KR KKK KKK KKK ck kk Ck kk kk ck kk ck kk ko kk Ck kk kk kk ko ko ko ko KK KKK Prog msg message file for programming driver Ck CK kk kk I II II SII I SII II SII II SII II SII II I III II II II SI Ik I Sk Sk Sk I I kk Ik Ik kk Sk Sk
45. executes these calls by executing a BGND instruction with register DO containing the appropriate fcode value Please refer to the BD32 documentation file BD32 DOC for more information concerning the debugger Eu A P MOTOROLA AN1255 D 8 Table 6 BDM32 Command Summary Name Function fcode Parameters QUIT stop driver execution 0 None PUTS display character string on screen 1 AO address of string PUTCHAR display single character on screen 2 D1 character GETS get string from user CR ends 3 AO address of buffer GETCHAR get single character from user 4 char returned in DO GETSTAT returns char ready not ready status 5 DO non zero if ready FOPEN open disk file on host PC gc ho Ename suing A1 pointer to mode FCLOSE close disk file 7 D1 file handle D1 file handle FREAD read n bytes from disk file 8 D2 byte count AO buffer address D1 file handle FWRITE read n bytes from disk file 9 D2 byte count AO buffer address FTELL return current file pointer pos 10 D1 file handle ks ES D1 file handle FSEEK Seek to position n in disk file 11 D2 offset D1 file handle FGETS read n terminated string from file 12 AO buffer x D1 file handle FPUTS write null terminated string to file 13 AO buffer EVAL evaluate expression from string 14 Cos Sing D1 return value FREADSREC read S record fro
46. ffset used below move l 28 a7 a0 get address of string stacked return address moveq l BD_PUTS d0 function call bgnd bsr FindStrEnd get end of ASCII string move l a0 d0 test for odd address addq 1 1 d0 skip past end of string btst 0 d0 beq Print addq 1 1 d0 it s odd return to next addr Print 1 move l d0 8 a7 update stacked return address movem l a7 d0 a0 get back registers rts done Ck Ck ck ck Ck ck ck Ck ck ck kk Ck Sk ck Ck Sk KKK ck Ck ck ck kk Ck kk KKK KKK kk ck kk ck kk kk ck kk ck kk ko kk kk Sk kk ck kk Sk kk Sk ko k Sk kv k ko ko ko kokok yq prints carriage return line feed combo Exit no registers corrupted ck ck Ck ck ck 0k ck Ck ck ck Ck ck ck ck ck Ck ck ck Ck ck Sk ck ck KK kk ck ck ck ck ck ck ck ck ck Ck ck ck ck KKK ck ck ck ck ck ck Ck ck ck ck ck ck ck ck kk ck ko ck kk ck Pk Sk Mk kx kv Mk ko KKK CELF bsr Print carriage return line feed dc b 13 10 0 0 rts Ck ck ck ck ck ck Ck ck ck kk Ck Sk ck Ck Sk ck Ck KKK KKK KKK Ck Sk ck KK ck kk ck kk KK KKK KK KKK KKK KKK ck kk ko kk Sk kk kk Sk kk kc k kc KK KKK getchar returns character typed by user Exit ck ck Ck ck ck Ck ck Ck ck ck Ck ck kk ck KK KKK KKK KK KKK dO contains character typed KKK ck ck ck Ck ck KKK ck kk Ck kk kk ck kk ck kk kk ck kk ck kk Sk kk Sk ko k Sk KKK KK kokok getchar moveq l Gl ETCHAR dO bgnd rts PSR SEES MOTOROLA AN1255 D 18 KKK KKK KKK KKK KK KKK KKK KKK KKK KK
47. ge For each byte or word to be programmed the PROG utility searches through all of the possible FLASH mod ule addresses to find a match PROG does not initialize the array base addresses before programming so the user must ensure that these are correctly configured When specifying programming data for the shadow registers unimplemented shadow bits must be set to zero to avoid verify errors Registers that may have unimplemented shadow bits are FEEMCR FEEBAH and FEEBAL Make certain that the array address does not overlap registers of the flash EEPROM module or another module See FINDING ERRORS for more detail Software Details The PROG routine applies programming pulses to the flash array until the location verifies as correctly pro grammed A final series of pulses is applied for programming margin The following sequence of steps is used to program the flash EEPROM array m EG Ul AN1255 D MOTOROLA 13 The source files for the PROG driver software are PROG S62 Program code source file PROG MSG Message text file used by BD32 IPD INC Definitions required for the BD32 system calls M68F333 INC MC68F333 constants definition file including register addresses other flash module information and programming erasure timing data Timing information is compatible with the definitions used in the MC68F333 device specification to simplify updates Common include files used by both drivers are shown after the erasure d
48. he 16K flash array to be used with the register file DEMOR Source file DEMOA S62 Object file DEMOA 0 Object file format Motorola S records ck ck Ck ck ck 0k ck 0k Ck ck Ck ck ck Ck ck Ck ck ck Ck ck Ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ck Ck ck ck ck ck ck ck ck kk ck ko ck ko Sk ke Sk kx kv Sk ko ko ko ko Character equates for terminal output ESC equ 1b Escape CR equ 0d Carr return LF equ 0a Line feed CRGT equ 1c Cursor right CLFT equ 1d Y left CUP equ 1e rr up CDN equ S1f M down Ck Ck ck ck ck ck ck Ck ck ck Ck ck KK KKK KKK KK KKK KKK KKK ck kk ck kk ck ck ck kk ck kk ck kk ck kk Ck kk Sk ko kk ck ko KKK KKK m Main code initializes system and displays start up message A Memory map x 000000 004000 16K flash array internal T 010000 010dff 3 5K TPURAM oo 2 010e00 010fff 0 5K SRAM 1 Ck CK ck ck Ck ck ck Ck ck ck Ck ck Ck Sk KKK KKK ck Ck KKK KKK KKK KKK ck kk ck kk kk kk ck ck kk Ck kk Ck kk KKK KKK KKK KKK section text org 1000 start move w 0100 5Sfffb04 TRAMBAR Set TPURAM base address move w 4 0000 Sfffb00 TRAMMCR Unrestricted spac move w S0e00 Sfffb46 SRAMBAL Set SRAM base address move w 4 0001 S fffb44 SRAMBAH move w 4 0000 S fffb40 SRAMMCR Unrestricted not locked move l S010ffe a7 Initialize stack pointer 1 V AN1255 D MOTOROLA 37
49. it as no data to program prog start move b a2 d6 get byte count from s record subi b 4 d6 remove byte count due to address move l a2 a0 get address note BD32 always stores 4 byte address field prog offs cmpi w 1 ModeAddr A5 Should we calculate offset bne prog addoff move l a0 d5 put address in d5 move l StartAddr a5 al Yes get desired start suba l d5 al use to calculate offset move l al OffsetAddr a5 Store clr w ModeAddr A5 Clear mode to signal done prog addoff adda l OffsetAddr a5 a0 add offset to address prog 1 move l a0 d5 store address in d5 andi l 1 d5 mask all but bit 0 bne prog 2 program byte if odd address cmpi 1 d6 count 1 bne prog_3 word program if not program byte data if address is odd or byte count is 1 prog_2 moveq 1 d5 flag byte write move b 42 0 byte get data bsr do_prog program byte word tst w do programmed O K beq prog_25 quitl bsr not progd no does user want to quit bne prog done Either programmed O K byte or user wishes to continue prog 25 addq l1 1 a0 increment target address addq 1 1 a2 increment buffer address subq 1 d6 dec byte count bne prog 1 loop till byte count 0 bra prog_good otherwise done program word data if address is even and byte count not equal to 1 prog_3 move b a2 d0 get word we don t know if asl w 8 d0 data in buffer is word aligned move b a2 d0 So read two bytes bsr do prog program byte wor
50. itialize global variables d returns non zero in DO if can t continue with programming Entry flash module address register block in ModAddress a5 Exit d0 cleared all other CPU registers preserved flash array address written to StartAddress a5 ck ck Ck ck ck 0k ck Ck ck ck Ck ck ck ck ck kc ck Ck ck kk ck KK ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck kk ck Ck ck ck ck ck kk ck ko ck ko ko ck Sk Sk kv kx kv Mk ko ko kokok Initialize movem l a3 a4 a7 preserve registers Initialise modules but leave STOPped Initialisation and STOP module 1 move w flashdis FEEMCR FER 1 STOP module 1 move w norm FEECTL FER_1 make sure verify mode off Initialisation and STOP module 2 move w flashdis FEEMCR FER 2 STOP module 1 move w norm FEECTL FER_2 make sure verify mode off Start up module to be erased and get array addresses move l ModAddress a5 a3 get module address into a3 move w flashen FEEMCR a3 clear STOP movea l FEEBAH a3 a4 get array start address move l a4 StartAddress a5 and store move PassError Error A5 initialise to successfull erase code movem l a7 a3 a4 restore registers rts done return no error ck ck Ck ck ck 0k ck 0k ck ck Ck Ck kk ck ck ck ck ck ck ck ck ck kk ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck kk ck ko ck kk ck Mk Sk ko kx kv ko ko ko KKK check array checks EEPROM array contents all are Era
51. k ck Ck ck ck Ck ck kk ck Ck ck ck Ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck kk ck ko ck kk ck Pk Sk ko kx kv Mk ko ko ko oko Print movem l a0 d0 a7 save registers move l 8 a7 a0 get address of string stacked return address moveq l BD_PUTS d0 function call bgnd bsr FindStrEnd get end of ASCII string move l a0 d0 test for odd address addgq 1 1 d0 skip past end of string btst 0 d0 beq Print 1 addq 1 1 d0 it s odd return to next addr Print 1 move l d0 8 a7 update stacked return address movem l a7 d0 a0 get back registers rts done Ck Ck ck ck Ck ck ck Ck ck ck ck ck ck ck ck Ck Sk KKK KKK ck kk KK KKK KKK ck kk ck kk KK KKK ck kk ck kk ko kk Ck kk kk Sk kk ck kk ck ko k Sk ck kc ko ko ko kokok ole oa op nt prints carriage return line feed combo Entry no parameters Exit all registers preserved ck ck Ck ck ck 0k ck 0k ck ck Ck Ck kk ck kc ck Ck ck ck ck ck cock ck ck ck Ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck KKK ko ck kk ck Mk Sk Mk Sk kv Mk ko ko ko ko erit bsr Print carriage return line feed dc b 13 10 0 0 even rts Ck Ck ck ck ck ck ck Ck ck ck kk Ck Sk ck Ck KKK ck Ck KKK KKK KKK KKK KK KKK KKK KKK ck kk Ck kk kk ck kk ck kk ck kk Ck kk kk kk ko kc k ko KK KKK getchar returns character typed by user Entry no parameters Exit d0 contains character typed KC Ck Ck Ck
52. k ck ck ck ck ck kk ck ko ck kk ck Sk Sk Mk kx kv Mk ko ko ko ko FindStrEnd move w d0 a7 push temp register moveq 1 d0 max loop count 1st time thru ESE 1 tst b 80 byte 0 dbeq dO FSE 1 uses loop mode bne FSE 1 loop till test true subq 1 1 a0 decrement address reg move w a7 d0 restore register rts KKK KKK KKK KKK KK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KR KKK KKK KKK KKK KKK KKK KKK KKK ko ko ko KKK ntoh prints hex value of register DO least sig nibble to screen Entry DO contains nibble value ck ck Ck ck ck 0k ck Ck ck ck Ck ck kk ck Ck ck ck Ck ck kk ck KK ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ock ck ko ck ko ko ck ko Sk ke Sk kv Mk ko ko kokok ntoh movem 1 d0 d1 a7 move b d0 dl andi w Sf dl addi b 0 dl cmpi b 10 0O dl bcs nt 1 addi b A 9 1 dl nt 1 moveq BD_PUTCHAR d0 bgnd movem l a7 4 d0 d1 rts UST AN1255 D MOTOROLA 17 KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KKK KEK KKK KKK KKK KKK KKK KKK KKK btoh prints hex value of byte register DO to screen Entry DO contains byte value ck ck Ck ck ck 0k ck 0k ck ck Ck Ck kk ck kc ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck oko ck ck ck ck KKK ck ck kk ck ck ock ck kk kk ck Pk Sk ke Sk kv Mk ko ko kokok btoh ror b 4 d0 bsr ntoh ror b 4 d0 bsr n
53. k d32 Include files M68F333 inc M68F333 addresses and programming constants ipd inc BD32 system call constants essage file bulk msg Object file format Motorola S records Execute from BD32 as bulk module ID Module ID can be 16 or 48 and specifies which MC68F333 flash module is to be bulk erased Addressing modes This code is designed as a driver for the BD32 background debugger for CPU32 devices A requirement is that the code must be fully relocateable All addresses apart from fixed module addresses are relative and where word alignment is not guaranteed byte accesses must be used Supervisor program space accesses are used when reading the flash array to allow operation regardless of the configuration of the flash modules s ASPC bits FEEMCR Word alignment The embedded text strings have been adjusted in size so that the following code remains word aligned any modifications to these strings should be adjusted accordingly An assembler even type directive to force word alignment could be used if available ck ck ck ck Ck ck Sk ck ck Ck ck kk ck Ck ck ck Ck ck Ck ck ck Ck ck ck ck ck ck ck ck Ck ck ck ck ck KKK ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck KKK ck ko ck ko ck ko kx kv Mk k ko ko ko ko Include files
54. k kk kk Sk Sk Sk Sk Sk Sk Sk Sk kk ko ko ko ko I EPROM modules BULK 16 48 Bulk erase Orion 16k 48k bulk usage error BULK 16 48 bulk bulk erase failed bulk unhandled exception encountered bulk module erased O K AN1255 D MOTOROLA 31 Initialization Files Used By Program and Erase Drivers KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK KKK KKK KKK KKK KKK I kk Sk Sk kk Sk Sk Sk Sk Sk Sk Sk Sk Sk Sk Sk kk ko ko ko M68F333 INC Define M68F333 addresses and programming constants ck ck Ck ck ck 0k ck Ck ck ck Ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck oco ck ck ck ck ck ck ck ck ck Ck ck ck oko ck kk ck ko Sk Mk kx kx Mk ko ko ko oko FER 1 equ SFFFFF800 register block address for array 1 16k bytes FEE SIZE 1 equ 4000 size of array 1 16k bytes FER 2 equ SFFFFF820 registers block address for array 2 48k bytes FEE SIZE 2 equ c000 size of array 2 48k bytes FER REGSZ equ 20 Size of register block both arrays register offsets FEEMCR equ 0 mod config register FEETST equ 2 test register FEEBAH equ 4 base address reg high word FEEBAL equ 6 base address reg low word FEECTL equ 8 program control reg FEEBSO equ 10 bootstrap info 0 FEEBS1 equ 12 bootstrap info 1 FEEBS2 equ 14 bootstrap i
55. l d0 a7 push working reg for now move l a0 d0 restrict address to 24 bits and 1 SOO0ffffff d0 move l d0 a0 Is a0 within 16K register block ca regs cmpa l FER l amp Sffffff a0 range 1 start test bcs ca 2 is a0 range start cmpa l FER_1 FER_REGSZ 1 amp Sffffff a0 x yes now test against end bhi ca_2 is a0 range end move l FER 1 81 yes within range bra ca good A Is a0 within 48K register block ca 2 cmpa l FER 2 amp Sffffff a0 range 2 start test bcs ca 3 is a0 range start cmpa l FER_2 FER_REGSZ 1 amp S ffffff 80 yes now test against end bhi ca 3 is a0 range end move l FER 2 81 yes within range bra ca good Is a0 within 16K flash array ca 3 move l FEEBAH FER_1 d0 read arrayl start address and 1 SOOffffff d0 clear d0 31 24 move l d0 al1 cmpa l al a0 bcs ca 4 is a0 range start add 1 FEE SIZE 1 1 d0 calculate end addresses move l d0 al cmpa l al a0 bhi ca 4 is a0 range end move l FER 1 81 yes within range bra ca good Is a0 within 48K flash array ca 4 move l FEEBAH FER_2 d0 read array2 start address and 1 Sooffffft do clear d0 31 24 move l d0 al1 cmpa l al a0 bcs ca bad is a0 range start add 1 FEE SIZE 2 1 d0 calculate end addresses stt AN1255 D MOTOROLA 19 d0 al cmpa l al a0 bhi ca_bad is a0 range end move l FER_2 al yes within range bra ca good x No valid mod
56. m disk file AO buffer PROGRAM ERASE OPERATION An erased bit has a logic state of one A bit must be programmed to change its state from one to zero Eras ing a bit returns it to a logic state of one Programming and erasing the FLASH module requires a series of control register writes and a write to an array address The same procedure is used to program control reg isters that contain flash shadow bits Programming is restricted to a single byte or aligned word at a time The entire array and the shadow register bits are erased at the same time When multiple FLASH modules share a single pin do not program or erase more than one module at a time Normal accesses to modules that are not being programmed are not affected by programming or erasure of another FLASH module Following paragraphs give step by step procedures for programming and erasure of flash EEPROM arrays Parameters used in the descriptions are defined and characterized in the electrical specifications section of the appropriate device manual AN1255 D MOTOROLA 9 Programming The following steps are performed to program the array Figure 3 is a flowchart of programming operation 1 Increase voltage applied to the VEpg pin to program erase verify level 2 Clear the ERAS bit and set the LAT bit in FEExCTL This enables the programming address and data latches 3 Write data to the address to be programmed This latches the address to be programme
57. nd 2 before erasing BD32 BACKGROUND DEBUGGER BD32 is a debugger program for CPU32 based devices that executes on an IBM PC compatible host and communicates with the background debugging mode BDM port of the device via the PC printer port Use of BDM makes a ROM based monitor program unnecessary and the only requirement for using it is access to the CPU32 BDM signals If the design includes the recommended 10 pin Berg type connector to provide access to the signals BDM can even be used with the final application hardware BD32 supports a method of extending the available functions through custom driver programs If a com mand that is not part of the standard command set is entered BD32 searches the PC disk for a file with the command name and the extension D32 If a matching file is found it is executed by the MCU in response to the command Parameters can be entered with the command and are passed to the driver program as an ASCII text list in memory pointed to by one of the processor registers To ensure that drivers will operate on application hardware systems with differing memory maps BD32 re quires that driver programs be relocatable and uses a load address specified by the BD32 driver com mand This feature is used often when programming and erasing the FLASH modules as the drivers must not be placed in an address range which will be overwritten by a flash array Table 6 shows available BD32 system calls A driver program
58. nfo 2 FEEBS3 equ 16 bootstrap info 3 bit assignments STOP equ 8000 FRZ equ 4000 BOOT equ 1000 LOCK equ 800 equ 200 ASPCO equ 100 WAITI equ 80 WAITO equ 40 FSTE equ 80 GADR equ 40 HVT equ 20 BTST equ 10 STRE equ 2 WPF equ 1 VFPE equ 8 ERAS equ 4 LAT equ 2 ENPE equ 1 Flash EEPROM timing constants Programming constants pwpp equ amp 20 program pulse width us tpr equ amp 10 program recovery time us npp equ amp 50 number of program pulses Erase constants tei equ 100 rase pulse increment time ms ter equ 1 rase recovery time ms nep equ 5 maximum number of erase pulses end of M68F333 inc ET MOTOROLA AN1255 D 32 KKKKKKKKKKKKKKKKKKKKKKKKKKKK KKK KKK KKK KKK KKK KK KKK KK KKK kk Sk Sk kk kk Sk Sk Sk Sk Sk Sk Sk Sk Sk Sk kk ko ko ko ipd inc equates for BD32 systems calls Ck Ck Kk I I I SI I II II I SII II II II SII II II SII SII II II II II SI I Sk I kk Sk Ik I kk kk kk kk Sk Sk Sk Sk Sk Sk Sk Sk Sk Sk ko ko ko ko BD QUIT equ 0 quit return to BD32 BD PUTS equ di puts put string to console BD PUTCHAR equ 2 putchar print character on console BD GETS equ 3 gets get string from user GETCHAR equ 4 getchar get single character from user BD GETSTAT equ 5 getstat return 1 if character waiting from user BD FOPEN equ 6 fopen open disk file with specified mode BD FCLOSE
59. ntil maximum allowed erase pulses x used or array has verified as correctly erased Entry module defined by ModAddress ModSize Exit DO is non zero if erase unsuccessful A0 contains first error address if erase unsuccessful d otherwise A0 corrupted All other registers unchanged ck ck Ck ck ck 0k ck Ck ck ck Ck ck kk ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck kk ck ck ock ko ko ck ko Sk Mk kx kv Mk ko ko kokok Erase movem l di1 d3 al1 a7 preserve registers Initialise timing and address parameters clr w d2 initialise pulse counter k 0 clr w d3 initialise cumulativ rase time 0 used as erase margin move 1 odAddress a5 al get module address into al move w erase_off FEECTL al set VFPE ERAS LAT move w dO al write data to EEPROM g Erase cycle db 1 bsr Print print progress dots dc b addq w 1 32 increment pulse counter k ii Calculate erase time move w tei dl rase pulse time tei mulu w d2 d1 k ms dl add w di d3 add to cumulative time d3 x Apply erase pulse move w erase_on FEECTL a1 enable prog voltage set ENPE bsr msdelay wait tei k milliseconds move w erase_off FEECTL al disable voltage clear ENPE 2 Recovery Off time move w ter dl delay erase recovery time ter bsr msdelay K Blank test array bsr check array array now blank tst b do bne db q miss register test if
60. number of driver parameters Exception Handling Basic exception handling routines are built into the PROG and BULK drivers In normal use no exceptions are generated so the handlers simply indicate that an error has caused an exception Such errors are typ ically caused by array address conflicts described in EFFECTS OF LOCK BIT OPERATION PROG Flash Programming Driver User Details The PROG driver is designed to enable programming of flash EPROM from an S record file on the PC run ning BD32 The syntax used is PROG lt filename ext gt lt start address gt where lt filename ext gt is the filename of the S record file and lt start address gt is an optional parameter that if specified defines the start address of programming overriding the start address specified in the S record The relative addresses of bytes in the S record are preserved with a fixed offset added to each S record address The offset is calculated as offset start address parameter first S record address If lt start address gt is not specified the addresses defined in the S record file are used unchanged Each byte or word is verified after programming Any verify errors are indicated by an error message and the user is given the option to abort or continue programming This facility is useful if an array is already partially programmed or damaged or if the S record contains programming data for a location not within any FLASH address ran
61. o ck Mk Sk Mk kx kx Mk ko KKK btoh ror b 4 d0 bsr ntoh ror b 4 d0 bsr ntoh rts a AN1255 D MOTOROLA 27 KKK KKK KKK KKK Ck Sk KKK KKK KKK KKK KK KKK KKK KKK KK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK ko ko ko KKK wtoh prints hex value of word register DO to screen Entry DO contains word value Exit all registers preserved Ck CK Kk SI I II II II I SII II II II SII SII SI III I III II II II SII kk Ik I kk kk Sk kk Sk Sk Sk Sk Sk Sk Sk Sk Sk Sk kk Sk ko ko ko wtoh rOr W 8 d00 bsr btoh rOr W 8 d00 bsr btoh rts KKK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KR KKK KKK KKK KKK KKK KKK KEK KKK KKK KKK KKK KKK ko ko kc KKK x ton prints hex value of long word register DO to screen Entry DO contains long word value Exit all registers preserved ck ck Ck ck ck 0k ck Ck ck ck Ck ck ck Ck ck Ck ck ck Ck ck ck ck ck KEK ck ck ck ck ck ck ck ck ck ck ck Ck ck ck KKK KKK ck ck ck ck ck ck ck ck ck ck ck ck KKK ko ck ko ko ck Pk Sk Mk KKK ko ko ko oko ltoh swap do bsr wtoh swap do bsr wtoh rts KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK PELNE prints constant string in code and returns to ses program at first even location after string Entry parameters indexed from stacked return PC Exit stacked return PC modified to give correct return all registers preserved ck ck Ck ck ck 0
62. or verification of erase dc w SFFFF SFFFF SFFFF SFFFE dc w 0000 0000 0000 0000 KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KEK KKK KKK KKK ko ko kckckokok CUSTOM VECTOR TABLE vectable ds 1 13 Alternate vector table KKK KKK KKK KKK KK KKK KKK KKK KK KKK KKK KKK KKK KKK KK KKK KKK KKK KKK KEK KKK KKK KKK KKK KKK KKK KKK EXCEPTION HANDLER ROUTINE Use Quits to BD32 with unhandled exception error code Exception handling is included because many user errors mapping of flash drivers etc could cause bus errors f line exceptions etc Flash programming voltage is disabled in case exception ocurred during a programming cycle ck ck Ck ck ck 0k ck 0k ck ck Ck ck ck ck Ck ck ck Ck ck ck ck KK kk ck Ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ck ck kk ck kock ko ko ck ko Sk ke kx kx Mk ko ko ko ko o xx ox ox excep h move w f norm FEECIL al normal flash reads writes disable programming voltage move ExcepError Error A5 unhandled excep error bra Bulk_end FileMode dc b read mode for file open KKK KKK KKK KKK KK KKK KKK KK KKK KKK KKK KKK KKK KKK KK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK k ko ko KKK
63. ove l d0 d2 get argc into d2 AN1255 D MOTOROLA 15 Print signon and warning message bsr Print print signon message ro ael M68F333 Flash EEPROM Programmer Version 2 0 13 10 0 x Main initialisation bsr Initialize init hardware and address list tst do bne Prog_end X Check command line cmpi 2 32 argc lt 2 bcs Prog 0 cmpi 3 04 gt 3 bls Prog 1 Prog 0 move UsageError Error A5 arg count is wrong bra Prog end hi Get filename open file check if OK Prog 1 addq 1 4 a2 skip over program name move l 82 4 80 get file name of S records lea 1 FileMode A5 al read mode r bsr fopen move w dO FilePtr A5 save file pointer bne Prog 11 continue if OK move FileError Error A5 can t open input file bra Prog_end ui Evaluate remaining parameters Prog 11 clr w odeAddr A5 Assume no offset first cmpi 3 32 argv 3 bne Prog_2 move l a2 a0 evaluate start address parameter bsr Eval beq Prog 12 move EvalErrorl Error A5 bra Prog 3 close file and exit Prog 12 move l di1 StartAddr A5 got first param move w 1 ModeAddr A5 signal to calculate offset Read an S Record check for errors Prog 2 bsr ReadSRecord get next S Record tst do beq Prog 25 continue if no error cmpi SRecS9 d0 S9 record beq Prog 3 yes close normally
64. prgloop Word data to programming latch dp word move w 80 write word data to EEPROM K Initialise prog pulse time dp prgloop move w pwpp dl pulse time ready for usdelay Programming stage move w prgen FEECIL al enable prog voltage set ENPE bsr w usdelay wait pwpp microseconds Off time move w latch FEECTL al disable voltage clear ENPE move w tpr dl delay tpr microseconds after turning off vprog bsr usdelay addq w 1703 increment pulse count Verify stage store diff in do 0 d0 dQ ready to hold byte word diff tst d5 byte or word beq dp verw move b a0 d0 byte verify bra dp vertst dp verw move w a0 d0 word verify dp vertst beq dp margin verify O K Failed to verify cmpi w npp d3 over max number of program pulses bcs dp prgloop no continue x Failed to verify and max program time used move w norm FEECTL a1 normal flash reads writes bra dp_end return programming data error to caller programmed OK now re program for the same number of pulses 100 margin ih E MOTOROLA AN1255 D 20 dp_margin subq w 1 d3 compensate for extra dbcc loop dp_mrgloop move w pwpp dl set program pulse time move w prgen FEECTL al enable prog voltage set ENPE bsr usdelay and delay move w latch FEECTL al disable voltage clear ENPE move w tpr dl set program recovery time bsr usdelay and delay dbf d3 dp_mrgloop count
65. r instance a 16 kbyte array can be located at any 16 kbyte boundary in the address map For M68300 family devices arrays can also be configured to reside in both program and data space or in program space alone Mj MOTOROLA Wm MOTOROLA INC 1996 A flash EEPROM array can be read as either bytes words or long words FLASH modules respond to back to back IMB accesses providing two bus cycle four system clock access for aligned long words Each module can also be programmed to insert up to two wait states per access to accommodate migration from slower external development memory without re timing the system Because an array can be mapped to a number of different base addresses it is possible for addresses in the array to overlap the addresses of it s own register block or addresses used by other MCU modules in cluding memory that the program erase utility is executing from The resulting conflicts can cause program ming or erasure to fail Thus the user must take special care to verify the array base address before attempting programming or erasure Programming is by byte or aligned word only and FLASH modules support only bulk erasure Hardware interlocks protect stored data from corruption if program erase voltage is enabled accidentally Flash EEPROM Registers Each control block contains five registers the flash EEPROM module configuration register FEEMCR the flash EEPROM test register FEETST the flash EEPROM array
66. river code PROG Driver Listing PROG Resident Command Driver for MC68F333 device Utility to program an MC68F333 flash EPROM module from an S record file Source file prog s62 Object file prog d32 Include files M68F333 inc M68F333 addresses and programming constants ipd inc BD32 system call constants essage file prog msg Object file format Motorola S records Execute as prog filename lt start_address gt Useage Start address specifies start of memory to be programmed if not Specified the S record start address is used Addressing modes This code is designed as a driver for the BD32 background debugger for CPU32 devices A requirement is that the code must be fully relocateable All addresses apart from fixed module addresses are relative and where word alignment is not guaranteed byte accesses must be used Word alignment The embedded text strings have been adjusted in size so that the following code remains word aligned any modifications to these strings should be adjusted accordingly An assembler even type directive to force word alignment could be used if available 32 23 bit addressing All flash addresses are forced to 24 bits with upper MSB ignored so that xxfff800 will always access
67. sedValue Entry StartAddress ModSize parameters initialised Exit if array checks as ErasedValue d0 0 a0 corrupted D1 corrupted else d0 1 a0 error address dl error data Ck Ck ck ck Ck ck ck Ck ck ck Ck ck Ck Sk KKK KKK ck Ck ck KK KKK KKK KKK KKK ck kk KK KKK ck kk kk Sk Ck kk kk Sk kk Sk kk ck kk Sk ko k Sk kv kc k ko ko kokok check array movem l d2 a7 preserve registers move l sup_prog d0 configure array accesses as movec d0 sfc supervisor program space move l StartAddress a5 a0 array start in a0 move l ModSize a5 dl array size in dl sh SEES MOTOROLA AN1255 D 30 asr l 1 dal calculate array size in words subq 1 1 d1 set up for dbcc loop move w ErasedValue 0 get erased value of EEPROM bc 1 moves w a0 d2 get array word from supervisor program space cmp w d2 d0 test ErasedValue dbne dat DC T loop while equal and not end of array beq bc 2 loop exit because of error move w d2 dl yes put error data in dl move b S01 d0 and flag error array not blank bra bo 3 bc 2 circ dO no flag no error array tests OK bc 3 movem l a7 d2 restore registers rts Ck Ck ck ck Ck ck ck Ck ck ck kk Ck Sk ck Ck Sk ck KKK KK KKK KK KKK KKK ck kk ck kk ck kk Ck ck ck kk ck kk Ck kk Ck ck ck kk ck kk ck kk Sk kk Sk kc kc ko ko kc KKK check regs routine to blank check flash shadow registers for a module A with register start address specified in
68. shadow MCR The field can be written only when LOCK 0 and STOP 1 The four possible encodings for ASPC are summarized in Table 2 In CPU 16 based systems only encodings for supervisor space are valid WAIT 1 0 Wait States Table 2 Array Space Encoding ASPC 1 0 Type of Access 00 Unrestricted program and data space 01 Unrestricted program space 10 Supervisor program and data space 11 Supervisor program space The default state of the WAIT field out of reset is determined by the value stored in the shadow MCR WAIT 1 0 specifies the number of wait states inserted during accesses to the FLASH module A wait state has the duration of one system clock cycle WAIT 1 0 affects both control block and array access es and can be written only if LOCK 0 and STOP 1 Table 3 shows wait state encodings and corre sponding clock cycles per transfer Table 3 Wait State Encoding WAIT 1 0 Wait States Clocks Transfer 00 0 3 01 1 4 10 2 5 11 1 2 The value of WAIT 1 0 is compatible with the lower two bits of the DSACK field in the integration module chip select option registers An encoding of 11 in the WAIT field corresponds to an encoding for fast termination Test Register FEETST Flash EEPROM Test Register This registers is used for factory test only 2 Base Address Registers The base address high register FEEBAH contains the 16 high order bits of the array b
69. sion 2 0 prog Programming completed O K Programming is successful Disable the VF PE supply if no more operations are required 8h FU E MOTOROLA AN1255 D 34 Example 2 Erasing The FLASH Modules As with the programming example the MCU is initialized to allow execution of the driver software in this case by using the macro file SRAMHIGH DO BD32 gt do sramhigh do The macro file terminates with the following information BD32 gt Finished should have TPURAM 100000 100e00 BD32 gt SRAM 100e00 100fff BD32 gt SSP 100ffe BD32 Drivers load 100000 BD32 gt BD32 gt BD32 gt Test read of TPURAM BD32 md 100000 10 00100000 5450 5520 5241 4D20 6D65 6D6F 7279 2020 TPU RAM memory BD32 gt BD32 gt Test read of SRAM BD32 md 100e00 10 00100E00 5352 414D 206D 656D 6F72 7920 2020 2020 SRAM memory BD32 gt BD32 gt Flash register area BD32 md fff800 40 OOFFF800 8200 0000 0000 0000 0000 0000 0000 0000 OOFFF810 0010 FFFE 0000 1000 0000 0000 0000 0000 eee OOFFF820 8200 0000 0001 0000 0000 0000 0000 0000 OOFFF830 0010 FFFE 0001 1000 0000 0000 0000 0000 Ito Si ater shel ene E NOTE Ensure that the MCU VFPE supply is enabled before the erase command is entered The erase driver is then executed BD32 gt bulk 16 SXE00030 er ete Download completed OK 35 records read M68F333 Flash EEPROM Bulk
70. source Because the MC68F333 has 4 kbytes of on board RAM there is no requirement for external memory to run the pro gramming utilities Source files for routines discussed in this note are available from Motorola Freeware Data Systems The Freeware BBS can be accessed by modem at 512 891 3733 For Internet access via telnet FTP use free ware aus sps mot com For World Wide Web access use http freeware aus sps mot com THE FLASH EEPROM MODULE Flash EEPROM provides high density non volatile memory that can be used for program or data storage Each FLASH module consists of a control register block that occupies a fixed position in MCU address space and a relocatable EEPROM array The control register block is shown in Table 1 It contains all of the registers to control mapping timing programming and erasing of the array Many of the control register bits have associated shadow flash EE PROM bits Shadow bits allow customization of the reset status of the module For example a module can be programmed to supply reset vectors from flash EEPROM bootstrap words Several interlocks are includ ed in the module to prevent accidental changes of critical parameters Unlike the control register block the flash EEPROM array is not fixed to a particular memory address but can be programmed to a particular address defined by the base address registers FEEBAH and FEEBAL Array base addresses boundaries are typically determined by array size Fo
71. the appropriate location Table 5 shows bootstrap word addresses in program space FEEBS 3 0 Flash EEPROM Bootstrap Words YFF 0 YFF 6 Table 5 Bootstrap Words Word Address FEEBSO 00000000 FEEBS1 00000002 FEEBS2 00000004 FEEBS3 00000006 APPLYING FLASH PROGRAM ERASE VOLTAGE A voltage of at least Vp 0 5 V must be applied at all times to the Vepe pins or damage to the FLASH module can occur FLASH modules can be damaged by power on and power off Vepe transients V must not rise to programming level while Vop is below specified minimum value and must not fall below minimum specified value while V5 is applied Figure 1 shows the and Vpp operating envelope Use of an external circuit to condition V pg S recommended Figure 2 shows a simple circuit that maintains required voltages and filters transients Vepe is pulled up to Vpp via Schottky diode D2 Application of pro gramming voltage via diode D1 reverse biases D2 protecting VDD from excessive reverse current D2 also protects the FLASH from damage should programming voltage go to zero Programming power supply volt age must be adjusted to compensate for the forward bias drop across D1 The charge time constant of R1 and C1 filters transients while R2 provides a discharge bleed path for C1 Allow for RC charge and dis charge time constants when applying and removing power When using this circuit keep leakage from ex ternal devices conn
72. to disable them by hold ing DATA 15 14 low during rest BD32 do sramhigh do The macro file terminates with the following information BD32 gt Finished should have TPURAM 100000 100e00 BD32 SRAM 100e00 100fff BD32 gt SSP 100ffe BD32 gt Drivers load 100000 BD32 gt BD32 gt BD32 gt Test read of TPURAM BD32 gt md 100000 10 00100000 5450 5520 5241 4D20 6D65 6D6F 7279 2020 TPU RAM memory BD32 gt BD32 gt Test read of SRAM BD32 md 100e00 10 00100E00 5352 414D 206D 656D 6F72 7920 2020 2020 SRAM memory BD32 gt BD32 gt Flash register area BD32 md Sfff800 40 OOFFF800 8200 0000 0000 0000 0000 0000 0000 0000 OOFFF810 0010 FFFE 0000 1000 0000 0000 0000 90000 OOFFF820 8200 0000 0001 0000 0000 0000 0000 0000 OOFFF830 0010 FFFE 0001 1000 0000 0000 0000 90000 The dump of the flash control register blocks shows that the arrays are now mapped to 00000 16 kbyte and 10000 48 kbyte These addresses are correct for the array data file ARRAY64 0 which contains a full 64 kbytes of test data covering both arrays Remember the VFPE supply must remain enabled for pro gramming to take place ARRAY64 0 takes around 35 seconds to program BD32 prog array64 0 v RTL coa ud plato o dr Download completed OK 53 records read M68F333 Flash EEPROM Programmer Ver
73. toh rts KKK KKK KKK KKK KK KKK KKK KK KKK KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK wtoh prints hex value of word register DO to screen Entry DO contains word value KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK SII SII II II I I II I I Sk Ik SI Sk I Sk Ik kk kk Sk Sk kk Sk Sk Sk Sk Sk Sk Sk kk ko ko ko wtoh rOr W 48 0 bsr btoh rOr W 8 d00 bsr btoh rts KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KKK KEK KKK KKK KKK KKK KKK KKK KKK Itoh prints hex value of long word register DO to screen Entry DO contains long word value ck ck Ck ck ck 0k ck Ck ck ck Ck ck kk ck Sk ck ck Ck ck ck ck KKK ck ck ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ko ck kk ck Pk Sk ko kx kv Mk ko ko ko ko ltoh swap do bsr wtoh swap do bsr wtoh rts KKK KKK KKK KKK KK KKK KKK KKK KKK KK KKK KKK KKK KK KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK Print prints constant string in code and returns to d program at first even location after string Entry parameters indexed from stacked return PC Exit stacked return PC modified to give correct return no registers corrupted KC CK kk Sk SI I I I II I I SII SII II II SII II II II II SII II II II SI kk Sk Ik Ik Sk kk kk Sk kk Sk Sk Sk Sk Sk Sk Sk Sk Sk Sk kk ko ko ko Print movem l a0 d0 a7 save registers X WARNING Any change to movem list will require change Ei to stack o
74. ule being addressed return 0 in Al ca_bad movea l 0 al ca_good movem l a7 d0 rts ck ck Ck ck ck kc Ck ck ck Ck ck kk ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck oco ck kk ck Ck ock ck cko ck kk ck Sk ck ko Sk kv kv Sk ko ok do prog Programs one byte word of data to memory Entry Target address in AO k byte or word data in DO ai byte flag in d5 non zero gt program byte data Exit dO contains difference between data to be programmed and read back data 00 if programming successful or Sff if address to be programmed is not recognised as flash d3 is corrupted a0 and d5 are unchanged ck ck CK ck ck 0k ck 0k ck ck Ck ck kk ck Ck ck ck Ck ck ck ck ck KK ck Ck ck ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ock ck kk kk ck ko ck ko Sk kv kx Sk ko ko do prog bsr dis both disable both modules STOP clr w d3 initialise pulse counter 0 bsr check_address get register address pst al address OK beq dp addrfail no bomb out move w flashen FEEMCR al only enable module to be programmed move latch FEECTL al enable verify latch tst d5 byte or word beq dp_word Byte data to programming latch move b dO 80 write byte data to EEPROM bra dp
75. verify use the BD32 DRIVER command to determine the BD32 driver execution address and examine the FEEBAH and FEEBAL registers of the module being programmed erased If the driver is within the array area either relocate the array Example 1 or the BD32 driver execution address Examples 1 and 3 2 Flash array mapped over the flash module register area or other registers Error symptoms BULK fails to verify blank after the maximum erase time has been used and prints the fail address This address corresponds to the first register within the array area The array may be fully erased in this case only the verify mechanism fails PROG will print a program fail error for the first array address being programmed that corresponds with a module register It will be impossible to program this location as the register takes priority To verify examine the FEEBAH and FEEBAL registers of the module being programmed erased and en sure that the module array does not conflict with any other registers To fix remap array either manually Example 1 or by programming shadow base registers Example 3 3 Attempting to program unimplemented shadow bits Error symptoms PROG prints a program fail error for the shadow register address The register may have been programmed correctly but verify always fails To fix make sure that programming data for unimplemented shadow bits is set to zero sh EE MOTOROLA AN1255 D 36 4 No VFPE supplied

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