RTE-200-TP
Contents
1. nnns sss 12 ervicomimand sc ee uet tee Eee E E EE ERE MI enu 12 COMMANA uod ed Dove rea cete aeu et aad ede e D Pe ae ee A 13 11 INTERFACE SPECIFICATIONS tna 14 Pir arrangement tables scsi ooi oto teet Deest erect e 14 ciae ect e ue d e 14 AIC METRE MM 14 Layout of the connectors on the meme nnne 15 12 16 13 ROM PROBE SPECIFICATIONS 17 32 HE 17 DIPz40 ROMIDEOD6 eas cg ete rete tette er ee RA ie eg eG eae rose 18 DIP 42 ROM Probe n Trn Pm 18 STD 16BL ROM pDrODG etie e RD a A eee am site ESA 19 APPENDIX A APPEARANCE OF ROM 21 DIP 32 ROM prope m eel UR EE Rl t Eee ad Ed Bus ia LEO e s 21 DIP 40 42 ROM prob6e ile e re eet debite Coe dr inve edie 21 STD 16BIT ROME eer TA NEEDS ABE 22 200 Hardware User s Manual 1 OVERVIEW RTE 200 TP is an in circuit emulator for NEC s RISC processor By controlling the d2. 200 Hardware User s Manual RealTimeEvaluator 200 Hardware User s Manual CONTENTS DOVER VIEW noe eher 2 2 Biwuuiicmme 3 3 HARDWARE SPECIFICATIONS 4 Emulation ER 4 Host system and interface o t d et teh e 4 4 SYSTEM CONFIGURATION 0 jcoc eccdcescccedeeceevedecsesesdecsevecceczessscuegeesscuegecpaceegeevadtapecvaceezeenececsexecceeyeszacs 5 5 COMPONENT NAMES AND 6 6 INSTALLATION PROCEDURE una racc m anie sm aane du aane cu auae ca aam 8 7 CONNECTION TO THE USER SYSTEM 9 Connection with the N Wire 1 nennen nennen nn nnne nennen nnns 9 Gontnection with a ROM probe err TRECE DIE IE EIDEM 9 Note on the DIP 32 ROM nnne rne 9 8 POWERING ON AND OFF raae aaro 10 uod snomo pe EE 10 Powering Off tita etn de teme temen n e d mni et deines 10 9 2 11 Starting GhKRTES2 exe 8 38 td o gd e epa Hg ee as a tastes 11 10 INITIALIZATION
3. supplied with the interface card N Wire cable for user system connection PC Card interface ROM probe for user system connection LAN Box High level language debuggers for Control softoware for each processor PC capable of running Windows 95 Card supporting the PC 9800 C bus Card supporting the PC AT ISA bus or PCI bus Type Il card version 2 1 of the PCMCIA specifications version 4 2 of the JEIDA specification or later Lan supporting the PC 10base T Cable for connecting RTE 200 TP to the host card Dedicated power supply RTE 200 TP Cable for connecting to the user system used for debugging Probe for ROM emulation 200 Hardware User s Manual 5 COMPONENT NAMES AND FUNCTIONS This chapter shows the appearance of RTE 200 TP as well as the names and functions of its components ROM USER POWER LED 4 N Wire connector ROM 1 connector PC host system connector Power jack ROM 2 connector Power LED DCU USER POWER LED EXT connector Power jack This is a connector for the power supply Power is supplied by inserting the plug of the supplied power supply into the jack Q Do not connect any device other than the supplied AC adapter RTE PS01 to the power jack PC host connector HOST This connector is used for connecting RTE 200 TP to the PC host system The host system interface cable is connected to
4. verify hispeed work ADDR Parameters Jauto If a break point is encountered during execution the break point causes a temporary break Choose Auto to automatically perform the subsequent execution Choose auto to suppress it Specifies whether the NMI is to be masked Enter if it is not to be masked Jint Specifies that pins INTxx are to be masked Enter if they are not to be masked jtag 12 25 Specifies the JTAG clock 12 5 MHz 25 MHz for N Wire Initial value of rte4win32 is 12 5 MHz Ver 4 37 or later or 25 MHz before Ver 4 37 verify Specifies the verification after writing memory is set Enter if it is not to be set Remark The CPU also accesses an area that emulates ROM jread or equivalent Therefore this command is useful for testing the area during downloading Note however that the processing speed slows down Ihispeed Specifies high speed mode to write data to memory specifies the normal mode Remark The high speed mode can be specified on condition that the ROM probe be connected If this mode is specified a control program temporarily located in the ROM emulated is executed in the foreground only when data of 128 bytes or more are contiguously written Use this mode after the hardware has been completely debugged because the CPU must be able to access the ROM correctly In normal mode data can be written to ROM via JTAG work ADDR Specifies an area
5. Bus width specification bits 8 16 32 Target ROM capacity bits 512K 1M 2M 4M 8M 16M 1 Pin mask functions Depends on the CPU specifications 1 An 8 bit ROM probe supports ROMs of up to 8M bits D 3 N 3 p x N 3 p x Host system and interface Target host machine PC 9800 Series and DOS V PCs Debugger GHS Multi Partner Win Windows 95 98 NT Interface card II version 2 1 of the PCMCIA specifications version 4 2 of the JEIDA specification or later PC 9800 C bus PC AT ISA bus and PCI bus or LAN BOX Power supply AC adapter in 100 V 5 V 2A RTE 200 TP 4 SYSTEM CONFIGURATION Hardware User s Manual The following figure shows the configuration of a system in which RTE 200 TP is used Windows95 98 Windows NT PC 9800 Series GHS Multi PARTNER Win Note type PC with a PC Card slot t GHS multi PARTNER Win PC 9800 Series PC interface PC AT interface card PC Card interface LAN Box Host system interface cable AC adapter N Wire cable ROM probe e i Ke d PC 9800 Series PC interface card L3 PC AT interface card gt E AC adapter power Host system interface cable
6. V ISA or DOS V PCI bus LAN BOX is connected via a LAN and is a 10Base T interface 200 Hardware User s Manual 3 HARDWARE SPECIFICATIONS Emulation Depends on the KIT xxxx TP specifications Emulation functions Operating frequency Depends on the CPU specifications JTAG N Wire Interface Break functions H W break points execution addresses Depends on the CPU specifications S W break points 100 Breaks that can be set using access events Depends on the CPU specifications Step breaks Supported Manual breaks Supported Trace functions 4 bits 4 bits x 128K words Depends on the CPU specifications Trace data bus Trace memory Trigger that can be set using an execution address Start that can be set using an execution address Depends on the CPU specifications Stop that can be set using an execution address Depends on the CPU specifications 0 1FFFFh 66 MHz max Depends on the CPU specifications Trace delay Trace clock Data trace conditions Disassembled trace data display function Depends on the CPU specifications ROM emulation functions Memory capacity 4 M Byte 50 ns Access time Number of ROMs that can be emulated DIP 32pin ROM 8 bit ROM DIP 40 42pin ROM 16 bit ROM STD16BIT ROM connector Types of ROMs that can be emulated DIP 32 ROM probe bits 1M 2M 4M 8M 27C010 020 040 080 DIP 40 ROM probe bits 1M 2M 4M 27C1024 2048 4096 DIP 42 ROM probe bits 8M 16M 27C8000 16000
7. this connector EXT connector EXT This connector is used for external signal input and internal signal output N Wire connector N Wire connector JDCU1 This connector is used for connecting RTE 200 TP to the user system via N Wire ROM emulator connector 1 ROM 1 connector JROM1 This is connector No 1 for connecting RTE 200 TP to the user system to emulate ROMs ROM emulator connector 2 ROM 2 connector JROM2 This is connector No 2 for connecting RTE 200 TP to the user system to emulate ROMs Power LED POWER This LED lights steadily while the power to RTE 200 TP is on DCU user system power LED DCU USER POWER LED DCU POWER This LED lights steadily while the power to the user system connected with the N Wire connector is on 200 Hardware User s Manual ROM user system power LEDs ROM USER POWER LEDs ROM POWER 1 2 3 4 These LEDs light steadily while the power to the power pins of the ROM sockets connected with the ROM emulator connectors is on The four LEDs have the following meanings If an 8 bit ROM probe is used LED1 to LED4 correspond to sockets ROM1 to ROMA at the end of ROM probes and light steadily when the power to the power pins of the sockets is on If a 16 bit ROM probe is used LED1 and LED2 light steadily at the same time while The power to ROM socket 1 connected with connector 1 is on LED3 and LED4 light steadily at the same time while The power to ROM socket 2 connected with c
8. user system is described below Connection with the N Wire cable Connect the JDCU1 connector of RTE 200 TP to the user system using the N Wire cable supplied with RTE 200 TP Connection with a ROM probe Connect the JROM1 or JROM2 connector of RTE 200 TP to the ROM socket of the user system using a ROM probe of a type appropriate for the ROM of the user system ROM probes are options Four types of ROM probe are available DIP 32 ROM probe This probe allows emulation of up to four 8 bit ROMs On the RTE 200 TP side connect a probe labeled ROM1 and 2 to JROM1 and a probe labeled ROMS and ROMA to JROM2 On the user system side connect ROM1 ROM2 ROMS and ROMA to the ROM sockets with the lowest second lowest second highest and highest addresses respectively if an 8 bit bus is used 16 bit bus is used connect ROM1 ROM2 to the ROM sockets corresponding to DO D7 D8 D15 of the lower addresses and ROM3 ROM4 to the ROM sockets corresponding to DO D7 D8 15 of the higher addresses DIP 40 ROM DIP 42 ROM probes and STD16BIT ROM probes These probes enable the emulation of up to two 16 bit ROMs On the RTE 200 TP side connect a probe labeled ROM1 to JROM1 and a probe labeled ROM to 2 On the user system side connect a probe labeled 1 to the ROM socket with the lower address and a probe labeled ROM to the ROM socket with the higher address if a 16 bit bus is used When connecting probes to ROM sockets
9. 15 1 A13 37 24 D12 A13 B13 A12 0012 WRH INH 14 36 26 013 14 14 A13 DO13 WRL GND A15 35 28 D14 A15 B15 14 0014 GND 2 34 A15 DO15 A 32 D15 psense 816 17 33 15 i Do 179 OF Di A18 2 D2 A18 B18 D3 A19 1 n D4 A19 19 05 A20 g2 voc D6 A20 B20 D7 VCC 19 9 08 21 06 07 21 09 9 22 010 22 22 Dii vec 010 011 32 012 A23 B23 013 BYTE VPP 012 013 11 12 014 A24 24 015 139 CE 1 ba Aog 014 015 Bo OE vss 27016000 JROMEMLT V V GND GND vec 9 U2A 1 2 1 Rt 9 3 2d 10K 74xx04 74 32 U3B 4 4 6 ROMCS 59 74 32 20 200 Hardware User s Manual APPENDIX A APPEARANCE of ROM PROBE DIP 32 ROM probe 19mm 280 300mm 43mm DIP 40 42 ROM probe 280 300mm A B C 3 3 Kind A B D CBL ROM40 CBL ROM42 21 200 Hardware User Manual STD 16BIT ROM probe 280 300 48mm 45 50mm 32mm 49mm 1pin mark ud 3 3 22 200 Hardware User s Manual Revision History Rev 1 0 Dec 15 1999 1 edition RTE 200 TP Hardware User s Manual M781MNLO2 Date of preparation Jun 15 1998 Rev2 0 23
10. T pin arrangement Applicable connector XG4M 1031 manufactured by Omron Corporation or equivalent 16 200 Hardware User s Manual 13 ROM PROBE SPECIFICATIONS DIP 32 ROM probe The DIP 32 ROM probe supports the following two pin arrangements The arrangement to support is determined with the jumper on JP1 JP1 1 2 jumpered A19 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 00 01 02 GND JP1 jumpered The labels at the end are marked and ROM at the factory If you purchase another DIP 32 ROM probe replace the labels with those supplied to distinguish it from the first one as shown in the figure below 1 gt ROM3 ROM gt ROMA 17 200 Hardware User s Manual DIP 40 ROM probe The DIP 40 ROM probe supports the following pin arrangement DIP 42 ROM probe The DIP 42 ROM probe supports the following pin arrangement The label at the end is labeled ROM1 or ROMe at the factory If you purchase another DIP 40 ROM or DIP 42 ROM probe replace the label with that supplied to distinguish it from the first one as shown in the figure below 1 gt ROM2 18 200 Hardware User s Manual STD 16BIT ROM probe Signal description Not used address connect to gnd A22 00 015 OUT DATABUS CHIP ENABLE Low active signal WRH Write High byte PSENSE INH amp GND jConnectto gr
11. choose 8 if a DIP 40 42 ROM probe is used choose rom16 bus8 bus16 bus32 Specifies the ROM bus size in the system to be emulated 8 bits 16 bits or 32 bits can be specified Little big Specifies the endian of the rom data If little endian is specified during downloading the binary image of a file is written as is If big endian is specified the data of the high order bytes and low order bytes are exchanged depending on the bus size of the ROM Function The rom command sets the ROM emulation environment Enter only the parameters that need to be changed Parameters may be entered in any order If the same parameter is entered twice only the last entry is valid The initial value of LENGTH is 0 not used 200 Hardware User s Manual INTERFACE SPECIFICATIONS This chapter describes the standard specifications of the connectors used for control that are required for the user system Detail is depend on the CPU See Kit xxx TP s manual Pin arrangement table peer 22 33 series resistor recommended 5 tropaTas 22 33 series resistor recommended mow oum 22 c0 sees restr vecommerae w m ok aw orn a ere DRST Input Open or connected ColdReset via external circuit outputs the reset signal of negative logic from TP Rmode Input Output 4 7 10 pullup E
12. ebugging control circuit DCU incorporated into the processor from the outside RTE 200 TP enables highly transparent emulation on the board The debugger may be Multi developed by GHS or PARTNER developed by MIDAS LAB INC both of which operate under Windows 95 98 NT The host system may be either a PC 9800 series or DOS V machine The PC and RTE 200 TP can be connected using a dedicated PCMCIA card host card designed for a bus LAN BOX etc depending on the environment This product comes with the following components First check that none of the components are missing RTE 200 TP User s manual N Wire cable Power supply 501 5V 2A Borges The following are required to use RTE 200 TP although they are not supplied with the product 5 required RTE for Win32 Setup Disk User s manual License sheet 6 ROM emulator probes Must be obtained as required Four types of probe are available DIP 32 ROM probe DIP 40 ROM probe DIP 42 ROM probe STD 16BIT ROM probe 7 Host interface One of the following is required One of the following is required PC card interface kit PC 9800 Series DeskTop PC interface kit DOS V DeskTop PC ISA bus interface kit DOS V DeskTop PC PCI bus interface kit e LAN BOX 8 Debugger Either is required e GHS Multi e PARTNER Win 200 Hardware User s Manual 2 MAIN FEATURES High level language debugge
13. evices is on When RTE 200 TP is installed for the first time 2 must be started once to select RTE Selecting RTE gt Set the Setup dialog box of 2 as follows Setup RTE 5432 Specify the Target to be used gt WF 2 02008 Specify the interface to be used Specify an address as necessary RTE section is an example in case of using with KIT VR5432 TP Function test If RTE 200 TP is properly connected to the user system and capable of debugging the following dialog box appears upon the normal completion of the function test In this state control from the debugger is possible for Windows Ea RTE functional test RTE functional test completed successfully If an error occurs during the test the N Wire cable is not properly connected Check its connection Perform the ChkRTE32 exe function test after the RTE 200 TP has been connected to the user system and the power to all the devices has been turned on 200 Hardware User s Manual 10 INITIALIZATION COMMANDS Before debugging can be started initialization is required normaly The following explains initialization using the appropriate internal commands with KIT VR5400 TP Method of initialization is defferent from KIT See KIT xxxx TP s manual nv comman Format env Jauto nmi int jtag 25 12
14. for clearing the cache or executing initialization processing Be sure to specify the RAM on uncache immediately after starting the system The VR5400 requires RAM on the user system for cache processing The monitor uses an area of 128 bytes from the specified address destructively Remark As this area is not used unless the cache area is accessed confirm that the RAM can be accessed in the uncache area before accessing the cache area Function The env command sets the emulation environment Enter only those parameters that need to be changed Parameters may be entered in any order If the same parameter is entered twice only the last entry is valid 200 Hardware User s Manual rom command Format rom ADDR LENGTH 512k 1m 2m 4m 8m 16m rom8 rom16 bus8 bus16 bus32 little big Parameters ADDR LENGTH Specifies an area to be emulated ADDR Specifies a start address An error occurs if the specified start address does not match the lowest address of the ROM to be emulated boundary of the ROM LENGTH Number of bytes of the ROM to be emulated Must be specified in boundary units of 4 bytes 512k 1m 2m 4m 8m 16m Specifies the bit size of the ROM to be emulated Sizes from 512K bits to 16M bits can be specified For the 27C 1024 for example specify 1M bits rom8 rom16 Specifies the number of data bits of the ROM to be emulated Either 8 bits or 16 bits can be specified If a DIP 32 ROM probe is used
15. onnector ROM 2 is on 200 Hardware User s Manual 6 INSTALLATION PROCEDURE This chapter describes the procedure for installing RTE 200 TP 1 Mount the interface card Note For information refer to the manual provided with the interface card 2 Install RTE for WIN32 Note For information refer to the manual provided with RTE for WIN32 At this point do not start CHKRTE32 EXE 3 Connect RTE 200 TP Connect RTE 200 TP to the host interface card or LAN BOX using the host system interface cable Make the AC adapter ready for connection 4 Connect RTE 200 TP to the user system Note For details see Chapter 7 5 Turn on the power Note For details see Chapter 8 6 Set RTE for WIN32 Start CHKRTES2 EXE and set the necessary parameters For details refer to the manual provided with RTE for WIN32 or see Chapter 9 of this manual 7 Run the debugger Note For information refer to the manual provided with the debugger The following figure shows an example how the devices are connected N Wire connector ROM socket VR5432 ESCOCGESESESEJEJE SEI IE User system Cs os User system connection cable N Wire amp ROM cable AC adapter RTE xxxx TP 200 Hardware User s Manual 7 CONNECTION TO THE USER SYSTEM The procedure for connecting RTE 200 TP to the
16. ound Pin arrangement table A side 10 Pp AST BTA B10 11 11 2 A4 AS A6 A CO 8 A9 BIO A21 3 D2 D4 010 24 25 21 ix xx xxx gt o n C ee 08 oD Ba 05 GND B5 GND 22 23 24 25 A 200 Hardware User s Manual Connectors Manufacturer KEL Models 8931E 050 1788 straight 8931E 050 178L right angle 8930E 050 178MS SMT straight Layout of the connectors on the board A2 1pinmark Al B B1 Edge of board Reference of the schematic n C E 0 15 X ut A 10 14 Do A B1 Al A2 9 A0 000 16 D1 2 A2 GND 0 B2 8 001 18 D2 M 2 A5 A2 DO2 A4 A4 7 20 D3 M B4 AT 003 5 6 A5 B d Do4 23 D4 fo s FBS 9 5 25 05 vcc 10 B6 11 5 005 A9 A10 AT 4 27 06 12 AT B7 A13 6 DO6 11 12 3 29 D7 14 BB A15 A9 41 7 007 15 08 A16 A9 13 14 17 10 40 Bon 17 D9 A18 A10 15 16 Big 19 AM 39 19 010 A20 AM Al 18 Bir 12 3g 10 0010 21 Dit Ai2 19 A20 Bia 9 11 0011 21 A22 78
17. pay careful attention to the ROM orientation The dot mark indicates pin 1 Note on the DIP 32 ROM probe For 32 pin ROMs of 1MB or greater there are two possible pin assignment schemes Set the jumper on the board for the ROM cable according to the ROM being used OE 24 pin A16 2 pin 1 2 Jumpered factory setting OE 2pin A16 24 pin 2 3 Jumpered 200 Hardware User s Manual 8 POWERING ON AND OFF The procedures for powering the system on and off are described below Complete all the steps in the installation procedure such as cable connection before powering the system on Powering on 1 Turn on the power to the host system 2 Turn on the power to RTE 200 TP Connect the dedicated AC adapter to the power jack of RTE 200 TP 3 Turn on the power to the user system 4 Start the debugger Powering off Quit the debugger Turn off the power to the user system Turn off the power to RTE 200 TP Disconnect the AC adapter from RTE 200 TP Turn off the power to the host system Do not turn on the power to the user system before powering on RTE 200 TP Doing so may cause a malfunction 200 Hardware User s Manual 9 RTE FOR WIN32 This chapter describes the setting of RTE for WINS32 with the focus on the aspects specific to RTE 200 TP Starting ChkRTE32 exe Start 2 after RTE 200 TP has been connected to the user system and the power to all the d
18. pen SES Lese me UN REC m m nn r Manufacturer KEL Models 8830 026 170 straight 8830E 026 170L right angle 8831E 026 170L right angle fixing hardware attached Wire length Keep the wire from CPU to the connector as short as possible gt gt 100 mm or shorter is recommended 14 200 Hardware User s Manual Layout of the connectors on the board The figure below shows the physical layout of the connectors on the board 4010 B2 A2 t B1 A1 lt Polarity indication Board end Top View Note When actually arranging the pins design them according to the connector dimensional information 200 Hardware User s Manual 12 EXT CONNECTOR The specifications of the EXT connector are given below Factory Use Output Must be left unconnected EXIO Input External input signal 0 pulled up with a 1 kQ resistor Edge detectable Factory Use Output Must be left unconnected External input signal 1 pulled up with a 1 kQ resistor roa e ee teat ra pind ia rae Eee e 0 Notes 1 The inputs to EXI1 EXI2 and EXI3 are at 5V TTL level The TRG signal is an open collector signal pulled up with a 1 kQ resistor EXIO can be specified as a trace trigger EXIO to EXI3 are recorded in memory as trace information Be Ot Pin arrangement JEX
19. rs Both Multi and PARTNER are high performance high level language debuggers that enable program execution break point setting variable inspection and other operations to be performed at the source level E nnection RTE 200 TP provides debugging capabilities equivalent to those of conventional in circuit emulators with the user system connected to the designated connector and the processor mounted on the board Highly transparent emulation By controlling the debugging control circuit DCU incorporated into CPU from the outside RTE 200 TP provides highly transparent emulation eliminating the problems associated with electrical interfaces ROM emulation RTE 200 TP incorporates up to 4MB of emulation memory for emulating ROMs probes for packages with 32 to 42 pins are available All probes are options Real time trace RTE 200 TP enables real time trace which is useful for debugging built in systems This capability uses a technique in which trace information conforming to the N Wire specifications is recorded into memory and supports trace clocks with frequencies of up to 66 MHz Communication with the host system via a dedicated card or LAN BOX Three types of cards and LAN BOX are available e The PC card is of Type Il as defined in version 2 1 of the PCMCIA specifications version 4 2 of the JEIDA specification and is for note type PCs The host card is for desktop PCs equipped with the PC 9800 C bus or DOS
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