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ADS512101 - Silicon Turnkey Express

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1. Pin No Description Pin Description 49 3 3 5 94 _ AD2 50 GND6 95 AD3 51 AD21 96 __ ADO 52 _ AD22 97 5 2 53 AD19 98 Reserved WIP1 54 020 99 55 GND7 100 Reserved WIP2 56 PAR 101 GND14 57 AD17 102 GND15 58 AD18 103 AC SYNC 59 not BE2 104 not M66E 60 AD16 105 AC SDIN 61 not IRDY 106 AC SDOUT 62 GND8 107 _ AC BCLK 3 3V6 108 AC CODEC IO 64 nofFRAME 109 AC CODECID1 65 not CLKRUN 110 RESET 66 not TRDY 111 MOD AUDIO MON 67 not SERR 112 Reserved 68 not STOP 113 AUDIO GND1 69 9 114 16 70 3 317 115 AUDIO OUT 71 116 AUDIO IN 72 not DEVSEL 117 AOUT GND 73 C nofBE1 118 AIN GND 74 GND10 119 AUDIO GND2 75 AD14 120 AUDIO GND3 76 AD15 121 Reserved8 77 GND11 122 _ 78 AD13 123 5VANA 79 AD12 124 3 3VAUX2 80 AD11 81 AD10 906 DVI I 82 GND12 Pin Description 1081 C1 _ ANALOG RED oi RSS C2 ANALOG SERE C3 ANALOG BLUE 99 Le NOBEN C4 ANALOG H SYNC SE IRE C5 1 ANALOG RTN1 SO C5 2 ANALOG RTN2 89 3 3 9 1 TX2 90 AD6 5 DOR S 205 3 TX2 4 SHLD 92 _ AD4 Tid 93 Reserved6
2. 35 6 8 06 VIDEO mM 35 6 8 07 EGD Backlighit tei e ete teni tasas 35 6 8 08 SATA Drive Interface tede Dios ec 35 6 8 09 Drive Iritertace i eo Hr Cherche deerit hes 36 6 8 10 36 6 8 11 HT 36 6 8 12 MiGtO S De E 36 VUE UU Io ELE 37 47 1 Standard Cormranads suoi eee 37 1 2 Start Up Display csie cen ea e rte a eee e o eet e REA ted 38 7 2 1 BOOR re D 38 7 2 2 Graphic Demonstration program spinning 38 7 2 3 Environment Variables set by 39 7 3 J Boot Instr cllons oerte tere etae 40 ALNU ORE 42 5 BSR eos Eo E A A E A A 42 8 2 Linux Auto 42 ADS512101 Page 7 of 56 September 4 2008 User Manual Rev 1 1 Appendix Appendix A Memory nene nnne nnn nenne 45 Appendix B Connector Pin 46 JO T Ethemet 46 JOZ AUCIO JACK ssc ai 46 46 306 EDAM 47 5VolEStand By
3. 19 3 2 2 P04 Boot Backup FLASH exit bet 19 3 2 3 Drive Voltage Select o iecit itc 19 3 2 4 P18 EEPROM WP tonio toc ice iudica ieu 19 3 2 5 P25 5 ec cot ledit edu ta 19 3 37 m 19 S NIENTE 19 LARUM 20 5 0 CPLD Configuration i n ete rh eere 21 9 01 21 5 02 GPLD Reglister 1 edet citet 21 9 03 CPLD Reglster 2 ete teo n Eod dee nh e eese 21 9 04 CRED 21 5 05 CPLD Register teinte tt 22 9 06 CPLD Reglister 5 edenda RE P ERE LR RUM 22 9 07 CRED Register PD 23 2 08 CPED Reglster RENE esee RERUM ERES 23 9 09 Register 24 5 10 GPED Register ERRARE ERR AREE ER 24 5 11 GPED 25 25 12 CPED Register AED RE D RE ae aa 25 5 19 CPED Register 12 ou 25 9 14 Register teo oet tees i ete 26 2 19 GPED Register eu toe RD 26 5 16 Register 15 ba i ae ta RE ERRAT 27 517 GPED Register
4. System Access Port yp Serial Advanced Technology Attachment SPDIF wit ee te ee Ae E ed Sony Philips Digital audio Interface Format Tap Linking Module TPM Test Port to Magenta Module a Triple Speed Ethernet Controller USB i i sedie pide adicit Universal Serial Bus reddened ee Battery Voltage Bypass Gide Watchdog Timer dette Ern er ue o Write Protect ADS512101 Page 55 of 56 September 4 2008 User Manual Rev 1 1 ADS512101 Page 56 of 56 September 4 2008 User Manual Rev 1 1
5. 14 1 1 36 P25 Power Switch 14 1 1 37 27 65232 UART aci reel Rest bo edes ca 14 1 1 38 28 ere doter eel duse tes ies ec rte bd ve een 14 1 1 39 P29 Micro SD Socket ete e bote ee 14 1 1 40 PWR 1 Power emen nennen nnns 15 1 1 41 PWR 2 DC Power 15 1 1 42 SW1 Power dot dee ed deb tre deed 15 1 1 43 SW2 Hibernate SwWilch niei eb dee te e c be ee bec uo 15 1 1 44 SW3 Mode intem od dedo e ceo dede te ees 15 ADS512101 Page 5 of 56 September 4 2008 User Manual Rev 1 1 Table of Contents 2 0 Hardware Design 4 Architecture sss eene menn 16 21 General Description eodera ree ce dhe qe Rode o ud d 16 2 2 Physical Specifications 2 Leg ie dere aL e eade 17 3 0 Control amp Configuration gettin 18 Sel SWIC SOUINGS s 18 3 1 1 SWI Power On Reset ie tpe aen eee bg 18 3 1 2 SW2 Hibemation Mode titor t eiie tette her 18 3 1 3 SW3 Boot MOG betreibt khoe idu 18 3 2 ER 19 3 2 1 P01 ATX Power Supply
6. a SDATA 1 3 Header Power Supply sequence 20 pin LVDS OK Figure 4 Block Diagram of ADS512101 Board ADS512101 Page 16 of 56 September 4 2008 User Manual Rev 1 1 2 2 Physical Specifications This section contains general information on the ADS512101 s physical characteristics Figure 5 ADS512101 Side View B ard mini ITX 170mm x 170mm Power Requirement or 5VDC Operating Temperature Standard Version uui etes Ep tnu 0 to 70 Industrial Vetsion i 40 to 85 M 200g pac Compliant ADS512101 Page 17 of 56 September 4 2008 User Manual Rev 1 1 3 0 Control amp Configuration This section contains general set up information about the various jumpers switches and LEDs found on the ADS512101 board Section 3 1 describes the function and recommended switch settings Section 3 2 describes the function and recommended jumpers on the board Section 3 3 describes the LED indicator function 3 1 Switch Settings This section provides a brief description of the functionality and recommended settings for the switches located on the ADS512101 Refer to Figure 2 for the locations of these switches 3 1 1 SW1 Power On Reset SW1 is a push button that provides a power on reset signal for the hardware on the ADS512
7. FLASH enable 0 enabled 0 Read Write ADS512101 Page 24 of 56 September 4 2008 User Manual Rev 1 1 5 11 CPLD Register 10 PCI Interrupt Masking Base Bit 1 interrupt is masked Value at reset Ability R W 7 PCI INTB SLOT3 1 Read Write 6 PCI INTA SLOT3 1 Read Write 5 PCI INTB SLOT2 1 Read Write 4 PCI INTA SLOT2 1 Read Write 3 PCI INTD SLOT1 1 Read Write 2 PCI INTC SLOT1 1 Read Write 1 PCI INTB SLOT1 1 Read Write 0 PCI INTA SLOT1 1 Read Write 5 12 CPLD Register 11 PCI Interrupt Status Base Bit PCI interrupts are received at the CPU on the PCI INTN Value at reset Ability R W signal this is a dedicated input on the CPU 0 pending corresponding mask bit also must be cleared 7 PCI INTB SLOT3 1 Read only 6 PCI INTA SLOT3 1 Read only 5 PCI INTB SLOT2 1 Read only 4 PCI INTA SLOT2 1 Read only 3 PCI INTD SLOT1 1 Read only 2 PCI INTC SLOT1 1 Read only 1 PCI INTB SLOT1 1 Read only 0 PCI INTA SLOT1 1 Read only 5 13 CPLD Register 12 Interrupt Routing Selection between CPU IRQO or IRQ1 Base 0 0 Bit Controls which IRQ is used for the listed IRQs Value at reset Ability R W 0 CPU IRQO 1 CPU IRQ1 7 SW1_HIBERNATE 0 Read Write 6 Secure Digital Card SD 0 Read Write 5 TOUCH SCR BUSYN 0 Read Write 4 TOUCH SCR off
8. eh iet ea de dites ena ette e RAE 54 02 5121 STAG pe Beca prd dee cea ee Pate ste ca ge ege cea bd 48 P03 Expansion D BOR dne Pee epo ee ae ERN 48 P05 S GPEDJ TAG idee ere se REP 49 POS UART Lee ect redet d e ee ca oe T e e P EP OD e TOL CREER VUE VeL CLR 49 POT DART nee eine a bed D 49 WAR A ale EUER 50 ale Bhan oo a Ie eae as ec i oe EEN 50 P09 esee Sel hee en Ree A ee A 50 PAO cities eee 50 12 2 2 ee ettet AA DeL ole valet see es 50 M D RM 51 PCI ae e e dr ede de 51 I IEEE 1850 EE 52 P16 SPDIF oe NO PS en Bo 52 P17 USB Mini AB Connector END bebe in 52 P19 ECD BackligliL ses Per tet ete e 52 20 EVDS CONNEC e eee eie 53 LCD TFT 53 P22 LCD TouUchS6treen 53 P23 POWerSWItCLl ari cet taie Remus cinta ceto 53 P24 Hibernate Switch iro citi testimo ecco ecco tu poA D Debent t 53 P27 UART 1 lIrterface eicit
9. eo cU oce hee cele e LOO bete o 53 P28 54 29 MiCKO2SD 54 Power GORFIGCIOF iioc tute cot 54 2 55V Power ee ed eto emt teo eer ette pese eain are cree Eu Ite 54 55 ADS512101 Page 8 of 56 September 4 2008 User Manual Rev 1 1 List of Figures Figure d ADSS12T01 10 Figure 2 05512101 Board Layout fet tea drei one 11 Figure ADS512101 Bottom Board 12 Figure 4 ADS512101 Block Diagram 16 Figure OD oNDS5121DB T EE iD DEUDA PEDE 17 Figure 6 U Boot Start Up SQIeeris 38 Figure 7 U Boot Re Install eene 41 List of Included Accessories User Manual on CD Schematic on CD 5V 15W Wall Mount Power Supply Null Modem Cable CodeWarrior Windows amp Linux Additional Freescale collateral material on CD List of Optional Accessories These accessories are available from Silicon Turnkey Express See the enclosed order form or visit web site
10. Bit 19 amp 18 RST CONF LPC DBW 01 LPC data port size 16 bit 20 CONF PS 1 FLASH page size 2k page size Bit 21 RST CONF DBW 1 NAND FLASH 8 bit data port size Bit 22 CONF CKS IN 0 checkstop input disabled Bit 26 to 23 RST CONF SYSPLL TBD Bit LPC AX3 31 to 27 CONF SYSDIV 6 6 Interrupts The CPU has 2 interrupt sources CPU IRQO and CPU The EPIC can receive 56 separate interrupts from three different interrupt domains as follows 2 external off chip interrupt signals sources are IRQ 1 0 57 internal on chip interrupt signals sources are DDR LPC PATA PCI MU FEC PSC FIFOC USB CSB arbiter CAN BDLC DIU AXE SPDIF SDHC RTC GTM I2C GPIO GPT SATA MBX TEMP IIM and PMC 1 external and 5 internal off chip interrupt signal source is IRQO On chip MCP interrupt signals sources are software watchdog timer WDT PCI temperature sensor and system bus arbiter SBA The CPLD accepts all other on board interrupts and multiplexes these interrupts onto the CPU s IRQ signals These will be user selectable see CPLD registers 12 to 15 PCI INTN PCI INTC SLOT1 FEC PHY INTN PCI INTD SLOT1 PCI INTA SLOT2 PCI INTB SLOT2 PCI SLOT3 PCI INTB SLOT3 PCI INTA SLOT1 PCI INTB SLOT1 PWR CPLD INT WATCHDOG TOUCH SCR IRQN TOUCH SCR BUSYN TEMP MON INT 67 Memory 671 DDR2 S
11. 10 NC NC2 Pin Name 11 NC NC3 1 12 SD CDZ CD SW1 2 GND 13 GND CD SW 3 Pwer Basrrel 6 14 GND GND1 4 15 GND GND2 16 GND GND3 17 GND GND4 P01 5Volt Stand By 2 pin Header Pin No Pin Name 1 5V 2 5V Standby ADS512101 User Manual Page 54 of 56 September 4 2008 Rev 1 1 Acronyms Below is a list of common terms and acronyms you may find incorporated in this manual AGO e tip e t e bee ede teorie a e ae Coe coe a Pe eei nied Audio Codec driver nupt Advanced Technology Extended mother board form factor AXE aite ee a doe 32 bit RISC Audio Acceleration Engine MM Byte Data Link Controller GAINS end PORE voc EE BER Dd Controller Area Network COP Debug Port CPED DE ed Eden n ten dead Complex Programmable Logic Device M Central Processor Unit DDR sinere d EE aad REEF Double Data Rate RAM acs dati dede Direct Memory Access DSP a etie Ra eda ith Digital Signal Processor idi acp e ie lie dai Digital Video Interface Input d External Memory Bus PEC cendo Redon itane de fe tet ac ie ERU TERN Fast Ethernet Controller eno eR eat codici tinet dede Giga
12. ADS512101 Page 47 of 56 September 4 2008 User Manual Rev 1 1 406 continued P03 Expansion Bus HARD RESET N NC Pin No Description Pin No Description 5 4 1 GND 6 DDC CLK 2 GND 7 DDC DATA 3 EMB ADO 8 ANALOG V SYNC 4 EMB AD1 9 1 5 EMB AD2 10 TX1 6 EMB AD3 11 TX1 3 SHLD 7 AD4 12 TX3 8 EMB AD5 13 TX3 9 EMB AD6 14 5VDC 10 AD7 15 GND 11 3 3VDC 16 TXO 12 3 3VDC 17 HP DETECT 13 18 14 AD9 19 TX0 5 SHLD 15 EMB AD10 20 TX5 16 EMB AD11 21 TX5 17 EMB AD12 22 TSC SHLD 18 EMB AD13 23 TXC 19 EMB AD14 24 TXC 20 EMB AD15 25 SHELL1 21 GND 26 SHELL2 22 GND 23 EMB AD16 P02 MPC5121e JTAG 24 EMB AD17 16 pin Header 25 EMB AD18 26 AD19 Pin Description 27 EMB AD20 28 EMB AD21 29 AD22 30 EMB AD23 31 3 3406 2 3300 6 3 3VDC 33 EMB AD24 uc 25_ ENB 38 EMB AD29 39 EMB AD30 40 AD31 5121 CPU CHKSTP OUT GND ADS512101 User Manual Page 48 of 56 September 4 2008 Rev 1 1 P03 Expansion Bus continued 52 TP117 62 TP115 CPU GPIO15 TP120 70 TP113 71 72 TP112 2 41 42 43 44 45 46 47 48 49 50 51 53 54 55 56
13. U Boot Re Installing Screen ADS512101 Page 41 of 56 September 4 2008 User Manual Rev 1 1 8 0 Linux 8 1 Freescale s Linux BSP For current versions of Freescale s Linux visit www freescale com 8 2 Linux Auto Boot Display Booting kernel from Legacy Image at ffc40000 Image Name Linux 2 6 24 6 Created 2008 08 27 20 57 35 UTC Image Type PowerPC Linux Kernel Image gzip compressed Data Size 1783490 Bytes 1 7 MB Load Address 00000000 Entry Point 00000000 Verifying Checksum OK Uncompressing Kernel Image OK Flattened Device Tr blob at ffec0000 Booting using the fdt blob at Oxffec0000 Loading Device Tree to 007fa000 end 007fffff 0 000000 Using MPC5121 ADS machine description 0 000000 Linux version 2 6 24 6 derazmus r21893 11 linux gcc version 4 1 2 1 PREEMPT Wed Aug 27 15 57 10 CDT 2008 0 000000 MPC5121 ADS board from Freescale Semiconductor 0 000000 preallocate diu videomemory diu size 5242880 0 000000 preallocate diu videomemory diu mem c4500000 0 000000 Found MPC512x PCI host bridge at 0x0000000080008500 Firmware bus number 0 gt 0 0 000000 Zone ranges 0 000000 0 gt 65536 0 000000 Normal 65536 gt 65536 0 000000 Movable zone start PFN for each node 0 000000 early node map 1 active PFN ranges 0 000000 0 0 65536 0 000000 Built 1 zonelists in Zone order mobility grouping on Total page 65024 0 000000 Ke
14. 00alpha2 0 873013 ide Assuming 33MHz system bus speed for PIO modes override with debus xx 0 881793 Driver sd needs updating please use bus type methods 0 892548 fc000000 flash Found 2 x16 devices at 0 0 in 32 bit bank 0 898984 Amd Fujitsu Extended Query Table at 0x0040 0 904364 fc000000 flash CFI does not contain boot bank location Assuming op 0 911917 number of CFI chips 1 0 915255 cfi cmdset 0002 Disabling erase suspend program due to code brokeness 0 923178 RedBoot partition parsing not available 0 928026 Creating 5 MTD partitions on fc000000 flash 0 933473 0x00000000 0x00040000 protected 0 939033 0x00040000 0x03c40000 filesystem 0 944388 0x03c40000 0x03ec0000 kernel 0 949373 0x03ec0000 0x03 00000 device tree 0 955121 0x03 00000 0x04000000 u boot 0 960320 MPC5121 MTD Driver 0 2 0 964706 NAND device Manufacturer ID Chip ID Hynix NAND 512MB 3 3V 8 bit 0 973357 2 NAND chips detected 0 979815 mpc5121r2nfc 40000000 nfc Using OF partition info 0 985771 Creating 1 MTD partitions on NAND 0 990332 0x00000000 0x40000000 nand 0 996831 Initializing USB Mass Storage driver 1 002188 usbcore registered new interface driver usb storage 1 008179 USB Mass Storage support registered 1 013153 mice PS 2 mouse device common for all mice 1 019714 mpc5121 rtc 80000a00 rtc rtc core registered mpc5121 rtc rtc0 1 027110 i2c dev entries driver 1 031878
15. 8 B5 5V 1 B28 GND20 5 5V A28 AD22 B6 5V 2 B29 AD21 A6 not INTA A29 AD20 B7 not INTB N30 AD19 AT not INTC A30 GND11 B8 not INTD B31 3 3V 2 A8 5V5 A31 AD18 B9 not PRSNT1 B32 AD17 A9 Reserved3 A32 AD16 B10 Reserved1 B33 C not BE2 A10 3 3V A33 3 3V 9 B11 not PRSNT2 B34 GND3 A11 Reserved4 A34 not FRAME B12 B35 not IRDY A12 A35 GND12 B13 B36 3 3V 3 A13 A36 not TRDY B14 Reserved2 B37 not DEVSEL A14 3 3v AUX A37 GND13 B15 GND1 B38 GND4 A15 not RST A38 not STOP B16 CLK B39 not LOCK A16 3 3V 1 0 3 A39 3 3V 10 B17 GND2 40 not PERR A17 GNT A40 Reserved5 B18 not REQ 41 3 3V 4 A18 GND9 41 Reserved6 B19 3 3V 1 B42 not SERR A19 not PME ADS512101 Page 51 of 56 September 4 2008 User Manual Rev d1 P14 PCI continued P15 J1850 Pin Pin Name 3 pin Header 42 GND14 Pin No Pin Name 43 3 3V 5 1 CPU J1850 TX A43 PAR 2 CPU J1850 RX B44 C not BE1 3 GND A44 AD15 B45 AD14 P16 SPDIF Bas 4 pin Header B46 GND5 A46 AD13 Pin Name B47 AD12 1 SPDIF TXCLK 47 AD 2 SPDIF TX B48 AD10 3 SPDIF RX A48 GND15 4 GND 549 NOSEN P17 USB Mini AB Connector B50 GND6 Pin Name GND16
16. Connector Pin Assignments J01 Ethernet J3 J4 Mini PCI 2 3 continued Pin No Description Pin Description 1 TOT 7 8PMJ7 2 TDP 8 8PMJA 3 TDN 9 8PMJ8 4 RDP 10 8PMJ5 5 RDN 11 LED1P 6 RCT 12 LED2P 7 LD1C 13 LED1N 14 LED2N 5 m 15 CHSGND 16 Reserved1 17 not INTB 18 5 1 26 G2 19 3 3V1 20 not INTA J02 Audio Jack 21 edid Pin No Description 22 Reserved3 1 SHIELD GND 23 GND1 J2C Microphone 24 3 3VAUX1 2 RIGHT MIC 2 OUTER 25 CLK 3 AGND 26 not RST 4 LEFT MIC 1 INNER 27 GND2 5 AGND 28 3 3V2 J2B Line Out 29 not REQ 22 RIGHT HP OUT OUTER 30 not GNT 23 AGND 31 3 3V3 24 LEFT HP OUT INNER 32 GND3 25 AGND 33 AD31 J2A Line In 34 32 RIGHT LINE IN OUTER 35 AD29 33 AGND 36 Reserved4 34 LEFT LINE IN INNER 37 GND4 35 AGND 38 AD30 39 AD27 J3 J4 Mini PCI 2 3 41 25 Description 42 AD28 1 TIP 43 RSVD5 2 RNG 44 AD26 3 8 45 C not BE3 4 8PMJ1 46 AD24 6 8 2 48 IDSEL ADS512101 Page 46 of 56 September 4 2008 User Manual Rev 1 1 4344 Mini PCI 2 3 continued J3 J4 Mini PCI 2 3 continued
17. Data Link Layer ISO 11898 defines the Physical Layer The CAN bus CAN bus is a balanced differential 2 wire interface running over either a Shielded Twisted Pair STP Un shielded Twisted Pair UTP or Ribbon cable Each node is connected to a male 9 pin D connector and a 10 pin header The Bit Encoding used is Non Return to Zero NRZ encoding with bit stuffing for data communication on a differential two wire bus The use of NRZ encoding ensures compact messages with a minimum number of transitions and high resilience to external disturbance Both CAN buses are directly connected to the MPC5121e s dedicated CAN bus and use a transceiver ADS512101 Page 34 of 56 September 4 2008 User Manual Rev 1 1 6 8 04 12 Bus Two 2 ports use Port 0 and Port 2 Port 0 2 is used for Serial EEPROM with address set to binary 1 0 1 0 A2 AO R W or 0 Temperature monitor with address set to binary 1 0 0 1 A2 1 AO R W or 0x90 Remote 8 bit expander with address set to 0x70 RTC with address hard coded at OxDO A battery backup is provided and is automatically switched within the device The RTC provides a square wave output RTC CLK OUT is connected to the CFG CPLD RTC CLK OUT is connected to the PS CPLD RTC CLK OUT is connected to the CPU as an optional input instead of the XTAL X1 Port 2 12C2 is used for Digital potentiometer with address is hard coded to Ox5C Digital Transmitter with ad
18. J2C Pink User Mic In LEDs USB Power Figure 2 ADS512101 Top Board Layout ADS512101 Page 11 of 56 September 4 2008 User Manual Rev 1 1 29 MicroSD ADS5121E 04 Silicon Turnkey Express STX 749 77738 m m i 15 IH Figure 3 ADS512101 Bottom Board Layout 1 1 01 BT1 Battery 1 1 04 J03 Connector Use a 3 Volt Lithium button battery See Figure 3 PCB Rev 1 x and 2 x used type CR2032 is a 32 bit connector with or equivalent PCB Rev 3 x or higher 3 3v that uses ID SEL AD22 1 1 05 404 Connector See Figure 3 1 1 02 J01 RJ45 10 100 BaseT J4 is a 32 bit connector with J1 is a standard Ethernet input jack 3 3v that uses ID SEL AD23 1 1 03 J02 Audio Connectors 1 1 06 J05 SATA Interface J2 has three stereo connection J2A J5 is the serial ATA interface connector Blue is Line In J2B Green is Line Out J2C Pink is Aux In ADS512101 Page 12 of 56 September 4 2008 User Manual Rev 1 1 1 1 07 406 DVI I 46 is the Digital Video Interface 1 1 08 LED 1 5V Good Indicates when 5 Volts is on 1 1 09 LED 2 to 5 CPLD Is user definable by the CPLD 1 1 10 LED 6 ATA Activity Indicates when ATA data fetches occur 1 1 11 LED 7 USB Power Indicates when USB power is on 1 1 12 P01 5V Only Operation
19. Pin Name Pin Pin Name 1 GND SW1 TOGGLEN PULSE 2 VID CLK 0 1 DEBOUCE 3 VID HSYNC 2 GND 4 VID VSYNC 5 GND P24 Hibernate Switch 6 VID REDO 2 pin Header VID REDI Pin No Pin Name 9 VID RED3 es 10 VID_RED4 11 VID RED5 GND P27 UART 1 Interface 13 VID GREENO Pin No Pin Name 14 VID GREEN1 1 3 3 V 15 VID GREEN2 2 5V 16 VID_GREEN3 3 GND 17 VID_GREEN4 4 GND 18 VID_GREEN5 5 UART1_TXD 19 GND 6 UART1_RXD 20 VID_BLUEO 7 NC 21 VID BLUE1 8 NC 22 VID BLUE2 ADS512101 Page 53 of 56 September 4 2008 User Manual Rev 1 1 P28 Audio PWR 1 ATX Power Connector 10 pin Header Pin No Description Pin No Pin Name 1 3 3VDC FUSED F2 1 AUD C AUX R 2 3 3VDC FUSED F2 2 AUD C AUX L 3 GND 3 GND 5V ONLY WALL PS OR 4 CONNECTOR 4 GND 5 GND 3 5V ONLY WALL PS OR 6 AUD C LOUT L 6 4PIN CONNECTOR 7 AUD C CD GND 7 GND 8 AUD C CD GND 8 POWER OK 9 AUD C CD INR 9 5V STANDBY 10 AUD C CD INL 10 12VDC 11 3 3VDC FUSED F2 P29 Micro SD 12 42VDC Pin Pin Name 13 GND 1 NC DAT2 14 POWER ONN 2 CPU PATA DACKZ CD DAT3 15 GND 3 CPU IOWZ CMD 16 GND 4 3 3v Vcc 17 GND 5 CPU PATA IORZ CLOCK 18 NC 6 GND GND 19 5VDC 7 CPU PATA IOCHRDY DATO 20 5VDC 8 CPU PATA INTRQ DAT1 9 NC NC1 PWR 2 5V Power Connector
20. See Jumpers Section 3 2 6 1 1 13 P02 JTAG Connector Connector P02 is a 16 pin header used for the COP JTAG input This port is made available to aid in the programming of the ADS512101 The pin outs for the connector are listed in Appendix A A JTAG interface device such as the Abatron s BDI2000 or Freescale s CW USB TAP or equivalent should be used 1 1 14 P03 Expansion Bus provides signals for EMB PLC and GPIO See Appendix C for pin out 1 1 15 P04 Back Up FLASH Normally Open A jumper is used to re FLASH U Boot to main FLASH See Section 7 3 Re Installing U Boot Instructions 1 1 16 P05 CPLD Header 5 is a CPLD JTAG port for programming and application debugging of the CPLD An Altera Quartus with a Byteblaster cable or equivalent programming should be used 1 1 18 P07 RS232 UART 0 P7 is a 9 pin D style connector for serial communications 1 1 19 P08 RS232 P8 is a header connector for an additional RS232 connector See Appendix B for pin out 1 1 20 P09 CAN 0 P9 is a 9 pin D style connector for Control Area Network 1 1 21 P10 CAN 1 P10 is a header connector for an additional CAN connector See Appendix B for pin out 1 1 22 11 ATA Drive Select See Jumper Section 3 2 3 1 1 23 P12 PATA Connector P12 is a 40 pin connector for attaching an optional parallel device 1 1 24 13 Front Panel ATA LED P13 is a 2 pin header
21. September 4 2008 User Manual Rev 1 1 Standard Commands continued saveenv save environment variables to persistent storage setenv set environment variables sleep delay execution for some time test minimal test like bin sh tftpboot boot image via network using TFTP protocol version print monitor version 7 2 Start Up Display U Boot 1 3 4 Sep 4 2008 15 00 00 MPC512X CPU MPC5121e rev 2 0 Core e300c4 at 399 999 MHz CSB at 199 MHz Board ADS5121 rev 0x0400 CPLD rev 0x05 512 64 Bus Dev VenId DevlId Class Int serial serial serial Net FEC ETHERNET Type run jffs2boot to boot Linux Hit any key to stop autoboot 0 Figure 6 U Boot Start Screen 7 2 1 Auto Linux Boot If Freescale s Linux has been pre loaded in the ADS512101 it will auto boot from U Boot The following information will appear after U Boot runs Booting kernel from Legacy Image at ffc40000 Image Name Linux 2 6 24 6 Created 2008 08 27 20 57 35 UTC Image Type PowerPC Linux Kernel Image gzip compressed If you do NOT want Linux to boot press any key after U Boot is running Linux takes several minutes to load and boot Linux is operating when the command line prompt appears Linux Prompt sh 2 05b 7 2 2 Graphic Demonstration program spinning vehicle A demonstration program may be loaded in your ADS512101 This program can be launched by typing after the Linux prompt demo
22. User Manual Rev 1 1 NOTICE The information contained within this guide is the property of Silicon Turnkey Express STx and except as otherwise indicated shall not be reproduced in whole or in part without the explicit written authorization of STx The distribution of this document outside of the company is prohibited without the written authorization of STx The following information is intended to alert the user to possible dangers and important information contained within this guide The WARNINGS CAUTIONS and NOTES do not eliminate these dangers Close attention to the information supplied along with common sense operation is the major accident prevention measure WARNING Failure to follow this warning may result in bodily injury CAUTION Failure to follow this caution may result in possible damage to the board NOTE Failure to follow this note may result in improper results from the board ADS512101 Page 3 of 56 September 4 2008 User Manual Rev 1 1 Reference Websites Below is a list of websites that can be used to obtain additional information and details that may not be fully provided in this manual Abatron BDI2000 JTAG Emulator www ultsol com mfgs emul abtr htm Altera Quartus emn nm nre www altera com CodeWarrior USB TAP www freescale com STx Support Site Updates amp Downloads www si
23. Value at reset Ability R W 7 Hibernation event must write 0 to clear this bit 0 Read Write This was removed and needs to be read within the CPU See Hibernation Section 6 2 3 for detailed explanation 6 TOUCH RESET on board touch screen U38 rev 4 only 0 Read Write 5 UARTO FOFF Z 1 Read Write 4 UART1_FOFF ADS5121e Rev 4 only 1 Read Write 3 TOUCH 1 MASKING on board touch screen U38 1 Read only rev 4 only 2 TOUCH 1 IRQ STATUS on board touch screen U38 1 Read only rev 4 only CPU IRQ Routing is the same as set for the off board touch screen controller Register 12 bit 4 1 PATA RESET 1 Read only 0 FEC PHY RSTN 1 Read only 5 17 CPLD Register 16 Video Control 1 Base 0x010 Bit Value at reset Ability R W 7 LCD LVDS FRAME RATE 0 Read Write 6 Reserved 0 Read Write 5 DVI MSEN 0 Read only 4 LCD LVDS SDIRn 0 Read Write 3 Reserved 0 Read only 2 DVI DAC PWRDNn 0 Read only 1 VGA DAC PWRDNn 0 Read only 0 LCD PWR DWNn 0 Read only ADS512101 Page 27 of 56 September 4 2008 User Manual Rev 1 1 5 18 CPLD Register 17 User LED Base 0x01 1 Bit Value at reset Ability R W 7 LED Control OZLEDO Reset Status 1 User Control 0 Read Write register 17 0 6 LED 2 Control O LEDO Reset Status 1 User Control 0 Read Write register 17 0 5 LED 1 Control O LEDO Reset Status 1 User Control 0 Read Write register 17 0 4 LED 0 Control O LEDO Reset Statu
24. an external power supply connected to PWR 2 It must be removed to use an ATX power supply 3 2 2 P04 Boot Backup FLASH Default Open When this jumper is installed powering the ADS512101 will launch U Boot in a protected back up FLASH and reinstall U Boot to main FLASH 3 2 3 P11 ATA Drive Voltage Select CAUTION Failure to follow this caution may result in possible damage to the board Be sure to select the correct voltage setting for the drive used prior to turning the power on to the board Default 3 3 Volts Pins 1 amp 2 Jumper P21 selects the appropriate power setting 3 3 or 5 0 per the ATA specification for the drive in use Pin No Description 1 2 PATA 3V PWR 2 3 PATA 5V PWR 3 2 4 P18 EEPROM WP Default Open With this jumper installed the EEPROM can be accessed allowing it to be programmed erased as needed When the jumper is removed the EEPROM cannot be programmed 3 2 5 P25 Power By Pass Default Open With this jumper iinstalled the Power On switch is by passed The ADS512101 will launch U Boot when power is applied 3 3 LED Indicators This section provides a list of functions for the LEDs on the ADS512101 board Refer to Figure 2 for the locations of these LEDs See CPLD Register 17 Section 5 18 for additional information LED Function Color 1 5VDC GOOD GREEN 2 USER DEFINED RED 3 USER DEFINED YE
25. off u boot_addr filesize era u boot_addr filesize cp b u boot_addr_r u boot_addr filesize upd run load update ethact FEC ETHERNET ethaddr 00 1E 59 7B 4E B9 kernel addr 0xff900000 bmp addr 0xffe40000 initrd high 0x1000000 u boot ads5121 u boot bin preboot echo echo run jffs2boot to boot Linux othbootargs mem 512M fdtflashaddr 0xffec0000 kernelflashaddr 0xffc40000 consoledev ttyPSCO jffs2boot set bootargs console consoledev baudrate root dev mtdblockl rw rootfstype jffs2 S othbootargs bootm kernelflashaddr fdtflashaddr bootcmd run jffs2boot filesize 3000 fileaddr 100000 stdin serial stdout serial stderr serial Environment size 1862 8187 bytes ADS512101 Page 39 of 56 September 4 2008 User Manual Rev 1 1 7 3 Re Install U Boot Instructions The ADS512101 has a protected back up FLASH memory for U Boot If U Boot should become corrupt for any reason U Boot can be re installed Please follow these instructions to re flash U Boot to the main memory 1 Remove power from the ADS512101 2 Install a jumper on the Up Flash Header P4 3 Reconnect power to the ADS5121 and use SW1 to launch U Boot This process will write the back up U Boot to main memory Follow the on screen instructions 4 Remove power from the ADS512101 5 Remove the jumper from header 6 Reconnect power to the ADS512101 and use S
26. 00 0001 default CPLD drives Reset Configuration Word Bit Ability to read Configuration switches through software Value at reset Ability R W Switch definitions are from 5121 user manual HRW 7 RST CONF SYSDIV EMB AXO driven 0 CFG word 31 Read only 6 RST CONF SYSDIV System PLL divider CFG word 30 Read only 5 RST CONF SYSDIV CFG word 29 Read only 4 RST CONF SYSDIV CFG word 28 Read only 3 RST CONF SYSPLL System PLL Multiply factor CFG word 27 Read only 2 RST CONF SYSPLL CFG word 26 Read only 1 RST CONF SYSPLL CFG word 25 Read only 0 RST CONF SYSPLL CFG word 24 Read only 5 06 CPLD Register 5 Configuration switch settings EMB AD 23 16 Base 0x05 0x1000 1101 default CPLD drives Reset Configuration Word Bit Ability to read Configuration switches by software Value at reset Ability R W Switch definitions from 5121 user manual HRW 7 RST CONF SYSPLL System PLL Multiply factor CFG word 23 Read only 6 RST CONF CKS IN Checkstop disabled CFG word 23 Read only 5 RST CONF NFC DBW NAND data port 8bit CFG word 21 Read only 4 RST CONF NFC PS NAND FLASH page size 2Kbytes CFG word 20 Read only 3 CONF DBW LPC DATA port 11 32 bit CFG word 19 Read only 2 RST CONF LPC DBW CFG word 18 Read only 1 Reserved not mentioned in manual CFG word 17 Read only 0 RST CONF LPC MXLPC Multiplexed mode CFG word 16 Read only ADS512101 Page 22 of 56 September 4 2008 Use
27. 1 USB CONMB PWR B51 GND7 2 USB CONMB DN A51 GND17 3 USB DP B52 ADOS 4 USB CONMB ID 52 C not BEO 5 GND B53 007 6 SHIELD GND A53 3 3V 12 7 SHIELD GND B54 3 8V 6 8 SHIELD GND 54 06 9 SHIELD GND B55 05 A55 04 P19 LCD Backlight B56 ADOS Pin Pin Name A56 GND18 1 12VDC B57 GND8 5 12VDC A57 02 3 GND B58 01 4 GND 5 LCD PWRDNN Eus 6 B DIGITAL POT 10K A59 3 3 I O 4 7 W DIGITAL 10K B60 not ACK64 8 NC A60 not REQ64 B61 5V 3 A61 5V6 B62 5V4 A62 5V7 ADS512101 Page 52 of 56 September 4 2008 User Manual Rev 1 1 P20 LCD LVDS Connector P21 LCD TFT 18bit continued Pin No Description Pin Pin Name 1 03 23 VID BLUE3 2 D3 24 VID BLUE4 3 DPS 25 BLUE5 4 FRC 26 GND 5 GND1 27 VID_BLANK 6 CK 28 LCD_TFT 7 CK 29 LCD_TFT 8 GND2 30 SCANDIR1 9 02 31 SCANDIR2 10 D2 32 NC 11 GND3 33 NC 12 01 13 D1 P22 LCD Touchscreen 14 GND4 Pin No Pin Name 15 DO 1 TS XP 16 2 17 GND5 3 TS XM 18 GND6 4 TS YM 19 VCC1 5 GND 20 VCC2 P23 Power Switch P21 LCD TFT 18bit 2 pin Header Pin No
28. 101 The push button can be remotely locate with connector P27 Push once to power on board and push and hold for five seconds to power down board 3 1 2 SW2 Hibernation Mode SW2 provide hibernation request to the ADS512101 Push once to put ADS512101 in hibernation mode Push again to bring ADS512101 out of hibernation 3 1 3 SW3 Boot Mode CAUTION Failure to follow this caution may result in possible damage to the board For proper operation these switches should be left in the factory default position SW3 Boot Mode Continued SW3 is the CPLD Boot Configuration Reset functions of the ADS512101 Refer to CPLD Register 18 Section 5 19 for additional information SW3 is a single pole single throw SPDT 8 position switch used to configure the CPLD for booting the ADS512101 during power up All switches should be set to factory default normal operation ON State Function OFF Watchdog Disabled 4 Undefined Resened OFF Resev M66en must also be high for 66mhz ADS512101 User Manual Page 18 of 56 September 4 2008 Rev 1 1 3 2 Jumper Settings This section provides a brief description of the functionality and recommended settings for the jumpers located on the ADS512101 Refer to Figure 2 for the locations of these jumpers 3 2 1 P01 ATX Power Supply Operation Default Open This jumper must be installed to use
29. 16 er E ERR 27 5 18 CPLD Register 28 5 19 CPLD Register 18 ette ede dete ae v dus 28 6 0 Operations i tete te a eae uite te i teretes leder 29 61 Central Processing ede cene iata e eda 29 62 Power sUpplies edet den tu cebat ile a et ela 29 6 2 1 Power Rall inte ed e 29 6 2 2 Power Sequencing eoe ena de ives d heeds 30 6 2 3 Hibernation Mode ete eade en e 31 6 3 EE 32 64 Clocks aede eret eu ene ace 32 65 CPU Configuration tee ecc e tee n ena dede 32 6 6 Interr pts edad d 33 67 Memory estote dere 33 6 7 1 DDR2 SDRAM bete ab ve aee 33 6 7 2 n ditat dee rd dede 34 6 7 3 NAND FLASH 34 ADS512101 Page 6 of 56 September 4 2008 User Manual Rev 1 1 Table of Contents 68 MVO FUNCION E ete eco t 34 6 8 01 10 100 Ethernet t pe Edu ev Pede dee ean dea 34 6 8 02 RS232 POr AWE 34 6 8 03 BU EAM 34 6 6 04 12 35 6 6 05 AUDIO and Touch Screen
30. 21 will be responsible for the PCI arbitration and interrupt controller The MCP5121 provides te interface to local on board resources including NOR FLASH memory NAND FLASH memory DDR2 SDRAM memory CPLD MII 10 100 Fast Ethernet Controller 2 EEPROM STM programmable serial controller for RS232 and AC97 audio Interrupt controller USB 2 0 PCI bus PCI controller Graphics on chip MBX controller PATA controller SATA controller and Micro SD See MPC5121e user manual for detail descriptions for each interface 6 2 Power supplies The ADS512101 board requires a mini ATX power supply 20 pins connector can be used or a 5v external power supply When using a 5v external power supply functions requiring 12v will not operate If a 5v external power supply is used jumper P1 is required The jumper connects the 5v with the 5v stby voltage which is required for the power up circuitry 6 2 1 Power Rails The ADS512101 board requires several power rails that are provided on board and include 1 4v TBD for the CPU Core voltage 1 2v 0 5A for the CPU Core voltage 1 8v for the CPU Core voltage 0 9v 3 3A for the CPU Core voltage 3 3v 2 0A for the CPLD reset circuitry clocks CPU I O and peripheral logic 12v Q 2A direct input from off board power supply for disk drive power and LCD ADS512101 Page 29 of 56 September 4 2008 User Manual Rev 1 1 Power Rails continued The
31. 57 58 59 61 63 64 65 7 6 73 74 75 76 77 78 79 P05 CPLD JTAG 10 pin Header Pin No Description CPLD TCK GND CPLD TDO 5V STANDBY CPLD TMS NC NC NC CPLD TDI GND P06 UART 0 10 pin Header Pin No Description NC CSER PB RXD CSER PB TXD NC GND NC CSER PB RTS CSER PB CTS 5 09 P07 UART 0 Pin No Description CSER RXD CSER PA TXD 005 GND 004 CSER PA RTS CSER PA CTS 006 ADS512101 User Manual Page 49 of 56 September 4 2008 Rev 1 1 P08 UART 1 12 PATA Connector 10 pin Header Pin No Description Pin Description 1 PATA CON RESET 1 NC 2 GND 2 CSER PB RXD 3 PATA CON AD7 3 CSER PB TXD 4 PATA CON AD98 4 NC 5 PATA CON AD6 5 GND 6 PATA CON AD9 6 NC 7 PATA CON AD5 7 CSER PB RTS 8 PATA CON AD10 8 CSER PB CTS 9 PATA CON AD4 9 NC 10 PATA CON AD11 10
32. 8 NOR FLASH Control Base 0x08 0x00000000 default configuration CPLD drives Reset Configuration Word Velveatreset 7 Back up FLASH Write Protect 1 Full write protected Read Write Write enable signal held high 6 Back up FLASH sector write protect 5 Boot FLASH Write Protect 1 Full write protected Write enable signal held high Boot FLASH sector write protect 1 1 Read Write 1 Read Write 1 Read Write 1 Boot or Backup FLASH status 0 Backup 1 Boot X Read only Dependant on P4 Jumper jumper installed Backup Or if OxAA is written to register 2 R W Control is Read Write immediate Backup NOR FLASH reset will be released from reset at power up if configuration is set for Backup FLASH Boot NOR FLASH reset 1 Read Write will be released from reset at power up if configuration is set for Backup FLASH Read Write NOR FL RDY tT Read only 5 10 CPLD Register 9 NAND FLASH CAN MEDIA GPIO Control Base 0x09 Bit Currently only chip select 0 is used Value at reset Ability R W chip select 1 3 are for future expansion 7 MEDIA GPIO 0 Read only 6 Reserved 0 Read Write 5 Reserved 0 Read Write 4 CAN Shut Down 0 Shut Down 0 Read Write 3 NAND FLASH enable 0 enabled 1 Read Write 2 FLASH enable 0 enabled 1 Read Write 1 FLASH enable 0 enabled 1 Read Write 0
33. ART 1 This is a 10 pin header to accommodate an external serial port 1 1 38 P28 Audio This is a 10 pin header to accommodate external audio connections 1 1 39 P29 Micro SD Socket See Figure 3 P29 allows use of any Micro SD memory ADS512101 User Manual Page 14 of 56 September 4 2008 Rev 1 1 1 1 40 PWR 1 ATX Power Connector PWR 1 is the main ATX power input connector for the ADS512101 It is designed to use a standard 20 pin ATX power supply 1 1 41 PWR 2 DC Power Input PWR 2 is the 5VDC to the board P01 needs to be installed to enable the on board power signal See Section 3 2 1 1 1 42 SW1 Power Switch See Switch Settings Section 3 1 1 1 1 43 SW2 Hibernate Switch See Switch Settings Section 3 1 2 1 1 44 SW3 Mode Switch See Switch Settings Section 3 1 3 ADS512101 User Manual Page 15 of 56 September 4 2008 Rev 1 1 2 0 Hardware Design amp Architecture 2 4 General Description Some of the features of the ADS512101 are Freescale Processor MPC5121e DDR2 RAM module capacity 512Mbyte to 2 Gbytes JTAG and control CPLD LVDS 24 bit LCD or CMOS Rev3 RS 232 and CAN port USB A B and OTG NOR NAND and backup FLASH Local bus IO connector Stereo Audio AC97 SATA PATA IDE Micro SD PCl mini PCl radio slots SATA Standard 7 pin 32 bit PCI BEES Mini PCI 32 bit slot Mini USB 5 DDR1 2 Memory Interface
34. Accessories Add On Features e Cases with custom silkscreen Bluetooth Radio e Backplates Custom silkscreen e Camera Image Capture e Microphone e GPS module e Echo Cancellation module e Profibus Fieldbus e LCDs Inverter Touchscreen e Monitors Touchscreen e USB 802 11 Radio MiniPCI WiMAX Radio e DRAM Modules e Memory Upgrades Software e Hard Drive IDE or SATA Operating Systems e Solid State Hard Drive FLASH Graphic Solutions e CD ROM or DVD Drive Cellular Connectivity e Wall Cube Power Supplies GPS Location Int IP Touchscreen un Ower Bluetooth Technology e PCI Riser Cards e Voice Recognition e Peripherals inside the case e Wireless e Cables All kinds amp Customs e Database Client ADS512101 Page 9 of 56 September 4 2008 User Manual Rev 1 1 1 0 General Description The ADS512101 Advanced Development System is a mini ITX form factor reference and mother board based Freescales 5121 microprocessor The board will provide on board DDR SDRAM NOR FLASH NAND FLASH 2 4 wire RS232 ports 2 CAN ports USB 2 0 10 100 Ethernet Audio in out mic SATA and PATA drive support PCI Micro SD 24bpp graphics all powered from a standard ATX or 5 Volt wall mount power supply The board can be integrated into any configuration required by the addition of optional peripherals These would include items such enclosures displays HDD numerous other
35. DRAM The dedicated DDR2 memory bus is 32 bits data single bank 256 Mbytes Max 200 MHz no ECC It uses the MPC5121e DDR2 SDRAM controller and is directly connection to the MPC5121e ADS512101 Page 33 of 56 September 4 2008 User Manual Rev 1 1 6 7 2 NOR FLASH The FLASH memory is 64 Mbytes total 16 bits wide and its interface consists of 3 devices 2 banks of main FLASH and 1 bank of BOOT Flash The FLASH uses the chip select 50 This chip select is connected to the CPLD and the CPLD directs the appropriate NOR FLx CSN signal to the correct FLASH 6 7 3 NAND FLASH Not operational in Revision 1 or Revision 2 of ADS512101 Dedicated NAND FLASH memory is 1 GB and directly connected to the MPC5121e 6 8 I O Function See Appendix B for pin definitions 6 8 01 10 100 Ethernet The 10 100 Ethernet port uses the Freescale MPC5121e interface and a standard RJ45 connector with indicator LEDs and a 10 100 Ethernet PHY The Port 0 PHY address is 00001 6 8 02 RS232 Port 4 wire PSC programmable serial controller ports can be configured as UART RS232 4 wire port The PSC is configured within the MPC5121e see user MPC5121e manual for details on setting up PSC Transceivers are directly connected to both the CPU a 9 pin D DB9 connector and a 10 pin header 6 8 03 CAN BUS Two Individual Controller Area Network Buses are a 2 wire interface used mainly by the automotive industry The CAN specification defines the
36. LLOW 4 USER DEFINED GREEN 5 USER DEFINED GREEN 6 ATA ACTIVITY GREEN 3 4 BT1 Battery Use only a 3 Volt Lithium battery properly sized for the socket The battery is used for the Real Time Clock The Real Time Clock in conjunction with the CPLD releases the Power Rail Regulators See Section 6 2 1 for more information ADS512101 User Manual Page 19 of 56 September 4 2008 Rev 1 1 40 Schematic The schematic and basic assembly information a portable document format for the ADS512101 can be located on the CD in the STx Engineering Document Folder supplied with the board The ADS512101 design can be customized for optional flexibility and custom interfaces so the embedded systems engineer can obtain a lower overall parts cost using a variety of fixed and user selectable options These options inherently are contained in connectors jumpers and switches on the board The schematic provides guidelines for using the already installed as well as user modifiable options available on the present design ADS512101 Page 20 of 56 September 4 2008 User Manual Rev 1 1 5 0 CPLD Configuration The configuration CPLD controls the MPC5121e hard reset configuration word The hardware configuration is controlled by switches SW3 to SW5 see section 3 1 3 through 3 1 7 and documented in the following CPLD table If all switches are set to ON then the CPLD will drive the default configuration word Other functi
37. NC 11 PATA CON AD3 12 PATA CON AD12 P09 CAN 0 13 PATA CON AD2 Pin No Description 4 CON E 16 CON 14 END 17 PATA CON ADO 18 PATA CON AD15 4 014 SNB 5 SIG GND 6 TP012 20 NC 21 PATA CON DRQ 7 CANH 8 13 22 OND 5 23 CON IOWN 24 GND 25 PATA CON IORN P10 1 26 GND 10 pin Header 27 PATA CON IOCHRDY Pin No Description 28 GND 1 NC 29 PATA CON DACK 2 CANL 30 END 3 GND 31 PATA CON INTRQ 4 NC 32 PATA CON 10 516 5 SIG GND 33 6 NC 34 NC 7 35 DAO 8 NC 36 PATA CON DA2 9 NC 37 PATA CON CSON 10 NC 38 CON 51 39 PATA CON DASPN 40 GND ADS512101 Page 50 of 56 September 4 2008 User Manual Rev 1 1 P13 ATA Activity P14 PCI continued 2 pin Header Pin No Pin Name Pin No Pin Name SIGNAL IO PWR d 1 CON DASPN 218 5 GNO A21 3 3V 7 B22 GND19 P14 PCI A2 28 B23 AD27 Pin No Pin Name A23 AD26 B1 12V B24 AD25 A1 not TRST A24 GND10 B2 TCK B25 3 3V 1 A2 12V A25 AD24 B3 GNDO B26 C not BE3 A3 TMS A26 IDSEL B4 TDO B27 AD23 A4 TDI A27 3 3V
38. OM sub system erase erase FLASH memory exit exit script fdt flattened device tr utility commands flinfo print FLASH memory information go start application at address addr help print online help i2c I2C sub system icrc32 checksum calculation iloop infinite loop on address range imd i2c memory display iminfo print header information for application image imls list all images found in flash imm i2c memory modify auto incrementing imw memory write fill imxtract extract a part of a multi image inm memory modify constant address iprobe probe to discover valid I2C chip addresses itest return true false on integer compare loadb load binary file over serial line kermit mode loads load S Record file over serial line loady load binary file over serial line ymodem mode loop infinite loop on address range md memory display mii MII utility commands mm memory modify auto incrementing mtest simple RAM test mw memory write fill nfs boot image via network using NFS protocol nm memory modify constant address pci list and access PCI Configuration Space ping send ICMP ECHO REQUEST to network host printenv print environment variables protect enable or disable FLASH write protection rarpboot boot image via network using RARP TFTP protocol reginfo print register information reset Perform RESET of the CPU run run commands in an environment variable ADS512101 Page 37 of 56
39. Silicon Turnkey eXpress Original Design Manufacturer ADS512101 Advanced Development System User s Manual Silicon Turnkey Express 749 Miner Road Highland Heights Ohio 44143 Phone 440 461 4700 800 827 2650 Copyright 2006 Silicon Turnkey Express An Affiliate of RPC Electronics Inc All Rights Reserved ADS512101 Page 1 of 56 September 4 2008 User Manual Rev 1 1 Revision History Rev Date Comments 1 0 Mar 24 2008 Release of user manual for PCB Rev 3 1 1 Sep 4 2008 Update for PCB Rev 4 1 2 Sep 8 2008 Corrected minor errors and formatting WARNING This document is preliminary It may contain errors and incomplete data Check with your provider or Silicon Turnkey Express www silicontkx com or call 440 461 4700 for the latest information Support Your ADS512101 does include technical support from STx If you should encounter any start up problems or if the ADS512101 does NOT include all the material immediately email ADS512101 silicontkx com and provide your name contact information and problem STx commits to acknowledging all requests within 4 hours and usually can resolve most issues within 24 hours Additional support information may be found at www silicontkx com Warranty To assure all future engineering notifications are communicated the enclosed warranty information must be completed ADS512101 Page 2 of 56 September 4 2008
40. W1 to launch U Boot See Figure 7 for display text ADS512101 Page 40 of 56 September 4 2008 User Manual Rev 1 1 Re install U Boot display U Boot 1 3 4 Aug 27 2008 11 00 02 MPC512X CPU 5121 rev 2 0 Core e300c4 at 399 999 MHz CSB at 199 MHz Board ADS5121 rev 0x0400 CPLD rev 0x05 I2C ready DRAM 512 MB FLASH 64 MB PCI Bus Dev VenId Devld Class Int In serial Out serial Err serial Net FEC ETHERNET BOOTING FROM BACKUP FLASH RECOVERY MODE PROCESS STARTING AT AUTOBOOT Hit any key to stop autoboot 0 Copy u boot main flash image to dram CRC32 for ff800000 ff832f3f gt 3072 67 Switching to MAIN flash Un Protect Flash Bank 1 done Erased 2 sectors PROGRAMMING MAIN FLASH done Erased 1 sectors Copy to Flash done CRC32 for 00000 fff32f3f gt a3072f67 Copy to Flash done Protected 2 sectors SETTING UP NEW ENVIRONMENT in MAIN FLASH SETTING BOOT PARAMETERS SAVING ENVIRONMENT in MAIN FLASH Saving Environment to Flash Un Protected 1 sectors Un Protected 1 sectors Erasing Flash done Erased 1 sectors Writing to Flash done Protected 1 sectors Protected 1 sectors Saving Environment to Flash Un Protected 1 sectors Un Protected 1 sectors Erasing Flash done Erased 1 sectors Writing to Flash done Protected 1 sectors Protected 1 sectors SELECT MAIN FLASH BY REMOVING JUMPER at P4 CYCLE POWER NOW Rebooting in 10 Seconds Figure 7
41. aid eA Anes dann aidan dae 13 1 1 13 P02 JTAG CORDD6ScGtOr a eee et et 13 1 1 14 P03 Expansion BUS in toe ce tie e sce e d eee Te 13 1 1 15 P04 Back Up EEASH den eren me eee tazen 13 1 1 16 CRED hee ee oat em ess 13 1 1 18 O at ee 13 1 1 19 POSISRS232 e ENT es 13 1 1 20 P09 GAN sm toe ec ote Ae 13 1 1 21 CAN atta bein te 13 1 1 22 11 lt Drive Select a 13 1 1 23 12 PATA GOohnHeclor 5 13 1 1 24 P13 Front Panel ATA LED 2 13 1 1 25 P414 PGI GOnneclor eite 14 1 1 26 P153 J41850 Interface dette rte eerte 14 1 1 27 P16 SPDIF Interface eee 14 1 1 28 Mini USB a ette dad t ete 14 1 1 29 P19 nii enr etitm ni rien 14 1 1 30 P19 LCD Backlight Inverter 14 1 1 31 P20 LCD Connector secedere beides es 14 1 1 32 P21 LCD Gonneclor eet orte desees Mead she e ee ical er ebat qa 14 1 1 34 22 Touch Screen beide a ea 14 1 1 34 P23 Front Panel Hardware 2 20 0 nnne 14 1 1 35 P24 Front Panel Hibernation Switch 2 2 0
42. ations many of these memory map settings are user defined Function Bytes 32 Bit Address CS Size Reserved Start End IMMRBAR 8000 0000 803F FFFF 1M Default setting at Recommend reset FF40 0000 4M For future Move after boot revs DDR SDRAM 256MB 0x0000 0000 OxOFFF FFFF DDR_MCSN 256MB BOOT Space 64MB 0 00 0000 OxFFFF FFFF LPC CSON 64MB NOR FLASH Boot High NAND FLASH 1MB 0x4000 0000 0x400F FFFF 1MB Upto 2GB PCI Memory 256MB 0 000 0000 OxAFFF FFFF 1GB PCILAWBARO 2 256MB 0 000 0000 OxBFFF FFFF 256MB 0 000 0000 OxCFFF FFFF 256MB 0 0000 0000 OxDFFF FFFF SRAM 256KB 0x3000 0000 0x3001 FFFF 128KB CPLD 32B 0x8200 0000 0x820F FFFF LPC CS2N 32B MBX graphics 16MB 0x2000 0000 0 20 FFFF 16MB USB ULPI 4KB IMMR 0x3000 IMMR 4KB 2 0 Device PATA Drive IMMR 0 1 0200 IMMR 0 1 2 SATA Drive IMMR 0x20000 IMMR 0 2 Local Configuration 1KB IMMR 0x0 0000 IMMR OxF FFFF 64B Registers RS232A PSC3 IMMR 0x1 1300 IMMR 0 1 13FF RS232 B 5 4 IMMR 0x1 1400 IMMR 0 1 14FF Audio AC97 PSC5 IMMR 0x1 1500 IMMR 0 1 15FF CAN A IMMR 0x0 1300 IMMR 0x0 137F CAN B IMMR 0x0 1380 IMMR 0x0 13FF IMMR 0x0 1700 IMMR_Ox0 171F 32B 2 IMMR 0x0 1740 IMMR 0 0 17FF 32B Fast Ethernet IMMR 0x0 2800 IMMR 0x0 2FFF 256B Controller ADS512101 Page 45 of 56 September 4 2008 User Manual Rev 1 1 Appendix B
43. bit Ethernet elm Gigabit Media Independent Interface EM General Purpose Input Output GPT etim es General Purpose Timers EDD uiii ett eH ERE M dre esed Hard Disk Drive laesi s MEC rr Inter Integrated Circuit ims itte mettre ast t estre CAN Protocol Ford GM Chrysler lox Integrated Programmable Interrupt JTAG EE oz te Test Port per IEEE 1149 c Liquid Crystal Display tae E mete ete bieten ettet LocalPlus Bus hier ete dtc dde ROTE ved Low Voltage Differential Signaling MBX Power VR Lite IP Intergrated Graphics Engine by Imagination Technologies Management Data Input Output Mini DX nation tret Low Power Motherboard Standard 17cm x 17cm form factor dutem nitentes cte EE NAND Flash Controller D EPI On The Go USB BATA tema tede i Parallel AT Attachment HH IR Peripheral Component Interconnect PMO Tte igit Power Management Control EEE TOA E EE I utu indies tad Programmable Serial Channel PRAM Random Access Memory iin rte ads Tb nig Reduced Gigabit Media Independent Interface Reduced Media Independent Interface Dare Real Time Clock
44. board 0 Read Write 3 FEC PHY INTN 0 Read Write 2 TEMP MON INT 0 Read Write 1 PCI Interrupts 0 Read Write 0 0 Read Write ADS512101 Page 25 of 56 September 4 2008 User Manual Rev 1 1 5 14 CPLD Register 13 Interrupt Masking Base 0 00 Bit 1 interrupt is masked Value at reset Ability R W 7 SW1 HIBERNATE Z writing 0 clears INT in register 14 1 Read Write 6 Secure Digital Card SD 1 Read Write 5 TOUCH SCR BUSYN 1 Read Write 4 TOUCH SCR IRQN off board 1 Read Write 3 FEC PHY INTN 1 Read Write 2 TEMP MON INT 1 Read Write 1 ALL PCI INT MASKING to CPU 1 Read Write 0 1 Read Write 5 15 CPLD Register 14 Interrupt Status Base OxOE Bit Value at reset Ability R W 7 SW1_HIBERNATE 1 Read Write Must be cleared by writing value 0 to register 13 bit 0 6 Secure digital card SD CD 1 Read Write 5 Reserved 1 Read Write 4 TOUCH_SCR_IRQN off board 1 Read Write 3 FEC_PHY_INTN 1 Read Write 2 1 Read only 1 PCI INT read CPLD register 11 for which PCI interrupt is 1 Read Write asserted 0 1 Read Write ADS512101 Page 26 of 56 September 4 2008 User Manual Rev 1 1 5 16 CPLD Register 15 MISC Control 0 Base OxOF Bit
45. dress is set to 0x70 read 0x71 write 6 8 05 AUDIO and Touch Screen controller The MPC5121e use a PSC programmable serial controller set for the AC97 communication protocol The audio codec is controlled by the AC97 controller and provides LINE IN LINEOUT and MIC IN 6 8 06 VIDEO The MPC5121e has an integrated graphics engine the PowerVR MBX Lite IP core The MBX controller is directly connected to 24 bit LVDS transceiver A Triple 8 bit video DAC with whose output is high speed video buffered then connected to the DVI I connector A Digital transmitter that is connected to the DVI I connector 6 8 07 LCD Backlight The LCD backlight uses a digital potentiometer to control the LCD backlight and is controlled directly from the CPU s I2C interface and addressed at Ox5C 6 8 08 SATA Drive Interface The MPC5121e directly connects to the SATA drive connector J5 ADS512101 Page 35 of 56 September 4 2008 User Manual Rev 1 1 6 8 09 PATA Drive Interface The PATA drive circuitry uses the MPC5121e PATA bus interface The MPC5121 PATA interface connects to signal level translator ICs to convert from the CPU s 3 3v signal level to the 5 0 signal level The level translated signals are then connected to the PATA connector The drive signal level voltage is selected with jumper P11 See section 3 2 2 for additional information The PATA power is enabled by an regulator and is controlled by the CPU s I2CO bus The
46. e 31 of 56 September 4 2008 User Manual Rev 1 1 6 3 Resets Two reset switches provide the on board resets Reset signal SW1_TOGGLE is connected to the power sequence PS CPLD and is the main on off switch This signal is used within the PS CPLD to enable or disable the on board power supplies The PS CPLD will also enable all on board power supplies properly and driving the MASTER RESETN signal to the main power on reset and watchdog timer IC Reset signal SOFT RESETN is connected to The main CPLD for use by this device The CPU for the soft reset function The COP JTAG port the COP JTAG can also drive this signal The main reset and watchdog timer device IC is held in reset until the PS CPLD has released the MASTER RESETN signal It then releases the RESETN signal once an internal time delay about 210ms has been met The PWRON RESETN signal is used by the Configuration CPLD and clears its internal registers It also is used by the CPU for its power on reset 6 4 Clocks The main clock driver is a programmable clock synthesizer IC The SYS CLK is the main processor clock 33 0 Mhz The SYS CLK CPLD is used by the Configuration CPLD for synchronization to the CPU s input clock and internal functions The USB CLK 24 000 is used by the CPU s internal USB circuitry The FEC 25 000 is used by both the CPU s internal fast Ethernet circuitry and the Ethernet PHY The SATA CLK 25M000M is used by the CPU s in
47. ich will turn off the external power sources The external signals SET WU SRCT 0 5 are used as external wakeup signals See Chapter 32 Real Time Clock RTC of the mpc5121e user manual SW2 is used as an external hibernate See CPLD registers 12 13 and 14 After the CPU is in hibernation mode SW2 will generate an assertion of GPI31 signal which is a non maskable wake from hibernation mode signal Hardware test can be performed as follows using the U Boot command prompt DDR2 self refresh mode must be enabled Values can be written to DDR2 memory Location 0 0000 0000 Read and confirm the actual time counter is counting register offset 0x24 Read location 0x80000a24 Write to the RTC keep Alive register and enable the hibernation mode Write to location 0x80000a28 the value 0x00000005 To assert the CPU HIB Mode write to the RTC target time register This will turn off the power supplies except for DDR and standby power Write to location 0x80000a20 the value When SW2 button is pushed to power the board back up verify the CPU recognizes the GPI31 signal Read location 0x80000a28 bit 16 should be set to a 1 writing 1 clears this bit The contents of the RTC target timer register offset 20 should be cleared before clearing the set sticky bit otherwise the CPU will perform another hibernate The contents of DDR can be verified that it is the same as prior to going into hibernate mode ADS512101 Pag
48. licontkx com support index php 5 Volt Only Operation CAUTION Failure to follow this caution may result in possible damage to the board The ADS512101 can operate from either 5 VDC only power supplies such as the 15 watt wall mounted power supply included in this kit or an ATX standard power supply When the ADS512101 is operated with the 15W wall mounted power supply included with this kit normal operation will be LIMITED The 15 watt 5 volts operation will NOT provide 12 volts required for peripherals or PCI However all other ADS512101 function will be normal for worse case maximum power usage ATX power supplies supports all power for all peripherals and PCI Follow the instructions in this manual for either 5 volts or ATX operation see Section 3 2 6 Media Access Control Address Every ADS512101 has a unique MAC address saved in memory as part of the standard environment A label on the backside of the PCB under the STx logo provides the PCB revision number the serial number and the MAC address This same information will appear on a label on the CD container If the MAC address needs to be set in U Boot use these steps 1 Boot from main FLASH 2 Type setenv ethaddr MAC Address as 00 1E 59 nn nn nn 3 If an incorrect MAC address is entered U Boot must be re installed then a new MAC address can be entered ADS512101 Page 4 of 56 September 4 2008 User Manual Rev 1 1 Table of Contents 5 V
49. loop This program has been provided by Freescale to demonstrated the graphics capability of the MPC5121e ADS512101 Page 38 of 56 September 4 2008 User Manual Rev 1 1 7 2 3 Environment Variables set by U Boot bootdelay 5 baudrate 115200 loads echo 1 rootpath opt eldk pco hostname ads5121 bootfile ads5121 uImage loadaddr 400000 u boot addr r 200000 kernel addr r 300000 fdt addr r 400000 ramdisk addr r 500000 u boot addr FFF00000 fdt addr FC2C0000 ramdisk addr FC300000 ramdiskfile ads5121 uRamdisk fdtfile ads5121 ads5121 dtb netdev ethO0 consdev ttyPSCO nfsargs setenv bootargs root dev nfs rw nfsroot serverip rootpath ramargs setenv bootargs root dev ram rw addip setenv bootargs bootargs ip S ipaddr serverip gatewayip netmask S hostname netdev off panic 1 addtty setenv bootargs bootargs console consdev baudrate flash nfs run nfsargs addip addtty bootm kernel addr fdt_addr flash self run ramargs addip addtty bootm kernel addr ramdisk addr fdt_addr net nfs tftp 1 addr bootfile tftp 5 9 addr fdtfile run nfsargs addip addtty bootm kernel addr fdt addr net self tftp kernel addr bootfile tftp ramdisk_ ramdiskfile tftp fdt fdtfile run ramargs addip addtty bootm 1 addr ramdisk_addr_r 5 95 addr load tftp u boot_addr_r u boot update protect
50. mini ITX accessories ADS512101 Rev 4 0 SN AVCO8081083 MAC HEX O01E597BAEBB Figure 1 ADS512101 Silicon Turnkey Express will work with your embedded systems engineers to integrate a final product that will give your end users the best performing and most cost effective embedded solution ADS512101 Page 10 of 56 September 4 2008 User Manual Rev 1 1 1 1 This section provides a description of the connectors jumpers switches and main components of the ADS512101 Device Placement and Functions Additional descriptions of the functionality of switches and jumpers along with their recommended settings board Refer to Figures 2 and 3 for will be found in Section 3 of this manual location of the devices referenced below EEPROM Write Protect Disk Drive Power PWR 1 Power 8 0m m g m 8 2 0 mm DA We mgg ADSS121E 04 Silicon Express STX xix MPC5121e 1 un 1 749 Miner Road A Highland Hieghts Ohio 44143 1 PH 440 461 4700 Dre m wwwsilicontkx com ll 2 p E 5 8 81 _ ica x ea mo CPLD 9 uidi 5 Boot Backup Video Activity ss i P27 Power 1 17 P21 Power Switch sva Em
51. must be toggled POWER ONN lt Power Up Delayed by Power up Rate Signaled by POWER OKAY If Standby is used This comes from Supply Otherwise itis tied to VCC 5V POWER OKAY No Big Delay Required in CPLD Enable Will Go active 2 Clocks after Power Good ENA 3V3 _2 5 V9V No Big Delay Required in CPLD SS RAMP on these is 2X 1 4 1V2 See Analog Ramps Set By SS on Regs PWR GOOD ALL PWRON RESETN HARD RESETN RESET DISTRIBUTION SIGNALS FLASH FEC PATA ETC ADS512101 Page 30 of 56 September 4 2008 User Manual Rev 1 1 6 2 3 Hibernation Mode Hibernate Not Operational in Revision 1 or Revision 2 of ADS512101 The Hibernate Pin from the CPU will shut down all of the regulators and devices that allow the MPC5121E to go into deep low power mode Still TBD Hibernate can wake or sleep per MPC5121E spec For controlled entry into the hibernate mode the CPU must prepare the MPC5121e in anticipation of entering the hibernate mode that is having the power supply removed The CPU must first write a value to the time target register that will give the MPC5121e enough time to complete all bus transactions in progress and shut down any other processes that must be terminated in an orderly manner and cause the MPC5121e to enter the hibernation mode before the HIB MODE pin is asserted wh
52. olt Only Operation aad t pde ean 4 Media Access Control Address 04400000 4 Table of Contents e eR ed edo de ec dd e e dete ee De De PO 5 mi aietan T NE 8 List of Incl ded ioci ci cte to coe E beet ex 9 List of Optional ACCESSOMIES btt MEER QE eb ena hor tees 9 1 0 General 2 2 erect eter adi a D Ab n ERU 10 1 1 Device Placement and nnne ae 11 1 1 01 Battery itte iib LE HL E 12 1 1 02 JOT RJ45 10 100 Base e cec Eoo Eten ee eme tet 12 1 1 03 J02 Audio GOornrnectOors eerte ee once bee ette ber eoe 12 1 1 04 J03 MinEPGI GOnReclor iiti cotto tete 12 1 1 05 904 cote e 12 1 1 06 J05 SATA Irterfaee ett eot aee 12 1 1 07 MAPA Rc 13 1 1 08 5 T anc nee e A tette 13 1 1 09 55 eee Lee os 13 1 1 10 LED 6 ATA ACIMVIt 13 1 1 11 LED 7 USB ROWER sich cetacean Lom 13 1 1 12 P01 5V Only Operationaas s
53. ons of the CPLD are driven by or read by internal registers that are memory mapped at the base address 0x6000 0000 The CPLD uses the MPC5121e s chip select 2 on the local bus as its chip select and address decodes the lower 5 address bits See the following table of CPLD registers descriptions for additional information 5 01 Register 0 Board ID 1 used along with register 1 Base 0x00 Bit A distinct board ID is assign to the board Value at reset Ability R W 16bits 0x0001 ADS5121e rev 04 7 0 Upper byte of Board ID 0x00 Read only 5 02 CPLD Register 1 Board ID 0 used along with register 0 Base 0x01 Bit Bit description Value at reset Ability R W 7 0 Upper byte of Board ID 0x04 Read only 5 03 CPLD Register 2 CPLD Revision Base 0x02 Bit CPLD rev Value at reset Ability R W 7 0 CPLD rev info 0x01 Read only Writing a sequence of AA then 55 then 96 5 04 CPLD Register 3 Configuration word bits 33 32 Base 0x03 0x1010 1000 default CPLD drives Reset Configuration Word Bit This register is reserved Value at reset Ability R W 7 2 Reserved 101010 Read Write 1 RST CONF EMB AX2 CFG word 33 Read only 0 RST CONF EMB CFG word 32 Read only ADS512101 User Manual Page 21 of 56 September 4 2008 Rev 1 1 5 05 CPLD Register 4 Configuration word bits 31 24 Base 0x04 0 00
54. power enables for each of the regulators are used to sequence the power supplies These will not release if the CPLD is not powered properly and the RTC clock are not running These are open drain signals and work in tandem with the SS RC time constants of the regulators They are used to Power down the regulators in 0 time but allow the time constants of SS for Power up 6 2 2 Power Sequencing Power sequencing rules require that the IO voltage rail is powered before the Core Voltages This is controlled by the SS time constants of the Core regulators are longer than that of the IO regulators During sequenced power down the CPLD will disable the Core regulators first and then disable the IO Regulators The normal controlled power down sequence will be on SW1 Toggle 1 Assert RESET via MASTER RESETN 2 De assert core Power ENA 1V4 ENA1V2 3 Wait some time 4 De assert IO Power ENA 3V3 ENA2V5 etc 5 De assert ATX POWER The Normal Power UP sequence will be on SW1 Toggle 1 Assert ATX POWER ONN 2 Assert Power 3V3 ENA2V5 etc 3 Wait some time 4 Assert core Power 1V4 ENA1V2 5 Assert PON RESET via MASTER RESETN The CPLD and the 8bit I O expander control the power up and power down of the entire board Power On Sequencing If Power is used This is generated from PB Switch PS1 Toggle and Not Hibernate If Hibernating the power will shut down and this
55. r Manual Rev 1 1 5 07 CPLD Register 6 Configuration switch settings EMB AD 15 8 Base 0x06 0x0101 0000 default CPLD drives Reset Configuration Word Bit Ability to read Configuration switches through software Value at reset Ability R Switch definitions are from 5121 user manual HRW RST CONF PCIARB enable PCI arbiter CFG word 15 Read only 6 RST CONF PCIHOST PCI Host mode word 14 Read only RST CONF COREPLL Core PLL Multiply factor CFG word 13 Read only 857 No LPG Address Extension 08 Read only_ 5 08 CPLD Register 7 Configuration switch settings EMB AD T7 0 Base 0x07 0x0010 0000 default CPLD drives Reset Configuration Word Bit Ability to read Configuration switches by software Switch Value at reset Ability R W definitions from 5121 user manual HRW 7 RST CONF PCI66EN M66EN signal 1 66 CFG word 07 Read only 6 RST CONF TLE Little ENDIAN CFG word 06 Read only 5 RST CONF BMS boot high CFG word 05 Read only 4 RST CONF COREDIS Core Disable mode normal CFG word 04 Read only 3 RST CONF TPR factory test mode disabled CFG word 03 Read only 2 RST CONF SWEN watchdog timer disabled at reset CFG word 02 Read only 1 RST CONFIG ROM LOC LPC boot CFG word 01 Read only 0 RST CONFIG ROM LOC LPC boot CFG word 00 Read only ADS512101 Page 23 of 56 September 4 2008 User Manual Rev 1 1 5 09 CPLD Register
56. rnel command line console ttyPSC0 115200 root dev mtdblockl rw rootfstype jffs2 mem 256M 0 000000 IPIC 128 IRQ sources at 7 00 0 000000 PID hash table entries 1024 order 10 4096 bytes 0 000009 clocksource timebase mult 5000002 shift 22 registered 0 000147 Console colour dummy device 80x25 0 000247 console ttyPSCO enabled 0 107603 Dentry cache hash table entries 32768 order 5 131072 bytes 0 115855 Inode cache hash table entries 16384 order 4 65536 bytes 0 142459 emory 184064k 262144k available 3580k kernel code 77852k reserved 152k data 118k bss 188k init 0 152849 SLUB Genslabs 9 HWalign 32 Order 0 1 MinObjects 4 CPUs 1 Nodes 1 0 240499 ount cache hash table entries 512 0 247489 net namespace 64 bytes 0 252697 NET Registered protocol family 16 0 268360 Reserved irq 66 0x42 for MBX 0 274695 Could not initialize clk spdif txclk without a calc routine 0 281397 Could not initialize clk spdif rxclk without a calc routine 0 288236 mapped ioctl to d1002000 and gpioctl to d1004100 0 293894 PCI Probing PCI hardware 0 306787 SCSI subsystem initialized 0 311696 usbcore registered new interface driver usbfs 0 317689 usbcore registered new interface driver hub ADS512101 Page 42 of 56 September 4 2008 User Manual Rev 1 1 0 323294 usbcore registered new device driver usb 0 343144 NET Registered pro
57. rtc m41t80 0 0068 chip found driver version 0 05 1 038262 rtc m41t80 0 0068 rtc core registered m41t62 as rtcl 1 051887 Freescale R MPC5121 DMA Engine found 64 channels 1 159720 fsldma Self test copy successfully 1 164787 usbcore registered new interface driver usbhid 1 170343 drivers hid usbhid hid core c v2 6 USB HID core driver 176856 Advanced Linux Sound Architecture Driver Version 1 0 15 Tue Nov 2 19 16 42 2007 UTC 1 186717 ASoC version 0 13 1 ADS512101 Page 43 of 56 September 4 2008 User Manual Rev 1 1 1 190098 Freescale MPC5121 ADS ALSA SoC fabric driver 1 196339 AC97 SoC Audio Codec 0 6 1 201852 asoc AC97 HiFi lt gt psc5 mapping ok 1 224906 ALSA device list 1 228011 0 MPC5121 ADS 97 1 231907 TCP cubic registered 1 235555 NET Registered protocol family 1 1 239956 NET Registered protocol family 17 1 245379 RPC Registered udp transport module 1 250055 Registered tcp transport module 1 254919 mpc5121 rtc 80000a00 rtc setting system clock to 1970 01 02 05 12 26 UTC 105146 2 725740 VFS Mounted root jffs2 filesystem 2 730523 Freeing unused kernel memory 188k init Setting the hostname to freescal Mounting proc and sys Starting the hotplug events dispatcher udevd Synthesizing initial hotplug events Mounting filesystems Starting syslogd and klogd Running sysctl Setting up networking on loopback device Warning no IPADDR is set please se
58. s 1 User Control 0 Read Write register 17 0 3 LED 3 0 Read Write 2 LED 2 0 Read Write 1 LED 1 0 Read Write 0 LED 0 0 Read Write 5 19 CPLD Register 18 Configuration Switch Settings SW3 Base 0x012 SW3 Value at reset 7 o 00 200mhz DDR2 clock 5 6 7 amp 6 cfg sys pll 01 166 67mhz DDR2 clock Read only 10 133 33mhz DDR2 clock 0 2x cfg watchdog 0 disabled o o Read only 2 3 Gl Speed M66en signal also must be Read high for 66mhz cfg NOR boot 0 NOR boot 0 Read only 1 LOW bo0t 0 high boot 0 Read only ADS512101 User Manual Page 28 of 56 September 4 2008 Rev 1 1 6 0 Operation All information contain this section is from STx s Design Requirements revision 4 0 dated August 27 2008 For additional information or clarifications visit web site www silicontkx com support index php or email ADS512101 silicontkx com 6 1 Central Processing Unit The ADS512101 s 5121 is configured to run at a 33 Mhz system clock and asynchronous mode 66 Mhz 33 Mhz PCI clock frequency The initial configuration is driven from the main CPLD reading the configuration of switch SW3 The boot strap options will be selectable from a configuration dip switch read by the CPLD the actual boot strap pins will be driven by the CPLD during reset only The switch setting can also be read from the CPLD see CPLD register 18 The MPC51
59. signal PATA PWR ENABN enables the PATA 12V PWR supplying the necessary 12v power to the PATA power connector 6 8 10 PCI The PCI slot is compliant to PCI2 3 32 bit bus It can either 33 MHz or 66 MHz which is determined by selectable clock with the Mode Switch SW3 This is 3 3 volts only 6 8 11 Two slots are compliant to PCI2 3 32 bit bus It can either 33 MHz 66 MHz which is determined by selectable clock with the Mode Switch SW3 This is 3 3 volts only 6 8 12 Micro SD Micro SD slot is available and is directly connected to the 5121 ATA controller ADS512101 Page 36 of 56 September 4 2008 User Manual Rev 1 1 U Boot Standard Commands askenv alias for help get environment variables from stdin autoscr run script from memory base print or set address offset bdinfo print Board Info structure boot boot default i e run bootomd bootd boot default i e run bootomd bootm boot application image from memory bootp boot image via network using BootP TFTP protocol clocks print clock configuration cmp memory compare coninfo print console devices and information memory copy crc32 checksum calculation date get set reset date amp tim dhcp invoke DHCP client to obtain IP boot params diufb init addr Init or Display BMP file echo echo args to console eeprom EEPR
60. t this from the ltib config screen or directly in etc rc d rc conf IP address setup bypassed Starting inetd Starting the dropbear ssh server 9 417644 dbgdrv module license unspecified taints kernel 9 504371 CLCDC Init major device 251 9 513018 9 522993 MBX Driver ALT Software Inc 9 533059 Build 05 Multi plane support March 4 2008 9 543341 9 553430 Setting up driver for 9 559166 DIU Framebuffer start 0 4501000 9 565787 DIU Framebuffer virtual 0xc4501000 9 572305 DIU Framebuffer size 3145728 bytes 9 578871 9 596153 bits per pixel 32 9 601166 width 1024 9 606338 height 768 9 611439 red length 8 9 616610 green length 8 9 621525 blue length 8 9 626623 AllocContiguousMemory pLinAddr cf000000 000000 size 3145728 9 637000 AllocContiguousMemory pLinAddr cec00000 dma ec00000 size 3145728 9 720669 CAMERA Init major device 250 9 726717 AllocContiguousMemory pLinAddr ce900000 dma e900000 size 524288 9 737113 AllocContiguousMemory pLinAddr ce980000 dma e980000 size 524288 9 747278 AllocContiguousMemory pLinAddr cea00000 dma ea00000 size 524288 Loaded PowerVR consumer services sh 2 05b ADS512101 Page 44 of 56 September 4 2008 User Manual Rev 1 1 Appendix Memory Map The following memory map isonly an example refer to the 5121 user manual for specific memory map configur
61. ternal SATA drive circuitry The CPLD CLK BASIC is used by the Configuration CPLD for internal functions The AUD CLK 24M576M is used by the Audio Codec U26 6 5 CPU Configuration The CPU configuration is completely user selectable by the bank of configuration switches SW3 to SW6 All 32 configuration signals are driven by the CPLD during power on reset only and correspond to the 32 independent switch positions Default configuration see table 7 3 Reset Configuration Word with in the MPC5121e user manual Bit 0 31 0000 0111 00 2211 0710 110 2222 Bit 1 0 RST CONF ROMLOC 00 LPC boot 2 RST CONF SWEN 0 watchdog timer at reset disabled Bit 3 RST CONF TPR 0 Factory test mode normal operation Bit 4 CONF COREDIS 0 Core disable mode normal operation Bit5 RST CONF BMS 1 boot mode select set so ROM loc start address OxFF80 Bit 6 RST CONF 1 little endian mode Bit 7 CONF PCI66EN 1 PCI66Mhz operation ADS512101 Page 32 of 56 September 4 2008 User Manual Rev 1 1 CPU Configuration continued Bit 9 amp 8 CONF LPC 00 no LPC address extension Bit 13 to 10 RST CONF COREPLL TBD Bit 14 RST CONF PCIHOST 1 PCI host mode Bit 15 RST CONF PCIARB 1 PCI arbiter enabled Bit 16 RST CONF LPC MX 0 LPC non multiplex mode Bit 17 not describe in user manual This may be used for LPC_AX3 For the switch function
62. tocol family 2 0 347439 Time timebase clocksource has been installed 0 391733 IP route cache hash table entries 2048 order 1 8192 bytes 0 399723 TCP established hash table entries 8192 order 4 65536 bytes 0 407184 TCP bind hash table entries 8192 order 3 32768 bytes 0 413822 TCP Hash tables configured established 8192 bind 8192 0 420121 TCP reno registered 0 452551 JFFS2 version 2 2 NAND 2001 2006 Red Hat Inc 0 459839 io scheduler noop registered 0 463750 io scheduler anticipatory registered default 0 469183 io scheduler deadline registered 0 473514 io scheduler cfq registered 0 519624 Console switching to colour frame buffer device 128x48 0 561565 fb0 10 fb device registered successfully 0 567606 fb1 Panell AOIO fb device registered successfully 0 573935 fb2 Panell 1 fb device registered successfully 0 580282 fb3 Panel2 AOIO fb device registered successfully 0 586619 fb4 Panel2 1 fb device registered successfully 0 592667 FSL DIU FB registed FB device driver 0 826161 Serial MPC52xx PSC UART driver 0 830832 80011300 serial ttyPSCO at MMIO 0x80011300 irq 40 is a MPC52x PSC 0 839429 80011400 serial ttyPSC1 at 0x80011400 irq 40 is a MPC52x PSC 0 848873 RAMDISK driver initialized 4 RAM disks of 16384K size 1024 blocksize 0 858276 eth0 fs enet 00 1e 59 7b 4e c5 0 863289 FEC MII Bus probed 0 866454 Uniform Multi Platform E IDE driver Revision 7
63. used to enable the front panel LED ADS512101 User Manual Page 13 of 56 September 4 2008 Rev 1 1 1 1 25 P14 PCI Connector P14 is the standard PCI connector that uses ID SEL AD21 1 1 26 15 91850 Interface P15 is a serial connection for 1850 1 1 27 P16 SPDIF Interface P16 is a connection header for the SPDIF to the MPC5121e 1 1 28 P17 Mini USB P17 is a USB mini AB connector that is compatible with the USB 2 0 format 1 1 29 P18 EEPROM WP See Jumper Seciton 3 2 2 1 1 30 P19 LCD Backlight Inverter Power This provides power and control signals to an LCD Inverter 1 1 31 P20 LCD Connector This is a 20 pin LVD connector 1 1 32 P21 LCD Connector This connector is for a TFT 18bit LCD to accommodate Media5200 monitors 1 1 34 P22 Touch Screen Interface This is an enhancement that may is not available on the standards ADS512101 1 1 34 P23 Front Panel Hardware Switch P23 is a header to provide a connection for the Front Panel Hardware Reset switch SW 1 Push once momentary causes a Power on Reset Push and hold for 5 seconds causes a power down 1 1 35 P24 Front Panel Hibernation Switch P24 is a header to provide a connection for the Front Panel Hibernation mode switch SW2 1 1 36 P25 Power Switch By Pass This jumper is used to by pass the power switch to allow for remote access by applying power to the ADS512101 1 1 37 27 RS232 U

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