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Freescale Semiconductor MPC852TVR50A datasheet: pdf

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1. MPC852T Hardware Specifications Rev 3 1 16 Freescale Semiconductor Table 9 Bus Operation Timings continued Bus Signal Timing Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Min Max Min Max Min Max Min Max Unit B29b CS negated to D 0 31 DP 0 3 High 7 GPCM write access ACS 00 TRLX 0 1 amp CSNT 0 MIN 0 25 x B1 2 00 5 60 4 30 3 00 1 80 ns B29c CS negated to D 0 31 DP 0 3 High Z GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 0 MIN 0 50 x B1 2 00 13 20 10 50 8 00 5 60 ns B29d WE 0 3 BS_B 0 3 negated to D 0 31 DP 0 3 High Z GPCM write access TRLX 1 CSNT 1 EBDF 0 MIN 1 50 x B1 2 00 43 50 35 50 28 00 20 70 ns B29e CS negated to D 0 31 DP 0 3 High Z GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 0 MIN 1 50 x B1 2 00 43 50 35 50 28 00 20 70 ns B29f WE 0 3 BS B 0 3 negated to D 0 31 DP 0 3 High Z GPCM write access TRLX 0 CSNT 1 EBDF 1 MIN 0 375 x B1 6 30 5 00 0 00 ns B29g CS negated to D 0 31 DP 0 3 High Z GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 1 MIN 0 375 x B1 6 30 5 00 0 00 ns B29h WE 0 3 BS_B 0 3 negated to D 0 31 DP 0 3 High Z GPCM write access TRLX
2. All Frequencies Num Characteristic Unit Min Max 134 TENA inactive delay from TCLK3 rising edge 10 50 ns 135 RSTRT active delay from TCLK3 falling edge 10 50 ns 136 RSTRT inactive delay from TCLK3 falling edge 10 50 ns 137 REJECT width low 1 CLK 138 CLKO1 low to SDACK asserted 2 20 ns 139 CLKO 1 low to SDACK negated 20 ns 1 The ratios SyncCLK RCLK3 and SyncCLK TCLK3 must be greater or equal to 2 1 SDACK is asserted whenever the SDMA writes the incoming frame DA into memory CLSN CTS1 Input CN e Figure 49 Ethernet Collision Timing Diagram RCLK3 RxD3 Input RENA CD3 Input Figure 50 Ethernet Receive Timing Diagram MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 51 CPM Electrical Characteristics TCLK3 TxD3 Output TENA RTS3 Input RENA CD3 Input N NOTE 2 NOTES 1 Transmit clock invert TCI bit in GSMR is set 2 If RENA is deasserted before TENA or RENA is not asserted at all during transmit the CSL bit is set in the buffer descriptor at the end of the frame transmission Figure 51 Ethernet Transmit Timing Diagram RxD3 Start Frame De 36 lt gt RSTRT Output Figure 52 CAM Interface Receive Start Timing Diagram REJECT 437 37 Figure 53 CAM Interface REJECT Timing
3. 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max CLKOUT to OPx Valid MAX 0 00 x B1 19 00 19 00 19 00 19 00 ns J95 19 00 HRESET negated to OPx drive MIN 0 75x 25 70 21 70 18 00 14 40 ns J96 B1 3 00 IP_Xx valid to CLKOUT rising edge MIN 0 00 5 00 5 00 5 00 5 00 ns J97 x B1 5 00 J98 CLKOUT rising edge to IP_Xx invalid MIN 1 00 1 00 1 00 1 00 ns 0 00 x B1 1 00 OP2 and OP3 only Figure 28 provides the PCMCIA output port timing for the MPC852T CLKOUT Output Signals HRESET OP2 OP3 Figure 28 PCMCIA Output Port Timing Figure 29 provides the PCMCIA output port timing for the MPC852T CLKOUT Input Signals Figure 29 PCMCIA Input Port Timing MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 37 Bus Signal Timing Table 13 shows the debug port timing for the MPC852T Table 13 Debug Port Timing All Frequencies Num Characteristic Unit Min Max J82 DSCK cycle time 3XTCLOCKOUT J83 DSCK clock pulse width 1 25XToiockoUT J84 DSCK rise and fall times 0 00 3 00 ns J85 0501 input data setup time 8 00 ns J86 DSDI data hold time 5 00 ns J87 DSCK low to DSDO data valid 0 00 15 00 ns J88 DSCK low to DSDO invali
4. CLKOUT Di UPWAIT saa X o o o Xo o o GPL B 0 5 Figure 18 Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing Figure 19 provides the timing for the asynchronous negated UPWAIT signal that the UPM controls CLKOUT UPWAIT 638 GOES U O Gb GPL 0 5 GPL B 0 5 X _ mE Figure 19 Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 31 Bus Signal Timing Figure 20 provides the timing for the synchronous external master access that the GPCM controls CLKOUT 0 31 _TSIZ 0 1 3 W BURST CSx Figure 20 Synchronous External Master Access Timing GPCM Handled ACS 00 Figure 21 provides the timing for the asynchronous external master memory access that the GPCM controls CLKOUT _ E NEM NM PME AS 0 31 z TSIZ 0 1 R W CSx Figure 21 Asynchronous External Master Memory Access Timing GPCM Controlled ACS 00 Figure 22 provides the timing for the asynchronous external master control signals negation AS 643 28x WE 0 3 V OE GPLx BS 0 3 Figure 22 Asynchronous External Master Control Signals Negation Timing MPC852T Hardware Specifications Rev 3 1 32 Freescale Semiconductor Bus Signal Timing Table 10 provides interrupt timing for the MPC852T Table 10 Interrupt Timing
5. All Frequencies Num Characteristic Unit Min Max 139 IRQx valid to CLKOUT rising edge set 6 00 ns up time 140 IRQx hold time after CLKOUT 2 00 ns 141 IRQx pulse width low 3 00 ns 142 IRQx pulse width high 3 00 ns 143 IRQx edge to edge time 4XTcLockoUT 1 The timings 139 and 140 describe the testing conditions under which the IRQ lines are tested when being defined as level sensitive The IRQ lines are synchronized internally and need not be asserted or negated with reference to the CLKOUT The timings 141 142 and 143 are specified to allow the correct function of the IRQ lines detection circuitry and have no direct relation with the total system interrupt latency that the MPC852T is able to support Figure 23 provides the interrupt detection timing for the external level sensitive lines CLKOUT Figure 23 Interrupt Detection Timing for External Level Sensitive Lines Figure 24 provides the interrupt detection timing for the external edge sensitive lines CLKOUT MEE EE MEM ESSE P ANM E 3 Figure 24 Interrupt Detection Timing for External Edge Sensitive Lines MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 33 Bus Signal Timing Table 11 shows the PCMCIA timing for the MPC852T Table 11 PCMCIA Timing 33 MHz 40 MHz 50 MHz 66 MHz Num Ch
6. Name Pin Number Type RSTCONF L5 Input 3 3 V only HRESET K5 Open drain SRESET N4 Open drain XTAL P2 Analog Output EXTAL N2 Analog Input 3 3 V only CLKOUT P7 Output EXTCLK P3 Input 3 3 V only ALE_A J2 Output CE1 A F6 Output CE2 A C4 Output WAIT A P4 Input 3 3 V only IP AO U3 Input 3 3 V only IP A1 N7 Input 3 3 V only IP A2 4 Input 3 3 V only 101516 A IP A3 N6 Input 3 3 V only IP A4 U4 Input 3 3 V only IP_A5 P6 Input 3 3 V only IP_A6 N8 Input 3 3 V only IP_A7 T3 Input 3 3 V only DSCK J3 Bidirectional Three state 3 3 V only IWP 0 1 J4 H2 Bidirectional 3 3 V only VFLS 0 1 OPO L2 Bidirectional 3 3 V only OP1 L3 Output OP2 L4 Bidirectional 3 3 V only MODCK1 STS OP3 M2 Bidirectional 3 3 V only MODCK2 DSDO BADDR 28 29 M4 M3 Output BADDR30 K4 Output REG MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 71 Mechanical Data and Ordering Information Table 31 Pin Assignments non JEDEC continued Name Pin Number Type AS K3 Input 3 3 V only PA11 F17 Bidirectional RXD3 Optional Open drain 5 V tolerant PA10 J16 Bidirectional TXD3 Optional Open drain 5 V tolerant PA9 K17 Bidirectional RXD4 Optional Open drain 5 V tolerant PA8 K16 Bidirectional TXD4 Optional Open drain 5 V tolerant PA3 L17 Bidirectional CLK5 5 V tolerant BRGOS3 2 115
7. Bus Signal Timing Figure 9 provides the timing for the input data controlled by the UPM for data beats where DLT3 1 in the UPM RAM words This is only the case where data is latched on the falling edge of CLKOUT CLKOUT NEP HE F amp F D 0 31 DP 0 3 Figure 9 Input Data Timing When Controlled by UPM in the Memory Controller and DLT3 1 Figure 10 through Figure 13 provide the timing for the external bus read that various GPCM factors control CLKOUT 7 N d N 0 31 D CSx WE 0 3 D 0 31 DP 0 3 Figure 10 External Bus Read Timing GPCM Controlled ACS 00 MPC852T Hardware Specifications Rev 3 1 24 Freescale Semiconductor Bus Signal Timing T gt 0 31 5 D 0 31 DP 0 3 Figure 11 External Bus Read Timing GPCM Controlled TRLX 0 ACS 10 T S 5 69 ate D 0 31 DP 0 3 Figure 12 External Bus Read Timing GPCM Controlled TRLX 0 ACS 11 MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 25 Bus Signal Timing CLKOUT 0 31 5 D 0 31 DP 0 3 Figure 13 External Bus Read Timing GPCM Controlled TRLX 0 or 1 ACS 10 ACS 11 MPC852T Hardware Specifications Rev 3 1 26 Freescale Semiconductor Bus Signal Timing Figure 14 through Figure 16 provid
8. TCK TCK TMS TDI TDO Figure 36 JTAG Test Access Port Timing Diagram TCK 2 TRST Figure 37 JTAG TRST Timing Diagram MPC852T Hardware Specifications Rev 3 1 42 Freescale Semiconductor CPM Electrical Characteristics TCK Signals Output Signals Output Signals Figure 38 Boundary Scan JTAG Timing Diagram 14 CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module CPM of the MPC852T 14 1 Port C Interrupt AC Electrical Specifications Table 16 provides the timings for port C interrupts Table 16 Port C Interrupt Timing 33 34 MHz Num Characteristic Unit Min Max 35 Port C interrupt pulse width low edge triggered mode 55 ns 36 Port C interrupt minimum time between active edges 55 ns Figure 39 shows the port C interrupt detection timing amp Port C Input Figure 39 Port C Interrupt Detection Timing MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 43 CPM Electrical Characteristics 14 2 IDMA Controller AC Electrical Specifications Table 17 provides the IDMA controller timings as shown in Figure 40 through Figure 43 Table 17 IDMA Controller Timing All Frequencies Num Characteristic Unit Min Max 40 DREQ setup time to clock high 7 ns
9. TX EN MII TX ER valid 25 M7 MII TX CLK pulse width high 35 65 MII TX CLK period M8 pulse width low 3596 65 MII TX CLK period Figure 59 shows the MII transmit signal timing diagram MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 57 FEC Electrical Characteristics M7 TX CLK input M5 MII TXD 3 0 outputs MII TX EN MII TX ER M M8 Lx 6 Figure 59 MII Transmit Signal Timing Diagram 15 3 MII Async Inputs Signal Timing CRS MII COL Table 27 provides information about the MII async inputs signal timing Table 27 MII Async Inputs Signal Timing Num Characteristic Min Max Unit M9 MII CRS COL minimum pulse width 1 5 MII TX CLK period Figure 60 shows the MII asynchronous inputs signal timing diagram CRS MII COL M9 Figure 60 MII Async Inputs Timing Diagram 15 4 MII Serial Management Channel Timing MII MDIO MII MDC Table 28 provides information on the MII serial management channel signal timing The FEC functions correctly with a maximum MDC frequency in excess of 2 5 MHz The exact upper bound is under investigation Table 28 MII Serial Management Channel Timing Num Characteristic Min Max Unit M10 MDC falling edge to MDIO output invalid minimum 0 ns propagation delay M11 MII MDC falling edge to MDIO output val
10. 0 00 x B1 2 50 15 00 2 50 15 00 2 50 15 00 2 50 15 00 ns 2 50 B16 TA valid to CLKOUT setup time 600 6 00 600 600 ns 0 00 x B1 6 00 B16a TEA KR RETRY CR valid to CLKOUT setup 4 50 4 50 4 50 4 50 ns time MIN 0 00 x B1 4 5 B16b BB BG BR valid to CLKOUT setup time 400 4 00 400 400 ns 4MIN 0 00 x B1 4 000 B17 CLKOUT to TA TEA BI BB BG BR valid 1 00 1 00 1 00 mE 2 00 ns hold time MIN 0 00 x B1 1 00 B17a CLKOUT to KR RETRY CR valid hold time 2 00 2 00 200 200 ns MIN 0 00 x B1 2 00 B18 D 0 31 DP 0 3 valid to CLKOUT rising edge 6 00 6 00 6 00 6 00 ns setup time MIN 0 00 x B1 6 00 B19 CLKOUT rising edge to D 0 31 DP 0 3 valid 1 00 1 00 100 200 ns hold time 5 MIN 0 00 x B1 1 009 B20 D 0 31 DP 0 3 valid to CLKOUT falling edge 4 00 400 4 00 400 ns setup time MIN 0 00 x B1 4 00 B21 CLKOUT falling edge to D 0 31 DP 0 3 valid 2 00 200 2 00 200 ns hold Time MIN 0 00 x B1 2 00 B22 CLKOUT rising edge to CS asserted GPCM 7 60 13 80 6 30 12 50 5 00 11 30 3 80 10 00 ns ACS 00 MAX 0 25 x 6 3 B22a CLKOUT falling edge to CS asserted GPCM 8 00 8 00 8 00
11. 1 CSNT 1 EBDF 1 MIN 0 375 x B1 3 30 38 40 31 10 24 20 17 50 ns B29i CS negated to D 0 31 DP 0 3 High Z GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 1 MIN 0 375 x 3 30 38 40 31 10 24 20 17 50 ns B30 CS WE 0 3 BS_B 0 3 negated to A 0 31 BADDR 28 30 Invalid GPCM write access 8 MIN 0 25 x B1 2 00 5 60 3 00 1 80 ns B30a WE 0 3 BS_B 0 3 negated to A 0 31 BADDR 28 30 Invalid GPCM write access TRLX 0 CSNT 1 CS negated to A 0 31 invalid GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 0 MIN 0 50 x B1 2 00 13 20 10 50 5 60 ns B30b WE 0 3 BS_B 0 3 negated to A 0 31 Invalid GPCM BADDR 28 30 invalid GPCM write access TRLX 1 CSNT 1 CS negated to A 0 31 Invalid GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 0 MIN 1 50 x B1 2 00 43 50 35 50 28 00 20 70 ns MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 17 Bus Signal Timing Table 9 Bus Operation Timings continued 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B30c WE 0 3 BS B 0 3 negated to A 0 31 8 40 6 40 4 50 2 70 ns BADDR 28 30 invalid GPCM write access TRLX 0 CSNT 1 CS negated to A 0 31 inval
12. 6 00 1 50 6 00 ns by control bit BST4 in the corresponding word in the UPM MAX 0 00 x B1 6 00 B32a CLKOUT falling edge to BS valid as 7 60 14 30 6 30 18 00 5 00 11 80 3 80 10 50 ns requested by control bit BST1 in the corresponding word in the UPM EBDF 0 MAX 0 25 x B1 6 80 B32b CLKOUT rising edge to BS valid as requested 1 50 8 00 1 50 8 00 1 50 8 00 1 50 8 00 ns by control bit BST2 in the corresponding word in the UPM MAX 0 00 x B1 8 00 B32c CLKOUT rising edge to BS valid as requested 7 60 14 30 6 30 13 00 5 00 11 80 3 80 10 50 ns by control bit BST3 in the corresponding word in the UPM MAX 0 25 x B1 6 80 MPC852T Hardware Specifications Rev 3 1 18 Freescale Semiconductor Table 9 Bus Operation Timings continued Bus Signal Timing 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B32d CLKOUT falling edge to BS valid as requested 13 30 18 00 11 30 16 00 9 40 14 10 7 60 12 30 ns by control bit BST1 in the corresponding word in the UPM EBDF 1 MAX 0 375 x B1 6 60 B33 CLKOUT falling edge to GPL valid as 1 50 6 00 1 50 6 00 1 50 6 00 1 50 6 00 ns requested by control bit GxT4 in the corresponding word in the UPM MAX 0 00 x
13. 8 00 ns ACS 10 TRLX 0 MAX 0 00 x B1 8 00 B22b CLKOUT falling edge to CS asserted GPCM 7 60 13 80 6 30 12 50 5 00 11 30 3 80 10 00 ns ACS 11 TRLX 0 EBDF 0 MAX 0 25 x B1 6 3 B22c CLKOUT falling edge to CS asserted GPCM 10 90 18 00 10 90 16 00 7 00 14 10 5 20 12 30 ns ACS 11 TRLX 0 EBDF 1 MAX 0 375 x B1 6 6 B23 CLKOUT rising edge to CS negated GPCM 2 00 8 00 2 00 8 00 2 00 8 00 2 00 8 00 ns read access GPCM write access ACS 00 TRLX 0 amp CSNT 0 MAX 0 00 x B1 8 00 MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 15 Bus Signal Timing Table 9 Bus Operation Timings continued 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B24 A 0 31 and BADDR 28 30 to CS asserted 5 60 4 30 3 00 1 80 ns GPCM ACS 10 TRLX 0 MIN 0 25 x B1 2 00 B24a A 0 31 and BADDR 28 30 to CS asserted 13 20 10 50 8 00 5 60 ns ACS 11 TRLX 0 MIN 0 50 x B1 2 00 B25 CLKOUT rising edge to OE 9 00 9 00 9 00 9 00 ns WE 0 3 BS B 0 3 asserted MAX 0 00 x B1 9 00 B26 CLKOUT rising edge to OE negated MAX 2 00 9 00 2 00 9 00 2 00 9 00 2 00 9 00 ns 0 00 x B1 9 00 B27 A 0 31 and BADDR 28 30 to CS asserted 35 90 29 30 23 00 16 90 ns GPCM ACS 10 TRLX 1 MIN 1 25 x B1 2
14. BSS g m o g 3 2 Jg m g w PD5 PD10 Q To m 9 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Figure 63 Pinout of the PBGA Package non JEDEC XO 8 SO O 5 0 RO O MPC852T Hardware Specifications Rev 3 1 68 Freescale Semiconductor Mechanical Data and Ordering Information Table 31 contains a list of the MPC852T input and output signals and shows multiplexing and pin assignments Table 31 Pin Assignments non JEDEC Name Pin Number Type 0 31 C16 B16 B15 D15 E14 F12 C15 B14 D14 C14 E13 F11 D13 Bidirectional C13 B13 E12 F10 D12 B10 B12 E11 D11 C9 B11 E10 D10 Three state 3 3 V only D9 C12 B9 C11 C10 E9 TSIZO F9 Bidirectional REG Three state 3 3 V only TSIZ1 F8 Bidirectional Three state 3 3 V only RD WR C2 Bidirectional Three state 3 3 V only BURST H4 Bidirectional Three state 3 3 V only BDIP E2 Output GPL B5 TS F3 Bidirectional Active Pull up 3 3 V only TA G5 Bidirectional Active Pull up 3 3 V only TEA F4 Open drain BI E3 Bidirectional Active Pull up 3 3 V only IRQ2 H3 Bidirectional RSV Three state 3 3 V only IRQ4 K2 Bidirectional KR Three state 3 3 V only RETRY SPKROUT CR G2 Input 3 3 V only IRQ3 D 0 31 T14 U12 T11 U11 U13 T10 T8 U7 U14 N11 P11 R11 R13 Bidirectional T13 N10 P10 R10 P12 U10 T9 R9 P9 U8 R12 R8
15. CD3 Input CD3 SYNC Input Figure 46 SCC NMSI Receive Timing Diagram TCLK3 TxD3 Output RTS3 Output CTS3 Input CTS3 SYNC Input Figure 47 SCC NMSI Transmit Timing Diagram MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 49 CPM Electrical Characteristics TCLK3 TxD3 Output RTS3 Output CTS3 Echo Input Figure 48 HDLC Bus Timing Diagram 14 6 Ethernet Electrical Specifications Table 22 provides the Ethernet timings as shown in Figure 49 through Figure 53 Table 22 Ethernet Timing All Frequencies Num Characteristic Unit Min Max 120 CLSN width high 40 ns 121 RCLKGS rise fall time 15 ns 122 RCLKS width low 40 ns 123 RCLK3 clock period 80 120 ns 124 RXD3 setup time 20 ns 125 RXD3 hold time 5 ns 126 RENA active delay from RCLK3 rising edge of the last data bit 10 ns 127 RENA width low 100 ns 128 TCLKGS rise fall time 15 ns 129 TCLK3 width low 40 ns 130 TCLK3 clock period 99 101 ns 131 TXD3 active delay from TCLK3 rising edge 50 ns 132 TXD3 inactive delay from TCLKS3 rising edge 6 5 50 ns 133 TENA active delay from rising edge 10 50 ns MPC852T Hardware Specifications Rev 3 1 50 Freescale Semiconductor CPM Electrical Characteristics Table 22 Ethernet Timing continued
16. E 242 C B 2945678 9101112 14 16 256 ene SIDE VIEW 0 3 lalBlc BOTTOM VIEW 0150A NOTES 1 All dimensions are in millimeters 2 Interpret dimensions and tolerances per ASME Y14 5M 1994 3 Maximum solder ball diameter measured parallel to datum A 4 Datum A the seating plane is defined by the spherical crowns of the solder balls Note Solder sphere composition is 95 5 Sn 45 Ag 0 5 Cu for MPC852TVRXXX Solder sphere composition is 62 Sn 36 Pb 2 Ag for MPC852TZTXXX Figure 64 Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 77 Document Revision History 17 Document Revision History Table 32 lists significant changes between revisions of this document Table 32 Document Revision History Revision Date Changes 3 1 1 18 2005 Document template update 3 0 11 2004 Added sentence to Spec B1A about EXTCLK and CLKOUT being in Alignment for Integer Values Added a footnote to Spec 41 specifying that EDM 1 Broke the Section 16 1 Pin Assignments into 2 smaller sections for the JEDEC and non JEDEC pinouts 2 0 12 2003 Put 852T on the 1st page in place of 8245 Figure 62 on page 59 had overbars added on signals CR pin G2 and WAIT pin P4 1 8 7 2003 Changed the pinout to be JEDEC Compliant changed timing parameters B28a through B28d and B29d to
17. use 9 80ns for B11a The timing required for BR input is relevant when the MPC852T is selected to work with internal bus arbiter The timing for BG input is relevant when the MPC852T is selected to work with external bus arbiter For part speeds above 50MHz use 2ns for B17 5 The D 0 31 and DP 0 3 input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is asserted For part speeds above 50MHz use 2ns for B19 7 The D 0 31 and DP 0 3 input timings B20 and B21 refer to the falling edge of the CLKOUT This timing is valid only for read accesses controlled by chip selects under control of the UPM in the memory controller for data beats where DLT3 1 in the UPM RAM words This is only the case where data is latched on the falling edge of CLKOUT The timing B30 refers to CS when ACS 00 and to WE 0 3 when CSNT 0 The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally The timings specified in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 18 10 The AS signal is considered asynchronous to the CLKOUT The timing B39 is specified in order to allow the behavior specified in Figure 21 MPC852T Hardware Specifications Rev 3 1 20 Freescale Semiconductor Bus Signal Timing Figure 3 is the control timing diagram CLKOUT Outputs Outputs Inputs Inputs A Maximum output delay specif
18. 0 00 0 00 ns J90 HRESET and RSTCONF asserted to data out drive MAX 0 00 x B1 25 00 25 00 25 00 125 00 125 00 ns RSTCONF negated to data out high impedance MAX 0 00 x B1 25 00 25 00 25 00 125 00 125 00 ns CLKOUT of last rising edge before chip three states HRESET to data out high impedance MAX 0 00 x B1 25 00 25 00 25 00 125 00 125 00 ns J93 DSDI DSCK set up MIN 3 00 x B1 90 90 75 00 60 00 45 50 ns J94 DSDI DSCK hold time MIN 0 00 x B1 0 00 0 00 0 00 0 00 0 00 ns J95 SRESET negated to CLKOUT rising edge for DSDI and DSCK sample MIN 8 00 x B1 242 40 200 00 160 00 121 20 ns MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 39 Bus Signal Timing Figure 32 shows the reset timing for the data bus configuration HRESET fe RSTCONF E r r R3 gt na Re Figure 32 Reset Timing Configuration from Data Bus Figure 33 provides the reset timing for the data bus weak drive during configuration CLKOUT D _ Sf HRESET RSTCONF D 0 31 OUT Weak 7 Figure 33 Reset Timing Data B
19. 00 B27a A 0 31 and BADDR 28 30 to CS asserted 43 50 35 50 28 00 20 701 ns GPCM ACS 11 TRLX 1 MIN 1 50 x B1 2 00 B28 CLKOUT rising edge to WE 0 3 BS B 0 3 9 00 9 00 9 00 EE 9 00 ns negated GPCM write access CSNT 0 MAX 0 00 x B1 9 00 B28a CLKOUT falling edge to WE 0 3 BS_B 0 3 7 60 14 30 6 30 13 00 5 00 11 80 3 80 10 50 ns negated GPCM write access TRLX 0 1 CSNT 1 EBDF 0 MAX 0 25 x B1 6 80 B28b CLKOUT falling edge to CS negated GPCM 14 30 13 00 11 80 10 50 ns write access TRLX 0 1 CSNT 1 ACS 10 or ACS 11 EBDF 0 MAX 0 25 x B1 6 80 28 CLKOUT falling edge to WE 0 3 BS_B 0 3 10 90 18 00 10 90 18 00 7 00 14 30 5 20 12 30 ns negated GPCM write access TRLX 0 1 CSNT 1 write access TRLX 0 1 CSNT 1 EBDF 1 MAX 0 375 x B1 6 6 B28d CLKOUT falling edge to CS negated GPCM 18 00 18 00 14 30 12 30 ns write access TRLX 0 1 CSNT 1 ACS 10 or ACS 11 EBDF 1 MAX 0 375 x B1 6 6 B29 WE 0 3 BS_B 0 3 negated to D 0 31 5 60 4 30 3 00 1 80 ns DP 0 3 High Z GPCM write access CSNT 0 EBDF 0 MIN 0 25 x B1 2 00 B29a WE 0 3 BS_B 0 3 negated D 0 31 13 20 10 50 8 00 5 60 ns DP 0 3 High Z GPCM write access TRLX 0 CSNT 1 EBDF 0 MIN 0 50 x B1 2 00
20. 3V only RD WR B1 Bidirectional Three state 3 3V only BURST G3 Bidirectional Three state 3 3V only BDIP D1 Output GPL B5 TS E2 Bidirectional Active Pull up 3 3V only TA F4 Bidirectional Active Pull up 3 3V only TEA E3 Open drain BI D2 Bidirectional Active Pull up 3 3V only IRQ2 G2 Bidirectional RSV Three state 3 3V only IRQ4 J1 Bidirectional KR Three state 3 3V only RETRY SPKROUT CR F1 Input 3 3V only IRQ3 D 0 31 R13 T11 R10 T10 T12 R9 R7 T6 T13 M10 N10 P10 P12 Bidirectional R12 9 N9 P9 N11 T9 R8 P8 N8 T7 P11 P7 7 M8 R11 R6 Three state 3 3V only P6 T5 R5 DPO P4 Bidirectional IRQ3 Three state 3 3V only DP1 P5 Bidirectional IRQ4 Three state 3 3V only DP2 T4 Bidirectional IRQ5 Three state 3 3V only DP3 R4 Bidirectional IRQ6 Three state 3 3V only BR 1 Bidirectional 3 3V only MPC852T Hardware Specifications Rev 3 1 62 Freescale Semiconductor Mechanical Data and Ordering Information Table 30 Pin Assignments JEDEC Standard continued Name Pin Number Type BG G4 Bidirectional 3 3V only BB F3 Bidirectional Active Pull up 3 3V only FRZ H4 Bidirectional 3 3V only IRQ6 IRQO P13 Input 3 3V only IRQ1 M11 Input 3 3V only M TX CLK N12 Input 3 3V only IRQ7 CS 0 5 B2 A2 D3 C3 E6 C4 Output CS6 D4 Output CS7 A3 Output WEO D6 Output BS_BO IORD WE1 C6 Outp
21. 41 DREQ hold time from clock high 3 ns 42 SDACK assertion delay from clock high 12 ns 43 SDACK negation delay from clock low 12 ns 44 SDACK negation delay from TA low 20 ns 45 SDACK negation delay from clock high 15 ns 46 TAassertion to falling edge of the clock setup time applies to external TA 7 ns Applies to high to low mode EDM 1 CLKO Output 1 DREQ Input Figure 40 IDMA External Requests Timing Diagram MPC852T Hardware Specifications Rev 3 1 44 Freescale Semiconductor CPM Electrical Characteristics CLKO Output TS Output RW Output TA Input SDACK Figure 41 SDACK Timing Diagram Peripheral Write Externally Generated TA CLKO Output TS Output R W Output TA Output SDACK Figure 42 SDACK Timing Diagram Peripheral Write Internally Generated TA MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 45 CPM Electrical Characteristics CLKO om _ _f _f N A N TS Output TA Output SDACK Figure 43 SDACK Timing Diagram Peripheral Read Internally Generated TA 14 3 Baud Rate Generator AC Electrical Specifications Table 18 provides the baud rate generator timings as shown in Figure 44 Table 18 Baud Rate Generator Timing All Frequencies Num Characteristic Unit Min Max 50 BRGO rise and fall time 10 ns 51 BRGO duty cycle
22. 5 V tolerant RXDO MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 73 Mechanical Data and Ordering Information Table 31 Pin Assignments non JEDEC continued Name Pin Number Type PD9 P15 Bidirectional RXD4 5 V tolerant MII TXDO PD8 N14 Bidirectional TXD4 5 V tolerant MII RX CLK PD7 U16 Bidirectional RTS3 5 V tolerant MII RX ER PD6 P14 Bidirectional RTS4 5 V tolerant MII RX DV PD5 T15 Bidirectional MII TXD3 5 V tolerant PD4 R15 Bidirectional MII TXD2 5 V tolerant PD3 N13 Bidirectional MII TXD1 5 V tolerant TMS G16 Input 5 V tolerant TDI H15 Input DSDI 5 V tolerant TCK J14 Input DSCK 5 V tolerant TRST G17 Input 5 V tolerant TDO G15 Output DSDO 5 V tolerant 7 Input MDIO H17 Bidirectional 5 V tolerant MII TX EN U15 Output 5 V tolerant MII COL G3 Input Vsssyn P5 PLL analog GND Vsssynt R4 PLL analog GND VpDSYN R3 PLL analog Vpp MPC852T Hardware Specifications Rev 3 1 74 Freescale Semiconductor Mechanical Data and Ordering Information Table 31 Pin Assignments non JEDEC continued Name Pin Number Type GND H7 H8 H9 H10 H11 H12 J7 J8 J9 J10 J11 J12 K7 K8 K9 Power K10 K11 K12 L7 L8 L9 L10 L11 L12 B8 D2 E17 H16 5 N3 T2 N16 U9 Power VDDH G6 G7 G8 G9 G10 G11 G12 G13 H6 H13 J6 J1
23. B1 6 00 B33a CLKOUT rising edge to GPL Valid as 7 60 14 30 6 30 18 00 5 00 11 80 3 80 10 50 ns requested by control bit GxT3 in the corresponding word in the UPM MAX 0 25 x B1 6 80 B34 A 0 31 BADDR 28 30 and D 0 31 to CS 5 60 4 30 3 00 1 80 ns valid as requested by control bit CST4 in the corresponding word in the UPM MIN 0 25 x B1 2 00 B34a 0 31 BADDR 28 30 and D 0 31 to CS 13 20 10 50 8 00 5 60 ns valid as requested by control bit CST1 in the corresponding word in the UPM MIN 0 50 x B1 2 00 B34b A 0 31 BADDR 28 30 and D 0 31 to CS 20 70 16 70 13 00 9 40 ns valid as requested by CST2 in the corresponding word in UPM MIN 0 75 x B1 2 00 B35 A 0 31 BADDR 28 30 to CS valid as 5 60 4 30 3 00 1 80 ns requested by control bit BST4 in the corresponding word in the UPM MIN 0 25 x B1 2 00 B35a A 0 31 BADDR 28 30 and D 0 31 to BS 13 20 10 50 8 00 5 60 ns valid As Requested by BST1 in the corresponding word in the UPM MIN 0 50 x B1 2 00 B35b A 0 31 BADDR 28 30 and D 0 31 to BS 20 70 16 70 13 00 9 40 ns valid as requested by control bit BST2 in the corresponding word in the UPM MIN 0 75 x B1 2 00 B36 A 0 31 BADDR 28 30 and D 0 31 to GPL 5 60 4 30 3 00 1 80 ns valid as requested by control bit GxT
24. Bidirectional CLK6 5 V tolerant TOUT3 PA1 M16 Bidirectional CLK7 5 V tolerant BRGO4 TIN4 PAO N17 Bidirectional CLK8 5 V tolerant TOUT4 PB31 F14 Bidirectional SPISEL Optional Open drain 5 V tolerant PB30 G14 Bidirectional SPICLK Optional Open drain 5 V tolerant PB29 E16 Bidirectional SPIMOSI Optional Open drain 5 V tolerant PB28 H14 Bidirectional SPIMISO Optional Open drain BRGO4 5 V tolerant MPC852T Hardware Specifications Rev 3 1 72 Freescale Semiconductor Mechanical Data and Ordering Information Table 31 Pin Assignments non JEDEC continued Name Pin Number Type PB25 J15 Bidirectional SMTXD1 Optional Open drain 5 V tolerant PB24 J17 Bidirectional SMRXD1 Optional Open drain 5 V tolerant PB15 M17 Bidirectional BRGOS3 5 V tolerant PC15 D17 Bidirectional DREQO 5 V tolerant PC13 F15 Bidirectional RTS3 5 V tolerant PC12 F16 Bidirectional RTS4 5 V tolerant PC7 K15 Bidirectional CTS3 5 V tolerant PC6 L16 Bidirectional CD3 5 V tolerant PC5 K14 Bidirectional CTS4 5 V tolerant SDACK1 PC4 M15 Bidirectional CD4 5 V tolerant PD15 N15 Bidirectional MII 5 V tolerant PD14 P17 Bidirectional MII RXD2 5 V tolerant PD13 L14 Bidirectional MII RXD1 5 V tolerant PD12 P16 Bidirectional MII MDC 5 V tolerant PD11 R17 Bidirectional RXD3 5 V tolerant MII TX ER PD10 T16 Bidirectional TXD3
25. OSCLK 15 MHz B2 CLKOUT pulse width low MIN 20 4 x B1 MAX 12 1 18 2 10 0 15 0 8 0 12 0 6 1 9 1 ns 0 6 x B1 B3 CLKOUT pulse width high MIN 0 4 x B1 12 1 18 2 10 0 150 80 120 61 9 1 ns MAX 0 6 x B1 B4 CLKOUT rise time 400 400 400 400 ns B5 CLKOUT fall time 400 400 400 4 00 ns B7 CLKOUT to A 0 31 BADDR 28 30 RD WR 760 6 30 5 00 3 80 ns BURST D 0 31 DP 0 3 output hold MIN 0 25 x B1 B7a CLKOUT to TSIZ 0 1 REG RSV BDIP PTR 7 60 6 30 500 3 80 ns output hold MIN 0 25 x B1 CLKOUT to BR BG FRZ VFLS 0 1 VF 0 2 7 60 6 30 5 00 380 ns IWP 0 2 LWP 0 1 STS output hold MIN 0 25 x B1 B8 CLKOUT to A 0 31 BADDR 28 30 RD WR 13 80 12 50 11 30 10 00 ns BURST D 0 31 DP 0 3 valid MAX 0 25 x B1 6 3 B8a CLKOUT to TSIZ 0 1 REG RSV BDIP PTR 13 80 12 50 11 30 10 00 ns valid MAX 0 25 x B1 6 3 B8b CLKOUT to BR BG VFLS 0 1 VF 0 2 13 80 1250 11 30 10 00 ns IWP 0 2 FRZ LWP 0 1 STS Valid 3 MAX 0 25 x B1 6 3 B9 CLKOUT to A 0 31 BADDR 28 30 RD WR 7 60 13 80 6 30 12 50 5 00 11 30 3 80 10 00 ns BURST D 0 31 DP 0 3 TSIZ 0 1 REG RSV PTR Hig
26. P8 N9 Three state 3 3 V only T12 T7 R7 U6 T6 DPO R5 Bidirectional IRQ3 Three state 3 3 V only DP1 R6 Bidirectional IRQ4 Three state 3 3 V only DP2 U5 Bidirectional IRQ5 Three state 3 3 V only DP3 T5 Bidirectional IRQ6 Three state 3 3 V only MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 69 Mechanical Data and Ordering Information Table 31 Pin Assignments non JEDEC continued Name Pin Number Type BR F2 Bidirectional 3 3 V only BG H5 Bidirectional 3 3 V only BB G4 Bidirectional Active Pull up 3 3 V only FRZ J5 Bidirectional 3 3 V only IRQ6 IRQO R14 Input 3 3 V only IRQ1 N12 Input 3 3 V only IRQ7 P13 Input 3 3 V only M TX CLK CS 0 5 C3 B3 E4 D4 F7 D5 Output CS6 E5 Output CS7 B4 Output WEO E7 Output BS_BO IORD WE1 D7 Output BS B1 IOWR WE2 B6 Output BS B2 PCOE WE3 C6 Output BS B3 PCWE BS A 0 3 B7 E8 D8 C8 Output GPL A0 D6 Output GPL BO OE E6 Output GPL A1 GPL B1 GPL A 2 3 B5 C5 Output GPL B 2 3 5 2 3 UPWAITA D3 Bidirectional 3 3 V only GPL_A4 GPL_A5 F5 Output PORESET R2 Input 3 3 V only MPC852T Hardware Specifications Rev 3 1 70 Freescale Semiconductor Mechanical Data and Ordering Information Table 31 Pin Assignments non JEDEC continued
27. PC13 E14 Bidirectional RTS3 5V tolerant PC12 E15 Bidirectional RTS4 5V tolerant PC7 J14 Bidirectional CTS3 5V tolerant PC6 K15 Bidirectional CD3 5V tolerant PC5 J13 Bidirectional CTS4 5V tolerant SDACK1 PC4 L14 Bidirectional CD4 5V tolerant PD15 M14 Bidirectional MII 5V tolerant PD14 N16 Bidirectional MII RXD2 5V tolerant PD13 K13 Bidirectional RXD1 5V tolerant PD12 N15 Bidirectional MII MDC 5V tolerant PD11 P16 Bidirectional RXD3 5V tolerant MII TX ER PD10 R15 Bidirectional TXD3 5V tolerant MII RXDO PD9 N14 Bidirectional RXD4 5V tolerant MII TXDO PD8 M13 Bidirectional TXD4 5V tolerant 07 T15 Bidirectional RTS3 5V tolerant MII ER MPC852T Hardware Specifications Rev 3 1 66 Freescale Semiconductor Mechanical Data and Ordering Information Table 30 Pin Assignments JEDEC Standard continued Name Pin Number Type PD6 N13 Bidirectional RTS4 5V tolerant MII RX DV PD5 R14 Bidirectional MII TXD3 5V tolerant PD4 P14 Bidirectional MII TXD2 5V tolerant PD3 M12 Bidirectional MII TXD1 5V tolerant TMS F15 Input 5V tolerant TDI G14 Input DSDI 5V tolerant TCK H13 Input DSCK 5V tolerant TRST F16 Input 5V tolerant TDO F14 Output DSDO 5V tolerant B6 Input MDIO G16 Bidirectional 5V tolerant TXEN T14 Output 5V tolerant MII COL F2 I
28. determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation where thermal characterization parameter thermocouple temperature on top of package Pp power dissipation in package The thermal characterization parameter is measured per JESD51 2 specification published by JEDEC using a 40 gauge type T thermocouple epoxied to the top center of the package case The thermocouple should be positioned so that the thermocouple junction rests on the package A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction The thermocouple wire is placed flat against the package case to avoid measurement errors that cooling effects of the thermocouple wire cause 8 References Semiconductor Equipment and Materials International 415 964 5111 805 East Middlefield Rd Mountain View CA 94043 MIL SPEC and EIA JESD JEDEC specifications800 854 7179 or Available from Global Engineering documents 303 397 7956 JEDEC Specifications http www jedec org 1 Triplett and B Joiner An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module Proceedings of SemiTherm San Diego 1998 pp 47 54 2 B Joiner and V Adams Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling Proceedings of SemiTherm San D
29. liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freesc
30. support option e Two SCCs serial communication controllers Ethernet IEEE 802 3 optional on SCC3 amp supporting full 10 Mbps operation HDLC SDLC HDLC bus implements an HDLC based local area network LAN Universal asynchronous receiver transmitter UART Totally transparent bit streams Totally transparent frame based with optional cyclic redundancy check CRC One SMC serial management channels UART e One SPI serial peripheral interface Supports master and slave modes Supports multimaster operation on the same bus e PCMCIA interface Master socket interface release 2 1 compliant MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 3 Features Supports one independent PCMCIA socket 8 memory or I O windows supported e Debug interface Eight comparators four operate on instruction address two operate on data address and two operate on data Supports conditions lt gt Each watchpoint can generate a break point internally e Normal high and normal low power modes to conserve power e 1 8 V Core and 3 3 V I O operation with 5 V TTL compatibility Refer to Table 5 for a listing of the 5 V Tolerant pins Instruction 4 Kbyte System Interface Unit SIU Bus Instruction Cache Instruction MMU Unified Memory Controller Bus UE eg 32 Entry ITLB Internal External BE Bus Interface Bus Interface a Core Load St
31. time 15 m ns 172 Slave enable lag time 15 ns 173 Slave clock SPICLK high or low time 1 toye 174 Slave sequential transfer delay does not require deselect 1 toye 175 Slave data setup time inputs 20 ns 176 Slave data hold time inputs 20 ns 177 Slave access time 50 ns MPC852T Hardware Specifications Rev 3 1 54 Freescale Semiconductor SPISEL Input SPICLK 1 0 Input SPICLK Cl 1 Input SPIMISO Output SPIMOSI Input Figure 56 SPI Slave CP 0 Timing Diagram MPC852T Hardware Specifications Rev 3 1 CPM Electrical Characteristics Freescale Semiconductor 55 FEC Electrical Characteristics SPISEL Input SPICLK Cl 0 Input SPICLK Cl 1 Input SPIMISO Output SPIMOSI Input Figure 57 SPI Slave CP 1 Timing Diagram 15 FEC Electrical Characteristics This section provides the AC electrical specifications for the fast Ethernet controller FEC Note that the timing specifications for the MII signals are independent of system clock frequency part speed designation Also MII signals use TTL signal levels compatible with devices operating at either 5 0 V or 3 3 V 15 1 MII Receive Signal Timing RXD 3 0 DV ER MII The receiver functions correctly up to a MIT_RX_CLK maximum frequency o
32. twice bus speed Table 4 Power Dissipation Pp Die Revision Bus Mode aa Typical 1 Maximum 2 Unit 50 110 140 mW nl 66 150 180 mW 0 66 140 160 mW 244 80 170 200 mW 100 210 250 mW Typical power dissipation is measured at 1 9 V MPC852T Hardware Specifications Rev 3 1 6 Freescale Semiconductor DC Characteristics Maximum power dissipation at Vpp and Vppgyn is at 1 9 V and Vppy is at 3 465 V NOTE Values in Table 4 represent Vppj based power dissipation and do not include I O power dissipation over Vppg I O power dissipation varies widely by application that buffer current can cause depending on external circuitry The Vppsyw power dissipation is negligible 6 DC Characteristics Table 5 provides the DC electrical characteristics for the MPC852T Table 5 DC Electrical Specifications Characteristic Symbol Min Max Unit Operating voltage VppH 3 135 3 465 V VDDpL 1 7 1 9 V VppsvN 1 7 1 9 V Difference between Vpp to 100 mV VppsYN Input high voltage all inputs except Vin 2 0 3 465 V PA 0 3 PA 8 11 PB15 PB 24 25 PB 28 31 PC 4 7 PC 12 13 PC15 PD 3 15 TDI TDO TRST TMS TXEN Input low voltage Vit GND 0 8 EXTAL EXTCLK input high voltage 0 7 xVppu Vppu Input leakage current Vin 5 5 lin 100 uA Except TMS TRST DSCK and DSDI pins
33. 3 K6 K13 Power L6 L13 M6 M7 M8 M9 M10 M11 M12 M13 N C B2 B17 C17 D16 E15 F13 M14 N5 R16 T17 U2 U17 No connect MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 75 Mechanical Data and Ordering Information 16 2 Mechanical Dimensions of the PBGA Package For more information on the printed circuit board layout of the PBGA package including thermal via design and suggested pad layout refer to Plastic Ball Grid Array Application Note order number AN1231 D that is available from your local Freescale sales office Figure 64 shows the mechanical dimensions of the PBGA package MPC852T Hardware Specifications Rev 3 1 76 Freescale Semiconductor Mechanical Data and Ordering Information 23 gt 194 SEATING A1 INDEX T 256x Q 0 2 A lI i SS 0 25 A pa 0 35 A 19 7 5 D 19 3 D D D SS A D 4X C 0 2 VIEW R 19 05 D 15X 1 27 L D 0 635 T b i D T R D P N 15X 1 27 M 0 7 t R 0 5 s 19 05 H 122 1 0 50 0 635 1 12 2 54
34. 4 in the corresponding word in the UPM MIN 0 25 x B1 2 00 B37 UPWAIT valid to CLKOUT falling edge MIN 6 00 6 00 6 00 6 00 ns 0 00 x B1 6 00 B38 CLKOUT falling edge to UPWAIT valid MIN 1 00 1 00 1 00 1 00 ns 0 00 x B1 1 00 MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 19 Bus Signal Timing Table 9 Bus Operation Timings continued 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B39 AS valid to CLKOUT rising edge MIN 0 00 7 00 7 00 7 00 7 00 ns x B1 7 00 B40 A 0 31 TSIZ 0 1 RD WR BURST valid to 7 00 7 00 7 00 7 00 ns CLKOUT rising edge MIN 0 00 x B1 7 00 B41 TS valid to CLKOUT rising edge setup time 7 00 7 00 7 00 7 00 ns MIN 0 00 x B1 7 00 B42 CLKOUT rising edge to TS valid hold time 2 00 2 00 2 00 2 00 ns MIN 0 00 x B1 2 00 B43 AS negation to memory controller signals TBD TBD TBD TBD ns negation MAX TBD If the rate of change of the frequency of EXTAL is slow that is it does not jump between the minimum and maximum values in one cycle or the frequency of the jitter is fast that is it does not stay at an extreme value for a long time then the maximum allowed jitter on EXTAL can be up to 2 For part speeds above 50MHz
35. 40 60 96 52 BRGO cycle 40 ns BRGOX Figure 44 Baud Rate Generator Timing Diagram MPC852T Hardware Specifications Rev 3 1 46 Freescale Semiconductor 14 4 Timer AC Electrical Specifications CPM Electrical Characteristics Table 19 provides the general purpose timer timings as shown in Figure 45 CLKO TIN TGATE Input TOUT Output Table 19 Timer Timing All Frequencies Num Characteristic Unit Min Max 61 TIN TGATE rise and fall time 10 ns 62 TIN TGATE low time 1 clk 63 high time 2 clk 64 TIN TGATE cycle time 3 clk 65 CLKO low to TOUT valid 3 25 ns Figure 45 CPM General Purpose Timers Timing Diagram 14 5 SCC in NMSI Mode Electrical Specifications Table 20 provides the NMSI external clock timing Table 20 NMSI External Clock Timing All Frequencies Num Characteristic Unit Min Max 100 RCLK3 and TCLK3 width high 1 SYNCCLK mE ns 101 RCLK3 and TCLK3 width low 1 SYNCCLK 5 ns 102 RCLK3 and TCLK3 rise fall time m 15 00 ns 103 TXD3 active delay from TCLK3 falling edge 0 00 50 00 ns 104 RTS3 active inactive delay from TCLK3 falling edge 0 00 50 00 ns 105 CTS3 setup time to TCLK3 rising edge 5 00 ns MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 47 CPM Electrical Characteristics Table 20
36. 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 0047 Japan 0120 191014 81 3 3440 3569 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Lid Technical Information Center 2 Dai King Street Tai Po Indusirial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 800 441 2447 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com MPC852TEC Rev 3 1 01 2005 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all
37. B 2 00 2 00 2 00 2 00 ns invalid MIN 0 00 x B1 2 00 PSST 1 Otherwise add PSST times cycle time PSHT 0 Otherwise add PSHT times cycle time These synchronous timings define when the WAITA signals are detected in order to freeze or relieve the PCMCIA current cycle The WAITA assertion is effective only if it is detected 2 cycles before the PSL timer expiration See PCMCIA Interface in the MPC852T PowerQUICC User s Manual MPC852T Hardware Specifications Rev 3 1 34 Freescale Semiconductor Bus Signal Timing Figure 25 provides the PCMCIA access cycle timing for the external bus read CLKOUT OA S NOA NAO AOON a fa COE IORD ALE D 0 31 Figure 25 PCMCIA Access Cycles Timing External Bus Read MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 35 Bus Signal Timing Figure 26 provides the PCMCIA access cycle timing for the external bus write CLKOUT 7 M fu PCWE IOWR ALE D 0 31 Figure 26 PCMCIA Access Cycles Timing External Bus Write Figure 27 provides the PCMCIA WAIT signals detection timing CLKOUT WAITA Figure 27 PCMCIA WAIT Signals Detection Timing MPC852T Hardware Specifications Rev 3 1 36 Freescale Semiconductor Bus Signal Timing Table 12 shows the PCMCIA port timing for the MPC852T Table 12 PCMCIA Port Timing
38. Diagram MPC852T Hardware Specifications Rev 3 1 52 Freescale Semiconductor CPM Electrical Characteristics 14 7 SPI Master AC Electrical Specifications Table 23 provides the SPI master timings as shown in Figure 54 and Figure 55 Table 23 SPI Master Timing All Frequencies Num Characteristic Unit Min Max 160 MASTER cycle time 4 1024 161 MASTER clock SCK high or low time 2 512 toye 162 MASTER data setup time inputs 15 ns 163 Master data hold time inputs 0 ns 164 Master data valid after SCK edge 10 ns 165 Master data hold time outputs 0 ns 166 Rise time output 15 ns 167 Fall time output 15 ns SPICLK Cl 0 Output SPICLK Cl 1 Output SPIMISO Input SPIMOSI Output Figure 54 SPI Master CP 0 Timing Diagram MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 53 CPM Electrical Characteristics SPICLK Cl 0 Output SPICLK Cl 1 Output SPIMISO Input SPIMOSI Output Figure 55 SPI Master CP 1 Timing Diagram 14 8 SPI Slave AC Electrical Specifications Table 24 provides the SPI slave timings as shown in Figure 56 and Figure 57 Table 24 SPI Slave Timing All Frequencies Num Characteristic Unit Min Max 170 Slave cycle time 2 171 Slave enable lead
39. Freescale Semiconductor Technical Data MPC852T Hardware Specifications This document contains detailed information for the MPC852T about power considerations DC AC electrical characteristics AC timing specifications and pertinent electrical and physical characteristics of the MPC852T For information about functional characteristics of the processor refer to the MPC666 PowerQUICC Family Users Manual MPC866UM The MPC8527T contains a PowerPC M processor core 1 Overview The MPC852T PowerQUICC is a 0 18 micron derivative of the MPC860 PowerQUICC family and can operate up to 100 MHz on the MPC8xx core with a 66 MHz external bus The MPC852T has a 1 8 V core and a 3 3 V I O operation with 5 V TTL compatibility The MPC852T integrated communications controller is a versatile one chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications It particularly excels in Ethernet control applications including CPE equipment Ethernet routers and hubs VoIP clients and WiFi access points The MPC852T is a PowerPC architecture based derivative of the Freescale MPC860 Quad Integrated Communications Controller PowerQUICC The CPU on the MPC852T is the MPC8xx core a 32 bit microprocessor that implements the PowerPC architecture incorporating memory management units MMUs and instruction and data caches The MPC852T is the subset of this family of devices Freescale Semiconduc
40. NMSI External Clock Timing continued All Frequencies Num Characteristic Unit Min Max 106 RXD3 setup time to RCLK3 rising edge 5 00 ns 107 RXD3 hold time from RCLK3 rising edge 2 5 00 ns 108 setup Time to RCLKS rising edge 5 00 ns 1 The ratios SyncCLK RCLK3 and SyncCLK TCLK3 must be greater than or equal to 2 25 1 Also applies to CD and CTS hold time when they are used as an external sync signal Table 21 provides the NMSI internal clock timing Table 21 NMSI Internal Clock Timing All Frequencies Num Characteristic Unit Min Max 100 RCLK3 and TCLK3 frequency 0 00 SYNCCLK 3 MHz 102 RCLK3 and TCLK3 rise fall time ns 103 TXD3 active delay from TCLKS falling edge 0 00 30 00 ns 104 RTS3 active inactive delay from TCLK3 falling edge 0 00 30 00 ns 105 CTS3 setup time to TCLK3 rising edge 40 00 ns 106 RXD3 setup time to RCLK rising edge 40 00 ns 107 RXD3 hold time from RCLK3 rising edge 2 0 00 ns 108 CD3 setup time to RCLK3 rising edge 40 00 ns 1 The ratios SyncCLK RCLK3 and SyncCLK TCLK3 must be greater or equal to 3 1 Also applies to CD and CTS hold time when they are used as an external sync signals MPC852T Hardware Specifications Rev 3 1 48 Freescale Semiconductor CPM Electrical Characteristics Figure 46 through Figure 48 show the NMSI timings RCLK3 RxD3 Input
41. PD11 MII RXO TXD3 PD10 MII TXDO RXD4 PDS MII RXCLK TXD4 PD8 MII TXD3 PD5 MII RXDV RTS4 PD6 MII RXERR RTS3 PD7 MII TXD2 REJECT3 PDA MII TXD1 REJECTA PD3 CRS MDIO TXEN COL BDIP GPL_B 5 BR BG FRZ IRQ6 CS 0 5 CS 6 CS 7 WEO BS BO IORD WE1 BS B1 IOWR WE2 BS B2 PCOE WE3 BS B3 PCWE BS A 0 3 GPL AO GPL OE GPL A1 GPL B1 GPL A 2 3 GPL 2 3 5 2 3 UPWAITA GPL A4 GPL A5 ALE A CE1_A CE2 A DSCK OP 0 1 OP2 MODCK1 STS OP3 MODCK2 DSDO BADDR 28 30 7 Thermal Calculation and Measurement For the following discussions Pp VppL x IDDL Pro where is the power dissipation of the I O drivers 7 1 Estimation with Junction to Ambient Thermal Resistance NOTE The Vppsyw power dissipation is negligible An estimation of the chip junction temperature in can be obtained from the equation where ambient temperature Roya package junction to ambient thermal resistance C W Pp power dissipation in package MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor Thermal Calculation and Measurement The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance However the answer is only an estimate test cases have demonstrated that errors of a factor of two in the quantity Tj T are possible 7 2 Estimation with Ju
42. XD3 Optional Open drain 5V tolerant MPC852T Hardware Specifications Rev 3 1 64 Freescale Semiconductor Table 30 Pin Assignments JEDEC Standard continued Mechanical Data and Ordering Information Name Pin Number Type PA10 H15 Bidirectional TXD3 5V tolerant 9 J16 Bidirectional RXD4 Optional Open drain 5V tolerant PA8 J15 Bidirectional TXD4 5V tolerant PA3 K16 Bidirectional CLK5 5V tolerant BRGO3 TIN3 PA2 K14 Bidirectional CLK6 5V tolerant TOUT3 PA1 L15 Bidirectional CLK7 5V tolerant BRGO4 TIN4 PAO M16 Bidirectional CLK8 5V tolerant TOUT4 PB31 E13 Bidirectional SPISEL Optional Open drain 5V tolerant PB30 F13 Bidirectional SPICLK Optional Open drain 5V tolerant PB29 D15 Bidirectional SPIMOSI Optional Open drain 5V tolerant PB28 G13 Bidirectional SPIMISO Optional Open drain BRGO4 5V tolerant PB25 H14 Bidirectional SMTXD1 Optional Open drain 5V tolerant PB24 H16 Bidirectional SMRXD1 Optional Open drain 5V tolerant PB15 L16 Bidirectional BRGOS3 5V tolerant MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 65 Mechanical Data and Ordering Information Table 30 Pin Assignments JEDEC Standard continued Name Pin Number Type PC15 C16 Bidirectional DREQO 5V tolerant
43. ale logo are trademarks of Freescale Semiconductor Inc The described product contains a PowerPC processor core The PowerPC name is a trademark of IBM Corp and used under license All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2005 2 freescale semiconductor
44. aracteristic Unit Min Max Min Max Min Max Min Max J82 A 0 31 REG valid to PCMCIA Strobe 20 70 16 70 13 00 9 40 ns asserted MIN 0 75 x B1 2 00 J83 A 0 31 REG valid to ALE negation MIN 28 30 23 00 18 00 13 20 ns 1 00 x B1 2 00 J84 CLKOUT to REG valid MAX 0 25 x B1 7 60 15 60 6 30 14 30 5 00 13 00 3 80 11 80 ns 8 00 CLKOUT to REG Invalid MIN 0 25 x B1 8 60 7 30 6 00 4 80 ns J85 1 00 J86 CLKOUT to CE1 CE2 asserted MAX 7 60 15 60 6 30 14 30 5 00 13 00 3 80 11 80 ns 0 25 x B1 8 00 J87 CLKOUT to CE1 CE2 negated MAX 7 60 15 60 6 30 14 30 5 00 13 00 3 80 11 80 ns 0 25 x B1 8 00 J88 CLKOUT to PCOE IORD PCWE IOWR 11 00 11 00 11 00 11 00 ns assert time MAX 0 00 x B1 11 00 J89 CLKOUT to PCOE IORD PCWE IOWR 2 00 11 00 2 00 11 00 2 00 11 00 2 00 11 00 ns negate time MAX 0 00 x B1 11 00 CLKOUT to ALE assert time MAX 0 25 7 60 13 80 6 30 12 50 5 00 11 30 3 80 10 00 ns J90 B1 6 30 CLKOUT to ALE negate time MAX 0 25x 15 60 14 30 13 00 11 80 ns J91 B1 8 00 J92 PCWE IOWR negated to D 0 31 invalid 5 60 m 4 30 3 00 1 80 ns MIN 0 25 x B1 2 00 J93 WAITA and WAITB valid to CLKOUT rising 8 00 m 8 00 8 00 8 00 ns edge MIN 0 00 x B1 8 00 J94 CLKOUT rising edge to WAITA and WAIT
45. current can flow through these diodes If the system power supply design does not control the voltage sequencing the circuit shown in Figure 2 can be added to meet these requirements The MUR420 Schottky diodes control the maximum potential difference between the external bus and core power supplies on power on reset and the 1N5820 diodes regulate the maximum potential difference on power down VppH MUR420 PP lt 1N5820 Figure 2 Example Voltage Sequencing Circuit 10 Mandatory Reset Configurations The MPC852T requires a mandatory configuration during reset If hardware reset configuration word HRCW is enabled by asserting the RSTCONF during HRESET assertion the HRCW DBGC value that is needed to be set to binary X1 in the hardware reset configuration word HRCW and the SIUMCR DBGC should be programmed with the same value in the boot code after reset If hardware reset configuration word HRCW is disabled by negating the RSTCONF during the HRESET assertion the SIUMCR DBGC should be programmed with binary in the boot code after reset MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor Layout Practices The MBMR GPLB4DIS PAPAR PADIR PBPAR PBDIR PCPAR and PCDIR should be configured with the mandatory value in Table 6 in the boot code after the reset deasserts Table 6 Mandatory Reset Configuration of MPC852T Regis
46. d 0 00 2 00 ns Figure 30 provides the input timing for the debug port clock DSCK Figure 30 Debug Port Clock Input Timing Figure 31 provides the timing for the debug port DSCK DSDI DSDO Figure 31 Debug Port Timings MPC852T Hardware Specifications Rev 3 1 38 Freescale Semiconductor Table 14 shows the reset timing for the MPC852T Table 14 Reset Timing Bus Signal Timing Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Min Max Min Max Min Max Min Max Unit CLKOUT to HRESET high impedance MAX 0 00 x B1 20 00 20 00 20 00 20 00 20 00 ns J83 CLKOUT to SRESET high impedance MAX 0 00 x B1 20 00 20 00 20 00 20 00 20 00 ns J84 RSTCONF pulse width MIN 17 00 x B1 515 20 425 00 340 00 257 60 ns J85 J86 Configuration data to HRESET rising edge set up time MIN 15 00 x B1 50 00 504 50 425 00 350 00 277 30 ns J87 Configuration data to RSTCONF rising edge set up time MIN 0 00 x B1 350 00 350 00 350 00 350 00 350 00 ns J88 Configuration data hold time after RSTCONF negation MIN 0 00 x B1 0 00 0 00 0 00 ns J89 Configuration data hold time after HRESET negation MIN 0 00 x B1 0 00
47. d pin listing for the JEDEC Compliant and the non JEDEC versions of the 16 x 16 PBGA package MPC852T Hardware Specifications Rev 3 1 60 Freescale Semiconductor Mechanical Data and Ordering Information 16 1 1 The JEDEC Compliant Pinout Figure 62 shows the JEDEC pinout of the PBGA package as viewed from the top surface For additional information see the MPC666 PowerQUICC Family User s Manual NOTE This is the top view of the device A2 A6 c O O D A31 A2 A15 N C 20 A A5 C PC13 9 F 000000 0 G 000000 0 H 0000000 J 000000 0 K O L 29999999 LKOUT 025 D 015 DIO 017 1807 D29 024 D11 Q D12 P O R D28 D13 PD5 PD10 N C JO 80 DOs O Q vi Aen Q Q Figure 62 Pinout of the PBGA Package JEDEC Standard MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 61 Mechanical Data and Ordering Information Table 30 contains a list of the MPC852T input and output signals and shows multiplexing and pin assignments Table 30 Pin Assignments JEDEC Standard Name Pin Number Type A 0 31 B15 A15 A14 C14 D13 E11 B14 A13 C13 B13 D12 E10 C12 Bidirectional B12 A12 D11 E9 C11 A9 11 D10 C10 B8 10 D9 C9 C8 Three state 3 3V only B11 A8 B10 B9 D8 TSIZO E8 Bidirectional REG Three state 3 3V only TSIZ1 E7 Bidirectional Three state 3
48. e 50 MHz 66 MHz core frequencies support both 1 1 and 2 1 modes The 80 MHz 100 MHz core frequencies support 2 1 mode only e Single issue 32 bit core compatible with the PowerPC architecture definition with 32 32 bit general purpose registers GPRs The core performs branch prediction with conditional prefetch without conditional execution 4 Kbyte data cache and 4 Kbyte instruction cache 4 Kbyte instruction cache is two way set associative with 128 sets 4 Kbyte data cacheis two way set associative with 128 sets Cache coherency for both instruction and data caches is maintained on 128 bit 4 word cache blocks Caches are physically addressed implement a least recently used LRU replacement algorithm and are lockable on a cache block basis MMUS with 32 entry TLB fully associative instruction and data TLBs MMUS support multiple page sizes of 4 16 and 512 Kbytes and 8 Mbytes 16 virtual address spaces and 16 protection groups e Up to 32 bit data bus dynamic bus sizing for 8 16 and 32 bits 32 address lines e Memory controller eight banks Contains complete dynamic RAM DRAM controller Each bank can be a chip select or RAS to support a DRAM bank Up to 30 wait states programmable per memory bank Glueless interface to DRAM SIMMS SRAM EPROMs Flash EPROMs and other memory devices DRAM controller programmable to support most size and speed memory interfaces Four CAS lines four WE lin
49. e the timing for the external bus write that various GPCM factors control D 0 31 DP 0 3 Figure 14 External Bus Write Timing GPCM Controlled TRLX 0 or 1 CSNT 0 MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 27 Bus Signal Timing CLKOUT _ o X X4 X un 0 31 622 re CSx WE 0 3 D 0 31 DP 0 3 Figure 15 External Bus Write Timing GPCM Controlled TRLX 0 or 1 CSNT 1 MPC852T Hardware Specifications Rev 3 1 28 Freescale Semiconductor Bus Signal Timing 0 31 5 0 3 D 0 31 DP 0 3 611 612 Figure 16 External Bus Write Timing GPCM Controlled TRLX 0 or 1 CSNT 1 MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 29 Bus Signal Timing Figure 17 provides the timing for the external bus that the UPM controls CLKOUT 5 2 nosy EL B lt gt 2 Lre LLL LLLA XX X GPL A 0 5 GPL B 0 5 gt 65 Figure 17 External Bus Timing Controlled Signals MPC852T Hardware Specifications Rev 3 1 30 Freescale Semiconductor Bus Signal Timing Figure 18 provides the timing for the asynchronous asserted UPWAIT signal that the UPM controls
50. es and one OE line Boot chip select available at reset options for 8 16 or 32 bit memory Variable block sizes 32 Kbytes 256 Mbytes Selectable write protection On chip bus arbitration logic e Fast Ethernet Controller FEC e General purpose timers Two 16 bit timers or one 32 bit timer Gate mode can enable or disable counting Interrupt can be masked on reference match and event capture MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor Features e System integration unit SIU Bus monitor Software watchdog Periodic interrupt timer PIT Clock synthesizer Decrementer and time base Reset controller JEEE 1149 1 test access port JTAG e Interrupts Seven external interrupt request IRQ lines Seven port pins with interrupt capability Eighteen internal interrupt sources Programmable priority between SCCs Programmable highest priority request Communications processor module CPM RISC controller Communication specific commands for example GRACEFUL STOP TRANSMIT ENTER HUNT MODE and RESTART TRANSMIT Supports continuous mode transmission and reception on all serial channels 8 Kbytes of dual port RAM 8 serial DMA SDMA channels Three parallel I O registers with open drain capability e Two baud rate generators Independent can be connected toany SCC3 4 or SMC1 Allows changes during operation Autobaud
51. evice Caution All inputs that tolerate 5 V cannot be more than 2 5 V greater than This restriction applies to power up and normal operation that is if the MPC852T is unpowered a voltage greater than 2 5 V must not be applied to its inputs Table 2 Operating Temperatures Rating Symbol Value Unit Temperature 1 standard TA min 0 C Tmax 95 C Temperature extended TA min 40 100 C 1 are guaranteed as junction temperature T Minimum temperatures are guaranteed as ambient temperature T4 Maximum temperatures This device contains circuitry protecting against damage that high static voltage or electrical fields cause however Freescale recommends taking normal precautions to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level for example either GND or Vppg 4 Thermal Characteristics Table 3 shows the thermal characteristics for the MPC852T MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor Power Dissipation Table 3 MPC852T Thermal Resistance Data Rating Environment Symbol Value Unit Junction to ambient Natural convection Single layer board 1s Roa z 49 C W Four layer board 252 Rema 32 Air flow 200 ft min Single la
52. f 25MHz 1 There is minimum frequency requirement In addition the processor clock frequency must exceed MII RX frequency 1 Table 25 provides information on the receive signal timing Table 25 MII Receive Signal Timing e ET MII RXD 0 MIL_RX_DV MIL ER to MIl_RX_CLK setup s to MII RXD 3 0 DV MII ER hold 5 pulse width high period MIL pulse width low MIL period MPC852T Hardware Specifications Rev 3 1 56 Freescale Semiconductor Figure 58 shows MII receive signal timing M3 input FEC Electrical Characteristics lt M1 M4 3 0 inputs MII RX DV RX ER M2 Figure 58 MII Receive Signal Timing Diagram 15 2 MII Transmit Signal Timing TXD 3 0 MII TX EN TX ER MII TX The transmitter functions correctly up to a MII TX CLK maximum frequency of 25 MHz 1 There is no minimum frequency requirement In addition the processor clock frequency must exceed the MII TX CLK frequency 1 Table 26 provides information about the MII transmit signal timing Table 26 MII Transmit Signal Timing Num Characteristic Min Max Unit M5 MII TX CLK to MII TXD 3 0 TX EN TX ER invalid 5 ns M6 TX CLK to MII TXD 3 0
53. for 5 V tolerant pins 1 Input leakage current Vin VppH lin 10 Except TMS TRST DSCK DSDI Input leakage current Vin 0 V Except lin 10 uA TMS TRST DSCK and DSDI pins Input capacitance Cin 20 pF MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor Thermal Calculation and Measurement Table 5 DC Electrical Specifications continued Characteristic Symbol Min Max Unit Output high voltage IOH 2 0 mA VOH 2 4 V Vppu 3 0 V Except XTAL and open drain pins Output low voltage VOL 0 5 V IOL 2 0 mA CLKOUT IOL 3 2 mA IOL 5 3 mA 4 IOL 7 0 mA Txd1 pa14 txd2 pa12 IOL 8 9 mA TS TA TEA BI BB HRESET SRESET N AR The PA 0 3 PA 8 11 PB15 PB 24 25 PB 28 31 PC 4 7 PC 12 13 PC15 PD 3 15 TDI TDO TRST TMS MII TXEN MII MDIO are 5 V tolerant pins Input capacitance is periodically sampled A 0 31 TSIZO REG TSIZ1 D 0 31 DP 0 3 IRQ 3 6 RD WR BURST RSV IRQ2 IWP 0 1 VFLS 0 1 RXD3 PA11 TXD3 PA10 RXD4 PA9 TXD4 PA8 TIN3 BRGO3 CLK5 PA3 BRGCLK2 TOUT3 CLK6 PA2 TIN4 BRGO4 CLK7 PA1 TOUT4 CLK8 PAO SPISEL PB31 SPICLK PB30 SPIMOSI PB29 BRGO4 SPIMISO PB28 SMTXD1 PB25 SMRXD1 PB24 BRGO3 PB15 RTS1 DREQO PC15 RTS3 PC13 RTS4 PC12 CTS3 PC7 CD3 PC6 CTS4 SDACK1 PC5 CD4 PC4 MII RXD3 PD15 MII RXD2 PD14 MII RXD1 PD13 MII MDC PD12 MII TXERR RXD3
54. h Z MAX 0 25 x B1 6 3 B11 CLKOUT to TS BB assertion MAX 20 25 x B1 7 60 13 60 6 30 12 30 5 00 11 00 3 80 9 80 ns 4 6 0 B11a CLKOUT to TA BI assertion when driven by 2 50 9 30 2 50 9 30 2 50 9 30 2 50 9 80 ns the memory controller or PCMCIA interface MAX 0 00 x B1 9 30 B12 CLKOUT to TS BB negation MAX 2 0 25 x B1 7 60 12 30 6 30 11 00 5 00 9 80 3 80 8 50 ns 4 8 B12a CLKOUT to TA BI negation when driven by 2 50 9 00 2 50 9 00 250 9 00 2 50 9 00 ns the memory controller or PCMCIA interface MAX 0 00 x B1 9 00 B13 CLKOUT to TS BB High Z MIN 0 25 x B1 7 60 21 60 6 30 20 30 5 00 19 00 3 80 14 00 ns MPC852T Hardware Specifications Rev 3 1 14 Freescale Semiconductor Table 9 Bus Operation Timings continued Bus Signal Timing 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B13a CLKOUT to TA BI High Z when driven by the 2 50 15 00 2 50 15 00 2 50 15 00 2 50 15 00 ns memory controller or PCMCIA interface MIN 0 00 x B1 2 5 B14 to TEA assertion MAX 20 00 xB1 2 50 9 00 2 50 9 00 2 50 9 00 2 50 9 00 ns 9 00 B15 to TEA High Z MIN
55. heat is conducted to the printed circuit board Thermal performance of most plastic packages and especially PBGA packages is strongly dependent on the board temperature If the board temperature is known an estimate of the junction temperature in the environment can be made using the following equation T Tg Royp X Pp where junction to board thermal resistance C W board temperature Pp power dissipation in package If the board temperature is known and the heat loss from the package case to the air can be ignored acceptable predictions of junction temperature can be made For this method to work the board and board mounting must be similar to the test board used to determine the junction to board thermal resistance namely a 2s2p board with a power and a ground plane and vias attaching the thermal balls to the ground plane 7 4 Estimation Using Simulation When the board temperature is not known a thermal simulation of the application is needed The simple two resistor model can be used with the thermal simulation of the application 2 or a more accurate and complex model of the package can be used in the thermal simulation MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 9 References 7 5 Experimental Determination To determine the junction temperature of the device in the application after prototypes are available the thermal characterization parameter V can be used to
56. ication Minimum output hold time c Minimum input setup time specification Minimum input hold time specification Figure 3 Control Timing Figure 4 provides the timing for the external clock CLKOUT Figure 4 External Clock Timing MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 21 Bus Signal Timing Figure 5 provides the timing for the synchronous output signals CLKOUT Output Signals Output Signals Output Signals ee eee ee eee XR A __ B8b ON ils Figure 5 Synchronous Output Signals Timing t f Figure 6 provides the timing for the synchronous active pull up and open drain output signals CLKOUT TEA Figure 6 Synchronous Active Pull Up Resistor and Open Drain Outputs Signals Timing MPC852T Hardware Specifications Rev 3 1 22 Freescale Semiconductor Bus Signal Timing Figure 7 provides the timing for the synchronous input signals CLKOUT EIU Figure 7 Synchronous Input Signals Timing Figure 8 provides normal case timing for input data It also applies to normal read accesses under the control of the UPM in the memory controller CLKOUT ME EE NEM NEN 00 NM Z7 D od XXX 0 XNNX DP 0 3 Figure 8 Input Data Timing in Normal Case MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 23
57. id max prop delay 25 ns M12 MDIO input to MDC rising edge setup 10 ns M13 input to MDC rising edge hold 0 ns MPC852T Hardware Specifications Rev 3 1 58 Freescale Semiconductor FEC Electrical Characteristics Table 28 MII Serial Management Channel Timing continued Num Characteristic Min Max Unit M14 pulse width high 40 60 MII MDC period M15 MDC pulse width low 4096 60 MII MDC period Figure 61 shows the MII serial management channel timing diagram M14 gt MM15 MII MDC output M10 MDIO output M11 MII MDIO input ZES 1 M12 Figure 61 MII Serial Management Channel Timing Diagram MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 59 Mechanical Data and Ordering Information 16 Mechanical Data and Ordering Information Table 29 identifies the packages and operating frequencies orderable for the MPC852T Table 29 MPC852T Package Frequency Orderable Package Type Temperature Tj Frequency MHz Order Number Plastic ball grid array 0 C to 95 C 50 MPC852TVR50 VR and ZT suffix MPC852TZT50 66 MPC852TVR66 MPC852TZT66 80 MPC852TVR80 MPC852TZT80 100 MPC852TVR100 MPC852TZT100 Plastic ball grid array 40 C to 100 C 66 TBD CVR suffix 16 1 Pin Assignments The following sections give the pinout an
58. id GPCM write access TRLX 0 CSNT 1 ACS 10 ACS 11 EBDF 1 MIN 0 375 x B1 3 00 B30d WE 0 3 BS_B 0 3 negated to A 0 31 38 67 31 38 24 50 17 83 ns BADDR 28 30 invalid GPCM write access TRLX 1 CSNT 1 CS negated to A 0 31 invalid GPCM write access TRLX 1 1 ACS 10 or 11 EBDF 1 B31 CLKOUT falling edge to CS valid as 1 50 6 00 1 50 6 00 1 50 6 00 1 50 600 ns requested by control bit CST4 in the corresponding word in the MAX 0 00 X B1 6 00 B31a CLKOUT falling edge to CS valid as 7 60 14 30 6 30 13 00 5 00 11 80 3 80 10 50 ns requested by control bit CST1 in the corresponding word in the UPM MAX 0 25 x B1 6 80 B31b CLKOUT rising edge to CS valid as requested 1 50 8 00 1 50 8 00 1 50 8 00 1 50 8 00 ns by control bit CST2 in the corresponding word in the UPM MAX 0 00 x B1 8 00 B31c CLKOUT rising edge to CS valid as requested 7 60 13 80 6 30 12 50 5 00 11 30 3 80 10 00 ns by control bit CST3 in the corresponding word in the UPM MAX 0 25 x B1 6 30 B31d CLKOUT falling edge to CS valid as requested 13 30 18 00 11 30 16 00 9 40 14 10 7 60 12 30 ns by control bit CST1 in the corresponding word in the UPM EBDF 1 MAX 0 375 x B1 6 6 B32 CLKOUT falling edge to BS valid as requested 1 50 6 00 1 50 6 00 1 50
59. iego 1999 pp 212 220 9 Power Supply and Power Sequencing This section provides design considerations for the MPC852T power supply The MPC852T has a core voltage Vppi and PLL voltage Vppsyn that operates at a lower voltage than the I O voltage Vppy The I O section of the MPC852T is supplied with 3 3 V across and Vss GND The signal PA 0 3 PA 8 11 PB15 PB 24 25 PB 28 31 PC 4 7 PC 12 13 PC15 PD 3 15 TDI TDO TCK TMS MII TXEN MII_MDIO are 5 V tolerant All inputs cannot be more than 2 5 V greater than Vppg In addition 5 V tolerant pins can not exceed 5 5 V and remaining input pins cannot exceed 3 465 V This restriction applies to power on reset or power down and normal operation MPC852T Hardware Specifications Rev 3 1 10 Freescale Semiconductor Mandatory Reset Configurations One consequence of multiple power supplies is that when power is initially applied the voltage rails ramp up at different rates The rates depend on the nature of the power supply the type of load on each power supply and the manner in which different voltages are derived The following restrictions apply Vppr must not exceed Vppy during power on reset or power down Vppr must not exceed 1 9 V and Vppy must not exceed 3 465 These cautions are necessary for the long term reliability of the part If they are violated the electrostatic discharge ESD protection diodes are forward biased and excessive
60. in Max Core 40 50 40 66 67 40 80 40 100 Freq Bus Freq 20 25 20 33 33 20 40 20 50 2 1 Table 9 provides the bus operation timing for the MPC852T at 33 40 50 and 66 MHz The timing for the MPC852T bus shown assumes a 50 pF load for maximum delays and a 0 pF load for minimum delays CLKOUT assumes a 100 pF load maximum delay Table 9 Bus Operation Timings 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B1 Bus period CLKOUT See Table 7 ns Bia EXTCLK to CLKOUT phase skew If CLKOUT 2 2 2 2 2 2 2 2 ns is an integer multiple of EXTCLK then the rising edge of EXTCLK is aligned with the rising edge of CLKOUT For a non integer multiple of EXTCLK this synchronization is lost and the rising edges of EXTCLK and CLKOUT have a continuously varying phase skew Bib CLKOUT frequency jitter peak to peak 1 1 1 1 ns Bic Frequency jitter on EXTCLK 0 50 0 50 0 50 0 50 96 MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 13 Bus Signal Timing Table 9 Bus Operation Timings continued 33 MHz 40 MHz 50 MHz 66 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max Bid CLKOUT phase jitter peak to peak 4 4 4 4 ns for OSCLK gt 15 MHz CLKOUT phase jitter peak to peak 5 5 5 5 ns for
61. nction to Case Thermal Resistance Historically the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance Rosa Roc Reca where Roya junction to ambient thermal resistance C W junction to case thermal resistance C W Roca case to ambient thermal resistance C W Rgjc is device related and cannot be influenced by the user The user adjusts the thermal environment to affect the case to ambient thermal resistance For instance the user can change the air flow around the device add a heat sink change the mounting arrangement on the printed circuit board or change the thermal dissipation on the printed circuit board surrounding the device This thermal model is most useful for ceramic packages with heat sinks where some 90 of the heat flows through the case and the heat sink to the ambient environment For most packages a better model is required T 3 Estimation with Junction to Board Thermal Resistance A simple package thermal model that has demonstrated reasonable accuracy about 20 is a two resistor model consisting of a junction to board and a junction to case thermal resistance The junction to case covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package The junction to board thermal resistance describes the thermal performance when most of the
62. nput Vsssyn N4 PLL analog GND Vsssyni P3 PLL analog GND VDDSYN P2 PLL analog Vpp GND G6 G7 G8 G9 G10 G11 H6 H7 H8 H9 H10 H11 J6 J7 J8 J9 Power J10 J11 K6 K7 K8 K9 K10 K11 VDDL A7 C1 D16 G15 L4 M2 R1 M15 T8 Power VDDH F5 F6 F7 F8 F9 F10 F11 F12 G5 G12 H5 H12 J5 J12 Power K5 K12 L5 L6 L7 L8 L9 L10 L11 L12 N C A1 A16 B16 C15 D14 E12 L13 M4 P15 R16 T1 T16 No connect MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 67 Mechanical Data and Ordering Information 16 1 2 The non JEDEC Pinout Figure 63 shows the non JEDEC pinout of the PBGA package as viewed from the top surface For additional information see the MPC666 PowerQUICC Family User s Manual NOTE This figure shows the top view of the device CS7 GPL A2 WE2 BS A0 VppL CE2 AGPL A3 WES3 MII CRSBS A3 4 CS3 CS5 GPL AO WE1 BS A2 CS2 56 WEO BS A1 O O TEA GPL 5 _ 1 CS4 15121 O 4 N o gt gt Oo R30 HRESET P2 RSTCONF R29 BADDR28 SRESET O LK WAIT A VSSSYN 5 CLI lt o T 0000 000000 000000 000000 000000 000000 900006 gt a gt o c Ds o E gt 2 2 U e c E a Jg 5 a g g RI 2 S SSSYN1DPO DP1 D31 g m g m
63. ore 4 Kbyte Unit Unit Bus Data Cache Data MMU 32 Entry DTLB System Functions PCMCIA ATA Interface Fast Ethernet Controller Interrupt 1 Virtual Controllers Dual Port RAM IDMA 10 100 32 Bit RISC Controller 8 Se ial Base T 2 Baud Rate VA Parallel I O Media Access Generators and Program DMA Control ROM Channels Timers Serial Interface NMSI Figure 1 MPC852T Block Diagram MPC852T Hardware Specifications Rev 3 1 4 Freescale Semiconductor 3 Maximum Tolerated Ratings Maximum Tolerated Ratings This section provides the maximum tolerated voltage and temperature ranges for the MPC852T Table 1 provides the maximum ratings and operating temperatures Table 1 Maximum Tolerated Ratings Rating Symbol Value Unit Supply voltage core 0 3 to 3 4 V voltage Vppg I O voltage 0 3 to 4 VDDSYN 0 3 to 3 4 Difference 100 mV between Vpp to VDDSYN Input voltage Vin GND 0 3 to VppH V Storage temperature range Tstg 5510 150 1 The power supply of the device must start its ramp from 0 0 V Functional operating conditions are provided with the DC electrical specifications in Table 5 Absolute maximum ratings are stress ratings only functional operation at the maxima is not guaranteed Stresses beyond those listed may affect device reliability or cause permanent damage to the d
64. rcuit PC trace interconnection length should be minimized to minimize undershoot and reflections that these fast output switching times cause This recommendation particularly applies to the address and data buses Maximum PC trace lengths of six inches are recommended Capacitance calculations should consider all device loads as well as parasitic capacitances that the PC traces cause Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the Vpp and GND circuits Pull up all unused inputs or signals that are inputs during reset Special care should be taken to minimize the noise levels on the PLL MPC852T Hardware Specifications Rev 3 1 12 Freescale Semiconductor Bus Signal Timing supply pins For more information please refer to MPC866 User s Manual Section 14 4 3 Clock Synthesizer Power Vppsyn Vsssy VsssYyNU 12 Bus Signal Timing The maximum bus speed that the MPC852T supports is 66 MHz Table 7 shows the frequency ranges for standard part frequencies Table 7 Frequency Ranges for Standard Part Frequencies 1 1 Bus Mode rant 50MHz 66MHz Freq Min Max Min Max Core 40 50 40 66 67 Freq Bus Freq 40 50 40 66 67 Table 8 Frequency Ranges for Standard Part Frequencies 2 1 Bus Mode Pan 50MHz 66MHz 80MHz 100MHz Freq Min Max Min Max Min Max M
65. show that TRLX can be 0 or 1 1 7 5 2003 Changed the SPI Master Timing Specs 162 and 164 1 6 4 2003 Changed the package drawing in Figure 15 63 1 5 4 2003 Changed 5 Port C pins with interrupt capability to 7 Port C pins Added the Note solder sphere composition for MPC852TVR and MPC852TCVR devices is 95 5 Sn 45 Ag 0 5 Cu to Figure 15 63 1 4 2 2003 Changed Table 15 30 Pin Assignments for the PLL Pins Vsssyn1 Vsssyn 1 3 1 2003 Added subscripts to timing diagrams for B1 B35 to specify memory controller settings for the specific edges 1 2 1 2003 In Table 15 30 specified EXTCLK as 3 3 V 1 1 12 2002 Added fast Ethernet controller to the features 1 11 2002 Added values for 80 and 100 MHz 0 10 2002 Initial release MPC852T Hardware Specifications Rev 3 1 78 Freescale Semiconductor Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 79 How to Reach Us Home Page www freescale com email support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 800 521 6274 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46
66. ter Configuration Field cna HRCW HRCW DBGC 1 Hardware reset configuration word SIUMCR SIUMCR DBGC X1 SIU module configuration register MBMR MBMR GPLB4DIS 0 Machine B mode register PAPAR PAPAR 4 7 0 Port A pin assignment register PAPAR 12 15 PADIR PADIR 4 7 1 Port A Data Direction Register PADIR 12 15 PBPAR PBPAR 14 0 Port B Pin Assignment Register PBPAR 16 23 PBPAR 26 27 PBDIR PBDIR 14 1 Port B Data Direction Register PBDIR 16 23 PBDIR 26 27 PCPAR PCPAR 8 11 0 Port C Pin Assignment Register PCDIR 14 PCDIR PCDIR 8 11 1 Port C Data Direction Register PCDIR 14 11 Layout Practices Each Vpp pin on the MPC852T should be provided with a low impedance path to the board s supply Each GND pin should likewise be provided with a low impedance path to ground The power supply pins drive distinct groups of logic on chip The Vpp power supply should be bypassed to ground using at least four 0 1 uF by pass capacitors located as close as possible to the four sides of the package Each board designed should be characterized and additional appropriate decoupling capacitors should be used if required The capacitor leads and associated printed circuit traces connecting to chip Vpp and GND should be kept to less than half an inch per capacitor lead At a minimum a four layer board employing two inner layers as Vpp and GND planes should be used All output pins on the MPC852T have fast rise and fall times Printed ci
67. tor Inc 2004 All rights reserved oo e ee e RU KY MPC852TEC Rev 3 1 01 2005 Contents s 1 sa ies heo D ea E aD o Meigs 2 Maximum Tolerated Ratings 5 Thermal Characteristics 5 Power Dissipation 00 greinni 6 DC Characteristics css sgr denori ciate a 7 Thermal Calculation and Measurement 8 References eds aq mg 10 Power Supply and Power Sequencing 10 Mandatory Reset Configurations 11 Layout Practices sos wine ener cca vA Rr ee 12 Bus Signal Timing 555 13 IEEE 1149 1 Electrical Specifications 41 CPM Electrical Characteristics 43 FEC Electrical Characteristics 56 Mechanical Data and Ordering Information 60 Document Revision History 78 2 freescale semiconductor Features 2 Features The MPC852T is comprised of three modules that each use the 32 bit internal bus the MPC8xx core the system integration unit SIU and the communication processor module CPM Figure 1 shows the MPC852T block diagram The following list summarizes the key MPC852T features e Embedded MPC8xx core up to 100 MHz e Maximum frequency operation of the external bus is 66 MHz Th
68. us Weak Drive during Configuration MPC852T Hardware Specifications Rev 3 1 40 Freescale Semiconductor IEEE 1149 1 Electrical Specifications Figure 34 provides the reset timing for the debug port configuration SRESET DSCK DSDI Figure 34 Reset Timing Debug Port Configuration 13 IEEE 1149 1 Electrical Specifications Table 15 provides the JTAG timings for the MPC852T shown in Figure 35 through Figure 38 Table 15 JTAG Timing All Frequencies Num Characteristic Unit Min Max J82 cycle time 100 00 ns J83 TCK clock pulse width measured at 1 5 V 40 00 ns J84 TCK rise and fall times 0 00 10 00 ns J85 TMS TDI data setup time 5 00 ns J86 TMS TDI data hold time 25 00 ns J87 TCK low to TDO data valid 27 00 ns J88 TCK low to TDO data invalid 0 00 ns J89 TCK low to TDO high impedance 20 00 ns J90 TRST assert time 100 00 ns J91 TRST setup time to TCK low 40 00 ns J92 TCK falling edge to output valid 50 00 ns J93 TCK falling edge to output valid out of high impedance 50 00 ns J94 TCK falling edge to output high impedance 50 00 ns J95 Boundary scan input valid to TCK rising edge 50 00 ns J96 TCK rising edge to boundary scan input invalid 50 00 ns MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 41 IEEE 1149 1 Electrical Specifications
69. ut BS B1 IOWR WE2 A5 Output BS B2 PCOE WE3 B5 Output BS_B3 PCWE BS A 0 3 A6 D7 C7 B7 Output GPL A0 C5 Output GPL BO OE D5 Output GPL A1 GPL B1 GPL A 2 3 A4 B4 Output GPL B 2 3 CS 2 3 UPWAITA C2 Bidirectional 3 3V only GPL_A4 GPL_A5 E4 Output PORESET P1 Input 3 3V only RSTCONF K4 Input 3 3V only HRESET J4 Open drain MPC852T Hardware Specifications Rev 3 1 Freescale Semiconductor 63 Mechanical Data and Ordering Information Table 30 Pin Assignments JEDEC Standard continued Name Pin Number Type SRESET M3 Open drain XTAL N1 Analog Output EXTAL M1 Analog Input 1 8V only CLKOUT N6 Output EXTCLK N2 Input 1 8V only ALE_A H1 Output CE1 A E5 Output CE2 A B3 Output WAIT A N3 Input 3 3V only IP T2 Input 3 3V only IP A1 M6 Input 3 3V only IP A2 R3 Input 3 3V only IOIS16 A IP A3 M5 Input 3 3V only IP A4 T3 Input 3 3V only IP A5 N5 Input 3 3V only IP A6 M7 Input 3 3V only IP A7 R2 Input 3 3V only DSCK H2 Bidirectional Three state 3 3V only IWP 0 1 H3 G1 Bidirectional 3 3V only VFLS 0 1 K1 Bidirectional 3 3V only OP1 K2 Output OP2 K3 Bidirectional 3 3V only MODCK1 STS OP3 L1 Bidirectional 3 3V only MODCK2 DSDO BADDR 28 29 L3 L2 Output BADDR30 J3 Output REG AS J2 Input 3 3V only PA11 E16 Bidirectional R
70. yer board 1s Rauma 41 Four layer board 2s2p Reyma 29 Junction to board 4 Rous 24 Junction to case Rouc 13 Junction to package top 9 Natural convection Yor 3 Air flow 200 ft min 2 1 Junction temperature is a function of on chip power dissipation package thermal resistance mounting site board temperature ambient temperature air flow power dissipation of other components on the board and board thermal resistance Per SEMI G38 87 and JEDEC JESD51 2 with the single layer board horizontal 3 Per JEDEC JESD51 6 with the board horizontal Thermal resistance between the die and the printed circuit board per JEDEC JESD51 8 Board temperature is measured on the top surface of the board near the package 5 Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method MIL SPEC 883 Method 1012 1 with the cold plate temperature used for the case temperature For exposed pad packages where the pad would be expected to be soldered junction to case thermal resistance is a simulated value from the junction to the exposed pad without contact resistance 6 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51 2 5 Power Dissipation Table 4 provides power dissipation information The modes are 1 1 where CPU and bus speeds are equal and 2 1 mode where CPU frequency is

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