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H8 5XX Programming

1. In assembly language coding it is usually not necessary to specify the general or special format by coding G etc If the format specification is omitted the assembler automatically generates the optimum object code If a format is specified the assembler follows the format specification 2 2 14 DADD Decimal ADD with extend carry Decimal ADD with extend carry DADD lt Operation gt lt Condition Code gt Rd 10 Rs 10 C gt Rd 10 N Z V C li 3 lt Assembly Language Format gt Sass N Previous value remains unchanged DADD Rs Rd Z Set to 1 if the previous Z bit value Example was 1 and the result of the instruction DADD RO R1 is zero otherwise cleared to 0 lt 3 Previous value remains unchanged lt Operand Size gt Byte C Set to 1 if a decimal carry occurs otherwise cleared to 0 lt Description gt This instruction adds the contents of a general register source operand and the C bit to the contents of a general register destination operand as decimal numbers and places the result in the destination register Correct results are not assured if word size is specified lt Instruction Format gt 1 0 100 rr r O 0 000 0 O0 0 1 0 100 hirm lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Destination Yes _ Za ane 2 2 15 DIVXU DIVide eXtend a
2. a Destination Yes Z a T MOV F Rs d 8 R6 Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Destination Yes i E z _ This instruction can specify R6 FP only 2 2 24 4 MOV I MOVe data I short format MOVe Immediate word MOV I lt Operation gt lt Condition Code gt IMM gt Rd Z V C N Acme N Set to 1 when the value moved is lt Assembly Language Format gt MOV 1 xx 16 Rd Example 1 MOV I H FFOO RS 2 MOV W H FF00 R5 negative otherwise cleared to 0 Z Set to 1 when the value moved is zero otherwise cleared to 0 lt Always cleared to 0 C Previous value remains unchanged lt Operand Size gt Word lt Description gt This instruction moves one word of immediate data to a general register and sets or clears the N and Z bits according to the data value This instruction is a short form of the MOV instruction Compared with the general form MOV G xx 16 Rd its object code is one byte shorter lt Instruction Format gt 01 01iirrr data H data L lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Destination Yes Tn assembly language coding it is usually not necessary to specify the general or special format by coding G etc If the forma
3. Branch conditionally lt Mnemonic and Condition Field gt Mnemonic BRA BRN BHI BLS BCC BCS BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE BT BF BHS BLO cc field 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bee Description Always True Never False High Low or Same Carry Clear High or Same Carry Set Low Not Equal Equal Overflow Clear Overflow Set Plus Minus Greater or Equal Less Than Greater Than Less or Equal Condition True False Cv Z 0 CvZ 1 C 0 ZA lt lt NNO II Or O m OF N V 0 N V 1 ZvV N V 0 ZV N V 1 2 2 7 BCLR Bit test and CLeaR Bit test and CLeaR lt Operation gt lt bit No gt of lt EAd gt gt Z 0 gt lt bit No gt of lt EAd gt lt Assembly Language Format gt BCLR xxX lt EAd gt BCLR Rs lt EAd gt Example BCLR B 7 H FFOO lt Operand Size gt Byte Word lt Description gt BCLR lt Condition Code gt N Previous value remains unchanged Z Set to 1 if the value of the bit tested was zero Otherwise cleared to 0 V Previous value remains unchanged C Previous value remains unchanged This instruction tests a specified bit in the destination operand sets or clears the Z bit according to the result then clears the specified bit to 0 The bit number 0 to 15 can be specified directly using immediate data or can be place
4. H 0021 H 0022 H 0023 H 0024 H 0025 H 0026 H 0027 H 0028 H 0029 H 002A H 002B H 002C H 002D H 002E H 002F Maximum mode H 0040 H 0043 H 0044 H 0047 H 0048 H 004B H 004C H 004F H 0050 H 0053 H 0054 H 0057 H 0058 H 005B H 005C H 005F TRAPA 8 9 10 11 12 13 14 15 A 4 bit number from 0 to 15 specifying an exception vector number acording to the table below VE Vector address C inimum mode H 0030 H 0031 H 0032 H 0033 H 0034 H 0035 H 0036 H 0037 H 0038 H 0039 H 003A H 003B H 003C H 003D H 003E H 003F Maximum mode H 0060 H 0063 H 0064 H 0067 H 0068 H 006B H 006C H 006F H 0070 H 0073 H 0074 H 0077 H 0078 H 007B H 007C H 007F 2 2 58 TRAP VS TRAP if oVerflow TRAP if oVerflow bit is Set lt Operation gt If V bit is set then TRAP else next lt Assembly Language Format gt TRAP VS Example TRAP VS lt Operand Size gt lt Description gt TRAP VS lt Condition Code gt N Previous value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged When this instruction is executed the CPU checks the CCR condition code register and initiates exception handling if the V bit is set to 1 If the V bit is cleared execution proceeds to the next instruction without an exception
5. The vector address of the exception generated by a TRAP VS instruction is shown below H 0008 H 0009 H 0010 H 0013 lt Instruction Format gt 00001 00 1 2 2 59 TST TeST TeST TST lt Operation gt lt Condition Code gt Set CCR according to result of EAd 0 Z V C N CIENTES N Set to 1 when the result is negative lt Assembly Language Format gt TST lt EAd gt Example TST H 1000 R1 otherwise cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 lt Al leared to 0 lt Operand Size gt ways cleared to 0 Byte Word C Always cleared to 0 lt Description gt This instruction compares the destination operand general register Rd or memory contents with 0 and sets the condition code register according to the result It does not modify the destination operand lt Instruction Format gt ee lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes Yes Yes Yes Yes Yes Yes 2 2 60 UNLK UNLinK UNLinK lt Operation gt FP R6 gt SP SP gt FP R6 lt Assembly Language Format gt UNLK FP Example UNLK FP lt Operand Size gt lt Description gt UNLK lt Condition Code gt N Previous value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged This instruction deallocates a stac
6. lt Operand Size gt C Set to the value shifted out from the Byte ie ee most significant bit Word lt Description gt This instruction rotates the destination operand general register Rd or memory contents left and sets the C bit to the value rotated out from the most significant bit MSB LSB lt Instruction Format gt lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes Yes Yes Yes Yes Yes Yes 2 2 38 ROTR ROTate Right ROTate Right ROTR lt Operation gt lt Condition Code gt EAd rotated right EAd Z V N C Fes aS N Set to 1 when the result is negative lt Assembly Language Format gt ROTR lt EAd gt Example otherwise cleared to 0 ROTR B R1 Z Set to 1 when the result is zero otherwise cleared to 0 lt Always cleared to 0 lt Operand Size gt C Set to the value shifted out from the Byte tee errr east significant bit Word lt Description gt This instruction rotates the destination operand general register Rd or memory contents right and sets the C bit to the value rotated out from the least significant bit MSB LSB lt Instruction Format gt oo EA o oooiinon lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes Yes Yes Yes Yes Yes Yes 2 2 39 ROTXL ROTate with eXtend carry Left ROTate with eXtend carry Left ROTXL lt Op
7. C Receives the value shifted out from the least significant bit lt Description gt This instruction rotates the destination operand general register Rd or memory contents right through the C bit The most significant bit of the destination operand receives the old value of the C bit The least significant bit is rotated to become the new value of the C bit MSB LSB ee si lt Instruction Format gt lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes Yes Yes Yes Yes Yes Yes 2 2 41 RTD ReTurn and Deallocate ReTurn and Deallocate lt Operation gt SP PC SP IMM SP lt Assembly Language Format gt RID xx Example RTD 4 lt Operand Size gt lt Description gt RTD lt Condition Code gt Z V C N N Previous value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged This instruction is used to return from a subroutine in the same page and deallocate the stack area used by the subroutine It pops the program counter PC from the stack then adjusts the stack pointer by adding immediate data specified in the instruction The immediate data value can be an 8 bit value from 128 to 127 or a 16 bit value from 32768 to 32767 Note When the stack is accessed an address error will occur if the stack pointer indicates an odd address
8. LINK FP UNLK FP n gt MOV W FP SP MOV W SP FP ADDS W n SP providing an n byte local variable area MOV W FP OP MOV W SP FP An example of the usage of these instructions in a C language program is shown below The program contains a function swap that uses two work variables temp 1 and temp2 to exchange the and d contents of four variables a Before swap is executed After swap is executed The coding in C language is int a Dr swap int templ t templ temp2 a b c d by Cy emp2 aj b d C temp2 templ Global variablesa b c d Accessible anywhere in the program Always present in memory Local variables temp1 temp2 Usable only in the swap function Present in memory only when the swap function is called LINK stack LINK lt Note Continued gt An assembly language coding of the swap function is Swap LINK FP 4 See on next page MOV a RO gt templ a MOV RO 2 FP MOV b RO gt temp2 b MOV RO 4 FP MOV d RO gt a d MOV RO a MOV c RO gt b C MOV RO b MOV 4 FP RO gt c temp2 MOV RO c MOV 2 FP RO gt d templ MOV RO d UNLK FP See on next page RTS See on next page LINK stack LINK lt Note Continued gt A map of the stack area in memory at various stages in this rout
9. This instruction obtains the logical exclusive OR of the source operand and the contents of general register Rd destination operand and places the result in general register Rd lt Instruction Format gt lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Destination Yes _ S 2 2 63 XORC eXclusive OR Control register eXclusive OR Control register XORC lt Operation gt lt Condition Code gt CR IMM gt CR Z V lt Assembly Language Format gt XORC xx CR Example XORC B H 01 CCR 1 When CR is the status register SR or CCR the N Z V and C bits are set according to the result of the operation 2 When CR is not the status register EP TP DP or BR the bits are set as below N Set to 1 when the MSB of the result is 1 otherwise cleared to 0 lt Operand Size gt Byte Word Z Set to 1 when the result is zero otherwise Depends on the control register cleared to 0 V Always cleared to 0 C Previous value remains unchanged lt Description gt This instruction exclusive ORs the contents of a control register CR with immediate data and places the result in the control register The operand size specified in the instruction depends on the control register as indicated in Table 1 12 in Section 1 3 6 Register Specification Interrupts are not accepted and trace exception pro
10. MOV E for xx 8 and MOV I for xx 16 Tn assembly language coding it is usually not necessary to specify the general or special format by coding G etc If the format specification is omitted the assembler automatically generates the optimum object code If a format is specified the assembler follows the format specification MOVe data from source to destination MOV G lt Instruction Format gt MOV G lt EAs gt Rd Za 100dOrrr l Ea 00000111 data H data L MOV G xx lt EAd gt Notes 1 The d bit indicates the direction of the transfer load if d 0 store if d 1 When d 1 the lt EA gt field cannot contain immediate data or specify a register 2 The lt EA gt field cannot contain immediate data or specify a register 3 Ifthe immediate data length is 8 bits but word size is specified in the lt EA gt field the sign bit of the immediate data is extended and 16 bits of data are transferred lt Addressing Modes gt MOV G Rs lt EAd gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Destination Yes Yes Yes Yes Yes Yes Yes MOV G xx lt EAd gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes Destination Yes Yes Yes Yes Yes Yes Yes MOV G lt EAs gt Rd Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes Yes Yes Yes Y
11. MOVe From Peripheral with E clock MOVFPE lt Operation gt lt Condition Code gt EAs gt Rd N Z V C Synchronized with E clock Sla lt Assembly Language Format gt N Previous value remains unchanged Z Previous value remains unchanged MOVFPE lt EAs gt Rd Example MOVFPE H FO00 RO V Previous value remains unchanged C Previous value remains unchanged lt Operand Size gt Byte lt Description gt This instruction transfers data from a source operand to a general register in synchronization with the E clock The operand must be byte size Correct results are not guaranteed if word size is specified Note This instruction should not be used with chips that do not have an E clock output pin Example the H8 520 lt Instruction Format gt o EA y y Joooooooojrioo0o0orrr lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes Yes Yes Yes Yes Yes Destination Yes gt na ne a ii be 2 2 26 MOVTPE MOVe To Peripheral with E clock MOVe To Peripheral with E clock MOVTPE lt Operation gt lt Condition Code gt Rs gt EAd N ZV C Synchronized with E clock Sla lt Assembly Language Format gt N Previous value remains unchanged Z Previous value remains unchanged MOVTPE Rs lt EAd gt Example MOVTPE R0 R1 V Previous value remains unchanged C Previous value remains unchanged lt Operand Size gt Byte
12. NEG CLR TAS Logical AND operations OR XOR NOT Size B B W B W B W B W B W B W B W Function 0 gt lt bits 15 to 8 gt of lt Rd gt Converts byte data in a general register to word data by padding with zero bits EAd 0 Compares general register or memory contents with 0 0 EAd gt EAd Obtains the two s complement of general register or memory contents 0 gt EAd Clears general register or memory contents to 0 EAd 0 1 2 gt lt bit 7 gt of lt EAd gt Tests general register or memory contents then sets the most significant bit bit 7 to 1 Rd a EAs gt Rd Performs a logical AND operation on a general register and another general register memory or immediate data Rd v EAs gt Rd Performs a logical OR operation on a general register and another general register memory or immediate data Rd EAs gt Rd Performs a logical exclusive OR operation on a general register and another general register memory or immediate data EAd EAd Obtains the one s complement of general register or memory contents Table 1 7 Instructions Listed by Function 4 Instruction Shift SHAL operations SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Bit BSET manipulations BCLR BNOT BIST Size B W B W B W B W B W B W B W B W B W B W B W B W Function EAd shift EAd Performs an arithmetic shift o
13. The immediate data should be an even number so that the stack pointer indicates an even address after execution of the RTD instruction lt Instruction Format gt RTD xx 16 0 0 011 1 0 0 data H data L ReTurn and Deallocate RTD lt Note gt The RTD instruction works efficiently with programs coded in high level languages that use function routines Besides returning from a function call it can deallocate an argument area used by the function The RTD instruction can be broken down into more general instructions as follows RTD n gt RTS ADDS W n SP where n is the size of the argument area The usage of the RTD instruction in a program coded in C language is illustrated below Sample program main int a b a 10 b func a Function call with argument a func x int x function processing In assembly language this program could be coded as follows main MOV I 10 RO MOV RO SP Pass argument to function via stack JSR func func MOV 2 SP RO Get argument a function processing RTD 2 Return and deallocate argument area ReTurn and Deallocate RTD lt Note Continued gt The stack area during and after the function call is shown below Stack Stack Return PC SP gt Duringfunc call After RTD The PC is popped as in RTS then the stack pointer is moved downward to deallocate the argument a In this examp
14. instruction code the register list is encoded as one byte in which bits set to 1 indicate registers to be pushed The highest numbered register in the list is pushed first the next highest numbered register second and so on At the end of this instruction general register R7 the stack pointer is updated to the value contents of R7 before this instruction 2 x number of registers pushed If the register list includes R7 the value pushed is contents of R7 before this instruction 2 lt Instruction Format gt 00010 01 0 register list Register list 7 6 5 4 3 2 1 0 R7 re r5 R4 Rs R2 Rt Ro STore Multiple registers STM lt Note gt The STM instruction can be used to save a group of registers to the stack at the beginning of exception handling routine or a subroutine When there are many registers to save the STM instruction is faster than the MOV instruction The status of the stack before and after an STM instruction is shown below Stack Stack Old RO Old R1 Old R2 Old R3 Old R7 2 SP gt Execution of STM RO R3 R7 SP If R7 the stack pointer is included in the register list the value of R7 pushed on the stack is contents of R7 before the instruction 2 The value of R7 after execution of the instruction is contents of R7 before the instruction 2 x number of registers restored Normally the STM instruction is paired with an LDM instruction which restores th
15. when the result is negative otherwise cleared to 0 EXTS Rd Example Z Set to 1 when the result is zero EXTS RO otherwise cleared to 0 lt Always cleared to 0 Al leared to 0 lt Operand Size gt C ways cleared to Byte lt Description gt This instruction converts byte data in general register Rd destination operand to word data by propagating the sign bit It copies bit 7 of Rd into bits 8 through 15 lt Instruction Format gt 10100 ir r r O0 0010 00 1 lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes s 2 a pe 2 2 18 EXTU EXTend as Unsigned EXTend as Unsigned EXTU lt Operation gt lt Condition Code gt 0 gt lt bits 15 to 8 gt of lt Rd gt N Z V C Zero extension MENEE Always cleared to 0 z lt Assembly Language Format gt Z Set to 1 when the result is zero EXTU Rd Example otherwise cleared to 0 EXTU R1 V Always cleared to 0 C Always cleared to 0 lt Operand Size gt Byte lt Description gt This instruction converts byte data in general register Rd destination register to word data by filling bits 8 to 15 of Rd with zeros lt Instruction Format gt 10100 ir r r jo 0 010 0 1 0 lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes s 2 a pe 2 2 19 JMP JuMP JuMP JMP lt Operation gt lt Condition Code
16. 0 Z Set to 1 when the result is zero otherwise cleared to 0 V Set to 1 when the shift changes the lt Operand Size gt aon value of the most significant bit Byte Word otherwise cleared to 0 C Set to the value shifted out from the most significant bit lt Description gt This instruction shifts the destination operand general register Rd or memory contents left and sets the C bit to the value shifted out from the most significant bit The least significant bit is cleared to 0 lt Instruction Format gt EA JO Ot OOD lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes Yes Yes Yes Yes Yes Yes 2 2 46 SHAR SHift Arithmetic Right SHift Arithmetic Right SHAR lt Operation gt lt Condition Code gt EAd shifted arithmetic right EAd Z V N C Fes aS N Set to 1 when the result is negative lt Assembly Language Format gt SHAR lt EAd gt Example SHAR W H FFOO otherwise cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 lt Always cleared to 0 C Set to the value shifted out from the least significant bit lt Operand Size gt Byte Word lt Description gt This instruction shifts the destination operand general register Rd or memory contents right and sets the C bit to the value shifted out from the least significant bit The most significant bit does not chan
17. 8 Rd 2 2 CMP G B xx 8 Rd 3 3 CMP I xx 16 Rd 3 3 CMP G W xx 16 Rd 4 4 MOV E xx 8 Rd 2 2 MOV G B xx 8 Rd 3 3 MOV 1 xx 16 Rd 3 3 MOV G W xx 16 Rd 4 4 MOV L aa 8 Rd 2 5 MOV G aa 8 Rd 3 5 MOV S Rs aa 8 2 5 MOV G Rs aa 8 3 5 MOV F d 8 R6 Rd 2 5 MOV G d 8 R6 Rd 3 5 MOV F Rs d 8 R6 2 5 MOV G Rs d 8 R6 3 5 Notes The ADD Q instruction accepts other destination operands in addition to a general register but the immediate data value xx is limited to 1 or 2 2 Number of execution states for access to on chip memory For the H8 510 the number of execution states for general register access 1 3 4 Basic Instruction Formats There are two basic CPU instruction formats the general format and the special format 1 General format This format consists of an effective address EA field an effective address extension field and an operation code OP field It is used in arithmetic instructions and other general instructions e Effective address field One byte containing information used to calculate the effective address of an operand e Effective address extension Zero to two bytes containing a displacement value immediate data or an absolute address e Operation code Defines the operation to be carried out on the operand located at the address calculated from the effective address information Each instruction has a unique operation code Fetch direction gt Effective address Effecti
18. H AA R3 2 CMP B H AA R3 lt Operand Size gt Byte Word lt Description gt CMP G lt Condition Code gt Z V C N Set to 1 when the result is negative F otherwise cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 V Set to 1 if an overflow occurs otherwise cleared to 0 C Set to 1 if a borrow occurs otherwise cleared to 0 This instruction subtracts the source operand from the destination operand and sets or clears the condition code CCR according to the result It does not alter the destination operand The CMP instruction also has short formats CMP E and CMP J that can be used to compare a general register with immediate data lt Instruction Format gt Ea f 00000101 data H data L CMP lt EAs gt Rd EA 01110rrr The length of the immediate data depends on the size Sz specified for the first operation code one byte when Sz 0 one word when Sz 1 Tn assembly language coding it is usually not necessary to specify the general or special format by coding G etc If the format specification is omitted the assembler automatically generates the optimum object code If a format is specified the assembler follows the format specification CoMPare CMP G lt Addressing Modes gt CMP xx lt EAd gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes Destinati
19. It pops the program counter PC from the stack Execution continues from the new PC address This instruction can be used to return from a subroutine called by the BSR or JSR instruction lt Instruction Format gt 00011 00 1 2 2 44 SCB Subtract Compare and Branch conditionally Subtract Compare and Branch conditionally SCB lt Operation gt lt Condition Code gt If condition is true then next N Z V C else Rn 1 gt Rn me If Rn 1 then next else PC disp PC N Previous value remains unchanged Z Previous value remains unchanged lt Assembly Language Format gt V Previous value remains unchanged SCB cc Rit disp C Previous value remains unchanged Note F False NE Not Equal or EQ EQual can be specified in the condition code field cc There are accordingly three mnemonics SCB F SCB NE and SCB EQ Example SCB EQ R4 LABEL lt Operand Size gt lt Description gt This instruction is used for loop control The condition code cc field can be set to create a pure counted loop SCB P or a do while or do until SCB NE or SCB EQ loop with a limiting count If the specified condition cc is true this instruction exits the loop by proceeding to the next instruction Otherwise it decrements the counter register Rc and exits the loop if the resultis 1 When it does not exit the loop this instruction branches to a relative address given by an 8 bit displacement value from 128
20. MOV W R3 R1 DIVXU B lt EA gt RI MOV B R1 RO 2 2 16 DSUB Decimal SUBtract with extend carry Decimal SUBtract with extend carry DSUB lt Operation gt lt Condition Code gt Rd 10 Rs 10 C gt Rd 10 N Z V C li 3 lt Assembly Language Format gt DSUB Rs Rd N Previous value remains unchanged Z Set to 1 if the previous Z bit value Example DSUB R2 R3 was 1 and the result of the instruction is zero otherwise cleared to 0 lt 3 Previous value remains unchanged lt Operand Size gt C Set to 1 if a decimal borrow occurs Byte otherwise cleared to 0 lt Description gt This instruction subtracts the contents of general register Rs source operand and the C bit from the contents of general register Rd destination operand as decimal numbers and places the result in general register Rd Correct results are not assured if word size is specified for the operand size lt Instruction Format gt 1 0 100 rr Te 0 0 000 00 0 1 0 1 10 ie tg lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Destination Yes _ Za ane 2 2 17 EXTS EXTend as Signed EXTend as Signed EXTS lt Operation gt lt Condition Code gt lt bit 7 gt of lt Rd gt gt lt bits 15 to 8 gt of lt Rd gt Z V C N Sign extension Ealo lt Assembly Language Format gt N Set to 1
21. Operand Size gt lt Description gt BSR lt Condition Code gt N Previous value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged This instruction branches to a subroutine at a specified address It saves the program counter contents to the stack area then adds a displacement to the program counter and jumps to the resulting address The displacement can be an 8 bit value from 128 to 127 bytes or 16 bit value from 32768 to 32767 bytes However it is not possible to branch across a page boundary This instruction is paired with the RTS instruction to execute a subroutine call The PC value saved to the stack and used in the address calculation is the address of the instruction immediately following this instruction lt Instruction Format gt BSR d 8 o 0 001 414 0 disp BSR d 16 0 0 0 11 11 0 disp H disp L 2 2 11 BTST Bit TeST Bit TeST lt Operation gt lt bit No gt of lt EAd gt gt Z lt Assembly Language Format gt BIST xx lt EAd gt BTST Rs lt EAd gt Example BTST B RO H FO 8 lt Operand Size gt Byte Word lt Description gt BTST lt Condition Code gt N Previous value remains unchanged Z Set to 1 if the value of the bit tested was zero Otherwise cleared to 0 V Previous value remains unchanged C Previous value remains unchanged This instru
22. Yes Yes Yes Yes 2 2 22 LDM LoaD to Multiple registers LoaD to Multiple registers LDM lt Operation gt lt Condition Code gt SP stack Rd register group N Z V C lt Assembly Language Format gt i N Previous value remains unchanged LDM SP lt register list gt Example LDM SP RO R2 R4 Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged lt Operand Size gt Word lt Description gt This instruction restores data saved on the stack to a specified list of general registers In the instruction code the register list is encoded as one byte in which bits set to 1 indicate registers that receive data The first word of data is restored to the lowest numbered register in the list the next word to the next lowest numbered register and so on At the end of this instruction general register R7 the stack pointer is updated to the value contents of R7 before this instruction 2 x number of registers restored lt Instruction Format gt 00 000 010 registerlist Register list 7 6 5 4 3 2 1 0 R7 re r5 R4 3 R2 Rt Ro LoaD to Multiple registers LDM lt Note gt The LDM instruction can be used to restore a group of registers from the stack on return from a subroutine call When there are many registers to restore the LDM instruction is faster than the MOV instruction The status of the stack before an
23. a page boundary lt Instruction Format gt lt Addressing Modes gt JSR aa 16 00011000 JSR Rn 0001000111011 rrr JSR d 8 Rn jooo10001 11101rrr disp JSR d 16 Rn 00010001111119rrr disp H disp L address H address L Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes ee oe O 2 2 21 LDC LoaD to Control register LoaD to Control register LDC lt Operation gt lt Condition Code gt EAs gt CR Z V lt Assembly Language Format gt 1 When CR is the status register SR or CCR the N Z V and C bits are set according to the result of the LDC lt EAs gt CR Example LDC B H 01 DP operation 2 When CR is not the status register EP TP DP or BR the previous value remains unchanged lt Operand Size gt Byte Word Depends on the control register lt Description gt This instruction loads the source operand immediate data or general register or memory contents into a specified control register CR The operand size specified in the instruction depends on the control register as indicated in Table 1 12 in Section 1 3 6 Register Specification Interrupts are not accepted and trace exception processing is not performed immediately after the end of this instruction lt Instruction Format gt ee lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes Yes Yes Yes Yes
24. d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes Yes Yes Yes Yes Yes Yes 2 2 31 OR inclusive OR logical Inclusive logical OR OR lt Operation gt lt Condition Code gt Rd v EAs gt Rd Z V C N slilol N Set to 1 when the result is negative lt Assembly Language Format gt OR lt EAs gt Rd Example OR B H FO 8 R1 otherwise cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 lt Al leared to 0 lt Operand Size gt ways Cleared to Byte Word C Previous value remains unchanged lt Description gt This instruction obtains the logical OR of the source operand and general register Rd destination operand and places the result in general register Rd lt Instruction Format gt lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Destination Yes _ S 2 2 32 ORC OR Control register OR Control register ORC lt Operation gt lt Condition Code gt CR v IMM gt CR Z V C lt Assembly Language Format gt ORC xx CR Example ORC W H 0700 SR 1 When CR is the status register SR or CCR the N Z V and C bits are set according to the result of the operation 2 When CR is not the status register EP TP DP or BR the bits are set as below N Set to 1 when the MSB of the result is 1 otherwise
25. gt ANDC xx 8 CR 00000100 daa lo1011 ccc ANDC xx 16 CRb0001100 data H data L 01011 ccc lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes 2 2 6 Bec Branch conditionally Branch conditionally lt Operation gt If condition is true then PC disp gt PC else next lt Assembly Language Format gt Bcc disp The mnemonic varies depending on the specified condition See lt Mnemonic and Condition Field gt below Example BEQ LABEL lt Operand Size gt lt Description gt Bee lt Condition Code gt N Previous value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged If the condition specified in the condition field cc is true the displacement disp is added to the program counter and execution branches to the resulting address If the condition is not true the next instruction is executed The displacement can be an 8 or 16 bit value The corresponding relative branching distances are 128 to 127 bytes and 32768 to 32767 bytes However it is not possible to branch across a page boundary The PC value used in the address calculation is the address of the instruction immediately following this instruction lt Instruction Format gt oo tol ce disp _ TECIE disp H disp L cc Condition field
26. gt Effective address gt PC Z VC N Previous value remains unchanged til lt Assembly Language Format gt JMP lt EA gt Example Z Previous value remains unchanged JMP H 10 R4 V Previous value remains unchanged C Previous value remains unchanged lt Operand Size gt lt Description gt This instruction branches unconditionally to a specified address in the same page It cannot branch across a page boundary lt Instruction Format gt JMP Rn JMP d 8 Rn 00010 001 11100rrr disp JMP d 16 Rn disp H disp L JMP aa 16 address H address L lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes Yes Yes 2 2 20 JSR Jump to SubRoutine Jump to SubRoutine lt Operation gt PC gt SP Effective address PC lt Assembly Language Format gt JSR lt EA gt Example JSR H OFFF R3 lt Operand Size gt lt Description gt JSR lt Condition Code gt Z V C N N Previous value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged This instruction pushes the program counter contents onto the stack then branches to a specified address in the same page The address pushed on the stack is the address of the instruction immediately following this instruction This instruction cannot branch across
27. gt Rd EAs C gt Rd Z V N C N Set to 1 when the result is negative lt Assembly Language Format gt ADDX lt EAs gt Rd Example ADDX B H 20 R4 RO otherwise cleared to 0 Z Set to 1 if the previous Z bit value was 1 and the result of the instruction is zero otherwise cleared to 0 lt Operand Size gt V Set to 1 if an overflow occurs Byte Word otherwise cleared to 0 C Set to 1 if a carry occurs otherwise cleared to 0 lt Description gt This instruction adds the source operand and the C bit to the contents of general register Rd destination operand and places the result in general register Rd lt Instruction Format gt lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Destination Yes _ me _ TE ME 2 2 4 AND AND logical AND logical AND lt Operation gt lt Condition Code gt Rd A EAs gt Rd Z V C N Jo N Set to 1 when the MSB of the result is 1 otherwise cleared to 0 lt Assembly Language Format gt AND lt EAs gt Rd Example Z Set to 1 when the result is zero AND B H F8 8 R1 otherwise cleared to 0 lt Al leared to 0 lt Operand Size gt ways Cleared to Byte Word C Previous value remains unchanged lt Description gt This instruction obtains the logical AND of the source operand a
28. instructions listed by function in Table 1 6 Detailed descriptions are given starting in Section 2 2 1 Table 1 6 Instruction Classification FunctionInstructions Types Data transfer MOV LDM STM XCH SWAP MOVTPE MOVFPE 7 Arithmetic operations ADD SUB ADDS SUBS ADDX SUBX DADD DSUB MULXU DIVXU CMP EXTS EXTU TST NEG CLR 17 TAS Logic operations AND OR XOR NOT Shift SHAL SHAR SHLL SHLR ROTL ROTR ROTXL 8 ROTXR Bit manipulation BSET BCLR BIST BNOT 4 Branch Bcc JMP PJMP BSR JSR PJSR RTS PRTS RTD PRTD SCB F NE EQ 11 System control TRAPA TRAP VS RTE SLEEP LDC STC ANDC ORC XORC NOP LINK UNLK 12 Total 63 Bec is the generic name of the conditional branch instructions 1 3 2 Instructions Listed by Function Tables 1 7 1 to 6 give a concise summary of the instructions in each functional category The notation used in these tables is listed below Operation Notation Rd General register destination Rs General register source Rn General register EAd Destination operand EAs Source operand CCR Condition code register N N negative bit of CCR Z Z zero bit of CCR V V overflow bit of CCR C C carry bit of CCR CR Control register PC Program counter CP Code page register SP Stack pointer FP Frame pointer IMM Immediate data disp Displacement Addition Subtra
29. lt Description gt This instruction transfers data from a general register to a destination in synchronization with the E clock The operand must be byte size Correct results are not guaranteed if word size is specified Note This instruction should not be used with chips that do not have an E clock output pin Example the H8 520 lt Instruction Format gt Lon ee ee lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes _ _ Destination Yes Yes Yes Yes Yes Yes Yes 2 2 27 MULXU MULtiply eXtend as Unsigned MULtiply eXtend as Unsigned lt Operation gt Rd x EAs gt Rd lt Assembly Language Format gt MULXU lt EAs gt Rd Example MULXU B RO R1 lt Operand Size gt Byte Word lt Description gt MULXU lt Condition Code gt Z V C N ae Seo 0 N Set to 1 when the result is negative otherwise cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 lt Always cleared to 0 C Always cleared to 0 This instruction multiplies the contents of general register Rd destination operand by a source operand and places the result in general register Rd When byte size is specified for the source operand the 8 bit value in the lower byte of Rd is multiplied by the 8 bit source operand yielding a 16 bit result When word size is specified for the source operand the 16 bit value in Rd
30. operand from general register Rd destination operand and places the result in general register Rd lt Instruction Format gt lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Destination Yes _ S 2 2 53 SUBS SUBtract with Sign extension SUBtract with Sign extension SUBS lt Operation gt lt Condition Code gt Rd EAs gt Rd N Z V C lt Assembly Language Format gt N Previous value remains unchanged SUBS lt EAs gt Rd Example SUBS W 2 R2 Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged lt Operand Size gt Byte Word lt Description gt This instruction subtracts the source operand from the contents of general register Rd destination operand and places the result in general register Rd Differing from the SUB instruction this instruction does not alter the condition code If byte size is specified the sign bit of the source operand is extended The subtraction is performed using the resulting word data General register Rd is always accessed as a word size operand lt Instruction Format gt lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Destination Yes a er _ i NE 2 2 54 SUBX SUBtract with eXtend carry SUBtract
31. register BR Base Register Figure 1 1 Registers in the CPU 1 2 Register Descriptions 1 2 1 General Registers All eight of the 16 bit general registers are functionally alike there is no distinction between data registers and address registers When these registers are accessed as data registers either byte or word size can be selected R6 and R7 in addition to functioning as general registers have special assignments R7 is the stack pointer used implicitly in exception handling and subroutine calls It is also used implicitly by the LDM and STM instructions which load and store multiple registers from to the stack and pre decrement or post increment R7 accordingly R6 functions as a frame pointer High level language compilers use R6 when they use instructions such as LINK and UNLK to reserve or release a stack frame Unused area Stack area Figure 1 2 Stack Pointer SP 1 2 2 Control Registers The control registers CR include a 16 bit program counter PC a 16 bit status register SR containing an 8 bit condition code register CCR four 8 bit page registers and one 8 bit base register BR The page registers are used only in the maximum mode They are ignored in the minimum mode 1 Program Counter PC This 16 bit register indicates the address of the next instruction the CPU will execute 2 Status Register Condition Code Register SR CCR This 16 bit register indicates the internal state of th
32. register Rd destination register with the lower eight bits lt Instruction Format gt 104100 rr rf O 0010 00 0 2 2 56 TAS Test And Set Test And Set TAS lt Operation gt lt Condition Code gt Set CCR according to result of EAd 0 Z V C N 1 2 gt lt bit 7 gt of lt EAd gt Ela lo lt Assembly Language Format gt N Set to 1 when the result is negative TAS lt EAd gt Example TAS H FOOO otherwise cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 lt Always cleared to 0 Al leared to 0 lt Operand Size gt C ways cleared to Byte lt Description gt This instruction tests a destination operand general register Rd or memory contents by comparing it with 0 sets the condition code register according to the result then sets the most significant bit of the operand to 1 lt Instruction Format gt pA to lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes Yes Yes Yes Yes Yes Yes Test And Set TAS lt Note gt Execution of the TAS instruction causes the CPU to perform the read modify write cycle shown below No signal is output to indicate this cycle but at the point between the read and write cycles the CPU will not accept interrupts and will not relinquish the bus If an address error or other exception condition occurs during the read cycle it is not handled until the write cycl
33. to 127 The loop counter register Rc is decremented as a word register The program counter PC value used in address calculation is the address of the instruction immediately following the SCB instruction Mnemonic Description Condition SCB F False SCB NE Not Equal Z 0 SCB EQ Equal Z 1 Subtract Compare and Branch conditionally SCB lt Instruction Format gt scB F o 0000001 10111rrr l disp scB NE 0 000011 0 101114rrr l disp SCB EC O 00 0 C4 alt Ot a Foe Fl isp Subtract Compare and Branch conditionally SCB lt Note gt The general SCB instruction controls a loop with a counter register and the CCR bits as termination conditions The H8 500 provides three SCB instructions SCB F SCB NE and SCB EQ The SCB F instruction can be broken down into the following more general instructions SCB F Rn LOOP gt SUB W 1 Rn CMP W 1 Rn BNE LOOP If a loop count is set in Rn this produces a simple counted loop In the following example the loop is executed 9 1 10 times The final value left in R1 is 10 MOV W 9 RO CLR W R1 LO ADD W 1 R1 Start loop SCB F RO LO End loop The SCB NE instruction can be broken down into the following more general instructions SCB NE Rn LOOP 9 BNE NEXT SUB W 1 Rn CMP W 1 Rn BNE LOOP NEXT In the following example a search for a value other than A is made in a block of the length indicated by general register R3 beginning at the address indi
34. with eXtend carry SUBX lt Operation gt lt Condition Code gt Rd EAs C gt Rd Z V N C N Set to 1 when the result is negative lt Assembly Language Format gt SUBX lt EAs gt Rd Example SUBX W R2 RO otherwise cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 V Set to 1 if an overflow occurs lt Operand Size gt f otherwise cleared to 0 oe C S l ifab Set to 1 if a borrow occurs Word otherwise cleared to 0 lt Description gt This instruction subtracts the source operand contents and the C bit from general register Rd destination operand and places the result in general register Rd lt Instruction Format gt lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Destination Yes _ S 2 2 55 SWAP SWAP register halves SWAP register halves SWAP lt Operation gt lt Condition Code gt Rd upper byte lt gt Rd lower byte Z V C N slilol N Set to 1 when the result is negative lt Assembly Language Format gt SWAP Rd Example otherwise cleared to 0 SWAP RO Z Set to 1 when the result is zero otherwise cleared to 0 lt Al leared to 0 lt Operand Size gt ways cleared to C Previous value remains unchanged Byte lt Description gt This instruction interchanges the upper eight bits of general
35. yO sf tiog Definitions N Rm Z Rm Rm 1 RO C Dm N Rm Z Rm Rm 1 RO C D0 N Rm Z Rm Rm 1 RO C Dm N Rm Z Rm Rm 1 RO C D0 Popped from the stack N Rm Z Rm Rm 1 RO V Dm Dm 1 Dm Dm 1 C Dm N Rm Z Rm Rm 1 RO C D0 N Rm Z Rm Rm 1 RO Table 2 7 Condition Code Changes 4 Instruction N Z SHLR SLEEP STC STM SUB SUBS SUBX SWAP TAS TRAPA TRAP VS TST UNLK XCH XOR XORC 0 gt Definitions Z Rm Rm 1 RO C D0 N Rm Z Rm Rm 1 RO V Sm Dm Rm Sm Dm Rm C Sm Dm Dm Rm Sm Rm N Rm Z Z Rm RO V Sm Dm Rm Sm Dm Rm C Sm Dm Dm Rm Sm Rm N Rm Z Rm Rm 1 RO N Rm Z Rm Rm 1 RO N Rm Z Rm Rm 1 RO N Rm Z Rm Rm 1 RO If CR SR CCR N Z V and C are exclusive ORed with source operand bits 3 to 0 If CR SR CCR N Rm Z Rm Rm 1 RO V 0 C remains unchanged Z is the Z bit before execution 2 6 Instruction Execution Cycles Tables 2 8 1 through 6 list the number of cycles required by the CPU to execute each instruction in each addressing mode The meaning of the symbols in the tables is explained below The values of I J and K are used to calculate the number of execution cycles when off chip memory is accessed for an instruction fetch or operand read write The formulas for these calculations are given next Different formulas are used for the H8 520 532 5
36. 053 12 H 0038 H 0039 H 0070 H 0073 5 H 002A H 002B H 0054 H 0057 13 H 003A H 003B H 0074 H 0077 6 H 002C H 002D H 0058 H 005B 14 H 003C H 003D H 0078 H 007B 7 H 002E H 002F _H 005C H 005F 15 H 003E H 003F _H 007C H 007F Example 1 ADD G B RO RI1 EA field OP field Table 2 1 a 1101Szrrr 0010O0rarara Machine code 11010000 00100001 H D021 Example 2 ADD G W H 11 8 R1 freee EA field OP field Table 2 1 a 0000Sz101 00010001 00100 rarara Machine code 00001101 00010001 00100001 H 0D1121 2 5 Condition Code Changes The changes in the condition code bits occurring after the execution of each CPU instruction are summarized in Tables 2 7 1 to 4 The following notation is used Sm Dm Most significant bit of source operand Most significant bit of destination operand Most significant bit of result Bit n of destination operand Not changed Changed according to the result of the instruction Always cleared to 0 Always set to 1 Handling depends on the operand Instruction N Z V C Definitions ADD Powe 2g ADDS a ADDX tt f t N V Cox Table 2 7 Condition Code Changes 1 Instruction ADD AND ANDC Bcc BCLR BNOT BSET BSR BIST CLR CMP DADD DIVXU N ZV C iid oe Or t Definitions N Rm Z Rm Rm 1 RO V Sm Dm Rm Sm Dm R
37. 15 8 7 0 Byte Rn MSB LSB 15 0 Word Rn MSB LSB 31 16 Rn MSB Upper word Rn 1 Lower word LSB Longword 15 0 For longword data n must be even 0 2 4 or 6 2 Data Formats in Memory Access to word data in memory must always begin at an even address Access to word data starting at an odd address causes an address error Table 1 2 Data Formats in Memory Data type Data format 1 Bit T ai in byte operand macros n 7 65 4 s3 2 1 lo 1 Bit Even address 5 14 13 helai 10 9 8 in word operand Odd address 7 6 s5 4 3 2 i ol a aw Byte Address n MSB LSB Word Even address MSB Upper 8 bits Odd address Lower 8 bits LSB Byte in Even address Undefined data stack Odd address MSB LSB Word in Even address MSB Upper 8 bits stack Odd address Lower 8 bits LSB a oF Note When the stack is accessed in exception processing word access is always performed regardless of the actual data size Similarly when the stack is accessed by an instruction using the R7 or R7 addressing mode word access is performed regardless of the operand size specified in the instruction An address error will therefore occur if the stack pointer indicates an odd address Programs should be constructed so that the stack pointer always indicates an even address 1 1 3 Address Space The CPU has two modes a minimum mode which supports an address space of up to 64K bytes and a maximum mode which supports an
38. 1A H IB H 1D to H 1F H 20 to H 7F H 88 to H 8F H 98 to H 9F H A8 to H AF Table 2 10 Instruction Codes Causing Invalid Instruction Exceptions c Effective address Prefix code Operation code Registeror Rn H 00 H 00 to H OF memory Rn H 10 to H 13 d 8 Rn d 16 Rn H 15 to H 18 Rn Rn H lA H lB aa 8 aa 16 H 1D to H 1F H 20 to H 7F H 88 to H 8F H 98 to H 9F H A8 to H AF The following additional instruction codes are invalid in minimum mode Table 2 10 Instruction Codes Causing Invalid Instruction Exceptions d Operation code Effective address H 03 H 13 H 11 H 14 H 19 H 1C H CO to H CF Section 3 State Transitions The CPU operates in five main states the program execution state exception handling state bus released state reset state and power down state Figure 3 1 shows the transitions among these states Program execution state SLEEP SLEEP instruction instruction with standby Bus released state Sleep mode Exception flag set handling request End of exception handling Interrupt request Exception handling Software standby state NMI 4 mode STBY 1 RES 0 Hardware standby Reset state mode 1 From any state except the hardware standby mode a transition to the reset state occurs whenever RES 0 ooo 2 A transition to the hardware standby mode from any state occurs when STBY 0 In the H8 520 this transition is made by selecting mode 6 at MD 2 to MDo 3 The
39. 34 536 which have an 8 bit external bus and the H8 510 570 which have a 16 bit external bus 2 6 1 Calculation of Instruction Execution States H8 520 H8 532 H8 534 H8 536 One state is one cycle of the system clock If 10MHz then one state 100ns Instruction fetch Operand read write Number of states On chip memory On chip memory general Value in Table 2 8 Value in Table 2 9 register or no operand On chip supporting module Byte Value in Table 2 8 Value in Table 2 9 I or off chip memory 2 Word Value in Table 2 8 Value in Table 2 9 2 I Off chip memory On chip memory general Value in Table 2 8 2 J K register or no operand On chip supporting module Byte Value in Table 2 8 I 2 J K or off chip memory 2 Word Value in Table 2 8 2 1 J K When the instruction is fetched from on chip memory ROM or RAM the number of execution states varies by 1 or 2 depending of whether the instruction is stored at an even or odd address This difference must be noted when software is used for timing and in other cases in which the exact number of states is important 2 If wait states are inserted in access to external memory add the necessary number of cycles 2 6 2 Tables of Instruction Execution Cycles Tables 2 8 1 through 6 should be read as shown below J K Number of instruction fetch cycles Addressing mode I Total number of bytes written and r
40. B W DIVXU B W CMP CMP G B W CMP E B CMP I W EXTS B Function Rd EAs gt Rd EAd IMM gt EAd Performs addition or subtraction on data in two general registers or a general register and memory or on immediate data and data in a general register or memory Rd EAs C gt Rd Performs addition or subtraction with carry or borrow on data in two general registers or a general register and memory or on immediate data and data in a general register Rd 10 Rs 10 C gt Rd 10 Performs decimal addition or subtraction on data in two general registers Rd x EAs gt Rd Performs 8 bit x 8 bit or 16 bit x 16 bit unsigned multiplication on data in a general register and data in another general register or memory or on data in a general register and immediate data Rd EAs gt Rd Performs 16 bit 8 bit or 32 bit 16 bit unsigned division on data in a general register and data in another general register or memory or on data in a general register and immediate data Rd EAs EAd IMM Compares data in a general register with data in another general register or memory or with immediate data or compares immediate data with data in memory lt bit 7 gt of lt Rd gt lt bits 15 to 8 gt of lt Rd gt Converts byte data in a general register to word data by extending the sign bit Table 1 7 Instructions Listed by Function 3 Instruction Arithmetic EXTU operations TST
41. BHS BCS BLO BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE v Logic OR Description Always true Never false High Low or Same Carry Clear Carry Set Low Not Equal Equal Overflow Clear Overflow Set Plus Minus Greater or Equal Less Than Greater Than Less or Equal Condition True False CvZ 0 Cv Z 1 C 0 High or Same C 1 Z Z lt lt NN oll Se Or OF CO N V 0 N V 1 Zv N V 0 ZvV N V 1 Branches unconditionally to a specified address in the same page Branches unconditionally to a specified address in a specified page Branches to a subroutine at a specified address in the same page Branches to a subroutine at a specified address in the same page Branches to a subroutine at a specified address in a specified page Returns from a subroutine in the same page Table 1 7 Instructions Listed by Function 6 Instruction Branch PRTS RTD PRTD SCB F SCB NE SCB EQ System TRAPA control TRAP VS RTE LINK UNLK SLEEP STC ANDC ORC XORC NOP Size B W B W B W B W B W Function Returns from a subroutine in a different page Returns from a subroutine in the same page and adjusts the stack pointer Returns from a subroutine in a different page and adjusts the stack pointer Controls a loop using a loop counter and or a specified CCR termination condition Generates a trap exception with
42. C STore Control register STore Control register lt Operation gt CR gt EAd lt Assembly Language Format gt STC CR lt EAd gt Example STC B BR RO lt Operand Size gt Byte Word Depends on the control register lt Description gt This instruction stores the contents of a control register CR to a general register or memory location destination operand The operand size specified in the instruction depends on the control register as indicated in Table 1 12 in Section 1 3 6 Register Specification lt Instruction Format gt STC lt Condition Code gt N Previous value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes Yes Yes Yes Yes Yes Yes 2 2 51 STM STore Multiple registers STore Multiple registers STM lt Operation gt lt Condition Code gt Rs register group gt SP stack N Z V C lt Assembly Language Format gt STM lt register 1ists sp N Previous value remains unchanged Example STM RO R3 SP Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged lt Operand Size gt Word lt Description gt This instruction pushes data from a specified list of general registers onto the stack In the
43. H8 500 Series Programming Manual Catalog No ADE 602 021 Preface The H8 500 Family of Hitachi original microcontrollers is built around a 16 bit CPU core that offers enhanced speed and a large address space The CPU has a highly orthogonal general register architecture and an optimized instruction set that efficiently executes programs coded in C language This manual describes the H8 500 instructions in detail and is written for use with all chips in the H8 500 Family For information on assembly language coding see the H8 500 Series Cross Assembler User s Manual For details on chip hardware see the hardware manual for the particular chip Section 1 CPU 1 1 Overview The H8 500 CPU is a high speed central processing unit designed for realtime control It can be used as a CPU core in application specific integrated circuits Its Hitachi original architecture features eight 16 bit general registers internal 16 bit data paths and an optimized instruction set Section 1 summarizes the CPU architecture and instruction set 1 1 1 Features The main features of the H8 500 CPU are listed below e General register machine Eight 16 bit general registers Seven control registers two 16 bit registers five 8 bit registers e High speed maximum 10MHz At 1OMHz a register register add operation takes only 200ns e Address space managed in 64K byte pages expandable to 16M bytes Simultaneous control is provided of four pa
44. H8 520 does not support BREQ 4 The H8 570 does not support recovery from software standby by NMI Figure 3 1 State Transitions 3 1 Program Execution State In this state the CPU executes program instructions in normal sequence 3 2 Exception Handling State 3 2 1 Types of Exception Handling and Their Priorities As indicated in Table 3 1 a and b exception handling can be initiated by a reset address error trace interrupt or instruction An instruction initiates exception handling if the instruction is an invalid instruction a trap instruction or a DIVXU instruction with zero divisor Exception handling begins with a hardware exception handling sequence which prepares for the execution of a user coded software exception handling routine There is a priority order among the different types of exceptions as shown in Table 3 1 a If two or more exceptions occur simultaneously they are handled in their order of priority An instruction exception cannot occur simultaneously with other types of exceptions Table 3 1 a Exceptions and Their Priority Priority High Low Exception type Reset Address error Trace Interrupt Source External internal Internal Internal External internal Detection timing RES Low to High transition Instruction fetch or data read write bus cycle End of instruction execution if T 1 in status register End of instruction execution or end of exc
45. Name A name indicating the function of the instruction Mnemonic The assembly language mnemonic of the instruction Operation A concise symbolic indication of the operation performed by the instruction The notation used is listed on the next page Operation notation Rd C CR PC CP SP General register destination General register source General register Destination operand Source operand Condition code register N negative bit of CCR Z zero bit of CCR V overflow bit of CCR C carry bit of CCR Control register Program counter Code page register Stack pointer FP IMM disp tl lt gt t J Frame pointer Immediate data Displacement Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move Exchange Not Condition code Changes in the condition code N Z V C after instruction execution are indicated by the following symbols Not changed Pore Sa oF Undetermined Always cleared to 0 Always set to 1 Handling depends on the operand Changed according to the result of the instruction Section 2 5 Condition Code Changes lists these changes with explicit formulas showing how the bit values are derived Assembly language format The assembly language coding of the instruction is indicated as below Example ADD lt EAs gt Rd f Destination operand Source operand Mnemonic For details on assembly language n
46. Size gt lt Description gt LINK lt Condition Code gt N Previous value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged This instruction saves the frame pointer FP R6 to the stack copies the stack pointer SP R7 contents to the frame pointer then adds a specified immediate value to the stack pointer to allocate a new frame in the stack area The immediate data can be an 8 bit value from 128 to 127 or a 16 bit value from 32768 to 32767 Note that the LINK instruction allows negative immediate data The frame allocated with the LINK instruction can be deallocated with the UNLK instruction Note When the stack is accessed an address error will occur if the stack pointer indicates an odd address The immediate data should be an even number so that the stack pointer indicates an even address after execution of the LINK instruction lt Instruction Format gt LINK FP xx 8 0 0 0 1 0 111 data LINK FP xx 16 0 0 0 1 1 data H data L LINK stack lt Note gt LINK The LINK and UNLK instructions provide an efficient way to allocate and deallocate areas for local variables used in subroutine and function calls in high level languages Local variables are accessed relative to R6 the frame pointer The LINK and UNLK instructions can be broken down into the following groups of more general instructions
47. a F short format MOVe stack Frame data lt Operation gt EAs gt Rd Rs gt EAd lt Assembly Language Format gt MOV F d 8 R6 Rd MOV F Rs d 8 R6 Example 1 MOV F B 4 R6 RO 2 MOV B 4 R6 RO lt Operand Size gt Byte Word lt Description gt MOV F lt Condition Code gt Z C N ACIES N Set to 1 when the value moved is lt negative otherwise cleared to 0 Z Set to 1 when the value moved is zero otherwise cleared to 0 V Always cleared to 0 C Previous value remains unchanged This instruction moves data between a stack frame and a general register and sets or clears the N and Z bits according to the data value This instruction is a short form of the MOV instruction Compared with the general form MOV G d 8 R6 RdorMOV G Rs d 8 R6 its object code is one byte shorter lt Instruction Format gt MOV F d 8 R6 Ra o o o 8 1 r dep MOV F Rs d 8 R6 1 0 o 1 sarr r dis In assembly language coding it is usually not necessary to specify the general or special format y languag 8 y ary by coding G etc If the format specification is omitted the assembler automatically generates the optimum object code If a format is specified the assembler follows the format specification MOVe stack Frame data MOV F lt Addressing Modes gt MOV F d 8 R6 Rd Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes
48. a specified vector number Generates a trap exception if the V bit is set when the instruction is executed Returns from an exception handling routine FP gt SP SP FP SP IMM gt SP Creates a stack frame FP gt SP SP FP Deallocates a stack frame created by the LINK instruction Causes a transition to the power down state EAs gt CR Moves immediate data or general register or memory contents to a specified control register CR gt EAd Moves control register data to a specified general register or memory location CRA IMM gt CR Logically ANDs a control register with immediate data CR v IMM gt CR Logically ORs a control register with immediate data CR IMM gt CR Logically exclusive ORs a control register with immediate data PC 1 PC No operation Only increments the program counter The size depends on the control register 1 3 3 Short Format Instructions The ADD CMP and MOV instructions have special short formats Table 1 8 lists these short formats together with the equivalent general formats The short formats are a byte shorter than the corresponding general formats and most of them execute one state faster Table 1 8 Short Format Instructions and Equivalent General Formats Short format Execution Equivalent general Execution instruction Length states 2 format instruction Length states 2 ADD Q xx Rd 2 2 ADD G xx 8 Rd 3 3 CMP E xx
49. access D15 to Do Write data write access Write access Figure 4 4 External Access Cycle H8 510 570 cont
50. address space of up to 16M bytes The mode is selected by input to the chip s mode pins For details see the HS Hardware Minimum mode Maximum mode 1 Minimum Mode Supports a maximum 64K byte address space The page register is Manual Supports program and data regions totaling up to 64K bytes CPU operating mode Supports program and data regions totaling up to 16M bytes ignored Branching instructions that cross page boundaries PJMP PJSR PRTS and PRTD are invalid 2 Maximum Mode The page register is valid supporting an address space of up to 16M bytes The address space is not continuous but is divided into 64K byte pages When a program crosses a page boundary it must therefore use a page crossing branching instruction or an interrupt It is recommended for a program to be contained in a single page When data access crosses a page boundary the program must rewrite the page register before accessing the data 1 1 4 Register Configuration Figure 1 2 shows the register structure of the CPU There are two groups of registers the general registers Rn and the control registers CR General registers Rn 15 J D N J R wo _ D ol FP Frame Pointer SP Stack Pointer D N Control registers CR PC Program Counter CCR Condition Code Register CP Code Page register SR Status Register DP Data Page register EP Extended Page register TP Stack Page
51. bus 16 bit bus and 2 state Value in Table 2 8 Value in Table 2 9 2 state access access address space address space or general register 16 bit bus and 3 state Byte Value in Table 2 8 Value in Table 2 9 I access address space Word Value in Table 2 8 Value in Table 2 9 I 2 8 bit bus and 2 state Byte Value in Table 2 8 Value in Table 2 9 access address space Word Value in Table 2 8 Value in Table 2 9 I 8 bit bus and 3 state Byte Value in Table 2 8 Value in Table 2 9 I access address space Word Value in Table 2 8 Value in Table 2 9 2I or on chip register field 16 bit bus 16 bit bus and 2 state Value in Table 2 8 Value in Table 2 9 J K 2 3 state access access address space address space or general register 16 bit bus and 3 state Byte Value in Table 2 8 Value in Table 2 9 I access address space J K 2 Word Value in Table 2 8 Value in Table 2 9 d J K 2 8 bit bus and 2 state Byte Value in Table 2 8 Value in Table 2 9 access address space J K 2 Word Value in Table 2 8 Value in Table 2 9 I J K 2 8 bit bus and 3 state Byte Value in Table 2 8 Value in Table 2 9 I access address space J K 2 or on chip register field Word Value in Table 2 8 Value in Table 2 9 21 J K 2 Instruction fetch Operand access Number of states 8 bit bus 16 bit bus and 2 state Value in Table 2 8 J K 2 state access a
52. cated by R4 Subtract Compare and Branch conditionally SCB lt Note Continued gt Length 10 bytes MOV W 9 R3 LO CMP B A R4 Start loop SCB NE R3 L0 End loop With the data shown the loop executes 7 times and ends with the Z bit cleared to 0 and the value 3 in R3 The position of the first non A data can be calculated as R4 10 R3 If all the data were A the loop would end with the Z bit set to 1 and R3 1 The SCB EQ instruction can be broken down into the following more general instructions SCB EQ Rn LOOP 2 BEQ NEXT SUB W 1 Rn CMP W 1 Rn BNE LOOP NEXT In the following example a search for the value A is made in a block of the length indicated by general register R3 beginning at the address indicated by R4 v ppocgaonrgrad F R4 R3 Length 10 bytes MOV W 9 R3 LO CMP B A R4 Startloop SCB EQ R3 LO End loop With the data shown the loop executes 4 times and ends with the Z bit set to 1 and the value 6 in R3 The position of the first A can be calculated as R4 10 R3 If there was no A the loop would end with the Z bit cleared to 0 and R3 1 2 2 45 SHAL SHift Arithmetic Left SHift Arithmetic Left SHAL lt Operation gt lt Condition Code gt EAd shifted arithmetic left EAd Z V N C N Set to 1 when the result is negative lt Assembly Language Format gt SHAL lt EAd gt Example SHAL B R2 otherwise cleared to
53. ccess address space address space or general register 16 bit bus and 3 state Byte Value in Table 2 8 I1 J K access address space Word Value in Table 2 8 I 2 J K 8 bit bus and 2 state Byte Value in Table 2 8 J K access address space Word Value in Table 2 8 1 J K 8 bit bus and 3 state Byte Value in Table 2 8 1 J K access address space Word Value in Table 2 8 21 J K or on chip register field 8 bit bus 16 bit bus and 2 state Value in Table 2 8 2 J K 3 state access access address space address space or general register 16 bit bus and 3 state Byte Value in Table 2 8 1 2 J K access address space Word Value in Table 2 8 I 2 2 J K 8 bit bus and 2 state Byte Value in Table 2 8 2 J K access address space Word Value in Table 2 8 1 2 J K 8 bit bus and 3 state Byte Value in Table 2 8 I 2 J K access address space Word Value in Table 2 8 211 J K or on chip register field Notes 1 When an instruction is fetched from the 16 bit bus access address space the number of states differs by 1 or 2 depending on whether the instruction is stored at an even or odd address This point should be noted in software timing routines and other situations in which the precise number of states must be known 2 If wait states or Tp states are inserted in access to the 3 state access address space add the necessary number of states 3 When an instruction is fetched from the 16 bit bus 3 state access addres
54. cessing is not performed immediately after the end of this instruction lt Instruction Format gt XORC xx 8 CR fo0000100 data o11014ccc XORC xx 16 CR 00001100 data H data L 01101 ccc lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes 2 3 Instruction Codes Table 2 1 shows the machine language coding of each instruction e How to read Table 2 1 a to d The general operand format consists of an effective address EA field and operation code OP field specified in the following order EA field Op field AC or OA or Pa eee eee es E Bytes 2 3 5 6 are not present in all instructions os lt o Q BS 7 2 ie P10 2 Sze rir efo fefe eesrn i r0seerr a Oooo Instruction x 16 00001100 data H data L Operation code OP BE 4 Povo sfro00 0 __ 3 Efroo qn d ahooronsd Shading indicates addressing modes not available for this instruction 3 4 3 4 o xs ooooo100 aa l z MOV G B lt EAs gt Rd MOV G W lt EAs gt Rd 2 3 Byte length of instruction __f gpg Rn a al 4 a e e ea 16 Rm 1111Szrrr dispay doo pote pote ern 10riszrrer o poo foto eR iiooserre S fofofo eas ooooszio1 address lela loai ooorszio1 address address instruction Some instructions have a special
55. cified the assembler follows the format specification 2 2 24 6 MOV S MOVe data S short format MOVe data Store register MOV S lt Operation gt lt Condition Code gt Rs gt EAd Z V C N ACIES N Set to 1 when the value moved is lt Assembly Language Format gt MOV S Rs aa 8 Example 1 MOV S W RO H AO 8 2 MOV W RO H AO 8 negative otherwise cleared to 0 Z Set to 1 when the value moved is zero otherwise cleared to 0 lt Always cleared to 0 C Previous value remains unchanged lt Operand Size gt Byte Word lt Description gt This instruction stores general register data to a destination and sets or clears the N and Z bits according to the data value This instruction is a short form of the MOV instruction Compared with the general form MOV G Rs aa 8 its object code is one byte shorter lt Instruction Format gt 01 11iSrror address L lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Destination Yes Tn assembly language coding it is usually not necessary to specify the general or special format by coding G etc If the format specification is omitted the assembler automatically generates the optimum object code If a format is specified the assembler follows the format specification 2 2 25 MOVFPE MOVe From Peripheral with E clock
56. cleared to 0 lt Operand Size gt Byte Word Z Set to 1 when the result is zero otherwise Depends on the control register cleared to 0 V Always cleared to 0 C Previous value remains unchanged lt Description gt This instruction ORs the contents of a control register CR with immediate data and places the result in the control register The operand size specified in the instruction depends on the control register as explained in Table 1 12 in Section 1 3 6 Register Specification Interrupts are not accepted and trace exception processing is not performed immediately after the end of this instruction lt Instruction Format gt ORC xx 8 CR 00000100 daa 01001 ccc ORC xx 16 CRl00001100 data H data 01001 ccc lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes 2 2 33 PJMP Page JuMP Page JuMP lt Operation gt Effective address gt CP PC lt Assembly Language Format gt PJMP aa 24 PJMP Rn Example PJMP R4 lt Operand Size gt lt Description gt PJMP lt Condition Code gt N Previous value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged This instruction branches unconditionally to a specified address in a specified page updating the code page CP register If register indirect Rn address
57. ction x Multiplication Division A AND logical Vv OR logical Exclusive OR logical gt Move lt gt Exchange Not J Table 1 7 Instructions Listed by Function 1 Instruction Data transfer B byte W word Notes Size 2 MOV MOV G B W MOV E B MOV I W MOV F B W MOV L B W MOV S B W LDM W STM W XCH W SWAP B MOVTPE B MOVFPE B Function EAs EAd IMM gt EAd Moves data between two general registers or between a general register and memory or moves immediate to a general register or memory Stack Rn register list Pops data from the stack to one or more registers Rn register list gt stack Pushes data from one or more registers onto the stack Rs Rd Exchanges data between two general registers Rd upper byte lt gt Rd lower byte Exchanges the upper and lower bytes in a general register Rn gt EAd Transfers data from a general register to memory in synchronization with the E clock EAs Rd Transfers data from memory to a general register in synchronization with the E clock 1 Do not use the MOVTPE and MOVFPE instructions with the H8 520 which has no E clock output pin 2 B byte W word Table 1 7 Instructions Listed by Function 2 Instruction Size Arithmetic ADD operations ADD G B W l ADD Q B W SUB B W ADDS B W SUBS B W ADDX B W SUBX B W DADD DSUB MULXU
58. ction tests a specified bit in the destination operand and sets or clears the Z bit according to the result The bit number 0 to 15 can be specified directly using immediate data or can be placed in a specified general register If a general register is used the lower 4 bits of the register specify the bit number and the upper 12 bits are ignored lt Instruction Format gt BTST Rs lt EAd gt EA 01444467 re lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes Yes Yes Yes Yes Yes 2 2 12 CLR CLeaR CLeaR lt Operation gt 0 gt EAd lt Assembly Language Format gt CLR lt EAd gt Example CLR W H 1000 R5 lt Operand Size gt Byte Word lt Description gt CLR lt Condition Code gt N Always cleared to 0 Z Always set to 1 V Always cleared to 0 C Always cleared to 0 This instruction clears the destination operand general register Rn or an operand in memory to Zero lt Instruction Format gt lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes Yes Yes Yes Yes Yes 2 2 13 CMP 1 CMP G CoMPare General format CoMPare lt Operation gt Set CCR according to result of EAd IMM Set CCR according to result of Rd EAs lt Assembly Language Format gt CMP G xx lt EAd gt CMP G lt EAs gt Rd Example 1 CMP G B
59. d after an LDM instruction is shown below Stack Stack SP 2 gt SP gt RO SP 2 gt SP toe SP 2 gt SP gt R5 j gt Re SP 2 gt SP X SP 2 gt SP Dummy read is SP gt Execution of LDM SP R0 R1 R5 R7 If R7 the stack pointer is included in the register list a dummy read of the stack is performed Accordingly the instruction will execute faster if R7 is not specified The value of R7 after execution of the instruction is contents of R7 before the instruction 2 x number of registers restored LoaD to Multiple registers LDM lt Note Continued gt The following graph compares the number of machine states required for execution of LDM and execution of the same process using the MOV instruction Repetitions of MOV W SP Rn LDM Number 30 of states 25 Oo 1 2 3 4 5 6 7 8 Number of registers loaded Note This graph is for the case in which instruction fetches and stack access are both to on chip memory The LDM instruction is faster when the number of registers is four or more The MOV instruction is faster when there are only one or two registers to restore When the instruction fetches are to off chip memory the LDM instruction is faster when there are two registers or more 2 2 23 LINK LINK LINK stack lt Operation gt FP R6 SP SP FP R6 SP IMM SP lt Assembly Language Format gt LINK FP xx Example LINK FP 4 lt Operand
60. d in a specified general register If a general register is used the lower 4 bits of the register specify the bit number and the upper 12 bits are ignored lt Instruction Format gt BCLR Rs lt EAd gt EA sdf dt Od de lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes Yes Yes Yes Yes Yes Yes 2 2 8 BNOT Bit test and NOT Bit test and NOT lt Operation gt lt bit No gt of lt EAd gt gt Z lt bit No gt of lt EAd gt lt Assembly Language Format gt BNOT xx lt EAd gt BNOT Rs lt EAd gt Example BNOT W RO R1 lt Operand Size gt Byte Word lt Description gt BNOT lt Condition Code gt N Previous value remains unchanged Z Set to 1 if the value of the bit tested was zero Otherwise cleared to 0 V Previous value remains unchanged C Previous value remains unchanged This instruction tests a specified bit in the destination operand sets or clears the Z bit according to the result then inverts the specified bit The bit number 0 to 15 can be specified directly using immediate data or can be placed in a specified general register If a general register is used the lower 4 bits of the register specify the bit number and the upper 12 bits are ignored lt Instruction Format gt BNOT Rs lt EAd gt EA JJotiiotirrr lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn R
61. dress The immediate data should be an even number so that the stack pointer indicates an even address after execution of the PRTD instruction lt Instruction Format gt PRTD xx 8 oo010 00100010100 data PRTD xx 16 00010001 00011 100 data H data L 2 2 36 PRTS Page ReTurn from Subroutine Page ReTurn from SubRoutine PRTS lt Operation gt lt Condition Code gt SP CP N Z V C SP PC Erre lt Assembly Language Format gt N Previous value remains unchanged Z Previous value remains unchanged PRTS Example V Previous value remains unchanged pie C Previous value remains unchanged lt Operand Size gt lt Description gt This instruction is used to return from a subroutine in a different page It pops the code page register CP and program counter PC from the stack Execution continues from the popped address This instruction is used to return from a subroutine called by PJSR instruction This instruction is invalid when the CPU is operating in minimum mode lt Instruction Format gt 000310 0031 0 00311 00 1 2 2 37 ROTL ROTate Left ROTate Left ROTL lt Operation gt lt Condition Code gt EAd rotated left EAd Z V N C Fes aS N Set to 1 when the result is negative lt Assembly Language Format gt ROTL lt EAd gt Example otherwise cleared to 0 ee eer Z Set to 1 when the result is zero otherwise cleared to 0 lt Always cleared to 0
62. e CPU The lower half of the status register is referred to as the condition code register CCR its 8 bits can be accessed as a 1 byte condition code SR _PrRr S OS CCR 1514131211109 8 7 6 543 2 1 0 Bit 15 Trace T When this bit is set to 1 the CPU operates in trace mode and generates a trace exception after every instruction When this bit is cleared to 0 instructions are executed in normal continuous sequence This bit is cleared to 0 at a reset Bits 14 to 11 Reserved These bits cannot be written and when read are always read as Q0 n Bits 10 to 8 Interrupt mask PE to Io These bits indicate the interrupt request mask level 0 to 7 As shown in 3 an interrupt request is not accepted unless it has a higher level than the value of the mask A nonmaskable interrupt NMJ which has level 8 is always accepted regardless of the mask level 4 indicates the values of the I bits after an interrupt is accepted When an interrupt is accepted the value of bits I2 to Io is raised to the same level as the interrupt to prevent a further interrupt from being accepted unless its level is higher A reset sets all three of bits 12 I1 and Io to 1 Table 1 3 Interrupt Mask Levels Interrupt mask Priority Level Pio Interrupts accepted High 7 111 NMI 6 110 Level 7 and NMI 5 101 Levels 6 to 7 and NMI 4 100 Levels 5 to 7 and NMI 3 011 Levels 4 to 7 and NMI 2 010 Levels 3 to 7 and NMI 1 001 Lev
63. e has been executed The timing chart below is for access to off chip memory by the H8 532 Read cycle Write cycle 2 2 57 TRAPA TRAP Always TRAP Always lt Operation gt PC gt SP If maximum mode then CP gt SP SR gt SP if maximum mode then lt vector gt CP lt vector gt PC lt Assembly Language Format gt TRAPA xXxX Example TRAPA 4 lt Operand Size gt lt Description gt TRAPA lt Condition Code gt N Previous value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged This instruction generates a trap exception with a specified vector number When a TRAPA instruction is executed the CPU initiates exception handling according to its current operating mode In the minimum mode it pushes the program counter PC and status register SR onto the stack then indexes the vector table by the vector number specified in the instruction and copies the vector at that location to the program counter In the maximum mode it pushes the code page register CP PC and SR onto the stack and copies the vector to CP and PC The code page register is byte size but the stack and vector table are always accessed as word data The lower eight bits are used TRAP Always lt Instruction Format gt 0 0 001 00 0 0 0 0 1 VEC VEC VEC NNN fF WN KF O Vector address Minimum mode H 0020
64. e registers LDM does not however restore R7 it performs a dummy read instead Accordingly the program will execute faster if R7 is not specified in the register list STore Multiple registers STM lt Note Continued gt The following graph compares the number of machine states required for execution of STM and execution of the same process using the MOV instruction Repetitions of MOV W Rn SP STM Number 30 of states 25 O 1 2 3 4 5 6 7 8 Number of registers pushed Note This graph is for the case in which instruction fetches and stack access are both to on chip memory The STM instruction is faster when the number of registers is four or more The MOV instruction is faster when there are only one or two registers to save If the instruction fetches are to off chip memory the STM instruction is faster when there are two registers or more 2 2 52 SUB SUBtract binary SUBtract binary SUB lt Operation gt lt Condition Code gt Rd EAs gt Rd Z V N C N Set to 1 when the result is negative lt Assembly Language Format gt SUB lt EAs gt Rd Example SUB W R1 RO otherwise cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 V Set to 1 if an overflow occurs lt Operand Size gt f otherwise cleared to 0 oe C S l ifab Set to 1 if a borrow occurs Word otherwise cleared to 0 lt Description gt This instruction subtracts a source
65. ead when operand is in ca seo appB dt mwa f2 7 7 E olallel ein Shading in the I column means the operand cannot be in memory Shading indicates addressing modes that cannot be used with this instruction 2 6 3 Examples of Calculation of Number of States Required for Execution H8 520 H8 532 H8 534 H8 536 Example 1 ADD G W R0 R1 instruction fetch from on chip memory Operand Start Assembler notation Table 2 8 Number Read Write addr Address Code Mnemonic Table 2 9 of states On chip memory Even H 0100 H D821 ADD RO RI 5 1 6 or general register Odd H 0101 H D821 ADD RO RI 5 0 5 Example 2 JSR RO instruction fetch from on chip memory Operand Branch Assembler notation Table 2 8 Number Read Write addr Address Code Mnemonic Table 2 9 21 of states External Even H FCOO H 11D8 JSR RO 9 04 2x2 13 memory word Odd H FCO L H l1l1D amp 8 JSR RO 9 14 2x2 14 Example 3 ADD G W R0O R1 instruction fetch from external memory Operand Assembler notation Table 2 8 Number Read Write Address Code Mnemonic 2 J K of states On chip memory H 9002 H D821 ADD G W RO RI 5 2x 1 1 9 or general register On chip supporting H 9002 H D821 module or external ADD G W RD R1 memory 5 2x 2 1 1 13 2 6 4 Number of Execution States H8 510 H8 570 One state is one cycle of the system clock If 1OMHz then one state 100ns Instruction fetch Operand access Number of states 16 bit
66. eceives an exception handling request such as a reset or an interrupt of an acceptable level The CPU then returns via the exception handling state to the program execution state 3 5 2 Software Standby Mode When the software standby SSBY bit in the standby control register SBYCR is set to 1 execution of a SLEEP instruction causes a transition to the software standby mode In this mode the CPU the clock and the other on chip supporting functions all stop operating The on chip supporting modules are reset but as long as a minimum voltage level is maintained the contents of CPU registers and on chip RAM remains unchanged The status of I O ports also remains unchanged A reset or nonmaskable interrupt is required to recover from the software standby mode The CPU returns via the exception handling state to the program execution state The H8 570 recovers from software standby mode by reset only Program execution restarts after the reset exception handling sequence If a Low STBY signal is received in the software standby mode the mode changes to the hardware standby mode See the H8 Hardware Manual 3 5 3 Hardware Standby Mode Input of a Low STBY signal causes a transition to the hardware standby mode In this mode as in the software standby mode all operations halt All clock signals stop and the on chip supporting modules are reset but as long as a minimum voltage level is maintained the contents of on chip RAM rema
67. els 2 to 7 and NMI Low 0 000 Levels 1 to 7 and NMI Table 1 4 Interrupt Mask Bits after an Interrupt is Accepted Level of interrupt accepted I2 I1 Io NMI 8 1 O 0O oD m m m 0O OF Dm m NU RADAN O oD o ee Bits 7 to 4 Reserved These bits cannot be written and when read are always read as 0 Bit 3 Negative N This bit indicates the most significant bit sign bit of the result of an instruction Bit 2 Zero Z This bit is set to 1 to indicate a zero result and cleared to 0 to indicate a nonzero result Bit 1 Overflow V This bit is set to 1 when an arithmetic overflow occurs and cleared to 0 at other times Bit 0 Carry C This bit is set to 1 when a carry or borrow occurs at the most significant bit and is cleared to 0 or left unchanged at other times The specific changes that occur in the condition code bits when each instruction is executed are detailed in the instruction descriptions in Section 2 2 1 and listed in Tables 2 7 1 to 4 in Section 2 5 Condition Code Changes 3 Code Page Register CP The code page register and the program counter combine to generate a 24 bit program code address thereby expanding the program area The code page register contains the upper 8 bits of the 24 bit address In the maximum mode both the code page register and program counter are saved and restored in exception handling and a new code page value is loaded from the e
68. eption handling sequence Table 3 1 b Instruction Exceptions Exception type Start of exception handling sequence Start of exception handling sequence Immediately End of instruction execution End of instruction execution End of instruction execution Invalid instruction Attempted execution of instruction with undefined code Trap instruction Started by execution of trap instruction Zero divide Attempted execution of DIV XU instruction with zero divisor 3 2 2 Exception Handling Sources and Vector Table Figure 3 2 classifies the sources of exception handling Each source has a different vector address as listed in Table 3 2 The vector addresses differ between the minimum and maximum modes Reset External l interrupt e Interrupt Interrupt Internal requested by interrupt on chip module Exception Address error e Trace Invalid instruction e Instruction Zero divide TRAPA instruction TRAP VS instruction Figure 3 2 Sources of Exception Handling Table 3 2 Exception Vector Table Type of exception Reset initialize PC reserved for system Invalid instruction DIVXU instruction zero divide TRAP VS instruction reserved for system Address error Trace reserved for system Nonmaskable external interrupt NMI reserved for system TRAPA instruction 16 factors External and Internal interrupt Minimum mode H 0000 to H 0001 H 0002 to H 0003 H 0004
69. eration gt lt Condition Code gt EAd rotated left through C bit EAd Z WV N C Fes aS N Set to 1 when the result is negative lt Assembly Language Format gt ROTXL lt EAd gt Example ROTXL W H 02 R1 otherwise cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 lt Al leared to 0 lt Operand Size gt ways cleared to 0 Byte Word C Receives the value shifted out from the most significant bit lt Description gt This instruction rotates the destination operand general register Rd or memory contents left through the C bit The least significant bit of the destination operand receives the old value of the C bit The most significant bit is rotated to become the new value of the C bit MSB LSB cJe _ lt Instruction Format gt lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes Yes Yes Yes Yes Yes Yes 2 2 40 ROTXR ROTate with eXtend carry Right ROTate with eXtend carry Right ROTXR lt Operation gt lt Condition Code gt EAd rotated right through C bit gt EAd Z WV N C Fes aS N Set to 1 when the result is negative lt Assembly Language Format gt ROTXR lt EAd gt Example otherwise cleared to 0 Z Set to 1 when the result is zero ROTXR B H FA 8 otherwise cleared to 0 lt Al leared to 0 lt Operand Size gt ways cleared to 0 Byte Word
70. es Yes Yes Yes Yes Destination Yes 2 2 24 2 MOV E MOVe data E short format MOVe immEdiate byte MOV E lt Operation gt lt Condition Code gt IMM Rd Z V C N Acme N Set to 1 when the value moved is lt Assembly Language Format gt MOV E xx 8 Rd Example 1 MOV E H 55 R0 2 MOV B H 55 RO negative otherwise cleared to 0 Z Set to 1 when the value moved is zero otherwise cleared to 0 lt Always cleared to 0 C Previous value remains unchanged lt Operand Size gt Byte lt Description gt This instruction moves one byte of immediate data to a general register and sets or clears the N and Z bits according to the data value This instruction is a short form of the MOV instruction Compared with the general form MOV G xx 8 Rd its object code is one byte shorter and it executes one state faster lt Instruction Format gt ototrorrery data lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Destination Yes Tn assembly language coding it is usually not necessary to specify the general or special format by coding G etc If the format specification is omitted the assembler automatically generates the optimum object code If a format is specified the assembler follows the format specification 2 2 24 3 MOV F MOVe dat
71. format in which the operation code comes first The following notation is used in the tables e Sz Operand size byte or word Byte Sz 0 Word Sz 1 e rrr General register number field rrr Sz 0 Byte Sz 1 Word 15 87 0 15 0 000 001 010 O11 100 101 110 111 e ccc Control register number field cecce Sz 0 Byte Sz 1 Word 000 Not allowed 15 0 7 001 CCR Not allowed 010 Not allowed Not allowed 011 Not allowed 100 Not allowed 101 Not allowed 110 Not allowed Not allowed 111 Not allowed Disallowed means that this combination of bits must not be specified Specifying a disallowed combination may cause abnormal results register list A byte in which bits indicate general registers as follows Bit 7 6 5 4 3 2 ar re rs we ms re a fo 1 0 VEC Four bits designating a vector number from 0 to 15 The vector numbers correspond to addresses of entries in the exception vector table as follows VEC Vector address Minimum mode Maximum mode Examples of machine language coding VE Vector address Cini mode Maximum mode 0 H 0020 H 0021 H 0040 H 0043 H 0030 H 0031 H 0060 H 0063 1 H 0022 H 0023 H 0044 H 0047 H 0032 H 0033 H 0064 H 0067 2 H 0024 H 0025 H 0048 H 004B 10 H 0034 H 0035 H 0068 H 006B 3 H 0026 H 0027 H 004C H 004F 11 H 0036 H 0037 H 006C H 006F 4 H 0028 H 0029 H 0050 H 0
72. ge so the sign of the result remains the same MSB LSB o lt Instruction Format gt pA lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes Yes Yes Yes Yes Yes Yes 2 2 47 SHLL SHift Logical Left SHift Logical Left SHLL lt Operation gt lt Condition Code gt EAd shifted logical left gt EAd Z V N C pa Seo ae N Set to 1 when the result is negative lt Assembly Language Format gt SHLL lt EAd gt Example otherwise cleared to 0 SHLL B R1 Z Set to 1 when the result is zero otherwise cleared to 0 lt Always cleared to 0 C Set to the value shifted out from the most significant bit lt Operand Size gt Byte Word lt Description gt This instruction shifts the destination operand general register Rd or memory contents left and sets the C bit to the value shifted out from the most significant bit The least significant bit is cleared to 0 The only difference between this instruction and SHAL is that this instruction clears the V bit to 0 MSB LSB c e _ id lt Instruction Format gt ER E lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes Yes Yes Yes Yes Yes Yes 2 2 48 SHLR SHift Logical Right SHift Logical Right SHLR lt Operation gt lt Condition Code gt EAd shifted logical right EAd N Z V C MENETES Al
73. ge coding it is usually not necessary to specify the general or special format by coding G etc If the format specification is omitted the assembler automatically generates the optimum object code If a format is specified the assembler follows the format specification 2 2 2 ADDS ADD with Sign extension ADD with Sign extension ADDS lt Operation gt lt Condition Code gt Rd EAs gt Rd N Z V C lt Assembly Language Format gt N Previous value remains unchanged ADDS lt EAs gt Rd Example ADDS W H 10 R3 Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged lt Operand Size gt Byte Word lt Description gt This instruction adds the source operand to the contents of general register Rd destination operand and places the result in general register Rd Differing from the ADD instruction this instruction does not alter the condition code If byte size is specified the sign bit of the source operand is extended The addition is performed using the resulting word data General register Rd is always accessed as a word size operand lt Instruction Format gt lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Destination Yes a er _ i NE 2 2 3 ADDX ADD with eXtend carry ADD with eXtend carry ADDX lt Operation gt lt Condition Code
74. ges a code page stack page data page and extended page Two address space modes can be selected Minimum mode Maximum 64K byte address space Maximum mode Maximum 16M byte address space e Highly orthogonal instruction set Addressing modes and data sizes can be specified independently within each instruction e Optimized for efficient programming in C language In addition to the general registers and orthogonal instruction set the H8 500 CPU has short two byte formats for frequently used instructions and addressing modes The CPU architecture supports up to 16M bytes but for specific chips the maximum address space is restricted by the number of external address lines example maximum 1M byte for the H8 532 1 1 2 Data Structures The H8 500 can process 1 bit data 4 bit BCD data 8 bit byte data 16 bit word data and 32 bit longword data Bit manipulation instructions operate on 1 bit data Decimal arithmetic instructions operate on 4 bit BCD data Almost all data transfer shift arithmetic and logical operation instructions operate on byte and word data Multiply and divide instructions operate on longword data Table 1 1 lists the data formats used in general registers Table 1 2 lists the data formats used in memory 1 General Register Data Formats Table 1 1 General Register Data Formats Data type Register No Data structure 1 Bit Rn is iafish2 1 ipo fa EN 15 8 7 4 3 0 ie Rn Upper digit BCD
75. gister Table 2 8 Instruction Execution Cycles 5 Instruction Bee da 8 Bee d 16 BSR JMP JSR NOP RTD RTE RTS SCB SLEEP STM Condition Condition false branch not taken Condition true branch taken Condition false branch not taken Condition true branch taken d 8 d 16 aa 16 Rn d 8 Rn d 16 Rn aa 16 Rn d 8 Rn d 16 Rn XX28 xx 16 xx 8 xx 16 Minimum mode Maximum mode Condition false branch not taken Count 1 branch not taken Other than the above branch taken Cycles preceding transition to power down mode Execution cycles 3 7 3 7 9 9 7 6 7 8 9 9 9 10 6 4n 6 7 2 9 9 1 1 8 3 4 8 2 6 3n nis the number of registers specified in the register list NNDIINNENN NID AINN 2n A DI NWW AJA AIU HR RPO NnNID ANUS HN An BID WIN N Se N Table 2 8 Instruction Execution Cycles 6 Instruction Condition Execution cycles I TRAPA Minimum mode 17 6 Maximum mode 22 TRAP VS V 0 trap not taken 3 V 1 trap taken minimum mode 18 6 V 1 trap taken maximum mode 23 UNLK PJMP aa 24 9 Rn 8 PJSR aa 24 15 Rn 13 PRTS PRTD xx 8 13 xx 16 13 Table 2 9 a Adjusted value branch instructions Instruction Address Adjusted value BSR JMP JSR RTS RTD RTE even 0 TRAPA PJMP PJSR PRTS PRTD odd 1 Bec SCB TRAP VS When branches even 0 odd 1 Table 2 9 b Adjusted value Other
76. h its two s complement It subtracts the destination operand from zero and places the result in the destination lt Instruction Format gt lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes Yes Yes Yes Yes Yes 2 2 29 NOP No OPeration No OPeration lt Operation gt PC 1 PC lt Assembly Language Format gt NOP Example NOP lt Operand Size gt lt Description gt NOP lt Condition Code gt N Previous value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged This instruction only increments the program counter lt Instruction Format gt 00000 00 0 2 2 30 NOT NOT logical complement Logical complement NOT lt Operation gt lt Condition Code gt EAd EAd Z V C N slilol N Set to 1 when the result is negative lt Assembly Language Format gt NOT lt EAd gt Example NOT B H 10 R2 otherwise cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 lt Al leared to 0 lt Operand Size gt ways cleared to Byte Word C Previous value remains unchanged lt Description gt This instruction replaces the destination operand general register Rd or memory contents with its one s complement lt Instruction Format gt pA Ot Ot OT lt Addressing Modes gt Rn Rn
77. ine is shown below Before LINK After LINK After UNLK After RTS Stack Stack Stack Stack SP temp2 area FP 4 e oe sp Teun Fo TETIS SP gt The LINK instruction The UNLK instruction saves the old FP copies copies the FP to the SP the SP to the FP then thus deallocating the allocates a temporary temporary area then area by moving the SP restores the FP up In this example the SP is decremented by 4 The temporary area is accessed relative to the FP 2 2 24 MOV 1 MOV G MOVe data from source to destination General format MOVe data from source to destination MOV G lt Operation gt lt Condition Code gt EAs gt EAd Z V C N 2 Jo N Set to 1 when the value moved is lt Assembly Language Format gt MOV G Rs lt EAd gt MOV G xx lt EAd gt MOV G lt EAs gt Rd Example 1 MOV G W RO R1 2 MOV W RO R1 negative otherwise cleared to 0 Z Set to 1 when the value moved is zero otherwise cleared to 0 V Always cleared to 0 C Previous value remains unchanged lt Operand Size gt Byte Word lt Description gt This instruction copies source operand data to a destination and sets or clears the N and Z bits according to the data value Alternative short formats can be used for the R6 indirect with displacement addressing mode MOV F the short aa 8 absolute addressing mode MOV L and MOV S and the immediate addressing modes
78. ing is used the lower byte of general register Rn is copied to the code page register and the contents of general register Rn 1 are copied to the program counter PC The register number n must be even n 0 2 4 or 6 Correct results are not assured if n is odd This instruction is invalid when the CPU is operating in minimum mode lt Instruction Format gt PUMP aa 24 00010011 page address H address L PUMP Rn 00010001 11000rrr 2 2 34 PJSR Page Jump to SubRoutine Page Jump to SubRoutine PJSR lt Operation gt lt Condition Code gt PC gt SP N Z V C CP gt SP eases Effective address CP PC N Previous value remains unchanged lt Assembly Language Format gt Z Previous value remains unchanged PJSR aa 24 V Previous value remains unchanged PJSR Rn C Previous value remains unchanged Example PJSR H 010000 lt Operand Size gt lt Description gt This instruction pushes the program counter PC and code page registers CP onto the stack then branches to a specified address in a specified page The PC and CP values pushed on the stack are the address of the instruction immediately following the PJSR instruction If register indirect Rn addressing is used the lower byte of general register Rn is copied to the code page register and the contents of general register Rn 1 are copied to the program counter The register number n must be even n 0 2 4 or 6 Correct resul
79. ins unchanged I O ports are set to the high impedance state A reset is required to recover from the software standby mode The CPU returns via the exception handling state to the program execution state Section 4 Basic Operation Timing The CPU operates on the clock which is created by dividing the clock oscillator output by 2 One cycle of the clock is called a state The following sections describe the timing of access to on chip memory on chip supporting modules and off chip devices 4 1 On Chip Memory Access Timing H8 520 532 534 536 570 For high speed execution access to on chip memory RAM and ROM is performed in two states The data width is 16 bits Figure 4 1 is a timing chart for access to on chip memory No wait state TW is inserted Bus cycle Ti state T2 state gt t Internal address bus X Address I Internal Read signal E Internal data bus for read access Read data Internal Write signal Internal data bus i CO wieda gt for write access Write data Figure 4 1 On Chip Memory Access Timing 4 2 On Chip Supporting Module Access Timing On chip supporting modules are accessed in three states as shown in Figure 4 2 The data width is 8 bits No wait state TW is inserted Bus cycle T1 state Internal address bus T2 state T3 state gt Address Internal Read signal Internal data bus for read access Inte
80. instructions by addressing modes Cm alal a alalafal AJA gt gt A Instructor Start address Nowra wove ot rae d 16 Rn EEC EER BSc ecom PERE FE 1 1 2 1 KAERA a Instructions other than above even et P 1 1 2 7 Invalid Instruction Exception Handling Handling of Undefined Instruction Codes When an attempt is made to execute an instruction with an undefined bit pattern undefined operation code or addressing mode the H8 500 initiates invalid instruction exception handling Undefined means that the corresponding entry in the operation code map is blank Table 2 10 lists the invalid instruction codes In addition to the instruction codes listed there are invalid combinations of addressing modes These do not cause an invalid instruction exception so proper handling is not assured Table 2 10 Instruction Codes Causing Invalid Instruction Exceptions a Effective address H 0B H 16 H 1B Register Memory Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 Immediate xx 8 xx 16 Operation code H 01 to H 07 H OA H OB H OE H OF H 01 to H 03 H OA H OB H OE H OF H 10 to H 12 H 00 to H OF H 10 to H 1F H 78 to H 7F H 90 to H 9F H CO to H CF H DO to H DF H EO to H EF H FO to H FF Table 2 10 Instruction Codes Causing Invalid Instruction Exceptions b Operation code Effective address H 01 H 00 to H OF H 06 H 10 to H 13 H 07 H 15 to H 18 H 11 H
81. is multiplied by the 16 bit source operand yielding a 32 bit result which is placed in Rd and Rd 1 15 Rd 0 7 EAs 0 15 Rd 0 exe muttipticand x mutipier prouet Rd 15 Rd 0 15 EAs 0 T product H 16 x 16 multiplicand x multiplier product L Rd 1 When word size is specified and the 32 bit product is placed in Rd and Rd 1 d must be even 0 2 4 or 6 Correct results are not assured if an odd register number is specified MULtiply eXtend as Unsigned MULXU lt Instruction Format gt EA 101041 rri r When Sz 0 8 bits x 8 bits 16 bits When Sz 1 16 bits x 16 bits 32 bits where Sz is the size bit in the EA code lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Destination Yes _ gt 2 2 28 NEG NEGate NEGate lt Operation gt 0 EAd gt EAd lt Assembly Language Format gt NEG lt EAd gt Example NEG W RO lt Operand Size gt Byte Word lt Description gt NEG lt Condition Code gt Z V N C N Set to 1 when the result is negative otherwise cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 V Set to 1 if an overflow occurs otherwise cleared to 0 C Set to 1 if a borrow occurs otherwise cleared to 0 This instruction replaces the destination operand general register Rd or memory contents wit
82. k frame created by a LINK instruction It copies the frame pointer FP R6 contents to the stack pointer SP R7 then pops the top word in the new stack area the FP saved by the LINK instruction to the frame pointer lt Instruction Format gt 00001 1 1 1 2 2 61 XCH eXCHange registers eX CHange register XCH lt Operation gt lt Condition Code gt Rs Rd N Z V C lt Assembly Language Format gt N Previous value remains unchanged XCH Rs Rad Z Previous value remains unchanged Example V Previous value remains unchanged XCH RO R1 C Previous value remains unchanged lt Operand Size gt Word lt Description gt This instruction interchanges the contents of two general registers lt Instruction Format gt lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Destination Yes 2s x 2 2 62 XOR eXclusive OR logical eXclusive OR logical XOR lt Operation gt lt Condition Code gt Rd EAs gt Rd ZV N Jo N Set to 1 when the result is negative lt Assembly Language Format gt XOR lt EAs gt Rd Example XOR B H AO 8 RO otherwise cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 lt Al leared to 0 lt Operand Size gt ways Cleared to Byte Word C Previous value remains unchanged lt Description gt
83. le the stack pointer is incremented by 2 2 2 42 RTE ReTurn from Exception ReTurn from Exception RTE lt Operation gt lt Condition Code gt SP SR N Z V C if maximum mode then SP CP SP PC N Popped from stack lt Assembly Language Format gt Z Popped from stack V Popped from stack RTE Example C Popped from stack RTE lt Operand Size gt lt Description gt This instruction returns from an exception handling routine It pops the program counter PC and status register SR from the stack In the maximum mode it also pops the code page register CP Execution continues from the new address in the program counter and code page register in maximum mode Interrupts are not accepted and trace exception processing is not performed immediately after the end of this instruction The code page CP register is one byte in length A full word is popped from the stack and the lower 8 bits are placed in the CP lt Instruction Format gt 00001 01 0 2 2 43 RTS ReTurn from Subroutine ReTurn from Subroutine RTS lt Operation gt lt Condition Code gt SP PC N Z V C lt Assembly Language Format gt N Previous value remains unchanged RTS Example Z Previous value remains unchanged RTS V Previous value remains unchanged C Previous value remains unchanged lt Operand Size gt lt Description gt This instruction is used to return from a subroutine in the same page
84. m C Sm Dm Dm Rm Sm Rm N Rm Z Z Rm RO V Sm Dm Rm Sm Dm Rm C Sm Dm Dm Rm Sm Rm N Rm Z Rm Rm 1 RO If CR SR CCR N Z V and C are ANDed with source operand bits 3 to 0 If CR SR CCR N Rm Z Rm Rm 1 RO V 0 C remains unchanged Z Dn Z Dn Z Dn Z Dn N Rm Z Rm Rm 1 RO V Sm Dm Rm Sm Dm Rm C Sm Dm Dm Rm Sm Rm Z Z Rm RO C decimal carry N Rm Z Rm Rm 1 RO V division overflow Z is the Z bit before execution Table 2 7 Condition Code Changes 2 Instruction DSUB EXTS EXTU H DC MOV MOVFPE MOVTPE MULXU NEG NOP NOT OR ORC N i gt JN t 0 0 Definitions Z Z Rm RO C decimal borrow N Rm Z Rm Rm 1 RO Z Rm Rm 1 RO If CR SR CCR then N Z V and C are loaded from the source operand If CR SR CCR then N Z V and C remain unchanged N Rm Z Rm Rm 1 RO N Rm Z Rm Rm 1 RO N Rm Z Rm Rm 1 RO V Dm Rm C Dm Rm N Rm Z Rm Rm 1 RO N Rm Z Rm Rm 1 RO If CR SR CCR N Z V and C are ORed with source operand bits 3 to 0 If CR SR CCR N Rm Z Rm Rm 1 RO V 0 C remains unchanged Table 2 7 Condition Code Changes 3 Instruction PJMP PJSR PRTS PRTD ROTL ROTR ROTXL ROTXR RTD RTE RTS SCB SHAL SHAR SHLL N Z C ta t ta t E t ae t Uo yd yoo wt
85. ment d 16 Rn Register indirect with 16 bit displacement Rn Register indirect with pre decrement Rn Register indirect with post increment aa 8 Short absolute address 8 bits aa 16 Absolute address 16 bits XX 8 Immediate 8 bits xx 16 Immediate 16 bits 2 2 Instruction Descriptions The individual instructions are described starting in Section 2 2 1 Yes Yes 2 2 1 ADD 1 ADD G ADD General format ADD Binary ADD G lt Operation gt lt Condition Code gt Rd EAs gt Rd Ze N eC N N Set to 1 when the result is negative lt Assembly Language Format gt ADD G lt EAs gt Rd Example 1 ADD G B RO R1 2 ADD B RO R1 otherwise cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 V Set to 1 if an overflow occurs i otherwise cleared to 0 lt Operand Size gt Byte Word C Set to 1 if a carry occurs otherwise cleared to 0 lt Description gt This instruction adds the source operand to the contents of general register Rd destination operand and places the result in general register Rd When the source operand is the immediate data 1 or 2 the ADD Q instruction in Section 2 2 1 2 can be used The ADD Q instruction is shorter and executes more quickly lt Instruction Format gt lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Des
86. n Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes Yes Yes Yes Yes Yes Yes 2 2 9 BSET Bit test and SET Bit test and SET lt Operation gt lt bit No gt of lt EAd gt gt Z 1 gt lt bit No gt of lt EAd gt lt Assembly Language Format gt BSET xx lt EAd gt BSET Rs lt EAd gt Example BSET B 0 R1 lt Operand Size gt Byte Word lt Description gt BSET lt Condition Code gt N V C N Previous value remains unchanged Z Set to 1 if the value of the bit tested was zero Otherwise cleared to 0 Ph V Previous value remains unchanged C Previous value remains unchanged This instruction tests a specified bit in the destination operand sets or clears the Z bit according to the result then sets the specified bit to 1 The bit number 0 to 15 can be specified directly using immediate data or can be placed in a specified general register If a general register is used the lower 4 bits of the register specify the bit number and the upper 12 bits are ignored lt Instruction Format gt BSET Rs lt EAd gt EA otoodi rrr lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes Yes Yes Yes Yes Yes 2 2 10 BSR Branch to SubRoutine Branch to SubRoutine lt Operation gt PC gt SP PC disp gt PC lt Assembly Language Format gt BSR disp Example BSR LABEL lt
87. nd the contents of general register Rd destination operand and places the result in general register Rd lt Instruction Format gt lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Destination Yes _ S 2 2 5 ANDC AND Control register AND Control register ANDC lt Operation gt lt Condition Code gt CR A IMM CR Z V lt Assembly Language Format gt ANDC xx CR Example ANDC B H FE CCR 1 When CR is the status register SR or CCR the N Z V and C bits are set according to the result of the operation 2 When CR is not the status register EP TP DP or BR the bits are set as below N Set to 1 when the MSB of the result is 1 otherwise cleared to 0 lt Operand Size gt Byte Word Z Setto 1 when the result is zero otherwise Depends on the control register cleared to 0 V Always cleared to 0 C Previous value remains unchanged lt Description gt This instruction ANDs the contents of a control register CR with immediate data and places the result in the control register The operand size specified in the instruction depends on the control register as indicated in Table 1 12 in Section 1 3 6 Register Specification Interrupts are not accepted and trace exception processing is not performed immediately after the end of this instruction lt Instruction Format
88. ng mode Mnemonic Effective Address and Extension Bytes 2 Register indirect Rn 1101Szrrr Register indirect d 8 Rn with displacement d 16 Rn 4 Register indirect Rn 1011Szrrr with pre decrement Register indirect Rn 1100Szrrr 1 with post increment eS TO NO fe 5 Absolute address 3 aa 8 2 aa 16 addr H addr L 3 6 Immediate XX 8 2 xx 16 data H data L 3 7 PC relative disp Effective address information is 1 or 2 specified in the operation code otes Sz Operand size Sz 0 byte operand Sz 1 word operand 2 rrr register number field General register number 000 RO O01 RI 010 R2 011 R3 100 R4 101 R5 110 R6 111 R7 3 The aa 8 addressing mode may be referred to as the short absolute addressing mode Table 1 10 Effective Address Calculation 1 Effective address No Addressing mode calculation Effective address 1 Register direct None Operand is contents of Rn Rn 10108z 2 Register indirect None 23 15 0 sie DP TP EP 1 1101Sz 2 3 Register indirect with displacement d 8 Rn 8 bit 15 23 15 0 1110Sz DP TP EP 2 15 disp sign extention 15 23 15 0 DP TP EP 1 x 15 z 4 Register indirect 15 23 15 0 with pre decrement Rn contents DP TP EP 1 Result 5 Ny Rn 1 C mwa H AA S Rn is decremented by 1 or 2 before instruction execution 3 4 5 Register indirect None 23 15 0 with post increment DP TP EP 1 Rn lt 1100Sz Rn is incremen
89. on Yes Yes Yes Yes Yes Yes Yes CMP lt EAs gt Rd Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Destination Yes Z mar _ 2 2 13 2 CMP E CoMPare E short format CoMPare immediate bytE CMP E lt Operation gt lt Condition Code gt Set CCR according to result of Rd IMM Z V N C N Set to 1 when the result is negative lt Assembly Language Format gt CMP E xx 8 Rd Example 1 CMP E H OO RO 2 CMP B H 00 RO otherwise cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 V Set to 1 if an overflow occurs otherwise cleared to 0 lt Operand Size gt C Set to 1 if a borrow occurs Byte otherwise cleared to 0 lt Description gt This instruction subtracts one byte of immediate data from general register Rd and sets or clears the condition code CCR according to the result It does not alter the contents of general register Rd This instruction is a short form of the CMP instruction Compared with CMP G xx 8 Rd its object code is one byte shorter and it executes one state faster lt Instruction Format gt o1o000rrr daa lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Destination Yes Tn assembly language coding it is usuall
90. otation see the HS 500 Series Cross Assembler Manual Operand size The available operand sizes are indicated Description A detailed description of the instruction Instruction format The machine language instruction format including the effective address is indicated as shown below EA field OP field T ir l rrr Register number field Register a ccc Control register number field Effective address Operation code No Addressing mode Mnemonic Effective address and extension Bytes 1 Register direct Rn 1 2 Register indirect Rn 3 Register indirect d 8 Rn with displacement d 16 Rn 4 Register indirect Rn with pre decrement Register indirect Rn 1100Szrrr 1 with post increment 5 Absolute address aa 8 0000Sz101 eS IO NO Re 2 6 Immediate xx 8 2 7 PC relative disp Effective address information is lor2 specified in the operation code The aa 8 addressing mode may be referred to as the short absolute addressing mode Addressing modes The addressing modes that can be specified for the source and destination operands are indicated in a table like the one below Yes means that the mode can be used means that it cannot Example ADD instruction Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes Yes Yes Yes Yes Yes Yes Destination Yes r Symbol Meaning Rn Register direct Rn Register indirect d 8 Rn Register indirect with 8 bit displace
91. peration on general register or memory contents EAd shift EAd Performs a logical shift operation on general register or memory contents EAd rotate gt EAd Rotates general register or memory contents EAd rotate with carry gt EAd Rotates general register or memory contents through the C carry bit lt bit No gt of lt EAd gt gt Z 1 gt lt bit No gt of lt EAd gt Tests a specified bit in a general register or memory then sets the bit to 1 The bit is specified by a bit number given in immediate data or a general register lt bit No gt of lt EAd gt gt Z 0 lt bit No gt of lt EAd gt Tests a specified bit in a general register or memory then clears the bit to 0 The bit is specified by a bit number given in immediate data or a general register lt bit No gt of lt EAd gt gt Z lt bit No gt of lt EAd gt Tests a specified bit in a general register or memory then inverts the bit The bit is specified by a bit number given in immediate data or a general register lt bit No gt of lt EAd gt gt Z Tests a specified bit in a general register or memory The bit is specified by a bit number given in immediate data or a general register Table 1 7 Instructions Listed by Function 5 Instruction Branch Bcc P JMP BSR JSR PJSR RTS Size Function Branches if condition is true Mnemonic BRA BT BRN BF BHI BLS BCC
92. put pins in the mode select bits MDSO to MDS2 of the mode control register MDCR Next the CPU reads the address of the reset handling routine from the exception vector table and executes the program at that address 3 3 Bus Released State When it receives a bus request BREQ signal from an external device the CPU waits until the end of a machine cycle then releases the bus To notify the external device that it has released the bus the CPU responds to the BREQ signal by asserting a Low BACK signal When it receives the BACK signal the device that requested the bus becomes the bus master and can use the address bus data bus and control bus The H8 520 does not support the BREQ signal 3 4 Reset State A reset has the highest exception handling priority A reset provides a way to initialize the system at power up or when recovering from a fatal error When the RES pin goes Low whatever process is being executed is halted and the micro computer unit enters the reset state A reset clears the T bit bit 15 of the status register SR to 0 to disable the trace mode and sets the interrupt mask level in I2 to Io SR bits 10 to 8 to 7 the highest level In the reset state all interrupts are disabled including the nonmaskable interrupt NMI When the RES pin returns from Low to High the microcomputer unit comes out of the reset state and begins executing the reset exception routine 3 5 Power Down State In the power do
93. rnal Write signal Read data Internal data bus 4 for write access j Write data Figure 4 2 On Chip Supporting Module Access Timing 4 3 External Device Access Timing Off chip devices are accessed in two or three states as shown in Figures 4 3 and 4 4 The access timing depends on the particular off chip device A wait state controller can insert additional wait states Tw as necessary Wait states cannot be inserted in access to the two state access address space however because of the high processing speed For details about the insertion of wait states see the HS Hardware Manual Read cycle Ti state T2 state Ts state a a A19t0 Ao Address z 2 a Le High Read data y H8 520 532 534 536 The H8 520 does not output R W and DS bus control signals Figure 4 3 a External Access Cycle Read Access b Write Write cycle T1 state T2 state T3 state a a A19to Ao Address D7 to Do Write data H8 520 532 534 536 Figure 4 3 b External Access Cycle Write Access a Two State Access Address Space Access Cycle Bus cycle T1 state T2 state gt A23 to AO Figure 4 4 External Access Cycle H8 510 570 b Three State Access Address Space Access Cycle Bus cycle T1 state T2 state T3 state a a HWR LWR D15 to Do Read data p read
94. ruction code Another bit may be used to indicate whether a register operand is a byte or word operand See Table 1 11 Table 1 11 General Register Specification tH A Effective address P Operation code EA field OP field eR KK GZ ri ri rh e RR KK TY rj rj n O z Size byte word ririri rjrjrj General register number ririri rj rj rj Sz 0 Byte Sz 1 Word 15 87 0 15 0 000 001 RI 010 Not used 2 ao R3 R4 R5 011 Not used 100 Not used 101 Not used 110 Not used 111 Not used o R7 2 Control Register Specification Control registers are specified by a control register number embedded in the operation code byte See Table 1 12 Table 1 12 Control Register Specification EA field OP field ccc Control register number field cece Sz 0 Byte Sz 1 Word 000 Not allowed 15 0 i i 001 CCR Not allowed 010 Not allowed Not allowed 011 Not allowed 100 Not allowed 101 Not allowed 110 Not allowed Not allowed 111 Not allowed Control register numbers indicated as Not allowed should not be used because they may cause the CPU to malfunction Section 2 Instruction Set Detailed Descriptions 2 1 Table Format and Notation Each instruction is described in a table with the following format Name Mnemonic lt Operation gt lt Condition Code gt lt Assembly Language Format gt lt Operand Size gt lt Description gt lt Instruction Format gt lt Addressing Modes gt
95. s Unsigned DIVide eXtend as Unsigned DIVXU lt Operation gt lt Condition Code gt Rd EAs gt Rd Z V C N JENES N Set to 1 when the result is negative lt Assembly Language Format gt DIVXU lt EAs gt Rd Example DIVXU W R3 RO otherwise cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 g V Set to 1 if an overflow occurs lt Operand Size gt Byte Word otherwise cleared to 0 C Always cleared to 0 lt Description gt When byte size is specified for the source operand the 16 bit value in Rd is divided by the 8 bit source operand yielding an 8 bit quotient which is placed in the lower byte of Rd and 8 bit remainder which is placed in the upper byte of Rd When word size is specified for the source operand the 32 bit value in Rd and Rd 1 is divided by the 16 bit source operand yielding a 16 bit quotient which is placed in Rd 1 and a 16 bit remainder which is placed in Rd 15 Rd 0 7 0 15 Rd 87 0 16 8 dividena divisor_ remainder quotient _ 15 0 15 0 15 0 Rd 1 dividend L Rd 1 quotient When the dividend is a 32 bit value located in Rd and Rd 1 d must be even 0 2 4 or 6 Correct results are not assured if an odd register number is specified Also 1 Attempted division by 0 causes a zero divide exception The N V and C bits are cleared to 0 and the Z bit is set to 1 2 When an overflow is detected the V bit is set to 1 and the di
96. s space the term J K 2 is rounded down to an integer 2 6 5 Examples of Calculation of Number of States Required for Execution H8 510 H8 570 Example 1 Instruction fetch from 16 bit bus 2 state access address space Operand Start Assembler notation Table 2 8 Number Read Write addr Address Code Mnemonic Table 2 9 of states 16 bit bus 2 state Even H 0100 D821 ADD RO RI 5 1 6 access address Odd H 0101 D821 ADD RO RI 5 0 5 space or general register Example 2 Instruction fetch from 16 bit bus 2 state access address space stack in 8 bit bus 3 state access address space Operand Branch Assembler notation Table 2 8 Number Read Write addr Address Code Mnemonic Table 2 9 2I of states 8 bit bus Even H FC00 11D8 JSR RO 9 0 2x2 13 3 state Odd H FCO1 11D8 JSR RO 94 1 2x2 14 access address space word Example 3 Instruction fetch from 8 bit bus 3 state access address space Operand Assembler notation Table 2 8 Number Read Write Address Code Mnemonic 2 J K of states 16 bit bus 2 state H 9002 D821 ADD RO RI 5 2x 14 1 9 access address space or general register Example 4 Instruction fetch from 16 bit bus 2 state access address space Table 2 8 Operand Start Assembler notation Table 2 9 Number Read Write addr Address Code Mnemonic J K 2 of states 16 bit bus Even H 0100 D821 ADD RO RI 5 1 1 1 2 7 2 state access Odd H 0101 D821 ADD RO RI 5 0 1 1 2 6 address space or general re
97. solute addressing mode a 16 bit operand address is generated by using the contents of the base register as the upper 8 bits and the address given in the instruction code as the lower 8 bits The page is always page 0 in the short absolute addressing mode p 8 Bits p E 16 Bits effective address Figure 1 4 Base Register 1 2 3 Initial Register Values When the CPU is reset its internal registers are initialized as shown in Table 1 5 Table 1 5 Initial Values of CPU Registers Initial value Register Minimum mode Maximum mode General registers RO R7 Undetermined Undetermined o1 oO Control registers 15 0 orcas ene vector table vector table SR SSNS eo CCR ae COSO 15 8 7 0 H 070 N H 070 N ZV and Care ZV and Car east undetermined undetermined 7 0 Loaded f Undetermined Vector table 7 0 Undetermined Undetermined 7 0 P Undetermined Undetermined 7 0 Undetermined Undetermined 7 0 Undetermined Undetermined 1 3 Instruction Set The main features of the CPU instruction set are A general register architecture Orthogonality Addressing modes and data sizes can be specified independently in each instruction 1 5 type addressing register register and register memory operations Affinity for high level languages particularly C Short formats for frequently used instructions and addressing modes 1 3 1 Types of Instructions The CPU instruction set includes 63 types of
98. t specification is omitted the assembler automatically generates the optimum object code If a format is specified the assembler follows the format specification 2 2 24 5 MOV L_ MOVe data L short format MOVe data Load register MOV L lt Operation gt lt Condition Code gt EAs gt Rd Z V C N ACIES N Set to 1 when the value moved is lt Assembly Language Format gt MOV L aa 8 Rd Example 1 MOV L B H AO 8 RO 2 MOV B H AO 8 RO negative otherwise cleared to 0 Z Set to 1 when the value moved is zero otherwise cleared to 0 lt Always cleared to 0 C Previous value remains unchanged lt Operand Size gt Byte Word lt Description gt This instruction copies source operand data to a general register and sets or clears the N and Z bits according to the data value This instruction is a short form of the MOV instruction Compared with the general form MOV G aa 8 Rd its object code is one byte shorter lt Instruction Format gt 01 10Srrr address L lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Destination Yes Tn assembly language coding it is usually not necessary to specify the general or special format by coding G etc If the format specification is omitted the assembler automatically generates the optimum object code If a format is spe
99. ted by 1 or 2 after instruction execution 3 4 5 5 Absolute address None 23 15 0 aa 8 Ho BR 0001Sz1101 EA extension data t aa 16 None 23 15 0 00008z 101 EA extension data Table 1 10 Effective Address Calculation 2 Effective address No Addressing mode calculation Effective address 6 Immediate None Operand is 1 byte XX 8 EA extension data 00000100 xx l6 sd None Operand is 2 byte 00001100 EA extension data 7 PC relative 8 Bits d 8 15 23 15 0 o 15 Displacement sign extension d 16 16 Bits 15 23 15 0 15 Notes 1 The page register is ignored in the minimum mode 2 In addressing modes No 2 3 and 4 the page register is as follows DP for register indirect addressing with RO R1 R2 or R3 EP for register indirect addressing with R4 or RS TP for register indirect addressing with R6 or R7 3 Increment Decrement by for a byte operand and by 2 for a word operand 4 In addressing mode No 4 register indirect with pre decrement or post increment when register R7 is specified the increment or decrement is always 2 even when operand size is 1 byte 5 If SP is saved by SP addressing mode and poped by SP the result will be as follows SPP gt SPD Old SP 2 ee after MOV W SP SP gt SPR after MOV W SP SP 1 3 6 Register Specification 1 General Register Specification General registers are specified by a three bit register number contained in the inst
100. tination Yes _ oa _ a io R Tn assembly language coding it is usually not necessary to specify the general or special format by coding G etc If the format specification is omitted the assembler automatically generates the optimum object code If a format is specified the assembler follows the format specification 2 2 1 2 ADD ADD Quick short format ADD Quick ADD Q lt Operation gt lt Condition Code gt EAd IMM gt EAd Z V C N CEE N Set to 1 when the result is negative lt Assembly Language Format gt ADD Q xx lt EAd gt Example 1 ADD Q W 1 RO 2 ADD W 1 RO otherwise cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 V Set to 1 if an overflow occurs otherwise cleared to 0 lt Operand Size gt Byte Word C Set to 1 if a carry occurs otherwise cleared to 0 lt Description gt This instruction adds immediate data to the destination operand and places the result in the destination operand The values 1 and 2 can be specified as immediate data lt Instruction Format gt ADD Q 1 lt EAd gt A 00001 00 0 i oO 4 ADD Q 2 lt EAd gt A 00001 0 ADD Q 1 lt EAd gt A 00001 10 0 i ADD Q 2 lt EAd gt A 00001 10 1 lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes Yes Yes Yes Yes Yes Yes Tn assembly langua
101. to H 0005 H 0006 to H 0007 H 0008 to H 0009 H 000A to H 000B H 000C to H 000D H 000E to H 000F H 0010 to H 0011 H 0012 to H 0013 H 0014 to H 0015 H 0016 to H 0017 H 0018 to H 0019 to H OO1E to H 001F H 0020 to H 0021 to H 003E to H 003F H 0040 to H 0041 to H 009E to H 009F Maximum mode H 0000 to H 0003 H 0004 to H 0007 H 0008 to H 000B H 000C to H 000F H 0010 to H 0013 H 0014 to H 0017 H 0018 to H 001B H 001C to H 001F H 0020 to H 0023 H 0024 to H 0027 H 0028 to H 002B H 002C to H 002F H 0030 to H 0033 to H 003C to H 003F H 0040 to H 0043 to H 007C to H 007F H 0080 to H 0083 to H 013C to H 013F Note 1 In maximum mode the exception vector table is located in page 0 2 Each products have different vector table See the H8 Hardware Manual for details Assigned to ISP address error in the H8 570 3 2 3 Exception Handling Operation When exception handling is started by a source other than a reset in the minimum mode the program counter PC and status register SR are pushed onto the stack in the maximum mode the code page register CP PC and SR are pushed onto the stack Then the trace T bit in the status register is cleared to 0 the address of the pertinent exception handling routine is read from the exception vector table and execution branches to that address A reset is handled as follows When the RES pin goes Low the CPU waits for the RES pin to go High then latches the value at the mode in
102. ts are not assured if n is odd This instruction is invalid when the CPU is operating in minimum mode The status of the stack after execution of this instruction is shown below TP SP Indeterminate data a __ op lt Instruction Format gt PJSR aa 24 00000011 page address H address L PJSR Rn 00010001j11001 rrr 2 2 35 PRTD Page ReTurn and Deallocate Page ReTurn and Deallocate PRTD lt Operation gt lt Condition Code gt SP CP N Z V C eSP gt PC SAS SP IMM gt SP N Previous value remains unchanged lt Assembly Language Format gt Z eon value Tans unchanged PRTD x V Previous value remains unchanged Example PRTD 8 C Previous value remains unchanged lt Operand Size gt lt Description gt This instruction is used to return from a subroutine in a different page and deallocate the stack area used by the subroutine It pops the code page register CP and program counter PC from the stack then adjusts the stack pointer by adding immediate data specified in the instruction The immediate data value can be an 8 bit value from 128 to 127 or a 16 bit value from 32768 to 32767 This instruction can be used to restore the previous stack when returning from a subroutine called by the PJSR instruction This instruction is invalid when the CPU is operating in minimum mode Note When the stack is accessed an address error will occur if the stack pointer indicates an odd ad
103. ve address extension Operation code Note Some instructions DADD DSUB MOVFPE MOVTPE have an extended format in which the operand code is preceded by a one byte prefix code Example MOVTPE instruction Prefix code Operation code eo Effective address 00000 00 0 1 0010 rf r rf rrr General register No 2 Special format In this format the operation code comes first followed by the effective address field and effective address extension This format is used in branching instructions system control instructions and other instructions that can be executed faster if the operation to be performed on the operand is specified first e Operation code One or two bytes defining the operation to be performed by the instruction e Effective address field and effective address extension Zero to three bytes containing information used to calculate the effective address of an operand Fetch direction gt Operation code Effective address Effective address extension 1 3 5 Addressing Modes and Effective Address Calculation The CPU supports the seven addressing modes listed in Table 1 9 below Due to the highly orthogonal nature of the instruction set most instructions having operands can use any applicable addressing mode from 1 through 6 Mode 7 is used by branching instructions Table 1 9 explains how the effective address EA is calculated in each addressing mode Table 1 9 Addressing Modes No Addressi
104. vision is not performed The N Z and C bits are cleared to 0 The contents of general register Rd are not updated DIVide eXtend as Unsigned DIVXU lt Instruction Format gt EA 1 01iiirr r When Sz 0 16 bits 8 bits When Sz 1 32 bits 16 bits where Sz is the size bit in the EA code lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Destination Yes _ gt DIVide eXtend as Unsigned DIVXU lt Note gt An overflow can occur in both cases of the DIVXU instruction 16bits 8bits 8 bit quotient 8 bit remainder 32bits 16bits gt 16 bit quotient 16 bit remainder Consider H FFFF H 1 H FFFF in case for example An overflow occurs because the quotient is longer than 8 bits Overflow can be avoided by using work registers as in the programs shown below 16 bits 8 bits 32 bits 16 bits DIVXU B lt EA gt RO DIVXU W lt EA gt RO RO dividend RO dividend H dividend L an RO H 00 dividend H R1 H 00 dividend L H 0000 D o R1 dividend H RO quotient R1 quotient L ne R3 dividend L ao R1 quotient L Re R3 quotient L MOV B RO R1 MOV W R1 R3 SWAP RO MOV W RO R1 AND W H OOFF 16 RO CLR W RO DIVXU B lt EA gt RO DIVXU W lt EA gt RO SWAP RO MOV W RO R2 SWAP R1 MOV W R1 RO MOV B RO R1 DIVXU W lt EA gt R2 SWAP R1
105. ways cleared to 0 lt Assembly Language Format gt Z SHLR lt EAd gt Z Set to 1 when the result is zero Example SHLR W R1 otherwise cleared to 0 V Always cleared to 0 i C Set to the value shifted out from the lt Operand Size gt Byte Word least significant bit lt Description gt This instruction shifts the destination operand general register Rd or memory contents right and sets the C bit to the value shifted out from the least significant bit The most significant bit is cleared to 0 lt Instruction Format gt e a eee eee lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Destination Yes Yes Yes Yes Yes Yes Yes Yes 2 2 49 SLEEP SLEEP SLEEP lt Operation gt Normal operating mode power down mode lt Assembly Language Format gt SLEEP Example SLEEP lt Operand Size gt lt Description gt SLEEP lt Condition Code gt N Previous value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged When the SLEEP instruction is executed the CPU enters the power down mode Its internal state remains unchanged but the CPU stops executing instructions and waits for an exception handling request When it receives such a request the CPU exits the power down mode and begins exception handling lt Instruction Format gt 00011 01 0 2 2 50 ST
106. wn state some or all of the clock signals are stopped to conserve power There are three power down modes Table 3 1 describes the state of the CPU and the on chip supporting functions in each mode Table 3 3 Power Down Modes Mode Clock CPU Supporting CPU registers Recovery methods functions and on chip RAM Sleep Runs Halts Run Held Interrupt Interrupt is accepted and interrupt handling begins RES Transition to reset state STBY 2 Transition to hardware standby mode Software Halts Halts Halt Held NMI MMI starts clock NMI standby and exception handling starts initialized automatically after time set in watchdog timer RES Clock starts followed by transition to reset state STBY 2 Hardware standby mode Hardware Halts Halts Halt Held High input at STBY pin and standby and Low input at RES pin followed initialized after clock settling time by High input at RES pin initiates reset exception handling routine Notes 1 Only on chip RAM contents are held 2 In the H8 520 select mode 6 at MD2 to MDO 3 In the H8 520 select mode 1 2 3 4 or 7 at MD2 to MDO 3 5 1 Sleep Mode Execution of the SLEEP instruction normally causes a transition to the sleep mode CPU operation halts immediately after execution of the SLEEP instruction but the CPU register contents remain unchanged The on chip supporting functions in particular the clock continue to operate The CPU wakes up from the sleep mode when it r
107. xception vector table 4 Data Page Register DP The data page register combines with general registers RO to R3 to generate a 24 bit effective address thereby expanding the data area The data page register contains the upper 8 bits of the 24 bit effective address The data page register is used to calculate effective addresses in the register indirect addressing mode using RO to R3 and in the 16 bit absolute addressing mode aa 16 5 Extended Page Register EP The extended page register combines with general register R4 or RS to generate a 24 bit effective address thereby expanding the data area The extended page register contains the upper 8 bits of the 24 bit address It is used to calculate effective addresses in the register indirect addressing mode using R4 or RS 6 Stack Page Register TP The stack page register combines with R6 Frame pointer or R7 Stack pointer to generate a 24 bit stack address thereby expanding the stack area The stack page register contains the upper 8 bits of the 24 bit stack address It is used to calculate effective addresses in the register indirect addressing mode using R6 or R7 Page register PC or general register 16 Bits 8 Bits 3 t _ _ _ 24 Bits effective address Figure 1 3 Combinations of Page Registers and PC or General Registers 7 Base Register BR This register stores the base address used in the short absolute addressing mode aa 8 In the short ab
108. y not necessary to specify the general or special format by coding G etc If the format specification is omitted the assembler automatically generates the optimum object code If a format is specified the assembler follows the format specification 2 2 13 3 CMP I CoMPare I short format CoMPare Immediate word CMP I lt Operation gt lt Condition Code gt Set CCR according to result of Rd IMM Z V N C N Set to 1 when the result is negative lt Assembly Language Format gt CMP I xx 16 Rd Example otherwise cleared to 0 Z Set to 1 when the result is zero 1 CMP 1 H FFFF RI1 2 CMP W H FFFF R1 otherwise cleared to 0 V Set to 1 if an overflow occurs otherwise cleared to 0 lt Operand Size gt C Set to 1 if a borrow occurs Word otherwise cleared to 0 lt Description gt This instruction subtracts one word of immediate data from general register Rd and sets or clears the condition code CCR according to the result It does not alter the contents of general register Rd This instruction is a short form of the CMP instruction Compared with CMP G xx 16 Rd its object code is one byte shorter and it executes one state faster lt Instruction Format gt 01001 rrr data H data L lt Addressing Modes gt Rn Rn d 8 Rn d 16 Rn Rn Rn aa 8 aa 16 xx 8 xx 16 Source Yes Destination Yes

H8 5XX Programming

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