Intel 82557 to 82596 Compatibility Guide
Contents
1. 1 3 0 FEATURE CHANGES IN THE 82557 aii tah tte aS irae 4 oss eben es 2 4 0 FUNCTIONAL CHANGES BETWEEN THE 82557 AND 82596 2 4 1 New Enhancements in the B255T ma ei ete Sos dude gc pee LY 2 4 2 Functions in the 82596 Not Supported by the 82557 3 CONTENTS PAGE 5 0 SOFTWARE INTERFACE COMPARISONS 3 5 1 The 82557 Control Status Register CSR sc Sasa Sa ane ante na 3 5 2 SCB Command Comparisons 7 5 3 SCB Status Acknowledge Comparisons e e eee 8 5 4 Action Command Comparisons 8 5 5 Configure Parameter Differences ee eee eee 9 5 6 PORT Interface Comparisons 11 5 7 Statistical Error Information Comparisons e eee ee 11 6 0 ADDITIONAL INFORMATION 12 intel 1 0 INTRODUCTION Over the last few years the networking environment has evolved to account for the needs of high band width Fast Ethernet otherwise known as IEEE 100BASE T is a technology derived from 10BASE T Ethernet and was designed to address many of the per formance bottlenecks associated with classic 10 Mbit Ethernet networks Intel s Fast Ethernet component product solution includes the 82557 and 82553 compo nents This application note provides information on the dif ferences between the Intel 82596 and the Intel 82557 next generation family of LAN controllers It explains 82596 to 82557 compatibility for Ethernet design2. T 0 0 0 RFA OFFSET CBL OFFSET CRC ERRORS ALIGNMENT ERRORS RESOURCE ERRORS OVERRUN ERRORS RCVCDT ERRORS SHORT FRAME ERRORS T ON TIMER T OFF TIMER Figure 3 82596 System Control Block 31 Upper Word 16 15 Lower Word 0 SCB Command Word SCB Status Word SCB General Pointer PORT EEPROM Control Register Flash Control Register MDI Control Register Figure 4 82557 Control Status Register The 82557 Command Block List linked list of individ ual action commands and Receive Frame Area list of free frame descriptors and data buffers are very similar to those of the 82596 Transmit commands can be pro grammed in either Simplified or Flexible memory modes The Receive Frame Area consists of Receive Frame Descriptors RFDs and Receive Buffer De scriptors RBDs The 82596 RFD can be one two types Simplified or Flexible For the 82557 its RFD can be one of three types Simplified Flexible or Head er Detailed memory structure differences are highlighted in Sections 5 2 through 5 7 PRELIMINARY intel 5 2 SCB Command Comparisons AP 368 82557 82596 ene PRE Parameter am Parameter CPU Acknowledge N A Acknowledge events are located N A CX CU completed action Events in SCB Status word command N A FR RU received a frame N A CNA Command Unit became not active N A RNR Receive Unit became not ready Interrupt Control 1
3. er can reuse resources to prepare a new transmit command e Transmit threshold the 82557 incorporates a trans mit threshold parameter which allows adjustment to the FIFO level at which the Transmit process be gins The 82596 begins the Transmit process as soon as the first Dword reaches the bottom of the trans mit FIFO e Addressing modes the 82557 uses an enhanced lin ear addressing mode for all operations The 82596 uses either linear or 32 bit segmented 82586 ad dressing modes 4 2 Functions in the 82596 not Supported by the 82557 e Byte Ordering the 82557 supports Little Endian mode only no Big Endian mode e Addressing the 82557 has no 82586 compatible ad dressing modes e Adjustable frame length the 82557 has no Mini mum Frame Length variable 82557 has a default minimum frame length of 64 bytes e Monitor mode the 82557 has no monitoring mode for evaluating incoming frames e Adjustable slot time the 82557 has no support for an adjustable slot time parameter Control structures the 82557 does not include SCP SCB or ISCP shared memory structures on chip CSR replaces SCB e CRC CRC flexibility is not supported in the 82557 No CRC and CRC 16 CRC 32 options are not present PRELIMINARY AP 368 5 0 SOFTWARE INTERFACE COMPARISONS Both the 82557 and 82596 use a shared memory com munication system with the CPU However the 82557 uses only three parts that comprise the shared memory struc
4. transmission within the mini mum inter frame spacing Fullsupportfor upto 1 Mbyte PRELIMINARY AP 368 of FLASH provides remote Boot capability a BIOS extension stored in the FLASH which could allow a node to boot itself off of a network drive For 100 Mbps applications the 82557 contains an IEEE MII compliant interface to the Intel 82553 physical in terface device or other MII compliant PHY which provides a complete LAN solution for 100 10 Mbps networks For 10 Mbps networks the 82557 can be interfaced to a standard ENDEC interface such as the Intel 82503 Serial Interface component while main taining software compatibility to 100 Mbps solutions The 82557 was designed to implement cost effective high performance PCI add in adapters or it can also be used directly on a PC motherboard designs Its combi nation of high integration and low cost make it ideal for either application 82557 Feature Summary e Glueless 32 bit PCI bus master interface direct drive of bus compatible to PCI spec Rev 2 1 e 82596 like chained memory structure e Improved dynamic transmit chaining for enhanced performance e Programmable transmit threshold for improved bus utilization e Early receive interrupt for concurrent processing of receive data e Built in FLASH interface with addressing up to 1 MByte e On chip receive and transmit FIFOs e On chip counters for network management e Support for back to back transmit interframe spa
5. 6 PORT Interface Comparisons 82557 82596 Software Reset Software Reset Self Test Self Test Selective Reset N A must use CU RU Abort Dump Dump N A SCP 5 7 Statistical Error Information Comparisons 82557 82596 Location in Location in Statistical Error Memory On Chip Statistical Error Memory On Chip Transmit Good Frames on chip counter N A N A Transmit Maximum Collisions Errors on chip counter Transmit Maximum Collisions number of collisions experience per frame used with Transmit Attempt Stopped in TCB per frame N A N A Transmit Attempt Stopped stopped because number of collisions exceeded max number of retries in TCB per frame Transmit Late Collisions Errors on chip counter in TCB Transmit Late Collision in TCB per frame Transmit Underrun Errors on chip counter Transmit Underrun in TCB per frame Transmit Lost Carrier Sense on chip counter Transmit Lost Carrier Sense in TCB per frame Transmit Deferred on chip counter Transmit Deferred in TCB per frame Transmit Single Collisions on chip counter Transmit Multiple Collisions on chip counter Transmit Total Collisions on chip counter Use Transmit Max Collisions Receive Good Frames on chip counter N A N A Receive CRC Errors on chip counter Receive CRC Errors in SCB Receive Alignment Errors on chip counter Receive Ali
6. Software Generated Interrupt N A N A Need external latch 1 Interrupt Mask bit CU Commands 000 NOP 000 NOP 001 CU Start 001 CU Start 010 CU Resume 010 CU Resume 011 Reserved 011 CU Suspend 100 Load Dump Counters Address 100 CU Abort 101 Dump Statistical Counters 101 Load Bus Throttle Timers 110 Load CU Base Load amp restart Bus Throttle Timers 111 Dump and Reset Statistical 111 Reserved Counters RU Commands 000 NOP 000 NOP 001 RU Start 001 RU Start 010 RU Resume 010 RU Resume 011 Reserved 011 RU Suspend 100 RU Abort 100 RU Abort 101 Load Header Data Size 101 Reserved 110 Load RU Base 110 Reserved 111 RBD Resume 111 Reserved Other N A Must use PORT reset N A Reset logically same as hardware RESET PRELIMINARY AP 368 5 3 SCB Status Acknowledge Comparisons Type of Status 82557 a intel 82596 Interrupt Acknowledgment CX TNO CU finished executing a command with I bit set or indicates transmit command ended NOT OK configurable CX CU finished executing a command with its I bit set FR RU finished receiving the frame or header part of frame FR RU finished receiving a frame CNA Command unit left the Active state and entered the idle state configurable CNA Command unit left the active state RNR Receive unit left the Ready state RNR Receive unit left the Ready state MDI MDI read or write cycle is N A completed confi
7. c ing IFS e Built in EEPROM interface e Support for both 10 Mbps and 100 Mbps networks e Interface to MII compliant physical interface such as the Intel 82553 Serial Component for 10 100 Mbps designs IEEE 802 3 100BASE T compatible e Interface to Intel 82503 for 10 Mbps designs IEEE 802 3 1OBASE T compatible e Autodetect and autoswitching for 10 or 100 Mbps network speeds e Full duplex capable at 10 and 100 Mbps e 160 Lead QFP package AP 368 3 0 FEATURE CHANGES IN THE 82557 The 82557 is a follow on to the 82596 LAN controller Intel made a number of changes and enhancements in the 82557 to increase performance while being cost sen sitive The following table highlights key functional and physical changes between the 82557 and 82596 Feature 82557 82596 Maximum Serial 10 or 100 Mbps 10 Mbps Speed MII Yes No Bus Interface 32 Bit PCI 32 Bit Local Bus Bus Bandwidth 132 Mbytes 106 Mbytes Sec 33 MHz Sec 33 MHz Architecture Master Master Shared Memory CSR CBL RFA Initialization Structures Root SCB CBL RFA Transmit Simplified 82586 Receive Flexible Simplified Structures Flexible Memory 32 Bit 82586 32 Bit Addressing Enhanced Segmented Linear Linear FIFO 3K RX 3K TX 128 Byte RX 64 Byte TX Byte Ordering Little Endian Little Big Endian FLASH Yes 1 M No Interface Package 160 Pin PQFP 132 Pin PQFP PGA Pin Compatible No No Bursting 256 Dw
8. cal counters that are automatically updated with each transmit receive command The 82596 TCB stores statistical data which must be compiled by the driver for each TCB before continuing to the next command MII the 82557 supports MII interface compatibility includes MII specific control and data signals and MDI register The 82596 includes a generic ENDEC serial interface PCI the 82557 includes a full 32 bit PCI standard interface The 82596 includes a 32 bit local bus in terface Bus throughput the 82557 allows a 132 Mbyte max imum parallel PCI bandwidth at 33 MHz The 82596 allows a 106 Mbyte maximum parallel band width at 33 MHz Flash capable the 82557 allows for a flash memory interface control and addressing up to 1 Mbyte The 82596 does not allow for designs requiring flash memory devices Full duplex the 82557 is truly Full duplex capable using FDX and FULHAL pins for controlling full duplex functionality The 82596 implements a limit ed full duplex capability PRELIMINARY intel e Adaptive IFS the 82557 supports an adaptive IFS algorithm which maximizes network throughput The 82596 includes a tunable IFS parameter for manually adjusting IFS Bursting the 82557 allows bursting of 256 Dword lengths The 82596 allows bursting of 4 Dword length e Early Transmit Completion Status the 82557 re ports a completion of a transmit command as soon as the frame is copied from memory so that the driv
9. cast Disable Broadcast Disable Promiscuous Mode Promiscuous Mode Linear Priority Mode N A No Source Address Insertion No Source Address Insertion N A Backoff Method PRELIMINARY N A Slot Time N A Maximum Retry Number N A Disable Backoff N A Exponential Priority AP 368 5 5 Configure Parameter Differences Continued Parameters Ase 82557 PNA 82596 Collision Parameters CRS or CDT N A N A Carrier Sense Filter N A Carrier Sense Source N A Collision Detect Filter N A Collision Detect Source N A Transmit on no CRS N A Collision Detect by Source Address Comparison Header Parameters N A Address Length N A use discard short frames Minimum Frame Length Multicast ALL Multicast ALL Multiple Individual Address Multiple Individual Address N A Preamble Until Carrier Sense Preamble Length Preamble Length Other Adaptive IFS N A Late SCB Update N A Transmit Not OK Interrupt N A CU Idle Interrupt N A Underrun Retry N A 503 MII N A Loopback Loopback N A Manchester NRZ Stripping Enable N A Padding Enable N A N A Bit Stuffing N A Padding for Bit Stuffing N A Auto Retransmit Byte Count Byte Count Force Full Duplex Full Duplex Operation Full Duplex Pin Enable Full Duplex Operation 19 PRELIMINARY intel AP 368 5
10. ers The application note can help designers transition from an existing 82596 LAN solution to an 82557 solution For further information on the 82557 refer to the 82557 Data Sheet and the 82557 User s Manual avail able from an Intel Sales Representative 2 0 THE 82557 LAN CONTROLLER The 82557 is Intel s first highly integrated 32 bit PCI LAN controller for 10 or 100 Mbps Fast Ethernet net works The 82557 offers a high performance LAN solu tion while maintaining low cost through its high inte gration It contains a high performance 32 bit PCI Bus Master interface to fully use the high bandwidth avail able up to 132 Mbytes per second to masters on the PCI bus The 82557 is optimized to support twisted pair Ethernet the required wiring media for 100BASE T The 82557 contains a number of high performance net working features that off load time critical tasks from the CPU Its bus master architecture can eliminate the intermediate copy step in Receive RCV and Trans mit XMT frame copies resulting in faster processing of these frames It maintains a similar memory struc ture to the Intel 82596 LAN Coprocessor however these memory structures have been streamlined for bet ter Network Operating System NOS interaction and improved performance The 82557 contains two separate RCV and XMT FIFOs preventing data overruns or underruns while waiting for access to the PCI bus The FIFOs also en able back to back frame
11. gnment Errors in SCB Receive Resource Errors on chip counter Receive Resource Errors in SCB Receive Overrun Errors on chip counter Receive Overrun Errors in SCB Receive Collision Detect Errors on chip counter Receive Collision Detect Errors in SCB Receive Short Frame Errors on chip counter Receive Short Frame Errors in SCB N A N A N A N A Heartbeat Indicator Transmit lost Clear to Send in TCB per frame in TCB per frame PRELIMINARY 11 AP 368 6 0 ADDITIONAL INFORMATION For additional literature contact your local Intel sales office or contact the Intel Literature Center by calling 1 800 548 4725 If you need design information con tact your local Intel Field Applications Engineer 12 PRELIMINARY
12. gurable SWI Software generated interrupt N A CU Status Idle Idle Suspended Suspended Active Active RU Status Idle Idle Suspended Suspended No Resources No Resources Ready Ready Suspended with no more RBDs N A No resources due to no more RBDs No resources due to no more RBDs Ready with no RBDs present Ready with no RBDs present 5 4 Action Command Comparisons Type of Command Op Code 82557 Op Code 82596 Action Commands 000 NOP 000 NOP 001 Individual Address Setup 001 Individual Address Setup 010 Configure 010 Configure 011 Multicast Address Setup 011 Multicast Address Setup 100 Transmit 100 Transmit 101 Reserved 101 TDR 110 Dump 110 Dump 111 Diagnose 111 Diagnose PRELIMINARY intel 5 5 Configure Parameter Differences AP 368 Op Op Parameters Code 82557 Code 82596 Configure Command 010 010 Parameters FIFO DMA Parameters RX FIFO Limit FIFO Limit TX FIFO Limit FIFO Limit RX DMA Max Byte Count N A TX DMA Max Byte Count N A DMA Max Byte Count Enable N A Statistical Error Parameters Save Bad Frames Save Bad Frames Discard Short Receive Frames N A use Min Frame length RCV CRC Transfer N A N A No CRC Insertion N A CRC 16 CRC 32 N A CRC in Memory N A Monitor Bits N A Monitor IEEE Parameters Linear Priority Linear Priority Interframe Spacing Interface Spacing Broad
13. intel 7 AP 368 APPLICATION NOTE 82557 10 100 Mbps PCI LAN Controller A Guide to 82596 Compatibility Technical Marketing Network Products Division November 1995 PRELIMINARY Order Number 644126 001 Information in this document is provided in connection with Intel products Intel assumes no liability whatsoev er including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata Other brands and names are the property of their respective owners Since publication of documents referenced in this document registration of the Pentium OverDrive and iCOMP trademarks has been issued to Intel Corporation Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained from Intel Corporation P O Box 7641 Mt Prospect IL 60056 7641 or call 1 800 879 4683 COPYRIGHT INTEL CORPORATION 1996 82557 10 100 Mbps PCI LAN CONTROLLER A GUIDE TO 82596 COMPATIBILITY CONTENTS PAGE 1 0 INTRODUCTION 1 2 0 THE 82557 LAN CONTROLLER
14. ord 4 Dword 4 0 FUNCTIONAL CHANGES BETWEEN THE 82557 AND 82596 This section lists primary functional changes between the 82557 and the 82596 Some are functional enhance ments others are deletions of the 82596 functionality intel 4 1 New Enhancements in the 82557 FIFO size the 82557 includes independent on chip Transmit and Receive FIFOs 3 Kbytes each the 82596 includes 64 byte transmit and 128 byte re ceive on chip FIFOs General chip control structure changes in the 82557 an on chip CSR structure incorporates SCB Flash EEPROM and MDI registers In the 82596 the shared memory SCB ISCP and SCP structures were used for general chip control Operational speed flexibility the 82557 supports ei ther 10 or 100 Mbit operation The 82596 supports a 10 Mbit operation only ignoring full duplex func tionality in both Reset functionality the 82557 includes a selective reset command which specifically resets CU and RU without affecting the overall device configura tion The 82596 includes the CU_ ABORT com mand which terminates the current CU activity and returns the CU to a known Idle state DMA resource tuning in the 82557 Tx and Rx DMA preempt counts allow direct manipulation of DMA resources to reflect design biases towards ei ther transmit or receive functions The 82596 has a fixed priority scheme for managing DMA resources Statistical counters the 82557 contains 16 on chip statisti
15. st the 82596 does not include FLASH or MDI in its SCB it uses RFA Off set CBL Offset as opposed to the 82557 General Pointer The 82596 also uses T ON and T OFF param eters in its SCB which the 82557 does not use Addi tionally the 82596 uses the PORT pin to allow the CPU to directly access it for certain function as op posed to the 82557 which has a PORT register within its SCB AP 368 l n SYSTEM CONTROL i BLOCK i ommand Block List System Memory COMMAND COMMAND COMMAND BLOCK BLOCK BLOCK 82557 Registers FRAME FRAME FRAME DESCRIPTOR DESCRIPTOR DESCRIPTOR RECEIVE RECEIVE RECEIVE BUFFER BUFFER BUFFER DESCRIPTOR DESCRIPTOR DESCRIPTOR RECEIVE RECEIVE RECEIVE BUFFER BUFFER BUFFER 644216 1 Figure 1 82557 Shared Memory Structure a PRELIMINARY l n A AP 368 SYSBUS System Memory SYSTEM CONTROL E BLOCK ij ommand Block List System Memory COMMAND COMMAND COMMAND BLOCK BLOCK BLOCK eceive Frame Area System Memory FRAME FRAME FRAME DESCRIPTOR DESCRIPTOR DESCRIPTOR RECEIVE RECEIVE RECEIVE BUFFER BUFFER BUFFER DESCRIPTOR DESCRIPTOR DESCRIPTOR RECEIVE RECEIVE RECEIVE BUFFER BUFFER BUFFER Figure 2 82596 Shared Memory Structure 644216 2 PRELIMINARY 5 G AP 368 l ntel 31 Upper Word 16 15 Lower Word 0 ACK X CUC R RUC 0jojojo STAT 0 CUS RUS
16. ture Control Status Registers CSR Command Block List CBL and the Receive Frame Area RFA The 82596 memory structure is divided into four parts the Initialization Root the System Control Block the Command Block List and the Receive Frame Area One of the main differences in the 82557 and 82596 memory structures is the 82557 System Control block SCB residing on chip accessed by either I O or memory cycles as part of the Control Status Register CSR In the 82596 the channel attention signal is used by the 82596 to access the System Configuration Pointer SCP and the Intermediate System Configura tion Pointer ISCP The ISCP then points to the SCB see Figure 2 However the SCB serves the same pur pose in both the 82596 and 82557 It is a central com munication point for exchanging control and status in formation between the CPU and the 82557 The CPU controls the state of the Command Unit CU and Re ceive Unit RU e g Active Suspended or Idle by writing commands to the SCB The 82557 and 82596 updates the SCB Status Word to provide status 5 1 The 82557 Control Status Register CSR The 82557 CSR registers MDI Flash PORT MDI Control and General Pointer allow the CPU to read to and from an EEPROM FLASH Management Data Interface in the case of MDI Flash and MDI Con trol They also point to various data structures in memory reset the 82557 etc for General Pointer and PORT respectively In contra
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